remove update of pc, msr and svstate from TestIssuerInOrder

diff --git a/src/soc/simple/inorder.py b/src/soc/simple/inorder.py
index b930ecb923f0286d28baddad1f251f7043c62dfa..3916ad423de6c6f9c7b974e80f0bd4a254d2fe9d 100644 (file)
--- a/src/soc/simple/inorder.py
+++ b/src/soc/simple/inorder.py
@@ -275,15 +275,6 @@ class TestIssuerInternalInOrder(TestIssuerBase):
                 with m.Else():
                     # tell core it's stopped, and acknowledge debug handshake
                     comb += dbg.core_stopped_i.eq(1)
-                    # while stopped, allow updating the MSR, PC and SVSTATE
-                    with m.If(self.pc_i.ok):
-                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
-                        comb += self.state_w_pc.i_data.eq(self.pc_i.data)
-                        sync += self.pc_changed.eq(1)
-                    with m.If(self.msr_i.ok):
-                        comb += self.state_w_msr.wen.eq(1 << StateRegs.MSR)
-                        comb += self.state_w_msr.i_data.eq(self.msr_i.data)
-                        sync += self.msr_changed.eq(1)
 
             # wait for an instruction to arrive from Fetch
             with m.State("INSN_WAIT"):