move to common ALUHelpers for CR test_pipe_caller.py

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 7bf1e260ed4b7ab471abff5071682e475bd3ea89..50bb6903bcb79d16b3b3e122f13fa74f0635e0dd 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -12,7 +12,7 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
-from soc.fu.test.common import TestCase
+from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.cr.pipeline import CRBasePipe
 from soc.fu.cr.pipe_data import CRPipeSpec
 import random
@@ -194,24 +194,12 @@ class TestRunner(FHDLTestCase):
 
     def set_inputs(self, alu, dec2, simulator):
         inp = yield from get_cu_inputs(dec2, simulator)
-        if 'full_cr' in inp:
-            yield alu.p.data_i.full_cr.eq(inp['full_cr'])
-        else:
-            yield alu.p.data_i.full_cr.eq(0)
-        if 'cr_a' in inp:
-            yield alu.p.data_i.cr_a.eq(inp['cr_a'])
-        if 'cr_b' in inp:
-            yield alu.p.data_i.cr_b.eq(inp['cr_b'])
-        if 'cr_c' in inp:
-            yield alu.p.data_i.cr_c.eq(inp['cr_c'])
-        if 'ra' in inp:
-            yield alu.p.data_i.ra.eq(inp['ra'])
-        else:
-            yield alu.p.data_i.ra.eq(0)
-        if 'rb' in inp:
-            yield alu.p.data_i.rb.eq(inp['rb'])
-        else:
-            yield alu.p.data_i.rb.eq(0)
+        yield from ALUHelpers.set_full_cr(alu, dec2, inp)
+        yield from ALUHelpers.set_cr_a(alu, dec2, inp)
+        yield from ALUHelpers.set_cr_b(alu, dec2, inp)
+        yield from ALUHelpers.set_cr_c(alu, dec2, inp)
+        yield from ALUHelpers.set_int_ra(alu, dec2, inp)
+        yield from ALUHelpers.set_int_rb(alu, dec2, inp)
 
     def assert_outputs(self, alu, dec2, simulator, code):
         whole_reg = yield dec2.e.write_cr_whole

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 302d1b797e412f163f57316d307dd37896513600..5ffd130bbaf5ecee22ecba476e9b08a09ea5a370 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -22,8 +22,11 @@ class ALUHelpers:
     def set_int_ra(alu, dec2, inp):
         if 'ra' in inp:
             yield alu.p.data_i.ra.eq(inp['ra'])
+        else:
+            yield alu.p.data_i.ra.eq(0)
 
     def set_int_rb(alu, dec2, inp):
+        yield alu.p.data_i.rb.eq(0)
         if 'rb' in inp:
             yield alu.p.data_i.rb.eq(inp['rb'])
         # If there's an immediate, set the B operand to that
@@ -57,5 +60,19 @@ class ALUHelpers:
 
     def set_cr_a(alu, dec2, inp):
         if 'cr_a' in inp:
-            yield alu.p.data_i.cr.eq(inp['cr_a'])
+            yield alu.p.data_i.cr_a.eq(inp['cr_a'])
+
+    def set_cr_b(alu, dec2, inp):
+        if 'cr_b' in inp:
+            yield alu.p.data_i.cr_b.eq(inp['cr_b'])
+
+    def set_cr_c(alu, dec2, inp):
+        if 'cr_c' in inp:
+            yield alu.p.data_i.cr_c.eq(inp['cr_c'])
+
+    def set_full_cr(alu, dec2, inp):
+        if 'full_cr' in inp:
+            yield alu.p.data_i.full_cr.eq(inp['full_cr'])
+        else:
+            yield alu.p.data_i.full_cr.eq(0)