clear instruction fault on exception WAIT_MMU ACK in LoadStore1

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 8ad751e7ec8714078f22aff4abe28526c67c6ad2..eb452dbf190aced9f4a33a83f232aa089d30015b 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -255,6 +255,7 @@ class LoadStore1(PortInterfaceBase):
                         # XXX there is no architected bit for this
                         # (probably should be a machine check in fact)
                         sync += self.dsisr[63 - 35].eq(d_in.cache_paradox)
+                        sync += self.r_instr_fault.eq(0)
 
                     with m.Else():
                         # Look up the translation for TLB miss