update perm validator test

diff --git a/src/TLB/PermissionValidator.py b/src/TLB/PermissionValidator.py
index 14f01e4294f9215cec9eb4ec2866c5b42e5969a3..e3058cb24cd4cee0ac43a42583af5949ff0ee3b8 100644 (file)
--- a/src/TLB/PermissionValidator.py
+++ b/src/TLB/PermissionValidator.py
@@ -1,7 +1,7 @@
 from nmigen import Module, Signal
 from nmigen.cli import main
 
-from PteEntry import PteEntry
+from .PteEntry import PteEntry
 
 class PermissionValidator():
     """ The purpose of this Module is to check the Permissions of a given PTE
@@ -64,4 +64,4 @@ class PermissionValidator():
                 m.d.comb += self.valid.eq(0)
         with m.Else():
             m.d.comb += self.valid.eq(0)
-        return m
\ No newline at end of file
+        return m

diff --git a/src/TLB/test/test_permission_validator.py b/src/TLB/test/test_permission_validator.py
index 59750c51a003cf7f0724393dc253eafa5883eed5..81873d7953391283e1b538d2ce8aa5fa3f73d767 100644 (file)
--- a/src/TLB/test/test_permission_validator.py
+++ b/src/TLB/test/test_permission_validator.py
@@ -1,12 +1,9 @@
-import sys
-sys.path.append("../src")
-sys.path.append("../../TestUtil")
-
 from nmigen.compat.sim import run_simulation
 
-from PermissionValidator import PermissionValidator
+from TLB.PermissionValidator import PermissionValidator
+
+from TestUtil.test_helper import assert_op
 
-from test_helper import assert_op
 
 def set_validator(dut, d, xwr, sm, sa, asid):
     yield dut.data.eq(d)
@@ -20,7 +17,7 @@ def check_valid(dut, v, op):
     out_v = yield dut.valid
     assert_op("Valid", out_v, v, op)
 
-def testbench(dut):
+def tbench(dut):
     # 80 bits represented. Ignore the MSB as it will be truncated
     # ASID is bits first 4 hex values (bits 64 - 78)
 
@@ -139,7 +136,11 @@ def testbench(dut):
     yield from set_validator(dut, data, xwr, super_mode, super_access, asid)
     yield from check_valid(dut, valid, 0)
 
-if __name__ == "__main__":
+
+def test_permv():
     dut = PermissionValidator(15, 64);
-    run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_permission_validator.vcd")
+    run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_permission_validator.vcd")
     print("PermissionValidator Unit Test Success")
+
+if __name__ == "__main__":
+    test_permv()