missed setting of link register on OP_BC in PowerDecoder2

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 5ad8a89fabebfcf3fbd1d5da815f779edfb51cd9..5f1e99eed50fa3a639c01dc4ce13a00a795392ca 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -363,9 +363,11 @@ class DecodeOut2(Elaboratable):
             comb += self.reg_out.eq(self.dec.RA)
             comb += self.reg_out.ok.eq(1)
 
-        # BC or BCREG: potential implicit register (LR) output
+        # B, BC or BCREG: potential implicit register (LR) output
+        # these give bl, bcl, bclrl, etc.
         op = self.dec.op
         with m.If((op.internal_op == InternalOp.OP_BC) |
+                  (op.internal_op == InternalOp.OP_B) |
                   (op.internal_op == InternalOp.OP_BCREG)):
             with m.If(self.lk): # "link" mode
                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR