too much debug info going past, so add the test registers to the
[soc.git] / src / soc / fu / div / test /
drwxr-xr-x   ..
-rw-r--r-- 10193 runner.py
-rw-r--r-- 2249 test_all_pipe_caller.py
-rw-r--r-- 12348 test_fsm.py
-rw-r--r-- 6532 test_pipe_caller.py