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missing a fastregs write-port
[soc.git] / src / soc / regfile /
drwxr-xr-x   ..
drwxr-xr-x - formal tree | history
-rw-r--r-- 9467 regfile.py blob | history | raw
-rw-r--r-- 4563 regfiles.py blob | history | raw
-rw-r--r-- 298 util.py blob | history | raw
-rw-r--r-- 5803 virtual_port.py blob | history | raw