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nope. put it back and connect to platform pads in LS180Platform
[soc.git]
/
src
/
soc
/
simple
/
drwxr-xr-x
..
-rw-r--r--
0
__init__.py
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raw
-rw-r--r--
21897
core.py
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raw
-rw-r--r--
20012
issuer.py
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history
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raw
-rw-r--r--
1331
issuer_verilog.py
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projects / soc.git / tree