reduce regfile ports by creating separate STATE regfile
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 17047 core.py
-rw-r--r-- 11149 issuer.py
-rw-r--r-- 953 issuer_verilog.py
drwxr-xr-x - test