Use nmutil simulator module to simplify choosing among engines
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 21706 core.py
-rw-r--r-- 18004 issuer.py
-rw-r--r-- 1260 issuer_verilog.py
drwxr-xr-x - test