whoops forgot that the mul pipeline is actually a pipeline (3 stage, first one)
[soc.git] / src / soc / simulator /
drwxr-xr-x   ..
-rw-r--r-- 967 gas.py
-rw-r--r-- 134 memmap
-rw-r--r-- 2560 program.py
-rw-r--r-- 4360 qemu.py
drwxr-xr-x - qemu_test
-rw-r--r-- 3866 test_div_sim.py
-rw-r--r-- 1790 test_mul_sim.py
-rw-r--r-- 10288 test_sim.py