add register specs to pipeline in/out so that they can be used to connect up
[soc.git] / src / soc /
drwxr-xr-x   ..
drwxr-xr-x - TestUtil
-rw-r--r-- 0 __init__.py
drwxr-xr-x - decoder
drwxr-xr-x - experiment
drwxr-xr-x - fu
drwxr-xr-x - memory_pipe_experiment
drwxr-xr-x - minerva
drwxr-xr-x - regfile
drwxr-xr-x - scoreboard
drwxr-xr-x - scoremulti
drwxr-xr-x - simulator