experiments9/non_generated/full_core_ls180.il

   1 # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os)
   2 autoidx 3721
   3 attribute \src "libresoc.v:5.1-277.10"
   4 attribute \cells_not_processed 1
   5 attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm"
   6 attribute \generator "nMigen"
   7 module \_fsm
   8   attribute \src "libresoc.v:125.3-239.6"
   9   wire width 4 $0\fsm_state$next[3:0]$25
  10   attribute \src "libresoc.v:91.3-92.35"
  11   wire width 4 $0\fsm_state[3:0]
  12   attribute \src "libresoc.v:6.7-6.20"
  13   wire $0\initial[0:0]
  14   attribute \src "libresoc.v:97.3-124.6"
  15   wire $0\isdr$next[0:0]$21
  16   attribute \src "libresoc.v:93.3-94.25"
  17   wire $0\isdr[0:0]
  18   attribute \src "libresoc.v:240.3-267.6"
  19   wire $0\isir$next[0:0]$38
  20   attribute \src "libresoc.v:95.3-96.25"
  21   wire $0\isir[0:0]
  22   attribute \src "libresoc.v:125.3-239.6"
  23   wire width 4 $10\fsm_state$next[3:0]$35
  24   attribute \src "libresoc.v:125.3-239.6"
  25   wire width 4 $11\fsm_state$next[3:0]$36
  26   attribute \src "libresoc.v:125.3-239.6"
  27   wire width 4 $1\fsm_state$next[3:0]$26
  28   attribute \src "libresoc.v:46.13-46.29"
  29   wire width 4 $1\fsm_state[3:0]
  30   attribute \src "libresoc.v:97.3-124.6"
  31   wire $1\isdr$next[0:0]$22
  32   attribute \src "libresoc.v:51.7-51.18"
  33   wire $1\isdr[0:0]
  34   attribute \src "libresoc.v:240.3-267.6"
  35   wire $1\isir$next[0:0]$39
  36   attribute \src "libresoc.v:56.7-56.18"
  37   wire $1\isir[0:0]
  38   attribute \src "libresoc.v:125.3-239.6"
  39   wire width 4 $2\fsm_state$next[3:0]$27
  40   attribute \src "libresoc.v:97.3-124.6"
  41   wire $2\isdr$next[0:0]$23
  42   attribute \src "libresoc.v:240.3-267.6"
  43   wire $2\isir$next[0:0]$40
  44   attribute \src "libresoc.v:125.3-239.6"
  45   wire width 4 $3\fsm_state$next[3:0]$28
  46   attribute \src "libresoc.v:125.3-239.6"
  47   wire width 4 $4\fsm_state$next[3:0]$29
  48   attribute \src "libresoc.v:125.3-239.6"
  49   wire width 4 $5\fsm_state$next[3:0]$30
  50   attribute \src "libresoc.v:125.3-239.6"
  51   wire width 4 $6\fsm_state$next[3:0]$31
  52   attribute \src "libresoc.v:125.3-239.6"
  53   wire width 4 $7\fsm_state$next[3:0]$32
  54   attribute \src "libresoc.v:125.3-239.6"
  55   wire width 4 $8\fsm_state$next[3:0]$33
  56   attribute \src "libresoc.v:125.3-239.6"
  57   wire width 4 $9\fsm_state$next[3:0]$34
  58   attribute \src "libresoc.v:75.17-75.110"
  59   wire $eq$libresoc.v:75$1_Y
  60   attribute \src "libresoc.v:76.18-76.111"
  61   wire $eq$libresoc.v:76$2_Y
  62   attribute \src "libresoc.v:77.18-77.111"
  63   wire $eq$libresoc.v:77$3_Y
  64   attribute \src "libresoc.v:78.18-78.111"
  65   wire $eq$libresoc.v:78$4_Y
  66   attribute \src "libresoc.v:79.18-79.111"
  67   wire $eq$libresoc.v:79$5_Y
  68   attribute \src "libresoc.v:80.17-80.108"
  69   wire $eq$libresoc.v:80$6_Y
  70   attribute \src "libresoc.v:81.18-81.111"
  71   wire $eq$libresoc.v:81$7_Y
  72   attribute \src "libresoc.v:82.18-82.111"
  73   wire $eq$libresoc.v:82$8_Y
  74   attribute \src "libresoc.v:83.18-83.111"
  75   wire $eq$libresoc.v:83$9_Y
  76   attribute \src "libresoc.v:84.18-84.111"
  77   wire $eq$libresoc.v:84$10_Y
  78   attribute \src "libresoc.v:85.18-85.111"
  79   wire $eq$libresoc.v:85$11_Y
  80   attribute \src "libresoc.v:86.18-86.111"
  81   wire $eq$libresoc.v:86$12_Y
  82   attribute \src "libresoc.v:87.18-87.112"
  83   wire $eq$libresoc.v:87$13_Y
  84   attribute \src "libresoc.v:88.17-88.108"
  85   wire $eq$libresoc.v:88$14_Y
  86   attribute \src "libresoc.v:89.17-89.108"
  87   wire $eq$libresoc.v:89$15_Y
  88   attribute \src "libresoc.v:90.17-90.108"
  89   wire $eq$libresoc.v:90$16_Y
  90   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113"
  91   wire \$1
  92   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
  93   wire \$11
  94   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
  95   wire \$13
  96   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
  97   wire \$15
  98   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
  99   wire \$17
 100   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
 101   wire \$19
 102   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
 103   wire \$21
 104   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
 105   wire \$23
 106   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
 107   wire \$25
 108   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
 109   wire \$27
 110   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
 111   wire \$29
 112   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114"
 113   wire \$3
 114   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
 115   wire \$31
 116   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115"
 117   wire \$5
 118   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116"
 119   wire \$7
 120   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
 121   wire \$9
 122   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
 123   wire input 9 \TAP_bus__tck
 124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
 125   wire input 10 \TAP_bus__tms
 126   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
 127   wire output 1 \capture
 128   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
 129   wire width 4 \fsm_state
 130   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
 131   wire width 4 \fsm_state$next
 132   attribute \src "libresoc.v:6.7-6.15"
 133   wire \initial
 134   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
 135   wire output 11 \isdr
 136   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
 137   wire \isdr$next
 138   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
 139   wire output 4 \isir
 140   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
 141   wire \isir$next
 142   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49"
 143   wire \local_clk
 144   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
 145   wire output 8 \negjtag_clk
 146   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
 147   wire output 6 \negjtag_rst
 148   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
 149   wire output 7 \posjtag_clk
 150   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
 151   wire output 5 \posjtag_rst
 152   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36"
 153   wire \rst
 154   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
 155   wire output 2 \shift
 156   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
 157   wire output 3 \update
 158   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
 159   cell $eq $eq$libresoc.v:75$1
 160     parameter \A_SIGNED 0
 161     parameter \A_WIDTH 1
 162     parameter \B_SIGNED 0
 163     parameter \B_WIDTH 1
 164     parameter \Y_WIDTH 1
 165     connect \A \TAP_bus__tms
 166     connect \B 1'0
 167     connect \Y $eq$libresoc.v:75$1_Y
 168   end
 169   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
 170   cell $eq $eq$libresoc.v:76$2
 171     parameter \A_SIGNED 0
 172     parameter \A_WIDTH 1
 173     parameter \B_SIGNED 0
 174     parameter \B_WIDTH 1
 175     parameter \Y_WIDTH 1
 176     connect \A \TAP_bus__tms
 177     connect \B 1'0
 178     connect \Y $eq$libresoc.v:76$2_Y
 179   end
 180   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
 181   cell $eq $eq$libresoc.v:77$3
 182     parameter \A_SIGNED 0
 183     parameter \A_WIDTH 1
 184     parameter \B_SIGNED 0
 185     parameter \B_WIDTH 1
 186     parameter \Y_WIDTH 1
 187     connect \A \TAP_bus__tms
 188     connect \B 1'0
 189     connect \Y $eq$libresoc.v:77$3_Y
 190   end
 191   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
 192   cell $eq $eq$libresoc.v:78$4
 193     parameter \A_SIGNED 0
 194     parameter \A_WIDTH 1
 195     parameter \B_SIGNED 0
 196     parameter \B_WIDTH 1
 197     parameter \Y_WIDTH 1
 198     connect \A \TAP_bus__tms
 199     connect \B 1'1
 200     connect \Y $eq$libresoc.v:78$4_Y
 201   end
 202   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
 203   cell $eq $eq$libresoc.v:79$5
 204     parameter \A_SIGNED 0
 205     parameter \A_WIDTH 1
 206     parameter \B_SIGNED 0
 207     parameter \B_WIDTH 1
 208     parameter \Y_WIDTH 1
 209     connect \A \TAP_bus__tms
 210     connect \B 1'0
 211     connect \Y $eq$libresoc.v:79$5_Y
 212   end
 213   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113"
 214   cell $eq $eq$libresoc.v:80$6
 215     parameter \A_SIGNED 0
 216     parameter \A_WIDTH 4
 217     parameter \B_SIGNED 0
 218     parameter \B_WIDTH 1
 219     parameter \Y_WIDTH 1
 220     connect \A \fsm_state
 221     connect \B 1'0
 222     connect \Y $eq$libresoc.v:80$6_Y
 223   end
 224   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
 225   cell $eq $eq$libresoc.v:81$7
 226     parameter \A_SIGNED 0
 227     parameter \A_WIDTH 1
 228     parameter \B_SIGNED 0
 229     parameter \B_WIDTH 1
 230     parameter \Y_WIDTH 1
 231     connect \A \TAP_bus__tms
 232     connect \B 1'0
 233     connect \Y $eq$libresoc.v:81$7_Y
 234   end
 235   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
 236   cell $eq $eq$libresoc.v:82$8
 237     parameter \A_SIGNED 0
 238     parameter \A_WIDTH 1
 239     parameter \B_SIGNED 0
 240     parameter \B_WIDTH 1
 241     parameter \Y_WIDTH 1
 242     connect \A \TAP_bus__tms
 243     connect \B 1'0
 244     connect \Y $eq$libresoc.v:82$8_Y
 245   end
 246   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
 247   cell $eq $eq$libresoc.v:83$9
 248     parameter \A_SIGNED 0
 249     parameter \A_WIDTH 1
 250     parameter \B_SIGNED 0
 251     parameter \B_WIDTH 1
 252     parameter \Y_WIDTH 1
 253     connect \A \TAP_bus__tms
 254     connect \B 1'1
 255     connect \Y $eq$libresoc.v:83$9_Y
 256   end
 257   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
 258   cell $eq $eq$libresoc.v:84$10
 259     parameter \A_SIGNED 0
 260     parameter \A_WIDTH 1
 261     parameter \B_SIGNED 0
 262     parameter \B_WIDTH 1
 263     parameter \Y_WIDTH 1
 264     connect \A \TAP_bus__tms
 265     connect \B 1'0
 266     connect \Y $eq$libresoc.v:84$10_Y
 267   end
 268   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
 269   cell $eq $eq$libresoc.v:85$11
 270     parameter \A_SIGNED 0
 271     parameter \A_WIDTH 1
 272     parameter \B_SIGNED 0
 273     parameter \B_WIDTH 1
 274     parameter \Y_WIDTH 1
 275     connect \A \TAP_bus__tms
 276     connect \B 1'1
 277     connect \Y $eq$libresoc.v:85$11_Y
 278   end
 279   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
 280   cell $eq $eq$libresoc.v:86$12
 281     parameter \A_SIGNED 0
 282     parameter \A_WIDTH 1
 283     parameter \B_SIGNED 0
 284     parameter \B_WIDTH 1
 285     parameter \Y_WIDTH 1
 286     connect \A \TAP_bus__tms
 287     connect \B 1'0
 288     connect \Y $eq$libresoc.v:86$12_Y
 289   end
 290   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
 291   cell $eq $eq$libresoc.v:87$13
 292     parameter \A_SIGNED 0
 293     parameter \A_WIDTH 1
 294     parameter \B_SIGNED 0
 295     parameter \B_WIDTH 1
 296     parameter \Y_WIDTH 1
 297     connect \A \TAP_bus__tms
 298     connect \B 1'0
 299     connect \Y $eq$libresoc.v:87$13_Y
 300   end
 301   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114"
 302   cell $eq $eq$libresoc.v:88$14
 303     parameter \A_SIGNED 0
 304     parameter \A_WIDTH 4
 305     parameter \B_SIGNED 0
 306     parameter \B_WIDTH 2
 307     parameter \Y_WIDTH 1
 308     connect \A \fsm_state
 309     connect \B 2'11
 310     connect \Y $eq$libresoc.v:88$14_Y
 311   end
 312   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115"
 313   cell $eq $eq$libresoc.v:89$15
 314     parameter \A_SIGNED 0
 315     parameter \A_WIDTH 4
 316     parameter \B_SIGNED 0
 317     parameter \B_WIDTH 3
 318     parameter \Y_WIDTH 1
 319     connect \A \fsm_state
 320     connect \B 3'101
 321     connect \Y $eq$libresoc.v:89$15_Y
 322   end
 323   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116"
 324   cell $eq $eq$libresoc.v:90$16
 325     parameter \A_SIGNED 0
 326     parameter \A_WIDTH 4
 327     parameter \B_SIGNED 0
 328     parameter \B_WIDTH 4
 329     parameter \Y_WIDTH 1
 330     connect \A \fsm_state
 331     connect \B 4'1000
 332     connect \Y $eq$libresoc.v:90$16_Y
 333   end
 334   attribute \src "libresoc.v:125.3-239.6"
 335   process $proc$libresoc.v:125$24
 336     assign { } { }
 337     assign { } { }
 338     assign $0\fsm_state$next[3:0]$25 $1\fsm_state$next[3:0]$26
 339     attribute \src "libresoc.v:126.5-126.29"
 340     switch \initial
 341       attribute \src "libresoc.v:126.9-126.17"
 342       case 1'1
 343       case
 344     end
 345     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
 346     switch \fsm_state
 347       attribute \src "libresoc.v:0.0-0.0"
 348       case 4'0000
 349         assign { } { }
 350         assign $1\fsm_state$next[3:0]$26 $2\fsm_state$next[3:0]$27
 351         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
 352         switch \$13
 353           attribute \src "libresoc.v:0.0-0.0"
 354           case 1'1
 355             assign { } { }
 356             assign $2\fsm_state$next[3:0]$27 4'0001
 357           case
 358             assign $2\fsm_state$next[3:0]$27 \fsm_state
 359         end
 360       attribute \src "libresoc.v:0.0-0.0"
 361       case 4'0001
 362         assign { } { }
 363         assign $1\fsm_state$next[3:0]$26 $3\fsm_state$next[3:0]$28
 364         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
 365         switch \$15
 366           attribute \src "libresoc.v:0.0-0.0"
 367           case 1'1
 368             assign { } { }
 369             assign $3\fsm_state$next[3:0]$28 4'0010
 370           case
 371             assign $3\fsm_state$next[3:0]$28 \fsm_state
 372         end
 373       attribute \src "libresoc.v:0.0-0.0"
 374       case 4'0010
 375         assign { } { }
 376         assign $1\fsm_state$next[3:0]$26 $4\fsm_state$next[3:0]$29
 377         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
 378         switch \$17
 379           attribute \src "libresoc.v:0.0-0.0"
 380           case 1'1
 381             assign { } { }
 382             assign $4\fsm_state$next[3:0]$29 4'0011
 383           attribute \src "libresoc.v:0.0-0.0"
 384           case
 385             assign { } { }
 386             assign $4\fsm_state$next[3:0]$29 4'0100
 387         end
 388       attribute \src "libresoc.v:0.0-0.0"
 389       case 4'0100
 390         assign { } { }
 391         assign $1\fsm_state$next[3:0]$26 $5\fsm_state$next[3:0]$30
 392         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
 393         switch \$19
 394           attribute \src "libresoc.v:0.0-0.0"
 395           case 1'1
 396             assign { } { }
 397             assign $5\fsm_state$next[3:0]$30 4'0011
 398           attribute \src "libresoc.v:0.0-0.0"
 399           case
 400             assign { } { }
 401             assign $5\fsm_state$next[3:0]$30 4'0000
 402         end
 403       attribute \src "libresoc.v:0.0-0.0"
 404       case 4'0011
 405         assign { } { }
 406         assign $1\fsm_state$next[3:0]$26 $6\fsm_state$next[3:0]$31
 407         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
 408         switch \$21
 409           attribute \src "libresoc.v:0.0-0.0"
 410           case 1'1
 411             assign { } { }
 412             assign $6\fsm_state$next[3:0]$31 4'0101
 413           attribute \src "libresoc.v:0.0-0.0"
 414           case
 415             assign { } { }
 416             assign $6\fsm_state$next[3:0]$31 4'0110
 417         end
 418       attribute \src "libresoc.v:0.0-0.0"
 419       case 4'0101
 420         assign { } { }
 421         assign $1\fsm_state$next[3:0]$26 $7\fsm_state$next[3:0]$32
 422         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
 423         switch \$23
 424           attribute \src "libresoc.v:0.0-0.0"
 425           case 1'1
 426             assign { } { }
 427             assign $7\fsm_state$next[3:0]$32 4'0110
 428           case
 429             assign $7\fsm_state$next[3:0]$32 \fsm_state
 430         end
 431       attribute \src "libresoc.v:0.0-0.0"
 432       case 4'0110
 433         assign { } { }
 434         assign $1\fsm_state$next[3:0]$26 $8\fsm_state$next[3:0]$33
 435         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
 436         switch \$25
 437           attribute \src "libresoc.v:0.0-0.0"
 438           case 1'1
 439             assign { } { }
 440             assign $8\fsm_state$next[3:0]$33 4'0111
 441           attribute \src "libresoc.v:0.0-0.0"
 442           case
 443             assign { } { }
 444             assign $8\fsm_state$next[3:0]$33 4'1000
 445         end
 446       attribute \src "libresoc.v:0.0-0.0"
 447       case 4'0111
 448         assign { } { }
 449         assign $1\fsm_state$next[3:0]$26 $9\fsm_state$next[3:0]$34
 450         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
 451         switch \$27
 452           attribute \src "libresoc.v:0.0-0.0"
 453           case 1'1
 454             assign { } { }
 455             assign $9\fsm_state$next[3:0]$34 4'1001
 456           case
 457             assign $9\fsm_state$next[3:0]$34 \fsm_state
 458         end
 459       attribute \src "libresoc.v:0.0-0.0"
 460       case 4'1001
 461         assign { } { }
 462         assign $1\fsm_state$next[3:0]$26 $10\fsm_state$next[3:0]$35
 463         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
 464         switch \$29
 465           attribute \src "libresoc.v:0.0-0.0"
 466           case 1'1
 467             assign { } { }
 468             assign $10\fsm_state$next[3:0]$35 4'0101
 469           attribute \src "libresoc.v:0.0-0.0"
 470           case
 471             assign { } { }
 472             assign $10\fsm_state$next[3:0]$35 4'1000
 473         end
 474       attribute \src "libresoc.v:0.0-0.0"
 475       case 4'1000
 476         assign { } { }
 477         assign $1\fsm_state$next[3:0]$26 $11\fsm_state$next[3:0]$36
 478         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
 479         switch \$31
 480           attribute \src "libresoc.v:0.0-0.0"
 481           case 1'1
 482             assign { } { }
 483             assign $11\fsm_state$next[3:0]$36 4'0001
 484           attribute \src "libresoc.v:0.0-0.0"
 485           case
 486             assign { } { }
 487             assign $11\fsm_state$next[3:0]$36 4'0010
 488         end
 489       case
 490         assign $1\fsm_state$next[3:0]$26 \fsm_state
 491     end
 492     sync always
 493       update \fsm_state$next $0\fsm_state$next[3:0]$25
 494   end
 495   attribute \src "libresoc.v:240.3-267.6"
 496   process $proc$libresoc.v:240$37
 497     assign { } { }
 498     assign { } { }
 499     assign $0\isir$next[0:0]$38 $1\isir$next[0:0]$39
 500     attribute \src "libresoc.v:241.5-241.29"
 501     switch \initial
 502       attribute \src "libresoc.v:241.9-241.17"
 503       case 1'1
 504       case
 505     end
 506     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
 507     switch \fsm_state
 508       attribute \src "libresoc.v:0.0-0.0"
 509       case 4'0000
 510         assign { } { }
 511         assign $1\isir$next[0:0]$39 1'0
 512       attribute \src "libresoc.v:0.0-0.0"
 513       case 4'0001
 514         assign { } { }
 515         assign $1\isir$next[0:0]$39 1'0
 516       attribute \src "libresoc.v:0.0-0.0"
 517       case 4'0100
 518         assign { } { }
 519         assign $1\isir$next[0:0]$39 $2\isir$next[0:0]$40
 520         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
 521         switch \$9
 522           attribute \src "libresoc.v:0.0-0.0"
 523           case 1'1
 524             assign { } { }
 525             assign $2\isir$next[0:0]$40 1'1
 526           case
 527             assign $2\isir$next[0:0]$40 \isir
 528         end
 529       attribute \src "libresoc.v:0.0-0.0"
 530       case 4'1000
 531         assign { } { }
 532         assign $1\isir$next[0:0]$39 1'0
 533       case
 534         assign $1\isir$next[0:0]$39 \isir
 535     end
 536     sync always
 537       update \isir$next $0\isir$next[0:0]$38
 538   end
 539   attribute \src "libresoc.v:46.13-46.29"
 540   process $proc$libresoc.v:46$42
 541     assign { } { }
 542     assign $1\fsm_state[3:0] 4'0000
 543     sync always
 544     sync init
 545       update \fsm_state $1\fsm_state[3:0]
 546   end
 547   attribute \src "libresoc.v:51.7-51.18"
 548   process $proc$libresoc.v:51$43
 549     assign { } { }
 550     assign $1\isdr[0:0] 1'0
 551     sync always
 552     sync init
 553       update \isdr $1\isdr[0:0]
 554   end
 555   attribute \src "libresoc.v:56.7-56.18"
 556   process $proc$libresoc.v:56$44
 557     assign { } { }
 558     assign $1\isir[0:0] 1'0
 559     sync always
 560     sync init
 561       update \isir $1\isir[0:0]
 562   end
 563   attribute \src "libresoc.v:6.7-6.20"
 564   process $proc$libresoc.v:6$41
 565     assign { } { }
 566     assign $0\initial[0:0] 1'0
 567     sync always
 568       update \initial $0\initial[0:0]
 569     sync init
 570   end
 571   attribute \src "libresoc.v:91.3-92.35"
 572   process $proc$libresoc.v:91$17
 573     assign { } { }
 574     assign $0\fsm_state[3:0] \fsm_state$next
 575     sync posedge \local_clk
 576       update \fsm_state $0\fsm_state[3:0]
 577   end
 578   attribute \src "libresoc.v:93.3-94.25"
 579   process $proc$libresoc.v:93$18
 580     assign { } { }
 581     assign $0\isdr[0:0] \isdr$next
 582     sync posedge \local_clk
 583       update \isdr $0\isdr[0:0]
 584   end
 585   attribute \src "libresoc.v:95.3-96.25"
 586   process $proc$libresoc.v:95$19
 587     assign { } { }
 588     assign $0\isir[0:0] \isir$next
 589     sync posedge \local_clk
 590       update \isir $0\isir[0:0]
 591   end
 592   attribute \src "libresoc.v:97.3-124.6"
 593   process $proc$libresoc.v:97$20
 594     assign { } { }
 595     assign { } { }
 596     assign $0\isdr$next[0:0]$21 $1\isdr$next[0:0]$22
 597     attribute \src "libresoc.v:98.5-98.29"
 598     switch \initial
 599       attribute \src "libresoc.v:98.9-98.17"
 600       case 1'1
 601       case
 602     end
 603     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
 604     switch \fsm_state
 605       attribute \src "libresoc.v:0.0-0.0"
 606       case 4'0000
 607         assign { } { }
 608         assign $1\isdr$next[0:0]$22 1'0
 609       attribute \src "libresoc.v:0.0-0.0"
 610       case 4'0001
 611         assign { } { }
 612         assign $1\isdr$next[0:0]$22 1'0
 613       attribute \src "libresoc.v:0.0-0.0"
 614       case 4'0010
 615         assign { } { }
 616         assign $1\isdr$next[0:0]$22 $2\isdr$next[0:0]$23
 617         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
 618         switch \$11
 619           attribute \src "libresoc.v:0.0-0.0"
 620           case 1'1
 621             assign { } { }
 622             assign $2\isdr$next[0:0]$23 1'1
 623           case
 624             assign $2\isdr$next[0:0]$23 \isdr
 625         end
 626       attribute \src "libresoc.v:0.0-0.0"
 627       case 4'1000
 628         assign { } { }
 629         assign $1\isdr$next[0:0]$22 1'0
 630       case
 631         assign $1\isdr$next[0:0]$22 \isdr
 632     end
 633     sync always
 634       update \isdr$next $0\isdr$next[0:0]$21
 635   end
 636   connect \$9 $eq$libresoc.v:75$1_Y
 637   connect \$11 $eq$libresoc.v:76$2_Y
 638   connect \$13 $eq$libresoc.v:77$3_Y
 639   connect \$15 $eq$libresoc.v:78$4_Y
 640   connect \$17 $eq$libresoc.v:79$5_Y
 641   connect \$1 $eq$libresoc.v:80$6_Y
 642   connect \$19 $eq$libresoc.v:81$7_Y
 643   connect \$21 $eq$libresoc.v:82$8_Y
 644   connect \$23 $eq$libresoc.v:83$9_Y
 645   connect \$25 $eq$libresoc.v:84$10_Y
 646   connect \$27 $eq$libresoc.v:85$11_Y
 647   connect \$29 $eq$libresoc.v:86$12_Y
 648   connect \$31 $eq$libresoc.v:87$13_Y
 649   connect \$3 $eq$libresoc.v:88$14_Y
 650   connect \$5 $eq$libresoc.v:89$15_Y
 651   connect \$7 $eq$libresoc.v:90$16_Y
 652   connect \update \$7
 653   connect \shift \$5
 654   connect \capture \$3
 655   connect \rst \$1
 656   connect \local_clk \TAP_bus__tck
 657   connect \negjtag_rst \rst
 658   connect \negjtag_clk \TAP_bus__tck
 659   connect \posjtag_rst \rst
 660   connect \posjtag_clk \TAP_bus__tck
 661 end
 662 attribute \src "libresoc.v:281.1-353.10"
 663 attribute \cells_not_processed 1
 664 attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock"
 665 attribute \generator "nMigen"
 666 module \_idblock
 667   attribute \src "libresoc.v:326.3-346.6"
 668   wire width 32 $0\TAP_id_sr$next[31:0]$50
 669   attribute \src "libresoc.v:324.3-325.35"
 670   wire width 32 $0\TAP_id_sr[31:0]
 671   attribute \src "libresoc.v:282.7-282.20"
 672   wire $0\initial[0:0]
 673   attribute \src "libresoc.v:326.3-346.6"
 674   wire width 32 $1\TAP_id_sr$next[31:0]$51
 675   attribute \src "libresoc.v:292.14-292.31"
 676   wire width 32 $1\TAP_id_sr[31:0]
 677   attribute \src "libresoc.v:326.3-346.6"
 678   wire width 32 $2\TAP_id_sr$next[31:0]$52
 679   attribute \src "libresoc.v:321.17-321.110"
 680   wire $and$libresoc.v:321$45_Y
 681   attribute \src "libresoc.v:322.17-322.108"
 682   wire $and$libresoc.v:322$46_Y
 683   attribute \src "libresoc.v:323.17-323.109"
 684   wire $and$libresoc.v:323$47_Y
 685   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383"
 686   wire \$1
 687   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384"
 688   wire \$3
 689   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385"
 690   wire \$5
 691   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
 692   wire input 5 \TAP_bus__tdi
 693   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236"
 694   wire width 32 \TAP_id_sr
 695   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236"
 696   wire width 32 \TAP_id_sr$next
 697   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225"
 698   wire output 6 \TAP_id_tdo
 699   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243"
 700   wire \_bypass
 701   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240"
 702   wire \_capture
 703   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241"
 704   wire \_shift
 705   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239"
 706   wire \_tdi
 707   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242"
 708   wire \_update
 709   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
 710   wire input 2 \capture
 711   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375"
 712   wire input 1 \id_bypass
 713   attribute \src "libresoc.v:282.7-282.15"
 714   wire \initial
 715   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
 716   wire input 8 \posjtag_clk
 717   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
 718   wire input 7 \posjtag_rst
 719   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
 720   wire input 9 \select_id
 721   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
 722   wire input 3 \shift
 723   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
 724   wire input 4 \update
 725   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383"
 726   cell $and $and$libresoc.v:321$45
 727     parameter \A_SIGNED 0
 728     parameter \A_WIDTH 1
 729     parameter \B_SIGNED 0
 730     parameter \B_WIDTH 1
 731     parameter \Y_WIDTH 1
 732     connect \A \select_id
 733     connect \B \capture
 734     connect \Y $and$libresoc.v:321$45_Y
 735   end
 736   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384"
 737   cell $and $and$libresoc.v:322$46
 738     parameter \A_SIGNED 0
 739     parameter \A_WIDTH 1
 740     parameter \B_SIGNED 0
 741     parameter \B_WIDTH 1
 742     parameter \Y_WIDTH 1
 743     connect \A \select_id
 744     connect \B \shift
 745     connect \Y $and$libresoc.v:322$46_Y
 746   end
 747   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385"
 748   cell $and $and$libresoc.v:323$47
 749     parameter \A_SIGNED 0
 750     parameter \A_WIDTH 1
 751     parameter \B_SIGNED 0
 752     parameter \B_WIDTH 1
 753     parameter \Y_WIDTH 1
 754     connect \A \select_id
 755     connect \B \update
 756     connect \Y $and$libresoc.v:323$47_Y
 757   end
 758   attribute \src "libresoc.v:282.7-282.20"
 759   process $proc$libresoc.v:282$53
 760     assign { } { }
 761     assign $0\initial[0:0] 1'0
 762     sync always
 763       update \initial $0\initial[0:0]
 764     sync init
 765   end
 766   attribute \src "libresoc.v:292.14-292.31"
 767   process $proc$libresoc.v:292$54
 768     assign { } { }
 769     assign $1\TAP_id_sr[31:0] 0
 770     sync always
 771     sync init
 772       update \TAP_id_sr $1\TAP_id_sr[31:0]
 773   end
 774   attribute \src "libresoc.v:324.3-325.35"
 775   process $proc$libresoc.v:324$48
 776     assign { } { }
 777     assign $0\TAP_id_sr[31:0] \TAP_id_sr$next
 778     sync posedge \posjtag_clk
 779       update \TAP_id_sr $0\TAP_id_sr[31:0]
 780   end
 781   attribute \src "libresoc.v:326.3-346.6"
 782   process $proc$libresoc.v:326$49
 783     assign { } { }
 784     assign { } { }
 785     assign $0\TAP_id_sr$next[31:0]$50 $1\TAP_id_sr$next[31:0]$51
 786     attribute \src "libresoc.v:327.5-327.29"
 787     switch \initial
 788       attribute \src "libresoc.v:327.9-327.17"
 789       case 1'1
 790       case
 791     end
 792     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254"
 793     switch { \_shift \_capture }
 794       attribute \src "libresoc.v:0.0-0.0"
 795       case 2'-1
 796         assign { } { }
 797         assign $1\TAP_id_sr$next[31:0]$51 6399
 798       attribute \src "libresoc.v:0.0-0.0"
 799       case 2'1-
 800         assign { } { }
 801         assign $1\TAP_id_sr$next[31:0]$51 $2\TAP_id_sr$next[31:0]$52
 802         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257"
 803         switch \_bypass
 804           attribute \src "libresoc.v:0.0-0.0"
 805           case 1'1
 806             assign $2\TAP_id_sr$next[31:0]$52 [31:1] \TAP_id_sr [31:1]
 807             assign $2\TAP_id_sr$next[31:0]$52 [0] \_tdi
 808           attribute \src "libresoc.v:0.0-0.0"
 809           case
 810             assign { } { }
 811             assign $2\TAP_id_sr$next[31:0]$52 { \_tdi \TAP_id_sr [31:1] }
 812         end
 813       case
 814         assign $1\TAP_id_sr$next[31:0]$51 \TAP_id_sr
 815     end
 816     sync always
 817       update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$50
 818   end
 819   connect \$1 $and$libresoc.v:321$45_Y
 820   connect \$3 $and$libresoc.v:322$46_Y
 821   connect \$5 $and$libresoc.v:323$47_Y
 822   connect \TAP_id_tdo \TAP_id_sr [0]
 823   connect \_bypass \id_bypass
 824   connect \_update \$5
 825   connect \_shift \$3
 826   connect \_capture \$1
 827   connect \_tdi \TAP_bus__tdi
 828 end
 829 attribute \src "libresoc.v:357.1-441.10"
 830 attribute \cells_not_processed 1
 831 attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock"
 832 attribute \generator "nMigen"
 833 module \_irblock
 834   attribute \src "libresoc.v:358.7-358.20"
 835   wire $0\initial[0:0]
 836   attribute \src "libresoc.v:419.3-439.6"
 837   wire width 4 $0\ir$next[3:0]$67
 838   attribute \src "libresoc.v:402.3-403.21"
 839   wire width 4 $0\ir[3:0]
 840   attribute \src "libresoc.v:406.3-418.6"
 841   wire width 4 $0\shift_ir$next[3:0]$64
 842   attribute \src "libresoc.v:404.3-405.33"
 843   wire width 4 $0\shift_ir[3:0]
 844   attribute \src "libresoc.v:419.3-439.6"
 845   wire width 4 $1\ir$next[3:0]$68
 846   attribute \src "libresoc.v:377.13-377.22"
 847   wire width 4 $1\ir[3:0]
 848   attribute \src "libresoc.v:406.3-418.6"
 849   wire width 4 $1\shift_ir$next[3:0]$65
 850   attribute \src "libresoc.v:389.13-389.28"
 851   wire width 4 $1\shift_ir[3:0]
 852   attribute \src "libresoc.v:419.3-439.6"
 853   wire width 4 $2\ir$next[3:0]$69
 854   attribute \src "libresoc.v:396.17-396.103"
 855   wire $and$libresoc.v:396$55_Y
 856   attribute \src "libresoc.v:397.18-397.105"
 857   wire $and$libresoc.v:397$56_Y
 858   attribute \src "libresoc.v:398.17-398.105"
 859   wire $and$libresoc.v:398$57_Y
 860   attribute \src "libresoc.v:399.17-399.103"
 861   wire $and$libresoc.v:399$58_Y
 862   attribute \src "libresoc.v:400.17-400.104"
 863   wire $and$libresoc.v:400$59_Y
 864   attribute \src "libresoc.v:401.17-401.105"
 865   wire $and$libresoc.v:401$60_Y
 866   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
 867   wire \$1
 868   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
 869   wire \$11
 870   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
 871   wire \$3
 872   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
 873   wire \$5
 874   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
 875   wire \$7
 876   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
 877   wire \$9
 878   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
 879   wire input 4 \TAP_bus__tdi
 880   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
 881   wire input 1 \capture
 882   attribute \src "libresoc.v:358.7-358.15"
 883   wire \initial
 884   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
 885   wire width 4 output 9 \ir
 886   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
 887   wire width 4 \ir$next
 888   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
 889   wire input 5 \isir
 890   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
 891   wire input 8 \posjtag_clk
 892   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
 893   wire input 7 \posjtag_rst
 894   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
 895   wire input 2 \shift
 896   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138"
 897   wire width 4 \shift_ir
 898   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138"
 899   wire width 4 \shift_ir$next
 900   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
 901   wire output 6 \tdo
 902   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
 903   wire input 3 \update
 904   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
 905   cell $and $and$libresoc.v:396$55
 906     parameter \A_SIGNED 0
 907     parameter \A_WIDTH 1
 908     parameter \B_SIGNED 0
 909     parameter \B_WIDTH 1
 910     parameter \Y_WIDTH 1
 911     connect \A \isir
 912     connect \B \shift
 913     connect \Y $and$libresoc.v:396$55_Y
 914   end
 915   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
 916   cell $and $and$libresoc.v:397$56
 917     parameter \A_SIGNED 0
 918     parameter \A_WIDTH 1
 919     parameter \B_SIGNED 0
 920     parameter \B_WIDTH 1
 921     parameter \Y_WIDTH 1
 922     connect \A \isir
 923     connect \B \update
 924     connect \Y $and$libresoc.v:397$56_Y
 925   end
 926   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
 927   cell $and $and$libresoc.v:398$57
 928     parameter \A_SIGNED 0
 929     parameter \A_WIDTH 1
 930     parameter \B_SIGNED 0
 931     parameter \B_WIDTH 1
 932     parameter \Y_WIDTH 1
 933     connect \A \isir
 934     connect \B \capture
 935     connect \Y $and$libresoc.v:398$57_Y
 936   end
 937   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
 938   cell $and $and$libresoc.v:399$58
 939     parameter \A_SIGNED 0
 940     parameter \A_WIDTH 1
 941     parameter \B_SIGNED 0
 942     parameter \B_WIDTH 1
 943     parameter \Y_WIDTH 1
 944     connect \A \isir
 945     connect \B \shift
 946     connect \Y $and$libresoc.v:399$58_Y
 947   end
 948   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
 949   cell $and $and$libresoc.v:400$59
 950     parameter \A_SIGNED 0
 951     parameter \A_WIDTH 1
 952     parameter \B_SIGNED 0
 953     parameter \B_WIDTH 1
 954     parameter \Y_WIDTH 1
 955     connect \A \isir
 956     connect \B \update
 957     connect \Y $and$libresoc.v:400$59_Y
 958   end
 959   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
 960   cell $and $and$libresoc.v:401$60
 961     parameter \A_SIGNED 0
 962     parameter \A_WIDTH 1
 963     parameter \B_SIGNED 0
 964     parameter \B_WIDTH 1
 965     parameter \Y_WIDTH 1
 966     connect \A \isir
 967     connect \B \capture
 968     connect \Y $and$libresoc.v:401$60_Y
 969   end
 970   attribute \src "libresoc.v:358.7-358.20"
 971   process $proc$libresoc.v:358$70
 972     assign { } { }
 973     assign $0\initial[0:0] 1'0
 974     sync always
 975       update \initial $0\initial[0:0]
 976     sync init
 977   end
 978   attribute \src "libresoc.v:377.13-377.22"
 979   process $proc$libresoc.v:377$71
 980     assign { } { }
 981     assign $1\ir[3:0] 4'0001
 982     sync always
 983     sync init
 984       update \ir $1\ir[3:0]
 985   end
 986   attribute \src "libresoc.v:389.13-389.28"
 987   process $proc$libresoc.v:389$72
 988     assign { } { }
 989     assign $1\shift_ir[3:0] 4'0000
 990     sync always
 991     sync init
 992       update \shift_ir $1\shift_ir[3:0]
 993   end
 994   attribute \src "libresoc.v:402.3-403.21"
 995   process $proc$libresoc.v:402$61
 996     assign { } { }
 997     assign $0\ir[3:0] \ir$next
 998     sync posedge \posjtag_clk
 999       update \ir $0\ir[3:0]
1000   end
1001   attribute \src "libresoc.v:404.3-405.33"
1002   process $proc$libresoc.v:404$62
1003     assign { } { }
1004     assign $0\shift_ir[3:0] \shift_ir$next
1005     sync posedge \posjtag_clk
1006       update \shift_ir $0\shift_ir[3:0]
1007   end
1008   attribute \src "libresoc.v:406.3-418.6"
1009   process $proc$libresoc.v:406$63
1010     assign { } { }
1011     assign { } { }
1012     assign $0\shift_ir$next[3:0]$64 $1\shift_ir$next[3:0]$65
1013     attribute \src "libresoc.v:407.5-407.29"
1014     switch \initial
1015       attribute \src "libresoc.v:407.9-407.17"
1016       case 1'1
1017       case
1018     end
1019     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
1020     switch { \$5 \$3 \$1 }
1021       attribute \src "libresoc.v:0.0-0.0"
1022       case 3'--1
1023         assign { } { }
1024         assign $1\shift_ir$next[3:0]$65 \ir
1025       attribute \src "libresoc.v:0.0-0.0"
1026       case 3'-1-
1027         assign { } { }
1028         assign $1\shift_ir$next[3:0]$65 { \TAP_bus__tdi \shift_ir [3:1] }
1029       case
1030         assign $1\shift_ir$next[3:0]$65 \shift_ir
1031     end
1032     sync always
1033       update \shift_ir$next $0\shift_ir$next[3:0]$64
1034   end
1035   attribute \src "libresoc.v:419.3-439.6"
1036   process $proc$libresoc.v:419$66
1037     assign { } { }
1038     assign { } { }
1039     assign { } { }
1040     assign $0\ir$next[3:0]$67 $2\ir$next[3:0]$69
1041     attribute \src "libresoc.v:420.5-420.29"
1042     switch \initial
1043       attribute \src "libresoc.v:420.9-420.17"
1044       case 1'1
1045       case
1046     end
1047     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
1048     switch { \$11 \$9 \$7 }
1049       attribute \src "libresoc.v:0.0-0.0"
1050       case 3'--1
1051         assign $1\ir$next[3:0]$68 \ir
1052       attribute \src "libresoc.v:0.0-0.0"
1053       case 3'-1-
1054         assign $1\ir$next[3:0]$68 \ir
1055       attribute \src "libresoc.v:0.0-0.0"
1056       case 3'1--
1057         assign { } { }
1058         assign $1\ir$next[3:0]$68 \shift_ir
1059       case
1060         assign $1\ir$next[3:0]$68 \ir
1061     end
1062     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
1063     switch \posjtag_rst
1064       attribute \src "libresoc.v:0.0-0.0"
1065       case 1'1
1066         assign { } { }
1067         assign $2\ir$next[3:0]$69 4'0001
1068       case
1069         assign $2\ir$next[3:0]$69 $1\ir$next[3:0]$68
1070     end
1071     sync always
1072       update \ir$next $0\ir$next[3:0]$67
1073   end
1074   connect \$9 $and$libresoc.v:396$55_Y
1075   connect \$11 $and$libresoc.v:397$56_Y
1076   connect \$1 $and$libresoc.v:398$57_Y
1077   connect \$3 $and$libresoc.v:399$58_Y
1078   connect \$5 $and$libresoc.v:400$59_Y
1079   connect \$7 $and$libresoc.v:401$60_Y
1080   connect \tdo \ir [0]
1081 end
1082 attribute \src "libresoc.v:445.1-469.10"
1083 attribute \cells_not_processed 1
1084 attribute \nmigen.hierarchy "test_issuer.ti.core"
1085 attribute \generator "nMigen"
1086 module \core
1087   attribute \src "libresoc.v:446.7-446.20"
1088   wire $0\initial[0:0]
1089   attribute \src "libresoc.v:460.3-468.6"
1090   wire $0\x$next[0:0]$76
1091   attribute \src "libresoc.v:458.3-459.19"
1092   wire $0\x[0:0]
1093   attribute \src "libresoc.v:460.3-468.6"
1094   wire $1\x$next[0:0]$77
1095   attribute \src "libresoc.v:454.7-454.15"
1096   wire $1\x[0:0]
1097   attribute \src "libresoc.v:457.17-457.89"
1098   wire $not$libresoc.v:457$73_Y
1099   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126"
1100   wire \$1
1101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
1102   wire input 2 \coresync_clk
1103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
1104   wire input 1 \coresync_rst
1105   attribute \src "libresoc.v:446.7-446.15"
1106   wire \initial
1107   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125"
1108   wire \x
1109   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125"
1110   wire \x$next
1111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126"
1112   cell $not $not$libresoc.v:457$73
1113     parameter \A_SIGNED 0
1114     parameter \A_WIDTH 1
1115     parameter \Y_WIDTH 1
1116     connect \A \x
1117     connect \Y $not$libresoc.v:457$73_Y
1118   end
1119   attribute \src "libresoc.v:446.7-446.20"
1120   process $proc$libresoc.v:446$78
1121     assign { } { }
1122     assign $0\initial[0:0] 1'0
1123     sync always
1124       update \initial $0\initial[0:0]
1125     sync init
1126   end
1127   attribute \src "libresoc.v:454.7-454.15"
1128   process $proc$libresoc.v:454$79
1129     assign { } { }
1130     assign $1\x[0:0] 1'0
1131     sync always
1132     sync init
1133       update \x $1\x[0:0]
1134   end
1135   attribute \src "libresoc.v:458.3-459.19"
1136   process $proc$libresoc.v:458$74
1137     assign { } { }
1138     assign $0\x[0:0] \x$next
1139     sync posedge \coresync_clk
1140       update \x $0\x[0:0]
1141   end
1142   attribute \src "libresoc.v:460.3-468.6"
1143   process $proc$libresoc.v:460$75
1144     assign { } { }
1145     assign { } { }
1146     assign $0\x$next[0:0]$76 $1\x$next[0:0]$77
1147     attribute \src "libresoc.v:461.5-461.29"
1148     switch \initial
1149       attribute \src "libresoc.v:461.9-461.17"
1150       case 1'1
1151       case
1152     end
1153     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
1154     switch \coresync_rst
1155       attribute \src "libresoc.v:0.0-0.0"
1156       case 1'1
1157         assign { } { }
1158         assign $1\x$next[0:0]$77 1'0
1159       case
1160         assign $1\x$next[0:0]$77 \$1
1161     end
1162     sync always
1163       update \x$next $0\x$next[0:0]$76
1164   end
1165   connect \$1 $not$libresoc.v:457$73_Y
1166 end
1167 attribute \src "libresoc.v:473.1-1187.10"
1168 attribute \cells_not_processed 1
1169 attribute \nmigen.hierarchy "test_issuer.ti.dbg"
1170 attribute \generator "nMigen"
1171 module \dbg
1172   attribute \src "libresoc.v:1003.3-1012.6"
1173   wire $0\d_cr_req[0:0]
1174   attribute \src "libresoc.v:810.3-819.6"
1175   wire $0\d_gpr_req[0:0]
1176   attribute \src "libresoc.v:1013.3-1022.6"
1177   wire $0\d_xer_req[0:0]
1178   attribute \src "libresoc.v:792.3-809.6"
1179   wire $0\dmi_ack_o[0:0]
1180   attribute \src "libresoc.v:1023.3-1053.6"
1181   wire width 64 $0\dmi_dout[63:0]
1182   attribute \src "libresoc.v:994.3-1002.6"
1183   wire $0\dmi_read_log_data$next[0:0]$193
1184   attribute \src "libresoc.v:770.3-771.51"
1185   wire $0\dmi_read_log_data[0:0]
1186   attribute \src "libresoc.v:985.3-993.6"
1187   wire $0\dmi_read_log_data_1$next[0:0]$190
1188   attribute \src "libresoc.v:772.3-773.55"
1189   wire $0\dmi_read_log_data_1[0:0]
1190   attribute \src "libresoc.v:820.3-828.6"
1191   wire $0\dmi_req_i_1$next[0:0]$156
1192   attribute \src "libresoc.v:782.3-783.39"
1193   wire $0\dmi_req_i_1[0:0]
1194   attribute \src "libresoc.v:1144.3-1177.6"
1195   wire $0\do_dmi_log_rd$next[0:0]$220
1196   attribute \src "libresoc.v:784.3-785.43"
1197   wire $0\do_dmi_log_rd[0:0]
1198   attribute \src "libresoc.v:1114.3-1143.6"
1199   wire $0\do_icreset$next[0:0]$213
1200   attribute \src "libresoc.v:786.3-787.37"
1201   wire $0\do_icreset[0:0]
1202   attribute \src "libresoc.v:1084.3-1113.6"
1203   wire $0\do_reset$next[0:0]$206
1204   attribute \src "libresoc.v:788.3-789.33"
1205   wire $0\do_reset[0:0]
1206   attribute \src "libresoc.v:1054.3-1083.6"
1207   wire $0\do_step$next[0:0]$199
1208   attribute \src "libresoc.v:790.3-791.31"
1209   wire $0\do_step[0:0]
1210   attribute \src "libresoc.v:923.3-950.6"
1211   wire width 7 $0\gspr_index$next[6:0]$178
1212   attribute \src "libresoc.v:776.3-777.37"
1213   wire width 7 $0\gspr_index[6:0]
1214   attribute \src "libresoc.v:474.7-474.20"
1215   wire $0\initial[0:0]
1216   attribute \src "libresoc.v:951.3-984.6"
1217   wire width 32 $0\log_dmi_addr$next[31:0]$184
1218   attribute \src "libresoc.v:774.3-775.41"
1219   wire width 32 $0\log_dmi_addr[31:0]
1220   attribute \src "libresoc.v:879.3-922.6"
1221   wire $0\stopping$next[0:0]$169
1222   attribute \src "libresoc.v:778.3-779.33"
1223   wire $0\stopping[0:0]
1224   attribute \src "libresoc.v:829.3-878.6"
1225   wire $0\terminated$next[0:0]$159
1226   attribute \src "libresoc.v:780.3-781.37"
1227   wire $0\terminated[0:0]
1228   attribute \src "libresoc.v:1003.3-1012.6"
1229   wire $1\d_cr_req[0:0]
1230   attribute \src "libresoc.v:810.3-819.6"
1231   wire $1\d_gpr_req[0:0]
1232   attribute \src "libresoc.v:1013.3-1022.6"
1233   wire $1\d_xer_req[0:0]
1234   attribute \src "libresoc.v:792.3-809.6"
1235   wire $1\dmi_ack_o[0:0]
1236   attribute \src "libresoc.v:1023.3-1053.6"
1237   wire width 64 $1\dmi_dout[63:0]
1238   attribute \src "libresoc.v:994.3-1002.6"
1239   wire $1\dmi_read_log_data$next[0:0]$194
1240   attribute \src "libresoc.v:647.7-647.31"
1241   wire $1\dmi_read_log_data[0:0]
1242   attribute \src "libresoc.v:985.3-993.6"
1243   wire $1\dmi_read_log_data_1$next[0:0]$191
1244   attribute \src "libresoc.v:651.7-651.33"
1245   wire $1\dmi_read_log_data_1[0:0]
1246   attribute \src "libresoc.v:820.3-828.6"
1247   wire $1\dmi_req_i_1$next[0:0]$157
1248   attribute \src "libresoc.v:657.7-657.25"
1249   wire $1\dmi_req_i_1[0:0]
1250   attribute \src "libresoc.v:1144.3-1177.6"
1251   wire $1\do_dmi_log_rd$next[0:0]$221
1252   attribute \src "libresoc.v:663.7-663.27"
1253   wire $1\do_dmi_log_rd[0:0]
1254   attribute \src "libresoc.v:1114.3-1143.6"
1255   wire $1\do_icreset$next[0:0]$214
1256   attribute \src "libresoc.v:667.7-667.24"
1257   wire $1\do_icreset[0:0]
1258   attribute \src "libresoc.v:1084.3-1113.6"
1259   wire $1\do_reset$next[0:0]$207
1260   attribute \src "libresoc.v:671.7-671.22"
1261   wire $1\do_reset[0:0]
1262   attribute \src "libresoc.v:1054.3-1083.6"
1263   wire $1\do_step$next[0:0]$200
1264   attribute \src "libresoc.v:675.7-675.21"
1265   wire $1\do_step[0:0]
1266   attribute \src "libresoc.v:923.3-950.6"
1267   wire width 7 $1\gspr_index$next[6:0]$179
1268   attribute \src "libresoc.v:679.13-679.31"
1269   wire width 7 $1\gspr_index[6:0]
1270   attribute \src "libresoc.v:951.3-984.6"
1271   wire width 32 $1\log_dmi_addr$next[31:0]$185
1272   attribute \src "libresoc.v:685.14-685.34"
1273   wire width 32 $1\log_dmi_addr[31:0]
1274   attribute \src "libresoc.v:879.3-922.6"
1275   wire $1\stopping$next[0:0]$170
1276   attribute \src "libresoc.v:697.7-697.22"
1277   wire $1\stopping[0:0]
1278   attribute \src "libresoc.v:829.3-878.6"
1279   wire $1\terminated$next[0:0]$160
1280   attribute \src "libresoc.v:703.7-703.24"
1281   wire $1\terminated[0:0]
1282   attribute \src "libresoc.v:1144.3-1177.6"
1283   wire $2\do_dmi_log_rd$next[0:0]$222
1284   attribute \src "libresoc.v:1114.3-1143.6"
1285   wire $2\do_icreset$next[0:0]$215
1286   attribute \src "libresoc.v:1084.3-1113.6"
1287   wire $2\do_reset$next[0:0]$208
1288   attribute \src "libresoc.v:1054.3-1083.6"
1289   wire $2\do_step$next[0:0]$201
1290   attribute \src "libresoc.v:923.3-950.6"
1291   wire width 7 $2\gspr_index$next[6:0]$180
1292   attribute \src "libresoc.v:951.3-984.6"
1293   wire width 32 $2\log_dmi_addr$next[31:0]$186
1294   attribute \src "libresoc.v:879.3-922.6"
1295   wire $2\stopping$next[0:0]$171
1296   attribute \src "libresoc.v:829.3-878.6"
1297   wire $2\terminated$next[0:0]$161
1298   attribute \src "libresoc.v:1144.3-1177.6"
1299   wire $3\do_dmi_log_rd$next[0:0]$223
1300   attribute \src "libresoc.v:1114.3-1143.6"
1301   wire $3\do_icreset$next[0:0]$216
1302   attribute \src "libresoc.v:1084.3-1113.6"
1303   wire $3\do_reset$next[0:0]$209
1304   attribute \src "libresoc.v:1054.3-1083.6"
1305   wire $3\do_step$next[0:0]$202
1306   attribute \src "libresoc.v:923.3-950.6"
1307   wire width 7 $3\gspr_index$next[6:0]$181
1308   attribute \src "libresoc.v:951.3-984.6"
1309   wire width 32 $3\log_dmi_addr$next[31:0]$187
1310   attribute \src "libresoc.v:879.3-922.6"
1311   wire $3\stopping$next[0:0]$172
1312   attribute \src "libresoc.v:829.3-878.6"
1313   wire $3\terminated$next[0:0]$162
1314   attribute \src "libresoc.v:1144.3-1177.6"
1315   wire $4\do_dmi_log_rd$next[0:0]$224
1316   attribute \src "libresoc.v:1114.3-1143.6"
1317   wire $4\do_icreset$next[0:0]$217
1318   attribute \src "libresoc.v:1084.3-1113.6"
1319   wire $4\do_reset$next[0:0]$210
1320   attribute \src "libresoc.v:1054.3-1083.6"
1321   wire $4\do_step$next[0:0]$203
1322   attribute \src "libresoc.v:923.3-950.6"
1323   wire width 7 $4\gspr_index$next[6:0]$182
1324   attribute \src "libresoc.v:951.3-984.6"
1325   wire width 32 $4\log_dmi_addr$next[31:0]$188
1326   attribute \src "libresoc.v:879.3-922.6"
1327   wire $4\stopping$next[0:0]$173
1328   attribute \src "libresoc.v:829.3-878.6"
1329   wire $4\terminated$next[0:0]$163
1330   attribute \src "libresoc.v:1114.3-1143.6"
1331   wire $5\do_icreset$next[0:0]$218
1332   attribute \src "libresoc.v:1084.3-1113.6"
1333   wire $5\do_reset$next[0:0]$211
1334   attribute \src "libresoc.v:1054.3-1083.6"
1335   wire $5\do_step$next[0:0]$204
1336   attribute \src "libresoc.v:879.3-922.6"
1337   wire $5\stopping$next[0:0]$174
1338   attribute \src "libresoc.v:829.3-878.6"
1339   wire $5\terminated$next[0:0]$164
1340   attribute \src "libresoc.v:879.3-922.6"
1341   wire $6\stopping$next[0:0]$175
1342   attribute \src "libresoc.v:829.3-878.6"
1343   wire $6\terminated$next[0:0]$165
1344   attribute \src "libresoc.v:879.3-922.6"
1345   wire $7\stopping$next[0:0]$176
1346   attribute \src "libresoc.v:829.3-878.6"
1347   wire $7\terminated$next[0:0]$166
1348   attribute \src "libresoc.v:829.3-878.6"
1349   wire $8\terminated$next[0:0]$167
1350   attribute \src "libresoc.v:717.19-717.110"
1351   wire width 3 $add$libresoc.v:717$89_Y
1352   attribute \src "libresoc.v:708.17-708.109"
1353   wire $and$libresoc.v:708$80_Y
1354   attribute \src "libresoc.v:711.19-711.103"
1355   wire $and$libresoc.v:711$83_Y
1356   attribute \src "libresoc.v:713.19-713.113"
1357   wire $and$libresoc.v:713$85_Y
1358   attribute \src "libresoc.v:720.19-720.103"
1359   wire $and$libresoc.v:720$92_Y
1360   attribute \src "libresoc.v:722.19-722.102"
1361   wire $and$libresoc.v:722$94_Y
1362   attribute \src "libresoc.v:727.18-727.101"
1363   wire $and$libresoc.v:727$99_Y
1364   attribute \src "libresoc.v:729.18-729.111"
1365   wire $and$libresoc.v:729$101_Y
1366   attribute \src "libresoc.v:734.18-734.101"
1367   wire $and$libresoc.v:734$106_Y
1368   attribute \src "libresoc.v:736.18-736.111"
1369   wire $and$libresoc.v:736$108_Y
1370   attribute \src "libresoc.v:742.18-742.101"
1371   wire $and$libresoc.v:742$114_Y
1372   attribute \src "libresoc.v:744.18-744.111"
1373   wire $and$libresoc.v:744$116_Y
1374   attribute \src "libresoc.v:748.17-748.99"
1375   wire $and$libresoc.v:748$120_Y
1376   attribute \src "libresoc.v:750.18-750.101"
1377   wire $and$libresoc.v:750$122_Y
1378   attribute \src "libresoc.v:752.18-752.111"
1379   wire $and$libresoc.v:752$124_Y
1380   attribute \src "libresoc.v:757.18-757.101"
1381   wire $and$libresoc.v:757$129_Y
1382   attribute \src "libresoc.v:760.18-760.111"
1383   wire $and$libresoc.v:760$132_Y
1384   attribute \src "libresoc.v:765.18-765.101"
1385   wire $and$libresoc.v:765$137_Y
1386   attribute \src "libresoc.v:767.18-767.111"
1387   wire $and$libresoc.v:767$139_Y
1388   attribute \src "libresoc.v:709.18-709.103"
1389   wire $eq$libresoc.v:709$81_Y
1390   attribute \src "libresoc.v:714.19-714.104"
1391   wire $eq$libresoc.v:714$86_Y
1392   attribute \src "libresoc.v:715.19-715.104"
1393   wire $eq$libresoc.v:715$87_Y
1394   attribute \src "libresoc.v:716.19-716.104"
1395   wire $eq$libresoc.v:716$88_Y
1396   attribute \src "libresoc.v:718.19-718.104"
1397   wire $eq$libresoc.v:718$90_Y
1398   attribute \src "libresoc.v:719.18-719.103"
1399   wire $eq$libresoc.v:719$91_Y
1400   attribute \src "libresoc.v:723.18-723.103"
1401   wire $eq$libresoc.v:723$95_Y
1402   attribute \src "libresoc.v:724.18-724.103"
1403   wire $eq$libresoc.v:724$96_Y
1404   attribute \src "libresoc.v:730.18-730.103"
1405   wire $eq$libresoc.v:730$102_Y
1406   attribute \src "libresoc.v:731.18-731.103"
1407   wire $eq$libresoc.v:731$103_Y
1408   attribute \src "libresoc.v:732.18-732.103"
1409   wire $eq$libresoc.v:732$104_Y
1410   attribute \src "libresoc.v:738.18-738.103"
1411   wire $eq$libresoc.v:738$110_Y
1412   attribute \src "libresoc.v:739.18-739.103"
1413   wire $eq$libresoc.v:739$111_Y
1414   attribute \src "libresoc.v:740.18-740.103"
1415   wire $eq$libresoc.v:740$112_Y
1416   attribute \src "libresoc.v:745.18-745.103"
1417   wire $eq$libresoc.v:745$117_Y
1418   attribute \src "libresoc.v:746.18-746.103"
1419   wire $eq$libresoc.v:746$118_Y
1420   attribute \src "libresoc.v:747.18-747.103"
1421   wire $eq$libresoc.v:747$119_Y
1422   attribute \src "libresoc.v:753.18-753.103"
1423   wire $eq$libresoc.v:753$125_Y
1424   attribute \src "libresoc.v:754.18-754.103"
1425   wire $eq$libresoc.v:754$126_Y
1426   attribute \src "libresoc.v:755.18-755.103"
1427   wire $eq$libresoc.v:755$127_Y
1428   attribute \src "libresoc.v:761.18-761.103"
1429   wire $eq$libresoc.v:761$133_Y
1430   attribute \src "libresoc.v:762.18-762.103"
1431   wire $eq$libresoc.v:762$134_Y
1432   attribute \src "libresoc.v:763.18-763.103"
1433   wire $eq$libresoc.v:763$135_Y
1434   attribute \src "libresoc.v:768.18-768.103"
1435   wire $eq$libresoc.v:768$140_Y
1436   attribute \src "libresoc.v:769.18-769.103"
1437   wire $eq$libresoc.v:769$141_Y
1438   attribute \src "libresoc.v:710.19-710.99"
1439   wire $not$libresoc.v:710$82_Y
1440   attribute \src "libresoc.v:712.19-712.105"
1441   wire $not$libresoc.v:712$84_Y
1442   attribute \src "libresoc.v:721.19-721.95"
1443   wire $not$libresoc.v:721$93_Y
1444   attribute \src "libresoc.v:725.18-725.98"
1445   wire $not$libresoc.v:725$97_Y
1446   attribute \src "libresoc.v:728.18-728.104"
1447   wire $not$libresoc.v:728$100_Y
1448   attribute \src "libresoc.v:733.18-733.98"
1449   wire $not$libresoc.v:733$105_Y
1450   attribute \src "libresoc.v:735.18-735.104"
1451   wire $not$libresoc.v:735$107_Y
1452   attribute \src "libresoc.v:737.17-737.97"
1453   wire $not$libresoc.v:737$109_Y
1454   attribute \src "libresoc.v:741.18-741.98"
1455   wire $not$libresoc.v:741$113_Y
1456   attribute \src "libresoc.v:743.18-743.104"
1457   wire $not$libresoc.v:743$115_Y
1458   attribute \src "libresoc.v:749.18-749.98"
1459   wire $not$libresoc.v:749$121_Y
1460   attribute \src "libresoc.v:751.18-751.104"
1461   wire $not$libresoc.v:751$123_Y
1462   attribute \src "libresoc.v:756.18-756.98"
1463   wire $not$libresoc.v:756$128_Y
1464   attribute \src "libresoc.v:758.18-758.104"
1465   wire $not$libresoc.v:758$130_Y
1466   attribute \src "libresoc.v:759.17-759.103"
1467   wire $not$libresoc.v:759$131_Y
1468   attribute \src "libresoc.v:764.18-764.98"
1469   wire $not$libresoc.v:764$136_Y
1470   attribute \src "libresoc.v:766.18-766.104"
1471   wire $not$libresoc.v:766$138_Y
1472   attribute \src "libresoc.v:726.17-726.126"
1473   wire width 64 $pos$libresoc.v:726$98_Y
1474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170"
1475   wire width 64 \$1
1476   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1477   wire \$101
1478   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1479   wire \$103
1480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1481   wire \$105
1482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1483   wire \$107
1484   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1485   wire \$109
1486   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1487   wire \$11
1488   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1489   wire \$111
1490   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1491   wire \$113
1492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
1493   wire width 3 \$115
1494   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
1495   wire width 3 \$116
1496   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
1497   wire \$118
1498   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
1499   wire \$120
1500   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
1501   wire \$122
1502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
1503   wire \$124
1504   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1505   wire \$13
1506   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1507   wire \$15
1508   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1509   wire \$17
1510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1511   wire \$19
1512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1513   wire \$21
1514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1515   wire \$23
1516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1517   wire \$25
1518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1519   wire \$27
1520   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1521   wire \$29
1522   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1523   wire \$3
1524   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1525   wire \$31
1526   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1527   wire \$33
1528   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1529   wire \$35
1530   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1531   wire \$37
1532   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1533   wire \$39
1534   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1535   wire \$41
1536   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1537   wire \$43
1538   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1539   wire \$45
1540   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1541   wire \$47
1542   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1543   wire \$49
1544   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1545   wire \$5
1546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1547   wire \$51
1548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1549   wire \$53
1550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1551   wire \$55
1552   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1553   wire \$57
1554   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1555   wire \$59
1556   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1557   wire \$61
1558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1559   wire \$63
1560   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1561   wire \$65
1562   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1563   wire \$67
1564   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1565   wire \$69
1566   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1567   wire \$7
1568   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1569   wire \$71
1570   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1571   wire \$73
1572   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1573   wire \$75
1574   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1575   wire \$77
1576   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1577   wire \$79
1578   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1579   wire \$81
1580   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1581   wire \$83
1582   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1583   wire \$85
1584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1585   wire \$87
1586   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1587   wire \$89
1588   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1589   wire \$9
1590   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1591   wire \$91
1592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1593   wire \$93
1594   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1595   wire \$95
1596   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1597   wire \$97
1598   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1599   wire \$99
1600   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
1601   wire input 24 \clk
1602   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
1603   wire width 64 input 11 \core_dbg_msr
1604   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
1605   wire width 64 input 10 \core_dbg_pc
1606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98"
1607   wire output 8 \core_rst_o
1608   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97"
1609   wire output 12 \core_stop_o
1610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103"
1611   wire input 13 \core_stopped_i
1612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
1613   wire input 20 \d_cr_ack
1614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
1615   wire width 64 input 19 \d_cr_data
1616   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
1617   wire output 18 \d_cr_req
1618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
1619   wire input 17 \d_gpr_ack
1620   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
1621   wire width 7 output 15 \d_gpr_addr
1622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
1623   wire width 64 input 16 \d_gpr_data
1624   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
1625   wire output 14 \d_gpr_req
1626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
1627   wire input 23 \d_xer_ack
1628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
1629   wire width 64 input 22 \d_xer_data
1630   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
1631   wire output 21 \d_xer_req
1632   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
1633   wire output 6 \dmi_ack_o
1634   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
1635   wire width 4 input 2 \dmi_addr_i
1636   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
1637   wire width 64 input 5 \dmi_din
1638   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59"
1639   wire width 64 output 7 \dmi_dout
1640   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148"
1641   wire \dmi_read_log_data
1642   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148"
1643   wire \dmi_read_log_data$next
1644   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149"
1645   wire \dmi_read_log_data_1
1646   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149"
1647   wire \dmi_read_log_data_1$next
1648   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
1649   wire input 3 \dmi_req_i
1650   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131"
1651   wire \dmi_req_i_1
1652   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131"
1653   wire \dmi_req_i_1$next
1654   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
1655   wire input 4 \dmi_we_i
1656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147"
1657   wire \do_dmi_log_rd
1658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147"
1659   wire \do_dmi_log_rd$next
1660   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140"
1661   wire \do_icreset
1662   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140"
1663   wire \do_icreset$next
1664   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139"
1665   wire \do_reset
1666   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139"
1667   wire \do_reset$next
1668   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138"
1669   wire \do_step
1670   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138"
1671   wire \do_step$next
1672   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143"
1673   wire width 7 \gspr_index
1674   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143"
1675   wire width 7 \gspr_index$next
1676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99"
1677   wire \icache_rst_o
1678   attribute \src "libresoc.v:474.7-474.15"
1679   wire \initial
1680   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145"
1681   wire width 32 \log_dmi_addr
1682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145"
1683   wire width 32 \log_dmi_addr$next
1684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146"
1685   wire width 64 \log_dmi_data
1686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119"
1687   wire width 32 \log_write_addr_o
1688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
1689   wire input 1 \rst
1690   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134"
1691   wire width 64 \stat_reg
1692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137"
1693   wire \stopping
1694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137"
1695   wire \stopping$next
1696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102"
1697   wire input 9 \terminate_i
1698   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141"
1699   wire \terminated
1700   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141"
1701   wire \terminated$next
1702   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122"
1703   wire \terminated_o
1704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237"
1705   cell $add $add$libresoc.v:717$89
1706     parameter \A_SIGNED 0
1707     parameter \A_WIDTH 2
1708     parameter \B_SIGNED 0
1709     parameter \B_WIDTH 1
1710     parameter \Y_WIDTH 3
1711     connect \A \log_dmi_addr [1:0]
1712     connect \B 1'1
1713     connect \Y $add$libresoc.v:717$89_Y
1714   end
1715   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1716   cell $and $and$libresoc.v:708$80
1717     parameter \A_SIGNED 0
1718     parameter \A_WIDTH 1
1719     parameter \B_SIGNED 0
1720     parameter \B_WIDTH 1
1721     parameter \Y_WIDTH 1
1722     connect \A \dmi_read_log_data_1
1723     connect \B \$7
1724     connect \Y $and$libresoc.v:708$80_Y
1725   end
1726   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1727   cell $and $and$libresoc.v:711$83
1728     parameter \A_SIGNED 0
1729     parameter \A_WIDTH 1
1730     parameter \B_SIGNED 0
1731     parameter \B_WIDTH 1
1732     parameter \Y_WIDTH 1
1733     connect \A \dmi_req_i
1734     connect \B \$101
1735     connect \Y $and$libresoc.v:711$83_Y
1736   end
1737   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1738   cell $and $and$libresoc.v:713$85
1739     parameter \A_SIGNED 0
1740     parameter \A_WIDTH 1
1741     parameter \B_SIGNED 0
1742     parameter \B_WIDTH 1
1743     parameter \Y_WIDTH 1
1744     connect \A \dmi_read_log_data_1
1745     connect \B \$105
1746     connect \Y $and$libresoc.v:713$85_Y
1747   end
1748   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
1749   cell $and $and$libresoc.v:720$92
1750     parameter \A_SIGNED 0
1751     parameter \A_WIDTH 1
1752     parameter \B_SIGNED 0
1753     parameter \B_WIDTH 1
1754     parameter \Y_WIDTH 1
1755     connect \A \dmi_req_i
1756     connect \B \$118
1757     connect \Y $and$libresoc.v:720$92_Y
1758   end
1759   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
1760   cell $and $and$libresoc.v:722$94
1761     parameter \A_SIGNED 0
1762     parameter \A_WIDTH 1
1763     parameter \B_SIGNED 0
1764     parameter \B_WIDTH 1
1765     parameter \Y_WIDTH 1
1766     connect \A \stopping
1767     connect \B \$122
1768     connect \Y $and$libresoc.v:722$94_Y
1769   end
1770   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1771   cell $and $and$libresoc.v:727$99
1772     parameter \A_SIGNED 0
1773     parameter \A_WIDTH 1
1774     parameter \B_SIGNED 0
1775     parameter \B_WIDTH 1
1776     parameter \Y_WIDTH 1
1777     connect \A \dmi_req_i
1778     connect \B \$17
1779     connect \Y $and$libresoc.v:727$99_Y
1780   end
1781   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1782   cell $and $and$libresoc.v:729$101
1783     parameter \A_SIGNED 0
1784     parameter \A_WIDTH 1
1785     parameter \B_SIGNED 0
1786     parameter \B_WIDTH 1
1787     parameter \Y_WIDTH 1
1788     connect \A \dmi_read_log_data_1
1789     connect \B \$21
1790     connect \Y $and$libresoc.v:729$101_Y
1791   end
1792   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1793   cell $and $and$libresoc.v:734$106
1794     parameter \A_SIGNED 0
1795     parameter \A_WIDTH 1
1796     parameter \B_SIGNED 0
1797     parameter \B_WIDTH 1
1798     parameter \Y_WIDTH 1
1799     connect \A \dmi_req_i
1800     connect \B \$31
1801     connect \Y $and$libresoc.v:734$106_Y
1802   end
1803   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1804   cell $and $and$libresoc.v:736$108
1805     parameter \A_SIGNED 0
1806     parameter \A_WIDTH 1
1807     parameter \B_SIGNED 0
1808     parameter \B_WIDTH 1
1809     parameter \Y_WIDTH 1
1810     connect \A \dmi_read_log_data_1
1811     connect \B \$35
1812     connect \Y $and$libresoc.v:736$108_Y
1813   end
1814   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1815   cell $and $and$libresoc.v:742$114
1816     parameter \A_SIGNED 0
1817     parameter \A_WIDTH 1
1818     parameter \B_SIGNED 0
1819     parameter \B_WIDTH 1
1820     parameter \Y_WIDTH 1
1821     connect \A \dmi_req_i
1822     connect \B \$45
1823     connect \Y $and$libresoc.v:742$114_Y
1824   end
1825   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1826   cell $and $and$libresoc.v:744$116
1827     parameter \A_SIGNED 0
1828     parameter \A_WIDTH 1
1829     parameter \B_SIGNED 0
1830     parameter \B_WIDTH 1
1831     parameter \Y_WIDTH 1
1832     connect \A \dmi_read_log_data_1
1833     connect \B \$49
1834     connect \Y $and$libresoc.v:744$116_Y
1835   end
1836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1837   cell $and $and$libresoc.v:748$120
1838     parameter \A_SIGNED 0
1839     parameter \A_WIDTH 1
1840     parameter \B_SIGNED 0
1841     parameter \B_WIDTH 1
1842     parameter \Y_WIDTH 1
1843     connect \A \dmi_req_i
1844     connect \B \$3
1845     connect \Y $and$libresoc.v:748$120_Y
1846   end
1847   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1848   cell $and $and$libresoc.v:750$122
1849     parameter \A_SIGNED 0
1850     parameter \A_WIDTH 1
1851     parameter \B_SIGNED 0
1852     parameter \B_WIDTH 1
1853     parameter \Y_WIDTH 1
1854     connect \A \dmi_req_i
1855     connect \B \$59
1856     connect \Y $and$libresoc.v:750$122_Y
1857   end
1858   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1859   cell $and $and$libresoc.v:752$124
1860     parameter \A_SIGNED 0
1861     parameter \A_WIDTH 1
1862     parameter \B_SIGNED 0
1863     parameter \B_WIDTH 1
1864     parameter \Y_WIDTH 1
1865     connect \A \dmi_read_log_data_1
1866     connect \B \$63
1867     connect \Y $and$libresoc.v:752$124_Y
1868   end
1869   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1870   cell $and $and$libresoc.v:757$129
1871     parameter \A_SIGNED 0
1872     parameter \A_WIDTH 1
1873     parameter \B_SIGNED 0
1874     parameter \B_WIDTH 1
1875     parameter \Y_WIDTH 1
1876     connect \A \dmi_req_i
1877     connect \B \$73
1878     connect \Y $and$libresoc.v:757$129_Y
1879   end
1880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1881   cell $and $and$libresoc.v:760$132
1882     parameter \A_SIGNED 0
1883     parameter \A_WIDTH 1
1884     parameter \B_SIGNED 0
1885     parameter \B_WIDTH 1
1886     parameter \Y_WIDTH 1
1887     connect \A \dmi_read_log_data_1
1888     connect \B \$77
1889     connect \Y $and$libresoc.v:760$132_Y
1890   end
1891   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
1892   cell $and $and$libresoc.v:765$137
1893     parameter \A_SIGNED 0
1894     parameter \A_WIDTH 1
1895     parameter \B_SIGNED 0
1896     parameter \B_WIDTH 1
1897     parameter \Y_WIDTH 1
1898     connect \A \dmi_req_i
1899     connect \B \$87
1900     connect \Y $and$libresoc.v:765$137_Y
1901   end
1902   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
1903   cell $and $and$libresoc.v:767$139
1904     parameter \A_SIGNED 0
1905     parameter \A_WIDTH 1
1906     parameter \B_SIGNED 0
1907     parameter \B_WIDTH 1
1908     parameter \Y_WIDTH 1
1909     connect \A \dmi_read_log_data_1
1910     connect \B \$91
1911     connect \Y $and$libresoc.v:767$139_Y
1912   end
1913   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1914   cell $eq $eq$libresoc.v:709$81
1915     parameter \A_SIGNED 0
1916     parameter \A_WIDTH 4
1917     parameter \B_SIGNED 0
1918     parameter \B_WIDTH 3
1919     parameter \Y_WIDTH 1
1920     connect \A \dmi_addr_i
1921     connect \B 3'110
1922     connect \Y $eq$libresoc.v:709$81_Y
1923   end
1924   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1925   cell $eq $eq$libresoc.v:714$86
1926     parameter \A_SIGNED 0
1927     parameter \A_WIDTH 4
1928     parameter \B_SIGNED 0
1929     parameter \B_WIDTH 1
1930     parameter \Y_WIDTH 1
1931     connect \A \dmi_addr_i
1932     connect \B 1'0
1933     connect \Y $eq$libresoc.v:714$86_Y
1934   end
1935   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1936   cell $eq $eq$libresoc.v:715$87
1937     parameter \A_SIGNED 0
1938     parameter \A_WIDTH 4
1939     parameter \B_SIGNED 0
1940     parameter \B_WIDTH 3
1941     parameter \Y_WIDTH 1
1942     connect \A \dmi_addr_i
1943     connect \B 3'100
1944     connect \Y $eq$libresoc.v:715$87_Y
1945   end
1946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1947   cell $eq $eq$libresoc.v:716$88
1948     parameter \A_SIGNED 0
1949     parameter \A_WIDTH 4
1950     parameter \B_SIGNED 0
1951     parameter \B_WIDTH 3
1952     parameter \Y_WIDTH 1
1953     connect \A \dmi_addr_i
1954     connect \B 3'110
1955     connect \Y $eq$libresoc.v:716$88_Y
1956   end
1957   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242"
1958   cell $eq $eq$libresoc.v:718$90
1959     parameter \A_SIGNED 0
1960     parameter \A_WIDTH 4
1961     parameter \B_SIGNED 0
1962     parameter \B_WIDTH 3
1963     parameter \Y_WIDTH 1
1964     connect \A \dmi_addr_i
1965     connect \B 3'111
1966     connect \Y $eq$libresoc.v:718$90_Y
1967   end
1968   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
1969   cell $eq $eq$libresoc.v:719$91
1970     parameter \A_SIGNED 0
1971     parameter \A_WIDTH 4
1972     parameter \B_SIGNED 0
1973     parameter \B_WIDTH 1
1974     parameter \Y_WIDTH 1
1975     connect \A \dmi_addr_i
1976     connect \B 1'0
1977     connect \Y $eq$libresoc.v:719$91_Y
1978   end
1979   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
1980   cell $eq $eq$libresoc.v:723$95
1981     parameter \A_SIGNED 0
1982     parameter \A_WIDTH 4
1983     parameter \B_SIGNED 0
1984     parameter \B_WIDTH 3
1985     parameter \Y_WIDTH 1
1986     connect \A \dmi_addr_i
1987     connect \B 3'100
1988     connect \Y $eq$libresoc.v:723$95_Y
1989   end
1990   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
1991   cell $eq $eq$libresoc.v:724$96
1992     parameter \A_SIGNED 0
1993     parameter \A_WIDTH 4
1994     parameter \B_SIGNED 0
1995     parameter \B_WIDTH 3
1996     parameter \Y_WIDTH 1
1997     connect \A \dmi_addr_i
1998     connect \B 3'110
1999     connect \Y $eq$libresoc.v:724$96_Y
2000   end
2001   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2002   cell $eq $eq$libresoc.v:730$102
2003     parameter \A_SIGNED 0
2004     parameter \A_WIDTH 4
2005     parameter \B_SIGNED 0
2006     parameter \B_WIDTH 1
2007     parameter \Y_WIDTH 1
2008     connect \A \dmi_addr_i
2009     connect \B 1'0
2010     connect \Y $eq$libresoc.v:730$102_Y
2011   end
2012   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
2013   cell $eq $eq$libresoc.v:731$103
2014     parameter \A_SIGNED 0
2015     parameter \A_WIDTH 4
2016     parameter \B_SIGNED 0
2017     parameter \B_WIDTH 3
2018     parameter \Y_WIDTH 1
2019     connect \A \dmi_addr_i
2020     connect \B 3'100
2021     connect \Y $eq$libresoc.v:731$103_Y
2022   end
2023   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
2024   cell $eq $eq$libresoc.v:732$104
2025     parameter \A_SIGNED 0
2026     parameter \A_WIDTH 4
2027     parameter \B_SIGNED 0
2028     parameter \B_WIDTH 3
2029     parameter \Y_WIDTH 1
2030     connect \A \dmi_addr_i
2031     connect \B 3'110
2032     connect \Y $eq$libresoc.v:732$104_Y
2033   end
2034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2035   cell $eq $eq$libresoc.v:738$110
2036     parameter \A_SIGNED 0
2037     parameter \A_WIDTH 4
2038     parameter \B_SIGNED 0
2039     parameter \B_WIDTH 1
2040     parameter \Y_WIDTH 1
2041     connect \A \dmi_addr_i
2042     connect \B 1'0
2043     connect \Y $eq$libresoc.v:738$110_Y
2044   end
2045   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
2046   cell $eq $eq$libresoc.v:739$111
2047     parameter \A_SIGNED 0
2048     parameter \A_WIDTH 4
2049     parameter \B_SIGNED 0
2050     parameter \B_WIDTH 3
2051     parameter \Y_WIDTH 1
2052     connect \A \dmi_addr_i
2053     connect \B 3'100
2054     connect \Y $eq$libresoc.v:739$111_Y
2055   end
2056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
2057   cell $eq $eq$libresoc.v:740$112
2058     parameter \A_SIGNED 0
2059     parameter \A_WIDTH 4
2060     parameter \B_SIGNED 0
2061     parameter \B_WIDTH 3
2062     parameter \Y_WIDTH 1
2063     connect \A \dmi_addr_i
2064     connect \B 3'110
2065     connect \Y $eq$libresoc.v:740$112_Y
2066   end
2067   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2068   cell $eq $eq$libresoc.v:745$117
2069     parameter \A_SIGNED 0
2070     parameter \A_WIDTH 4
2071     parameter \B_SIGNED 0
2072     parameter \B_WIDTH 1
2073     parameter \Y_WIDTH 1
2074     connect \A \dmi_addr_i
2075     connect \B 1'0
2076     connect \Y $eq$libresoc.v:745$117_Y
2077   end
2078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
2079   cell $eq $eq$libresoc.v:746$118
2080     parameter \A_SIGNED 0
2081     parameter \A_WIDTH 4
2082     parameter \B_SIGNED 0
2083     parameter \B_WIDTH 3
2084     parameter \Y_WIDTH 1
2085     connect \A \dmi_addr_i
2086     connect \B 3'100
2087     connect \Y $eq$libresoc.v:746$118_Y
2088   end
2089   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
2090   cell $eq $eq$libresoc.v:747$119
2091     parameter \A_SIGNED 0
2092     parameter \A_WIDTH 4
2093     parameter \B_SIGNED 0
2094     parameter \B_WIDTH 3
2095     parameter \Y_WIDTH 1
2096     connect \A \dmi_addr_i
2097     connect \B 3'110
2098     connect \Y $eq$libresoc.v:747$119_Y
2099   end
2100   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2101   cell $eq $eq$libresoc.v:753$125
2102     parameter \A_SIGNED 0
2103     parameter \A_WIDTH 4
2104     parameter \B_SIGNED 0
2105     parameter \B_WIDTH 1
2106     parameter \Y_WIDTH 1
2107     connect \A \dmi_addr_i
2108     connect \B 1'0
2109     connect \Y $eq$libresoc.v:753$125_Y
2110   end
2111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
2112   cell $eq $eq$libresoc.v:754$126
2113     parameter \A_SIGNED 0
2114     parameter \A_WIDTH 4
2115     parameter \B_SIGNED 0
2116     parameter \B_WIDTH 3
2117     parameter \Y_WIDTH 1
2118     connect \A \dmi_addr_i
2119     connect \B 3'100
2120     connect \Y $eq$libresoc.v:754$126_Y
2121   end
2122   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
2123   cell $eq $eq$libresoc.v:755$127
2124     parameter \A_SIGNED 0
2125     parameter \A_WIDTH 4
2126     parameter \B_SIGNED 0
2127     parameter \B_WIDTH 3
2128     parameter \Y_WIDTH 1
2129     connect \A \dmi_addr_i
2130     connect \B 3'110
2131     connect \Y $eq$libresoc.v:755$127_Y
2132   end
2133   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2134   cell $eq $eq$libresoc.v:761$133
2135     parameter \A_SIGNED 0
2136     parameter \A_WIDTH 4
2137     parameter \B_SIGNED 0
2138     parameter \B_WIDTH 1
2139     parameter \Y_WIDTH 1
2140     connect \A \dmi_addr_i
2141     connect \B 1'0
2142     connect \Y $eq$libresoc.v:761$133_Y
2143   end
2144   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
2145   cell $eq $eq$libresoc.v:762$134
2146     parameter \A_SIGNED 0
2147     parameter \A_WIDTH 4
2148     parameter \B_SIGNED 0
2149     parameter \B_WIDTH 3
2150     parameter \Y_WIDTH 1
2151     connect \A \dmi_addr_i
2152     connect \B 3'100
2153     connect \Y $eq$libresoc.v:762$134_Y
2154   end
2155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
2156   cell $eq $eq$libresoc.v:763$135
2157     parameter \A_SIGNED 0
2158     parameter \A_WIDTH 4
2159     parameter \B_SIGNED 0
2160     parameter \B_WIDTH 3
2161     parameter \Y_WIDTH 1
2162     connect \A \dmi_addr_i
2163     connect \B 3'110
2164     connect \Y $eq$libresoc.v:763$135_Y
2165   end
2166   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2167   cell $eq $eq$libresoc.v:768$140
2168     parameter \A_SIGNED 0
2169     parameter \A_WIDTH 4
2170     parameter \B_SIGNED 0
2171     parameter \B_WIDTH 1
2172     parameter \Y_WIDTH 1
2173     connect \A \dmi_addr_i
2174     connect \B 1'0
2175     connect \Y $eq$libresoc.v:768$140_Y
2176   end
2177   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223"
2178   cell $eq $eq$libresoc.v:769$141
2179     parameter \A_SIGNED 0
2180     parameter \A_WIDTH 4
2181     parameter \B_SIGNED 0
2182     parameter \B_WIDTH 3
2183     parameter \Y_WIDTH 1
2184     connect \A \dmi_addr_i
2185     connect \B 3'100
2186     connect \Y $eq$libresoc.v:769$141_Y
2187   end
2188   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2189   cell $not $not$libresoc.v:710$82
2190     parameter \A_SIGNED 0
2191     parameter \A_WIDTH 1
2192     parameter \Y_WIDTH 1
2193     connect \A \dmi_req_i_1
2194     connect \Y $not$libresoc.v:710$82_Y
2195   end
2196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2197   cell $not $not$libresoc.v:712$84
2198     parameter \A_SIGNED 0
2199     parameter \A_WIDTH 1
2200     parameter \Y_WIDTH 1
2201     connect \A \dmi_read_log_data
2202     connect \Y $not$libresoc.v:712$84_Y
2203   end
2204   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254"
2205   cell $not $not$libresoc.v:721$93
2206     parameter \A_SIGNED 0
2207     parameter \A_WIDTH 1
2208     parameter \Y_WIDTH 1
2209     connect \A \do_step
2210     connect \Y $not$libresoc.v:721$93_Y
2211   end
2212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2213   cell $not $not$libresoc.v:725$97
2214     parameter \A_SIGNED 0
2215     parameter \A_WIDTH 1
2216     parameter \Y_WIDTH 1
2217     connect \A \dmi_req_i_1
2218     connect \Y $not$libresoc.v:725$97_Y
2219   end
2220   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2221   cell $not $not$libresoc.v:728$100
2222     parameter \A_SIGNED 0
2223     parameter \A_WIDTH 1
2224     parameter \Y_WIDTH 1
2225     connect \A \dmi_read_log_data
2226     connect \Y $not$libresoc.v:728$100_Y
2227   end
2228   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2229   cell $not $not$libresoc.v:733$105
2230     parameter \A_SIGNED 0
2231     parameter \A_WIDTH 1
2232     parameter \Y_WIDTH 1
2233     connect \A \dmi_req_i_1
2234     connect \Y $not$libresoc.v:733$105_Y
2235   end
2236   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2237   cell $not $not$libresoc.v:735$107
2238     parameter \A_SIGNED 0
2239     parameter \A_WIDTH 1
2240     parameter \Y_WIDTH 1
2241     connect \A \dmi_read_log_data
2242     connect \Y $not$libresoc.v:735$107_Y
2243   end
2244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2245   cell $not $not$libresoc.v:737$109
2246     parameter \A_SIGNED 0
2247     parameter \A_WIDTH 1
2248     parameter \Y_WIDTH 1
2249     connect \A \dmi_req_i_1
2250     connect \Y $not$libresoc.v:737$109_Y
2251   end
2252   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2253   cell $not $not$libresoc.v:741$113
2254     parameter \A_SIGNED 0
2255     parameter \A_WIDTH 1
2256     parameter \Y_WIDTH 1
2257     connect \A \dmi_req_i_1
2258     connect \Y $not$libresoc.v:741$113_Y
2259   end
2260   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2261   cell $not $not$libresoc.v:743$115
2262     parameter \A_SIGNED 0
2263     parameter \A_WIDTH 1
2264     parameter \Y_WIDTH 1
2265     connect \A \dmi_read_log_data
2266     connect \Y $not$libresoc.v:743$115_Y
2267   end
2268   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2269   cell $not $not$libresoc.v:749$121
2270     parameter \A_SIGNED 0
2271     parameter \A_WIDTH 1
2272     parameter \Y_WIDTH 1
2273     connect \A \dmi_req_i_1
2274     connect \Y $not$libresoc.v:749$121_Y
2275   end
2276   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2277   cell $not $not$libresoc.v:751$123
2278     parameter \A_SIGNED 0
2279     parameter \A_WIDTH 1
2280     parameter \Y_WIDTH 1
2281     connect \A \dmi_read_log_data
2282     connect \Y $not$libresoc.v:751$123_Y
2283   end
2284   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2285   cell $not $not$libresoc.v:756$128
2286     parameter \A_SIGNED 0
2287     parameter \A_WIDTH 1
2288     parameter \Y_WIDTH 1
2289     connect \A \dmi_req_i_1
2290     connect \Y $not$libresoc.v:756$128_Y
2291   end
2292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2293   cell $not $not$libresoc.v:758$130
2294     parameter \A_SIGNED 0
2295     parameter \A_WIDTH 1
2296     parameter \Y_WIDTH 1
2297     connect \A \dmi_read_log_data
2298     connect \Y $not$libresoc.v:758$130_Y
2299   end
2300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2301   cell $not $not$libresoc.v:759$131
2302     parameter \A_SIGNED 0
2303     parameter \A_WIDTH 1
2304     parameter \Y_WIDTH 1
2305     connect \A \dmi_read_log_data
2306     connect \Y $not$libresoc.v:759$131_Y
2307   end
2308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2309   cell $not $not$libresoc.v:764$136
2310     parameter \A_SIGNED 0
2311     parameter \A_WIDTH 1
2312     parameter \Y_WIDTH 1
2313     connect \A \dmi_req_i_1
2314     connect \Y $not$libresoc.v:764$136_Y
2315   end
2316   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234"
2317   cell $not $not$libresoc.v:766$138
2318     parameter \A_SIGNED 0
2319     parameter \A_WIDTH 1
2320     parameter \Y_WIDTH 1
2321     connect \A \dmi_read_log_data
2322     connect \Y $not$libresoc.v:766$138_Y
2323   end
2324   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170"
2325   cell $pos $pos$libresoc.v:726$98
2326     parameter \A_SIGNED 0
2327     parameter \A_WIDTH 64
2328     parameter \Y_WIDTH 64
2329     connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping }
2330     connect \Y $pos$libresoc.v:726$98_Y
2331   end
2332   attribute \src "libresoc.v:1003.3-1012.6"
2333   process $proc$libresoc.v:1003$195
2334     assign { } { }
2335     assign { } { }
2336     assign $0\d_cr_req[0:0] $1\d_cr_req[0:0]
2337     attribute \src "libresoc.v:1004.5-1004.29"
2338     switch \initial
2339       attribute \src "libresoc.v:1004.9-1004.17"
2340       case 1'1
2341       case
2342     end
2343     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
2344     switch \dmi_addr_i
2345       attribute \src "libresoc.v:0.0-0.0"
2346       case 4'1000
2347         assign { } { }
2348         assign $1\d_cr_req[0:0] \dmi_req_i
2349       case
2350         assign $1\d_cr_req[0:0] 1'0
2351     end
2352     sync always
2353       update \d_cr_req $0\d_cr_req[0:0]
2354   end
2355   attribute \src "libresoc.v:1013.3-1022.6"
2356   process $proc$libresoc.v:1013$196
2357     assign { } { }
2358     assign { } { }
2359     assign $0\d_xer_req[0:0] $1\d_xer_req[0:0]
2360     attribute \src "libresoc.v:1014.5-1014.29"
2361     switch \initial
2362       attribute \src "libresoc.v:1014.9-1014.17"
2363       case 1'1
2364       case
2365     end
2366     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
2367     switch \dmi_addr_i
2368       attribute \src "libresoc.v:0.0-0.0"
2369       case 4'1001
2370         assign { } { }
2371         assign $1\d_xer_req[0:0] \dmi_req_i
2372       case
2373         assign $1\d_xer_req[0:0] 1'0
2374     end
2375     sync always
2376       update \d_xer_req $0\d_xer_req[0:0]
2377   end
2378   attribute \src "libresoc.v:1023.3-1053.6"
2379   process $proc$libresoc.v:1023$197
2380     assign { } { }
2381     assign { } { }
2382     assign $0\dmi_dout[63:0] $1\dmi_dout[63:0]
2383     attribute \src "libresoc.v:1024.5-1024.29"
2384     switch \initial
2385       attribute \src "libresoc.v:1024.9-1024.17"
2386       case 1'1
2387       case
2388     end
2389     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173"
2390     switch \dmi_addr_i
2391       attribute \src "libresoc.v:0.0-0.0"
2392       case 4'0001
2393         assign { } { }
2394         assign $1\dmi_dout[63:0] \stat_reg
2395       attribute \src "libresoc.v:0.0-0.0"
2396       case 4'0010
2397         assign { } { }
2398         assign $1\dmi_dout[63:0] \core_dbg_pc
2399       attribute \src "libresoc.v:0.0-0.0"
2400       case 4'0011
2401         assign { } { }
2402         assign $1\dmi_dout[63:0] \core_dbg_msr
2403       attribute \src "libresoc.v:0.0-0.0"
2404       case 4'0101
2405         assign { } { }
2406         assign $1\dmi_dout[63:0] \d_gpr_data
2407       attribute \src "libresoc.v:0.0-0.0"
2408       case 4'0110
2409         assign { } { }
2410         assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr }
2411       attribute \src "libresoc.v:0.0-0.0"
2412       case 4'0111
2413         assign { } { }
2414         assign $1\dmi_dout[63:0] \log_dmi_data
2415       attribute \src "libresoc.v:0.0-0.0"
2416       case 4'1000
2417         assign { } { }
2418         assign $1\dmi_dout[63:0] \d_cr_data
2419       attribute \src "libresoc.v:0.0-0.0"
2420       case 4'1001
2421         assign { } { }
2422         assign $1\dmi_dout[63:0] \d_xer_data
2423       case
2424         assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
2425     end
2426     sync always
2427       update \dmi_dout $0\dmi_dout[63:0]
2428   end
2429   attribute \src "libresoc.v:1054.3-1083.6"
2430   process $proc$libresoc.v:1054$198
2431     assign { } { }
2432     assign { } { }
2433     assign { } { }
2434     assign $0\do_step$next[0:0]$199 $5\do_step$next[0:0]$204
2435     attribute \src "libresoc.v:1055.5-1055.29"
2436     switch \initial
2437       attribute \src "libresoc.v:1055.9-1055.17"
2438       case 1'1
2439       case
2440     end
2441     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2442     switch { \$9 \$5 }
2443       attribute \src "libresoc.v:0.0-0.0"
2444       case 2'-1
2445         assign { } { }
2446         assign $1\do_step$next[0:0]$200 $2\do_step$next[0:0]$201
2447         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
2448         switch \dmi_we_i
2449           attribute \src "libresoc.v:0.0-0.0"
2450           case 1'1
2451             assign { } { }
2452             assign $2\do_step$next[0:0]$201 $3\do_step$next[0:0]$202
2453             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2454             switch { \$15 \$13 \$11 }
2455               attribute \src "libresoc.v:0.0-0.0"
2456               case 3'--1
2457                 assign { } { }
2458                 assign $3\do_step$next[0:0]$202 $4\do_step$next[0:0]$203
2459                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213"
2460                 switch \dmi_din [3]
2461                   attribute \src "libresoc.v:0.0-0.0"
2462                   case 1'1
2463                     assign { } { }
2464                     assign $4\do_step$next[0:0]$203 1'1
2465                   case
2466                     assign $4\do_step$next[0:0]$203 1'0
2467                 end
2468               case
2469                 assign $3\do_step$next[0:0]$202 1'0
2470             end
2471           case
2472             assign $2\do_step$next[0:0]$201 1'0
2473         end
2474       case
2475         assign $1\do_step$next[0:0]$200 1'0
2476     end
2477     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
2478     switch \rst
2479       attribute \src "libresoc.v:0.0-0.0"
2480       case 1'1
2481         assign { } { }
2482         assign $5\do_step$next[0:0]$204 1'0
2483       case
2484         assign $5\do_step$next[0:0]$204 $1\do_step$next[0:0]$200
2485     end
2486     sync always
2487       update \do_step$next $0\do_step$next[0:0]$199
2488   end
2489   attribute \src "libresoc.v:1084.3-1113.6"
2490   process $proc$libresoc.v:1084$205
2491     assign { } { }
2492     assign { } { }
2493     assign { } { }
2494     assign $0\do_reset$next[0:0]$206 $5\do_reset$next[0:0]$211
2495     attribute \src "libresoc.v:1085.5-1085.29"
2496     switch \initial
2497       attribute \src "libresoc.v:1085.9-1085.17"
2498       case 1'1
2499       case
2500     end
2501     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2502     switch { \$23 \$19 }
2503       attribute \src "libresoc.v:0.0-0.0"
2504       case 2'-1
2505         assign { } { }
2506         assign $1\do_reset$next[0:0]$207 $2\do_reset$next[0:0]$208
2507         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
2508         switch \dmi_we_i
2509           attribute \src "libresoc.v:0.0-0.0"
2510           case 1'1
2511             assign { } { }
2512             assign $2\do_reset$next[0:0]$208 $3\do_reset$next[0:0]$209
2513             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2514             switch { \$29 \$27 \$25 }
2515               attribute \src "libresoc.v:0.0-0.0"
2516               case 3'--1
2517                 assign { } { }
2518                 assign $3\do_reset$next[0:0]$209 $4\do_reset$next[0:0]$210
2519                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
2520                 switch \dmi_din [1]
2521                   attribute \src "libresoc.v:0.0-0.0"
2522                   case 1'1
2523                     assign { } { }
2524                     assign $4\do_reset$next[0:0]$210 1'1
2525                   case
2526                     assign $4\do_reset$next[0:0]$210 1'0
2527                 end
2528               case
2529                 assign $3\do_reset$next[0:0]$209 1'0
2530             end
2531           case
2532             assign $2\do_reset$next[0:0]$208 1'0
2533         end
2534       case
2535         assign $1\do_reset$next[0:0]$207 1'0
2536     end
2537     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
2538     switch \rst
2539       attribute \src "libresoc.v:0.0-0.0"
2540       case 1'1
2541         assign { } { }
2542         assign $5\do_reset$next[0:0]$211 1'0
2543       case
2544         assign $5\do_reset$next[0:0]$211 $1\do_reset$next[0:0]$207
2545     end
2546     sync always
2547       update \do_reset$next $0\do_reset$next[0:0]$206
2548   end
2549   attribute \src "libresoc.v:1114.3-1143.6"
2550   process $proc$libresoc.v:1114$212
2551     assign { } { }
2552     assign { } { }
2553     assign { } { }
2554     assign $0\do_icreset$next[0:0]$213 $5\do_icreset$next[0:0]$218
2555     attribute \src "libresoc.v:1115.5-1115.29"
2556     switch \initial
2557       attribute \src "libresoc.v:1115.9-1115.17"
2558       case 1'1
2559       case
2560     end
2561     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2562     switch { \$37 \$33 }
2563       attribute \src "libresoc.v:0.0-0.0"
2564       case 2'-1
2565         assign { } { }
2566         assign $1\do_icreset$next[0:0]$214 $2\do_icreset$next[0:0]$215
2567         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
2568         switch \dmi_we_i
2569           attribute \src "libresoc.v:0.0-0.0"
2570           case 1'1
2571             assign { } { }
2572             assign $2\do_icreset$next[0:0]$215 $3\do_icreset$next[0:0]$216
2573             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2574             switch { \$43 \$41 \$39 }
2575               attribute \src "libresoc.v:0.0-0.0"
2576               case 3'--1
2577                 assign { } { }
2578                 assign $3\do_icreset$next[0:0]$216 $4\do_icreset$next[0:0]$217
2579                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216"
2580                 switch \dmi_din [2]
2581                   attribute \src "libresoc.v:0.0-0.0"
2582                   case 1'1
2583                     assign { } { }
2584                     assign $4\do_icreset$next[0:0]$217 1'1
2585                   case
2586                     assign $4\do_icreset$next[0:0]$217 1'0
2587                 end
2588               case
2589                 assign $3\do_icreset$next[0:0]$216 1'0
2590             end
2591           case
2592             assign $2\do_icreset$next[0:0]$215 1'0
2593         end
2594       case
2595         assign $1\do_icreset$next[0:0]$214 1'0
2596     end
2597     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
2598     switch \rst
2599       attribute \src "libresoc.v:0.0-0.0"
2600       case 1'1
2601         assign { } { }
2602         assign $5\do_icreset$next[0:0]$218 1'0
2603       case
2604         assign $5\do_icreset$next[0:0]$218 $1\do_icreset$next[0:0]$214
2605     end
2606     sync always
2607       update \do_icreset$next $0\do_icreset$next[0:0]$213
2608   end
2609   attribute \src "libresoc.v:1144.3-1177.6"
2610   process $proc$libresoc.v:1144$219
2611     assign { } { }
2612     assign { } { }
2613     assign { } { }
2614     assign $0\do_dmi_log_rd$next[0:0]$220 $4\do_dmi_log_rd$next[0:0]$224
2615     attribute \src "libresoc.v:1145.5-1145.29"
2616     switch \initial
2617       attribute \src "libresoc.v:1145.9-1145.17"
2618       case 1'1
2619       case
2620     end
2621     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2622     switch { \$51 \$47 }
2623       attribute \src "libresoc.v:0.0-0.0"
2624       case 2'-1
2625         assign { } { }
2626         assign $1\do_dmi_log_rd$next[0:0]$221 $2\do_dmi_log_rd$next[0:0]$222
2627         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
2628         switch \dmi_we_i
2629           attribute \src "libresoc.v:0.0-0.0"
2630           case 1'1
2631             assign { } { }
2632             assign $2\do_dmi_log_rd$next[0:0]$222 $3\do_dmi_log_rd$next[0:0]$223
2633             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2634             switch { \$57 \$55 \$53 }
2635               attribute \src "libresoc.v:0.0-0.0"
2636               case 3'--1
2637                 assign $3\do_dmi_log_rd$next[0:0]$223 1'0
2638               attribute \src "libresoc.v:0.0-0.0"
2639               case 3'-1-
2640                 assign $3\do_dmi_log_rd$next[0:0]$223 1'0
2641               attribute \src "libresoc.v:0.0-0.0"
2642               case 3'1--
2643                 assign { } { }
2644                 assign $3\do_dmi_log_rd$next[0:0]$223 1'1
2645               case
2646                 assign $3\do_dmi_log_rd$next[0:0]$223 1'0
2647             end
2648           case
2649             assign $2\do_dmi_log_rd$next[0:0]$222 1'0
2650         end
2651       attribute \src "libresoc.v:0.0-0.0"
2652       case 2'1-
2653         assign { } { }
2654         assign $1\do_dmi_log_rd$next[0:0]$221 1'1
2655       case
2656         assign $1\do_dmi_log_rd$next[0:0]$221 1'0
2657     end
2658     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
2659     switch \rst
2660       attribute \src "libresoc.v:0.0-0.0"
2661       case 1'1
2662         assign { } { }
2663         assign $4\do_dmi_log_rd$next[0:0]$224 1'0
2664       case
2665         assign $4\do_dmi_log_rd$next[0:0]$224 $1\do_dmi_log_rd$next[0:0]$221
2666     end
2667     sync always
2668       update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$220
2669   end
2670   attribute \src "libresoc.v:474.7-474.20"
2671   process $proc$libresoc.v:474$225
2672     assign { } { }
2673     assign $0\initial[0:0] 1'0
2674     sync always
2675       update \initial $0\initial[0:0]
2676     sync init
2677   end
2678   attribute \src "libresoc.v:647.7-647.31"
2679   process $proc$libresoc.v:647$226
2680     assign { } { }
2681     assign $1\dmi_read_log_data[0:0] 1'0
2682     sync always
2683     sync init
2684       update \dmi_read_log_data $1\dmi_read_log_data[0:0]
2685   end
2686   attribute \src "libresoc.v:651.7-651.33"
2687   process $proc$libresoc.v:651$227
2688     assign { } { }
2689     assign $1\dmi_read_log_data_1[0:0] 1'0
2690     sync always
2691     sync init
2692       update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0]
2693   end
2694   attribute \src "libresoc.v:657.7-657.25"
2695   process $proc$libresoc.v:657$228
2696     assign { } { }
2697     assign $1\dmi_req_i_1[0:0] 1'0
2698     sync always
2699     sync init
2700       update \dmi_req_i_1 $1\dmi_req_i_1[0:0]
2701   end
2702   attribute \src "libresoc.v:663.7-663.27"
2703   process $proc$libresoc.v:663$229
2704     assign { } { }
2705     assign $1\do_dmi_log_rd[0:0] 1'0
2706     sync always
2707     sync init
2708       update \do_dmi_log_rd $1\do_dmi_log_rd[0:0]
2709   end
2710   attribute \src "libresoc.v:667.7-667.24"
2711   process $proc$libresoc.v:667$230
2712     assign { } { }
2713     assign $1\do_icreset[0:0] 1'0
2714     sync always
2715     sync init
2716       update \do_icreset $1\do_icreset[0:0]
2717   end
2718   attribute \src "libresoc.v:671.7-671.22"
2719   process $proc$libresoc.v:671$231
2720     assign { } { }
2721     assign $1\do_reset[0:0] 1'0
2722     sync always
2723     sync init
2724       update \do_reset $1\do_reset[0:0]
2725   end
2726   attribute \src "libresoc.v:675.7-675.21"
2727   process $proc$libresoc.v:675$232
2728     assign { } { }
2729     assign $1\do_step[0:0] 1'0
2730     sync always
2731     sync init
2732       update \do_step $1\do_step[0:0]
2733   end
2734   attribute \src "libresoc.v:679.13-679.31"
2735   process $proc$libresoc.v:679$233
2736     assign { } { }
2737     assign $1\gspr_index[6:0] 7'0000000
2738     sync always
2739     sync init
2740       update \gspr_index $1\gspr_index[6:0]
2741   end
2742   attribute \src "libresoc.v:685.14-685.34"
2743   process $proc$libresoc.v:685$234
2744     assign { } { }
2745     assign $1\log_dmi_addr[31:0] 0
2746     sync always
2747     sync init
2748       update \log_dmi_addr $1\log_dmi_addr[31:0]
2749   end
2750   attribute \src "libresoc.v:697.7-697.22"
2751   process $proc$libresoc.v:697$235
2752     assign { } { }
2753     assign $1\stopping[0:0] 1'0
2754     sync always
2755     sync init
2756       update \stopping $1\stopping[0:0]
2757   end
2758   attribute \src "libresoc.v:703.7-703.24"
2759   process $proc$libresoc.v:703$236
2760     assign { } { }
2761     assign $1\terminated[0:0] 1'0
2762     sync always
2763     sync init
2764       update \terminated $1\terminated[0:0]
2765   end
2766   attribute \src "libresoc.v:770.3-771.51"
2767   process $proc$libresoc.v:770$142
2768     assign { } { }
2769     assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next
2770     sync posedge \clk
2771       update \dmi_read_log_data $0\dmi_read_log_data[0:0]
2772   end
2773   attribute \src "libresoc.v:772.3-773.55"
2774   process $proc$libresoc.v:772$143
2775     assign { } { }
2776     assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next
2777     sync posedge \clk
2778       update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0]
2779   end
2780   attribute \src "libresoc.v:774.3-775.41"
2781   process $proc$libresoc.v:774$144
2782     assign { } { }
2783     assign $0\log_dmi_addr[31:0] \log_dmi_addr$next
2784     sync posedge \clk
2785       update \log_dmi_addr $0\log_dmi_addr[31:0]
2786   end
2787   attribute \src "libresoc.v:776.3-777.37"
2788   process $proc$libresoc.v:776$145
2789     assign { } { }
2790     assign $0\gspr_index[6:0] \gspr_index$next
2791     sync posedge \clk
2792       update \gspr_index $0\gspr_index[6:0]
2793   end
2794   attribute \src "libresoc.v:778.3-779.33"
2795   process $proc$libresoc.v:778$146
2796     assign { } { }
2797     assign $0\stopping[0:0] \stopping$next
2798     sync posedge \clk
2799       update \stopping $0\stopping[0:0]
2800   end
2801   attribute \src "libresoc.v:780.3-781.37"
2802   process $proc$libresoc.v:780$147
2803     assign { } { }
2804     assign $0\terminated[0:0] \terminated$next
2805     sync posedge \clk
2806       update \terminated $0\terminated[0:0]
2807   end
2808   attribute \src "libresoc.v:782.3-783.39"
2809   process $proc$libresoc.v:782$148
2810     assign { } { }
2811     assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next
2812     sync posedge \clk
2813       update \dmi_req_i_1 $0\dmi_req_i_1[0:0]
2814   end
2815   attribute \src "libresoc.v:784.3-785.43"
2816   process $proc$libresoc.v:784$149
2817     assign { } { }
2818     assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next
2819     sync posedge \clk
2820       update \do_dmi_log_rd $0\do_dmi_log_rd[0:0]
2821   end
2822   attribute \src "libresoc.v:786.3-787.37"
2823   process $proc$libresoc.v:786$150
2824     assign { } { }
2825     assign $0\do_icreset[0:0] \do_icreset$next
2826     sync posedge \clk
2827       update \do_icreset $0\do_icreset[0:0]
2828   end
2829   attribute \src "libresoc.v:788.3-789.33"
2830   process $proc$libresoc.v:788$151
2831     assign { } { }
2832     assign $0\do_reset[0:0] \do_reset$next
2833     sync posedge \clk
2834       update \do_reset $0\do_reset[0:0]
2835   end
2836   attribute \src "libresoc.v:790.3-791.31"
2837   process $proc$libresoc.v:790$152
2838     assign { } { }
2839     assign $0\do_step[0:0] \do_step$next
2840     sync posedge \clk
2841       update \do_step $0\do_step[0:0]
2842   end
2843   attribute \src "libresoc.v:792.3-809.6"
2844   process $proc$libresoc.v:792$153
2845     assign { } { }
2846     assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0]
2847     attribute \src "libresoc.v:793.5-793.29"
2848     switch \initial
2849       attribute \src "libresoc.v:793.9-793.17"
2850       case 1'1
2851       case
2852     end
2853     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
2854     switch \dmi_addr_i
2855       attribute \src "libresoc.v:0.0-0.0"
2856       case 4'0101
2857         assign { } { }
2858         assign $1\dmi_ack_o[0:0] \d_gpr_ack
2859       attribute \src "libresoc.v:0.0-0.0"
2860       case 4'1000
2861         assign { } { }
2862         assign $1\dmi_ack_o[0:0] \d_cr_ack
2863       attribute \src "libresoc.v:0.0-0.0"
2864       case 4'1001
2865         assign { } { }
2866         assign $1\dmi_ack_o[0:0] \d_xer_ack
2867       attribute \src "libresoc.v:0.0-0.0"
2868       case
2869         assign { } { }
2870         assign $1\dmi_ack_o[0:0] \dmi_req_i
2871     end
2872     sync always
2873       update \dmi_ack_o $0\dmi_ack_o[0:0]
2874   end
2875   attribute \src "libresoc.v:810.3-819.6"
2876   process $proc$libresoc.v:810$154
2877     assign { } { }
2878     assign { } { }
2879     assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0]
2880     attribute \src "libresoc.v:811.5-811.29"
2881     switch \initial
2882       attribute \src "libresoc.v:811.9-811.17"
2883       case 1'1
2884       case
2885     end
2886     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154"
2887     switch \dmi_addr_i
2888       attribute \src "libresoc.v:0.0-0.0"
2889       case 4'0101
2890         assign { } { }
2891         assign $1\d_gpr_req[0:0] \dmi_req_i
2892       case
2893         assign $1\d_gpr_req[0:0] 1'0
2894     end
2895     sync always
2896       update \d_gpr_req $0\d_gpr_req[0:0]
2897   end
2898   attribute \src "libresoc.v:820.3-828.6"
2899   process $proc$libresoc.v:820$155
2900     assign { } { }
2901     assign { } { }
2902     assign $0\dmi_req_i_1$next[0:0]$156 $1\dmi_req_i_1$next[0:0]$157
2903     attribute \src "libresoc.v:821.5-821.29"
2904     switch \initial
2905       attribute \src "libresoc.v:821.9-821.17"
2906       case 1'1
2907       case
2908     end
2909     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
2910     switch \rst
2911       attribute \src "libresoc.v:0.0-0.0"
2912       case 1'1
2913         assign { } { }
2914         assign $1\dmi_req_i_1$next[0:0]$157 1'0
2915       case
2916         assign $1\dmi_req_i_1$next[0:0]$157 \dmi_req_i
2917     end
2918     sync always
2919       update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$156
2920   end
2921   attribute \src "libresoc.v:829.3-878.6"
2922   process $proc$libresoc.v:829$158
2923     assign { } { }
2924     assign { } { }
2925     assign { } { }
2926     assign { } { }
2927     assign $0\terminated$next[0:0]$159 $8\terminated$next[0:0]$167
2928     attribute \src "libresoc.v:830.5-830.29"
2929     switch \initial
2930       attribute \src "libresoc.v:830.9-830.17"
2931       case 1'1
2932       case
2933     end
2934     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
2935     switch { \$65 \$61 }
2936       attribute \src "libresoc.v:0.0-0.0"
2937       case 2'-1
2938         assign { } { }
2939         assign $1\terminated$next[0:0]$160 $2\terminated$next[0:0]$161
2940         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
2941         switch \dmi_we_i
2942           attribute \src "libresoc.v:0.0-0.0"
2943           case 1'1
2944             assign { } { }
2945             assign $2\terminated$next[0:0]$161 $3\terminated$next[0:0]$162
2946             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
2947             switch { \$71 \$69 \$67 }
2948               attribute \src "libresoc.v:0.0-0.0"
2949               case 3'--1
2950                 assign { } { }
2951                 assign { } { }
2952                 assign { } { }
2953                 assign $3\terminated$next[0:0]$162 $6\terminated$next[0:0]$165
2954                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208"
2955                 switch \dmi_din [1]
2956                   attribute \src "libresoc.v:0.0-0.0"
2957                   case 1'1
2958                     assign { } { }
2959                     assign $4\terminated$next[0:0]$163 1'0
2960                   case
2961                     assign $4\terminated$next[0:0]$163 \terminated
2962                 end
2963                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213"
2964                 switch \dmi_din [3]
2965                   attribute \src "libresoc.v:0.0-0.0"
2966                   case 1'1
2967                     assign { } { }
2968                     assign $5\terminated$next[0:0]$164 1'0
2969                   case
2970                     assign $5\terminated$next[0:0]$164 $4\terminated$next[0:0]$163
2971                 end
2972                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
2973                 switch \dmi_din [4]
2974                   attribute \src "libresoc.v:0.0-0.0"
2975                   case 1'1
2976                     assign { } { }
2977                     assign $6\terminated$next[0:0]$165 1'0
2978                   case
2979                     assign $6\terminated$next[0:0]$165 $5\terminated$next[0:0]$164
2980                 end
2981               case
2982                 assign $3\terminated$next[0:0]$162 \terminated
2983             end
2984           case
2985             assign $2\terminated$next[0:0]$161 \terminated
2986         end
2987       case
2988         assign $1\terminated$next[0:0]$160 \terminated
2989     end
2990     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
2991     switch \terminate_i
2992       attribute \src "libresoc.v:0.0-0.0"
2993       case 1'1
2994         assign { } { }
2995         assign $7\terminated$next[0:0]$166 1'1
2996       case
2997         assign $7\terminated$next[0:0]$166 $1\terminated$next[0:0]$160
2998     end
2999     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
3000     switch \rst
3001       attribute \src "libresoc.v:0.0-0.0"
3002       case 1'1
3003         assign { } { }
3004         assign $8\terminated$next[0:0]$167 1'0
3005       case
3006         assign $8\terminated$next[0:0]$167 $7\terminated$next[0:0]$166
3007     end
3008     sync always
3009       update \terminated$next $0\terminated$next[0:0]$159
3010   end
3011   attribute \src "libresoc.v:879.3-922.6"
3012   process $proc$libresoc.v:879$168
3013     assign { } { }
3014     assign { } { }
3015     assign { } { }
3016     assign { } { }
3017     assign $0\stopping$next[0:0]$169 $7\stopping$next[0:0]$176
3018     attribute \src "libresoc.v:880.5-880.29"
3019     switch \initial
3020       attribute \src "libresoc.v:880.9-880.17"
3021       case 1'1
3022       case
3023     end
3024     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
3025     switch { \$79 \$75 }
3026       attribute \src "libresoc.v:0.0-0.0"
3027       case 2'-1
3028         assign { } { }
3029         assign $1\stopping$next[0:0]$170 $2\stopping$next[0:0]$171
3030         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
3031         switch \dmi_we_i
3032           attribute \src "libresoc.v:0.0-0.0"
3033           case 1'1
3034             assign { } { }
3035             assign $2\stopping$next[0:0]$171 $3\stopping$next[0:0]$172
3036             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
3037             switch { \$85 \$83 \$81 }
3038               attribute \src "libresoc.v:0.0-0.0"
3039               case 3'--1
3040                 assign { } { }
3041                 assign { } { }
3042                 assign $3\stopping$next[0:0]$172 $5\stopping$next[0:0]$174
3043                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
3044                 switch \dmi_din [0]
3045                   attribute \src "libresoc.v:0.0-0.0"
3046                   case 1'1
3047                     assign { } { }
3048                     assign $4\stopping$next[0:0]$173 1'1
3049                   case
3050                     assign $4\stopping$next[0:0]$173 \stopping
3051                 end
3052                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
3053                 switch \dmi_din [4]
3054                   attribute \src "libresoc.v:0.0-0.0"
3055                   case 1'1
3056                     assign { } { }
3057                     assign $5\stopping$next[0:0]$174 1'0
3058                   case
3059                     assign $5\stopping$next[0:0]$174 $4\stopping$next[0:0]$173
3060                 end
3061               case
3062                 assign $3\stopping$next[0:0]$172 \stopping
3063             end
3064           case
3065             assign $2\stopping$next[0:0]$171 \stopping
3066         end
3067       case
3068         assign $1\stopping$next[0:0]$170 \stopping
3069     end
3070     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247"
3071     switch \terminate_i
3072       attribute \src "libresoc.v:0.0-0.0"
3073       case 1'1
3074         assign { } { }
3075         assign $6\stopping$next[0:0]$175 1'1
3076       case
3077         assign $6\stopping$next[0:0]$175 $1\stopping$next[0:0]$170
3078     end
3079     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
3080     switch \rst
3081       attribute \src "libresoc.v:0.0-0.0"
3082       case 1'1
3083         assign { } { }
3084         assign $7\stopping$next[0:0]$176 1'0
3085       case
3086         assign $7\stopping$next[0:0]$176 $6\stopping$next[0:0]$175
3087     end
3088     sync always
3089       update \stopping$next $0\stopping$next[0:0]$169
3090   end
3091   attribute \src "libresoc.v:923.3-950.6"
3092   process $proc$libresoc.v:923$177
3093     assign { } { }
3094     assign { } { }
3095     assign { } { }
3096     assign $0\gspr_index$next[6:0]$178 $4\gspr_index$next[6:0]$182
3097     attribute \src "libresoc.v:924.5-924.29"
3098     switch \initial
3099       attribute \src "libresoc.v:924.9-924.17"
3100       case 1'1
3101       case
3102     end
3103     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
3104     switch { \$93 \$89 }
3105       attribute \src "libresoc.v:0.0-0.0"
3106       case 2'-1
3107         assign { } { }
3108         assign $1\gspr_index$next[6:0]$179 $2\gspr_index$next[6:0]$180
3109         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
3110         switch \dmi_we_i
3111           attribute \src "libresoc.v:0.0-0.0"
3112           case 1'1
3113             assign { } { }
3114             assign $2\gspr_index$next[6:0]$180 $3\gspr_index$next[6:0]$181
3115             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
3116             switch { \$99 \$97 \$95 }
3117               attribute \src "libresoc.v:0.0-0.0"
3118               case 3'--1
3119                 assign $3\gspr_index$next[6:0]$181 \gspr_index
3120               attribute \src "libresoc.v:0.0-0.0"
3121               case 3'-1-
3122                 assign { } { }
3123                 assign $3\gspr_index$next[6:0]$181 \dmi_din [6:0]
3124               case
3125                 assign $3\gspr_index$next[6:0]$181 \gspr_index
3126             end
3127           case
3128             assign $2\gspr_index$next[6:0]$180 \gspr_index
3129         end
3130       case
3131         assign $1\gspr_index$next[6:0]$179 \gspr_index
3132     end
3133     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
3134     switch \rst
3135       attribute \src "libresoc.v:0.0-0.0"
3136       case 1'1
3137         assign { } { }
3138         assign $4\gspr_index$next[6:0]$182 7'0000000
3139       case
3140         assign $4\gspr_index$next[6:0]$182 $1\gspr_index$next[6:0]$179
3141     end
3142     sync always
3143       update \gspr_index$next $0\gspr_index$next[6:0]$178
3144   end
3145   attribute \src "libresoc.v:951.3-984.6"
3146   process $proc$libresoc.v:951$183
3147     assign { } { }
3148     assign { } { }
3149     assign { } { }
3150     assign $0\log_dmi_addr$next[31:0]$184 $4\log_dmi_addr$next[31:0]$188
3151     attribute \src "libresoc.v:952.5-952.29"
3152     switch \initial
3153       attribute \src "libresoc.v:952.9-952.17"
3154       case 1'1
3155       case
3156     end
3157     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200"
3158     switch { \$107 \$103 }
3159       attribute \src "libresoc.v:0.0-0.0"
3160       case 2'-1
3161         assign { } { }
3162         assign $1\log_dmi_addr$next[31:0]$185 $2\log_dmi_addr$next[31:0]$186
3163         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
3164         switch \dmi_we_i
3165           attribute \src "libresoc.v:0.0-0.0"
3166           case 1'1
3167             assign { } { }
3168             assign $2\log_dmi_addr$next[31:0]$186 $3\log_dmi_addr$next[31:0]$187
3169             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207"
3170             switch { \$113 \$111 \$109 }
3171               attribute \src "libresoc.v:0.0-0.0"
3172               case 3'--1
3173                 assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr
3174               attribute \src "libresoc.v:0.0-0.0"
3175               case 3'-1-
3176                 assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr
3177               attribute \src "libresoc.v:0.0-0.0"
3178               case 3'1--
3179                 assign { } { }
3180                 assign $3\log_dmi_addr$next[31:0]$187 \dmi_din [31:0]
3181               case
3182                 assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr
3183             end
3184           case
3185             assign $2\log_dmi_addr$next[31:0]$186 \log_dmi_addr
3186         end
3187       attribute \src "libresoc.v:0.0-0.0"
3188       case 2'1-
3189         assign $1\log_dmi_addr$next[31:0]$185 [31:2] \log_dmi_addr [31:2]
3190         assign $1\log_dmi_addr$next[31:0]$185 [1:0] \$115 [1:0]
3191       case
3192         assign $1\log_dmi_addr$next[31:0]$185 \log_dmi_addr
3193     end
3194     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
3195     switch \rst
3196       attribute \src "libresoc.v:0.0-0.0"
3197       case 1'1
3198         assign { } { }
3199         assign $4\log_dmi_addr$next[31:0]$188 0
3200       case
3201         assign $4\log_dmi_addr$next[31:0]$188 $1\log_dmi_addr$next[31:0]$185
3202     end
3203     sync always
3204       update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$184
3205   end
3206   attribute \src "libresoc.v:985.3-993.6"
3207   process $proc$libresoc.v:985$189
3208     assign { } { }
3209     assign { } { }
3210     assign $0\dmi_read_log_data_1$next[0:0]$190 $1\dmi_read_log_data_1$next[0:0]$191
3211     attribute \src "libresoc.v:986.5-986.29"
3212     switch \initial
3213       attribute \src "libresoc.v:986.9-986.17"
3214       case 1'1
3215       case
3216     end
3217     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
3218     switch \rst
3219       attribute \src "libresoc.v:0.0-0.0"
3220       case 1'1
3221         assign { } { }
3222         assign $1\dmi_read_log_data_1$next[0:0]$191 1'0
3223       case
3224         assign $1\dmi_read_log_data_1$next[0:0]$191 \dmi_read_log_data
3225     end
3226     sync always
3227       update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$190
3228   end
3229   attribute \src "libresoc.v:994.3-1002.6"
3230   process $proc$libresoc.v:994$192
3231     assign { } { }
3232     assign { } { }
3233     assign $0\dmi_read_log_data$next[0:0]$193 $1\dmi_read_log_data$next[0:0]$194
3234     attribute \src "libresoc.v:995.5-995.29"
3235     switch \initial
3236       attribute \src "libresoc.v:995.9-995.17"
3237       case 1'1
3238       case
3239     end
3240     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
3241     switch \rst
3242       attribute \src "libresoc.v:0.0-0.0"
3243       case 1'1
3244         assign { } { }
3245         assign $1\dmi_read_log_data$next[0:0]$194 1'0
3246       case
3247         assign $1\dmi_read_log_data$next[0:0]$194 \$120
3248     end
3249     sync always
3250       update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$193
3251   end
3252   connect \$9 $and$libresoc.v:708$80_Y
3253   connect \$99 $eq$libresoc.v:709$81_Y
3254   connect \$101 $not$libresoc.v:710$82_Y
3255   connect \$103 $and$libresoc.v:711$83_Y
3256   connect \$105 $not$libresoc.v:712$84_Y
3257   connect \$107 $and$libresoc.v:713$85_Y
3258   connect \$109 $eq$libresoc.v:714$86_Y
3259   connect \$111 $eq$libresoc.v:715$87_Y
3260   connect \$113 $eq$libresoc.v:716$88_Y
3261   connect \$116 $add$libresoc.v:717$89_Y
3262   connect \$118 $eq$libresoc.v:718$90_Y
3263   connect \$11 $eq$libresoc.v:719$91_Y
3264   connect \$120 $and$libresoc.v:720$92_Y
3265   connect \$122 $not$libresoc.v:721$93_Y
3266   connect \$124 $and$libresoc.v:722$94_Y
3267   connect \$13 $eq$libresoc.v:723$95_Y
3268   connect \$15 $eq$libresoc.v:724$96_Y
3269   connect \$17 $not$libresoc.v:725$97_Y
3270   connect \$1 $pos$libresoc.v:726$98_Y
3271   connect \$19 $and$libresoc.v:727$99_Y
3272   connect \$21 $not$libresoc.v:728$100_Y
3273   connect \$23 $and$libresoc.v:729$101_Y
3274   connect \$25 $eq$libresoc.v:730$102_Y
3275   connect \$27 $eq$libresoc.v:731$103_Y
3276   connect \$29 $eq$libresoc.v:732$104_Y
3277   connect \$31 $not$libresoc.v:733$105_Y
3278   connect \$33 $and$libresoc.v:734$106_Y
3279   connect \$35 $not$libresoc.v:735$107_Y
3280   connect \$37 $and$libresoc.v:736$108_Y
3281   connect \$3 $not$libresoc.v:737$109_Y
3282   connect \$39 $eq$libresoc.v:738$110_Y
3283   connect \$41 $eq$libresoc.v:739$111_Y
3284   connect \$43 $eq$libresoc.v:740$112_Y
3285   connect \$45 $not$libresoc.v:741$113_Y
3286   connect \$47 $and$libresoc.v:742$114_Y
3287   connect \$49 $not$libresoc.v:743$115_Y
3288   connect \$51 $and$libresoc.v:744$116_Y
3289   connect \$53 $eq$libresoc.v:745$117_Y
3290   connect \$55 $eq$libresoc.v:746$118_Y
3291   connect \$57 $eq$libresoc.v:747$119_Y
3292   connect \$5 $and$libresoc.v:748$120_Y
3293   connect \$59 $not$libresoc.v:749$121_Y
3294   connect \$61 $and$libresoc.v:750$122_Y
3295   connect \$63 $not$libresoc.v:751$123_Y
3296   connect \$65 $and$libresoc.v:752$124_Y
3297   connect \$67 $eq$libresoc.v:753$125_Y
3298   connect \$69 $eq$libresoc.v:754$126_Y
3299   connect \$71 $eq$libresoc.v:755$127_Y
3300   connect \$73 $not$libresoc.v:756$128_Y
3301   connect \$75 $and$libresoc.v:757$129_Y
3302   connect \$77 $not$libresoc.v:758$130_Y
3303   connect \$7 $not$libresoc.v:759$131_Y
3304   connect \$79 $and$libresoc.v:760$132_Y
3305   connect \$81 $eq$libresoc.v:761$133_Y
3306   connect \$83 $eq$libresoc.v:762$134_Y
3307   connect \$85 $eq$libresoc.v:763$135_Y
3308   connect \$87 $not$libresoc.v:764$136_Y
3309   connect \$89 $and$libresoc.v:765$137_Y
3310   connect \$91 $not$libresoc.v:766$138_Y
3311   connect \$93 $and$libresoc.v:767$139_Y
3312   connect \$95 $eq$libresoc.v:768$140_Y
3313   connect \$97 $eq$libresoc.v:769$141_Y
3314   connect \$115 \$116
3315   connect \log_write_addr_o 0
3316   connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000
3317   connect \terminated_o \terminated
3318   connect \icache_rst_o \do_icreset
3319   connect \core_rst_o \do_reset
3320   connect \core_stop_o \$124
3321   connect \d_gpr_addr \gspr_index
3322   connect \stat_reg \$1
3323 end
3324 attribute \src "libresoc.v:1191.1-7124.10"
3325 attribute \cells_not_processed 1
3326 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec"
3327 attribute \generator "nMigen"
3328 module \dec
3329   attribute \src "libresoc.v:3385.3-3523.6"
3330   wire width 8 $0\asmcode[7:0]
3331   attribute \src "libresoc.v:5370.3-5511.6"
3332   wire $0\br[0:0]
3333   attribute \src "libresoc.v:4092.3-4233.6"
3334   wire width 3 $0\cr_in[2:0]
3335   attribute \src "libresoc.v:4234.3-4375.6"
3336   wire width 3 $0\cr_out[2:0]
3337   attribute \src "libresoc.v:4802.3-4943.6"
3338   wire width 2 $0\cry_in[1:0]
3339   attribute \src "libresoc.v:5228.3-5369.6"
3340   wire $0\cry_out[0:0]
3341   attribute \src "libresoc.v:6648.3-6789.6"
3342   wire width 5 $0\form[4:0]
3343   attribute \src "libresoc.v:6364.3-6505.6"
3344   wire width 12 $0\function_unit[11:0]
3345   attribute \src "libresoc.v:3524.3-3665.6"
3346   wire width 3 $0\in1_sel[2:0]
3347   attribute \src "libresoc.v:3666.3-3807.6"
3348   wire width 4 $0\in2_sel[3:0]
3349   attribute \src "libresoc.v:3808.3-3949.6"
3350   wire width 2 $0\in3_sel[1:0]
3351   attribute \src "libresoc.v:1192.7-1192.20"
3352   wire $0\initial[0:0]
3353   attribute \src "libresoc.v:6506.3-6647.6"
3354   wire width 7 $0\internal_op[6:0]
3355   attribute \src "libresoc.v:4944.3-5085.6"
3356   wire $0\inv_a[0:0]
3357   attribute \src "libresoc.v:5086.3-5227.6"
3358   wire $0\inv_out[0:0]
3359   attribute \src "libresoc.v:5796.3-5937.6"
3360   wire $0\is_32b[0:0]
3361   attribute \src "libresoc.v:4376.3-4517.6"
3362   wire width 4 $0\ldst_len[3:0]
3363   attribute \src "libresoc.v:6080.3-6221.6"
3364   wire $0\lk[0:0]
3365   attribute \src "libresoc.v:3950.3-4091.6"
3366   wire width 2 $0\out_sel[1:0]
3367   attribute \src "libresoc.v:4660.3-4801.6"
3368   wire width 2 $0\rc_sel[1:0]
3369   attribute \src "libresoc.v:5654.3-5795.6"
3370   wire $0\rsrv[0:0]
3371   attribute \src "libresoc.v:6222.3-6363.6"
3372   wire $0\sgl_pipe[0:0]
3373   attribute \src "libresoc.v:5938.3-6079.6"
3374   wire $0\sgn[0:0]
3375   attribute \src "libresoc.v:5512.3-5653.6"
3376   wire $0\sgn_ext[0:0]
3377   attribute \src "libresoc.v:4518.3-4659.6"
3378   wire width 2 $0\upd[1:0]
3379   attribute \src "libresoc.v:3385.3-3523.6"
3380   wire width 8 $1\asmcode[7:0]
3381   attribute \src "libresoc.v:5370.3-5511.6"
3382   wire $1\br[0:0]
3383   attribute \src "libresoc.v:4092.3-4233.6"
3384   wire width 3 $1\cr_in[2:0]
3385   attribute \src "libresoc.v:4234.3-4375.6"
3386   wire width 3 $1\cr_out[2:0]
3387   attribute \src "libresoc.v:4802.3-4943.6"
3388   wire width 2 $1\cry_in[1:0]
3389   attribute \src "libresoc.v:5228.3-5369.6"
3390   wire $1\cry_out[0:0]
3391   attribute \src "libresoc.v:6648.3-6789.6"
3392   wire width 5 $1\form[4:0]
3393   attribute \src "libresoc.v:6364.3-6505.6"
3394   wire width 12 $1\function_unit[11:0]
3395   attribute \src "libresoc.v:3524.3-3665.6"
3396   wire width 3 $1\in1_sel[2:0]
3397   attribute \src "libresoc.v:3666.3-3807.6"
3398   wire width 4 $1\in2_sel[3:0]
3399   attribute \src "libresoc.v:3808.3-3949.6"
3400   wire width 2 $1\in3_sel[1:0]
3401   attribute \src "libresoc.v:6506.3-6647.6"
3402   wire width 7 $1\internal_op[6:0]
3403   attribute \src "libresoc.v:4944.3-5085.6"
3404   wire $1\inv_a[0:0]
3405   attribute \src "libresoc.v:5086.3-5227.6"
3406   wire $1\inv_out[0:0]
3407   attribute \src "libresoc.v:5796.3-5937.6"
3408   wire $1\is_32b[0:0]
3409   attribute \src "libresoc.v:4376.3-4517.6"
3410   wire width 4 $1\ldst_len[3:0]
3411   attribute \src "libresoc.v:6080.3-6221.6"
3412   wire $1\lk[0:0]
3413   attribute \src "libresoc.v:3950.3-4091.6"
3414   wire width 2 $1\out_sel[1:0]
3415   attribute \src "libresoc.v:4660.3-4801.6"
3416   wire width 2 $1\rc_sel[1:0]
3417   attribute \src "libresoc.v:5654.3-5795.6"
3418   wire $1\rsrv[0:0]
3419   attribute \src "libresoc.v:6222.3-6363.6"
3420   wire $1\sgl_pipe[0:0]
3421   attribute \src "libresoc.v:5938.3-6079.6"
3422   wire $1\sgn[0:0]
3423   attribute \src "libresoc.v:5512.3-5653.6"
3424   wire $1\sgn_ext[0:0]
3425   attribute \src "libresoc.v:4518.3-4659.6"
3426   wire width 2 $1\upd[1:0]
3427   attribute \src "libresoc.v:3385.3-3523.6"
3428   wire width 8 $2\asmcode[7:0]
3429   attribute \src "libresoc.v:5370.3-5511.6"
3430   wire $2\br[0:0]
3431   attribute \src "libresoc.v:4092.3-4233.6"
3432   wire width 3 $2\cr_in[2:0]
3433   attribute \src "libresoc.v:4234.3-4375.6"
3434   wire width 3 $2\cr_out[2:0]
3435   attribute \src "libresoc.v:4802.3-4943.6"
3436   wire width 2 $2\cry_in[1:0]
3437   attribute \src "libresoc.v:5228.3-5369.6"
3438   wire $2\cry_out[0:0]
3439   attribute \src "libresoc.v:6648.3-6789.6"
3440   wire width 5 $2\form[4:0]
3441   attribute \src "libresoc.v:6364.3-6505.6"
3442   wire width 12 $2\function_unit[11:0]
3443   attribute \src "libresoc.v:3524.3-3665.6"
3444   wire width 3 $2\in1_sel[2:0]
3445   attribute \src "libresoc.v:3666.3-3807.6"
3446   wire width 4 $2\in2_sel[3:0]
3447   attribute \src "libresoc.v:3808.3-3949.6"
3448   wire width 2 $2\in3_sel[1:0]
3449   attribute \src "libresoc.v:6506.3-6647.6"
3450   wire width 7 $2\internal_op[6:0]
3451   attribute \src "libresoc.v:4944.3-5085.6"
3452   wire $2\inv_a[0:0]
3453   attribute \src "libresoc.v:5086.3-5227.6"
3454   wire $2\inv_out[0:0]
3455   attribute \src "libresoc.v:5796.3-5937.6"
3456   wire $2\is_32b[0:0]
3457   attribute \src "libresoc.v:4376.3-4517.6"
3458   wire width 4 $2\ldst_len[3:0]
3459   attribute \src "libresoc.v:6080.3-6221.6"
3460   wire $2\lk[0:0]
3461   attribute \src "libresoc.v:3950.3-4091.6"
3462   wire width 2 $2\out_sel[1:0]
3463   attribute \src "libresoc.v:4660.3-4801.6"
3464   wire width 2 $2\rc_sel[1:0]
3465   attribute \src "libresoc.v:5654.3-5795.6"
3466   wire $2\rsrv[0:0]
3467   attribute \src "libresoc.v:6222.3-6363.6"
3468   wire $2\sgl_pipe[0:0]
3469   attribute \src "libresoc.v:5938.3-6079.6"
3470   wire $2\sgn[0:0]
3471   attribute \src "libresoc.v:5512.3-5653.6"
3472   wire $2\sgn_ext[0:0]
3473   attribute \src "libresoc.v:4518.3-4659.6"
3474   wire width 2 $2\upd[1:0]
3475   attribute \src "libresoc.v:3249.17-3249.211"
3476   wire width 32 $ternary$libresoc.v:3249$237_Y
3477   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485"
3478   wire width 32 \$2
3479   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3480   wire \AA
3481   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3482   wire width 5 \A_BC
3483   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3484   wire width 5 \A_FRA
3485   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3486   wire width 5 \A_FRB
3487   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3488   wire width 5 \A_FRC
3489   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3490   wire width 5 \A_FRT
3491   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3492   wire width 5 \A_RA
3493   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3494   wire width 5 \A_RB
3495   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3496   wire width 5 \A_RT
3497   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3498   wire \A_Rc
3499   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3500   wire width 5 \A_XO
3501   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3502   wire width 5 output 25 \BA
3503   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3504   wire width 5 output 24 \BB
3505   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3506   wire width 5 output 30 \BC
3507   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3508   wire width 14 \BD
3509   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3510   wire width 3 \BF
3511   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3512   wire width 2 \BH
3513   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3514   wire width 5 output 29 \BI
3515   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3516   wire width 5 output 28 \BO
3517   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3518   wire width 5 output 26 \BT
3519   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3520   wire \B_AA
3521   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3522   wire width 14 \B_BD
3523   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3524   wire width 5 \B_BI
3525   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3526   wire width 5 \B_BO
3527   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3528   wire \B_LK
3529   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3530   wire width 10 \CR
3531   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3532   wire width 16 \D
3533   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3534   wire width 5 \DQE_RA
3535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3536   wire width 5 \DQE_RT
3537   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3538   wire width 2 \DQE_XO
3539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3540   wire width 12 \DQ_DQ
3541   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3542   wire width 4 \DQ_PT
3543   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3544   wire width 5 \DQ_RA
3545   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3546   wire width 5 \DQ_RTp
3547   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3548   wire width 5 \DQ_S
3549   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3550   wire \DQ_SX
3551   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3552   wire width 6 \DQ_SX_S
3553   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3554   wire width 5 \DQ_T
3555   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3556   wire \DQ_TX
3557   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3558   wire width 6 \DQ_TX_T
3559   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3560   wire width 3 \DQ_XO
3561   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3562   wire width 14 \DS
3563   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3564   wire width 14 \DS_DS
3565   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3566   wire width 5 \DS_FRSp
3567   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3568   wire width 5 \DS_FRTp
3569   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3570   wire width 5 \DS_RA
3571   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3572   wire width 5 \DS_RS
3573   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3574   wire width 5 \DS_RSp
3575   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3576   wire width 5 \DS_RT
3577   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3578   wire width 5 \DS_VRS
3579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3580   wire width 5 \DS_VRT
3581   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3582   wire width 2 \DS_XO
3583   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3584   wire width 5 \DX_RT
3585   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3586   wire width 5 \DX_XO
3587   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3588   wire width 10 \DX_d0
3589   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3590   wire width 16 \DX_d0_d1_d2
3591   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3592   wire width 5 \DX_d1
3593   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3594   wire \DX_d2
3595   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3596   wire width 3 \D_BF
3597   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3598   wire width 16 \D_D
3599   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3600   wire width 5 \D_FRS
3601   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3602   wire width 5 \D_FRT
3603   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3604   wire \D_L
3605   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3606   wire width 5 \D_RA
3607   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3608   wire width 5 \D_RS
3609   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3610   wire width 5 \D_RT
3611   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3612   wire width 16 \D_SI
3613   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3614   wire width 5 \D_TO
3615   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3616   wire width 16 \D_UI
3617   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3618   wire width 3 \EVS_BFA
3619   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3620   wire width 8 output 27 \FXM
3621   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3622   wire \I_AA
3623   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3624   wire width 24 \I_LI
3625   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3626   wire \I_LK
3627   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3628   wire \L
3629   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3630   wire width 24 \LI
3631   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3632   wire output 11 \LK
3633   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3634   wire width 5 \MB
3635   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3636   wire width 5 \MB32
3637   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3638   wire width 5 \MDS_IB
3639   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3640   wire width 5 \MDS_IS
3641   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3642   wire width 5 \MDS_RA
3643   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3644   wire width 5 \MDS_RB
3645   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3646   wire width 5 \MDS_RS
3647   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3648   wire \MDS_Rc
3649   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3650   wire width 4 \MDS_XBI
3651   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3652   wire width 4 \MDS_XBI_1
3653   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3654   wire width 4 \MDS_XO
3655   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3656   wire width 6 \MDS_mb
3657   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3658   wire width 6 \MDS_me
3659   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3660   wire width 5 \MD_RA
3661   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3662   wire width 5 \MD_RS
3663   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3664   wire \MD_Rc
3665   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3666   wire width 3 \MD_XO
3667   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3668   wire width 6 \MD_mb
3669   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3670   wire width 6 \MD_me
3671   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3672   wire width 6 \MD_sh
3673   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3674   wire width 5 \ME
3675   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3676   wire width 5 \ME32
3677   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3678   wire width 5 \M_MB
3679   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3680   wire width 5 \M_ME
3681   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3682   wire width 5 \M_RA
3683   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3684   wire width 5 \M_RB
3685   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3686   wire width 5 \M_RS
3687   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3688   wire \M_Rc
3689   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3690   wire width 5 \M_SH
3691   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3692   wire output 23 \OE
3693   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3694   wire width 5 output 20 \RA
3695   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3696   wire width 5 output 21 \RB
3697   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3698   wire width 5 output 18 \RS
3699   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3700   wire width 5 output 19 \RT
3701   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3702   wire output 22 \Rc
3703   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3704   wire width 7 \SC_LEV
3705   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3706   wire \SC_XO
3707   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3708   wire width 2 \SC_XO_1
3709   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3710   wire width 5 \SH
3711   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3712   wire width 5 \SH32
3713   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3714   wire width 16 \SI
3715   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3716   wire width 10 output 31 \SPR
3717   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3718   wire width 5 \TO
3719   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3720   wire width 5 \TX_RA
3721   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3722   wire width 5 \TX_UI
3723   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3724   wire width 4 \TX_XBI
3725   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3726   wire width 6 \TX_XO
3727   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
3728   wire width 16 \UI
3729   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3730   wire width 5 \VA_RA
3731   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3732   wire width 5 \VA_RB
3733   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3734   wire width 5 \VA_RC
3735   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3736   wire width 5 \VA_RT
3737   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3738   wire width 4 \VA_SHB
3739   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3740   wire width 5 \VA_VRA
3741   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3742   wire width 5 \VA_VRB
3743   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3744   wire width 5 \VA_VRC
3745   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3746   wire width 5 \VA_VRT
3747   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3748   wire width 6 \VA_XO
3749   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3750   wire \VC_Rc
3751   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3752   wire width 5 \VC_VRA
3753   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3754   wire width 5 \VC_VRB
3755   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3756   wire width 5 \VC_VRT
3757   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3758   wire width 10 \VC_XO
3759   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3760   wire width 5 \VX_EO
3761   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3762   wire \VX_PS
3763   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3764   wire width 5 \VX_RA
3765   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3766   wire width 5 \VX_RT
3767   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3768   wire width 5 \VX_SIM
3769   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3770   wire width 5 \VX_UIM
3771   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3772   wire width 4 \VX_UIM_1
3773   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3774   wire width 3 \VX_UIM_2
3775   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3776   wire width 2 \VX_UIM_3
3777   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3778   wire width 5 \VX_VRA
3779   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3780   wire width 5 \VX_VRB
3781   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3782   wire width 5 \VX_VRT
3783   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3784   wire width 10 \VX_XO
3785   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3786   wire width 11 \VX_XO_1
3787   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3788   wire width 8 \XFL_FLM
3789   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3790   wire width 5 \XFL_FRB
3791   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3792   wire \XFL_L
3793   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3794   wire \XFL_Rc
3795   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3796   wire \XFL_W
3797   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3798   wire width 10 \XFL_XO
3799   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3800   wire width 10 \XFX_BHRBE
3801   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3802   wire width 5 \XFX_DUI
3803   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3804   wire width 10 \XFX_DUIS
3805   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3806   wire width 8 \XFX_FXM
3807   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3808   wire width 5 \XFX_RS
3809   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3810   wire width 5 \XFX_RT
3811   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3812   wire width 10 \XFX_SPR
3813   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3814   wire width 10 \XFX_XO
3815   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3816   wire width 5 \XL_BA
3817   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3818   wire width 5 \XL_BB
3819   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3820   wire width 3 \XL_BF
3821   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3822   wire width 3 \XL_BFA
3823   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3824   wire width 2 \XL_BH
3825   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3826   wire width 5 \XL_BI
3827   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3828   wire width 5 \XL_BO
3829   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3830   wire width 5 \XL_BO_1
3831   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3832   wire width 5 output 34 \XL_BT
3833   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3834   wire \XL_LK
3835   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3836   wire width 15 \XL_OC
3837   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3838   wire \XL_S
3839   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3840   wire width 10 output 35 \XL_XO
3841   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3842   wire \XO_OE
3843   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3844   wire width 5 \XO_RA
3845   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3846   wire width 5 \XO_RB
3847   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3848   wire width 5 \XO_RT
3849   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3850   wire \XO_Rc
3851   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3852   wire width 9 \XO_XO
3853   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3854   wire width 5 \XS_RA
3855   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3856   wire width 5 \XS_RS
3857   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3858   wire \XS_Rc
3859   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3860   wire width 9 \XS_XO
3861   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3862   wire width 6 \XS_sh
3863   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3864   wire width 5 \XX2_B
3865   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3866   wire width 3 \XX2_BF
3867   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3868   wire \XX2_BX
3869   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3870   wire width 6 \XX2_BX_B
3871   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3872   wire width 7 \XX2_DCMX
3873   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3874   wire width 5 \XX2_EO
3875   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3876   wire width 5 \XX2_RT
3877   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3878   wire width 5 \XX2_T
3879   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3880   wire \XX2_TX
3881   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3882   wire width 6 \XX2_TX_T
3883   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3884   wire width 4 \XX2_UIM
3885   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3886   wire width 2 \XX2_UIM_1
3887   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3888   wire width 7 \XX2_XO
3889   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3890   wire width 9 \XX2_XO_1
3891   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3892   wire \XX2_dc
3893   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3894   wire width 7 \XX2_dc_dm_dx
3895   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3896   wire \XX2_dm
3897   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3898   wire width 5 \XX2_dx
3899   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3900   wire width 5 \XX3_A
3901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3902   wire \XX3_AX
3903   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3904   wire width 6 \XX3_AX_A
3905   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3906   wire width 5 \XX3_B
3907   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3908   wire width 3 \XX3_BF
3909   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3910   wire \XX3_BX
3911   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3912   wire width 6 \XX3_BX_B
3913   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3914   wire width 2 \XX3_DM
3915   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3916   wire \XX3_Rc
3917   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3918   wire width 2 \XX3_SHW
3919   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3920   wire width 5 \XX3_T
3921   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3922   wire \XX3_TX
3923   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3924   wire width 6 \XX3_TX_T
3925   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3926   wire width 4 \XX3_XO
3927   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3928   wire width 8 \XX3_XO_1
3929   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3930   wire width 9 \XX3_XO_2
3931   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3932   wire width 5 \XX4_A
3933   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3934   wire \XX4_AX
3935   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3936   wire width 6 \XX4_AX_A
3937   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3938   wire width 5 \XX4_B
3939   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3940   wire \XX4_BX
3941   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3942   wire width 6 \XX4_BX_B
3943   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3944   wire width 5 \XX4_C
3945   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3946   wire \XX4_CX
3947   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3948   wire width 6 \XX4_CX_C
3949   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3950   wire width 5 \XX4_T
3951   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3952   wire \XX4_TX
3953   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3954   wire width 6 \XX4_TX_T
3955   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3956   wire width 2 \XX4_XO
3957   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3958   wire \X_A
3959   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3960   wire width 3 output 32 \X_BF
3961   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3962   wire width 3 output 33 \X_BFA
3963   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3964   wire width 5 \X_BO
3965   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3966   wire width 4 \X_CT
3967   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3968   wire width 7 \X_DCMX
3969   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3970   wire width 3 \X_DRM
3971   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3972   wire \X_E
3973   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3974   wire width 2 \X_EO
3975   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3976   wire width 5 \X_EO_1
3977   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3978   wire \X_EX
3979   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3980   wire width 4 \X_E_1
3981   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3982   wire width 5 \X_FC
3983   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3984   wire width 5 \X_FRA
3985   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3986   wire width 5 \X_FRAp
3987   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3988   wire width 5 \X_FRB
3989   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3990   wire width 5 \X_FRBp
3991   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3992   wire width 5 \X_FRS
3993   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3994   wire width 5 \X_FRSp
3995   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3996   wire width 5 \X_FRT
3997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
3998   wire width 5 \X_FRTp
3999   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4000   wire width 3 \X_IH
4001   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4002   wire width 8 \X_IMM8
4003   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4004   wire \X_L
4005   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4006   wire \X_L1
4007   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4008   wire width 2 \X_L2
4009   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4010   wire width 2 \X_L3
4011   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4012   wire width 5 \X_MO
4013   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4014   wire width 5 \X_NB
4015   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4016   wire \X_PRS
4017   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4018   wire \X_R
4019   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4020   wire width 5 \X_RA
4021   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4022   wire width 5 \X_RB
4023   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4024   wire width 2 \X_RIC
4025   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4026   wire width 2 \X_RM
4027   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4028   wire \X_RO
4029   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4030   wire width 5 \X_RS
4031   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4032   wire width 5 \X_RSp
4033   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4034   wire width 5 \X_RT
4035   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4036   wire width 5 \X_RTp
4037   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4038   wire \X_R_1
4039   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4040   wire \X_Rc
4041   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4042   wire width 5 \X_S
4043   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4044   wire width 5 \X_SH
4045   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4046   wire width 5 \X_SI
4047   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4048   wire width 2 \X_SP
4049   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4050   wire width 4 \X_SR
4051   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4052   wire \X_SX
4053   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4054   wire width 6 \X_SX_S
4055   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4056   wire width 5 \X_T
4057   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4058   wire width 10 \X_TBR
4059   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4060   wire width 5 \X_TH
4061   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4062   wire width 5 \X_TO
4063   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4064   wire \X_TX
4065   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4066   wire width 6 \X_TX_T
4067   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4068   wire width 4 \X_U
4069   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4070   wire width 5 \X_UIM
4071   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4072   wire width 5 \X_VRS
4073   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4074   wire width 5 \X_VRT
4075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4076   wire \X_W
4077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4078   wire width 2 \X_WC
4079   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4080   wire width 10 \X_XO
4081   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4082   wire width 8 \X_XO_1
4083   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4084   wire width 3 \Z22_BF
4085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4086   wire width 6 \Z22_DCM
4087   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4088   wire width 6 \Z22_DGM
4089   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4090   wire width 5 \Z22_FRA
4091   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4092   wire width 5 \Z22_FRAp
4093   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4094   wire width 5 \Z22_FRT
4095   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4096   wire width 5 \Z22_FRTp
4097   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4098   wire \Z22_Rc
4099   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4100   wire width 6 \Z22_SH
4101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4102   wire width 9 \Z22_XO
4103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4104   wire width 5 \Z23_FRA
4105   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4106   wire width 5 \Z23_FRAp
4107   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4108   wire width 5 \Z23_FRB
4109   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4110   wire width 5 \Z23_FRBp
4111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4112   wire width 5 \Z23_FRT
4113   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4114   wire width 5 \Z23_FRTp
4115   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4116   wire \Z23_R
4117   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4118   wire width 2 \Z23_RMC
4119   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4120   wire \Z23_Rc
4121   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4122   wire width 5 \Z23_TE
4123   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4124   wire width 8 \Z23_XO
4125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4126   wire width 6 \all_OPCD
4127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
4128   wire width 6 \all_PO
4129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4130   wire width 8 output 16 \asmcode
4131   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446"
4132   wire input 36 \bigendian
4133   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4134   wire \br
4135   attribute \enum_base_type "CRInSel"
4136   attribute \enum_value_000 "NONE"
4137   attribute \enum_value_001 "CR0"
4138   attribute \enum_value_010 "BI"
4139   attribute \enum_value_011 "BFA"
4140   attribute \enum_value_100 "BA_BB"
4141   attribute \enum_value_101 "BC"
4142   attribute \enum_value_110 "WHOLE_REG"
4143   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4144   wire width 3 output 4 \cr_in
4145   attribute \enum_base_type "CROutSel"
4146   attribute \enum_value_000 "NONE"
4147   attribute \enum_value_001 "CR0"
4148   attribute \enum_value_010 "BF"
4149   attribute \enum_value_011 "BT"
4150   attribute \enum_value_100 "WHOLE_REG"
4151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4152   wire width 3 output 5 \cr_out
4153   attribute \enum_base_type "CryIn"
4154   attribute \enum_value_00 "ZERO"
4155   attribute \enum_value_01 "ONE"
4156   attribute \enum_value_10 "CA"
4157   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4158   wire width 2 output 8 \cry_in
4159   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4160   wire \cry_out
4161   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4162   wire width 8 \dec19_dec19_asmcode
4163   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4164   wire \dec19_dec19_br
4165   attribute \enum_base_type "CRInSel"
4166   attribute \enum_value_000 "NONE"
4167   attribute \enum_value_001 "CR0"
4168   attribute \enum_value_010 "BI"
4169   attribute \enum_value_011 "BFA"
4170   attribute \enum_value_100 "BA_BB"
4171   attribute \enum_value_101 "BC"
4172   attribute \enum_value_110 "WHOLE_REG"
4173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4174   wire width 3 \dec19_dec19_cr_in
4175   attribute \enum_base_type "CROutSel"
4176   attribute \enum_value_000 "NONE"
4177   attribute \enum_value_001 "CR0"
4178   attribute \enum_value_010 "BF"
4179   attribute \enum_value_011 "BT"
4180   attribute \enum_value_100 "WHOLE_REG"
4181   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4182   wire width 3 \dec19_dec19_cr_out
4183   attribute \enum_base_type "CryIn"
4184   attribute \enum_value_00 "ZERO"
4185   attribute \enum_value_01 "ONE"
4186   attribute \enum_value_10 "CA"
4187   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4188   wire width 2 \dec19_dec19_cry_in
4189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4190   wire \dec19_dec19_cry_out
4191   attribute \enum_base_type "Form"
4192   attribute \enum_value_00000 "NONE"
4193   attribute \enum_value_00001 "I"
4194   attribute \enum_value_00010 "B"
4195   attribute \enum_value_00011 "SC"
4196   attribute \enum_value_00100 "D"
4197   attribute \enum_value_00101 "DS"
4198   attribute \enum_value_00110 "DQ"
4199   attribute \enum_value_00111 "DX"
4200   attribute \enum_value_01000 "X"
4201   attribute \enum_value_01001 "XL"
4202   attribute \enum_value_01010 "XFX"
4203   attribute \enum_value_01011 "XFL"
4204   attribute \enum_value_01100 "XX1"
4205   attribute \enum_value_01101 "XX2"
4206   attribute \enum_value_01110 "XX3"
4207   attribute \enum_value_01111 "XX4"
4208   attribute \enum_value_10000 "XS"
4209   attribute \enum_value_10001 "XO"
4210   attribute \enum_value_10010 "A"
4211   attribute \enum_value_10011 "M"
4212   attribute \enum_value_10100 "MD"
4213   attribute \enum_value_10101 "MDS"
4214   attribute \enum_value_10110 "VA"
4215   attribute \enum_value_10111 "VC"
4216   attribute \enum_value_11000 "VX"
4217   attribute \enum_value_11001 "EVX"
4218   attribute \enum_value_11010 "EVS"
4219   attribute \enum_value_11011 "Z22"
4220   attribute \enum_value_11100 "Z23"
4221   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4222   wire width 5 \dec19_dec19_form
4223   attribute \enum_base_type "Function"
4224   attribute \enum_value_000000000000 "NONE"
4225   attribute \enum_value_000000000010 "ALU"
4226   attribute \enum_value_000000000100 "LDST"
4227   attribute \enum_value_000000001000 "SHIFT_ROT"
4228   attribute \enum_value_000000010000 "LOGICAL"
4229   attribute \enum_value_000000100000 "BRANCH"
4230   attribute \enum_value_000001000000 "CR"
4231   attribute \enum_value_000010000000 "TRAP"
4232   attribute \enum_value_000100000000 "MUL"
4233   attribute \enum_value_001000000000 "DIV"
4234   attribute \enum_value_010000000000 "SPR"
4235   attribute \enum_value_100000000000 "MMU"
4236   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4237   wire width 12 \dec19_dec19_function_unit
4238   attribute \enum_base_type "In1Sel"
4239   attribute \enum_value_000 "NONE"
4240   attribute \enum_value_001 "RA"
4241   attribute \enum_value_010 "RA_OR_ZERO"
4242   attribute \enum_value_011 "SPR"
4243   attribute \enum_value_100 "RS"
4244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4245   wire width 3 \dec19_dec19_in1_sel
4246   attribute \enum_base_type "In2Sel"
4247   attribute \enum_value_0000 "NONE"
4248   attribute \enum_value_0001 "RB"
4249   attribute \enum_value_0010 "CONST_UI"
4250   attribute \enum_value_0011 "CONST_SI"
4251   attribute \enum_value_0100 "CONST_UI_HI"
4252   attribute \enum_value_0101 "CONST_SI_HI"
4253   attribute \enum_value_0110 "CONST_LI"
4254   attribute \enum_value_0111 "CONST_BD"
4255   attribute \enum_value_1000 "CONST_DS"
4256   attribute \enum_value_1001 "CONST_M1"
4257   attribute \enum_value_1010 "CONST_SH"
4258   attribute \enum_value_1011 "CONST_SH32"
4259   attribute \enum_value_1100 "SPR"
4260   attribute \enum_value_1101 "RS"
4261   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4262   wire width 4 \dec19_dec19_in2_sel
4263   attribute \enum_base_type "In3Sel"
4264   attribute \enum_value_00 "NONE"
4265   attribute \enum_value_01 "RS"
4266   attribute \enum_value_10 "RB"
4267   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4268   wire width 2 \dec19_dec19_in3_sel
4269   attribute \enum_base_type "MicrOp"
4270   attribute \enum_value_0000000 "OP_ILLEGAL"
4271   attribute \enum_value_0000001 "OP_NOP"
4272   attribute \enum_value_0000010 "OP_ADD"
4273   attribute \enum_value_0000011 "OP_ADDPCIS"
4274   attribute \enum_value_0000100 "OP_AND"
4275   attribute \enum_value_0000101 "OP_ATTN"
4276   attribute \enum_value_0000110 "OP_B"
4277   attribute \enum_value_0000111 "OP_BC"
4278   attribute \enum_value_0001000 "OP_BCREG"
4279   attribute \enum_value_0001001 "OP_BPERM"
4280   attribute \enum_value_0001010 "OP_CMP"
4281   attribute \enum_value_0001011 "OP_CMPB"
4282   attribute \enum_value_0001100 "OP_CMPEQB"
4283   attribute \enum_value_0001101 "OP_CMPRB"
4284   attribute \enum_value_0001110 "OP_CNTZ"
4285   attribute \enum_value_0001111 "OP_CRAND"
4286   attribute \enum_value_0010000 "OP_CRANDC"
4287   attribute \enum_value_0010001 "OP_CREQV"
4288   attribute \enum_value_0010010 "OP_CRNAND"
4289   attribute \enum_value_0010011 "OP_CRNOR"
4290   attribute \enum_value_0010100 "OP_CROR"
4291   attribute \enum_value_0010101 "OP_CRORC"
4292   attribute \enum_value_0010110 "OP_CRXOR"
4293   attribute \enum_value_0010111 "OP_DARN"
4294   attribute \enum_value_0011000 "OP_DCBF"
4295   attribute \enum_value_0011001 "OP_DCBST"
4296   attribute \enum_value_0011010 "OP_DCBT"
4297   attribute \enum_value_0011011 "OP_DCBTST"
4298   attribute \enum_value_0011100 "OP_DCBZ"
4299   attribute \enum_value_0011101 "OP_DIV"
4300   attribute \enum_value_0011110 "OP_DIVE"
4301   attribute \enum_value_0011111 "OP_EXTS"
4302   attribute \enum_value_0100000 "OP_EXTSWSLI"
4303   attribute \enum_value_0100001 "OP_ICBI"
4304   attribute \enum_value_0100010 "OP_ICBT"
4305   attribute \enum_value_0100011 "OP_ISEL"
4306   attribute \enum_value_0100100 "OP_ISYNC"
4307   attribute \enum_value_0100101 "OP_LOAD"
4308   attribute \enum_value_0100110 "OP_STORE"
4309   attribute \enum_value_0100111 "OP_MADDHD"
4310   attribute \enum_value_0101000 "OP_MADDHDU"
4311   attribute \enum_value_0101001 "OP_MADDLD"
4312   attribute \enum_value_0101010 "OP_MCRF"
4313   attribute \enum_value_0101011 "OP_MCRXR"
4314   attribute \enum_value_0101100 "OP_MCRXRX"
4315   attribute \enum_value_0101101 "OP_MFCR"
4316   attribute \enum_value_0101110 "OP_MFSPR"
4317   attribute \enum_value_0101111 "OP_MOD"
4318   attribute \enum_value_0110000 "OP_MTCRF"
4319   attribute \enum_value_0110001 "OP_MTSPR"
4320   attribute \enum_value_0110010 "OP_MUL_L64"
4321   attribute \enum_value_0110011 "OP_MUL_H64"
4322   attribute \enum_value_0110100 "OP_MUL_H32"
4323   attribute \enum_value_0110101 "OP_OR"
4324   attribute \enum_value_0110110 "OP_POPCNT"
4325   attribute \enum_value_0110111 "OP_PRTY"
4326   attribute \enum_value_0111000 "OP_RLC"
4327   attribute \enum_value_0111001 "OP_RLCL"
4328   attribute \enum_value_0111010 "OP_RLCR"
4329   attribute \enum_value_0111011 "OP_SETB"
4330   attribute \enum_value_0111100 "OP_SHL"
4331   attribute \enum_value_0111101 "OP_SHR"
4332   attribute \enum_value_0111110 "OP_SYNC"
4333   attribute \enum_value_0111111 "OP_TRAP"
4334   attribute \enum_value_1000011 "OP_XOR"
4335   attribute \enum_value_1000100 "OP_SIM_CONFIG"
4336   attribute \enum_value_1000101 "OP_CROP"
4337   attribute \enum_value_1000110 "OP_RFID"
4338   attribute \enum_value_1000111 "OP_MFMSR"
4339   attribute \enum_value_1001000 "OP_MTMSRD"
4340   attribute \enum_value_1001001 "OP_SC"
4341   attribute \enum_value_1001010 "OP_MTMSR"
4342   attribute \enum_value_1001011 "OP_TLBIE"
4343   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4344   wire width 7 \dec19_dec19_internal_op
4345   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4346   wire \dec19_dec19_inv_a
4347   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4348   wire \dec19_dec19_inv_out
4349   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4350   wire \dec19_dec19_is_32b
4351   attribute \enum_base_type "LdstLen"
4352   attribute \enum_value_0000 "NONE"
4353   attribute \enum_value_0001 "is1B"
4354   attribute \enum_value_0010 "is2B"
4355   attribute \enum_value_0100 "is4B"
4356   attribute \enum_value_1000 "is8B"
4357   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4358   wire width 4 \dec19_dec19_ldst_len
4359   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4360   wire \dec19_dec19_lk
4361   attribute \enum_base_type "OutSel"
4362   attribute \enum_value_00 "NONE"
4363   attribute \enum_value_01 "RT"
4364   attribute \enum_value_10 "RA"
4365   attribute \enum_value_11 "SPR"
4366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4367   wire width 2 \dec19_dec19_out_sel
4368   attribute \enum_base_type "RC"
4369   attribute \enum_value_00 "NONE"
4370   attribute \enum_value_01 "ONE"
4371   attribute \enum_value_10 "RC"
4372   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4373   wire width 2 \dec19_dec19_rc_sel
4374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4375   wire \dec19_dec19_rsrv
4376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4377   wire \dec19_dec19_sgl_pipe
4378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4379   wire \dec19_dec19_sgn
4380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4381   wire \dec19_dec19_sgn_ext
4382   attribute \enum_base_type "LDSTMode"
4383   attribute \enum_value_00 "NONE"
4384   attribute \enum_value_01 "update"
4385   attribute \enum_value_10 "cix"
4386   attribute \enum_value_11 "cx"
4387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4388   wire width 2 \dec19_dec19_upd
4389   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
4390   wire width 32 \dec19_opcode_in
4391   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4392   wire width 8 \dec30_dec30_asmcode
4393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4394   wire \dec30_dec30_br
4395   attribute \enum_base_type "CRInSel"
4396   attribute \enum_value_000 "NONE"
4397   attribute \enum_value_001 "CR0"
4398   attribute \enum_value_010 "BI"
4399   attribute \enum_value_011 "BFA"
4400   attribute \enum_value_100 "BA_BB"
4401   attribute \enum_value_101 "BC"
4402   attribute \enum_value_110 "WHOLE_REG"
4403   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4404   wire width 3 \dec30_dec30_cr_in
4405   attribute \enum_base_type "CROutSel"
4406   attribute \enum_value_000 "NONE"
4407   attribute \enum_value_001 "CR0"
4408   attribute \enum_value_010 "BF"
4409   attribute \enum_value_011 "BT"
4410   attribute \enum_value_100 "WHOLE_REG"
4411   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4412   wire width 3 \dec30_dec30_cr_out
4413   attribute \enum_base_type "CryIn"
4414   attribute \enum_value_00 "ZERO"
4415   attribute \enum_value_01 "ONE"
4416   attribute \enum_value_10 "CA"
4417   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4418   wire width 2 \dec30_dec30_cry_in
4419   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4420   wire \dec30_dec30_cry_out
4421   attribute \enum_base_type "Form"
4422   attribute \enum_value_00000 "NONE"
4423   attribute \enum_value_00001 "I"
4424   attribute \enum_value_00010 "B"
4425   attribute \enum_value_00011 "SC"
4426   attribute \enum_value_00100 "D"
4427   attribute \enum_value_00101 "DS"
4428   attribute \enum_value_00110 "DQ"
4429   attribute \enum_value_00111 "DX"
4430   attribute \enum_value_01000 "X"
4431   attribute \enum_value_01001 "XL"
4432   attribute \enum_value_01010 "XFX"
4433   attribute \enum_value_01011 "XFL"
4434   attribute \enum_value_01100 "XX1"
4435   attribute \enum_value_01101 "XX2"
4436   attribute \enum_value_01110 "XX3"
4437   attribute \enum_value_01111 "XX4"
4438   attribute \enum_value_10000 "XS"
4439   attribute \enum_value_10001 "XO"
4440   attribute \enum_value_10010 "A"
4441   attribute \enum_value_10011 "M"
4442   attribute \enum_value_10100 "MD"
4443   attribute \enum_value_10101 "MDS"
4444   attribute \enum_value_10110 "VA"
4445   attribute \enum_value_10111 "VC"
4446   attribute \enum_value_11000 "VX"
4447   attribute \enum_value_11001 "EVX"
4448   attribute \enum_value_11010 "EVS"
4449   attribute \enum_value_11011 "Z22"
4450   attribute \enum_value_11100 "Z23"
4451   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4452   wire width 5 \dec30_dec30_form
4453   attribute \enum_base_type "Function"
4454   attribute \enum_value_000000000000 "NONE"
4455   attribute \enum_value_000000000010 "ALU"
4456   attribute \enum_value_000000000100 "LDST"
4457   attribute \enum_value_000000001000 "SHIFT_ROT"
4458   attribute \enum_value_000000010000 "LOGICAL"
4459   attribute \enum_value_000000100000 "BRANCH"
4460   attribute \enum_value_000001000000 "CR"
4461   attribute \enum_value_000010000000 "TRAP"
4462   attribute \enum_value_000100000000 "MUL"
4463   attribute \enum_value_001000000000 "DIV"
4464   attribute \enum_value_010000000000 "SPR"
4465   attribute \enum_value_100000000000 "MMU"
4466   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4467   wire width 12 \dec30_dec30_function_unit
4468   attribute \enum_base_type "In1Sel"
4469   attribute \enum_value_000 "NONE"
4470   attribute \enum_value_001 "RA"
4471   attribute \enum_value_010 "RA_OR_ZERO"
4472   attribute \enum_value_011 "SPR"
4473   attribute \enum_value_100 "RS"
4474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4475   wire width 3 \dec30_dec30_in1_sel
4476   attribute \enum_base_type "In2Sel"
4477   attribute \enum_value_0000 "NONE"
4478   attribute \enum_value_0001 "RB"
4479   attribute \enum_value_0010 "CONST_UI"
4480   attribute \enum_value_0011 "CONST_SI"
4481   attribute \enum_value_0100 "CONST_UI_HI"
4482   attribute \enum_value_0101 "CONST_SI_HI"
4483   attribute \enum_value_0110 "CONST_LI"
4484   attribute \enum_value_0111 "CONST_BD"
4485   attribute \enum_value_1000 "CONST_DS"
4486   attribute \enum_value_1001 "CONST_M1"
4487   attribute \enum_value_1010 "CONST_SH"
4488   attribute \enum_value_1011 "CONST_SH32"
4489   attribute \enum_value_1100 "SPR"
4490   attribute \enum_value_1101 "RS"
4491   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4492   wire width 4 \dec30_dec30_in2_sel
4493   attribute \enum_base_type "In3Sel"
4494   attribute \enum_value_00 "NONE"
4495   attribute \enum_value_01 "RS"
4496   attribute \enum_value_10 "RB"
4497   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4498   wire width 2 \dec30_dec30_in3_sel
4499   attribute \enum_base_type "MicrOp"
4500   attribute \enum_value_0000000 "OP_ILLEGAL"
4501   attribute \enum_value_0000001 "OP_NOP"
4502   attribute \enum_value_0000010 "OP_ADD"
4503   attribute \enum_value_0000011 "OP_ADDPCIS"
4504   attribute \enum_value_0000100 "OP_AND"
4505   attribute \enum_value_0000101 "OP_ATTN"
4506   attribute \enum_value_0000110 "OP_B"
4507   attribute \enum_value_0000111 "OP_BC"
4508   attribute \enum_value_0001000 "OP_BCREG"
4509   attribute \enum_value_0001001 "OP_BPERM"
4510   attribute \enum_value_0001010 "OP_CMP"
4511   attribute \enum_value_0001011 "OP_CMPB"
4512   attribute \enum_value_0001100 "OP_CMPEQB"
4513   attribute \enum_value_0001101 "OP_CMPRB"
4514   attribute \enum_value_0001110 "OP_CNTZ"
4515   attribute \enum_value_0001111 "OP_CRAND"
4516   attribute \enum_value_0010000 "OP_CRANDC"
4517   attribute \enum_value_0010001 "OP_CREQV"
4518   attribute \enum_value_0010010 "OP_CRNAND"
4519   attribute \enum_value_0010011 "OP_CRNOR"
4520   attribute \enum_value_0010100 "OP_CROR"
4521   attribute \enum_value_0010101 "OP_CRORC"
4522   attribute \enum_value_0010110 "OP_CRXOR"
4523   attribute \enum_value_0010111 "OP_DARN"
4524   attribute \enum_value_0011000 "OP_DCBF"
4525   attribute \enum_value_0011001 "OP_DCBST"
4526   attribute \enum_value_0011010 "OP_DCBT"
4527   attribute \enum_value_0011011 "OP_DCBTST"
4528   attribute \enum_value_0011100 "OP_DCBZ"
4529   attribute \enum_value_0011101 "OP_DIV"
4530   attribute \enum_value_0011110 "OP_DIVE"
4531   attribute \enum_value_0011111 "OP_EXTS"
4532   attribute \enum_value_0100000 "OP_EXTSWSLI"
4533   attribute \enum_value_0100001 "OP_ICBI"
4534   attribute \enum_value_0100010 "OP_ICBT"
4535   attribute \enum_value_0100011 "OP_ISEL"
4536   attribute \enum_value_0100100 "OP_ISYNC"
4537   attribute \enum_value_0100101 "OP_LOAD"
4538   attribute \enum_value_0100110 "OP_STORE"
4539   attribute \enum_value_0100111 "OP_MADDHD"
4540   attribute \enum_value_0101000 "OP_MADDHDU"
4541   attribute \enum_value_0101001 "OP_MADDLD"
4542   attribute \enum_value_0101010 "OP_MCRF"
4543   attribute \enum_value_0101011 "OP_MCRXR"
4544   attribute \enum_value_0101100 "OP_MCRXRX"
4545   attribute \enum_value_0101101 "OP_MFCR"
4546   attribute \enum_value_0101110 "OP_MFSPR"
4547   attribute \enum_value_0101111 "OP_MOD"
4548   attribute \enum_value_0110000 "OP_MTCRF"
4549   attribute \enum_value_0110001 "OP_MTSPR"
4550   attribute \enum_value_0110010 "OP_MUL_L64"
4551   attribute \enum_value_0110011 "OP_MUL_H64"
4552   attribute \enum_value_0110100 "OP_MUL_H32"
4553   attribute \enum_value_0110101 "OP_OR"
4554   attribute \enum_value_0110110 "OP_POPCNT"
4555   attribute \enum_value_0110111 "OP_PRTY"
4556   attribute \enum_value_0111000 "OP_RLC"
4557   attribute \enum_value_0111001 "OP_RLCL"
4558   attribute \enum_value_0111010 "OP_RLCR"
4559   attribute \enum_value_0111011 "OP_SETB"
4560   attribute \enum_value_0111100 "OP_SHL"
4561   attribute \enum_value_0111101 "OP_SHR"
4562   attribute \enum_value_0111110 "OP_SYNC"
4563   attribute \enum_value_0111111 "OP_TRAP"
4564   attribute \enum_value_1000011 "OP_XOR"
4565   attribute \enum_value_1000100 "OP_SIM_CONFIG"
4566   attribute \enum_value_1000101 "OP_CROP"
4567   attribute \enum_value_1000110 "OP_RFID"
4568   attribute \enum_value_1000111 "OP_MFMSR"
4569   attribute \enum_value_1001000 "OP_MTMSRD"
4570   attribute \enum_value_1001001 "OP_SC"
4571   attribute \enum_value_1001010 "OP_MTMSR"
4572   attribute \enum_value_1001011 "OP_TLBIE"
4573   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4574   wire width 7 \dec30_dec30_internal_op
4575   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4576   wire \dec30_dec30_inv_a
4577   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4578   wire \dec30_dec30_inv_out
4579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4580   wire \dec30_dec30_is_32b
4581   attribute \enum_base_type "LdstLen"
4582   attribute \enum_value_0000 "NONE"
4583   attribute \enum_value_0001 "is1B"
4584   attribute \enum_value_0010 "is2B"
4585   attribute \enum_value_0100 "is4B"
4586   attribute \enum_value_1000 "is8B"
4587   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4588   wire width 4 \dec30_dec30_ldst_len
4589   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4590   wire \dec30_dec30_lk
4591   attribute \enum_base_type "OutSel"
4592   attribute \enum_value_00 "NONE"
4593   attribute \enum_value_01 "RT"
4594   attribute \enum_value_10 "RA"
4595   attribute \enum_value_11 "SPR"
4596   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4597   wire width 2 \dec30_dec30_out_sel
4598   attribute \enum_base_type "RC"
4599   attribute \enum_value_00 "NONE"
4600   attribute \enum_value_01 "ONE"
4601   attribute \enum_value_10 "RC"
4602   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4603   wire width 2 \dec30_dec30_rc_sel
4604   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4605   wire \dec30_dec30_rsrv
4606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4607   wire \dec30_dec30_sgl_pipe
4608   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4609   wire \dec30_dec30_sgn
4610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4611   wire \dec30_dec30_sgn_ext
4612   attribute \enum_base_type "LDSTMode"
4613   attribute \enum_value_00 "NONE"
4614   attribute \enum_value_01 "update"
4615   attribute \enum_value_10 "cix"
4616   attribute \enum_value_11 "cx"
4617   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4618   wire width 2 \dec30_dec30_upd
4619   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
4620   wire width 32 \dec30_opcode_in
4621   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4622   wire width 8 \dec31_dec31_asmcode
4623   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4624   wire \dec31_dec31_br
4625   attribute \enum_base_type "CRInSel"
4626   attribute \enum_value_000 "NONE"
4627   attribute \enum_value_001 "CR0"
4628   attribute \enum_value_010 "BI"
4629   attribute \enum_value_011 "BFA"
4630   attribute \enum_value_100 "BA_BB"
4631   attribute \enum_value_101 "BC"
4632   attribute \enum_value_110 "WHOLE_REG"
4633   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4634   wire width 3 \dec31_dec31_cr_in
4635   attribute \enum_base_type "CROutSel"
4636   attribute \enum_value_000 "NONE"
4637   attribute \enum_value_001 "CR0"
4638   attribute \enum_value_010 "BF"
4639   attribute \enum_value_011 "BT"
4640   attribute \enum_value_100 "WHOLE_REG"
4641   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4642   wire width 3 \dec31_dec31_cr_out
4643   attribute \enum_base_type "CryIn"
4644   attribute \enum_value_00 "ZERO"
4645   attribute \enum_value_01 "ONE"
4646   attribute \enum_value_10 "CA"
4647   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4648   wire width 2 \dec31_dec31_cry_in
4649   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4650   wire \dec31_dec31_cry_out
4651   attribute \enum_base_type "Form"
4652   attribute \enum_value_00000 "NONE"
4653   attribute \enum_value_00001 "I"
4654   attribute \enum_value_00010 "B"
4655   attribute \enum_value_00011 "SC"
4656   attribute \enum_value_00100 "D"
4657   attribute \enum_value_00101 "DS"
4658   attribute \enum_value_00110 "DQ"
4659   attribute \enum_value_00111 "DX"
4660   attribute \enum_value_01000 "X"
4661   attribute \enum_value_01001 "XL"
4662   attribute \enum_value_01010 "XFX"
4663   attribute \enum_value_01011 "XFL"
4664   attribute \enum_value_01100 "XX1"
4665   attribute \enum_value_01101 "XX2"
4666   attribute \enum_value_01110 "XX3"
4667   attribute \enum_value_01111 "XX4"
4668   attribute \enum_value_10000 "XS"
4669   attribute \enum_value_10001 "XO"
4670   attribute \enum_value_10010 "A"
4671   attribute \enum_value_10011 "M"
4672   attribute \enum_value_10100 "MD"
4673   attribute \enum_value_10101 "MDS"
4674   attribute \enum_value_10110 "VA"
4675   attribute \enum_value_10111 "VC"
4676   attribute \enum_value_11000 "VX"
4677   attribute \enum_value_11001 "EVX"
4678   attribute \enum_value_11010 "EVS"
4679   attribute \enum_value_11011 "Z22"
4680   attribute \enum_value_11100 "Z23"
4681   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4682   wire width 5 \dec31_dec31_form
4683   attribute \enum_base_type "Function"
4684   attribute \enum_value_000000000000 "NONE"
4685   attribute \enum_value_000000000010 "ALU"
4686   attribute \enum_value_000000000100 "LDST"
4687   attribute \enum_value_000000001000 "SHIFT_ROT"
4688   attribute \enum_value_000000010000 "LOGICAL"
4689   attribute \enum_value_000000100000 "BRANCH"
4690   attribute \enum_value_000001000000 "CR"
4691   attribute \enum_value_000010000000 "TRAP"
4692   attribute \enum_value_000100000000 "MUL"
4693   attribute \enum_value_001000000000 "DIV"
4694   attribute \enum_value_010000000000 "SPR"
4695   attribute \enum_value_100000000000 "MMU"
4696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4697   wire width 12 \dec31_dec31_function_unit
4698   attribute \enum_base_type "In1Sel"
4699   attribute \enum_value_000 "NONE"
4700   attribute \enum_value_001 "RA"
4701   attribute \enum_value_010 "RA_OR_ZERO"
4702   attribute \enum_value_011 "SPR"
4703   attribute \enum_value_100 "RS"
4704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4705   wire width 3 \dec31_dec31_in1_sel
4706   attribute \enum_base_type "In2Sel"
4707   attribute \enum_value_0000 "NONE"
4708   attribute \enum_value_0001 "RB"
4709   attribute \enum_value_0010 "CONST_UI"
4710   attribute \enum_value_0011 "CONST_SI"
4711   attribute \enum_value_0100 "CONST_UI_HI"
4712   attribute \enum_value_0101 "CONST_SI_HI"
4713   attribute \enum_value_0110 "CONST_LI"
4714   attribute \enum_value_0111 "CONST_BD"
4715   attribute \enum_value_1000 "CONST_DS"
4716   attribute \enum_value_1001 "CONST_M1"
4717   attribute \enum_value_1010 "CONST_SH"
4718   attribute \enum_value_1011 "CONST_SH32"
4719   attribute \enum_value_1100 "SPR"
4720   attribute \enum_value_1101 "RS"
4721   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4722   wire width 4 \dec31_dec31_in2_sel
4723   attribute \enum_base_type "In3Sel"
4724   attribute \enum_value_00 "NONE"
4725   attribute \enum_value_01 "RS"
4726   attribute \enum_value_10 "RB"
4727   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4728   wire width 2 \dec31_dec31_in3_sel
4729   attribute \enum_base_type "MicrOp"
4730   attribute \enum_value_0000000 "OP_ILLEGAL"
4731   attribute \enum_value_0000001 "OP_NOP"
4732   attribute \enum_value_0000010 "OP_ADD"
4733   attribute \enum_value_0000011 "OP_ADDPCIS"
4734   attribute \enum_value_0000100 "OP_AND"
4735   attribute \enum_value_0000101 "OP_ATTN"
4736   attribute \enum_value_0000110 "OP_B"
4737   attribute \enum_value_0000111 "OP_BC"
4738   attribute \enum_value_0001000 "OP_BCREG"
4739   attribute \enum_value_0001001 "OP_BPERM"
4740   attribute \enum_value_0001010 "OP_CMP"
4741   attribute \enum_value_0001011 "OP_CMPB"
4742   attribute \enum_value_0001100 "OP_CMPEQB"
4743   attribute \enum_value_0001101 "OP_CMPRB"
4744   attribute \enum_value_0001110 "OP_CNTZ"
4745   attribute \enum_value_0001111 "OP_CRAND"
4746   attribute \enum_value_0010000 "OP_CRANDC"
4747   attribute \enum_value_0010001 "OP_CREQV"
4748   attribute \enum_value_0010010 "OP_CRNAND"
4749   attribute \enum_value_0010011 "OP_CRNOR"
4750   attribute \enum_value_0010100 "OP_CROR"
4751   attribute \enum_value_0010101 "OP_CRORC"
4752   attribute \enum_value_0010110 "OP_CRXOR"
4753   attribute \enum_value_0010111 "OP_DARN"
4754   attribute \enum_value_0011000 "OP_DCBF"
4755   attribute \enum_value_0011001 "OP_DCBST"
4756   attribute \enum_value_0011010 "OP_DCBT"
4757   attribute \enum_value_0011011 "OP_DCBTST"
4758   attribute \enum_value_0011100 "OP_DCBZ"
4759   attribute \enum_value_0011101 "OP_DIV"
4760   attribute \enum_value_0011110 "OP_DIVE"
4761   attribute \enum_value_0011111 "OP_EXTS"
4762   attribute \enum_value_0100000 "OP_EXTSWSLI"
4763   attribute \enum_value_0100001 "OP_ICBI"
4764   attribute \enum_value_0100010 "OP_ICBT"
4765   attribute \enum_value_0100011 "OP_ISEL"
4766   attribute \enum_value_0100100 "OP_ISYNC"
4767   attribute \enum_value_0100101 "OP_LOAD"
4768   attribute \enum_value_0100110 "OP_STORE"
4769   attribute \enum_value_0100111 "OP_MADDHD"
4770   attribute \enum_value_0101000 "OP_MADDHDU"
4771   attribute \enum_value_0101001 "OP_MADDLD"
4772   attribute \enum_value_0101010 "OP_MCRF"
4773   attribute \enum_value_0101011 "OP_MCRXR"
4774   attribute \enum_value_0101100 "OP_MCRXRX"
4775   attribute \enum_value_0101101 "OP_MFCR"
4776   attribute \enum_value_0101110 "OP_MFSPR"
4777   attribute \enum_value_0101111 "OP_MOD"
4778   attribute \enum_value_0110000 "OP_MTCRF"
4779   attribute \enum_value_0110001 "OP_MTSPR"
4780   attribute \enum_value_0110010 "OP_MUL_L64"
4781   attribute \enum_value_0110011 "OP_MUL_H64"
4782   attribute \enum_value_0110100 "OP_MUL_H32"
4783   attribute \enum_value_0110101 "OP_OR"
4784   attribute \enum_value_0110110 "OP_POPCNT"
4785   attribute \enum_value_0110111 "OP_PRTY"
4786   attribute \enum_value_0111000 "OP_RLC"
4787   attribute \enum_value_0111001 "OP_RLCL"
4788   attribute \enum_value_0111010 "OP_RLCR"
4789   attribute \enum_value_0111011 "OP_SETB"
4790   attribute \enum_value_0111100 "OP_SHL"
4791   attribute \enum_value_0111101 "OP_SHR"
4792   attribute \enum_value_0111110 "OP_SYNC"
4793   attribute \enum_value_0111111 "OP_TRAP"
4794   attribute \enum_value_1000011 "OP_XOR"
4795   attribute \enum_value_1000100 "OP_SIM_CONFIG"
4796   attribute \enum_value_1000101 "OP_CROP"
4797   attribute \enum_value_1000110 "OP_RFID"
4798   attribute \enum_value_1000111 "OP_MFMSR"
4799   attribute \enum_value_1001000 "OP_MTMSRD"
4800   attribute \enum_value_1001001 "OP_SC"
4801   attribute \enum_value_1001010 "OP_MTMSR"
4802   attribute \enum_value_1001011 "OP_TLBIE"
4803   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4804   wire width 7 \dec31_dec31_internal_op
4805   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4806   wire \dec31_dec31_inv_a
4807   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4808   wire \dec31_dec31_inv_out
4809   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4810   wire \dec31_dec31_is_32b
4811   attribute \enum_base_type "LdstLen"
4812   attribute \enum_value_0000 "NONE"
4813   attribute \enum_value_0001 "is1B"
4814   attribute \enum_value_0010 "is2B"
4815   attribute \enum_value_0100 "is4B"
4816   attribute \enum_value_1000 "is8B"
4817   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4818   wire width 4 \dec31_dec31_ldst_len
4819   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4820   wire \dec31_dec31_lk
4821   attribute \enum_base_type "OutSel"
4822   attribute \enum_value_00 "NONE"
4823   attribute \enum_value_01 "RT"
4824   attribute \enum_value_10 "RA"
4825   attribute \enum_value_11 "SPR"
4826   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4827   wire width 2 \dec31_dec31_out_sel
4828   attribute \enum_base_type "RC"
4829   attribute \enum_value_00 "NONE"
4830   attribute \enum_value_01 "ONE"
4831   attribute \enum_value_10 "RC"
4832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4833   wire width 2 \dec31_dec31_rc_sel
4834   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4835   wire \dec31_dec31_rsrv
4836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4837   wire \dec31_dec31_sgl_pipe
4838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4839   wire \dec31_dec31_sgn
4840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4841   wire \dec31_dec31_sgn_ext
4842   attribute \enum_base_type "LDSTMode"
4843   attribute \enum_value_00 "NONE"
4844   attribute \enum_value_01 "update"
4845   attribute \enum_value_10 "cix"
4846   attribute \enum_value_11 "cx"
4847   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4848   wire width 2 \dec31_dec31_upd
4849   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
4850   wire width 32 \dec31_opcode_in
4851   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4852   wire width 8 \dec58_dec58_asmcode
4853   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4854   wire \dec58_dec58_br
4855   attribute \enum_base_type "CRInSel"
4856   attribute \enum_value_000 "NONE"
4857   attribute \enum_value_001 "CR0"
4858   attribute \enum_value_010 "BI"
4859   attribute \enum_value_011 "BFA"
4860   attribute \enum_value_100 "BA_BB"
4861   attribute \enum_value_101 "BC"
4862   attribute \enum_value_110 "WHOLE_REG"
4863   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4864   wire width 3 \dec58_dec58_cr_in
4865   attribute \enum_base_type "CROutSel"
4866   attribute \enum_value_000 "NONE"
4867   attribute \enum_value_001 "CR0"
4868   attribute \enum_value_010 "BF"
4869   attribute \enum_value_011 "BT"
4870   attribute \enum_value_100 "WHOLE_REG"
4871   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4872   wire width 3 \dec58_dec58_cr_out
4873   attribute \enum_base_type "CryIn"
4874   attribute \enum_value_00 "ZERO"
4875   attribute \enum_value_01 "ONE"
4876   attribute \enum_value_10 "CA"
4877   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4878   wire width 2 \dec58_dec58_cry_in
4879   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
4880   wire \dec58_dec58_cry_out
4881   attribute \enum_base_type "Form"
4882   attribute \enum_value_00000 "NONE"
4883   attribute \enum_value_00001 "I"
4884   attribute \enum_value_00010 "B"
4885   attribute \enum_value_00011 "SC"
4886   attribute \enum_value_00100 "D"
4887   attribute \enum_value_00101 "DS"
4888   attribute \enum_value_00110 "DQ"
4889   attribute \enum_value_00111 "DX"
4890   attribute \enum_value_01000 "X"
4891   attribute \enum_value_01001 "XL"
4892   attribute \enum_value_01010 "XFX"
4893   attribute \enum_value_01011 "XFL"
4894   attribute \enum_value_01100 "XX1"
4895   attribute \enum_value_01101 "XX2"
4896   attribute \enum_value_01110 "XX3"
4897   attribute \enum_value_01111 "XX4"
4898   attribute \enum_value_10000 "XS"
4899   attribute \enum_value_10001 "XO"
4900   attribute \enum_value_10010 "A"
4901   attribute \enum_value_10011 "M"
4902   attribute \enum_value_10100 "MD"
4903   attribute \enum_value_10101 "MDS"
4904   attribute \enum_value_10110 "VA"
4905   attribute \enum_value_10111 "VC"
4906   attribute \enum_value_11000 "VX"
4907   attribute \enum_value_11001 "EVX"
4908   attribute \enum_value_11010 "EVS"
4909   attribute \enum_value_11011 "Z22"
4910   attribute \enum_value_11100 "Z23"
4911   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4912   wire width 5 \dec58_dec58_form
4913   attribute \enum_base_type "Function"
4914   attribute \enum_value_000000000000 "NONE"
4915   attribute \enum_value_000000000010 "ALU"
4916   attribute \enum_value_000000000100 "LDST"
4917   attribute \enum_value_000000001000 "SHIFT_ROT"
4918   attribute \enum_value_000000010000 "LOGICAL"
4919   attribute \enum_value_000000100000 "BRANCH"
4920   attribute \enum_value_000001000000 "CR"
4921   attribute \enum_value_000010000000 "TRAP"
4922   attribute \enum_value_000100000000 "MUL"
4923   attribute \enum_value_001000000000 "DIV"
4924   attribute \enum_value_010000000000 "SPR"
4925   attribute \enum_value_100000000000 "MMU"
4926   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4927   wire width 12 \dec58_dec58_function_unit
4928   attribute \enum_base_type "In1Sel"
4929   attribute \enum_value_000 "NONE"
4930   attribute \enum_value_001 "RA"
4931   attribute \enum_value_010 "RA_OR_ZERO"
4932   attribute \enum_value_011 "SPR"
4933   attribute \enum_value_100 "RS"
4934   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4935   wire width 3 \dec58_dec58_in1_sel
4936   attribute \enum_base_type "In2Sel"
4937   attribute \enum_value_0000 "NONE"
4938   attribute \enum_value_0001 "RB"
4939   attribute \enum_value_0010 "CONST_UI"
4940   attribute \enum_value_0011 "CONST_SI"
4941   attribute \enum_value_0100 "CONST_UI_HI"
4942   attribute \enum_value_0101 "CONST_SI_HI"
4943   attribute \enum_value_0110 "CONST_LI"
4944   attribute \enum_value_0111 "CONST_BD"
4945   attribute \enum_value_1000 "CONST_DS"
4946   attribute \enum_value_1001 "CONST_M1"
4947   attribute \enum_value_1010 "CONST_SH"
4948   attribute \enum_value_1011 "CONST_SH32"
4949   attribute \enum_value_1100 "SPR"
4950   attribute \enum_value_1101 "RS"
4951   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4952   wire width 4 \dec58_dec58_in2_sel
4953   attribute \enum_base_type "In3Sel"
4954   attribute \enum_value_00 "NONE"
4955   attribute \enum_value_01 "RS"
4956   attribute \enum_value_10 "RB"
4957   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
4958   wire width 2 \dec58_dec58_in3_sel
4959   attribute \enum_base_type "MicrOp"
4960   attribute \enum_value_0000000 "OP_ILLEGAL"
4961   attribute \enum_value_0000001 "OP_NOP"
4962   attribute \enum_value_0000010 "OP_ADD"
4963   attribute \enum_value_0000011 "OP_ADDPCIS"
4964   attribute \enum_value_0000100 "OP_AND"
4965   attribute \enum_value_0000101 "OP_ATTN"
4966   attribute \enum_value_0000110 "OP_B"
4967   attribute \enum_value_0000111 "OP_BC"
4968   attribute \enum_value_0001000 "OP_BCREG"
4969   attribute \enum_value_0001001 "OP_BPERM"
4970   attribute \enum_value_0001010 "OP_CMP"
4971   attribute \enum_value_0001011 "OP_CMPB"
4972   attribute \enum_value_0001100 "OP_CMPEQB"
4973   attribute \enum_value_0001101 "OP_CMPRB"
4974   attribute \enum_value_0001110 "OP_CNTZ"
4975   attribute \enum_value_0001111 "OP_CRAND"
4976   attribute \enum_value_0010000 "OP_CRANDC"
4977   attribute \enum_value_0010001 "OP_CREQV"
4978   attribute \enum_value_0010010 "OP_CRNAND"
4979   attribute \enum_value_0010011 "OP_CRNOR"
4980   attribute \enum_value_0010100 "OP_CROR"
4981   attribute \enum_value_0010101 "OP_CRORC"
4982   attribute \enum_value_0010110 "OP_CRXOR"
4983   attribute \enum_value_0010111 "OP_DARN"
4984   attribute \enum_value_0011000 "OP_DCBF"
4985   attribute \enum_value_0011001 "OP_DCBST"
4986   attribute \enum_value_0011010 "OP_DCBT"
4987   attribute \enum_value_0011011 "OP_DCBTST"
4988   attribute \enum_value_0011100 "OP_DCBZ"
4989   attribute \enum_value_0011101 "OP_DIV"
4990   attribute \enum_value_0011110 "OP_DIVE"
4991   attribute \enum_value_0011111 "OP_EXTS"
4992   attribute \enum_value_0100000 "OP_EXTSWSLI"
4993   attribute \enum_value_0100001 "OP_ICBI"
4994   attribute \enum_value_0100010 "OP_ICBT"
4995   attribute \enum_value_0100011 "OP_ISEL"
4996   attribute \enum_value_0100100 "OP_ISYNC"
4997   attribute \enum_value_0100101 "OP_LOAD"
4998   attribute \enum_value_0100110 "OP_STORE"
4999   attribute \enum_value_0100111 "OP_MADDHD"
5000   attribute \enum_value_0101000 "OP_MADDHDU"
5001   attribute \enum_value_0101001 "OP_MADDLD"
5002   attribute \enum_value_0101010 "OP_MCRF"
5003   attribute \enum_value_0101011 "OP_MCRXR"
5004   attribute \enum_value_0101100 "OP_MCRXRX"
5005   attribute \enum_value_0101101 "OP_MFCR"
5006   attribute \enum_value_0101110 "OP_MFSPR"
5007   attribute \enum_value_0101111 "OP_MOD"
5008   attribute \enum_value_0110000 "OP_MTCRF"
5009   attribute \enum_value_0110001 "OP_MTSPR"
5010   attribute \enum_value_0110010 "OP_MUL_L64"
5011   attribute \enum_value_0110011 "OP_MUL_H64"
5012   attribute \enum_value_0110100 "OP_MUL_H32"
5013   attribute \enum_value_0110101 "OP_OR"
5014   attribute \enum_value_0110110 "OP_POPCNT"
5015   attribute \enum_value_0110111 "OP_PRTY"
5016   attribute \enum_value_0111000 "OP_RLC"
5017   attribute \enum_value_0111001 "OP_RLCL"
5018   attribute \enum_value_0111010 "OP_RLCR"
5019   attribute \enum_value_0111011 "OP_SETB"
5020   attribute \enum_value_0111100 "OP_SHL"
5021   attribute \enum_value_0111101 "OP_SHR"
5022   attribute \enum_value_0111110 "OP_SYNC"
5023   attribute \enum_value_0111111 "OP_TRAP"
5024   attribute \enum_value_1000011 "OP_XOR"
5025   attribute \enum_value_1000100 "OP_SIM_CONFIG"
5026   attribute \enum_value_1000101 "OP_CROP"
5027   attribute \enum_value_1000110 "OP_RFID"
5028   attribute \enum_value_1000111 "OP_MFMSR"
5029   attribute \enum_value_1001000 "OP_MTMSRD"
5030   attribute \enum_value_1001001 "OP_SC"
5031   attribute \enum_value_1001010 "OP_MTMSR"
5032   attribute \enum_value_1001011 "OP_TLBIE"
5033   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5034   wire width 7 \dec58_dec58_internal_op
5035   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5036   wire \dec58_dec58_inv_a
5037   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5038   wire \dec58_dec58_inv_out
5039   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5040   wire \dec58_dec58_is_32b
5041   attribute \enum_base_type "LdstLen"
5042   attribute \enum_value_0000 "NONE"
5043   attribute \enum_value_0001 "is1B"
5044   attribute \enum_value_0010 "is2B"
5045   attribute \enum_value_0100 "is4B"
5046   attribute \enum_value_1000 "is8B"
5047   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5048   wire width 4 \dec58_dec58_ldst_len
5049   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5050   wire \dec58_dec58_lk
5051   attribute \enum_base_type "OutSel"
5052   attribute \enum_value_00 "NONE"
5053   attribute \enum_value_01 "RT"
5054   attribute \enum_value_10 "RA"
5055   attribute \enum_value_11 "SPR"
5056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5057   wire width 2 \dec58_dec58_out_sel
5058   attribute \enum_base_type "RC"
5059   attribute \enum_value_00 "NONE"
5060   attribute \enum_value_01 "ONE"
5061   attribute \enum_value_10 "RC"
5062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5063   wire width 2 \dec58_dec58_rc_sel
5064   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5065   wire \dec58_dec58_rsrv
5066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5067   wire \dec58_dec58_sgl_pipe
5068   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5069   wire \dec58_dec58_sgn
5070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5071   wire \dec58_dec58_sgn_ext
5072   attribute \enum_base_type "LDSTMode"
5073   attribute \enum_value_00 "NONE"
5074   attribute \enum_value_01 "update"
5075   attribute \enum_value_10 "cix"
5076   attribute \enum_value_11 "cx"
5077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5078   wire width 2 \dec58_dec58_upd
5079   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
5080   wire width 32 \dec58_opcode_in
5081   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5082   wire width 8 \dec62_dec62_asmcode
5083   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5084   wire \dec62_dec62_br
5085   attribute \enum_base_type "CRInSel"
5086   attribute \enum_value_000 "NONE"
5087   attribute \enum_value_001 "CR0"
5088   attribute \enum_value_010 "BI"
5089   attribute \enum_value_011 "BFA"
5090   attribute \enum_value_100 "BA_BB"
5091   attribute \enum_value_101 "BC"
5092   attribute \enum_value_110 "WHOLE_REG"
5093   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5094   wire width 3 \dec62_dec62_cr_in
5095   attribute \enum_base_type "CROutSel"
5096   attribute \enum_value_000 "NONE"
5097   attribute \enum_value_001 "CR0"
5098   attribute \enum_value_010 "BF"
5099   attribute \enum_value_011 "BT"
5100   attribute \enum_value_100 "WHOLE_REG"
5101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5102   wire width 3 \dec62_dec62_cr_out
5103   attribute \enum_base_type "CryIn"
5104   attribute \enum_value_00 "ZERO"
5105   attribute \enum_value_01 "ONE"
5106   attribute \enum_value_10 "CA"
5107   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5108   wire width 2 \dec62_dec62_cry_in
5109   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5110   wire \dec62_dec62_cry_out
5111   attribute \enum_base_type "Form"
5112   attribute \enum_value_00000 "NONE"
5113   attribute \enum_value_00001 "I"
5114   attribute \enum_value_00010 "B"
5115   attribute \enum_value_00011 "SC"
5116   attribute \enum_value_00100 "D"
5117   attribute \enum_value_00101 "DS"
5118   attribute \enum_value_00110 "DQ"
5119   attribute \enum_value_00111 "DX"
5120   attribute \enum_value_01000 "X"
5121   attribute \enum_value_01001 "XL"
5122   attribute \enum_value_01010 "XFX"
5123   attribute \enum_value_01011 "XFL"
5124   attribute \enum_value_01100 "XX1"
5125   attribute \enum_value_01101 "XX2"
5126   attribute \enum_value_01110 "XX3"
5127   attribute \enum_value_01111 "XX4"
5128   attribute \enum_value_10000 "XS"
5129   attribute \enum_value_10001 "XO"
5130   attribute \enum_value_10010 "A"
5131   attribute \enum_value_10011 "M"
5132   attribute \enum_value_10100 "MD"
5133   attribute \enum_value_10101 "MDS"
5134   attribute \enum_value_10110 "VA"
5135   attribute \enum_value_10111 "VC"
5136   attribute \enum_value_11000 "VX"
5137   attribute \enum_value_11001 "EVX"
5138   attribute \enum_value_11010 "EVS"
5139   attribute \enum_value_11011 "Z22"
5140   attribute \enum_value_11100 "Z23"
5141   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5142   wire width 5 \dec62_dec62_form
5143   attribute \enum_base_type "Function"
5144   attribute \enum_value_000000000000 "NONE"
5145   attribute \enum_value_000000000010 "ALU"
5146   attribute \enum_value_000000000100 "LDST"
5147   attribute \enum_value_000000001000 "SHIFT_ROT"
5148   attribute \enum_value_000000010000 "LOGICAL"
5149   attribute \enum_value_000000100000 "BRANCH"
5150   attribute \enum_value_000001000000 "CR"
5151   attribute \enum_value_000010000000 "TRAP"
5152   attribute \enum_value_000100000000 "MUL"
5153   attribute \enum_value_001000000000 "DIV"
5154   attribute \enum_value_010000000000 "SPR"
5155   attribute \enum_value_100000000000 "MMU"
5156   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5157   wire width 12 \dec62_dec62_function_unit
5158   attribute \enum_base_type "In1Sel"
5159   attribute \enum_value_000 "NONE"
5160   attribute \enum_value_001 "RA"
5161   attribute \enum_value_010 "RA_OR_ZERO"
5162   attribute \enum_value_011 "SPR"
5163   attribute \enum_value_100 "RS"
5164   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5165   wire width 3 \dec62_dec62_in1_sel
5166   attribute \enum_base_type "In2Sel"
5167   attribute \enum_value_0000 "NONE"
5168   attribute \enum_value_0001 "RB"
5169   attribute \enum_value_0010 "CONST_UI"
5170   attribute \enum_value_0011 "CONST_SI"
5171   attribute \enum_value_0100 "CONST_UI_HI"
5172   attribute \enum_value_0101 "CONST_SI_HI"
5173   attribute \enum_value_0110 "CONST_LI"
5174   attribute \enum_value_0111 "CONST_BD"
5175   attribute \enum_value_1000 "CONST_DS"
5176   attribute \enum_value_1001 "CONST_M1"
5177   attribute \enum_value_1010 "CONST_SH"
5178   attribute \enum_value_1011 "CONST_SH32"
5179   attribute \enum_value_1100 "SPR"
5180   attribute \enum_value_1101 "RS"
5181   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5182   wire width 4 \dec62_dec62_in2_sel
5183   attribute \enum_base_type "In3Sel"
5184   attribute \enum_value_00 "NONE"
5185   attribute \enum_value_01 "RS"
5186   attribute \enum_value_10 "RB"
5187   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5188   wire width 2 \dec62_dec62_in3_sel
5189   attribute \enum_base_type "MicrOp"
5190   attribute \enum_value_0000000 "OP_ILLEGAL"
5191   attribute \enum_value_0000001 "OP_NOP"
5192   attribute \enum_value_0000010 "OP_ADD"
5193   attribute \enum_value_0000011 "OP_ADDPCIS"
5194   attribute \enum_value_0000100 "OP_AND"
5195   attribute \enum_value_0000101 "OP_ATTN"
5196   attribute \enum_value_0000110 "OP_B"
5197   attribute \enum_value_0000111 "OP_BC"
5198   attribute \enum_value_0001000 "OP_BCREG"
5199   attribute \enum_value_0001001 "OP_BPERM"
5200   attribute \enum_value_0001010 "OP_CMP"
5201   attribute \enum_value_0001011 "OP_CMPB"
5202   attribute \enum_value_0001100 "OP_CMPEQB"
5203   attribute \enum_value_0001101 "OP_CMPRB"
5204   attribute \enum_value_0001110 "OP_CNTZ"
5205   attribute \enum_value_0001111 "OP_CRAND"
5206   attribute \enum_value_0010000 "OP_CRANDC"
5207   attribute \enum_value_0010001 "OP_CREQV"
5208   attribute \enum_value_0010010 "OP_CRNAND"
5209   attribute \enum_value_0010011 "OP_CRNOR"
5210   attribute \enum_value_0010100 "OP_CROR"
5211   attribute \enum_value_0010101 "OP_CRORC"
5212   attribute \enum_value_0010110 "OP_CRXOR"
5213   attribute \enum_value_0010111 "OP_DARN"
5214   attribute \enum_value_0011000 "OP_DCBF"
5215   attribute \enum_value_0011001 "OP_DCBST"
5216   attribute \enum_value_0011010 "OP_DCBT"
5217   attribute \enum_value_0011011 "OP_DCBTST"
5218   attribute \enum_value_0011100 "OP_DCBZ"
5219   attribute \enum_value_0011101 "OP_DIV"
5220   attribute \enum_value_0011110 "OP_DIVE"
5221   attribute \enum_value_0011111 "OP_EXTS"
5222   attribute \enum_value_0100000 "OP_EXTSWSLI"
5223   attribute \enum_value_0100001 "OP_ICBI"
5224   attribute \enum_value_0100010 "OP_ICBT"
5225   attribute \enum_value_0100011 "OP_ISEL"
5226   attribute \enum_value_0100100 "OP_ISYNC"
5227   attribute \enum_value_0100101 "OP_LOAD"
5228   attribute \enum_value_0100110 "OP_STORE"
5229   attribute \enum_value_0100111 "OP_MADDHD"
5230   attribute \enum_value_0101000 "OP_MADDHDU"
5231   attribute \enum_value_0101001 "OP_MADDLD"
5232   attribute \enum_value_0101010 "OP_MCRF"
5233   attribute \enum_value_0101011 "OP_MCRXR"
5234   attribute \enum_value_0101100 "OP_MCRXRX"
5235   attribute \enum_value_0101101 "OP_MFCR"
5236   attribute \enum_value_0101110 "OP_MFSPR"
5237   attribute \enum_value_0101111 "OP_MOD"
5238   attribute \enum_value_0110000 "OP_MTCRF"
5239   attribute \enum_value_0110001 "OP_MTSPR"
5240   attribute \enum_value_0110010 "OP_MUL_L64"
5241   attribute \enum_value_0110011 "OP_MUL_H64"
5242   attribute \enum_value_0110100 "OP_MUL_H32"
5243   attribute \enum_value_0110101 "OP_OR"
5244   attribute \enum_value_0110110 "OP_POPCNT"
5245   attribute \enum_value_0110111 "OP_PRTY"
5246   attribute \enum_value_0111000 "OP_RLC"
5247   attribute \enum_value_0111001 "OP_RLCL"
5248   attribute \enum_value_0111010 "OP_RLCR"
5249   attribute \enum_value_0111011 "OP_SETB"
5250   attribute \enum_value_0111100 "OP_SHL"
5251   attribute \enum_value_0111101 "OP_SHR"
5252   attribute \enum_value_0111110 "OP_SYNC"
5253   attribute \enum_value_0111111 "OP_TRAP"
5254   attribute \enum_value_1000011 "OP_XOR"
5255   attribute \enum_value_1000100 "OP_SIM_CONFIG"
5256   attribute \enum_value_1000101 "OP_CROP"
5257   attribute \enum_value_1000110 "OP_RFID"
5258   attribute \enum_value_1000111 "OP_MFMSR"
5259   attribute \enum_value_1001000 "OP_MTMSRD"
5260   attribute \enum_value_1001001 "OP_SC"
5261   attribute \enum_value_1001010 "OP_MTMSR"
5262   attribute \enum_value_1001011 "OP_TLBIE"
5263   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5264   wire width 7 \dec62_dec62_internal_op
5265   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5266   wire \dec62_dec62_inv_a
5267   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5268   wire \dec62_dec62_inv_out
5269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5270   wire \dec62_dec62_is_32b
5271   attribute \enum_base_type "LdstLen"
5272   attribute \enum_value_0000 "NONE"
5273   attribute \enum_value_0001 "is1B"
5274   attribute \enum_value_0010 "is2B"
5275   attribute \enum_value_0100 "is4B"
5276   attribute \enum_value_1000 "is8B"
5277   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5278   wire width 4 \dec62_dec62_ldst_len
5279   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5280   wire \dec62_dec62_lk
5281   attribute \enum_base_type "OutSel"
5282   attribute \enum_value_00 "NONE"
5283   attribute \enum_value_01 "RT"
5284   attribute \enum_value_10 "RA"
5285   attribute \enum_value_11 "SPR"
5286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5287   wire width 2 \dec62_dec62_out_sel
5288   attribute \enum_base_type "RC"
5289   attribute \enum_value_00 "NONE"
5290   attribute \enum_value_01 "ONE"
5291   attribute \enum_value_10 "RC"
5292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5293   wire width 2 \dec62_dec62_rc_sel
5294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5295   wire \dec62_dec62_rsrv
5296   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5297   wire \dec62_dec62_sgl_pipe
5298   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5299   wire \dec62_dec62_sgn
5300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5301   wire \dec62_dec62_sgn_ext
5302   attribute \enum_base_type "LDSTMode"
5303   attribute \enum_value_00 "NONE"
5304   attribute \enum_value_01 "update"
5305   attribute \enum_value_10 "cix"
5306   attribute \enum_value_11 "cx"
5307   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5308   wire width 2 \dec62_dec62_upd
5309   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
5310   wire width 32 \dec62_opcode_in
5311   attribute \enum_base_type "Form"
5312   attribute \enum_value_00000 "NONE"
5313   attribute \enum_value_00001 "I"
5314   attribute \enum_value_00010 "B"
5315   attribute \enum_value_00011 "SC"
5316   attribute \enum_value_00100 "D"
5317   attribute \enum_value_00101 "DS"
5318   attribute \enum_value_00110 "DQ"
5319   attribute \enum_value_00111 "DX"
5320   attribute \enum_value_01000 "X"
5321   attribute \enum_value_01001 "XL"
5322   attribute \enum_value_01010 "XFX"
5323   attribute \enum_value_01011 "XFL"
5324   attribute \enum_value_01100 "XX1"
5325   attribute \enum_value_01101 "XX2"
5326   attribute \enum_value_01110 "XX3"
5327   attribute \enum_value_01111 "XX4"
5328   attribute \enum_value_10000 "XS"
5329   attribute \enum_value_10001 "XO"
5330   attribute \enum_value_10010 "A"
5331   attribute \enum_value_10011 "M"
5332   attribute \enum_value_10100 "MD"
5333   attribute \enum_value_10101 "MDS"
5334   attribute \enum_value_10110 "VA"
5335   attribute \enum_value_10111 "VC"
5336   attribute \enum_value_11000 "VX"
5337   attribute \enum_value_11001 "EVX"
5338   attribute \enum_value_11010 "EVS"
5339   attribute \enum_value_11011 "Z22"
5340   attribute \enum_value_11100 "Z23"
5341   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5342   wire width 5 \form
5343   attribute \enum_base_type "Function"
5344   attribute \enum_value_000000000000 "NONE"
5345   attribute \enum_value_000000000010 "ALU"
5346   attribute \enum_value_000000000100 "LDST"
5347   attribute \enum_value_000000001000 "SHIFT_ROT"
5348   attribute \enum_value_000000010000 "LOGICAL"
5349   attribute \enum_value_000000100000 "BRANCH"
5350   attribute \enum_value_000001000000 "CR"
5351   attribute \enum_value_000010000000 "TRAP"
5352   attribute \enum_value_000100000000 "MUL"
5353   attribute \enum_value_001000000000 "DIV"
5354   attribute \enum_value_010000000000 "SPR"
5355   attribute \enum_value_100000000000 "MMU"
5356   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5357   wire width 12 output 7 \function_unit
5358   attribute \enum_base_type "In1Sel"
5359   attribute \enum_value_000 "NONE"
5360   attribute \enum_value_001 "RA"
5361   attribute \enum_value_010 "RA_OR_ZERO"
5362   attribute \enum_value_011 "SPR"
5363   attribute \enum_value_100 "RS"
5364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5365   wire width 3 output 12 \in1_sel
5366   attribute \enum_base_type "In2Sel"
5367   attribute \enum_value_0000 "NONE"
5368   attribute \enum_value_0001 "RB"
5369   attribute \enum_value_0010 "CONST_UI"
5370   attribute \enum_value_0011 "CONST_SI"
5371   attribute \enum_value_0100 "CONST_UI_HI"
5372   attribute \enum_value_0101 "CONST_SI_HI"
5373   attribute \enum_value_0110 "CONST_LI"
5374   attribute \enum_value_0111 "CONST_BD"
5375   attribute \enum_value_1000 "CONST_DS"
5376   attribute \enum_value_1001 "CONST_M1"
5377   attribute \enum_value_1010 "CONST_SH"
5378   attribute \enum_value_1011 "CONST_SH32"
5379   attribute \enum_value_1100 "SPR"
5380   attribute \enum_value_1101 "RS"
5381   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5382   wire width 4 output 13 \in2_sel
5383   attribute \enum_base_type "In3Sel"
5384   attribute \enum_value_00 "NONE"
5385   attribute \enum_value_01 "RS"
5386   attribute \enum_value_10 "RB"
5387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5388   wire width 2 output 14 \in3_sel
5389   attribute \src "libresoc.v:1192.7-1192.15"
5390   wire \initial
5391   attribute \enum_base_type "MicrOp"
5392   attribute \enum_value_0000000 "OP_ILLEGAL"
5393   attribute \enum_value_0000001 "OP_NOP"
5394   attribute \enum_value_0000010 "OP_ADD"
5395   attribute \enum_value_0000011 "OP_ADDPCIS"
5396   attribute \enum_value_0000100 "OP_AND"
5397   attribute \enum_value_0000101 "OP_ATTN"
5398   attribute \enum_value_0000110 "OP_B"
5399   attribute \enum_value_0000111 "OP_BC"
5400   attribute \enum_value_0001000 "OP_BCREG"
5401   attribute \enum_value_0001001 "OP_BPERM"
5402   attribute \enum_value_0001010 "OP_CMP"
5403   attribute \enum_value_0001011 "OP_CMPB"
5404   attribute \enum_value_0001100 "OP_CMPEQB"
5405   attribute \enum_value_0001101 "OP_CMPRB"
5406   attribute \enum_value_0001110 "OP_CNTZ"
5407   attribute \enum_value_0001111 "OP_CRAND"
5408   attribute \enum_value_0010000 "OP_CRANDC"
5409   attribute \enum_value_0010001 "OP_CREQV"
5410   attribute \enum_value_0010010 "OP_CRNAND"
5411   attribute \enum_value_0010011 "OP_CRNOR"
5412   attribute \enum_value_0010100 "OP_CROR"
5413   attribute \enum_value_0010101 "OP_CRORC"
5414   attribute \enum_value_0010110 "OP_CRXOR"
5415   attribute \enum_value_0010111 "OP_DARN"
5416   attribute \enum_value_0011000 "OP_DCBF"
5417   attribute \enum_value_0011001 "OP_DCBST"
5418   attribute \enum_value_0011010 "OP_DCBT"
5419   attribute \enum_value_0011011 "OP_DCBTST"
5420   attribute \enum_value_0011100 "OP_DCBZ"
5421   attribute \enum_value_0011101 "OP_DIV"
5422   attribute \enum_value_0011110 "OP_DIVE"
5423   attribute \enum_value_0011111 "OP_EXTS"
5424   attribute \enum_value_0100000 "OP_EXTSWSLI"
5425   attribute \enum_value_0100001 "OP_ICBI"
5426   attribute \enum_value_0100010 "OP_ICBT"
5427   attribute \enum_value_0100011 "OP_ISEL"
5428   attribute \enum_value_0100100 "OP_ISYNC"
5429   attribute \enum_value_0100101 "OP_LOAD"
5430   attribute \enum_value_0100110 "OP_STORE"
5431   attribute \enum_value_0100111 "OP_MADDHD"
5432   attribute \enum_value_0101000 "OP_MADDHDU"
5433   attribute \enum_value_0101001 "OP_MADDLD"
5434   attribute \enum_value_0101010 "OP_MCRF"
5435   attribute \enum_value_0101011 "OP_MCRXR"
5436   attribute \enum_value_0101100 "OP_MCRXRX"
5437   attribute \enum_value_0101101 "OP_MFCR"
5438   attribute \enum_value_0101110 "OP_MFSPR"
5439   attribute \enum_value_0101111 "OP_MOD"
5440   attribute \enum_value_0110000 "OP_MTCRF"
5441   attribute \enum_value_0110001 "OP_MTSPR"
5442   attribute \enum_value_0110010 "OP_MUL_L64"
5443   attribute \enum_value_0110011 "OP_MUL_H64"
5444   attribute \enum_value_0110100 "OP_MUL_H32"
5445   attribute \enum_value_0110101 "OP_OR"
5446   attribute \enum_value_0110110 "OP_POPCNT"
5447   attribute \enum_value_0110111 "OP_PRTY"
5448   attribute \enum_value_0111000 "OP_RLC"
5449   attribute \enum_value_0111001 "OP_RLCL"
5450   attribute \enum_value_0111010 "OP_RLCR"
5451   attribute \enum_value_0111011 "OP_SETB"
5452   attribute \enum_value_0111100 "OP_SHL"
5453   attribute \enum_value_0111101 "OP_SHR"
5454   attribute \enum_value_0111110 "OP_SYNC"
5455   attribute \enum_value_0111111 "OP_TRAP"
5456   attribute \enum_value_1000011 "OP_XOR"
5457   attribute \enum_value_1000100 "OP_SIM_CONFIG"
5458   attribute \enum_value_1000101 "OP_CROP"
5459   attribute \enum_value_1000110 "OP_RFID"
5460   attribute \enum_value_1000111 "OP_MFMSR"
5461   attribute \enum_value_1001000 "OP_MTMSRD"
5462   attribute \enum_value_1001001 "OP_SC"
5463   attribute \enum_value_1001010 "OP_MTMSR"
5464   attribute \enum_value_1001011 "OP_TLBIE"
5465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5466   wire width 7 output 6 \internal_op
5467   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5468   wire \inv_a
5469   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5470   wire \inv_out
5471   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5472   wire output 9 \is_32b
5473   attribute \enum_base_type "LdstLen"
5474   attribute \enum_value_0000 "NONE"
5475   attribute \enum_value_0001 "is1B"
5476   attribute \enum_value_0010 "is2B"
5477   attribute \enum_value_0100 "is4B"
5478   attribute \enum_value_1000 "is8B"
5479   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5480   wire width 4 \ldst_len
5481   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5482   wire output 10 \lk
5483   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
5484   wire width 32 output 2 \opcode_in
5485   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
5486   wire width 6 \opcode_switch
5487   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
5488   wire width 32 \opcode_switch$1
5489   attribute \enum_base_type "OutSel"
5490   attribute \enum_value_00 "NONE"
5491   attribute \enum_value_01 "RT"
5492   attribute \enum_value_10 "RA"
5493   attribute \enum_value_11 "SPR"
5494   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5495   wire width 2 output 15 \out_sel
5496   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445"
5497   wire width 32 input 1 \raw_opcode_in
5498   attribute \enum_base_type "RC"
5499   attribute \enum_value_00 "NONE"
5500   attribute \enum_value_01 "ONE"
5501   attribute \enum_value_10 "RC"
5502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5503   wire width 2 output 3 \rc_sel
5504   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5505   wire \rsrv
5506   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5507   wire \sgl_pipe
5508   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5509   wire \sgn
5510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
5511   wire \sgn_ext
5512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
5513   wire width 6 \sh
5514   attribute \enum_base_type "LDSTMode"
5515   attribute \enum_value_00 "NONE"
5516   attribute \enum_value_01 "update"
5517   attribute \enum_value_10 "cix"
5518   attribute \enum_value_11 "cx"
5519   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
5520   wire width 2 output 17 \upd
5521   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485"
5522   cell $mux $ternary$libresoc.v:3249$237
5523     parameter \WIDTH 32
5524     connect \A \raw_opcode_in
5525     connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
5526     connect \S \bigendian
5527     connect \Y $ternary$libresoc.v:3249$237_Y
5528   end
5529   attribute \module_not_derived 1
5530   attribute \src "libresoc.v:3250.9-3276.4"
5531   cell \dec19 \dec19
5532     connect \dec19_asmcode \dec19_dec19_asmcode
5533     connect \dec19_br \dec19_dec19_br
5534     connect \dec19_cr_in \dec19_dec19_cr_in
5535     connect \dec19_cr_out \dec19_dec19_cr_out
5536     connect \dec19_cry_in \dec19_dec19_cry_in
5537     connect \dec19_cry_out \dec19_dec19_cry_out
5538     connect \dec19_form \dec19_dec19_form
5539     connect \dec19_function_unit \dec19_dec19_function_unit
5540     connect \dec19_in1_sel \dec19_dec19_in1_sel
5541     connect \dec19_in2_sel \dec19_dec19_in2_sel
5542     connect \dec19_in3_sel \dec19_dec19_in3_sel
5543     connect \dec19_internal_op \dec19_dec19_internal_op
5544     connect \dec19_inv_a \dec19_dec19_inv_a
5545     connect \dec19_inv_out \dec19_dec19_inv_out
5546     connect \dec19_is_32b \dec19_dec19_is_32b
5547     connect \dec19_ldst_len \dec19_dec19_ldst_len
5548     connect \dec19_lk \dec19_dec19_lk
5549     connect \dec19_out_sel \dec19_dec19_out_sel
5550     connect \dec19_rc_sel \dec19_dec19_rc_sel
5551     connect \dec19_rsrv \dec19_dec19_rsrv
5552     connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe
5553     connect \dec19_sgn \dec19_dec19_sgn
5554     connect \dec19_sgn_ext \dec19_dec19_sgn_ext
5555     connect \dec19_upd \dec19_dec19_upd
5556     connect \opcode_in \dec19_opcode_in
5557   end
5558   attribute \module_not_derived 1
5559   attribute \src "libresoc.v:3277.9-3303.4"
5560   cell \dec30 \dec30
5561     connect \dec30_asmcode \dec30_dec30_asmcode
5562     connect \dec30_br \dec30_dec30_br
5563     connect \dec30_cr_in \dec30_dec30_cr_in
5564     connect \dec30_cr_out \dec30_dec30_cr_out
5565     connect \dec30_cry_in \dec30_dec30_cry_in
5566     connect \dec30_cry_out \dec30_dec30_cry_out
5567     connect \dec30_form \dec30_dec30_form
5568     connect \dec30_function_unit \dec30_dec30_function_unit
5569     connect \dec30_in1_sel \dec30_dec30_in1_sel
5570     connect \dec30_in2_sel \dec30_dec30_in2_sel
5571     connect \dec30_in3_sel \dec30_dec30_in3_sel
5572     connect \dec30_internal_op \dec30_dec30_internal_op
5573     connect \dec30_inv_a \dec30_dec30_inv_a
5574     connect \dec30_inv_out \dec30_dec30_inv_out
5575     connect \dec30_is_32b \dec30_dec30_is_32b
5576     connect \dec30_ldst_len \dec30_dec30_ldst_len
5577     connect \dec30_lk \dec30_dec30_lk
5578     connect \dec30_out_sel \dec30_dec30_out_sel
5579     connect \dec30_rc_sel \dec30_dec30_rc_sel
5580     connect \dec30_rsrv \dec30_dec30_rsrv
5581     connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe
5582     connect \dec30_sgn \dec30_dec30_sgn
5583     connect \dec30_sgn_ext \dec30_dec30_sgn_ext
5584     connect \dec30_upd \dec30_dec30_upd
5585     connect \opcode_in \dec30_opcode_in
5586   end
5587   attribute \module_not_derived 1
5588   attribute \src "libresoc.v:3304.9-3330.4"
5589   cell \dec31 \dec31
5590     connect \dec31_asmcode \dec31_dec31_asmcode
5591     connect \dec31_br \dec31_dec31_br
5592     connect \dec31_cr_in \dec31_dec31_cr_in
5593     connect \dec31_cr_out \dec31_dec31_cr_out
5594     connect \dec31_cry_in \dec31_dec31_cry_in
5595     connect \dec31_cry_out \dec31_dec31_cry_out
5596     connect \dec31_form \dec31_dec31_form
5597     connect \dec31_function_unit \dec31_dec31_function_unit
5598     connect \dec31_in1_sel \dec31_dec31_in1_sel
5599     connect \dec31_in2_sel \dec31_dec31_in2_sel
5600     connect \dec31_in3_sel \dec31_dec31_in3_sel
5601     connect \dec31_internal_op \dec31_dec31_internal_op
5602     connect \dec31_inv_a \dec31_dec31_inv_a
5603     connect \dec31_inv_out \dec31_dec31_inv_out
5604     connect \dec31_is_32b \dec31_dec31_is_32b
5605     connect \dec31_ldst_len \dec31_dec31_ldst_len
5606     connect \dec31_lk \dec31_dec31_lk
5607     connect \dec31_out_sel \dec31_dec31_out_sel
5608     connect \dec31_rc_sel \dec31_dec31_rc_sel
5609     connect \dec31_rsrv \dec31_dec31_rsrv
5610     connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe
5611     connect \dec31_sgn \dec31_dec31_sgn
5612     connect \dec31_sgn_ext \dec31_dec31_sgn_ext
5613     connect \dec31_upd \dec31_dec31_upd
5614     connect \opcode_in \dec31_opcode_in
5615   end
5616   attribute \module_not_derived 1
5617   attribute \src "libresoc.v:3331.9-3357.4"
5618   cell \dec58 \dec58
5619     connect \dec58_asmcode \dec58_dec58_asmcode
5620     connect \dec58_br \dec58_dec58_br
5621     connect \dec58_cr_in \dec58_dec58_cr_in
5622     connect \dec58_cr_out \dec58_dec58_cr_out
5623     connect \dec58_cry_in \dec58_dec58_cry_in
5624     connect \dec58_cry_out \dec58_dec58_cry_out
5625     connect \dec58_form \dec58_dec58_form
5626     connect \dec58_function_unit \dec58_dec58_function_unit
5627     connect \dec58_in1_sel \dec58_dec58_in1_sel
5628     connect \dec58_in2_sel \dec58_dec58_in2_sel
5629     connect \dec58_in3_sel \dec58_dec58_in3_sel
5630     connect \dec58_internal_op \dec58_dec58_internal_op
5631     connect \dec58_inv_a \dec58_dec58_inv_a
5632     connect \dec58_inv_out \dec58_dec58_inv_out
5633     connect \dec58_is_32b \dec58_dec58_is_32b
5634     connect \dec58_ldst_len \dec58_dec58_ldst_len
5635     connect \dec58_lk \dec58_dec58_lk
5636     connect \dec58_out_sel \dec58_dec58_out_sel
5637     connect \dec58_rc_sel \dec58_dec58_rc_sel
5638     connect \dec58_rsrv \dec58_dec58_rsrv
5639     connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe
5640     connect \dec58_sgn \dec58_dec58_sgn
5641     connect \dec58_sgn_ext \dec58_dec58_sgn_ext
5642     connect \dec58_upd \dec58_dec58_upd
5643     connect \opcode_in \dec58_opcode_in
5644   end
5645   attribute \module_not_derived 1
5646   attribute \src "libresoc.v:3358.9-3384.4"
5647   cell \dec62 \dec62
5648     connect \dec62_asmcode \dec62_dec62_asmcode
5649     connect \dec62_br \dec62_dec62_br
5650     connect \dec62_cr_in \dec62_dec62_cr_in
5651     connect \dec62_cr_out \dec62_dec62_cr_out
5652     connect \dec62_cry_in \dec62_dec62_cry_in
5653     connect \dec62_cry_out \dec62_dec62_cry_out
5654     connect \dec62_form \dec62_dec62_form
5655     connect \dec62_function_unit \dec62_dec62_function_unit
5656     connect \dec62_in1_sel \dec62_dec62_in1_sel
5657     connect \dec62_in2_sel \dec62_dec62_in2_sel
5658     connect \dec62_in3_sel \dec62_dec62_in3_sel
5659     connect \dec62_internal_op \dec62_dec62_internal_op
5660     connect \dec62_inv_a \dec62_dec62_inv_a
5661     connect \dec62_inv_out \dec62_dec62_inv_out
5662     connect \dec62_is_32b \dec62_dec62_is_32b
5663     connect \dec62_ldst_len \dec62_dec62_ldst_len
5664     connect \dec62_lk \dec62_dec62_lk
5665     connect \dec62_out_sel \dec62_dec62_out_sel
5666     connect \dec62_rc_sel \dec62_dec62_rc_sel
5667     connect \dec62_rsrv \dec62_dec62_rsrv
5668     connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe
5669     connect \dec62_sgn \dec62_dec62_sgn
5670     connect \dec62_sgn_ext \dec62_dec62_sgn_ext
5671     connect \dec62_upd \dec62_dec62_upd
5672     connect \opcode_in \dec62_opcode_in
5673   end
5674   attribute \src "libresoc.v:1192.7-1192.20"
5675   process $proc$libresoc.v:1192$262
5676     assign { } { }
5677     assign $0\initial[0:0] 1'0
5678     sync always
5679       update \initial $0\initial[0:0]
5680     sync init
5681   end
5682   attribute \src "libresoc.v:3385.3-3523.6"
5683   process $proc$libresoc.v:3385$238
5684     assign { } { }
5685     assign { } { }
5686     assign { } { }
5687     assign $0\asmcode[7:0] $2\asmcode[7:0]
5688     attribute \src "libresoc.v:3386.5-3386.29"
5689     switch \initial
5690       attribute \src "libresoc.v:3386.9-3386.17"
5691       case 1'1
5692       case
5693     end
5694     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
5695     switch \opcode_switch
5696       attribute \src "libresoc.v:0.0-0.0"
5697       case 6'010011
5698         assign { } { }
5699         assign $1\asmcode[7:0] \dec19_dec19_asmcode
5700       attribute \src "libresoc.v:0.0-0.0"
5701       case 6'011110
5702         assign { } { }
5703         assign $1\asmcode[7:0] \dec30_dec30_asmcode
5704       attribute \src "libresoc.v:0.0-0.0"
5705       case 6'011111
5706         assign { } { }
5707         assign $1\asmcode[7:0] \dec31_dec31_asmcode
5708       attribute \src "libresoc.v:0.0-0.0"
5709       case 6'111010
5710         assign { } { }
5711         assign $1\asmcode[7:0] \dec58_dec58_asmcode
5712       attribute \src "libresoc.v:0.0-0.0"
5713       case 6'111110
5714         assign { } { }
5715         assign $1\asmcode[7:0] \dec62_dec62_asmcode
5716       attribute \src "libresoc.v:0.0-0.0"
5717       case 6'001100
5718         assign { } { }
5719         assign $1\asmcode[7:0] 8'00000111
5720       attribute \src "libresoc.v:0.0-0.0"
5721       case 6'001101
5722         assign { } { }
5723         assign $1\asmcode[7:0] 8'00001000
5724       attribute \src "libresoc.v:0.0-0.0"
5725       case 6'001110
5726         assign { } { }
5727         assign $1\asmcode[7:0] 8'00000110
5728       attribute \src "libresoc.v:0.0-0.0"
5729       case 6'001111
5730         assign { } { }
5731         assign $1\asmcode[7:0] 8'00001001
5732       attribute \src "libresoc.v:0.0-0.0"
5733       case 6'011100
5734         assign { } { }
5735         assign $1\asmcode[7:0] 8'00010001
5736       attribute \src "libresoc.v:0.0-0.0"
5737       case 6'011101
5738         assign { } { }
5739         assign $1\asmcode[7:0] 8'00010010
5740       attribute \src "libresoc.v:0.0-0.0"
5741       case 6'010010
5742         assign { } { }
5743         assign $1\asmcode[7:0] 8'00010100
5744       attribute \src "libresoc.v:0.0-0.0"
5745       case 6'010000
5746         assign { } { }
5747         assign $1\asmcode[7:0] 8'00010101
5748       attribute \src "libresoc.v:0.0-0.0"
5749       case 6'001011
5750         assign { } { }
5751         assign $1\asmcode[7:0] 8'00011101
5752       attribute \src "libresoc.v:0.0-0.0"
5753       case 6'001010
5754         assign { } { }
5755         assign $1\asmcode[7:0] 8'00011111
5756       attribute \src "libresoc.v:0.0-0.0"
5757       case 6'100010
5758         assign { } { }
5759         assign $1\asmcode[7:0] 8'01001110
5760       attribute \src "libresoc.v:0.0-0.0"
5761       case 6'100011
5762         assign { } { }
5763         assign $1\asmcode[7:0] 8'01001111
5764       attribute \src "libresoc.v:0.0-0.0"
5765       case 6'101010
5766         assign { } { }
5767         assign $1\asmcode[7:0] 8'01011000
5768       attribute \src "libresoc.v:0.0-0.0"
5769       case 6'101011
5770         assign { } { }
5771         assign $1\asmcode[7:0] 8'01011010
5772       attribute \src "libresoc.v:0.0-0.0"
5773       case 6'101000
5774         assign { } { }
5775         assign $1\asmcode[7:0] 8'01011110
5776       attribute \src "libresoc.v:0.0-0.0"
5777       case 6'101001
5778         assign { } { }
5779         assign $1\asmcode[7:0] 8'01011111
5780       attribute \src "libresoc.v:0.0-0.0"
5781       case 6'100000
5782         assign { } { }
5783         assign $1\asmcode[7:0] 8'01100111
5784       attribute \src "libresoc.v:0.0-0.0"
5785       case 6'100001
5786         assign { } { }
5787         assign $1\asmcode[7:0] 8'01101001
5788       attribute \src "libresoc.v:0.0-0.0"
5789       case 6'000111
5790         assign { } { }
5791         assign $1\asmcode[7:0] 8'10000000
5792       attribute \src "libresoc.v:0.0-0.0"
5793       case 6'011000
5794         assign { } { }
5795         assign $1\asmcode[7:0] 8'10001010
5796       attribute \src "libresoc.v:0.0-0.0"
5797       case 6'011001
5798         assign { } { }
5799         assign $1\asmcode[7:0] 8'10001011
5800       attribute \src "libresoc.v:0.0-0.0"
5801       case 6'010100
5802         assign { } { }
5803         assign $1\asmcode[7:0] 8'10011000
5804       attribute \src "libresoc.v:0.0-0.0"
5805       case 6'010101
5806         assign { } { }
5807         assign $1\asmcode[7:0] 8'10011001
5808       attribute \src "libresoc.v:0.0-0.0"
5809       case 6'010111
5810         assign { } { }
5811         assign $1\asmcode[7:0] 8'10011010
5812       attribute \src "libresoc.v:0.0-0.0"
5813       case 6'100110
5814         assign { } { }
5815         assign $1\asmcode[7:0] 8'10100110
5816       attribute \src "libresoc.v:0.0-0.0"
5817       case 6'100111
5818         assign { } { }
5819         assign $1\asmcode[7:0] 8'10101001
5820       attribute \src "libresoc.v:0.0-0.0"
5821       case 6'101100
5822         assign { } { }
5823         assign $1\asmcode[7:0] 8'10110010
5824       attribute \src "libresoc.v:0.0-0.0"
5825       case 6'101101
5826         assign { } { }
5827         assign $1\asmcode[7:0] 8'10110101
5828       attribute \src "libresoc.v:0.0-0.0"
5829       case 6'100100
5830         assign { } { }
5831         assign $1\asmcode[7:0] 8'10111000
5832       attribute \src "libresoc.v:0.0-0.0"
5833       case 6'100101
5834         assign { } { }
5835         assign $1\asmcode[7:0] 8'10111011
5836       attribute \src "libresoc.v:0.0-0.0"
5837       case 6'001000
5838         assign { } { }
5839         assign $1\asmcode[7:0] 8'11000011
5840       attribute \src "libresoc.v:0.0-0.0"
5841       case 6'000010
5842         assign { } { }
5843         assign $1\asmcode[7:0] 8'11001011
5844       attribute \src "libresoc.v:0.0-0.0"
5845       case 6'000011
5846         assign { } { }
5847         assign $1\asmcode[7:0] 8'11001111
5848       attribute \src "libresoc.v:0.0-0.0"
5849       case 6'011010
5850         assign { } { }
5851         assign $1\asmcode[7:0] 8'11010001
5852       attribute \src "libresoc.v:0.0-0.0"
5853       case 6'011011
5854         assign { } { }
5855         assign $1\asmcode[7:0] 8'11010010
5856       case
5857         assign $1\asmcode[7:0] 8'00000000
5858     end
5859     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
5860     switch \opcode_switch$1
5861       attribute \src "libresoc.v:0.0-0.0"
5862       case 32'000000---------------0100000000-
5863         assign { } { }
5864         assign $2\asmcode[7:0] 8'00010011
5865       attribute \src "libresoc.v:0.0-0.0"
5866       case 1610612736
5867         assign { } { }
5868         assign $2\asmcode[7:0] 8'10000110
5869       attribute \src "libresoc.v:0.0-0.0"
5870       case 32'000001---------------0000000011-
5871         assign { } { }
5872         assign $2\asmcode[7:0] 8'10011100
5873       case
5874         assign $2\asmcode[7:0] $1\asmcode[7:0]
5875     end
5876     sync always
5877       update \asmcode $0\asmcode[7:0]
5878   end
5879   attribute \src "libresoc.v:3524.3-3665.6"
5880   process $proc$libresoc.v:3524$239
5881     assign { } { }
5882     assign { } { }
5883     assign { } { }
5884     assign $0\in1_sel[2:0] $2\in1_sel[2:0]
5885     attribute \src "libresoc.v:3525.5-3525.29"
5886     switch \initial
5887       attribute \src "libresoc.v:3525.9-3525.17"
5888       case 1'1
5889       case
5890     end
5891     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
5892     switch \opcode_switch
5893       attribute \src "libresoc.v:0.0-0.0"
5894       case 6'010011
5895         assign { } { }
5896         assign $1\in1_sel[2:0] \dec19_dec19_in1_sel
5897       attribute \src "libresoc.v:0.0-0.0"
5898       case 6'011110
5899         assign { } { }
5900         assign $1\in1_sel[2:0] \dec30_dec30_in1_sel
5901       attribute \src "libresoc.v:0.0-0.0"
5902       case 6'011111
5903         assign { } { }
5904         assign $1\in1_sel[2:0] \dec31_dec31_in1_sel
5905       attribute \src "libresoc.v:0.0-0.0"
5906       case 6'111010
5907         assign { } { }
5908         assign $1\in1_sel[2:0] \dec58_dec58_in1_sel
5909       attribute \src "libresoc.v:0.0-0.0"
5910       case 6'111110
5911         assign { } { }
5912         assign $1\in1_sel[2:0] \dec62_dec62_in1_sel
5913       attribute \src "libresoc.v:0.0-0.0"
5914       case 6'001100
5915         assign { } { }
5916         assign $1\in1_sel[2:0] 3'001
5917       attribute \src "libresoc.v:0.0-0.0"
5918       case 6'001101
5919         assign { } { }
5920         assign $1\in1_sel[2:0] 3'001
5921       attribute \src "libresoc.v:0.0-0.0"
5922       case 6'001110
5923         assign { } { }
5924         assign $1\in1_sel[2:0] 3'010
5925       attribute \src "libresoc.v:0.0-0.0"
5926       case 6'001111
5927         assign { } { }
5928         assign $1\in1_sel[2:0] 3'010
5929       attribute \src "libresoc.v:0.0-0.0"
5930       case 6'010001
5931         assign { } { }
5932         assign $1\in1_sel[2:0] 3'000
5933       attribute \src "libresoc.v:0.0-0.0"
5934       case 6'011100
5935         assign { } { }
5936         assign $1\in1_sel[2:0] 3'100
5937       attribute \src "libresoc.v:0.0-0.0"
5938       case 6'011101
5939         assign { } { }
5940         assign $1\in1_sel[2:0] 3'100
5941       attribute \src "libresoc.v:0.0-0.0"
5942       case 6'010010
5943         assign { } { }
5944         assign $1\in1_sel[2:0] 3'000
5945       attribute \src "libresoc.v:0.0-0.0"
5946       case 6'010000
5947         assign { } { }
5948         assign $1\in1_sel[2:0] 3'011
5949       attribute \src "libresoc.v:0.0-0.0"
5950       case 6'001011
5951         assign { } { }
5952         assign $1\in1_sel[2:0] 3'001
5953       attribute \src "libresoc.v:0.0-0.0"
5954       case 6'001010
5955         assign { } { }
5956         assign $1\in1_sel[2:0] 3'001
5957       attribute \src "libresoc.v:0.0-0.0"
5958       case 6'100010
5959         assign { } { }
5960         assign $1\in1_sel[2:0] 3'010
5961       attribute \src "libresoc.v:0.0-0.0"
5962       case 6'100011
5963         assign { } { }
5964         assign $1\in1_sel[2:0] 3'010
5965       attribute \src "libresoc.v:0.0-0.0"
5966       case 6'101010
5967         assign { } { }
5968         assign $1\in1_sel[2:0] 3'010
5969       attribute \src "libresoc.v:0.0-0.0"
5970       case 6'101011
5971         assign { } { }
5972         assign $1\in1_sel[2:0] 3'010
5973       attribute \src "libresoc.v:0.0-0.0"
5974       case 6'101000
5975         assign { } { }
5976         assign $1\in1_sel[2:0] 3'010
5977       attribute \src "libresoc.v:0.0-0.0"
5978       case 6'101001
5979         assign { } { }
5980         assign $1\in1_sel[2:0] 3'010
5981       attribute \src "libresoc.v:0.0-0.0"
5982       case 6'100000
5983         assign { } { }
5984         assign $1\in1_sel[2:0] 3'010
5985       attribute \src "libresoc.v:0.0-0.0"
5986       case 6'100001
5987         assign { } { }
5988         assign $1\in1_sel[2:0] 3'010
5989       attribute \src "libresoc.v:0.0-0.0"
5990       case 6'000111
5991         assign { } { }
5992         assign $1\in1_sel[2:0] 3'001
5993       attribute \src "libresoc.v:0.0-0.0"
5994       case 6'011000
5995         assign { } { }
5996         assign $1\in1_sel[2:0] 3'100
5997       attribute \src "libresoc.v:0.0-0.0"
5998       case 6'011001
5999         assign { } { }
6000         assign $1\in1_sel[2:0] 3'100
6001       attribute \src "libresoc.v:0.0-0.0"
6002       case 6'010100
6003         assign { } { }
6004         assign $1\in1_sel[2:0] 3'001
6005       attribute \src "libresoc.v:0.0-0.0"
6006       case 6'010101
6007         assign { } { }
6008         assign $1\in1_sel[2:0] 3'000
6009       attribute \src "libresoc.v:0.0-0.0"
6010       case 6'010111
6011         assign { } { }
6012         assign $1\in1_sel[2:0] 3'000
6013       attribute \src "libresoc.v:0.0-0.0"
6014       case 6'100110
6015         assign { } { }
6016         assign $1\in1_sel[2:0] 3'010
6017       attribute \src "libresoc.v:0.0-0.0"
6018       case 6'100111
6019         assign { } { }
6020         assign $1\in1_sel[2:0] 3'010
6021       attribute \src "libresoc.v:0.0-0.0"
6022       case 6'101100
6023         assign { } { }
6024         assign $1\in1_sel[2:0] 3'010
6025       attribute \src "libresoc.v:0.0-0.0"
6026       case 6'101101
6027         assign { } { }
6028         assign $1\in1_sel[2:0] 3'010
6029       attribute \src "libresoc.v:0.0-0.0"
6030       case 6'100100
6031         assign { } { }
6032         assign $1\in1_sel[2:0] 3'010
6033       attribute \src "libresoc.v:0.0-0.0"
6034       case 6'100101
6035         assign { } { }
6036         assign $1\in1_sel[2:0] 3'010
6037       attribute \src "libresoc.v:0.0-0.0"
6038       case 6'001000
6039         assign { } { }
6040         assign $1\in1_sel[2:0] 3'001
6041       attribute \src "libresoc.v:0.0-0.0"
6042       case 6'000010
6043         assign { } { }
6044         assign $1\in1_sel[2:0] 3'001
6045       attribute \src "libresoc.v:0.0-0.0"
6046       case 6'000011
6047         assign { } { }
6048         assign $1\in1_sel[2:0] 3'001
6049       attribute \src "libresoc.v:0.0-0.0"
6050       case 6'011010
6051         assign { } { }
6052         assign $1\in1_sel[2:0] 3'100
6053       attribute \src "libresoc.v:0.0-0.0"
6054       case 6'011011
6055         assign { } { }
6056         assign $1\in1_sel[2:0] 3'100
6057       case
6058         assign $1\in1_sel[2:0] 3'000
6059     end
6060     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6061     switch \opcode_switch$1
6062       attribute \src "libresoc.v:0.0-0.0"
6063       case 32'000000---------------0100000000-
6064         assign { } { }
6065         assign $2\in1_sel[2:0] 3'000
6066       attribute \src "libresoc.v:0.0-0.0"
6067       case 1610612736
6068         assign { } { }
6069         assign $2\in1_sel[2:0] 3'000
6070       attribute \src "libresoc.v:0.0-0.0"
6071       case 32'000001---------------0000000011-
6072         assign { } { }
6073         assign $2\in1_sel[2:0] 3'000
6074       case
6075         assign $2\in1_sel[2:0] $1\in1_sel[2:0]
6076     end
6077     sync always
6078       update \in1_sel $0\in1_sel[2:0]
6079   end
6080   attribute \src "libresoc.v:3666.3-3807.6"
6081   process $proc$libresoc.v:3666$240
6082     assign { } { }
6083     assign { } { }
6084     assign { } { }
6085     assign $0\in2_sel[3:0] $2\in2_sel[3:0]
6086     attribute \src "libresoc.v:3667.5-3667.29"
6087     switch \initial
6088       attribute \src "libresoc.v:3667.9-3667.17"
6089       case 1'1
6090       case
6091     end
6092     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6093     switch \opcode_switch
6094       attribute \src "libresoc.v:0.0-0.0"
6095       case 6'010011
6096         assign { } { }
6097         assign $1\in2_sel[3:0] \dec19_dec19_in2_sel
6098       attribute \src "libresoc.v:0.0-0.0"
6099       case 6'011110
6100         assign { } { }
6101         assign $1\in2_sel[3:0] \dec30_dec30_in2_sel
6102       attribute \src "libresoc.v:0.0-0.0"
6103       case 6'011111
6104         assign { } { }
6105         assign $1\in2_sel[3:0] \dec31_dec31_in2_sel
6106       attribute \src "libresoc.v:0.0-0.0"
6107       case 6'111010
6108         assign { } { }
6109         assign $1\in2_sel[3:0] \dec58_dec58_in2_sel
6110       attribute \src "libresoc.v:0.0-0.0"
6111       case 6'111110
6112         assign { } { }
6113         assign $1\in2_sel[3:0] \dec62_dec62_in2_sel
6114       attribute \src "libresoc.v:0.0-0.0"
6115       case 6'001100
6116         assign { } { }
6117         assign $1\in2_sel[3:0] 4'0011
6118       attribute \src "libresoc.v:0.0-0.0"
6119       case 6'001101
6120         assign { } { }
6121         assign $1\in2_sel[3:0] 4'0011
6122       attribute \src "libresoc.v:0.0-0.0"
6123       case 6'001110
6124         assign { } { }
6125         assign $1\in2_sel[3:0] 4'0011
6126       attribute \src "libresoc.v:0.0-0.0"
6127       case 6'001111
6128         assign { } { }
6129         assign $1\in2_sel[3:0] 4'0101
6130       attribute \src "libresoc.v:0.0-0.0"
6131       case 6'010001
6132         assign { } { }
6133         assign $1\in2_sel[3:0] 4'0000
6134       attribute \src "libresoc.v:0.0-0.0"
6135       case 6'011100
6136         assign { } { }
6137         assign $1\in2_sel[3:0] 4'0010
6138       attribute \src "libresoc.v:0.0-0.0"
6139       case 6'011101
6140         assign { } { }
6141         assign $1\in2_sel[3:0] 4'0100
6142       attribute \src "libresoc.v:0.0-0.0"
6143       case 6'010010
6144         assign { } { }
6145         assign $1\in2_sel[3:0] 4'0110
6146       attribute \src "libresoc.v:0.0-0.0"
6147       case 6'010000
6148         assign { } { }
6149         assign $1\in2_sel[3:0] 4'0111
6150       attribute \src "libresoc.v:0.0-0.0"
6151       case 6'001011
6152         assign { } { }
6153         assign $1\in2_sel[3:0] 4'0011
6154       attribute \src "libresoc.v:0.0-0.0"
6155       case 6'001010
6156         assign { } { }
6157         assign $1\in2_sel[3:0] 4'0010
6158       attribute \src "libresoc.v:0.0-0.0"
6159       case 6'100010
6160         assign { } { }
6161         assign $1\in2_sel[3:0] 4'0011
6162       attribute \src "libresoc.v:0.0-0.0"
6163       case 6'100011
6164         assign { } { }
6165         assign $1\in2_sel[3:0] 4'0011
6166       attribute \src "libresoc.v:0.0-0.0"
6167       case 6'101010
6168         assign { } { }
6169         assign $1\in2_sel[3:0] 4'0011
6170       attribute \src "libresoc.v:0.0-0.0"
6171       case 6'101011
6172         assign { } { }
6173         assign $1\in2_sel[3:0] 4'0011
6174       attribute \src "libresoc.v:0.0-0.0"
6175       case 6'101000
6176         assign { } { }
6177         assign $1\in2_sel[3:0] 4'0011
6178       attribute \src "libresoc.v:0.0-0.0"
6179       case 6'101001
6180         assign { } { }
6181         assign $1\in2_sel[3:0] 4'0011
6182       attribute \src "libresoc.v:0.0-0.0"
6183       case 6'100000
6184         assign { } { }
6185         assign $1\in2_sel[3:0] 4'0011
6186       attribute \src "libresoc.v:0.0-0.0"
6187       case 6'100001
6188         assign { } { }
6189         assign $1\in2_sel[3:0] 4'0011
6190       attribute \src "libresoc.v:0.0-0.0"
6191       case 6'000111
6192         assign { } { }
6193         assign $1\in2_sel[3:0] 4'0011
6194       attribute \src "libresoc.v:0.0-0.0"
6195       case 6'011000
6196         assign { } { }
6197         assign $1\in2_sel[3:0] 4'0010
6198       attribute \src "libresoc.v:0.0-0.0"
6199       case 6'011001
6200         assign { } { }
6201         assign $1\in2_sel[3:0] 4'0100
6202       attribute \src "libresoc.v:0.0-0.0"
6203       case 6'010100
6204         assign { } { }
6205         assign $1\in2_sel[3:0] 4'1011
6206       attribute \src "libresoc.v:0.0-0.0"
6207       case 6'010101
6208         assign { } { }
6209         assign $1\in2_sel[3:0] 4'1011
6210       attribute \src "libresoc.v:0.0-0.0"
6211       case 6'010111
6212         assign { } { }
6213         assign $1\in2_sel[3:0] 4'0001
6214       attribute \src "libresoc.v:0.0-0.0"
6215       case 6'100110
6216         assign { } { }
6217         assign $1\in2_sel[3:0] 4'0011
6218       attribute \src "libresoc.v:0.0-0.0"
6219       case 6'100111
6220         assign { } { }
6221         assign $1\in2_sel[3:0] 4'0011
6222       attribute \src "libresoc.v:0.0-0.0"
6223       case 6'101100
6224         assign { } { }
6225         assign $1\in2_sel[3:0] 4'0011
6226       attribute \src "libresoc.v:0.0-0.0"
6227       case 6'101101
6228         assign { } { }
6229         assign $1\in2_sel[3:0] 4'0011
6230       attribute \src "libresoc.v:0.0-0.0"
6231       case 6'100100
6232         assign { } { }
6233         assign $1\in2_sel[3:0] 4'0011
6234       attribute \src "libresoc.v:0.0-0.0"
6235       case 6'100101
6236         assign { } { }
6237         assign $1\in2_sel[3:0] 4'0011
6238       attribute \src "libresoc.v:0.0-0.0"
6239       case 6'001000
6240         assign { } { }
6241         assign $1\in2_sel[3:0] 4'0011
6242       attribute \src "libresoc.v:0.0-0.0"
6243       case 6'000010
6244         assign { } { }
6245         assign $1\in2_sel[3:0] 4'0011
6246       attribute \src "libresoc.v:0.0-0.0"
6247       case 6'000011
6248         assign { } { }
6249         assign $1\in2_sel[3:0] 4'0011
6250       attribute \src "libresoc.v:0.0-0.0"
6251       case 6'011010
6252         assign { } { }
6253         assign $1\in2_sel[3:0] 4'0010
6254       attribute \src "libresoc.v:0.0-0.0"
6255       case 6'011011
6256         assign { } { }
6257         assign $1\in2_sel[3:0] 4'0100
6258       case
6259         assign $1\in2_sel[3:0] 4'0000
6260     end
6261     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6262     switch \opcode_switch$1
6263       attribute \src "libresoc.v:0.0-0.0"
6264       case 32'000000---------------0100000000-
6265         assign { } { }
6266         assign $2\in2_sel[3:0] 4'0000
6267       attribute \src "libresoc.v:0.0-0.0"
6268       case 1610612736
6269         assign { } { }
6270         assign $2\in2_sel[3:0] 4'0000
6271       attribute \src "libresoc.v:0.0-0.0"
6272       case 32'000001---------------0000000011-
6273         assign { } { }
6274         assign $2\in2_sel[3:0] 4'0000
6275       case
6276         assign $2\in2_sel[3:0] $1\in2_sel[3:0]
6277     end
6278     sync always
6279       update \in2_sel $0\in2_sel[3:0]
6280   end
6281   attribute \src "libresoc.v:3808.3-3949.6"
6282   process $proc$libresoc.v:3808$241
6283     assign { } { }
6284     assign { } { }
6285     assign { } { }
6286     assign $0\in3_sel[1:0] $2\in3_sel[1:0]
6287     attribute \src "libresoc.v:3809.5-3809.29"
6288     switch \initial
6289       attribute \src "libresoc.v:3809.9-3809.17"
6290       case 1'1
6291       case
6292     end
6293     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6294     switch \opcode_switch
6295       attribute \src "libresoc.v:0.0-0.0"
6296       case 6'010011
6297         assign { } { }
6298         assign $1\in3_sel[1:0] \dec19_dec19_in3_sel
6299       attribute \src "libresoc.v:0.0-0.0"
6300       case 6'011110
6301         assign { } { }
6302         assign $1\in3_sel[1:0] \dec30_dec30_in3_sel
6303       attribute \src "libresoc.v:0.0-0.0"
6304       case 6'011111
6305         assign { } { }
6306         assign $1\in3_sel[1:0] \dec31_dec31_in3_sel
6307       attribute \src "libresoc.v:0.0-0.0"
6308       case 6'111010
6309         assign { } { }
6310         assign $1\in3_sel[1:0] \dec58_dec58_in3_sel
6311       attribute \src "libresoc.v:0.0-0.0"
6312       case 6'111110
6313         assign { } { }
6314         assign $1\in3_sel[1:0] \dec62_dec62_in3_sel
6315       attribute \src "libresoc.v:0.0-0.0"
6316       case 6'001100
6317         assign { } { }
6318         assign $1\in3_sel[1:0] 2'00
6319       attribute \src "libresoc.v:0.0-0.0"
6320       case 6'001101
6321         assign { } { }
6322         assign $1\in3_sel[1:0] 2'00
6323       attribute \src "libresoc.v:0.0-0.0"
6324       case 6'001110
6325         assign { } { }
6326         assign $1\in3_sel[1:0] 2'00
6327       attribute \src "libresoc.v:0.0-0.0"
6328       case 6'001111
6329         assign { } { }
6330         assign $1\in3_sel[1:0] 2'00
6331       attribute \src "libresoc.v:0.0-0.0"
6332       case 6'010001
6333         assign { } { }
6334         assign $1\in3_sel[1:0] 2'00
6335       attribute \src "libresoc.v:0.0-0.0"
6336       case 6'011100
6337         assign { } { }
6338         assign $1\in3_sel[1:0] 2'00
6339       attribute \src "libresoc.v:0.0-0.0"
6340       case 6'011101
6341         assign { } { }
6342         assign $1\in3_sel[1:0] 2'00
6343       attribute \src "libresoc.v:0.0-0.0"
6344       case 6'010010
6345         assign { } { }
6346         assign $1\in3_sel[1:0] 2'00
6347       attribute \src "libresoc.v:0.0-0.0"
6348       case 6'010000
6349         assign { } { }
6350         assign $1\in3_sel[1:0] 2'00
6351       attribute \src "libresoc.v:0.0-0.0"
6352       case 6'001011
6353         assign { } { }
6354         assign $1\in3_sel[1:0] 2'00
6355       attribute \src "libresoc.v:0.0-0.0"
6356       case 6'001010
6357         assign { } { }
6358         assign $1\in3_sel[1:0] 2'00
6359       attribute \src "libresoc.v:0.0-0.0"
6360       case 6'100010
6361         assign { } { }
6362         assign $1\in3_sel[1:0] 2'00
6363       attribute \src "libresoc.v:0.0-0.0"
6364       case 6'100011
6365         assign { } { }
6366         assign $1\in3_sel[1:0] 2'00
6367       attribute \src "libresoc.v:0.0-0.0"
6368       case 6'101010
6369         assign { } { }
6370         assign $1\in3_sel[1:0] 2'00
6371       attribute \src "libresoc.v:0.0-0.0"
6372       case 6'101011
6373         assign { } { }
6374         assign $1\in3_sel[1:0] 2'00
6375       attribute \src "libresoc.v:0.0-0.0"
6376       case 6'101000
6377         assign { } { }
6378         assign $1\in3_sel[1:0] 2'00
6379       attribute \src "libresoc.v:0.0-0.0"
6380       case 6'101001
6381         assign { } { }
6382         assign $1\in3_sel[1:0] 2'00
6383       attribute \src "libresoc.v:0.0-0.0"
6384       case 6'100000
6385         assign { } { }
6386         assign $1\in3_sel[1:0] 2'00
6387       attribute \src "libresoc.v:0.0-0.0"
6388       case 6'100001
6389         assign { } { }
6390         assign $1\in3_sel[1:0] 2'00
6391       attribute \src "libresoc.v:0.0-0.0"
6392       case 6'000111
6393         assign { } { }
6394         assign $1\in3_sel[1:0] 2'00
6395       attribute \src "libresoc.v:0.0-0.0"
6396       case 6'011000
6397         assign { } { }
6398         assign $1\in3_sel[1:0] 2'00
6399       attribute \src "libresoc.v:0.0-0.0"
6400       case 6'011001
6401         assign { } { }
6402         assign $1\in3_sel[1:0] 2'00
6403       attribute \src "libresoc.v:0.0-0.0"
6404       case 6'010100
6405         assign { } { }
6406         assign $1\in3_sel[1:0] 2'01
6407       attribute \src "libresoc.v:0.0-0.0"
6408       case 6'010101
6409         assign { } { }
6410         assign $1\in3_sel[1:0] 2'01
6411       attribute \src "libresoc.v:0.0-0.0"
6412       case 6'010111
6413         assign { } { }
6414         assign $1\in3_sel[1:0] 2'01
6415       attribute \src "libresoc.v:0.0-0.0"
6416       case 6'100110
6417         assign { } { }
6418         assign $1\in3_sel[1:0] 2'01
6419       attribute \src "libresoc.v:0.0-0.0"
6420       case 6'100111
6421         assign { } { }
6422         assign $1\in3_sel[1:0] 2'01
6423       attribute \src "libresoc.v:0.0-0.0"
6424       case 6'101100
6425         assign { } { }
6426         assign $1\in3_sel[1:0] 2'01
6427       attribute \src "libresoc.v:0.0-0.0"
6428       case 6'101101
6429         assign { } { }
6430         assign $1\in3_sel[1:0] 2'01
6431       attribute \src "libresoc.v:0.0-0.0"
6432       case 6'100100
6433         assign { } { }
6434         assign $1\in3_sel[1:0] 2'01
6435       attribute \src "libresoc.v:0.0-0.0"
6436       case 6'100101
6437         assign { } { }
6438         assign $1\in3_sel[1:0] 2'01
6439       attribute \src "libresoc.v:0.0-0.0"
6440       case 6'001000
6441         assign { } { }
6442         assign $1\in3_sel[1:0] 2'00
6443       attribute \src "libresoc.v:0.0-0.0"
6444       case 6'000010
6445         assign { } { }
6446         assign $1\in3_sel[1:0] 2'00
6447       attribute \src "libresoc.v:0.0-0.0"
6448       case 6'000011
6449         assign { } { }
6450         assign $1\in3_sel[1:0] 2'00
6451       attribute \src "libresoc.v:0.0-0.0"
6452       case 6'011010
6453         assign { } { }
6454         assign $1\in3_sel[1:0] 2'00
6455       attribute \src "libresoc.v:0.0-0.0"
6456       case 6'011011
6457         assign { } { }
6458         assign $1\in3_sel[1:0] 2'00
6459       case
6460         assign $1\in3_sel[1:0] 2'00
6461     end
6462     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6463     switch \opcode_switch$1
6464       attribute \src "libresoc.v:0.0-0.0"
6465       case 32'000000---------------0100000000-
6466         assign { } { }
6467         assign $2\in3_sel[1:0] 2'00
6468       attribute \src "libresoc.v:0.0-0.0"
6469       case 1610612736
6470         assign { } { }
6471         assign $2\in3_sel[1:0] 2'00
6472       attribute \src "libresoc.v:0.0-0.0"
6473       case 32'000001---------------0000000011-
6474         assign { } { }
6475         assign $2\in3_sel[1:0] 2'00
6476       case
6477         assign $2\in3_sel[1:0] $1\in3_sel[1:0]
6478     end
6479     sync always
6480       update \in3_sel $0\in3_sel[1:0]
6481   end
6482   attribute \src "libresoc.v:3950.3-4091.6"
6483   process $proc$libresoc.v:3950$242
6484     assign { } { }
6485     assign { } { }
6486     assign { } { }
6487     assign $0\out_sel[1:0] $2\out_sel[1:0]
6488     attribute \src "libresoc.v:3951.5-3951.29"
6489     switch \initial
6490       attribute \src "libresoc.v:3951.9-3951.17"
6491       case 1'1
6492       case
6493     end
6494     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6495     switch \opcode_switch
6496       attribute \src "libresoc.v:0.0-0.0"
6497       case 6'010011
6498         assign { } { }
6499         assign $1\out_sel[1:0] \dec19_dec19_out_sel
6500       attribute \src "libresoc.v:0.0-0.0"
6501       case 6'011110
6502         assign { } { }
6503         assign $1\out_sel[1:0] \dec30_dec30_out_sel
6504       attribute \src "libresoc.v:0.0-0.0"
6505       case 6'011111
6506         assign { } { }
6507         assign $1\out_sel[1:0] \dec31_dec31_out_sel
6508       attribute \src "libresoc.v:0.0-0.0"
6509       case 6'111010
6510         assign { } { }
6511         assign $1\out_sel[1:0] \dec58_dec58_out_sel
6512       attribute \src "libresoc.v:0.0-0.0"
6513       case 6'111110
6514         assign { } { }
6515         assign $1\out_sel[1:0] \dec62_dec62_out_sel
6516       attribute \src "libresoc.v:0.0-0.0"
6517       case 6'001100
6518         assign { } { }
6519         assign $1\out_sel[1:0] 2'01
6520       attribute \src "libresoc.v:0.0-0.0"
6521       case 6'001101
6522         assign { } { }
6523         assign $1\out_sel[1:0] 2'01
6524       attribute \src "libresoc.v:0.0-0.0"
6525       case 6'001110
6526         assign { } { }
6527         assign $1\out_sel[1:0] 2'01
6528       attribute \src "libresoc.v:0.0-0.0"
6529       case 6'001111
6530         assign { } { }
6531         assign $1\out_sel[1:0] 2'01
6532       attribute \src "libresoc.v:0.0-0.0"
6533       case 6'010001
6534         assign { } { }
6535         assign $1\out_sel[1:0] 2'00
6536       attribute \src "libresoc.v:0.0-0.0"
6537       case 6'011100
6538         assign { } { }
6539         assign $1\out_sel[1:0] 2'10
6540       attribute \src "libresoc.v:0.0-0.0"
6541       case 6'011101
6542         assign { } { }
6543         assign $1\out_sel[1:0] 2'10
6544       attribute \src "libresoc.v:0.0-0.0"
6545       case 6'010010
6546         assign { } { }
6547         assign $1\out_sel[1:0] 2'00
6548       attribute \src "libresoc.v:0.0-0.0"
6549       case 6'010000
6550         assign { } { }
6551         assign $1\out_sel[1:0] 2'11
6552       attribute \src "libresoc.v:0.0-0.0"
6553       case 6'001011
6554         assign { } { }
6555         assign $1\out_sel[1:0] 2'00
6556       attribute \src "libresoc.v:0.0-0.0"
6557       case 6'001010
6558         assign { } { }
6559         assign $1\out_sel[1:0] 2'00
6560       attribute \src "libresoc.v:0.0-0.0"
6561       case 6'100010
6562         assign { } { }
6563         assign $1\out_sel[1:0] 2'01
6564       attribute \src "libresoc.v:0.0-0.0"
6565       case 6'100011
6566         assign { } { }
6567         assign $1\out_sel[1:0] 2'01
6568       attribute \src "libresoc.v:0.0-0.0"
6569       case 6'101010
6570         assign { } { }
6571         assign $1\out_sel[1:0] 2'01
6572       attribute \src "libresoc.v:0.0-0.0"
6573       case 6'101011
6574         assign { } { }
6575         assign $1\out_sel[1:0] 2'01
6576       attribute \src "libresoc.v:0.0-0.0"
6577       case 6'101000
6578         assign { } { }
6579         assign $1\out_sel[1:0] 2'01
6580       attribute \src "libresoc.v:0.0-0.0"
6581       case 6'101001
6582         assign { } { }
6583         assign $1\out_sel[1:0] 2'01
6584       attribute \src "libresoc.v:0.0-0.0"
6585       case 6'100000
6586         assign { } { }
6587         assign $1\out_sel[1:0] 2'01
6588       attribute \src "libresoc.v:0.0-0.0"
6589       case 6'100001
6590         assign { } { }
6591         assign $1\out_sel[1:0] 2'01
6592       attribute \src "libresoc.v:0.0-0.0"
6593       case 6'000111
6594         assign { } { }
6595         assign $1\out_sel[1:0] 2'01
6596       attribute \src "libresoc.v:0.0-0.0"
6597       case 6'011000
6598         assign { } { }
6599         assign $1\out_sel[1:0] 2'10
6600       attribute \src "libresoc.v:0.0-0.0"
6601       case 6'011001
6602         assign { } { }
6603         assign $1\out_sel[1:0] 2'10
6604       attribute \src "libresoc.v:0.0-0.0"
6605       case 6'010100
6606         assign { } { }
6607         assign $1\out_sel[1:0] 2'10
6608       attribute \src "libresoc.v:0.0-0.0"
6609       case 6'010101
6610         assign { } { }
6611         assign $1\out_sel[1:0] 2'10
6612       attribute \src "libresoc.v:0.0-0.0"
6613       case 6'010111
6614         assign { } { }
6615         assign $1\out_sel[1:0] 2'10
6616       attribute \src "libresoc.v:0.0-0.0"
6617       case 6'100110
6618         assign { } { }
6619         assign $1\out_sel[1:0] 2'00
6620       attribute \src "libresoc.v:0.0-0.0"
6621       case 6'100111
6622         assign { } { }
6623         assign $1\out_sel[1:0] 2'00
6624       attribute \src "libresoc.v:0.0-0.0"
6625       case 6'101100
6626         assign { } { }
6627         assign $1\out_sel[1:0] 2'00
6628       attribute \src "libresoc.v:0.0-0.0"
6629       case 6'101101
6630         assign { } { }
6631         assign $1\out_sel[1:0] 2'00
6632       attribute \src "libresoc.v:0.0-0.0"
6633       case 6'100100
6634         assign { } { }
6635         assign $1\out_sel[1:0] 2'00
6636       attribute \src "libresoc.v:0.0-0.0"
6637       case 6'100101
6638         assign { } { }
6639         assign $1\out_sel[1:0] 2'00
6640       attribute \src "libresoc.v:0.0-0.0"
6641       case 6'001000
6642         assign { } { }
6643         assign $1\out_sel[1:0] 2'01
6644       attribute \src "libresoc.v:0.0-0.0"
6645       case 6'000010
6646         assign { } { }
6647         assign $1\out_sel[1:0] 2'00
6648       attribute \src "libresoc.v:0.0-0.0"
6649       case 6'000011
6650         assign { } { }
6651         assign $1\out_sel[1:0] 2'00
6652       attribute \src "libresoc.v:0.0-0.0"
6653       case 6'011010
6654         assign { } { }
6655         assign $1\out_sel[1:0] 2'10
6656       attribute \src "libresoc.v:0.0-0.0"
6657       case 6'011011
6658         assign { } { }
6659         assign $1\out_sel[1:0] 2'10
6660       case
6661         assign $1\out_sel[1:0] 2'00
6662     end
6663     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6664     switch \opcode_switch$1
6665       attribute \src "libresoc.v:0.0-0.0"
6666       case 32'000000---------------0100000000-
6667         assign { } { }
6668         assign $2\out_sel[1:0] 2'00
6669       attribute \src "libresoc.v:0.0-0.0"
6670       case 1610612736
6671         assign { } { }
6672         assign $2\out_sel[1:0] 2'00
6673       attribute \src "libresoc.v:0.0-0.0"
6674       case 32'000001---------------0000000011-
6675         assign { } { }
6676         assign $2\out_sel[1:0] 2'01
6677       case
6678         assign $2\out_sel[1:0] $1\out_sel[1:0]
6679     end
6680     sync always
6681       update \out_sel $0\out_sel[1:0]
6682   end
6683   attribute \src "libresoc.v:4092.3-4233.6"
6684   process $proc$libresoc.v:4092$243
6685     assign { } { }
6686     assign { } { }
6687     assign { } { }
6688     assign $0\cr_in[2:0] $2\cr_in[2:0]
6689     attribute \src "libresoc.v:4093.5-4093.29"
6690     switch \initial
6691       attribute \src "libresoc.v:4093.9-4093.17"
6692       case 1'1
6693       case
6694     end
6695     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6696     switch \opcode_switch
6697       attribute \src "libresoc.v:0.0-0.0"
6698       case 6'010011
6699         assign { } { }
6700         assign $1\cr_in[2:0] \dec19_dec19_cr_in
6701       attribute \src "libresoc.v:0.0-0.0"
6702       case 6'011110
6703         assign { } { }
6704         assign $1\cr_in[2:0] \dec30_dec30_cr_in
6705       attribute \src "libresoc.v:0.0-0.0"
6706       case 6'011111
6707         assign { } { }
6708         assign $1\cr_in[2:0] \dec31_dec31_cr_in
6709       attribute \src "libresoc.v:0.0-0.0"
6710       case 6'111010
6711         assign { } { }
6712         assign $1\cr_in[2:0] \dec58_dec58_cr_in
6713       attribute \src "libresoc.v:0.0-0.0"
6714       case 6'111110
6715         assign { } { }
6716         assign $1\cr_in[2:0] \dec62_dec62_cr_in
6717       attribute \src "libresoc.v:0.0-0.0"
6718       case 6'001100
6719         assign { } { }
6720         assign $1\cr_in[2:0] 3'000
6721       attribute \src "libresoc.v:0.0-0.0"
6722       case 6'001101
6723         assign { } { }
6724         assign $1\cr_in[2:0] 3'000
6725       attribute \src "libresoc.v:0.0-0.0"
6726       case 6'001110
6727         assign { } { }
6728         assign $1\cr_in[2:0] 3'000
6729       attribute \src "libresoc.v:0.0-0.0"
6730       case 6'001111
6731         assign { } { }
6732         assign $1\cr_in[2:0] 3'000
6733       attribute \src "libresoc.v:0.0-0.0"
6734       case 6'010001
6735         assign { } { }
6736         assign $1\cr_in[2:0] 3'000
6737       attribute \src "libresoc.v:0.0-0.0"
6738       case 6'011100
6739         assign { } { }
6740         assign $1\cr_in[2:0] 3'000
6741       attribute \src "libresoc.v:0.0-0.0"
6742       case 6'011101
6743         assign { } { }
6744         assign $1\cr_in[2:0] 3'000
6745       attribute \src "libresoc.v:0.0-0.0"
6746       case 6'010010
6747         assign { } { }
6748         assign $1\cr_in[2:0] 3'000
6749       attribute \src "libresoc.v:0.0-0.0"
6750       case 6'010000
6751         assign { } { }
6752         assign $1\cr_in[2:0] 3'010
6753       attribute \src "libresoc.v:0.0-0.0"
6754       case 6'001011
6755         assign { } { }
6756         assign $1\cr_in[2:0] 3'000
6757       attribute \src "libresoc.v:0.0-0.0"
6758       case 6'001010
6759         assign { } { }
6760         assign $1\cr_in[2:0] 3'000
6761       attribute \src "libresoc.v:0.0-0.0"
6762       case 6'100010
6763         assign { } { }
6764         assign $1\cr_in[2:0] 3'000
6765       attribute \src "libresoc.v:0.0-0.0"
6766       case 6'100011
6767         assign { } { }
6768         assign $1\cr_in[2:0] 3'000
6769       attribute \src "libresoc.v:0.0-0.0"
6770       case 6'101010
6771         assign { } { }
6772         assign $1\cr_in[2:0] 3'000
6773       attribute \src "libresoc.v:0.0-0.0"
6774       case 6'101011
6775         assign { } { }
6776         assign $1\cr_in[2:0] 3'000
6777       attribute \src "libresoc.v:0.0-0.0"
6778       case 6'101000
6779         assign { } { }
6780         assign $1\cr_in[2:0] 3'000
6781       attribute \src "libresoc.v:0.0-0.0"
6782       case 6'101001
6783         assign { } { }
6784         assign $1\cr_in[2:0] 3'000
6785       attribute \src "libresoc.v:0.0-0.0"
6786       case 6'100000
6787         assign { } { }
6788         assign $1\cr_in[2:0] 3'000
6789       attribute \src "libresoc.v:0.0-0.0"
6790       case 6'100001
6791         assign { } { }
6792         assign $1\cr_in[2:0] 3'000
6793       attribute \src "libresoc.v:0.0-0.0"
6794       case 6'000111
6795         assign { } { }
6796         assign $1\cr_in[2:0] 3'000
6797       attribute \src "libresoc.v:0.0-0.0"
6798       case 6'011000
6799         assign { } { }
6800         assign $1\cr_in[2:0] 3'000
6801       attribute \src "libresoc.v:0.0-0.0"
6802       case 6'011001
6803         assign { } { }
6804         assign $1\cr_in[2:0] 3'000
6805       attribute \src "libresoc.v:0.0-0.0"
6806       case 6'010100
6807         assign { } { }
6808         assign $1\cr_in[2:0] 3'000
6809       attribute \src "libresoc.v:0.0-0.0"
6810       case 6'010101
6811         assign { } { }
6812         assign $1\cr_in[2:0] 3'000
6813       attribute \src "libresoc.v:0.0-0.0"
6814       case 6'010111
6815         assign { } { }
6816         assign $1\cr_in[2:0] 3'000
6817       attribute \src "libresoc.v:0.0-0.0"
6818       case 6'100110
6819         assign { } { }
6820         assign $1\cr_in[2:0] 3'000
6821       attribute \src "libresoc.v:0.0-0.0"
6822       case 6'100111
6823         assign { } { }
6824         assign $1\cr_in[2:0] 3'000
6825       attribute \src "libresoc.v:0.0-0.0"
6826       case 6'101100
6827         assign { } { }
6828         assign $1\cr_in[2:0] 3'000
6829       attribute \src "libresoc.v:0.0-0.0"
6830       case 6'101101
6831         assign { } { }
6832         assign $1\cr_in[2:0] 3'000
6833       attribute \src "libresoc.v:0.0-0.0"
6834       case 6'100100
6835         assign { } { }
6836         assign $1\cr_in[2:0] 3'000
6837       attribute \src "libresoc.v:0.0-0.0"
6838       case 6'100101
6839         assign { } { }
6840         assign $1\cr_in[2:0] 3'000
6841       attribute \src "libresoc.v:0.0-0.0"
6842       case 6'001000
6843         assign { } { }
6844         assign $1\cr_in[2:0] 3'000
6845       attribute \src "libresoc.v:0.0-0.0"
6846       case 6'000010
6847         assign { } { }
6848         assign $1\cr_in[2:0] 3'000
6849       attribute \src "libresoc.v:0.0-0.0"
6850       case 6'000011
6851         assign { } { }
6852         assign $1\cr_in[2:0] 3'000
6853       attribute \src "libresoc.v:0.0-0.0"
6854       case 6'011010
6855         assign { } { }
6856         assign $1\cr_in[2:0] 3'000
6857       attribute \src "libresoc.v:0.0-0.0"
6858       case 6'011011
6859         assign { } { }
6860         assign $1\cr_in[2:0] 3'000
6861       case
6862         assign $1\cr_in[2:0] 3'000
6863     end
6864     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6865     switch \opcode_switch$1
6866       attribute \src "libresoc.v:0.0-0.0"
6867       case 32'000000---------------0100000000-
6868         assign { } { }
6869         assign $2\cr_in[2:0] 3'000
6870       attribute \src "libresoc.v:0.0-0.0"
6871       case 1610612736
6872         assign { } { }
6873         assign $2\cr_in[2:0] 3'000
6874       attribute \src "libresoc.v:0.0-0.0"
6875       case 32'000001---------------0000000011-
6876         assign { } { }
6877         assign $2\cr_in[2:0] 3'000
6878       case
6879         assign $2\cr_in[2:0] $1\cr_in[2:0]
6880     end
6881     sync always
6882       update \cr_in $0\cr_in[2:0]
6883   end
6884   attribute \src "libresoc.v:4234.3-4375.6"
6885   process $proc$libresoc.v:4234$244
6886     assign { } { }
6887     assign { } { }
6888     assign { } { }
6889     assign $0\cr_out[2:0] $2\cr_out[2:0]
6890     attribute \src "libresoc.v:4235.5-4235.29"
6891     switch \initial
6892       attribute \src "libresoc.v:4235.9-4235.17"
6893       case 1'1
6894       case
6895     end
6896     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
6897     switch \opcode_switch
6898       attribute \src "libresoc.v:0.0-0.0"
6899       case 6'010011
6900         assign { } { }
6901         assign $1\cr_out[2:0] \dec19_dec19_cr_out
6902       attribute \src "libresoc.v:0.0-0.0"
6903       case 6'011110
6904         assign { } { }
6905         assign $1\cr_out[2:0] \dec30_dec30_cr_out
6906       attribute \src "libresoc.v:0.0-0.0"
6907       case 6'011111
6908         assign { } { }
6909         assign $1\cr_out[2:0] \dec31_dec31_cr_out
6910       attribute \src "libresoc.v:0.0-0.0"
6911       case 6'111010
6912         assign { } { }
6913         assign $1\cr_out[2:0] \dec58_dec58_cr_out
6914       attribute \src "libresoc.v:0.0-0.0"
6915       case 6'111110
6916         assign { } { }
6917         assign $1\cr_out[2:0] \dec62_dec62_cr_out
6918       attribute \src "libresoc.v:0.0-0.0"
6919       case 6'001100
6920         assign { } { }
6921         assign $1\cr_out[2:0] 3'000
6922       attribute \src "libresoc.v:0.0-0.0"
6923       case 6'001101
6924         assign { } { }
6925         assign $1\cr_out[2:0] 3'001
6926       attribute \src "libresoc.v:0.0-0.0"
6927       case 6'001110
6928         assign { } { }
6929         assign $1\cr_out[2:0] 3'000
6930       attribute \src "libresoc.v:0.0-0.0"
6931       case 6'001111
6932         assign { } { }
6933         assign $1\cr_out[2:0] 3'000
6934       attribute \src "libresoc.v:0.0-0.0"
6935       case 6'010001
6936         assign { } { }
6937         assign $1\cr_out[2:0] 3'000
6938       attribute \src "libresoc.v:0.0-0.0"
6939       case 6'011100
6940         assign { } { }
6941         assign $1\cr_out[2:0] 3'001
6942       attribute \src "libresoc.v:0.0-0.0"
6943       case 6'011101
6944         assign { } { }
6945         assign $1\cr_out[2:0] 3'001
6946       attribute \src "libresoc.v:0.0-0.0"
6947       case 6'010010
6948         assign { } { }
6949         assign $1\cr_out[2:0] 3'000
6950       attribute \src "libresoc.v:0.0-0.0"
6951       case 6'010000
6952         assign { } { }
6953         assign $1\cr_out[2:0] 3'000
6954       attribute \src "libresoc.v:0.0-0.0"
6955       case 6'001011
6956         assign { } { }
6957         assign $1\cr_out[2:0] 3'010
6958       attribute \src "libresoc.v:0.0-0.0"
6959       case 6'001010
6960         assign { } { }
6961         assign $1\cr_out[2:0] 3'010
6962       attribute \src "libresoc.v:0.0-0.0"
6963       case 6'100010
6964         assign { } { }
6965         assign $1\cr_out[2:0] 3'000
6966       attribute \src "libresoc.v:0.0-0.0"
6967       case 6'100011
6968         assign { } { }
6969         assign $1\cr_out[2:0] 3'000
6970       attribute \src "libresoc.v:0.0-0.0"
6971       case 6'101010
6972         assign { } { }
6973         assign $1\cr_out[2:0] 3'000
6974       attribute \src "libresoc.v:0.0-0.0"
6975       case 6'101011
6976         assign { } { }
6977         assign $1\cr_out[2:0] 3'000
6978       attribute \src "libresoc.v:0.0-0.0"
6979       case 6'101000
6980         assign { } { }
6981         assign $1\cr_out[2:0] 3'000
6982       attribute \src "libresoc.v:0.0-0.0"
6983       case 6'101001
6984         assign { } { }
6985         assign $1\cr_out[2:0] 3'000
6986       attribute \src "libresoc.v:0.0-0.0"
6987       case 6'100000
6988         assign { } { }
6989         assign $1\cr_out[2:0] 3'000
6990       attribute \src "libresoc.v:0.0-0.0"
6991       case 6'100001
6992         assign { } { }
6993         assign $1\cr_out[2:0] 3'000
6994       attribute \src "libresoc.v:0.0-0.0"
6995       case 6'000111
6996         assign { } { }
6997         assign $1\cr_out[2:0] 3'001
6998       attribute \src "libresoc.v:0.0-0.0"
6999       case 6'011000
7000         assign { } { }
7001         assign $1\cr_out[2:0] 3'000
7002       attribute \src "libresoc.v:0.0-0.0"
7003       case 6'011001
7004         assign { } { }
7005         assign $1\cr_out[2:0] 3'000
7006       attribute \src "libresoc.v:0.0-0.0"
7007       case 6'010100
7008         assign { } { }
7009         assign $1\cr_out[2:0] 3'001
7010       attribute \src "libresoc.v:0.0-0.0"
7011       case 6'010101
7012         assign { } { }
7013         assign $1\cr_out[2:0] 3'001
7014       attribute \src "libresoc.v:0.0-0.0"
7015       case 6'010111
7016         assign { } { }
7017         assign $1\cr_out[2:0] 3'001
7018       attribute \src "libresoc.v:0.0-0.0"
7019       case 6'100110
7020         assign { } { }
7021         assign $1\cr_out[2:0] 3'000
7022       attribute \src "libresoc.v:0.0-0.0"
7023       case 6'100111
7024         assign { } { }
7025         assign $1\cr_out[2:0] 3'000
7026       attribute \src "libresoc.v:0.0-0.0"
7027       case 6'101100
7028         assign { } { }
7029         assign $1\cr_out[2:0] 3'000
7030       attribute \src "libresoc.v:0.0-0.0"
7031       case 6'101101
7032         assign { } { }
7033         assign $1\cr_out[2:0] 3'000
7034       attribute \src "libresoc.v:0.0-0.0"
7035       case 6'100100
7036         assign { } { }
7037         assign $1\cr_out[2:0] 3'000
7038       attribute \src "libresoc.v:0.0-0.0"
7039       case 6'100101
7040         assign { } { }
7041         assign $1\cr_out[2:0] 3'000
7042       attribute \src "libresoc.v:0.0-0.0"
7043       case 6'001000
7044         assign { } { }
7045         assign $1\cr_out[2:0] 3'000
7046       attribute \src "libresoc.v:0.0-0.0"
7047       case 6'000010
7048         assign { } { }
7049         assign $1\cr_out[2:0] 3'000
7050       attribute \src "libresoc.v:0.0-0.0"
7051       case 6'000011
7052         assign { } { }
7053         assign $1\cr_out[2:0] 3'000
7054       attribute \src "libresoc.v:0.0-0.0"
7055       case 6'011010
7056         assign { } { }
7057         assign $1\cr_out[2:0] 3'000
7058       attribute \src "libresoc.v:0.0-0.0"
7059       case 6'011011
7060         assign { } { }
7061         assign $1\cr_out[2:0] 3'000
7062       case
7063         assign $1\cr_out[2:0] 3'000
7064     end
7065     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7066     switch \opcode_switch$1
7067       attribute \src "libresoc.v:0.0-0.0"
7068       case 32'000000---------------0100000000-
7069         assign { } { }
7070         assign $2\cr_out[2:0] 3'000
7071       attribute \src "libresoc.v:0.0-0.0"
7072       case 1610612736
7073         assign { } { }
7074         assign $2\cr_out[2:0] 3'000
7075       attribute \src "libresoc.v:0.0-0.0"
7076       case 32'000001---------------0000000011-
7077         assign { } { }
7078         assign $2\cr_out[2:0] 3'000
7079       case
7080         assign $2\cr_out[2:0] $1\cr_out[2:0]
7081     end
7082     sync always
7083       update \cr_out $0\cr_out[2:0]
7084   end
7085   attribute \src "libresoc.v:4376.3-4517.6"
7086   process $proc$libresoc.v:4376$245
7087     assign { } { }
7088     assign { } { }
7089     assign { } { }
7090     assign $0\ldst_len[3:0] $2\ldst_len[3:0]
7091     attribute \src "libresoc.v:4377.5-4377.29"
7092     switch \initial
7093       attribute \src "libresoc.v:4377.9-4377.17"
7094       case 1'1
7095       case
7096     end
7097     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7098     switch \opcode_switch
7099       attribute \src "libresoc.v:0.0-0.0"
7100       case 6'010011
7101         assign { } { }
7102         assign $1\ldst_len[3:0] \dec19_dec19_ldst_len
7103       attribute \src "libresoc.v:0.0-0.0"
7104       case 6'011110
7105         assign { } { }
7106         assign $1\ldst_len[3:0] \dec30_dec30_ldst_len
7107       attribute \src "libresoc.v:0.0-0.0"
7108       case 6'011111
7109         assign { } { }
7110         assign $1\ldst_len[3:0] \dec31_dec31_ldst_len
7111       attribute \src "libresoc.v:0.0-0.0"
7112       case 6'111010
7113         assign { } { }
7114         assign $1\ldst_len[3:0] \dec58_dec58_ldst_len
7115       attribute \src "libresoc.v:0.0-0.0"
7116       case 6'111110
7117         assign { } { }
7118         assign $1\ldst_len[3:0] \dec62_dec62_ldst_len
7119       attribute \src "libresoc.v:0.0-0.0"
7120       case 6'001100
7121         assign { } { }
7122         assign $1\ldst_len[3:0] 4'0000
7123       attribute \src "libresoc.v:0.0-0.0"
7124       case 6'001101
7125         assign { } { }
7126         assign $1\ldst_len[3:0] 4'0000
7127       attribute \src "libresoc.v:0.0-0.0"
7128       case 6'001110
7129         assign { } { }
7130         assign $1\ldst_len[3:0] 4'0000
7131       attribute \src "libresoc.v:0.0-0.0"
7132       case 6'001111
7133         assign { } { }
7134         assign $1\ldst_len[3:0] 4'0000
7135       attribute \src "libresoc.v:0.0-0.0"
7136       case 6'010001
7137         assign { } { }
7138         assign $1\ldst_len[3:0] 4'0000
7139       attribute \src "libresoc.v:0.0-0.0"
7140       case 6'011100
7141         assign { } { }
7142         assign $1\ldst_len[3:0] 4'0000
7143       attribute \src "libresoc.v:0.0-0.0"
7144       case 6'011101
7145         assign { } { }
7146         assign $1\ldst_len[3:0] 4'0000
7147       attribute \src "libresoc.v:0.0-0.0"
7148       case 6'010010
7149         assign { } { }
7150         assign $1\ldst_len[3:0] 4'0000
7151       attribute \src "libresoc.v:0.0-0.0"
7152       case 6'010000
7153         assign { } { }
7154         assign $1\ldst_len[3:0] 4'0000
7155       attribute \src "libresoc.v:0.0-0.0"
7156       case 6'001011
7157         assign { } { }
7158         assign $1\ldst_len[3:0] 4'0000
7159       attribute \src "libresoc.v:0.0-0.0"
7160       case 6'001010
7161         assign { } { }
7162         assign $1\ldst_len[3:0] 4'0000
7163       attribute \src "libresoc.v:0.0-0.0"
7164       case 6'100010
7165         assign { } { }
7166         assign $1\ldst_len[3:0] 4'0001
7167       attribute \src "libresoc.v:0.0-0.0"
7168       case 6'100011
7169         assign { } { }
7170         assign $1\ldst_len[3:0] 4'0001
7171       attribute \src "libresoc.v:0.0-0.0"
7172       case 6'101010
7173         assign { } { }
7174         assign $1\ldst_len[3:0] 4'0010
7175       attribute \src "libresoc.v:0.0-0.0"
7176       case 6'101011
7177         assign { } { }
7178         assign $1\ldst_len[3:0] 4'0010
7179       attribute \src "libresoc.v:0.0-0.0"
7180       case 6'101000
7181         assign { } { }
7182         assign $1\ldst_len[3:0] 4'0010
7183       attribute \src "libresoc.v:0.0-0.0"
7184       case 6'101001
7185         assign { } { }
7186         assign $1\ldst_len[3:0] 4'0010
7187       attribute \src "libresoc.v:0.0-0.0"
7188       case 6'100000
7189         assign { } { }
7190         assign $1\ldst_len[3:0] 4'0100
7191       attribute \src "libresoc.v:0.0-0.0"
7192       case 6'100001
7193         assign { } { }
7194         assign $1\ldst_len[3:0] 4'0100
7195       attribute \src "libresoc.v:0.0-0.0"
7196       case 6'000111
7197         assign { } { }
7198         assign $1\ldst_len[3:0] 4'0000
7199       attribute \src "libresoc.v:0.0-0.0"
7200       case 6'011000
7201         assign { } { }
7202         assign $1\ldst_len[3:0] 4'0000
7203       attribute \src "libresoc.v:0.0-0.0"
7204       case 6'011001
7205         assign { } { }
7206         assign $1\ldst_len[3:0] 4'0000
7207       attribute \src "libresoc.v:0.0-0.0"
7208       case 6'010100
7209         assign { } { }
7210         assign $1\ldst_len[3:0] 4'0000
7211       attribute \src "libresoc.v:0.0-0.0"
7212       case 6'010101
7213         assign { } { }
7214         assign $1\ldst_len[3:0] 4'0000
7215       attribute \src "libresoc.v:0.0-0.0"
7216       case 6'010111
7217         assign { } { }
7218         assign $1\ldst_len[3:0] 4'0000
7219       attribute \src "libresoc.v:0.0-0.0"
7220       case 6'100110
7221         assign { } { }
7222         assign $1\ldst_len[3:0] 4'0001
7223       attribute \src "libresoc.v:0.0-0.0"
7224       case 6'100111
7225         assign { } { }
7226         assign $1\ldst_len[3:0] 4'0001
7227       attribute \src "libresoc.v:0.0-0.0"
7228       case 6'101100
7229         assign { } { }
7230         assign $1\ldst_len[3:0] 4'0010
7231       attribute \src "libresoc.v:0.0-0.0"
7232       case 6'101101
7233         assign { } { }
7234         assign $1\ldst_len[3:0] 4'0010
7235       attribute \src "libresoc.v:0.0-0.0"
7236       case 6'100100
7237         assign { } { }
7238         assign $1\ldst_len[3:0] 4'0100
7239       attribute \src "libresoc.v:0.0-0.0"
7240       case 6'100101
7241         assign { } { }
7242         assign $1\ldst_len[3:0] 4'0100
7243       attribute \src "libresoc.v:0.0-0.0"
7244       case 6'001000
7245         assign { } { }
7246         assign $1\ldst_len[3:0] 4'0000
7247       attribute \src "libresoc.v:0.0-0.0"
7248       case 6'000010
7249         assign { } { }
7250         assign $1\ldst_len[3:0] 4'0000
7251       attribute \src "libresoc.v:0.0-0.0"
7252       case 6'000011
7253         assign { } { }
7254         assign $1\ldst_len[3:0] 4'0000
7255       attribute \src "libresoc.v:0.0-0.0"
7256       case 6'011010
7257         assign { } { }
7258         assign $1\ldst_len[3:0] 4'0000
7259       attribute \src "libresoc.v:0.0-0.0"
7260       case 6'011011
7261         assign { } { }
7262         assign $1\ldst_len[3:0] 4'0000
7263       case
7264         assign $1\ldst_len[3:0] 4'0000
7265     end
7266     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7267     switch \opcode_switch$1
7268       attribute \src "libresoc.v:0.0-0.0"
7269       case 32'000000---------------0100000000-
7270         assign { } { }
7271         assign $2\ldst_len[3:0] 4'0000
7272       attribute \src "libresoc.v:0.0-0.0"
7273       case 1610612736
7274         assign { } { }
7275         assign $2\ldst_len[3:0] 4'0000
7276       attribute \src "libresoc.v:0.0-0.0"
7277       case 32'000001---------------0000000011-
7278         assign { } { }
7279         assign $2\ldst_len[3:0] 4'0000
7280       case
7281         assign $2\ldst_len[3:0] $1\ldst_len[3:0]
7282     end
7283     sync always
7284       update \ldst_len $0\ldst_len[3:0]
7285   end
7286   attribute \src "libresoc.v:4518.3-4659.6"
7287   process $proc$libresoc.v:4518$246
7288     assign { } { }
7289     assign { } { }
7290     assign { } { }
7291     assign $0\upd[1:0] $2\upd[1:0]
7292     attribute \src "libresoc.v:4519.5-4519.29"
7293     switch \initial
7294       attribute \src "libresoc.v:4519.9-4519.17"
7295       case 1'1
7296       case
7297     end
7298     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7299     switch \opcode_switch
7300       attribute \src "libresoc.v:0.0-0.0"
7301       case 6'010011
7302         assign { } { }
7303         assign $1\upd[1:0] \dec19_dec19_upd
7304       attribute \src "libresoc.v:0.0-0.0"
7305       case 6'011110
7306         assign { } { }
7307         assign $1\upd[1:0] \dec30_dec30_upd
7308       attribute \src "libresoc.v:0.0-0.0"
7309       case 6'011111
7310         assign { } { }
7311         assign $1\upd[1:0] \dec31_dec31_upd
7312       attribute \src "libresoc.v:0.0-0.0"
7313       case 6'111010
7314         assign { } { }
7315         assign $1\upd[1:0] \dec58_dec58_upd
7316       attribute \src "libresoc.v:0.0-0.0"
7317       case 6'111110
7318         assign { } { }
7319         assign $1\upd[1:0] \dec62_dec62_upd
7320       attribute \src "libresoc.v:0.0-0.0"
7321       case 6'001100
7322         assign { } { }
7323         assign $1\upd[1:0] 2'00
7324       attribute \src "libresoc.v:0.0-0.0"
7325       case 6'001101
7326         assign { } { }
7327         assign $1\upd[1:0] 2'00
7328       attribute \src "libresoc.v:0.0-0.0"
7329       case 6'001110
7330         assign { } { }
7331         assign $1\upd[1:0] 2'00
7332       attribute \src "libresoc.v:0.0-0.0"
7333       case 6'001111
7334         assign { } { }
7335         assign $1\upd[1:0] 2'00
7336       attribute \src "libresoc.v:0.0-0.0"
7337       case 6'010001
7338         assign { } { }
7339         assign $1\upd[1:0] 2'00
7340       attribute \src "libresoc.v:0.0-0.0"
7341       case 6'011100
7342         assign { } { }
7343         assign $1\upd[1:0] 2'00
7344       attribute \src "libresoc.v:0.0-0.0"
7345       case 6'011101
7346         assign { } { }
7347         assign $1\upd[1:0] 2'00
7348       attribute \src "libresoc.v:0.0-0.0"
7349       case 6'010010
7350         assign { } { }
7351         assign $1\upd[1:0] 2'00
7352       attribute \src "libresoc.v:0.0-0.0"
7353       case 6'010000
7354         assign { } { }
7355         assign $1\upd[1:0] 2'00
7356       attribute \src "libresoc.v:0.0-0.0"
7357       case 6'001011
7358         assign { } { }
7359         assign $1\upd[1:0] 2'00
7360       attribute \src "libresoc.v:0.0-0.0"
7361       case 6'001010
7362         assign { } { }
7363         assign $1\upd[1:0] 2'00
7364       attribute \src "libresoc.v:0.0-0.0"
7365       case 6'100010
7366         assign { } { }
7367         assign $1\upd[1:0] 2'00
7368       attribute \src "libresoc.v:0.0-0.0"
7369       case 6'100011
7370         assign { } { }
7371         assign $1\upd[1:0] 2'01
7372       attribute \src "libresoc.v:0.0-0.0"
7373       case 6'101010
7374         assign { } { }
7375         assign $1\upd[1:0] 2'00
7376       attribute \src "libresoc.v:0.0-0.0"
7377       case 6'101011
7378         assign { } { }
7379         assign $1\upd[1:0] 2'01
7380       attribute \src "libresoc.v:0.0-0.0"
7381       case 6'101000
7382         assign { } { }
7383         assign $1\upd[1:0] 2'00
7384       attribute \src "libresoc.v:0.0-0.0"
7385       case 6'101001
7386         assign { } { }
7387         assign $1\upd[1:0] 2'01
7388       attribute \src "libresoc.v:0.0-0.0"
7389       case 6'100000
7390         assign { } { }
7391         assign $1\upd[1:0] 2'00
7392       attribute \src "libresoc.v:0.0-0.0"
7393       case 6'100001
7394         assign { } { }
7395         assign $1\upd[1:0] 2'01
7396       attribute \src "libresoc.v:0.0-0.0"
7397       case 6'000111
7398         assign { } { }
7399         assign $1\upd[1:0] 2'00
7400       attribute \src "libresoc.v:0.0-0.0"
7401       case 6'011000
7402         assign { } { }
7403         assign $1\upd[1:0] 2'00
7404       attribute \src "libresoc.v:0.0-0.0"
7405       case 6'011001
7406         assign { } { }
7407         assign $1\upd[1:0] 2'00
7408       attribute \src "libresoc.v:0.0-0.0"
7409       case 6'010100
7410         assign { } { }
7411         assign $1\upd[1:0] 2'00
7412       attribute \src "libresoc.v:0.0-0.0"
7413       case 6'010101
7414         assign { } { }
7415         assign $1\upd[1:0] 2'00
7416       attribute \src "libresoc.v:0.0-0.0"
7417       case 6'010111
7418         assign { } { }
7419         assign $1\upd[1:0] 2'00
7420       attribute \src "libresoc.v:0.0-0.0"
7421       case 6'100110
7422         assign { } { }
7423         assign $1\upd[1:0] 2'00
7424       attribute \src "libresoc.v:0.0-0.0"
7425       case 6'100111
7426         assign { } { }
7427         assign $1\upd[1:0] 2'01
7428       attribute \src "libresoc.v:0.0-0.0"
7429       case 6'101100
7430         assign { } { }
7431         assign $1\upd[1:0] 2'00
7432       attribute \src "libresoc.v:0.0-0.0"
7433       case 6'101101
7434         assign { } { }
7435         assign $1\upd[1:0] 2'01
7436       attribute \src "libresoc.v:0.0-0.0"
7437       case 6'100100
7438         assign { } { }
7439         assign $1\upd[1:0] 2'00
7440       attribute \src "libresoc.v:0.0-0.0"
7441       case 6'100101
7442         assign { } { }
7443         assign $1\upd[1:0] 2'01
7444       attribute \src "libresoc.v:0.0-0.0"
7445       case 6'001000
7446         assign { } { }
7447         assign $1\upd[1:0] 2'00
7448       attribute \src "libresoc.v:0.0-0.0"
7449       case 6'000010
7450         assign { } { }
7451         assign $1\upd[1:0] 2'00
7452       attribute \src "libresoc.v:0.0-0.0"
7453       case 6'000011
7454         assign { } { }
7455         assign $1\upd[1:0] 2'00
7456       attribute \src "libresoc.v:0.0-0.0"
7457       case 6'011010
7458         assign { } { }
7459         assign $1\upd[1:0] 2'00
7460       attribute \src "libresoc.v:0.0-0.0"
7461       case 6'011011
7462         assign { } { }
7463         assign $1\upd[1:0] 2'00
7464       case
7465         assign $1\upd[1:0] 2'00
7466     end
7467     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7468     switch \opcode_switch$1
7469       attribute \src "libresoc.v:0.0-0.0"
7470       case 32'000000---------------0100000000-
7471         assign { } { }
7472         assign $2\upd[1:0] 2'00
7473       attribute \src "libresoc.v:0.0-0.0"
7474       case 1610612736
7475         assign { } { }
7476         assign $2\upd[1:0] 2'00
7477       attribute \src "libresoc.v:0.0-0.0"
7478       case 32'000001---------------0000000011-
7479         assign { } { }
7480         assign $2\upd[1:0] 2'00
7481       case
7482         assign $2\upd[1:0] $1\upd[1:0]
7483     end
7484     sync always
7485       update \upd $0\upd[1:0]
7486   end
7487   attribute \src "libresoc.v:4660.3-4801.6"
7488   process $proc$libresoc.v:4660$247
7489     assign { } { }
7490     assign { } { }
7491     assign { } { }
7492     assign $0\rc_sel[1:0] $2\rc_sel[1:0]
7493     attribute \src "libresoc.v:4661.5-4661.29"
7494     switch \initial
7495       attribute \src "libresoc.v:4661.9-4661.17"
7496       case 1'1
7497       case
7498     end
7499     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7500     switch \opcode_switch
7501       attribute \src "libresoc.v:0.0-0.0"
7502       case 6'010011
7503         assign { } { }
7504         assign $1\rc_sel[1:0] \dec19_dec19_rc_sel
7505       attribute \src "libresoc.v:0.0-0.0"
7506       case 6'011110
7507         assign { } { }
7508         assign $1\rc_sel[1:0] \dec30_dec30_rc_sel
7509       attribute \src "libresoc.v:0.0-0.0"
7510       case 6'011111
7511         assign { } { }
7512         assign $1\rc_sel[1:0] \dec31_dec31_rc_sel
7513       attribute \src "libresoc.v:0.0-0.0"
7514       case 6'111010
7515         assign { } { }
7516         assign $1\rc_sel[1:0] \dec58_dec58_rc_sel
7517       attribute \src "libresoc.v:0.0-0.0"
7518       case 6'111110
7519         assign { } { }
7520         assign $1\rc_sel[1:0] \dec62_dec62_rc_sel
7521       attribute \src "libresoc.v:0.0-0.0"
7522       case 6'001100
7523         assign { } { }
7524         assign $1\rc_sel[1:0] 2'00
7525       attribute \src "libresoc.v:0.0-0.0"
7526       case 6'001101
7527         assign { } { }
7528         assign $1\rc_sel[1:0] 2'01
7529       attribute \src "libresoc.v:0.0-0.0"
7530       case 6'001110
7531         assign { } { }
7532         assign $1\rc_sel[1:0] 2'00
7533       attribute \src "libresoc.v:0.0-0.0"
7534       case 6'001111
7535         assign { } { }
7536         assign $1\rc_sel[1:0] 2'00
7537       attribute \src "libresoc.v:0.0-0.0"
7538       case 6'010001
7539         assign { } { }
7540         assign $1\rc_sel[1:0] 2'00
7541       attribute \src "libresoc.v:0.0-0.0"
7542       case 6'011100
7543         assign { } { }
7544         assign $1\rc_sel[1:0] 2'01
7545       attribute \src "libresoc.v:0.0-0.0"
7546       case 6'011101
7547         assign { } { }
7548         assign $1\rc_sel[1:0] 2'01
7549       attribute \src "libresoc.v:0.0-0.0"
7550       case 6'010010
7551         assign { } { }
7552         assign $1\rc_sel[1:0] 2'00
7553       attribute \src "libresoc.v:0.0-0.0"
7554       case 6'010000
7555         assign { } { }
7556         assign $1\rc_sel[1:0] 2'00
7557       attribute \src "libresoc.v:0.0-0.0"
7558       case 6'001011
7559         assign { } { }
7560         assign $1\rc_sel[1:0] 2'00
7561       attribute \src "libresoc.v:0.0-0.0"
7562       case 6'001010
7563         assign { } { }
7564         assign $1\rc_sel[1:0] 2'00
7565       attribute \src "libresoc.v:0.0-0.0"
7566       case 6'100010
7567         assign { } { }
7568         assign $1\rc_sel[1:0] 2'00
7569       attribute \src "libresoc.v:0.0-0.0"
7570       case 6'100011
7571         assign { } { }
7572         assign $1\rc_sel[1:0] 2'00
7573       attribute \src "libresoc.v:0.0-0.0"
7574       case 6'101010
7575         assign { } { }
7576         assign $1\rc_sel[1:0] 2'00
7577       attribute \src "libresoc.v:0.0-0.0"
7578       case 6'101011
7579         assign { } { }
7580         assign $1\rc_sel[1:0] 2'00
7581       attribute \src "libresoc.v:0.0-0.0"
7582       case 6'101000
7583         assign { } { }
7584         assign $1\rc_sel[1:0] 2'00
7585       attribute \src "libresoc.v:0.0-0.0"
7586       case 6'101001
7587         assign { } { }
7588         assign $1\rc_sel[1:0] 2'00
7589       attribute \src "libresoc.v:0.0-0.0"
7590       case 6'100000
7591         assign { } { }
7592         assign $1\rc_sel[1:0] 2'00
7593       attribute \src "libresoc.v:0.0-0.0"
7594       case 6'100001
7595         assign { } { }
7596         assign $1\rc_sel[1:0] 2'00
7597       attribute \src "libresoc.v:0.0-0.0"
7598       case 6'000111
7599         assign { } { }
7600         assign $1\rc_sel[1:0] 2'00
7601       attribute \src "libresoc.v:0.0-0.0"
7602       case 6'011000
7603         assign { } { }
7604         assign $1\rc_sel[1:0] 2'00
7605       attribute \src "libresoc.v:0.0-0.0"
7606       case 6'011001
7607         assign { } { }
7608         assign $1\rc_sel[1:0] 2'00
7609       attribute \src "libresoc.v:0.0-0.0"
7610       case 6'010100
7611         assign { } { }
7612         assign $1\rc_sel[1:0] 2'10
7613       attribute \src "libresoc.v:0.0-0.0"
7614       case 6'010101
7615         assign { } { }
7616         assign $1\rc_sel[1:0] 2'10
7617       attribute \src "libresoc.v:0.0-0.0"
7618       case 6'010111
7619         assign { } { }
7620         assign $1\rc_sel[1:0] 2'10
7621       attribute \src "libresoc.v:0.0-0.0"
7622       case 6'100110
7623         assign { } { }
7624         assign $1\rc_sel[1:0] 2'00
7625       attribute \src "libresoc.v:0.0-0.0"
7626       case 6'100111
7627         assign { } { }
7628         assign $1\rc_sel[1:0] 2'00
7629       attribute \src "libresoc.v:0.0-0.0"
7630       case 6'101100
7631         assign { } { }
7632         assign $1\rc_sel[1:0] 2'00
7633       attribute \src "libresoc.v:0.0-0.0"
7634       case 6'101101
7635         assign { } { }
7636         assign $1\rc_sel[1:0] 2'00
7637       attribute \src "libresoc.v:0.0-0.0"
7638       case 6'100100
7639         assign { } { }
7640         assign $1\rc_sel[1:0] 2'00
7641       attribute \src "libresoc.v:0.0-0.0"
7642       case 6'100101
7643         assign { } { }
7644         assign $1\rc_sel[1:0] 2'00
7645       attribute \src "libresoc.v:0.0-0.0"
7646       case 6'001000
7647         assign { } { }
7648         assign $1\rc_sel[1:0] 2'00
7649       attribute \src "libresoc.v:0.0-0.0"
7650       case 6'000010
7651         assign { } { }
7652         assign $1\rc_sel[1:0] 2'00
7653       attribute \src "libresoc.v:0.0-0.0"
7654       case 6'000011
7655         assign { } { }
7656         assign $1\rc_sel[1:0] 2'00
7657       attribute \src "libresoc.v:0.0-0.0"
7658       case 6'011010
7659         assign { } { }
7660         assign $1\rc_sel[1:0] 2'00
7661       attribute \src "libresoc.v:0.0-0.0"
7662       case 6'011011
7663         assign { } { }
7664         assign $1\rc_sel[1:0] 2'00
7665       case
7666         assign $1\rc_sel[1:0] 2'00
7667     end
7668     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7669     switch \opcode_switch$1
7670       attribute \src "libresoc.v:0.0-0.0"
7671       case 32'000000---------------0100000000-
7672         assign { } { }
7673         assign $2\rc_sel[1:0] 2'10
7674       attribute \src "libresoc.v:0.0-0.0"
7675       case 1610612736
7676         assign { } { }
7677         assign $2\rc_sel[1:0] 2'00
7678       attribute \src "libresoc.v:0.0-0.0"
7679       case 32'000001---------------0000000011-
7680         assign { } { }
7681         assign $2\rc_sel[1:0] 2'00
7682       case
7683         assign $2\rc_sel[1:0] $1\rc_sel[1:0]
7684     end
7685     sync always
7686       update \rc_sel $0\rc_sel[1:0]
7687   end
7688   attribute \src "libresoc.v:4802.3-4943.6"
7689   process $proc$libresoc.v:4802$248
7690     assign { } { }
7691     assign { } { }
7692     assign { } { }
7693     assign $0\cry_in[1:0] $2\cry_in[1:0]
7694     attribute \src "libresoc.v:4803.5-4803.29"
7695     switch \initial
7696       attribute \src "libresoc.v:4803.9-4803.17"
7697       case 1'1
7698       case
7699     end
7700     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7701     switch \opcode_switch
7702       attribute \src "libresoc.v:0.0-0.0"
7703       case 6'010011
7704         assign { } { }
7705         assign $1\cry_in[1:0] \dec19_dec19_cry_in
7706       attribute \src "libresoc.v:0.0-0.0"
7707       case 6'011110
7708         assign { } { }
7709         assign $1\cry_in[1:0] \dec30_dec30_cry_in
7710       attribute \src "libresoc.v:0.0-0.0"
7711       case 6'011111
7712         assign { } { }
7713         assign $1\cry_in[1:0] \dec31_dec31_cry_in
7714       attribute \src "libresoc.v:0.0-0.0"
7715       case 6'111010
7716         assign { } { }
7717         assign $1\cry_in[1:0] \dec58_dec58_cry_in
7718       attribute \src "libresoc.v:0.0-0.0"
7719       case 6'111110
7720         assign { } { }
7721         assign $1\cry_in[1:0] \dec62_dec62_cry_in
7722       attribute \src "libresoc.v:0.0-0.0"
7723       case 6'001100
7724         assign { } { }
7725         assign $1\cry_in[1:0] 2'00
7726       attribute \src "libresoc.v:0.0-0.0"
7727       case 6'001101
7728         assign { } { }
7729         assign $1\cry_in[1:0] 2'00
7730       attribute \src "libresoc.v:0.0-0.0"
7731       case 6'001110
7732         assign { } { }
7733         assign $1\cry_in[1:0] 2'00
7734       attribute \src "libresoc.v:0.0-0.0"
7735       case 6'001111
7736         assign { } { }
7737         assign $1\cry_in[1:0] 2'00
7738       attribute \src "libresoc.v:0.0-0.0"
7739       case 6'010001
7740         assign { } { }
7741         assign $1\cry_in[1:0] 2'00
7742       attribute \src "libresoc.v:0.0-0.0"
7743       case 6'011100
7744         assign { } { }
7745         assign $1\cry_in[1:0] 2'00
7746       attribute \src "libresoc.v:0.0-0.0"
7747       case 6'011101
7748         assign { } { }
7749         assign $1\cry_in[1:0] 2'00
7750       attribute \src "libresoc.v:0.0-0.0"
7751       case 6'010010
7752         assign { } { }
7753         assign $1\cry_in[1:0] 2'00
7754       attribute \src "libresoc.v:0.0-0.0"
7755       case 6'010000
7756         assign { } { }
7757         assign $1\cry_in[1:0] 2'00
7758       attribute \src "libresoc.v:0.0-0.0"
7759       case 6'001011
7760         assign { } { }
7761         assign $1\cry_in[1:0] 2'01
7762       attribute \src "libresoc.v:0.0-0.0"
7763       case 6'001010
7764         assign { } { }
7765         assign $1\cry_in[1:0] 2'01
7766       attribute \src "libresoc.v:0.0-0.0"
7767       case 6'100010
7768         assign { } { }
7769         assign $1\cry_in[1:0] 2'00
7770       attribute \src "libresoc.v:0.0-0.0"
7771       case 6'100011
7772         assign { } { }
7773         assign $1\cry_in[1:0] 2'00
7774       attribute \src "libresoc.v:0.0-0.0"
7775       case 6'101010
7776         assign { } { }
7777         assign $1\cry_in[1:0] 2'00
7778       attribute \src "libresoc.v:0.0-0.0"
7779       case 6'101011
7780         assign { } { }
7781         assign $1\cry_in[1:0] 2'00
7782       attribute \src "libresoc.v:0.0-0.0"
7783       case 6'101000
7784         assign { } { }
7785         assign $1\cry_in[1:0] 2'00
7786       attribute \src "libresoc.v:0.0-0.0"
7787       case 6'101001
7788         assign { } { }
7789         assign $1\cry_in[1:0] 2'00
7790       attribute \src "libresoc.v:0.0-0.0"
7791       case 6'100000
7792         assign { } { }
7793         assign $1\cry_in[1:0] 2'00
7794       attribute \src "libresoc.v:0.0-0.0"
7795       case 6'100001
7796         assign { } { }
7797         assign $1\cry_in[1:0] 2'00
7798       attribute \src "libresoc.v:0.0-0.0"
7799       case 6'000111
7800         assign { } { }
7801         assign $1\cry_in[1:0] 2'00
7802       attribute \src "libresoc.v:0.0-0.0"
7803       case 6'011000
7804         assign { } { }
7805         assign $1\cry_in[1:0] 2'00
7806       attribute \src "libresoc.v:0.0-0.0"
7807       case 6'011001
7808         assign { } { }
7809         assign $1\cry_in[1:0] 2'00
7810       attribute \src "libresoc.v:0.0-0.0"
7811       case 6'010100
7812         assign { } { }
7813         assign $1\cry_in[1:0] 2'00
7814       attribute \src "libresoc.v:0.0-0.0"
7815       case 6'010101
7816         assign { } { }
7817         assign $1\cry_in[1:0] 2'00
7818       attribute \src "libresoc.v:0.0-0.0"
7819       case 6'010111
7820         assign { } { }
7821         assign $1\cry_in[1:0] 2'00
7822       attribute \src "libresoc.v:0.0-0.0"
7823       case 6'100110
7824         assign { } { }
7825         assign $1\cry_in[1:0] 2'00
7826       attribute \src "libresoc.v:0.0-0.0"
7827       case 6'100111
7828         assign { } { }
7829         assign $1\cry_in[1:0] 2'00
7830       attribute \src "libresoc.v:0.0-0.0"
7831       case 6'101100
7832         assign { } { }
7833         assign $1\cry_in[1:0] 2'00
7834       attribute \src "libresoc.v:0.0-0.0"
7835       case 6'101101
7836         assign { } { }
7837         assign $1\cry_in[1:0] 2'00
7838       attribute \src "libresoc.v:0.0-0.0"
7839       case 6'100100
7840         assign { } { }
7841         assign $1\cry_in[1:0] 2'00
7842       attribute \src "libresoc.v:0.0-0.0"
7843       case 6'100101
7844         assign { } { }
7845         assign $1\cry_in[1:0] 2'00
7846       attribute \src "libresoc.v:0.0-0.0"
7847       case 6'001000
7848         assign { } { }
7849         assign $1\cry_in[1:0] 2'01
7850       attribute \src "libresoc.v:0.0-0.0"
7851       case 6'000010
7852         assign { } { }
7853         assign $1\cry_in[1:0] 2'00
7854       attribute \src "libresoc.v:0.0-0.0"
7855       case 6'000011
7856         assign { } { }
7857         assign $1\cry_in[1:0] 2'00
7858       attribute \src "libresoc.v:0.0-0.0"
7859       case 6'011010
7860         assign { } { }
7861         assign $1\cry_in[1:0] 2'00
7862       attribute \src "libresoc.v:0.0-0.0"
7863       case 6'011011
7864         assign { } { }
7865         assign $1\cry_in[1:0] 2'00
7866       case
7867         assign $1\cry_in[1:0] 2'00
7868     end
7869     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7870     switch \opcode_switch$1
7871       attribute \src "libresoc.v:0.0-0.0"
7872       case 32'000000---------------0100000000-
7873         assign { } { }
7874         assign $2\cry_in[1:0] 2'00
7875       attribute \src "libresoc.v:0.0-0.0"
7876       case 1610612736
7877         assign { } { }
7878         assign $2\cry_in[1:0] 2'00
7879       attribute \src "libresoc.v:0.0-0.0"
7880       case 32'000001---------------0000000011-
7881         assign { } { }
7882         assign $2\cry_in[1:0] 2'00
7883       case
7884         assign $2\cry_in[1:0] $1\cry_in[1:0]
7885     end
7886     sync always
7887       update \cry_in $0\cry_in[1:0]
7888   end
7889   attribute \src "libresoc.v:4944.3-5085.6"
7890   process $proc$libresoc.v:4944$249
7891     assign { } { }
7892     assign { } { }
7893     assign { } { }
7894     assign $0\inv_a[0:0] $2\inv_a[0:0]
7895     attribute \src "libresoc.v:4945.5-4945.29"
7896     switch \initial
7897       attribute \src "libresoc.v:4945.9-4945.17"
7898       case 1'1
7899       case
7900     end
7901     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
7902     switch \opcode_switch
7903       attribute \src "libresoc.v:0.0-0.0"
7904       case 6'010011
7905         assign { } { }
7906         assign $1\inv_a[0:0] \dec19_dec19_inv_a
7907       attribute \src "libresoc.v:0.0-0.0"
7908       case 6'011110
7909         assign { } { }
7910         assign $1\inv_a[0:0] \dec30_dec30_inv_a
7911       attribute \src "libresoc.v:0.0-0.0"
7912       case 6'011111
7913         assign { } { }
7914         assign $1\inv_a[0:0] \dec31_dec31_inv_a
7915       attribute \src "libresoc.v:0.0-0.0"
7916       case 6'111010
7917         assign { } { }
7918         assign $1\inv_a[0:0] \dec58_dec58_inv_a
7919       attribute \src "libresoc.v:0.0-0.0"
7920       case 6'111110
7921         assign { } { }
7922         assign $1\inv_a[0:0] \dec62_dec62_inv_a
7923       attribute \src "libresoc.v:0.0-0.0"
7924       case 6'001100
7925         assign { } { }
7926         assign $1\inv_a[0:0] 1'0
7927       attribute \src "libresoc.v:0.0-0.0"
7928       case 6'001101
7929         assign { } { }
7930         assign $1\inv_a[0:0] 1'0
7931       attribute \src "libresoc.v:0.0-0.0"
7932       case 6'001110
7933         assign { } { }
7934         assign $1\inv_a[0:0] 1'0
7935       attribute \src "libresoc.v:0.0-0.0"
7936       case 6'001111
7937         assign { } { }
7938         assign $1\inv_a[0:0] 1'0
7939       attribute \src "libresoc.v:0.0-0.0"
7940       case 6'010001
7941         assign { } { }
7942         assign $1\inv_a[0:0] 1'0
7943       attribute \src "libresoc.v:0.0-0.0"
7944       case 6'011100
7945         assign { } { }
7946         assign $1\inv_a[0:0] 1'0
7947       attribute \src "libresoc.v:0.0-0.0"
7948       case 6'011101
7949         assign { } { }
7950         assign $1\inv_a[0:0] 1'0
7951       attribute \src "libresoc.v:0.0-0.0"
7952       case 6'010010
7953         assign { } { }
7954         assign $1\inv_a[0:0] 1'0
7955       attribute \src "libresoc.v:0.0-0.0"
7956       case 6'010000
7957         assign { } { }
7958         assign $1\inv_a[0:0] 1'0
7959       attribute \src "libresoc.v:0.0-0.0"
7960       case 6'001011
7961         assign { } { }
7962         assign $1\inv_a[0:0] 1'1
7963       attribute \src "libresoc.v:0.0-0.0"
7964       case 6'001010
7965         assign { } { }
7966         assign $1\inv_a[0:0] 1'1
7967       attribute \src "libresoc.v:0.0-0.0"
7968       case 6'100010
7969         assign { } { }
7970         assign $1\inv_a[0:0] 1'0
7971       attribute \src "libresoc.v:0.0-0.0"
7972       case 6'100011
7973         assign { } { }
7974         assign $1\inv_a[0:0] 1'0
7975       attribute \src "libresoc.v:0.0-0.0"
7976       case 6'101010
7977         assign { } { }
7978         assign $1\inv_a[0:0] 1'0
7979       attribute \src "libresoc.v:0.0-0.0"
7980       case 6'101011
7981         assign { } { }
7982         assign $1\inv_a[0:0] 1'0
7983       attribute \src "libresoc.v:0.0-0.0"
7984       case 6'101000
7985         assign { } { }
7986         assign $1\inv_a[0:0] 1'0
7987       attribute \src "libresoc.v:0.0-0.0"
7988       case 6'101001
7989         assign { } { }
7990         assign $1\inv_a[0:0] 1'0
7991       attribute \src "libresoc.v:0.0-0.0"
7992       case 6'100000
7993         assign { } { }
7994         assign $1\inv_a[0:0] 1'0
7995       attribute \src "libresoc.v:0.0-0.0"
7996       case 6'100001
7997         assign { } { }
7998         assign $1\inv_a[0:0] 1'0
7999       attribute \src "libresoc.v:0.0-0.0"
8000       case 6'000111
8001         assign { } { }
8002         assign $1\inv_a[0:0] 1'0
8003       attribute \src "libresoc.v:0.0-0.0"
8004       case 6'011000
8005         assign { } { }
8006         assign $1\inv_a[0:0] 1'0
8007       attribute \src "libresoc.v:0.0-0.0"
8008       case 6'011001
8009         assign { } { }
8010         assign $1\inv_a[0:0] 1'0
8011       attribute \src "libresoc.v:0.0-0.0"
8012       case 6'010100
8013         assign { } { }
8014         assign $1\inv_a[0:0] 1'0
8015       attribute \src "libresoc.v:0.0-0.0"
8016       case 6'010101
8017         assign { } { }
8018         assign $1\inv_a[0:0] 1'0
8019       attribute \src "libresoc.v:0.0-0.0"
8020       case 6'010111
8021         assign { } { }
8022         assign $1\inv_a[0:0] 1'0
8023       attribute \src "libresoc.v:0.0-0.0"
8024       case 6'100110
8025         assign { } { }
8026         assign $1\inv_a[0:0] 1'0
8027       attribute \src "libresoc.v:0.0-0.0"
8028       case 6'100111
8029         assign { } { }
8030         assign $1\inv_a[0:0] 1'0
8031       attribute \src "libresoc.v:0.0-0.0"
8032       case 6'101100
8033         assign { } { }
8034         assign $1\inv_a[0:0] 1'0
8035       attribute \src "libresoc.v:0.0-0.0"
8036       case 6'101101
8037         assign { } { }
8038         assign $1\inv_a[0:0] 1'0
8039       attribute \src "libresoc.v:0.0-0.0"
8040       case 6'100100
8041         assign { } { }
8042         assign $1\inv_a[0:0] 1'0
8043       attribute \src "libresoc.v:0.0-0.0"
8044       case 6'100101
8045         assign { } { }
8046         assign $1\inv_a[0:0] 1'0
8047       attribute \src "libresoc.v:0.0-0.0"
8048       case 6'001000
8049         assign { } { }
8050         assign $1\inv_a[0:0] 1'1
8051       attribute \src "libresoc.v:0.0-0.0"
8052       case 6'000010
8053         assign { } { }
8054         assign $1\inv_a[0:0] 1'0
8055       attribute \src "libresoc.v:0.0-0.0"
8056       case 6'000011
8057         assign { } { }
8058         assign $1\inv_a[0:0] 1'0
8059       attribute \src "libresoc.v:0.0-0.0"
8060       case 6'011010
8061         assign { } { }
8062         assign $1\inv_a[0:0] 1'0
8063       attribute \src "libresoc.v:0.0-0.0"
8064       case 6'011011
8065         assign { } { }
8066         assign $1\inv_a[0:0] 1'0
8067       case
8068         assign $1\inv_a[0:0] 1'0
8069     end
8070     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8071     switch \opcode_switch$1
8072       attribute \src "libresoc.v:0.0-0.0"
8073       case 32'000000---------------0100000000-
8074         assign { } { }
8075         assign $2\inv_a[0:0] 1'0
8076       attribute \src "libresoc.v:0.0-0.0"
8077       case 1610612736
8078         assign { } { }
8079         assign $2\inv_a[0:0] 1'0
8080       attribute \src "libresoc.v:0.0-0.0"
8081       case 32'000001---------------0000000011-
8082         assign { } { }
8083         assign $2\inv_a[0:0] 1'0
8084       case
8085         assign $2\inv_a[0:0] $1\inv_a[0:0]
8086     end
8087     sync always
8088       update \inv_a $0\inv_a[0:0]
8089   end
8090   attribute \src "libresoc.v:5086.3-5227.6"
8091   process $proc$libresoc.v:5086$250
8092     assign { } { }
8093     assign { } { }
8094     assign { } { }
8095     assign $0\inv_out[0:0] $2\inv_out[0:0]
8096     attribute \src "libresoc.v:5087.5-5087.29"
8097     switch \initial
8098       attribute \src "libresoc.v:5087.9-5087.17"
8099       case 1'1
8100       case
8101     end
8102     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8103     switch \opcode_switch
8104       attribute \src "libresoc.v:0.0-0.0"
8105       case 6'010011
8106         assign { } { }
8107         assign $1\inv_out[0:0] \dec19_dec19_inv_out
8108       attribute \src "libresoc.v:0.0-0.0"
8109       case 6'011110
8110         assign { } { }
8111         assign $1\inv_out[0:0] \dec30_dec30_inv_out
8112       attribute \src "libresoc.v:0.0-0.0"
8113       case 6'011111
8114         assign { } { }
8115         assign $1\inv_out[0:0] \dec31_dec31_inv_out
8116       attribute \src "libresoc.v:0.0-0.0"
8117       case 6'111010
8118         assign { } { }
8119         assign $1\inv_out[0:0] \dec58_dec58_inv_out
8120       attribute \src "libresoc.v:0.0-0.0"
8121       case 6'111110
8122         assign { } { }
8123         assign $1\inv_out[0:0] \dec62_dec62_inv_out
8124       attribute \src "libresoc.v:0.0-0.0"
8125       case 6'001100
8126         assign { } { }
8127         assign $1\inv_out[0:0] 1'0
8128       attribute \src "libresoc.v:0.0-0.0"
8129       case 6'001101
8130         assign { } { }
8131         assign $1\inv_out[0:0] 1'0
8132       attribute \src "libresoc.v:0.0-0.0"
8133       case 6'001110
8134         assign { } { }
8135         assign $1\inv_out[0:0] 1'0
8136       attribute \src "libresoc.v:0.0-0.0"
8137       case 6'001111
8138         assign { } { }
8139         assign $1\inv_out[0:0] 1'0
8140       attribute \src "libresoc.v:0.0-0.0"
8141       case 6'010001
8142         assign { } { }
8143         assign $1\inv_out[0:0] 1'0
8144       attribute \src "libresoc.v:0.0-0.0"
8145       case 6'011100
8146         assign { } { }
8147         assign $1\inv_out[0:0] 1'0
8148       attribute \src "libresoc.v:0.0-0.0"
8149       case 6'011101
8150         assign { } { }
8151         assign $1\inv_out[0:0] 1'0
8152       attribute \src "libresoc.v:0.0-0.0"
8153       case 6'010010
8154         assign { } { }
8155         assign $1\inv_out[0:0] 1'0
8156       attribute \src "libresoc.v:0.0-0.0"
8157       case 6'010000
8158         assign { } { }
8159         assign $1\inv_out[0:0] 1'0
8160       attribute \src "libresoc.v:0.0-0.0"
8161       case 6'001011
8162         assign { } { }
8163         assign $1\inv_out[0:0] 1'0
8164       attribute \src "libresoc.v:0.0-0.0"
8165       case 6'001010
8166         assign { } { }
8167         assign $1\inv_out[0:0] 1'0
8168       attribute \src "libresoc.v:0.0-0.0"
8169       case 6'100010
8170         assign { } { }
8171         assign $1\inv_out[0:0] 1'0
8172       attribute \src "libresoc.v:0.0-0.0"
8173       case 6'100011
8174         assign { } { }
8175         assign $1\inv_out[0:0] 1'0
8176       attribute \src "libresoc.v:0.0-0.0"
8177       case 6'101010
8178         assign { } { }
8179         assign $1\inv_out[0:0] 1'0
8180       attribute \src "libresoc.v:0.0-0.0"
8181       case 6'101011
8182         assign { } { }
8183         assign $1\inv_out[0:0] 1'0
8184       attribute \src "libresoc.v:0.0-0.0"
8185       case 6'101000
8186         assign { } { }
8187         assign $1\inv_out[0:0] 1'0
8188       attribute \src "libresoc.v:0.0-0.0"
8189       case 6'101001
8190         assign { } { }
8191         assign $1\inv_out[0:0] 1'0
8192       attribute \src "libresoc.v:0.0-0.0"
8193       case 6'100000
8194         assign { } { }
8195         assign $1\inv_out[0:0] 1'0
8196       attribute \src "libresoc.v:0.0-0.0"
8197       case 6'100001
8198         assign { } { }
8199         assign $1\inv_out[0:0] 1'0
8200       attribute \src "libresoc.v:0.0-0.0"
8201       case 6'000111
8202         assign { } { }
8203         assign $1\inv_out[0:0] 1'0
8204       attribute \src "libresoc.v:0.0-0.0"
8205       case 6'011000
8206         assign { } { }
8207         assign $1\inv_out[0:0] 1'0
8208       attribute \src "libresoc.v:0.0-0.0"
8209       case 6'011001
8210         assign { } { }
8211         assign $1\inv_out[0:0] 1'0
8212       attribute \src "libresoc.v:0.0-0.0"
8213       case 6'010100
8214         assign { } { }
8215         assign $1\inv_out[0:0] 1'0
8216       attribute \src "libresoc.v:0.0-0.0"
8217       case 6'010101
8218         assign { } { }
8219         assign $1\inv_out[0:0] 1'0
8220       attribute \src "libresoc.v:0.0-0.0"
8221       case 6'010111
8222         assign { } { }
8223         assign $1\inv_out[0:0] 1'0
8224       attribute \src "libresoc.v:0.0-0.0"
8225       case 6'100110
8226         assign { } { }
8227         assign $1\inv_out[0:0] 1'0
8228       attribute \src "libresoc.v:0.0-0.0"
8229       case 6'100111
8230         assign { } { }
8231         assign $1\inv_out[0:0] 1'0
8232       attribute \src "libresoc.v:0.0-0.0"
8233       case 6'101100
8234         assign { } { }
8235         assign $1\inv_out[0:0] 1'0
8236       attribute \src "libresoc.v:0.0-0.0"
8237       case 6'101101
8238         assign { } { }
8239         assign $1\inv_out[0:0] 1'0
8240       attribute \src "libresoc.v:0.0-0.0"
8241       case 6'100100
8242         assign { } { }
8243         assign $1\inv_out[0:0] 1'0
8244       attribute \src "libresoc.v:0.0-0.0"
8245       case 6'100101
8246         assign { } { }
8247         assign $1\inv_out[0:0] 1'0
8248       attribute \src "libresoc.v:0.0-0.0"
8249       case 6'001000
8250         assign { } { }
8251         assign $1\inv_out[0:0] 1'0
8252       attribute \src "libresoc.v:0.0-0.0"
8253       case 6'000010
8254         assign { } { }
8255         assign $1\inv_out[0:0] 1'0
8256       attribute \src "libresoc.v:0.0-0.0"
8257       case 6'000011
8258         assign { } { }
8259         assign $1\inv_out[0:0] 1'0
8260       attribute \src "libresoc.v:0.0-0.0"
8261       case 6'011010
8262         assign { } { }
8263         assign $1\inv_out[0:0] 1'0
8264       attribute \src "libresoc.v:0.0-0.0"
8265       case 6'011011
8266         assign { } { }
8267         assign $1\inv_out[0:0] 1'0
8268       case
8269         assign $1\inv_out[0:0] 1'0
8270     end
8271     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8272     switch \opcode_switch$1
8273       attribute \src "libresoc.v:0.0-0.0"
8274       case 32'000000---------------0100000000-
8275         assign { } { }
8276         assign $2\inv_out[0:0] 1'0
8277       attribute \src "libresoc.v:0.0-0.0"
8278       case 1610612736
8279         assign { } { }
8280         assign $2\inv_out[0:0] 1'0
8281       attribute \src "libresoc.v:0.0-0.0"
8282       case 32'000001---------------0000000011-
8283         assign { } { }
8284         assign $2\inv_out[0:0] 1'0
8285       case
8286         assign $2\inv_out[0:0] $1\inv_out[0:0]
8287     end
8288     sync always
8289       update \inv_out $0\inv_out[0:0]
8290   end
8291   attribute \src "libresoc.v:5228.3-5369.6"
8292   process $proc$libresoc.v:5228$251
8293     assign { } { }
8294     assign { } { }
8295     assign { } { }
8296     assign $0\cry_out[0:0] $2\cry_out[0:0]
8297     attribute \src "libresoc.v:5229.5-5229.29"
8298     switch \initial
8299       attribute \src "libresoc.v:5229.9-5229.17"
8300       case 1'1
8301       case
8302     end
8303     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8304     switch \opcode_switch
8305       attribute \src "libresoc.v:0.0-0.0"
8306       case 6'010011
8307         assign { } { }
8308         assign $1\cry_out[0:0] \dec19_dec19_cry_out
8309       attribute \src "libresoc.v:0.0-0.0"
8310       case 6'011110
8311         assign { } { }
8312         assign $1\cry_out[0:0] \dec30_dec30_cry_out
8313       attribute \src "libresoc.v:0.0-0.0"
8314       case 6'011111
8315         assign { } { }
8316         assign $1\cry_out[0:0] \dec31_dec31_cry_out
8317       attribute \src "libresoc.v:0.0-0.0"
8318       case 6'111010
8319         assign { } { }
8320         assign $1\cry_out[0:0] \dec58_dec58_cry_out
8321       attribute \src "libresoc.v:0.0-0.0"
8322       case 6'111110
8323         assign { } { }
8324         assign $1\cry_out[0:0] \dec62_dec62_cry_out
8325       attribute \src "libresoc.v:0.0-0.0"
8326       case 6'001100
8327         assign { } { }
8328         assign $1\cry_out[0:0] 1'1
8329       attribute \src "libresoc.v:0.0-0.0"
8330       case 6'001101
8331         assign { } { }
8332         assign $1\cry_out[0:0] 1'1
8333       attribute \src "libresoc.v:0.0-0.0"
8334       case 6'001110
8335         assign { } { }
8336         assign $1\cry_out[0:0] 1'0
8337       attribute \src "libresoc.v:0.0-0.0"
8338       case 6'001111
8339         assign { } { }
8340         assign $1\cry_out[0:0] 1'0
8341       attribute \src "libresoc.v:0.0-0.0"
8342       case 6'010001
8343         assign { } { }
8344         assign $1\cry_out[0:0] 1'0
8345       attribute \src "libresoc.v:0.0-0.0"
8346       case 6'011100
8347         assign { } { }
8348         assign $1\cry_out[0:0] 1'0
8349       attribute \src "libresoc.v:0.0-0.0"
8350       case 6'011101
8351         assign { } { }
8352         assign $1\cry_out[0:0] 1'0
8353       attribute \src "libresoc.v:0.0-0.0"
8354       case 6'010010
8355         assign { } { }
8356         assign $1\cry_out[0:0] 1'0
8357       attribute \src "libresoc.v:0.0-0.0"
8358       case 6'010000
8359         assign { } { }
8360         assign $1\cry_out[0:0] 1'0
8361       attribute \src "libresoc.v:0.0-0.0"
8362       case 6'001011
8363         assign { } { }
8364         assign $1\cry_out[0:0] 1'0
8365       attribute \src "libresoc.v:0.0-0.0"
8366       case 6'001010
8367         assign { } { }
8368         assign $1\cry_out[0:0] 1'0
8369       attribute \src "libresoc.v:0.0-0.0"
8370       case 6'100010
8371         assign { } { }
8372         assign $1\cry_out[0:0] 1'0
8373       attribute \src "libresoc.v:0.0-0.0"
8374       case 6'100011
8375         assign { } { }
8376         assign $1\cry_out[0:0] 1'0
8377       attribute \src "libresoc.v:0.0-0.0"
8378       case 6'101010
8379         assign { } { }
8380         assign $1\cry_out[0:0] 1'0
8381       attribute \src "libresoc.v:0.0-0.0"
8382       case 6'101011
8383         assign { } { }
8384         assign $1\cry_out[0:0] 1'0
8385       attribute \src "libresoc.v:0.0-0.0"
8386       case 6'101000
8387         assign { } { }
8388         assign $1\cry_out[0:0] 1'0
8389       attribute \src "libresoc.v:0.0-0.0"
8390       case 6'101001
8391         assign { } { }
8392         assign $1\cry_out[0:0] 1'0
8393       attribute \src "libresoc.v:0.0-0.0"
8394       case 6'100000
8395         assign { } { }
8396         assign $1\cry_out[0:0] 1'0
8397       attribute \src "libresoc.v:0.0-0.0"
8398       case 6'100001
8399         assign { } { }
8400         assign $1\cry_out[0:0] 1'0
8401       attribute \src "libresoc.v:0.0-0.0"
8402       case 6'000111
8403         assign { } { }
8404         assign $1\cry_out[0:0] 1'0
8405       attribute \src "libresoc.v:0.0-0.0"
8406       case 6'011000
8407         assign { } { }
8408         assign $1\cry_out[0:0] 1'0
8409       attribute \src "libresoc.v:0.0-0.0"
8410       case 6'011001
8411         assign { } { }
8412         assign $1\cry_out[0:0] 1'0
8413       attribute \src "libresoc.v:0.0-0.0"
8414       case 6'010100
8415         assign { } { }
8416         assign $1\cry_out[0:0] 1'0
8417       attribute \src "libresoc.v:0.0-0.0"
8418       case 6'010101
8419         assign { } { }
8420         assign $1\cry_out[0:0] 1'0
8421       attribute \src "libresoc.v:0.0-0.0"
8422       case 6'010111
8423         assign { } { }
8424         assign $1\cry_out[0:0] 1'0
8425       attribute \src "libresoc.v:0.0-0.0"
8426       case 6'100110
8427         assign { } { }
8428         assign $1\cry_out[0:0] 1'0
8429       attribute \src "libresoc.v:0.0-0.0"
8430       case 6'100111
8431         assign { } { }
8432         assign $1\cry_out[0:0] 1'0
8433       attribute \src "libresoc.v:0.0-0.0"
8434       case 6'101100
8435         assign { } { }
8436         assign $1\cry_out[0:0] 1'0
8437       attribute \src "libresoc.v:0.0-0.0"
8438       case 6'101101
8439         assign { } { }
8440         assign $1\cry_out[0:0] 1'0
8441       attribute \src "libresoc.v:0.0-0.0"
8442       case 6'100100
8443         assign { } { }
8444         assign $1\cry_out[0:0] 1'0
8445       attribute \src "libresoc.v:0.0-0.0"
8446       case 6'100101
8447         assign { } { }
8448         assign $1\cry_out[0:0] 1'0
8449       attribute \src "libresoc.v:0.0-0.0"
8450       case 6'001000
8451         assign { } { }
8452         assign $1\cry_out[0:0] 1'1
8453       attribute \src "libresoc.v:0.0-0.0"
8454       case 6'000010
8455         assign { } { }
8456         assign $1\cry_out[0:0] 1'0
8457       attribute \src "libresoc.v:0.0-0.0"
8458       case 6'000011
8459         assign { } { }
8460         assign $1\cry_out[0:0] 1'0
8461       attribute \src "libresoc.v:0.0-0.0"
8462       case 6'011010
8463         assign { } { }
8464         assign $1\cry_out[0:0] 1'0
8465       attribute \src "libresoc.v:0.0-0.0"
8466       case 6'011011
8467         assign { } { }
8468         assign $1\cry_out[0:0] 1'0
8469       case
8470         assign $1\cry_out[0:0] 1'0
8471     end
8472     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8473     switch \opcode_switch$1
8474       attribute \src "libresoc.v:0.0-0.0"
8475       case 32'000000---------------0100000000-
8476         assign { } { }
8477         assign $2\cry_out[0:0] 1'0
8478       attribute \src "libresoc.v:0.0-0.0"
8479       case 1610612736
8480         assign { } { }
8481         assign $2\cry_out[0:0] 1'0
8482       attribute \src "libresoc.v:0.0-0.0"
8483       case 32'000001---------------0000000011-
8484         assign { } { }
8485         assign $2\cry_out[0:0] 1'0
8486       case
8487         assign $2\cry_out[0:0] $1\cry_out[0:0]
8488     end
8489     sync always
8490       update \cry_out $0\cry_out[0:0]
8491   end
8492   attribute \src "libresoc.v:5370.3-5511.6"
8493   process $proc$libresoc.v:5370$252
8494     assign { } { }
8495     assign { } { }
8496     assign { } { }
8497     assign $0\br[0:0] $2\br[0:0]
8498     attribute \src "libresoc.v:5371.5-5371.29"
8499     switch \initial
8500       attribute \src "libresoc.v:5371.9-5371.17"
8501       case 1'1
8502       case
8503     end
8504     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8505     switch \opcode_switch
8506       attribute \src "libresoc.v:0.0-0.0"
8507       case 6'010011
8508         assign { } { }
8509         assign $1\br[0:0] \dec19_dec19_br
8510       attribute \src "libresoc.v:0.0-0.0"
8511       case 6'011110
8512         assign { } { }
8513         assign $1\br[0:0] \dec30_dec30_br
8514       attribute \src "libresoc.v:0.0-0.0"
8515       case 6'011111
8516         assign { } { }
8517         assign $1\br[0:0] \dec31_dec31_br
8518       attribute \src "libresoc.v:0.0-0.0"
8519       case 6'111010
8520         assign { } { }
8521         assign $1\br[0:0] \dec58_dec58_br
8522       attribute \src "libresoc.v:0.0-0.0"
8523       case 6'111110
8524         assign { } { }
8525         assign $1\br[0:0] \dec62_dec62_br
8526       attribute \src "libresoc.v:0.0-0.0"
8527       case 6'001100
8528         assign { } { }
8529         assign $1\br[0:0] 1'0
8530       attribute \src "libresoc.v:0.0-0.0"
8531       case 6'001101
8532         assign { } { }
8533         assign $1\br[0:0] 1'0
8534       attribute \src "libresoc.v:0.0-0.0"
8535       case 6'001110
8536         assign { } { }
8537         assign $1\br[0:0] 1'0
8538       attribute \src "libresoc.v:0.0-0.0"
8539       case 6'001111
8540         assign { } { }
8541         assign $1\br[0:0] 1'0
8542       attribute \src "libresoc.v:0.0-0.0"
8543       case 6'010001
8544         assign { } { }
8545         assign $1\br[0:0] 1'0
8546       attribute \src "libresoc.v:0.0-0.0"
8547       case 6'011100
8548         assign { } { }
8549         assign $1\br[0:0] 1'0
8550       attribute \src "libresoc.v:0.0-0.0"
8551       case 6'011101
8552         assign { } { }
8553         assign $1\br[0:0] 1'0
8554       attribute \src "libresoc.v:0.0-0.0"
8555       case 6'010010
8556         assign { } { }
8557         assign $1\br[0:0] 1'0
8558       attribute \src "libresoc.v:0.0-0.0"
8559       case 6'010000
8560         assign { } { }
8561         assign $1\br[0:0] 1'0
8562       attribute \src "libresoc.v:0.0-0.0"
8563       case 6'001011
8564         assign { } { }
8565         assign $1\br[0:0] 1'0
8566       attribute \src "libresoc.v:0.0-0.0"
8567       case 6'001010
8568         assign { } { }
8569         assign $1\br[0:0] 1'0
8570       attribute \src "libresoc.v:0.0-0.0"
8571       case 6'100010
8572         assign { } { }
8573         assign $1\br[0:0] 1'0
8574       attribute \src "libresoc.v:0.0-0.0"
8575       case 6'100011
8576         assign { } { }
8577         assign $1\br[0:0] 1'0
8578       attribute \src "libresoc.v:0.0-0.0"
8579       case 6'101010
8580         assign { } { }
8581         assign $1\br[0:0] 1'0
8582       attribute \src "libresoc.v:0.0-0.0"
8583       case 6'101011
8584         assign { } { }
8585         assign $1\br[0:0] 1'0
8586       attribute \src "libresoc.v:0.0-0.0"
8587       case 6'101000
8588         assign { } { }
8589         assign $1\br[0:0] 1'0
8590       attribute \src "libresoc.v:0.0-0.0"
8591       case 6'101001
8592         assign { } { }
8593         assign $1\br[0:0] 1'0
8594       attribute \src "libresoc.v:0.0-0.0"
8595       case 6'100000
8596         assign { } { }
8597         assign $1\br[0:0] 1'0
8598       attribute \src "libresoc.v:0.0-0.0"
8599       case 6'100001
8600         assign { } { }
8601         assign $1\br[0:0] 1'0
8602       attribute \src "libresoc.v:0.0-0.0"
8603       case 6'000111
8604         assign { } { }
8605         assign $1\br[0:0] 1'0
8606       attribute \src "libresoc.v:0.0-0.0"
8607       case 6'011000
8608         assign { } { }
8609         assign $1\br[0:0] 1'0
8610       attribute \src "libresoc.v:0.0-0.0"
8611       case 6'011001
8612         assign { } { }
8613         assign $1\br[0:0] 1'0
8614       attribute \src "libresoc.v:0.0-0.0"
8615       case 6'010100
8616         assign { } { }
8617         assign $1\br[0:0] 1'0
8618       attribute \src "libresoc.v:0.0-0.0"
8619       case 6'010101
8620         assign { } { }
8621         assign $1\br[0:0] 1'0
8622       attribute \src "libresoc.v:0.0-0.0"
8623       case 6'010111
8624         assign { } { }
8625         assign $1\br[0:0] 1'0
8626       attribute \src "libresoc.v:0.0-0.0"
8627       case 6'100110
8628         assign { } { }
8629         assign $1\br[0:0] 1'0
8630       attribute \src "libresoc.v:0.0-0.0"
8631       case 6'100111
8632         assign { } { }
8633         assign $1\br[0:0] 1'0
8634       attribute \src "libresoc.v:0.0-0.0"
8635       case 6'101100
8636         assign { } { }
8637         assign $1\br[0:0] 1'0
8638       attribute \src "libresoc.v:0.0-0.0"
8639       case 6'101101
8640         assign { } { }
8641         assign $1\br[0:0] 1'0
8642       attribute \src "libresoc.v:0.0-0.0"
8643       case 6'100100
8644         assign { } { }
8645         assign $1\br[0:0] 1'0
8646       attribute \src "libresoc.v:0.0-0.0"
8647       case 6'100101
8648         assign { } { }
8649         assign $1\br[0:0] 1'0
8650       attribute \src "libresoc.v:0.0-0.0"
8651       case 6'001000
8652         assign { } { }
8653         assign $1\br[0:0] 1'0
8654       attribute \src "libresoc.v:0.0-0.0"
8655       case 6'000010
8656         assign { } { }
8657         assign $1\br[0:0] 1'0
8658       attribute \src "libresoc.v:0.0-0.0"
8659       case 6'000011
8660         assign { } { }
8661         assign $1\br[0:0] 1'0
8662       attribute \src "libresoc.v:0.0-0.0"
8663       case 6'011010
8664         assign { } { }
8665         assign $1\br[0:0] 1'0
8666       attribute \src "libresoc.v:0.0-0.0"
8667       case 6'011011
8668         assign { } { }
8669         assign $1\br[0:0] 1'0
8670       case
8671         assign $1\br[0:0] 1'0
8672     end
8673     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8674     switch \opcode_switch$1
8675       attribute \src "libresoc.v:0.0-0.0"
8676       case 32'000000---------------0100000000-
8677         assign { } { }
8678         assign $2\br[0:0] 1'0
8679       attribute \src "libresoc.v:0.0-0.0"
8680       case 1610612736
8681         assign { } { }
8682         assign $2\br[0:0] 1'0
8683       attribute \src "libresoc.v:0.0-0.0"
8684       case 32'000001---------------0000000011-
8685         assign { } { }
8686         assign $2\br[0:0] 1'0
8687       case
8688         assign $2\br[0:0] $1\br[0:0]
8689     end
8690     sync always
8691       update \br $0\br[0:0]
8692   end
8693   attribute \src "libresoc.v:5512.3-5653.6"
8694   process $proc$libresoc.v:5512$253
8695     assign { } { }
8696     assign { } { }
8697     assign { } { }
8698     assign $0\sgn_ext[0:0] $2\sgn_ext[0:0]
8699     attribute \src "libresoc.v:5513.5-5513.29"
8700     switch \initial
8701       attribute \src "libresoc.v:5513.9-5513.17"
8702       case 1'1
8703       case
8704     end
8705     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8706     switch \opcode_switch
8707       attribute \src "libresoc.v:0.0-0.0"
8708       case 6'010011
8709         assign { } { }
8710         assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext
8711       attribute \src "libresoc.v:0.0-0.0"
8712       case 6'011110
8713         assign { } { }
8714         assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext
8715       attribute \src "libresoc.v:0.0-0.0"
8716       case 6'011111
8717         assign { } { }
8718         assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext
8719       attribute \src "libresoc.v:0.0-0.0"
8720       case 6'111010
8721         assign { } { }
8722         assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext
8723       attribute \src "libresoc.v:0.0-0.0"
8724       case 6'111110
8725         assign { } { }
8726         assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext
8727       attribute \src "libresoc.v:0.0-0.0"
8728       case 6'001100
8729         assign { } { }
8730         assign $1\sgn_ext[0:0] 1'0
8731       attribute \src "libresoc.v:0.0-0.0"
8732       case 6'001101
8733         assign { } { }
8734         assign $1\sgn_ext[0:0] 1'0
8735       attribute \src "libresoc.v:0.0-0.0"
8736       case 6'001110
8737         assign { } { }
8738         assign $1\sgn_ext[0:0] 1'0
8739       attribute \src "libresoc.v:0.0-0.0"
8740       case 6'001111
8741         assign { } { }
8742         assign $1\sgn_ext[0:0] 1'0
8743       attribute \src "libresoc.v:0.0-0.0"
8744       case 6'010001
8745         assign { } { }
8746         assign $1\sgn_ext[0:0] 1'0
8747       attribute \src "libresoc.v:0.0-0.0"
8748       case 6'011100
8749         assign { } { }
8750         assign $1\sgn_ext[0:0] 1'0
8751       attribute \src "libresoc.v:0.0-0.0"
8752       case 6'011101
8753         assign { } { }
8754         assign $1\sgn_ext[0:0] 1'0
8755       attribute \src "libresoc.v:0.0-0.0"
8756       case 6'010010
8757         assign { } { }
8758         assign $1\sgn_ext[0:0] 1'0
8759       attribute \src "libresoc.v:0.0-0.0"
8760       case 6'010000
8761         assign { } { }
8762         assign $1\sgn_ext[0:0] 1'0
8763       attribute \src "libresoc.v:0.0-0.0"
8764       case 6'001011
8765         assign { } { }
8766         assign $1\sgn_ext[0:0] 1'0
8767       attribute \src "libresoc.v:0.0-0.0"
8768       case 6'001010
8769         assign { } { }
8770         assign $1\sgn_ext[0:0] 1'0
8771       attribute \src "libresoc.v:0.0-0.0"
8772       case 6'100010
8773         assign { } { }
8774         assign $1\sgn_ext[0:0] 1'0
8775       attribute \src "libresoc.v:0.0-0.0"
8776       case 6'100011
8777         assign { } { }
8778         assign $1\sgn_ext[0:0] 1'0
8779       attribute \src "libresoc.v:0.0-0.0"
8780       case 6'101010
8781         assign { } { }
8782         assign $1\sgn_ext[0:0] 1'1
8783       attribute \src "libresoc.v:0.0-0.0"
8784       case 6'101011
8785         assign { } { }
8786         assign $1\sgn_ext[0:0] 1'1
8787       attribute \src "libresoc.v:0.0-0.0"
8788       case 6'101000
8789         assign { } { }
8790         assign $1\sgn_ext[0:0] 1'0
8791       attribute \src "libresoc.v:0.0-0.0"
8792       case 6'101001
8793         assign { } { }
8794         assign $1\sgn_ext[0:0] 1'0
8795       attribute \src "libresoc.v:0.0-0.0"
8796       case 6'100000
8797         assign { } { }
8798         assign $1\sgn_ext[0:0] 1'0
8799       attribute \src "libresoc.v:0.0-0.0"
8800       case 6'100001
8801         assign { } { }
8802         assign $1\sgn_ext[0:0] 1'0
8803       attribute \src "libresoc.v:0.0-0.0"
8804       case 6'000111
8805         assign { } { }
8806         assign $1\sgn_ext[0:0] 1'0
8807       attribute \src "libresoc.v:0.0-0.0"
8808       case 6'011000
8809         assign { } { }
8810         assign $1\sgn_ext[0:0] 1'0
8811       attribute \src "libresoc.v:0.0-0.0"
8812       case 6'011001
8813         assign { } { }
8814         assign $1\sgn_ext[0:0] 1'0
8815       attribute \src "libresoc.v:0.0-0.0"
8816       case 6'010100
8817         assign { } { }
8818         assign $1\sgn_ext[0:0] 1'0
8819       attribute \src "libresoc.v:0.0-0.0"
8820       case 6'010101
8821         assign { } { }
8822         assign $1\sgn_ext[0:0] 1'0
8823       attribute \src "libresoc.v:0.0-0.0"
8824       case 6'010111
8825         assign { } { }
8826         assign $1\sgn_ext[0:0] 1'0
8827       attribute \src "libresoc.v:0.0-0.0"
8828       case 6'100110
8829         assign { } { }
8830         assign $1\sgn_ext[0:0] 1'0
8831       attribute \src "libresoc.v:0.0-0.0"
8832       case 6'100111
8833         assign { } { }
8834         assign $1\sgn_ext[0:0] 1'0
8835       attribute \src "libresoc.v:0.0-0.0"
8836       case 6'101100
8837         assign { } { }
8838         assign $1\sgn_ext[0:0] 1'0
8839       attribute \src "libresoc.v:0.0-0.0"
8840       case 6'101101
8841         assign { } { }
8842         assign $1\sgn_ext[0:0] 1'0
8843       attribute \src "libresoc.v:0.0-0.0"
8844       case 6'100100
8845         assign { } { }
8846         assign $1\sgn_ext[0:0] 1'0
8847       attribute \src "libresoc.v:0.0-0.0"
8848       case 6'100101
8849         assign { } { }
8850         assign $1\sgn_ext[0:0] 1'0
8851       attribute \src "libresoc.v:0.0-0.0"
8852       case 6'001000
8853         assign { } { }
8854         assign $1\sgn_ext[0:0] 1'0
8855       attribute \src "libresoc.v:0.0-0.0"
8856       case 6'000010
8857         assign { } { }
8858         assign $1\sgn_ext[0:0] 1'0
8859       attribute \src "libresoc.v:0.0-0.0"
8860       case 6'000011
8861         assign { } { }
8862         assign $1\sgn_ext[0:0] 1'0
8863       attribute \src "libresoc.v:0.0-0.0"
8864       case 6'011010
8865         assign { } { }
8866         assign $1\sgn_ext[0:0] 1'0
8867       attribute \src "libresoc.v:0.0-0.0"
8868       case 6'011011
8869         assign { } { }
8870         assign $1\sgn_ext[0:0] 1'0
8871       case
8872         assign $1\sgn_ext[0:0] 1'0
8873     end
8874     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8875     switch \opcode_switch$1
8876       attribute \src "libresoc.v:0.0-0.0"
8877       case 32'000000---------------0100000000-
8878         assign { } { }
8879         assign $2\sgn_ext[0:0] 1'0
8880       attribute \src "libresoc.v:0.0-0.0"
8881       case 1610612736
8882         assign { } { }
8883         assign $2\sgn_ext[0:0] 1'0
8884       attribute \src "libresoc.v:0.0-0.0"
8885       case 32'000001---------------0000000011-
8886         assign { } { }
8887         assign $2\sgn_ext[0:0] 1'0
8888       case
8889         assign $2\sgn_ext[0:0] $1\sgn_ext[0:0]
8890     end
8891     sync always
8892       update \sgn_ext $0\sgn_ext[0:0]
8893   end
8894   attribute \src "libresoc.v:5654.3-5795.6"
8895   process $proc$libresoc.v:5654$254
8896     assign { } { }
8897     assign { } { }
8898     assign { } { }
8899     assign $0\rsrv[0:0] $2\rsrv[0:0]
8900     attribute \src "libresoc.v:5655.5-5655.29"
8901     switch \initial
8902       attribute \src "libresoc.v:5655.9-5655.17"
8903       case 1'1
8904       case
8905     end
8906     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
8907     switch \opcode_switch
8908       attribute \src "libresoc.v:0.0-0.0"
8909       case 6'010011
8910         assign { } { }
8911         assign $1\rsrv[0:0] \dec19_dec19_rsrv
8912       attribute \src "libresoc.v:0.0-0.0"
8913       case 6'011110
8914         assign { } { }
8915         assign $1\rsrv[0:0] \dec30_dec30_rsrv
8916       attribute \src "libresoc.v:0.0-0.0"
8917       case 6'011111
8918         assign { } { }
8919         assign $1\rsrv[0:0] \dec31_dec31_rsrv
8920       attribute \src "libresoc.v:0.0-0.0"
8921       case 6'111010
8922         assign { } { }
8923         assign $1\rsrv[0:0] \dec58_dec58_rsrv
8924       attribute \src "libresoc.v:0.0-0.0"
8925       case 6'111110
8926         assign { } { }
8927         assign $1\rsrv[0:0] \dec62_dec62_rsrv
8928       attribute \src "libresoc.v:0.0-0.0"
8929       case 6'001100
8930         assign { } { }
8931         assign $1\rsrv[0:0] 1'0
8932       attribute \src "libresoc.v:0.0-0.0"
8933       case 6'001101
8934         assign { } { }
8935         assign $1\rsrv[0:0] 1'0
8936       attribute \src "libresoc.v:0.0-0.0"
8937       case 6'001110
8938         assign { } { }
8939         assign $1\rsrv[0:0] 1'0
8940       attribute \src "libresoc.v:0.0-0.0"
8941       case 6'001111
8942         assign { } { }
8943         assign $1\rsrv[0:0] 1'0
8944       attribute \src "libresoc.v:0.0-0.0"
8945       case 6'010001
8946         assign { } { }
8947         assign $1\rsrv[0:0] 1'0
8948       attribute \src "libresoc.v:0.0-0.0"
8949       case 6'011100
8950         assign { } { }
8951         assign $1\rsrv[0:0] 1'0
8952       attribute \src "libresoc.v:0.0-0.0"
8953       case 6'011101
8954         assign { } { }
8955         assign $1\rsrv[0:0] 1'0
8956       attribute \src "libresoc.v:0.0-0.0"
8957       case 6'010010
8958         assign { } { }
8959         assign $1\rsrv[0:0] 1'0
8960       attribute \src "libresoc.v:0.0-0.0"
8961       case 6'010000
8962         assign { } { }
8963         assign $1\rsrv[0:0] 1'0
8964       attribute \src "libresoc.v:0.0-0.0"
8965       case 6'001011
8966         assign { } { }
8967         assign $1\rsrv[0:0] 1'0
8968       attribute \src "libresoc.v:0.0-0.0"
8969       case 6'001010
8970         assign { } { }
8971         assign $1\rsrv[0:0] 1'0
8972       attribute \src "libresoc.v:0.0-0.0"
8973       case 6'100010
8974         assign { } { }
8975         assign $1\rsrv[0:0] 1'0
8976       attribute \src "libresoc.v:0.0-0.0"
8977       case 6'100011
8978         assign { } { }
8979         assign $1\rsrv[0:0] 1'0
8980       attribute \src "libresoc.v:0.0-0.0"
8981       case 6'101010
8982         assign { } { }
8983         assign $1\rsrv[0:0] 1'0
8984       attribute \src "libresoc.v:0.0-0.0"
8985       case 6'101011
8986         assign { } { }
8987         assign $1\rsrv[0:0] 1'0
8988       attribute \src "libresoc.v:0.0-0.0"
8989       case 6'101000
8990         assign { } { }
8991         assign $1\rsrv[0:0] 1'0
8992       attribute \src "libresoc.v:0.0-0.0"
8993       case 6'101001
8994         assign { } { }
8995         assign $1\rsrv[0:0] 1'0
8996       attribute \src "libresoc.v:0.0-0.0"
8997       case 6'100000
8998         assign { } { }
8999         assign $1\rsrv[0:0] 1'0
9000       attribute \src "libresoc.v:0.0-0.0"
9001       case 6'100001
9002         assign { } { }
9003         assign $1\rsrv[0:0] 1'0
9004       attribute \src "libresoc.v:0.0-0.0"
9005       case 6'000111
9006         assign { } { }
9007         assign $1\rsrv[0:0] 1'0
9008       attribute \src "libresoc.v:0.0-0.0"
9009       case 6'011000
9010         assign { } { }
9011         assign $1\rsrv[0:0] 1'0
9012       attribute \src "libresoc.v:0.0-0.0"
9013       case 6'011001
9014         assign { } { }
9015         assign $1\rsrv[0:0] 1'0
9016       attribute \src "libresoc.v:0.0-0.0"
9017       case 6'010100
9018         assign { } { }
9019         assign $1\rsrv[0:0] 1'0
9020       attribute \src "libresoc.v:0.0-0.0"
9021       case 6'010101
9022         assign { } { }
9023         assign $1\rsrv[0:0] 1'0
9024       attribute \src "libresoc.v:0.0-0.0"
9025       case 6'010111
9026         assign { } { }
9027         assign $1\rsrv[0:0] 1'0
9028       attribute \src "libresoc.v:0.0-0.0"
9029       case 6'100110
9030         assign { } { }
9031         assign $1\rsrv[0:0] 1'0
9032       attribute \src "libresoc.v:0.0-0.0"
9033       case 6'100111
9034         assign { } { }
9035         assign $1\rsrv[0:0] 1'0
9036       attribute \src "libresoc.v:0.0-0.0"
9037       case 6'101100
9038         assign { } { }
9039         assign $1\rsrv[0:0] 1'0
9040       attribute \src "libresoc.v:0.0-0.0"
9041       case 6'101101
9042         assign { } { }
9043         assign $1\rsrv[0:0] 1'0
9044       attribute \src "libresoc.v:0.0-0.0"
9045       case 6'100100
9046         assign { } { }
9047         assign $1\rsrv[0:0] 1'0
9048       attribute \src "libresoc.v:0.0-0.0"
9049       case 6'100101
9050         assign { } { }
9051         assign $1\rsrv[0:0] 1'0
9052       attribute \src "libresoc.v:0.0-0.0"
9053       case 6'001000
9054         assign { } { }
9055         assign $1\rsrv[0:0] 1'0
9056       attribute \src "libresoc.v:0.0-0.0"
9057       case 6'000010
9058         assign { } { }
9059         assign $1\rsrv[0:0] 1'0
9060       attribute \src "libresoc.v:0.0-0.0"
9061       case 6'000011
9062         assign { } { }
9063         assign $1\rsrv[0:0] 1'0
9064       attribute \src "libresoc.v:0.0-0.0"
9065       case 6'011010
9066         assign { } { }
9067         assign $1\rsrv[0:0] 1'0
9068       attribute \src "libresoc.v:0.0-0.0"
9069       case 6'011011
9070         assign { } { }
9071         assign $1\rsrv[0:0] 1'0
9072       case
9073         assign $1\rsrv[0:0] 1'0
9074     end
9075     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9076     switch \opcode_switch$1
9077       attribute \src "libresoc.v:0.0-0.0"
9078       case 32'000000---------------0100000000-
9079         assign { } { }
9080         assign $2\rsrv[0:0] 1'0
9081       attribute \src "libresoc.v:0.0-0.0"
9082       case 1610612736
9083         assign { } { }
9084         assign $2\rsrv[0:0] 1'0
9085       attribute \src "libresoc.v:0.0-0.0"
9086       case 32'000001---------------0000000011-
9087         assign { } { }
9088         assign $2\rsrv[0:0] 1'0
9089       case
9090         assign $2\rsrv[0:0] $1\rsrv[0:0]
9091     end
9092     sync always
9093       update \rsrv $0\rsrv[0:0]
9094   end
9095   attribute \src "libresoc.v:5796.3-5937.6"
9096   process $proc$libresoc.v:5796$255
9097     assign { } { }
9098     assign { } { }
9099     assign { } { }
9100     assign $0\is_32b[0:0] $2\is_32b[0:0]
9101     attribute \src "libresoc.v:5797.5-5797.29"
9102     switch \initial
9103       attribute \src "libresoc.v:5797.9-5797.17"
9104       case 1'1
9105       case
9106     end
9107     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9108     switch \opcode_switch
9109       attribute \src "libresoc.v:0.0-0.0"
9110       case 6'010011
9111         assign { } { }
9112         assign $1\is_32b[0:0] \dec19_dec19_is_32b
9113       attribute \src "libresoc.v:0.0-0.0"
9114       case 6'011110
9115         assign { } { }
9116         assign $1\is_32b[0:0] \dec30_dec30_is_32b
9117       attribute \src "libresoc.v:0.0-0.0"
9118       case 6'011111
9119         assign { } { }
9120         assign $1\is_32b[0:0] \dec31_dec31_is_32b
9121       attribute \src "libresoc.v:0.0-0.0"
9122       case 6'111010
9123         assign { } { }
9124         assign $1\is_32b[0:0] \dec58_dec58_is_32b
9125       attribute \src "libresoc.v:0.0-0.0"
9126       case 6'111110
9127         assign { } { }
9128         assign $1\is_32b[0:0] \dec62_dec62_is_32b
9129       attribute \src "libresoc.v:0.0-0.0"
9130       case 6'001100
9131         assign { } { }
9132         assign $1\is_32b[0:0] 1'0
9133       attribute \src "libresoc.v:0.0-0.0"
9134       case 6'001101
9135         assign { } { }
9136         assign $1\is_32b[0:0] 1'0
9137       attribute \src "libresoc.v:0.0-0.0"
9138       case 6'001110
9139         assign { } { }
9140         assign $1\is_32b[0:0] 1'0
9141       attribute \src "libresoc.v:0.0-0.0"
9142       case 6'001111
9143         assign { } { }
9144         assign $1\is_32b[0:0] 1'0
9145       attribute \src "libresoc.v:0.0-0.0"
9146       case 6'010001
9147         assign { } { }
9148         assign $1\is_32b[0:0] 1'0
9149       attribute \src "libresoc.v:0.0-0.0"
9150       case 6'011100
9151         assign { } { }
9152         assign $1\is_32b[0:0] 1'0
9153       attribute \src "libresoc.v:0.0-0.0"
9154       case 6'011101
9155         assign { } { }
9156         assign $1\is_32b[0:0] 1'0
9157       attribute \src "libresoc.v:0.0-0.0"
9158       case 6'010010
9159         assign { } { }
9160         assign $1\is_32b[0:0] 1'0
9161       attribute \src "libresoc.v:0.0-0.0"
9162       case 6'010000
9163         assign { } { }
9164         assign $1\is_32b[0:0] 1'0
9165       attribute \src "libresoc.v:0.0-0.0"
9166       case 6'001011
9167         assign { } { }
9168         assign $1\is_32b[0:0] 1'0
9169       attribute \src "libresoc.v:0.0-0.0"
9170       case 6'001010
9171         assign { } { }
9172         assign $1\is_32b[0:0] 1'0
9173       attribute \src "libresoc.v:0.0-0.0"
9174       case 6'100010
9175         assign { } { }
9176         assign $1\is_32b[0:0] 1'0
9177       attribute \src "libresoc.v:0.0-0.0"
9178       case 6'100011
9179         assign { } { }
9180         assign $1\is_32b[0:0] 1'0
9181       attribute \src "libresoc.v:0.0-0.0"
9182       case 6'101010
9183         assign { } { }
9184         assign $1\is_32b[0:0] 1'0
9185       attribute \src "libresoc.v:0.0-0.0"
9186       case 6'101011
9187         assign { } { }
9188         assign $1\is_32b[0:0] 1'0
9189       attribute \src "libresoc.v:0.0-0.0"
9190       case 6'101000
9191         assign { } { }
9192         assign $1\is_32b[0:0] 1'0
9193       attribute \src "libresoc.v:0.0-0.0"
9194       case 6'101001
9195         assign { } { }
9196         assign $1\is_32b[0:0] 1'0
9197       attribute \src "libresoc.v:0.0-0.0"
9198       case 6'100000
9199         assign { } { }
9200         assign $1\is_32b[0:0] 1'0
9201       attribute \src "libresoc.v:0.0-0.0"
9202       case 6'100001
9203         assign { } { }
9204         assign $1\is_32b[0:0] 1'0
9205       attribute \src "libresoc.v:0.0-0.0"
9206       case 6'000111
9207         assign { } { }
9208         assign $1\is_32b[0:0] 1'0
9209       attribute \src "libresoc.v:0.0-0.0"
9210       case 6'011000
9211         assign { } { }
9212         assign $1\is_32b[0:0] 1'0
9213       attribute \src "libresoc.v:0.0-0.0"
9214       case 6'011001
9215         assign { } { }
9216         assign $1\is_32b[0:0] 1'0
9217       attribute \src "libresoc.v:0.0-0.0"
9218       case 6'010100
9219         assign { } { }
9220         assign $1\is_32b[0:0] 1'1
9221       attribute \src "libresoc.v:0.0-0.0"
9222       case 6'010101
9223         assign { } { }
9224         assign $1\is_32b[0:0] 1'1
9225       attribute \src "libresoc.v:0.0-0.0"
9226       case 6'010111
9227         assign { } { }
9228         assign $1\is_32b[0:0] 1'1
9229       attribute \src "libresoc.v:0.0-0.0"
9230       case 6'100110
9231         assign { } { }
9232         assign $1\is_32b[0:0] 1'0
9233       attribute \src "libresoc.v:0.0-0.0"
9234       case 6'100111
9235         assign { } { }
9236         assign $1\is_32b[0:0] 1'0
9237       attribute \src "libresoc.v:0.0-0.0"
9238       case 6'101100
9239         assign { } { }
9240         assign $1\is_32b[0:0] 1'0
9241       attribute \src "libresoc.v:0.0-0.0"
9242       case 6'101101
9243         assign { } { }
9244         assign $1\is_32b[0:0] 1'0
9245       attribute \src "libresoc.v:0.0-0.0"
9246       case 6'100100
9247         assign { } { }
9248         assign $1\is_32b[0:0] 1'0
9249       attribute \src "libresoc.v:0.0-0.0"
9250       case 6'100101
9251         assign { } { }
9252         assign $1\is_32b[0:0] 1'0
9253       attribute \src "libresoc.v:0.0-0.0"
9254       case 6'001000
9255         assign { } { }
9256         assign $1\is_32b[0:0] 1'0
9257       attribute \src "libresoc.v:0.0-0.0"
9258       case 6'000010
9259         assign { } { }
9260         assign $1\is_32b[0:0] 1'0
9261       attribute \src "libresoc.v:0.0-0.0"
9262       case 6'000011
9263         assign { } { }
9264         assign $1\is_32b[0:0] 1'1
9265       attribute \src "libresoc.v:0.0-0.0"
9266       case 6'011010
9267         assign { } { }
9268         assign $1\is_32b[0:0] 1'0
9269       attribute \src "libresoc.v:0.0-0.0"
9270       case 6'011011
9271         assign { } { }
9272         assign $1\is_32b[0:0] 1'0
9273       case
9274         assign $1\is_32b[0:0] 1'0
9275     end
9276     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9277     switch \opcode_switch$1
9278       attribute \src "libresoc.v:0.0-0.0"
9279       case 32'000000---------------0100000000-
9280         assign { } { }
9281         assign $2\is_32b[0:0] 1'0
9282       attribute \src "libresoc.v:0.0-0.0"
9283       case 1610612736
9284         assign { } { }
9285         assign $2\is_32b[0:0] 1'0
9286       attribute \src "libresoc.v:0.0-0.0"
9287       case 32'000001---------------0000000011-
9288         assign { } { }
9289         assign $2\is_32b[0:0] 1'0
9290       case
9291         assign $2\is_32b[0:0] $1\is_32b[0:0]
9292     end
9293     sync always
9294       update \is_32b $0\is_32b[0:0]
9295   end
9296   attribute \src "libresoc.v:5938.3-6079.6"
9297   process $proc$libresoc.v:5938$256
9298     assign { } { }
9299     assign { } { }
9300     assign { } { }
9301     assign $0\sgn[0:0] $2\sgn[0:0]
9302     attribute \src "libresoc.v:5939.5-5939.29"
9303     switch \initial
9304       attribute \src "libresoc.v:5939.9-5939.17"
9305       case 1'1
9306       case
9307     end
9308     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9309     switch \opcode_switch
9310       attribute \src "libresoc.v:0.0-0.0"
9311       case 6'010011
9312         assign { } { }
9313         assign $1\sgn[0:0] \dec19_dec19_sgn
9314       attribute \src "libresoc.v:0.0-0.0"
9315       case 6'011110
9316         assign { } { }
9317         assign $1\sgn[0:0] \dec30_dec30_sgn
9318       attribute \src "libresoc.v:0.0-0.0"
9319       case 6'011111
9320         assign { } { }
9321         assign $1\sgn[0:0] \dec31_dec31_sgn
9322       attribute \src "libresoc.v:0.0-0.0"
9323       case 6'111010
9324         assign { } { }
9325         assign $1\sgn[0:0] \dec58_dec58_sgn
9326       attribute \src "libresoc.v:0.0-0.0"
9327       case 6'111110
9328         assign { } { }
9329         assign $1\sgn[0:0] \dec62_dec62_sgn
9330       attribute \src "libresoc.v:0.0-0.0"
9331       case 6'001100
9332         assign { } { }
9333         assign $1\sgn[0:0] 1'0
9334       attribute \src "libresoc.v:0.0-0.0"
9335       case 6'001101
9336         assign { } { }
9337         assign $1\sgn[0:0] 1'0
9338       attribute \src "libresoc.v:0.0-0.0"
9339       case 6'001110
9340         assign { } { }
9341         assign $1\sgn[0:0] 1'0
9342       attribute \src "libresoc.v:0.0-0.0"
9343       case 6'001111
9344         assign { } { }
9345         assign $1\sgn[0:0] 1'0
9346       attribute \src "libresoc.v:0.0-0.0"
9347       case 6'010001
9348         assign { } { }
9349         assign $1\sgn[0:0] 1'0
9350       attribute \src "libresoc.v:0.0-0.0"
9351       case 6'011100
9352         assign { } { }
9353         assign $1\sgn[0:0] 1'0
9354       attribute \src "libresoc.v:0.0-0.0"
9355       case 6'011101
9356         assign { } { }
9357         assign $1\sgn[0:0] 1'0
9358       attribute \src "libresoc.v:0.0-0.0"
9359       case 6'010010
9360         assign { } { }
9361         assign $1\sgn[0:0] 1'0
9362       attribute \src "libresoc.v:0.0-0.0"
9363       case 6'010000
9364         assign { } { }
9365         assign $1\sgn[0:0] 1'0
9366       attribute \src "libresoc.v:0.0-0.0"
9367       case 6'001011
9368         assign { } { }
9369         assign $1\sgn[0:0] 1'1
9370       attribute \src "libresoc.v:0.0-0.0"
9371       case 6'001010
9372         assign { } { }
9373         assign $1\sgn[0:0] 1'0
9374       attribute \src "libresoc.v:0.0-0.0"
9375       case 6'100010
9376         assign { } { }
9377         assign $1\sgn[0:0] 1'0
9378       attribute \src "libresoc.v:0.0-0.0"
9379       case 6'100011
9380         assign { } { }
9381         assign $1\sgn[0:0] 1'0
9382       attribute \src "libresoc.v:0.0-0.0"
9383       case 6'101010
9384         assign { } { }
9385         assign $1\sgn[0:0] 1'0
9386       attribute \src "libresoc.v:0.0-0.0"
9387       case 6'101011
9388         assign { } { }
9389         assign $1\sgn[0:0] 1'0
9390       attribute \src "libresoc.v:0.0-0.0"
9391       case 6'101000
9392         assign { } { }
9393         assign $1\sgn[0:0] 1'0
9394       attribute \src "libresoc.v:0.0-0.0"
9395       case 6'101001
9396         assign { } { }
9397         assign $1\sgn[0:0] 1'0
9398       attribute \src "libresoc.v:0.0-0.0"
9399       case 6'100000
9400         assign { } { }
9401         assign $1\sgn[0:0] 1'0
9402       attribute \src "libresoc.v:0.0-0.0"
9403       case 6'100001
9404         assign { } { }
9405         assign $1\sgn[0:0] 1'0
9406       attribute \src "libresoc.v:0.0-0.0"
9407       case 6'000111
9408         assign { } { }
9409         assign $1\sgn[0:0] 1'1
9410       attribute \src "libresoc.v:0.0-0.0"
9411       case 6'011000
9412         assign { } { }
9413         assign $1\sgn[0:0] 1'0
9414       attribute \src "libresoc.v:0.0-0.0"
9415       case 6'011001
9416         assign { } { }
9417         assign $1\sgn[0:0] 1'0
9418       attribute \src "libresoc.v:0.0-0.0"
9419       case 6'010100
9420         assign { } { }
9421         assign $1\sgn[0:0] 1'0
9422       attribute \src "libresoc.v:0.0-0.0"
9423       case 6'010101
9424         assign { } { }
9425         assign $1\sgn[0:0] 1'0
9426       attribute \src "libresoc.v:0.0-0.0"
9427       case 6'010111
9428         assign { } { }
9429         assign $1\sgn[0:0] 1'0
9430       attribute \src "libresoc.v:0.0-0.0"
9431       case 6'100110
9432         assign { } { }
9433         assign $1\sgn[0:0] 1'0
9434       attribute \src "libresoc.v:0.0-0.0"
9435       case 6'100111
9436         assign { } { }
9437         assign $1\sgn[0:0] 1'0
9438       attribute \src "libresoc.v:0.0-0.0"
9439       case 6'101100
9440         assign { } { }
9441         assign $1\sgn[0:0] 1'0
9442       attribute \src "libresoc.v:0.0-0.0"
9443       case 6'101101
9444         assign { } { }
9445         assign $1\sgn[0:0] 1'0
9446       attribute \src "libresoc.v:0.0-0.0"
9447       case 6'100100
9448         assign { } { }
9449         assign $1\sgn[0:0] 1'0
9450       attribute \src "libresoc.v:0.0-0.0"
9451       case 6'100101
9452         assign { } { }
9453         assign $1\sgn[0:0] 1'0
9454       attribute \src "libresoc.v:0.0-0.0"
9455       case 6'001000
9456         assign { } { }
9457         assign $1\sgn[0:0] 1'0
9458       attribute \src "libresoc.v:0.0-0.0"
9459       case 6'000010
9460         assign { } { }
9461         assign $1\sgn[0:0] 1'0
9462       attribute \src "libresoc.v:0.0-0.0"
9463       case 6'000011
9464         assign { } { }
9465         assign $1\sgn[0:0] 1'0
9466       attribute \src "libresoc.v:0.0-0.0"
9467       case 6'011010
9468         assign { } { }
9469         assign $1\sgn[0:0] 1'0
9470       attribute \src "libresoc.v:0.0-0.0"
9471       case 6'011011
9472         assign { } { }
9473         assign $1\sgn[0:0] 1'0
9474       case
9475         assign $1\sgn[0:0] 1'0
9476     end
9477     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9478     switch \opcode_switch$1
9479       attribute \src "libresoc.v:0.0-0.0"
9480       case 32'000000---------------0100000000-
9481         assign { } { }
9482         assign $2\sgn[0:0] 1'0
9483       attribute \src "libresoc.v:0.0-0.0"
9484       case 1610612736
9485         assign { } { }
9486         assign $2\sgn[0:0] 1'0
9487       attribute \src "libresoc.v:0.0-0.0"
9488       case 32'000001---------------0000000011-
9489         assign { } { }
9490         assign $2\sgn[0:0] 1'0
9491       case
9492         assign $2\sgn[0:0] $1\sgn[0:0]
9493     end
9494     sync always
9495       update \sgn $0\sgn[0:0]
9496   end
9497   attribute \src "libresoc.v:6080.3-6221.6"
9498   process $proc$libresoc.v:6080$257
9499     assign { } { }
9500     assign { } { }
9501     assign { } { }
9502     assign $0\lk[0:0] $2\lk[0:0]
9503     attribute \src "libresoc.v:6081.5-6081.29"
9504     switch \initial
9505       attribute \src "libresoc.v:6081.9-6081.17"
9506       case 1'1
9507       case
9508     end
9509     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9510     switch \opcode_switch
9511       attribute \src "libresoc.v:0.0-0.0"
9512       case 6'010011
9513         assign { } { }
9514         assign $1\lk[0:0] \dec19_dec19_lk
9515       attribute \src "libresoc.v:0.0-0.0"
9516       case 6'011110
9517         assign { } { }
9518         assign $1\lk[0:0] \dec30_dec30_lk
9519       attribute \src "libresoc.v:0.0-0.0"
9520       case 6'011111
9521         assign { } { }
9522         assign $1\lk[0:0] \dec31_dec31_lk
9523       attribute \src "libresoc.v:0.0-0.0"
9524       case 6'111010
9525         assign { } { }
9526         assign $1\lk[0:0] \dec58_dec58_lk
9527       attribute \src "libresoc.v:0.0-0.0"
9528       case 6'111110
9529         assign { } { }
9530         assign $1\lk[0:0] \dec62_dec62_lk
9531       attribute \src "libresoc.v:0.0-0.0"
9532       case 6'001100
9533         assign { } { }
9534         assign $1\lk[0:0] 1'0
9535       attribute \src "libresoc.v:0.0-0.0"
9536       case 6'001101
9537         assign { } { }
9538         assign $1\lk[0:0] 1'0
9539       attribute \src "libresoc.v:0.0-0.0"
9540       case 6'001110
9541         assign { } { }
9542         assign $1\lk[0:0] 1'0
9543       attribute \src "libresoc.v:0.0-0.0"
9544       case 6'001111
9545         assign { } { }
9546         assign $1\lk[0:0] 1'0
9547       attribute \src "libresoc.v:0.0-0.0"
9548       case 6'010001
9549         assign { } { }
9550         assign $1\lk[0:0] 1'0
9551       attribute \src "libresoc.v:0.0-0.0"
9552       case 6'011100
9553         assign { } { }
9554         assign $1\lk[0:0] 1'0
9555       attribute \src "libresoc.v:0.0-0.0"
9556       case 6'011101
9557         assign { } { }
9558         assign $1\lk[0:0] 1'0
9559       attribute \src "libresoc.v:0.0-0.0"
9560       case 6'010010
9561         assign { } { }
9562         assign $1\lk[0:0] 1'1
9563       attribute \src "libresoc.v:0.0-0.0"
9564       case 6'010000
9565         assign { } { }
9566         assign $1\lk[0:0] 1'1
9567       attribute \src "libresoc.v:0.0-0.0"
9568       case 6'001011
9569         assign { } { }
9570         assign $1\lk[0:0] 1'0
9571       attribute \src "libresoc.v:0.0-0.0"
9572       case 6'001010
9573         assign { } { }
9574         assign $1\lk[0:0] 1'0
9575       attribute \src "libresoc.v:0.0-0.0"
9576       case 6'100010
9577         assign { } { }
9578         assign $1\lk[0:0] 1'0
9579       attribute \src "libresoc.v:0.0-0.0"
9580       case 6'100011
9581         assign { } { }
9582         assign $1\lk[0:0] 1'0
9583       attribute \src "libresoc.v:0.0-0.0"
9584       case 6'101010
9585         assign { } { }
9586         assign $1\lk[0:0] 1'0
9587       attribute \src "libresoc.v:0.0-0.0"
9588       case 6'101011
9589         assign { } { }
9590         assign $1\lk[0:0] 1'0
9591       attribute \src "libresoc.v:0.0-0.0"
9592       case 6'101000
9593         assign { } { }
9594         assign $1\lk[0:0] 1'0
9595       attribute \src "libresoc.v:0.0-0.0"
9596       case 6'101001
9597         assign { } { }
9598         assign $1\lk[0:0] 1'0
9599       attribute \src "libresoc.v:0.0-0.0"
9600       case 6'100000
9601         assign { } { }
9602         assign $1\lk[0:0] 1'0
9603       attribute \src "libresoc.v:0.0-0.0"
9604       case 6'100001
9605         assign { } { }
9606         assign $1\lk[0:0] 1'0
9607       attribute \src "libresoc.v:0.0-0.0"
9608       case 6'000111
9609         assign { } { }
9610         assign $1\lk[0:0] 1'0
9611       attribute \src "libresoc.v:0.0-0.0"
9612       case 6'011000
9613         assign { } { }
9614         assign $1\lk[0:0] 1'0
9615       attribute \src "libresoc.v:0.0-0.0"
9616       case 6'011001
9617         assign { } { }
9618         assign $1\lk[0:0] 1'0
9619       attribute \src "libresoc.v:0.0-0.0"
9620       case 6'010100
9621         assign { } { }
9622         assign $1\lk[0:0] 1'0
9623       attribute \src "libresoc.v:0.0-0.0"
9624       case 6'010101
9625         assign { } { }
9626         assign $1\lk[0:0] 1'0
9627       attribute \src "libresoc.v:0.0-0.0"
9628       case 6'010111
9629         assign { } { }
9630         assign $1\lk[0:0] 1'0
9631       attribute \src "libresoc.v:0.0-0.0"
9632       case 6'100110
9633         assign { } { }
9634         assign $1\lk[0:0] 1'0
9635       attribute \src "libresoc.v:0.0-0.0"
9636       case 6'100111
9637         assign { } { }
9638         assign $1\lk[0:0] 1'0
9639       attribute \src "libresoc.v:0.0-0.0"
9640       case 6'101100
9641         assign { } { }
9642         assign $1\lk[0:0] 1'0
9643       attribute \src "libresoc.v:0.0-0.0"
9644       case 6'101101
9645         assign { } { }
9646         assign $1\lk[0:0] 1'0
9647       attribute \src "libresoc.v:0.0-0.0"
9648       case 6'100100
9649         assign { } { }
9650         assign $1\lk[0:0] 1'0
9651       attribute \src "libresoc.v:0.0-0.0"
9652       case 6'100101
9653         assign { } { }
9654         assign $1\lk[0:0] 1'0
9655       attribute \src "libresoc.v:0.0-0.0"
9656       case 6'001000
9657         assign { } { }
9658         assign $1\lk[0:0] 1'0
9659       attribute \src "libresoc.v:0.0-0.0"
9660       case 6'000010
9661         assign { } { }
9662         assign $1\lk[0:0] 1'0
9663       attribute \src "libresoc.v:0.0-0.0"
9664       case 6'000011
9665         assign { } { }
9666         assign $1\lk[0:0] 1'0
9667       attribute \src "libresoc.v:0.0-0.0"
9668       case 6'011010
9669         assign { } { }
9670         assign $1\lk[0:0] 1'0
9671       attribute \src "libresoc.v:0.0-0.0"
9672       case 6'011011
9673         assign { } { }
9674         assign $1\lk[0:0] 1'0
9675       case
9676         assign $1\lk[0:0] 1'0
9677     end
9678     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9679     switch \opcode_switch$1
9680       attribute \src "libresoc.v:0.0-0.0"
9681       case 32'000000---------------0100000000-
9682         assign { } { }
9683         assign $2\lk[0:0] 1'0
9684       attribute \src "libresoc.v:0.0-0.0"
9685       case 1610612736
9686         assign { } { }
9687         assign $2\lk[0:0] 1'0
9688       attribute \src "libresoc.v:0.0-0.0"
9689       case 32'000001---------------0000000011-
9690         assign { } { }
9691         assign $2\lk[0:0] 1'0
9692       case
9693         assign $2\lk[0:0] $1\lk[0:0]
9694     end
9695     sync always
9696       update \lk $0\lk[0:0]
9697   end
9698   attribute \src "libresoc.v:6222.3-6363.6"
9699   process $proc$libresoc.v:6222$258
9700     assign { } { }
9701     assign { } { }
9702     assign { } { }
9703     assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0]
9704     attribute \src "libresoc.v:6223.5-6223.29"
9705     switch \initial
9706       attribute \src "libresoc.v:6223.9-6223.17"
9707       case 1'1
9708       case
9709     end
9710     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9711     switch \opcode_switch
9712       attribute \src "libresoc.v:0.0-0.0"
9713       case 6'010011
9714         assign { } { }
9715         assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe
9716       attribute \src "libresoc.v:0.0-0.0"
9717       case 6'011110
9718         assign { } { }
9719         assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe
9720       attribute \src "libresoc.v:0.0-0.0"
9721       case 6'011111
9722         assign { } { }
9723         assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe
9724       attribute \src "libresoc.v:0.0-0.0"
9725       case 6'111010
9726         assign { } { }
9727         assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe
9728       attribute \src "libresoc.v:0.0-0.0"
9729       case 6'111110
9730         assign { } { }
9731         assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe
9732       attribute \src "libresoc.v:0.0-0.0"
9733       case 6'001100
9734         assign { } { }
9735         assign $1\sgl_pipe[0:0] 1'0
9736       attribute \src "libresoc.v:0.0-0.0"
9737       case 6'001101
9738         assign { } { }
9739         assign $1\sgl_pipe[0:0] 1'0
9740       attribute \src "libresoc.v:0.0-0.0"
9741       case 6'001110
9742         assign { } { }
9743         assign $1\sgl_pipe[0:0] 1'0
9744       attribute \src "libresoc.v:0.0-0.0"
9745       case 6'001111
9746         assign { } { }
9747         assign $1\sgl_pipe[0:0] 1'0
9748       attribute \src "libresoc.v:0.0-0.0"
9749       case 6'010001
9750         assign { } { }
9751         assign $1\sgl_pipe[0:0] 1'0
9752       attribute \src "libresoc.v:0.0-0.0"
9753       case 6'011100
9754         assign { } { }
9755         assign $1\sgl_pipe[0:0] 1'0
9756       attribute \src "libresoc.v:0.0-0.0"
9757       case 6'011101
9758         assign { } { }
9759         assign $1\sgl_pipe[0:0] 1'0
9760       attribute \src "libresoc.v:0.0-0.0"
9761       case 6'010010
9762         assign { } { }
9763         assign $1\sgl_pipe[0:0] 1'0
9764       attribute \src "libresoc.v:0.0-0.0"
9765       case 6'010000
9766         assign { } { }
9767         assign $1\sgl_pipe[0:0] 1'0
9768       attribute \src "libresoc.v:0.0-0.0"
9769       case 6'001011
9770         assign { } { }
9771         assign $1\sgl_pipe[0:0] 1'0
9772       attribute \src "libresoc.v:0.0-0.0"
9773       case 6'001010
9774         assign { } { }
9775         assign $1\sgl_pipe[0:0] 1'0
9776       attribute \src "libresoc.v:0.0-0.0"
9777       case 6'100010
9778         assign { } { }
9779         assign $1\sgl_pipe[0:0] 1'1
9780       attribute \src "libresoc.v:0.0-0.0"
9781       case 6'100011
9782         assign { } { }
9783         assign $1\sgl_pipe[0:0] 1'1
9784       attribute \src "libresoc.v:0.0-0.0"
9785       case 6'101010
9786         assign { } { }
9787         assign $1\sgl_pipe[0:0] 1'1
9788       attribute \src "libresoc.v:0.0-0.0"
9789       case 6'101011
9790         assign { } { }
9791         assign $1\sgl_pipe[0:0] 1'1
9792       attribute \src "libresoc.v:0.0-0.0"
9793       case 6'101000
9794         assign { } { }
9795         assign $1\sgl_pipe[0:0] 1'1
9796       attribute \src "libresoc.v:0.0-0.0"
9797       case 6'101001
9798         assign { } { }
9799         assign $1\sgl_pipe[0:0] 1'1
9800       attribute \src "libresoc.v:0.0-0.0"
9801       case 6'100000
9802         assign { } { }
9803         assign $1\sgl_pipe[0:0] 1'1
9804       attribute \src "libresoc.v:0.0-0.0"
9805       case 6'100001
9806         assign { } { }
9807         assign $1\sgl_pipe[0:0] 1'1
9808       attribute \src "libresoc.v:0.0-0.0"
9809       case 6'000111
9810         assign { } { }
9811         assign $1\sgl_pipe[0:0] 1'0
9812       attribute \src "libresoc.v:0.0-0.0"
9813       case 6'011000
9814         assign { } { }
9815         assign $1\sgl_pipe[0:0] 1'0
9816       attribute \src "libresoc.v:0.0-0.0"
9817       case 6'011001
9818         assign { } { }
9819         assign $1\sgl_pipe[0:0] 1'0
9820       attribute \src "libresoc.v:0.0-0.0"
9821       case 6'010100
9822         assign { } { }
9823         assign $1\sgl_pipe[0:0] 1'0
9824       attribute \src "libresoc.v:0.0-0.0"
9825       case 6'010101
9826         assign { } { }
9827         assign $1\sgl_pipe[0:0] 1'0
9828       attribute \src "libresoc.v:0.0-0.0"
9829       case 6'010111
9830         assign { } { }
9831         assign $1\sgl_pipe[0:0] 1'0
9832       attribute \src "libresoc.v:0.0-0.0"
9833       case 6'100110
9834         assign { } { }
9835         assign $1\sgl_pipe[0:0] 1'1
9836       attribute \src "libresoc.v:0.0-0.0"
9837       case 6'100111
9838         assign { } { }
9839         assign $1\sgl_pipe[0:0] 1'1
9840       attribute \src "libresoc.v:0.0-0.0"
9841       case 6'101100
9842         assign { } { }
9843         assign $1\sgl_pipe[0:0] 1'1
9844       attribute \src "libresoc.v:0.0-0.0"
9845       case 6'101101
9846         assign { } { }
9847         assign $1\sgl_pipe[0:0] 1'1
9848       attribute \src "libresoc.v:0.0-0.0"
9849       case 6'100100
9850         assign { } { }
9851         assign $1\sgl_pipe[0:0] 1'1
9852       attribute \src "libresoc.v:0.0-0.0"
9853       case 6'100101
9854         assign { } { }
9855         assign $1\sgl_pipe[0:0] 1'1
9856       attribute \src "libresoc.v:0.0-0.0"
9857       case 6'001000
9858         assign { } { }
9859         assign $1\sgl_pipe[0:0] 1'0
9860       attribute \src "libresoc.v:0.0-0.0"
9861       case 6'000010
9862         assign { } { }
9863         assign $1\sgl_pipe[0:0] 1'1
9864       attribute \src "libresoc.v:0.0-0.0"
9865       case 6'000011
9866         assign { } { }
9867         assign $1\sgl_pipe[0:0] 1'1
9868       attribute \src "libresoc.v:0.0-0.0"
9869       case 6'011010
9870         assign { } { }
9871         assign $1\sgl_pipe[0:0] 1'0
9872       attribute \src "libresoc.v:0.0-0.0"
9873       case 6'011011
9874         assign { } { }
9875         assign $1\sgl_pipe[0:0] 1'0
9876       case
9877         assign $1\sgl_pipe[0:0] 1'0
9878     end
9879     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9880     switch \opcode_switch$1
9881       attribute \src "libresoc.v:0.0-0.0"
9882       case 32'000000---------------0100000000-
9883         assign { } { }
9884         assign $2\sgl_pipe[0:0] 1'1
9885       attribute \src "libresoc.v:0.0-0.0"
9886       case 1610612736
9887         assign { } { }
9888         assign $2\sgl_pipe[0:0] 1'0
9889       attribute \src "libresoc.v:0.0-0.0"
9890       case 32'000001---------------0000000011-
9891         assign { } { }
9892         assign $2\sgl_pipe[0:0] 1'1
9893       case
9894         assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0]
9895     end
9896     sync always
9897       update \sgl_pipe $0\sgl_pipe[0:0]
9898   end
9899   attribute \src "libresoc.v:6364.3-6505.6"
9900   process $proc$libresoc.v:6364$259
9901     assign { } { }
9902     assign { } { }
9903     assign { } { }
9904     assign $0\function_unit[11:0] $2\function_unit[11:0]
9905     attribute \src "libresoc.v:6365.5-6365.29"
9906     switch \initial
9907       attribute \src "libresoc.v:6365.9-6365.17"
9908       case 1'1
9909       case
9910     end
9911     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
9912     switch \opcode_switch
9913       attribute \src "libresoc.v:0.0-0.0"
9914       case 6'010011
9915         assign { } { }
9916         assign $1\function_unit[11:0] \dec19_dec19_function_unit
9917       attribute \src "libresoc.v:0.0-0.0"
9918       case 6'011110
9919         assign { } { }
9920         assign $1\function_unit[11:0] \dec30_dec30_function_unit
9921       attribute \src "libresoc.v:0.0-0.0"
9922       case 6'011111
9923         assign { } { }
9924         assign $1\function_unit[11:0] \dec31_dec31_function_unit
9925       attribute \src "libresoc.v:0.0-0.0"
9926       case 6'111010
9927         assign { } { }
9928         assign $1\function_unit[11:0] \dec58_dec58_function_unit
9929       attribute \src "libresoc.v:0.0-0.0"
9930       case 6'111110
9931         assign { } { }
9932         assign $1\function_unit[11:0] \dec62_dec62_function_unit
9933       attribute \src "libresoc.v:0.0-0.0"
9934       case 6'001100
9935         assign { } { }
9936         assign $1\function_unit[11:0] 12'000000000010
9937       attribute \src "libresoc.v:0.0-0.0"
9938       case 6'001101
9939         assign { } { }
9940         assign $1\function_unit[11:0] 12'000000000010
9941       attribute \src "libresoc.v:0.0-0.0"
9942       case 6'001110
9943         assign { } { }
9944         assign $1\function_unit[11:0] 12'000000000010
9945       attribute \src "libresoc.v:0.0-0.0"
9946       case 6'001111
9947         assign { } { }
9948         assign $1\function_unit[11:0] 12'000000000010
9949       attribute \src "libresoc.v:0.0-0.0"
9950       case 6'010001
9951         assign { } { }
9952         assign $1\function_unit[11:0] 12'000010000000
9953       attribute \src "libresoc.v:0.0-0.0"
9954       case 6'011100
9955         assign { } { }
9956         assign $1\function_unit[11:0] 12'000000010000
9957       attribute \src "libresoc.v:0.0-0.0"
9958       case 6'011101
9959         assign { } { }
9960         assign $1\function_unit[11:0] 12'000000010000
9961       attribute \src "libresoc.v:0.0-0.0"
9962       case 6'010010
9963         assign { } { }
9964         assign $1\function_unit[11:0] 12'000000100000
9965       attribute \src "libresoc.v:0.0-0.0"
9966       case 6'010000
9967         assign { } { }
9968         assign $1\function_unit[11:0] 12'000000100000
9969       attribute \src "libresoc.v:0.0-0.0"
9970       case 6'001011
9971         assign { } { }
9972         assign $1\function_unit[11:0] 12'000000000010
9973       attribute \src "libresoc.v:0.0-0.0"
9974       case 6'001010
9975         assign { } { }
9976         assign $1\function_unit[11:0] 12'000000000010
9977       attribute \src "libresoc.v:0.0-0.0"
9978       case 6'100010
9979         assign { } { }
9980         assign $1\function_unit[11:0] 12'000000000100
9981       attribute \src "libresoc.v:0.0-0.0"
9982       case 6'100011
9983         assign { } { }
9984         assign $1\function_unit[11:0] 12'000000000100
9985       attribute \src "libresoc.v:0.0-0.0"
9986       case 6'101010
9987         assign { } { }
9988         assign $1\function_unit[11:0] 12'000000000100
9989       attribute \src "libresoc.v:0.0-0.0"
9990       case 6'101011
9991         assign { } { }
9992         assign $1\function_unit[11:0] 12'000000000100
9993       attribute \src "libresoc.v:0.0-0.0"
9994       case 6'101000
9995         assign { } { }
9996         assign $1\function_unit[11:0] 12'000000000100
9997       attribute \src "libresoc.v:0.0-0.0"
9998       case 6'101001
9999         assign { } { }
10000         assign $1\function_unit[11:0] 12'000000000100
10001       attribute \src "libresoc.v:0.0-0.0"
10002       case 6'100000
10003         assign { } { }
10004         assign $1\function_unit[11:0] 12'000000000100
10005       attribute \src "libresoc.v:0.0-0.0"
10006       case 6'100001
10007         assign { } { }
10008         assign $1\function_unit[11:0] 12'000000000100
10009       attribute \src "libresoc.v:0.0-0.0"
10010       case 6'000111
10011         assign { } { }
10012         assign $1\function_unit[11:0] 12'000100000000
10013       attribute \src "libresoc.v:0.0-0.0"
10014       case 6'011000
10015         assign { } { }
10016         assign $1\function_unit[11:0] 12'000000010000
10017       attribute \src "libresoc.v:0.0-0.0"
10018       case 6'011001
10019         assign { } { }
10020         assign $1\function_unit[11:0] 12'000000010000
10021       attribute \src "libresoc.v:0.0-0.0"
10022       case 6'010100
10023         assign { } { }
10024         assign $1\function_unit[11:0] 12'000000001000
10025       attribute \src "libresoc.v:0.0-0.0"
10026       case 6'010101
10027         assign { } { }
10028         assign $1\function_unit[11:0] 12'000000001000
10029       attribute \src "libresoc.v:0.0-0.0"
10030       case 6'010111
10031         assign { } { }
10032         assign $1\function_unit[11:0] 12'000000001000
10033       attribute \src "libresoc.v:0.0-0.0"
10034       case 6'100110
10035         assign { } { }
10036         assign $1\function_unit[11:0] 12'000000000100
10037       attribute \src "libresoc.v:0.0-0.0"
10038       case 6'100111
10039         assign { } { }
10040         assign $1\function_unit[11:0] 12'000000000100
10041       attribute \src "libresoc.v:0.0-0.0"
10042       case 6'101100
10043         assign { } { }
10044         assign $1\function_unit[11:0] 12'000000000100
10045       attribute \src "libresoc.v:0.0-0.0"
10046       case 6'101101
10047         assign { } { }
10048         assign $1\function_unit[11:0] 12'000000000100
10049       attribute \src "libresoc.v:0.0-0.0"
10050       case 6'100100
10051         assign { } { }
10052         assign $1\function_unit[11:0] 12'000000000100
10053       attribute \src "libresoc.v:0.0-0.0"
10054       case 6'100101
10055         assign { } { }
10056         assign $1\function_unit[11:0] 12'000000000100
10057       attribute \src "libresoc.v:0.0-0.0"
10058       case 6'001000
10059         assign { } { }
10060         assign $1\function_unit[11:0] 12'000000000010
10061       attribute \src "libresoc.v:0.0-0.0"
10062       case 6'000010
10063         assign { } { }
10064         assign $1\function_unit[11:0] 12'000010000000
10065       attribute \src "libresoc.v:0.0-0.0"
10066       case 6'000011
10067         assign { } { }
10068         assign $1\function_unit[11:0] 12'000010000000
10069       attribute \src "libresoc.v:0.0-0.0"
10070       case 6'011010
10071         assign { } { }
10072         assign $1\function_unit[11:0] 12'000000010000
10073       attribute \src "libresoc.v:0.0-0.0"
10074       case 6'011011
10075         assign { } { }
10076         assign $1\function_unit[11:0] 12'000000010000
10077       case
10078         assign $1\function_unit[11:0] 12'000000000000
10079     end
10080     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
10081     switch \opcode_switch$1
10082       attribute \src "libresoc.v:0.0-0.0"
10083       case 32'000000---------------0100000000-
10084         assign { } { }
10085         assign $2\function_unit[11:0] 12'000000000000
10086       attribute \src "libresoc.v:0.0-0.0"
10087       case 1610612736
10088         assign { } { }
10089         assign $2\function_unit[11:0] 12'000000000000
10090       attribute \src "libresoc.v:0.0-0.0"
10091       case 32'000001---------------0000000011-
10092         assign { } { }
10093         assign $2\function_unit[11:0] 12'000000000000
10094       case
10095         assign $2\function_unit[11:0] $1\function_unit[11:0]
10096     end
10097     sync always
10098       update \function_unit $0\function_unit[11:0]
10099   end
10100   attribute \src "libresoc.v:6506.3-6647.6"
10101   process $proc$libresoc.v:6506$260
10102     assign { } { }
10103     assign { } { }
10104     assign { } { }
10105     assign $0\internal_op[6:0] $2\internal_op[6:0]
10106     attribute \src "libresoc.v:6507.5-6507.29"
10107     switch \initial
10108       attribute \src "libresoc.v:6507.9-6507.17"
10109       case 1'1
10110       case
10111     end
10112     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
10113     switch \opcode_switch
10114       attribute \src "libresoc.v:0.0-0.0"
10115       case 6'010011
10116         assign { } { }
10117         assign $1\internal_op[6:0] \dec19_dec19_internal_op
10118       attribute \src "libresoc.v:0.0-0.0"
10119       case 6'011110
10120         assign { } { }
10121         assign $1\internal_op[6:0] \dec30_dec30_internal_op
10122       attribute \src "libresoc.v:0.0-0.0"
10123       case 6'011111
10124         assign { } { }
10125         assign $1\internal_op[6:0] \dec31_dec31_internal_op
10126       attribute \src "libresoc.v:0.0-0.0"
10127       case 6'111010
10128         assign { } { }
10129         assign $1\internal_op[6:0] \dec58_dec58_internal_op
10130       attribute \src "libresoc.v:0.0-0.0"
10131       case 6'111110
10132         assign { } { }
10133         assign $1\internal_op[6:0] \dec62_dec62_internal_op
10134       attribute \src "libresoc.v:0.0-0.0"
10135       case 6'001100
10136         assign { } { }
10137         assign $1\internal_op[6:0] 7'0000010
10138       attribute \src "libresoc.v:0.0-0.0"
10139       case 6'001101
10140         assign { } { }
10141         assign $1\internal_op[6:0] 7'0000010
10142       attribute \src "libresoc.v:0.0-0.0"
10143       case 6'001110
10144         assign { } { }
10145         assign $1\internal_op[6:0] 7'0000010
10146       attribute \src "libresoc.v:0.0-0.0"
10147       case 6'001111
10148         assign { } { }
10149         assign $1\internal_op[6:0] 7'0000010
10150       attribute \src "libresoc.v:0.0-0.0"
10151       case 6'010001
10152         assign { } { }
10153         assign $1\internal_op[6:0] 7'1001001
10154       attribute \src "libresoc.v:0.0-0.0"
10155       case 6'011100
10156         assign { } { }
10157         assign $1\internal_op[6:0] 7'0000100
10158       attribute \src "libresoc.v:0.0-0.0"
10159       case 6'011101
10160         assign { } { }
10161         assign $1\internal_op[6:0] 7'0000100
10162       attribute \src "libresoc.v:0.0-0.0"
10163       case 6'010010
10164         assign { } { }
10165         assign $1\internal_op[6:0] 7'0000110
10166       attribute \src "libresoc.v:0.0-0.0"
10167       case 6'010000
10168         assign { } { }
10169         assign $1\internal_op[6:0] 7'0000111
10170       attribute \src "libresoc.v:0.0-0.0"
10171       case 6'001011
10172         assign { } { }
10173         assign $1\internal_op[6:0] 7'0001010
10174       attribute \src "libresoc.v:0.0-0.0"
10175       case 6'001010
10176         assign { } { }
10177         assign $1\internal_op[6:0] 7'0001010
10178       attribute \src "libresoc.v:0.0-0.0"
10179       case 6'100010
10180         assign { } { }
10181         assign $1\internal_op[6:0] 7'0100101
10182       attribute \src "libresoc.v:0.0-0.0"
10183       case 6'100011
10184         assign { } { }
10185         assign $1\internal_op[6:0] 7'0100101
10186       attribute \src "libresoc.v:0.0-0.0"
10187       case 6'101010
10188         assign { } { }
10189         assign $1\internal_op[6:0] 7'0100101
10190       attribute \src "libresoc.v:0.0-0.0"
10191       case 6'101011
10192         assign { } { }
10193         assign $1\internal_op[6:0] 7'0100101
10194       attribute \src "libresoc.v:0.0-0.0"
10195       case 6'101000
10196         assign { } { }
10197         assign $1\internal_op[6:0] 7'0100101
10198       attribute \src "libresoc.v:0.0-0.0"
10199       case 6'101001
10200         assign { } { }
10201         assign $1\internal_op[6:0] 7'0100101
10202       attribute \src "libresoc.v:0.0-0.0"
10203       case 6'100000
10204         assign { } { }
10205         assign $1\internal_op[6:0] 7'0100101
10206       attribute \src "libresoc.v:0.0-0.0"
10207       case 6'100001
10208         assign { } { }
10209         assign $1\internal_op[6:0] 7'0100101
10210       attribute \src "libresoc.v:0.0-0.0"
10211       case 6'000111
10212         assign { } { }
10213         assign $1\internal_op[6:0] 7'0110010
10214       attribute \src "libresoc.v:0.0-0.0"
10215       case 6'011000
10216         assign { } { }
10217         assign $1\internal_op[6:0] 7'0110101
10218       attribute \src "libresoc.v:0.0-0.0"
10219       case 6'011001
10220         assign { } { }
10221         assign $1\internal_op[6:0] 7'0110101
10222       attribute \src "libresoc.v:0.0-0.0"
10223       case 6'010100
10224         assign { } { }
10225         assign $1\internal_op[6:0] 7'0111000
10226       attribute \src "libresoc.v:0.0-0.0"
10227       case 6'010101
10228         assign { } { }
10229         assign $1\internal_op[6:0] 7'0111000
10230       attribute \src "libresoc.v:0.0-0.0"
10231       case 6'010111
10232         assign { } { }
10233         assign $1\internal_op[6:0] 7'0111000
10234       attribute \src "libresoc.v:0.0-0.0"
10235       case 6'100110
10236         assign { } { }
10237         assign $1\internal_op[6:0] 7'0100110
10238       attribute \src "libresoc.v:0.0-0.0"
10239       case 6'100111
10240         assign { } { }
10241         assign $1\internal_op[6:0] 7'0100110
10242       attribute \src "libresoc.v:0.0-0.0"
10243       case 6'101100
10244         assign { } { }
10245         assign $1\internal_op[6:0] 7'0100110
10246       attribute \src "libresoc.v:0.0-0.0"
10247       case 6'101101
10248         assign { } { }
10249         assign $1\internal_op[6:0] 7'0100110
10250       attribute \src "libresoc.v:0.0-0.0"
10251       case 6'100100
10252         assign { } { }
10253         assign $1\internal_op[6:0] 7'0100110
10254       attribute \src "libresoc.v:0.0-0.0"
10255       case 6'100101
10256         assign { } { }
10257         assign $1\internal_op[6:0] 7'0100110
10258       attribute \src "libresoc.v:0.0-0.0"
10259       case 6'001000
10260         assign { } { }
10261         assign $1\internal_op[6:0] 7'0000010
10262       attribute \src "libresoc.v:0.0-0.0"
10263       case 6'000010
10264         assign { } { }
10265         assign $1\internal_op[6:0] 7'0111111
10266       attribute \src "libresoc.v:0.0-0.0"
10267       case 6'000011
10268         assign { } { }
10269         assign $1\internal_op[6:0] 7'0111111
10270       attribute \src "libresoc.v:0.0-0.0"
10271       case 6'011010
10272         assign { } { }
10273         assign $1\internal_op[6:0] 7'1000011
10274       attribute \src "libresoc.v:0.0-0.0"
10275       case 6'011011
10276         assign { } { }
10277         assign $1\internal_op[6:0] 7'1000011
10278       case
10279         assign $1\internal_op[6:0] 7'0000000
10280     end
10281     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
10282     switch \opcode_switch$1
10283       attribute \src "libresoc.v:0.0-0.0"
10284       case 32'000000---------------0100000000-
10285         assign { } { }
10286         assign $2\internal_op[6:0] 7'0000101
10287       attribute \src "libresoc.v:0.0-0.0"
10288       case 1610612736
10289         assign { } { }
10290         assign $2\internal_op[6:0] 7'0000001
10291       attribute \src "libresoc.v:0.0-0.0"
10292       case 32'000001---------------0000000011-
10293         assign { } { }
10294         assign $2\internal_op[6:0] 7'1000100
10295       case
10296         assign $2\internal_op[6:0] $1\internal_op[6:0]
10297     end
10298     sync always
10299       update \internal_op $0\internal_op[6:0]
10300   end
10301   attribute \src "libresoc.v:6648.3-6789.6"
10302   process $proc$libresoc.v:6648$261
10303     assign { } { }
10304     assign { } { }
10305     assign { } { }
10306     assign $0\form[4:0] $2\form[4:0]
10307     attribute \src "libresoc.v:6649.5-6649.29"
10308     switch \initial
10309       attribute \src "libresoc.v:6649.9-6649.17"
10310       case 1'1
10311       case
10312     end
10313     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
10314     switch \opcode_switch
10315       attribute \src "libresoc.v:0.0-0.0"
10316       case 6'010011
10317         assign { } { }
10318         assign $1\form[4:0] \dec19_dec19_form
10319       attribute \src "libresoc.v:0.0-0.0"
10320       case 6'011110
10321         assign { } { }
10322         assign $1\form[4:0] \dec30_dec30_form
10323       attribute \src "libresoc.v:0.0-0.0"
10324       case 6'011111
10325         assign { } { }
10326         assign $1\form[4:0] \dec31_dec31_form
10327       attribute \src "libresoc.v:0.0-0.0"
10328       case 6'111010
10329         assign { } { }
10330         assign $1\form[4:0] \dec58_dec58_form
10331       attribute \src "libresoc.v:0.0-0.0"
10332       case 6'111110
10333         assign { } { }
10334         assign $1\form[4:0] \dec62_dec62_form
10335       attribute \src "libresoc.v:0.0-0.0"
10336       case 6'001100
10337         assign { } { }
10338         assign $1\form[4:0] 5'00100
10339       attribute \src "libresoc.v:0.0-0.0"
10340       case 6'001101
10341         assign { } { }
10342         assign $1\form[4:0] 5'00100
10343       attribute \src "libresoc.v:0.0-0.0"
10344       case 6'001110
10345         assign { } { }
10346         assign $1\form[4:0] 5'00100
10347       attribute \src "libresoc.v:0.0-0.0"
10348       case 6'001111
10349         assign { } { }
10350         assign $1\form[4:0] 5'00100
10351       attribute \src "libresoc.v:0.0-0.0"
10352       case 6'010001
10353         assign { } { }
10354         assign $1\form[4:0] 5'00011
10355       attribute \src "libresoc.v:0.0-0.0"
10356       case 6'011100
10357         assign { } { }
10358         assign $1\form[4:0] 5'00010
10359       attribute \src "libresoc.v:0.0-0.0"
10360       case 6'011101
10361         assign { } { }
10362         assign $1\form[4:0] 5'00010
10363       attribute \src "libresoc.v:0.0-0.0"
10364       case 6'010010
10365         assign { } { }
10366         assign $1\form[4:0] 5'00001
10367       attribute \src "libresoc.v:0.0-0.0"
10368       case 6'010000
10369         assign { } { }
10370         assign $1\form[4:0] 5'00010
10371       attribute \src "libresoc.v:0.0-0.0"
10372       case 6'001011
10373         assign { } { }
10374         assign $1\form[4:0] 5'00100
10375       attribute \src "libresoc.v:0.0-0.0"
10376       case 6'001010
10377         assign { } { }
10378         assign $1\form[4:0] 5'00100
10379       attribute \src "libresoc.v:0.0-0.0"
10380       case 6'100010
10381         assign { } { }
10382         assign $1\form[4:0] 5'00100
10383       attribute \src "libresoc.v:0.0-0.0"
10384       case 6'100011
10385         assign { } { }
10386         assign $1\form[4:0] 5'00100
10387       attribute \src "libresoc.v:0.0-0.0"
10388       case 6'101010
10389         assign { } { }
10390         assign $1\form[4:0] 5'00100
10391       attribute \src "libresoc.v:0.0-0.0"
10392       case 6'101011
10393         assign { } { }
10394         assign $1\form[4:0] 5'00100
10395       attribute \src "libresoc.v:0.0-0.0"
10396       case 6'101000
10397         assign { } { }
10398         assign $1\form[4:0] 5'00100
10399       attribute \src "libresoc.v:0.0-0.0"
10400       case 6'101001
10401         assign { } { }
10402         assign $1\form[4:0] 5'00100
10403       attribute \src "libresoc.v:0.0-0.0"
10404       case 6'100000
10405         assign { } { }
10406         assign $1\form[4:0] 5'00100
10407       attribute \src "libresoc.v:0.0-0.0"
10408       case 6'100001
10409         assign { } { }
10410         assign $1\form[4:0] 5'00100
10411       attribute \src "libresoc.v:0.0-0.0"
10412       case 6'000111
10413         assign { } { }
10414         assign $1\form[4:0] 5'00100
10415       attribute \src "libresoc.v:0.0-0.0"
10416       case 6'011000
10417         assign { } { }
10418         assign $1\form[4:0] 5'00100
10419       attribute \src "libresoc.v:0.0-0.0"
10420       case 6'011001
10421         assign { } { }
10422         assign $1\form[4:0] 5'00100
10423       attribute \src "libresoc.v:0.0-0.0"
10424       case 6'010100
10425         assign { } { }
10426         assign $1\form[4:0] 5'10011
10427       attribute \src "libresoc.v:0.0-0.0"
10428       case 6'010101
10429         assign { } { }
10430         assign $1\form[4:0] 5'10011
10431       attribute \src "libresoc.v:0.0-0.0"
10432       case 6'010111
10433         assign { } { }
10434         assign $1\form[4:0] 5'10011
10435       attribute \src "libresoc.v:0.0-0.0"
10436       case 6'100110
10437         assign { } { }
10438         assign $1\form[4:0] 5'00100
10439       attribute \src "libresoc.v:0.0-0.0"
10440       case 6'100111
10441         assign { } { }
10442         assign $1\form[4:0] 5'00100
10443       attribute \src "libresoc.v:0.0-0.0"
10444       case 6'101100
10445         assign { } { }
10446         assign $1\form[4:0] 5'00100
10447       attribute \src "libresoc.v:0.0-0.0"
10448       case 6'101101
10449         assign { } { }
10450         assign $1\form[4:0] 5'00100
10451       attribute \src "libresoc.v:0.0-0.0"
10452       case 6'100100
10453         assign { } { }
10454         assign $1\form[4:0] 5'00100
10455       attribute \src "libresoc.v:0.0-0.0"
10456       case 6'100101
10457         assign { } { }
10458         assign $1\form[4:0] 5'00100
10459       attribute \src "libresoc.v:0.0-0.0"
10460       case 6'001000
10461         assign { } { }
10462         assign $1\form[4:0] 5'00100
10463       attribute \src "libresoc.v:0.0-0.0"
10464       case 6'000010
10465         assign { } { }
10466         assign $1\form[4:0] 5'00100
10467       attribute \src "libresoc.v:0.0-0.0"
10468       case 6'000011
10469         assign { } { }
10470         assign $1\form[4:0] 5'00100
10471       attribute \src "libresoc.v:0.0-0.0"
10472       case 6'011010
10473         assign { } { }
10474         assign $1\form[4:0] 5'00100
10475       attribute \src "libresoc.v:0.0-0.0"
10476       case 6'011011
10477         assign { } { }
10478         assign $1\form[4:0] 5'00100
10479       case
10480         assign $1\form[4:0] 5'00000
10481     end
10482     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
10483     switch \opcode_switch$1
10484       attribute \src "libresoc.v:0.0-0.0"
10485       case 32'000000---------------0100000000-
10486         assign { } { }
10487         assign $2\form[4:0] 5'00000
10488       attribute \src "libresoc.v:0.0-0.0"
10489       case 1610612736
10490         assign { } { }
10491         assign $2\form[4:0] 5'00100
10492       attribute \src "libresoc.v:0.0-0.0"
10493       case 32'000001---------------0000000011-
10494         assign { } { }
10495         assign $2\form[4:0] 5'00000
10496       case
10497         assign $2\form[4:0] $1\form[4:0]
10498     end
10499     sync always
10500       update \form $0\form[4:0]
10501   end
10502   connect \$2 $ternary$libresoc.v:3249$237_Y
10503   connect \VC_XO \opcode_in [9:0]
10504   connect \VC_VRT \opcode_in [25:21]
10505   connect \VC_VRB \opcode_in [15:11]
10506   connect \VC_VRA \opcode_in [20:16]
10507   connect \VC_Rc \opcode_in [10]
10508   connect \XS_XO \opcode_in [10:2]
10509   connect \XS_sh { \opcode_in [1] \opcode_in [15:11] }
10510   connect \XS_RS \opcode_in [25:21]
10511   connect \XS_Rc \opcode_in [0]
10512   connect \XS_RA \opcode_in [20:16]
10513   connect \VA_XO \opcode_in [5:0]
10514   connect \VA_VRT \opcode_in [25:21]
10515   connect \VA_VRC \opcode_in [10:6]
10516   connect \VA_VRB \opcode_in [15:11]
10517   connect \VA_VRA \opcode_in [20:16]
10518   connect \VA_SHB \opcode_in [9:6]
10519   connect \VA_RT \opcode_in [25:21]
10520   connect \VA_RC \opcode_in [10:6]
10521   connect \VA_RB \opcode_in [15:11]
10522   connect \VA_RA \opcode_in [20:16]
10523   connect \TX_XO \opcode_in [6:1]
10524   connect \TX_XBI \opcode_in [10:7]
10525   connect \TX_UI \opcode_in [15:11]
10526   connect \TX_RA \opcode_in [20:16]
10527   connect \DQE_XO \opcode_in [1:0]
10528   connect \DQE_RT \opcode_in [25:21]
10529   connect \DQE_RA \opcode_in [20:16]
10530   connect \XO_XO \opcode_in [9:1]
10531   connect \XO_RT \opcode_in [25:21]
10532   connect \XO_Rc \opcode_in [0]
10533   connect \XO_RB \opcode_in [15:11]
10534   connect \XO_RA \opcode_in [20:16]
10535   connect \XO_OE \opcode_in [10]
10536   connect \all_PO \opcode_in [31:26]
10537   connect \all_OPCD \opcode_in [31:26]
10538   connect \MD_XO \opcode_in [4:2]
10539   connect \MD_sh { \opcode_in [1] \opcode_in [15:11] }
10540   connect \MD_RS \opcode_in [25:21]
10541   connect \MD_Rc \opcode_in [0]
10542   connect \MD_RA \opcode_in [20:16]
10543   connect \MD_me \opcode_in [10:5]
10544   connect \MD_mb \opcode_in [10:5]
10545   connect \M_SH \opcode_in [15:11]
10546   connect \M_RS \opcode_in [25:21]
10547   connect \M_Rc \opcode_in [0]
10548   connect \M_RB \opcode_in [15:11]
10549   connect \M_RA \opcode_in [20:16]
10550   connect \M_ME \opcode_in [5:1]
10551   connect \M_MB \opcode_in [10:6]
10552   connect \SC_XO_1 \opcode_in [1:0]
10553   connect \SC_XO \opcode_in [1]
10554   connect \SC_LEV \opcode_in [11:5]
10555   connect \MDS_XO \opcode_in [4:1]
10556   connect \MDS_XBI_1 \opcode_in [10:7]
10557   connect \MDS_XBI \opcode_in [10:7]
10558   connect \MDS_RS \opcode_in [25:21]
10559   connect \MDS_Rc \opcode_in [0]
10560   connect \MDS_RB \opcode_in [15:11]
10561   connect \MDS_RA \opcode_in [20:16]
10562   connect \MDS_me \opcode_in [10:5]
10563   connect \MDS_mb \opcode_in [10:5]
10564   connect \MDS_IS \opcode_in [25:21]
10565   connect \MDS_IB \opcode_in [15:11]
10566   connect \Z23_XO \opcode_in [8:1]
10567   connect \Z23_TE \opcode_in [20:16]
10568   connect \Z23_RMC \opcode_in [10:9]
10569   connect \Z23_Rc \opcode_in [0]
10570   connect \Z23_R \opcode_in [16]
10571   connect \Z23_FRTp \opcode_in [25:21]
10572   connect \Z23_FRT \opcode_in [25:21]
10573   connect \Z23_FRBp \opcode_in [15:11]
10574   connect \Z23_FRB \opcode_in [15:11]
10575   connect \Z23_FRAp \opcode_in [20:16]
10576   connect \Z23_FRA \opcode_in [20:16]
10577   connect \XFL_XO \opcode_in [10:1]
10578   connect \XFL_W \opcode_in [16]
10579   connect \XFL_Rc \opcode_in [0]
10580   connect \XFL_L \opcode_in [25]
10581   connect \XFL_FRB \opcode_in [15:11]
10582   connect \XFL_FLM \opcode_in [24:17]
10583   connect \VX_XO_1 \opcode_in [10:0]
10584   connect \VX_XO { \opcode_in [10] \opcode_in [8:0] }
10585   connect \VX_VRT \opcode_in [25:21]
10586   connect \VX_VRB \opcode_in [15:11]
10587   connect \VX_VRA \opcode_in [20:16]
10588   connect \VX_UIM_3 \opcode_in [17:16]
10589   connect \VX_UIM_2 \opcode_in [18:16]
10590   connect \VX_UIM_1 \opcode_in [19:16]
10591   connect \VX_UIM \opcode_in [20:16]
10592   connect \VX_SIM \opcode_in [20:16]
10593   connect \VX_RT \opcode_in [25:21]
10594   connect \VX_RA \opcode_in [20:16]
10595   connect \VX_PS \opcode_in [9]
10596   connect \VX_EO \opcode_in [20:16]
10597   connect \DS_XO \opcode_in [1:0]
10598   connect \DS_VRT \opcode_in [25:21]
10599   connect \DS_VRS \opcode_in [25:21]
10600   connect \DS_RT \opcode_in [25:21]
10601   connect \DS_RSp \opcode_in [25:21]
10602   connect \DS_RS \opcode_in [25:21]
10603   connect \DS_RA \opcode_in [20:16]
10604   connect \DS_FRTp \opcode_in [25:21]
10605   connect \DS_FRSp \opcode_in [25:21]
10606   connect \DS_DS \opcode_in [15:2]
10607   connect \DQ_XO \opcode_in [2:0]
10608   connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] }
10609   connect \DQ_T \opcode_in [25:21]
10610   connect \DQ_TX \opcode_in [3]
10611   connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] }
10612   connect \DQ_S \opcode_in [25:21]
10613   connect \DQ_SX \opcode_in [3]
10614   connect \DQ_RTp \opcode_in [25:21]
10615   connect \DQ_RA \opcode_in [20:16]
10616   connect \DQ_PT \opcode_in [3:0]
10617   connect \DQ_DQ \opcode_in [15:4]
10618   connect \DX_XO \opcode_in [5:1]
10619   connect \DX_RT \opcode_in [25:21]
10620   connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] }
10621   connect \DX_d2 \opcode_in [0]
10622   connect \DX_d1 \opcode_in [20:16]
10623   connect \DX_d0 \opcode_in [15:6]
10624   connect \XFX_XO \opcode_in [10:1]
10625   connect \XFX_SPR \opcode_in [20:11]
10626   connect \XFX_RT \opcode_in [25:21]
10627   connect \XFX_RS \opcode_in [25:21]
10628   connect \XFX_FXM \opcode_in [19:12]
10629   connect \XFX_DUIS \opcode_in [20:11]
10630   connect \XFX_DUI \opcode_in [25:21]
10631   connect \XFX_BHRBE \opcode_in [20:11]
10632   connect \EVS_BFA \opcode_in [2:0]
10633   connect \Z22_XO \opcode_in [9:1]
10634   connect \Z22_SH \opcode_in [15:10]
10635   connect \Z22_Rc \opcode_in [0]
10636   connect \Z22_FRTp \opcode_in [25:21]
10637   connect \Z22_FRT \opcode_in [25:21]
10638   connect \Z22_FRAp \opcode_in [20:16]
10639   connect \Z22_FRA \opcode_in [20:16]
10640   connect \Z22_DGM \opcode_in [15:10]
10641   connect \Z22_DCM \opcode_in [15:10]
10642   connect \Z22_BF \opcode_in [25:23]
10643   connect \XX2_XO_1 \opcode_in [10:2]
10644   connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] }
10645   connect \XX2_UIM_1 \opcode_in [17:16]
10646   connect \XX2_UIM \opcode_in [19:16]
10647   connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] }
10648   connect \XX2_T \opcode_in [25:21]
10649   connect \XX2_TX \opcode_in [0]
10650   connect \XX2_RT \opcode_in [25:21]
10651   connect \XX2_EO \opcode_in [20:16]
10652   connect \XX2_DCMX \opcode_in [22:16]
10653   connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] }
10654   connect \XX2_dx \opcode_in [20:16]
10655   connect \XX2_dm \opcode_in [2]
10656   connect \XX2_dc \opcode_in [6]
10657   connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] }
10658   connect \XX2_B \opcode_in [15:11]
10659   connect \XX2_BX \opcode_in [1]
10660   connect \XX2_BF \opcode_in [25:23]
10661   connect \D_UI \opcode_in [15:0]
10662   connect \D_TO \opcode_in [25:21]
10663   connect \D_SI \opcode_in [15:0]
10664   connect \D_RT \opcode_in [25:21]
10665   connect \D_RS \opcode_in [25:21]
10666   connect \D_RA \opcode_in [20:16]
10667   connect \D_L \opcode_in [21]
10668   connect \D_FRT \opcode_in [25:21]
10669   connect \D_FRS \opcode_in [25:21]
10670   connect \D_D \opcode_in [15:0]
10671   connect \D_BF \opcode_in [25:23]
10672   connect \A_XO \opcode_in [5:1]
10673   connect \A_RT \opcode_in [25:21]
10674   connect \A_Rc \opcode_in [0]
10675   connect \A_RB \opcode_in [15:11]
10676   connect \A_RA \opcode_in [20:16]
10677   connect \A_FRT \opcode_in [25:21]
10678   connect \A_FRC \opcode_in [10:6]
10679   connect \A_FRB \opcode_in [15:11]
10680   connect \A_FRA \opcode_in [20:16]
10681   connect \A_BC \opcode_in [10:6]
10682   connect \XL_XO \opcode_in [10:1]
10683   connect \XL_S \opcode_in [11]
10684   connect \XL_OC \opcode_in [25:11]
10685   connect \XL_LK \opcode_in [0]
10686   connect \XL_BT \opcode_in [25:21]
10687   connect \XL_BO_1 \opcode_in [25:21]
10688   connect \XL_BO \opcode_in [25:21]
10689   connect \XL_BI \opcode_in [20:16]
10690   connect \XL_BH \opcode_in [12:11]
10691   connect \XL_BFA \opcode_in [20:18]
10692   connect \XL_BF \opcode_in [25:23]
10693   connect \XL_BB \opcode_in [15:11]
10694   connect \XL_BA \opcode_in [20:16]
10695   connect \XX4_XO \opcode_in [5:4]
10696   connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] }
10697   connect \XX4_T \opcode_in [25:21]
10698   connect \XX4_TX \opcode_in [0]
10699   connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] }
10700   connect \XX4_C \opcode_in [10:6]
10701   connect \XX4_CX \opcode_in [3]
10702   connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] }
10703   connect \XX4_B \opcode_in [15:11]
10704   connect \XX4_BX \opcode_in [1]
10705   connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] }
10706   connect \XX4_A \opcode_in [20:16]
10707   connect \XX4_AX \opcode_in [2]
10708   connect \XX3_XO_2 \opcode_in [9:1]
10709   connect \XX3_XO_1 \opcode_in [10:3]
10710   connect \XX3_XO \opcode_in [10:7]
10711   connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] }
10712   connect \XX3_T \opcode_in [25:21]
10713   connect \XX3_TX \opcode_in [0]
10714   connect \XX3_SHW \opcode_in [9:8]
10715   connect \XX3_Rc \opcode_in [10]
10716   connect \XX3_DM \opcode_in [9:8]
10717   connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] }
10718   connect \XX3_B \opcode_in [15:11]
10719   connect \XX3_BX \opcode_in [1]
10720   connect \XX3_BF \opcode_in [25:23]
10721   connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] }
10722   connect \XX3_A \opcode_in [20:16]
10723   connect \XX3_AX \opcode_in [2]
10724   connect \I_LK \opcode_in [0]
10725   connect \I_LI \opcode_in [25:2]
10726   connect \I_AA \opcode_in [1]
10727   connect \B_LK \opcode_in [0]
10728   connect \B_BO \opcode_in [25:21]
10729   connect \B_BI \opcode_in [20:16]
10730   connect \B_BD \opcode_in [15:2]
10731   connect \B_AA \opcode_in [1]
10732   connect \X_XO_1 \opcode_in [8:1]
10733   connect \X_XO \opcode_in [10:1]
10734   connect \X_WC \opcode_in [22:21]
10735   connect \X_W \opcode_in [16]
10736   connect \X_VRT \opcode_in [25:21]
10737   connect \X_VRS \opcode_in [25:21]
10738   connect \X_UIM \opcode_in [20:16]
10739   connect \X_U \opcode_in [15:12]
10740   connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] }
10741   connect \X_TX \opcode_in [0]
10742   connect \X_TO \opcode_in [25:21]
10743   connect \X_TH \opcode_in [25:21]
10744   connect \X_TBR \opcode_in [20:11]
10745   connect \X_T \opcode_in [25:21]
10746   connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] }
10747   connect \X_SX \opcode_in [0]
10748   connect \X_SR \opcode_in [19:16]
10749   connect \X_SP \opcode_in [20:19]
10750   connect \X_SI \opcode_in [15:11]
10751   connect \X_SH \opcode_in [15:11]
10752   connect \X_S \opcode_in [25:21]
10753   connect \X_RTp \opcode_in [25:21]
10754   connect \X_RT \opcode_in [25:21]
10755   connect \X_RSp \opcode_in [25:21]
10756   connect \X_RS \opcode_in [25:21]
10757   connect \X_RO \opcode_in [0]
10758   connect \X_RM \opcode_in [12:11]
10759   connect \X_RIC \opcode_in [19:18]
10760   connect \X_Rc \opcode_in [0]
10761   connect \X_RB \opcode_in [15:11]
10762   connect \X_RA \opcode_in [20:16]
10763   connect \X_R_1 \opcode_in [16]
10764   connect \X_R \opcode_in [21]
10765   connect \X_PRS \opcode_in [17]
10766   connect \X_NB \opcode_in [15:11]
10767   connect \X_MO \opcode_in [25:21]
10768   connect \X_L3 \opcode_in [17:16]
10769   connect \X_L1 \opcode_in [16]
10770   connect \X_L \opcode_in [21]
10771   connect \X_L2 \opcode_in [22:21]
10772   connect \X_IMM8 \opcode_in [18:11]
10773   connect \X_IH \opcode_in [23:21]
10774   connect \X_FRTp \opcode_in [25:21]
10775   connect \X_FRT \opcode_in [25:21]
10776   connect \X_FRSp \opcode_in [25:21]
10777   connect \X_FRS \opcode_in [25:21]
10778   connect \X_FRBp \opcode_in [15:11]
10779   connect \X_FRB \opcode_in [15:11]
10780   connect \X_FRAp \opcode_in [20:16]
10781   connect \X_FRA \opcode_in [20:16]
10782   connect \X_FC \opcode_in [15:11]
10783   connect \X_EX \opcode_in [0]
10784   connect \X_EO_1 \opcode_in [20:16]
10785   connect \X_EO \opcode_in [20:19]
10786   connect \X_E_1 \opcode_in [19:16]
10787   connect \X_E \opcode_in [15]
10788   connect \X_DRM \opcode_in [13:11]
10789   connect \X_DCMX \opcode_in [22:16]
10790   connect \X_CT \opcode_in [24:21]
10791   connect \X_BO \opcode_in [25:21]
10792   connect \X_BFA \opcode_in [20:18]
10793   connect \X_BF \opcode_in [25:23]
10794   connect \X_A \opcode_in [25]
10795   connect \SPR \opcode_in [20:11]
10796   connect \MB \opcode_in [10:6]
10797   connect \ME \opcode_in [5:1]
10798   connect \SH \opcode_in [15:11]
10799   connect \BC \opcode_in [10:6]
10800   connect \TO \opcode_in [25:21]
10801   connect \DS \opcode_in [15:2]
10802   connect \D \opcode_in [15:0]
10803   connect \BH \opcode_in [12:11]
10804   connect \BI \opcode_in [20:16]
10805   connect \BO \opcode_in [25:21]
10806   connect \FXM \opcode_in [19:12]
10807   connect \BT \opcode_in [25:21]
10808   connect \BA \opcode_in [20:16]
10809   connect \BB \opcode_in [15:11]
10810   connect \CR \opcode_in [10:1]
10811   connect \BF \opcode_in [25:23]
10812   connect \BD \opcode_in [15:2]
10813   connect \OE \opcode_in [10]
10814   connect \Rc \opcode_in [0]
10815   connect \AA \opcode_in [1]
10816   connect \LK \opcode_in [0]
10817   connect \LI \opcode_in [25:2]
10818   connect \ME32 \opcode_in [5:1]
10819   connect \MB32 \opcode_in [10:6]
10820   connect \sh { \opcode_in [1] \opcode_in [15:11] }
10821   connect \SH32 \opcode_in [15:11]
10822   connect \L \opcode_in [21]
10823   connect \UI \opcode_in [15:0]
10824   connect \SI \opcode_in [15:0]
10825   connect \RB \opcode_in [15:11]
10826   connect \RA \opcode_in [20:16]
10827   connect \RT \opcode_in [25:21]
10828   connect \RS \opcode_in [25:21]
10829   connect \opcode_in \$2
10830   connect \opcode_switch$1 \opcode_in
10831   connect \dec62_opcode_in \opcode_in
10832   connect \dec58_opcode_in \opcode_in
10833   connect \dec31_opcode_in \opcode_in
10834   connect \dec30_opcode_in \opcode_in
10835   connect \dec19_opcode_in \opcode_in
10836   connect \opcode_switch \opcode_in [31:26]
10837 end
10838 attribute \src "libresoc.v:7128.1-8635.10"
10839 attribute \cells_not_processed 1
10840 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19"
10841 attribute \generator "nMigen"
10842 module \dec19
10843   attribute \src "libresoc.v:7646.3-7697.6"
10844   wire width 8 $0\dec19_asmcode[7:0]
10845   attribute \src "libresoc.v:7854.3-7905.6"
10846   wire $0\dec19_br[0:0]
10847   attribute \src "libresoc.v:8530.3-8581.6"
10848   wire width 3 $0\dec19_cr_in[2:0]
10849   attribute \src "libresoc.v:8582.3-8633.6"
10850   wire width 3 $0\dec19_cr_out[2:0]
10851   attribute \src "libresoc.v:7594.3-7645.6"
10852   wire width 2 $0\dec19_cry_in[1:0]
10853   attribute \src "libresoc.v:7802.3-7853.6"
10854   wire $0\dec19_cry_out[0:0]
10855   attribute \src "libresoc.v:8270.3-8321.6"
10856   wire width 5 $0\dec19_form[4:0]
10857   attribute \src "libresoc.v:7386.3-7437.6"
10858   wire width 12 $0\dec19_function_unit[11:0]
10859   attribute \src "libresoc.v:8322.3-8373.6"
10860   wire width 3 $0\dec19_in1_sel[2:0]
10861   attribute \src "libresoc.v:8374.3-8425.6"
10862   wire width 4 $0\dec19_in2_sel[3:0]
10863   attribute \src "libresoc.v:8426.3-8477.6"
10864   wire width 2 $0\dec19_in3_sel[1:0]
10865   attribute \src "libresoc.v:7958.3-8009.6"
10866   wire width 7 $0\dec19_internal_op[6:0]
10867   attribute \src "libresoc.v:7698.3-7749.6"
10868   wire $0\dec19_inv_a[0:0]
10869   attribute \src "libresoc.v:7750.3-7801.6"
10870   wire $0\dec19_inv_out[0:0]
10871   attribute \src "libresoc.v:8062.3-8113.6"
10872   wire $0\dec19_is_32b[0:0]
10873   attribute \src "libresoc.v:7438.3-7489.6"
10874   wire width 4 $0\dec19_ldst_len[3:0]
10875   attribute \src "libresoc.v:8166.3-8217.6"
10876   wire $0\dec19_lk[0:0]
10877   attribute \src "libresoc.v:8478.3-8529.6"
10878   wire width 2 $0\dec19_out_sel[1:0]
10879   attribute \src "libresoc.v:7542.3-7593.6"
10880   wire width 2 $0\dec19_rc_sel[1:0]
10881   attribute \src "libresoc.v:8010.3-8061.6"
10882   wire $0\dec19_rsrv[0:0]
10883   attribute \src "libresoc.v:8218.3-8269.6"
10884   wire $0\dec19_sgl_pipe[0:0]
10885   attribute \src "libresoc.v:8114.3-8165.6"
10886   wire $0\dec19_sgn[0:0]
10887   attribute \src "libresoc.v:7906.3-7957.6"
10888   wire $0\dec19_sgn_ext[0:0]
10889   attribute \src "libresoc.v:7490.3-7541.6"
10890   wire width 2 $0\dec19_upd[1:0]
10891   attribute \src "libresoc.v:7129.7-7129.20"
10892   wire $0\initial[0:0]
10893   attribute \src "libresoc.v:7646.3-7697.6"
10894   wire width 8 $1\dec19_asmcode[7:0]
10895   attribute \src "libresoc.v:7854.3-7905.6"
10896   wire $1\dec19_br[0:0]
10897   attribute \src "libresoc.v:8530.3-8581.6"
10898   wire width 3 $1\dec19_cr_in[2:0]
10899   attribute \src "libresoc.v:8582.3-8633.6"
10900   wire width 3 $1\dec19_cr_out[2:0]
10901   attribute \src "libresoc.v:7594.3-7645.6"
10902   wire width 2 $1\dec19_cry_in[1:0]
10903   attribute \src "libresoc.v:7802.3-7853.6"
10904   wire $1\dec19_cry_out[0:0]
10905   attribute \src "libresoc.v:8270.3-8321.6"
10906   wire width 5 $1\dec19_form[4:0]
10907   attribute \src "libresoc.v:7386.3-7437.6"
10908   wire width 12 $1\dec19_function_unit[11:0]
10909   attribute \src "libresoc.v:8322.3-8373.6"
10910   wire width 3 $1\dec19_in1_sel[2:0]
10911   attribute \src "libresoc.v:8374.3-8425.6"
10912   wire width 4 $1\dec19_in2_sel[3:0]
10913   attribute \src "libresoc.v:8426.3-8477.6"
10914   wire width 2 $1\dec19_in3_sel[1:0]
10915   attribute \src "libresoc.v:7958.3-8009.6"
10916   wire width 7 $1\dec19_internal_op[6:0]
10917   attribute \src "libresoc.v:7698.3-7749.6"
10918   wire $1\dec19_inv_a[0:0]
10919   attribute \src "libresoc.v:7750.3-7801.6"
10920   wire $1\dec19_inv_out[0:0]
10921   attribute \src "libresoc.v:8062.3-8113.6"
10922   wire $1\dec19_is_32b[0:0]
10923   attribute \src "libresoc.v:7438.3-7489.6"
10924   wire width 4 $1\dec19_ldst_len[3:0]
10925   attribute \src "libresoc.v:8166.3-8217.6"
10926   wire $1\dec19_lk[0:0]
10927   attribute \src "libresoc.v:8478.3-8529.6"
10928   wire width 2 $1\dec19_out_sel[1:0]
10929   attribute \src "libresoc.v:7542.3-7593.6"
10930   wire width 2 $1\dec19_rc_sel[1:0]
10931   attribute \src "libresoc.v:8010.3-8061.6"
10932   wire $1\dec19_rsrv[0:0]
10933   attribute \src "libresoc.v:8218.3-8269.6"
10934   wire $1\dec19_sgl_pipe[0:0]
10935   attribute \src "libresoc.v:8114.3-8165.6"
10936   wire $1\dec19_sgn[0:0]
10937   attribute \src "libresoc.v:7906.3-7957.6"
10938   wire $1\dec19_sgn_ext[0:0]
10939   attribute \src "libresoc.v:7490.3-7541.6"
10940   wire width 2 $1\dec19_upd[1:0]
10941   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
10942   wire width 8 output 4 \dec19_asmcode
10943   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
10944   wire output 18 \dec19_br
10945   attribute \enum_base_type "CRInSel"
10946   attribute \enum_value_000 "NONE"
10947   attribute \enum_value_001 "CR0"
10948   attribute \enum_value_010 "BI"
10949   attribute \enum_value_011 "BFA"
10950   attribute \enum_value_100 "BA_BB"
10951   attribute \enum_value_101 "BC"
10952   attribute \enum_value_110 "WHOLE_REG"
10953   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
10954   wire width 3 output 9 \dec19_cr_in
10955   attribute \enum_base_type "CROutSel"
10956   attribute \enum_value_000 "NONE"
10957   attribute \enum_value_001 "CR0"
10958   attribute \enum_value_010 "BF"
10959   attribute \enum_value_011 "BT"
10960   attribute \enum_value_100 "WHOLE_REG"
10961   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
10962   wire width 3 output 10 \dec19_cr_out
10963   attribute \enum_base_type "CryIn"
10964   attribute \enum_value_00 "ZERO"
10965   attribute \enum_value_01 "ONE"
10966   attribute \enum_value_10 "CA"
10967   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
10968   wire width 2 output 14 \dec19_cry_in
10969   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
10970   wire output 17 \dec19_cry_out
10971   attribute \enum_base_type "Form"
10972   attribute \enum_value_00000 "NONE"
10973   attribute \enum_value_00001 "I"
10974   attribute \enum_value_00010 "B"
10975   attribute \enum_value_00011 "SC"
10976   attribute \enum_value_00100 "D"
10977   attribute \enum_value_00101 "DS"
10978   attribute \enum_value_00110 "DQ"
10979   attribute \enum_value_00111 "DX"
10980   attribute \enum_value_01000 "X"
10981   attribute \enum_value_01001 "XL"
10982   attribute \enum_value_01010 "XFX"
10983   attribute \enum_value_01011 "XFL"
10984   attribute \enum_value_01100 "XX1"
10985   attribute \enum_value_01101 "XX2"
10986   attribute \enum_value_01110 "XX3"
10987   attribute \enum_value_01111 "XX4"
10988   attribute \enum_value_10000 "XS"
10989   attribute \enum_value_10001 "XO"
10990   attribute \enum_value_10010 "A"
10991   attribute \enum_value_10011 "M"
10992   attribute \enum_value_10100 "MD"
10993   attribute \enum_value_10101 "MDS"
10994   attribute \enum_value_10110 "VA"
10995   attribute \enum_value_10111 "VC"
10996   attribute \enum_value_11000 "VX"
10997   attribute \enum_value_11001 "EVX"
10998   attribute \enum_value_11010 "EVS"
10999   attribute \enum_value_11011 "Z22"
11000   attribute \enum_value_11100 "Z23"
11001   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11002   wire width 5 output 3 \dec19_form
11003   attribute \enum_base_type "Function"
11004   attribute \enum_value_000000000000 "NONE"
11005   attribute \enum_value_000000000010 "ALU"
11006   attribute \enum_value_000000000100 "LDST"
11007   attribute \enum_value_000000001000 "SHIFT_ROT"
11008   attribute \enum_value_000000010000 "LOGICAL"
11009   attribute \enum_value_000000100000 "BRANCH"
11010   attribute \enum_value_000001000000 "CR"
11011   attribute \enum_value_000010000000 "TRAP"
11012   attribute \enum_value_000100000000 "MUL"
11013   attribute \enum_value_001000000000 "DIV"
11014   attribute \enum_value_010000000000 "SPR"
11015   attribute \enum_value_100000000000 "MMU"
11016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11017   wire width 12 output 1 \dec19_function_unit
11018   attribute \enum_base_type "In1Sel"
11019   attribute \enum_value_000 "NONE"
11020   attribute \enum_value_001 "RA"
11021   attribute \enum_value_010 "RA_OR_ZERO"
11022   attribute \enum_value_011 "SPR"
11023   attribute \enum_value_100 "RS"
11024   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11025   wire width 3 output 5 \dec19_in1_sel
11026   attribute \enum_base_type "In2Sel"
11027   attribute \enum_value_0000 "NONE"
11028   attribute \enum_value_0001 "RB"
11029   attribute \enum_value_0010 "CONST_UI"
11030   attribute \enum_value_0011 "CONST_SI"
11031   attribute \enum_value_0100 "CONST_UI_HI"
11032   attribute \enum_value_0101 "CONST_SI_HI"
11033   attribute \enum_value_0110 "CONST_LI"
11034   attribute \enum_value_0111 "CONST_BD"
11035   attribute \enum_value_1000 "CONST_DS"
11036   attribute \enum_value_1001 "CONST_M1"
11037   attribute \enum_value_1010 "CONST_SH"
11038   attribute \enum_value_1011 "CONST_SH32"
11039   attribute \enum_value_1100 "SPR"
11040   attribute \enum_value_1101 "RS"
11041   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11042   wire width 4 output 6 \dec19_in2_sel
11043   attribute \enum_base_type "In3Sel"
11044   attribute \enum_value_00 "NONE"
11045   attribute \enum_value_01 "RS"
11046   attribute \enum_value_10 "RB"
11047   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11048   wire width 2 output 7 \dec19_in3_sel
11049   attribute \enum_base_type "MicrOp"
11050   attribute \enum_value_0000000 "OP_ILLEGAL"
11051   attribute \enum_value_0000001 "OP_NOP"
11052   attribute \enum_value_0000010 "OP_ADD"
11053   attribute \enum_value_0000011 "OP_ADDPCIS"
11054   attribute \enum_value_0000100 "OP_AND"
11055   attribute \enum_value_0000101 "OP_ATTN"
11056   attribute \enum_value_0000110 "OP_B"
11057   attribute \enum_value_0000111 "OP_BC"
11058   attribute \enum_value_0001000 "OP_BCREG"
11059   attribute \enum_value_0001001 "OP_BPERM"
11060   attribute \enum_value_0001010 "OP_CMP"
11061   attribute \enum_value_0001011 "OP_CMPB"
11062   attribute \enum_value_0001100 "OP_CMPEQB"
11063   attribute \enum_value_0001101 "OP_CMPRB"
11064   attribute \enum_value_0001110 "OP_CNTZ"
11065   attribute \enum_value_0001111 "OP_CRAND"
11066   attribute \enum_value_0010000 "OP_CRANDC"
11067   attribute \enum_value_0010001 "OP_CREQV"
11068   attribute \enum_value_0010010 "OP_CRNAND"
11069   attribute \enum_value_0010011 "OP_CRNOR"
11070   attribute \enum_value_0010100 "OP_CROR"
11071   attribute \enum_value_0010101 "OP_CRORC"
11072   attribute \enum_value_0010110 "OP_CRXOR"
11073   attribute \enum_value_0010111 "OP_DARN"
11074   attribute \enum_value_0011000 "OP_DCBF"
11075   attribute \enum_value_0011001 "OP_DCBST"
11076   attribute \enum_value_0011010 "OP_DCBT"
11077   attribute \enum_value_0011011 "OP_DCBTST"
11078   attribute \enum_value_0011100 "OP_DCBZ"
11079   attribute \enum_value_0011101 "OP_DIV"
11080   attribute \enum_value_0011110 "OP_DIVE"
11081   attribute \enum_value_0011111 "OP_EXTS"
11082   attribute \enum_value_0100000 "OP_EXTSWSLI"
11083   attribute \enum_value_0100001 "OP_ICBI"
11084   attribute \enum_value_0100010 "OP_ICBT"
11085   attribute \enum_value_0100011 "OP_ISEL"
11086   attribute \enum_value_0100100 "OP_ISYNC"
11087   attribute \enum_value_0100101 "OP_LOAD"
11088   attribute \enum_value_0100110 "OP_STORE"
11089   attribute \enum_value_0100111 "OP_MADDHD"
11090   attribute \enum_value_0101000 "OP_MADDHDU"
11091   attribute \enum_value_0101001 "OP_MADDLD"
11092   attribute \enum_value_0101010 "OP_MCRF"
11093   attribute \enum_value_0101011 "OP_MCRXR"
11094   attribute \enum_value_0101100 "OP_MCRXRX"
11095   attribute \enum_value_0101101 "OP_MFCR"
11096   attribute \enum_value_0101110 "OP_MFSPR"
11097   attribute \enum_value_0101111 "OP_MOD"
11098   attribute \enum_value_0110000 "OP_MTCRF"
11099   attribute \enum_value_0110001 "OP_MTSPR"
11100   attribute \enum_value_0110010 "OP_MUL_L64"
11101   attribute \enum_value_0110011 "OP_MUL_H64"
11102   attribute \enum_value_0110100 "OP_MUL_H32"
11103   attribute \enum_value_0110101 "OP_OR"
11104   attribute \enum_value_0110110 "OP_POPCNT"
11105   attribute \enum_value_0110111 "OP_PRTY"
11106   attribute \enum_value_0111000 "OP_RLC"
11107   attribute \enum_value_0111001 "OP_RLCL"
11108   attribute \enum_value_0111010 "OP_RLCR"
11109   attribute \enum_value_0111011 "OP_SETB"
11110   attribute \enum_value_0111100 "OP_SHL"
11111   attribute \enum_value_0111101 "OP_SHR"
11112   attribute \enum_value_0111110 "OP_SYNC"
11113   attribute \enum_value_0111111 "OP_TRAP"
11114   attribute \enum_value_1000011 "OP_XOR"
11115   attribute \enum_value_1000100 "OP_SIM_CONFIG"
11116   attribute \enum_value_1000101 "OP_CROP"
11117   attribute \enum_value_1000110 "OP_RFID"
11118   attribute \enum_value_1000111 "OP_MFMSR"
11119   attribute \enum_value_1001000 "OP_MTMSRD"
11120   attribute \enum_value_1001001 "OP_SC"
11121   attribute \enum_value_1001010 "OP_MTMSR"
11122   attribute \enum_value_1001011 "OP_TLBIE"
11123   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11124   wire width 7 output 2 \dec19_internal_op
11125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11126   wire output 15 \dec19_inv_a
11127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11128   wire output 16 \dec19_inv_out
11129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11130   wire output 21 \dec19_is_32b
11131   attribute \enum_base_type "LdstLen"
11132   attribute \enum_value_0000 "NONE"
11133   attribute \enum_value_0001 "is1B"
11134   attribute \enum_value_0010 "is2B"
11135   attribute \enum_value_0100 "is4B"
11136   attribute \enum_value_1000 "is8B"
11137   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11138   wire width 4 output 11 \dec19_ldst_len
11139   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11140   wire output 23 \dec19_lk
11141   attribute \enum_base_type "OutSel"
11142   attribute \enum_value_00 "NONE"
11143   attribute \enum_value_01 "RT"
11144   attribute \enum_value_10 "RA"
11145   attribute \enum_value_11 "SPR"
11146   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11147   wire width 2 output 8 \dec19_out_sel
11148   attribute \enum_base_type "RC"
11149   attribute \enum_value_00 "NONE"
11150   attribute \enum_value_01 "ONE"
11151   attribute \enum_value_10 "RC"
11152   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11153   wire width 2 output 13 \dec19_rc_sel
11154   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11155   wire output 20 \dec19_rsrv
11156   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11157   wire output 24 \dec19_sgl_pipe
11158   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11159   wire output 22 \dec19_sgn
11160   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
11161   wire output 19 \dec19_sgn_ext
11162   attribute \enum_base_type "LDSTMode"
11163   attribute \enum_value_00 "NONE"
11164   attribute \enum_value_01 "update"
11165   attribute \enum_value_10 "cix"
11166   attribute \enum_value_11 "cx"
11167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
11168   wire width 2 output 12 \dec19_upd
11169   attribute \src "libresoc.v:7129.7-7129.15"
11170   wire \initial
11171   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
11172   wire width 32 input 25 \opcode_in
11173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
11174   wire width 10 \opcode_switch
11175   attribute \src "libresoc.v:7129.7-7129.20"
11176   process $proc$libresoc.v:7129$287
11177     assign { } { }
11178     assign $0\initial[0:0] 1'0
11179     sync always
11180       update \initial $0\initial[0:0]
11181     sync init
11182   end
11183   attribute \src "libresoc.v:7386.3-7437.6"
11184   process $proc$libresoc.v:7386$263
11185     assign { } { }
11186     assign { } { }
11187     assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0]
11188     attribute \src "libresoc.v:7387.5-7387.29"
11189     switch \initial
11190       attribute \src "libresoc.v:7387.9-7387.17"
11191       case 1'1
11192       case
11193     end
11194     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11195     switch \opcode_switch
11196       attribute \src "libresoc.v:0.0-0.0"
11197       case 10'0000000000
11198         assign { } { }
11199         assign $1\dec19_function_unit[11:0] 12'000001000000
11200       attribute \src "libresoc.v:0.0-0.0"
11201       case 10'0100000001
11202         assign { } { }
11203         assign $1\dec19_function_unit[11:0] 12'000001000000
11204       attribute \src "libresoc.v:0.0-0.0"
11205       case 10'0010000001
11206         assign { } { }
11207         assign $1\dec19_function_unit[11:0] 12'000001000000
11208       attribute \src "libresoc.v:0.0-0.0"
11209       case 10'0100100001
11210         assign { } { }
11211         assign $1\dec19_function_unit[11:0] 12'000001000000
11212       attribute \src "libresoc.v:0.0-0.0"
11213       case 10'0011100001
11214         assign { } { }
11215         assign $1\dec19_function_unit[11:0] 12'000001000000
11216       attribute \src "libresoc.v:0.0-0.0"
11217       case 10'0000100001
11218         assign { } { }
11219         assign $1\dec19_function_unit[11:0] 12'000001000000
11220       attribute \src "libresoc.v:0.0-0.0"
11221       case 10'0111000001
11222         assign { } { }
11223         assign $1\dec19_function_unit[11:0] 12'000001000000
11224       attribute \src "libresoc.v:0.0-0.0"
11225       case 10'0110100001
11226         assign { } { }
11227         assign $1\dec19_function_unit[11:0] 12'000001000000
11228       attribute \src "libresoc.v:0.0-0.0"
11229       case 10'0011000001
11230         assign { } { }
11231         assign $1\dec19_function_unit[11:0] 12'000001000000
11232       attribute \src "libresoc.v:0.0-0.0"
11233       case 10'1000010000
11234         assign { } { }
11235         assign $1\dec19_function_unit[11:0] 12'000000100000
11236       attribute \src "libresoc.v:0.0-0.0"
11237       case 10'0000010000
11238         assign { } { }
11239         assign $1\dec19_function_unit[11:0] 12'000000100000
11240       attribute \src "libresoc.v:0.0-0.0"
11241       case 10'1000110000
11242         assign { } { }
11243         assign $1\dec19_function_unit[11:0] 12'000000100000
11244       attribute \src "libresoc.v:0.0-0.0"
11245       case 10'0010010110
11246         assign { } { }
11247         assign $1\dec19_function_unit[11:0] 12'000000000010
11248       attribute \src "libresoc.v:0.0-0.0"
11249       case 10'0000010010
11250         assign { } { }
11251         assign $1\dec19_function_unit[11:0] 12'000010000000
11252       attribute \src "libresoc.v:0.0-0.0"
11253       case 10'0100010010
11254         assign { } { }
11255         assign $1\dec19_function_unit[11:0] 12'000010000000
11256       case
11257         assign $1\dec19_function_unit[11:0] 12'000000000000
11258     end
11259     sync always
11260       update \dec19_function_unit $0\dec19_function_unit[11:0]
11261   end
11262   attribute \src "libresoc.v:7438.3-7489.6"
11263   process $proc$libresoc.v:7438$264
11264     assign { } { }
11265     assign { } { }
11266     assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0]
11267     attribute \src "libresoc.v:7439.5-7439.29"
11268     switch \initial
11269       attribute \src "libresoc.v:7439.9-7439.17"
11270       case 1'1
11271       case
11272     end
11273     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11274     switch \opcode_switch
11275       attribute \src "libresoc.v:0.0-0.0"
11276       case 10'0000000000
11277         assign { } { }
11278         assign $1\dec19_ldst_len[3:0] 4'0000
11279       attribute \src "libresoc.v:0.0-0.0"
11280       case 10'0100000001
11281         assign { } { }
11282         assign $1\dec19_ldst_len[3:0] 4'0000
11283       attribute \src "libresoc.v:0.0-0.0"
11284       case 10'0010000001
11285         assign { } { }
11286         assign $1\dec19_ldst_len[3:0] 4'0000
11287       attribute \src "libresoc.v:0.0-0.0"
11288       case 10'0100100001
11289         assign { } { }
11290         assign $1\dec19_ldst_len[3:0] 4'0000
11291       attribute \src "libresoc.v:0.0-0.0"
11292       case 10'0011100001
11293         assign { } { }
11294         assign $1\dec19_ldst_len[3:0] 4'0000
11295       attribute \src "libresoc.v:0.0-0.0"
11296       case 10'0000100001
11297         assign { } { }
11298         assign $1\dec19_ldst_len[3:0] 4'0000
11299       attribute \src "libresoc.v:0.0-0.0"
11300       case 10'0111000001
11301         assign { } { }
11302         assign $1\dec19_ldst_len[3:0] 4'0000
11303       attribute \src "libresoc.v:0.0-0.0"
11304       case 10'0110100001
11305         assign { } { }
11306         assign $1\dec19_ldst_len[3:0] 4'0000
11307       attribute \src "libresoc.v:0.0-0.0"
11308       case 10'0011000001
11309         assign { } { }
11310         assign $1\dec19_ldst_len[3:0] 4'0000
11311       attribute \src "libresoc.v:0.0-0.0"
11312       case 10'1000010000
11313         assign { } { }
11314         assign $1\dec19_ldst_len[3:0] 4'0000
11315       attribute \src "libresoc.v:0.0-0.0"
11316       case 10'0000010000
11317         assign { } { }
11318         assign $1\dec19_ldst_len[3:0] 4'0000
11319       attribute \src "libresoc.v:0.0-0.0"
11320       case 10'1000110000
11321         assign { } { }
11322         assign $1\dec19_ldst_len[3:0] 4'0000
11323       attribute \src "libresoc.v:0.0-0.0"
11324       case 10'0010010110
11325         assign { } { }
11326         assign $1\dec19_ldst_len[3:0] 4'0000
11327       attribute \src "libresoc.v:0.0-0.0"
11328       case 10'0000010010
11329         assign { } { }
11330         assign $1\dec19_ldst_len[3:0] 4'0000
11331       attribute \src "libresoc.v:0.0-0.0"
11332       case 10'0100010010
11333         assign { } { }
11334         assign $1\dec19_ldst_len[3:0] 4'0000
11335       case
11336         assign $1\dec19_ldst_len[3:0] 4'0000
11337     end
11338     sync always
11339       update \dec19_ldst_len $0\dec19_ldst_len[3:0]
11340   end
11341   attribute \src "libresoc.v:7490.3-7541.6"
11342   process $proc$libresoc.v:7490$265
11343     assign { } { }
11344     assign { } { }
11345     assign $0\dec19_upd[1:0] $1\dec19_upd[1:0]
11346     attribute \src "libresoc.v:7491.5-7491.29"
11347     switch \initial
11348       attribute \src "libresoc.v:7491.9-7491.17"
11349       case 1'1
11350       case
11351     end
11352     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11353     switch \opcode_switch
11354       attribute \src "libresoc.v:0.0-0.0"
11355       case 10'0000000000
11356         assign { } { }
11357         assign $1\dec19_upd[1:0] 2'00
11358       attribute \src "libresoc.v:0.0-0.0"
11359       case 10'0100000001
11360         assign { } { }
11361         assign $1\dec19_upd[1:0] 2'00
11362       attribute \src "libresoc.v:0.0-0.0"
11363       case 10'0010000001
11364         assign { } { }
11365         assign $1\dec19_upd[1:0] 2'00
11366       attribute \src "libresoc.v:0.0-0.0"
11367       case 10'0100100001
11368         assign { } { }
11369         assign $1\dec19_upd[1:0] 2'00
11370       attribute \src "libresoc.v:0.0-0.0"
11371       case 10'0011100001
11372         assign { } { }
11373         assign $1\dec19_upd[1:0] 2'00
11374       attribute \src "libresoc.v:0.0-0.0"
11375       case 10'0000100001
11376         assign { } { }
11377         assign $1\dec19_upd[1:0] 2'00
11378       attribute \src "libresoc.v:0.0-0.0"
11379       case 10'0111000001
11380         assign { } { }
11381         assign $1\dec19_upd[1:0] 2'00
11382       attribute \src "libresoc.v:0.0-0.0"
11383       case 10'0110100001
11384         assign { } { }
11385         assign $1\dec19_upd[1:0] 2'00
11386       attribute \src "libresoc.v:0.0-0.0"
11387       case 10'0011000001
11388         assign { } { }
11389         assign $1\dec19_upd[1:0] 2'00
11390       attribute \src "libresoc.v:0.0-0.0"
11391       case 10'1000010000
11392         assign { } { }
11393         assign $1\dec19_upd[1:0] 2'00
11394       attribute \src "libresoc.v:0.0-0.0"
11395       case 10'0000010000
11396         assign { } { }
11397         assign $1\dec19_upd[1:0] 2'00
11398       attribute \src "libresoc.v:0.0-0.0"
11399       case 10'1000110000
11400         assign { } { }
11401         assign $1\dec19_upd[1:0] 2'00
11402       attribute \src "libresoc.v:0.0-0.0"
11403       case 10'0010010110
11404         assign { } { }
11405         assign $1\dec19_upd[1:0] 2'00
11406       attribute \src "libresoc.v:0.0-0.0"
11407       case 10'0000010010
11408         assign { } { }
11409         assign $1\dec19_upd[1:0] 2'00
11410       attribute \src "libresoc.v:0.0-0.0"
11411       case 10'0100010010
11412         assign { } { }
11413         assign $1\dec19_upd[1:0] 2'00
11414       case
11415         assign $1\dec19_upd[1:0] 2'00
11416     end
11417     sync always
11418       update \dec19_upd $0\dec19_upd[1:0]
11419   end
11420   attribute \src "libresoc.v:7542.3-7593.6"
11421   process $proc$libresoc.v:7542$266
11422     assign { } { }
11423     assign { } { }
11424     assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0]
11425     attribute \src "libresoc.v:7543.5-7543.29"
11426     switch \initial
11427       attribute \src "libresoc.v:7543.9-7543.17"
11428       case 1'1
11429       case
11430     end
11431     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11432     switch \opcode_switch
11433       attribute \src "libresoc.v:0.0-0.0"
11434       case 10'0000000000
11435         assign { } { }
11436         assign $1\dec19_rc_sel[1:0] 2'00
11437       attribute \src "libresoc.v:0.0-0.0"
11438       case 10'0100000001
11439         assign { } { }
11440         assign $1\dec19_rc_sel[1:0] 2'00
11441       attribute \src "libresoc.v:0.0-0.0"
11442       case 10'0010000001
11443         assign { } { }
11444         assign $1\dec19_rc_sel[1:0] 2'00
11445       attribute \src "libresoc.v:0.0-0.0"
11446       case 10'0100100001
11447         assign { } { }
11448         assign $1\dec19_rc_sel[1:0] 2'00
11449       attribute \src "libresoc.v:0.0-0.0"
11450       case 10'0011100001
11451         assign { } { }
11452         assign $1\dec19_rc_sel[1:0] 2'00
11453       attribute \src "libresoc.v:0.0-0.0"
11454       case 10'0000100001
11455         assign { } { }
11456         assign $1\dec19_rc_sel[1:0] 2'00
11457       attribute \src "libresoc.v:0.0-0.0"
11458       case 10'0111000001
11459         assign { } { }
11460         assign $1\dec19_rc_sel[1:0] 2'00
11461       attribute \src "libresoc.v:0.0-0.0"
11462       case 10'0110100001
11463         assign { } { }
11464         assign $1\dec19_rc_sel[1:0] 2'00
11465       attribute \src "libresoc.v:0.0-0.0"
11466       case 10'0011000001
11467         assign { } { }
11468         assign $1\dec19_rc_sel[1:0] 2'00
11469       attribute \src "libresoc.v:0.0-0.0"
11470       case 10'1000010000
11471         assign { } { }
11472         assign $1\dec19_rc_sel[1:0] 2'00
11473       attribute \src "libresoc.v:0.0-0.0"
11474       case 10'0000010000
11475         assign { } { }
11476         assign $1\dec19_rc_sel[1:0] 2'00
11477       attribute \src "libresoc.v:0.0-0.0"
11478       case 10'1000110000
11479         assign { } { }
11480         assign $1\dec19_rc_sel[1:0] 2'00
11481       attribute \src "libresoc.v:0.0-0.0"
11482       case 10'0010010110
11483         assign { } { }
11484         assign $1\dec19_rc_sel[1:0] 2'00
11485       attribute \src "libresoc.v:0.0-0.0"
11486       case 10'0000010010
11487         assign { } { }
11488         assign $1\dec19_rc_sel[1:0] 2'00
11489       attribute \src "libresoc.v:0.0-0.0"
11490       case 10'0100010010
11491         assign { } { }
11492         assign $1\dec19_rc_sel[1:0] 2'00
11493       case
11494         assign $1\dec19_rc_sel[1:0] 2'00
11495     end
11496     sync always
11497       update \dec19_rc_sel $0\dec19_rc_sel[1:0]
11498   end
11499   attribute \src "libresoc.v:7594.3-7645.6"
11500   process $proc$libresoc.v:7594$267
11501     assign { } { }
11502     assign { } { }
11503     assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0]
11504     attribute \src "libresoc.v:7595.5-7595.29"
11505     switch \initial
11506       attribute \src "libresoc.v:7595.9-7595.17"
11507       case 1'1
11508       case
11509     end
11510     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11511     switch \opcode_switch
11512       attribute \src "libresoc.v:0.0-0.0"
11513       case 10'0000000000
11514         assign { } { }
11515         assign $1\dec19_cry_in[1:0] 2'00
11516       attribute \src "libresoc.v:0.0-0.0"
11517       case 10'0100000001
11518         assign { } { }
11519         assign $1\dec19_cry_in[1:0] 2'00
11520       attribute \src "libresoc.v:0.0-0.0"
11521       case 10'0010000001
11522         assign { } { }
11523         assign $1\dec19_cry_in[1:0] 2'00
11524       attribute \src "libresoc.v:0.0-0.0"
11525       case 10'0100100001
11526         assign { } { }
11527         assign $1\dec19_cry_in[1:0] 2'00
11528       attribute \src "libresoc.v:0.0-0.0"
11529       case 10'0011100001
11530         assign { } { }
11531         assign $1\dec19_cry_in[1:0] 2'00
11532       attribute \src "libresoc.v:0.0-0.0"
11533       case 10'0000100001
11534         assign { } { }
11535         assign $1\dec19_cry_in[1:0] 2'00
11536       attribute \src "libresoc.v:0.0-0.0"
11537       case 10'0111000001
11538         assign { } { }
11539         assign $1\dec19_cry_in[1:0] 2'00
11540       attribute \src "libresoc.v:0.0-0.0"
11541       case 10'0110100001
11542         assign { } { }
11543         assign $1\dec19_cry_in[1:0] 2'00
11544       attribute \src "libresoc.v:0.0-0.0"
11545       case 10'0011000001
11546         assign { } { }
11547         assign $1\dec19_cry_in[1:0] 2'00
11548       attribute \src "libresoc.v:0.0-0.0"
11549       case 10'1000010000
11550         assign { } { }
11551         assign $1\dec19_cry_in[1:0] 2'00
11552       attribute \src "libresoc.v:0.0-0.0"
11553       case 10'0000010000
11554         assign { } { }
11555         assign $1\dec19_cry_in[1:0] 2'00
11556       attribute \src "libresoc.v:0.0-0.0"
11557       case 10'1000110000
11558         assign { } { }
11559         assign $1\dec19_cry_in[1:0] 2'00
11560       attribute \src "libresoc.v:0.0-0.0"
11561       case 10'0010010110
11562         assign { } { }
11563         assign $1\dec19_cry_in[1:0] 2'00
11564       attribute \src "libresoc.v:0.0-0.0"
11565       case 10'0000010010
11566         assign { } { }
11567         assign $1\dec19_cry_in[1:0] 2'00
11568       attribute \src "libresoc.v:0.0-0.0"
11569       case 10'0100010010
11570         assign { } { }
11571         assign $1\dec19_cry_in[1:0] 2'00
11572       case
11573         assign $1\dec19_cry_in[1:0] 2'00
11574     end
11575     sync always
11576       update \dec19_cry_in $0\dec19_cry_in[1:0]
11577   end
11578   attribute \src "libresoc.v:7646.3-7697.6"
11579   process $proc$libresoc.v:7646$268
11580     assign { } { }
11581     assign { } { }
11582     assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0]
11583     attribute \src "libresoc.v:7647.5-7647.29"
11584     switch \initial
11585       attribute \src "libresoc.v:7647.9-7647.17"
11586       case 1'1
11587       case
11588     end
11589     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11590     switch \opcode_switch
11591       attribute \src "libresoc.v:0.0-0.0"
11592       case 10'0000000000
11593         assign { } { }
11594         assign $1\dec19_asmcode[7:0] 8'01101100
11595       attribute \src "libresoc.v:0.0-0.0"
11596       case 10'0100000001
11597         assign { } { }
11598         assign $1\dec19_asmcode[7:0] 8'00100101
11599       attribute \src "libresoc.v:0.0-0.0"
11600       case 10'0010000001
11601         assign { } { }
11602         assign $1\dec19_asmcode[7:0] 8'00100110
11603       attribute \src "libresoc.v:0.0-0.0"
11604       case 10'0100100001
11605         assign { } { }
11606         assign $1\dec19_asmcode[7:0] 8'00100111
11607       attribute \src "libresoc.v:0.0-0.0"
11608       case 10'0011100001
11609         assign { } { }
11610         assign $1\dec19_asmcode[7:0] 8'00101000
11611       attribute \src "libresoc.v:0.0-0.0"
11612       case 10'0000100001
11613         assign { } { }
11614         assign $1\dec19_asmcode[7:0] 8'00101001
11615       attribute \src "libresoc.v:0.0-0.0"
11616       case 10'0111000001
11617         assign { } { }
11618         assign $1\dec19_asmcode[7:0] 8'00101010
11619       attribute \src "libresoc.v:0.0-0.0"
11620       case 10'0110100001
11621         assign { } { }
11622         assign $1\dec19_asmcode[7:0] 8'00101011
11623       attribute \src "libresoc.v:0.0-0.0"
11624       case 10'0011000001
11625         assign { } { }
11626         assign $1\dec19_asmcode[7:0] 8'00101100
11627       attribute \src "libresoc.v:0.0-0.0"
11628       case 10'1000010000
11629         assign { } { }
11630         assign $1\dec19_asmcode[7:0] 8'00010110
11631       attribute \src "libresoc.v:0.0-0.0"
11632       case 10'0000010000
11633         assign { } { }
11634         assign $1\dec19_asmcode[7:0] 8'00010111
11635       attribute \src "libresoc.v:0.0-0.0"
11636       case 10'1000110000
11637         assign { } { }
11638         assign $1\dec19_asmcode[7:0] 8'00011000
11639       attribute \src "libresoc.v:0.0-0.0"
11640       case 10'0010010110
11641         assign { } { }
11642         assign $1\dec19_asmcode[7:0] 8'01001100
11643       attribute \src "libresoc.v:0.0-0.0"
11644       case 10'0000010010
11645         assign { } { }
11646         assign $1\dec19_asmcode[7:0] 8'10010001
11647       attribute \src "libresoc.v:0.0-0.0"
11648       case 10'0100010010
11649         assign { } { }
11650         assign $1\dec19_asmcode[7:0] 8'01001000
11651       case
11652         assign $1\dec19_asmcode[7:0] 8'00000000
11653     end
11654     sync always
11655       update \dec19_asmcode $0\dec19_asmcode[7:0]
11656   end
11657   attribute \src "libresoc.v:7698.3-7749.6"
11658   process $proc$libresoc.v:7698$269
11659     assign { } { }
11660     assign { } { }
11661     assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0]
11662     attribute \src "libresoc.v:7699.5-7699.29"
11663     switch \initial
11664       attribute \src "libresoc.v:7699.9-7699.17"
11665       case 1'1
11666       case
11667     end
11668     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11669     switch \opcode_switch
11670       attribute \src "libresoc.v:0.0-0.0"
11671       case 10'0000000000
11672         assign { } { }
11673         assign $1\dec19_inv_a[0:0] 1'0
11674       attribute \src "libresoc.v:0.0-0.0"
11675       case 10'0100000001
11676         assign { } { }
11677         assign $1\dec19_inv_a[0:0] 1'0
11678       attribute \src "libresoc.v:0.0-0.0"
11679       case 10'0010000001
11680         assign { } { }
11681         assign $1\dec19_inv_a[0:0] 1'0
11682       attribute \src "libresoc.v:0.0-0.0"
11683       case 10'0100100001
11684         assign { } { }
11685         assign $1\dec19_inv_a[0:0] 1'0
11686       attribute \src "libresoc.v:0.0-0.0"
11687       case 10'0011100001
11688         assign { } { }
11689         assign $1\dec19_inv_a[0:0] 1'0
11690       attribute \src "libresoc.v:0.0-0.0"
11691       case 10'0000100001
11692         assign { } { }
11693         assign $1\dec19_inv_a[0:0] 1'0
11694       attribute \src "libresoc.v:0.0-0.0"
11695       case 10'0111000001
11696         assign { } { }
11697         assign $1\dec19_inv_a[0:0] 1'0
11698       attribute \src "libresoc.v:0.0-0.0"
11699       case 10'0110100001
11700         assign { } { }
11701         assign $1\dec19_inv_a[0:0] 1'0
11702       attribute \src "libresoc.v:0.0-0.0"
11703       case 10'0011000001
11704         assign { } { }
11705         assign $1\dec19_inv_a[0:0] 1'0
11706       attribute \src "libresoc.v:0.0-0.0"
11707       case 10'1000010000
11708         assign { } { }
11709         assign $1\dec19_inv_a[0:0] 1'0
11710       attribute \src "libresoc.v:0.0-0.0"
11711       case 10'0000010000
11712         assign { } { }
11713         assign $1\dec19_inv_a[0:0] 1'0
11714       attribute \src "libresoc.v:0.0-0.0"
11715       case 10'1000110000
11716         assign { } { }
11717         assign $1\dec19_inv_a[0:0] 1'0
11718       attribute \src "libresoc.v:0.0-0.0"
11719       case 10'0010010110
11720         assign { } { }
11721         assign $1\dec19_inv_a[0:0] 1'0
11722       attribute \src "libresoc.v:0.0-0.0"
11723       case 10'0000010010
11724         assign { } { }
11725         assign $1\dec19_inv_a[0:0] 1'0
11726       attribute \src "libresoc.v:0.0-0.0"
11727       case 10'0100010010
11728         assign { } { }
11729         assign $1\dec19_inv_a[0:0] 1'0
11730       case
11731         assign $1\dec19_inv_a[0:0] 1'0
11732     end
11733     sync always
11734       update \dec19_inv_a $0\dec19_inv_a[0:0]
11735   end
11736   attribute \src "libresoc.v:7750.3-7801.6"
11737   process $proc$libresoc.v:7750$270
11738     assign { } { }
11739     assign { } { }
11740     assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0]
11741     attribute \src "libresoc.v:7751.5-7751.29"
11742     switch \initial
11743       attribute \src "libresoc.v:7751.9-7751.17"
11744       case 1'1
11745       case
11746     end
11747     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11748     switch \opcode_switch
11749       attribute \src "libresoc.v:0.0-0.0"
11750       case 10'0000000000
11751         assign { } { }
11752         assign $1\dec19_inv_out[0:0] 1'0
11753       attribute \src "libresoc.v:0.0-0.0"
11754       case 10'0100000001
11755         assign { } { }
11756         assign $1\dec19_inv_out[0:0] 1'0
11757       attribute \src "libresoc.v:0.0-0.0"
11758       case 10'0010000001
11759         assign { } { }
11760         assign $1\dec19_inv_out[0:0] 1'0
11761       attribute \src "libresoc.v:0.0-0.0"
11762       case 10'0100100001
11763         assign { } { }
11764         assign $1\dec19_inv_out[0:0] 1'0
11765       attribute \src "libresoc.v:0.0-0.0"
11766       case 10'0011100001
11767         assign { } { }
11768         assign $1\dec19_inv_out[0:0] 1'0
11769       attribute \src "libresoc.v:0.0-0.0"
11770       case 10'0000100001
11771         assign { } { }
11772         assign $1\dec19_inv_out[0:0] 1'0
11773       attribute \src "libresoc.v:0.0-0.0"
11774       case 10'0111000001
11775         assign { } { }
11776         assign $1\dec19_inv_out[0:0] 1'0
11777       attribute \src "libresoc.v:0.0-0.0"
11778       case 10'0110100001
11779         assign { } { }
11780         assign $1\dec19_inv_out[0:0] 1'0
11781       attribute \src "libresoc.v:0.0-0.0"
11782       case 10'0011000001
11783         assign { } { }
11784         assign $1\dec19_inv_out[0:0] 1'0
11785       attribute \src "libresoc.v:0.0-0.0"
11786       case 10'1000010000
11787         assign { } { }
11788         assign $1\dec19_inv_out[0:0] 1'0
11789       attribute \src "libresoc.v:0.0-0.0"
11790       case 10'0000010000
11791         assign { } { }
11792         assign $1\dec19_inv_out[0:0] 1'0
11793       attribute \src "libresoc.v:0.0-0.0"
11794       case 10'1000110000
11795         assign { } { }
11796         assign $1\dec19_inv_out[0:0] 1'0
11797       attribute \src "libresoc.v:0.0-0.0"
11798       case 10'0010010110
11799         assign { } { }
11800         assign $1\dec19_inv_out[0:0] 1'0
11801       attribute \src "libresoc.v:0.0-0.0"
11802       case 10'0000010010
11803         assign { } { }
11804         assign $1\dec19_inv_out[0:0] 1'0
11805       attribute \src "libresoc.v:0.0-0.0"
11806       case 10'0100010010
11807         assign { } { }
11808         assign $1\dec19_inv_out[0:0] 1'0
11809       case
11810         assign $1\dec19_inv_out[0:0] 1'0
11811     end
11812     sync always
11813       update \dec19_inv_out $0\dec19_inv_out[0:0]
11814   end
11815   attribute \src "libresoc.v:7802.3-7853.6"
11816   process $proc$libresoc.v:7802$271
11817     assign { } { }
11818     assign { } { }
11819     assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0]
11820     attribute \src "libresoc.v:7803.5-7803.29"
11821     switch \initial
11822       attribute \src "libresoc.v:7803.9-7803.17"
11823       case 1'1
11824       case
11825     end
11826     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11827     switch \opcode_switch
11828       attribute \src "libresoc.v:0.0-0.0"
11829       case 10'0000000000
11830         assign { } { }
11831         assign $1\dec19_cry_out[0:0] 1'0
11832       attribute \src "libresoc.v:0.0-0.0"
11833       case 10'0100000001
11834         assign { } { }
11835         assign $1\dec19_cry_out[0:0] 1'0
11836       attribute \src "libresoc.v:0.0-0.0"
11837       case 10'0010000001
11838         assign { } { }
11839         assign $1\dec19_cry_out[0:0] 1'0
11840       attribute \src "libresoc.v:0.0-0.0"
11841       case 10'0100100001
11842         assign { } { }
11843         assign $1\dec19_cry_out[0:0] 1'0
11844       attribute \src "libresoc.v:0.0-0.0"
11845       case 10'0011100001
11846         assign { } { }
11847         assign $1\dec19_cry_out[0:0] 1'0
11848       attribute \src "libresoc.v:0.0-0.0"
11849       case 10'0000100001
11850         assign { } { }
11851         assign $1\dec19_cry_out[0:0] 1'0
11852       attribute \src "libresoc.v:0.0-0.0"
11853       case 10'0111000001
11854         assign { } { }
11855         assign $1\dec19_cry_out[0:0] 1'0
11856       attribute \src "libresoc.v:0.0-0.0"
11857       case 10'0110100001
11858         assign { } { }
11859         assign $1\dec19_cry_out[0:0] 1'0
11860       attribute \src "libresoc.v:0.0-0.0"
11861       case 10'0011000001
11862         assign { } { }
11863         assign $1\dec19_cry_out[0:0] 1'0
11864       attribute \src "libresoc.v:0.0-0.0"
11865       case 10'1000010000
11866         assign { } { }
11867         assign $1\dec19_cry_out[0:0] 1'0
11868       attribute \src "libresoc.v:0.0-0.0"
11869       case 10'0000010000
11870         assign { } { }
11871         assign $1\dec19_cry_out[0:0] 1'0
11872       attribute \src "libresoc.v:0.0-0.0"
11873       case 10'1000110000
11874         assign { } { }
11875         assign $1\dec19_cry_out[0:0] 1'0
11876       attribute \src "libresoc.v:0.0-0.0"
11877       case 10'0010010110
11878         assign { } { }
11879         assign $1\dec19_cry_out[0:0] 1'0
11880       attribute \src "libresoc.v:0.0-0.0"
11881       case 10'0000010010
11882         assign { } { }
11883         assign $1\dec19_cry_out[0:0] 1'0
11884       attribute \src "libresoc.v:0.0-0.0"
11885       case 10'0100010010
11886         assign { } { }
11887         assign $1\dec19_cry_out[0:0] 1'0
11888       case
11889         assign $1\dec19_cry_out[0:0] 1'0
11890     end
11891     sync always
11892       update \dec19_cry_out $0\dec19_cry_out[0:0]
11893   end
11894   attribute \src "libresoc.v:7854.3-7905.6"
11895   process $proc$libresoc.v:7854$272
11896     assign { } { }
11897     assign { } { }
11898     assign $0\dec19_br[0:0] $1\dec19_br[0:0]
11899     attribute \src "libresoc.v:7855.5-7855.29"
11900     switch \initial
11901       attribute \src "libresoc.v:7855.9-7855.17"
11902       case 1'1
11903       case
11904     end
11905     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11906     switch \opcode_switch
11907       attribute \src "libresoc.v:0.0-0.0"
11908       case 10'0000000000
11909         assign { } { }
11910         assign $1\dec19_br[0:0] 1'0
11911       attribute \src "libresoc.v:0.0-0.0"
11912       case 10'0100000001
11913         assign { } { }
11914         assign $1\dec19_br[0:0] 1'0
11915       attribute \src "libresoc.v:0.0-0.0"
11916       case 10'0010000001
11917         assign { } { }
11918         assign $1\dec19_br[0:0] 1'0
11919       attribute \src "libresoc.v:0.0-0.0"
11920       case 10'0100100001
11921         assign { } { }
11922         assign $1\dec19_br[0:0] 1'0
11923       attribute \src "libresoc.v:0.0-0.0"
11924       case 10'0011100001
11925         assign { } { }
11926         assign $1\dec19_br[0:0] 1'0
11927       attribute \src "libresoc.v:0.0-0.0"
11928       case 10'0000100001
11929         assign { } { }
11930         assign $1\dec19_br[0:0] 1'0
11931       attribute \src "libresoc.v:0.0-0.0"
11932       case 10'0111000001
11933         assign { } { }
11934         assign $1\dec19_br[0:0] 1'0
11935       attribute \src "libresoc.v:0.0-0.0"
11936       case 10'0110100001
11937         assign { } { }
11938         assign $1\dec19_br[0:0] 1'0
11939       attribute \src "libresoc.v:0.0-0.0"
11940       case 10'0011000001
11941         assign { } { }
11942         assign $1\dec19_br[0:0] 1'0
11943       attribute \src "libresoc.v:0.0-0.0"
11944       case 10'1000010000
11945         assign { } { }
11946         assign $1\dec19_br[0:0] 1'0
11947       attribute \src "libresoc.v:0.0-0.0"
11948       case 10'0000010000
11949         assign { } { }
11950         assign $1\dec19_br[0:0] 1'0
11951       attribute \src "libresoc.v:0.0-0.0"
11952       case 10'1000110000
11953         assign { } { }
11954         assign $1\dec19_br[0:0] 1'0
11955       attribute \src "libresoc.v:0.0-0.0"
11956       case 10'0010010110
11957         assign { } { }
11958         assign $1\dec19_br[0:0] 1'0
11959       attribute \src "libresoc.v:0.0-0.0"
11960       case 10'0000010010
11961         assign { } { }
11962         assign $1\dec19_br[0:0] 1'0
11963       attribute \src "libresoc.v:0.0-0.0"
11964       case 10'0100010010
11965         assign { } { }
11966         assign $1\dec19_br[0:0] 1'0
11967       case
11968         assign $1\dec19_br[0:0] 1'0
11969     end
11970     sync always
11971       update \dec19_br $0\dec19_br[0:0]
11972   end
11973   attribute \src "libresoc.v:7906.3-7957.6"
11974   process $proc$libresoc.v:7906$273
11975     assign { } { }
11976     assign { } { }
11977     assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0]
11978     attribute \src "libresoc.v:7907.5-7907.29"
11979     switch \initial
11980       attribute \src "libresoc.v:7907.9-7907.17"
11981       case 1'1
11982       case
11983     end
11984     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
11985     switch \opcode_switch
11986       attribute \src "libresoc.v:0.0-0.0"
11987       case 10'0000000000
11988         assign { } { }
11989         assign $1\dec19_sgn_ext[0:0] 1'0
11990       attribute \src "libresoc.v:0.0-0.0"
11991       case 10'0100000001
11992         assign { } { }
11993         assign $1\dec19_sgn_ext[0:0] 1'0
11994       attribute \src "libresoc.v:0.0-0.0"
11995       case 10'0010000001
11996         assign { } { }
11997         assign $1\dec19_sgn_ext[0:0] 1'0
11998       attribute \src "libresoc.v:0.0-0.0"
11999       case 10'0100100001
12000         assign { } { }
12001         assign $1\dec19_sgn_ext[0:0] 1'0
12002       attribute \src "libresoc.v:0.0-0.0"
12003       case 10'0011100001
12004         assign { } { }
12005         assign $1\dec19_sgn_ext[0:0] 1'0
12006       attribute \src "libresoc.v:0.0-0.0"
12007       case 10'0000100001
12008         assign { } { }
12009         assign $1\dec19_sgn_ext[0:0] 1'0
12010       attribute \src "libresoc.v:0.0-0.0"
12011       case 10'0111000001
12012         assign { } { }
12013         assign $1\dec19_sgn_ext[0:0] 1'0
12014       attribute \src "libresoc.v:0.0-0.0"
12015       case 10'0110100001
12016         assign { } { }
12017         assign $1\dec19_sgn_ext[0:0] 1'0
12018       attribute \src "libresoc.v:0.0-0.0"
12019       case 10'0011000001
12020         assign { } { }
12021         assign $1\dec19_sgn_ext[0:0] 1'0
12022       attribute \src "libresoc.v:0.0-0.0"
12023       case 10'1000010000
12024         assign { } { }
12025         assign $1\dec19_sgn_ext[0:0] 1'0
12026       attribute \src "libresoc.v:0.0-0.0"
12027       case 10'0000010000
12028         assign { } { }
12029         assign $1\dec19_sgn_ext[0:0] 1'0
12030       attribute \src "libresoc.v:0.0-0.0"
12031       case 10'1000110000
12032         assign { } { }
12033         assign $1\dec19_sgn_ext[0:0] 1'0
12034       attribute \src "libresoc.v:0.0-0.0"
12035       case 10'0010010110
12036         assign { } { }
12037         assign $1\dec19_sgn_ext[0:0] 1'0
12038       attribute \src "libresoc.v:0.0-0.0"
12039       case 10'0000010010
12040         assign { } { }
12041         assign $1\dec19_sgn_ext[0:0] 1'0
12042       attribute \src "libresoc.v:0.0-0.0"
12043       case 10'0100010010
12044         assign { } { }
12045         assign $1\dec19_sgn_ext[0:0] 1'0
12046       case
12047         assign $1\dec19_sgn_ext[0:0] 1'0
12048     end
12049     sync always
12050       update \dec19_sgn_ext $0\dec19_sgn_ext[0:0]
12051   end
12052   attribute \src "libresoc.v:7958.3-8009.6"
12053   process $proc$libresoc.v:7958$274
12054     assign { } { }
12055     assign { } { }
12056     assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0]
12057     attribute \src "libresoc.v:7959.5-7959.29"
12058     switch \initial
12059       attribute \src "libresoc.v:7959.9-7959.17"
12060       case 1'1
12061       case
12062     end
12063     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12064     switch \opcode_switch
12065       attribute \src "libresoc.v:0.0-0.0"
12066       case 10'0000000000
12067         assign { } { }
12068         assign $1\dec19_internal_op[6:0] 7'0101010
12069       attribute \src "libresoc.v:0.0-0.0"
12070       case 10'0100000001
12071         assign { } { }
12072         assign $1\dec19_internal_op[6:0] 7'1000101
12073       attribute \src "libresoc.v:0.0-0.0"
12074       case 10'0010000001
12075         assign { } { }
12076         assign $1\dec19_internal_op[6:0] 7'1000101
12077       attribute \src "libresoc.v:0.0-0.0"
12078       case 10'0100100001
12079         assign { } { }
12080         assign $1\dec19_internal_op[6:0] 7'1000101
12081       attribute \src "libresoc.v:0.0-0.0"
12082       case 10'0011100001
12083         assign { } { }
12084         assign $1\dec19_internal_op[6:0] 7'1000101
12085       attribute \src "libresoc.v:0.0-0.0"
12086       case 10'0000100001
12087         assign { } { }
12088         assign $1\dec19_internal_op[6:0] 7'1000101
12089       attribute \src "libresoc.v:0.0-0.0"
12090       case 10'0111000001
12091         assign { } { }
12092         assign $1\dec19_internal_op[6:0] 7'1000101
12093       attribute \src "libresoc.v:0.0-0.0"
12094       case 10'0110100001
12095         assign { } { }
12096         assign $1\dec19_internal_op[6:0] 7'1000101
12097       attribute \src "libresoc.v:0.0-0.0"
12098       case 10'0011000001
12099         assign { } { }
12100         assign $1\dec19_internal_op[6:0] 7'1000101
12101       attribute \src "libresoc.v:0.0-0.0"
12102       case 10'1000010000
12103         assign { } { }
12104         assign $1\dec19_internal_op[6:0] 7'0001000
12105       attribute \src "libresoc.v:0.0-0.0"
12106       case 10'0000010000
12107         assign { } { }
12108         assign $1\dec19_internal_op[6:0] 7'0001000
12109       attribute \src "libresoc.v:0.0-0.0"
12110       case 10'1000110000
12111         assign { } { }
12112         assign $1\dec19_internal_op[6:0] 7'0001000
12113       attribute \src "libresoc.v:0.0-0.0"
12114       case 10'0010010110
12115         assign { } { }
12116         assign $1\dec19_internal_op[6:0] 7'0100100
12117       attribute \src "libresoc.v:0.0-0.0"
12118       case 10'0000010010
12119         assign { } { }
12120         assign $1\dec19_internal_op[6:0] 7'1000110
12121       attribute \src "libresoc.v:0.0-0.0"
12122       case 10'0100010010
12123         assign { } { }
12124         assign $1\dec19_internal_op[6:0] 7'1000110
12125       case
12126         assign $1\dec19_internal_op[6:0] 7'0000000
12127     end
12128     sync always
12129       update \dec19_internal_op $0\dec19_internal_op[6:0]
12130   end
12131   attribute \src "libresoc.v:8010.3-8061.6"
12132   process $proc$libresoc.v:8010$275
12133     assign { } { }
12134     assign { } { }
12135     assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0]
12136     attribute \src "libresoc.v:8011.5-8011.29"
12137     switch \initial
12138       attribute \src "libresoc.v:8011.9-8011.17"
12139       case 1'1
12140       case
12141     end
12142     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12143     switch \opcode_switch
12144       attribute \src "libresoc.v:0.0-0.0"
12145       case 10'0000000000
12146         assign { } { }
12147         assign $1\dec19_rsrv[0:0] 1'0
12148       attribute \src "libresoc.v:0.0-0.0"
12149       case 10'0100000001
12150         assign { } { }
12151         assign $1\dec19_rsrv[0:0] 1'0
12152       attribute \src "libresoc.v:0.0-0.0"
12153       case 10'0010000001
12154         assign { } { }
12155         assign $1\dec19_rsrv[0:0] 1'0
12156       attribute \src "libresoc.v:0.0-0.0"
12157       case 10'0100100001
12158         assign { } { }
12159         assign $1\dec19_rsrv[0:0] 1'0
12160       attribute \src "libresoc.v:0.0-0.0"
12161       case 10'0011100001
12162         assign { } { }
12163         assign $1\dec19_rsrv[0:0] 1'0
12164       attribute \src "libresoc.v:0.0-0.0"
12165       case 10'0000100001
12166         assign { } { }
12167         assign $1\dec19_rsrv[0:0] 1'0
12168       attribute \src "libresoc.v:0.0-0.0"
12169       case 10'0111000001
12170         assign { } { }
12171         assign $1\dec19_rsrv[0:0] 1'0
12172       attribute \src "libresoc.v:0.0-0.0"
12173       case 10'0110100001
12174         assign { } { }
12175         assign $1\dec19_rsrv[0:0] 1'0
12176       attribute \src "libresoc.v:0.0-0.0"
12177       case 10'0011000001
12178         assign { } { }
12179         assign $1\dec19_rsrv[0:0] 1'0
12180       attribute \src "libresoc.v:0.0-0.0"
12181       case 10'1000010000
12182         assign { } { }
12183         assign $1\dec19_rsrv[0:0] 1'0
12184       attribute \src "libresoc.v:0.0-0.0"
12185       case 10'0000010000
12186         assign { } { }
12187         assign $1\dec19_rsrv[0:0] 1'0
12188       attribute \src "libresoc.v:0.0-0.0"
12189       case 10'1000110000
12190         assign { } { }
12191         assign $1\dec19_rsrv[0:0] 1'0
12192       attribute \src "libresoc.v:0.0-0.0"
12193       case 10'0010010110
12194         assign { } { }
12195         assign $1\dec19_rsrv[0:0] 1'0
12196       attribute \src "libresoc.v:0.0-0.0"
12197       case 10'0000010010
12198         assign { } { }
12199         assign $1\dec19_rsrv[0:0] 1'0
12200       attribute \src "libresoc.v:0.0-0.0"
12201       case 10'0100010010
12202         assign { } { }
12203         assign $1\dec19_rsrv[0:0] 1'0
12204       case
12205         assign $1\dec19_rsrv[0:0] 1'0
12206     end
12207     sync always
12208       update \dec19_rsrv $0\dec19_rsrv[0:0]
12209   end
12210   attribute \src "libresoc.v:8062.3-8113.6"
12211   process $proc$libresoc.v:8062$276
12212     assign { } { }
12213     assign { } { }
12214     assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0]
12215     attribute \src "libresoc.v:8063.5-8063.29"
12216     switch \initial
12217       attribute \src "libresoc.v:8063.9-8063.17"
12218       case 1'1
12219       case
12220     end
12221     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12222     switch \opcode_switch
12223       attribute \src "libresoc.v:0.0-0.0"
12224       case 10'0000000000
12225         assign { } { }
12226         assign $1\dec19_is_32b[0:0] 1'0
12227       attribute \src "libresoc.v:0.0-0.0"
12228       case 10'0100000001
12229         assign { } { }
12230         assign $1\dec19_is_32b[0:0] 1'0
12231       attribute \src "libresoc.v:0.0-0.0"
12232       case 10'0010000001
12233         assign { } { }
12234         assign $1\dec19_is_32b[0:0] 1'0
12235       attribute \src "libresoc.v:0.0-0.0"
12236       case 10'0100100001
12237         assign { } { }
12238         assign $1\dec19_is_32b[0:0] 1'0
12239       attribute \src "libresoc.v:0.0-0.0"
12240       case 10'0011100001
12241         assign { } { }
12242         assign $1\dec19_is_32b[0:0] 1'0
12243       attribute \src "libresoc.v:0.0-0.0"
12244       case 10'0000100001
12245         assign { } { }
12246         assign $1\dec19_is_32b[0:0] 1'0
12247       attribute \src "libresoc.v:0.0-0.0"
12248       case 10'0111000001
12249         assign { } { }
12250         assign $1\dec19_is_32b[0:0] 1'0
12251       attribute \src "libresoc.v:0.0-0.0"
12252       case 10'0110100001
12253         assign { } { }
12254         assign $1\dec19_is_32b[0:0] 1'0
12255       attribute \src "libresoc.v:0.0-0.0"
12256       case 10'0011000001
12257         assign { } { }
12258         assign $1\dec19_is_32b[0:0] 1'0
12259       attribute \src "libresoc.v:0.0-0.0"
12260       case 10'1000010000
12261         assign { } { }
12262         assign $1\dec19_is_32b[0:0] 1'0
12263       attribute \src "libresoc.v:0.0-0.0"
12264       case 10'0000010000
12265         assign { } { }
12266         assign $1\dec19_is_32b[0:0] 1'0
12267       attribute \src "libresoc.v:0.0-0.0"
12268       case 10'1000110000
12269         assign { } { }
12270         assign $1\dec19_is_32b[0:0] 1'0
12271       attribute \src "libresoc.v:0.0-0.0"
12272       case 10'0010010110
12273         assign { } { }
12274         assign $1\dec19_is_32b[0:0] 1'0
12275       attribute \src "libresoc.v:0.0-0.0"
12276       case 10'0000010010
12277         assign { } { }
12278         assign $1\dec19_is_32b[0:0] 1'0
12279       attribute \src "libresoc.v:0.0-0.0"
12280       case 10'0100010010
12281         assign { } { }
12282         assign $1\dec19_is_32b[0:0] 1'0
12283       case
12284         assign $1\dec19_is_32b[0:0] 1'0
12285     end
12286     sync always
12287       update \dec19_is_32b $0\dec19_is_32b[0:0]
12288   end
12289   attribute \src "libresoc.v:8114.3-8165.6"
12290   process $proc$libresoc.v:8114$277
12291     assign { } { }
12292     assign { } { }
12293     assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0]
12294     attribute \src "libresoc.v:8115.5-8115.29"
12295     switch \initial
12296       attribute \src "libresoc.v:8115.9-8115.17"
12297       case 1'1
12298       case
12299     end
12300     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12301     switch \opcode_switch
12302       attribute \src "libresoc.v:0.0-0.0"
12303       case 10'0000000000
12304         assign { } { }
12305         assign $1\dec19_sgn[0:0] 1'0
12306       attribute \src "libresoc.v:0.0-0.0"
12307       case 10'0100000001
12308         assign { } { }
12309         assign $1\dec19_sgn[0:0] 1'0
12310       attribute \src "libresoc.v:0.0-0.0"
12311       case 10'0010000001
12312         assign { } { }
12313         assign $1\dec19_sgn[0:0] 1'0
12314       attribute \src "libresoc.v:0.0-0.0"
12315       case 10'0100100001
12316         assign { } { }
12317         assign $1\dec19_sgn[0:0] 1'0
12318       attribute \src "libresoc.v:0.0-0.0"
12319       case 10'0011100001
12320         assign { } { }
12321         assign $1\dec19_sgn[0:0] 1'0
12322       attribute \src "libresoc.v:0.0-0.0"
12323       case 10'0000100001
12324         assign { } { }
12325         assign $1\dec19_sgn[0:0] 1'0
12326       attribute \src "libresoc.v:0.0-0.0"
12327       case 10'0111000001
12328         assign { } { }
12329         assign $1\dec19_sgn[0:0] 1'0
12330       attribute \src "libresoc.v:0.0-0.0"
12331       case 10'0110100001
12332         assign { } { }
12333         assign $1\dec19_sgn[0:0] 1'0
12334       attribute \src "libresoc.v:0.0-0.0"
12335       case 10'0011000001
12336         assign { } { }
12337         assign $1\dec19_sgn[0:0] 1'0
12338       attribute \src "libresoc.v:0.0-0.0"
12339       case 10'1000010000
12340         assign { } { }
12341         assign $1\dec19_sgn[0:0] 1'0
12342       attribute \src "libresoc.v:0.0-0.0"
12343       case 10'0000010000
12344         assign { } { }
12345         assign $1\dec19_sgn[0:0] 1'0
12346       attribute \src "libresoc.v:0.0-0.0"
12347       case 10'1000110000
12348         assign { } { }
12349         assign $1\dec19_sgn[0:0] 1'0
12350       attribute \src "libresoc.v:0.0-0.0"
12351       case 10'0010010110
12352         assign { } { }
12353         assign $1\dec19_sgn[0:0] 1'0
12354       attribute \src "libresoc.v:0.0-0.0"
12355       case 10'0000010010
12356         assign { } { }
12357         assign $1\dec19_sgn[0:0] 1'0
12358       attribute \src "libresoc.v:0.0-0.0"
12359       case 10'0100010010
12360         assign { } { }
12361         assign $1\dec19_sgn[0:0] 1'0
12362       case
12363         assign $1\dec19_sgn[0:0] 1'0
12364     end
12365     sync always
12366       update \dec19_sgn $0\dec19_sgn[0:0]
12367   end
12368   attribute \src "libresoc.v:8166.3-8217.6"
12369   process $proc$libresoc.v:8166$278
12370     assign { } { }
12371     assign { } { }
12372     assign $0\dec19_lk[0:0] $1\dec19_lk[0:0]
12373     attribute \src "libresoc.v:8167.5-8167.29"
12374     switch \initial
12375       attribute \src "libresoc.v:8167.9-8167.17"
12376       case 1'1
12377       case
12378     end
12379     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12380     switch \opcode_switch
12381       attribute \src "libresoc.v:0.0-0.0"
12382       case 10'0000000000
12383         assign { } { }
12384         assign $1\dec19_lk[0:0] 1'0
12385       attribute \src "libresoc.v:0.0-0.0"
12386       case 10'0100000001
12387         assign { } { }
12388         assign $1\dec19_lk[0:0] 1'0
12389       attribute \src "libresoc.v:0.0-0.0"
12390       case 10'0010000001
12391         assign { } { }
12392         assign $1\dec19_lk[0:0] 1'0
12393       attribute \src "libresoc.v:0.0-0.0"
12394       case 10'0100100001
12395         assign { } { }
12396         assign $1\dec19_lk[0:0] 1'0
12397       attribute \src "libresoc.v:0.0-0.0"
12398       case 10'0011100001
12399         assign { } { }
12400         assign $1\dec19_lk[0:0] 1'0
12401       attribute \src "libresoc.v:0.0-0.0"
12402       case 10'0000100001
12403         assign { } { }
12404         assign $1\dec19_lk[0:0] 1'0
12405       attribute \src "libresoc.v:0.0-0.0"
12406       case 10'0111000001
12407         assign { } { }
12408         assign $1\dec19_lk[0:0] 1'0
12409       attribute \src "libresoc.v:0.0-0.0"
12410       case 10'0110100001
12411         assign { } { }
12412         assign $1\dec19_lk[0:0] 1'0
12413       attribute \src "libresoc.v:0.0-0.0"
12414       case 10'0011000001
12415         assign { } { }
12416         assign $1\dec19_lk[0:0] 1'0
12417       attribute \src "libresoc.v:0.0-0.0"
12418       case 10'1000010000
12419         assign { } { }
12420         assign $1\dec19_lk[0:0] 1'1
12421       attribute \src "libresoc.v:0.0-0.0"
12422       case 10'0000010000
12423         assign { } { }
12424         assign $1\dec19_lk[0:0] 1'1
12425       attribute \src "libresoc.v:0.0-0.0"
12426       case 10'1000110000
12427         assign { } { }
12428         assign $1\dec19_lk[0:0] 1'1
12429       attribute \src "libresoc.v:0.0-0.0"
12430       case 10'0010010110
12431         assign { } { }
12432         assign $1\dec19_lk[0:0] 1'0
12433       attribute \src "libresoc.v:0.0-0.0"
12434       case 10'0000010010
12435         assign { } { }
12436         assign $1\dec19_lk[0:0] 1'0
12437       attribute \src "libresoc.v:0.0-0.0"
12438       case 10'0100010010
12439         assign { } { }
12440         assign $1\dec19_lk[0:0] 1'0
12441       case
12442         assign $1\dec19_lk[0:0] 1'0
12443     end
12444     sync always
12445       update \dec19_lk $0\dec19_lk[0:0]
12446   end
12447   attribute \src "libresoc.v:8218.3-8269.6"
12448   process $proc$libresoc.v:8218$279
12449     assign { } { }
12450     assign { } { }
12451     assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0]
12452     attribute \src "libresoc.v:8219.5-8219.29"
12453     switch \initial
12454       attribute \src "libresoc.v:8219.9-8219.17"
12455       case 1'1
12456       case
12457     end
12458     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12459     switch \opcode_switch
12460       attribute \src "libresoc.v:0.0-0.0"
12461       case 10'0000000000
12462         assign { } { }
12463         assign $1\dec19_sgl_pipe[0:0] 1'0
12464       attribute \src "libresoc.v:0.0-0.0"
12465       case 10'0100000001
12466         assign { } { }
12467         assign $1\dec19_sgl_pipe[0:0] 1'0
12468       attribute \src "libresoc.v:0.0-0.0"
12469       case 10'0010000001
12470         assign { } { }
12471         assign $1\dec19_sgl_pipe[0:0] 1'0
12472       attribute \src "libresoc.v:0.0-0.0"
12473       case 10'0100100001
12474         assign { } { }
12475         assign $1\dec19_sgl_pipe[0:0] 1'0
12476       attribute \src "libresoc.v:0.0-0.0"
12477       case 10'0011100001
12478         assign { } { }
12479         assign $1\dec19_sgl_pipe[0:0] 1'0
12480       attribute \src "libresoc.v:0.0-0.0"
12481       case 10'0000100001
12482         assign { } { }
12483         assign $1\dec19_sgl_pipe[0:0] 1'0
12484       attribute \src "libresoc.v:0.0-0.0"
12485       case 10'0111000001
12486         assign { } { }
12487         assign $1\dec19_sgl_pipe[0:0] 1'0
12488       attribute \src "libresoc.v:0.0-0.0"
12489       case 10'0110100001
12490         assign { } { }
12491         assign $1\dec19_sgl_pipe[0:0] 1'0
12492       attribute \src "libresoc.v:0.0-0.0"
12493       case 10'0011000001
12494         assign { } { }
12495         assign $1\dec19_sgl_pipe[0:0] 1'0
12496       attribute \src "libresoc.v:0.0-0.0"
12497       case 10'1000010000
12498         assign { } { }
12499         assign $1\dec19_sgl_pipe[0:0] 1'0
12500       attribute \src "libresoc.v:0.0-0.0"
12501       case 10'0000010000
12502         assign { } { }
12503         assign $1\dec19_sgl_pipe[0:0] 1'0
12504       attribute \src "libresoc.v:0.0-0.0"
12505       case 10'1000110000
12506         assign { } { }
12507         assign $1\dec19_sgl_pipe[0:0] 1'0
12508       attribute \src "libresoc.v:0.0-0.0"
12509       case 10'0010010110
12510         assign { } { }
12511         assign $1\dec19_sgl_pipe[0:0] 1'1
12512       attribute \src "libresoc.v:0.0-0.0"
12513       case 10'0000010010
12514         assign { } { }
12515         assign $1\dec19_sgl_pipe[0:0] 1'0
12516       attribute \src "libresoc.v:0.0-0.0"
12517       case 10'0100010010
12518         assign { } { }
12519         assign $1\dec19_sgl_pipe[0:0] 1'0
12520       case
12521         assign $1\dec19_sgl_pipe[0:0] 1'0
12522     end
12523     sync always
12524       update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0]
12525   end
12526   attribute \src "libresoc.v:8270.3-8321.6"
12527   process $proc$libresoc.v:8270$280
12528     assign { } { }
12529     assign { } { }
12530     assign $0\dec19_form[4:0] $1\dec19_form[4:0]
12531     attribute \src "libresoc.v:8271.5-8271.29"
12532     switch \initial
12533       attribute \src "libresoc.v:8271.9-8271.17"
12534       case 1'1
12535       case
12536     end
12537     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12538     switch \opcode_switch
12539       attribute \src "libresoc.v:0.0-0.0"
12540       case 10'0000000000
12541         assign { } { }
12542         assign $1\dec19_form[4:0] 5'01001
12543       attribute \src "libresoc.v:0.0-0.0"
12544       case 10'0100000001
12545         assign { } { }
12546         assign $1\dec19_form[4:0] 5'01001
12547       attribute \src "libresoc.v:0.0-0.0"
12548       case 10'0010000001
12549         assign { } { }
12550         assign $1\dec19_form[4:0] 5'01001
12551       attribute \src "libresoc.v:0.0-0.0"
12552       case 10'0100100001
12553         assign { } { }
12554         assign $1\dec19_form[4:0] 5'01001
12555       attribute \src "libresoc.v:0.0-0.0"
12556       case 10'0011100001
12557         assign { } { }
12558         assign $1\dec19_form[4:0] 5'01001
12559       attribute \src "libresoc.v:0.0-0.0"
12560       case 10'0000100001
12561         assign { } { }
12562         assign $1\dec19_form[4:0] 5'01001
12563       attribute \src "libresoc.v:0.0-0.0"
12564       case 10'0111000001
12565         assign { } { }
12566         assign $1\dec19_form[4:0] 5'01001
12567       attribute \src "libresoc.v:0.0-0.0"
12568       case 10'0110100001
12569         assign { } { }
12570         assign $1\dec19_form[4:0] 5'01001
12571       attribute \src "libresoc.v:0.0-0.0"
12572       case 10'0011000001
12573         assign { } { }
12574         assign $1\dec19_form[4:0] 5'01001
12575       attribute \src "libresoc.v:0.0-0.0"
12576       case 10'1000010000
12577         assign { } { }
12578         assign $1\dec19_form[4:0] 5'01001
12579       attribute \src "libresoc.v:0.0-0.0"
12580       case 10'0000010000
12581         assign { } { }
12582         assign $1\dec19_form[4:0] 5'01001
12583       attribute \src "libresoc.v:0.0-0.0"
12584       case 10'1000110000
12585         assign { } { }
12586         assign $1\dec19_form[4:0] 5'01001
12587       attribute \src "libresoc.v:0.0-0.0"
12588       case 10'0010010110
12589         assign { } { }
12590         assign $1\dec19_form[4:0] 5'01001
12591       attribute \src "libresoc.v:0.0-0.0"
12592       case 10'0000010010
12593         assign { } { }
12594         assign $1\dec19_form[4:0] 5'01001
12595       attribute \src "libresoc.v:0.0-0.0"
12596       case 10'0100010010
12597         assign { } { }
12598         assign $1\dec19_form[4:0] 5'01001
12599       case
12600         assign $1\dec19_form[4:0] 5'00000
12601     end
12602     sync always
12603       update \dec19_form $0\dec19_form[4:0]
12604   end
12605   attribute \src "libresoc.v:8322.3-8373.6"
12606   process $proc$libresoc.v:8322$281
12607     assign { } { }
12608     assign { } { }
12609     assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0]
12610     attribute \src "libresoc.v:8323.5-8323.29"
12611     switch \initial
12612       attribute \src "libresoc.v:8323.9-8323.17"
12613       case 1'1
12614       case
12615     end
12616     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12617     switch \opcode_switch
12618       attribute \src "libresoc.v:0.0-0.0"
12619       case 10'0000000000
12620         assign { } { }
12621         assign $1\dec19_in1_sel[2:0] 3'000
12622       attribute \src "libresoc.v:0.0-0.0"
12623       case 10'0100000001
12624         assign { } { }
12625         assign $1\dec19_in1_sel[2:0] 3'000
12626       attribute \src "libresoc.v:0.0-0.0"
12627       case 10'0010000001
12628         assign { } { }
12629         assign $1\dec19_in1_sel[2:0] 3'000
12630       attribute \src "libresoc.v:0.0-0.0"
12631       case 10'0100100001
12632         assign { } { }
12633         assign $1\dec19_in1_sel[2:0] 3'000
12634       attribute \src "libresoc.v:0.0-0.0"
12635       case 10'0011100001
12636         assign { } { }
12637         assign $1\dec19_in1_sel[2:0] 3'000
12638       attribute \src "libresoc.v:0.0-0.0"
12639       case 10'0000100001
12640         assign { } { }
12641         assign $1\dec19_in1_sel[2:0] 3'000
12642       attribute \src "libresoc.v:0.0-0.0"
12643       case 10'0111000001
12644         assign { } { }
12645         assign $1\dec19_in1_sel[2:0] 3'000
12646       attribute \src "libresoc.v:0.0-0.0"
12647       case 10'0110100001
12648         assign { } { }
12649         assign $1\dec19_in1_sel[2:0] 3'000
12650       attribute \src "libresoc.v:0.0-0.0"
12651       case 10'0011000001
12652         assign { } { }
12653         assign $1\dec19_in1_sel[2:0] 3'000
12654       attribute \src "libresoc.v:0.0-0.0"
12655       case 10'1000010000
12656         assign { } { }
12657         assign $1\dec19_in1_sel[2:0] 3'011
12658       attribute \src "libresoc.v:0.0-0.0"
12659       case 10'0000010000
12660         assign { } { }
12661         assign $1\dec19_in1_sel[2:0] 3'011
12662       attribute \src "libresoc.v:0.0-0.0"
12663       case 10'1000110000
12664         assign { } { }
12665         assign $1\dec19_in1_sel[2:0] 3'011
12666       attribute \src "libresoc.v:0.0-0.0"
12667       case 10'0010010110
12668         assign { } { }
12669         assign $1\dec19_in1_sel[2:0] 3'000
12670       attribute \src "libresoc.v:0.0-0.0"
12671       case 10'0000010010
12672         assign { } { }
12673         assign $1\dec19_in1_sel[2:0] 3'011
12674       attribute \src "libresoc.v:0.0-0.0"
12675       case 10'0100010010
12676         assign { } { }
12677         assign $1\dec19_in1_sel[2:0] 3'011
12678       case
12679         assign $1\dec19_in1_sel[2:0] 3'000
12680     end
12681     sync always
12682       update \dec19_in1_sel $0\dec19_in1_sel[2:0]
12683   end
12684   attribute \src "libresoc.v:8374.3-8425.6"
12685   process $proc$libresoc.v:8374$282
12686     assign { } { }
12687     assign { } { }
12688     assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0]
12689     attribute \src "libresoc.v:8375.5-8375.29"
12690     switch \initial
12691       attribute \src "libresoc.v:8375.9-8375.17"
12692       case 1'1
12693       case
12694     end
12695     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12696     switch \opcode_switch
12697       attribute \src "libresoc.v:0.0-0.0"
12698       case 10'0000000000
12699         assign { } { }
12700         assign $1\dec19_in2_sel[3:0] 4'0000
12701       attribute \src "libresoc.v:0.0-0.0"
12702       case 10'0100000001
12703         assign { } { }
12704         assign $1\dec19_in2_sel[3:0] 4'0000
12705       attribute \src "libresoc.v:0.0-0.0"
12706       case 10'0010000001
12707         assign { } { }
12708         assign $1\dec19_in2_sel[3:0] 4'0000
12709       attribute \src "libresoc.v:0.0-0.0"
12710       case 10'0100100001
12711         assign { } { }
12712         assign $1\dec19_in2_sel[3:0] 4'0000
12713       attribute \src "libresoc.v:0.0-0.0"
12714       case 10'0011100001
12715         assign { } { }
12716         assign $1\dec19_in2_sel[3:0] 4'0000
12717       attribute \src "libresoc.v:0.0-0.0"
12718       case 10'0000100001
12719         assign { } { }
12720         assign $1\dec19_in2_sel[3:0] 4'0000
12721       attribute \src "libresoc.v:0.0-0.0"
12722       case 10'0111000001
12723         assign { } { }
12724         assign $1\dec19_in2_sel[3:0] 4'0000
12725       attribute \src "libresoc.v:0.0-0.0"
12726       case 10'0110100001
12727         assign { } { }
12728         assign $1\dec19_in2_sel[3:0] 4'0000
12729       attribute \src "libresoc.v:0.0-0.0"
12730       case 10'0011000001
12731         assign { } { }
12732         assign $1\dec19_in2_sel[3:0] 4'0000
12733       attribute \src "libresoc.v:0.0-0.0"
12734       case 10'1000010000
12735         assign { } { }
12736         assign $1\dec19_in2_sel[3:0] 4'1100
12737       attribute \src "libresoc.v:0.0-0.0"
12738       case 10'0000010000
12739         assign { } { }
12740         assign $1\dec19_in2_sel[3:0] 4'1100
12741       attribute \src "libresoc.v:0.0-0.0"
12742       case 10'1000110000
12743         assign { } { }
12744         assign $1\dec19_in2_sel[3:0] 4'1100
12745       attribute \src "libresoc.v:0.0-0.0"
12746       case 10'0010010110
12747         assign { } { }
12748         assign $1\dec19_in2_sel[3:0] 4'0000
12749       attribute \src "libresoc.v:0.0-0.0"
12750       case 10'0000010010
12751         assign { } { }
12752         assign $1\dec19_in2_sel[3:0] 4'1100
12753       attribute \src "libresoc.v:0.0-0.0"
12754       case 10'0100010010
12755         assign { } { }
12756         assign $1\dec19_in2_sel[3:0] 4'1100
12757       case
12758         assign $1\dec19_in2_sel[3:0] 4'0000
12759     end
12760     sync always
12761       update \dec19_in2_sel $0\dec19_in2_sel[3:0]
12762   end
12763   attribute \src "libresoc.v:8426.3-8477.6"
12764   process $proc$libresoc.v:8426$283
12765     assign { } { }
12766     assign { } { }
12767     assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0]
12768     attribute \src "libresoc.v:8427.5-8427.29"
12769     switch \initial
12770       attribute \src "libresoc.v:8427.9-8427.17"
12771       case 1'1
12772       case
12773     end
12774     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12775     switch \opcode_switch
12776       attribute \src "libresoc.v:0.0-0.0"
12777       case 10'0000000000
12778         assign { } { }
12779         assign $1\dec19_in3_sel[1:0] 2'00
12780       attribute \src "libresoc.v:0.0-0.0"
12781       case 10'0100000001
12782         assign { } { }
12783         assign $1\dec19_in3_sel[1:0] 2'00
12784       attribute \src "libresoc.v:0.0-0.0"
12785       case 10'0010000001
12786         assign { } { }
12787         assign $1\dec19_in3_sel[1:0] 2'00
12788       attribute \src "libresoc.v:0.0-0.0"
12789       case 10'0100100001
12790         assign { } { }
12791         assign $1\dec19_in3_sel[1:0] 2'00
12792       attribute \src "libresoc.v:0.0-0.0"
12793       case 10'0011100001
12794         assign { } { }
12795         assign $1\dec19_in3_sel[1:0] 2'00
12796       attribute \src "libresoc.v:0.0-0.0"
12797       case 10'0000100001
12798         assign { } { }
12799         assign $1\dec19_in3_sel[1:0] 2'00
12800       attribute \src "libresoc.v:0.0-0.0"
12801       case 10'0111000001
12802         assign { } { }
12803         assign $1\dec19_in3_sel[1:0] 2'00
12804       attribute \src "libresoc.v:0.0-0.0"
12805       case 10'0110100001
12806         assign { } { }
12807         assign $1\dec19_in3_sel[1:0] 2'00
12808       attribute \src "libresoc.v:0.0-0.0"
12809       case 10'0011000001
12810         assign { } { }
12811         assign $1\dec19_in3_sel[1:0] 2'00
12812       attribute \src "libresoc.v:0.0-0.0"
12813       case 10'1000010000
12814         assign { } { }
12815         assign $1\dec19_in3_sel[1:0] 2'00
12816       attribute \src "libresoc.v:0.0-0.0"
12817       case 10'0000010000
12818         assign { } { }
12819         assign $1\dec19_in3_sel[1:0] 2'00
12820       attribute \src "libresoc.v:0.0-0.0"
12821       case 10'1000110000
12822         assign { } { }
12823         assign $1\dec19_in3_sel[1:0] 2'00
12824       attribute \src "libresoc.v:0.0-0.0"
12825       case 10'0010010110
12826         assign { } { }
12827         assign $1\dec19_in3_sel[1:0] 2'00
12828       attribute \src "libresoc.v:0.0-0.0"
12829       case 10'0000010010
12830         assign { } { }
12831         assign $1\dec19_in3_sel[1:0] 2'00
12832       attribute \src "libresoc.v:0.0-0.0"
12833       case 10'0100010010
12834         assign { } { }
12835         assign $1\dec19_in3_sel[1:0] 2'00
12836       case
12837         assign $1\dec19_in3_sel[1:0] 2'00
12838     end
12839     sync always
12840       update \dec19_in3_sel $0\dec19_in3_sel[1:0]
12841   end
12842   attribute \src "libresoc.v:8478.3-8529.6"
12843   process $proc$libresoc.v:8478$284
12844     assign { } { }
12845     assign { } { }
12846     assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0]
12847     attribute \src "libresoc.v:8479.5-8479.29"
12848     switch \initial
12849       attribute \src "libresoc.v:8479.9-8479.17"
12850       case 1'1
12851       case
12852     end
12853     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12854     switch \opcode_switch
12855       attribute \src "libresoc.v:0.0-0.0"
12856       case 10'0000000000
12857         assign { } { }
12858         assign $1\dec19_out_sel[1:0] 2'00
12859       attribute \src "libresoc.v:0.0-0.0"
12860       case 10'0100000001
12861         assign { } { }
12862         assign $1\dec19_out_sel[1:0] 2'00
12863       attribute \src "libresoc.v:0.0-0.0"
12864       case 10'0010000001
12865         assign { } { }
12866         assign $1\dec19_out_sel[1:0] 2'00
12867       attribute \src "libresoc.v:0.0-0.0"
12868       case 10'0100100001
12869         assign { } { }
12870         assign $1\dec19_out_sel[1:0] 2'00
12871       attribute \src "libresoc.v:0.0-0.0"
12872       case 10'0011100001
12873         assign { } { }
12874         assign $1\dec19_out_sel[1:0] 2'00
12875       attribute \src "libresoc.v:0.0-0.0"
12876       case 10'0000100001
12877         assign { } { }
12878         assign $1\dec19_out_sel[1:0] 2'00
12879       attribute \src "libresoc.v:0.0-0.0"
12880       case 10'0111000001
12881         assign { } { }
12882         assign $1\dec19_out_sel[1:0] 2'00
12883       attribute \src "libresoc.v:0.0-0.0"
12884       case 10'0110100001
12885         assign { } { }
12886         assign $1\dec19_out_sel[1:0] 2'00
12887       attribute \src "libresoc.v:0.0-0.0"
12888       case 10'0011000001
12889         assign { } { }
12890         assign $1\dec19_out_sel[1:0] 2'00
12891       attribute \src "libresoc.v:0.0-0.0"
12892       case 10'1000010000
12893         assign { } { }
12894         assign $1\dec19_out_sel[1:0] 2'11
12895       attribute \src "libresoc.v:0.0-0.0"
12896       case 10'0000010000
12897         assign { } { }
12898         assign $1\dec19_out_sel[1:0] 2'11
12899       attribute \src "libresoc.v:0.0-0.0"
12900       case 10'1000110000
12901         assign { } { }
12902         assign $1\dec19_out_sel[1:0] 2'11
12903       attribute \src "libresoc.v:0.0-0.0"
12904       case 10'0010010110
12905         assign { } { }
12906         assign $1\dec19_out_sel[1:0] 2'00
12907       attribute \src "libresoc.v:0.0-0.0"
12908       case 10'0000010010
12909         assign { } { }
12910         assign $1\dec19_out_sel[1:0] 2'00
12911       attribute \src "libresoc.v:0.0-0.0"
12912       case 10'0100010010
12913         assign { } { }
12914         assign $1\dec19_out_sel[1:0] 2'00
12915       case
12916         assign $1\dec19_out_sel[1:0] 2'00
12917     end
12918     sync always
12919       update \dec19_out_sel $0\dec19_out_sel[1:0]
12920   end
12921   attribute \src "libresoc.v:8530.3-8581.6"
12922   process $proc$libresoc.v:8530$285
12923     assign { } { }
12924     assign { } { }
12925     assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0]
12926     attribute \src "libresoc.v:8531.5-8531.29"
12927     switch \initial
12928       attribute \src "libresoc.v:8531.9-8531.17"
12929       case 1'1
12930       case
12931     end
12932     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
12933     switch \opcode_switch
12934       attribute \src "libresoc.v:0.0-0.0"
12935       case 10'0000000000
12936         assign { } { }
12937         assign $1\dec19_cr_in[2:0] 3'011
12938       attribute \src "libresoc.v:0.0-0.0"
12939       case 10'0100000001
12940         assign { } { }
12941         assign $1\dec19_cr_in[2:0] 3'100
12942       attribute \src "libresoc.v:0.0-0.0"
12943       case 10'0010000001
12944         assign { } { }
12945         assign $1\dec19_cr_in[2:0] 3'100
12946       attribute \src "libresoc.v:0.0-0.0"
12947       case 10'0100100001
12948         assign { } { }
12949         assign $1\dec19_cr_in[2:0] 3'100
12950       attribute \src "libresoc.v:0.0-0.0"
12951       case 10'0011100001
12952         assign { } { }
12953         assign $1\dec19_cr_in[2:0] 3'100
12954       attribute \src "libresoc.v:0.0-0.0"
12955       case 10'0000100001
12956         assign { } { }
12957         assign $1\dec19_cr_in[2:0] 3'100
12958       attribute \src "libresoc.v:0.0-0.0"
12959       case 10'0111000001
12960         assign { } { }
12961         assign $1\dec19_cr_in[2:0] 3'100
12962       attribute \src "libresoc.v:0.0-0.0"
12963       case 10'0110100001
12964         assign { } { }
12965         assign $1\dec19_cr_in[2:0] 3'100
12966       attribute \src "libresoc.v:0.0-0.0"
12967       case 10'0011000001
12968         assign { } { }
12969         assign $1\dec19_cr_in[2:0] 3'100
12970       attribute \src "libresoc.v:0.0-0.0"
12971       case 10'1000010000
12972         assign { } { }
12973         assign $1\dec19_cr_in[2:0] 3'010
12974       attribute \src "libresoc.v:0.0-0.0"
12975       case 10'0000010000
12976         assign { } { }
12977         assign $1\dec19_cr_in[2:0] 3'010
12978       attribute \src "libresoc.v:0.0-0.0"
12979       case 10'1000110000
12980         assign { } { }
12981         assign $1\dec19_cr_in[2:0] 3'010
12982       attribute \src "libresoc.v:0.0-0.0"
12983       case 10'0010010110
12984         assign { } { }
12985         assign $1\dec19_cr_in[2:0] 3'000
12986       attribute \src "libresoc.v:0.0-0.0"
12987       case 10'0000010010
12988         assign { } { }
12989         assign $1\dec19_cr_in[2:0] 3'000
12990       attribute \src "libresoc.v:0.0-0.0"
12991       case 10'0100010010
12992         assign { } { }
12993         assign $1\dec19_cr_in[2:0] 3'000
12994       case
12995         assign $1\dec19_cr_in[2:0] 3'000
12996     end
12997     sync always
12998       update \dec19_cr_in $0\dec19_cr_in[2:0]
12999   end
13000   attribute \src "libresoc.v:8582.3-8633.6"
13001   process $proc$libresoc.v:8582$286
13002     assign { } { }
13003     assign { } { }
13004     assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0]
13005     attribute \src "libresoc.v:8583.5-8583.29"
13006     switch \initial
13007       attribute \src "libresoc.v:8583.9-8583.17"
13008       case 1'1
13009       case
13010     end
13011     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
13012     switch \opcode_switch
13013       attribute \src "libresoc.v:0.0-0.0"
13014       case 10'0000000000
13015         assign { } { }
13016         assign $1\dec19_cr_out[2:0] 3'010
13017       attribute \src "libresoc.v:0.0-0.0"
13018       case 10'0100000001
13019         assign { } { }
13020         assign $1\dec19_cr_out[2:0] 3'011
13021       attribute \src "libresoc.v:0.0-0.0"
13022       case 10'0010000001
13023         assign { } { }
13024         assign $1\dec19_cr_out[2:0] 3'011
13025       attribute \src "libresoc.v:0.0-0.0"
13026       case 10'0100100001
13027         assign { } { }
13028         assign $1\dec19_cr_out[2:0] 3'011
13029       attribute \src "libresoc.v:0.0-0.0"
13030       case 10'0011100001
13031         assign { } { }
13032         assign $1\dec19_cr_out[2:0] 3'011
13033       attribute \src "libresoc.v:0.0-0.0"
13034       case 10'0000100001
13035         assign { } { }
13036         assign $1\dec19_cr_out[2:0] 3'011
13037       attribute \src "libresoc.v:0.0-0.0"
13038       case 10'0111000001
13039         assign { } { }
13040         assign $1\dec19_cr_out[2:0] 3'011
13041       attribute \src "libresoc.v:0.0-0.0"
13042       case 10'0110100001
13043         assign { } { }
13044         assign $1\dec19_cr_out[2:0] 3'011
13045       attribute \src "libresoc.v:0.0-0.0"
13046       case 10'0011000001
13047         assign { } { }
13048         assign $1\dec19_cr_out[2:0] 3'011
13049       attribute \src "libresoc.v:0.0-0.0"
13050       case 10'1000010000
13051         assign { } { }
13052         assign $1\dec19_cr_out[2:0] 3'000
13053       attribute \src "libresoc.v:0.0-0.0"
13054       case 10'0000010000
13055         assign { } { }
13056         assign $1\dec19_cr_out[2:0] 3'000
13057       attribute \src "libresoc.v:0.0-0.0"
13058       case 10'1000110000
13059         assign { } { }
13060         assign $1\dec19_cr_out[2:0] 3'000
13061       attribute \src "libresoc.v:0.0-0.0"
13062       case 10'0010010110
13063         assign { } { }
13064         assign $1\dec19_cr_out[2:0] 3'000
13065       attribute \src "libresoc.v:0.0-0.0"
13066       case 10'0000010010
13067         assign { } { }
13068         assign $1\dec19_cr_out[2:0] 3'000
13069       attribute \src "libresoc.v:0.0-0.0"
13070       case 10'0100010010
13071         assign { } { }
13072         assign $1\dec19_cr_out[2:0] 3'000
13073       case
13074         assign $1\dec19_cr_out[2:0] 3'000
13075     end
13076     sync always
13077       update \dec19_cr_out $0\dec19_cr_out[2:0]
13078   end
13079   connect \opcode_switch \opcode_in [10:1]
13080 end
13081 attribute \src "libresoc.v:8639.1-10676.10"
13082 attribute \cells_not_processed 1
13083 attribute \nmigen.hierarchy "test_issuer.ti.dec2"
13084 attribute \generator "nMigen"
13085 module \dec2
13086   attribute \src "libresoc.v:10450.3-10607.6"
13087   wire width 8 $0\asmcode[7:0]
13088   attribute \src "libresoc.v:10450.3-10607.6"
13089   wire width 64 $0\cia[63:0]
13090   attribute \src "libresoc.v:10450.3-10607.6"
13091   wire width 3 $0\cr_in1[2:0]
13092   attribute \src "libresoc.v:10450.3-10607.6"
13093   wire $0\cr_in1_ok[0:0]
13094   attribute \src "libresoc.v:10450.3-10607.6"
13095   wire width 3 $0\cr_in2$1[2:0]$306
13096   attribute \src "libresoc.v:10450.3-10607.6"
13097   wire width 3 $0\cr_in2[2:0]
13098   attribute \src "libresoc.v:10450.3-10607.6"
13099   wire $0\cr_in2_ok$2[0:0]$307
13100   attribute \src "libresoc.v:10450.3-10607.6"
13101   wire $0\cr_in2_ok[0:0]
13102   attribute \src "libresoc.v:10450.3-10607.6"
13103   wire width 3 $0\cr_out[2:0]
13104   attribute \src "libresoc.v:10450.3-10607.6"
13105   wire $0\cr_out_ok[0:0]
13106   attribute \src "libresoc.v:10450.3-10607.6"
13107   wire width 8 $0\cr_rd[7:0]
13108   attribute \src "libresoc.v:10450.3-10607.6"
13109   wire $0\cr_rd_ok[0:0]
13110   attribute \src "libresoc.v:10450.3-10607.6"
13111   wire width 8 $0\cr_wr[7:0]
13112   attribute \src "libresoc.v:10450.3-10607.6"
13113   wire $0\cr_wr_ok[0:0]
13114   attribute \src "libresoc.v:10450.3-10607.6"
13115   wire width 5 $0\ea[4:0]
13116   attribute \src "libresoc.v:10450.3-10607.6"
13117   wire $0\ea_ok[0:0]
13118   attribute \src "libresoc.v:10450.3-10607.6"
13119   wire $0\exc_$signal$3[0:0]$309
13120   attribute \src "libresoc.v:10450.3-10607.6"
13121   wire $0\exc_$signal$4[0:0]$310
13122   attribute \src "libresoc.v:10450.3-10607.6"
13123   wire $0\exc_$signal$5[0:0]$311
13124   attribute \src "libresoc.v:10450.3-10607.6"
13125   wire $0\exc_$signal$6[0:0]$312
13126   attribute \src "libresoc.v:10450.3-10607.6"
13127   wire $0\exc_$signal$7[0:0]$313
13128   attribute \src "libresoc.v:10450.3-10607.6"
13129   wire $0\exc_$signal$8[0:0]$314
13130   attribute \src "libresoc.v:10450.3-10607.6"
13131   wire $0\exc_$signal$9[0:0]$315
13132   attribute \src "libresoc.v:10450.3-10607.6"
13133   wire $0\exc_$signal[0:0]$308
13134   attribute \src "libresoc.v:10450.3-10607.6"
13135   wire width 3 $0\fast1[2:0]
13136   attribute \src "libresoc.v:10450.3-10607.6"
13137   wire $0\fast1_ok[0:0]
13138   attribute \src "libresoc.v:10450.3-10607.6"
13139   wire width 3 $0\fast2[2:0]
13140   attribute \src "libresoc.v:10450.3-10607.6"
13141   wire $0\fast2_ok[0:0]
13142   attribute \src "libresoc.v:10450.3-10607.6"
13143   wire width 3 $0\fasto1[2:0]
13144   attribute \src "libresoc.v:10450.3-10607.6"
13145   wire $0\fasto1_ok[0:0]
13146   attribute \src "libresoc.v:10450.3-10607.6"
13147   wire width 3 $0\fasto2[2:0]
13148   attribute \src "libresoc.v:10450.3-10607.6"
13149   wire $0\fasto2_ok[0:0]
13150   attribute \src "libresoc.v:10450.3-10607.6"
13151   wire width 12 $0\fn_unit[11:0]
13152   attribute \src "libresoc.v:8640.7-8640.20"
13153   wire $0\initial[0:0]
13154   attribute \src "libresoc.v:10450.3-10607.6"
13155   wire width 2 $0\input_carry[1:0]
13156   attribute \src "libresoc.v:10450.3-10607.6"
13157   wire width 32 $0\insn[31:0]
13158   attribute \src "libresoc.v:10450.3-10607.6"
13159   wire width 7 $0\insn_type[6:0]
13160   attribute \src "libresoc.v:10450.3-10607.6"
13161   wire $0\is_32bit[0:0]
13162   attribute \src "libresoc.v:10430.3-10449.6"
13163   wire $0\is_priv_insn[0:0]
13164   attribute \src "libresoc.v:10450.3-10607.6"
13165   wire $0\lk[0:0]
13166   attribute \src "libresoc.v:10450.3-10607.6"
13167   wire width 64 $0\msr[63:0]
13168   attribute \src "libresoc.v:10450.3-10607.6"
13169   wire $0\oe[0:0]
13170   attribute \src "libresoc.v:10450.3-10607.6"
13171   wire $0\oe_ok[0:0]
13172   attribute \src "libresoc.v:10450.3-10607.6"
13173   wire $0\rc[0:0]
13174   attribute \src "libresoc.v:10450.3-10607.6"
13175   wire $0\rc_ok[0:0]
13176   attribute \src "libresoc.v:10450.3-10607.6"
13177   wire width 5 $0\reg1[4:0]
13178   attribute \src "libresoc.v:10450.3-10607.6"
13179   wire $0\reg1_ok[0:0]
13180   attribute \src "libresoc.v:10450.3-10607.6"
13181   wire width 5 $0\reg2[4:0]
13182   attribute \src "libresoc.v:10450.3-10607.6"
13183   wire $0\reg2_ok[0:0]
13184   attribute \src "libresoc.v:10450.3-10607.6"
13185   wire width 5 $0\reg3[4:0]
13186   attribute \src "libresoc.v:10450.3-10607.6"
13187   wire $0\reg3_ok[0:0]
13188   attribute \src "libresoc.v:10450.3-10607.6"
13189   wire width 5 $0\rego[4:0]
13190   attribute \src "libresoc.v:10450.3-10607.6"
13191   wire $0\rego_ok[0:0]
13192   attribute \src "libresoc.v:10450.3-10607.6"
13193   wire width 10 $0\spr1[9:0]
13194   attribute \src "libresoc.v:10450.3-10607.6"
13195   wire $0\spr1_ok[0:0]
13196   attribute \src "libresoc.v:10450.3-10607.6"
13197   wire width 10 $0\spro[9:0]
13198   attribute \src "libresoc.v:10450.3-10607.6"
13199   wire $0\spro_ok[0:0]
13200   attribute \src "libresoc.v:10384.3-10393.6"
13201   wire $0\tmp_tmp_lk[0:0]
13202   attribute \src "libresoc.v:10420.3-10429.6"
13203   wire width 13 $0\tmp_tmp_trapaddr[12:0]
13204   attribute \src "libresoc.v:10394.3-10409.6"
13205   wire width 3 $0\tmp_xer_in[2:0]
13206   attribute \src "libresoc.v:10410.3-10419.6"
13207   wire $0\tmp_xer_out[0:0]
13208   attribute \src "libresoc.v:10450.3-10607.6"
13209   wire width 13 $0\trapaddr[12:0]
13210   attribute \src "libresoc.v:10450.3-10607.6"
13211   wire width 8 $0\traptype[7:0]
13212   attribute \src "libresoc.v:10450.3-10607.6"
13213   wire width 3 $0\xer_in[2:0]
13214   attribute \src "libresoc.v:10450.3-10607.6"
13215   wire $0\xer_out[0:0]
13216   attribute \src "libresoc.v:10450.3-10607.6"
13217   wire width 8 $1\asmcode[7:0]
13218   attribute \src "libresoc.v:10450.3-10607.6"
13219   wire width 64 $1\cia[63:0]
13220   attribute \src "libresoc.v:10450.3-10607.6"
13221   wire width 3 $1\cr_in1[2:0]
13222   attribute \src "libresoc.v:10450.3-10607.6"
13223   wire $1\cr_in1_ok[0:0]
13224   attribute \src "libresoc.v:10450.3-10607.6"
13225   wire width 3 $1\cr_in2$1[2:0]$316
13226   attribute \src "libresoc.v:10450.3-10607.6"
13227   wire width 3 $1\cr_in2[2:0]
13228   attribute \src "libresoc.v:10450.3-10607.6"
13229   wire $1\cr_in2_ok$2[0:0]$317
13230   attribute \src "libresoc.v:10450.3-10607.6"
13231   wire $1\cr_in2_ok[0:0]
13232   attribute \src "libresoc.v:10450.3-10607.6"
13233   wire width 3 $1\cr_out[2:0]
13234   attribute \src "libresoc.v:10450.3-10607.6"
13235   wire $1\cr_out_ok[0:0]
13236   attribute \src "libresoc.v:10450.3-10607.6"
13237   wire width 8 $1\cr_rd[7:0]
13238   attribute \src "libresoc.v:10450.3-10607.6"
13239   wire $1\cr_rd_ok[0:0]
13240   attribute \src "libresoc.v:10450.3-10607.6"
13241   wire width 8 $1\cr_wr[7:0]
13242   attribute \src "libresoc.v:10450.3-10607.6"
13243   wire $1\cr_wr_ok[0:0]
13244   attribute \src "libresoc.v:10450.3-10607.6"
13245   wire width 5 $1\ea[4:0]
13246   attribute \src "libresoc.v:10450.3-10607.6"
13247   wire $1\ea_ok[0:0]
13248   attribute \src "libresoc.v:10450.3-10607.6"
13249   wire $1\exc_$signal$3[0:0]$319
13250   attribute \src "libresoc.v:10450.3-10607.6"
13251   wire $1\exc_$signal$4[0:0]$320
13252   attribute \src "libresoc.v:10450.3-10607.6"
13253   wire $1\exc_$signal$5[0:0]$321
13254   attribute \src "libresoc.v:10450.3-10607.6"
13255   wire $1\exc_$signal$6[0:0]$322
13256   attribute \src "libresoc.v:10450.3-10607.6"
13257   wire $1\exc_$signal$7[0:0]$323
13258   attribute \src "libresoc.v:10450.3-10607.6"
13259   wire $1\exc_$signal$8[0:0]$324
13260   attribute \src "libresoc.v:10450.3-10607.6"
13261   wire $1\exc_$signal$9[0:0]$325
13262   attribute \src "libresoc.v:10450.3-10607.6"
13263   wire $1\exc_$signal[0:0]$318
13264   attribute \src "libresoc.v:10450.3-10607.6"
13265   wire width 3 $1\fast1[2:0]
13266   attribute \src "libresoc.v:10450.3-10607.6"
13267   wire $1\fast1_ok[0:0]
13268   attribute \src "libresoc.v:10450.3-10607.6"
13269   wire width 3 $1\fast2[2:0]
13270   attribute \src "libresoc.v:10450.3-10607.6"
13271   wire $1\fast2_ok[0:0]
13272   attribute \src "libresoc.v:10450.3-10607.6"
13273   wire width 3 $1\fasto1[2:0]
13274   attribute \src "libresoc.v:10450.3-10607.6"
13275   wire $1\fasto1_ok[0:0]
13276   attribute \src "libresoc.v:10450.3-10607.6"
13277   wire width 3 $1\fasto2[2:0]
13278   attribute \src "libresoc.v:10450.3-10607.6"
13279   wire $1\fasto2_ok[0:0]
13280   attribute \src "libresoc.v:10450.3-10607.6"
13281   wire width 12 $1\fn_unit[11:0]
13282   attribute \src "libresoc.v:10450.3-10607.6"
13283   wire width 2 $1\input_carry[1:0]
13284   attribute \src "libresoc.v:10450.3-10607.6"
13285   wire width 32 $1\insn[31:0]
13286   attribute \src "libresoc.v:10450.3-10607.6"
13287   wire width 7 $1\insn_type[6:0]
13288   attribute \src "libresoc.v:10450.3-10607.6"
13289   wire $1\is_32bit[0:0]
13290   attribute \src "libresoc.v:10430.3-10449.6"
13291   wire $1\is_priv_insn[0:0]
13292   attribute \src "libresoc.v:10450.3-10607.6"
13293   wire $1\lk[0:0]
13294   attribute \src "libresoc.v:10450.3-10607.6"
13295   wire width 64 $1\msr[63:0]
13296   attribute \src "libresoc.v:10450.3-10607.6"
13297   wire $1\oe[0:0]
13298   attribute \src "libresoc.v:10450.3-10607.6"
13299   wire $1\oe_ok[0:0]
13300   attribute \src "libresoc.v:10450.3-10607.6"
13301   wire $1\rc[0:0]
13302   attribute \src "libresoc.v:10450.3-10607.6"
13303   wire $1\rc_ok[0:0]
13304   attribute \src "libresoc.v:10450.3-10607.6"
13305   wire width 5 $1\reg1[4:0]
13306   attribute \src "libresoc.v:10450.3-10607.6"
13307   wire $1\reg1_ok[0:0]
13308   attribute \src "libresoc.v:10450.3-10607.6"
13309   wire width 5 $1\reg2[4:0]
13310   attribute \src "libresoc.v:10450.3-10607.6"
13311   wire $1\reg2_ok[0:0]
13312   attribute \src "libresoc.v:10450.3-10607.6"
13313   wire width 5 $1\reg3[4:0]
13314   attribute \src "libresoc.v:10450.3-10607.6"
13315   wire $1\reg3_ok[0:0]
13316   attribute \src "libresoc.v:10450.3-10607.6"
13317   wire width 5 $1\rego[4:0]
13318   attribute \src "libresoc.v:10450.3-10607.6"
13319   wire $1\rego_ok[0:0]
13320   attribute \src "libresoc.v:10450.3-10607.6"
13321   wire width 10 $1\spr1[9:0]
13322   attribute \src "libresoc.v:10450.3-10607.6"
13323   wire $1\spr1_ok[0:0]
13324   attribute \src "libresoc.v:10450.3-10607.6"
13325   wire width 10 $1\spro[9:0]
13326   attribute \src "libresoc.v:10450.3-10607.6"
13327   wire $1\spro_ok[0:0]
13328   attribute \src "libresoc.v:10384.3-10393.6"
13329   wire $1\tmp_tmp_lk[0:0]
13330   attribute \src "libresoc.v:10420.3-10429.6"
13331   wire width 13 $1\tmp_tmp_trapaddr[12:0]
13332   attribute \src "libresoc.v:10394.3-10409.6"
13333   wire width 3 $1\tmp_xer_in[2:0]
13334   attribute \src "libresoc.v:10410.3-10419.6"
13335   wire $1\tmp_xer_out[0:0]
13336   attribute \src "libresoc.v:10450.3-10607.6"
13337   wire width 13 $1\trapaddr[12:0]
13338   attribute \src "libresoc.v:10450.3-10607.6"
13339   wire width 8 $1\traptype[7:0]
13340   attribute \src "libresoc.v:10450.3-10607.6"
13341   wire width 3 $1\xer_in[2:0]
13342   attribute \src "libresoc.v:10450.3-10607.6"
13343   wire $1\xer_out[0:0]
13344   attribute \src "libresoc.v:10450.3-10607.6"
13345   wire width 8 $2\asmcode[7:0]
13346   attribute \src "libresoc.v:10450.3-10607.6"
13347   wire width 64 $2\cia[63:0]
13348   attribute \src "libresoc.v:10450.3-10607.6"
13349   wire width 3 $2\cr_in1[2:0]
13350   attribute \src "libresoc.v:10450.3-10607.6"
13351   wire $2\cr_in1_ok[0:0]
13352   attribute \src "libresoc.v:10450.3-10607.6"
13353   wire width 3 $2\cr_in2$1[2:0]$326
13354   attribute \src "libresoc.v:10450.3-10607.6"
13355   wire width 3 $2\cr_in2[2:0]
13356   attribute \src "libresoc.v:10450.3-10607.6"
13357   wire $2\cr_in2_ok$2[0:0]$327
13358   attribute \src "libresoc.v:10450.3-10607.6"
13359   wire $2\cr_in2_ok[0:0]
13360   attribute \src "libresoc.v:10450.3-10607.6"
13361   wire width 3 $2\cr_out[2:0]
13362   attribute \src "libresoc.v:10450.3-10607.6"
13363   wire $2\cr_out_ok[0:0]
13364   attribute \src "libresoc.v:10450.3-10607.6"
13365   wire width 8 $2\cr_rd[7:0]
13366   attribute \src "libresoc.v:10450.3-10607.6"
13367   wire $2\cr_rd_ok[0:0]
13368   attribute \src "libresoc.v:10450.3-10607.6"
13369   wire width 8 $2\cr_wr[7:0]
13370   attribute \src "libresoc.v:10450.3-10607.6"
13371   wire $2\cr_wr_ok[0:0]
13372   attribute \src "libresoc.v:10450.3-10607.6"
13373   wire width 5 $2\ea[4:0]
13374   attribute \src "libresoc.v:10450.3-10607.6"
13375   wire $2\ea_ok[0:0]
13376   attribute \src "libresoc.v:10450.3-10607.6"
13377   wire $2\exc_$signal$3[0:0]$329
13378   attribute \src "libresoc.v:10450.3-10607.6"
13379   wire $2\exc_$signal$4[0:0]$330
13380   attribute \src "libresoc.v:10450.3-10607.6"
13381   wire $2\exc_$signal$5[0:0]$331
13382   attribute \src "libresoc.v:10450.3-10607.6"
13383   wire $2\exc_$signal$6[0:0]$332
13384   attribute \src "libresoc.v:10450.3-10607.6"
13385   wire $2\exc_$signal$7[0:0]$333
13386   attribute \src "libresoc.v:10450.3-10607.6"
13387   wire $2\exc_$signal$8[0:0]$334
13388   attribute \src "libresoc.v:10450.3-10607.6"
13389   wire $2\exc_$signal$9[0:0]$335
13390   attribute \src "libresoc.v:10450.3-10607.6"
13391   wire $2\exc_$signal[0:0]$328
13392   attribute \src "libresoc.v:10450.3-10607.6"
13393   wire width 3 $2\fast1[2:0]
13394   attribute \src "libresoc.v:10450.3-10607.6"
13395   wire $2\fast1_ok[0:0]
13396   attribute \src "libresoc.v:10450.3-10607.6"
13397   wire width 3 $2\fast2[2:0]
13398   attribute \src "libresoc.v:10450.3-10607.6"
13399   wire $2\fast2_ok[0:0]
13400   attribute \src "libresoc.v:10450.3-10607.6"
13401   wire width 3 $2\fasto1[2:0]
13402   attribute \src "libresoc.v:10450.3-10607.6"
13403   wire $2\fasto1_ok[0:0]
13404   attribute \src "libresoc.v:10450.3-10607.6"
13405   wire width 3 $2\fasto2[2:0]
13406   attribute \src "libresoc.v:10450.3-10607.6"
13407   wire $2\fasto2_ok[0:0]
13408   attribute \src "libresoc.v:10450.3-10607.6"
13409   wire width 12 $2\fn_unit[11:0]
13410   attribute \src "libresoc.v:10450.3-10607.6"
13411   wire width 2 $2\input_carry[1:0]
13412   attribute \src "libresoc.v:10450.3-10607.6"
13413   wire width 32 $2\insn[31:0]
13414   attribute \src "libresoc.v:10450.3-10607.6"
13415   wire width 7 $2\insn_type[6:0]
13416   attribute \src "libresoc.v:10450.3-10607.6"
13417   wire $2\is_32bit[0:0]
13418   attribute \src "libresoc.v:10430.3-10449.6"
13419   wire $2\is_priv_insn[0:0]
13420   attribute \src "libresoc.v:10450.3-10607.6"
13421   wire $2\lk[0:0]
13422   attribute \src "libresoc.v:10450.3-10607.6"
13423   wire width 64 $2\msr[63:0]
13424   attribute \src "libresoc.v:10450.3-10607.6"
13425   wire $2\oe[0:0]
13426   attribute \src "libresoc.v:10450.3-10607.6"
13427   wire $2\oe_ok[0:0]
13428   attribute \src "libresoc.v:10450.3-10607.6"
13429   wire $2\rc[0:0]
13430   attribute \src "libresoc.v:10450.3-10607.6"
13431   wire $2\rc_ok[0:0]
13432   attribute \src "libresoc.v:10450.3-10607.6"
13433   wire width 5 $2\reg1[4:0]
13434   attribute \src "libresoc.v:10450.3-10607.6"
13435   wire $2\reg1_ok[0:0]
13436   attribute \src "libresoc.v:10450.3-10607.6"
13437   wire width 5 $2\reg2[4:0]
13438   attribute \src "libresoc.v:10450.3-10607.6"
13439   wire $2\reg2_ok[0:0]
13440   attribute \src "libresoc.v:10450.3-10607.6"
13441   wire width 5 $2\reg3[4:0]
13442   attribute \src "libresoc.v:10450.3-10607.6"
13443   wire $2\reg3_ok[0:0]
13444   attribute \src "libresoc.v:10450.3-10607.6"
13445   wire width 5 $2\rego[4:0]
13446   attribute \src "libresoc.v:10450.3-10607.6"
13447   wire $2\rego_ok[0:0]
13448   attribute \src "libresoc.v:10450.3-10607.6"
13449   wire width 10 $2\spr1[9:0]
13450   attribute \src "libresoc.v:10450.3-10607.6"
13451   wire $2\spr1_ok[0:0]
13452   attribute \src "libresoc.v:10450.3-10607.6"
13453   wire width 10 $2\spro[9:0]
13454   attribute \src "libresoc.v:10450.3-10607.6"
13455   wire $2\spro_ok[0:0]
13456   attribute \src "libresoc.v:10394.3-10409.6"
13457   wire width 3 $2\tmp_xer_in[2:0]
13458   attribute \src "libresoc.v:10450.3-10607.6"
13459   wire width 13 $2\trapaddr[12:0]
13460   attribute \src "libresoc.v:10450.3-10607.6"
13461   wire width 8 $2\traptype[7:0]
13462   attribute \src "libresoc.v:10450.3-10607.6"
13463   wire width 3 $2\xer_in[2:0]
13464   attribute \src "libresoc.v:10450.3-10607.6"
13465   wire $2\xer_out[0:0]
13466   attribute \src "libresoc.v:10450.3-10607.6"
13467   wire width 8 $3\asmcode[7:0]
13468   attribute \src "libresoc.v:10450.3-10607.6"
13469   wire width 64 $3\cia[63:0]
13470   attribute \src "libresoc.v:10450.3-10607.6"
13471   wire width 3 $3\cr_in1[2:0]
13472   attribute \src "libresoc.v:10450.3-10607.6"
13473   wire $3\cr_in1_ok[0:0]
13474   attribute \src "libresoc.v:10450.3-10607.6"
13475   wire width 3 $3\cr_in2$1[2:0]$336
13476   attribute \src "libresoc.v:10450.3-10607.6"
13477   wire width 3 $3\cr_in2[2:0]
13478   attribute \src "libresoc.v:10450.3-10607.6"
13479   wire $3\cr_in2_ok$2[0:0]$337
13480   attribute \src "libresoc.v:10450.3-10607.6"
13481   wire $3\cr_in2_ok[0:0]
13482   attribute \src "libresoc.v:10450.3-10607.6"
13483   wire width 3 $3\cr_out[2:0]
13484   attribute \src "libresoc.v:10450.3-10607.6"
13485   wire $3\cr_out_ok[0:0]
13486   attribute \src "libresoc.v:10450.3-10607.6"
13487   wire width 8 $3\cr_rd[7:0]
13488   attribute \src "libresoc.v:10450.3-10607.6"
13489   wire $3\cr_rd_ok[0:0]
13490   attribute \src "libresoc.v:10450.3-10607.6"
13491   wire width 8 $3\cr_wr[7:0]
13492   attribute \src "libresoc.v:10450.3-10607.6"
13493   wire $3\cr_wr_ok[0:0]
13494   attribute \src "libresoc.v:10450.3-10607.6"
13495   wire width 5 $3\ea[4:0]
13496   attribute \src "libresoc.v:10450.3-10607.6"
13497   wire $3\ea_ok[0:0]
13498   attribute \src "libresoc.v:10450.3-10607.6"
13499   wire $3\exc_$signal$3[0:0]$339
13500   attribute \src "libresoc.v:10450.3-10607.6"
13501   wire $3\exc_$signal$4[0:0]$340
13502   attribute \src "libresoc.v:10450.3-10607.6"
13503   wire $3\exc_$signal$5[0:0]$341
13504   attribute \src "libresoc.v:10450.3-10607.6"
13505   wire $3\exc_$signal$6[0:0]$342
13506   attribute \src "libresoc.v:10450.3-10607.6"
13507   wire $3\exc_$signal$7[0:0]$343
13508   attribute \src "libresoc.v:10450.3-10607.6"
13509   wire $3\exc_$signal$8[0:0]$344
13510   attribute \src "libresoc.v:10450.3-10607.6"
13511   wire $3\exc_$signal$9[0:0]$345
13512   attribute \src "libresoc.v:10450.3-10607.6"
13513   wire $3\exc_$signal[0:0]$338
13514   attribute \src "libresoc.v:10450.3-10607.6"
13515   wire width 3 $3\fast1[2:0]
13516   attribute \src "libresoc.v:10450.3-10607.6"
13517   wire $3\fast1_ok[0:0]
13518   attribute \src "libresoc.v:10450.3-10607.6"
13519   wire width 3 $3\fast2[2:0]
13520   attribute \src "libresoc.v:10450.3-10607.6"
13521   wire $3\fast2_ok[0:0]
13522   attribute \src "libresoc.v:10450.3-10607.6"
13523   wire width 3 $3\fasto1[2:0]
13524   attribute \src "libresoc.v:10450.3-10607.6"
13525   wire $3\fasto1_ok[0:0]
13526   attribute \src "libresoc.v:10450.3-10607.6"
13527   wire width 3 $3\fasto2[2:0]
13528   attribute \src "libresoc.v:10450.3-10607.6"
13529   wire $3\fasto2_ok[0:0]
13530   attribute \src "libresoc.v:10450.3-10607.6"
13531   wire width 12 $3\fn_unit[11:0]
13532   attribute \src "libresoc.v:10450.3-10607.6"
13533   wire width 2 $3\input_carry[1:0]
13534   attribute \src "libresoc.v:10450.3-10607.6"
13535   wire width 32 $3\insn[31:0]
13536   attribute \src "libresoc.v:10450.3-10607.6"
13537   wire width 7 $3\insn_type[6:0]
13538   attribute \src "libresoc.v:10450.3-10607.6"
13539   wire $3\is_32bit[0:0]
13540   attribute \src "libresoc.v:10450.3-10607.6"
13541   wire $3\lk[0:0]
13542   attribute \src "libresoc.v:10450.3-10607.6"
13543   wire width 64 $3\msr[63:0]
13544   attribute \src "libresoc.v:10450.3-10607.6"
13545   wire $3\oe[0:0]
13546   attribute \src "libresoc.v:10450.3-10607.6"
13547   wire $3\oe_ok[0:0]
13548   attribute \src "libresoc.v:10450.3-10607.6"
13549   wire $3\rc[0:0]
13550   attribute \src "libresoc.v:10450.3-10607.6"
13551   wire $3\rc_ok[0:0]
13552   attribute \src "libresoc.v:10450.3-10607.6"
13553   wire width 5 $3\reg1[4:0]
13554   attribute \src "libresoc.v:10450.3-10607.6"
13555   wire $3\reg1_ok[0:0]
13556   attribute \src "libresoc.v:10450.3-10607.6"
13557   wire width 5 $3\reg2[4:0]
13558   attribute \src "libresoc.v:10450.3-10607.6"
13559   wire $3\reg2_ok[0:0]
13560   attribute \src "libresoc.v:10450.3-10607.6"
13561   wire width 5 $3\reg3[4:0]
13562   attribute \src "libresoc.v:10450.3-10607.6"
13563   wire $3\reg3_ok[0:0]
13564   attribute \src "libresoc.v:10450.3-10607.6"
13565   wire width 5 $3\rego[4:0]
13566   attribute \src "libresoc.v:10450.3-10607.6"
13567   wire $3\rego_ok[0:0]
13568   attribute \src "libresoc.v:10450.3-10607.6"
13569   wire width 10 $3\spr1[9:0]
13570   attribute \src "libresoc.v:10450.3-10607.6"
13571   wire $3\spr1_ok[0:0]
13572   attribute \src "libresoc.v:10450.3-10607.6"
13573   wire width 10 $3\spro[9:0]
13574   attribute \src "libresoc.v:10450.3-10607.6"
13575   wire $3\spro_ok[0:0]
13576   attribute \src "libresoc.v:10450.3-10607.6"
13577   wire width 13 $3\trapaddr[12:0]
13578   attribute \src "libresoc.v:10450.3-10607.6"
13579   wire width 8 $3\traptype[7:0]
13580   attribute \src "libresoc.v:10450.3-10607.6"
13581   wire width 3 $3\xer_in[2:0]
13582   attribute \src "libresoc.v:10450.3-10607.6"
13583   wire $3\xer_out[0:0]
13584   attribute \src "libresoc.v:10450.3-10607.6"
13585   wire width 8 $4\asmcode[7:0]
13586   attribute \src "libresoc.v:10450.3-10607.6"
13587   wire width 64 $4\cia[63:0]
13588   attribute \src "libresoc.v:10450.3-10607.6"
13589   wire width 3 $4\cr_in1[2:0]
13590   attribute \src "libresoc.v:10450.3-10607.6"
13591   wire $4\cr_in1_ok[0:0]
13592   attribute \src "libresoc.v:10450.3-10607.6"
13593   wire width 3 $4\cr_in2$1[2:0]$346
13594   attribute \src "libresoc.v:10450.3-10607.6"
13595   wire width 3 $4\cr_in2[2:0]
13596   attribute \src "libresoc.v:10450.3-10607.6"
13597   wire $4\cr_in2_ok$2[0:0]$347
13598   attribute \src "libresoc.v:10450.3-10607.6"
13599   wire $4\cr_in2_ok[0:0]
13600   attribute \src "libresoc.v:10450.3-10607.6"
13601   wire width 3 $4\cr_out[2:0]
13602   attribute \src "libresoc.v:10450.3-10607.6"
13603   wire $4\cr_out_ok[0:0]
13604   attribute \src "libresoc.v:10450.3-10607.6"
13605   wire width 8 $4\cr_rd[7:0]
13606   attribute \src "libresoc.v:10450.3-10607.6"
13607   wire $4\cr_rd_ok[0:0]
13608   attribute \src "libresoc.v:10450.3-10607.6"
13609   wire width 8 $4\cr_wr[7:0]
13610   attribute \src "libresoc.v:10450.3-10607.6"
13611   wire $4\cr_wr_ok[0:0]
13612   attribute \src "libresoc.v:10450.3-10607.6"
13613   wire width 5 $4\ea[4:0]
13614   attribute \src "libresoc.v:10450.3-10607.6"
13615   wire $4\ea_ok[0:0]
13616   attribute \src "libresoc.v:10450.3-10607.6"
13617   wire $4\exc_$signal$3[0:0]$349
13618   attribute \src "libresoc.v:10450.3-10607.6"
13619   wire $4\exc_$signal$4[0:0]$350
13620   attribute \src "libresoc.v:10450.3-10607.6"
13621   wire $4\exc_$signal$5[0:0]$351
13622   attribute \src "libresoc.v:10450.3-10607.6"
13623   wire $4\exc_$signal$6[0:0]$352
13624   attribute \src "libresoc.v:10450.3-10607.6"
13625   wire $4\exc_$signal$7[0:0]$353
13626   attribute \src "libresoc.v:10450.3-10607.6"
13627   wire $4\exc_$signal$8[0:0]$354
13628   attribute \src "libresoc.v:10450.3-10607.6"
13629   wire $4\exc_$signal$9[0:0]$355
13630   attribute \src "libresoc.v:10450.3-10607.6"
13631   wire $4\exc_$signal[0:0]$348
13632   attribute \src "libresoc.v:10450.3-10607.6"
13633   wire width 3 $4\fast1[2:0]
13634   attribute \src "libresoc.v:10450.3-10607.6"
13635   wire $4\fast1_ok[0:0]
13636   attribute \src "libresoc.v:10450.3-10607.6"
13637   wire width 3 $4\fast2[2:0]
13638   attribute \src "libresoc.v:10450.3-10607.6"
13639   wire $4\fast2_ok[0:0]
13640   attribute \src "libresoc.v:10450.3-10607.6"
13641   wire width 3 $4\fasto1[2:0]
13642   attribute \src "libresoc.v:10450.3-10607.6"
13643   wire $4\fasto1_ok[0:0]
13644   attribute \src "libresoc.v:10450.3-10607.6"
13645   wire width 3 $4\fasto2[2:0]
13646   attribute \src "libresoc.v:10450.3-10607.6"
13647   wire $4\fasto2_ok[0:0]
13648   attribute \src "libresoc.v:10450.3-10607.6"
13649   wire width 12 $4\fn_unit[11:0]
13650   attribute \src "libresoc.v:10450.3-10607.6"
13651   wire width 2 $4\input_carry[1:0]
13652   attribute \src "libresoc.v:10450.3-10607.6"
13653   wire width 32 $4\insn[31:0]
13654   attribute \src "libresoc.v:10450.3-10607.6"
13655   wire width 7 $4\insn_type[6:0]
13656   attribute \src "libresoc.v:10450.3-10607.6"
13657   wire $4\is_32bit[0:0]
13658   attribute \src "libresoc.v:10450.3-10607.6"
13659   wire $4\lk[0:0]
13660   attribute \src "libresoc.v:10450.3-10607.6"
13661   wire width 64 $4\msr[63:0]
13662   attribute \src "libresoc.v:10450.3-10607.6"
13663   wire $4\oe[0:0]
13664   attribute \src "libresoc.v:10450.3-10607.6"
13665   wire $4\oe_ok[0:0]
13666   attribute \src "libresoc.v:10450.3-10607.6"
13667   wire $4\rc[0:0]
13668   attribute \src "libresoc.v:10450.3-10607.6"
13669   wire $4\rc_ok[0:0]
13670   attribute \src "libresoc.v:10450.3-10607.6"
13671   wire width 5 $4\reg1[4:0]
13672   attribute \src "libresoc.v:10450.3-10607.6"
13673   wire $4\reg1_ok[0:0]
13674   attribute \src "libresoc.v:10450.3-10607.6"
13675   wire width 5 $4\reg2[4:0]
13676   attribute \src "libresoc.v:10450.3-10607.6"
13677   wire $4\reg2_ok[0:0]
13678   attribute \src "libresoc.v:10450.3-10607.6"
13679   wire width 5 $4\reg3[4:0]
13680   attribute \src "libresoc.v:10450.3-10607.6"
13681   wire $4\reg3_ok[0:0]
13682   attribute \src "libresoc.v:10450.3-10607.6"
13683   wire width 5 $4\rego[4:0]
13684   attribute \src "libresoc.v:10450.3-10607.6"
13685   wire $4\rego_ok[0:0]
13686   attribute \src "libresoc.v:10450.3-10607.6"
13687   wire width 10 $4\spr1[9:0]
13688   attribute \src "libresoc.v:10450.3-10607.6"
13689   wire $4\spr1_ok[0:0]
13690   attribute \src "libresoc.v:10450.3-10607.6"
13691   wire width 10 $4\spro[9:0]
13692   attribute \src "libresoc.v:10450.3-10607.6"
13693   wire $4\spro_ok[0:0]
13694   attribute \src "libresoc.v:10450.3-10607.6"
13695   wire width 13 $4\trapaddr[12:0]
13696   attribute \src "libresoc.v:10450.3-10607.6"
13697   wire width 8 $4\traptype[7:0]
13698   attribute \src "libresoc.v:10450.3-10607.6"
13699   wire width 3 $4\xer_in[2:0]
13700   attribute \src "libresoc.v:10450.3-10607.6"
13701   wire $4\xer_out[0:0]
13702   attribute \src "libresoc.v:10450.3-10607.6"
13703   wire width 3 $5\fast1[2:0]
13704   attribute \src "libresoc.v:10450.3-10607.6"
13705   wire $5\fast1_ok[0:0]
13706   attribute \src "libresoc.v:10450.3-10607.6"
13707   wire width 3 $5\fast2[2:0]
13708   attribute \src "libresoc.v:10450.3-10607.6"
13709   wire $5\fast2_ok[0:0]
13710   attribute \src "libresoc.v:10450.3-10607.6"
13711   wire width 3 $5\fasto1[2:0]
13712   attribute \src "libresoc.v:10450.3-10607.6"
13713   wire $5\fasto1_ok[0:0]
13714   attribute \src "libresoc.v:10450.3-10607.6"
13715   wire width 3 $5\fasto2[2:0]
13716   attribute \src "libresoc.v:10450.3-10607.6"
13717   wire $5\fasto2_ok[0:0]
13718   attribute \src "libresoc.v:10239.18-10239.120"
13719   wire $and$libresoc.v:10239$296_Y
13720   attribute \src "libresoc.v:10240.18-10240.123"
13721   wire $and$libresoc.v:10240$297_Y
13722   attribute \src "libresoc.v:10241.18-10241.124"
13723   wire $and$libresoc.v:10241$298_Y
13724   attribute \src "libresoc.v:10231.18-10231.116"
13725   wire $eq$libresoc.v:10231$288_Y
13726   attribute \src "libresoc.v:10232.18-10232.116"
13727   wire $eq$libresoc.v:10232$289_Y
13728   attribute \src "libresoc.v:10234.18-10234.116"
13729   wire $eq$libresoc.v:10234$291_Y
13730   attribute \src "libresoc.v:10235.18-10235.122"
13731   wire $eq$libresoc.v:10235$292_Y
13732   attribute \src "libresoc.v:10236.18-10236.122"
13733   wire $eq$libresoc.v:10236$293_Y
13734   attribute \src "libresoc.v:10237.18-10237.122"
13735   wire $eq$libresoc.v:10237$294_Y
13736   attribute \src "libresoc.v:10238.18-10238.122"
13737   wire $eq$libresoc.v:10238$295_Y
13738   attribute \src "libresoc.v:10242.18-10242.122"
13739   wire $eq$libresoc.v:10242$299_Y
13740   attribute \src "libresoc.v:10233.18-10233.110"
13741   wire $or$libresoc.v:10233$290_Y
13742   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960"
13743   wire \$28
13744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961"
13745   wire \$30
13746   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961"
13747   wire \$32
13748   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970"
13749   wire \$34
13750   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878"
13751   wire \$42
13752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880"
13753   wire \$44
13754   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882"
13755   wire \$46
13756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886"
13757   wire \$48
13758   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909"
13759   wire \$50
13760   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910"
13761   wire \$52
13762   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911"
13763   wire \$54
13764   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912"
13765   wire \$56
13766   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
13767   wire width 8 output 5 \asmcode
13768   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446"
13769   wire input 1 \bigendian
13770   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
13771   wire width 64 output 39 \cia
13772   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13773   wire width 3 output 30 \cr_in1
13774   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13775   wire output 31 \cr_in1_ok
13776   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13777   wire width 3 output 32 \cr_in2
13778   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13779   wire width 3 output 34 \cr_in2$1
13780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13781   wire output 33 \cr_in2_ok
13782   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13783   wire output 35 \cr_in2_ok$2
13784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13785   wire width 3 output 36 \cr_out
13786   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13787   wire output 37 \cr_out_ok
13788   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13789   wire width 8 output 59 \cr_rd
13790   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13791   wire output 60 \cr_rd_ok
13792   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13793   wire width 8 output 61 \cr_wr
13794   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13795   wire output 62 \cr_wr_ok
13796   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11"
13797   wire width 64 input 64 \cur_dec
13798   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10"
13799   wire input 65 \cur_eint
13800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
13801   wire width 64 input 3 \cur_msr
13802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
13803   wire width 64 input 2 \cur_pc
13804   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13805   wire \dec2_exc_$signal
13806   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13807   wire \dec2_exc_$signal$12
13808   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13809   wire \dec2_exc_$signal$13
13810   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13811   wire \dec2_exc_$signal$14
13812   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13813   wire \dec2_exc_$signal$15
13814   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13815   wire \dec2_exc_$signal$16
13816   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13817   wire \dec2_exc_$signal$17
13818   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
13819   wire \dec2_exc_$signal$18
13820   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13821   wire width 5 \dec_BA
13822   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13823   wire width 5 \dec_BB
13824   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13825   wire width 5 \dec_BC
13826   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13827   wire width 5 \dec_BI
13828   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13829   wire width 5 \dec_BO
13830   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13831   wire width 5 \dec_BT
13832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13833   wire width 8 \dec_FXM
13834   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13835   wire \dec_LK
13836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13837   wire \dec_OE
13838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13839   wire width 5 \dec_RA
13840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13841   wire width 5 \dec_RB
13842   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13843   wire width 5 \dec_RS
13844   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13845   wire width 5 \dec_RT
13846   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13847   wire \dec_Rc
13848   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
13849   wire width 10 \dec_SPR
13850   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
13851   wire width 5 \dec_XL_BT
13852   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
13853   wire width 10 \dec_XL_XO
13854   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
13855   wire width 3 \dec_X_BF
13856   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
13857   wire width 3 \dec_X_BFA
13858   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13859   wire width 3 \dec_a_fast_a
13860   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13861   wire \dec_a_fast_a_ok
13862   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13863   wire width 5 \dec_a_reg_a
13864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13865   wire \dec_a_reg_a_ok
13866   attribute \enum_base_type "In1Sel"
13867   attribute \enum_value_000 "NONE"
13868   attribute \enum_value_001 "RA"
13869   attribute \enum_value_010 "RA_OR_ZERO"
13870   attribute \enum_value_011 "SPR"
13871   attribute \enum_value_100 "RS"
13872   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88"
13873   wire width 3 \dec_a_sel_in
13874   attribute \enum_base_type "SPR"
13875   attribute \enum_value_0000000001 "XER"
13876   attribute \enum_value_0000000011 "DSCR"
13877   attribute \enum_value_0000001000 "LR"
13878   attribute \enum_value_0000001001 "CTR"
13879   attribute \enum_value_0000001101 "AMR"
13880   attribute \enum_value_0000010001 "DSCR_priv"
13881   attribute \enum_value_0000010010 "DSISR"
13882   attribute \enum_value_0000010011 "DAR"
13883   attribute \enum_value_0000010110 "DEC"
13884   attribute \enum_value_0000011010 "SRR0"
13885   attribute \enum_value_0000011011 "SRR1"
13886   attribute \enum_value_0000011100 "CFAR"
13887   attribute \enum_value_0000011101 "AMR_priv"
13888   attribute \enum_value_0000110000 "PIDR"
13889   attribute \enum_value_0000111101 "IAMR"
13890   attribute \enum_value_0010000000 "TFHAR"
13891   attribute \enum_value_0010000001 "TFIAR"
13892   attribute \enum_value_0010000010 "TEXASR"
13893   attribute \enum_value_0010000011 "TEXASRU"
13894   attribute \enum_value_0010001000 "CTRL"
13895   attribute \enum_value_0010010000 "TIDR"
13896   attribute \enum_value_0010011000 "CTRL_priv"
13897   attribute \enum_value_0010011001 "FSCR"
13898   attribute \enum_value_0010011101 "UAMOR"
13899   attribute \enum_value_0010011110 "GSR"
13900   attribute \enum_value_0010011111 "PSPB"
13901   attribute \enum_value_0010110000 "DPDES"
13902   attribute \enum_value_0010110100 "DAWR0"
13903   attribute \enum_value_0010111010 "RPR"
13904   attribute \enum_value_0010111011 "CIABR"
13905   attribute \enum_value_0010111100 "DAWRX0"
13906   attribute \enum_value_0010111110 "HFSCR"
13907   attribute \enum_value_0100000000 "VRSAVE"
13908   attribute \enum_value_0100000011 "SPRG3"
13909   attribute \enum_value_0100001100 "TB"
13910   attribute \enum_value_0100001101 "TBU"
13911   attribute \enum_value_0100010000 "SPRG0_priv"
13912   attribute \enum_value_0100010001 "SPRG1_priv"
13913   attribute \enum_value_0100010010 "SPRG2_priv"
13914   attribute \enum_value_0100010011 "SPRG3_priv"
13915   attribute \enum_value_0100011011 "CIR"
13916   attribute \enum_value_0100011100 "TBL"
13917   attribute \enum_value_0100011101 "TBU_hypv"
13918   attribute \enum_value_0100011110 "TBU40"
13919   attribute \enum_value_0100011111 "PVR"
13920   attribute \enum_value_0100110000 "HSPRG0"
13921   attribute \enum_value_0100110001 "HSPRG1"
13922   attribute \enum_value_0100110010 "HDSISR"
13923   attribute \enum_value_0100110011 "HDAR"
13924   attribute \enum_value_0100110100 "SPURR"
13925   attribute \enum_value_0100110101 "PURR"
13926   attribute \enum_value_0100110110 "HDEC"
13927   attribute \enum_value_0100111001 "HRMOR"
13928   attribute \enum_value_0100111010 "HSRR0"
13929   attribute \enum_value_0100111011 "HSRR1"
13930   attribute \enum_value_0100111110 "LPCR"
13931   attribute \enum_value_0100111111 "LPIDR"
13932   attribute \enum_value_0101010000 "HMER"
13933   attribute \enum_value_0101010001 "HMEER"
13934   attribute \enum_value_0101010010 "PCR"
13935   attribute \enum_value_0101010011 "HEIR"
13936   attribute \enum_value_0101011101 "AMOR"
13937   attribute \enum_value_0110111110 "TIR"
13938   attribute \enum_value_0111010000 "PTCR"
13939   attribute \enum_value_1100000000 "SIER"
13940   attribute \enum_value_1100000001 "MMCR2"
13941   attribute \enum_value_1100000010 "MMCRA"
13942   attribute \enum_value_1100000011 "PMC1"
13943   attribute \enum_value_1100000100 "PMC2"
13944   attribute \enum_value_1100000101 "PMC3"
13945   attribute \enum_value_1100000110 "PMC4"
13946   attribute \enum_value_1100000111 "PMC5"
13947   attribute \enum_value_1100001000 "PMC6"
13948   attribute \enum_value_1100001011 "MMCR0"
13949   attribute \enum_value_1100001100 "SIAR"
13950   attribute \enum_value_1100001101 "SDAR"
13951   attribute \enum_value_1100001110 "MMCR1"
13952   attribute \enum_value_1100010000 "SIER_priv"
13953   attribute \enum_value_1100010001 "MMCR2_priv"
13954   attribute \enum_value_1100010010 "MMCRA_priv"
13955   attribute \enum_value_1100010011 "PMC1_priv"
13956   attribute \enum_value_1100010100 "PMC2_priv"
13957   attribute \enum_value_1100010101 "PMC3_priv"
13958   attribute \enum_value_1100010110 "PMC4_priv"
13959   attribute \enum_value_1100010111 "PMC5_priv"
13960   attribute \enum_value_1100011000 "PMC6_priv"
13961   attribute \enum_value_1100011011 "MMCR0_priv"
13962   attribute \enum_value_1100011100 "SIAR_priv"
13963   attribute \enum_value_1100011101 "SDAR_priv"
13964   attribute \enum_value_1100011110 "MMCR1_priv"
13965   attribute \enum_value_1100100000 "BESCRS"
13966   attribute \enum_value_1100100001 "BESCRSU"
13967   attribute \enum_value_1100100010 "BESCRR"
13968   attribute \enum_value_1100100011 "BESCRRU"
13969   attribute \enum_value_1100100100 "EBBHR"
13970   attribute \enum_value_1100100101 "EBBRR"
13971   attribute \enum_value_1100100110 "BESCR"
13972   attribute \enum_value_1100101000 "reserved808"
13973   attribute \enum_value_1100101001 "reserved809"
13974   attribute \enum_value_1100101010 "reserved810"
13975   attribute \enum_value_1100101011 "reserved811"
13976   attribute \enum_value_1100101111 "TAR"
13977   attribute \enum_value_1100110000 "ASDR"
13978   attribute \enum_value_1100110111 "PSSCR"
13979   attribute \enum_value_1101010000 "IC"
13980   attribute \enum_value_1101010001 "VTB"
13981   attribute \enum_value_1101010111 "PSSCR_hypv"
13982   attribute \enum_value_1110000000 "PPR"
13983   attribute \enum_value_1110000010 "PPR32"
13984   attribute \enum_value_1111111111 "PIR"
13985   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13986   wire width 10 \dec_a_spr_a
13987   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13988   wire \dec_a_spr_a_ok
13989   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
13990   wire width 8 \dec_asmcode
13991   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13992   wire width 3 \dec_b_fast_b
13993   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13994   wire \dec_b_fast_b_ok
13995   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13996   wire width 5 \dec_b_reg_b
13997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
13998   wire \dec_b_reg_b_ok
13999   attribute \enum_base_type "In2Sel"
14000   attribute \enum_value_0000 "NONE"
14001   attribute \enum_value_0001 "RB"
14002   attribute \enum_value_0010 "CONST_UI"
14003   attribute \enum_value_0011 "CONST_SI"
14004   attribute \enum_value_0100 "CONST_UI_HI"
14005   attribute \enum_value_0101 "CONST_SI_HI"
14006   attribute \enum_value_0110 "CONST_LI"
14007   attribute \enum_value_0111 "CONST_BD"
14008   attribute \enum_value_1000 "CONST_DS"
14009   attribute \enum_value_1001 "CONST_M1"
14010   attribute \enum_value_1010 "CONST_SH"
14011   attribute \enum_value_1011 "CONST_SH32"
14012   attribute \enum_value_1100 "SPR"
14013   attribute \enum_value_1101 "RS"
14014   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
14015   wire width 4 \dec_b_sel_in
14016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14017   wire width 5 \dec_c_reg_c
14018   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14019   wire \dec_c_reg_c_ok
14020   attribute \enum_base_type "In3Sel"
14021   attribute \enum_value_00 "NONE"
14022   attribute \enum_value_01 "RS"
14023   attribute \enum_value_10 "RB"
14024   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282"
14025   wire width 2 \dec_c_sel_in
14026   attribute \enum_base_type "CRInSel"
14027   attribute \enum_value_000 "NONE"
14028   attribute \enum_value_001 "CR0"
14029   attribute \enum_value_010 "BI"
14030   attribute \enum_value_011 "BFA"
14031   attribute \enum_value_100 "BA_BB"
14032   attribute \enum_value_101 "BC"
14033   attribute \enum_value_110 "WHOLE_REG"
14034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14035   wire width 3 \dec_cr_in
14036   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14037   wire width 3 \dec_cr_in_cr_bitfield
14038   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14039   wire width 3 \dec_cr_in_cr_bitfield_b
14040   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14041   wire \dec_cr_in_cr_bitfield_b_ok
14042   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14043   wire width 3 \dec_cr_in_cr_bitfield_o
14044   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14045   wire \dec_cr_in_cr_bitfield_o_ok
14046   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14047   wire \dec_cr_in_cr_bitfield_ok
14048   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14049   wire width 8 \dec_cr_in_cr_fxm
14050   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14051   wire \dec_cr_in_cr_fxm_ok
14052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
14053   wire width 32 \dec_cr_in_insn_in
14054   attribute \enum_base_type "CRInSel"
14055   attribute \enum_value_000 "NONE"
14056   attribute \enum_value_001 "CR0"
14057   attribute \enum_value_010 "BI"
14058   attribute \enum_value_011 "BFA"
14059   attribute \enum_value_100 "BA_BB"
14060   attribute \enum_value_101 "BC"
14061   attribute \enum_value_110 "WHOLE_REG"
14062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488"
14063   wire width 3 \dec_cr_in_sel_in
14064   attribute \enum_base_type "CROutSel"
14065   attribute \enum_value_000 "NONE"
14066   attribute \enum_value_001 "CR0"
14067   attribute \enum_value_010 "BF"
14068   attribute \enum_value_011 "BT"
14069   attribute \enum_value_100 "WHOLE_REG"
14070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14071   wire width 3 \dec_cr_out
14072   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14073   wire width 3 \dec_cr_out_cr_bitfield
14074   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14075   wire \dec_cr_out_cr_bitfield_ok
14076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14077   wire width 8 \dec_cr_out_cr_fxm
14078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14079   wire \dec_cr_out_cr_fxm_ok
14080   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554"
14081   wire width 32 \dec_cr_out_insn_in
14082   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552"
14083   wire \dec_cr_out_rc_in
14084   attribute \enum_base_type "CROutSel"
14085   attribute \enum_value_000 "NONE"
14086   attribute \enum_value_001 "CR0"
14087   attribute \enum_value_010 "BF"
14088   attribute \enum_value_011 "BT"
14089   attribute \enum_value_100 "WHOLE_REG"
14090   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553"
14091   wire width 3 \dec_cr_out_sel_in
14092   attribute \enum_base_type "CryIn"
14093   attribute \enum_value_00 "ZERO"
14094   attribute \enum_value_01 "ONE"
14095   attribute \enum_value_10 "CA"
14096   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14097   wire width 2 \dec_cry_in
14098   attribute \enum_base_type "Function"
14099   attribute \enum_value_000000000000 "NONE"
14100   attribute \enum_value_000000000010 "ALU"
14101   attribute \enum_value_000000000100 "LDST"
14102   attribute \enum_value_000000001000 "SHIFT_ROT"
14103   attribute \enum_value_000000010000 "LOGICAL"
14104   attribute \enum_value_000000100000 "BRANCH"
14105   attribute \enum_value_000001000000 "CR"
14106   attribute \enum_value_000010000000 "TRAP"
14107   attribute \enum_value_000100000000 "MUL"
14108   attribute \enum_value_001000000000 "DIV"
14109   attribute \enum_value_010000000000 "SPR"
14110   attribute \enum_value_100000000000 "MMU"
14111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14112   wire width 12 \dec_function_unit
14113   attribute \enum_base_type "In1Sel"
14114   attribute \enum_value_000 "NONE"
14115   attribute \enum_value_001 "RA"
14116   attribute \enum_value_010 "RA_OR_ZERO"
14117   attribute \enum_value_011 "SPR"
14118   attribute \enum_value_100 "RS"
14119   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14120   wire width 3 \dec_in1_sel
14121   attribute \enum_base_type "In2Sel"
14122   attribute \enum_value_0000 "NONE"
14123   attribute \enum_value_0001 "RB"
14124   attribute \enum_value_0010 "CONST_UI"
14125   attribute \enum_value_0011 "CONST_SI"
14126   attribute \enum_value_0100 "CONST_UI_HI"
14127   attribute \enum_value_0101 "CONST_SI_HI"
14128   attribute \enum_value_0110 "CONST_LI"
14129   attribute \enum_value_0111 "CONST_BD"
14130   attribute \enum_value_1000 "CONST_DS"
14131   attribute \enum_value_1001 "CONST_M1"
14132   attribute \enum_value_1010 "CONST_SH"
14133   attribute \enum_value_1011 "CONST_SH32"
14134   attribute \enum_value_1100 "SPR"
14135   attribute \enum_value_1101 "RS"
14136   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14137   wire width 4 \dec_in2_sel
14138   attribute \enum_base_type "In3Sel"
14139   attribute \enum_value_00 "NONE"
14140   attribute \enum_value_01 "RS"
14141   attribute \enum_value_10 "RB"
14142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14143   wire width 2 \dec_in3_sel
14144   attribute \enum_base_type "MicrOp"
14145   attribute \enum_value_0000000 "OP_ILLEGAL"
14146   attribute \enum_value_0000001 "OP_NOP"
14147   attribute \enum_value_0000010 "OP_ADD"
14148   attribute \enum_value_0000011 "OP_ADDPCIS"
14149   attribute \enum_value_0000100 "OP_AND"
14150   attribute \enum_value_0000101 "OP_ATTN"
14151   attribute \enum_value_0000110 "OP_B"
14152   attribute \enum_value_0000111 "OP_BC"
14153   attribute \enum_value_0001000 "OP_BCREG"
14154   attribute \enum_value_0001001 "OP_BPERM"
14155   attribute \enum_value_0001010 "OP_CMP"
14156   attribute \enum_value_0001011 "OP_CMPB"
14157   attribute \enum_value_0001100 "OP_CMPEQB"
14158   attribute \enum_value_0001101 "OP_CMPRB"
14159   attribute \enum_value_0001110 "OP_CNTZ"
14160   attribute \enum_value_0001111 "OP_CRAND"
14161   attribute \enum_value_0010000 "OP_CRANDC"
14162   attribute \enum_value_0010001 "OP_CREQV"
14163   attribute \enum_value_0010010 "OP_CRNAND"
14164   attribute \enum_value_0010011 "OP_CRNOR"
14165   attribute \enum_value_0010100 "OP_CROR"
14166   attribute \enum_value_0010101 "OP_CRORC"
14167   attribute \enum_value_0010110 "OP_CRXOR"
14168   attribute \enum_value_0010111 "OP_DARN"
14169   attribute \enum_value_0011000 "OP_DCBF"
14170   attribute \enum_value_0011001 "OP_DCBST"
14171   attribute \enum_value_0011010 "OP_DCBT"
14172   attribute \enum_value_0011011 "OP_DCBTST"
14173   attribute \enum_value_0011100 "OP_DCBZ"
14174   attribute \enum_value_0011101 "OP_DIV"
14175   attribute \enum_value_0011110 "OP_DIVE"
14176   attribute \enum_value_0011111 "OP_EXTS"
14177   attribute \enum_value_0100000 "OP_EXTSWSLI"
14178   attribute \enum_value_0100001 "OP_ICBI"
14179   attribute \enum_value_0100010 "OP_ICBT"
14180   attribute \enum_value_0100011 "OP_ISEL"
14181   attribute \enum_value_0100100 "OP_ISYNC"
14182   attribute \enum_value_0100101 "OP_LOAD"
14183   attribute \enum_value_0100110 "OP_STORE"
14184   attribute \enum_value_0100111 "OP_MADDHD"
14185   attribute \enum_value_0101000 "OP_MADDHDU"
14186   attribute \enum_value_0101001 "OP_MADDLD"
14187   attribute \enum_value_0101010 "OP_MCRF"
14188   attribute \enum_value_0101011 "OP_MCRXR"
14189   attribute \enum_value_0101100 "OP_MCRXRX"
14190   attribute \enum_value_0101101 "OP_MFCR"
14191   attribute \enum_value_0101110 "OP_MFSPR"
14192   attribute \enum_value_0101111 "OP_MOD"
14193   attribute \enum_value_0110000 "OP_MTCRF"
14194   attribute \enum_value_0110001 "OP_MTSPR"
14195   attribute \enum_value_0110010 "OP_MUL_L64"
14196   attribute \enum_value_0110011 "OP_MUL_H64"
14197   attribute \enum_value_0110100 "OP_MUL_H32"
14198   attribute \enum_value_0110101 "OP_OR"
14199   attribute \enum_value_0110110 "OP_POPCNT"
14200   attribute \enum_value_0110111 "OP_PRTY"
14201   attribute \enum_value_0111000 "OP_RLC"
14202   attribute \enum_value_0111001 "OP_RLCL"
14203   attribute \enum_value_0111010 "OP_RLCR"
14204   attribute \enum_value_0111011 "OP_SETB"
14205   attribute \enum_value_0111100 "OP_SHL"
14206   attribute \enum_value_0111101 "OP_SHR"
14207   attribute \enum_value_0111110 "OP_SYNC"
14208   attribute \enum_value_0111111 "OP_TRAP"
14209   attribute \enum_value_1000011 "OP_XOR"
14210   attribute \enum_value_1000100 "OP_SIM_CONFIG"
14211   attribute \enum_value_1000101 "OP_CROP"
14212   attribute \enum_value_1000110 "OP_RFID"
14213   attribute \enum_value_1000111 "OP_MFMSR"
14214   attribute \enum_value_1001000 "OP_MTMSRD"
14215   attribute \enum_value_1001001 "OP_SC"
14216   attribute \enum_value_1001010 "OP_MTMSR"
14217   attribute \enum_value_1001011 "OP_TLBIE"
14218   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14219   wire width 7 \dec_internal_op
14220   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:904"
14221   wire \dec_irq_ok
14222   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
14223   wire \dec_is_32b
14224   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
14225   wire \dec_lk
14226   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14227   wire width 3 \dec_o2_fast_o
14228   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14229   wire \dec_o2_fast_o_ok
14230   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366"
14231   wire \dec_o2_lk
14232   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14233   wire width 5 \dec_o2_reg_o
14234   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14235   wire \dec_o2_reg_o_ok
14236   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14237   wire width 3 \dec_o_fast_o
14238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14239   wire \dec_o_fast_o_ok
14240   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14241   wire width 5 \dec_o_reg_o
14242   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14243   wire \dec_o_reg_o_ok
14244   attribute \enum_base_type "OutSel"
14245   attribute \enum_value_00 "NONE"
14246   attribute \enum_value_01 "RT"
14247   attribute \enum_value_10 "RA"
14248   attribute \enum_value_11 "SPR"
14249   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
14250   wire width 2 \dec_o_sel_in
14251   attribute \enum_base_type "SPR"
14252   attribute \enum_value_0000000001 "XER"
14253   attribute \enum_value_0000000011 "DSCR"
14254   attribute \enum_value_0000001000 "LR"
14255   attribute \enum_value_0000001001 "CTR"
14256   attribute \enum_value_0000001101 "AMR"
14257   attribute \enum_value_0000010001 "DSCR_priv"
14258   attribute \enum_value_0000010010 "DSISR"
14259   attribute \enum_value_0000010011 "DAR"
14260   attribute \enum_value_0000010110 "DEC"
14261   attribute \enum_value_0000011010 "SRR0"
14262   attribute \enum_value_0000011011 "SRR1"
14263   attribute \enum_value_0000011100 "CFAR"
14264   attribute \enum_value_0000011101 "AMR_priv"
14265   attribute \enum_value_0000110000 "PIDR"
14266   attribute \enum_value_0000111101 "IAMR"
14267   attribute \enum_value_0010000000 "TFHAR"
14268   attribute \enum_value_0010000001 "TFIAR"
14269   attribute \enum_value_0010000010 "TEXASR"
14270   attribute \enum_value_0010000011 "TEXASRU"
14271   attribute \enum_value_0010001000 "CTRL"
14272   attribute \enum_value_0010010000 "TIDR"
14273   attribute \enum_value_0010011000 "CTRL_priv"
14274   attribute \enum_value_0010011001 "FSCR"
14275   attribute \enum_value_0010011101 "UAMOR"
14276   attribute \enum_value_0010011110 "GSR"
14277   attribute \enum_value_0010011111 "PSPB"
14278   attribute \enum_value_0010110000 "DPDES"
14279   attribute \enum_value_0010110100 "DAWR0"
14280   attribute \enum_value_0010111010 "RPR"
14281   attribute \enum_value_0010111011 "CIABR"
14282   attribute \enum_value_0010111100 "DAWRX0"
14283   attribute \enum_value_0010111110 "HFSCR"
14284   attribute \enum_value_0100000000 "VRSAVE"
14285   attribute \enum_value_0100000011 "SPRG3"
14286   attribute \enum_value_0100001100 "TB"
14287   attribute \enum_value_0100001101 "TBU"
14288   attribute \enum_value_0100010000 "SPRG0_priv"
14289   attribute \enum_value_0100010001 "SPRG1_priv"
14290   attribute \enum_value_0100010010 "SPRG2_priv"
14291   attribute \enum_value_0100010011 "SPRG3_priv"
14292   attribute \enum_value_0100011011 "CIR"
14293   attribute \enum_value_0100011100 "TBL"
14294   attribute \enum_value_0100011101 "TBU_hypv"
14295   attribute \enum_value_0100011110 "TBU40"
14296   attribute \enum_value_0100011111 "PVR"
14297   attribute \enum_value_0100110000 "HSPRG0"
14298   attribute \enum_value_0100110001 "HSPRG1"
14299   attribute \enum_value_0100110010 "HDSISR"
14300   attribute \enum_value_0100110011 "HDAR"
14301   attribute \enum_value_0100110100 "SPURR"
14302   attribute \enum_value_0100110101 "PURR"
14303   attribute \enum_value_0100110110 "HDEC"
14304   attribute \enum_value_0100111001 "HRMOR"
14305   attribute \enum_value_0100111010 "HSRR0"
14306   attribute \enum_value_0100111011 "HSRR1"
14307   attribute \enum_value_0100111110 "LPCR"
14308   attribute \enum_value_0100111111 "LPIDR"
14309   attribute \enum_value_0101010000 "HMER"
14310   attribute \enum_value_0101010001 "HMEER"
14311   attribute \enum_value_0101010010 "PCR"
14312   attribute \enum_value_0101010011 "HEIR"
14313   attribute \enum_value_0101011101 "AMOR"
14314   attribute \enum_value_0110111110 "TIR"
14315   attribute \enum_value_0111010000 "PTCR"
14316   attribute \enum_value_1100000000 "SIER"
14317   attribute \enum_value_1100000001 "MMCR2"
14318   attribute \enum_value_1100000010 "MMCRA"
14319   attribute \enum_value_1100000011 "PMC1"
14320   attribute \enum_value_1100000100 "PMC2"
14321   attribute \enum_value_1100000101 "PMC3"
14322   attribute \enum_value_1100000110 "PMC4"
14323   attribute \enum_value_1100000111 "PMC5"
14324   attribute \enum_value_1100001000 "PMC6"
14325   attribute \enum_value_1100001011 "MMCR0"
14326   attribute \enum_value_1100001100 "SIAR"
14327   attribute \enum_value_1100001101 "SDAR"
14328   attribute \enum_value_1100001110 "MMCR1"
14329   attribute \enum_value_1100010000 "SIER_priv"
14330   attribute \enum_value_1100010001 "MMCR2_priv"
14331   attribute \enum_value_1100010010 "MMCRA_priv"
14332   attribute \enum_value_1100010011 "PMC1_priv"
14333   attribute \enum_value_1100010100 "PMC2_priv"
14334   attribute \enum_value_1100010101 "PMC3_priv"
14335   attribute \enum_value_1100010110 "PMC4_priv"
14336   attribute \enum_value_1100010111 "PMC5_priv"
14337   attribute \enum_value_1100011000 "PMC6_priv"
14338   attribute \enum_value_1100011011 "MMCR0_priv"
14339   attribute \enum_value_1100011100 "SIAR_priv"
14340   attribute \enum_value_1100011101 "SDAR_priv"
14341   attribute \enum_value_1100011110 "MMCR1_priv"
14342   attribute \enum_value_1100100000 "BESCRS"
14343   attribute \enum_value_1100100001 "BESCRSU"
14344   attribute \enum_value_1100100010 "BESCRR"
14345   attribute \enum_value_1100100011 "BESCRRU"
14346   attribute \enum_value_1100100100 "EBBHR"
14347   attribute \enum_value_1100100101 "EBBRR"
14348   attribute \enum_value_1100100110 "BESCR"
14349   attribute \enum_value_1100101000 "reserved808"
14350   attribute \enum_value_1100101001 "reserved809"
14351   attribute \enum_value_1100101010 "reserved810"
14352   attribute \enum_value_1100101011 "reserved811"
14353   attribute \enum_value_1100101111 "TAR"
14354   attribute \enum_value_1100110000 "ASDR"
14355   attribute \enum_value_1100110111 "PSSCR"
14356   attribute \enum_value_1101010000 "IC"
14357   attribute \enum_value_1101010001 "VTB"
14358   attribute \enum_value_1101010111 "PSSCR_hypv"
14359   attribute \enum_value_1110000000 "PPR"
14360   attribute \enum_value_1110000010 "PPR32"
14361   attribute \enum_value_1111111111 "PIR"
14362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14363   wire width 10 \dec_o_spr_o
14364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14365   wire \dec_o_spr_o_ok
14366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14367   wire \dec_oe_oe
14368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14369   wire \dec_oe_oe_ok
14370   attribute \enum_base_type "RC"
14371   attribute \enum_value_00 "NONE"
14372   attribute \enum_value_01 "ONE"
14373   attribute \enum_value_10 "RC"
14374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445"
14375   wire width 2 \dec_oe_sel_in
14376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
14377   wire width 32 \dec_opcode_in
14378   attribute \enum_base_type "OutSel"
14379   attribute \enum_value_00 "NONE"
14380   attribute \enum_value_01 "RT"
14381   attribute \enum_value_10 "RA"
14382   attribute \enum_value_11 "SPR"
14383   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14384   wire width 2 \dec_out_sel
14385   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14386   wire \dec_rc_rc
14387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14388   wire \dec_rc_rc_ok
14389   attribute \enum_base_type "RC"
14390   attribute \enum_value_00 "NONE"
14391   attribute \enum_value_01 "ONE"
14392   attribute \enum_value_10 "RC"
14393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14394   wire width 2 \dec_rc_sel
14395   attribute \enum_base_type "RC"
14396   attribute \enum_value_00 "NONE"
14397   attribute \enum_value_01 "ONE"
14398   attribute \enum_value_10 "RC"
14399   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408"
14400   wire width 2 \dec_rc_sel_in
14401   attribute \enum_base_type "LDSTMode"
14402   attribute \enum_value_00 "NONE"
14403   attribute \enum_value_01 "update"
14404   attribute \enum_value_10 "cix"
14405   attribute \enum_value_11 "cx"
14406   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
14407   wire width 2 \dec_upd
14408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14409   wire width 5 output 8 \ea
14410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14411   wire output 9 \ea_ok
14412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14413   wire output 50 \exc_$signal
14414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14415   wire output 51 \exc_$signal$3
14416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14417   wire output 52 \exc_$signal$4
14418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14419   wire output 53 \exc_$signal$5
14420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14421   wire output 54 \exc_$signal$6
14422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14423   wire output 55 \exc_$signal$7
14424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14425   wire output 56 \exc_$signal$8
14426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
14427   wire output 57 \exc_$signal$9
14428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903"
14429   wire \ext_irq_ok
14430   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14431   wire width 3 output 22 \fast1
14432   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14433   wire output 23 \fast1_ok
14434   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14435   wire width 3 output 24 \fast2
14436   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14437   wire output 25 \fast2_ok
14438   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14439   wire width 3 output 26 \fasto1
14440   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14441   wire output 27 \fasto1_ok
14442   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14443   wire width 3 output 28 \fasto2
14444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14445   wire output 29 \fasto2_ok
14446   attribute \enum_base_type "Function"
14447   attribute \enum_value_000000000000 "NONE"
14448   attribute \enum_value_000000000010 "ALU"
14449   attribute \enum_value_000000000100 "LDST"
14450   attribute \enum_value_000000001000 "SHIFT_ROT"
14451   attribute \enum_value_000000010000 "LOGICAL"
14452   attribute \enum_value_000000100000 "BRANCH"
14453   attribute \enum_value_000001000000 "CR"
14454   attribute \enum_value_000010000000 "TRAP"
14455   attribute \enum_value_000100000000 "MUL"
14456   attribute \enum_value_001000000000 "DIV"
14457   attribute \enum_value_010000000000 "SPR"
14458   attribute \enum_value_100000000000 "MMU"
14459   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
14460   wire width 12 output 42 \fn_unit
14461   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906"
14462   wire \illeg_ok
14463   attribute \src "libresoc.v:8640.7-8640.15"
14464   wire \initial
14465   attribute \enum_base_type "CryIn"
14466   attribute \enum_value_00 "ZERO"
14467   attribute \enum_value_01 "ONE"
14468   attribute \enum_value_10 "CA"
14469   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
14470   wire width 2 output 48 \input_carry
14471   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
14472   wire width 32 output 40 \insn
14473   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409"
14474   wire width 32 \insn_in
14475   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446"
14476   wire width 32 \insn_in$36
14477   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89"
14478   wire width 32 \insn_in$37
14479   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
14480   wire width 32 \insn_in$38
14481   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:283"
14482   wire width 32 \insn_in$39
14483   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
14484   wire width 32 \insn_in$40
14485   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
14486   wire width 32 \insn_in$41
14487   attribute \enum_base_type "MicrOp"
14488   attribute \enum_value_0000000 "OP_ILLEGAL"
14489   attribute \enum_value_0000001 "OP_NOP"
14490   attribute \enum_value_0000010 "OP_ADD"
14491   attribute \enum_value_0000011 "OP_ADDPCIS"
14492   attribute \enum_value_0000100 "OP_AND"
14493   attribute \enum_value_0000101 "OP_ATTN"
14494   attribute \enum_value_0000110 "OP_B"
14495   attribute \enum_value_0000111 "OP_BC"
14496   attribute \enum_value_0001000 "OP_BCREG"
14497   attribute \enum_value_0001001 "OP_BPERM"
14498   attribute \enum_value_0001010 "OP_CMP"
14499   attribute \enum_value_0001011 "OP_CMPB"
14500   attribute \enum_value_0001100 "OP_CMPEQB"
14501   attribute \enum_value_0001101 "OP_CMPRB"
14502   attribute \enum_value_0001110 "OP_CNTZ"
14503   attribute \enum_value_0001111 "OP_CRAND"
14504   attribute \enum_value_0010000 "OP_CRANDC"
14505   attribute \enum_value_0010001 "OP_CREQV"
14506   attribute \enum_value_0010010 "OP_CRNAND"
14507   attribute \enum_value_0010011 "OP_CRNOR"
14508   attribute \enum_value_0010100 "OP_CROR"
14509   attribute \enum_value_0010101 "OP_CRORC"
14510   attribute \enum_value_0010110 "OP_CRXOR"
14511   attribute \enum_value_0010111 "OP_DARN"
14512   attribute \enum_value_0011000 "OP_DCBF"
14513   attribute \enum_value_0011001 "OP_DCBST"
14514   attribute \enum_value_0011010 "OP_DCBT"
14515   attribute \enum_value_0011011 "OP_DCBTST"
14516   attribute \enum_value_0011100 "OP_DCBZ"
14517   attribute \enum_value_0011101 "OP_DIV"
14518   attribute \enum_value_0011110 "OP_DIVE"
14519   attribute \enum_value_0011111 "OP_EXTS"
14520   attribute \enum_value_0100000 "OP_EXTSWSLI"
14521   attribute \enum_value_0100001 "OP_ICBI"
14522   attribute \enum_value_0100010 "OP_ICBT"
14523   attribute \enum_value_0100011 "OP_ISEL"
14524   attribute \enum_value_0100100 "OP_ISYNC"
14525   attribute \enum_value_0100101 "OP_LOAD"
14526   attribute \enum_value_0100110 "OP_STORE"
14527   attribute \enum_value_0100111 "OP_MADDHD"
14528   attribute \enum_value_0101000 "OP_MADDHDU"
14529   attribute \enum_value_0101001 "OP_MADDLD"
14530   attribute \enum_value_0101010 "OP_MCRF"
14531   attribute \enum_value_0101011 "OP_MCRXR"
14532   attribute \enum_value_0101100 "OP_MCRXRX"
14533   attribute \enum_value_0101101 "OP_MFCR"
14534   attribute \enum_value_0101110 "OP_MFSPR"
14535   attribute \enum_value_0101111 "OP_MOD"
14536   attribute \enum_value_0110000 "OP_MTCRF"
14537   attribute \enum_value_0110001 "OP_MTSPR"
14538   attribute \enum_value_0110010 "OP_MUL_L64"
14539   attribute \enum_value_0110011 "OP_MUL_H64"
14540   attribute \enum_value_0110100 "OP_MUL_H32"
14541   attribute \enum_value_0110101 "OP_OR"
14542   attribute \enum_value_0110110 "OP_POPCNT"
14543   attribute \enum_value_0110111 "OP_PRTY"
14544   attribute \enum_value_0111000 "OP_RLC"
14545   attribute \enum_value_0111001 "OP_RLCL"
14546   attribute \enum_value_0111010 "OP_RLCR"
14547   attribute \enum_value_0111011 "OP_SETB"
14548   attribute \enum_value_0111100 "OP_SHL"
14549   attribute \enum_value_0111101 "OP_SHR"
14550   attribute \enum_value_0111110 "OP_SYNC"
14551   attribute \enum_value_0111111 "OP_TRAP"
14552   attribute \enum_value_1000011 "OP_XOR"
14553   attribute \enum_value_1000100 "OP_SIM_CONFIG"
14554   attribute \enum_value_1000101 "OP_CROP"
14555   attribute \enum_value_1000110 "OP_RFID"
14556   attribute \enum_value_1000111 "OP_MFMSR"
14557   attribute \enum_value_1001000 "OP_MTMSRD"
14558   attribute \enum_value_1001001 "OP_SC"
14559   attribute \enum_value_1001010 "OP_MTMSR"
14560   attribute \enum_value_1001011 "OP_TLBIE"
14561   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
14562   wire width 7 output 41 \insn_type
14563   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
14564   wire output 63 \is_32bit
14565   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44"
14566   wire \is_priv_insn
14567   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
14568   wire output 43 \lk
14569   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
14570   wire width 64 output 38 \msr
14571   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14572   wire output 46 \oe
14573   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14574   wire output 47 \oe_ok
14575   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905"
14576   wire \priv_ok
14577   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445"
14578   wire width 32 input 4 \raw_opcode_in
14579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14580   wire output 44 \rc
14581   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14582   wire output 45 \rc_ok
14583   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14584   wire width 5 output 10 \reg1
14585   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14586   wire output 11 \reg1_ok
14587   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14588   wire width 5 output 12 \reg2
14589   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14590   wire output 13 \reg2_ok
14591   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14592   wire width 5 output 14 \reg3
14593   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14594   wire output 15 \reg3_ok
14595   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14596   wire width 5 output 6 \rego
14597   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14598   wire output 7 \rego_ok
14599   attribute \enum_base_type "OutSel"
14600   attribute \enum_value_00 "NONE"
14601   attribute \enum_value_01 "RT"
14602   attribute \enum_value_10 "RA"
14603   attribute \enum_value_11 "SPR"
14604   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
14605   wire width 2 \sel_in
14606   attribute \enum_base_type "SPR"
14607   attribute \enum_value_0000000001 "XER"
14608   attribute \enum_value_0000000011 "DSCR"
14609   attribute \enum_value_0000001000 "LR"
14610   attribute \enum_value_0000001001 "CTR"
14611   attribute \enum_value_0000001101 "AMR"
14612   attribute \enum_value_0000010001 "DSCR_priv"
14613   attribute \enum_value_0000010010 "DSISR"
14614   attribute \enum_value_0000010011 "DAR"
14615   attribute \enum_value_0000010110 "DEC"
14616   attribute \enum_value_0000011010 "SRR0"
14617   attribute \enum_value_0000011011 "SRR1"
14618   attribute \enum_value_0000011100 "CFAR"
14619   attribute \enum_value_0000011101 "AMR_priv"
14620   attribute \enum_value_0000110000 "PIDR"
14621   attribute \enum_value_0000111101 "IAMR"
14622   attribute \enum_value_0010000000 "TFHAR"
14623   attribute \enum_value_0010000001 "TFIAR"
14624   attribute \enum_value_0010000010 "TEXASR"
14625   attribute \enum_value_0010000011 "TEXASRU"
14626   attribute \enum_value_0010001000 "CTRL"
14627   attribute \enum_value_0010010000 "TIDR"
14628   attribute \enum_value_0010011000 "CTRL_priv"
14629   attribute \enum_value_0010011001 "FSCR"
14630   attribute \enum_value_0010011101 "UAMOR"
14631   attribute \enum_value_0010011110 "GSR"
14632   attribute \enum_value_0010011111 "PSPB"
14633   attribute \enum_value_0010110000 "DPDES"
14634   attribute \enum_value_0010110100 "DAWR0"
14635   attribute \enum_value_0010111010 "RPR"
14636   attribute \enum_value_0010111011 "CIABR"
14637   attribute \enum_value_0010111100 "DAWRX0"
14638   attribute \enum_value_0010111110 "HFSCR"
14639   attribute \enum_value_0100000000 "VRSAVE"
14640   attribute \enum_value_0100000011 "SPRG3"
14641   attribute \enum_value_0100001100 "TB"
14642   attribute \enum_value_0100001101 "TBU"
14643   attribute \enum_value_0100010000 "SPRG0_priv"
14644   attribute \enum_value_0100010001 "SPRG1_priv"
14645   attribute \enum_value_0100010010 "SPRG2_priv"
14646   attribute \enum_value_0100010011 "SPRG3_priv"
14647   attribute \enum_value_0100011011 "CIR"
14648   attribute \enum_value_0100011100 "TBL"
14649   attribute \enum_value_0100011101 "TBU_hypv"
14650   attribute \enum_value_0100011110 "TBU40"
14651   attribute \enum_value_0100011111 "PVR"
14652   attribute \enum_value_0100110000 "HSPRG0"
14653   attribute \enum_value_0100110001 "HSPRG1"
14654   attribute \enum_value_0100110010 "HDSISR"
14655   attribute \enum_value_0100110011 "HDAR"
14656   attribute \enum_value_0100110100 "SPURR"
14657   attribute \enum_value_0100110101 "PURR"
14658   attribute \enum_value_0100110110 "HDEC"
14659   attribute \enum_value_0100111001 "HRMOR"
14660   attribute \enum_value_0100111010 "HSRR0"
14661   attribute \enum_value_0100111011 "HSRR1"
14662   attribute \enum_value_0100111110 "LPCR"
14663   attribute \enum_value_0100111111 "LPIDR"
14664   attribute \enum_value_0101010000 "HMER"
14665   attribute \enum_value_0101010001 "HMEER"
14666   attribute \enum_value_0101010010 "PCR"
14667   attribute \enum_value_0101010011 "HEIR"
14668   attribute \enum_value_0101011101 "AMOR"
14669   attribute \enum_value_0110111110 "TIR"
14670   attribute \enum_value_0111010000 "PTCR"
14671   attribute \enum_value_1100000000 "SIER"
14672   attribute \enum_value_1100000001 "MMCR2"
14673   attribute \enum_value_1100000010 "MMCRA"
14674   attribute \enum_value_1100000011 "PMC1"
14675   attribute \enum_value_1100000100 "PMC2"
14676   attribute \enum_value_1100000101 "PMC3"
14677   attribute \enum_value_1100000110 "PMC4"
14678   attribute \enum_value_1100000111 "PMC5"
14679   attribute \enum_value_1100001000 "PMC6"
14680   attribute \enum_value_1100001011 "MMCR0"
14681   attribute \enum_value_1100001100 "SIAR"
14682   attribute \enum_value_1100001101 "SDAR"
14683   attribute \enum_value_1100001110 "MMCR1"
14684   attribute \enum_value_1100010000 "SIER_priv"
14685   attribute \enum_value_1100010001 "MMCR2_priv"
14686   attribute \enum_value_1100010010 "MMCRA_priv"
14687   attribute \enum_value_1100010011 "PMC1_priv"
14688   attribute \enum_value_1100010100 "PMC2_priv"
14689   attribute \enum_value_1100010101 "PMC3_priv"
14690   attribute \enum_value_1100010110 "PMC4_priv"
14691   attribute \enum_value_1100010111 "PMC5_priv"
14692   attribute \enum_value_1100011000 "PMC6_priv"
14693   attribute \enum_value_1100011011 "MMCR0_priv"
14694   attribute \enum_value_1100011100 "SIAR_priv"
14695   attribute \enum_value_1100011101 "SDAR_priv"
14696   attribute \enum_value_1100011110 "MMCR1_priv"
14697   attribute \enum_value_1100100000 "BESCRS"
14698   attribute \enum_value_1100100001 "BESCRSU"
14699   attribute \enum_value_1100100010 "BESCRR"
14700   attribute \enum_value_1100100011 "BESCRRU"
14701   attribute \enum_value_1100100100 "EBBHR"
14702   attribute \enum_value_1100100101 "EBBRR"
14703   attribute \enum_value_1100100110 "BESCR"
14704   attribute \enum_value_1100101000 "reserved808"
14705   attribute \enum_value_1100101001 "reserved809"
14706   attribute \enum_value_1100101010 "reserved810"
14707   attribute \enum_value_1100101011 "reserved811"
14708   attribute \enum_value_1100101111 "TAR"
14709   attribute \enum_value_1100110000 "ASDR"
14710   attribute \enum_value_1100110111 "PSSCR"
14711   attribute \enum_value_1101010000 "IC"
14712   attribute \enum_value_1101010001 "VTB"
14713   attribute \enum_value_1101010111 "PSSCR_hypv"
14714   attribute \enum_value_1110000000 "PPR"
14715   attribute \enum_value_1110000010 "PPR32"
14716   attribute \enum_value_1111111111 "PIR"
14717   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14718   wire width 10 output 18 \spr1
14719   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14720   wire output 19 \spr1_ok
14721   attribute \enum_base_type "SPR"
14722   attribute \enum_value_0000000001 "XER"
14723   attribute \enum_value_0000000011 "DSCR"
14724   attribute \enum_value_0000001000 "LR"
14725   attribute \enum_value_0000001001 "CTR"
14726   attribute \enum_value_0000001101 "AMR"
14727   attribute \enum_value_0000010001 "DSCR_priv"
14728   attribute \enum_value_0000010010 "DSISR"
14729   attribute \enum_value_0000010011 "DAR"
14730   attribute \enum_value_0000010110 "DEC"
14731   attribute \enum_value_0000011010 "SRR0"
14732   attribute \enum_value_0000011011 "SRR1"
14733   attribute \enum_value_0000011100 "CFAR"
14734   attribute \enum_value_0000011101 "AMR_priv"
14735   attribute \enum_value_0000110000 "PIDR"
14736   attribute \enum_value_0000111101 "IAMR"
14737   attribute \enum_value_0010000000 "TFHAR"
14738   attribute \enum_value_0010000001 "TFIAR"
14739   attribute \enum_value_0010000010 "TEXASR"
14740   attribute \enum_value_0010000011 "TEXASRU"
14741   attribute \enum_value_0010001000 "CTRL"
14742   attribute \enum_value_0010010000 "TIDR"
14743   attribute \enum_value_0010011000 "CTRL_priv"
14744   attribute \enum_value_0010011001 "FSCR"
14745   attribute \enum_value_0010011101 "UAMOR"
14746   attribute \enum_value_0010011110 "GSR"
14747   attribute \enum_value_0010011111 "PSPB"
14748   attribute \enum_value_0010110000 "DPDES"
14749   attribute \enum_value_0010110100 "DAWR0"
14750   attribute \enum_value_0010111010 "RPR"
14751   attribute \enum_value_0010111011 "CIABR"
14752   attribute \enum_value_0010111100 "DAWRX0"
14753   attribute \enum_value_0010111110 "HFSCR"
14754   attribute \enum_value_0100000000 "VRSAVE"
14755   attribute \enum_value_0100000011 "SPRG3"
14756   attribute \enum_value_0100001100 "TB"
14757   attribute \enum_value_0100001101 "TBU"
14758   attribute \enum_value_0100010000 "SPRG0_priv"
14759   attribute \enum_value_0100010001 "SPRG1_priv"
14760   attribute \enum_value_0100010010 "SPRG2_priv"
14761   attribute \enum_value_0100010011 "SPRG3_priv"
14762   attribute \enum_value_0100011011 "CIR"
14763   attribute \enum_value_0100011100 "TBL"
14764   attribute \enum_value_0100011101 "TBU_hypv"
14765   attribute \enum_value_0100011110 "TBU40"
14766   attribute \enum_value_0100011111 "PVR"
14767   attribute \enum_value_0100110000 "HSPRG0"
14768   attribute \enum_value_0100110001 "HSPRG1"
14769   attribute \enum_value_0100110010 "HDSISR"
14770   attribute \enum_value_0100110011 "HDAR"
14771   attribute \enum_value_0100110100 "SPURR"
14772   attribute \enum_value_0100110101 "PURR"
14773   attribute \enum_value_0100110110 "HDEC"
14774   attribute \enum_value_0100111001 "HRMOR"
14775   attribute \enum_value_0100111010 "HSRR0"
14776   attribute \enum_value_0100111011 "HSRR1"
14777   attribute \enum_value_0100111110 "LPCR"
14778   attribute \enum_value_0100111111 "LPIDR"
14779   attribute \enum_value_0101010000 "HMER"
14780   attribute \enum_value_0101010001 "HMEER"
14781   attribute \enum_value_0101010010 "PCR"
14782   attribute \enum_value_0101010011 "HEIR"
14783   attribute \enum_value_0101011101 "AMOR"
14784   attribute \enum_value_0110111110 "TIR"
14785   attribute \enum_value_0111010000 "PTCR"
14786   attribute \enum_value_1100000000 "SIER"
14787   attribute \enum_value_1100000001 "MMCR2"
14788   attribute \enum_value_1100000010 "MMCRA"
14789   attribute \enum_value_1100000011 "PMC1"
14790   attribute \enum_value_1100000100 "PMC2"
14791   attribute \enum_value_1100000101 "PMC3"
14792   attribute \enum_value_1100000110 "PMC4"
14793   attribute \enum_value_1100000111 "PMC5"
14794   attribute \enum_value_1100001000 "PMC6"
14795   attribute \enum_value_1100001011 "MMCR0"
14796   attribute \enum_value_1100001100 "SIAR"
14797   attribute \enum_value_1100001101 "SDAR"
14798   attribute \enum_value_1100001110 "MMCR1"
14799   attribute \enum_value_1100010000 "SIER_priv"
14800   attribute \enum_value_1100010001 "MMCR2_priv"
14801   attribute \enum_value_1100010010 "MMCRA_priv"
14802   attribute \enum_value_1100010011 "PMC1_priv"
14803   attribute \enum_value_1100010100 "PMC2_priv"
14804   attribute \enum_value_1100010101 "PMC3_priv"
14805   attribute \enum_value_1100010110 "PMC4_priv"
14806   attribute \enum_value_1100010111 "PMC5_priv"
14807   attribute \enum_value_1100011000 "PMC6_priv"
14808   attribute \enum_value_1100011011 "MMCR0_priv"
14809   attribute \enum_value_1100011100 "SIAR_priv"
14810   attribute \enum_value_1100011101 "SDAR_priv"
14811   attribute \enum_value_1100011110 "MMCR1_priv"
14812   attribute \enum_value_1100100000 "BESCRS"
14813   attribute \enum_value_1100100001 "BESCRSU"
14814   attribute \enum_value_1100100010 "BESCRR"
14815   attribute \enum_value_1100100011 "BESCRRU"
14816   attribute \enum_value_1100100100 "EBBHR"
14817   attribute \enum_value_1100100101 "EBBRR"
14818   attribute \enum_value_1100100110 "BESCR"
14819   attribute \enum_value_1100101000 "reserved808"
14820   attribute \enum_value_1100101001 "reserved809"
14821   attribute \enum_value_1100101010 "reserved810"
14822   attribute \enum_value_1100101011 "reserved811"
14823   attribute \enum_value_1100101111 "TAR"
14824   attribute \enum_value_1100110000 "ASDR"
14825   attribute \enum_value_1100110111 "PSSCR"
14826   attribute \enum_value_1101010000 "IC"
14827   attribute \enum_value_1101010001 "VTB"
14828   attribute \enum_value_1101010111 "PSSCR_hypv"
14829   attribute \enum_value_1110000000 "PPR"
14830   attribute \enum_value_1110000010 "PPR32"
14831   attribute \enum_value_1111111111 "PIR"
14832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14833   wire width 10 output 16 \spro
14834   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14835   wire output 17 \spro_ok
14836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
14837   wire width 8 \tmp_asmcode
14838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14839   wire width 3 \tmp_cr_in1
14840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14841   wire \tmp_cr_in1_ok
14842   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14843   wire width 3 \tmp_cr_in2
14844   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14845   wire width 3 \tmp_cr_in2$19
14846   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14847   wire \tmp_cr_in2_ok
14848   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14849   wire \tmp_cr_in2_ok$20
14850   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14851   wire width 3 \tmp_cr_out
14852   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14853   wire \tmp_cr_out_ok
14854   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14855   wire width 5 \tmp_ea
14856   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14857   wire \tmp_ea_ok
14858   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14859   wire width 3 \tmp_fast1
14860   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14861   wire \tmp_fast1_ok
14862   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14863   wire width 3 \tmp_fast2
14864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14865   wire \tmp_fast2_ok
14866   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14867   wire width 3 \tmp_fasto1
14868   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14869   wire \tmp_fasto1_ok
14870   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14871   wire width 3 \tmp_fasto2
14872   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14873   wire \tmp_fasto2_ok
14874   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14875   wire width 5 \tmp_reg1
14876   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14877   wire \tmp_reg1_ok
14878   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14879   wire width 5 \tmp_reg2
14880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14881   wire \tmp_reg2_ok
14882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14883   wire width 5 \tmp_reg3
14884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14885   wire \tmp_reg3_ok
14886   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14887   wire width 5 \tmp_rego
14888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
14889   wire \tmp_rego_ok
14890   attribute \enum_base_type "SPR"
14891   attribute \enum_value_0000000001 "XER"
14892   attribute \enum_value_0000000011 "DSCR"
14893   attribute \enum_value_0000001000 "LR"
14894   attribute \enum_value_0000001001 "CTR"
14895   attribute \enum_value_0000001101 "AMR"
14896   attribute \enum_value_0000010001 "DSCR_priv"
14897   attribute \enum_value_0000010010 "DSISR"
14898   attribute \enum_value_0000010011 "DAR"
14899   attribute \enum_value_0000010110 "DEC"
14900   attribute \enum_value_0000011010 "SRR0"
14901   attribute \enum_value_0000011011 "SRR1"
14902   attribute \enum_value_0000011100 "CFAR"
14903   attribute \enum_value_0000011101 "AMR_priv"
14904   attribute \enum_value_0000110000 "PIDR"
14905   attribute \enum_value_0000111101 "IAMR"
14906   attribute \enum_value_0010000000 "TFHAR"
14907   attribute \enum_value_0010000001 "TFIAR"
14908   attribute \enum_value_0010000010 "TEXASR"
14909   attribute \enum_value_0010000011 "TEXASRU"
14910   attribute \enum_value_0010001000 "CTRL"
14911   attribute \enum_value_0010010000 "TIDR"
14912   attribute \enum_value_0010011000 "CTRL_priv"
14913   attribute \enum_value_0010011001 "FSCR"
14914   attribute \enum_value_0010011101 "UAMOR"
14915   attribute \enum_value_0010011110 "GSR"
14916   attribute \enum_value_0010011111 "PSPB"
14917   attribute \enum_value_0010110000 "DPDES"
14918   attribute \enum_value_0010110100 "DAWR0"
14919   attribute \enum_value_0010111010 "RPR"
14920   attribute \enum_value_0010111011 "CIABR"
14921   attribute \enum_value_0010111100 "DAWRX0"
14922   attribute \enum_value_0010111110 "HFSCR"
14923   attribute \enum_value_0100000000 "VRSAVE"
14924   attribute \enum_value_0100000011 "SPRG3"
14925   attribute \enum_value_0100001100 "TB"
14926   attribute \enum_value_0100001101 "TBU"
14927   attribute \enum_value_0100010000 "SPRG0_priv"
14928   attribute \enum_value_0100010001 "SPRG1_priv"
14929   attribute \enum_value_0100010010 "SPRG2_priv"
14930   attribute \enum_value_0100010011 "SPRG3_priv"
14931   attribute \enum_value_0100011011 "CIR"
14932   attribute \enum_value_0100011100 "TBL"
14933   attribute \enum_value_0100011101 "TBU_hypv"
14934   attribute \enum_value_0100011110 "TBU40"
14935   attribute \enum_value_0100011111 "PVR"
14936   attribute \enum_value_0100110000 "HSPRG0"
14937   attribute \enum_value_0100110001 "HSPRG1"
14938   attribute \enum_value_0100110010 "HDSISR"
14939   attribute \enum_value_0100110011 "HDAR"
14940   attribute \enum_value_0100110100 "SPURR"
14941   attribute \enum_value_0100110101 "PURR"
14942   attribute \enum_value_0100110110 "HDEC"
14943   attribute \enum_value_0100111001 "HRMOR"
14944   attribute \enum_value_0100111010 "HSRR0"
14945   attribute \enum_value_0100111011 "HSRR1"
14946   attribute \enum_value_0100111110 "LPCR"
14947   attribute \enum_value_0100111111 "LPIDR"
14948   attribute \enum_value_0101010000 "HMER"
14949   attribute \enum_value_0101010001 "HMEER"
14950   attribute \enum_value_0101010010 "PCR"
14951   attribute \enum_value_0101010011 "HEIR"
14952   attribute \enum_value_0101011101 "AMOR"
14953   attribute \enum_value_0110111110 "TIR"
14954   attribute \enum_value_0111010000 "PTCR"
14955   attribute \enum_value_1100000000 "SIER"
14956   attribute \enum_value_1100000001 "MMCR2"
14957   attribute \enum_value_1100000010 "MMCRA"
14958   attribute \enum_value_1100000011 "PMC1"
14959   attribute \enum_value_1100000100 "PMC2"
14960   attribute \enum_value_1100000101 "PMC3"
14961   attribute \enum_value_1100000110 "PMC4"
14962   attribute \enum_value_1100000111 "PMC5"
14963   attribute \enum_value_1100001000 "PMC6"
14964   attribute \enum_value_1100001011 "MMCR0"
14965   attribute \enum_value_1100001100 "SIAR"
14966   attribute \enum_value_1100001101 "SDAR"
14967   attribute \enum_value_1100001110 "MMCR1"
14968   attribute \enum_value_1100010000 "SIER_priv"
14969   attribute \enum_value_1100010001 "MMCR2_priv"
14970   attribute \enum_value_1100010010 "MMCRA_priv"
14971   attribute \enum_value_1100010011 "PMC1_priv"
14972   attribute \enum_value_1100010100 "PMC2_priv"
14973   attribute \enum_value_1100010101 "PMC3_priv"
14974   attribute \enum_value_1100010110 "PMC4_priv"
14975   attribute \enum_value_1100010111 "PMC5_priv"
14976   attribute \enum_value_1100011000 "PMC6_priv"
14977   attribute \enum_value_1100011011 "MMCR0_priv"
14978   attribute \enum_value_1100011100 "SIAR_priv"
14979   attribute \enum_value_1100011101 "SDAR_priv"
14980   attribute \enum_value_1100011110 "MMCR1_priv"
14981   attribute \enum_value_1100100000 "BESCRS"
14982   attribute \enum_value_1100100001 "BESCRSU"
14983   attribute \enum_value_1100100010 "BESCRR"
14984   attribute \enum_value_1100100011 "BESCRRU"
14985   attribute \enum_value_1100100100 "EBBHR"
14986   attribute \enum_value_1100100101 "EBBRR"
14987   attribute \enum_value_1100100110 "BESCR"
14988   attribute \enum_value_1100101000 "reserved808"
14989   attribute \enum_value_1100101001 "reserved809"
14990   attribute \enum_value_1100101010 "reserved810"
14991   attribute \enum_value_1100101011 "reserved811"
14992   attribute \enum_value_1100101111 "TAR"
14993   attribute \enum_value_1100110000 "ASDR"
14994   attribute \enum_value_1100110111 "PSSCR"
14995   attribute \enum_value_1101010000 "IC"
14996   attribute \enum_value_1101010001 "VTB"
14997   attribute \enum_value_1101010111 "PSSCR_hypv"
14998   attribute \enum_value_1110000000 "PPR"
14999   attribute \enum_value_1110000010 "PPR32"
15000   attribute \enum_value_1111111111 "PIR"
15001   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15002   wire width 10 \tmp_spr1
15003   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15004   wire \tmp_spr1_ok
15005   attribute \enum_base_type "SPR"
15006   attribute \enum_value_0000000001 "XER"
15007   attribute \enum_value_0000000011 "DSCR"
15008   attribute \enum_value_0000001000 "LR"
15009   attribute \enum_value_0000001001 "CTR"
15010   attribute \enum_value_0000001101 "AMR"
15011   attribute \enum_value_0000010001 "DSCR_priv"
15012   attribute \enum_value_0000010010 "DSISR"
15013   attribute \enum_value_0000010011 "DAR"
15014   attribute \enum_value_0000010110 "DEC"
15015   attribute \enum_value_0000011010 "SRR0"
15016   attribute \enum_value_0000011011 "SRR1"
15017   attribute \enum_value_0000011100 "CFAR"
15018   attribute \enum_value_0000011101 "AMR_priv"
15019   attribute \enum_value_0000110000 "PIDR"
15020   attribute \enum_value_0000111101 "IAMR"
15021   attribute \enum_value_0010000000 "TFHAR"
15022   attribute \enum_value_0010000001 "TFIAR"
15023   attribute \enum_value_0010000010 "TEXASR"
15024   attribute \enum_value_0010000011 "TEXASRU"
15025   attribute \enum_value_0010001000 "CTRL"
15026   attribute \enum_value_0010010000 "TIDR"
15027   attribute \enum_value_0010011000 "CTRL_priv"
15028   attribute \enum_value_0010011001 "FSCR"
15029   attribute \enum_value_0010011101 "UAMOR"
15030   attribute \enum_value_0010011110 "GSR"
15031   attribute \enum_value_0010011111 "PSPB"
15032   attribute \enum_value_0010110000 "DPDES"
15033   attribute \enum_value_0010110100 "DAWR0"
15034   attribute \enum_value_0010111010 "RPR"
15035   attribute \enum_value_0010111011 "CIABR"
15036   attribute \enum_value_0010111100 "DAWRX0"
15037   attribute \enum_value_0010111110 "HFSCR"
15038   attribute \enum_value_0100000000 "VRSAVE"
15039   attribute \enum_value_0100000011 "SPRG3"
15040   attribute \enum_value_0100001100 "TB"
15041   attribute \enum_value_0100001101 "TBU"
15042   attribute \enum_value_0100010000 "SPRG0_priv"
15043   attribute \enum_value_0100010001 "SPRG1_priv"
15044   attribute \enum_value_0100010010 "SPRG2_priv"
15045   attribute \enum_value_0100010011 "SPRG3_priv"
15046   attribute \enum_value_0100011011 "CIR"
15047   attribute \enum_value_0100011100 "TBL"
15048   attribute \enum_value_0100011101 "TBU_hypv"
15049   attribute \enum_value_0100011110 "TBU40"
15050   attribute \enum_value_0100011111 "PVR"
15051   attribute \enum_value_0100110000 "HSPRG0"
15052   attribute \enum_value_0100110001 "HSPRG1"
15053   attribute \enum_value_0100110010 "HDSISR"
15054   attribute \enum_value_0100110011 "HDAR"
15055   attribute \enum_value_0100110100 "SPURR"
15056   attribute \enum_value_0100110101 "PURR"
15057   attribute \enum_value_0100110110 "HDEC"
15058   attribute \enum_value_0100111001 "HRMOR"
15059   attribute \enum_value_0100111010 "HSRR0"
15060   attribute \enum_value_0100111011 "HSRR1"
15061   attribute \enum_value_0100111110 "LPCR"
15062   attribute \enum_value_0100111111 "LPIDR"
15063   attribute \enum_value_0101010000 "HMER"
15064   attribute \enum_value_0101010001 "HMEER"
15065   attribute \enum_value_0101010010 "PCR"
15066   attribute \enum_value_0101010011 "HEIR"
15067   attribute \enum_value_0101011101 "AMOR"
15068   attribute \enum_value_0110111110 "TIR"
15069   attribute \enum_value_0111010000 "PTCR"
15070   attribute \enum_value_1100000000 "SIER"
15071   attribute \enum_value_1100000001 "MMCR2"
15072   attribute \enum_value_1100000010 "MMCRA"
15073   attribute \enum_value_1100000011 "PMC1"
15074   attribute \enum_value_1100000100 "PMC2"
15075   attribute \enum_value_1100000101 "PMC3"
15076   attribute \enum_value_1100000110 "PMC4"
15077   attribute \enum_value_1100000111 "PMC5"
15078   attribute \enum_value_1100001000 "PMC6"
15079   attribute \enum_value_1100001011 "MMCR0"
15080   attribute \enum_value_1100001100 "SIAR"
15081   attribute \enum_value_1100001101 "SDAR"
15082   attribute \enum_value_1100001110 "MMCR1"
15083   attribute \enum_value_1100010000 "SIER_priv"
15084   attribute \enum_value_1100010001 "MMCR2_priv"
15085   attribute \enum_value_1100010010 "MMCRA_priv"
15086   attribute \enum_value_1100010011 "PMC1_priv"
15087   attribute \enum_value_1100010100 "PMC2_priv"
15088   attribute \enum_value_1100010101 "PMC3_priv"
15089   attribute \enum_value_1100010110 "PMC4_priv"
15090   attribute \enum_value_1100010111 "PMC5_priv"
15091   attribute \enum_value_1100011000 "PMC6_priv"
15092   attribute \enum_value_1100011011 "MMCR0_priv"
15093   attribute \enum_value_1100011100 "SIAR_priv"
15094   attribute \enum_value_1100011101 "SDAR_priv"
15095   attribute \enum_value_1100011110 "MMCR1_priv"
15096   attribute \enum_value_1100100000 "BESCRS"
15097   attribute \enum_value_1100100001 "BESCRSU"
15098   attribute \enum_value_1100100010 "BESCRR"
15099   attribute \enum_value_1100100011 "BESCRRU"
15100   attribute \enum_value_1100100100 "EBBHR"
15101   attribute \enum_value_1100100101 "EBBRR"
15102   attribute \enum_value_1100100110 "BESCR"
15103   attribute \enum_value_1100101000 "reserved808"
15104   attribute \enum_value_1100101001 "reserved809"
15105   attribute \enum_value_1100101010 "reserved810"
15106   attribute \enum_value_1100101011 "reserved811"
15107   attribute \enum_value_1100101111 "TAR"
15108   attribute \enum_value_1100110000 "ASDR"
15109   attribute \enum_value_1100110111 "PSSCR"
15110   attribute \enum_value_1101010000 "IC"
15111   attribute \enum_value_1101010001 "VTB"
15112   attribute \enum_value_1101010111 "PSSCR_hypv"
15113   attribute \enum_value_1110000000 "PPR"
15114   attribute \enum_value_1110000010 "PPR32"
15115   attribute \enum_value_1111111111 "PIR"
15116   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15117   wire width 10 \tmp_spro
15118   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15119   wire \tmp_spro_ok
15120   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
15121   wire width 64 \tmp_tmp_cia
15122   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15123   wire width 8 \tmp_tmp_cr_rd
15124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15125   wire \tmp_tmp_cr_rd_ok
15126   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15127   wire width 8 \tmp_tmp_cr_wr
15128   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15129   wire \tmp_tmp_cr_wr_ok
15130   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15131   wire \tmp_tmp_exc_$signal
15132   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15133   wire \tmp_tmp_exc_$signal$21
15134   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15135   wire \tmp_tmp_exc_$signal$22
15136   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15137   wire \tmp_tmp_exc_$signal$23
15138   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15139   wire \tmp_tmp_exc_$signal$24
15140   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15141   wire \tmp_tmp_exc_$signal$25
15142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15143   wire \tmp_tmp_exc_$signal$26
15144   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
15145   wire \tmp_tmp_exc_$signal$27
15146   attribute \enum_base_type "Function"
15147   attribute \enum_value_000000000000 "NONE"
15148   attribute \enum_value_000000000010 "ALU"
15149   attribute \enum_value_000000000100 "LDST"
15150   attribute \enum_value_000000001000 "SHIFT_ROT"
15151   attribute \enum_value_000000010000 "LOGICAL"
15152   attribute \enum_value_000000100000 "BRANCH"
15153   attribute \enum_value_000001000000 "CR"
15154   attribute \enum_value_000010000000 "TRAP"
15155   attribute \enum_value_000100000000 "MUL"
15156   attribute \enum_value_001000000000 "DIV"
15157   attribute \enum_value_010000000000 "SPR"
15158   attribute \enum_value_100000000000 "MMU"
15159   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
15160   wire width 12 \tmp_tmp_fn_unit
15161   attribute \enum_base_type "CryIn"
15162   attribute \enum_value_00 "ZERO"
15163   attribute \enum_value_01 "ONE"
15164   attribute \enum_value_10 "CA"
15165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
15166   wire width 2 \tmp_tmp_input_carry
15167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
15168   wire width 32 \tmp_tmp_insn
15169   attribute \enum_base_type "MicrOp"
15170   attribute \enum_value_0000000 "OP_ILLEGAL"
15171   attribute \enum_value_0000001 "OP_NOP"
15172   attribute \enum_value_0000010 "OP_ADD"
15173   attribute \enum_value_0000011 "OP_ADDPCIS"
15174   attribute \enum_value_0000100 "OP_AND"
15175   attribute \enum_value_0000101 "OP_ATTN"
15176   attribute \enum_value_0000110 "OP_B"
15177   attribute \enum_value_0000111 "OP_BC"
15178   attribute \enum_value_0001000 "OP_BCREG"
15179   attribute \enum_value_0001001 "OP_BPERM"
15180   attribute \enum_value_0001010 "OP_CMP"
15181   attribute \enum_value_0001011 "OP_CMPB"
15182   attribute \enum_value_0001100 "OP_CMPEQB"
15183   attribute \enum_value_0001101 "OP_CMPRB"
15184   attribute \enum_value_0001110 "OP_CNTZ"
15185   attribute \enum_value_0001111 "OP_CRAND"
15186   attribute \enum_value_0010000 "OP_CRANDC"
15187   attribute \enum_value_0010001 "OP_CREQV"
15188   attribute \enum_value_0010010 "OP_CRNAND"
15189   attribute \enum_value_0010011 "OP_CRNOR"
15190   attribute \enum_value_0010100 "OP_CROR"
15191   attribute \enum_value_0010101 "OP_CRORC"
15192   attribute \enum_value_0010110 "OP_CRXOR"
15193   attribute \enum_value_0010111 "OP_DARN"
15194   attribute \enum_value_0011000 "OP_DCBF"
15195   attribute \enum_value_0011001 "OP_DCBST"
15196   attribute \enum_value_0011010 "OP_DCBT"
15197   attribute \enum_value_0011011 "OP_DCBTST"
15198   attribute \enum_value_0011100 "OP_DCBZ"
15199   attribute \enum_value_0011101 "OP_DIV"
15200   attribute \enum_value_0011110 "OP_DIVE"
15201   attribute \enum_value_0011111 "OP_EXTS"
15202   attribute \enum_value_0100000 "OP_EXTSWSLI"
15203   attribute \enum_value_0100001 "OP_ICBI"
15204   attribute \enum_value_0100010 "OP_ICBT"
15205   attribute \enum_value_0100011 "OP_ISEL"
15206   attribute \enum_value_0100100 "OP_ISYNC"
15207   attribute \enum_value_0100101 "OP_LOAD"
15208   attribute \enum_value_0100110 "OP_STORE"
15209   attribute \enum_value_0100111 "OP_MADDHD"
15210   attribute \enum_value_0101000 "OP_MADDHDU"
15211   attribute \enum_value_0101001 "OP_MADDLD"
15212   attribute \enum_value_0101010 "OP_MCRF"
15213   attribute \enum_value_0101011 "OP_MCRXR"
15214   attribute \enum_value_0101100 "OP_MCRXRX"
15215   attribute \enum_value_0101101 "OP_MFCR"
15216   attribute \enum_value_0101110 "OP_MFSPR"
15217   attribute \enum_value_0101111 "OP_MOD"
15218   attribute \enum_value_0110000 "OP_MTCRF"
15219   attribute \enum_value_0110001 "OP_MTSPR"
15220   attribute \enum_value_0110010 "OP_MUL_L64"
15221   attribute \enum_value_0110011 "OP_MUL_H64"
15222   attribute \enum_value_0110100 "OP_MUL_H32"
15223   attribute \enum_value_0110101 "OP_OR"
15224   attribute \enum_value_0110110 "OP_POPCNT"
15225   attribute \enum_value_0110111 "OP_PRTY"
15226   attribute \enum_value_0111000 "OP_RLC"
15227   attribute \enum_value_0111001 "OP_RLCL"
15228   attribute \enum_value_0111010 "OP_RLCR"
15229   attribute \enum_value_0111011 "OP_SETB"
15230   attribute \enum_value_0111100 "OP_SHL"
15231   attribute \enum_value_0111101 "OP_SHR"
15232   attribute \enum_value_0111110 "OP_SYNC"
15233   attribute \enum_value_0111111 "OP_TRAP"
15234   attribute \enum_value_1000011 "OP_XOR"
15235   attribute \enum_value_1000100 "OP_SIM_CONFIG"
15236   attribute \enum_value_1000101 "OP_CROP"
15237   attribute \enum_value_1000110 "OP_RFID"
15238   attribute \enum_value_1000111 "OP_MFMSR"
15239   attribute \enum_value_1001000 "OP_MTMSRD"
15240   attribute \enum_value_1001001 "OP_SC"
15241   attribute \enum_value_1001010 "OP_MTMSR"
15242   attribute \enum_value_1001011 "OP_TLBIE"
15243   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
15244   wire width 7 \tmp_tmp_insn_type
15245   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
15246   wire \tmp_tmp_is_32bit
15247   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
15248   wire \tmp_tmp_lk
15249   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
15250   wire width 64 \tmp_tmp_msr
15251   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15252   wire \tmp_tmp_oe
15253   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15254   wire \tmp_tmp_oe_ok
15255   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15256   wire \tmp_tmp_rc
15257   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
15258   wire \tmp_tmp_rc_ok
15259   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
15260   wire width 13 \tmp_tmp_trapaddr
15261   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
15262   wire width 8 \tmp_tmp_traptype
15263   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
15264   wire width 3 \tmp_xer_in
15265   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
15266   wire \tmp_xer_out
15267   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
15268   wire width 13 output 58 \trapaddr
15269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
15270   wire width 8 output 49 \traptype
15271   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
15272   wire width 3 output 20 \xer_in
15273   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
15274   wire output 21 \xer_out
15275   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909"
15276   cell $and $and$libresoc.v:10239$296
15277     parameter \A_SIGNED 0
15278     parameter \A_WIDTH 1
15279     parameter \B_SIGNED 0
15280     parameter \B_WIDTH 1
15281     parameter \Y_WIDTH 1
15282     connect \A \cur_eint
15283     connect \B \cur_msr [15]
15284     connect \Y $and$libresoc.v:10239$296_Y
15285   end
15286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910"
15287   cell $and $and$libresoc.v:10240$297
15288     parameter \A_SIGNED 0
15289     parameter \A_WIDTH 1
15290     parameter \B_SIGNED 0
15291     parameter \B_WIDTH 1
15292     parameter \Y_WIDTH 1
15293     connect \A \cur_dec [63]
15294     connect \B \cur_msr [15]
15295     connect \Y $and$libresoc.v:10240$297_Y
15296   end
15297   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911"
15298   cell $and $and$libresoc.v:10241$298
15299     parameter \A_SIGNED 0
15300     parameter \A_WIDTH 1
15301     parameter \B_SIGNED 0
15302     parameter \B_WIDTH 1
15303     parameter \Y_WIDTH 1
15304     connect \A \is_priv_insn
15305     connect \B \cur_msr [14]
15306     connect \Y $and$libresoc.v:10241$298_Y
15307   end
15308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960"
15309   cell $eq $eq$libresoc.v:10231$288
15310     parameter \A_SIGNED 0
15311     parameter \A_WIDTH 7
15312     parameter \B_SIGNED 0
15313     parameter \B_WIDTH 7
15314     parameter \Y_WIDTH 1
15315     connect \A \insn_type
15316     connect \B 7'0111111
15317     connect \Y $eq$libresoc.v:10231$288_Y
15318   end
15319   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961"
15320   cell $eq $eq$libresoc.v:10232$289
15321     parameter \A_SIGNED 0
15322     parameter \A_WIDTH 7
15323     parameter \B_SIGNED 0
15324     parameter \B_WIDTH 7
15325     parameter \Y_WIDTH 1
15326     connect \A \insn_type
15327     connect \B 7'1001001
15328     connect \Y $eq$libresoc.v:10232$289_Y
15329   end
15330   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970"
15331   cell $eq $eq$libresoc.v:10234$291
15332     parameter \A_SIGNED 0
15333     parameter \A_WIDTH 7
15334     parameter \B_SIGNED 0
15335     parameter \B_WIDTH 7
15336     parameter \Y_WIDTH 1
15337     connect \A \insn_type
15338     connect \B 7'1000110
15339     connect \Y $eq$libresoc.v:10234$291_Y
15340   end
15341   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878"
15342   cell $eq $eq$libresoc.v:10235$292
15343     parameter \A_SIGNED 0
15344     parameter \A_WIDTH 7
15345     parameter \B_SIGNED 0
15346     parameter \B_WIDTH 7
15347     parameter \Y_WIDTH 1
15348     connect \A \dec_internal_op
15349     connect \B 7'0101110
15350     connect \Y $eq$libresoc.v:10235$292_Y
15351   end
15352   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880"
15353   cell $eq $eq$libresoc.v:10236$293
15354     parameter \A_SIGNED 0
15355     parameter \A_WIDTH 7
15356     parameter \B_SIGNED 0
15357     parameter \B_WIDTH 7
15358     parameter \Y_WIDTH 1
15359     connect \A \dec_internal_op
15360     connect \B 7'0001010
15361     connect \Y $eq$libresoc.v:10236$293_Y
15362   end
15363   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882"
15364   cell $eq $eq$libresoc.v:10237$294
15365     parameter \A_SIGNED 0
15366     parameter \A_WIDTH 7
15367     parameter \B_SIGNED 0
15368     parameter \B_WIDTH 7
15369     parameter \Y_WIDTH 1
15370     connect \A \dec_internal_op
15371     connect \B 7'0110001
15372     connect \Y $eq$libresoc.v:10237$294_Y
15373   end
15374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886"
15375   cell $eq $eq$libresoc.v:10238$295
15376     parameter \A_SIGNED 0
15377     parameter \A_WIDTH 7
15378     parameter \B_SIGNED 0
15379     parameter \B_WIDTH 7
15380     parameter \Y_WIDTH 1
15381     connect \A \dec_internal_op
15382     connect \B 7'0111111
15383     connect \Y $eq$libresoc.v:10238$295_Y
15384   end
15385   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912"
15386   cell $eq $eq$libresoc.v:10242$299
15387     parameter \A_SIGNED 0
15388     parameter \A_WIDTH 7
15389     parameter \B_SIGNED 0
15390     parameter \B_WIDTH 7
15391     parameter \Y_WIDTH 1
15392     connect \A \dec_internal_op
15393     connect \B 7'0000000
15394     connect \Y $eq$libresoc.v:10242$299_Y
15395   end
15396   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961"
15397   cell $or $or$libresoc.v:10233$290
15398     parameter \A_SIGNED 0
15399     parameter \A_WIDTH 1
15400     parameter \B_SIGNED 0
15401     parameter \B_WIDTH 1
15402     parameter \Y_WIDTH 1
15403     connect \A \$28
15404     connect \B \$30
15405     connect \Y $or$libresoc.v:10233$290_Y
15406   end
15407   attribute \module_not_derived 1
15408   attribute \src "libresoc.v:10243.7-10280.4"
15409   cell \dec \dec
15410     connect \BA \dec_BA
15411     connect \BB \dec_BB
15412     connect \BC \dec_BC
15413     connect \BI \dec_BI
15414     connect \BO \dec_BO
15415     connect \BT \dec_BT
15416     connect \FXM \dec_FXM
15417     connect \LK \dec_LK
15418     connect \OE \dec_OE
15419     connect \RA \dec_RA
15420     connect \RB \dec_RB
15421     connect \RS \dec_RS
15422     connect \RT \dec_RT
15423     connect \Rc \dec_Rc
15424     connect \SPR \dec_SPR
15425     connect \XL_BT \dec_XL_BT
15426     connect \XL_XO \dec_XL_XO
15427     connect \X_BF \dec_X_BF
15428     connect \X_BFA \dec_X_BFA
15429     connect \asmcode \dec_asmcode
15430     connect \bigendian \bigendian
15431     connect \cr_in \dec_cr_in
15432     connect \cr_out \dec_cr_out
15433     connect \cry_in \dec_cry_in
15434     connect \function_unit \dec_function_unit
15435     connect \in1_sel \dec_in1_sel
15436     connect \in2_sel \dec_in2_sel
15437     connect \in3_sel \dec_in3_sel
15438     connect \internal_op \dec_internal_op
15439     connect \is_32b \dec_is_32b
15440     connect \lk \dec_lk
15441     connect \opcode_in \dec_opcode_in
15442     connect \out_sel \dec_out_sel
15443     connect \raw_opcode_in \raw_opcode_in
15444     connect \rc_sel \dec_rc_sel
15445     connect \upd \dec_upd
15446   end
15447   attribute \module_not_derived 1
15448   attribute \src "libresoc.v:10281.9-10295.4"
15449   cell \dec_a \dec_a
15450     connect \BO \dec_BO
15451     connect \RA \dec_RA
15452     connect \RS \dec_RS
15453     connect \SPR \dec_SPR
15454     connect \XL_XO \dec_XL_XO
15455     connect \fast_a \dec_a_fast_a
15456     connect \fast_a_ok \dec_a_fast_a_ok
15457     connect \internal_op \dec_internal_op
15458     connect \reg_a \dec_a_reg_a
15459     connect \reg_a_ok \dec_a_reg_a_ok
15460     connect \sel_in \dec_a_sel_in
15461     connect \spr_a \dec_a_spr_a
15462     connect \spr_a_ok \dec_a_spr_a_ok
15463   end
15464   attribute \module_not_derived 1
15465   attribute \src "libresoc.v:10296.9-10306.4"
15466   cell \dec_b \dec_b
15467     connect \RB \dec_RB
15468     connect \RS \dec_RS
15469     connect \XL_XO \dec_XL_XO
15470     connect \fast_b \dec_b_fast_b
15471     connect \fast_b_ok \dec_b_fast_b_ok
15472     connect \internal_op \dec_internal_op
15473     connect \reg_b \dec_b_reg_b
15474     connect \reg_b_ok \dec_b_reg_b_ok
15475     connect \sel_in \dec_b_sel_in
15476   end
15477   attribute \module_not_derived 1
15478   attribute \src "libresoc.v:10307.9-10313.4"
15479   cell \dec_c \dec_c
15480     connect \RB \dec_RB
15481     connect \RS \dec_RS
15482     connect \reg_c \dec_c_reg_c
15483     connect \reg_c_ok \dec_c_reg_c_ok
15484     connect \sel_in \dec_c_sel_in
15485   end
15486   attribute \module_not_derived 1
15487   attribute \src "libresoc.v:10314.13-10333.4"
15488   cell \dec_cr_in \dec_cr_in$10
15489     connect \BA \dec_BA
15490     connect \BB \dec_BB
15491     connect \BC \dec_BC
15492     connect \BI \dec_BI
15493     connect \BT \dec_BT
15494     connect \FXM \dec_FXM
15495     connect \X_BFA \dec_X_BFA
15496     connect \cr_bitfield \dec_cr_in_cr_bitfield
15497     connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b
15498     connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok
15499     connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o
15500     connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok
15501     connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok
15502     connect \cr_fxm \dec_cr_in_cr_fxm
15503     connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok
15504     connect \insn_in \dec_cr_in_insn_in
15505     connect \internal_op \dec_internal_op
15506     connect \sel_in \dec_cr_in_sel_in
15507   end
15508   attribute \module_not_derived 1
15509   attribute \src "libresoc.v:10334.14-10346.4"
15510   cell \dec_cr_out \dec_cr_out$11
15511     connect \FXM \dec_FXM
15512     connect \XL_BT \dec_XL_BT
15513     connect \X_BF \dec_X_BF
15514     connect \cr_bitfield \dec_cr_out_cr_bitfield
15515     connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok
15516     connect \cr_fxm \dec_cr_out_cr_fxm
15517     connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok
15518     connect \insn_in \dec_cr_out_insn_in
15519     connect \internal_op \dec_internal_op
15520     connect \rc_in \dec_cr_out_rc_in
15521     connect \sel_in \dec_cr_out_sel_in
15522   end
15523   attribute \module_not_derived 1
15524   attribute \src "libresoc.v:10347.9-10360.4"
15525   cell \dec_o \dec_o
15526     connect \BO \dec_BO
15527     connect \RA \dec_RA
15528     connect \RT \dec_RT
15529     connect \SPR \dec_SPR
15530     connect \fast_o \dec_o_fast_o
15531     connect \fast_o_ok \dec_o_fast_o_ok
15532     connect \internal_op \dec_internal_op
15533     connect \reg_o \dec_o_reg_o
15534     connect \reg_o_ok \dec_o_reg_o_ok
15535     connect \sel_in \dec_o_sel_in
15536     connect \spr_o \dec_o_spr_o
15537     connect \spr_o_ok \dec_o_spr_o_ok
15538   end
15539   attribute \module_not_derived 1
15540   attribute \src "libresoc.v:10361.10-10370.4"
15541   cell \dec_o2 \dec_o2
15542     connect \RA \dec_RA
15543     connect \fast_o \dec_o2_fast_o
15544     connect \fast_o_ok \dec_o2_fast_o_ok
15545     connect \internal_op \dec_internal_op
15546     connect \lk \dec_o2_lk
15547     connect \reg_o \dec_o2_reg_o
15548     connect \reg_o_ok \dec_o2_reg_o_ok
15549     connect \upd \dec_upd
15550   end
15551   attribute \module_not_derived 1
15552   attribute \src "libresoc.v:10371.10-10377.4"
15553   cell \dec_oe \dec_oe
15554     connect \OE \dec_OE
15555     connect \internal_op \dec_internal_op
15556     connect \oe \dec_oe_oe
15557     connect \oe_ok \dec_oe_oe_ok
15558     connect \sel_in \dec_oe_sel_in
15559   end
15560   attribute \module_not_derived 1
15561   attribute \src "libresoc.v:10378.10-10383.4"
15562   cell \dec_rc \dec_rc
15563     connect \Rc \dec_Rc
15564     connect \rc \dec_rc_rc
15565     connect \rc_ok \dec_rc_rc_ok
15566     connect \sel_in \dec_rc_sel_in
15567   end
15568   attribute \src "libresoc.v:10384.3-10393.6"
15569   process $proc$libresoc.v:10384$300
15570     assign { } { }
15571     assign { } { }
15572     assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0]
15573     attribute \src "libresoc.v:10385.5-10385.29"
15574     switch \initial
15575       attribute \src "libresoc.v:10385.9-10385.17"
15576       case 1'1
15577       case
15578     end
15579     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762"
15580     switch \dec_lk
15581       attribute \src "libresoc.v:0.0-0.0"
15582       case 1'1
15583         assign { } { }
15584         assign $1\tmp_tmp_lk[0:0] \dec_LK
15585       case
15586         assign $1\tmp_tmp_lk[0:0] 1'0
15587     end
15588     sync always
15589       update \tmp_tmp_lk $0\tmp_tmp_lk[0:0]
15590   end
15591   attribute \src "libresoc.v:10394.3-10409.6"
15592   process $proc$libresoc.v:10394$301
15593     assign { } { }
15594     assign { } { }
15595     assign { } { }
15596     assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0]
15597     attribute \src "libresoc.v:10395.5-10395.29"
15598     switch \initial
15599       attribute \src "libresoc.v:10395.9-10395.17"
15600       case 1'1
15601       case
15602     end
15603     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878"
15604     switch \$42
15605       attribute \src "libresoc.v:0.0-0.0"
15606       case 1'1
15607         assign { } { }
15608         assign $1\tmp_xer_in[2:0] 3'111
15609       case
15610         assign $1\tmp_xer_in[2:0] 3'000
15611     end
15612     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880"
15613     switch \$44
15614       attribute \src "libresoc.v:0.0-0.0"
15615       case 1'1
15616         assign { } { }
15617         assign $2\tmp_xer_in[2:0] 3'001
15618       case
15619         assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0]
15620     end
15621     sync always
15622       update \tmp_xer_in $0\tmp_xer_in[2:0]
15623   end
15624   attribute \src "libresoc.v:10410.3-10419.6"
15625   process $proc$libresoc.v:10410$302
15626     assign { } { }
15627     assign { } { }
15628     assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0]
15629     attribute \src "libresoc.v:10411.5-10411.29"
15630     switch \initial
15631       attribute \src "libresoc.v:10411.9-10411.17"
15632       case 1'1
15633       case
15634     end
15635     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882"
15636     switch \$46
15637       attribute \src "libresoc.v:0.0-0.0"
15638       case 1'1
15639         assign { } { }
15640         assign $1\tmp_xer_out[0:0] 1'1
15641       case
15642         assign $1\tmp_xer_out[0:0] 1'0
15643     end
15644     sync always
15645       update \tmp_xer_out $0\tmp_xer_out[0:0]
15646   end
15647   attribute \src "libresoc.v:10420.3-10429.6"
15648   process $proc$libresoc.v:10420$303
15649     assign { } { }
15650     assign { } { }
15651     assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0]
15652     attribute \src "libresoc.v:10421.5-10421.29"
15653     switch \initial
15654       attribute \src "libresoc.v:10421.9-10421.17"
15655       case 1'1
15656       case
15657     end
15658     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886"
15659     switch \$48
15660       attribute \src "libresoc.v:0.0-0.0"
15661       case 1'1
15662         assign { } { }
15663         assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000
15664       case
15665         assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000
15666     end
15667     sync always
15668       update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0]
15669   end
15670   attribute \src "libresoc.v:10430.3-10449.6"
15671   process $proc$libresoc.v:10430$304
15672     assign { } { }
15673     assign { } { }
15674     assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0]
15675     attribute \src "libresoc.v:10431.5-10431.29"
15676     switch \initial
15677       attribute \src "libresoc.v:10431.9-10431.17"
15678       case 1'1
15679       case
15680     end
15681     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45"
15682     switch \dec_internal_op
15683       attribute \src "libresoc.v:0.0-0.0"
15684       case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110
15685         assign { } { }
15686         assign $1\is_priv_insn[0:0] 1'1
15687       attribute \src "libresoc.v:0.0-0.0"
15688       case 7'0101110 , 7'0110001
15689         assign { } { }
15690         assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0]
15691         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52"
15692         switch \tmp_tmp_insn [20]
15693           attribute \src "libresoc.v:0.0-0.0"
15694           case 1'1
15695             assign { } { }
15696             assign $2\is_priv_insn[0:0] 1'1
15697           case
15698             assign $2\is_priv_insn[0:0] 1'0
15699         end
15700       case
15701         assign $1\is_priv_insn[0:0] 1'0
15702     end
15703     sync always
15704       update \is_priv_insn $0\is_priv_insn[0:0]
15705   end
15706   attribute \src "libresoc.v:10450.3-10607.6"
15707   process $proc$libresoc.v:10450$305
15708     assign { } { }
15709     assign { } { }
15710     assign { } { }
15711     assign { } { }
15712     assign { } { }
15713     assign { } { }
15714     assign { } { }
15715     assign { } { }
15716     assign { } { }
15717     assign { } { }
15718     assign { } { }
15719     assign { } { }
15720     assign { } { }
15721     assign { } { }
15722     assign { } { }
15723     assign { } { }
15724     assign { } { }
15725     assign { } { }
15726     assign { } { }
15727     assign { } { }
15728     assign { } { }
15729     assign { } { }
15730     assign { } { }
15731     assign { } { }
15732     assign { } { }
15733     assign { } { }
15734     assign { } { }
15735     assign { } { }
15736     assign { } { }
15737     assign { } { }
15738     assign { } { }
15739     assign { } { }
15740     assign { } { }
15741     assign { } { }
15742     assign { } { }
15743     assign { } { }
15744     assign { } { }
15745     assign { } { }
15746     assign { } { }
15747     assign { } { }
15748     assign { } { }
15749     assign { } { }
15750     assign { } { }
15751     assign { } { }
15752     assign { } { }
15753     assign { } { }
15754     assign { } { }
15755     assign { } { }
15756     assign { } { }
15757     assign { } { }
15758     assign { } { }
15759     assign { } { }
15760     assign { } { }
15761     assign { } { }
15762     assign { } { }
15763     assign { } { }
15764     assign { } { }
15765     assign { } { }
15766     assign { } { }
15767     assign { } { }
15768     assign $0\cr_out[2:0] $1\cr_out[2:0]
15769     assign $0\lk[0:0] $1\lk[0:0]
15770     assign $0\cia[63:0] $1\cia[63:0]
15771     assign $0\cr_in1[2:0] $1\cr_in1[2:0]
15772     assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0]
15773     assign $0\cr_in2[2:0] $1\cr_in2[2:0]
15774     assign $0\cr_in2$1[2:0]$306 $1\cr_in2$1[2:0]$316
15775     assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0]
15776     assign $0\cr_in2_ok$2[0:0]$307 $1\cr_in2_ok$2[0:0]$317
15777     assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0]
15778     assign $0\cr_rd[7:0] $1\cr_rd[7:0]
15779     assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0]
15780     assign $0\cr_wr[7:0] $1\cr_wr[7:0]
15781     assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0]
15782     assign $0\ea[4:0] $1\ea[4:0]
15783     assign $0\ea_ok[0:0] $1\ea_ok[0:0]
15784     assign $0\exc_$signal[0:0]$308 $1\exc_$signal[0:0]$318
15785     assign $0\exc_$signal$3[0:0]$309 $1\exc_$signal$3[0:0]$319
15786     assign $0\exc_$signal$4[0:0]$310 $1\exc_$signal$4[0:0]$320
15787     assign $0\exc_$signal$5[0:0]$311 $1\exc_$signal$5[0:0]$321
15788     assign $0\exc_$signal$6[0:0]$312 $1\exc_$signal$6[0:0]$322
15789     assign $0\exc_$signal$7[0:0]$313 $1\exc_$signal$7[0:0]$323
15790     assign $0\exc_$signal$8[0:0]$314 $1\exc_$signal$8[0:0]$324
15791     assign $0\exc_$signal$9[0:0]$315 $1\exc_$signal$9[0:0]$325
15792     assign { } { }
15793     assign { } { }
15794     assign { } { }
15795     assign { } { }
15796     assign { } { }
15797     assign { } { }
15798     assign { } { }
15799     assign { } { }
15800     assign $0\fn_unit[11:0] $1\fn_unit[11:0]
15801     assign $0\input_carry[1:0] $1\input_carry[1:0]
15802     assign $0\insn[31:0] $1\insn[31:0]
15803     assign $0\insn_type[6:0] $1\insn_type[6:0]
15804     assign $0\is_32bit[0:0] $1\is_32bit[0:0]
15805     assign $0\msr[63:0] $1\msr[63:0]
15806     assign $0\oe[0:0] $1\oe[0:0]
15807     assign $0\oe_ok[0:0] $1\oe_ok[0:0]
15808     assign $0\rc[0:0] $1\rc[0:0]
15809     assign $0\rc_ok[0:0] $1\rc_ok[0:0]
15810     assign $0\reg1[4:0] $1\reg1[4:0]
15811     assign $0\reg1_ok[0:0] $1\reg1_ok[0:0]
15812     assign $0\reg2[4:0] $1\reg2[4:0]
15813     assign $0\reg2_ok[0:0] $1\reg2_ok[0:0]
15814     assign $0\reg3[4:0] $1\reg3[4:0]
15815     assign $0\reg3_ok[0:0] $1\reg3_ok[0:0]
15816     assign $0\rego[4:0] $1\rego[4:0]
15817     assign $0\rego_ok[0:0] $1\rego_ok[0:0]
15818     assign $0\spr1[9:0] $1\spr1[9:0]
15819     assign $0\spr1_ok[0:0] $1\spr1_ok[0:0]
15820     assign $0\spro[9:0] $1\spro[9:0]
15821     assign $0\spro_ok[0:0] $1\spro_ok[0:0]
15822     assign $0\trapaddr[12:0] $1\trapaddr[12:0]
15823     assign $0\traptype[7:0] $1\traptype[7:0]
15824     assign $0\xer_in[2:0] $1\xer_in[2:0]
15825     assign $0\xer_out[0:0] $1\xer_out[0:0]
15826     assign $0\fasto1[2:0] $5\fasto1[2:0]
15827     assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0]
15828     assign $0\fasto2[2:0] $5\fasto2[2:0]
15829     assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0]
15830     assign $0\fast1[2:0] $5\fast1[2:0]
15831     assign $0\fast1_ok[0:0] $5\fast1_ok[0:0]
15832     assign $0\fast2[2:0] $5\fast2[2:0]
15833     assign $0\fast2_ok[0:0] $5\fast2_ok[0:0]
15834     assign $0\asmcode[7:0] \dec_asmcode
15835     attribute \src "libresoc.v:10451.5-10451.29"
15836     switch \initial
15837       attribute \src "libresoc.v:10451.9-10451.17"
15838       case 1'1
15839       case
15840     end
15841     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916"
15842     switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal }
15843       attribute \src "libresoc.v:0.0-0.0"
15844       case 5'----1
15845         assign { } { }
15846         assign { } { }
15847         assign { } { }
15848         assign { } { }
15849         assign { } { }
15850         assign { } { }
15851         assign { } { }
15852         assign { } { }
15853         assign { } { }
15854         assign { } { }
15855         assign { } { }
15856         assign { } { }
15857         assign { } { }
15858         assign { } { }
15859         assign { } { }
15860         assign { } { }
15861         assign { } { }
15862         assign { } { }
15863         assign { } { }
15864         assign { } { }
15865         assign { } { }
15866         assign { } { }
15867         assign { } { }
15868         assign { } { }
15869         assign { } { }
15870         assign { } { }
15871         assign { } { }
15872         assign { } { }
15873         assign { } { }
15874         assign { } { }
15875         assign { } { }
15876         assign { } { }
15877         assign { } { }
15878         assign { } { }
15879         assign { } { }
15880         assign { } { }
15881         assign { } { }
15882         assign { } { }
15883         assign { } { }
15884         assign { } { }
15885         assign { } { }
15886         assign { } { }
15887         assign { } { }
15888         assign { } { }
15889         assign { } { }
15890         assign { } { }
15891         assign { } { }
15892         assign { } { }
15893         assign { } { }
15894         assign { } { }
15895         assign { } { }
15896         assign { } { }
15897         assign { } { }
15898         assign { } { }
15899         assign { } { }
15900         assign { } { }
15901         assign { } { }
15902         assign { } { }
15903         assign { } { }
15904         assign $1\asmcode[7:0] $2\asmcode[7:0]
15905         assign $1\cr_out[2:0] $2\cr_out[2:0]
15906         assign $1\lk[0:0] $2\lk[0:0]
15907         assign $1\cia[63:0] $2\cia[63:0]
15908         assign $1\cr_in1[2:0] $2\cr_in1[2:0]
15909         assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0]
15910         assign $1\cr_in2[2:0] $2\cr_in2[2:0]
15911         assign $1\cr_in2$1[2:0]$316 $2\cr_in2$1[2:0]$326
15912         assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0]
15913         assign $1\cr_in2_ok$2[0:0]$317 $2\cr_in2_ok$2[0:0]$327
15914         assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0]
15915         assign $1\cr_rd[7:0] $2\cr_rd[7:0]
15916         assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0]
15917         assign $1\cr_wr[7:0] $2\cr_wr[7:0]
15918         assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0]
15919         assign $1\ea[4:0] $2\ea[4:0]
15920         assign $1\ea_ok[0:0] $2\ea_ok[0:0]
15921         assign $1\exc_$signal[0:0]$318 $2\exc_$signal[0:0]$328
15922         assign $1\exc_$signal$3[0:0]$319 $2\exc_$signal$3[0:0]$329
15923         assign $1\exc_$signal$4[0:0]$320 $2\exc_$signal$4[0:0]$330
15924         assign $1\exc_$signal$5[0:0]$321 $2\exc_$signal$5[0:0]$331
15925         assign $1\exc_$signal$6[0:0]$322 $2\exc_$signal$6[0:0]$332
15926         assign $1\exc_$signal$7[0:0]$323 $2\exc_$signal$7[0:0]$333
15927         assign $1\exc_$signal$8[0:0]$324 $2\exc_$signal$8[0:0]$334
15928         assign $1\exc_$signal$9[0:0]$325 $2\exc_$signal$9[0:0]$335
15929         assign $1\fast1[2:0] $2\fast1[2:0]
15930         assign $1\fast1_ok[0:0] $2\fast1_ok[0:0]
15931         assign $1\fast2[2:0] $2\fast2[2:0]
15932         assign $1\fast2_ok[0:0] $2\fast2_ok[0:0]
15933         assign $1\fasto1[2:0] $2\fasto1[2:0]
15934         assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0]
15935         assign $1\fasto2[2:0] $2\fasto2[2:0]
15936         assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0]
15937         assign $1\fn_unit[11:0] $2\fn_unit[11:0]
15938         assign $1\input_carry[1:0] $2\input_carry[1:0]
15939         assign $1\insn[31:0] $2\insn[31:0]
15940         assign $1\insn_type[6:0] $2\insn_type[6:0]
15941         assign $1\is_32bit[0:0] $2\is_32bit[0:0]
15942         assign $1\msr[63:0] $2\msr[63:0]
15943         assign $1\oe[0:0] $2\oe[0:0]
15944         assign $1\oe_ok[0:0] $2\oe_ok[0:0]
15945         assign $1\rc[0:0] $2\rc[0:0]
15946         assign $1\rc_ok[0:0] $2\rc_ok[0:0]
15947         assign $1\reg1[4:0] $2\reg1[4:0]
15948         assign $1\reg1_ok[0:0] $2\reg1_ok[0:0]
15949         assign $1\reg2[4:0] $2\reg2[4:0]
15950         assign $1\reg2_ok[0:0] $2\reg2_ok[0:0]
15951         assign $1\reg3[4:0] $2\reg3[4:0]
15952         assign $1\reg3_ok[0:0] $2\reg3_ok[0:0]
15953         assign $1\rego[4:0] $2\rego[4:0]
15954         assign $1\rego_ok[0:0] $2\rego_ok[0:0]
15955         assign $1\spr1[9:0] $2\spr1[9:0]
15956         assign $1\spr1_ok[0:0] $2\spr1_ok[0:0]
15957         assign $1\spro[9:0] $2\spro[9:0]
15958         assign $1\spro_ok[0:0] $2\spro_ok[0:0]
15959         assign $1\trapaddr[12:0] $2\trapaddr[12:0]
15960         assign $1\traptype[7:0] $2\traptype[7:0]
15961         assign $1\xer_in[2:0] $2\xer_in[2:0]
15962         assign $1\xer_out[0:0] $2\xer_out[0:0]
15963         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917"
15964         switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 }
15965           attribute \src "libresoc.v:0.0-0.0"
15966           case 2'-1
15967             assign { } { }
15968             assign { } { }
15969             assign { } { }
15970             assign { } { }
15971             assign { } { }
15972             assign { } { }
15973             assign { } { }
15974             assign { } { }
15975             assign { } { }
15976             assign { } { }
15977             assign { } { }
15978             assign { } { }
15979             assign { } { }
15980             assign { } { }
15981             assign { } { }
15982             assign { } { }
15983             assign { } { }
15984             assign { } { }
15985             assign { } { }
15986             assign { } { }
15987             assign { } { }
15988             assign { } { }
15989             assign { } { }
15990             assign { } { }
15991             assign { } { }
15992             assign { } { }
15993             assign { } { }
15994             assign { } { }
15995             assign { } { }
15996             assign { } { }
15997             assign { } { }
15998             assign { } { }
15999             assign { } { }
16000             assign { } { }
16001             assign { } { }
16002             assign { } { }
16003             assign { } { }
16004             assign { } { }
16005             assign { } { }
16006             assign { } { }
16007             assign { } { }
16008             assign { } { }
16009             assign { } { }
16010             assign { } { }
16011             assign { } { }
16012             assign { } { }
16013             assign { } { }
16014             assign { } { }
16015             assign { } { }
16016             assign { } { }
16017             assign { } { }
16018             assign { } { }
16019             assign { } { }
16020             assign { } { }
16021             assign { } { }
16022             assign { } { }
16023             assign { } { }
16024             assign { } { }
16025             assign { } { }
16026             assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$335 $2\exc_$signal$8[0:0]$334 $2\exc_$signal$7[0:0]$333 $2\exc_$signal$6[0:0]$332 $2\exc_$signal$5[0:0]$331 $2\exc_$signal$4[0:0]$330 $2\exc_$signal$3[0:0]$329 $2\exc_$signal[0:0]$328 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$327 $2\cr_in2$1[2:0]$326 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16027             assign $2\insn[31:0] \dec_opcode_in
16028             assign $2\insn_type[6:0] 7'0111111
16029             assign $2\fn_unit[11:0] 12'000010000000
16030             assign $2\trapaddr[12:0] 13'0000001100000
16031             assign $2\traptype[7:0] 8'00000010
16032             assign $2\msr[63:0] \cur_msr
16033             assign $2\cia[63:0] \cur_pc
16034           attribute \src "libresoc.v:0.0-0.0"
16035           case 2'1-
16036             assign { } { }
16037             assign { } { }
16038             assign { } { }
16039             assign { } { }
16040             assign { } { }
16041             assign { } { }
16042             assign { } { }
16043             assign { } { }
16044             assign { } { }
16045             assign { } { }
16046             assign { } { }
16047             assign { } { }
16048             assign { } { }
16049             assign { } { }
16050             assign { } { }
16051             assign { } { }
16052             assign { } { }
16053             assign { } { }
16054             assign { } { }
16055             assign { } { }
16056             assign { } { }
16057             assign { } { }
16058             assign { } { }
16059             assign { } { }
16060             assign { } { }
16061             assign { } { }
16062             assign { } { }
16063             assign { } { }
16064             assign { } { }
16065             assign { } { }
16066             assign { } { }
16067             assign { } { }
16068             assign { } { }
16069             assign { } { }
16070             assign { } { }
16071             assign { } { }
16072             assign { } { }
16073             assign { } { }
16074             assign { } { }
16075             assign { } { }
16076             assign { } { }
16077             assign { } { }
16078             assign { } { }
16079             assign { } { }
16080             assign { } { }
16081             assign { } { }
16082             assign { } { }
16083             assign { } { }
16084             assign { } { }
16085             assign { } { }
16086             assign { } { }
16087             assign { } { }
16088             assign { } { }
16089             assign { } { }
16090             assign { } { }
16091             assign { } { }
16092             assign { } { }
16093             assign { } { }
16094             assign { } { }
16095             assign $2\asmcode[7:0] $3\asmcode[7:0]
16096             assign $2\cr_out[2:0] $3\cr_out[2:0]
16097             assign $2\lk[0:0] $3\lk[0:0]
16098             assign $2\cia[63:0] $3\cia[63:0]
16099             assign $2\cr_in1[2:0] $3\cr_in1[2:0]
16100             assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0]
16101             assign $2\cr_in2[2:0] $3\cr_in2[2:0]
16102             assign $2\cr_in2$1[2:0]$326 $3\cr_in2$1[2:0]$336
16103             assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0]
16104             assign $2\cr_in2_ok$2[0:0]$327 $3\cr_in2_ok$2[0:0]$337
16105             assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0]
16106             assign $2\cr_rd[7:0] $3\cr_rd[7:0]
16107             assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0]
16108             assign $2\cr_wr[7:0] $3\cr_wr[7:0]
16109             assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0]
16110             assign $2\ea[4:0] $3\ea[4:0]
16111             assign $2\ea_ok[0:0] $3\ea_ok[0:0]
16112             assign $2\exc_$signal[0:0]$328 $3\exc_$signal[0:0]$338
16113             assign $2\exc_$signal$3[0:0]$329 $3\exc_$signal$3[0:0]$339
16114             assign $2\exc_$signal$4[0:0]$330 $3\exc_$signal$4[0:0]$340
16115             assign $2\exc_$signal$5[0:0]$331 $3\exc_$signal$5[0:0]$341
16116             assign $2\exc_$signal$6[0:0]$332 $3\exc_$signal$6[0:0]$342
16117             assign $2\exc_$signal$7[0:0]$333 $3\exc_$signal$7[0:0]$343
16118             assign $2\exc_$signal$8[0:0]$334 $3\exc_$signal$8[0:0]$344
16119             assign $2\exc_$signal$9[0:0]$335 $3\exc_$signal$9[0:0]$345
16120             assign $2\fast1[2:0] $3\fast1[2:0]
16121             assign $2\fast1_ok[0:0] $3\fast1_ok[0:0]
16122             assign $2\fast2[2:0] $3\fast2[2:0]
16123             assign $2\fast2_ok[0:0] $3\fast2_ok[0:0]
16124             assign $2\fasto1[2:0] $3\fasto1[2:0]
16125             assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0]
16126             assign $2\fasto2[2:0] $3\fasto2[2:0]
16127             assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0]
16128             assign $2\fn_unit[11:0] $3\fn_unit[11:0]
16129             assign $2\input_carry[1:0] $3\input_carry[1:0]
16130             assign $2\insn[31:0] $3\insn[31:0]
16131             assign $2\insn_type[6:0] $3\insn_type[6:0]
16132             assign $2\is_32bit[0:0] $3\is_32bit[0:0]
16133             assign $2\msr[63:0] $3\msr[63:0]
16134             assign $2\oe[0:0] $3\oe[0:0]
16135             assign $2\oe_ok[0:0] $3\oe_ok[0:0]
16136             assign $2\rc[0:0] $3\rc[0:0]
16137             assign $2\rc_ok[0:0] $3\rc_ok[0:0]
16138             assign $2\reg1[4:0] $3\reg1[4:0]
16139             assign $2\reg1_ok[0:0] $3\reg1_ok[0:0]
16140             assign $2\reg2[4:0] $3\reg2[4:0]
16141             assign $2\reg2_ok[0:0] $3\reg2_ok[0:0]
16142             assign $2\reg3[4:0] $3\reg3[4:0]
16143             assign $2\reg3_ok[0:0] $3\reg3_ok[0:0]
16144             assign $2\rego[4:0] $3\rego[4:0]
16145             assign $2\rego_ok[0:0] $3\rego_ok[0:0]
16146             assign $2\spr1[9:0] $3\spr1[9:0]
16147             assign $2\spr1_ok[0:0] $3\spr1_ok[0:0]
16148             assign $2\spro[9:0] $3\spro[9:0]
16149             assign $2\spro_ok[0:0] $3\spro_ok[0:0]
16150             assign $2\trapaddr[12:0] $3\trapaddr[12:0]
16151             assign $2\traptype[7:0] $3\traptype[7:0]
16152             assign $2\xer_in[2:0] $3\xer_in[2:0]
16153             assign $2\xer_out[0:0] $3\xer_out[0:0]
16154             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920"
16155             switch \dec2_exc_$signal$14
16156               attribute \src "libresoc.v:0.0-0.0"
16157               case 1'1
16158                 assign { } { }
16159                 assign { } { }
16160                 assign { } { }
16161                 assign { } { }
16162                 assign { } { }
16163                 assign { } { }
16164                 assign { } { }
16165                 assign { } { }
16166                 assign { } { }
16167                 assign { } { }
16168                 assign { } { }
16169                 assign { } { }
16170                 assign { } { }
16171                 assign { } { }
16172                 assign { } { }
16173                 assign { } { }
16174                 assign { } { }
16175                 assign { } { }
16176                 assign { } { }
16177                 assign { } { }
16178                 assign { } { }
16179                 assign { } { }
16180                 assign { } { }
16181                 assign { } { }
16182                 assign { } { }
16183                 assign { } { }
16184                 assign { } { }
16185                 assign { } { }
16186                 assign { } { }
16187                 assign { } { }
16188                 assign { } { }
16189                 assign { } { }
16190                 assign { } { }
16191                 assign { } { }
16192                 assign { } { }
16193                 assign { } { }
16194                 assign { } { }
16195                 assign { } { }
16196                 assign { } { }
16197                 assign { } { }
16198                 assign { } { }
16199                 assign { } { }
16200                 assign { } { }
16201                 assign { } { }
16202                 assign { } { }
16203                 assign { } { }
16204                 assign { } { }
16205                 assign { } { }
16206                 assign { } { }
16207                 assign { } { }
16208                 assign { } { }
16209                 assign { } { }
16210                 assign { } { }
16211                 assign { } { }
16212                 assign { } { }
16213                 assign { } { }
16214                 assign { } { }
16215                 assign { } { }
16216                 assign { } { }
16217                 assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16218                 assign $3\insn[31:0] \dec_opcode_in
16219                 assign $3\insn_type[6:0] 7'0111111
16220                 assign $3\fn_unit[11:0] 12'000010000000
16221                 assign $3\trapaddr[12:0] 13'0000001001000
16222                 assign $3\traptype[7:0] 8'00000010
16223                 assign $3\msr[63:0] \cur_msr
16224                 assign $3\cia[63:0] \cur_pc
16225               attribute \src "libresoc.v:0.0-0.0"
16226               case
16227                 assign { } { }
16228                 assign { } { }
16229                 assign { } { }
16230                 assign { } { }
16231                 assign { } { }
16232                 assign { } { }
16233                 assign { } { }
16234                 assign { } { }
16235                 assign { } { }
16236                 assign { } { }
16237                 assign { } { }
16238                 assign { } { }
16239                 assign { } { }
16240                 assign { } { }
16241                 assign { } { }
16242                 assign { } { }
16243                 assign { } { }
16244                 assign { } { }
16245                 assign { } { }
16246                 assign { } { }
16247                 assign { } { }
16248                 assign { } { }
16249                 assign { } { }
16250                 assign { } { }
16251                 assign { } { }
16252                 assign { } { }
16253                 assign { } { }
16254                 assign { } { }
16255                 assign { } { }
16256                 assign { } { }
16257                 assign { } { }
16258                 assign { } { }
16259                 assign { } { }
16260                 assign { } { }
16261                 assign { } { }
16262                 assign { } { }
16263                 assign { } { }
16264                 assign { } { }
16265                 assign { } { }
16266                 assign { } { }
16267                 assign { } { }
16268                 assign { } { }
16269                 assign { } { }
16270                 assign { } { }
16271                 assign { } { }
16272                 assign { } { }
16273                 assign { } { }
16274                 assign { } { }
16275                 assign { } { }
16276                 assign { } { }
16277                 assign { } { }
16278                 assign { } { }
16279                 assign { } { }
16280                 assign { } { }
16281                 assign { } { }
16282                 assign { } { }
16283                 assign { } { }
16284                 assign { } { }
16285                 assign { } { }
16286                 assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16287                 assign $3\insn[31:0] \dec_opcode_in
16288                 assign $3\insn_type[6:0] 7'0111111
16289                 assign $3\fn_unit[11:0] 12'000010000000
16290                 assign $3\trapaddr[12:0] 13'0000001000000
16291                 assign $3\traptype[7:0] 8'01000000
16292                 assign { $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal }
16293                 assign $3\msr[63:0] \cur_msr
16294                 assign $3\cia[63:0] \cur_pc
16295             end
16296           attribute \src "libresoc.v:0.0-0.0"
16297           case
16298             assign { } { }
16299             assign { } { }
16300             assign { } { }
16301             assign { } { }
16302             assign { } { }
16303             assign { } { }
16304             assign { } { }
16305             assign { } { }
16306             assign { } { }
16307             assign { } { }
16308             assign { } { }
16309             assign { } { }
16310             assign { } { }
16311             assign { } { }
16312             assign { } { }
16313             assign { } { }
16314             assign { } { }
16315             assign { } { }
16316             assign { } { }
16317             assign { } { }
16318             assign { } { }
16319             assign { } { }
16320             assign { } { }
16321             assign { } { }
16322             assign { } { }
16323             assign { } { }
16324             assign { } { }
16325             assign { } { }
16326             assign { } { }
16327             assign { } { }
16328             assign { } { }
16329             assign { } { }
16330             assign { } { }
16331             assign { } { }
16332             assign { } { }
16333             assign { } { }
16334             assign { } { }
16335             assign { } { }
16336             assign { } { }
16337             assign { } { }
16338             assign { } { }
16339             assign { } { }
16340             assign { } { }
16341             assign { } { }
16342             assign { } { }
16343             assign { } { }
16344             assign { } { }
16345             assign { } { }
16346             assign { } { }
16347             assign { } { }
16348             assign { } { }
16349             assign { } { }
16350             assign { } { }
16351             assign { } { }
16352             assign { } { }
16353             assign { } { }
16354             assign { } { }
16355             assign { } { }
16356             assign { } { }
16357             assign $2\asmcode[7:0] $4\asmcode[7:0]
16358             assign $2\cr_out[2:0] $4\cr_out[2:0]
16359             assign $2\lk[0:0] $4\lk[0:0]
16360             assign $2\cia[63:0] $4\cia[63:0]
16361             assign $2\cr_in1[2:0] $4\cr_in1[2:0]
16362             assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0]
16363             assign $2\cr_in2[2:0] $4\cr_in2[2:0]
16364             assign $2\cr_in2$1[2:0]$326 $4\cr_in2$1[2:0]$346
16365             assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0]
16366             assign $2\cr_in2_ok$2[0:0]$327 $4\cr_in2_ok$2[0:0]$347
16367             assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0]
16368             assign $2\cr_rd[7:0] $4\cr_rd[7:0]
16369             assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0]
16370             assign $2\cr_wr[7:0] $4\cr_wr[7:0]
16371             assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0]
16372             assign $2\ea[4:0] $4\ea[4:0]
16373             assign $2\ea_ok[0:0] $4\ea_ok[0:0]
16374             assign $2\exc_$signal[0:0]$328 $4\exc_$signal[0:0]$348
16375             assign $2\exc_$signal$3[0:0]$329 $4\exc_$signal$3[0:0]$349
16376             assign $2\exc_$signal$4[0:0]$330 $4\exc_$signal$4[0:0]$350
16377             assign $2\exc_$signal$5[0:0]$331 $4\exc_$signal$5[0:0]$351
16378             assign $2\exc_$signal$6[0:0]$332 $4\exc_$signal$6[0:0]$352
16379             assign $2\exc_$signal$7[0:0]$333 $4\exc_$signal$7[0:0]$353
16380             assign $2\exc_$signal$8[0:0]$334 $4\exc_$signal$8[0:0]$354
16381             assign $2\exc_$signal$9[0:0]$335 $4\exc_$signal$9[0:0]$355
16382             assign $2\fast1[2:0] $4\fast1[2:0]
16383             assign $2\fast1_ok[0:0] $4\fast1_ok[0:0]
16384             assign $2\fast2[2:0] $4\fast2[2:0]
16385             assign $2\fast2_ok[0:0] $4\fast2_ok[0:0]
16386             assign $2\fasto1[2:0] $4\fasto1[2:0]
16387             assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0]
16388             assign $2\fasto2[2:0] $4\fasto2[2:0]
16389             assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0]
16390             assign $2\fn_unit[11:0] $4\fn_unit[11:0]
16391             assign $2\input_carry[1:0] $4\input_carry[1:0]
16392             assign $2\insn[31:0] $4\insn[31:0]
16393             assign $2\insn_type[6:0] $4\insn_type[6:0]
16394             assign $2\is_32bit[0:0] $4\is_32bit[0:0]
16395             assign $2\msr[63:0] $4\msr[63:0]
16396             assign $2\oe[0:0] $4\oe[0:0]
16397             assign $2\oe_ok[0:0] $4\oe_ok[0:0]
16398             assign $2\rc[0:0] $4\rc[0:0]
16399             assign $2\rc_ok[0:0] $4\rc_ok[0:0]
16400             assign $2\reg1[4:0] $4\reg1[4:0]
16401             assign $2\reg1_ok[0:0] $4\reg1_ok[0:0]
16402             assign $2\reg2[4:0] $4\reg2[4:0]
16403             assign $2\reg2_ok[0:0] $4\reg2_ok[0:0]
16404             assign $2\reg3[4:0] $4\reg3[4:0]
16405             assign $2\reg3_ok[0:0] $4\reg3_ok[0:0]
16406             assign $2\rego[4:0] $4\rego[4:0]
16407             assign $2\rego_ok[0:0] $4\rego_ok[0:0]
16408             assign $2\spr1[9:0] $4\spr1[9:0]
16409             assign $2\spr1_ok[0:0] $4\spr1_ok[0:0]
16410             assign $2\spro[9:0] $4\spro[9:0]
16411             assign $2\spro_ok[0:0] $4\spro_ok[0:0]
16412             assign $2\trapaddr[12:0] $4\trapaddr[12:0]
16413             assign $2\traptype[7:0] $4\traptype[7:0]
16414             assign $2\xer_in[2:0] $4\xer_in[2:0]
16415             assign $2\xer_out[0:0] $4\xer_out[0:0]
16416             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926"
16417             switch \dec2_exc_$signal$14
16418               attribute \src "libresoc.v:0.0-0.0"
16419               case 1'1
16420                 assign { } { }
16421                 assign { } { }
16422                 assign { } { }
16423                 assign { } { }
16424                 assign { } { }
16425                 assign { } { }
16426                 assign { } { }
16427                 assign { } { }
16428                 assign { } { }
16429                 assign { } { }
16430                 assign { } { }
16431                 assign { } { }
16432                 assign { } { }
16433                 assign { } { }
16434                 assign { } { }
16435                 assign { } { }
16436                 assign { } { }
16437                 assign { } { }
16438                 assign { } { }
16439                 assign { } { }
16440                 assign { } { }
16441                 assign { } { }
16442                 assign { } { }
16443                 assign { } { }
16444                 assign { } { }
16445                 assign { } { }
16446                 assign { } { }
16447                 assign { } { }
16448                 assign { } { }
16449                 assign { } { }
16450                 assign { } { }
16451                 assign { } { }
16452                 assign { } { }
16453                 assign { } { }
16454                 assign { } { }
16455                 assign { } { }
16456                 assign { } { }
16457                 assign { } { }
16458                 assign { } { }
16459                 assign { } { }
16460                 assign { } { }
16461                 assign { } { }
16462                 assign { } { }
16463                 assign { } { }
16464                 assign { } { }
16465                 assign { } { }
16466                 assign { } { }
16467                 assign { } { }
16468                 assign { } { }
16469                 assign { } { }
16470                 assign { } { }
16471                 assign { } { }
16472                 assign { } { }
16473                 assign { } { }
16474                 assign { } { }
16475                 assign { } { }
16476                 assign { } { }
16477                 assign { } { }
16478                 assign { } { }
16479                 assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16480                 assign $4\insn[31:0] \dec_opcode_in
16481                 assign $4\insn_type[6:0] 7'0111111
16482                 assign $4\fn_unit[11:0] 12'000010000000
16483                 assign $4\trapaddr[12:0] 13'0000000111000
16484                 assign $4\traptype[7:0] 8'00000010
16485                 assign $4\msr[63:0] \cur_msr
16486                 assign $4\cia[63:0] \cur_pc
16487               attribute \src "libresoc.v:0.0-0.0"
16488               case
16489                 assign { } { }
16490                 assign { } { }
16491                 assign { } { }
16492                 assign { } { }
16493                 assign { } { }
16494                 assign { } { }
16495                 assign { } { }
16496                 assign { } { }
16497                 assign { } { }
16498                 assign { } { }
16499                 assign { } { }
16500                 assign { } { }
16501                 assign { } { }
16502                 assign { } { }
16503                 assign { } { }
16504                 assign { } { }
16505                 assign { } { }
16506                 assign { } { }
16507                 assign { } { }
16508                 assign { } { }
16509                 assign { } { }
16510                 assign { } { }
16511                 assign { } { }
16512                 assign { } { }
16513                 assign { } { }
16514                 assign { } { }
16515                 assign { } { }
16516                 assign { } { }
16517                 assign { } { }
16518                 assign { } { }
16519                 assign { } { }
16520                 assign { } { }
16521                 assign { } { }
16522                 assign { } { }
16523                 assign { } { }
16524                 assign { } { }
16525                 assign { } { }
16526                 assign { } { }
16527                 assign { } { }
16528                 assign { } { }
16529                 assign { } { }
16530                 assign { } { }
16531                 assign { } { }
16532                 assign { } { }
16533                 assign { } { }
16534                 assign { } { }
16535                 assign { } { }
16536                 assign { } { }
16537                 assign { } { }
16538                 assign { } { }
16539                 assign { } { }
16540                 assign { } { }
16541                 assign { } { }
16542                 assign { } { }
16543                 assign { } { }
16544                 assign { } { }
16545                 assign { } { }
16546                 assign { } { }
16547                 assign { } { }
16548                 assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16549                 assign $4\insn[31:0] \dec_opcode_in
16550                 assign $4\insn_type[6:0] 7'0111111
16551                 assign $4\fn_unit[11:0] 12'000010000000
16552                 assign $4\trapaddr[12:0] 13'0000000110000
16553                 assign $4\traptype[7:0] 8'00000010
16554                 assign $4\msr[63:0] \cur_msr
16555                 assign $4\cia[63:0] \cur_pc
16556             end
16557         end
16558       attribute \src "libresoc.v:0.0-0.0"
16559       case 5'---1-
16560         assign { } { }
16561         assign { } { }
16562         assign { } { }
16563         assign { } { }
16564         assign { } { }
16565         assign { } { }
16566         assign { } { }
16567         assign { } { }
16568         assign { } { }
16569         assign { } { }
16570         assign { } { }
16571         assign { } { }
16572         assign { } { }
16573         assign { } { }
16574         assign { } { }
16575         assign { } { }
16576         assign { } { }
16577         assign { } { }
16578         assign { } { }
16579         assign { } { }
16580         assign { } { }
16581         assign { } { }
16582         assign { } { }
16583         assign { } { }
16584         assign { } { }
16585         assign { } { }
16586         assign { } { }
16587         assign { } { }
16588         assign { } { }
16589         assign { } { }
16590         assign { } { }
16591         assign { } { }
16592         assign { } { }
16593         assign { } { }
16594         assign { } { }
16595         assign { } { }
16596         assign { } { }
16597         assign { } { }
16598         assign { } { }
16599         assign { } { }
16600         assign { } { }
16601         assign { } { }
16602         assign { } { }
16603         assign { } { }
16604         assign { } { }
16605         assign { } { }
16606         assign { } { }
16607         assign { } { }
16608         assign { } { }
16609         assign { } { }
16610         assign { } { }
16611         assign { } { }
16612         assign { } { }
16613         assign { } { }
16614         assign { } { }
16615         assign { } { }
16616         assign { } { }
16617         assign { } { }
16618         assign { } { }
16619         assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16620         assign $1\insn[31:0] \dec_opcode_in
16621         assign $1\insn_type[6:0] 7'0111111
16622         assign $1\fn_unit[11:0] 12'000010000000
16623         assign $1\trapaddr[12:0] 13'0000010010000
16624         assign $1\traptype[7:0] 8'00100000
16625         assign $1\msr[63:0] \cur_msr
16626         assign $1\cia[63:0] \cur_pc
16627       attribute \src "libresoc.v:0.0-0.0"
16628       case 5'--1--
16629         assign { } { }
16630         assign { } { }
16631         assign { } { }
16632         assign { } { }
16633         assign { } { }
16634         assign { } { }
16635         assign { } { }
16636         assign { } { }
16637         assign { } { }
16638         assign { } { }
16639         assign { } { }
16640         assign { } { }
16641         assign { } { }
16642         assign { } { }
16643         assign { } { }
16644         assign { } { }
16645         assign { } { }
16646         assign { } { }
16647         assign { } { }
16648         assign { } { }
16649         assign { } { }
16650         assign { } { }
16651         assign { } { }
16652         assign { } { }
16653         assign { } { }
16654         assign { } { }
16655         assign { } { }
16656         assign { } { }
16657         assign { } { }
16658         assign { } { }
16659         assign { } { }
16660         assign { } { }
16661         assign { } { }
16662         assign { } { }
16663         assign { } { }
16664         assign { } { }
16665         assign { } { }
16666         assign { } { }
16667         assign { } { }
16668         assign { } { }
16669         assign { } { }
16670         assign { } { }
16671         assign { } { }
16672         assign { } { }
16673         assign { } { }
16674         assign { } { }
16675         assign { } { }
16676         assign { } { }
16677         assign { } { }
16678         assign { } { }
16679         assign { } { }
16680         assign { } { }
16681         assign { } { }
16682         assign { } { }
16683         assign { } { }
16684         assign { } { }
16685         assign { } { }
16686         assign { } { }
16687         assign { } { }
16688         assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16689         assign $1\insn[31:0] \dec_opcode_in
16690         assign $1\insn_type[6:0] 7'0111111
16691         assign $1\fn_unit[11:0] 12'000010000000
16692         assign $1\trapaddr[12:0] 13'0000001010000
16693         assign $1\traptype[7:0] 8'00010000
16694         assign $1\msr[63:0] \cur_msr
16695         assign $1\cia[63:0] \cur_pc
16696       attribute \src "libresoc.v:0.0-0.0"
16697       case 5'-1---
16698         assign { } { }
16699         assign { } { }
16700         assign { } { }
16701         assign { } { }
16702         assign { } { }
16703         assign { } { }
16704         assign { } { }
16705         assign { } { }
16706         assign { } { }
16707         assign { } { }
16708         assign { } { }
16709         assign { } { }
16710         assign { } { }
16711         assign { } { }
16712         assign { } { }
16713         assign { } { }
16714         assign { } { }
16715         assign { } { }
16716         assign { } { }
16717         assign { } { }
16718         assign { } { }
16719         assign { } { }
16720         assign { } { }
16721         assign { } { }
16722         assign { } { }
16723         assign { } { }
16724         assign { } { }
16725         assign { } { }
16726         assign { } { }
16727         assign { } { }
16728         assign { } { }
16729         assign { } { }
16730         assign { } { }
16731         assign { } { }
16732         assign { } { }
16733         assign { } { }
16734         assign { } { }
16735         assign { } { }
16736         assign { } { }
16737         assign { } { }
16738         assign { } { }
16739         assign { } { }
16740         assign { } { }
16741         assign { } { }
16742         assign { } { }
16743         assign { } { }
16744         assign { } { }
16745         assign { } { }
16746         assign { } { }
16747         assign { } { }
16748         assign { } { }
16749         assign { } { }
16750         assign { } { }
16751         assign { } { }
16752         assign { } { }
16753         assign { } { }
16754         assign { } { }
16755         assign { } { }
16756         assign { } { }
16757         assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16758         assign $1\insn[31:0] \dec_opcode_in
16759         assign $1\insn_type[6:0] 7'0111111
16760         assign $1\fn_unit[11:0] 12'000010000000
16761         assign $1\trapaddr[12:0] 13'0000001110000
16762         assign $1\traptype[7:0] 8'00000010
16763         assign $1\msr[63:0] \cur_msr
16764         assign $1\cia[63:0] \cur_pc
16765       attribute \src "libresoc.v:0.0-0.0"
16766       case 5'1----
16767         assign { } { }
16768         assign { } { }
16769         assign { } { }
16770         assign { } { }
16771         assign { } { }
16772         assign { } { }
16773         assign { } { }
16774         assign { } { }
16775         assign { } { }
16776         assign { } { }
16777         assign { } { }
16778         assign { } { }
16779         assign { } { }
16780         assign { } { }
16781         assign { } { }
16782         assign { } { }
16783         assign { } { }
16784         assign { } { }
16785         assign { } { }
16786         assign { } { }
16787         assign { } { }
16788         assign { } { }
16789         assign { } { }
16790         assign { } { }
16791         assign { } { }
16792         assign { } { }
16793         assign { } { }
16794         assign { } { }
16795         assign { } { }
16796         assign { } { }
16797         assign { } { }
16798         assign { } { }
16799         assign { } { }
16800         assign { } { }
16801         assign { } { }
16802         assign { } { }
16803         assign { } { }
16804         assign { } { }
16805         assign { } { }
16806         assign { } { }
16807         assign { } { }
16808         assign { } { }
16809         assign { } { }
16810         assign { } { }
16811         assign { } { }
16812         assign { } { }
16813         assign { } { }
16814         assign { } { }
16815         assign { } { }
16816         assign { } { }
16817         assign { } { }
16818         assign { } { }
16819         assign { } { }
16820         assign { } { }
16821         assign { } { }
16822         assign { } { }
16823         assign { } { }
16824         assign { } { }
16825         assign { } { }
16826         assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
16827         assign $1\insn[31:0] \dec_opcode_in
16828         assign $1\insn_type[6:0] 7'0111111
16829         assign $1\fn_unit[11:0] 12'000010000000
16830         assign $1\trapaddr[12:0] 13'0000001110000
16831         assign $1\traptype[7:0] 8'10000000
16832         assign $1\msr[63:0] \cur_msr
16833         assign $1\cia[63:0] \cur_pc
16834       attribute \src "libresoc.v:0.0-0.0"
16835       case
16836         assign { } { }
16837         assign { } { }
16838         assign { } { }
16839         assign { } { }
16840         assign { } { }
16841         assign { } { }
16842         assign { } { }
16843         assign { } { }
16844         assign { } { }
16845         assign { } { }
16846         assign { } { }
16847         assign { } { }
16848         assign { } { }
16849         assign { } { }
16850         assign { } { }
16851         assign { } { }
16852         assign { } { }
16853         assign { } { }
16854         assign { } { }
16855         assign { } { }
16856         assign { } { }
16857         assign { } { }
16858         assign { } { }
16859         assign { } { }
16860         assign { } { }
16861         assign { } { }
16862         assign { } { }
16863         assign { } { }
16864         assign { } { }
16865         assign { } { }
16866         assign { } { }
16867         assign { } { }
16868         assign { } { }
16869         assign { } { }
16870         assign { } { }
16871         assign { } { }
16872         assign { } { }
16873         assign { } { }
16874         assign { } { }
16875         assign { } { }
16876         assign { } { }
16877         assign { } { }
16878         assign { } { }
16879         assign { } { }
16880         assign { } { }
16881         assign { } { }
16882         assign { } { }
16883         assign { } { }
16884         assign { } { }
16885         assign { } { }
16886         assign { } { }
16887         assign { } { }
16888         assign { } { }
16889         assign { } { }
16890         assign { } { }
16891         assign { } { }
16892         assign { } { }
16893         assign { } { }
16894         assign { } { }
16895         assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
16896     end
16897     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961"
16898     switch \$32
16899       attribute \src "libresoc.v:0.0-0.0"
16900       case 1'1
16901         assign { } { }
16902         assign { } { }
16903         assign { } { }
16904         assign { } { }
16905         assign $5\fasto1[2:0] 3'011
16906         assign $5\fasto1_ok[0:0] 1'1
16907         assign $5\fasto2[2:0] 3'100
16908         assign $5\fasto2_ok[0:0] 1'1
16909       case
16910         assign $5\fasto1[2:0] $1\fasto1[2:0]
16911         assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0]
16912         assign $5\fasto2[2:0] $1\fasto2[2:0]
16913         assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0]
16914     end
16915     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970"
16916     switch \$34
16917       attribute \src "libresoc.v:0.0-0.0"
16918       case 1'1
16919         assign { } { }
16920         assign { } { }
16921         assign { } { }
16922         assign { } { }
16923         assign $5\fast1[2:0] 3'011
16924         assign $5\fast1_ok[0:0] 1'1
16925         assign $5\fast2[2:0] 3'100
16926         assign $5\fast2_ok[0:0] 1'1
16927       case
16928         assign $5\fast1[2:0] $1\fast1[2:0]
16929         assign $5\fast1_ok[0:0] $1\fast1_ok[0:0]
16930         assign $5\fast2[2:0] $1\fast2[2:0]
16931         assign $5\fast2_ok[0:0] $1\fast2_ok[0:0]
16932     end
16933     sync always
16934       update \asmcode $0\asmcode[7:0]
16935       update \cr_out $0\cr_out[2:0]
16936       update \lk $0\lk[0:0]
16937       update \cia $0\cia[63:0]
16938       update \cr_in1 $0\cr_in1[2:0]
16939       update \cr_in1_ok $0\cr_in1_ok[0:0]
16940       update \cr_in2 $0\cr_in2[2:0]
16941       update \cr_in2$1 $0\cr_in2$1[2:0]$306
16942       update \cr_in2_ok $0\cr_in2_ok[0:0]
16943       update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$307
16944       update \cr_out_ok $0\cr_out_ok[0:0]
16945       update \cr_rd $0\cr_rd[7:0]
16946       update \cr_rd_ok $0\cr_rd_ok[0:0]
16947       update \cr_wr $0\cr_wr[7:0]
16948       update \cr_wr_ok $0\cr_wr_ok[0:0]
16949       update \ea $0\ea[4:0]
16950       update \ea_ok $0\ea_ok[0:0]
16951       update \exc_$signal $0\exc_$signal[0:0]$308
16952       update \exc_$signal$3 $0\exc_$signal$3[0:0]$309
16953       update \exc_$signal$4 $0\exc_$signal$4[0:0]$310
16954       update \exc_$signal$5 $0\exc_$signal$5[0:0]$311
16955       update \exc_$signal$6 $0\exc_$signal$6[0:0]$312
16956       update \exc_$signal$7 $0\exc_$signal$7[0:0]$313
16957       update \exc_$signal$8 $0\exc_$signal$8[0:0]$314
16958       update \exc_$signal$9 $0\exc_$signal$9[0:0]$315
16959       update \fast1 $0\fast1[2:0]
16960       update \fast1_ok $0\fast1_ok[0:0]
16961       update \fast2 $0\fast2[2:0]
16962       update \fast2_ok $0\fast2_ok[0:0]
16963       update \fasto1 $0\fasto1[2:0]
16964       update \fasto1_ok $0\fasto1_ok[0:0]
16965       update \fasto2 $0\fasto2[2:0]
16966       update \fasto2_ok $0\fasto2_ok[0:0]
16967       update \fn_unit $0\fn_unit[11:0]
16968       update \input_carry $0\input_carry[1:0]
16969       update \insn $0\insn[31:0]
16970       update \insn_type $0\insn_type[6:0]
16971       update \is_32bit $0\is_32bit[0:0]
16972       update \msr $0\msr[63:0]
16973       update \oe $0\oe[0:0]
16974       update \oe_ok $0\oe_ok[0:0]
16975       update \rc $0\rc[0:0]
16976       update \rc_ok $0\rc_ok[0:0]
16977       update \reg1 $0\reg1[4:0]
16978       update \reg1_ok $0\reg1_ok[0:0]
16979       update \reg2 $0\reg2[4:0]
16980       update \reg2_ok $0\reg2_ok[0:0]
16981       update \reg3 $0\reg3[4:0]
16982       update \reg3_ok $0\reg3_ok[0:0]
16983       update \rego $0\rego[4:0]
16984       update \rego_ok $0\rego_ok[0:0]
16985       update \spr1 $0\spr1[9:0]
16986       update \spr1_ok $0\spr1_ok[0:0]
16987       update \spro $0\spro[9:0]
16988       update \spro_ok $0\spro_ok[0:0]
16989       update \trapaddr $0\trapaddr[12:0]
16990       update \traptype $0\traptype[7:0]
16991       update \xer_in $0\xer_in[2:0]
16992       update \xer_out $0\xer_out[0:0]
16993   end
16994   attribute \src "libresoc.v:8640.7-8640.20"
16995   process $proc$libresoc.v:8640$356
16996     assign { } { }
16997     assign $0\initial[0:0] 1'0
16998     sync always
16999       update \initial $0\initial[0:0]
17000     sync init
17001   end
17002   connect \$28 $eq$libresoc.v:10231$288_Y
17003   connect \$30 $eq$libresoc.v:10232$289_Y
17004   connect \$32 $or$libresoc.v:10233$290_Y
17005   connect \$34 $eq$libresoc.v:10234$291_Y
17006   connect \$42 $eq$libresoc.v:10235$292_Y
17007   connect \$44 $eq$libresoc.v:10236$293_Y
17008   connect \$46 $eq$libresoc.v:10237$294_Y
17009   connect \$48 $eq$libresoc.v:10238$295_Y
17010   connect \$50 $and$libresoc.v:10239$296_Y
17011   connect \$52 $and$libresoc.v:10240$297_Y
17012   connect \$54 $and$libresoc.v:10241$298_Y
17013   connect \$56 $eq$libresoc.v:10242$299_Y
17014   connect \dec2_exc_$signal 1'0
17015   connect \dec2_exc_$signal$12 1'0
17016   connect \dec2_exc_$signal$13 1'0
17017   connect \dec2_exc_$signal$14 1'0
17018   connect \dec2_exc_$signal$15 1'0
17019   connect \dec2_exc_$signal$16 1'0
17020   connect \dec2_exc_$signal$17 1'0
17021   connect \dec2_exc_$signal$18 1'0
17022   connect \tmp_asmcode 8'00000000
17023   connect \tmp_tmp_traptype 8'00000000
17024   connect \tmp_tmp_exc_$signal 1'0
17025   connect \tmp_tmp_exc_$signal$21 1'0
17026   connect \tmp_tmp_exc_$signal$22 1'0
17027   connect \tmp_tmp_exc_$signal$23 1'0
17028   connect \tmp_tmp_exc_$signal$24 1'0
17029   connect \tmp_tmp_exc_$signal$25 1'0
17030   connect \tmp_tmp_exc_$signal$26 1'0
17031   connect \tmp_tmp_exc_$signal$27 1'0
17032   connect \illeg_ok \$56
17033   connect \priv_ok \$54
17034   connect \dec_irq_ok \$52
17035   connect \ext_irq_ok \$50
17036   connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield }
17037   connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o }
17038   connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b }
17039   connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield }
17040   connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o }
17041   connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o }
17042   connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b }
17043   connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a }
17044   connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o }
17045   connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a }
17046   connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o }
17047   connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o }
17048   connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c }
17049   connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b }
17050   connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a }
17051   connect \dec_o2_lk \tmp_tmp_lk
17052   connect \sel_in \dec_out_sel
17053   connect \dec_o_sel_in \dec_out_sel
17054   connect \dec_c_sel_in \dec_in3_sel
17055   connect \dec_b_sel_in \dec_in2_sel
17056   connect \dec_a_sel_in \dec_in1_sel
17057   connect \insn_in$41 \dec_opcode_in
17058   connect \insn_in$40 \dec_opcode_in
17059   connect \insn_in$39 \dec_opcode_in
17060   connect \insn_in$38 \dec_opcode_in
17061   connect \insn_in$37 \dec_opcode_in
17062   connect \tmp_tmp_insn \dec_opcode_in
17063   connect \tmp_tmp_is_32bit \dec_is_32b
17064   connect \tmp_tmp_input_carry \dec_cry_in
17065   connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm }
17066   connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm }
17067   connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe }
17068   connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc }
17069   connect \tmp_tmp_fn_unit \dec_function_unit
17070   connect \tmp_tmp_insn_type \dec_internal_op
17071   connect \tmp_tmp_cia \cur_pc
17072   connect \tmp_tmp_msr \cur_msr
17073   connect \dec_cr_out_rc_in \dec_rc_rc
17074   connect \dec_cr_out_sel_in \dec_cr_out
17075   connect \dec_cr_in_sel_in \dec_cr_in
17076   connect \dec_oe_sel_in \dec_rc_sel
17077   connect \dec_rc_sel_in \dec_rc_sel
17078   connect \dec_cr_out_insn_in \dec_opcode_in
17079   connect \dec_cr_in_insn_in \dec_opcode_in
17080   connect \insn_in$36 \dec_opcode_in
17081   connect \insn_in \dec_opcode_in
17082 end
17083 attribute \src "libresoc.v:10680.1-11827.10"
17084 attribute \cells_not_processed 1
17085 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30"
17086 attribute \generator "nMigen"
17087 module \dec30
17088   attribute \src "libresoc.v:11123.3-11159.6"
17089   wire width 8 $0\dec30_asmcode[7:0]
17090   attribute \src "libresoc.v:11271.3-11307.6"
17091   wire $0\dec30_br[0:0]
17092   attribute \src "libresoc.v:11752.3-11788.6"
17093   wire width 3 $0\dec30_cr_in[2:0]
17094   attribute \src "libresoc.v:11789.3-11825.6"
17095   wire width 3 $0\dec30_cr_out[2:0]
17096   attribute \src "libresoc.v:11086.3-11122.6"
17097   wire width 2 $0\dec30_cry_in[1:0]
17098   attribute \src "libresoc.v:11234.3-11270.6"
17099   wire $0\dec30_cry_out[0:0]
17100   attribute \src "libresoc.v:11567.3-11603.6"
17101   wire width 5 $0\dec30_form[4:0]
17102   attribute \src "libresoc.v:10938.3-10974.6"
17103   wire width 12 $0\dec30_function_unit[11:0]
17104   attribute \src "libresoc.v:11604.3-11640.6"
17105   wire width 3 $0\dec30_in1_sel[2:0]
17106   attribute \src "libresoc.v:11641.3-11677.6"
17107   wire width 4 $0\dec30_in2_sel[3:0]
17108   attribute \src "libresoc.v:11678.3-11714.6"
17109   wire width 2 $0\dec30_in3_sel[1:0]
17110   attribute \src "libresoc.v:11345.3-11381.6"
17111   wire width 7 $0\dec30_internal_op[6:0]
17112   attribute \src "libresoc.v:11160.3-11196.6"
17113   wire $0\dec30_inv_a[0:0]
17114   attribute \src "libresoc.v:11197.3-11233.6"
17115   wire $0\dec30_inv_out[0:0]
17116   attribute \src "libresoc.v:11419.3-11455.6"
17117   wire $0\dec30_is_32b[0:0]
17118   attribute \src "libresoc.v:10975.3-11011.6"
17119   wire width 4 $0\dec30_ldst_len[3:0]
17120   attribute \src "libresoc.v:11493.3-11529.6"
17121   wire $0\dec30_lk[0:0]
17122   attribute \src "libresoc.v:11715.3-11751.6"
17123   wire width 2 $0\dec30_out_sel[1:0]
17124   attribute \src "libresoc.v:11049.3-11085.6"
17125   wire width 2 $0\dec30_rc_sel[1:0]
17126   attribute \src "libresoc.v:11382.3-11418.6"
17127   wire $0\dec30_rsrv[0:0]
17128   attribute \src "libresoc.v:11530.3-11566.6"
17129   wire $0\dec30_sgl_pipe[0:0]
17130   attribute \src "libresoc.v:11456.3-11492.6"
17131   wire $0\dec30_sgn[0:0]
17132   attribute \src "libresoc.v:11308.3-11344.6"
17133   wire $0\dec30_sgn_ext[0:0]
17134   attribute \src "libresoc.v:11012.3-11048.6"
17135   wire width 2 $0\dec30_upd[1:0]
17136   attribute \src "libresoc.v:10681.7-10681.20"
17137   wire $0\initial[0:0]
17138   attribute \src "libresoc.v:11123.3-11159.6"
17139   wire width 8 $1\dec30_asmcode[7:0]
17140   attribute \src "libresoc.v:11271.3-11307.6"
17141   wire $1\dec30_br[0:0]
17142   attribute \src "libresoc.v:11752.3-11788.6"
17143   wire width 3 $1\dec30_cr_in[2:0]
17144   attribute \src "libresoc.v:11789.3-11825.6"
17145   wire width 3 $1\dec30_cr_out[2:0]
17146   attribute \src "libresoc.v:11086.3-11122.6"
17147   wire width 2 $1\dec30_cry_in[1:0]
17148   attribute \src "libresoc.v:11234.3-11270.6"
17149   wire $1\dec30_cry_out[0:0]
17150   attribute \src "libresoc.v:11567.3-11603.6"
17151   wire width 5 $1\dec30_form[4:0]
17152   attribute \src "libresoc.v:10938.3-10974.6"
17153   wire width 12 $1\dec30_function_unit[11:0]
17154   attribute \src "libresoc.v:11604.3-11640.6"
17155   wire width 3 $1\dec30_in1_sel[2:0]
17156   attribute \src "libresoc.v:11641.3-11677.6"
17157   wire width 4 $1\dec30_in2_sel[3:0]
17158   attribute \src "libresoc.v:11678.3-11714.6"
17159   wire width 2 $1\dec30_in3_sel[1:0]
17160   attribute \src "libresoc.v:11345.3-11381.6"
17161   wire width 7 $1\dec30_internal_op[6:0]
17162   attribute \src "libresoc.v:11160.3-11196.6"
17163   wire $1\dec30_inv_a[0:0]
17164   attribute \src "libresoc.v:11197.3-11233.6"
17165   wire $1\dec30_inv_out[0:0]
17166   attribute \src "libresoc.v:11419.3-11455.6"
17167   wire $1\dec30_is_32b[0:0]
17168   attribute \src "libresoc.v:10975.3-11011.6"
17169   wire width 4 $1\dec30_ldst_len[3:0]
17170   attribute \src "libresoc.v:11493.3-11529.6"
17171   wire $1\dec30_lk[0:0]
17172   attribute \src "libresoc.v:11715.3-11751.6"
17173   wire width 2 $1\dec30_out_sel[1:0]
17174   attribute \src "libresoc.v:11049.3-11085.6"
17175   wire width 2 $1\dec30_rc_sel[1:0]
17176   attribute \src "libresoc.v:11382.3-11418.6"
17177   wire $1\dec30_rsrv[0:0]
17178   attribute \src "libresoc.v:11530.3-11566.6"
17179   wire $1\dec30_sgl_pipe[0:0]
17180   attribute \src "libresoc.v:11456.3-11492.6"
17181   wire $1\dec30_sgn[0:0]
17182   attribute \src "libresoc.v:11308.3-11344.6"
17183   wire $1\dec30_sgn_ext[0:0]
17184   attribute \src "libresoc.v:11012.3-11048.6"
17185   wire width 2 $1\dec30_upd[1:0]
17186   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17187   wire width 8 output 4 \dec30_asmcode
17188   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17189   wire output 18 \dec30_br
17190   attribute \enum_base_type "CRInSel"
17191   attribute \enum_value_000 "NONE"
17192   attribute \enum_value_001 "CR0"
17193   attribute \enum_value_010 "BI"
17194   attribute \enum_value_011 "BFA"
17195   attribute \enum_value_100 "BA_BB"
17196   attribute \enum_value_101 "BC"
17197   attribute \enum_value_110 "WHOLE_REG"
17198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17199   wire width 3 output 9 \dec30_cr_in
17200   attribute \enum_base_type "CROutSel"
17201   attribute \enum_value_000 "NONE"
17202   attribute \enum_value_001 "CR0"
17203   attribute \enum_value_010 "BF"
17204   attribute \enum_value_011 "BT"
17205   attribute \enum_value_100 "WHOLE_REG"
17206   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17207   wire width 3 output 10 \dec30_cr_out
17208   attribute \enum_base_type "CryIn"
17209   attribute \enum_value_00 "ZERO"
17210   attribute \enum_value_01 "ONE"
17211   attribute \enum_value_10 "CA"
17212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17213   wire width 2 output 14 \dec30_cry_in
17214   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17215   wire output 17 \dec30_cry_out
17216   attribute \enum_base_type "Form"
17217   attribute \enum_value_00000 "NONE"
17218   attribute \enum_value_00001 "I"
17219   attribute \enum_value_00010 "B"
17220   attribute \enum_value_00011 "SC"
17221   attribute \enum_value_00100 "D"
17222   attribute \enum_value_00101 "DS"
17223   attribute \enum_value_00110 "DQ"
17224   attribute \enum_value_00111 "DX"
17225   attribute \enum_value_01000 "X"
17226   attribute \enum_value_01001 "XL"
17227   attribute \enum_value_01010 "XFX"
17228   attribute \enum_value_01011 "XFL"
17229   attribute \enum_value_01100 "XX1"
17230   attribute \enum_value_01101 "XX2"
17231   attribute \enum_value_01110 "XX3"
17232   attribute \enum_value_01111 "XX4"
17233   attribute \enum_value_10000 "XS"
17234   attribute \enum_value_10001 "XO"
17235   attribute \enum_value_10010 "A"
17236   attribute \enum_value_10011 "M"
17237   attribute \enum_value_10100 "MD"
17238   attribute \enum_value_10101 "MDS"
17239   attribute \enum_value_10110 "VA"
17240   attribute \enum_value_10111 "VC"
17241   attribute \enum_value_11000 "VX"
17242   attribute \enum_value_11001 "EVX"
17243   attribute \enum_value_11010 "EVS"
17244   attribute \enum_value_11011 "Z22"
17245   attribute \enum_value_11100 "Z23"
17246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17247   wire width 5 output 3 \dec30_form
17248   attribute \enum_base_type "Function"
17249   attribute \enum_value_000000000000 "NONE"
17250   attribute \enum_value_000000000010 "ALU"
17251   attribute \enum_value_000000000100 "LDST"
17252   attribute \enum_value_000000001000 "SHIFT_ROT"
17253   attribute \enum_value_000000010000 "LOGICAL"
17254   attribute \enum_value_000000100000 "BRANCH"
17255   attribute \enum_value_000001000000 "CR"
17256   attribute \enum_value_000010000000 "TRAP"
17257   attribute \enum_value_000100000000 "MUL"
17258   attribute \enum_value_001000000000 "DIV"
17259   attribute \enum_value_010000000000 "SPR"
17260   attribute \enum_value_100000000000 "MMU"
17261   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17262   wire width 12 output 1 \dec30_function_unit
17263   attribute \enum_base_type "In1Sel"
17264   attribute \enum_value_000 "NONE"
17265   attribute \enum_value_001 "RA"
17266   attribute \enum_value_010 "RA_OR_ZERO"
17267   attribute \enum_value_011 "SPR"
17268   attribute \enum_value_100 "RS"
17269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17270   wire width 3 output 5 \dec30_in1_sel
17271   attribute \enum_base_type "In2Sel"
17272   attribute \enum_value_0000 "NONE"
17273   attribute \enum_value_0001 "RB"
17274   attribute \enum_value_0010 "CONST_UI"
17275   attribute \enum_value_0011 "CONST_SI"
17276   attribute \enum_value_0100 "CONST_UI_HI"
17277   attribute \enum_value_0101 "CONST_SI_HI"
17278   attribute \enum_value_0110 "CONST_LI"
17279   attribute \enum_value_0111 "CONST_BD"
17280   attribute \enum_value_1000 "CONST_DS"
17281   attribute \enum_value_1001 "CONST_M1"
17282   attribute \enum_value_1010 "CONST_SH"
17283   attribute \enum_value_1011 "CONST_SH32"
17284   attribute \enum_value_1100 "SPR"
17285   attribute \enum_value_1101 "RS"
17286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17287   wire width 4 output 6 \dec30_in2_sel
17288   attribute \enum_base_type "In3Sel"
17289   attribute \enum_value_00 "NONE"
17290   attribute \enum_value_01 "RS"
17291   attribute \enum_value_10 "RB"
17292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17293   wire width 2 output 7 \dec30_in3_sel
17294   attribute \enum_base_type "MicrOp"
17295   attribute \enum_value_0000000 "OP_ILLEGAL"
17296   attribute \enum_value_0000001 "OP_NOP"
17297   attribute \enum_value_0000010 "OP_ADD"
17298   attribute \enum_value_0000011 "OP_ADDPCIS"
17299   attribute \enum_value_0000100 "OP_AND"
17300   attribute \enum_value_0000101 "OP_ATTN"
17301   attribute \enum_value_0000110 "OP_B"
17302   attribute \enum_value_0000111 "OP_BC"
17303   attribute \enum_value_0001000 "OP_BCREG"
17304   attribute \enum_value_0001001 "OP_BPERM"
17305   attribute \enum_value_0001010 "OP_CMP"
17306   attribute \enum_value_0001011 "OP_CMPB"
17307   attribute \enum_value_0001100 "OP_CMPEQB"
17308   attribute \enum_value_0001101 "OP_CMPRB"
17309   attribute \enum_value_0001110 "OP_CNTZ"
17310   attribute \enum_value_0001111 "OP_CRAND"
17311   attribute \enum_value_0010000 "OP_CRANDC"
17312   attribute \enum_value_0010001 "OP_CREQV"
17313   attribute \enum_value_0010010 "OP_CRNAND"
17314   attribute \enum_value_0010011 "OP_CRNOR"
17315   attribute \enum_value_0010100 "OP_CROR"
17316   attribute \enum_value_0010101 "OP_CRORC"
17317   attribute \enum_value_0010110 "OP_CRXOR"
17318   attribute \enum_value_0010111 "OP_DARN"
17319   attribute \enum_value_0011000 "OP_DCBF"
17320   attribute \enum_value_0011001 "OP_DCBST"
17321   attribute \enum_value_0011010 "OP_DCBT"
17322   attribute \enum_value_0011011 "OP_DCBTST"
17323   attribute \enum_value_0011100 "OP_DCBZ"
17324   attribute \enum_value_0011101 "OP_DIV"
17325   attribute \enum_value_0011110 "OP_DIVE"
17326   attribute \enum_value_0011111 "OP_EXTS"
17327   attribute \enum_value_0100000 "OP_EXTSWSLI"
17328   attribute \enum_value_0100001 "OP_ICBI"
17329   attribute \enum_value_0100010 "OP_ICBT"
17330   attribute \enum_value_0100011 "OP_ISEL"
17331   attribute \enum_value_0100100 "OP_ISYNC"
17332   attribute \enum_value_0100101 "OP_LOAD"
17333   attribute \enum_value_0100110 "OP_STORE"
17334   attribute \enum_value_0100111 "OP_MADDHD"
17335   attribute \enum_value_0101000 "OP_MADDHDU"
17336   attribute \enum_value_0101001 "OP_MADDLD"
17337   attribute \enum_value_0101010 "OP_MCRF"
17338   attribute \enum_value_0101011 "OP_MCRXR"
17339   attribute \enum_value_0101100 "OP_MCRXRX"
17340   attribute \enum_value_0101101 "OP_MFCR"
17341   attribute \enum_value_0101110 "OP_MFSPR"
17342   attribute \enum_value_0101111 "OP_MOD"
17343   attribute \enum_value_0110000 "OP_MTCRF"
17344   attribute \enum_value_0110001 "OP_MTSPR"
17345   attribute \enum_value_0110010 "OP_MUL_L64"
17346   attribute \enum_value_0110011 "OP_MUL_H64"
17347   attribute \enum_value_0110100 "OP_MUL_H32"
17348   attribute \enum_value_0110101 "OP_OR"
17349   attribute \enum_value_0110110 "OP_POPCNT"
17350   attribute \enum_value_0110111 "OP_PRTY"
17351   attribute \enum_value_0111000 "OP_RLC"
17352   attribute \enum_value_0111001 "OP_RLCL"
17353   attribute \enum_value_0111010 "OP_RLCR"
17354   attribute \enum_value_0111011 "OP_SETB"
17355   attribute \enum_value_0111100 "OP_SHL"
17356   attribute \enum_value_0111101 "OP_SHR"
17357   attribute \enum_value_0111110 "OP_SYNC"
17358   attribute \enum_value_0111111 "OP_TRAP"
17359   attribute \enum_value_1000011 "OP_XOR"
17360   attribute \enum_value_1000100 "OP_SIM_CONFIG"
17361   attribute \enum_value_1000101 "OP_CROP"
17362   attribute \enum_value_1000110 "OP_RFID"
17363   attribute \enum_value_1000111 "OP_MFMSR"
17364   attribute \enum_value_1001000 "OP_MTMSRD"
17365   attribute \enum_value_1001001 "OP_SC"
17366   attribute \enum_value_1001010 "OP_MTMSR"
17367   attribute \enum_value_1001011 "OP_TLBIE"
17368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17369   wire width 7 output 2 \dec30_internal_op
17370   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17371   wire output 15 \dec30_inv_a
17372   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17373   wire output 16 \dec30_inv_out
17374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17375   wire output 21 \dec30_is_32b
17376   attribute \enum_base_type "LdstLen"
17377   attribute \enum_value_0000 "NONE"
17378   attribute \enum_value_0001 "is1B"
17379   attribute \enum_value_0010 "is2B"
17380   attribute \enum_value_0100 "is4B"
17381   attribute \enum_value_1000 "is8B"
17382   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17383   wire width 4 output 11 \dec30_ldst_len
17384   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17385   wire output 23 \dec30_lk
17386   attribute \enum_base_type "OutSel"
17387   attribute \enum_value_00 "NONE"
17388   attribute \enum_value_01 "RT"
17389   attribute \enum_value_10 "RA"
17390   attribute \enum_value_11 "SPR"
17391   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17392   wire width 2 output 8 \dec30_out_sel
17393   attribute \enum_base_type "RC"
17394   attribute \enum_value_00 "NONE"
17395   attribute \enum_value_01 "ONE"
17396   attribute \enum_value_10 "RC"
17397   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17398   wire width 2 output 13 \dec30_rc_sel
17399   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17400   wire output 20 \dec30_rsrv
17401   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17402   wire output 24 \dec30_sgl_pipe
17403   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17404   wire output 22 \dec30_sgn
17405   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
17406   wire output 19 \dec30_sgn_ext
17407   attribute \enum_base_type "LDSTMode"
17408   attribute \enum_value_00 "NONE"
17409   attribute \enum_value_01 "update"
17410   attribute \enum_value_10 "cix"
17411   attribute \enum_value_11 "cx"
17412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
17413   wire width 2 output 12 \dec30_upd
17414   attribute \src "libresoc.v:10681.7-10681.15"
17415   wire \initial
17416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
17417   wire width 32 input 25 \opcode_in
17418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
17419   wire width 4 \opcode_switch
17420   attribute \src "libresoc.v:10681.7-10681.20"
17421   process $proc$libresoc.v:10681$381
17422     assign { } { }
17423     assign $0\initial[0:0] 1'0
17424     sync always
17425       update \initial $0\initial[0:0]
17426     sync init
17427   end
17428   attribute \src "libresoc.v:10938.3-10974.6"
17429   process $proc$libresoc.v:10938$357
17430     assign { } { }
17431     assign { } { }
17432     assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0]
17433     attribute \src "libresoc.v:10939.5-10939.29"
17434     switch \initial
17435       attribute \src "libresoc.v:10939.9-10939.17"
17436       case 1'1
17437       case
17438     end
17439     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17440     switch \opcode_switch
17441       attribute \src "libresoc.v:0.0-0.0"
17442       case 4'0100
17443         assign { } { }
17444         assign $1\dec30_function_unit[11:0] 12'000000001000
17445       attribute \src "libresoc.v:0.0-0.0"
17446       case 4'0101
17447         assign { } { }
17448         assign $1\dec30_function_unit[11:0] 12'000000001000
17449       attribute \src "libresoc.v:0.0-0.0"
17450       case 4'0000
17451         assign { } { }
17452         assign $1\dec30_function_unit[11:0] 12'000000001000
17453       attribute \src "libresoc.v:0.0-0.0"
17454       case 4'0001
17455         assign { } { }
17456         assign $1\dec30_function_unit[11:0] 12'000000001000
17457       attribute \src "libresoc.v:0.0-0.0"
17458       case 4'0010
17459         assign { } { }
17460         assign $1\dec30_function_unit[11:0] 12'000000001000
17461       attribute \src "libresoc.v:0.0-0.0"
17462       case 4'0011
17463         assign { } { }
17464         assign $1\dec30_function_unit[11:0] 12'000000001000
17465       attribute \src "libresoc.v:0.0-0.0"
17466       case 4'0110
17467         assign { } { }
17468         assign $1\dec30_function_unit[11:0] 12'000000001000
17469       attribute \src "libresoc.v:0.0-0.0"
17470       case 4'0111
17471         assign { } { }
17472         assign $1\dec30_function_unit[11:0] 12'000000001000
17473       attribute \src "libresoc.v:0.0-0.0"
17474       case 4'1000
17475         assign { } { }
17476         assign $1\dec30_function_unit[11:0] 12'000000001000
17477       attribute \src "libresoc.v:0.0-0.0"
17478       case 4'1001
17479         assign { } { }
17480         assign $1\dec30_function_unit[11:0] 12'000000001000
17481       case
17482         assign $1\dec30_function_unit[11:0] 12'000000000000
17483     end
17484     sync always
17485       update \dec30_function_unit $0\dec30_function_unit[11:0]
17486   end
17487   attribute \src "libresoc.v:10975.3-11011.6"
17488   process $proc$libresoc.v:10975$358
17489     assign { } { }
17490     assign { } { }
17491     assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0]
17492     attribute \src "libresoc.v:10976.5-10976.29"
17493     switch \initial
17494       attribute \src "libresoc.v:10976.9-10976.17"
17495       case 1'1
17496       case
17497     end
17498     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17499     switch \opcode_switch
17500       attribute \src "libresoc.v:0.0-0.0"
17501       case 4'0100
17502         assign { } { }
17503         assign $1\dec30_ldst_len[3:0] 4'0000
17504       attribute \src "libresoc.v:0.0-0.0"
17505       case 4'0101
17506         assign { } { }
17507         assign $1\dec30_ldst_len[3:0] 4'0000
17508       attribute \src "libresoc.v:0.0-0.0"
17509       case 4'0000
17510         assign { } { }
17511         assign $1\dec30_ldst_len[3:0] 4'0000
17512       attribute \src "libresoc.v:0.0-0.0"
17513       case 4'0001
17514         assign { } { }
17515         assign $1\dec30_ldst_len[3:0] 4'0000
17516       attribute \src "libresoc.v:0.0-0.0"
17517       case 4'0010
17518         assign { } { }
17519         assign $1\dec30_ldst_len[3:0] 4'0000
17520       attribute \src "libresoc.v:0.0-0.0"
17521       case 4'0011
17522         assign { } { }
17523         assign $1\dec30_ldst_len[3:0] 4'0000
17524       attribute \src "libresoc.v:0.0-0.0"
17525       case 4'0110
17526         assign { } { }
17527         assign $1\dec30_ldst_len[3:0] 4'0000
17528       attribute \src "libresoc.v:0.0-0.0"
17529       case 4'0111
17530         assign { } { }
17531         assign $1\dec30_ldst_len[3:0] 4'0000
17532       attribute \src "libresoc.v:0.0-0.0"
17533       case 4'1000
17534         assign { } { }
17535         assign $1\dec30_ldst_len[3:0] 4'0000
17536       attribute \src "libresoc.v:0.0-0.0"
17537       case 4'1001
17538         assign { } { }
17539         assign $1\dec30_ldst_len[3:0] 4'0000
17540       case
17541         assign $1\dec30_ldst_len[3:0] 4'0000
17542     end
17543     sync always
17544       update \dec30_ldst_len $0\dec30_ldst_len[3:0]
17545   end
17546   attribute \src "libresoc.v:11012.3-11048.6"
17547   process $proc$libresoc.v:11012$359
17548     assign { } { }
17549     assign { } { }
17550     assign $0\dec30_upd[1:0] $1\dec30_upd[1:0]
17551     attribute \src "libresoc.v:11013.5-11013.29"
17552     switch \initial
17553       attribute \src "libresoc.v:11013.9-11013.17"
17554       case 1'1
17555       case
17556     end
17557     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17558     switch \opcode_switch
17559       attribute \src "libresoc.v:0.0-0.0"
17560       case 4'0100
17561         assign { } { }
17562         assign $1\dec30_upd[1:0] 2'00
17563       attribute \src "libresoc.v:0.0-0.0"
17564       case 4'0101
17565         assign { } { }
17566         assign $1\dec30_upd[1:0] 2'00
17567       attribute \src "libresoc.v:0.0-0.0"
17568       case 4'0000
17569         assign { } { }
17570         assign $1\dec30_upd[1:0] 2'00
17571       attribute \src "libresoc.v:0.0-0.0"
17572       case 4'0001
17573         assign { } { }
17574         assign $1\dec30_upd[1:0] 2'00
17575       attribute \src "libresoc.v:0.0-0.0"
17576       case 4'0010
17577         assign { } { }
17578         assign $1\dec30_upd[1:0] 2'00
17579       attribute \src "libresoc.v:0.0-0.0"
17580       case 4'0011
17581         assign { } { }
17582         assign $1\dec30_upd[1:0] 2'00
17583       attribute \src "libresoc.v:0.0-0.0"
17584       case 4'0110
17585         assign { } { }
17586         assign $1\dec30_upd[1:0] 2'00
17587       attribute \src "libresoc.v:0.0-0.0"
17588       case 4'0111
17589         assign { } { }
17590         assign $1\dec30_upd[1:0] 2'00
17591       attribute \src "libresoc.v:0.0-0.0"
17592       case 4'1000
17593         assign { } { }
17594         assign $1\dec30_upd[1:0] 2'00
17595       attribute \src "libresoc.v:0.0-0.0"
17596       case 4'1001
17597         assign { } { }
17598         assign $1\dec30_upd[1:0] 2'00
17599       case
17600         assign $1\dec30_upd[1:0] 2'00
17601     end
17602     sync always
17603       update \dec30_upd $0\dec30_upd[1:0]
17604   end
17605   attribute \src "libresoc.v:11049.3-11085.6"
17606   process $proc$libresoc.v:11049$360
17607     assign { } { }
17608     assign { } { }
17609     assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0]
17610     attribute \src "libresoc.v:11050.5-11050.29"
17611     switch \initial
17612       attribute \src "libresoc.v:11050.9-11050.17"
17613       case 1'1
17614       case
17615     end
17616     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17617     switch \opcode_switch
17618       attribute \src "libresoc.v:0.0-0.0"
17619       case 4'0100
17620         assign { } { }
17621         assign $1\dec30_rc_sel[1:0] 2'10
17622       attribute \src "libresoc.v:0.0-0.0"
17623       case 4'0101
17624         assign { } { }
17625         assign $1\dec30_rc_sel[1:0] 2'10
17626       attribute \src "libresoc.v:0.0-0.0"
17627       case 4'0000
17628         assign { } { }
17629         assign $1\dec30_rc_sel[1:0] 2'10
17630       attribute \src "libresoc.v:0.0-0.0"
17631       case 4'0001
17632         assign { } { }
17633         assign $1\dec30_rc_sel[1:0] 2'10
17634       attribute \src "libresoc.v:0.0-0.0"
17635       case 4'0010
17636         assign { } { }
17637         assign $1\dec30_rc_sel[1:0] 2'10
17638       attribute \src "libresoc.v:0.0-0.0"
17639       case 4'0011
17640         assign { } { }
17641         assign $1\dec30_rc_sel[1:0] 2'10
17642       attribute \src "libresoc.v:0.0-0.0"
17643       case 4'0110
17644         assign { } { }
17645         assign $1\dec30_rc_sel[1:0] 2'10
17646       attribute \src "libresoc.v:0.0-0.0"
17647       case 4'0111
17648         assign { } { }
17649         assign $1\dec30_rc_sel[1:0] 2'10
17650       attribute \src "libresoc.v:0.0-0.0"
17651       case 4'1000
17652         assign { } { }
17653         assign $1\dec30_rc_sel[1:0] 2'10
17654       attribute \src "libresoc.v:0.0-0.0"
17655       case 4'1001
17656         assign { } { }
17657         assign $1\dec30_rc_sel[1:0] 2'10
17658       case
17659         assign $1\dec30_rc_sel[1:0] 2'00
17660     end
17661     sync always
17662       update \dec30_rc_sel $0\dec30_rc_sel[1:0]
17663   end
17664   attribute \src "libresoc.v:11086.3-11122.6"
17665   process $proc$libresoc.v:11086$361
17666     assign { } { }
17667     assign { } { }
17668     assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0]
17669     attribute \src "libresoc.v:11087.5-11087.29"
17670     switch \initial
17671       attribute \src "libresoc.v:11087.9-11087.17"
17672       case 1'1
17673       case
17674     end
17675     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17676     switch \opcode_switch
17677       attribute \src "libresoc.v:0.0-0.0"
17678       case 4'0100
17679         assign { } { }
17680         assign $1\dec30_cry_in[1:0] 2'00
17681       attribute \src "libresoc.v:0.0-0.0"
17682       case 4'0101
17683         assign { } { }
17684         assign $1\dec30_cry_in[1:0] 2'00
17685       attribute \src "libresoc.v:0.0-0.0"
17686       case 4'0000
17687         assign { } { }
17688         assign $1\dec30_cry_in[1:0] 2'00
17689       attribute \src "libresoc.v:0.0-0.0"
17690       case 4'0001
17691         assign { } { }
17692         assign $1\dec30_cry_in[1:0] 2'00
17693       attribute \src "libresoc.v:0.0-0.0"
17694       case 4'0010
17695         assign { } { }
17696         assign $1\dec30_cry_in[1:0] 2'00
17697       attribute \src "libresoc.v:0.0-0.0"
17698       case 4'0011
17699         assign { } { }
17700         assign $1\dec30_cry_in[1:0] 2'00
17701       attribute \src "libresoc.v:0.0-0.0"
17702       case 4'0110
17703         assign { } { }
17704         assign $1\dec30_cry_in[1:0] 2'00
17705       attribute \src "libresoc.v:0.0-0.0"
17706       case 4'0111
17707         assign { } { }
17708         assign $1\dec30_cry_in[1:0] 2'00
17709       attribute \src "libresoc.v:0.0-0.0"
17710       case 4'1000
17711         assign { } { }
17712         assign $1\dec30_cry_in[1:0] 2'00
17713       attribute \src "libresoc.v:0.0-0.0"
17714       case 4'1001
17715         assign { } { }
17716         assign $1\dec30_cry_in[1:0] 2'00
17717       case
17718         assign $1\dec30_cry_in[1:0] 2'00
17719     end
17720     sync always
17721       update \dec30_cry_in $0\dec30_cry_in[1:0]
17722   end
17723   attribute \src "libresoc.v:11123.3-11159.6"
17724   process $proc$libresoc.v:11123$362
17725     assign { } { }
17726     assign { } { }
17727     assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0]
17728     attribute \src "libresoc.v:11124.5-11124.29"
17729     switch \initial
17730       attribute \src "libresoc.v:11124.9-11124.17"
17731       case 1'1
17732       case
17733     end
17734     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17735     switch \opcode_switch
17736       attribute \src "libresoc.v:0.0-0.0"
17737       case 4'0100
17738         assign { } { }
17739         assign $1\dec30_asmcode[7:0] 8'10010100
17740       attribute \src "libresoc.v:0.0-0.0"
17741       case 4'0101
17742         assign { } { }
17743         assign $1\dec30_asmcode[7:0] 8'10010100
17744       attribute \src "libresoc.v:0.0-0.0"
17745       case 4'0000
17746         assign { } { }
17747         assign $1\dec30_asmcode[7:0] 8'10010101
17748       attribute \src "libresoc.v:0.0-0.0"
17749       case 4'0001
17750         assign { } { }
17751         assign $1\dec30_asmcode[7:0] 8'10010101
17752       attribute \src "libresoc.v:0.0-0.0"
17753       case 4'0010
17754         assign { } { }
17755         assign $1\dec30_asmcode[7:0] 8'10010110
17756       attribute \src "libresoc.v:0.0-0.0"
17757       case 4'0011
17758         assign { } { }
17759         assign $1\dec30_asmcode[7:0] 8'10010110
17760       attribute \src "libresoc.v:0.0-0.0"
17761       case 4'0110
17762         assign { } { }
17763         assign $1\dec30_asmcode[7:0] 8'10010111
17764       attribute \src "libresoc.v:0.0-0.0"
17765       case 4'0111
17766         assign { } { }
17767         assign $1\dec30_asmcode[7:0] 8'10010111
17768       attribute \src "libresoc.v:0.0-0.0"
17769       case 4'1000
17770         assign { } { }
17771         assign $1\dec30_asmcode[7:0] 8'10010010
17772       attribute \src "libresoc.v:0.0-0.0"
17773       case 4'1001
17774         assign { } { }
17775         assign $1\dec30_asmcode[7:0] 8'10010011
17776       case
17777         assign $1\dec30_asmcode[7:0] 8'00000000
17778     end
17779     sync always
17780       update \dec30_asmcode $0\dec30_asmcode[7:0]
17781   end
17782   attribute \src "libresoc.v:11160.3-11196.6"
17783   process $proc$libresoc.v:11160$363
17784     assign { } { }
17785     assign { } { }
17786     assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0]
17787     attribute \src "libresoc.v:11161.5-11161.29"
17788     switch \initial
17789       attribute \src "libresoc.v:11161.9-11161.17"
17790       case 1'1
17791       case
17792     end
17793     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17794     switch \opcode_switch
17795       attribute \src "libresoc.v:0.0-0.0"
17796       case 4'0100
17797         assign { } { }
17798         assign $1\dec30_inv_a[0:0] 1'0
17799       attribute \src "libresoc.v:0.0-0.0"
17800       case 4'0101
17801         assign { } { }
17802         assign $1\dec30_inv_a[0:0] 1'0
17803       attribute \src "libresoc.v:0.0-0.0"
17804       case 4'0000
17805         assign { } { }
17806         assign $1\dec30_inv_a[0:0] 1'0
17807       attribute \src "libresoc.v:0.0-0.0"
17808       case 4'0001
17809         assign { } { }
17810         assign $1\dec30_inv_a[0:0] 1'0
17811       attribute \src "libresoc.v:0.0-0.0"
17812       case 4'0010
17813         assign { } { }
17814         assign $1\dec30_inv_a[0:0] 1'0
17815       attribute \src "libresoc.v:0.0-0.0"
17816       case 4'0011
17817         assign { } { }
17818         assign $1\dec30_inv_a[0:0] 1'0
17819       attribute \src "libresoc.v:0.0-0.0"
17820       case 4'0110
17821         assign { } { }
17822         assign $1\dec30_inv_a[0:0] 1'0
17823       attribute \src "libresoc.v:0.0-0.0"
17824       case 4'0111
17825         assign { } { }
17826         assign $1\dec30_inv_a[0:0] 1'0
17827       attribute \src "libresoc.v:0.0-0.0"
17828       case 4'1000
17829         assign { } { }
17830         assign $1\dec30_inv_a[0:0] 1'0
17831       attribute \src "libresoc.v:0.0-0.0"
17832       case 4'1001
17833         assign { } { }
17834         assign $1\dec30_inv_a[0:0] 1'0
17835       case
17836         assign $1\dec30_inv_a[0:0] 1'0
17837     end
17838     sync always
17839       update \dec30_inv_a $0\dec30_inv_a[0:0]
17840   end
17841   attribute \src "libresoc.v:11197.3-11233.6"
17842   process $proc$libresoc.v:11197$364
17843     assign { } { }
17844     assign { } { }
17845     assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0]
17846     attribute \src "libresoc.v:11198.5-11198.29"
17847     switch \initial
17848       attribute \src "libresoc.v:11198.9-11198.17"
17849       case 1'1
17850       case
17851     end
17852     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17853     switch \opcode_switch
17854       attribute \src "libresoc.v:0.0-0.0"
17855       case 4'0100
17856         assign { } { }
17857         assign $1\dec30_inv_out[0:0] 1'0
17858       attribute \src "libresoc.v:0.0-0.0"
17859       case 4'0101
17860         assign { } { }
17861         assign $1\dec30_inv_out[0:0] 1'0
17862       attribute \src "libresoc.v:0.0-0.0"
17863       case 4'0000
17864         assign { } { }
17865         assign $1\dec30_inv_out[0:0] 1'0
17866       attribute \src "libresoc.v:0.0-0.0"
17867       case 4'0001
17868         assign { } { }
17869         assign $1\dec30_inv_out[0:0] 1'0
17870       attribute \src "libresoc.v:0.0-0.0"
17871       case 4'0010
17872         assign { } { }
17873         assign $1\dec30_inv_out[0:0] 1'0
17874       attribute \src "libresoc.v:0.0-0.0"
17875       case 4'0011
17876         assign { } { }
17877         assign $1\dec30_inv_out[0:0] 1'0
17878       attribute \src "libresoc.v:0.0-0.0"
17879       case 4'0110
17880         assign { } { }
17881         assign $1\dec30_inv_out[0:0] 1'0
17882       attribute \src "libresoc.v:0.0-0.0"
17883       case 4'0111
17884         assign { } { }
17885         assign $1\dec30_inv_out[0:0] 1'0
17886       attribute \src "libresoc.v:0.0-0.0"
17887       case 4'1000
17888         assign { } { }
17889         assign $1\dec30_inv_out[0:0] 1'0
17890       attribute \src "libresoc.v:0.0-0.0"
17891       case 4'1001
17892         assign { } { }
17893         assign $1\dec30_inv_out[0:0] 1'0
17894       case
17895         assign $1\dec30_inv_out[0:0] 1'0
17896     end
17897     sync always
17898       update \dec30_inv_out $0\dec30_inv_out[0:0]
17899   end
17900   attribute \src "libresoc.v:11234.3-11270.6"
17901   process $proc$libresoc.v:11234$365
17902     assign { } { }
17903     assign { } { }
17904     assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0]
17905     attribute \src "libresoc.v:11235.5-11235.29"
17906     switch \initial
17907       attribute \src "libresoc.v:11235.9-11235.17"
17908       case 1'1
17909       case
17910     end
17911     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17912     switch \opcode_switch
17913       attribute \src "libresoc.v:0.0-0.0"
17914       case 4'0100
17915         assign { } { }
17916         assign $1\dec30_cry_out[0:0] 1'0
17917       attribute \src "libresoc.v:0.0-0.0"
17918       case 4'0101
17919         assign { } { }
17920         assign $1\dec30_cry_out[0:0] 1'0
17921       attribute \src "libresoc.v:0.0-0.0"
17922       case 4'0000
17923         assign { } { }
17924         assign $1\dec30_cry_out[0:0] 1'0
17925       attribute \src "libresoc.v:0.0-0.0"
17926       case 4'0001
17927         assign { } { }
17928         assign $1\dec30_cry_out[0:0] 1'0
17929       attribute \src "libresoc.v:0.0-0.0"
17930       case 4'0010
17931         assign { } { }
17932         assign $1\dec30_cry_out[0:0] 1'0
17933       attribute \src "libresoc.v:0.0-0.0"
17934       case 4'0011
17935         assign { } { }
17936         assign $1\dec30_cry_out[0:0] 1'0
17937       attribute \src "libresoc.v:0.0-0.0"
17938       case 4'0110
17939         assign { } { }
17940         assign $1\dec30_cry_out[0:0] 1'0
17941       attribute \src "libresoc.v:0.0-0.0"
17942       case 4'0111
17943         assign { } { }
17944         assign $1\dec30_cry_out[0:0] 1'0
17945       attribute \src "libresoc.v:0.0-0.0"
17946       case 4'1000
17947         assign { } { }
17948         assign $1\dec30_cry_out[0:0] 1'0
17949       attribute \src "libresoc.v:0.0-0.0"
17950       case 4'1001
17951         assign { } { }
17952         assign $1\dec30_cry_out[0:0] 1'0
17953       case
17954         assign $1\dec30_cry_out[0:0] 1'0
17955     end
17956     sync always
17957       update \dec30_cry_out $0\dec30_cry_out[0:0]
17958   end
17959   attribute \src "libresoc.v:11271.3-11307.6"
17960   process $proc$libresoc.v:11271$366
17961     assign { } { }
17962     assign { } { }
17963     assign $0\dec30_br[0:0] $1\dec30_br[0:0]
17964     attribute \src "libresoc.v:11272.5-11272.29"
17965     switch \initial
17966       attribute \src "libresoc.v:11272.9-11272.17"
17967       case 1'1
17968       case
17969     end
17970     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
17971     switch \opcode_switch
17972       attribute \src "libresoc.v:0.0-0.0"
17973       case 4'0100
17974         assign { } { }
17975         assign $1\dec30_br[0:0] 1'0
17976       attribute \src "libresoc.v:0.0-0.0"
17977       case 4'0101
17978         assign { } { }
17979         assign $1\dec30_br[0:0] 1'0
17980       attribute \src "libresoc.v:0.0-0.0"
17981       case 4'0000
17982         assign { } { }
17983         assign $1\dec30_br[0:0] 1'0
17984       attribute \src "libresoc.v:0.0-0.0"
17985       case 4'0001
17986         assign { } { }
17987         assign $1\dec30_br[0:0] 1'0
17988       attribute \src "libresoc.v:0.0-0.0"
17989       case 4'0010
17990         assign { } { }
17991         assign $1\dec30_br[0:0] 1'0
17992       attribute \src "libresoc.v:0.0-0.0"
17993       case 4'0011
17994         assign { } { }
17995         assign $1\dec30_br[0:0] 1'0
17996       attribute \src "libresoc.v:0.0-0.0"
17997       case 4'0110
17998         assign { } { }
17999         assign $1\dec30_br[0:0] 1'0
18000       attribute \src "libresoc.v:0.0-0.0"
18001       case 4'0111
18002         assign { } { }
18003         assign $1\dec30_br[0:0] 1'0
18004       attribute \src "libresoc.v:0.0-0.0"
18005       case 4'1000
18006         assign { } { }
18007         assign $1\dec30_br[0:0] 1'0
18008       attribute \src "libresoc.v:0.0-0.0"
18009       case 4'1001
18010         assign { } { }
18011         assign $1\dec30_br[0:0] 1'0
18012       case
18013         assign $1\dec30_br[0:0] 1'0
18014     end
18015     sync always
18016       update \dec30_br $0\dec30_br[0:0]
18017   end
18018   attribute \src "libresoc.v:11308.3-11344.6"
18019   process $proc$libresoc.v:11308$367
18020     assign { } { }
18021     assign { } { }
18022     assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0]
18023     attribute \src "libresoc.v:11309.5-11309.29"
18024     switch \initial
18025       attribute \src "libresoc.v:11309.9-11309.17"
18026       case 1'1
18027       case
18028     end
18029     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18030     switch \opcode_switch
18031       attribute \src "libresoc.v:0.0-0.0"
18032       case 4'0100
18033         assign { } { }
18034         assign $1\dec30_sgn_ext[0:0] 1'0
18035       attribute \src "libresoc.v:0.0-0.0"
18036       case 4'0101
18037         assign { } { }
18038         assign $1\dec30_sgn_ext[0:0] 1'0
18039       attribute \src "libresoc.v:0.0-0.0"
18040       case 4'0000
18041         assign { } { }
18042         assign $1\dec30_sgn_ext[0:0] 1'0
18043       attribute \src "libresoc.v:0.0-0.0"
18044       case 4'0001
18045         assign { } { }
18046         assign $1\dec30_sgn_ext[0:0] 1'0
18047       attribute \src "libresoc.v:0.0-0.0"
18048       case 4'0010
18049         assign { } { }
18050         assign $1\dec30_sgn_ext[0:0] 1'0
18051       attribute \src "libresoc.v:0.0-0.0"
18052       case 4'0011
18053         assign { } { }
18054         assign $1\dec30_sgn_ext[0:0] 1'0
18055       attribute \src "libresoc.v:0.0-0.0"
18056       case 4'0110
18057         assign { } { }
18058         assign $1\dec30_sgn_ext[0:0] 1'0
18059       attribute \src "libresoc.v:0.0-0.0"
18060       case 4'0111
18061         assign { } { }
18062         assign $1\dec30_sgn_ext[0:0] 1'0
18063       attribute \src "libresoc.v:0.0-0.0"
18064       case 4'1000
18065         assign { } { }
18066         assign $1\dec30_sgn_ext[0:0] 1'0
18067       attribute \src "libresoc.v:0.0-0.0"
18068       case 4'1001
18069         assign { } { }
18070         assign $1\dec30_sgn_ext[0:0] 1'0
18071       case
18072         assign $1\dec30_sgn_ext[0:0] 1'0
18073     end
18074     sync always
18075       update \dec30_sgn_ext $0\dec30_sgn_ext[0:0]
18076   end
18077   attribute \src "libresoc.v:11345.3-11381.6"
18078   process $proc$libresoc.v:11345$368
18079     assign { } { }
18080     assign { } { }
18081     assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0]
18082     attribute \src "libresoc.v:11346.5-11346.29"
18083     switch \initial
18084       attribute \src "libresoc.v:11346.9-11346.17"
18085       case 1'1
18086       case
18087     end
18088     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18089     switch \opcode_switch
18090       attribute \src "libresoc.v:0.0-0.0"
18091       case 4'0100
18092         assign { } { }
18093         assign $1\dec30_internal_op[6:0] 7'0111000
18094       attribute \src "libresoc.v:0.0-0.0"
18095       case 4'0101
18096         assign { } { }
18097         assign $1\dec30_internal_op[6:0] 7'0111000
18098       attribute \src "libresoc.v:0.0-0.0"
18099       case 4'0000
18100         assign { } { }
18101         assign $1\dec30_internal_op[6:0] 7'0111001
18102       attribute \src "libresoc.v:0.0-0.0"
18103       case 4'0001
18104         assign { } { }
18105         assign $1\dec30_internal_op[6:0] 7'0111001
18106       attribute \src "libresoc.v:0.0-0.0"
18107       case 4'0010
18108         assign { } { }
18109         assign $1\dec30_internal_op[6:0] 7'0111010
18110       attribute \src "libresoc.v:0.0-0.0"
18111       case 4'0011
18112         assign { } { }
18113         assign $1\dec30_internal_op[6:0] 7'0111010
18114       attribute \src "libresoc.v:0.0-0.0"
18115       case 4'0110
18116         assign { } { }
18117         assign $1\dec30_internal_op[6:0] 7'0111000
18118       attribute \src "libresoc.v:0.0-0.0"
18119       case 4'0111
18120         assign { } { }
18121         assign $1\dec30_internal_op[6:0] 7'0111000
18122       attribute \src "libresoc.v:0.0-0.0"
18123       case 4'1000
18124         assign { } { }
18125         assign $1\dec30_internal_op[6:0] 7'0111001
18126       attribute \src "libresoc.v:0.0-0.0"
18127       case 4'1001
18128         assign { } { }
18129         assign $1\dec30_internal_op[6:0] 7'0111010
18130       case
18131         assign $1\dec30_internal_op[6:0] 7'0000000
18132     end
18133     sync always
18134       update \dec30_internal_op $0\dec30_internal_op[6:0]
18135   end
18136   attribute \src "libresoc.v:11382.3-11418.6"
18137   process $proc$libresoc.v:11382$369
18138     assign { } { }
18139     assign { } { }
18140     assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0]
18141     attribute \src "libresoc.v:11383.5-11383.29"
18142     switch \initial
18143       attribute \src "libresoc.v:11383.9-11383.17"
18144       case 1'1
18145       case
18146     end
18147     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18148     switch \opcode_switch
18149       attribute \src "libresoc.v:0.0-0.0"
18150       case 4'0100
18151         assign { } { }
18152         assign $1\dec30_rsrv[0:0] 1'0
18153       attribute \src "libresoc.v:0.0-0.0"
18154       case 4'0101
18155         assign { } { }
18156         assign $1\dec30_rsrv[0:0] 1'0
18157       attribute \src "libresoc.v:0.0-0.0"
18158       case 4'0000
18159         assign { } { }
18160         assign $1\dec30_rsrv[0:0] 1'0
18161       attribute \src "libresoc.v:0.0-0.0"
18162       case 4'0001
18163         assign { } { }
18164         assign $1\dec30_rsrv[0:0] 1'0
18165       attribute \src "libresoc.v:0.0-0.0"
18166       case 4'0010
18167         assign { } { }
18168         assign $1\dec30_rsrv[0:0] 1'0
18169       attribute \src "libresoc.v:0.0-0.0"
18170       case 4'0011
18171         assign { } { }
18172         assign $1\dec30_rsrv[0:0] 1'0
18173       attribute \src "libresoc.v:0.0-0.0"
18174       case 4'0110
18175         assign { } { }
18176         assign $1\dec30_rsrv[0:0] 1'0
18177       attribute \src "libresoc.v:0.0-0.0"
18178       case 4'0111
18179         assign { } { }
18180         assign $1\dec30_rsrv[0:0] 1'0
18181       attribute \src "libresoc.v:0.0-0.0"
18182       case 4'1000
18183         assign { } { }
18184         assign $1\dec30_rsrv[0:0] 1'0
18185       attribute \src "libresoc.v:0.0-0.0"
18186       case 4'1001
18187         assign { } { }
18188         assign $1\dec30_rsrv[0:0] 1'0
18189       case
18190         assign $1\dec30_rsrv[0:0] 1'0
18191     end
18192     sync always
18193       update \dec30_rsrv $0\dec30_rsrv[0:0]
18194   end
18195   attribute \src "libresoc.v:11419.3-11455.6"
18196   process $proc$libresoc.v:11419$370
18197     assign { } { }
18198     assign { } { }
18199     assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0]
18200     attribute \src "libresoc.v:11420.5-11420.29"
18201     switch \initial
18202       attribute \src "libresoc.v:11420.9-11420.17"
18203       case 1'1
18204       case
18205     end
18206     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18207     switch \opcode_switch
18208       attribute \src "libresoc.v:0.0-0.0"
18209       case 4'0100
18210         assign { } { }
18211         assign $1\dec30_is_32b[0:0] 1'0
18212       attribute \src "libresoc.v:0.0-0.0"
18213       case 4'0101
18214         assign { } { }
18215         assign $1\dec30_is_32b[0:0] 1'0
18216       attribute \src "libresoc.v:0.0-0.0"
18217       case 4'0000
18218         assign { } { }
18219         assign $1\dec30_is_32b[0:0] 1'0
18220       attribute \src "libresoc.v:0.0-0.0"
18221       case 4'0001
18222         assign { } { }
18223         assign $1\dec30_is_32b[0:0] 1'0
18224       attribute \src "libresoc.v:0.0-0.0"
18225       case 4'0010
18226         assign { } { }
18227         assign $1\dec30_is_32b[0:0] 1'0
18228       attribute \src "libresoc.v:0.0-0.0"
18229       case 4'0011
18230         assign { } { }
18231         assign $1\dec30_is_32b[0:0] 1'0
18232       attribute \src "libresoc.v:0.0-0.0"
18233       case 4'0110
18234         assign { } { }
18235         assign $1\dec30_is_32b[0:0] 1'0
18236       attribute \src "libresoc.v:0.0-0.0"
18237       case 4'0111
18238         assign { } { }
18239         assign $1\dec30_is_32b[0:0] 1'0
18240       attribute \src "libresoc.v:0.0-0.0"
18241       case 4'1000
18242         assign { } { }
18243         assign $1\dec30_is_32b[0:0] 1'0
18244       attribute \src "libresoc.v:0.0-0.0"
18245       case 4'1001
18246         assign { } { }
18247         assign $1\dec30_is_32b[0:0] 1'0
18248       case
18249         assign $1\dec30_is_32b[0:0] 1'0
18250     end
18251     sync always
18252       update \dec30_is_32b $0\dec30_is_32b[0:0]
18253   end
18254   attribute \src "libresoc.v:11456.3-11492.6"
18255   process $proc$libresoc.v:11456$371
18256     assign { } { }
18257     assign { } { }
18258     assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0]
18259     attribute \src "libresoc.v:11457.5-11457.29"
18260     switch \initial
18261       attribute \src "libresoc.v:11457.9-11457.17"
18262       case 1'1
18263       case
18264     end
18265     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18266     switch \opcode_switch
18267       attribute \src "libresoc.v:0.0-0.0"
18268       case 4'0100
18269         assign { } { }
18270         assign $1\dec30_sgn[0:0] 1'0
18271       attribute \src "libresoc.v:0.0-0.0"
18272       case 4'0101
18273         assign { } { }
18274         assign $1\dec30_sgn[0:0] 1'0
18275       attribute \src "libresoc.v:0.0-0.0"
18276       case 4'0000
18277         assign { } { }
18278         assign $1\dec30_sgn[0:0] 1'0
18279       attribute \src "libresoc.v:0.0-0.0"
18280       case 4'0001
18281         assign { } { }
18282         assign $1\dec30_sgn[0:0] 1'0
18283       attribute \src "libresoc.v:0.0-0.0"
18284       case 4'0010
18285         assign { } { }
18286         assign $1\dec30_sgn[0:0] 1'0
18287       attribute \src "libresoc.v:0.0-0.0"
18288       case 4'0011
18289         assign { } { }
18290         assign $1\dec30_sgn[0:0] 1'0
18291       attribute \src "libresoc.v:0.0-0.0"
18292       case 4'0110
18293         assign { } { }
18294         assign $1\dec30_sgn[0:0] 1'0
18295       attribute \src "libresoc.v:0.0-0.0"
18296       case 4'0111
18297         assign { } { }
18298         assign $1\dec30_sgn[0:0] 1'0
18299       attribute \src "libresoc.v:0.0-0.0"
18300       case 4'1000
18301         assign { } { }
18302         assign $1\dec30_sgn[0:0] 1'0
18303       attribute \src "libresoc.v:0.0-0.0"
18304       case 4'1001
18305         assign { } { }
18306         assign $1\dec30_sgn[0:0] 1'0
18307       case
18308         assign $1\dec30_sgn[0:0] 1'0
18309     end
18310     sync always
18311       update \dec30_sgn $0\dec30_sgn[0:0]
18312   end
18313   attribute \src "libresoc.v:11493.3-11529.6"
18314   process $proc$libresoc.v:11493$372
18315     assign { } { }
18316     assign { } { }
18317     assign $0\dec30_lk[0:0] $1\dec30_lk[0:0]
18318     attribute \src "libresoc.v:11494.5-11494.29"
18319     switch \initial
18320       attribute \src "libresoc.v:11494.9-11494.17"
18321       case 1'1
18322       case
18323     end
18324     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18325     switch \opcode_switch
18326       attribute \src "libresoc.v:0.0-0.0"
18327       case 4'0100
18328         assign { } { }
18329         assign $1\dec30_lk[0:0] 1'0
18330       attribute \src "libresoc.v:0.0-0.0"
18331       case 4'0101
18332         assign { } { }
18333         assign $1\dec30_lk[0:0] 1'0
18334       attribute \src "libresoc.v:0.0-0.0"
18335       case 4'0000
18336         assign { } { }
18337         assign $1\dec30_lk[0:0] 1'0
18338       attribute \src "libresoc.v:0.0-0.0"
18339       case 4'0001
18340         assign { } { }
18341         assign $1\dec30_lk[0:0] 1'0
18342       attribute \src "libresoc.v:0.0-0.0"
18343       case 4'0010
18344         assign { } { }
18345         assign $1\dec30_lk[0:0] 1'0
18346       attribute \src "libresoc.v:0.0-0.0"
18347       case 4'0011
18348         assign { } { }
18349         assign $1\dec30_lk[0:0] 1'0
18350       attribute \src "libresoc.v:0.0-0.0"
18351       case 4'0110
18352         assign { } { }
18353         assign $1\dec30_lk[0:0] 1'0
18354       attribute \src "libresoc.v:0.0-0.0"
18355       case 4'0111
18356         assign { } { }
18357         assign $1\dec30_lk[0:0] 1'0
18358       attribute \src "libresoc.v:0.0-0.0"
18359       case 4'1000
18360         assign { } { }
18361         assign $1\dec30_lk[0:0] 1'0
18362       attribute \src "libresoc.v:0.0-0.0"
18363       case 4'1001
18364         assign { } { }
18365         assign $1\dec30_lk[0:0] 1'0
18366       case
18367         assign $1\dec30_lk[0:0] 1'0
18368     end
18369     sync always
18370       update \dec30_lk $0\dec30_lk[0:0]
18371   end
18372   attribute \src "libresoc.v:11530.3-11566.6"
18373   process $proc$libresoc.v:11530$373
18374     assign { } { }
18375     assign { } { }
18376     assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0]
18377     attribute \src "libresoc.v:11531.5-11531.29"
18378     switch \initial
18379       attribute \src "libresoc.v:11531.9-11531.17"
18380       case 1'1
18381       case
18382     end
18383     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18384     switch \opcode_switch
18385       attribute \src "libresoc.v:0.0-0.0"
18386       case 4'0100
18387         assign { } { }
18388         assign $1\dec30_sgl_pipe[0:0] 1'0
18389       attribute \src "libresoc.v:0.0-0.0"
18390       case 4'0101
18391         assign { } { }
18392         assign $1\dec30_sgl_pipe[0:0] 1'0
18393       attribute \src "libresoc.v:0.0-0.0"
18394       case 4'0000
18395         assign { } { }
18396         assign $1\dec30_sgl_pipe[0:0] 1'0
18397       attribute \src "libresoc.v:0.0-0.0"
18398       case 4'0001
18399         assign { } { }
18400         assign $1\dec30_sgl_pipe[0:0] 1'0
18401       attribute \src "libresoc.v:0.0-0.0"
18402       case 4'0010
18403         assign { } { }
18404         assign $1\dec30_sgl_pipe[0:0] 1'0
18405       attribute \src "libresoc.v:0.0-0.0"
18406       case 4'0011
18407         assign { } { }
18408         assign $1\dec30_sgl_pipe[0:0] 1'0
18409       attribute \src "libresoc.v:0.0-0.0"
18410       case 4'0110
18411         assign { } { }
18412         assign $1\dec30_sgl_pipe[0:0] 1'0
18413       attribute \src "libresoc.v:0.0-0.0"
18414       case 4'0111
18415         assign { } { }
18416         assign $1\dec30_sgl_pipe[0:0] 1'0
18417       attribute \src "libresoc.v:0.0-0.0"
18418       case 4'1000
18419         assign { } { }
18420         assign $1\dec30_sgl_pipe[0:0] 1'0
18421       attribute \src "libresoc.v:0.0-0.0"
18422       case 4'1001
18423         assign { } { }
18424         assign $1\dec30_sgl_pipe[0:0] 1'0
18425       case
18426         assign $1\dec30_sgl_pipe[0:0] 1'0
18427     end
18428     sync always
18429       update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0]
18430   end
18431   attribute \src "libresoc.v:11567.3-11603.6"
18432   process $proc$libresoc.v:11567$374
18433     assign { } { }
18434     assign { } { }
18435     assign $0\dec30_form[4:0] $1\dec30_form[4:0]
18436     attribute \src "libresoc.v:11568.5-11568.29"
18437     switch \initial
18438       attribute \src "libresoc.v:11568.9-11568.17"
18439       case 1'1
18440       case
18441     end
18442     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18443     switch \opcode_switch
18444       attribute \src "libresoc.v:0.0-0.0"
18445       case 4'0100
18446         assign { } { }
18447         assign $1\dec30_form[4:0] 5'10100
18448       attribute \src "libresoc.v:0.0-0.0"
18449       case 4'0101
18450         assign { } { }
18451         assign $1\dec30_form[4:0] 5'10100
18452       attribute \src "libresoc.v:0.0-0.0"
18453       case 4'0000
18454         assign { } { }
18455         assign $1\dec30_form[4:0] 5'10101
18456       attribute \src "libresoc.v:0.0-0.0"
18457       case 4'0001
18458         assign { } { }
18459         assign $1\dec30_form[4:0] 5'10101
18460       attribute \src "libresoc.v:0.0-0.0"
18461       case 4'0010
18462         assign { } { }
18463         assign $1\dec30_form[4:0] 5'10100
18464       attribute \src "libresoc.v:0.0-0.0"
18465       case 4'0011
18466         assign { } { }
18467         assign $1\dec30_form[4:0] 5'10100
18468       attribute \src "libresoc.v:0.0-0.0"
18469       case 4'0110
18470         assign { } { }
18471         assign $1\dec30_form[4:0] 5'10100
18472       attribute \src "libresoc.v:0.0-0.0"
18473       case 4'0111
18474         assign { } { }
18475         assign $1\dec30_form[4:0] 5'10100
18476       attribute \src "libresoc.v:0.0-0.0"
18477       case 4'1000
18478         assign { } { }
18479         assign $1\dec30_form[4:0] 5'10100
18480       attribute \src "libresoc.v:0.0-0.0"
18481       case 4'1001
18482         assign { } { }
18483         assign $1\dec30_form[4:0] 5'10100
18484       case
18485         assign $1\dec30_form[4:0] 5'00000
18486     end
18487     sync always
18488       update \dec30_form $0\dec30_form[4:0]
18489   end
18490   attribute \src "libresoc.v:11604.3-11640.6"
18491   process $proc$libresoc.v:11604$375
18492     assign { } { }
18493     assign { } { }
18494     assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0]
18495     attribute \src "libresoc.v:11605.5-11605.29"
18496     switch \initial
18497       attribute \src "libresoc.v:11605.9-11605.17"
18498       case 1'1
18499       case
18500     end
18501     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18502     switch \opcode_switch
18503       attribute \src "libresoc.v:0.0-0.0"
18504       case 4'0100
18505         assign { } { }
18506         assign $1\dec30_in1_sel[2:0] 3'000
18507       attribute \src "libresoc.v:0.0-0.0"
18508       case 4'0101
18509         assign { } { }
18510         assign $1\dec30_in1_sel[2:0] 3'000
18511       attribute \src "libresoc.v:0.0-0.0"
18512       case 4'0000
18513         assign { } { }
18514         assign $1\dec30_in1_sel[2:0] 3'000
18515       attribute \src "libresoc.v:0.0-0.0"
18516       case 4'0001
18517         assign { } { }
18518         assign $1\dec30_in1_sel[2:0] 3'000
18519       attribute \src "libresoc.v:0.0-0.0"
18520       case 4'0010
18521         assign { } { }
18522         assign $1\dec30_in1_sel[2:0] 3'000
18523       attribute \src "libresoc.v:0.0-0.0"
18524       case 4'0011
18525         assign { } { }
18526         assign $1\dec30_in1_sel[2:0] 3'000
18527       attribute \src "libresoc.v:0.0-0.0"
18528       case 4'0110
18529         assign { } { }
18530         assign $1\dec30_in1_sel[2:0] 3'001
18531       attribute \src "libresoc.v:0.0-0.0"
18532       case 4'0111
18533         assign { } { }
18534         assign $1\dec30_in1_sel[2:0] 3'001
18535       attribute \src "libresoc.v:0.0-0.0"
18536       case 4'1000
18537         assign { } { }
18538         assign $1\dec30_in1_sel[2:0] 3'000
18539       attribute \src "libresoc.v:0.0-0.0"
18540       case 4'1001
18541         assign { } { }
18542         assign $1\dec30_in1_sel[2:0] 3'000
18543       case
18544         assign $1\dec30_in1_sel[2:0] 3'000
18545     end
18546     sync always
18547       update \dec30_in1_sel $0\dec30_in1_sel[2:0]
18548   end
18549   attribute \src "libresoc.v:11641.3-11677.6"
18550   process $proc$libresoc.v:11641$376
18551     assign { } { }
18552     assign { } { }
18553     assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0]
18554     attribute \src "libresoc.v:11642.5-11642.29"
18555     switch \initial
18556       attribute \src "libresoc.v:11642.9-11642.17"
18557       case 1'1
18558       case
18559     end
18560     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18561     switch \opcode_switch
18562       attribute \src "libresoc.v:0.0-0.0"
18563       case 4'0100
18564         assign { } { }
18565         assign $1\dec30_in2_sel[3:0] 4'1010
18566       attribute \src "libresoc.v:0.0-0.0"
18567       case 4'0101
18568         assign { } { }
18569         assign $1\dec30_in2_sel[3:0] 4'1010
18570       attribute \src "libresoc.v:0.0-0.0"
18571       case 4'0000
18572         assign { } { }
18573         assign $1\dec30_in2_sel[3:0] 4'1010
18574       attribute \src "libresoc.v:0.0-0.0"
18575       case 4'0001
18576         assign { } { }
18577         assign $1\dec30_in2_sel[3:0] 4'1010
18578       attribute \src "libresoc.v:0.0-0.0"
18579       case 4'0010
18580         assign { } { }
18581         assign $1\dec30_in2_sel[3:0] 4'1010
18582       attribute \src "libresoc.v:0.0-0.0"
18583       case 4'0011
18584         assign { } { }
18585         assign $1\dec30_in2_sel[3:0] 4'1010
18586       attribute \src "libresoc.v:0.0-0.0"
18587       case 4'0110
18588         assign { } { }
18589         assign $1\dec30_in2_sel[3:0] 4'1010
18590       attribute \src "libresoc.v:0.0-0.0"
18591       case 4'0111
18592         assign { } { }
18593         assign $1\dec30_in2_sel[3:0] 4'1010
18594       attribute \src "libresoc.v:0.0-0.0"
18595       case 4'1000
18596         assign { } { }
18597         assign $1\dec30_in2_sel[3:0] 4'0001
18598       attribute \src "libresoc.v:0.0-0.0"
18599       case 4'1001
18600         assign { } { }
18601         assign $1\dec30_in2_sel[3:0] 4'0001
18602       case
18603         assign $1\dec30_in2_sel[3:0] 4'0000
18604     end
18605     sync always
18606       update \dec30_in2_sel $0\dec30_in2_sel[3:0]
18607   end
18608   attribute \src "libresoc.v:11678.3-11714.6"
18609   process $proc$libresoc.v:11678$377
18610     assign { } { }
18611     assign { } { }
18612     assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0]
18613     attribute \src "libresoc.v:11679.5-11679.29"
18614     switch \initial
18615       attribute \src "libresoc.v:11679.9-11679.17"
18616       case 1'1
18617       case
18618     end
18619     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18620     switch \opcode_switch
18621       attribute \src "libresoc.v:0.0-0.0"
18622       case 4'0100
18623         assign { } { }
18624         assign $1\dec30_in3_sel[1:0] 2'01
18625       attribute \src "libresoc.v:0.0-0.0"
18626       case 4'0101
18627         assign { } { }
18628         assign $1\dec30_in3_sel[1:0] 2'01
18629       attribute \src "libresoc.v:0.0-0.0"
18630       case 4'0000
18631         assign { } { }
18632         assign $1\dec30_in3_sel[1:0] 2'01
18633       attribute \src "libresoc.v:0.0-0.0"
18634       case 4'0001
18635         assign { } { }
18636         assign $1\dec30_in3_sel[1:0] 2'01
18637       attribute \src "libresoc.v:0.0-0.0"
18638       case 4'0010
18639         assign { } { }
18640         assign $1\dec30_in3_sel[1:0] 2'01
18641       attribute \src "libresoc.v:0.0-0.0"
18642       case 4'0011
18643         assign { } { }
18644         assign $1\dec30_in3_sel[1:0] 2'01
18645       attribute \src "libresoc.v:0.0-0.0"
18646       case 4'0110
18647         assign { } { }
18648         assign $1\dec30_in3_sel[1:0] 2'01
18649       attribute \src "libresoc.v:0.0-0.0"
18650       case 4'0111
18651         assign { } { }
18652         assign $1\dec30_in3_sel[1:0] 2'01
18653       attribute \src "libresoc.v:0.0-0.0"
18654       case 4'1000
18655         assign { } { }
18656         assign $1\dec30_in3_sel[1:0] 2'01
18657       attribute \src "libresoc.v:0.0-0.0"
18658       case 4'1001
18659         assign { } { }
18660         assign $1\dec30_in3_sel[1:0] 2'01
18661       case
18662         assign $1\dec30_in3_sel[1:0] 2'00
18663     end
18664     sync always
18665       update \dec30_in3_sel $0\dec30_in3_sel[1:0]
18666   end
18667   attribute \src "libresoc.v:11715.3-11751.6"
18668   process $proc$libresoc.v:11715$378
18669     assign { } { }
18670     assign { } { }
18671     assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0]
18672     attribute \src "libresoc.v:11716.5-11716.29"
18673     switch \initial
18674       attribute \src "libresoc.v:11716.9-11716.17"
18675       case 1'1
18676       case
18677     end
18678     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18679     switch \opcode_switch
18680       attribute \src "libresoc.v:0.0-0.0"
18681       case 4'0100
18682         assign { } { }
18683         assign $1\dec30_out_sel[1:0] 2'10
18684       attribute \src "libresoc.v:0.0-0.0"
18685       case 4'0101
18686         assign { } { }
18687         assign $1\dec30_out_sel[1:0] 2'10
18688       attribute \src "libresoc.v:0.0-0.0"
18689       case 4'0000
18690         assign { } { }
18691         assign $1\dec30_out_sel[1:0] 2'10
18692       attribute \src "libresoc.v:0.0-0.0"
18693       case 4'0001
18694         assign { } { }
18695         assign $1\dec30_out_sel[1:0] 2'10
18696       attribute \src "libresoc.v:0.0-0.0"
18697       case 4'0010
18698         assign { } { }
18699         assign $1\dec30_out_sel[1:0] 2'10
18700       attribute \src "libresoc.v:0.0-0.0"
18701       case 4'0011
18702         assign { } { }
18703         assign $1\dec30_out_sel[1:0] 2'10
18704       attribute \src "libresoc.v:0.0-0.0"
18705       case 4'0110
18706         assign { } { }
18707         assign $1\dec30_out_sel[1:0] 2'10
18708       attribute \src "libresoc.v:0.0-0.0"
18709       case 4'0111
18710         assign { } { }
18711         assign $1\dec30_out_sel[1:0] 2'10
18712       attribute \src "libresoc.v:0.0-0.0"
18713       case 4'1000
18714         assign { } { }
18715         assign $1\dec30_out_sel[1:0] 2'10
18716       attribute \src "libresoc.v:0.0-0.0"
18717       case 4'1001
18718         assign { } { }
18719         assign $1\dec30_out_sel[1:0] 2'10
18720       case
18721         assign $1\dec30_out_sel[1:0] 2'00
18722     end
18723     sync always
18724       update \dec30_out_sel $0\dec30_out_sel[1:0]
18725   end
18726   attribute \src "libresoc.v:11752.3-11788.6"
18727   process $proc$libresoc.v:11752$379
18728     assign { } { }
18729     assign { } { }
18730     assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0]
18731     attribute \src "libresoc.v:11753.5-11753.29"
18732     switch \initial
18733       attribute \src "libresoc.v:11753.9-11753.17"
18734       case 1'1
18735       case
18736     end
18737     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18738     switch \opcode_switch
18739       attribute \src "libresoc.v:0.0-0.0"
18740       case 4'0100
18741         assign { } { }
18742         assign $1\dec30_cr_in[2:0] 3'000
18743       attribute \src "libresoc.v:0.0-0.0"
18744       case 4'0101
18745         assign { } { }
18746         assign $1\dec30_cr_in[2:0] 3'000
18747       attribute \src "libresoc.v:0.0-0.0"
18748       case 4'0000
18749         assign { } { }
18750         assign $1\dec30_cr_in[2:0] 3'000
18751       attribute \src "libresoc.v:0.0-0.0"
18752       case 4'0001
18753         assign { } { }
18754         assign $1\dec30_cr_in[2:0] 3'000
18755       attribute \src "libresoc.v:0.0-0.0"
18756       case 4'0010
18757         assign { } { }
18758         assign $1\dec30_cr_in[2:0] 3'000
18759       attribute \src "libresoc.v:0.0-0.0"
18760       case 4'0011
18761         assign { } { }
18762         assign $1\dec30_cr_in[2:0] 3'000
18763       attribute \src "libresoc.v:0.0-0.0"
18764       case 4'0110
18765         assign { } { }
18766         assign $1\dec30_cr_in[2:0] 3'000
18767       attribute \src "libresoc.v:0.0-0.0"
18768       case 4'0111
18769         assign { } { }
18770         assign $1\dec30_cr_in[2:0] 3'000
18771       attribute \src "libresoc.v:0.0-0.0"
18772       case 4'1000
18773         assign { } { }
18774         assign $1\dec30_cr_in[2:0] 3'000
18775       attribute \src "libresoc.v:0.0-0.0"
18776       case 4'1001
18777         assign { } { }
18778         assign $1\dec30_cr_in[2:0] 3'000
18779       case
18780         assign $1\dec30_cr_in[2:0] 3'000
18781     end
18782     sync always
18783       update \dec30_cr_in $0\dec30_cr_in[2:0]
18784   end
18785   attribute \src "libresoc.v:11789.3-11825.6"
18786   process $proc$libresoc.v:11789$380
18787     assign { } { }
18788     assign { } { }
18789     assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0]
18790     attribute \src "libresoc.v:11790.5-11790.29"
18791     switch \initial
18792       attribute \src "libresoc.v:11790.9-11790.17"
18793       case 1'1
18794       case
18795     end
18796     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
18797     switch \opcode_switch
18798       attribute \src "libresoc.v:0.0-0.0"
18799       case 4'0100
18800         assign { } { }
18801         assign $1\dec30_cr_out[2:0] 3'001
18802       attribute \src "libresoc.v:0.0-0.0"
18803       case 4'0101
18804         assign { } { }
18805         assign $1\dec30_cr_out[2:0] 3'001
18806       attribute \src "libresoc.v:0.0-0.0"
18807       case 4'0000
18808         assign { } { }
18809         assign $1\dec30_cr_out[2:0] 3'001
18810       attribute \src "libresoc.v:0.0-0.0"
18811       case 4'0001
18812         assign { } { }
18813         assign $1\dec30_cr_out[2:0] 3'001
18814       attribute \src "libresoc.v:0.0-0.0"
18815       case 4'0010
18816         assign { } { }
18817         assign $1\dec30_cr_out[2:0] 3'001
18818       attribute \src "libresoc.v:0.0-0.0"
18819       case 4'0011
18820         assign { } { }
18821         assign $1\dec30_cr_out[2:0] 3'001
18822       attribute \src "libresoc.v:0.0-0.0"
18823       case 4'0110
18824         assign { } { }
18825         assign $1\dec30_cr_out[2:0] 3'001
18826       attribute \src "libresoc.v:0.0-0.0"
18827       case 4'0111
18828         assign { } { }
18829         assign $1\dec30_cr_out[2:0] 3'001
18830       attribute \src "libresoc.v:0.0-0.0"
18831       case 4'1000
18832         assign { } { }
18833         assign $1\dec30_cr_out[2:0] 3'001
18834       attribute \src "libresoc.v:0.0-0.0"
18835       case 4'1001
18836         assign { } { }
18837         assign $1\dec30_cr_out[2:0] 3'001
18838       case
18839         assign $1\dec30_cr_out[2:0] 3'000
18840     end
18841     sync always
18842       update \dec30_cr_out $0\dec30_cr_out[2:0]
18843   end
18844   connect \opcode_switch \opcode_in [4:1]
18845 end
18846 attribute \src "libresoc.v:11831.1-18201.10"
18847 attribute \cells_not_processed 1
18848 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31"
18849 attribute \generator "nMigen"
18850 module \dec31
18851   attribute \src "libresoc.v:16900.3-16960.6"
18852   wire width 8 $0\dec31_asmcode[7:0]
18853   attribute \src "libresoc.v:17754.3-17814.6"
18854   wire $0\dec31_br[0:0]
18855   attribute \src "libresoc.v:17205.3-17265.6"
18856   wire width 3 $0\dec31_cr_in[2:0]
18857   attribute \src "libresoc.v:17266.3-17326.6"
18858   wire width 3 $0\dec31_cr_out[2:0]
18859   attribute \src "libresoc.v:17510.3-17570.6"
18860   wire width 2 $0\dec31_cry_in[1:0]
18861   attribute \src "libresoc.v:17693.3-17753.6"
18862   wire $0\dec31_cry_out[0:0]
18863   attribute \src "libresoc.v:16839.3-16899.6"
18864   wire width 5 $0\dec31_form[4:0]
18865   attribute \src "libresoc.v:16717.3-16777.6"
18866   wire width 12 $0\dec31_function_unit[11:0]
18867   attribute \src "libresoc.v:16961.3-17021.6"
18868   wire width 3 $0\dec31_in1_sel[2:0]
18869   attribute \src "libresoc.v:17022.3-17082.6"
18870   wire width 4 $0\dec31_in2_sel[3:0]
18871   attribute \src "libresoc.v:17083.3-17143.6"
18872   wire width 2 $0\dec31_in3_sel[1:0]
18873   attribute \src "libresoc.v:16778.3-16838.6"
18874   wire width 7 $0\dec31_internal_op[6:0]
18875   attribute \src "libresoc.v:17571.3-17631.6"
18876   wire $0\dec31_inv_a[0:0]
18877   attribute \src "libresoc.v:17632.3-17692.6"
18878   wire $0\dec31_inv_out[0:0]
18879   attribute \src "libresoc.v:17937.3-17997.6"
18880   wire $0\dec31_is_32b[0:0]
18881   attribute \src "libresoc.v:17327.3-17387.6"
18882   wire width 4 $0\dec31_ldst_len[3:0]
18883   attribute \src "libresoc.v:18059.3-18119.6"
18884   wire $0\dec31_lk[0:0]
18885   attribute \src "libresoc.v:17144.3-17204.6"
18886   wire width 2 $0\dec31_out_sel[1:0]
18887   attribute \src "libresoc.v:17449.3-17509.6"
18888   wire width 2 $0\dec31_rc_sel[1:0]
18889   attribute \src "libresoc.v:17876.3-17936.6"
18890   wire $0\dec31_rsrv[0:0]
18891   attribute \src "libresoc.v:18120.3-18180.6"
18892   wire $0\dec31_sgl_pipe[0:0]
18893   attribute \src "libresoc.v:17998.3-18058.6"
18894   wire $0\dec31_sgn[0:0]
18895   attribute \src "libresoc.v:17815.3-17875.6"
18896   wire $0\dec31_sgn_ext[0:0]
18897   attribute \src "libresoc.v:17388.3-17448.6"
18898   wire width 2 $0\dec31_upd[1:0]
18899   attribute \src "libresoc.v:11832.7-11832.20"
18900   wire $0\initial[0:0]
18901   attribute \src "libresoc.v:16900.3-16960.6"
18902   wire width 8 $1\dec31_asmcode[7:0]
18903   attribute \src "libresoc.v:17754.3-17814.6"
18904   wire $1\dec31_br[0:0]
18905   attribute \src "libresoc.v:17205.3-17265.6"
18906   wire width 3 $1\dec31_cr_in[2:0]
18907   attribute \src "libresoc.v:17266.3-17326.6"
18908   wire width 3 $1\dec31_cr_out[2:0]
18909   attribute \src "libresoc.v:17510.3-17570.6"
18910   wire width 2 $1\dec31_cry_in[1:0]
18911   attribute \src "libresoc.v:17693.3-17753.6"
18912   wire $1\dec31_cry_out[0:0]
18913   attribute \src "libresoc.v:16839.3-16899.6"
18914   wire width 5 $1\dec31_form[4:0]
18915   attribute \src "libresoc.v:16717.3-16777.6"
18916   wire width 12 $1\dec31_function_unit[11:0]
18917   attribute \src "libresoc.v:16961.3-17021.6"
18918   wire width 3 $1\dec31_in1_sel[2:0]
18919   attribute \src "libresoc.v:17022.3-17082.6"
18920   wire width 4 $1\dec31_in2_sel[3:0]
18921   attribute \src "libresoc.v:17083.3-17143.6"
18922   wire width 2 $1\dec31_in3_sel[1:0]
18923   attribute \src "libresoc.v:16778.3-16838.6"
18924   wire width 7 $1\dec31_internal_op[6:0]
18925   attribute \src "libresoc.v:17571.3-17631.6"
18926   wire $1\dec31_inv_a[0:0]
18927   attribute \src "libresoc.v:17632.3-17692.6"
18928   wire $1\dec31_inv_out[0:0]
18929   attribute \src "libresoc.v:17937.3-17997.6"
18930   wire $1\dec31_is_32b[0:0]
18931   attribute \src "libresoc.v:17327.3-17387.6"
18932   wire width 4 $1\dec31_ldst_len[3:0]
18933   attribute \src "libresoc.v:18059.3-18119.6"
18934   wire $1\dec31_lk[0:0]
18935   attribute \src "libresoc.v:17144.3-17204.6"
18936   wire width 2 $1\dec31_out_sel[1:0]
18937   attribute \src "libresoc.v:17449.3-17509.6"
18938   wire width 2 $1\dec31_rc_sel[1:0]
18939   attribute \src "libresoc.v:17876.3-17936.6"
18940   wire $1\dec31_rsrv[0:0]
18941   attribute \src "libresoc.v:18120.3-18180.6"
18942   wire $1\dec31_sgl_pipe[0:0]
18943   attribute \src "libresoc.v:17998.3-18058.6"
18944   wire $1\dec31_sgn[0:0]
18945   attribute \src "libresoc.v:17815.3-17875.6"
18946   wire $1\dec31_sgn_ext[0:0]
18947   attribute \src "libresoc.v:17388.3-17448.6"
18948   wire width 2 $1\dec31_upd[1:0]
18949   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
18950   wire width 8 output 4 \dec31_asmcode
18951   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
18952   wire output 18 \dec31_br
18953   attribute \enum_base_type "CRInSel"
18954   attribute \enum_value_000 "NONE"
18955   attribute \enum_value_001 "CR0"
18956   attribute \enum_value_010 "BI"
18957   attribute \enum_value_011 "BFA"
18958   attribute \enum_value_100 "BA_BB"
18959   attribute \enum_value_101 "BC"
18960   attribute \enum_value_110 "WHOLE_REG"
18961   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
18962   wire width 3 output 9 \dec31_cr_in
18963   attribute \enum_base_type "CROutSel"
18964   attribute \enum_value_000 "NONE"
18965   attribute \enum_value_001 "CR0"
18966   attribute \enum_value_010 "BF"
18967   attribute \enum_value_011 "BT"
18968   attribute \enum_value_100 "WHOLE_REG"
18969   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
18970   wire width 3 output 10 \dec31_cr_out
18971   attribute \enum_base_type "CryIn"
18972   attribute \enum_value_00 "ZERO"
18973   attribute \enum_value_01 "ONE"
18974   attribute \enum_value_10 "CA"
18975   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
18976   wire width 2 output 14 \dec31_cry_in
18977   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
18978   wire output 17 \dec31_cry_out
18979   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
18980   wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode
18981   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
18982   wire \dec31_dec_sub0_dec31_dec_sub0_br
18983   attribute \enum_base_type "CRInSel"
18984   attribute \enum_value_000 "NONE"
18985   attribute \enum_value_001 "CR0"
18986   attribute \enum_value_010 "BI"
18987   attribute \enum_value_011 "BFA"
18988   attribute \enum_value_100 "BA_BB"
18989   attribute \enum_value_101 "BC"
18990   attribute \enum_value_110 "WHOLE_REG"
18991   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
18992   wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in
18993   attribute \enum_base_type "CROutSel"
18994   attribute \enum_value_000 "NONE"
18995   attribute \enum_value_001 "CR0"
18996   attribute \enum_value_010 "BF"
18997   attribute \enum_value_011 "BT"
18998   attribute \enum_value_100 "WHOLE_REG"
18999   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19000   wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out
19001   attribute \enum_base_type "CryIn"
19002   attribute \enum_value_00 "ZERO"
19003   attribute \enum_value_01 "ONE"
19004   attribute \enum_value_10 "CA"
19005   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19006   wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in
19007   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19008   wire \dec31_dec_sub0_dec31_dec_sub0_cry_out
19009   attribute \enum_base_type "Form"
19010   attribute \enum_value_00000 "NONE"
19011   attribute \enum_value_00001 "I"
19012   attribute \enum_value_00010 "B"
19013   attribute \enum_value_00011 "SC"
19014   attribute \enum_value_00100 "D"
19015   attribute \enum_value_00101 "DS"
19016   attribute \enum_value_00110 "DQ"
19017   attribute \enum_value_00111 "DX"
19018   attribute \enum_value_01000 "X"
19019   attribute \enum_value_01001 "XL"
19020   attribute \enum_value_01010 "XFX"
19021   attribute \enum_value_01011 "XFL"
19022   attribute \enum_value_01100 "XX1"
19023   attribute \enum_value_01101 "XX2"
19024   attribute \enum_value_01110 "XX3"
19025   attribute \enum_value_01111 "XX4"
19026   attribute \enum_value_10000 "XS"
19027   attribute \enum_value_10001 "XO"
19028   attribute \enum_value_10010 "A"
19029   attribute \enum_value_10011 "M"
19030   attribute \enum_value_10100 "MD"
19031   attribute \enum_value_10101 "MDS"
19032   attribute \enum_value_10110 "VA"
19033   attribute \enum_value_10111 "VC"
19034   attribute \enum_value_11000 "VX"
19035   attribute \enum_value_11001 "EVX"
19036   attribute \enum_value_11010 "EVS"
19037   attribute \enum_value_11011 "Z22"
19038   attribute \enum_value_11100 "Z23"
19039   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19040   wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form
19041   attribute \enum_base_type "Function"
19042   attribute \enum_value_000000000000 "NONE"
19043   attribute \enum_value_000000000010 "ALU"
19044   attribute \enum_value_000000000100 "LDST"
19045   attribute \enum_value_000000001000 "SHIFT_ROT"
19046   attribute \enum_value_000000010000 "LOGICAL"
19047   attribute \enum_value_000000100000 "BRANCH"
19048   attribute \enum_value_000001000000 "CR"
19049   attribute \enum_value_000010000000 "TRAP"
19050   attribute \enum_value_000100000000 "MUL"
19051   attribute \enum_value_001000000000 "DIV"
19052   attribute \enum_value_010000000000 "SPR"
19053   attribute \enum_value_100000000000 "MMU"
19054   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19055   wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit
19056   attribute \enum_base_type "In1Sel"
19057   attribute \enum_value_000 "NONE"
19058   attribute \enum_value_001 "RA"
19059   attribute \enum_value_010 "RA_OR_ZERO"
19060   attribute \enum_value_011 "SPR"
19061   attribute \enum_value_100 "RS"
19062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19063   wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel
19064   attribute \enum_base_type "In2Sel"
19065   attribute \enum_value_0000 "NONE"
19066   attribute \enum_value_0001 "RB"
19067   attribute \enum_value_0010 "CONST_UI"
19068   attribute \enum_value_0011 "CONST_SI"
19069   attribute \enum_value_0100 "CONST_UI_HI"
19070   attribute \enum_value_0101 "CONST_SI_HI"
19071   attribute \enum_value_0110 "CONST_LI"
19072   attribute \enum_value_0111 "CONST_BD"
19073   attribute \enum_value_1000 "CONST_DS"
19074   attribute \enum_value_1001 "CONST_M1"
19075   attribute \enum_value_1010 "CONST_SH"
19076   attribute \enum_value_1011 "CONST_SH32"
19077   attribute \enum_value_1100 "SPR"
19078   attribute \enum_value_1101 "RS"
19079   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19080   wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel
19081   attribute \enum_base_type "In3Sel"
19082   attribute \enum_value_00 "NONE"
19083   attribute \enum_value_01 "RS"
19084   attribute \enum_value_10 "RB"
19085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19086   wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel
19087   attribute \enum_base_type "MicrOp"
19088   attribute \enum_value_0000000 "OP_ILLEGAL"
19089   attribute \enum_value_0000001 "OP_NOP"
19090   attribute \enum_value_0000010 "OP_ADD"
19091   attribute \enum_value_0000011 "OP_ADDPCIS"
19092   attribute \enum_value_0000100 "OP_AND"
19093   attribute \enum_value_0000101 "OP_ATTN"
19094   attribute \enum_value_0000110 "OP_B"
19095   attribute \enum_value_0000111 "OP_BC"
19096   attribute \enum_value_0001000 "OP_BCREG"
19097   attribute \enum_value_0001001 "OP_BPERM"
19098   attribute \enum_value_0001010 "OP_CMP"
19099   attribute \enum_value_0001011 "OP_CMPB"
19100   attribute \enum_value_0001100 "OP_CMPEQB"
19101   attribute \enum_value_0001101 "OP_CMPRB"
19102   attribute \enum_value_0001110 "OP_CNTZ"
19103   attribute \enum_value_0001111 "OP_CRAND"
19104   attribute \enum_value_0010000 "OP_CRANDC"
19105   attribute \enum_value_0010001 "OP_CREQV"
19106   attribute \enum_value_0010010 "OP_CRNAND"
19107   attribute \enum_value_0010011 "OP_CRNOR"
19108   attribute \enum_value_0010100 "OP_CROR"
19109   attribute \enum_value_0010101 "OP_CRORC"
19110   attribute \enum_value_0010110 "OP_CRXOR"
19111   attribute \enum_value_0010111 "OP_DARN"
19112   attribute \enum_value_0011000 "OP_DCBF"
19113   attribute \enum_value_0011001 "OP_DCBST"
19114   attribute \enum_value_0011010 "OP_DCBT"
19115   attribute \enum_value_0011011 "OP_DCBTST"
19116   attribute \enum_value_0011100 "OP_DCBZ"
19117   attribute \enum_value_0011101 "OP_DIV"
19118   attribute \enum_value_0011110 "OP_DIVE"
19119   attribute \enum_value_0011111 "OP_EXTS"
19120   attribute \enum_value_0100000 "OP_EXTSWSLI"
19121   attribute \enum_value_0100001 "OP_ICBI"
19122   attribute \enum_value_0100010 "OP_ICBT"
19123   attribute \enum_value_0100011 "OP_ISEL"
19124   attribute \enum_value_0100100 "OP_ISYNC"
19125   attribute \enum_value_0100101 "OP_LOAD"
19126   attribute \enum_value_0100110 "OP_STORE"
19127   attribute \enum_value_0100111 "OP_MADDHD"
19128   attribute \enum_value_0101000 "OP_MADDHDU"
19129   attribute \enum_value_0101001 "OP_MADDLD"
19130   attribute \enum_value_0101010 "OP_MCRF"
19131   attribute \enum_value_0101011 "OP_MCRXR"
19132   attribute \enum_value_0101100 "OP_MCRXRX"
19133   attribute \enum_value_0101101 "OP_MFCR"
19134   attribute \enum_value_0101110 "OP_MFSPR"
19135   attribute \enum_value_0101111 "OP_MOD"
19136   attribute \enum_value_0110000 "OP_MTCRF"
19137   attribute \enum_value_0110001 "OP_MTSPR"
19138   attribute \enum_value_0110010 "OP_MUL_L64"
19139   attribute \enum_value_0110011 "OP_MUL_H64"
19140   attribute \enum_value_0110100 "OP_MUL_H32"
19141   attribute \enum_value_0110101 "OP_OR"
19142   attribute \enum_value_0110110 "OP_POPCNT"
19143   attribute \enum_value_0110111 "OP_PRTY"
19144   attribute \enum_value_0111000 "OP_RLC"
19145   attribute \enum_value_0111001 "OP_RLCL"
19146   attribute \enum_value_0111010 "OP_RLCR"
19147   attribute \enum_value_0111011 "OP_SETB"
19148   attribute \enum_value_0111100 "OP_SHL"
19149   attribute \enum_value_0111101 "OP_SHR"
19150   attribute \enum_value_0111110 "OP_SYNC"
19151   attribute \enum_value_0111111 "OP_TRAP"
19152   attribute \enum_value_1000011 "OP_XOR"
19153   attribute \enum_value_1000100 "OP_SIM_CONFIG"
19154   attribute \enum_value_1000101 "OP_CROP"
19155   attribute \enum_value_1000110 "OP_RFID"
19156   attribute \enum_value_1000111 "OP_MFMSR"
19157   attribute \enum_value_1001000 "OP_MTMSRD"
19158   attribute \enum_value_1001001 "OP_SC"
19159   attribute \enum_value_1001010 "OP_MTMSR"
19160   attribute \enum_value_1001011 "OP_TLBIE"
19161   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19162   wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op
19163   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19164   wire \dec31_dec_sub0_dec31_dec_sub0_inv_a
19165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19166   wire \dec31_dec_sub0_dec31_dec_sub0_inv_out
19167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19168   wire \dec31_dec_sub0_dec31_dec_sub0_is_32b
19169   attribute \enum_base_type "LdstLen"
19170   attribute \enum_value_0000 "NONE"
19171   attribute \enum_value_0001 "is1B"
19172   attribute \enum_value_0010 "is2B"
19173   attribute \enum_value_0100 "is4B"
19174   attribute \enum_value_1000 "is8B"
19175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19176   wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len
19177   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19178   wire \dec31_dec_sub0_dec31_dec_sub0_lk
19179   attribute \enum_base_type "OutSel"
19180   attribute \enum_value_00 "NONE"
19181   attribute \enum_value_01 "RT"
19182   attribute \enum_value_10 "RA"
19183   attribute \enum_value_11 "SPR"
19184   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19185   wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel
19186   attribute \enum_base_type "RC"
19187   attribute \enum_value_00 "NONE"
19188   attribute \enum_value_01 "ONE"
19189   attribute \enum_value_10 "RC"
19190   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19191   wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel
19192   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19193   wire \dec31_dec_sub0_dec31_dec_sub0_rsrv
19194   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19195   wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe
19196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19197   wire \dec31_dec_sub0_dec31_dec_sub0_sgn
19198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19199   wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext
19200   attribute \enum_base_type "LDSTMode"
19201   attribute \enum_value_00 "NONE"
19202   attribute \enum_value_01 "update"
19203   attribute \enum_value_10 "cix"
19204   attribute \enum_value_11 "cx"
19205   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19206   wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd
19207   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
19208   wire width 32 \dec31_dec_sub0_opcode_in
19209   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19210   wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode
19211   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19212   wire \dec31_dec_sub10_dec31_dec_sub10_br
19213   attribute \enum_base_type "CRInSel"
19214   attribute \enum_value_000 "NONE"
19215   attribute \enum_value_001 "CR0"
19216   attribute \enum_value_010 "BI"
19217   attribute \enum_value_011 "BFA"
19218   attribute \enum_value_100 "BA_BB"
19219   attribute \enum_value_101 "BC"
19220   attribute \enum_value_110 "WHOLE_REG"
19221   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19222   wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in
19223   attribute \enum_base_type "CROutSel"
19224   attribute \enum_value_000 "NONE"
19225   attribute \enum_value_001 "CR0"
19226   attribute \enum_value_010 "BF"
19227   attribute \enum_value_011 "BT"
19228   attribute \enum_value_100 "WHOLE_REG"
19229   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19230   wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out
19231   attribute \enum_base_type "CryIn"
19232   attribute \enum_value_00 "ZERO"
19233   attribute \enum_value_01 "ONE"
19234   attribute \enum_value_10 "CA"
19235   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19236   wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in
19237   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19238   wire \dec31_dec_sub10_dec31_dec_sub10_cry_out
19239   attribute \enum_base_type "Form"
19240   attribute \enum_value_00000 "NONE"
19241   attribute \enum_value_00001 "I"
19242   attribute \enum_value_00010 "B"
19243   attribute \enum_value_00011 "SC"
19244   attribute \enum_value_00100 "D"
19245   attribute \enum_value_00101 "DS"
19246   attribute \enum_value_00110 "DQ"
19247   attribute \enum_value_00111 "DX"
19248   attribute \enum_value_01000 "X"
19249   attribute \enum_value_01001 "XL"
19250   attribute \enum_value_01010 "XFX"
19251   attribute \enum_value_01011 "XFL"
19252   attribute \enum_value_01100 "XX1"
19253   attribute \enum_value_01101 "XX2"
19254   attribute \enum_value_01110 "XX3"
19255   attribute \enum_value_01111 "XX4"
19256   attribute \enum_value_10000 "XS"
19257   attribute \enum_value_10001 "XO"
19258   attribute \enum_value_10010 "A"
19259   attribute \enum_value_10011 "M"
19260   attribute \enum_value_10100 "MD"
19261   attribute \enum_value_10101 "MDS"
19262   attribute \enum_value_10110 "VA"
19263   attribute \enum_value_10111 "VC"
19264   attribute \enum_value_11000 "VX"
19265   attribute \enum_value_11001 "EVX"
19266   attribute \enum_value_11010 "EVS"
19267   attribute \enum_value_11011 "Z22"
19268   attribute \enum_value_11100 "Z23"
19269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19270   wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form
19271   attribute \enum_base_type "Function"
19272   attribute \enum_value_000000000000 "NONE"
19273   attribute \enum_value_000000000010 "ALU"
19274   attribute \enum_value_000000000100 "LDST"
19275   attribute \enum_value_000000001000 "SHIFT_ROT"
19276   attribute \enum_value_000000010000 "LOGICAL"
19277   attribute \enum_value_000000100000 "BRANCH"
19278   attribute \enum_value_000001000000 "CR"
19279   attribute \enum_value_000010000000 "TRAP"
19280   attribute \enum_value_000100000000 "MUL"
19281   attribute \enum_value_001000000000 "DIV"
19282   attribute \enum_value_010000000000 "SPR"
19283   attribute \enum_value_100000000000 "MMU"
19284   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19285   wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit
19286   attribute \enum_base_type "In1Sel"
19287   attribute \enum_value_000 "NONE"
19288   attribute \enum_value_001 "RA"
19289   attribute \enum_value_010 "RA_OR_ZERO"
19290   attribute \enum_value_011 "SPR"
19291   attribute \enum_value_100 "RS"
19292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19293   wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel
19294   attribute \enum_base_type "In2Sel"
19295   attribute \enum_value_0000 "NONE"
19296   attribute \enum_value_0001 "RB"
19297   attribute \enum_value_0010 "CONST_UI"
19298   attribute \enum_value_0011 "CONST_SI"
19299   attribute \enum_value_0100 "CONST_UI_HI"
19300   attribute \enum_value_0101 "CONST_SI_HI"
19301   attribute \enum_value_0110 "CONST_LI"
19302   attribute \enum_value_0111 "CONST_BD"
19303   attribute \enum_value_1000 "CONST_DS"
19304   attribute \enum_value_1001 "CONST_M1"
19305   attribute \enum_value_1010 "CONST_SH"
19306   attribute \enum_value_1011 "CONST_SH32"
19307   attribute \enum_value_1100 "SPR"
19308   attribute \enum_value_1101 "RS"
19309   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19310   wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel
19311   attribute \enum_base_type "In3Sel"
19312   attribute \enum_value_00 "NONE"
19313   attribute \enum_value_01 "RS"
19314   attribute \enum_value_10 "RB"
19315   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19316   wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel
19317   attribute \enum_base_type "MicrOp"
19318   attribute \enum_value_0000000 "OP_ILLEGAL"
19319   attribute \enum_value_0000001 "OP_NOP"
19320   attribute \enum_value_0000010 "OP_ADD"
19321   attribute \enum_value_0000011 "OP_ADDPCIS"
19322   attribute \enum_value_0000100 "OP_AND"
19323   attribute \enum_value_0000101 "OP_ATTN"
19324   attribute \enum_value_0000110 "OP_B"
19325   attribute \enum_value_0000111 "OP_BC"
19326   attribute \enum_value_0001000 "OP_BCREG"
19327   attribute \enum_value_0001001 "OP_BPERM"
19328   attribute \enum_value_0001010 "OP_CMP"
19329   attribute \enum_value_0001011 "OP_CMPB"
19330   attribute \enum_value_0001100 "OP_CMPEQB"
19331   attribute \enum_value_0001101 "OP_CMPRB"
19332   attribute \enum_value_0001110 "OP_CNTZ"
19333   attribute \enum_value_0001111 "OP_CRAND"
19334   attribute \enum_value_0010000 "OP_CRANDC"
19335   attribute \enum_value_0010001 "OP_CREQV"
19336   attribute \enum_value_0010010 "OP_CRNAND"
19337   attribute \enum_value_0010011 "OP_CRNOR"
19338   attribute \enum_value_0010100 "OP_CROR"
19339   attribute \enum_value_0010101 "OP_CRORC"
19340   attribute \enum_value_0010110 "OP_CRXOR"
19341   attribute \enum_value_0010111 "OP_DARN"
19342   attribute \enum_value_0011000 "OP_DCBF"
19343   attribute \enum_value_0011001 "OP_DCBST"
19344   attribute \enum_value_0011010 "OP_DCBT"
19345   attribute \enum_value_0011011 "OP_DCBTST"
19346   attribute \enum_value_0011100 "OP_DCBZ"
19347   attribute \enum_value_0011101 "OP_DIV"
19348   attribute \enum_value_0011110 "OP_DIVE"
19349   attribute \enum_value_0011111 "OP_EXTS"
19350   attribute \enum_value_0100000 "OP_EXTSWSLI"
19351   attribute \enum_value_0100001 "OP_ICBI"
19352   attribute \enum_value_0100010 "OP_ICBT"
19353   attribute \enum_value_0100011 "OP_ISEL"
19354   attribute \enum_value_0100100 "OP_ISYNC"
19355   attribute \enum_value_0100101 "OP_LOAD"
19356   attribute \enum_value_0100110 "OP_STORE"
19357   attribute \enum_value_0100111 "OP_MADDHD"
19358   attribute \enum_value_0101000 "OP_MADDHDU"
19359   attribute \enum_value_0101001 "OP_MADDLD"
19360   attribute \enum_value_0101010 "OP_MCRF"
19361   attribute \enum_value_0101011 "OP_MCRXR"
19362   attribute \enum_value_0101100 "OP_MCRXRX"
19363   attribute \enum_value_0101101 "OP_MFCR"
19364   attribute \enum_value_0101110 "OP_MFSPR"
19365   attribute \enum_value_0101111 "OP_MOD"
19366   attribute \enum_value_0110000 "OP_MTCRF"
19367   attribute \enum_value_0110001 "OP_MTSPR"
19368   attribute \enum_value_0110010 "OP_MUL_L64"
19369   attribute \enum_value_0110011 "OP_MUL_H64"
19370   attribute \enum_value_0110100 "OP_MUL_H32"
19371   attribute \enum_value_0110101 "OP_OR"
19372   attribute \enum_value_0110110 "OP_POPCNT"
19373   attribute \enum_value_0110111 "OP_PRTY"
19374   attribute \enum_value_0111000 "OP_RLC"
19375   attribute \enum_value_0111001 "OP_RLCL"
19376   attribute \enum_value_0111010 "OP_RLCR"
19377   attribute \enum_value_0111011 "OP_SETB"
19378   attribute \enum_value_0111100 "OP_SHL"
19379   attribute \enum_value_0111101 "OP_SHR"
19380   attribute \enum_value_0111110 "OP_SYNC"
19381   attribute \enum_value_0111111 "OP_TRAP"
19382   attribute \enum_value_1000011 "OP_XOR"
19383   attribute \enum_value_1000100 "OP_SIM_CONFIG"
19384   attribute \enum_value_1000101 "OP_CROP"
19385   attribute \enum_value_1000110 "OP_RFID"
19386   attribute \enum_value_1000111 "OP_MFMSR"
19387   attribute \enum_value_1001000 "OP_MTMSRD"
19388   attribute \enum_value_1001001 "OP_SC"
19389   attribute \enum_value_1001010 "OP_MTMSR"
19390   attribute \enum_value_1001011 "OP_TLBIE"
19391   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19392   wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op
19393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19394   wire \dec31_dec_sub10_dec31_dec_sub10_inv_a
19395   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19396   wire \dec31_dec_sub10_dec31_dec_sub10_inv_out
19397   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19398   wire \dec31_dec_sub10_dec31_dec_sub10_is_32b
19399   attribute \enum_base_type "LdstLen"
19400   attribute \enum_value_0000 "NONE"
19401   attribute \enum_value_0001 "is1B"
19402   attribute \enum_value_0010 "is2B"
19403   attribute \enum_value_0100 "is4B"
19404   attribute \enum_value_1000 "is8B"
19405   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19406   wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len
19407   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19408   wire \dec31_dec_sub10_dec31_dec_sub10_lk
19409   attribute \enum_base_type "OutSel"
19410   attribute \enum_value_00 "NONE"
19411   attribute \enum_value_01 "RT"
19412   attribute \enum_value_10 "RA"
19413   attribute \enum_value_11 "SPR"
19414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19415   wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel
19416   attribute \enum_base_type "RC"
19417   attribute \enum_value_00 "NONE"
19418   attribute \enum_value_01 "ONE"
19419   attribute \enum_value_10 "RC"
19420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19421   wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel
19422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19423   wire \dec31_dec_sub10_dec31_dec_sub10_rsrv
19424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19425   wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe
19426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19427   wire \dec31_dec_sub10_dec31_dec_sub10_sgn
19428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19429   wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext
19430   attribute \enum_base_type "LDSTMode"
19431   attribute \enum_value_00 "NONE"
19432   attribute \enum_value_01 "update"
19433   attribute \enum_value_10 "cix"
19434   attribute \enum_value_11 "cx"
19435   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19436   wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd
19437   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
19438   wire width 32 \dec31_dec_sub10_opcode_in
19439   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19440   wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode
19441   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19442   wire \dec31_dec_sub11_dec31_dec_sub11_br
19443   attribute \enum_base_type "CRInSel"
19444   attribute \enum_value_000 "NONE"
19445   attribute \enum_value_001 "CR0"
19446   attribute \enum_value_010 "BI"
19447   attribute \enum_value_011 "BFA"
19448   attribute \enum_value_100 "BA_BB"
19449   attribute \enum_value_101 "BC"
19450   attribute \enum_value_110 "WHOLE_REG"
19451   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19452   wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in
19453   attribute \enum_base_type "CROutSel"
19454   attribute \enum_value_000 "NONE"
19455   attribute \enum_value_001 "CR0"
19456   attribute \enum_value_010 "BF"
19457   attribute \enum_value_011 "BT"
19458   attribute \enum_value_100 "WHOLE_REG"
19459   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19460   wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out
19461   attribute \enum_base_type "CryIn"
19462   attribute \enum_value_00 "ZERO"
19463   attribute \enum_value_01 "ONE"
19464   attribute \enum_value_10 "CA"
19465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19466   wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in
19467   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19468   wire \dec31_dec_sub11_dec31_dec_sub11_cry_out
19469   attribute \enum_base_type "Form"
19470   attribute \enum_value_00000 "NONE"
19471   attribute \enum_value_00001 "I"
19472   attribute \enum_value_00010 "B"
19473   attribute \enum_value_00011 "SC"
19474   attribute \enum_value_00100 "D"
19475   attribute \enum_value_00101 "DS"
19476   attribute \enum_value_00110 "DQ"
19477   attribute \enum_value_00111 "DX"
19478   attribute \enum_value_01000 "X"
19479   attribute \enum_value_01001 "XL"
19480   attribute \enum_value_01010 "XFX"
19481   attribute \enum_value_01011 "XFL"
19482   attribute \enum_value_01100 "XX1"
19483   attribute \enum_value_01101 "XX2"
19484   attribute \enum_value_01110 "XX3"
19485   attribute \enum_value_01111 "XX4"
19486   attribute \enum_value_10000 "XS"
19487   attribute \enum_value_10001 "XO"
19488   attribute \enum_value_10010 "A"
19489   attribute \enum_value_10011 "M"
19490   attribute \enum_value_10100 "MD"
19491   attribute \enum_value_10101 "MDS"
19492   attribute \enum_value_10110 "VA"
19493   attribute \enum_value_10111 "VC"
19494   attribute \enum_value_11000 "VX"
19495   attribute \enum_value_11001 "EVX"
19496   attribute \enum_value_11010 "EVS"
19497   attribute \enum_value_11011 "Z22"
19498   attribute \enum_value_11100 "Z23"
19499   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19500   wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form
19501   attribute \enum_base_type "Function"
19502   attribute \enum_value_000000000000 "NONE"
19503   attribute \enum_value_000000000010 "ALU"
19504   attribute \enum_value_000000000100 "LDST"
19505   attribute \enum_value_000000001000 "SHIFT_ROT"
19506   attribute \enum_value_000000010000 "LOGICAL"
19507   attribute \enum_value_000000100000 "BRANCH"
19508   attribute \enum_value_000001000000 "CR"
19509   attribute \enum_value_000010000000 "TRAP"
19510   attribute \enum_value_000100000000 "MUL"
19511   attribute \enum_value_001000000000 "DIV"
19512   attribute \enum_value_010000000000 "SPR"
19513   attribute \enum_value_100000000000 "MMU"
19514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19515   wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit
19516   attribute \enum_base_type "In1Sel"
19517   attribute \enum_value_000 "NONE"
19518   attribute \enum_value_001 "RA"
19519   attribute \enum_value_010 "RA_OR_ZERO"
19520   attribute \enum_value_011 "SPR"
19521   attribute \enum_value_100 "RS"
19522   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19523   wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel
19524   attribute \enum_base_type "In2Sel"
19525   attribute \enum_value_0000 "NONE"
19526   attribute \enum_value_0001 "RB"
19527   attribute \enum_value_0010 "CONST_UI"
19528   attribute \enum_value_0011 "CONST_SI"
19529   attribute \enum_value_0100 "CONST_UI_HI"
19530   attribute \enum_value_0101 "CONST_SI_HI"
19531   attribute \enum_value_0110 "CONST_LI"
19532   attribute \enum_value_0111 "CONST_BD"
19533   attribute \enum_value_1000 "CONST_DS"
19534   attribute \enum_value_1001 "CONST_M1"
19535   attribute \enum_value_1010 "CONST_SH"
19536   attribute \enum_value_1011 "CONST_SH32"
19537   attribute \enum_value_1100 "SPR"
19538   attribute \enum_value_1101 "RS"
19539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19540   wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel
19541   attribute \enum_base_type "In3Sel"
19542   attribute \enum_value_00 "NONE"
19543   attribute \enum_value_01 "RS"
19544   attribute \enum_value_10 "RB"
19545   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19546   wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel
19547   attribute \enum_base_type "MicrOp"
19548   attribute \enum_value_0000000 "OP_ILLEGAL"
19549   attribute \enum_value_0000001 "OP_NOP"
19550   attribute \enum_value_0000010 "OP_ADD"
19551   attribute \enum_value_0000011 "OP_ADDPCIS"
19552   attribute \enum_value_0000100 "OP_AND"
19553   attribute \enum_value_0000101 "OP_ATTN"
19554   attribute \enum_value_0000110 "OP_B"
19555   attribute \enum_value_0000111 "OP_BC"
19556   attribute \enum_value_0001000 "OP_BCREG"
19557   attribute \enum_value_0001001 "OP_BPERM"
19558   attribute \enum_value_0001010 "OP_CMP"
19559   attribute \enum_value_0001011 "OP_CMPB"
19560   attribute \enum_value_0001100 "OP_CMPEQB"
19561   attribute \enum_value_0001101 "OP_CMPRB"
19562   attribute \enum_value_0001110 "OP_CNTZ"
19563   attribute \enum_value_0001111 "OP_CRAND"
19564   attribute \enum_value_0010000 "OP_CRANDC"
19565   attribute \enum_value_0010001 "OP_CREQV"
19566   attribute \enum_value_0010010 "OP_CRNAND"
19567   attribute \enum_value_0010011 "OP_CRNOR"
19568   attribute \enum_value_0010100 "OP_CROR"
19569   attribute \enum_value_0010101 "OP_CRORC"
19570   attribute \enum_value_0010110 "OP_CRXOR"
19571   attribute \enum_value_0010111 "OP_DARN"
19572   attribute \enum_value_0011000 "OP_DCBF"
19573   attribute \enum_value_0011001 "OP_DCBST"
19574   attribute \enum_value_0011010 "OP_DCBT"
19575   attribute \enum_value_0011011 "OP_DCBTST"
19576   attribute \enum_value_0011100 "OP_DCBZ"
19577   attribute \enum_value_0011101 "OP_DIV"
19578   attribute \enum_value_0011110 "OP_DIVE"
19579   attribute \enum_value_0011111 "OP_EXTS"
19580   attribute \enum_value_0100000 "OP_EXTSWSLI"
19581   attribute \enum_value_0100001 "OP_ICBI"
19582   attribute \enum_value_0100010 "OP_ICBT"
19583   attribute \enum_value_0100011 "OP_ISEL"
19584   attribute \enum_value_0100100 "OP_ISYNC"
19585   attribute \enum_value_0100101 "OP_LOAD"
19586   attribute \enum_value_0100110 "OP_STORE"
19587   attribute \enum_value_0100111 "OP_MADDHD"
19588   attribute \enum_value_0101000 "OP_MADDHDU"
19589   attribute \enum_value_0101001 "OP_MADDLD"
19590   attribute \enum_value_0101010 "OP_MCRF"
19591   attribute \enum_value_0101011 "OP_MCRXR"
19592   attribute \enum_value_0101100 "OP_MCRXRX"
19593   attribute \enum_value_0101101 "OP_MFCR"
19594   attribute \enum_value_0101110 "OP_MFSPR"
19595   attribute \enum_value_0101111 "OP_MOD"
19596   attribute \enum_value_0110000 "OP_MTCRF"
19597   attribute \enum_value_0110001 "OP_MTSPR"
19598   attribute \enum_value_0110010 "OP_MUL_L64"
19599   attribute \enum_value_0110011 "OP_MUL_H64"
19600   attribute \enum_value_0110100 "OP_MUL_H32"
19601   attribute \enum_value_0110101 "OP_OR"
19602   attribute \enum_value_0110110 "OP_POPCNT"
19603   attribute \enum_value_0110111 "OP_PRTY"
19604   attribute \enum_value_0111000 "OP_RLC"
19605   attribute \enum_value_0111001 "OP_RLCL"
19606   attribute \enum_value_0111010 "OP_RLCR"
19607   attribute \enum_value_0111011 "OP_SETB"
19608   attribute \enum_value_0111100 "OP_SHL"
19609   attribute \enum_value_0111101 "OP_SHR"
19610   attribute \enum_value_0111110 "OP_SYNC"
19611   attribute \enum_value_0111111 "OP_TRAP"
19612   attribute \enum_value_1000011 "OP_XOR"
19613   attribute \enum_value_1000100 "OP_SIM_CONFIG"
19614   attribute \enum_value_1000101 "OP_CROP"
19615   attribute \enum_value_1000110 "OP_RFID"
19616   attribute \enum_value_1000111 "OP_MFMSR"
19617   attribute \enum_value_1001000 "OP_MTMSRD"
19618   attribute \enum_value_1001001 "OP_SC"
19619   attribute \enum_value_1001010 "OP_MTMSR"
19620   attribute \enum_value_1001011 "OP_TLBIE"
19621   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19622   wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op
19623   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19624   wire \dec31_dec_sub11_dec31_dec_sub11_inv_a
19625   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19626   wire \dec31_dec_sub11_dec31_dec_sub11_inv_out
19627   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19628   wire \dec31_dec_sub11_dec31_dec_sub11_is_32b
19629   attribute \enum_base_type "LdstLen"
19630   attribute \enum_value_0000 "NONE"
19631   attribute \enum_value_0001 "is1B"
19632   attribute \enum_value_0010 "is2B"
19633   attribute \enum_value_0100 "is4B"
19634   attribute \enum_value_1000 "is8B"
19635   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19636   wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len
19637   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19638   wire \dec31_dec_sub11_dec31_dec_sub11_lk
19639   attribute \enum_base_type "OutSel"
19640   attribute \enum_value_00 "NONE"
19641   attribute \enum_value_01 "RT"
19642   attribute \enum_value_10 "RA"
19643   attribute \enum_value_11 "SPR"
19644   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19645   wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel
19646   attribute \enum_base_type "RC"
19647   attribute \enum_value_00 "NONE"
19648   attribute \enum_value_01 "ONE"
19649   attribute \enum_value_10 "RC"
19650   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19651   wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel
19652   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19653   wire \dec31_dec_sub11_dec31_dec_sub11_rsrv
19654   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19655   wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe
19656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19657   wire \dec31_dec_sub11_dec31_dec_sub11_sgn
19658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19659   wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext
19660   attribute \enum_base_type "LDSTMode"
19661   attribute \enum_value_00 "NONE"
19662   attribute \enum_value_01 "update"
19663   attribute \enum_value_10 "cix"
19664   attribute \enum_value_11 "cx"
19665   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19666   wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd
19667   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
19668   wire width 32 \dec31_dec_sub11_opcode_in
19669   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19670   wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode
19671   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19672   wire \dec31_dec_sub15_dec31_dec_sub15_br
19673   attribute \enum_base_type "CRInSel"
19674   attribute \enum_value_000 "NONE"
19675   attribute \enum_value_001 "CR0"
19676   attribute \enum_value_010 "BI"
19677   attribute \enum_value_011 "BFA"
19678   attribute \enum_value_100 "BA_BB"
19679   attribute \enum_value_101 "BC"
19680   attribute \enum_value_110 "WHOLE_REG"
19681   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19682   wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in
19683   attribute \enum_base_type "CROutSel"
19684   attribute \enum_value_000 "NONE"
19685   attribute \enum_value_001 "CR0"
19686   attribute \enum_value_010 "BF"
19687   attribute \enum_value_011 "BT"
19688   attribute \enum_value_100 "WHOLE_REG"
19689   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19690   wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out
19691   attribute \enum_base_type "CryIn"
19692   attribute \enum_value_00 "ZERO"
19693   attribute \enum_value_01 "ONE"
19694   attribute \enum_value_10 "CA"
19695   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19696   wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in
19697   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19698   wire \dec31_dec_sub15_dec31_dec_sub15_cry_out
19699   attribute \enum_base_type "Form"
19700   attribute \enum_value_00000 "NONE"
19701   attribute \enum_value_00001 "I"
19702   attribute \enum_value_00010 "B"
19703   attribute \enum_value_00011 "SC"
19704   attribute \enum_value_00100 "D"
19705   attribute \enum_value_00101 "DS"
19706   attribute \enum_value_00110 "DQ"
19707   attribute \enum_value_00111 "DX"
19708   attribute \enum_value_01000 "X"
19709   attribute \enum_value_01001 "XL"
19710   attribute \enum_value_01010 "XFX"
19711   attribute \enum_value_01011 "XFL"
19712   attribute \enum_value_01100 "XX1"
19713   attribute \enum_value_01101 "XX2"
19714   attribute \enum_value_01110 "XX3"
19715   attribute \enum_value_01111 "XX4"
19716   attribute \enum_value_10000 "XS"
19717   attribute \enum_value_10001 "XO"
19718   attribute \enum_value_10010 "A"
19719   attribute \enum_value_10011 "M"
19720   attribute \enum_value_10100 "MD"
19721   attribute \enum_value_10101 "MDS"
19722   attribute \enum_value_10110 "VA"
19723   attribute \enum_value_10111 "VC"
19724   attribute \enum_value_11000 "VX"
19725   attribute \enum_value_11001 "EVX"
19726   attribute \enum_value_11010 "EVS"
19727   attribute \enum_value_11011 "Z22"
19728   attribute \enum_value_11100 "Z23"
19729   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19730   wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form
19731   attribute \enum_base_type "Function"
19732   attribute \enum_value_000000000000 "NONE"
19733   attribute \enum_value_000000000010 "ALU"
19734   attribute \enum_value_000000000100 "LDST"
19735   attribute \enum_value_000000001000 "SHIFT_ROT"
19736   attribute \enum_value_000000010000 "LOGICAL"
19737   attribute \enum_value_000000100000 "BRANCH"
19738   attribute \enum_value_000001000000 "CR"
19739   attribute \enum_value_000010000000 "TRAP"
19740   attribute \enum_value_000100000000 "MUL"
19741   attribute \enum_value_001000000000 "DIV"
19742   attribute \enum_value_010000000000 "SPR"
19743   attribute \enum_value_100000000000 "MMU"
19744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19745   wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit
19746   attribute \enum_base_type "In1Sel"
19747   attribute \enum_value_000 "NONE"
19748   attribute \enum_value_001 "RA"
19749   attribute \enum_value_010 "RA_OR_ZERO"
19750   attribute \enum_value_011 "SPR"
19751   attribute \enum_value_100 "RS"
19752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19753   wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel
19754   attribute \enum_base_type "In2Sel"
19755   attribute \enum_value_0000 "NONE"
19756   attribute \enum_value_0001 "RB"
19757   attribute \enum_value_0010 "CONST_UI"
19758   attribute \enum_value_0011 "CONST_SI"
19759   attribute \enum_value_0100 "CONST_UI_HI"
19760   attribute \enum_value_0101 "CONST_SI_HI"
19761   attribute \enum_value_0110 "CONST_LI"
19762   attribute \enum_value_0111 "CONST_BD"
19763   attribute \enum_value_1000 "CONST_DS"
19764   attribute \enum_value_1001 "CONST_M1"
19765   attribute \enum_value_1010 "CONST_SH"
19766   attribute \enum_value_1011 "CONST_SH32"
19767   attribute \enum_value_1100 "SPR"
19768   attribute \enum_value_1101 "RS"
19769   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19770   wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel
19771   attribute \enum_base_type "In3Sel"
19772   attribute \enum_value_00 "NONE"
19773   attribute \enum_value_01 "RS"
19774   attribute \enum_value_10 "RB"
19775   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19776   wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel
19777   attribute \enum_base_type "MicrOp"
19778   attribute \enum_value_0000000 "OP_ILLEGAL"
19779   attribute \enum_value_0000001 "OP_NOP"
19780   attribute \enum_value_0000010 "OP_ADD"
19781   attribute \enum_value_0000011 "OP_ADDPCIS"
19782   attribute \enum_value_0000100 "OP_AND"
19783   attribute \enum_value_0000101 "OP_ATTN"
19784   attribute \enum_value_0000110 "OP_B"
19785   attribute \enum_value_0000111 "OP_BC"
19786   attribute \enum_value_0001000 "OP_BCREG"
19787   attribute \enum_value_0001001 "OP_BPERM"
19788   attribute \enum_value_0001010 "OP_CMP"
19789   attribute \enum_value_0001011 "OP_CMPB"
19790   attribute \enum_value_0001100 "OP_CMPEQB"
19791   attribute \enum_value_0001101 "OP_CMPRB"
19792   attribute \enum_value_0001110 "OP_CNTZ"
19793   attribute \enum_value_0001111 "OP_CRAND"
19794   attribute \enum_value_0010000 "OP_CRANDC"
19795   attribute \enum_value_0010001 "OP_CREQV"
19796   attribute \enum_value_0010010 "OP_CRNAND"
19797   attribute \enum_value_0010011 "OP_CRNOR"
19798   attribute \enum_value_0010100 "OP_CROR"
19799   attribute \enum_value_0010101 "OP_CRORC"
19800   attribute \enum_value_0010110 "OP_CRXOR"
19801   attribute \enum_value_0010111 "OP_DARN"
19802   attribute \enum_value_0011000 "OP_DCBF"
19803   attribute \enum_value_0011001 "OP_DCBST"
19804   attribute \enum_value_0011010 "OP_DCBT"
19805   attribute \enum_value_0011011 "OP_DCBTST"
19806   attribute \enum_value_0011100 "OP_DCBZ"
19807   attribute \enum_value_0011101 "OP_DIV"
19808   attribute \enum_value_0011110 "OP_DIVE"
19809   attribute \enum_value_0011111 "OP_EXTS"
19810   attribute \enum_value_0100000 "OP_EXTSWSLI"
19811   attribute \enum_value_0100001 "OP_ICBI"
19812   attribute \enum_value_0100010 "OP_ICBT"
19813   attribute \enum_value_0100011 "OP_ISEL"
19814   attribute \enum_value_0100100 "OP_ISYNC"
19815   attribute \enum_value_0100101 "OP_LOAD"
19816   attribute \enum_value_0100110 "OP_STORE"
19817   attribute \enum_value_0100111 "OP_MADDHD"
19818   attribute \enum_value_0101000 "OP_MADDHDU"
19819   attribute \enum_value_0101001 "OP_MADDLD"
19820   attribute \enum_value_0101010 "OP_MCRF"
19821   attribute \enum_value_0101011 "OP_MCRXR"
19822   attribute \enum_value_0101100 "OP_MCRXRX"
19823   attribute \enum_value_0101101 "OP_MFCR"
19824   attribute \enum_value_0101110 "OP_MFSPR"
19825   attribute \enum_value_0101111 "OP_MOD"
19826   attribute \enum_value_0110000 "OP_MTCRF"
19827   attribute \enum_value_0110001 "OP_MTSPR"
19828   attribute \enum_value_0110010 "OP_MUL_L64"
19829   attribute \enum_value_0110011 "OP_MUL_H64"
19830   attribute \enum_value_0110100 "OP_MUL_H32"
19831   attribute \enum_value_0110101 "OP_OR"
19832   attribute \enum_value_0110110 "OP_POPCNT"
19833   attribute \enum_value_0110111 "OP_PRTY"
19834   attribute \enum_value_0111000 "OP_RLC"
19835   attribute \enum_value_0111001 "OP_RLCL"
19836   attribute \enum_value_0111010 "OP_RLCR"
19837   attribute \enum_value_0111011 "OP_SETB"
19838   attribute \enum_value_0111100 "OP_SHL"
19839   attribute \enum_value_0111101 "OP_SHR"
19840   attribute \enum_value_0111110 "OP_SYNC"
19841   attribute \enum_value_0111111 "OP_TRAP"
19842   attribute \enum_value_1000011 "OP_XOR"
19843   attribute \enum_value_1000100 "OP_SIM_CONFIG"
19844   attribute \enum_value_1000101 "OP_CROP"
19845   attribute \enum_value_1000110 "OP_RFID"
19846   attribute \enum_value_1000111 "OP_MFMSR"
19847   attribute \enum_value_1001000 "OP_MTMSRD"
19848   attribute \enum_value_1001001 "OP_SC"
19849   attribute \enum_value_1001010 "OP_MTMSR"
19850   attribute \enum_value_1001011 "OP_TLBIE"
19851   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19852   wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op
19853   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19854   wire \dec31_dec_sub15_dec31_dec_sub15_inv_a
19855   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19856   wire \dec31_dec_sub15_dec31_dec_sub15_inv_out
19857   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19858   wire \dec31_dec_sub15_dec31_dec_sub15_is_32b
19859   attribute \enum_base_type "LdstLen"
19860   attribute \enum_value_0000 "NONE"
19861   attribute \enum_value_0001 "is1B"
19862   attribute \enum_value_0010 "is2B"
19863   attribute \enum_value_0100 "is4B"
19864   attribute \enum_value_1000 "is8B"
19865   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19866   wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len
19867   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19868   wire \dec31_dec_sub15_dec31_dec_sub15_lk
19869   attribute \enum_base_type "OutSel"
19870   attribute \enum_value_00 "NONE"
19871   attribute \enum_value_01 "RT"
19872   attribute \enum_value_10 "RA"
19873   attribute \enum_value_11 "SPR"
19874   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19875   wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel
19876   attribute \enum_base_type "RC"
19877   attribute \enum_value_00 "NONE"
19878   attribute \enum_value_01 "ONE"
19879   attribute \enum_value_10 "RC"
19880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19881   wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel
19882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19883   wire \dec31_dec_sub15_dec31_dec_sub15_rsrv
19884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19885   wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe
19886   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19887   wire \dec31_dec_sub15_dec31_dec_sub15_sgn
19888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19889   wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext
19890   attribute \enum_base_type "LDSTMode"
19891   attribute \enum_value_00 "NONE"
19892   attribute \enum_value_01 "update"
19893   attribute \enum_value_10 "cix"
19894   attribute \enum_value_11 "cx"
19895   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19896   wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd
19897   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
19898   wire width 32 \dec31_dec_sub15_opcode_in
19899   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19900   wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode
19901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19902   wire \dec31_dec_sub16_dec31_dec_sub16_br
19903   attribute \enum_base_type "CRInSel"
19904   attribute \enum_value_000 "NONE"
19905   attribute \enum_value_001 "CR0"
19906   attribute \enum_value_010 "BI"
19907   attribute \enum_value_011 "BFA"
19908   attribute \enum_value_100 "BA_BB"
19909   attribute \enum_value_101 "BC"
19910   attribute \enum_value_110 "WHOLE_REG"
19911   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19912   wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in
19913   attribute \enum_base_type "CROutSel"
19914   attribute \enum_value_000 "NONE"
19915   attribute \enum_value_001 "CR0"
19916   attribute \enum_value_010 "BF"
19917   attribute \enum_value_011 "BT"
19918   attribute \enum_value_100 "WHOLE_REG"
19919   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19920   wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out
19921   attribute \enum_base_type "CryIn"
19922   attribute \enum_value_00 "ZERO"
19923   attribute \enum_value_01 "ONE"
19924   attribute \enum_value_10 "CA"
19925   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19926   wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in
19927   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
19928   wire \dec31_dec_sub16_dec31_dec_sub16_cry_out
19929   attribute \enum_base_type "Form"
19930   attribute \enum_value_00000 "NONE"
19931   attribute \enum_value_00001 "I"
19932   attribute \enum_value_00010 "B"
19933   attribute \enum_value_00011 "SC"
19934   attribute \enum_value_00100 "D"
19935   attribute \enum_value_00101 "DS"
19936   attribute \enum_value_00110 "DQ"
19937   attribute \enum_value_00111 "DX"
19938   attribute \enum_value_01000 "X"
19939   attribute \enum_value_01001 "XL"
19940   attribute \enum_value_01010 "XFX"
19941   attribute \enum_value_01011 "XFL"
19942   attribute \enum_value_01100 "XX1"
19943   attribute \enum_value_01101 "XX2"
19944   attribute \enum_value_01110 "XX3"
19945   attribute \enum_value_01111 "XX4"
19946   attribute \enum_value_10000 "XS"
19947   attribute \enum_value_10001 "XO"
19948   attribute \enum_value_10010 "A"
19949   attribute \enum_value_10011 "M"
19950   attribute \enum_value_10100 "MD"
19951   attribute \enum_value_10101 "MDS"
19952   attribute \enum_value_10110 "VA"
19953   attribute \enum_value_10111 "VC"
19954   attribute \enum_value_11000 "VX"
19955   attribute \enum_value_11001 "EVX"
19956   attribute \enum_value_11010 "EVS"
19957   attribute \enum_value_11011 "Z22"
19958   attribute \enum_value_11100 "Z23"
19959   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19960   wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form
19961   attribute \enum_base_type "Function"
19962   attribute \enum_value_000000000000 "NONE"
19963   attribute \enum_value_000000000010 "ALU"
19964   attribute \enum_value_000000000100 "LDST"
19965   attribute \enum_value_000000001000 "SHIFT_ROT"
19966   attribute \enum_value_000000010000 "LOGICAL"
19967   attribute \enum_value_000000100000 "BRANCH"
19968   attribute \enum_value_000001000000 "CR"
19969   attribute \enum_value_000010000000 "TRAP"
19970   attribute \enum_value_000100000000 "MUL"
19971   attribute \enum_value_001000000000 "DIV"
19972   attribute \enum_value_010000000000 "SPR"
19973   attribute \enum_value_100000000000 "MMU"
19974   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19975   wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit
19976   attribute \enum_base_type "In1Sel"
19977   attribute \enum_value_000 "NONE"
19978   attribute \enum_value_001 "RA"
19979   attribute \enum_value_010 "RA_OR_ZERO"
19980   attribute \enum_value_011 "SPR"
19981   attribute \enum_value_100 "RS"
19982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
19983   wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel
19984   attribute \enum_base_type "In2Sel"
19985   attribute \enum_value_0000 "NONE"
19986   attribute \enum_value_0001 "RB"
19987   attribute \enum_value_0010 "CONST_UI"
19988   attribute \enum_value_0011 "CONST_SI"
19989   attribute \enum_value_0100 "CONST_UI_HI"
19990   attribute \enum_value_0101 "CONST_SI_HI"
19991   attribute \enum_value_0110 "CONST_LI"
19992   attribute \enum_value_0111 "CONST_BD"
19993   attribute \enum_value_1000 "CONST_DS"
19994   attribute \enum_value_1001 "CONST_M1"
19995   attribute \enum_value_1010 "CONST_SH"
19996   attribute \enum_value_1011 "CONST_SH32"
19997   attribute \enum_value_1100 "SPR"
19998   attribute \enum_value_1101 "RS"
19999   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20000   wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel
20001   attribute \enum_base_type "In3Sel"
20002   attribute \enum_value_00 "NONE"
20003   attribute \enum_value_01 "RS"
20004   attribute \enum_value_10 "RB"
20005   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20006   wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel
20007   attribute \enum_base_type "MicrOp"
20008   attribute \enum_value_0000000 "OP_ILLEGAL"
20009   attribute \enum_value_0000001 "OP_NOP"
20010   attribute \enum_value_0000010 "OP_ADD"
20011   attribute \enum_value_0000011 "OP_ADDPCIS"
20012   attribute \enum_value_0000100 "OP_AND"
20013   attribute \enum_value_0000101 "OP_ATTN"
20014   attribute \enum_value_0000110 "OP_B"
20015   attribute \enum_value_0000111 "OP_BC"
20016   attribute \enum_value_0001000 "OP_BCREG"
20017   attribute \enum_value_0001001 "OP_BPERM"
20018   attribute \enum_value_0001010 "OP_CMP"
20019   attribute \enum_value_0001011 "OP_CMPB"
20020   attribute \enum_value_0001100 "OP_CMPEQB"
20021   attribute \enum_value_0001101 "OP_CMPRB"
20022   attribute \enum_value_0001110 "OP_CNTZ"
20023   attribute \enum_value_0001111 "OP_CRAND"
20024   attribute \enum_value_0010000 "OP_CRANDC"
20025   attribute \enum_value_0010001 "OP_CREQV"
20026   attribute \enum_value_0010010 "OP_CRNAND"
20027   attribute \enum_value_0010011 "OP_CRNOR"
20028   attribute \enum_value_0010100 "OP_CROR"
20029   attribute \enum_value_0010101 "OP_CRORC"
20030   attribute \enum_value_0010110 "OP_CRXOR"
20031   attribute \enum_value_0010111 "OP_DARN"
20032   attribute \enum_value_0011000 "OP_DCBF"
20033   attribute \enum_value_0011001 "OP_DCBST"
20034   attribute \enum_value_0011010 "OP_DCBT"
20035   attribute \enum_value_0011011 "OP_DCBTST"
20036   attribute \enum_value_0011100 "OP_DCBZ"
20037   attribute \enum_value_0011101 "OP_DIV"
20038   attribute \enum_value_0011110 "OP_DIVE"
20039   attribute \enum_value_0011111 "OP_EXTS"
20040   attribute \enum_value_0100000 "OP_EXTSWSLI"
20041   attribute \enum_value_0100001 "OP_ICBI"
20042   attribute \enum_value_0100010 "OP_ICBT"
20043   attribute \enum_value_0100011 "OP_ISEL"
20044   attribute \enum_value_0100100 "OP_ISYNC"
20045   attribute \enum_value_0100101 "OP_LOAD"
20046   attribute \enum_value_0100110 "OP_STORE"
20047   attribute \enum_value_0100111 "OP_MADDHD"
20048   attribute \enum_value_0101000 "OP_MADDHDU"
20049   attribute \enum_value_0101001 "OP_MADDLD"
20050   attribute \enum_value_0101010 "OP_MCRF"
20051   attribute \enum_value_0101011 "OP_MCRXR"
20052   attribute \enum_value_0101100 "OP_MCRXRX"
20053   attribute \enum_value_0101101 "OP_MFCR"
20054   attribute \enum_value_0101110 "OP_MFSPR"
20055   attribute \enum_value_0101111 "OP_MOD"
20056   attribute \enum_value_0110000 "OP_MTCRF"
20057   attribute \enum_value_0110001 "OP_MTSPR"
20058   attribute \enum_value_0110010 "OP_MUL_L64"
20059   attribute \enum_value_0110011 "OP_MUL_H64"
20060   attribute \enum_value_0110100 "OP_MUL_H32"
20061   attribute \enum_value_0110101 "OP_OR"
20062   attribute \enum_value_0110110 "OP_POPCNT"
20063   attribute \enum_value_0110111 "OP_PRTY"
20064   attribute \enum_value_0111000 "OP_RLC"
20065   attribute \enum_value_0111001 "OP_RLCL"
20066   attribute \enum_value_0111010 "OP_RLCR"
20067   attribute \enum_value_0111011 "OP_SETB"
20068   attribute \enum_value_0111100 "OP_SHL"
20069   attribute \enum_value_0111101 "OP_SHR"
20070   attribute \enum_value_0111110 "OP_SYNC"
20071   attribute \enum_value_0111111 "OP_TRAP"
20072   attribute \enum_value_1000011 "OP_XOR"
20073   attribute \enum_value_1000100 "OP_SIM_CONFIG"
20074   attribute \enum_value_1000101 "OP_CROP"
20075   attribute \enum_value_1000110 "OP_RFID"
20076   attribute \enum_value_1000111 "OP_MFMSR"
20077   attribute \enum_value_1001000 "OP_MTMSRD"
20078   attribute \enum_value_1001001 "OP_SC"
20079   attribute \enum_value_1001010 "OP_MTMSR"
20080   attribute \enum_value_1001011 "OP_TLBIE"
20081   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20082   wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op
20083   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20084   wire \dec31_dec_sub16_dec31_dec_sub16_inv_a
20085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20086   wire \dec31_dec_sub16_dec31_dec_sub16_inv_out
20087   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20088   wire \dec31_dec_sub16_dec31_dec_sub16_is_32b
20089   attribute \enum_base_type "LdstLen"
20090   attribute \enum_value_0000 "NONE"
20091   attribute \enum_value_0001 "is1B"
20092   attribute \enum_value_0010 "is2B"
20093   attribute \enum_value_0100 "is4B"
20094   attribute \enum_value_1000 "is8B"
20095   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20096   wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len
20097   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20098   wire \dec31_dec_sub16_dec31_dec_sub16_lk
20099   attribute \enum_base_type "OutSel"
20100   attribute \enum_value_00 "NONE"
20101   attribute \enum_value_01 "RT"
20102   attribute \enum_value_10 "RA"
20103   attribute \enum_value_11 "SPR"
20104   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20105   wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel
20106   attribute \enum_base_type "RC"
20107   attribute \enum_value_00 "NONE"
20108   attribute \enum_value_01 "ONE"
20109   attribute \enum_value_10 "RC"
20110   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20111   wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel
20112   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20113   wire \dec31_dec_sub16_dec31_dec_sub16_rsrv
20114   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20115   wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe
20116   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20117   wire \dec31_dec_sub16_dec31_dec_sub16_sgn
20118   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20119   wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext
20120   attribute \enum_base_type "LDSTMode"
20121   attribute \enum_value_00 "NONE"
20122   attribute \enum_value_01 "update"
20123   attribute \enum_value_10 "cix"
20124   attribute \enum_value_11 "cx"
20125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20126   wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd
20127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
20128   wire width 32 \dec31_dec_sub16_opcode_in
20129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20130   wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode
20131   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20132   wire \dec31_dec_sub18_dec31_dec_sub18_br
20133   attribute \enum_base_type "CRInSel"
20134   attribute \enum_value_000 "NONE"
20135   attribute \enum_value_001 "CR0"
20136   attribute \enum_value_010 "BI"
20137   attribute \enum_value_011 "BFA"
20138   attribute \enum_value_100 "BA_BB"
20139   attribute \enum_value_101 "BC"
20140   attribute \enum_value_110 "WHOLE_REG"
20141   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20142   wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in
20143   attribute \enum_base_type "CROutSel"
20144   attribute \enum_value_000 "NONE"
20145   attribute \enum_value_001 "CR0"
20146   attribute \enum_value_010 "BF"
20147   attribute \enum_value_011 "BT"
20148   attribute \enum_value_100 "WHOLE_REG"
20149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20150   wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out
20151   attribute \enum_base_type "CryIn"
20152   attribute \enum_value_00 "ZERO"
20153   attribute \enum_value_01 "ONE"
20154   attribute \enum_value_10 "CA"
20155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20156   wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in
20157   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20158   wire \dec31_dec_sub18_dec31_dec_sub18_cry_out
20159   attribute \enum_base_type "Form"
20160   attribute \enum_value_00000 "NONE"
20161   attribute \enum_value_00001 "I"
20162   attribute \enum_value_00010 "B"
20163   attribute \enum_value_00011 "SC"
20164   attribute \enum_value_00100 "D"
20165   attribute \enum_value_00101 "DS"
20166   attribute \enum_value_00110 "DQ"
20167   attribute \enum_value_00111 "DX"
20168   attribute \enum_value_01000 "X"
20169   attribute \enum_value_01001 "XL"
20170   attribute \enum_value_01010 "XFX"
20171   attribute \enum_value_01011 "XFL"
20172   attribute \enum_value_01100 "XX1"
20173   attribute \enum_value_01101 "XX2"
20174   attribute \enum_value_01110 "XX3"
20175   attribute \enum_value_01111 "XX4"
20176   attribute \enum_value_10000 "XS"
20177   attribute \enum_value_10001 "XO"
20178   attribute \enum_value_10010 "A"
20179   attribute \enum_value_10011 "M"
20180   attribute \enum_value_10100 "MD"
20181   attribute \enum_value_10101 "MDS"
20182   attribute \enum_value_10110 "VA"
20183   attribute \enum_value_10111 "VC"
20184   attribute \enum_value_11000 "VX"
20185   attribute \enum_value_11001 "EVX"
20186   attribute \enum_value_11010 "EVS"
20187   attribute \enum_value_11011 "Z22"
20188   attribute \enum_value_11100 "Z23"
20189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20190   wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form
20191   attribute \enum_base_type "Function"
20192   attribute \enum_value_000000000000 "NONE"
20193   attribute \enum_value_000000000010 "ALU"
20194   attribute \enum_value_000000000100 "LDST"
20195   attribute \enum_value_000000001000 "SHIFT_ROT"
20196   attribute \enum_value_000000010000 "LOGICAL"
20197   attribute \enum_value_000000100000 "BRANCH"
20198   attribute \enum_value_000001000000 "CR"
20199   attribute \enum_value_000010000000 "TRAP"
20200   attribute \enum_value_000100000000 "MUL"
20201   attribute \enum_value_001000000000 "DIV"
20202   attribute \enum_value_010000000000 "SPR"
20203   attribute \enum_value_100000000000 "MMU"
20204   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20205   wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit
20206   attribute \enum_base_type "In1Sel"
20207   attribute \enum_value_000 "NONE"
20208   attribute \enum_value_001 "RA"
20209   attribute \enum_value_010 "RA_OR_ZERO"
20210   attribute \enum_value_011 "SPR"
20211   attribute \enum_value_100 "RS"
20212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20213   wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel
20214   attribute \enum_base_type "In2Sel"
20215   attribute \enum_value_0000 "NONE"
20216   attribute \enum_value_0001 "RB"
20217   attribute \enum_value_0010 "CONST_UI"
20218   attribute \enum_value_0011 "CONST_SI"
20219   attribute \enum_value_0100 "CONST_UI_HI"
20220   attribute \enum_value_0101 "CONST_SI_HI"
20221   attribute \enum_value_0110 "CONST_LI"
20222   attribute \enum_value_0111 "CONST_BD"
20223   attribute \enum_value_1000 "CONST_DS"
20224   attribute \enum_value_1001 "CONST_M1"
20225   attribute \enum_value_1010 "CONST_SH"
20226   attribute \enum_value_1011 "CONST_SH32"
20227   attribute \enum_value_1100 "SPR"
20228   attribute \enum_value_1101 "RS"
20229   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20230   wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel
20231   attribute \enum_base_type "In3Sel"
20232   attribute \enum_value_00 "NONE"
20233   attribute \enum_value_01 "RS"
20234   attribute \enum_value_10 "RB"
20235   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20236   wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel
20237   attribute \enum_base_type "MicrOp"
20238   attribute \enum_value_0000000 "OP_ILLEGAL"
20239   attribute \enum_value_0000001 "OP_NOP"
20240   attribute \enum_value_0000010 "OP_ADD"
20241   attribute \enum_value_0000011 "OP_ADDPCIS"
20242   attribute \enum_value_0000100 "OP_AND"
20243   attribute \enum_value_0000101 "OP_ATTN"
20244   attribute \enum_value_0000110 "OP_B"
20245   attribute \enum_value_0000111 "OP_BC"
20246   attribute \enum_value_0001000 "OP_BCREG"
20247   attribute \enum_value_0001001 "OP_BPERM"
20248   attribute \enum_value_0001010 "OP_CMP"
20249   attribute \enum_value_0001011 "OP_CMPB"
20250   attribute \enum_value_0001100 "OP_CMPEQB"
20251   attribute \enum_value_0001101 "OP_CMPRB"
20252   attribute \enum_value_0001110 "OP_CNTZ"
20253   attribute \enum_value_0001111 "OP_CRAND"
20254   attribute \enum_value_0010000 "OP_CRANDC"
20255   attribute \enum_value_0010001 "OP_CREQV"
20256   attribute \enum_value_0010010 "OP_CRNAND"
20257   attribute \enum_value_0010011 "OP_CRNOR"
20258   attribute \enum_value_0010100 "OP_CROR"
20259   attribute \enum_value_0010101 "OP_CRORC"
20260   attribute \enum_value_0010110 "OP_CRXOR"
20261   attribute \enum_value_0010111 "OP_DARN"
20262   attribute \enum_value_0011000 "OP_DCBF"
20263   attribute \enum_value_0011001 "OP_DCBST"
20264   attribute \enum_value_0011010 "OP_DCBT"
20265   attribute \enum_value_0011011 "OP_DCBTST"
20266   attribute \enum_value_0011100 "OP_DCBZ"
20267   attribute \enum_value_0011101 "OP_DIV"
20268   attribute \enum_value_0011110 "OP_DIVE"
20269   attribute \enum_value_0011111 "OP_EXTS"
20270   attribute \enum_value_0100000 "OP_EXTSWSLI"
20271   attribute \enum_value_0100001 "OP_ICBI"
20272   attribute \enum_value_0100010 "OP_ICBT"
20273   attribute \enum_value_0100011 "OP_ISEL"
20274   attribute \enum_value_0100100 "OP_ISYNC"
20275   attribute \enum_value_0100101 "OP_LOAD"
20276   attribute \enum_value_0100110 "OP_STORE"
20277   attribute \enum_value_0100111 "OP_MADDHD"
20278   attribute \enum_value_0101000 "OP_MADDHDU"
20279   attribute \enum_value_0101001 "OP_MADDLD"
20280   attribute \enum_value_0101010 "OP_MCRF"
20281   attribute \enum_value_0101011 "OP_MCRXR"
20282   attribute \enum_value_0101100 "OP_MCRXRX"
20283   attribute \enum_value_0101101 "OP_MFCR"
20284   attribute \enum_value_0101110 "OP_MFSPR"
20285   attribute \enum_value_0101111 "OP_MOD"
20286   attribute \enum_value_0110000 "OP_MTCRF"
20287   attribute \enum_value_0110001 "OP_MTSPR"
20288   attribute \enum_value_0110010 "OP_MUL_L64"
20289   attribute \enum_value_0110011 "OP_MUL_H64"
20290   attribute \enum_value_0110100 "OP_MUL_H32"
20291   attribute \enum_value_0110101 "OP_OR"
20292   attribute \enum_value_0110110 "OP_POPCNT"
20293   attribute \enum_value_0110111 "OP_PRTY"
20294   attribute \enum_value_0111000 "OP_RLC"
20295   attribute \enum_value_0111001 "OP_RLCL"
20296   attribute \enum_value_0111010 "OP_RLCR"
20297   attribute \enum_value_0111011 "OP_SETB"
20298   attribute \enum_value_0111100 "OP_SHL"
20299   attribute \enum_value_0111101 "OP_SHR"
20300   attribute \enum_value_0111110 "OP_SYNC"
20301   attribute \enum_value_0111111 "OP_TRAP"
20302   attribute \enum_value_1000011 "OP_XOR"
20303   attribute \enum_value_1000100 "OP_SIM_CONFIG"
20304   attribute \enum_value_1000101 "OP_CROP"
20305   attribute \enum_value_1000110 "OP_RFID"
20306   attribute \enum_value_1000111 "OP_MFMSR"
20307   attribute \enum_value_1001000 "OP_MTMSRD"
20308   attribute \enum_value_1001001 "OP_SC"
20309   attribute \enum_value_1001010 "OP_MTMSR"
20310   attribute \enum_value_1001011 "OP_TLBIE"
20311   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20312   wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op
20313   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20314   wire \dec31_dec_sub18_dec31_dec_sub18_inv_a
20315   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20316   wire \dec31_dec_sub18_dec31_dec_sub18_inv_out
20317   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20318   wire \dec31_dec_sub18_dec31_dec_sub18_is_32b
20319   attribute \enum_base_type "LdstLen"
20320   attribute \enum_value_0000 "NONE"
20321   attribute \enum_value_0001 "is1B"
20322   attribute \enum_value_0010 "is2B"
20323   attribute \enum_value_0100 "is4B"
20324   attribute \enum_value_1000 "is8B"
20325   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20326   wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len
20327   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20328   wire \dec31_dec_sub18_dec31_dec_sub18_lk
20329   attribute \enum_base_type "OutSel"
20330   attribute \enum_value_00 "NONE"
20331   attribute \enum_value_01 "RT"
20332   attribute \enum_value_10 "RA"
20333   attribute \enum_value_11 "SPR"
20334   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20335   wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel
20336   attribute \enum_base_type "RC"
20337   attribute \enum_value_00 "NONE"
20338   attribute \enum_value_01 "ONE"
20339   attribute \enum_value_10 "RC"
20340   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20341   wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel
20342   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20343   wire \dec31_dec_sub18_dec31_dec_sub18_rsrv
20344   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20345   wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe
20346   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20347   wire \dec31_dec_sub18_dec31_dec_sub18_sgn
20348   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20349   wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext
20350   attribute \enum_base_type "LDSTMode"
20351   attribute \enum_value_00 "NONE"
20352   attribute \enum_value_01 "update"
20353   attribute \enum_value_10 "cix"
20354   attribute \enum_value_11 "cx"
20355   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20356   wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd
20357   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
20358   wire width 32 \dec31_dec_sub18_opcode_in
20359   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20360   wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode
20361   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20362   wire \dec31_dec_sub19_dec31_dec_sub19_br
20363   attribute \enum_base_type "CRInSel"
20364   attribute \enum_value_000 "NONE"
20365   attribute \enum_value_001 "CR0"
20366   attribute \enum_value_010 "BI"
20367   attribute \enum_value_011 "BFA"
20368   attribute \enum_value_100 "BA_BB"
20369   attribute \enum_value_101 "BC"
20370   attribute \enum_value_110 "WHOLE_REG"
20371   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20372   wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in
20373   attribute \enum_base_type "CROutSel"
20374   attribute \enum_value_000 "NONE"
20375   attribute \enum_value_001 "CR0"
20376   attribute \enum_value_010 "BF"
20377   attribute \enum_value_011 "BT"
20378   attribute \enum_value_100 "WHOLE_REG"
20379   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20380   wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out
20381   attribute \enum_base_type "CryIn"
20382   attribute \enum_value_00 "ZERO"
20383   attribute \enum_value_01 "ONE"
20384   attribute \enum_value_10 "CA"
20385   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20386   wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in
20387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20388   wire \dec31_dec_sub19_dec31_dec_sub19_cry_out
20389   attribute \enum_base_type "Form"
20390   attribute \enum_value_00000 "NONE"
20391   attribute \enum_value_00001 "I"
20392   attribute \enum_value_00010 "B"
20393   attribute \enum_value_00011 "SC"
20394   attribute \enum_value_00100 "D"
20395   attribute \enum_value_00101 "DS"
20396   attribute \enum_value_00110 "DQ"
20397   attribute \enum_value_00111 "DX"
20398   attribute \enum_value_01000 "X"
20399   attribute \enum_value_01001 "XL"
20400   attribute \enum_value_01010 "XFX"
20401   attribute \enum_value_01011 "XFL"
20402   attribute \enum_value_01100 "XX1"
20403   attribute \enum_value_01101 "XX2"
20404   attribute \enum_value_01110 "XX3"
20405   attribute \enum_value_01111 "XX4"
20406   attribute \enum_value_10000 "XS"
20407   attribute \enum_value_10001 "XO"
20408   attribute \enum_value_10010 "A"
20409   attribute \enum_value_10011 "M"
20410   attribute \enum_value_10100 "MD"
20411   attribute \enum_value_10101 "MDS"
20412   attribute \enum_value_10110 "VA"
20413   attribute \enum_value_10111 "VC"
20414   attribute \enum_value_11000 "VX"
20415   attribute \enum_value_11001 "EVX"
20416   attribute \enum_value_11010 "EVS"
20417   attribute \enum_value_11011 "Z22"
20418   attribute \enum_value_11100 "Z23"
20419   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20420   wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form
20421   attribute \enum_base_type "Function"
20422   attribute \enum_value_000000000000 "NONE"
20423   attribute \enum_value_000000000010 "ALU"
20424   attribute \enum_value_000000000100 "LDST"
20425   attribute \enum_value_000000001000 "SHIFT_ROT"
20426   attribute \enum_value_000000010000 "LOGICAL"
20427   attribute \enum_value_000000100000 "BRANCH"
20428   attribute \enum_value_000001000000 "CR"
20429   attribute \enum_value_000010000000 "TRAP"
20430   attribute \enum_value_000100000000 "MUL"
20431   attribute \enum_value_001000000000 "DIV"
20432   attribute \enum_value_010000000000 "SPR"
20433   attribute \enum_value_100000000000 "MMU"
20434   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20435   wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit
20436   attribute \enum_base_type "In1Sel"
20437   attribute \enum_value_000 "NONE"
20438   attribute \enum_value_001 "RA"
20439   attribute \enum_value_010 "RA_OR_ZERO"
20440   attribute \enum_value_011 "SPR"
20441   attribute \enum_value_100 "RS"
20442   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20443   wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel
20444   attribute \enum_base_type "In2Sel"
20445   attribute \enum_value_0000 "NONE"
20446   attribute \enum_value_0001 "RB"
20447   attribute \enum_value_0010 "CONST_UI"
20448   attribute \enum_value_0011 "CONST_SI"
20449   attribute \enum_value_0100 "CONST_UI_HI"
20450   attribute \enum_value_0101 "CONST_SI_HI"
20451   attribute \enum_value_0110 "CONST_LI"
20452   attribute \enum_value_0111 "CONST_BD"
20453   attribute \enum_value_1000 "CONST_DS"
20454   attribute \enum_value_1001 "CONST_M1"
20455   attribute \enum_value_1010 "CONST_SH"
20456   attribute \enum_value_1011 "CONST_SH32"
20457   attribute \enum_value_1100 "SPR"
20458   attribute \enum_value_1101 "RS"
20459   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20460   wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel
20461   attribute \enum_base_type "In3Sel"
20462   attribute \enum_value_00 "NONE"
20463   attribute \enum_value_01 "RS"
20464   attribute \enum_value_10 "RB"
20465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20466   wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel
20467   attribute \enum_base_type "MicrOp"
20468   attribute \enum_value_0000000 "OP_ILLEGAL"
20469   attribute \enum_value_0000001 "OP_NOP"
20470   attribute \enum_value_0000010 "OP_ADD"
20471   attribute \enum_value_0000011 "OP_ADDPCIS"
20472   attribute \enum_value_0000100 "OP_AND"
20473   attribute \enum_value_0000101 "OP_ATTN"
20474   attribute \enum_value_0000110 "OP_B"
20475   attribute \enum_value_0000111 "OP_BC"
20476   attribute \enum_value_0001000 "OP_BCREG"
20477   attribute \enum_value_0001001 "OP_BPERM"
20478   attribute \enum_value_0001010 "OP_CMP"
20479   attribute \enum_value_0001011 "OP_CMPB"
20480   attribute \enum_value_0001100 "OP_CMPEQB"
20481   attribute \enum_value_0001101 "OP_CMPRB"
20482   attribute \enum_value_0001110 "OP_CNTZ"
20483   attribute \enum_value_0001111 "OP_CRAND"
20484   attribute \enum_value_0010000 "OP_CRANDC"
20485   attribute \enum_value_0010001 "OP_CREQV"
20486   attribute \enum_value_0010010 "OP_CRNAND"
20487   attribute \enum_value_0010011 "OP_CRNOR"
20488   attribute \enum_value_0010100 "OP_CROR"
20489   attribute \enum_value_0010101 "OP_CRORC"
20490   attribute \enum_value_0010110 "OP_CRXOR"
20491   attribute \enum_value_0010111 "OP_DARN"
20492   attribute \enum_value_0011000 "OP_DCBF"
20493   attribute \enum_value_0011001 "OP_DCBST"
20494   attribute \enum_value_0011010 "OP_DCBT"
20495   attribute \enum_value_0011011 "OP_DCBTST"
20496   attribute \enum_value_0011100 "OP_DCBZ"
20497   attribute \enum_value_0011101 "OP_DIV"
20498   attribute \enum_value_0011110 "OP_DIVE"
20499   attribute \enum_value_0011111 "OP_EXTS"
20500   attribute \enum_value_0100000 "OP_EXTSWSLI"
20501   attribute \enum_value_0100001 "OP_ICBI"
20502   attribute \enum_value_0100010 "OP_ICBT"
20503   attribute \enum_value_0100011 "OP_ISEL"
20504   attribute \enum_value_0100100 "OP_ISYNC"
20505   attribute \enum_value_0100101 "OP_LOAD"
20506   attribute \enum_value_0100110 "OP_STORE"
20507   attribute \enum_value_0100111 "OP_MADDHD"
20508   attribute \enum_value_0101000 "OP_MADDHDU"
20509   attribute \enum_value_0101001 "OP_MADDLD"
20510   attribute \enum_value_0101010 "OP_MCRF"
20511   attribute \enum_value_0101011 "OP_MCRXR"
20512   attribute \enum_value_0101100 "OP_MCRXRX"
20513   attribute \enum_value_0101101 "OP_MFCR"
20514   attribute \enum_value_0101110 "OP_MFSPR"
20515   attribute \enum_value_0101111 "OP_MOD"
20516   attribute \enum_value_0110000 "OP_MTCRF"
20517   attribute \enum_value_0110001 "OP_MTSPR"
20518   attribute \enum_value_0110010 "OP_MUL_L64"
20519   attribute \enum_value_0110011 "OP_MUL_H64"
20520   attribute \enum_value_0110100 "OP_MUL_H32"
20521   attribute \enum_value_0110101 "OP_OR"
20522   attribute \enum_value_0110110 "OP_POPCNT"
20523   attribute \enum_value_0110111 "OP_PRTY"
20524   attribute \enum_value_0111000 "OP_RLC"
20525   attribute \enum_value_0111001 "OP_RLCL"
20526   attribute \enum_value_0111010 "OP_RLCR"
20527   attribute \enum_value_0111011 "OP_SETB"
20528   attribute \enum_value_0111100 "OP_SHL"
20529   attribute \enum_value_0111101 "OP_SHR"
20530   attribute \enum_value_0111110 "OP_SYNC"
20531   attribute \enum_value_0111111 "OP_TRAP"
20532   attribute \enum_value_1000011 "OP_XOR"
20533   attribute \enum_value_1000100 "OP_SIM_CONFIG"
20534   attribute \enum_value_1000101 "OP_CROP"
20535   attribute \enum_value_1000110 "OP_RFID"
20536   attribute \enum_value_1000111 "OP_MFMSR"
20537   attribute \enum_value_1001000 "OP_MTMSRD"
20538   attribute \enum_value_1001001 "OP_SC"
20539   attribute \enum_value_1001010 "OP_MTMSR"
20540   attribute \enum_value_1001011 "OP_TLBIE"
20541   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20542   wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op
20543   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20544   wire \dec31_dec_sub19_dec31_dec_sub19_inv_a
20545   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20546   wire \dec31_dec_sub19_dec31_dec_sub19_inv_out
20547   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20548   wire \dec31_dec_sub19_dec31_dec_sub19_is_32b
20549   attribute \enum_base_type "LdstLen"
20550   attribute \enum_value_0000 "NONE"
20551   attribute \enum_value_0001 "is1B"
20552   attribute \enum_value_0010 "is2B"
20553   attribute \enum_value_0100 "is4B"
20554   attribute \enum_value_1000 "is8B"
20555   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20556   wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len
20557   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20558   wire \dec31_dec_sub19_dec31_dec_sub19_lk
20559   attribute \enum_base_type "OutSel"
20560   attribute \enum_value_00 "NONE"
20561   attribute \enum_value_01 "RT"
20562   attribute \enum_value_10 "RA"
20563   attribute \enum_value_11 "SPR"
20564   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20565   wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel
20566   attribute \enum_base_type "RC"
20567   attribute \enum_value_00 "NONE"
20568   attribute \enum_value_01 "ONE"
20569   attribute \enum_value_10 "RC"
20570   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20571   wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel
20572   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20573   wire \dec31_dec_sub19_dec31_dec_sub19_rsrv
20574   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20575   wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe
20576   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20577   wire \dec31_dec_sub19_dec31_dec_sub19_sgn
20578   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20579   wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext
20580   attribute \enum_base_type "LDSTMode"
20581   attribute \enum_value_00 "NONE"
20582   attribute \enum_value_01 "update"
20583   attribute \enum_value_10 "cix"
20584   attribute \enum_value_11 "cx"
20585   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20586   wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd
20587   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
20588   wire width 32 \dec31_dec_sub19_opcode_in
20589   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20590   wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode
20591   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20592   wire \dec31_dec_sub20_dec31_dec_sub20_br
20593   attribute \enum_base_type "CRInSel"
20594   attribute \enum_value_000 "NONE"
20595   attribute \enum_value_001 "CR0"
20596   attribute \enum_value_010 "BI"
20597   attribute \enum_value_011 "BFA"
20598   attribute \enum_value_100 "BA_BB"
20599   attribute \enum_value_101 "BC"
20600   attribute \enum_value_110 "WHOLE_REG"
20601   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20602   wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in
20603   attribute \enum_base_type "CROutSel"
20604   attribute \enum_value_000 "NONE"
20605   attribute \enum_value_001 "CR0"
20606   attribute \enum_value_010 "BF"
20607   attribute \enum_value_011 "BT"
20608   attribute \enum_value_100 "WHOLE_REG"
20609   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20610   wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out
20611   attribute \enum_base_type "CryIn"
20612   attribute \enum_value_00 "ZERO"
20613   attribute \enum_value_01 "ONE"
20614   attribute \enum_value_10 "CA"
20615   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20616   wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in
20617   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20618   wire \dec31_dec_sub20_dec31_dec_sub20_cry_out
20619   attribute \enum_base_type "Form"
20620   attribute \enum_value_00000 "NONE"
20621   attribute \enum_value_00001 "I"
20622   attribute \enum_value_00010 "B"
20623   attribute \enum_value_00011 "SC"
20624   attribute \enum_value_00100 "D"
20625   attribute \enum_value_00101 "DS"
20626   attribute \enum_value_00110 "DQ"
20627   attribute \enum_value_00111 "DX"
20628   attribute \enum_value_01000 "X"
20629   attribute \enum_value_01001 "XL"
20630   attribute \enum_value_01010 "XFX"
20631   attribute \enum_value_01011 "XFL"
20632   attribute \enum_value_01100 "XX1"
20633   attribute \enum_value_01101 "XX2"
20634   attribute \enum_value_01110 "XX3"
20635   attribute \enum_value_01111 "XX4"
20636   attribute \enum_value_10000 "XS"
20637   attribute \enum_value_10001 "XO"
20638   attribute \enum_value_10010 "A"
20639   attribute \enum_value_10011 "M"
20640   attribute \enum_value_10100 "MD"
20641   attribute \enum_value_10101 "MDS"
20642   attribute \enum_value_10110 "VA"
20643   attribute \enum_value_10111 "VC"
20644   attribute \enum_value_11000 "VX"
20645   attribute \enum_value_11001 "EVX"
20646   attribute \enum_value_11010 "EVS"
20647   attribute \enum_value_11011 "Z22"
20648   attribute \enum_value_11100 "Z23"
20649   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20650   wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form
20651   attribute \enum_base_type "Function"
20652   attribute \enum_value_000000000000 "NONE"
20653   attribute \enum_value_000000000010 "ALU"
20654   attribute \enum_value_000000000100 "LDST"
20655   attribute \enum_value_000000001000 "SHIFT_ROT"
20656   attribute \enum_value_000000010000 "LOGICAL"
20657   attribute \enum_value_000000100000 "BRANCH"
20658   attribute \enum_value_000001000000 "CR"
20659   attribute \enum_value_000010000000 "TRAP"
20660   attribute \enum_value_000100000000 "MUL"
20661   attribute \enum_value_001000000000 "DIV"
20662   attribute \enum_value_010000000000 "SPR"
20663   attribute \enum_value_100000000000 "MMU"
20664   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20665   wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit
20666   attribute \enum_base_type "In1Sel"
20667   attribute \enum_value_000 "NONE"
20668   attribute \enum_value_001 "RA"
20669   attribute \enum_value_010 "RA_OR_ZERO"
20670   attribute \enum_value_011 "SPR"
20671   attribute \enum_value_100 "RS"
20672   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20673   wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel
20674   attribute \enum_base_type "In2Sel"
20675   attribute \enum_value_0000 "NONE"
20676   attribute \enum_value_0001 "RB"
20677   attribute \enum_value_0010 "CONST_UI"
20678   attribute \enum_value_0011 "CONST_SI"
20679   attribute \enum_value_0100 "CONST_UI_HI"
20680   attribute \enum_value_0101 "CONST_SI_HI"
20681   attribute \enum_value_0110 "CONST_LI"
20682   attribute \enum_value_0111 "CONST_BD"
20683   attribute \enum_value_1000 "CONST_DS"
20684   attribute \enum_value_1001 "CONST_M1"
20685   attribute \enum_value_1010 "CONST_SH"
20686   attribute \enum_value_1011 "CONST_SH32"
20687   attribute \enum_value_1100 "SPR"
20688   attribute \enum_value_1101 "RS"
20689   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20690   wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel
20691   attribute \enum_base_type "In3Sel"
20692   attribute \enum_value_00 "NONE"
20693   attribute \enum_value_01 "RS"
20694   attribute \enum_value_10 "RB"
20695   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20696   wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel
20697   attribute \enum_base_type "MicrOp"
20698   attribute \enum_value_0000000 "OP_ILLEGAL"
20699   attribute \enum_value_0000001 "OP_NOP"
20700   attribute \enum_value_0000010 "OP_ADD"
20701   attribute \enum_value_0000011 "OP_ADDPCIS"
20702   attribute \enum_value_0000100 "OP_AND"
20703   attribute \enum_value_0000101 "OP_ATTN"
20704   attribute \enum_value_0000110 "OP_B"
20705   attribute \enum_value_0000111 "OP_BC"
20706   attribute \enum_value_0001000 "OP_BCREG"
20707   attribute \enum_value_0001001 "OP_BPERM"
20708   attribute \enum_value_0001010 "OP_CMP"
20709   attribute \enum_value_0001011 "OP_CMPB"
20710   attribute \enum_value_0001100 "OP_CMPEQB"
20711   attribute \enum_value_0001101 "OP_CMPRB"
20712   attribute \enum_value_0001110 "OP_CNTZ"
20713   attribute \enum_value_0001111 "OP_CRAND"
20714   attribute \enum_value_0010000 "OP_CRANDC"
20715   attribute \enum_value_0010001 "OP_CREQV"
20716   attribute \enum_value_0010010 "OP_CRNAND"
20717   attribute \enum_value_0010011 "OP_CRNOR"
20718   attribute \enum_value_0010100 "OP_CROR"
20719   attribute \enum_value_0010101 "OP_CRORC"
20720   attribute \enum_value_0010110 "OP_CRXOR"
20721   attribute \enum_value_0010111 "OP_DARN"
20722   attribute \enum_value_0011000 "OP_DCBF"
20723   attribute \enum_value_0011001 "OP_DCBST"
20724   attribute \enum_value_0011010 "OP_DCBT"
20725   attribute \enum_value_0011011 "OP_DCBTST"
20726   attribute \enum_value_0011100 "OP_DCBZ"
20727   attribute \enum_value_0011101 "OP_DIV"
20728   attribute \enum_value_0011110 "OP_DIVE"
20729   attribute \enum_value_0011111 "OP_EXTS"
20730   attribute \enum_value_0100000 "OP_EXTSWSLI"
20731   attribute \enum_value_0100001 "OP_ICBI"
20732   attribute \enum_value_0100010 "OP_ICBT"
20733   attribute \enum_value_0100011 "OP_ISEL"
20734   attribute \enum_value_0100100 "OP_ISYNC"
20735   attribute \enum_value_0100101 "OP_LOAD"
20736   attribute \enum_value_0100110 "OP_STORE"
20737   attribute \enum_value_0100111 "OP_MADDHD"
20738   attribute \enum_value_0101000 "OP_MADDHDU"
20739   attribute \enum_value_0101001 "OP_MADDLD"
20740   attribute \enum_value_0101010 "OP_MCRF"
20741   attribute \enum_value_0101011 "OP_MCRXR"
20742   attribute \enum_value_0101100 "OP_MCRXRX"
20743   attribute \enum_value_0101101 "OP_MFCR"
20744   attribute \enum_value_0101110 "OP_MFSPR"
20745   attribute \enum_value_0101111 "OP_MOD"
20746   attribute \enum_value_0110000 "OP_MTCRF"
20747   attribute \enum_value_0110001 "OP_MTSPR"
20748   attribute \enum_value_0110010 "OP_MUL_L64"
20749   attribute \enum_value_0110011 "OP_MUL_H64"
20750   attribute \enum_value_0110100 "OP_MUL_H32"
20751   attribute \enum_value_0110101 "OP_OR"
20752   attribute \enum_value_0110110 "OP_POPCNT"
20753   attribute \enum_value_0110111 "OP_PRTY"
20754   attribute \enum_value_0111000 "OP_RLC"
20755   attribute \enum_value_0111001 "OP_RLCL"
20756   attribute \enum_value_0111010 "OP_RLCR"
20757   attribute \enum_value_0111011 "OP_SETB"
20758   attribute \enum_value_0111100 "OP_SHL"
20759   attribute \enum_value_0111101 "OP_SHR"
20760   attribute \enum_value_0111110 "OP_SYNC"
20761   attribute \enum_value_0111111 "OP_TRAP"
20762   attribute \enum_value_1000011 "OP_XOR"
20763   attribute \enum_value_1000100 "OP_SIM_CONFIG"
20764   attribute \enum_value_1000101 "OP_CROP"
20765   attribute \enum_value_1000110 "OP_RFID"
20766   attribute \enum_value_1000111 "OP_MFMSR"
20767   attribute \enum_value_1001000 "OP_MTMSRD"
20768   attribute \enum_value_1001001 "OP_SC"
20769   attribute \enum_value_1001010 "OP_MTMSR"
20770   attribute \enum_value_1001011 "OP_TLBIE"
20771   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20772   wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op
20773   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20774   wire \dec31_dec_sub20_dec31_dec_sub20_inv_a
20775   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20776   wire \dec31_dec_sub20_dec31_dec_sub20_inv_out
20777   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20778   wire \dec31_dec_sub20_dec31_dec_sub20_is_32b
20779   attribute \enum_base_type "LdstLen"
20780   attribute \enum_value_0000 "NONE"
20781   attribute \enum_value_0001 "is1B"
20782   attribute \enum_value_0010 "is2B"
20783   attribute \enum_value_0100 "is4B"
20784   attribute \enum_value_1000 "is8B"
20785   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20786   wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len
20787   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20788   wire \dec31_dec_sub20_dec31_dec_sub20_lk
20789   attribute \enum_base_type "OutSel"
20790   attribute \enum_value_00 "NONE"
20791   attribute \enum_value_01 "RT"
20792   attribute \enum_value_10 "RA"
20793   attribute \enum_value_11 "SPR"
20794   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20795   wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel
20796   attribute \enum_base_type "RC"
20797   attribute \enum_value_00 "NONE"
20798   attribute \enum_value_01 "ONE"
20799   attribute \enum_value_10 "RC"
20800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20801   wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel
20802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20803   wire \dec31_dec_sub20_dec31_dec_sub20_rsrv
20804   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20805   wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe
20806   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20807   wire \dec31_dec_sub20_dec31_dec_sub20_sgn
20808   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20809   wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext
20810   attribute \enum_base_type "LDSTMode"
20811   attribute \enum_value_00 "NONE"
20812   attribute \enum_value_01 "update"
20813   attribute \enum_value_10 "cix"
20814   attribute \enum_value_11 "cx"
20815   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20816   wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd
20817   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
20818   wire width 32 \dec31_dec_sub20_opcode_in
20819   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20820   wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode
20821   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20822   wire \dec31_dec_sub21_dec31_dec_sub21_br
20823   attribute \enum_base_type "CRInSel"
20824   attribute \enum_value_000 "NONE"
20825   attribute \enum_value_001 "CR0"
20826   attribute \enum_value_010 "BI"
20827   attribute \enum_value_011 "BFA"
20828   attribute \enum_value_100 "BA_BB"
20829   attribute \enum_value_101 "BC"
20830   attribute \enum_value_110 "WHOLE_REG"
20831   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20832   wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in
20833   attribute \enum_base_type "CROutSel"
20834   attribute \enum_value_000 "NONE"
20835   attribute \enum_value_001 "CR0"
20836   attribute \enum_value_010 "BF"
20837   attribute \enum_value_011 "BT"
20838   attribute \enum_value_100 "WHOLE_REG"
20839   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20840   wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out
20841   attribute \enum_base_type "CryIn"
20842   attribute \enum_value_00 "ZERO"
20843   attribute \enum_value_01 "ONE"
20844   attribute \enum_value_10 "CA"
20845   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20846   wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in
20847   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
20848   wire \dec31_dec_sub21_dec31_dec_sub21_cry_out
20849   attribute \enum_base_type "Form"
20850   attribute \enum_value_00000 "NONE"
20851   attribute \enum_value_00001 "I"
20852   attribute \enum_value_00010 "B"
20853   attribute \enum_value_00011 "SC"
20854   attribute \enum_value_00100 "D"
20855   attribute \enum_value_00101 "DS"
20856   attribute \enum_value_00110 "DQ"
20857   attribute \enum_value_00111 "DX"
20858   attribute \enum_value_01000 "X"
20859   attribute \enum_value_01001 "XL"
20860   attribute \enum_value_01010 "XFX"
20861   attribute \enum_value_01011 "XFL"
20862   attribute \enum_value_01100 "XX1"
20863   attribute \enum_value_01101 "XX2"
20864   attribute \enum_value_01110 "XX3"
20865   attribute \enum_value_01111 "XX4"
20866   attribute \enum_value_10000 "XS"
20867   attribute \enum_value_10001 "XO"
20868   attribute \enum_value_10010 "A"
20869   attribute \enum_value_10011 "M"
20870   attribute \enum_value_10100 "MD"
20871   attribute \enum_value_10101 "MDS"
20872   attribute \enum_value_10110 "VA"
20873   attribute \enum_value_10111 "VC"
20874   attribute \enum_value_11000 "VX"
20875   attribute \enum_value_11001 "EVX"
20876   attribute \enum_value_11010 "EVS"
20877   attribute \enum_value_11011 "Z22"
20878   attribute \enum_value_11100 "Z23"
20879   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20880   wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form
20881   attribute \enum_base_type "Function"
20882   attribute \enum_value_000000000000 "NONE"
20883   attribute \enum_value_000000000010 "ALU"
20884   attribute \enum_value_000000000100 "LDST"
20885   attribute \enum_value_000000001000 "SHIFT_ROT"
20886   attribute \enum_value_000000010000 "LOGICAL"
20887   attribute \enum_value_000000100000 "BRANCH"
20888   attribute \enum_value_000001000000 "CR"
20889   attribute \enum_value_000010000000 "TRAP"
20890   attribute \enum_value_000100000000 "MUL"
20891   attribute \enum_value_001000000000 "DIV"
20892   attribute \enum_value_010000000000 "SPR"
20893   attribute \enum_value_100000000000 "MMU"
20894   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20895   wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit
20896   attribute \enum_base_type "In1Sel"
20897   attribute \enum_value_000 "NONE"
20898   attribute \enum_value_001 "RA"
20899   attribute \enum_value_010 "RA_OR_ZERO"
20900   attribute \enum_value_011 "SPR"
20901   attribute \enum_value_100 "RS"
20902   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20903   wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel
20904   attribute \enum_base_type "In2Sel"
20905   attribute \enum_value_0000 "NONE"
20906   attribute \enum_value_0001 "RB"
20907   attribute \enum_value_0010 "CONST_UI"
20908   attribute \enum_value_0011 "CONST_SI"
20909   attribute \enum_value_0100 "CONST_UI_HI"
20910   attribute \enum_value_0101 "CONST_SI_HI"
20911   attribute \enum_value_0110 "CONST_LI"
20912   attribute \enum_value_0111 "CONST_BD"
20913   attribute \enum_value_1000 "CONST_DS"
20914   attribute \enum_value_1001 "CONST_M1"
20915   attribute \enum_value_1010 "CONST_SH"
20916   attribute \enum_value_1011 "CONST_SH32"
20917   attribute \enum_value_1100 "SPR"
20918   attribute \enum_value_1101 "RS"
20919   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20920   wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel
20921   attribute \enum_base_type "In3Sel"
20922   attribute \enum_value_00 "NONE"
20923   attribute \enum_value_01 "RS"
20924   attribute \enum_value_10 "RB"
20925   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
20926   wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel
20927   attribute \enum_base_type "MicrOp"
20928   attribute \enum_value_0000000 "OP_ILLEGAL"
20929   attribute \enum_value_0000001 "OP_NOP"
20930   attribute \enum_value_0000010 "OP_ADD"
20931   attribute \enum_value_0000011 "OP_ADDPCIS"
20932   attribute \enum_value_0000100 "OP_AND"
20933   attribute \enum_value_0000101 "OP_ATTN"
20934   attribute \enum_value_0000110 "OP_B"
20935   attribute \enum_value_0000111 "OP_BC"
20936   attribute \enum_value_0001000 "OP_BCREG"
20937   attribute \enum_value_0001001 "OP_BPERM"
20938   attribute \enum_value_0001010 "OP_CMP"
20939   attribute \enum_value_0001011 "OP_CMPB"
20940   attribute \enum_value_0001100 "OP_CMPEQB"
20941   attribute \enum_value_0001101 "OP_CMPRB"
20942   attribute \enum_value_0001110 "OP_CNTZ"
20943   attribute \enum_value_0001111 "OP_CRAND"
20944   attribute \enum_value_0010000 "OP_CRANDC"
20945   attribute \enum_value_0010001 "OP_CREQV"
20946   attribute \enum_value_0010010 "OP_CRNAND"
20947   attribute \enum_value_0010011 "OP_CRNOR"
20948   attribute \enum_value_0010100 "OP_CROR"
20949   attribute \enum_value_0010101 "OP_CRORC"
20950   attribute \enum_value_0010110 "OP_CRXOR"
20951   attribute \enum_value_0010111 "OP_DARN"
20952   attribute \enum_value_0011000 "OP_DCBF"
20953   attribute \enum_value_0011001 "OP_DCBST"
20954   attribute \enum_value_0011010 "OP_DCBT"
20955   attribute \enum_value_0011011 "OP_DCBTST"
20956   attribute \enum_value_0011100 "OP_DCBZ"
20957   attribute \enum_value_0011101 "OP_DIV"
20958   attribute \enum_value_0011110 "OP_DIVE"
20959   attribute \enum_value_0011111 "OP_EXTS"
20960   attribute \enum_value_0100000 "OP_EXTSWSLI"
20961   attribute \enum_value_0100001 "OP_ICBI"
20962   attribute \enum_value_0100010 "OP_ICBT"
20963   attribute \enum_value_0100011 "OP_ISEL"
20964   attribute \enum_value_0100100 "OP_ISYNC"
20965   attribute \enum_value_0100101 "OP_LOAD"
20966   attribute \enum_value_0100110 "OP_STORE"
20967   attribute \enum_value_0100111 "OP_MADDHD"
20968   attribute \enum_value_0101000 "OP_MADDHDU"
20969   attribute \enum_value_0101001 "OP_MADDLD"
20970   attribute \enum_value_0101010 "OP_MCRF"
20971   attribute \enum_value_0101011 "OP_MCRXR"
20972   attribute \enum_value_0101100 "OP_MCRXRX"
20973   attribute \enum_value_0101101 "OP_MFCR"
20974   attribute \enum_value_0101110 "OP_MFSPR"
20975   attribute \enum_value_0101111 "OP_MOD"
20976   attribute \enum_value_0110000 "OP_MTCRF"
20977   attribute \enum_value_0110001 "OP_MTSPR"
20978   attribute \enum_value_0110010 "OP_MUL_L64"
20979   attribute \enum_value_0110011 "OP_MUL_H64"
20980   attribute \enum_value_0110100 "OP_MUL_H32"
20981   attribute \enum_value_0110101 "OP_OR"
20982   attribute \enum_value_0110110 "OP_POPCNT"
20983   attribute \enum_value_0110111 "OP_PRTY"
20984   attribute \enum_value_0111000 "OP_RLC"
20985   attribute \enum_value_0111001 "OP_RLCL"
20986   attribute \enum_value_0111010 "OP_RLCR"
20987   attribute \enum_value_0111011 "OP_SETB"
20988   attribute \enum_value_0111100 "OP_SHL"
20989   attribute \enum_value_0111101 "OP_SHR"
20990   attribute \enum_value_0111110 "OP_SYNC"
20991   attribute \enum_value_0111111 "OP_TRAP"
20992   attribute \enum_value_1000011 "OP_XOR"
20993   attribute \enum_value_1000100 "OP_SIM_CONFIG"
20994   attribute \enum_value_1000101 "OP_CROP"
20995   attribute \enum_value_1000110 "OP_RFID"
20996   attribute \enum_value_1000111 "OP_MFMSR"
20997   attribute \enum_value_1001000 "OP_MTMSRD"
20998   attribute \enum_value_1001001 "OP_SC"
20999   attribute \enum_value_1001010 "OP_MTMSR"
21000   attribute \enum_value_1001011 "OP_TLBIE"
21001   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21002   wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op
21003   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21004   wire \dec31_dec_sub21_dec31_dec_sub21_inv_a
21005   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21006   wire \dec31_dec_sub21_dec31_dec_sub21_inv_out
21007   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21008   wire \dec31_dec_sub21_dec31_dec_sub21_is_32b
21009   attribute \enum_base_type "LdstLen"
21010   attribute \enum_value_0000 "NONE"
21011   attribute \enum_value_0001 "is1B"
21012   attribute \enum_value_0010 "is2B"
21013   attribute \enum_value_0100 "is4B"
21014   attribute \enum_value_1000 "is8B"
21015   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21016   wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len
21017   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21018   wire \dec31_dec_sub21_dec31_dec_sub21_lk
21019   attribute \enum_base_type "OutSel"
21020   attribute \enum_value_00 "NONE"
21021   attribute \enum_value_01 "RT"
21022   attribute \enum_value_10 "RA"
21023   attribute \enum_value_11 "SPR"
21024   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21025   wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel
21026   attribute \enum_base_type "RC"
21027   attribute \enum_value_00 "NONE"
21028   attribute \enum_value_01 "ONE"
21029   attribute \enum_value_10 "RC"
21030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21031   wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel
21032   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21033   wire \dec31_dec_sub21_dec31_dec_sub21_rsrv
21034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21035   wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe
21036   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21037   wire \dec31_dec_sub21_dec31_dec_sub21_sgn
21038   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21039   wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext
21040   attribute \enum_base_type "LDSTMode"
21041   attribute \enum_value_00 "NONE"
21042   attribute \enum_value_01 "update"
21043   attribute \enum_value_10 "cix"
21044   attribute \enum_value_11 "cx"
21045   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21046   wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd
21047   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
21048   wire width 32 \dec31_dec_sub21_opcode_in
21049   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21050   wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode
21051   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21052   wire \dec31_dec_sub22_dec31_dec_sub22_br
21053   attribute \enum_base_type "CRInSel"
21054   attribute \enum_value_000 "NONE"
21055   attribute \enum_value_001 "CR0"
21056   attribute \enum_value_010 "BI"
21057   attribute \enum_value_011 "BFA"
21058   attribute \enum_value_100 "BA_BB"
21059   attribute \enum_value_101 "BC"
21060   attribute \enum_value_110 "WHOLE_REG"
21061   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21062   wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in
21063   attribute \enum_base_type "CROutSel"
21064   attribute \enum_value_000 "NONE"
21065   attribute \enum_value_001 "CR0"
21066   attribute \enum_value_010 "BF"
21067   attribute \enum_value_011 "BT"
21068   attribute \enum_value_100 "WHOLE_REG"
21069   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21070   wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out
21071   attribute \enum_base_type "CryIn"
21072   attribute \enum_value_00 "ZERO"
21073   attribute \enum_value_01 "ONE"
21074   attribute \enum_value_10 "CA"
21075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21076   wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in
21077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21078   wire \dec31_dec_sub22_dec31_dec_sub22_cry_out
21079   attribute \enum_base_type "Form"
21080   attribute \enum_value_00000 "NONE"
21081   attribute \enum_value_00001 "I"
21082   attribute \enum_value_00010 "B"
21083   attribute \enum_value_00011 "SC"
21084   attribute \enum_value_00100 "D"
21085   attribute \enum_value_00101 "DS"
21086   attribute \enum_value_00110 "DQ"
21087   attribute \enum_value_00111 "DX"
21088   attribute \enum_value_01000 "X"
21089   attribute \enum_value_01001 "XL"
21090   attribute \enum_value_01010 "XFX"
21091   attribute \enum_value_01011 "XFL"
21092   attribute \enum_value_01100 "XX1"
21093   attribute \enum_value_01101 "XX2"
21094   attribute \enum_value_01110 "XX3"
21095   attribute \enum_value_01111 "XX4"
21096   attribute \enum_value_10000 "XS"
21097   attribute \enum_value_10001 "XO"
21098   attribute \enum_value_10010 "A"
21099   attribute \enum_value_10011 "M"
21100   attribute \enum_value_10100 "MD"
21101   attribute \enum_value_10101 "MDS"
21102   attribute \enum_value_10110 "VA"
21103   attribute \enum_value_10111 "VC"
21104   attribute \enum_value_11000 "VX"
21105   attribute \enum_value_11001 "EVX"
21106   attribute \enum_value_11010 "EVS"
21107   attribute \enum_value_11011 "Z22"
21108   attribute \enum_value_11100 "Z23"
21109   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21110   wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form
21111   attribute \enum_base_type "Function"
21112   attribute \enum_value_000000000000 "NONE"
21113   attribute \enum_value_000000000010 "ALU"
21114   attribute \enum_value_000000000100 "LDST"
21115   attribute \enum_value_000000001000 "SHIFT_ROT"
21116   attribute \enum_value_000000010000 "LOGICAL"
21117   attribute \enum_value_000000100000 "BRANCH"
21118   attribute \enum_value_000001000000 "CR"
21119   attribute \enum_value_000010000000 "TRAP"
21120   attribute \enum_value_000100000000 "MUL"
21121   attribute \enum_value_001000000000 "DIV"
21122   attribute \enum_value_010000000000 "SPR"
21123   attribute \enum_value_100000000000 "MMU"
21124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21125   wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit
21126   attribute \enum_base_type "In1Sel"
21127   attribute \enum_value_000 "NONE"
21128   attribute \enum_value_001 "RA"
21129   attribute \enum_value_010 "RA_OR_ZERO"
21130   attribute \enum_value_011 "SPR"
21131   attribute \enum_value_100 "RS"
21132   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21133   wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel
21134   attribute \enum_base_type "In2Sel"
21135   attribute \enum_value_0000 "NONE"
21136   attribute \enum_value_0001 "RB"
21137   attribute \enum_value_0010 "CONST_UI"
21138   attribute \enum_value_0011 "CONST_SI"
21139   attribute \enum_value_0100 "CONST_UI_HI"
21140   attribute \enum_value_0101 "CONST_SI_HI"
21141   attribute \enum_value_0110 "CONST_LI"
21142   attribute \enum_value_0111 "CONST_BD"
21143   attribute \enum_value_1000 "CONST_DS"
21144   attribute \enum_value_1001 "CONST_M1"
21145   attribute \enum_value_1010 "CONST_SH"
21146   attribute \enum_value_1011 "CONST_SH32"
21147   attribute \enum_value_1100 "SPR"
21148   attribute \enum_value_1101 "RS"
21149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21150   wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel
21151   attribute \enum_base_type "In3Sel"
21152   attribute \enum_value_00 "NONE"
21153   attribute \enum_value_01 "RS"
21154   attribute \enum_value_10 "RB"
21155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21156   wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel
21157   attribute \enum_base_type "MicrOp"
21158   attribute \enum_value_0000000 "OP_ILLEGAL"
21159   attribute \enum_value_0000001 "OP_NOP"
21160   attribute \enum_value_0000010 "OP_ADD"
21161   attribute \enum_value_0000011 "OP_ADDPCIS"
21162   attribute \enum_value_0000100 "OP_AND"
21163   attribute \enum_value_0000101 "OP_ATTN"
21164   attribute \enum_value_0000110 "OP_B"
21165   attribute \enum_value_0000111 "OP_BC"
21166   attribute \enum_value_0001000 "OP_BCREG"
21167   attribute \enum_value_0001001 "OP_BPERM"
21168   attribute \enum_value_0001010 "OP_CMP"
21169   attribute \enum_value_0001011 "OP_CMPB"
21170   attribute \enum_value_0001100 "OP_CMPEQB"
21171   attribute \enum_value_0001101 "OP_CMPRB"
21172   attribute \enum_value_0001110 "OP_CNTZ"
21173   attribute \enum_value_0001111 "OP_CRAND"
21174   attribute \enum_value_0010000 "OP_CRANDC"
21175   attribute \enum_value_0010001 "OP_CREQV"
21176   attribute \enum_value_0010010 "OP_CRNAND"
21177   attribute \enum_value_0010011 "OP_CRNOR"
21178   attribute \enum_value_0010100 "OP_CROR"
21179   attribute \enum_value_0010101 "OP_CRORC"
21180   attribute \enum_value_0010110 "OP_CRXOR"
21181   attribute \enum_value_0010111 "OP_DARN"
21182   attribute \enum_value_0011000 "OP_DCBF"
21183   attribute \enum_value_0011001 "OP_DCBST"
21184   attribute \enum_value_0011010 "OP_DCBT"
21185   attribute \enum_value_0011011 "OP_DCBTST"
21186   attribute \enum_value_0011100 "OP_DCBZ"
21187   attribute \enum_value_0011101 "OP_DIV"
21188   attribute \enum_value_0011110 "OP_DIVE"
21189   attribute \enum_value_0011111 "OP_EXTS"
21190   attribute \enum_value_0100000 "OP_EXTSWSLI"
21191   attribute \enum_value_0100001 "OP_ICBI"
21192   attribute \enum_value_0100010 "OP_ICBT"
21193   attribute \enum_value_0100011 "OP_ISEL"
21194   attribute \enum_value_0100100 "OP_ISYNC"
21195   attribute \enum_value_0100101 "OP_LOAD"
21196   attribute \enum_value_0100110 "OP_STORE"
21197   attribute \enum_value_0100111 "OP_MADDHD"
21198   attribute \enum_value_0101000 "OP_MADDHDU"
21199   attribute \enum_value_0101001 "OP_MADDLD"
21200   attribute \enum_value_0101010 "OP_MCRF"
21201   attribute \enum_value_0101011 "OP_MCRXR"
21202   attribute \enum_value_0101100 "OP_MCRXRX"
21203   attribute \enum_value_0101101 "OP_MFCR"
21204   attribute \enum_value_0101110 "OP_MFSPR"
21205   attribute \enum_value_0101111 "OP_MOD"
21206   attribute \enum_value_0110000 "OP_MTCRF"
21207   attribute \enum_value_0110001 "OP_MTSPR"
21208   attribute \enum_value_0110010 "OP_MUL_L64"
21209   attribute \enum_value_0110011 "OP_MUL_H64"
21210   attribute \enum_value_0110100 "OP_MUL_H32"
21211   attribute \enum_value_0110101 "OP_OR"
21212   attribute \enum_value_0110110 "OP_POPCNT"
21213   attribute \enum_value_0110111 "OP_PRTY"
21214   attribute \enum_value_0111000 "OP_RLC"
21215   attribute \enum_value_0111001 "OP_RLCL"
21216   attribute \enum_value_0111010 "OP_RLCR"
21217   attribute \enum_value_0111011 "OP_SETB"
21218   attribute \enum_value_0111100 "OP_SHL"
21219   attribute \enum_value_0111101 "OP_SHR"
21220   attribute \enum_value_0111110 "OP_SYNC"
21221   attribute \enum_value_0111111 "OP_TRAP"
21222   attribute \enum_value_1000011 "OP_XOR"
21223   attribute \enum_value_1000100 "OP_SIM_CONFIG"
21224   attribute \enum_value_1000101 "OP_CROP"
21225   attribute \enum_value_1000110 "OP_RFID"
21226   attribute \enum_value_1000111 "OP_MFMSR"
21227   attribute \enum_value_1001000 "OP_MTMSRD"
21228   attribute \enum_value_1001001 "OP_SC"
21229   attribute \enum_value_1001010 "OP_MTMSR"
21230   attribute \enum_value_1001011 "OP_TLBIE"
21231   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21232   wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op
21233   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21234   wire \dec31_dec_sub22_dec31_dec_sub22_inv_a
21235   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21236   wire \dec31_dec_sub22_dec31_dec_sub22_inv_out
21237   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21238   wire \dec31_dec_sub22_dec31_dec_sub22_is_32b
21239   attribute \enum_base_type "LdstLen"
21240   attribute \enum_value_0000 "NONE"
21241   attribute \enum_value_0001 "is1B"
21242   attribute \enum_value_0010 "is2B"
21243   attribute \enum_value_0100 "is4B"
21244   attribute \enum_value_1000 "is8B"
21245   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21246   wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len
21247   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21248   wire \dec31_dec_sub22_dec31_dec_sub22_lk
21249   attribute \enum_base_type "OutSel"
21250   attribute \enum_value_00 "NONE"
21251   attribute \enum_value_01 "RT"
21252   attribute \enum_value_10 "RA"
21253   attribute \enum_value_11 "SPR"
21254   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21255   wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel
21256   attribute \enum_base_type "RC"
21257   attribute \enum_value_00 "NONE"
21258   attribute \enum_value_01 "ONE"
21259   attribute \enum_value_10 "RC"
21260   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21261   wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel
21262   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21263   wire \dec31_dec_sub22_dec31_dec_sub22_rsrv
21264   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21265   wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe
21266   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21267   wire \dec31_dec_sub22_dec31_dec_sub22_sgn
21268   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21269   wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext
21270   attribute \enum_base_type "LDSTMode"
21271   attribute \enum_value_00 "NONE"
21272   attribute \enum_value_01 "update"
21273   attribute \enum_value_10 "cix"
21274   attribute \enum_value_11 "cx"
21275   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21276   wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd
21277   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
21278   wire width 32 \dec31_dec_sub22_opcode_in
21279   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21280   wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode
21281   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21282   wire \dec31_dec_sub23_dec31_dec_sub23_br
21283   attribute \enum_base_type "CRInSel"
21284   attribute \enum_value_000 "NONE"
21285   attribute \enum_value_001 "CR0"
21286   attribute \enum_value_010 "BI"
21287   attribute \enum_value_011 "BFA"
21288   attribute \enum_value_100 "BA_BB"
21289   attribute \enum_value_101 "BC"
21290   attribute \enum_value_110 "WHOLE_REG"
21291   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21292   wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in
21293   attribute \enum_base_type "CROutSel"
21294   attribute \enum_value_000 "NONE"
21295   attribute \enum_value_001 "CR0"
21296   attribute \enum_value_010 "BF"
21297   attribute \enum_value_011 "BT"
21298   attribute \enum_value_100 "WHOLE_REG"
21299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21300   wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out
21301   attribute \enum_base_type "CryIn"
21302   attribute \enum_value_00 "ZERO"
21303   attribute \enum_value_01 "ONE"
21304   attribute \enum_value_10 "CA"
21305   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21306   wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in
21307   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21308   wire \dec31_dec_sub23_dec31_dec_sub23_cry_out
21309   attribute \enum_base_type "Form"
21310   attribute \enum_value_00000 "NONE"
21311   attribute \enum_value_00001 "I"
21312   attribute \enum_value_00010 "B"
21313   attribute \enum_value_00011 "SC"
21314   attribute \enum_value_00100 "D"
21315   attribute \enum_value_00101 "DS"
21316   attribute \enum_value_00110 "DQ"
21317   attribute \enum_value_00111 "DX"
21318   attribute \enum_value_01000 "X"
21319   attribute \enum_value_01001 "XL"
21320   attribute \enum_value_01010 "XFX"
21321   attribute \enum_value_01011 "XFL"
21322   attribute \enum_value_01100 "XX1"
21323   attribute \enum_value_01101 "XX2"
21324   attribute \enum_value_01110 "XX3"
21325   attribute \enum_value_01111 "XX4"
21326   attribute \enum_value_10000 "XS"
21327   attribute \enum_value_10001 "XO"
21328   attribute \enum_value_10010 "A"
21329   attribute \enum_value_10011 "M"
21330   attribute \enum_value_10100 "MD"
21331   attribute \enum_value_10101 "MDS"
21332   attribute \enum_value_10110 "VA"
21333   attribute \enum_value_10111 "VC"
21334   attribute \enum_value_11000 "VX"
21335   attribute \enum_value_11001 "EVX"
21336   attribute \enum_value_11010 "EVS"
21337   attribute \enum_value_11011 "Z22"
21338   attribute \enum_value_11100 "Z23"
21339   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21340   wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form
21341   attribute \enum_base_type "Function"
21342   attribute \enum_value_000000000000 "NONE"
21343   attribute \enum_value_000000000010 "ALU"
21344   attribute \enum_value_000000000100 "LDST"
21345   attribute \enum_value_000000001000 "SHIFT_ROT"
21346   attribute \enum_value_000000010000 "LOGICAL"
21347   attribute \enum_value_000000100000 "BRANCH"
21348   attribute \enum_value_000001000000 "CR"
21349   attribute \enum_value_000010000000 "TRAP"
21350   attribute \enum_value_000100000000 "MUL"
21351   attribute \enum_value_001000000000 "DIV"
21352   attribute \enum_value_010000000000 "SPR"
21353   attribute \enum_value_100000000000 "MMU"
21354   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21355   wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit
21356   attribute \enum_base_type "In1Sel"
21357   attribute \enum_value_000 "NONE"
21358   attribute \enum_value_001 "RA"
21359   attribute \enum_value_010 "RA_OR_ZERO"
21360   attribute \enum_value_011 "SPR"
21361   attribute \enum_value_100 "RS"
21362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21363   wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel
21364   attribute \enum_base_type "In2Sel"
21365   attribute \enum_value_0000 "NONE"
21366   attribute \enum_value_0001 "RB"
21367   attribute \enum_value_0010 "CONST_UI"
21368   attribute \enum_value_0011 "CONST_SI"
21369   attribute \enum_value_0100 "CONST_UI_HI"
21370   attribute \enum_value_0101 "CONST_SI_HI"
21371   attribute \enum_value_0110 "CONST_LI"
21372   attribute \enum_value_0111 "CONST_BD"
21373   attribute \enum_value_1000 "CONST_DS"
21374   attribute \enum_value_1001 "CONST_M1"
21375   attribute \enum_value_1010 "CONST_SH"
21376   attribute \enum_value_1011 "CONST_SH32"
21377   attribute \enum_value_1100 "SPR"
21378   attribute \enum_value_1101 "RS"
21379   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21380   wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel
21381   attribute \enum_base_type "In3Sel"
21382   attribute \enum_value_00 "NONE"
21383   attribute \enum_value_01 "RS"
21384   attribute \enum_value_10 "RB"
21385   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21386   wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel
21387   attribute \enum_base_type "MicrOp"
21388   attribute \enum_value_0000000 "OP_ILLEGAL"
21389   attribute \enum_value_0000001 "OP_NOP"
21390   attribute \enum_value_0000010 "OP_ADD"
21391   attribute \enum_value_0000011 "OP_ADDPCIS"
21392   attribute \enum_value_0000100 "OP_AND"
21393   attribute \enum_value_0000101 "OP_ATTN"
21394   attribute \enum_value_0000110 "OP_B"
21395   attribute \enum_value_0000111 "OP_BC"
21396   attribute \enum_value_0001000 "OP_BCREG"
21397   attribute \enum_value_0001001 "OP_BPERM"
21398   attribute \enum_value_0001010 "OP_CMP"
21399   attribute \enum_value_0001011 "OP_CMPB"
21400   attribute \enum_value_0001100 "OP_CMPEQB"
21401   attribute \enum_value_0001101 "OP_CMPRB"
21402   attribute \enum_value_0001110 "OP_CNTZ"
21403   attribute \enum_value_0001111 "OP_CRAND"
21404   attribute \enum_value_0010000 "OP_CRANDC"
21405   attribute \enum_value_0010001 "OP_CREQV"
21406   attribute \enum_value_0010010 "OP_CRNAND"
21407   attribute \enum_value_0010011 "OP_CRNOR"
21408   attribute \enum_value_0010100 "OP_CROR"
21409   attribute \enum_value_0010101 "OP_CRORC"
21410   attribute \enum_value_0010110 "OP_CRXOR"
21411   attribute \enum_value_0010111 "OP_DARN"
21412   attribute \enum_value_0011000 "OP_DCBF"
21413   attribute \enum_value_0011001 "OP_DCBST"
21414   attribute \enum_value_0011010 "OP_DCBT"
21415   attribute \enum_value_0011011 "OP_DCBTST"
21416   attribute \enum_value_0011100 "OP_DCBZ"
21417   attribute \enum_value_0011101 "OP_DIV"
21418   attribute \enum_value_0011110 "OP_DIVE"
21419   attribute \enum_value_0011111 "OP_EXTS"
21420   attribute \enum_value_0100000 "OP_EXTSWSLI"
21421   attribute \enum_value_0100001 "OP_ICBI"
21422   attribute \enum_value_0100010 "OP_ICBT"
21423   attribute \enum_value_0100011 "OP_ISEL"
21424   attribute \enum_value_0100100 "OP_ISYNC"
21425   attribute \enum_value_0100101 "OP_LOAD"
21426   attribute \enum_value_0100110 "OP_STORE"
21427   attribute \enum_value_0100111 "OP_MADDHD"
21428   attribute \enum_value_0101000 "OP_MADDHDU"
21429   attribute \enum_value_0101001 "OP_MADDLD"
21430   attribute \enum_value_0101010 "OP_MCRF"
21431   attribute \enum_value_0101011 "OP_MCRXR"
21432   attribute \enum_value_0101100 "OP_MCRXRX"
21433   attribute \enum_value_0101101 "OP_MFCR"
21434   attribute \enum_value_0101110 "OP_MFSPR"
21435   attribute \enum_value_0101111 "OP_MOD"
21436   attribute \enum_value_0110000 "OP_MTCRF"
21437   attribute \enum_value_0110001 "OP_MTSPR"
21438   attribute \enum_value_0110010 "OP_MUL_L64"
21439   attribute \enum_value_0110011 "OP_MUL_H64"
21440   attribute \enum_value_0110100 "OP_MUL_H32"
21441   attribute \enum_value_0110101 "OP_OR"
21442   attribute \enum_value_0110110 "OP_POPCNT"
21443   attribute \enum_value_0110111 "OP_PRTY"
21444   attribute \enum_value_0111000 "OP_RLC"
21445   attribute \enum_value_0111001 "OP_RLCL"
21446   attribute \enum_value_0111010 "OP_RLCR"
21447   attribute \enum_value_0111011 "OP_SETB"
21448   attribute \enum_value_0111100 "OP_SHL"
21449   attribute \enum_value_0111101 "OP_SHR"
21450   attribute \enum_value_0111110 "OP_SYNC"
21451   attribute \enum_value_0111111 "OP_TRAP"
21452   attribute \enum_value_1000011 "OP_XOR"
21453   attribute \enum_value_1000100 "OP_SIM_CONFIG"
21454   attribute \enum_value_1000101 "OP_CROP"
21455   attribute \enum_value_1000110 "OP_RFID"
21456   attribute \enum_value_1000111 "OP_MFMSR"
21457   attribute \enum_value_1001000 "OP_MTMSRD"
21458   attribute \enum_value_1001001 "OP_SC"
21459   attribute \enum_value_1001010 "OP_MTMSR"
21460   attribute \enum_value_1001011 "OP_TLBIE"
21461   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21462   wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op
21463   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21464   wire \dec31_dec_sub23_dec31_dec_sub23_inv_a
21465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21466   wire \dec31_dec_sub23_dec31_dec_sub23_inv_out
21467   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21468   wire \dec31_dec_sub23_dec31_dec_sub23_is_32b
21469   attribute \enum_base_type "LdstLen"
21470   attribute \enum_value_0000 "NONE"
21471   attribute \enum_value_0001 "is1B"
21472   attribute \enum_value_0010 "is2B"
21473   attribute \enum_value_0100 "is4B"
21474   attribute \enum_value_1000 "is8B"
21475   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21476   wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len
21477   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21478   wire \dec31_dec_sub23_dec31_dec_sub23_lk
21479   attribute \enum_base_type "OutSel"
21480   attribute \enum_value_00 "NONE"
21481   attribute \enum_value_01 "RT"
21482   attribute \enum_value_10 "RA"
21483   attribute \enum_value_11 "SPR"
21484   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21485   wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel
21486   attribute \enum_base_type "RC"
21487   attribute \enum_value_00 "NONE"
21488   attribute \enum_value_01 "ONE"
21489   attribute \enum_value_10 "RC"
21490   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21491   wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel
21492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21493   wire \dec31_dec_sub23_dec31_dec_sub23_rsrv
21494   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21495   wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe
21496   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21497   wire \dec31_dec_sub23_dec31_dec_sub23_sgn
21498   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21499   wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext
21500   attribute \enum_base_type "LDSTMode"
21501   attribute \enum_value_00 "NONE"
21502   attribute \enum_value_01 "update"
21503   attribute \enum_value_10 "cix"
21504   attribute \enum_value_11 "cx"
21505   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21506   wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd
21507   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
21508   wire width 32 \dec31_dec_sub23_opcode_in
21509   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21510   wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode
21511   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21512   wire \dec31_dec_sub24_dec31_dec_sub24_br
21513   attribute \enum_base_type "CRInSel"
21514   attribute \enum_value_000 "NONE"
21515   attribute \enum_value_001 "CR0"
21516   attribute \enum_value_010 "BI"
21517   attribute \enum_value_011 "BFA"
21518   attribute \enum_value_100 "BA_BB"
21519   attribute \enum_value_101 "BC"
21520   attribute \enum_value_110 "WHOLE_REG"
21521   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21522   wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in
21523   attribute \enum_base_type "CROutSel"
21524   attribute \enum_value_000 "NONE"
21525   attribute \enum_value_001 "CR0"
21526   attribute \enum_value_010 "BF"
21527   attribute \enum_value_011 "BT"
21528   attribute \enum_value_100 "WHOLE_REG"
21529   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21530   wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out
21531   attribute \enum_base_type "CryIn"
21532   attribute \enum_value_00 "ZERO"
21533   attribute \enum_value_01 "ONE"
21534   attribute \enum_value_10 "CA"
21535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21536   wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in
21537   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21538   wire \dec31_dec_sub24_dec31_dec_sub24_cry_out
21539   attribute \enum_base_type "Form"
21540   attribute \enum_value_00000 "NONE"
21541   attribute \enum_value_00001 "I"
21542   attribute \enum_value_00010 "B"
21543   attribute \enum_value_00011 "SC"
21544   attribute \enum_value_00100 "D"
21545   attribute \enum_value_00101 "DS"
21546   attribute \enum_value_00110 "DQ"
21547   attribute \enum_value_00111 "DX"
21548   attribute \enum_value_01000 "X"
21549   attribute \enum_value_01001 "XL"
21550   attribute \enum_value_01010 "XFX"
21551   attribute \enum_value_01011 "XFL"
21552   attribute \enum_value_01100 "XX1"
21553   attribute \enum_value_01101 "XX2"
21554   attribute \enum_value_01110 "XX3"
21555   attribute \enum_value_01111 "XX4"
21556   attribute \enum_value_10000 "XS"
21557   attribute \enum_value_10001 "XO"
21558   attribute \enum_value_10010 "A"
21559   attribute \enum_value_10011 "M"
21560   attribute \enum_value_10100 "MD"
21561   attribute \enum_value_10101 "MDS"
21562   attribute \enum_value_10110 "VA"
21563   attribute \enum_value_10111 "VC"
21564   attribute \enum_value_11000 "VX"
21565   attribute \enum_value_11001 "EVX"
21566   attribute \enum_value_11010 "EVS"
21567   attribute \enum_value_11011 "Z22"
21568   attribute \enum_value_11100 "Z23"
21569   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21570   wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form
21571   attribute \enum_base_type "Function"
21572   attribute \enum_value_000000000000 "NONE"
21573   attribute \enum_value_000000000010 "ALU"
21574   attribute \enum_value_000000000100 "LDST"
21575   attribute \enum_value_000000001000 "SHIFT_ROT"
21576   attribute \enum_value_000000010000 "LOGICAL"
21577   attribute \enum_value_000000100000 "BRANCH"
21578   attribute \enum_value_000001000000 "CR"
21579   attribute \enum_value_000010000000 "TRAP"
21580   attribute \enum_value_000100000000 "MUL"
21581   attribute \enum_value_001000000000 "DIV"
21582   attribute \enum_value_010000000000 "SPR"
21583   attribute \enum_value_100000000000 "MMU"
21584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21585   wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit
21586   attribute \enum_base_type "In1Sel"
21587   attribute \enum_value_000 "NONE"
21588   attribute \enum_value_001 "RA"
21589   attribute \enum_value_010 "RA_OR_ZERO"
21590   attribute \enum_value_011 "SPR"
21591   attribute \enum_value_100 "RS"
21592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21593   wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel
21594   attribute \enum_base_type "In2Sel"
21595   attribute \enum_value_0000 "NONE"
21596   attribute \enum_value_0001 "RB"
21597   attribute \enum_value_0010 "CONST_UI"
21598   attribute \enum_value_0011 "CONST_SI"
21599   attribute \enum_value_0100 "CONST_UI_HI"
21600   attribute \enum_value_0101 "CONST_SI_HI"
21601   attribute \enum_value_0110 "CONST_LI"
21602   attribute \enum_value_0111 "CONST_BD"
21603   attribute \enum_value_1000 "CONST_DS"
21604   attribute \enum_value_1001 "CONST_M1"
21605   attribute \enum_value_1010 "CONST_SH"
21606   attribute \enum_value_1011 "CONST_SH32"
21607   attribute \enum_value_1100 "SPR"
21608   attribute \enum_value_1101 "RS"
21609   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21610   wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel
21611   attribute \enum_base_type "In3Sel"
21612   attribute \enum_value_00 "NONE"
21613   attribute \enum_value_01 "RS"
21614   attribute \enum_value_10 "RB"
21615   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21616   wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel
21617   attribute \enum_base_type "MicrOp"
21618   attribute \enum_value_0000000 "OP_ILLEGAL"
21619   attribute \enum_value_0000001 "OP_NOP"
21620   attribute \enum_value_0000010 "OP_ADD"
21621   attribute \enum_value_0000011 "OP_ADDPCIS"
21622   attribute \enum_value_0000100 "OP_AND"
21623   attribute \enum_value_0000101 "OP_ATTN"
21624   attribute \enum_value_0000110 "OP_B"
21625   attribute \enum_value_0000111 "OP_BC"
21626   attribute \enum_value_0001000 "OP_BCREG"
21627   attribute \enum_value_0001001 "OP_BPERM"
21628   attribute \enum_value_0001010 "OP_CMP"
21629   attribute \enum_value_0001011 "OP_CMPB"
21630   attribute \enum_value_0001100 "OP_CMPEQB"
21631   attribute \enum_value_0001101 "OP_CMPRB"
21632   attribute \enum_value_0001110 "OP_CNTZ"
21633   attribute \enum_value_0001111 "OP_CRAND"
21634   attribute \enum_value_0010000 "OP_CRANDC"
21635   attribute \enum_value_0010001 "OP_CREQV"
21636   attribute \enum_value_0010010 "OP_CRNAND"
21637   attribute \enum_value_0010011 "OP_CRNOR"
21638   attribute \enum_value_0010100 "OP_CROR"
21639   attribute \enum_value_0010101 "OP_CRORC"
21640   attribute \enum_value_0010110 "OP_CRXOR"
21641   attribute \enum_value_0010111 "OP_DARN"
21642   attribute \enum_value_0011000 "OP_DCBF"
21643   attribute \enum_value_0011001 "OP_DCBST"
21644   attribute \enum_value_0011010 "OP_DCBT"
21645   attribute \enum_value_0011011 "OP_DCBTST"
21646   attribute \enum_value_0011100 "OP_DCBZ"
21647   attribute \enum_value_0011101 "OP_DIV"
21648   attribute \enum_value_0011110 "OP_DIVE"
21649   attribute \enum_value_0011111 "OP_EXTS"
21650   attribute \enum_value_0100000 "OP_EXTSWSLI"
21651   attribute \enum_value_0100001 "OP_ICBI"
21652   attribute \enum_value_0100010 "OP_ICBT"
21653   attribute \enum_value_0100011 "OP_ISEL"
21654   attribute \enum_value_0100100 "OP_ISYNC"
21655   attribute \enum_value_0100101 "OP_LOAD"
21656   attribute \enum_value_0100110 "OP_STORE"
21657   attribute \enum_value_0100111 "OP_MADDHD"
21658   attribute \enum_value_0101000 "OP_MADDHDU"
21659   attribute \enum_value_0101001 "OP_MADDLD"
21660   attribute \enum_value_0101010 "OP_MCRF"
21661   attribute \enum_value_0101011 "OP_MCRXR"
21662   attribute \enum_value_0101100 "OP_MCRXRX"
21663   attribute \enum_value_0101101 "OP_MFCR"
21664   attribute \enum_value_0101110 "OP_MFSPR"
21665   attribute \enum_value_0101111 "OP_MOD"
21666   attribute \enum_value_0110000 "OP_MTCRF"
21667   attribute \enum_value_0110001 "OP_MTSPR"
21668   attribute \enum_value_0110010 "OP_MUL_L64"
21669   attribute \enum_value_0110011 "OP_MUL_H64"
21670   attribute \enum_value_0110100 "OP_MUL_H32"
21671   attribute \enum_value_0110101 "OP_OR"
21672   attribute \enum_value_0110110 "OP_POPCNT"
21673   attribute \enum_value_0110111 "OP_PRTY"
21674   attribute \enum_value_0111000 "OP_RLC"
21675   attribute \enum_value_0111001 "OP_RLCL"
21676   attribute \enum_value_0111010 "OP_RLCR"
21677   attribute \enum_value_0111011 "OP_SETB"
21678   attribute \enum_value_0111100 "OP_SHL"
21679   attribute \enum_value_0111101 "OP_SHR"
21680   attribute \enum_value_0111110 "OP_SYNC"
21681   attribute \enum_value_0111111 "OP_TRAP"
21682   attribute \enum_value_1000011 "OP_XOR"
21683   attribute \enum_value_1000100 "OP_SIM_CONFIG"
21684   attribute \enum_value_1000101 "OP_CROP"
21685   attribute \enum_value_1000110 "OP_RFID"
21686   attribute \enum_value_1000111 "OP_MFMSR"
21687   attribute \enum_value_1001000 "OP_MTMSRD"
21688   attribute \enum_value_1001001 "OP_SC"
21689   attribute \enum_value_1001010 "OP_MTMSR"
21690   attribute \enum_value_1001011 "OP_TLBIE"
21691   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21692   wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op
21693   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21694   wire \dec31_dec_sub24_dec31_dec_sub24_inv_a
21695   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21696   wire \dec31_dec_sub24_dec31_dec_sub24_inv_out
21697   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21698   wire \dec31_dec_sub24_dec31_dec_sub24_is_32b
21699   attribute \enum_base_type "LdstLen"
21700   attribute \enum_value_0000 "NONE"
21701   attribute \enum_value_0001 "is1B"
21702   attribute \enum_value_0010 "is2B"
21703   attribute \enum_value_0100 "is4B"
21704   attribute \enum_value_1000 "is8B"
21705   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21706   wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len
21707   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21708   wire \dec31_dec_sub24_dec31_dec_sub24_lk
21709   attribute \enum_base_type "OutSel"
21710   attribute \enum_value_00 "NONE"
21711   attribute \enum_value_01 "RT"
21712   attribute \enum_value_10 "RA"
21713   attribute \enum_value_11 "SPR"
21714   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21715   wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel
21716   attribute \enum_base_type "RC"
21717   attribute \enum_value_00 "NONE"
21718   attribute \enum_value_01 "ONE"
21719   attribute \enum_value_10 "RC"
21720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21721   wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel
21722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21723   wire \dec31_dec_sub24_dec31_dec_sub24_rsrv
21724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21725   wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe
21726   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21727   wire \dec31_dec_sub24_dec31_dec_sub24_sgn
21728   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21729   wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext
21730   attribute \enum_base_type "LDSTMode"
21731   attribute \enum_value_00 "NONE"
21732   attribute \enum_value_01 "update"
21733   attribute \enum_value_10 "cix"
21734   attribute \enum_value_11 "cx"
21735   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21736   wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd
21737   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
21738   wire width 32 \dec31_dec_sub24_opcode_in
21739   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21740   wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode
21741   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21742   wire \dec31_dec_sub26_dec31_dec_sub26_br
21743   attribute \enum_base_type "CRInSel"
21744   attribute \enum_value_000 "NONE"
21745   attribute \enum_value_001 "CR0"
21746   attribute \enum_value_010 "BI"
21747   attribute \enum_value_011 "BFA"
21748   attribute \enum_value_100 "BA_BB"
21749   attribute \enum_value_101 "BC"
21750   attribute \enum_value_110 "WHOLE_REG"
21751   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21752   wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in
21753   attribute \enum_base_type "CROutSel"
21754   attribute \enum_value_000 "NONE"
21755   attribute \enum_value_001 "CR0"
21756   attribute \enum_value_010 "BF"
21757   attribute \enum_value_011 "BT"
21758   attribute \enum_value_100 "WHOLE_REG"
21759   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21760   wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out
21761   attribute \enum_base_type "CryIn"
21762   attribute \enum_value_00 "ZERO"
21763   attribute \enum_value_01 "ONE"
21764   attribute \enum_value_10 "CA"
21765   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21766   wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in
21767   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21768   wire \dec31_dec_sub26_dec31_dec_sub26_cry_out
21769   attribute \enum_base_type "Form"
21770   attribute \enum_value_00000 "NONE"
21771   attribute \enum_value_00001 "I"
21772   attribute \enum_value_00010 "B"
21773   attribute \enum_value_00011 "SC"
21774   attribute \enum_value_00100 "D"
21775   attribute \enum_value_00101 "DS"
21776   attribute \enum_value_00110 "DQ"
21777   attribute \enum_value_00111 "DX"
21778   attribute \enum_value_01000 "X"
21779   attribute \enum_value_01001 "XL"
21780   attribute \enum_value_01010 "XFX"
21781   attribute \enum_value_01011 "XFL"
21782   attribute \enum_value_01100 "XX1"
21783   attribute \enum_value_01101 "XX2"
21784   attribute \enum_value_01110 "XX3"
21785   attribute \enum_value_01111 "XX4"
21786   attribute \enum_value_10000 "XS"
21787   attribute \enum_value_10001 "XO"
21788   attribute \enum_value_10010 "A"
21789   attribute \enum_value_10011 "M"
21790   attribute \enum_value_10100 "MD"
21791   attribute \enum_value_10101 "MDS"
21792   attribute \enum_value_10110 "VA"
21793   attribute \enum_value_10111 "VC"
21794   attribute \enum_value_11000 "VX"
21795   attribute \enum_value_11001 "EVX"
21796   attribute \enum_value_11010 "EVS"
21797   attribute \enum_value_11011 "Z22"
21798   attribute \enum_value_11100 "Z23"
21799   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21800   wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form
21801   attribute \enum_base_type "Function"
21802   attribute \enum_value_000000000000 "NONE"
21803   attribute \enum_value_000000000010 "ALU"
21804   attribute \enum_value_000000000100 "LDST"
21805   attribute \enum_value_000000001000 "SHIFT_ROT"
21806   attribute \enum_value_000000010000 "LOGICAL"
21807   attribute \enum_value_000000100000 "BRANCH"
21808   attribute \enum_value_000001000000 "CR"
21809   attribute \enum_value_000010000000 "TRAP"
21810   attribute \enum_value_000100000000 "MUL"
21811   attribute \enum_value_001000000000 "DIV"
21812   attribute \enum_value_010000000000 "SPR"
21813   attribute \enum_value_100000000000 "MMU"
21814   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21815   wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit
21816   attribute \enum_base_type "In1Sel"
21817   attribute \enum_value_000 "NONE"
21818   attribute \enum_value_001 "RA"
21819   attribute \enum_value_010 "RA_OR_ZERO"
21820   attribute \enum_value_011 "SPR"
21821   attribute \enum_value_100 "RS"
21822   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21823   wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel
21824   attribute \enum_base_type "In2Sel"
21825   attribute \enum_value_0000 "NONE"
21826   attribute \enum_value_0001 "RB"
21827   attribute \enum_value_0010 "CONST_UI"
21828   attribute \enum_value_0011 "CONST_SI"
21829   attribute \enum_value_0100 "CONST_UI_HI"
21830   attribute \enum_value_0101 "CONST_SI_HI"
21831   attribute \enum_value_0110 "CONST_LI"
21832   attribute \enum_value_0111 "CONST_BD"
21833   attribute \enum_value_1000 "CONST_DS"
21834   attribute \enum_value_1001 "CONST_M1"
21835   attribute \enum_value_1010 "CONST_SH"
21836   attribute \enum_value_1011 "CONST_SH32"
21837   attribute \enum_value_1100 "SPR"
21838   attribute \enum_value_1101 "RS"
21839   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21840   wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel
21841   attribute \enum_base_type "In3Sel"
21842   attribute \enum_value_00 "NONE"
21843   attribute \enum_value_01 "RS"
21844   attribute \enum_value_10 "RB"
21845   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21846   wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel
21847   attribute \enum_base_type "MicrOp"
21848   attribute \enum_value_0000000 "OP_ILLEGAL"
21849   attribute \enum_value_0000001 "OP_NOP"
21850   attribute \enum_value_0000010 "OP_ADD"
21851   attribute \enum_value_0000011 "OP_ADDPCIS"
21852   attribute \enum_value_0000100 "OP_AND"
21853   attribute \enum_value_0000101 "OP_ATTN"
21854   attribute \enum_value_0000110 "OP_B"
21855   attribute \enum_value_0000111 "OP_BC"
21856   attribute \enum_value_0001000 "OP_BCREG"
21857   attribute \enum_value_0001001 "OP_BPERM"
21858   attribute \enum_value_0001010 "OP_CMP"
21859   attribute \enum_value_0001011 "OP_CMPB"
21860   attribute \enum_value_0001100 "OP_CMPEQB"
21861   attribute \enum_value_0001101 "OP_CMPRB"
21862   attribute \enum_value_0001110 "OP_CNTZ"
21863   attribute \enum_value_0001111 "OP_CRAND"
21864   attribute \enum_value_0010000 "OP_CRANDC"
21865   attribute \enum_value_0010001 "OP_CREQV"
21866   attribute \enum_value_0010010 "OP_CRNAND"
21867   attribute \enum_value_0010011 "OP_CRNOR"
21868   attribute \enum_value_0010100 "OP_CROR"
21869   attribute \enum_value_0010101 "OP_CRORC"
21870   attribute \enum_value_0010110 "OP_CRXOR"
21871   attribute \enum_value_0010111 "OP_DARN"
21872   attribute \enum_value_0011000 "OP_DCBF"
21873   attribute \enum_value_0011001 "OP_DCBST"
21874   attribute \enum_value_0011010 "OP_DCBT"
21875   attribute \enum_value_0011011 "OP_DCBTST"
21876   attribute \enum_value_0011100 "OP_DCBZ"
21877   attribute \enum_value_0011101 "OP_DIV"
21878   attribute \enum_value_0011110 "OP_DIVE"
21879   attribute \enum_value_0011111 "OP_EXTS"
21880   attribute \enum_value_0100000 "OP_EXTSWSLI"
21881   attribute \enum_value_0100001 "OP_ICBI"
21882   attribute \enum_value_0100010 "OP_ICBT"
21883   attribute \enum_value_0100011 "OP_ISEL"
21884   attribute \enum_value_0100100 "OP_ISYNC"
21885   attribute \enum_value_0100101 "OP_LOAD"
21886   attribute \enum_value_0100110 "OP_STORE"
21887   attribute \enum_value_0100111 "OP_MADDHD"
21888   attribute \enum_value_0101000 "OP_MADDHDU"
21889   attribute \enum_value_0101001 "OP_MADDLD"
21890   attribute \enum_value_0101010 "OP_MCRF"
21891   attribute \enum_value_0101011 "OP_MCRXR"
21892   attribute \enum_value_0101100 "OP_MCRXRX"
21893   attribute \enum_value_0101101 "OP_MFCR"
21894   attribute \enum_value_0101110 "OP_MFSPR"
21895   attribute \enum_value_0101111 "OP_MOD"
21896   attribute \enum_value_0110000 "OP_MTCRF"
21897   attribute \enum_value_0110001 "OP_MTSPR"
21898   attribute \enum_value_0110010 "OP_MUL_L64"
21899   attribute \enum_value_0110011 "OP_MUL_H64"
21900   attribute \enum_value_0110100 "OP_MUL_H32"
21901   attribute \enum_value_0110101 "OP_OR"
21902   attribute \enum_value_0110110 "OP_POPCNT"
21903   attribute \enum_value_0110111 "OP_PRTY"
21904   attribute \enum_value_0111000 "OP_RLC"
21905   attribute \enum_value_0111001 "OP_RLCL"
21906   attribute \enum_value_0111010 "OP_RLCR"
21907   attribute \enum_value_0111011 "OP_SETB"
21908   attribute \enum_value_0111100 "OP_SHL"
21909   attribute \enum_value_0111101 "OP_SHR"
21910   attribute \enum_value_0111110 "OP_SYNC"
21911   attribute \enum_value_0111111 "OP_TRAP"
21912   attribute \enum_value_1000011 "OP_XOR"
21913   attribute \enum_value_1000100 "OP_SIM_CONFIG"
21914   attribute \enum_value_1000101 "OP_CROP"
21915   attribute \enum_value_1000110 "OP_RFID"
21916   attribute \enum_value_1000111 "OP_MFMSR"
21917   attribute \enum_value_1001000 "OP_MTMSRD"
21918   attribute \enum_value_1001001 "OP_SC"
21919   attribute \enum_value_1001010 "OP_MTMSR"
21920   attribute \enum_value_1001011 "OP_TLBIE"
21921   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21922   wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op
21923   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21924   wire \dec31_dec_sub26_dec31_dec_sub26_inv_a
21925   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21926   wire \dec31_dec_sub26_dec31_dec_sub26_inv_out
21927   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21928   wire \dec31_dec_sub26_dec31_dec_sub26_is_32b
21929   attribute \enum_base_type "LdstLen"
21930   attribute \enum_value_0000 "NONE"
21931   attribute \enum_value_0001 "is1B"
21932   attribute \enum_value_0010 "is2B"
21933   attribute \enum_value_0100 "is4B"
21934   attribute \enum_value_1000 "is8B"
21935   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21936   wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len
21937   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21938   wire \dec31_dec_sub26_dec31_dec_sub26_lk
21939   attribute \enum_base_type "OutSel"
21940   attribute \enum_value_00 "NONE"
21941   attribute \enum_value_01 "RT"
21942   attribute \enum_value_10 "RA"
21943   attribute \enum_value_11 "SPR"
21944   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21945   wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel
21946   attribute \enum_base_type "RC"
21947   attribute \enum_value_00 "NONE"
21948   attribute \enum_value_01 "ONE"
21949   attribute \enum_value_10 "RC"
21950   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21951   wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel
21952   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21953   wire \dec31_dec_sub26_dec31_dec_sub26_rsrv
21954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21955   wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe
21956   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21957   wire \dec31_dec_sub26_dec31_dec_sub26_sgn
21958   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21959   wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext
21960   attribute \enum_base_type "LDSTMode"
21961   attribute \enum_value_00 "NONE"
21962   attribute \enum_value_01 "update"
21963   attribute \enum_value_10 "cix"
21964   attribute \enum_value_11 "cx"
21965   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21966   wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd
21967   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
21968   wire width 32 \dec31_dec_sub26_opcode_in
21969   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21970   wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode
21971   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21972   wire \dec31_dec_sub27_dec31_dec_sub27_br
21973   attribute \enum_base_type "CRInSel"
21974   attribute \enum_value_000 "NONE"
21975   attribute \enum_value_001 "CR0"
21976   attribute \enum_value_010 "BI"
21977   attribute \enum_value_011 "BFA"
21978   attribute \enum_value_100 "BA_BB"
21979   attribute \enum_value_101 "BC"
21980   attribute \enum_value_110 "WHOLE_REG"
21981   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21982   wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in
21983   attribute \enum_base_type "CROutSel"
21984   attribute \enum_value_000 "NONE"
21985   attribute \enum_value_001 "CR0"
21986   attribute \enum_value_010 "BF"
21987   attribute \enum_value_011 "BT"
21988   attribute \enum_value_100 "WHOLE_REG"
21989   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21990   wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out
21991   attribute \enum_base_type "CryIn"
21992   attribute \enum_value_00 "ZERO"
21993   attribute \enum_value_01 "ONE"
21994   attribute \enum_value_10 "CA"
21995   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
21996   wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in
21997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
21998   wire \dec31_dec_sub27_dec31_dec_sub27_cry_out
21999   attribute \enum_base_type "Form"
22000   attribute \enum_value_00000 "NONE"
22001   attribute \enum_value_00001 "I"
22002   attribute \enum_value_00010 "B"
22003   attribute \enum_value_00011 "SC"
22004   attribute \enum_value_00100 "D"
22005   attribute \enum_value_00101 "DS"
22006   attribute \enum_value_00110 "DQ"
22007   attribute \enum_value_00111 "DX"
22008   attribute \enum_value_01000 "X"
22009   attribute \enum_value_01001 "XL"
22010   attribute \enum_value_01010 "XFX"
22011   attribute \enum_value_01011 "XFL"
22012   attribute \enum_value_01100 "XX1"
22013   attribute \enum_value_01101 "XX2"
22014   attribute \enum_value_01110 "XX3"
22015   attribute \enum_value_01111 "XX4"
22016   attribute \enum_value_10000 "XS"
22017   attribute \enum_value_10001 "XO"
22018   attribute \enum_value_10010 "A"
22019   attribute \enum_value_10011 "M"
22020   attribute \enum_value_10100 "MD"
22021   attribute \enum_value_10101 "MDS"
22022   attribute \enum_value_10110 "VA"
22023   attribute \enum_value_10111 "VC"
22024   attribute \enum_value_11000 "VX"
22025   attribute \enum_value_11001 "EVX"
22026   attribute \enum_value_11010 "EVS"
22027   attribute \enum_value_11011 "Z22"
22028   attribute \enum_value_11100 "Z23"
22029   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22030   wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form
22031   attribute \enum_base_type "Function"
22032   attribute \enum_value_000000000000 "NONE"
22033   attribute \enum_value_000000000010 "ALU"
22034   attribute \enum_value_000000000100 "LDST"
22035   attribute \enum_value_000000001000 "SHIFT_ROT"
22036   attribute \enum_value_000000010000 "LOGICAL"
22037   attribute \enum_value_000000100000 "BRANCH"
22038   attribute \enum_value_000001000000 "CR"
22039   attribute \enum_value_000010000000 "TRAP"
22040   attribute \enum_value_000100000000 "MUL"
22041   attribute \enum_value_001000000000 "DIV"
22042   attribute \enum_value_010000000000 "SPR"
22043   attribute \enum_value_100000000000 "MMU"
22044   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22045   wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit
22046   attribute \enum_base_type "In1Sel"
22047   attribute \enum_value_000 "NONE"
22048   attribute \enum_value_001 "RA"
22049   attribute \enum_value_010 "RA_OR_ZERO"
22050   attribute \enum_value_011 "SPR"
22051   attribute \enum_value_100 "RS"
22052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22053   wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel
22054   attribute \enum_base_type "In2Sel"
22055   attribute \enum_value_0000 "NONE"
22056   attribute \enum_value_0001 "RB"
22057   attribute \enum_value_0010 "CONST_UI"
22058   attribute \enum_value_0011 "CONST_SI"
22059   attribute \enum_value_0100 "CONST_UI_HI"
22060   attribute \enum_value_0101 "CONST_SI_HI"
22061   attribute \enum_value_0110 "CONST_LI"
22062   attribute \enum_value_0111 "CONST_BD"
22063   attribute \enum_value_1000 "CONST_DS"
22064   attribute \enum_value_1001 "CONST_M1"
22065   attribute \enum_value_1010 "CONST_SH"
22066   attribute \enum_value_1011 "CONST_SH32"
22067   attribute \enum_value_1100 "SPR"
22068   attribute \enum_value_1101 "RS"
22069   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22070   wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel
22071   attribute \enum_base_type "In3Sel"
22072   attribute \enum_value_00 "NONE"
22073   attribute \enum_value_01 "RS"
22074   attribute \enum_value_10 "RB"
22075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22076   wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel
22077   attribute \enum_base_type "MicrOp"
22078   attribute \enum_value_0000000 "OP_ILLEGAL"
22079   attribute \enum_value_0000001 "OP_NOP"
22080   attribute \enum_value_0000010 "OP_ADD"
22081   attribute \enum_value_0000011 "OP_ADDPCIS"
22082   attribute \enum_value_0000100 "OP_AND"
22083   attribute \enum_value_0000101 "OP_ATTN"
22084   attribute \enum_value_0000110 "OP_B"
22085   attribute \enum_value_0000111 "OP_BC"
22086   attribute \enum_value_0001000 "OP_BCREG"
22087   attribute \enum_value_0001001 "OP_BPERM"
22088   attribute \enum_value_0001010 "OP_CMP"
22089   attribute \enum_value_0001011 "OP_CMPB"
22090   attribute \enum_value_0001100 "OP_CMPEQB"
22091   attribute \enum_value_0001101 "OP_CMPRB"
22092   attribute \enum_value_0001110 "OP_CNTZ"
22093   attribute \enum_value_0001111 "OP_CRAND"
22094   attribute \enum_value_0010000 "OP_CRANDC"
22095   attribute \enum_value_0010001 "OP_CREQV"
22096   attribute \enum_value_0010010 "OP_CRNAND"
22097   attribute \enum_value_0010011 "OP_CRNOR"
22098   attribute \enum_value_0010100 "OP_CROR"
22099   attribute \enum_value_0010101 "OP_CRORC"
22100   attribute \enum_value_0010110 "OP_CRXOR"
22101   attribute \enum_value_0010111 "OP_DARN"
22102   attribute \enum_value_0011000 "OP_DCBF"
22103   attribute \enum_value_0011001 "OP_DCBST"
22104   attribute \enum_value_0011010 "OP_DCBT"
22105   attribute \enum_value_0011011 "OP_DCBTST"
22106   attribute \enum_value_0011100 "OP_DCBZ"
22107   attribute \enum_value_0011101 "OP_DIV"
22108   attribute \enum_value_0011110 "OP_DIVE"
22109   attribute \enum_value_0011111 "OP_EXTS"
22110   attribute \enum_value_0100000 "OP_EXTSWSLI"
22111   attribute \enum_value_0100001 "OP_ICBI"
22112   attribute \enum_value_0100010 "OP_ICBT"
22113   attribute \enum_value_0100011 "OP_ISEL"
22114   attribute \enum_value_0100100 "OP_ISYNC"
22115   attribute \enum_value_0100101 "OP_LOAD"
22116   attribute \enum_value_0100110 "OP_STORE"
22117   attribute \enum_value_0100111 "OP_MADDHD"
22118   attribute \enum_value_0101000 "OP_MADDHDU"
22119   attribute \enum_value_0101001 "OP_MADDLD"
22120   attribute \enum_value_0101010 "OP_MCRF"
22121   attribute \enum_value_0101011 "OP_MCRXR"
22122   attribute \enum_value_0101100 "OP_MCRXRX"
22123   attribute \enum_value_0101101 "OP_MFCR"
22124   attribute \enum_value_0101110 "OP_MFSPR"
22125   attribute \enum_value_0101111 "OP_MOD"
22126   attribute \enum_value_0110000 "OP_MTCRF"
22127   attribute \enum_value_0110001 "OP_MTSPR"
22128   attribute \enum_value_0110010 "OP_MUL_L64"
22129   attribute \enum_value_0110011 "OP_MUL_H64"
22130   attribute \enum_value_0110100 "OP_MUL_H32"
22131   attribute \enum_value_0110101 "OP_OR"
22132   attribute \enum_value_0110110 "OP_POPCNT"
22133   attribute \enum_value_0110111 "OP_PRTY"
22134   attribute \enum_value_0111000 "OP_RLC"
22135   attribute \enum_value_0111001 "OP_RLCL"
22136   attribute \enum_value_0111010 "OP_RLCR"
22137   attribute \enum_value_0111011 "OP_SETB"
22138   attribute \enum_value_0111100 "OP_SHL"
22139   attribute \enum_value_0111101 "OP_SHR"
22140   attribute \enum_value_0111110 "OP_SYNC"
22141   attribute \enum_value_0111111 "OP_TRAP"
22142   attribute \enum_value_1000011 "OP_XOR"
22143   attribute \enum_value_1000100 "OP_SIM_CONFIG"
22144   attribute \enum_value_1000101 "OP_CROP"
22145   attribute \enum_value_1000110 "OP_RFID"
22146   attribute \enum_value_1000111 "OP_MFMSR"
22147   attribute \enum_value_1001000 "OP_MTMSRD"
22148   attribute \enum_value_1001001 "OP_SC"
22149   attribute \enum_value_1001010 "OP_MTMSR"
22150   attribute \enum_value_1001011 "OP_TLBIE"
22151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22152   wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op
22153   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22154   wire \dec31_dec_sub27_dec31_dec_sub27_inv_a
22155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22156   wire \dec31_dec_sub27_dec31_dec_sub27_inv_out
22157   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22158   wire \dec31_dec_sub27_dec31_dec_sub27_is_32b
22159   attribute \enum_base_type "LdstLen"
22160   attribute \enum_value_0000 "NONE"
22161   attribute \enum_value_0001 "is1B"
22162   attribute \enum_value_0010 "is2B"
22163   attribute \enum_value_0100 "is4B"
22164   attribute \enum_value_1000 "is8B"
22165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22166   wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len
22167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22168   wire \dec31_dec_sub27_dec31_dec_sub27_lk
22169   attribute \enum_base_type "OutSel"
22170   attribute \enum_value_00 "NONE"
22171   attribute \enum_value_01 "RT"
22172   attribute \enum_value_10 "RA"
22173   attribute \enum_value_11 "SPR"
22174   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22175   wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel
22176   attribute \enum_base_type "RC"
22177   attribute \enum_value_00 "NONE"
22178   attribute \enum_value_01 "ONE"
22179   attribute \enum_value_10 "RC"
22180   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22181   wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel
22182   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22183   wire \dec31_dec_sub27_dec31_dec_sub27_rsrv
22184   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22185   wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe
22186   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22187   wire \dec31_dec_sub27_dec31_dec_sub27_sgn
22188   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22189   wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext
22190   attribute \enum_base_type "LDSTMode"
22191   attribute \enum_value_00 "NONE"
22192   attribute \enum_value_01 "update"
22193   attribute \enum_value_10 "cix"
22194   attribute \enum_value_11 "cx"
22195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22196   wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd
22197   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
22198   wire width 32 \dec31_dec_sub27_opcode_in
22199   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22200   wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode
22201   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22202   wire \dec31_dec_sub28_dec31_dec_sub28_br
22203   attribute \enum_base_type "CRInSel"
22204   attribute \enum_value_000 "NONE"
22205   attribute \enum_value_001 "CR0"
22206   attribute \enum_value_010 "BI"
22207   attribute \enum_value_011 "BFA"
22208   attribute \enum_value_100 "BA_BB"
22209   attribute \enum_value_101 "BC"
22210   attribute \enum_value_110 "WHOLE_REG"
22211   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22212   wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in
22213   attribute \enum_base_type "CROutSel"
22214   attribute \enum_value_000 "NONE"
22215   attribute \enum_value_001 "CR0"
22216   attribute \enum_value_010 "BF"
22217   attribute \enum_value_011 "BT"
22218   attribute \enum_value_100 "WHOLE_REG"
22219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22220   wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out
22221   attribute \enum_base_type "CryIn"
22222   attribute \enum_value_00 "ZERO"
22223   attribute \enum_value_01 "ONE"
22224   attribute \enum_value_10 "CA"
22225   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22226   wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in
22227   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22228   wire \dec31_dec_sub28_dec31_dec_sub28_cry_out
22229   attribute \enum_base_type "Form"
22230   attribute \enum_value_00000 "NONE"
22231   attribute \enum_value_00001 "I"
22232   attribute \enum_value_00010 "B"
22233   attribute \enum_value_00011 "SC"
22234   attribute \enum_value_00100 "D"
22235   attribute \enum_value_00101 "DS"
22236   attribute \enum_value_00110 "DQ"
22237   attribute \enum_value_00111 "DX"
22238   attribute \enum_value_01000 "X"
22239   attribute \enum_value_01001 "XL"
22240   attribute \enum_value_01010 "XFX"
22241   attribute \enum_value_01011 "XFL"
22242   attribute \enum_value_01100 "XX1"
22243   attribute \enum_value_01101 "XX2"
22244   attribute \enum_value_01110 "XX3"
22245   attribute \enum_value_01111 "XX4"
22246   attribute \enum_value_10000 "XS"
22247   attribute \enum_value_10001 "XO"
22248   attribute \enum_value_10010 "A"
22249   attribute \enum_value_10011 "M"
22250   attribute \enum_value_10100 "MD"
22251   attribute \enum_value_10101 "MDS"
22252   attribute \enum_value_10110 "VA"
22253   attribute \enum_value_10111 "VC"
22254   attribute \enum_value_11000 "VX"
22255   attribute \enum_value_11001 "EVX"
22256   attribute \enum_value_11010 "EVS"
22257   attribute \enum_value_11011 "Z22"
22258   attribute \enum_value_11100 "Z23"
22259   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22260   wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form
22261   attribute \enum_base_type "Function"
22262   attribute \enum_value_000000000000 "NONE"
22263   attribute \enum_value_000000000010 "ALU"
22264   attribute \enum_value_000000000100 "LDST"
22265   attribute \enum_value_000000001000 "SHIFT_ROT"
22266   attribute \enum_value_000000010000 "LOGICAL"
22267   attribute \enum_value_000000100000 "BRANCH"
22268   attribute \enum_value_000001000000 "CR"
22269   attribute \enum_value_000010000000 "TRAP"
22270   attribute \enum_value_000100000000 "MUL"
22271   attribute \enum_value_001000000000 "DIV"
22272   attribute \enum_value_010000000000 "SPR"
22273   attribute \enum_value_100000000000 "MMU"
22274   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22275   wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit
22276   attribute \enum_base_type "In1Sel"
22277   attribute \enum_value_000 "NONE"
22278   attribute \enum_value_001 "RA"
22279   attribute \enum_value_010 "RA_OR_ZERO"
22280   attribute \enum_value_011 "SPR"
22281   attribute \enum_value_100 "RS"
22282   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22283   wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel
22284   attribute \enum_base_type "In2Sel"
22285   attribute \enum_value_0000 "NONE"
22286   attribute \enum_value_0001 "RB"
22287   attribute \enum_value_0010 "CONST_UI"
22288   attribute \enum_value_0011 "CONST_SI"
22289   attribute \enum_value_0100 "CONST_UI_HI"
22290   attribute \enum_value_0101 "CONST_SI_HI"
22291   attribute \enum_value_0110 "CONST_LI"
22292   attribute \enum_value_0111 "CONST_BD"
22293   attribute \enum_value_1000 "CONST_DS"
22294   attribute \enum_value_1001 "CONST_M1"
22295   attribute \enum_value_1010 "CONST_SH"
22296   attribute \enum_value_1011 "CONST_SH32"
22297   attribute \enum_value_1100 "SPR"
22298   attribute \enum_value_1101 "RS"
22299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22300   wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel
22301   attribute \enum_base_type "In3Sel"
22302   attribute \enum_value_00 "NONE"
22303   attribute \enum_value_01 "RS"
22304   attribute \enum_value_10 "RB"
22305   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22306   wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel
22307   attribute \enum_base_type "MicrOp"
22308   attribute \enum_value_0000000 "OP_ILLEGAL"
22309   attribute \enum_value_0000001 "OP_NOP"
22310   attribute \enum_value_0000010 "OP_ADD"
22311   attribute \enum_value_0000011 "OP_ADDPCIS"
22312   attribute \enum_value_0000100 "OP_AND"
22313   attribute \enum_value_0000101 "OP_ATTN"
22314   attribute \enum_value_0000110 "OP_B"
22315   attribute \enum_value_0000111 "OP_BC"
22316   attribute \enum_value_0001000 "OP_BCREG"
22317   attribute \enum_value_0001001 "OP_BPERM"
22318   attribute \enum_value_0001010 "OP_CMP"
22319   attribute \enum_value_0001011 "OP_CMPB"
22320   attribute \enum_value_0001100 "OP_CMPEQB"
22321   attribute \enum_value_0001101 "OP_CMPRB"
22322   attribute \enum_value_0001110 "OP_CNTZ"
22323   attribute \enum_value_0001111 "OP_CRAND"
22324   attribute \enum_value_0010000 "OP_CRANDC"
22325   attribute \enum_value_0010001 "OP_CREQV"
22326   attribute \enum_value_0010010 "OP_CRNAND"
22327   attribute \enum_value_0010011 "OP_CRNOR"
22328   attribute \enum_value_0010100 "OP_CROR"
22329   attribute \enum_value_0010101 "OP_CRORC"
22330   attribute \enum_value_0010110 "OP_CRXOR"
22331   attribute \enum_value_0010111 "OP_DARN"
22332   attribute \enum_value_0011000 "OP_DCBF"
22333   attribute \enum_value_0011001 "OP_DCBST"
22334   attribute \enum_value_0011010 "OP_DCBT"
22335   attribute \enum_value_0011011 "OP_DCBTST"
22336   attribute \enum_value_0011100 "OP_DCBZ"
22337   attribute \enum_value_0011101 "OP_DIV"
22338   attribute \enum_value_0011110 "OP_DIVE"
22339   attribute \enum_value_0011111 "OP_EXTS"
22340   attribute \enum_value_0100000 "OP_EXTSWSLI"
22341   attribute \enum_value_0100001 "OP_ICBI"
22342   attribute \enum_value_0100010 "OP_ICBT"
22343   attribute \enum_value_0100011 "OP_ISEL"
22344   attribute \enum_value_0100100 "OP_ISYNC"
22345   attribute \enum_value_0100101 "OP_LOAD"
22346   attribute \enum_value_0100110 "OP_STORE"
22347   attribute \enum_value_0100111 "OP_MADDHD"
22348   attribute \enum_value_0101000 "OP_MADDHDU"
22349   attribute \enum_value_0101001 "OP_MADDLD"
22350   attribute \enum_value_0101010 "OP_MCRF"
22351   attribute \enum_value_0101011 "OP_MCRXR"
22352   attribute \enum_value_0101100 "OP_MCRXRX"
22353   attribute \enum_value_0101101 "OP_MFCR"
22354   attribute \enum_value_0101110 "OP_MFSPR"
22355   attribute \enum_value_0101111 "OP_MOD"
22356   attribute \enum_value_0110000 "OP_MTCRF"
22357   attribute \enum_value_0110001 "OP_MTSPR"
22358   attribute \enum_value_0110010 "OP_MUL_L64"
22359   attribute \enum_value_0110011 "OP_MUL_H64"
22360   attribute \enum_value_0110100 "OP_MUL_H32"
22361   attribute \enum_value_0110101 "OP_OR"
22362   attribute \enum_value_0110110 "OP_POPCNT"
22363   attribute \enum_value_0110111 "OP_PRTY"
22364   attribute \enum_value_0111000 "OP_RLC"
22365   attribute \enum_value_0111001 "OP_RLCL"
22366   attribute \enum_value_0111010 "OP_RLCR"
22367   attribute \enum_value_0111011 "OP_SETB"
22368   attribute \enum_value_0111100 "OP_SHL"
22369   attribute \enum_value_0111101 "OP_SHR"
22370   attribute \enum_value_0111110 "OP_SYNC"
22371   attribute \enum_value_0111111 "OP_TRAP"
22372   attribute \enum_value_1000011 "OP_XOR"
22373   attribute \enum_value_1000100 "OP_SIM_CONFIG"
22374   attribute \enum_value_1000101 "OP_CROP"
22375   attribute \enum_value_1000110 "OP_RFID"
22376   attribute \enum_value_1000111 "OP_MFMSR"
22377   attribute \enum_value_1001000 "OP_MTMSRD"
22378   attribute \enum_value_1001001 "OP_SC"
22379   attribute \enum_value_1001010 "OP_MTMSR"
22380   attribute \enum_value_1001011 "OP_TLBIE"
22381   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22382   wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op
22383   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22384   wire \dec31_dec_sub28_dec31_dec_sub28_inv_a
22385   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22386   wire \dec31_dec_sub28_dec31_dec_sub28_inv_out
22387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22388   wire \dec31_dec_sub28_dec31_dec_sub28_is_32b
22389   attribute \enum_base_type "LdstLen"
22390   attribute \enum_value_0000 "NONE"
22391   attribute \enum_value_0001 "is1B"
22392   attribute \enum_value_0010 "is2B"
22393   attribute \enum_value_0100 "is4B"
22394   attribute \enum_value_1000 "is8B"
22395   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22396   wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len
22397   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22398   wire \dec31_dec_sub28_dec31_dec_sub28_lk
22399   attribute \enum_base_type "OutSel"
22400   attribute \enum_value_00 "NONE"
22401   attribute \enum_value_01 "RT"
22402   attribute \enum_value_10 "RA"
22403   attribute \enum_value_11 "SPR"
22404   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22405   wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel
22406   attribute \enum_base_type "RC"
22407   attribute \enum_value_00 "NONE"
22408   attribute \enum_value_01 "ONE"
22409   attribute \enum_value_10 "RC"
22410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22411   wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel
22412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22413   wire \dec31_dec_sub28_dec31_dec_sub28_rsrv
22414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22415   wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe
22416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22417   wire \dec31_dec_sub28_dec31_dec_sub28_sgn
22418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22419   wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext
22420   attribute \enum_base_type "LDSTMode"
22421   attribute \enum_value_00 "NONE"
22422   attribute \enum_value_01 "update"
22423   attribute \enum_value_10 "cix"
22424   attribute \enum_value_11 "cx"
22425   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22426   wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd
22427   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
22428   wire width 32 \dec31_dec_sub28_opcode_in
22429   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22430   wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode
22431   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22432   wire \dec31_dec_sub4_dec31_dec_sub4_br
22433   attribute \enum_base_type "CRInSel"
22434   attribute \enum_value_000 "NONE"
22435   attribute \enum_value_001 "CR0"
22436   attribute \enum_value_010 "BI"
22437   attribute \enum_value_011 "BFA"
22438   attribute \enum_value_100 "BA_BB"
22439   attribute \enum_value_101 "BC"
22440   attribute \enum_value_110 "WHOLE_REG"
22441   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22442   wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in
22443   attribute \enum_base_type "CROutSel"
22444   attribute \enum_value_000 "NONE"
22445   attribute \enum_value_001 "CR0"
22446   attribute \enum_value_010 "BF"
22447   attribute \enum_value_011 "BT"
22448   attribute \enum_value_100 "WHOLE_REG"
22449   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22450   wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out
22451   attribute \enum_base_type "CryIn"
22452   attribute \enum_value_00 "ZERO"
22453   attribute \enum_value_01 "ONE"
22454   attribute \enum_value_10 "CA"
22455   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22456   wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in
22457   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22458   wire \dec31_dec_sub4_dec31_dec_sub4_cry_out
22459   attribute \enum_base_type "Form"
22460   attribute \enum_value_00000 "NONE"
22461   attribute \enum_value_00001 "I"
22462   attribute \enum_value_00010 "B"
22463   attribute \enum_value_00011 "SC"
22464   attribute \enum_value_00100 "D"
22465   attribute \enum_value_00101 "DS"
22466   attribute \enum_value_00110 "DQ"
22467   attribute \enum_value_00111 "DX"
22468   attribute \enum_value_01000 "X"
22469   attribute \enum_value_01001 "XL"
22470   attribute \enum_value_01010 "XFX"
22471   attribute \enum_value_01011 "XFL"
22472   attribute \enum_value_01100 "XX1"
22473   attribute \enum_value_01101 "XX2"
22474   attribute \enum_value_01110 "XX3"
22475   attribute \enum_value_01111 "XX4"
22476   attribute \enum_value_10000 "XS"
22477   attribute \enum_value_10001 "XO"
22478   attribute \enum_value_10010 "A"
22479   attribute \enum_value_10011 "M"
22480   attribute \enum_value_10100 "MD"
22481   attribute \enum_value_10101 "MDS"
22482   attribute \enum_value_10110 "VA"
22483   attribute \enum_value_10111 "VC"
22484   attribute \enum_value_11000 "VX"
22485   attribute \enum_value_11001 "EVX"
22486   attribute \enum_value_11010 "EVS"
22487   attribute \enum_value_11011 "Z22"
22488   attribute \enum_value_11100 "Z23"
22489   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22490   wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form
22491   attribute \enum_base_type "Function"
22492   attribute \enum_value_000000000000 "NONE"
22493   attribute \enum_value_000000000010 "ALU"
22494   attribute \enum_value_000000000100 "LDST"
22495   attribute \enum_value_000000001000 "SHIFT_ROT"
22496   attribute \enum_value_000000010000 "LOGICAL"
22497   attribute \enum_value_000000100000 "BRANCH"
22498   attribute \enum_value_000001000000 "CR"
22499   attribute \enum_value_000010000000 "TRAP"
22500   attribute \enum_value_000100000000 "MUL"
22501   attribute \enum_value_001000000000 "DIV"
22502   attribute \enum_value_010000000000 "SPR"
22503   attribute \enum_value_100000000000 "MMU"
22504   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22505   wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit
22506   attribute \enum_base_type "In1Sel"
22507   attribute \enum_value_000 "NONE"
22508   attribute \enum_value_001 "RA"
22509   attribute \enum_value_010 "RA_OR_ZERO"
22510   attribute \enum_value_011 "SPR"
22511   attribute \enum_value_100 "RS"
22512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22513   wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel
22514   attribute \enum_base_type "In2Sel"
22515   attribute \enum_value_0000 "NONE"
22516   attribute \enum_value_0001 "RB"
22517   attribute \enum_value_0010 "CONST_UI"
22518   attribute \enum_value_0011 "CONST_SI"
22519   attribute \enum_value_0100 "CONST_UI_HI"
22520   attribute \enum_value_0101 "CONST_SI_HI"
22521   attribute \enum_value_0110 "CONST_LI"
22522   attribute \enum_value_0111 "CONST_BD"
22523   attribute \enum_value_1000 "CONST_DS"
22524   attribute \enum_value_1001 "CONST_M1"
22525   attribute \enum_value_1010 "CONST_SH"
22526   attribute \enum_value_1011 "CONST_SH32"
22527   attribute \enum_value_1100 "SPR"
22528   attribute \enum_value_1101 "RS"
22529   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22530   wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel
22531   attribute \enum_base_type "In3Sel"
22532   attribute \enum_value_00 "NONE"
22533   attribute \enum_value_01 "RS"
22534   attribute \enum_value_10 "RB"
22535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22536   wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel
22537   attribute \enum_base_type "MicrOp"
22538   attribute \enum_value_0000000 "OP_ILLEGAL"
22539   attribute \enum_value_0000001 "OP_NOP"
22540   attribute \enum_value_0000010 "OP_ADD"
22541   attribute \enum_value_0000011 "OP_ADDPCIS"
22542   attribute \enum_value_0000100 "OP_AND"
22543   attribute \enum_value_0000101 "OP_ATTN"
22544   attribute \enum_value_0000110 "OP_B"
22545   attribute \enum_value_0000111 "OP_BC"
22546   attribute \enum_value_0001000 "OP_BCREG"
22547   attribute \enum_value_0001001 "OP_BPERM"
22548   attribute \enum_value_0001010 "OP_CMP"
22549   attribute \enum_value_0001011 "OP_CMPB"
22550   attribute \enum_value_0001100 "OP_CMPEQB"
22551   attribute \enum_value_0001101 "OP_CMPRB"
22552   attribute \enum_value_0001110 "OP_CNTZ"
22553   attribute \enum_value_0001111 "OP_CRAND"
22554   attribute \enum_value_0010000 "OP_CRANDC"
22555   attribute \enum_value_0010001 "OP_CREQV"
22556   attribute \enum_value_0010010 "OP_CRNAND"
22557   attribute \enum_value_0010011 "OP_CRNOR"
22558   attribute \enum_value_0010100 "OP_CROR"
22559   attribute \enum_value_0010101 "OP_CRORC"
22560   attribute \enum_value_0010110 "OP_CRXOR"
22561   attribute \enum_value_0010111 "OP_DARN"
22562   attribute \enum_value_0011000 "OP_DCBF"
22563   attribute \enum_value_0011001 "OP_DCBST"
22564   attribute \enum_value_0011010 "OP_DCBT"
22565   attribute \enum_value_0011011 "OP_DCBTST"
22566   attribute \enum_value_0011100 "OP_DCBZ"
22567   attribute \enum_value_0011101 "OP_DIV"
22568   attribute \enum_value_0011110 "OP_DIVE"
22569   attribute \enum_value_0011111 "OP_EXTS"
22570   attribute \enum_value_0100000 "OP_EXTSWSLI"
22571   attribute \enum_value_0100001 "OP_ICBI"
22572   attribute \enum_value_0100010 "OP_ICBT"
22573   attribute \enum_value_0100011 "OP_ISEL"
22574   attribute \enum_value_0100100 "OP_ISYNC"
22575   attribute \enum_value_0100101 "OP_LOAD"
22576   attribute \enum_value_0100110 "OP_STORE"
22577   attribute \enum_value_0100111 "OP_MADDHD"
22578   attribute \enum_value_0101000 "OP_MADDHDU"
22579   attribute \enum_value_0101001 "OP_MADDLD"
22580   attribute \enum_value_0101010 "OP_MCRF"
22581   attribute \enum_value_0101011 "OP_MCRXR"
22582   attribute \enum_value_0101100 "OP_MCRXRX"
22583   attribute \enum_value_0101101 "OP_MFCR"
22584   attribute \enum_value_0101110 "OP_MFSPR"
22585   attribute \enum_value_0101111 "OP_MOD"
22586   attribute \enum_value_0110000 "OP_MTCRF"
22587   attribute \enum_value_0110001 "OP_MTSPR"
22588   attribute \enum_value_0110010 "OP_MUL_L64"
22589   attribute \enum_value_0110011 "OP_MUL_H64"
22590   attribute \enum_value_0110100 "OP_MUL_H32"
22591   attribute \enum_value_0110101 "OP_OR"
22592   attribute \enum_value_0110110 "OP_POPCNT"
22593   attribute \enum_value_0110111 "OP_PRTY"
22594   attribute \enum_value_0111000 "OP_RLC"
22595   attribute \enum_value_0111001 "OP_RLCL"
22596   attribute \enum_value_0111010 "OP_RLCR"
22597   attribute \enum_value_0111011 "OP_SETB"
22598   attribute \enum_value_0111100 "OP_SHL"
22599   attribute \enum_value_0111101 "OP_SHR"
22600   attribute \enum_value_0111110 "OP_SYNC"
22601   attribute \enum_value_0111111 "OP_TRAP"
22602   attribute \enum_value_1000011 "OP_XOR"
22603   attribute \enum_value_1000100 "OP_SIM_CONFIG"
22604   attribute \enum_value_1000101 "OP_CROP"
22605   attribute \enum_value_1000110 "OP_RFID"
22606   attribute \enum_value_1000111 "OP_MFMSR"
22607   attribute \enum_value_1001000 "OP_MTMSRD"
22608   attribute \enum_value_1001001 "OP_SC"
22609   attribute \enum_value_1001010 "OP_MTMSR"
22610   attribute \enum_value_1001011 "OP_TLBIE"
22611   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22612   wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op
22613   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22614   wire \dec31_dec_sub4_dec31_dec_sub4_inv_a
22615   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22616   wire \dec31_dec_sub4_dec31_dec_sub4_inv_out
22617   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22618   wire \dec31_dec_sub4_dec31_dec_sub4_is_32b
22619   attribute \enum_base_type "LdstLen"
22620   attribute \enum_value_0000 "NONE"
22621   attribute \enum_value_0001 "is1B"
22622   attribute \enum_value_0010 "is2B"
22623   attribute \enum_value_0100 "is4B"
22624   attribute \enum_value_1000 "is8B"
22625   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22626   wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len
22627   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22628   wire \dec31_dec_sub4_dec31_dec_sub4_lk
22629   attribute \enum_base_type "OutSel"
22630   attribute \enum_value_00 "NONE"
22631   attribute \enum_value_01 "RT"
22632   attribute \enum_value_10 "RA"
22633   attribute \enum_value_11 "SPR"
22634   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22635   wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel
22636   attribute \enum_base_type "RC"
22637   attribute \enum_value_00 "NONE"
22638   attribute \enum_value_01 "ONE"
22639   attribute \enum_value_10 "RC"
22640   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22641   wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel
22642   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22643   wire \dec31_dec_sub4_dec31_dec_sub4_rsrv
22644   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22645   wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe
22646   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22647   wire \dec31_dec_sub4_dec31_dec_sub4_sgn
22648   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22649   wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext
22650   attribute \enum_base_type "LDSTMode"
22651   attribute \enum_value_00 "NONE"
22652   attribute \enum_value_01 "update"
22653   attribute \enum_value_10 "cix"
22654   attribute \enum_value_11 "cx"
22655   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22656   wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd
22657   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
22658   wire width 32 \dec31_dec_sub4_opcode_in
22659   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22660   wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode
22661   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22662   wire \dec31_dec_sub8_dec31_dec_sub8_br
22663   attribute \enum_base_type "CRInSel"
22664   attribute \enum_value_000 "NONE"
22665   attribute \enum_value_001 "CR0"
22666   attribute \enum_value_010 "BI"
22667   attribute \enum_value_011 "BFA"
22668   attribute \enum_value_100 "BA_BB"
22669   attribute \enum_value_101 "BC"
22670   attribute \enum_value_110 "WHOLE_REG"
22671   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22672   wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in
22673   attribute \enum_base_type "CROutSel"
22674   attribute \enum_value_000 "NONE"
22675   attribute \enum_value_001 "CR0"
22676   attribute \enum_value_010 "BF"
22677   attribute \enum_value_011 "BT"
22678   attribute \enum_value_100 "WHOLE_REG"
22679   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22680   wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out
22681   attribute \enum_base_type "CryIn"
22682   attribute \enum_value_00 "ZERO"
22683   attribute \enum_value_01 "ONE"
22684   attribute \enum_value_10 "CA"
22685   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22686   wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in
22687   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22688   wire \dec31_dec_sub8_dec31_dec_sub8_cry_out
22689   attribute \enum_base_type "Form"
22690   attribute \enum_value_00000 "NONE"
22691   attribute \enum_value_00001 "I"
22692   attribute \enum_value_00010 "B"
22693   attribute \enum_value_00011 "SC"
22694   attribute \enum_value_00100 "D"
22695   attribute \enum_value_00101 "DS"
22696   attribute \enum_value_00110 "DQ"
22697   attribute \enum_value_00111 "DX"
22698   attribute \enum_value_01000 "X"
22699   attribute \enum_value_01001 "XL"
22700   attribute \enum_value_01010 "XFX"
22701   attribute \enum_value_01011 "XFL"
22702   attribute \enum_value_01100 "XX1"
22703   attribute \enum_value_01101 "XX2"
22704   attribute \enum_value_01110 "XX3"
22705   attribute \enum_value_01111 "XX4"
22706   attribute \enum_value_10000 "XS"
22707   attribute \enum_value_10001 "XO"
22708   attribute \enum_value_10010 "A"
22709   attribute \enum_value_10011 "M"
22710   attribute \enum_value_10100 "MD"
22711   attribute \enum_value_10101 "MDS"
22712   attribute \enum_value_10110 "VA"
22713   attribute \enum_value_10111 "VC"
22714   attribute \enum_value_11000 "VX"
22715   attribute \enum_value_11001 "EVX"
22716   attribute \enum_value_11010 "EVS"
22717   attribute \enum_value_11011 "Z22"
22718   attribute \enum_value_11100 "Z23"
22719   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22720   wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form
22721   attribute \enum_base_type "Function"
22722   attribute \enum_value_000000000000 "NONE"
22723   attribute \enum_value_000000000010 "ALU"
22724   attribute \enum_value_000000000100 "LDST"
22725   attribute \enum_value_000000001000 "SHIFT_ROT"
22726   attribute \enum_value_000000010000 "LOGICAL"
22727   attribute \enum_value_000000100000 "BRANCH"
22728   attribute \enum_value_000001000000 "CR"
22729   attribute \enum_value_000010000000 "TRAP"
22730   attribute \enum_value_000100000000 "MUL"
22731   attribute \enum_value_001000000000 "DIV"
22732   attribute \enum_value_010000000000 "SPR"
22733   attribute \enum_value_100000000000 "MMU"
22734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22735   wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit
22736   attribute \enum_base_type "In1Sel"
22737   attribute \enum_value_000 "NONE"
22738   attribute \enum_value_001 "RA"
22739   attribute \enum_value_010 "RA_OR_ZERO"
22740   attribute \enum_value_011 "SPR"
22741   attribute \enum_value_100 "RS"
22742   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22743   wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel
22744   attribute \enum_base_type "In2Sel"
22745   attribute \enum_value_0000 "NONE"
22746   attribute \enum_value_0001 "RB"
22747   attribute \enum_value_0010 "CONST_UI"
22748   attribute \enum_value_0011 "CONST_SI"
22749   attribute \enum_value_0100 "CONST_UI_HI"
22750   attribute \enum_value_0101 "CONST_SI_HI"
22751   attribute \enum_value_0110 "CONST_LI"
22752   attribute \enum_value_0111 "CONST_BD"
22753   attribute \enum_value_1000 "CONST_DS"
22754   attribute \enum_value_1001 "CONST_M1"
22755   attribute \enum_value_1010 "CONST_SH"
22756   attribute \enum_value_1011 "CONST_SH32"
22757   attribute \enum_value_1100 "SPR"
22758   attribute \enum_value_1101 "RS"
22759   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22760   wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel
22761   attribute \enum_base_type "In3Sel"
22762   attribute \enum_value_00 "NONE"
22763   attribute \enum_value_01 "RS"
22764   attribute \enum_value_10 "RB"
22765   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22766   wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel
22767   attribute \enum_base_type "MicrOp"
22768   attribute \enum_value_0000000 "OP_ILLEGAL"
22769   attribute \enum_value_0000001 "OP_NOP"
22770   attribute \enum_value_0000010 "OP_ADD"
22771   attribute \enum_value_0000011 "OP_ADDPCIS"
22772   attribute \enum_value_0000100 "OP_AND"
22773   attribute \enum_value_0000101 "OP_ATTN"
22774   attribute \enum_value_0000110 "OP_B"
22775   attribute \enum_value_0000111 "OP_BC"
22776   attribute \enum_value_0001000 "OP_BCREG"
22777   attribute \enum_value_0001001 "OP_BPERM"
22778   attribute \enum_value_0001010 "OP_CMP"
22779   attribute \enum_value_0001011 "OP_CMPB"
22780   attribute \enum_value_0001100 "OP_CMPEQB"
22781   attribute \enum_value_0001101 "OP_CMPRB"
22782   attribute \enum_value_0001110 "OP_CNTZ"
22783   attribute \enum_value_0001111 "OP_CRAND"
22784   attribute \enum_value_0010000 "OP_CRANDC"
22785   attribute \enum_value_0010001 "OP_CREQV"
22786   attribute \enum_value_0010010 "OP_CRNAND"
22787   attribute \enum_value_0010011 "OP_CRNOR"
22788   attribute \enum_value_0010100 "OP_CROR"
22789   attribute \enum_value_0010101 "OP_CRORC"
22790   attribute \enum_value_0010110 "OP_CRXOR"
22791   attribute \enum_value_0010111 "OP_DARN"
22792   attribute \enum_value_0011000 "OP_DCBF"
22793   attribute \enum_value_0011001 "OP_DCBST"
22794   attribute \enum_value_0011010 "OP_DCBT"
22795   attribute \enum_value_0011011 "OP_DCBTST"
22796   attribute \enum_value_0011100 "OP_DCBZ"
22797   attribute \enum_value_0011101 "OP_DIV"
22798   attribute \enum_value_0011110 "OP_DIVE"
22799   attribute \enum_value_0011111 "OP_EXTS"
22800   attribute \enum_value_0100000 "OP_EXTSWSLI"
22801   attribute \enum_value_0100001 "OP_ICBI"
22802   attribute \enum_value_0100010 "OP_ICBT"
22803   attribute \enum_value_0100011 "OP_ISEL"
22804   attribute \enum_value_0100100 "OP_ISYNC"
22805   attribute \enum_value_0100101 "OP_LOAD"
22806   attribute \enum_value_0100110 "OP_STORE"
22807   attribute \enum_value_0100111 "OP_MADDHD"
22808   attribute \enum_value_0101000 "OP_MADDHDU"
22809   attribute \enum_value_0101001 "OP_MADDLD"
22810   attribute \enum_value_0101010 "OP_MCRF"
22811   attribute \enum_value_0101011 "OP_MCRXR"
22812   attribute \enum_value_0101100 "OP_MCRXRX"
22813   attribute \enum_value_0101101 "OP_MFCR"
22814   attribute \enum_value_0101110 "OP_MFSPR"
22815   attribute \enum_value_0101111 "OP_MOD"
22816   attribute \enum_value_0110000 "OP_MTCRF"
22817   attribute \enum_value_0110001 "OP_MTSPR"
22818   attribute \enum_value_0110010 "OP_MUL_L64"
22819   attribute \enum_value_0110011 "OP_MUL_H64"
22820   attribute \enum_value_0110100 "OP_MUL_H32"
22821   attribute \enum_value_0110101 "OP_OR"
22822   attribute \enum_value_0110110 "OP_POPCNT"
22823   attribute \enum_value_0110111 "OP_PRTY"
22824   attribute \enum_value_0111000 "OP_RLC"
22825   attribute \enum_value_0111001 "OP_RLCL"
22826   attribute \enum_value_0111010 "OP_RLCR"
22827   attribute \enum_value_0111011 "OP_SETB"
22828   attribute \enum_value_0111100 "OP_SHL"
22829   attribute \enum_value_0111101 "OP_SHR"
22830   attribute \enum_value_0111110 "OP_SYNC"
22831   attribute \enum_value_0111111 "OP_TRAP"
22832   attribute \enum_value_1000011 "OP_XOR"
22833   attribute \enum_value_1000100 "OP_SIM_CONFIG"
22834   attribute \enum_value_1000101 "OP_CROP"
22835   attribute \enum_value_1000110 "OP_RFID"
22836   attribute \enum_value_1000111 "OP_MFMSR"
22837   attribute \enum_value_1001000 "OP_MTMSRD"
22838   attribute \enum_value_1001001 "OP_SC"
22839   attribute \enum_value_1001010 "OP_MTMSR"
22840   attribute \enum_value_1001011 "OP_TLBIE"
22841   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22842   wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op
22843   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22844   wire \dec31_dec_sub8_dec31_dec_sub8_inv_a
22845   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22846   wire \dec31_dec_sub8_dec31_dec_sub8_inv_out
22847   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22848   wire \dec31_dec_sub8_dec31_dec_sub8_is_32b
22849   attribute \enum_base_type "LdstLen"
22850   attribute \enum_value_0000 "NONE"
22851   attribute \enum_value_0001 "is1B"
22852   attribute \enum_value_0010 "is2B"
22853   attribute \enum_value_0100 "is4B"
22854   attribute \enum_value_1000 "is8B"
22855   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22856   wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len
22857   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22858   wire \dec31_dec_sub8_dec31_dec_sub8_lk
22859   attribute \enum_base_type "OutSel"
22860   attribute \enum_value_00 "NONE"
22861   attribute \enum_value_01 "RT"
22862   attribute \enum_value_10 "RA"
22863   attribute \enum_value_11 "SPR"
22864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22865   wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel
22866   attribute \enum_base_type "RC"
22867   attribute \enum_value_00 "NONE"
22868   attribute \enum_value_01 "ONE"
22869   attribute \enum_value_10 "RC"
22870   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22871   wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel
22872   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22873   wire \dec31_dec_sub8_dec31_dec_sub8_rsrv
22874   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22875   wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe
22876   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22877   wire \dec31_dec_sub8_dec31_dec_sub8_sgn
22878   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22879   wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext
22880   attribute \enum_base_type "LDSTMode"
22881   attribute \enum_value_00 "NONE"
22882   attribute \enum_value_01 "update"
22883   attribute \enum_value_10 "cix"
22884   attribute \enum_value_11 "cx"
22885   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22886   wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd
22887   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
22888   wire width 32 \dec31_dec_sub8_opcode_in
22889   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22890   wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode
22891   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22892   wire \dec31_dec_sub9_dec31_dec_sub9_br
22893   attribute \enum_base_type "CRInSel"
22894   attribute \enum_value_000 "NONE"
22895   attribute \enum_value_001 "CR0"
22896   attribute \enum_value_010 "BI"
22897   attribute \enum_value_011 "BFA"
22898   attribute \enum_value_100 "BA_BB"
22899   attribute \enum_value_101 "BC"
22900   attribute \enum_value_110 "WHOLE_REG"
22901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22902   wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in
22903   attribute \enum_base_type "CROutSel"
22904   attribute \enum_value_000 "NONE"
22905   attribute \enum_value_001 "CR0"
22906   attribute \enum_value_010 "BF"
22907   attribute \enum_value_011 "BT"
22908   attribute \enum_value_100 "WHOLE_REG"
22909   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22910   wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out
22911   attribute \enum_base_type "CryIn"
22912   attribute \enum_value_00 "ZERO"
22913   attribute \enum_value_01 "ONE"
22914   attribute \enum_value_10 "CA"
22915   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22916   wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in
22917   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
22918   wire \dec31_dec_sub9_dec31_dec_sub9_cry_out
22919   attribute \enum_base_type "Form"
22920   attribute \enum_value_00000 "NONE"
22921   attribute \enum_value_00001 "I"
22922   attribute \enum_value_00010 "B"
22923   attribute \enum_value_00011 "SC"
22924   attribute \enum_value_00100 "D"
22925   attribute \enum_value_00101 "DS"
22926   attribute \enum_value_00110 "DQ"
22927   attribute \enum_value_00111 "DX"
22928   attribute \enum_value_01000 "X"
22929   attribute \enum_value_01001 "XL"
22930   attribute \enum_value_01010 "XFX"
22931   attribute \enum_value_01011 "XFL"
22932   attribute \enum_value_01100 "XX1"
22933   attribute \enum_value_01101 "XX2"
22934   attribute \enum_value_01110 "XX3"
22935   attribute \enum_value_01111 "XX4"
22936   attribute \enum_value_10000 "XS"
22937   attribute \enum_value_10001 "XO"
22938   attribute \enum_value_10010 "A"
22939   attribute \enum_value_10011 "M"
22940   attribute \enum_value_10100 "MD"
22941   attribute \enum_value_10101 "MDS"
22942   attribute \enum_value_10110 "VA"
22943   attribute \enum_value_10111 "VC"
22944   attribute \enum_value_11000 "VX"
22945   attribute \enum_value_11001 "EVX"
22946   attribute \enum_value_11010 "EVS"
22947   attribute \enum_value_11011 "Z22"
22948   attribute \enum_value_11100 "Z23"
22949   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22950   wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form
22951   attribute \enum_base_type "Function"
22952   attribute \enum_value_000000000000 "NONE"
22953   attribute \enum_value_000000000010 "ALU"
22954   attribute \enum_value_000000000100 "LDST"
22955   attribute \enum_value_000000001000 "SHIFT_ROT"
22956   attribute \enum_value_000000010000 "LOGICAL"
22957   attribute \enum_value_000000100000 "BRANCH"
22958   attribute \enum_value_000001000000 "CR"
22959   attribute \enum_value_000010000000 "TRAP"
22960   attribute \enum_value_000100000000 "MUL"
22961   attribute \enum_value_001000000000 "DIV"
22962   attribute \enum_value_010000000000 "SPR"
22963   attribute \enum_value_100000000000 "MMU"
22964   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22965   wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit
22966   attribute \enum_base_type "In1Sel"
22967   attribute \enum_value_000 "NONE"
22968   attribute \enum_value_001 "RA"
22969   attribute \enum_value_010 "RA_OR_ZERO"
22970   attribute \enum_value_011 "SPR"
22971   attribute \enum_value_100 "RS"
22972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22973   wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel
22974   attribute \enum_base_type "In2Sel"
22975   attribute \enum_value_0000 "NONE"
22976   attribute \enum_value_0001 "RB"
22977   attribute \enum_value_0010 "CONST_UI"
22978   attribute \enum_value_0011 "CONST_SI"
22979   attribute \enum_value_0100 "CONST_UI_HI"
22980   attribute \enum_value_0101 "CONST_SI_HI"
22981   attribute \enum_value_0110 "CONST_LI"
22982   attribute \enum_value_0111 "CONST_BD"
22983   attribute \enum_value_1000 "CONST_DS"
22984   attribute \enum_value_1001 "CONST_M1"
22985   attribute \enum_value_1010 "CONST_SH"
22986   attribute \enum_value_1011 "CONST_SH32"
22987   attribute \enum_value_1100 "SPR"
22988   attribute \enum_value_1101 "RS"
22989   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22990   wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel
22991   attribute \enum_base_type "In3Sel"
22992   attribute \enum_value_00 "NONE"
22993   attribute \enum_value_01 "RS"
22994   attribute \enum_value_10 "RB"
22995   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
22996   wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel
22997   attribute \enum_base_type "MicrOp"
22998   attribute \enum_value_0000000 "OP_ILLEGAL"
22999   attribute \enum_value_0000001 "OP_NOP"
23000   attribute \enum_value_0000010 "OP_ADD"
23001   attribute \enum_value_0000011 "OP_ADDPCIS"
23002   attribute \enum_value_0000100 "OP_AND"
23003   attribute \enum_value_0000101 "OP_ATTN"
23004   attribute \enum_value_0000110 "OP_B"
23005   attribute \enum_value_0000111 "OP_BC"
23006   attribute \enum_value_0001000 "OP_BCREG"
23007   attribute \enum_value_0001001 "OP_BPERM"
23008   attribute \enum_value_0001010 "OP_CMP"
23009   attribute \enum_value_0001011 "OP_CMPB"
23010   attribute \enum_value_0001100 "OP_CMPEQB"
23011   attribute \enum_value_0001101 "OP_CMPRB"
23012   attribute \enum_value_0001110 "OP_CNTZ"
23013   attribute \enum_value_0001111 "OP_CRAND"
23014   attribute \enum_value_0010000 "OP_CRANDC"
23015   attribute \enum_value_0010001 "OP_CREQV"
23016   attribute \enum_value_0010010 "OP_CRNAND"
23017   attribute \enum_value_0010011 "OP_CRNOR"
23018   attribute \enum_value_0010100 "OP_CROR"
23019   attribute \enum_value_0010101 "OP_CRORC"
23020   attribute \enum_value_0010110 "OP_CRXOR"
23021   attribute \enum_value_0010111 "OP_DARN"
23022   attribute \enum_value_0011000 "OP_DCBF"
23023   attribute \enum_value_0011001 "OP_DCBST"
23024   attribute \enum_value_0011010 "OP_DCBT"
23025   attribute \enum_value_0011011 "OP_DCBTST"
23026   attribute \enum_value_0011100 "OP_DCBZ"
23027   attribute \enum_value_0011101 "OP_DIV"
23028   attribute \enum_value_0011110 "OP_DIVE"
23029   attribute \enum_value_0011111 "OP_EXTS"
23030   attribute \enum_value_0100000 "OP_EXTSWSLI"
23031   attribute \enum_value_0100001 "OP_ICBI"
23032   attribute \enum_value_0100010 "OP_ICBT"
23033   attribute \enum_value_0100011 "OP_ISEL"
23034   attribute \enum_value_0100100 "OP_ISYNC"
23035   attribute \enum_value_0100101 "OP_LOAD"
23036   attribute \enum_value_0100110 "OP_STORE"
23037   attribute \enum_value_0100111 "OP_MADDHD"
23038   attribute \enum_value_0101000 "OP_MADDHDU"
23039   attribute \enum_value_0101001 "OP_MADDLD"
23040   attribute \enum_value_0101010 "OP_MCRF"
23041   attribute \enum_value_0101011 "OP_MCRXR"
23042   attribute \enum_value_0101100 "OP_MCRXRX"
23043   attribute \enum_value_0101101 "OP_MFCR"
23044   attribute \enum_value_0101110 "OP_MFSPR"
23045   attribute \enum_value_0101111 "OP_MOD"
23046   attribute \enum_value_0110000 "OP_MTCRF"
23047   attribute \enum_value_0110001 "OP_MTSPR"
23048   attribute \enum_value_0110010 "OP_MUL_L64"
23049   attribute \enum_value_0110011 "OP_MUL_H64"
23050   attribute \enum_value_0110100 "OP_MUL_H32"
23051   attribute \enum_value_0110101 "OP_OR"
23052   attribute \enum_value_0110110 "OP_POPCNT"
23053   attribute \enum_value_0110111 "OP_PRTY"
23054   attribute \enum_value_0111000 "OP_RLC"
23055   attribute \enum_value_0111001 "OP_RLCL"
23056   attribute \enum_value_0111010 "OP_RLCR"
23057   attribute \enum_value_0111011 "OP_SETB"
23058   attribute \enum_value_0111100 "OP_SHL"
23059   attribute \enum_value_0111101 "OP_SHR"
23060   attribute \enum_value_0111110 "OP_SYNC"
23061   attribute \enum_value_0111111 "OP_TRAP"
23062   attribute \enum_value_1000011 "OP_XOR"
23063   attribute \enum_value_1000100 "OP_SIM_CONFIG"
23064   attribute \enum_value_1000101 "OP_CROP"
23065   attribute \enum_value_1000110 "OP_RFID"
23066   attribute \enum_value_1000111 "OP_MFMSR"
23067   attribute \enum_value_1001000 "OP_MTMSRD"
23068   attribute \enum_value_1001001 "OP_SC"
23069   attribute \enum_value_1001010 "OP_MTMSR"
23070   attribute \enum_value_1001011 "OP_TLBIE"
23071   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23072   wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op
23073   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23074   wire \dec31_dec_sub9_dec31_dec_sub9_inv_a
23075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23076   wire \dec31_dec_sub9_dec31_dec_sub9_inv_out
23077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23078   wire \dec31_dec_sub9_dec31_dec_sub9_is_32b
23079   attribute \enum_base_type "LdstLen"
23080   attribute \enum_value_0000 "NONE"
23081   attribute \enum_value_0001 "is1B"
23082   attribute \enum_value_0010 "is2B"
23083   attribute \enum_value_0100 "is4B"
23084   attribute \enum_value_1000 "is8B"
23085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23086   wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len
23087   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23088   wire \dec31_dec_sub9_dec31_dec_sub9_lk
23089   attribute \enum_base_type "OutSel"
23090   attribute \enum_value_00 "NONE"
23091   attribute \enum_value_01 "RT"
23092   attribute \enum_value_10 "RA"
23093   attribute \enum_value_11 "SPR"
23094   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23095   wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel
23096   attribute \enum_base_type "RC"
23097   attribute \enum_value_00 "NONE"
23098   attribute \enum_value_01 "ONE"
23099   attribute \enum_value_10 "RC"
23100   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23101   wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel
23102   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23103   wire \dec31_dec_sub9_dec31_dec_sub9_rsrv
23104   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23105   wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe
23106   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23107   wire \dec31_dec_sub9_dec31_dec_sub9_sgn
23108   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23109   wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext
23110   attribute \enum_base_type "LDSTMode"
23111   attribute \enum_value_00 "NONE"
23112   attribute \enum_value_01 "update"
23113   attribute \enum_value_10 "cix"
23114   attribute \enum_value_11 "cx"
23115   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23116   wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd
23117   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
23118   wire width 32 \dec31_dec_sub9_opcode_in
23119   attribute \enum_base_type "Form"
23120   attribute \enum_value_00000 "NONE"
23121   attribute \enum_value_00001 "I"
23122   attribute \enum_value_00010 "B"
23123   attribute \enum_value_00011 "SC"
23124   attribute \enum_value_00100 "D"
23125   attribute \enum_value_00101 "DS"
23126   attribute \enum_value_00110 "DQ"
23127   attribute \enum_value_00111 "DX"
23128   attribute \enum_value_01000 "X"
23129   attribute \enum_value_01001 "XL"
23130   attribute \enum_value_01010 "XFX"
23131   attribute \enum_value_01011 "XFL"
23132   attribute \enum_value_01100 "XX1"
23133   attribute \enum_value_01101 "XX2"
23134   attribute \enum_value_01110 "XX3"
23135   attribute \enum_value_01111 "XX4"
23136   attribute \enum_value_10000 "XS"
23137   attribute \enum_value_10001 "XO"
23138   attribute \enum_value_10010 "A"
23139   attribute \enum_value_10011 "M"
23140   attribute \enum_value_10100 "MD"
23141   attribute \enum_value_10101 "MDS"
23142   attribute \enum_value_10110 "VA"
23143   attribute \enum_value_10111 "VC"
23144   attribute \enum_value_11000 "VX"
23145   attribute \enum_value_11001 "EVX"
23146   attribute \enum_value_11010 "EVS"
23147   attribute \enum_value_11011 "Z22"
23148   attribute \enum_value_11100 "Z23"
23149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23150   wire width 5 output 3 \dec31_form
23151   attribute \enum_base_type "Function"
23152   attribute \enum_value_000000000000 "NONE"
23153   attribute \enum_value_000000000010 "ALU"
23154   attribute \enum_value_000000000100 "LDST"
23155   attribute \enum_value_000000001000 "SHIFT_ROT"
23156   attribute \enum_value_000000010000 "LOGICAL"
23157   attribute \enum_value_000000100000 "BRANCH"
23158   attribute \enum_value_000001000000 "CR"
23159   attribute \enum_value_000010000000 "TRAP"
23160   attribute \enum_value_000100000000 "MUL"
23161   attribute \enum_value_001000000000 "DIV"
23162   attribute \enum_value_010000000000 "SPR"
23163   attribute \enum_value_100000000000 "MMU"
23164   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23165   wire width 12 output 1 \dec31_function_unit
23166   attribute \enum_base_type "In1Sel"
23167   attribute \enum_value_000 "NONE"
23168   attribute \enum_value_001 "RA"
23169   attribute \enum_value_010 "RA_OR_ZERO"
23170   attribute \enum_value_011 "SPR"
23171   attribute \enum_value_100 "RS"
23172   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23173   wire width 3 output 5 \dec31_in1_sel
23174   attribute \enum_base_type "In2Sel"
23175   attribute \enum_value_0000 "NONE"
23176   attribute \enum_value_0001 "RB"
23177   attribute \enum_value_0010 "CONST_UI"
23178   attribute \enum_value_0011 "CONST_SI"
23179   attribute \enum_value_0100 "CONST_UI_HI"
23180   attribute \enum_value_0101 "CONST_SI_HI"
23181   attribute \enum_value_0110 "CONST_LI"
23182   attribute \enum_value_0111 "CONST_BD"
23183   attribute \enum_value_1000 "CONST_DS"
23184   attribute \enum_value_1001 "CONST_M1"
23185   attribute \enum_value_1010 "CONST_SH"
23186   attribute \enum_value_1011 "CONST_SH32"
23187   attribute \enum_value_1100 "SPR"
23188   attribute \enum_value_1101 "RS"
23189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23190   wire width 4 output 6 \dec31_in2_sel
23191   attribute \enum_base_type "In3Sel"
23192   attribute \enum_value_00 "NONE"
23193   attribute \enum_value_01 "RS"
23194   attribute \enum_value_10 "RB"
23195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23196   wire width 2 output 7 \dec31_in3_sel
23197   attribute \enum_base_type "MicrOp"
23198   attribute \enum_value_0000000 "OP_ILLEGAL"
23199   attribute \enum_value_0000001 "OP_NOP"
23200   attribute \enum_value_0000010 "OP_ADD"
23201   attribute \enum_value_0000011 "OP_ADDPCIS"
23202   attribute \enum_value_0000100 "OP_AND"
23203   attribute \enum_value_0000101 "OP_ATTN"
23204   attribute \enum_value_0000110 "OP_B"
23205   attribute \enum_value_0000111 "OP_BC"
23206   attribute \enum_value_0001000 "OP_BCREG"
23207   attribute \enum_value_0001001 "OP_BPERM"
23208   attribute \enum_value_0001010 "OP_CMP"
23209   attribute \enum_value_0001011 "OP_CMPB"
23210   attribute \enum_value_0001100 "OP_CMPEQB"
23211   attribute \enum_value_0001101 "OP_CMPRB"
23212   attribute \enum_value_0001110 "OP_CNTZ"
23213   attribute \enum_value_0001111 "OP_CRAND"
23214   attribute \enum_value_0010000 "OP_CRANDC"
23215   attribute \enum_value_0010001 "OP_CREQV"
23216   attribute \enum_value_0010010 "OP_CRNAND"
23217   attribute \enum_value_0010011 "OP_CRNOR"
23218   attribute \enum_value_0010100 "OP_CROR"
23219   attribute \enum_value_0010101 "OP_CRORC"
23220   attribute \enum_value_0010110 "OP_CRXOR"
23221   attribute \enum_value_0010111 "OP_DARN"
23222   attribute \enum_value_0011000 "OP_DCBF"
23223   attribute \enum_value_0011001 "OP_DCBST"
23224   attribute \enum_value_0011010 "OP_DCBT"
23225   attribute \enum_value_0011011 "OP_DCBTST"
23226   attribute \enum_value_0011100 "OP_DCBZ"
23227   attribute \enum_value_0011101 "OP_DIV"
23228   attribute \enum_value_0011110 "OP_DIVE"
23229   attribute \enum_value_0011111 "OP_EXTS"
23230   attribute \enum_value_0100000 "OP_EXTSWSLI"
23231   attribute \enum_value_0100001 "OP_ICBI"
23232   attribute \enum_value_0100010 "OP_ICBT"
23233   attribute \enum_value_0100011 "OP_ISEL"
23234   attribute \enum_value_0100100 "OP_ISYNC"
23235   attribute \enum_value_0100101 "OP_LOAD"
23236   attribute \enum_value_0100110 "OP_STORE"
23237   attribute \enum_value_0100111 "OP_MADDHD"
23238   attribute \enum_value_0101000 "OP_MADDHDU"
23239   attribute \enum_value_0101001 "OP_MADDLD"
23240   attribute \enum_value_0101010 "OP_MCRF"
23241   attribute \enum_value_0101011 "OP_MCRXR"
23242   attribute \enum_value_0101100 "OP_MCRXRX"
23243   attribute \enum_value_0101101 "OP_MFCR"
23244   attribute \enum_value_0101110 "OP_MFSPR"
23245   attribute \enum_value_0101111 "OP_MOD"
23246   attribute \enum_value_0110000 "OP_MTCRF"
23247   attribute \enum_value_0110001 "OP_MTSPR"
23248   attribute \enum_value_0110010 "OP_MUL_L64"
23249   attribute \enum_value_0110011 "OP_MUL_H64"
23250   attribute \enum_value_0110100 "OP_MUL_H32"
23251   attribute \enum_value_0110101 "OP_OR"
23252   attribute \enum_value_0110110 "OP_POPCNT"
23253   attribute \enum_value_0110111 "OP_PRTY"
23254   attribute \enum_value_0111000 "OP_RLC"
23255   attribute \enum_value_0111001 "OP_RLCL"
23256   attribute \enum_value_0111010 "OP_RLCR"
23257   attribute \enum_value_0111011 "OP_SETB"
23258   attribute \enum_value_0111100 "OP_SHL"
23259   attribute \enum_value_0111101 "OP_SHR"
23260   attribute \enum_value_0111110 "OP_SYNC"
23261   attribute \enum_value_0111111 "OP_TRAP"
23262   attribute \enum_value_1000011 "OP_XOR"
23263   attribute \enum_value_1000100 "OP_SIM_CONFIG"
23264   attribute \enum_value_1000101 "OP_CROP"
23265   attribute \enum_value_1000110 "OP_RFID"
23266   attribute \enum_value_1000111 "OP_MFMSR"
23267   attribute \enum_value_1001000 "OP_MTMSRD"
23268   attribute \enum_value_1001001 "OP_SC"
23269   attribute \enum_value_1001010 "OP_MTMSR"
23270   attribute \enum_value_1001011 "OP_TLBIE"
23271   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23272   wire width 7 output 2 \dec31_internal_op
23273   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23274   wire output 15 \dec31_inv_a
23275   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23276   wire output 16 \dec31_inv_out
23277   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23278   wire output 21 \dec31_is_32b
23279   attribute \enum_base_type "LdstLen"
23280   attribute \enum_value_0000 "NONE"
23281   attribute \enum_value_0001 "is1B"
23282   attribute \enum_value_0010 "is2B"
23283   attribute \enum_value_0100 "is4B"
23284   attribute \enum_value_1000 "is8B"
23285   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23286   wire width 4 output 11 \dec31_ldst_len
23287   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23288   wire output 23 \dec31_lk
23289   attribute \enum_base_type "OutSel"
23290   attribute \enum_value_00 "NONE"
23291   attribute \enum_value_01 "RT"
23292   attribute \enum_value_10 "RA"
23293   attribute \enum_value_11 "SPR"
23294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23295   wire width 2 output 8 \dec31_out_sel
23296   attribute \enum_base_type "RC"
23297   attribute \enum_value_00 "NONE"
23298   attribute \enum_value_01 "ONE"
23299   attribute \enum_value_10 "RC"
23300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23301   wire width 2 output 13 \dec31_rc_sel
23302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23303   wire output 20 \dec31_rsrv
23304   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23305   wire output 24 \dec31_sgl_pipe
23306   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23307   wire output 22 \dec31_sgn
23308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
23309   wire output 19 \dec31_sgn_ext
23310   attribute \enum_base_type "LDSTMode"
23311   attribute \enum_value_00 "NONE"
23312   attribute \enum_value_01 "update"
23313   attribute \enum_value_10 "cix"
23314   attribute \enum_value_11 "cx"
23315   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
23316   wire width 2 output 12 \dec31_upd
23317   attribute \src "libresoc.v:11832.7-11832.15"
23318   wire \initial
23319   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
23320   wire width 5 \opc_in
23321   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
23322   wire width 32 input 25 \opcode_in
23323   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
23324   wire width 10 \opcode_switch
23325   attribute \module_not_derived 1
23326   attribute \src "libresoc.v:16231.18-16257.4"
23327   cell \dec31_dec_sub0 \dec31_dec_sub0
23328     connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode
23329     connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br
23330     connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in
23331     connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out
23332     connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in
23333     connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out
23334     connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form
23335     connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit
23336     connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel
23337     connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel
23338     connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel
23339     connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op
23340     connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a
23341     connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out
23342     connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b
23343     connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len
23344     connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk
23345     connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel
23346     connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel
23347     connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv
23348     connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe
23349     connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn
23350     connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext
23351     connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd
23352     connect \opcode_in \dec31_dec_sub0_opcode_in
23353   end
23354   attribute \module_not_derived 1
23355   attribute \src "libresoc.v:16258.19-16284.4"
23356   cell \dec31_dec_sub10 \dec31_dec_sub10
23357     connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode
23358     connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br
23359     connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in
23360     connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out
23361     connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in
23362     connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out
23363     connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form
23364     connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit
23365     connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel
23366     connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel
23367     connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel
23368     connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op
23369     connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a
23370     connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out
23371     connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b
23372     connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len
23373     connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk
23374     connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel
23375     connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel
23376     connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv
23377     connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe
23378     connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn
23379     connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext
23380     connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd
23381     connect \opcode_in \dec31_dec_sub10_opcode_in
23382   end
23383   attribute \module_not_derived 1
23384   attribute \src "libresoc.v:16285.19-16311.4"
23385   cell \dec31_dec_sub11 \dec31_dec_sub11
23386     connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode
23387     connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br
23388     connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in
23389     connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out
23390     connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in
23391     connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out
23392     connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form
23393     connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit
23394     connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel
23395     connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel
23396     connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel
23397     connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op
23398     connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a
23399     connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out
23400     connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b
23401     connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len
23402     connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk
23403     connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel
23404     connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel
23405     connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv
23406     connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe
23407     connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn
23408     connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext
23409     connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd
23410     connect \opcode_in \dec31_dec_sub11_opcode_in
23411   end
23412   attribute \module_not_derived 1
23413   attribute \src "libresoc.v:16312.19-16338.4"
23414   cell \dec31_dec_sub15 \dec31_dec_sub15
23415     connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode
23416     connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br
23417     connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in
23418     connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out
23419     connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in
23420     connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out
23421     connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form
23422     connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit
23423     connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel
23424     connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel
23425     connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel
23426     connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op
23427     connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a
23428     connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out
23429     connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b
23430     connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len
23431     connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk
23432     connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel
23433     connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel
23434     connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv
23435     connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe
23436     connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn
23437     connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext
23438     connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd
23439     connect \opcode_in \dec31_dec_sub15_opcode_in
23440   end
23441   attribute \module_not_derived 1
23442   attribute \src "libresoc.v:16339.19-16365.4"
23443   cell \dec31_dec_sub16 \dec31_dec_sub16
23444     connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode
23445     connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br
23446     connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in
23447     connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out
23448     connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in
23449     connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out
23450     connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form
23451     connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit
23452     connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel
23453     connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel
23454     connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel
23455     connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op
23456     connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a
23457     connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out
23458     connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b
23459     connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len
23460     connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk
23461     connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel
23462     connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel
23463     connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv
23464     connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe
23465     connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn
23466     connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext
23467     connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd
23468     connect \opcode_in \dec31_dec_sub16_opcode_in
23469   end
23470   attribute \module_not_derived 1
23471   attribute \src "libresoc.v:16366.19-16392.4"
23472   cell \dec31_dec_sub18 \dec31_dec_sub18
23473     connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode
23474     connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br
23475     connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in
23476     connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out
23477     connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in
23478     connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out
23479     connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form
23480     connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit
23481     connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel
23482     connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel
23483     connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel
23484     connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op
23485     connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a
23486     connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out
23487     connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b
23488     connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len
23489     connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk
23490     connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel
23491     connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel
23492     connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv
23493     connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe
23494     connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn
23495     connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext
23496     connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd
23497     connect \opcode_in \dec31_dec_sub18_opcode_in
23498   end
23499   attribute \module_not_derived 1
23500   attribute \src "libresoc.v:16393.19-16419.4"
23501   cell \dec31_dec_sub19 \dec31_dec_sub19
23502     connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode
23503     connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br
23504     connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in
23505     connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out
23506     connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in
23507     connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out
23508     connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form
23509     connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit
23510     connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel
23511     connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel
23512     connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel
23513     connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op
23514     connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a
23515     connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out
23516     connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b
23517     connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len
23518     connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk
23519     connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel
23520     connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel
23521     connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv
23522     connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe
23523     connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn
23524     connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext
23525     connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd
23526     connect \opcode_in \dec31_dec_sub19_opcode_in
23527   end
23528   attribute \module_not_derived 1
23529   attribute \src "libresoc.v:16420.19-16446.4"
23530   cell \dec31_dec_sub20 \dec31_dec_sub20
23531     connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode
23532     connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br
23533     connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in
23534     connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out
23535     connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in
23536     connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out
23537     connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form
23538     connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit
23539     connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel
23540     connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel
23541     connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel
23542     connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op
23543     connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a
23544     connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out
23545     connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b
23546     connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len
23547     connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk
23548     connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel
23549     connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel
23550     connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv
23551     connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe
23552     connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn
23553     connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext
23554     connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd
23555     connect \opcode_in \dec31_dec_sub20_opcode_in
23556   end
23557   attribute \module_not_derived 1
23558   attribute \src "libresoc.v:16447.19-16473.4"
23559   cell \dec31_dec_sub21 \dec31_dec_sub21
23560     connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode
23561     connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br
23562     connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in
23563     connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out
23564     connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in
23565     connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out
23566     connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form
23567     connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit
23568     connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel
23569     connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel
23570     connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel
23571     connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op
23572     connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a
23573     connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out
23574     connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b
23575     connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len
23576     connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk
23577     connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel
23578     connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel
23579     connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv
23580     connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe
23581     connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn
23582     connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext
23583     connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd
23584     connect \opcode_in \dec31_dec_sub21_opcode_in
23585   end
23586   attribute \module_not_derived 1
23587   attribute \src "libresoc.v:16474.19-16500.4"
23588   cell \dec31_dec_sub22 \dec31_dec_sub22
23589     connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode
23590     connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br
23591     connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in
23592     connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out
23593     connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in
23594     connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out
23595     connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form
23596     connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit
23597     connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel
23598     connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel
23599     connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel
23600     connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op
23601     connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a
23602     connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out
23603     connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b
23604     connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len
23605     connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk
23606     connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel
23607     connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel
23608     connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv
23609     connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe
23610     connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn
23611     connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext
23612     connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd
23613     connect \opcode_in \dec31_dec_sub22_opcode_in
23614   end
23615   attribute \module_not_derived 1
23616   attribute \src "libresoc.v:16501.19-16527.4"
23617   cell \dec31_dec_sub23 \dec31_dec_sub23
23618     connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode
23619     connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br
23620     connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in
23621     connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out
23622     connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in
23623     connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out
23624     connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form
23625     connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit
23626     connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel
23627     connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel
23628     connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel
23629     connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op
23630     connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a
23631     connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out
23632     connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b
23633     connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len
23634     connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk
23635     connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel
23636     connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel
23637     connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv
23638     connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe
23639     connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn
23640     connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext
23641     connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd
23642     connect \opcode_in \dec31_dec_sub23_opcode_in
23643   end
23644   attribute \module_not_derived 1
23645   attribute \src "libresoc.v:16528.19-16554.4"
23646   cell \dec31_dec_sub24 \dec31_dec_sub24
23647     connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode
23648     connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br
23649     connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in
23650     connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out
23651     connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in
23652     connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out
23653     connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form
23654     connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit
23655     connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel
23656     connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel
23657     connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel
23658     connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op
23659     connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a
23660     connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out
23661     connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b
23662     connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len
23663     connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk
23664     connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel
23665     connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel
23666     connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv
23667     connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe
23668     connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn
23669     connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext
23670     connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd
23671     connect \opcode_in \dec31_dec_sub24_opcode_in
23672   end
23673   attribute \module_not_derived 1
23674   attribute \src "libresoc.v:16555.19-16581.4"
23675   cell \dec31_dec_sub26 \dec31_dec_sub26
23676     connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode
23677     connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br
23678     connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in
23679     connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out
23680     connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in
23681     connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out
23682     connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form
23683     connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit
23684     connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel
23685     connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel
23686     connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel
23687     connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op
23688     connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a
23689     connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out
23690     connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b
23691     connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len
23692     connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk
23693     connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel
23694     connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel
23695     connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv
23696     connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe
23697     connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn
23698     connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext
23699     connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd
23700     connect \opcode_in \dec31_dec_sub26_opcode_in
23701   end
23702   attribute \module_not_derived 1
23703   attribute \src "libresoc.v:16582.19-16608.4"
23704   cell \dec31_dec_sub27 \dec31_dec_sub27
23705     connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode
23706     connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br
23707     connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in
23708     connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out
23709     connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in
23710     connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out
23711     connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form
23712     connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit
23713     connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel
23714     connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel
23715     connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel
23716     connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op
23717     connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a
23718     connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out
23719     connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b
23720     connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len
23721     connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk
23722     connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel
23723     connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel
23724     connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv
23725     connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe
23726     connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn
23727     connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext
23728     connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd
23729     connect \opcode_in \dec31_dec_sub27_opcode_in
23730   end
23731   attribute \module_not_derived 1
23732   attribute \src "libresoc.v:16609.19-16635.4"
23733   cell \dec31_dec_sub28 \dec31_dec_sub28
23734     connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode
23735     connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br
23736     connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in
23737     connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out
23738     connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in
23739     connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out
23740     connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form
23741     connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit
23742     connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel
23743     connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel
23744     connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel
23745     connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op
23746     connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a
23747     connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out
23748     connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b
23749     connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len
23750     connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk
23751     connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel
23752     connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel
23753     connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv
23754     connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe
23755     connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn
23756     connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext
23757     connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd
23758     connect \opcode_in \dec31_dec_sub28_opcode_in
23759   end
23760   attribute \module_not_derived 1
23761   attribute \src "libresoc.v:16636.18-16662.4"
23762   cell \dec31_dec_sub4 \dec31_dec_sub4
23763     connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode
23764     connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br
23765     connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in
23766     connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out
23767     connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in
23768     connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out
23769     connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form
23770     connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit
23771     connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel
23772     connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel
23773     connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel
23774     connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op
23775     connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a
23776     connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out
23777     connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b
23778     connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len
23779     connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk
23780     connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel
23781     connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel
23782     connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv
23783     connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe
23784     connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn
23785     connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext
23786     connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd
23787     connect \opcode_in \dec31_dec_sub4_opcode_in
23788   end
23789   attribute \module_not_derived 1
23790   attribute \src "libresoc.v:16663.18-16689.4"
23791   cell \dec31_dec_sub8 \dec31_dec_sub8
23792     connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode
23793     connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br
23794     connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in
23795     connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out
23796     connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in
23797     connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out
23798     connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form
23799     connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit
23800     connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel
23801     connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel
23802     connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel
23803     connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op
23804     connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a
23805     connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out
23806     connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b
23807     connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len
23808     connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk
23809     connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel
23810     connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel
23811     connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv
23812     connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe
23813     connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn
23814     connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext
23815     connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd
23816     connect \opcode_in \dec31_dec_sub8_opcode_in
23817   end
23818   attribute \module_not_derived 1
23819   attribute \src "libresoc.v:16690.18-16716.4"
23820   cell \dec31_dec_sub9 \dec31_dec_sub9
23821     connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode
23822     connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br
23823     connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in
23824     connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out
23825     connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in
23826     connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out
23827     connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form
23828     connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit
23829     connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel
23830     connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel
23831     connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel
23832     connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op
23833     connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a
23834     connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out
23835     connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b
23836     connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len
23837     connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk
23838     connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel
23839     connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel
23840     connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv
23841     connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe
23842     connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn
23843     connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext
23844     connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd
23845     connect \opcode_in \dec31_dec_sub9_opcode_in
23846   end
23847   attribute \src "libresoc.v:11832.7-11832.20"
23848   process $proc$libresoc.v:11832$406
23849     assign { } { }
23850     assign $0\initial[0:0] 1'0
23851     sync always
23852       update \initial $0\initial[0:0]
23853     sync init
23854   end
23855   attribute \src "libresoc.v:16717.3-16777.6"
23856   process $proc$libresoc.v:16717$382
23857     assign { } { }
23858     assign { } { }
23859     assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0]
23860     attribute \src "libresoc.v:16718.5-16718.29"
23861     switch \initial
23862       attribute \src "libresoc.v:16718.9-16718.17"
23863       case 1'1
23864       case
23865     end
23866     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
23867     switch \opc_in
23868       attribute \src "libresoc.v:0.0-0.0"
23869       case 5'01010
23870         assign { } { }
23871         assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit
23872       attribute \src "libresoc.v:0.0-0.0"
23873       case 5'11100
23874         assign { } { }
23875         assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit
23876       attribute \src "libresoc.v:0.0-0.0"
23877       case 5'00000
23878         assign { } { }
23879         assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit
23880       attribute \src "libresoc.v:0.0-0.0"
23881       case 5'11010
23882         assign { } { }
23883         assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit
23884       attribute \src "libresoc.v:0.0-0.0"
23885       case 5'10011
23886         assign { } { }
23887         assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit
23888       attribute \src "libresoc.v:0.0-0.0"
23889       case 5'10110
23890         assign { } { }
23891         assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit
23892       attribute \src "libresoc.v:0.0-0.0"
23893       case 5'01001
23894         assign { } { }
23895         assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit
23896       attribute \src "libresoc.v:0.0-0.0"
23897       case 5'01011
23898         assign { } { }
23899         assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit
23900       attribute \src "libresoc.v:0.0-0.0"
23901       case 5'11011
23902         assign { } { }
23903         assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit
23904       attribute \src "libresoc.v:0.0-0.0"
23905       case 5'01111
23906         assign { } { }
23907         assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit
23908       attribute \src "libresoc.v:0.0-0.0"
23909       case 5'10100
23910         assign { } { }
23911         assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit
23912       attribute \src "libresoc.v:0.0-0.0"
23913       case 5'10101
23914         assign { } { }
23915         assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit
23916       attribute \src "libresoc.v:0.0-0.0"
23917       case 5'10111
23918         assign { } { }
23919         assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit
23920       attribute \src "libresoc.v:0.0-0.0"
23921       case 5'10000
23922         assign { } { }
23923         assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit
23924       attribute \src "libresoc.v:0.0-0.0"
23925       case 5'10010
23926         assign { } { }
23927         assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit
23928       attribute \src "libresoc.v:0.0-0.0"
23929       case 5'01000
23930         assign { } { }
23931         assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit
23932       attribute \src "libresoc.v:0.0-0.0"
23933       case 5'11000
23934         assign { } { }
23935         assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit
23936       attribute \src "libresoc.v:0.0-0.0"
23937       case 5'00100
23938         assign { } { }
23939         assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit
23940       case
23941         assign $1\dec31_function_unit[11:0] 12'000000000000
23942     end
23943     sync always
23944       update \dec31_function_unit $0\dec31_function_unit[11:0]
23945   end
23946   attribute \src "libresoc.v:16778.3-16838.6"
23947   process $proc$libresoc.v:16778$383
23948     assign { } { }
23949     assign { } { }
23950     assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0]
23951     attribute \src "libresoc.v:16779.5-16779.29"
23952     switch \initial
23953       attribute \src "libresoc.v:16779.9-16779.17"
23954       case 1'1
23955       case
23956     end
23957     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
23958     switch \opc_in
23959       attribute \src "libresoc.v:0.0-0.0"
23960       case 5'01010
23961         assign { } { }
23962         assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op
23963       attribute \src "libresoc.v:0.0-0.0"
23964       case 5'11100
23965         assign { } { }
23966         assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op
23967       attribute \src "libresoc.v:0.0-0.0"
23968       case 5'00000
23969         assign { } { }
23970         assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op
23971       attribute \src "libresoc.v:0.0-0.0"
23972       case 5'11010
23973         assign { } { }
23974         assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op
23975       attribute \src "libresoc.v:0.0-0.0"
23976       case 5'10011
23977         assign { } { }
23978         assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op
23979       attribute \src "libresoc.v:0.0-0.0"
23980       case 5'10110
23981         assign { } { }
23982         assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op
23983       attribute \src "libresoc.v:0.0-0.0"
23984       case 5'01001
23985         assign { } { }
23986         assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op
23987       attribute \src "libresoc.v:0.0-0.0"
23988       case 5'01011
23989         assign { } { }
23990         assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op
23991       attribute \src "libresoc.v:0.0-0.0"
23992       case 5'11011
23993         assign { } { }
23994         assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op
23995       attribute \src "libresoc.v:0.0-0.0"
23996       case 5'01111
23997         assign { } { }
23998         assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op
23999       attribute \src "libresoc.v:0.0-0.0"
24000       case 5'10100
24001         assign { } { }
24002         assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op
24003       attribute \src "libresoc.v:0.0-0.0"
24004       case 5'10101
24005         assign { } { }
24006         assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op
24007       attribute \src "libresoc.v:0.0-0.0"
24008       case 5'10111
24009         assign { } { }
24010         assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op
24011       attribute \src "libresoc.v:0.0-0.0"
24012       case 5'10000
24013         assign { } { }
24014         assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op
24015       attribute \src "libresoc.v:0.0-0.0"
24016       case 5'10010
24017         assign { } { }
24018         assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op
24019       attribute \src "libresoc.v:0.0-0.0"
24020       case 5'01000
24021         assign { } { }
24022         assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op
24023       attribute \src "libresoc.v:0.0-0.0"
24024       case 5'11000
24025         assign { } { }
24026         assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op
24027       attribute \src "libresoc.v:0.0-0.0"
24028       case 5'00100
24029         assign { } { }
24030         assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op
24031       case
24032         assign $1\dec31_internal_op[6:0] 7'0000000
24033     end
24034     sync always
24035       update \dec31_internal_op $0\dec31_internal_op[6:0]
24036   end
24037   attribute \src "libresoc.v:16839.3-16899.6"
24038   process $proc$libresoc.v:16839$384
24039     assign { } { }
24040     assign { } { }
24041     assign $0\dec31_form[4:0] $1\dec31_form[4:0]
24042     attribute \src "libresoc.v:16840.5-16840.29"
24043     switch \initial
24044       attribute \src "libresoc.v:16840.9-16840.17"
24045       case 1'1
24046       case
24047     end
24048     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24049     switch \opc_in
24050       attribute \src "libresoc.v:0.0-0.0"
24051       case 5'01010
24052         assign { } { }
24053         assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form
24054       attribute \src "libresoc.v:0.0-0.0"
24055       case 5'11100
24056         assign { } { }
24057         assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form
24058       attribute \src "libresoc.v:0.0-0.0"
24059       case 5'00000
24060         assign { } { }
24061         assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form
24062       attribute \src "libresoc.v:0.0-0.0"
24063       case 5'11010
24064         assign { } { }
24065         assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form
24066       attribute \src "libresoc.v:0.0-0.0"
24067       case 5'10011
24068         assign { } { }
24069         assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form
24070       attribute \src "libresoc.v:0.0-0.0"
24071       case 5'10110
24072         assign { } { }
24073         assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form
24074       attribute \src "libresoc.v:0.0-0.0"
24075       case 5'01001
24076         assign { } { }
24077         assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form
24078       attribute \src "libresoc.v:0.0-0.0"
24079       case 5'01011
24080         assign { } { }
24081         assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form
24082       attribute \src "libresoc.v:0.0-0.0"
24083       case 5'11011
24084         assign { } { }
24085         assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form
24086       attribute \src "libresoc.v:0.0-0.0"
24087       case 5'01111
24088         assign { } { }
24089         assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form
24090       attribute \src "libresoc.v:0.0-0.0"
24091       case 5'10100
24092         assign { } { }
24093         assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form
24094       attribute \src "libresoc.v:0.0-0.0"
24095       case 5'10101
24096         assign { } { }
24097         assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form
24098       attribute \src "libresoc.v:0.0-0.0"
24099       case 5'10111
24100         assign { } { }
24101         assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form
24102       attribute \src "libresoc.v:0.0-0.0"
24103       case 5'10000
24104         assign { } { }
24105         assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form
24106       attribute \src "libresoc.v:0.0-0.0"
24107       case 5'10010
24108         assign { } { }
24109         assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form
24110       attribute \src "libresoc.v:0.0-0.0"
24111       case 5'01000
24112         assign { } { }
24113         assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form
24114       attribute \src "libresoc.v:0.0-0.0"
24115       case 5'11000
24116         assign { } { }
24117         assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form
24118       attribute \src "libresoc.v:0.0-0.0"
24119       case 5'00100
24120         assign { } { }
24121         assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form
24122       case
24123         assign $1\dec31_form[4:0] 5'00000
24124     end
24125     sync always
24126       update \dec31_form $0\dec31_form[4:0]
24127   end
24128   attribute \src "libresoc.v:16900.3-16960.6"
24129   process $proc$libresoc.v:16900$385
24130     assign { } { }
24131     assign { } { }
24132     assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0]
24133     attribute \src "libresoc.v:16901.5-16901.29"
24134     switch \initial
24135       attribute \src "libresoc.v:16901.9-16901.17"
24136       case 1'1
24137       case
24138     end
24139     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24140     switch \opc_in
24141       attribute \src "libresoc.v:0.0-0.0"
24142       case 5'01010
24143         assign { } { }
24144         assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode
24145       attribute \src "libresoc.v:0.0-0.0"
24146       case 5'11100
24147         assign { } { }
24148         assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode
24149       attribute \src "libresoc.v:0.0-0.0"
24150       case 5'00000
24151         assign { } { }
24152         assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode
24153       attribute \src "libresoc.v:0.0-0.0"
24154       case 5'11010
24155         assign { } { }
24156         assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode
24157       attribute \src "libresoc.v:0.0-0.0"
24158       case 5'10011
24159         assign { } { }
24160         assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode
24161       attribute \src "libresoc.v:0.0-0.0"
24162       case 5'10110
24163         assign { } { }
24164         assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode
24165       attribute \src "libresoc.v:0.0-0.0"
24166       case 5'01001
24167         assign { } { }
24168         assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode
24169       attribute \src "libresoc.v:0.0-0.0"
24170       case 5'01011
24171         assign { } { }
24172         assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode
24173       attribute \src "libresoc.v:0.0-0.0"
24174       case 5'11011
24175         assign { } { }
24176         assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode
24177       attribute \src "libresoc.v:0.0-0.0"
24178       case 5'01111
24179         assign { } { }
24180         assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode
24181       attribute \src "libresoc.v:0.0-0.0"
24182       case 5'10100
24183         assign { } { }
24184         assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode
24185       attribute \src "libresoc.v:0.0-0.0"
24186       case 5'10101
24187         assign { } { }
24188         assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode
24189       attribute \src "libresoc.v:0.0-0.0"
24190       case 5'10111
24191         assign { } { }
24192         assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode
24193       attribute \src "libresoc.v:0.0-0.0"
24194       case 5'10000
24195         assign { } { }
24196         assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode
24197       attribute \src "libresoc.v:0.0-0.0"
24198       case 5'10010
24199         assign { } { }
24200         assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode
24201       attribute \src "libresoc.v:0.0-0.0"
24202       case 5'01000
24203         assign { } { }
24204         assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode
24205       attribute \src "libresoc.v:0.0-0.0"
24206       case 5'11000
24207         assign { } { }
24208         assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode
24209       attribute \src "libresoc.v:0.0-0.0"
24210       case 5'00100
24211         assign { } { }
24212         assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode
24213       case
24214         assign $1\dec31_asmcode[7:0] 8'00000000
24215     end
24216     sync always
24217       update \dec31_asmcode $0\dec31_asmcode[7:0]
24218   end
24219   attribute \src "libresoc.v:16961.3-17021.6"
24220   process $proc$libresoc.v:16961$386
24221     assign { } { }
24222     assign { } { }
24223     assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0]
24224     attribute \src "libresoc.v:16962.5-16962.29"
24225     switch \initial
24226       attribute \src "libresoc.v:16962.9-16962.17"
24227       case 1'1
24228       case
24229     end
24230     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24231     switch \opc_in
24232       attribute \src "libresoc.v:0.0-0.0"
24233       case 5'01010
24234         assign { } { }
24235         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel
24236       attribute \src "libresoc.v:0.0-0.0"
24237       case 5'11100
24238         assign { } { }
24239         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel
24240       attribute \src "libresoc.v:0.0-0.0"
24241       case 5'00000
24242         assign { } { }
24243         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel
24244       attribute \src "libresoc.v:0.0-0.0"
24245       case 5'11010
24246         assign { } { }
24247         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel
24248       attribute \src "libresoc.v:0.0-0.0"
24249       case 5'10011
24250         assign { } { }
24251         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel
24252       attribute \src "libresoc.v:0.0-0.0"
24253       case 5'10110
24254         assign { } { }
24255         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel
24256       attribute \src "libresoc.v:0.0-0.0"
24257       case 5'01001
24258         assign { } { }
24259         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel
24260       attribute \src "libresoc.v:0.0-0.0"
24261       case 5'01011
24262         assign { } { }
24263         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel
24264       attribute \src "libresoc.v:0.0-0.0"
24265       case 5'11011
24266         assign { } { }
24267         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel
24268       attribute \src "libresoc.v:0.0-0.0"
24269       case 5'01111
24270         assign { } { }
24271         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel
24272       attribute \src "libresoc.v:0.0-0.0"
24273       case 5'10100
24274         assign { } { }
24275         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel
24276       attribute \src "libresoc.v:0.0-0.0"
24277       case 5'10101
24278         assign { } { }
24279         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel
24280       attribute \src "libresoc.v:0.0-0.0"
24281       case 5'10111
24282         assign { } { }
24283         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel
24284       attribute \src "libresoc.v:0.0-0.0"
24285       case 5'10000
24286         assign { } { }
24287         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel
24288       attribute \src "libresoc.v:0.0-0.0"
24289       case 5'10010
24290         assign { } { }
24291         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel
24292       attribute \src "libresoc.v:0.0-0.0"
24293       case 5'01000
24294         assign { } { }
24295         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel
24296       attribute \src "libresoc.v:0.0-0.0"
24297       case 5'11000
24298         assign { } { }
24299         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel
24300       attribute \src "libresoc.v:0.0-0.0"
24301       case 5'00100
24302         assign { } { }
24303         assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel
24304       case
24305         assign $1\dec31_in1_sel[2:0] 3'000
24306     end
24307     sync always
24308       update \dec31_in1_sel $0\dec31_in1_sel[2:0]
24309   end
24310   attribute \src "libresoc.v:17022.3-17082.6"
24311   process $proc$libresoc.v:17022$387
24312     assign { } { }
24313     assign { } { }
24314     assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0]
24315     attribute \src "libresoc.v:17023.5-17023.29"
24316     switch \initial
24317       attribute \src "libresoc.v:17023.9-17023.17"
24318       case 1'1
24319       case
24320     end
24321     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24322     switch \opc_in
24323       attribute \src "libresoc.v:0.0-0.0"
24324       case 5'01010
24325         assign { } { }
24326         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel
24327       attribute \src "libresoc.v:0.0-0.0"
24328       case 5'11100
24329         assign { } { }
24330         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel
24331       attribute \src "libresoc.v:0.0-0.0"
24332       case 5'00000
24333         assign { } { }
24334         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel
24335       attribute \src "libresoc.v:0.0-0.0"
24336       case 5'11010
24337         assign { } { }
24338         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel
24339       attribute \src "libresoc.v:0.0-0.0"
24340       case 5'10011
24341         assign { } { }
24342         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel
24343       attribute \src "libresoc.v:0.0-0.0"
24344       case 5'10110
24345         assign { } { }
24346         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel
24347       attribute \src "libresoc.v:0.0-0.0"
24348       case 5'01001
24349         assign { } { }
24350         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel
24351       attribute \src "libresoc.v:0.0-0.0"
24352       case 5'01011
24353         assign { } { }
24354         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel
24355       attribute \src "libresoc.v:0.0-0.0"
24356       case 5'11011
24357         assign { } { }
24358         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel
24359       attribute \src "libresoc.v:0.0-0.0"
24360       case 5'01111
24361         assign { } { }
24362         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel
24363       attribute \src "libresoc.v:0.0-0.0"
24364       case 5'10100
24365         assign { } { }
24366         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel
24367       attribute \src "libresoc.v:0.0-0.0"
24368       case 5'10101
24369         assign { } { }
24370         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel
24371       attribute \src "libresoc.v:0.0-0.0"
24372       case 5'10111
24373         assign { } { }
24374         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel
24375       attribute \src "libresoc.v:0.0-0.0"
24376       case 5'10000
24377         assign { } { }
24378         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel
24379       attribute \src "libresoc.v:0.0-0.0"
24380       case 5'10010
24381         assign { } { }
24382         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel
24383       attribute \src "libresoc.v:0.0-0.0"
24384       case 5'01000
24385         assign { } { }
24386         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel
24387       attribute \src "libresoc.v:0.0-0.0"
24388       case 5'11000
24389         assign { } { }
24390         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel
24391       attribute \src "libresoc.v:0.0-0.0"
24392       case 5'00100
24393         assign { } { }
24394         assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel
24395       case
24396         assign $1\dec31_in2_sel[3:0] 4'0000
24397     end
24398     sync always
24399       update \dec31_in2_sel $0\dec31_in2_sel[3:0]
24400   end
24401   attribute \src "libresoc.v:17083.3-17143.6"
24402   process $proc$libresoc.v:17083$388
24403     assign { } { }
24404     assign { } { }
24405     assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0]
24406     attribute \src "libresoc.v:17084.5-17084.29"
24407     switch \initial
24408       attribute \src "libresoc.v:17084.9-17084.17"
24409       case 1'1
24410       case
24411     end
24412     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24413     switch \opc_in
24414       attribute \src "libresoc.v:0.0-0.0"
24415       case 5'01010
24416         assign { } { }
24417         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel
24418       attribute \src "libresoc.v:0.0-0.0"
24419       case 5'11100
24420         assign { } { }
24421         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel
24422       attribute \src "libresoc.v:0.0-0.0"
24423       case 5'00000
24424         assign { } { }
24425         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel
24426       attribute \src "libresoc.v:0.0-0.0"
24427       case 5'11010
24428         assign { } { }
24429         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel
24430       attribute \src "libresoc.v:0.0-0.0"
24431       case 5'10011
24432         assign { } { }
24433         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel
24434       attribute \src "libresoc.v:0.0-0.0"
24435       case 5'10110
24436         assign { } { }
24437         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel
24438       attribute \src "libresoc.v:0.0-0.0"
24439       case 5'01001
24440         assign { } { }
24441         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel
24442       attribute \src "libresoc.v:0.0-0.0"
24443       case 5'01011
24444         assign { } { }
24445         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel
24446       attribute \src "libresoc.v:0.0-0.0"
24447       case 5'11011
24448         assign { } { }
24449         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel
24450       attribute \src "libresoc.v:0.0-0.0"
24451       case 5'01111
24452         assign { } { }
24453         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel
24454       attribute \src "libresoc.v:0.0-0.0"
24455       case 5'10100
24456         assign { } { }
24457         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel
24458       attribute \src "libresoc.v:0.0-0.0"
24459       case 5'10101
24460         assign { } { }
24461         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel
24462       attribute \src "libresoc.v:0.0-0.0"
24463       case 5'10111
24464         assign { } { }
24465         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel
24466       attribute \src "libresoc.v:0.0-0.0"
24467       case 5'10000
24468         assign { } { }
24469         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel
24470       attribute \src "libresoc.v:0.0-0.0"
24471       case 5'10010
24472         assign { } { }
24473         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel
24474       attribute \src "libresoc.v:0.0-0.0"
24475       case 5'01000
24476         assign { } { }
24477         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel
24478       attribute \src "libresoc.v:0.0-0.0"
24479       case 5'11000
24480         assign { } { }
24481         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel
24482       attribute \src "libresoc.v:0.0-0.0"
24483       case 5'00100
24484         assign { } { }
24485         assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel
24486       case
24487         assign $1\dec31_in3_sel[1:0] 2'00
24488     end
24489     sync always
24490       update \dec31_in3_sel $0\dec31_in3_sel[1:0]
24491   end
24492   attribute \src "libresoc.v:17144.3-17204.6"
24493   process $proc$libresoc.v:17144$389
24494     assign { } { }
24495     assign { } { }
24496     assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0]
24497     attribute \src "libresoc.v:17145.5-17145.29"
24498     switch \initial
24499       attribute \src "libresoc.v:17145.9-17145.17"
24500       case 1'1
24501       case
24502     end
24503     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24504     switch \opc_in
24505       attribute \src "libresoc.v:0.0-0.0"
24506       case 5'01010
24507         assign { } { }
24508         assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel
24509       attribute \src "libresoc.v:0.0-0.0"
24510       case 5'11100
24511         assign { } { }
24512         assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel
24513       attribute \src "libresoc.v:0.0-0.0"
24514       case 5'00000
24515         assign { } { }
24516         assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel
24517       attribute \src "libresoc.v:0.0-0.0"
24518       case 5'11010
24519         assign { } { }
24520         assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel
24521       attribute \src "libresoc.v:0.0-0.0"
24522       case 5'10011
24523         assign { } { }
24524         assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel
24525       attribute \src "libresoc.v:0.0-0.0"
24526       case 5'10110
24527         assign { } { }
24528         assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel
24529       attribute \src "libresoc.v:0.0-0.0"
24530       case 5'01001
24531         assign { } { }
24532         assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel
24533       attribute \src "libresoc.v:0.0-0.0"
24534       case 5'01011
24535         assign { } { }
24536         assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel
24537       attribute \src "libresoc.v:0.0-0.0"
24538       case 5'11011
24539         assign { } { }
24540         assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel
24541       attribute \src "libresoc.v:0.0-0.0"
24542       case 5'01111
24543         assign { } { }
24544         assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel
24545       attribute \src "libresoc.v:0.0-0.0"
24546       case 5'10100
24547         assign { } { }
24548         assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel
24549       attribute \src "libresoc.v:0.0-0.0"
24550       case 5'10101
24551         assign { } { }
24552         assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel
24553       attribute \src "libresoc.v:0.0-0.0"
24554       case 5'10111
24555         assign { } { }
24556         assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel
24557       attribute \src "libresoc.v:0.0-0.0"
24558       case 5'10000
24559         assign { } { }
24560         assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel
24561       attribute \src "libresoc.v:0.0-0.0"
24562       case 5'10010
24563         assign { } { }
24564         assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel
24565       attribute \src "libresoc.v:0.0-0.0"
24566       case 5'01000
24567         assign { } { }
24568         assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel
24569       attribute \src "libresoc.v:0.0-0.0"
24570       case 5'11000
24571         assign { } { }
24572         assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel
24573       attribute \src "libresoc.v:0.0-0.0"
24574       case 5'00100
24575         assign { } { }
24576         assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel
24577       case
24578         assign $1\dec31_out_sel[1:0] 2'00
24579     end
24580     sync always
24581       update \dec31_out_sel $0\dec31_out_sel[1:0]
24582   end
24583   attribute \src "libresoc.v:17205.3-17265.6"
24584   process $proc$libresoc.v:17205$390
24585     assign { } { }
24586     assign { } { }
24587     assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0]
24588     attribute \src "libresoc.v:17206.5-17206.29"
24589     switch \initial
24590       attribute \src "libresoc.v:17206.9-17206.17"
24591       case 1'1
24592       case
24593     end
24594     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24595     switch \opc_in
24596       attribute \src "libresoc.v:0.0-0.0"
24597       case 5'01010
24598         assign { } { }
24599         assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in
24600       attribute \src "libresoc.v:0.0-0.0"
24601       case 5'11100
24602         assign { } { }
24603         assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in
24604       attribute \src "libresoc.v:0.0-0.0"
24605       case 5'00000
24606         assign { } { }
24607         assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in
24608       attribute \src "libresoc.v:0.0-0.0"
24609       case 5'11010
24610         assign { } { }
24611         assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in
24612       attribute \src "libresoc.v:0.0-0.0"
24613       case 5'10011
24614         assign { } { }
24615         assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in
24616       attribute \src "libresoc.v:0.0-0.0"
24617       case 5'10110
24618         assign { } { }
24619         assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in
24620       attribute \src "libresoc.v:0.0-0.0"
24621       case 5'01001
24622         assign { } { }
24623         assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in
24624       attribute \src "libresoc.v:0.0-0.0"
24625       case 5'01011
24626         assign { } { }
24627         assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in
24628       attribute \src "libresoc.v:0.0-0.0"
24629       case 5'11011
24630         assign { } { }
24631         assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in
24632       attribute \src "libresoc.v:0.0-0.0"
24633       case 5'01111
24634         assign { } { }
24635         assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in
24636       attribute \src "libresoc.v:0.0-0.0"
24637       case 5'10100
24638         assign { } { }
24639         assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in
24640       attribute \src "libresoc.v:0.0-0.0"
24641       case 5'10101
24642         assign { } { }
24643         assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in
24644       attribute \src "libresoc.v:0.0-0.0"
24645       case 5'10111
24646         assign { } { }
24647         assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in
24648       attribute \src "libresoc.v:0.0-0.0"
24649       case 5'10000
24650         assign { } { }
24651         assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in
24652       attribute \src "libresoc.v:0.0-0.0"
24653       case 5'10010
24654         assign { } { }
24655         assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in
24656       attribute \src "libresoc.v:0.0-0.0"
24657       case 5'01000
24658         assign { } { }
24659         assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in
24660       attribute \src "libresoc.v:0.0-0.0"
24661       case 5'11000
24662         assign { } { }
24663         assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in
24664       attribute \src "libresoc.v:0.0-0.0"
24665       case 5'00100
24666         assign { } { }
24667         assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in
24668       case
24669         assign $1\dec31_cr_in[2:0] 3'000
24670     end
24671     sync always
24672       update \dec31_cr_in $0\dec31_cr_in[2:0]
24673   end
24674   attribute \src "libresoc.v:17266.3-17326.6"
24675   process $proc$libresoc.v:17266$391
24676     assign { } { }
24677     assign { } { }
24678     assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0]
24679     attribute \src "libresoc.v:17267.5-17267.29"
24680     switch \initial
24681       attribute \src "libresoc.v:17267.9-17267.17"
24682       case 1'1
24683       case
24684     end
24685     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24686     switch \opc_in
24687       attribute \src "libresoc.v:0.0-0.0"
24688       case 5'01010
24689         assign { } { }
24690         assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out
24691       attribute \src "libresoc.v:0.0-0.0"
24692       case 5'11100
24693         assign { } { }
24694         assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out
24695       attribute \src "libresoc.v:0.0-0.0"
24696       case 5'00000
24697         assign { } { }
24698         assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out
24699       attribute \src "libresoc.v:0.0-0.0"
24700       case 5'11010
24701         assign { } { }
24702         assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out
24703       attribute \src "libresoc.v:0.0-0.0"
24704       case 5'10011
24705         assign { } { }
24706         assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out
24707       attribute \src "libresoc.v:0.0-0.0"
24708       case 5'10110
24709         assign { } { }
24710         assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out
24711       attribute \src "libresoc.v:0.0-0.0"
24712       case 5'01001
24713         assign { } { }
24714         assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out
24715       attribute \src "libresoc.v:0.0-0.0"
24716       case 5'01011
24717         assign { } { }
24718         assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out
24719       attribute \src "libresoc.v:0.0-0.0"
24720       case 5'11011
24721         assign { } { }
24722         assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out
24723       attribute \src "libresoc.v:0.0-0.0"
24724       case 5'01111
24725         assign { } { }
24726         assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out
24727       attribute \src "libresoc.v:0.0-0.0"
24728       case 5'10100
24729         assign { } { }
24730         assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out
24731       attribute \src "libresoc.v:0.0-0.0"
24732       case 5'10101
24733         assign { } { }
24734         assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out
24735       attribute \src "libresoc.v:0.0-0.0"
24736       case 5'10111
24737         assign { } { }
24738         assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out
24739       attribute \src "libresoc.v:0.0-0.0"
24740       case 5'10000
24741         assign { } { }
24742         assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out
24743       attribute \src "libresoc.v:0.0-0.0"
24744       case 5'10010
24745         assign { } { }
24746         assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out
24747       attribute \src "libresoc.v:0.0-0.0"
24748       case 5'01000
24749         assign { } { }
24750         assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out
24751       attribute \src "libresoc.v:0.0-0.0"
24752       case 5'11000
24753         assign { } { }
24754         assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out
24755       attribute \src "libresoc.v:0.0-0.0"
24756       case 5'00100
24757         assign { } { }
24758         assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out
24759       case
24760         assign $1\dec31_cr_out[2:0] 3'000
24761     end
24762     sync always
24763       update \dec31_cr_out $0\dec31_cr_out[2:0]
24764   end
24765   attribute \src "libresoc.v:17327.3-17387.6"
24766   process $proc$libresoc.v:17327$392
24767     assign { } { }
24768     assign { } { }
24769     assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0]
24770     attribute \src "libresoc.v:17328.5-17328.29"
24771     switch \initial
24772       attribute \src "libresoc.v:17328.9-17328.17"
24773       case 1'1
24774       case
24775     end
24776     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24777     switch \opc_in
24778       attribute \src "libresoc.v:0.0-0.0"
24779       case 5'01010
24780         assign { } { }
24781         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len
24782       attribute \src "libresoc.v:0.0-0.0"
24783       case 5'11100
24784         assign { } { }
24785         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len
24786       attribute \src "libresoc.v:0.0-0.0"
24787       case 5'00000
24788         assign { } { }
24789         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len
24790       attribute \src "libresoc.v:0.0-0.0"
24791       case 5'11010
24792         assign { } { }
24793         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len
24794       attribute \src "libresoc.v:0.0-0.0"
24795       case 5'10011
24796         assign { } { }
24797         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len
24798       attribute \src "libresoc.v:0.0-0.0"
24799       case 5'10110
24800         assign { } { }
24801         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len
24802       attribute \src "libresoc.v:0.0-0.0"
24803       case 5'01001
24804         assign { } { }
24805         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len
24806       attribute \src "libresoc.v:0.0-0.0"
24807       case 5'01011
24808         assign { } { }
24809         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len
24810       attribute \src "libresoc.v:0.0-0.0"
24811       case 5'11011
24812         assign { } { }
24813         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len
24814       attribute \src "libresoc.v:0.0-0.0"
24815       case 5'01111
24816         assign { } { }
24817         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len
24818       attribute \src "libresoc.v:0.0-0.0"
24819       case 5'10100
24820         assign { } { }
24821         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len
24822       attribute \src "libresoc.v:0.0-0.0"
24823       case 5'10101
24824         assign { } { }
24825         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len
24826       attribute \src "libresoc.v:0.0-0.0"
24827       case 5'10111
24828         assign { } { }
24829         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len
24830       attribute \src "libresoc.v:0.0-0.0"
24831       case 5'10000
24832         assign { } { }
24833         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len
24834       attribute \src "libresoc.v:0.0-0.0"
24835       case 5'10010
24836         assign { } { }
24837         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len
24838       attribute \src "libresoc.v:0.0-0.0"
24839       case 5'01000
24840         assign { } { }
24841         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len
24842       attribute \src "libresoc.v:0.0-0.0"
24843       case 5'11000
24844         assign { } { }
24845         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len
24846       attribute \src "libresoc.v:0.0-0.0"
24847       case 5'00100
24848         assign { } { }
24849         assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len
24850       case
24851         assign $1\dec31_ldst_len[3:0] 4'0000
24852     end
24853     sync always
24854       update \dec31_ldst_len $0\dec31_ldst_len[3:0]
24855   end
24856   attribute \src "libresoc.v:17388.3-17448.6"
24857   process $proc$libresoc.v:17388$393
24858     assign { } { }
24859     assign { } { }
24860     assign $0\dec31_upd[1:0] $1\dec31_upd[1:0]
24861     attribute \src "libresoc.v:17389.5-17389.29"
24862     switch \initial
24863       attribute \src "libresoc.v:17389.9-17389.17"
24864       case 1'1
24865       case
24866     end
24867     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24868     switch \opc_in
24869       attribute \src "libresoc.v:0.0-0.0"
24870       case 5'01010
24871         assign { } { }
24872         assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd
24873       attribute \src "libresoc.v:0.0-0.0"
24874       case 5'11100
24875         assign { } { }
24876         assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd
24877       attribute \src "libresoc.v:0.0-0.0"
24878       case 5'00000
24879         assign { } { }
24880         assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd
24881       attribute \src "libresoc.v:0.0-0.0"
24882       case 5'11010
24883         assign { } { }
24884         assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd
24885       attribute \src "libresoc.v:0.0-0.0"
24886       case 5'10011
24887         assign { } { }
24888         assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd
24889       attribute \src "libresoc.v:0.0-0.0"
24890       case 5'10110
24891         assign { } { }
24892         assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd
24893       attribute \src "libresoc.v:0.0-0.0"
24894       case 5'01001
24895         assign { } { }
24896         assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd
24897       attribute \src "libresoc.v:0.0-0.0"
24898       case 5'01011
24899         assign { } { }
24900         assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd
24901       attribute \src "libresoc.v:0.0-0.0"
24902       case 5'11011
24903         assign { } { }
24904         assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd
24905       attribute \src "libresoc.v:0.0-0.0"
24906       case 5'01111
24907         assign { } { }
24908         assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd
24909       attribute \src "libresoc.v:0.0-0.0"
24910       case 5'10100
24911         assign { } { }
24912         assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd
24913       attribute \src "libresoc.v:0.0-0.0"
24914       case 5'10101
24915         assign { } { }
24916         assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd
24917       attribute \src "libresoc.v:0.0-0.0"
24918       case 5'10111
24919         assign { } { }
24920         assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd
24921       attribute \src "libresoc.v:0.0-0.0"
24922       case 5'10000
24923         assign { } { }
24924         assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd
24925       attribute \src "libresoc.v:0.0-0.0"
24926       case 5'10010
24927         assign { } { }
24928         assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd
24929       attribute \src "libresoc.v:0.0-0.0"
24930       case 5'01000
24931         assign { } { }
24932         assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd
24933       attribute \src "libresoc.v:0.0-0.0"
24934       case 5'11000
24935         assign { } { }
24936         assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd
24937       attribute \src "libresoc.v:0.0-0.0"
24938       case 5'00100
24939         assign { } { }
24940         assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd
24941       case
24942         assign $1\dec31_upd[1:0] 2'00
24943     end
24944     sync always
24945       update \dec31_upd $0\dec31_upd[1:0]
24946   end
24947   attribute \src "libresoc.v:17449.3-17509.6"
24948   process $proc$libresoc.v:17449$394
24949     assign { } { }
24950     assign { } { }
24951     assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0]
24952     attribute \src "libresoc.v:17450.5-17450.29"
24953     switch \initial
24954       attribute \src "libresoc.v:17450.9-17450.17"
24955       case 1'1
24956       case
24957     end
24958     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
24959     switch \opc_in
24960       attribute \src "libresoc.v:0.0-0.0"
24961       case 5'01010
24962         assign { } { }
24963         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel
24964       attribute \src "libresoc.v:0.0-0.0"
24965       case 5'11100
24966         assign { } { }
24967         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel
24968       attribute \src "libresoc.v:0.0-0.0"
24969       case 5'00000
24970         assign { } { }
24971         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel
24972       attribute \src "libresoc.v:0.0-0.0"
24973       case 5'11010
24974         assign { } { }
24975         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel
24976       attribute \src "libresoc.v:0.0-0.0"
24977       case 5'10011
24978         assign { } { }
24979         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel
24980       attribute \src "libresoc.v:0.0-0.0"
24981       case 5'10110
24982         assign { } { }
24983         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel
24984       attribute \src "libresoc.v:0.0-0.0"
24985       case 5'01001
24986         assign { } { }
24987         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel
24988       attribute \src "libresoc.v:0.0-0.0"
24989       case 5'01011
24990         assign { } { }
24991         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel
24992       attribute \src "libresoc.v:0.0-0.0"
24993       case 5'11011
24994         assign { } { }
24995         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel
24996       attribute \src "libresoc.v:0.0-0.0"
24997       case 5'01111
24998         assign { } { }
24999         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel
25000       attribute \src "libresoc.v:0.0-0.0"
25001       case 5'10100
25002         assign { } { }
25003         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel
25004       attribute \src "libresoc.v:0.0-0.0"
25005       case 5'10101
25006         assign { } { }
25007         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel
25008       attribute \src "libresoc.v:0.0-0.0"
25009       case 5'10111
25010         assign { } { }
25011         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel
25012       attribute \src "libresoc.v:0.0-0.0"
25013       case 5'10000
25014         assign { } { }
25015         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel
25016       attribute \src "libresoc.v:0.0-0.0"
25017       case 5'10010
25018         assign { } { }
25019         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel
25020       attribute \src "libresoc.v:0.0-0.0"
25021       case 5'01000
25022         assign { } { }
25023         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel
25024       attribute \src "libresoc.v:0.0-0.0"
25025       case 5'11000
25026         assign { } { }
25027         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel
25028       attribute \src "libresoc.v:0.0-0.0"
25029       case 5'00100
25030         assign { } { }
25031         assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel
25032       case
25033         assign $1\dec31_rc_sel[1:0] 2'00
25034     end
25035     sync always
25036       update \dec31_rc_sel $0\dec31_rc_sel[1:0]
25037   end
25038   attribute \src "libresoc.v:17510.3-17570.6"
25039   process $proc$libresoc.v:17510$395
25040     assign { } { }
25041     assign { } { }
25042     assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0]
25043     attribute \src "libresoc.v:17511.5-17511.29"
25044     switch \initial
25045       attribute \src "libresoc.v:17511.9-17511.17"
25046       case 1'1
25047       case
25048     end
25049     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25050     switch \opc_in
25051       attribute \src "libresoc.v:0.0-0.0"
25052       case 5'01010
25053         assign { } { }
25054         assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in
25055       attribute \src "libresoc.v:0.0-0.0"
25056       case 5'11100
25057         assign { } { }
25058         assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in
25059       attribute \src "libresoc.v:0.0-0.0"
25060       case 5'00000
25061         assign { } { }
25062         assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in
25063       attribute \src "libresoc.v:0.0-0.0"
25064       case 5'11010
25065         assign { } { }
25066         assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in
25067       attribute \src "libresoc.v:0.0-0.0"
25068       case 5'10011
25069         assign { } { }
25070         assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in
25071       attribute \src "libresoc.v:0.0-0.0"
25072       case 5'10110
25073         assign { } { }
25074         assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in
25075       attribute \src "libresoc.v:0.0-0.0"
25076       case 5'01001
25077         assign { } { }
25078         assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in
25079       attribute \src "libresoc.v:0.0-0.0"
25080       case 5'01011
25081         assign { } { }
25082         assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in
25083       attribute \src "libresoc.v:0.0-0.0"
25084       case 5'11011
25085         assign { } { }
25086         assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in
25087       attribute \src "libresoc.v:0.0-0.0"
25088       case 5'01111
25089         assign { } { }
25090         assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in
25091       attribute \src "libresoc.v:0.0-0.0"
25092       case 5'10100
25093         assign { } { }
25094         assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in
25095       attribute \src "libresoc.v:0.0-0.0"
25096       case 5'10101
25097         assign { } { }
25098         assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in
25099       attribute \src "libresoc.v:0.0-0.0"
25100       case 5'10111
25101         assign { } { }
25102         assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in
25103       attribute \src "libresoc.v:0.0-0.0"
25104       case 5'10000
25105         assign { } { }
25106         assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in
25107       attribute \src "libresoc.v:0.0-0.0"
25108       case 5'10010
25109         assign { } { }
25110         assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in
25111       attribute \src "libresoc.v:0.0-0.0"
25112       case 5'01000
25113         assign { } { }
25114         assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in
25115       attribute \src "libresoc.v:0.0-0.0"
25116       case 5'11000
25117         assign { } { }
25118         assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in
25119       attribute \src "libresoc.v:0.0-0.0"
25120       case 5'00100
25121         assign { } { }
25122         assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in
25123       case
25124         assign $1\dec31_cry_in[1:0] 2'00
25125     end
25126     sync always
25127       update \dec31_cry_in $0\dec31_cry_in[1:0]
25128   end
25129   attribute \src "libresoc.v:17571.3-17631.6"
25130   process $proc$libresoc.v:17571$396
25131     assign { } { }
25132     assign { } { }
25133     assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0]
25134     attribute \src "libresoc.v:17572.5-17572.29"
25135     switch \initial
25136       attribute \src "libresoc.v:17572.9-17572.17"
25137       case 1'1
25138       case
25139     end
25140     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25141     switch \opc_in
25142       attribute \src "libresoc.v:0.0-0.0"
25143       case 5'01010
25144         assign { } { }
25145         assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a
25146       attribute \src "libresoc.v:0.0-0.0"
25147       case 5'11100
25148         assign { } { }
25149         assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a
25150       attribute \src "libresoc.v:0.0-0.0"
25151       case 5'00000
25152         assign { } { }
25153         assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a
25154       attribute \src "libresoc.v:0.0-0.0"
25155       case 5'11010
25156         assign { } { }
25157         assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a
25158       attribute \src "libresoc.v:0.0-0.0"
25159       case 5'10011
25160         assign { } { }
25161         assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a
25162       attribute \src "libresoc.v:0.0-0.0"
25163       case 5'10110
25164         assign { } { }
25165         assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a
25166       attribute \src "libresoc.v:0.0-0.0"
25167       case 5'01001
25168         assign { } { }
25169         assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a
25170       attribute \src "libresoc.v:0.0-0.0"
25171       case 5'01011
25172         assign { } { }
25173         assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a
25174       attribute \src "libresoc.v:0.0-0.0"
25175       case 5'11011
25176         assign { } { }
25177         assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a
25178       attribute \src "libresoc.v:0.0-0.0"
25179       case 5'01111
25180         assign { } { }
25181         assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a
25182       attribute \src "libresoc.v:0.0-0.0"
25183       case 5'10100
25184         assign { } { }
25185         assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a
25186       attribute \src "libresoc.v:0.0-0.0"
25187       case 5'10101
25188         assign { } { }
25189         assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a
25190       attribute \src "libresoc.v:0.0-0.0"
25191       case 5'10111
25192         assign { } { }
25193         assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a
25194       attribute \src "libresoc.v:0.0-0.0"
25195       case 5'10000
25196         assign { } { }
25197         assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a
25198       attribute \src "libresoc.v:0.0-0.0"
25199       case 5'10010
25200         assign { } { }
25201         assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a
25202       attribute \src "libresoc.v:0.0-0.0"
25203       case 5'01000
25204         assign { } { }
25205         assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a
25206       attribute \src "libresoc.v:0.0-0.0"
25207       case 5'11000
25208         assign { } { }
25209         assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a
25210       attribute \src "libresoc.v:0.0-0.0"
25211       case 5'00100
25212         assign { } { }
25213         assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a
25214       case
25215         assign $1\dec31_inv_a[0:0] 1'0
25216     end
25217     sync always
25218       update \dec31_inv_a $0\dec31_inv_a[0:0]
25219   end
25220   attribute \src "libresoc.v:17632.3-17692.6"
25221   process $proc$libresoc.v:17632$397
25222     assign { } { }
25223     assign { } { }
25224     assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0]
25225     attribute \src "libresoc.v:17633.5-17633.29"
25226     switch \initial
25227       attribute \src "libresoc.v:17633.9-17633.17"
25228       case 1'1
25229       case
25230     end
25231     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25232     switch \opc_in
25233       attribute \src "libresoc.v:0.0-0.0"
25234       case 5'01010
25235         assign { } { }
25236         assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out
25237       attribute \src "libresoc.v:0.0-0.0"
25238       case 5'11100
25239         assign { } { }
25240         assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out
25241       attribute \src "libresoc.v:0.0-0.0"
25242       case 5'00000
25243         assign { } { }
25244         assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out
25245       attribute \src "libresoc.v:0.0-0.0"
25246       case 5'11010
25247         assign { } { }
25248         assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out
25249       attribute \src "libresoc.v:0.0-0.0"
25250       case 5'10011
25251         assign { } { }
25252         assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out
25253       attribute \src "libresoc.v:0.0-0.0"
25254       case 5'10110
25255         assign { } { }
25256         assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out
25257       attribute \src "libresoc.v:0.0-0.0"
25258       case 5'01001
25259         assign { } { }
25260         assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out
25261       attribute \src "libresoc.v:0.0-0.0"
25262       case 5'01011
25263         assign { } { }
25264         assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out
25265       attribute \src "libresoc.v:0.0-0.0"
25266       case 5'11011
25267         assign { } { }
25268         assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out
25269       attribute \src "libresoc.v:0.0-0.0"
25270       case 5'01111
25271         assign { } { }
25272         assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out
25273       attribute \src "libresoc.v:0.0-0.0"
25274       case 5'10100
25275         assign { } { }
25276         assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out
25277       attribute \src "libresoc.v:0.0-0.0"
25278       case 5'10101
25279         assign { } { }
25280         assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out
25281       attribute \src "libresoc.v:0.0-0.0"
25282       case 5'10111
25283         assign { } { }
25284         assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out
25285       attribute \src "libresoc.v:0.0-0.0"
25286       case 5'10000
25287         assign { } { }
25288         assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out
25289       attribute \src "libresoc.v:0.0-0.0"
25290       case 5'10010
25291         assign { } { }
25292         assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out
25293       attribute \src "libresoc.v:0.0-0.0"
25294       case 5'01000
25295         assign { } { }
25296         assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out
25297       attribute \src "libresoc.v:0.0-0.0"
25298       case 5'11000
25299         assign { } { }
25300         assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out
25301       attribute \src "libresoc.v:0.0-0.0"
25302       case 5'00100
25303         assign { } { }
25304         assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out
25305       case
25306         assign $1\dec31_inv_out[0:0] 1'0
25307     end
25308     sync always
25309       update \dec31_inv_out $0\dec31_inv_out[0:0]
25310   end
25311   attribute \src "libresoc.v:17693.3-17753.6"
25312   process $proc$libresoc.v:17693$398
25313     assign { } { }
25314     assign { } { }
25315     assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0]
25316     attribute \src "libresoc.v:17694.5-17694.29"
25317     switch \initial
25318       attribute \src "libresoc.v:17694.9-17694.17"
25319       case 1'1
25320       case
25321     end
25322     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25323     switch \opc_in
25324       attribute \src "libresoc.v:0.0-0.0"
25325       case 5'01010
25326         assign { } { }
25327         assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out
25328       attribute \src "libresoc.v:0.0-0.0"
25329       case 5'11100
25330         assign { } { }
25331         assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out
25332       attribute \src "libresoc.v:0.0-0.0"
25333       case 5'00000
25334         assign { } { }
25335         assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out
25336       attribute \src "libresoc.v:0.0-0.0"
25337       case 5'11010
25338         assign { } { }
25339         assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out
25340       attribute \src "libresoc.v:0.0-0.0"
25341       case 5'10011
25342         assign { } { }
25343         assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out
25344       attribute \src "libresoc.v:0.0-0.0"
25345       case 5'10110
25346         assign { } { }
25347         assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out
25348       attribute \src "libresoc.v:0.0-0.0"
25349       case 5'01001
25350         assign { } { }
25351         assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out
25352       attribute \src "libresoc.v:0.0-0.0"
25353       case 5'01011
25354         assign { } { }
25355         assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out
25356       attribute \src "libresoc.v:0.0-0.0"
25357       case 5'11011
25358         assign { } { }
25359         assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out
25360       attribute \src "libresoc.v:0.0-0.0"
25361       case 5'01111
25362         assign { } { }
25363         assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out
25364       attribute \src "libresoc.v:0.0-0.0"
25365       case 5'10100
25366         assign { } { }
25367         assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out
25368       attribute \src "libresoc.v:0.0-0.0"
25369       case 5'10101
25370         assign { } { }
25371         assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out
25372       attribute \src "libresoc.v:0.0-0.0"
25373       case 5'10111
25374         assign { } { }
25375         assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out
25376       attribute \src "libresoc.v:0.0-0.0"
25377       case 5'10000
25378         assign { } { }
25379         assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out
25380       attribute \src "libresoc.v:0.0-0.0"
25381       case 5'10010
25382         assign { } { }
25383         assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out
25384       attribute \src "libresoc.v:0.0-0.0"
25385       case 5'01000
25386         assign { } { }
25387         assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out
25388       attribute \src "libresoc.v:0.0-0.0"
25389       case 5'11000
25390         assign { } { }
25391         assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out
25392       attribute \src "libresoc.v:0.0-0.0"
25393       case 5'00100
25394         assign { } { }
25395         assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out
25396       case
25397         assign $1\dec31_cry_out[0:0] 1'0
25398     end
25399     sync always
25400       update \dec31_cry_out $0\dec31_cry_out[0:0]
25401   end
25402   attribute \src "libresoc.v:17754.3-17814.6"
25403   process $proc$libresoc.v:17754$399
25404     assign { } { }
25405     assign { } { }
25406     assign $0\dec31_br[0:0] $1\dec31_br[0:0]
25407     attribute \src "libresoc.v:17755.5-17755.29"
25408     switch \initial
25409       attribute \src "libresoc.v:17755.9-17755.17"
25410       case 1'1
25411       case
25412     end
25413     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25414     switch \opc_in
25415       attribute \src "libresoc.v:0.0-0.0"
25416       case 5'01010
25417         assign { } { }
25418         assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br
25419       attribute \src "libresoc.v:0.0-0.0"
25420       case 5'11100
25421         assign { } { }
25422         assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br
25423       attribute \src "libresoc.v:0.0-0.0"
25424       case 5'00000
25425         assign { } { }
25426         assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br
25427       attribute \src "libresoc.v:0.0-0.0"
25428       case 5'11010
25429         assign { } { }
25430         assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br
25431       attribute \src "libresoc.v:0.0-0.0"
25432       case 5'10011
25433         assign { } { }
25434         assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br
25435       attribute \src "libresoc.v:0.0-0.0"
25436       case 5'10110
25437         assign { } { }
25438         assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br
25439       attribute \src "libresoc.v:0.0-0.0"
25440       case 5'01001
25441         assign { } { }
25442         assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br
25443       attribute \src "libresoc.v:0.0-0.0"
25444       case 5'01011
25445         assign { } { }
25446         assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br
25447       attribute \src "libresoc.v:0.0-0.0"
25448       case 5'11011
25449         assign { } { }
25450         assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br
25451       attribute \src "libresoc.v:0.0-0.0"
25452       case 5'01111
25453         assign { } { }
25454         assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br
25455       attribute \src "libresoc.v:0.0-0.0"
25456       case 5'10100
25457         assign { } { }
25458         assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br
25459       attribute \src "libresoc.v:0.0-0.0"
25460       case 5'10101
25461         assign { } { }
25462         assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br
25463       attribute \src "libresoc.v:0.0-0.0"
25464       case 5'10111
25465         assign { } { }
25466         assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br
25467       attribute \src "libresoc.v:0.0-0.0"
25468       case 5'10000
25469         assign { } { }
25470         assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br
25471       attribute \src "libresoc.v:0.0-0.0"
25472       case 5'10010
25473         assign { } { }
25474         assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br
25475       attribute \src "libresoc.v:0.0-0.0"
25476       case 5'01000
25477         assign { } { }
25478         assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br
25479       attribute \src "libresoc.v:0.0-0.0"
25480       case 5'11000
25481         assign { } { }
25482         assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br
25483       attribute \src "libresoc.v:0.0-0.0"
25484       case 5'00100
25485         assign { } { }
25486         assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br
25487       case
25488         assign $1\dec31_br[0:0] 1'0
25489     end
25490     sync always
25491       update \dec31_br $0\dec31_br[0:0]
25492   end
25493   attribute \src "libresoc.v:17815.3-17875.6"
25494   process $proc$libresoc.v:17815$400
25495     assign { } { }
25496     assign { } { }
25497     assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0]
25498     attribute \src "libresoc.v:17816.5-17816.29"
25499     switch \initial
25500       attribute \src "libresoc.v:17816.9-17816.17"
25501       case 1'1
25502       case
25503     end
25504     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25505     switch \opc_in
25506       attribute \src "libresoc.v:0.0-0.0"
25507       case 5'01010
25508         assign { } { }
25509         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext
25510       attribute \src "libresoc.v:0.0-0.0"
25511       case 5'11100
25512         assign { } { }
25513         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext
25514       attribute \src "libresoc.v:0.0-0.0"
25515       case 5'00000
25516         assign { } { }
25517         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext
25518       attribute \src "libresoc.v:0.0-0.0"
25519       case 5'11010
25520         assign { } { }
25521         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext
25522       attribute \src "libresoc.v:0.0-0.0"
25523       case 5'10011
25524         assign { } { }
25525         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext
25526       attribute \src "libresoc.v:0.0-0.0"
25527       case 5'10110
25528         assign { } { }
25529         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext
25530       attribute \src "libresoc.v:0.0-0.0"
25531       case 5'01001
25532         assign { } { }
25533         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext
25534       attribute \src "libresoc.v:0.0-0.0"
25535       case 5'01011
25536         assign { } { }
25537         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext
25538       attribute \src "libresoc.v:0.0-0.0"
25539       case 5'11011
25540         assign { } { }
25541         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext
25542       attribute \src "libresoc.v:0.0-0.0"
25543       case 5'01111
25544         assign { } { }
25545         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext
25546       attribute \src "libresoc.v:0.0-0.0"
25547       case 5'10100
25548         assign { } { }
25549         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext
25550       attribute \src "libresoc.v:0.0-0.0"
25551       case 5'10101
25552         assign { } { }
25553         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext
25554       attribute \src "libresoc.v:0.0-0.0"
25555       case 5'10111
25556         assign { } { }
25557         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext
25558       attribute \src "libresoc.v:0.0-0.0"
25559       case 5'10000
25560         assign { } { }
25561         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext
25562       attribute \src "libresoc.v:0.0-0.0"
25563       case 5'10010
25564         assign { } { }
25565         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext
25566       attribute \src "libresoc.v:0.0-0.0"
25567       case 5'01000
25568         assign { } { }
25569         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext
25570       attribute \src "libresoc.v:0.0-0.0"
25571       case 5'11000
25572         assign { } { }
25573         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext
25574       attribute \src "libresoc.v:0.0-0.0"
25575       case 5'00100
25576         assign { } { }
25577         assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext
25578       case
25579         assign $1\dec31_sgn_ext[0:0] 1'0
25580     end
25581     sync always
25582       update \dec31_sgn_ext $0\dec31_sgn_ext[0:0]
25583   end
25584   attribute \src "libresoc.v:17876.3-17936.6"
25585   process $proc$libresoc.v:17876$401
25586     assign { } { }
25587     assign { } { }
25588     assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0]
25589     attribute \src "libresoc.v:17877.5-17877.29"
25590     switch \initial
25591       attribute \src "libresoc.v:17877.9-17877.17"
25592       case 1'1
25593       case
25594     end
25595     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25596     switch \opc_in
25597       attribute \src "libresoc.v:0.0-0.0"
25598       case 5'01010
25599         assign { } { }
25600         assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv
25601       attribute \src "libresoc.v:0.0-0.0"
25602       case 5'11100
25603         assign { } { }
25604         assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv
25605       attribute \src "libresoc.v:0.0-0.0"
25606       case 5'00000
25607         assign { } { }
25608         assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv
25609       attribute \src "libresoc.v:0.0-0.0"
25610       case 5'11010
25611         assign { } { }
25612         assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv
25613       attribute \src "libresoc.v:0.0-0.0"
25614       case 5'10011
25615         assign { } { }
25616         assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv
25617       attribute \src "libresoc.v:0.0-0.0"
25618       case 5'10110
25619         assign { } { }
25620         assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv
25621       attribute \src "libresoc.v:0.0-0.0"
25622       case 5'01001
25623         assign { } { }
25624         assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv
25625       attribute \src "libresoc.v:0.0-0.0"
25626       case 5'01011
25627         assign { } { }
25628         assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv
25629       attribute \src "libresoc.v:0.0-0.0"
25630       case 5'11011
25631         assign { } { }
25632         assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv
25633       attribute \src "libresoc.v:0.0-0.0"
25634       case 5'01111
25635         assign { } { }
25636         assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv
25637       attribute \src "libresoc.v:0.0-0.0"
25638       case 5'10100
25639         assign { } { }
25640         assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv
25641       attribute \src "libresoc.v:0.0-0.0"
25642       case 5'10101
25643         assign { } { }
25644         assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv
25645       attribute \src "libresoc.v:0.0-0.0"
25646       case 5'10111
25647         assign { } { }
25648         assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv
25649       attribute \src "libresoc.v:0.0-0.0"
25650       case 5'10000
25651         assign { } { }
25652         assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv
25653       attribute \src "libresoc.v:0.0-0.0"
25654       case 5'10010
25655         assign { } { }
25656         assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv
25657       attribute \src "libresoc.v:0.0-0.0"
25658       case 5'01000
25659         assign { } { }
25660         assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv
25661       attribute \src "libresoc.v:0.0-0.0"
25662       case 5'11000
25663         assign { } { }
25664         assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv
25665       attribute \src "libresoc.v:0.0-0.0"
25666       case 5'00100
25667         assign { } { }
25668         assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv
25669       case
25670         assign $1\dec31_rsrv[0:0] 1'0
25671     end
25672     sync always
25673       update \dec31_rsrv $0\dec31_rsrv[0:0]
25674   end
25675   attribute \src "libresoc.v:17937.3-17997.6"
25676   process $proc$libresoc.v:17937$402
25677     assign { } { }
25678     assign { } { }
25679     assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0]
25680     attribute \src "libresoc.v:17938.5-17938.29"
25681     switch \initial
25682       attribute \src "libresoc.v:17938.9-17938.17"
25683       case 1'1
25684       case
25685     end
25686     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25687     switch \opc_in
25688       attribute \src "libresoc.v:0.0-0.0"
25689       case 5'01010
25690         assign { } { }
25691         assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b
25692       attribute \src "libresoc.v:0.0-0.0"
25693       case 5'11100
25694         assign { } { }
25695         assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b
25696       attribute \src "libresoc.v:0.0-0.0"
25697       case 5'00000
25698         assign { } { }
25699         assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b
25700       attribute \src "libresoc.v:0.0-0.0"
25701       case 5'11010
25702         assign { } { }
25703         assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b
25704       attribute \src "libresoc.v:0.0-0.0"
25705       case 5'10011
25706         assign { } { }
25707         assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b
25708       attribute \src "libresoc.v:0.0-0.0"
25709       case 5'10110
25710         assign { } { }
25711         assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b
25712       attribute \src "libresoc.v:0.0-0.0"
25713       case 5'01001
25714         assign { } { }
25715         assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b
25716       attribute \src "libresoc.v:0.0-0.0"
25717       case 5'01011
25718         assign { } { }
25719         assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b
25720       attribute \src "libresoc.v:0.0-0.0"
25721       case 5'11011
25722         assign { } { }
25723         assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b
25724       attribute \src "libresoc.v:0.0-0.0"
25725       case 5'01111
25726         assign { } { }
25727         assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b
25728       attribute \src "libresoc.v:0.0-0.0"
25729       case 5'10100
25730         assign { } { }
25731         assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b
25732       attribute \src "libresoc.v:0.0-0.0"
25733       case 5'10101
25734         assign { } { }
25735         assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b
25736       attribute \src "libresoc.v:0.0-0.0"
25737       case 5'10111
25738         assign { } { }
25739         assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b
25740       attribute \src "libresoc.v:0.0-0.0"
25741       case 5'10000
25742         assign { } { }
25743         assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b
25744       attribute \src "libresoc.v:0.0-0.0"
25745       case 5'10010
25746         assign { } { }
25747         assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b
25748       attribute \src "libresoc.v:0.0-0.0"
25749       case 5'01000
25750         assign { } { }
25751         assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b
25752       attribute \src "libresoc.v:0.0-0.0"
25753       case 5'11000
25754         assign { } { }
25755         assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b
25756       attribute \src "libresoc.v:0.0-0.0"
25757       case 5'00100
25758         assign { } { }
25759         assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b
25760       case
25761         assign $1\dec31_is_32b[0:0] 1'0
25762     end
25763     sync always
25764       update \dec31_is_32b $0\dec31_is_32b[0:0]
25765   end
25766   attribute \src "libresoc.v:17998.3-18058.6"
25767   process $proc$libresoc.v:17998$403
25768     assign { } { }
25769     assign { } { }
25770     assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0]
25771     attribute \src "libresoc.v:17999.5-17999.29"
25772     switch \initial
25773       attribute \src "libresoc.v:17999.9-17999.17"
25774       case 1'1
25775       case
25776     end
25777     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25778     switch \opc_in
25779       attribute \src "libresoc.v:0.0-0.0"
25780       case 5'01010
25781         assign { } { }
25782         assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn
25783       attribute \src "libresoc.v:0.0-0.0"
25784       case 5'11100
25785         assign { } { }
25786         assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn
25787       attribute \src "libresoc.v:0.0-0.0"
25788       case 5'00000
25789         assign { } { }
25790         assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn
25791       attribute \src "libresoc.v:0.0-0.0"
25792       case 5'11010
25793         assign { } { }
25794         assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn
25795       attribute \src "libresoc.v:0.0-0.0"
25796       case 5'10011
25797         assign { } { }
25798         assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn
25799       attribute \src "libresoc.v:0.0-0.0"
25800       case 5'10110
25801         assign { } { }
25802         assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn
25803       attribute \src "libresoc.v:0.0-0.0"
25804       case 5'01001
25805         assign { } { }
25806         assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn
25807       attribute \src "libresoc.v:0.0-0.0"
25808       case 5'01011
25809         assign { } { }
25810         assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn
25811       attribute \src "libresoc.v:0.0-0.0"
25812       case 5'11011
25813         assign { } { }
25814         assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn
25815       attribute \src "libresoc.v:0.0-0.0"
25816       case 5'01111
25817         assign { } { }
25818         assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn
25819       attribute \src "libresoc.v:0.0-0.0"
25820       case 5'10100
25821         assign { } { }
25822         assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn
25823       attribute \src "libresoc.v:0.0-0.0"
25824       case 5'10101
25825         assign { } { }
25826         assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn
25827       attribute \src "libresoc.v:0.0-0.0"
25828       case 5'10111
25829         assign { } { }
25830         assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn
25831       attribute \src "libresoc.v:0.0-0.0"
25832       case 5'10000
25833         assign { } { }
25834         assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn
25835       attribute \src "libresoc.v:0.0-0.0"
25836       case 5'10010
25837         assign { } { }
25838         assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn
25839       attribute \src "libresoc.v:0.0-0.0"
25840       case 5'01000
25841         assign { } { }
25842         assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn
25843       attribute \src "libresoc.v:0.0-0.0"
25844       case 5'11000
25845         assign { } { }
25846         assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn
25847       attribute \src "libresoc.v:0.0-0.0"
25848       case 5'00100
25849         assign { } { }
25850         assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn
25851       case
25852         assign $1\dec31_sgn[0:0] 1'0
25853     end
25854     sync always
25855       update \dec31_sgn $0\dec31_sgn[0:0]
25856   end
25857   attribute \src "libresoc.v:18059.3-18119.6"
25858   process $proc$libresoc.v:18059$404
25859     assign { } { }
25860     assign { } { }
25861     assign $0\dec31_lk[0:0] $1\dec31_lk[0:0]
25862     attribute \src "libresoc.v:18060.5-18060.29"
25863     switch \initial
25864       attribute \src "libresoc.v:18060.9-18060.17"
25865       case 1'1
25866       case
25867     end
25868     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25869     switch \opc_in
25870       attribute \src "libresoc.v:0.0-0.0"
25871       case 5'01010
25872         assign { } { }
25873         assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk
25874       attribute \src "libresoc.v:0.0-0.0"
25875       case 5'11100
25876         assign { } { }
25877         assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk
25878       attribute \src "libresoc.v:0.0-0.0"
25879       case 5'00000
25880         assign { } { }
25881         assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk
25882       attribute \src "libresoc.v:0.0-0.0"
25883       case 5'11010
25884         assign { } { }
25885         assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk
25886       attribute \src "libresoc.v:0.0-0.0"
25887       case 5'10011
25888         assign { } { }
25889         assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk
25890       attribute \src "libresoc.v:0.0-0.0"
25891       case 5'10110
25892         assign { } { }
25893         assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk
25894       attribute \src "libresoc.v:0.0-0.0"
25895       case 5'01001
25896         assign { } { }
25897         assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk
25898       attribute \src "libresoc.v:0.0-0.0"
25899       case 5'01011
25900         assign { } { }
25901         assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk
25902       attribute \src "libresoc.v:0.0-0.0"
25903       case 5'11011
25904         assign { } { }
25905         assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk
25906       attribute \src "libresoc.v:0.0-0.0"
25907       case 5'01111
25908         assign { } { }
25909         assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk
25910       attribute \src "libresoc.v:0.0-0.0"
25911       case 5'10100
25912         assign { } { }
25913         assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk
25914       attribute \src "libresoc.v:0.0-0.0"
25915       case 5'10101
25916         assign { } { }
25917         assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk
25918       attribute \src "libresoc.v:0.0-0.0"
25919       case 5'10111
25920         assign { } { }
25921         assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk
25922       attribute \src "libresoc.v:0.0-0.0"
25923       case 5'10000
25924         assign { } { }
25925         assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk
25926       attribute \src "libresoc.v:0.0-0.0"
25927       case 5'10010
25928         assign { } { }
25929         assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk
25930       attribute \src "libresoc.v:0.0-0.0"
25931       case 5'01000
25932         assign { } { }
25933         assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk
25934       attribute \src "libresoc.v:0.0-0.0"
25935       case 5'11000
25936         assign { } { }
25937         assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk
25938       attribute \src "libresoc.v:0.0-0.0"
25939       case 5'00100
25940         assign { } { }
25941         assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk
25942       case
25943         assign $1\dec31_lk[0:0] 1'0
25944     end
25945     sync always
25946       update \dec31_lk $0\dec31_lk[0:0]
25947   end
25948   attribute \src "libresoc.v:18120.3-18180.6"
25949   process $proc$libresoc.v:18120$405
25950     assign { } { }
25951     assign { } { }
25952     assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0]
25953     attribute \src "libresoc.v:18121.5-18121.29"
25954     switch \initial
25955       attribute \src "libresoc.v:18121.9-18121.17"
25956       case 1'1
25957       case
25958     end
25959     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
25960     switch \opc_in
25961       attribute \src "libresoc.v:0.0-0.0"
25962       case 5'01010
25963         assign { } { }
25964         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe
25965       attribute \src "libresoc.v:0.0-0.0"
25966       case 5'11100
25967         assign { } { }
25968         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe
25969       attribute \src "libresoc.v:0.0-0.0"
25970       case 5'00000
25971         assign { } { }
25972         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe
25973       attribute \src "libresoc.v:0.0-0.0"
25974       case 5'11010
25975         assign { } { }
25976         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe
25977       attribute \src "libresoc.v:0.0-0.0"
25978       case 5'10011
25979         assign { } { }
25980         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe
25981       attribute \src "libresoc.v:0.0-0.0"
25982       case 5'10110
25983         assign { } { }
25984         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe
25985       attribute \src "libresoc.v:0.0-0.0"
25986       case 5'01001
25987         assign { } { }
25988         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe
25989       attribute \src "libresoc.v:0.0-0.0"
25990       case 5'01011
25991         assign { } { }
25992         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe
25993       attribute \src "libresoc.v:0.0-0.0"
25994       case 5'11011
25995         assign { } { }
25996         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe
25997       attribute \src "libresoc.v:0.0-0.0"
25998       case 5'01111
25999         assign { } { }
26000         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe
26001       attribute \src "libresoc.v:0.0-0.0"
26002       case 5'10100
26003         assign { } { }
26004         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe
26005       attribute \src "libresoc.v:0.0-0.0"
26006       case 5'10101
26007         assign { } { }
26008         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe
26009       attribute \src "libresoc.v:0.0-0.0"
26010       case 5'10111
26011         assign { } { }
26012         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe
26013       attribute \src "libresoc.v:0.0-0.0"
26014       case 5'10000
26015         assign { } { }
26016         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe
26017       attribute \src "libresoc.v:0.0-0.0"
26018       case 5'10010
26019         assign { } { }
26020         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe
26021       attribute \src "libresoc.v:0.0-0.0"
26022       case 5'01000
26023         assign { } { }
26024         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe
26025       attribute \src "libresoc.v:0.0-0.0"
26026       case 5'11000
26027         assign { } { }
26028         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe
26029       attribute \src "libresoc.v:0.0-0.0"
26030       case 5'00100
26031         assign { } { }
26032         assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe
26033       case
26034         assign $1\dec31_sgl_pipe[0:0] 1'0
26035     end
26036     sync always
26037       update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0]
26038   end
26039   connect \dec31_dec_sub4_opcode_in \opcode_in
26040   connect \dec31_dec_sub24_opcode_in \opcode_in
26041   connect \dec31_dec_sub8_opcode_in \opcode_in
26042   connect \dec31_dec_sub18_opcode_in \opcode_in
26043   connect \dec31_dec_sub16_opcode_in \opcode_in
26044   connect \dec31_dec_sub23_opcode_in \opcode_in
26045   connect \dec31_dec_sub21_opcode_in \opcode_in
26046   connect \dec31_dec_sub20_opcode_in \opcode_in
26047   connect \dec31_dec_sub15_opcode_in \opcode_in
26048   connect \dec31_dec_sub27_opcode_in \opcode_in
26049   connect \dec31_dec_sub11_opcode_in \opcode_in
26050   connect \dec31_dec_sub9_opcode_in \opcode_in
26051   connect \dec31_dec_sub22_opcode_in \opcode_in
26052   connect \dec31_dec_sub19_opcode_in \opcode_in
26053   connect \dec31_dec_sub26_opcode_in \opcode_in
26054   connect \dec31_dec_sub0_opcode_in \opcode_in
26055   connect \dec31_dec_sub28_opcode_in \opcode_in
26056   connect \dec31_dec_sub10_opcode_in \opcode_in
26057   connect \opc_in \opcode_switch [4:0]
26058   connect \opcode_switch \opcode_in [10:1]
26059 end
26060 attribute \src "libresoc.v:18205.1-18920.10"
26061 attribute \cells_not_processed 1
26062 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0"
26063 attribute \generator "nMigen"
26064 module \dec31_dec_sub0
26065   attribute \src "libresoc.v:18558.3-18576.6"
26066   wire width 8 $0\dec31_dec_sub0_asmcode[7:0]
26067   attribute \src "libresoc.v:18634.3-18652.6"
26068   wire $0\dec31_dec_sub0_br[0:0]
26069   attribute \src "libresoc.v:18881.3-18899.6"
26070   wire width 3 $0\dec31_dec_sub0_cr_in[2:0]
26071   attribute \src "libresoc.v:18900.3-18918.6"
26072   wire width 3 $0\dec31_dec_sub0_cr_out[2:0]
26073   attribute \src "libresoc.v:18539.3-18557.6"
26074   wire width 2 $0\dec31_dec_sub0_cry_in[1:0]
26075   attribute \src "libresoc.v:18615.3-18633.6"
26076   wire $0\dec31_dec_sub0_cry_out[0:0]
26077   attribute \src "libresoc.v:18786.3-18804.6"
26078   wire width 5 $0\dec31_dec_sub0_form[4:0]
26079   attribute \src "libresoc.v:18463.3-18481.6"
26080   wire width 12 $0\dec31_dec_sub0_function_unit[11:0]
26081   attribute \src "libresoc.v:18805.3-18823.6"
26082   wire width 3 $0\dec31_dec_sub0_in1_sel[2:0]
26083   attribute \src "libresoc.v:18824.3-18842.6"
26084   wire width 4 $0\dec31_dec_sub0_in2_sel[3:0]
26085   attribute \src "libresoc.v:18843.3-18861.6"
26086   wire width 2 $0\dec31_dec_sub0_in3_sel[1:0]
26087   attribute \src "libresoc.v:18672.3-18690.6"
26088   wire width 7 $0\dec31_dec_sub0_internal_op[6:0]
26089   attribute \src "libresoc.v:18577.3-18595.6"
26090   wire $0\dec31_dec_sub0_inv_a[0:0]
26091   attribute \src "libresoc.v:18596.3-18614.6"
26092   wire $0\dec31_dec_sub0_inv_out[0:0]
26093   attribute \src "libresoc.v:18710.3-18728.6"
26094   wire $0\dec31_dec_sub0_is_32b[0:0]
26095   attribute \src "libresoc.v:18482.3-18500.6"
26096   wire width 4 $0\dec31_dec_sub0_ldst_len[3:0]
26097   attribute \src "libresoc.v:18748.3-18766.6"
26098   wire $0\dec31_dec_sub0_lk[0:0]
26099   attribute \src "libresoc.v:18862.3-18880.6"
26100   wire width 2 $0\dec31_dec_sub0_out_sel[1:0]
26101   attribute \src "libresoc.v:18520.3-18538.6"
26102   wire width 2 $0\dec31_dec_sub0_rc_sel[1:0]
26103   attribute \src "libresoc.v:18691.3-18709.6"
26104   wire $0\dec31_dec_sub0_rsrv[0:0]
26105   attribute \src "libresoc.v:18767.3-18785.6"
26106   wire $0\dec31_dec_sub0_sgl_pipe[0:0]
26107   attribute \src "libresoc.v:18729.3-18747.6"
26108   wire $0\dec31_dec_sub0_sgn[0:0]
26109   attribute \src "libresoc.v:18653.3-18671.6"
26110   wire $0\dec31_dec_sub0_sgn_ext[0:0]
26111   attribute \src "libresoc.v:18501.3-18519.6"
26112   wire width 2 $0\dec31_dec_sub0_upd[1:0]
26113   attribute \src "libresoc.v:18206.7-18206.20"
26114   wire $0\initial[0:0]
26115   attribute \src "libresoc.v:18558.3-18576.6"
26116   wire width 8 $1\dec31_dec_sub0_asmcode[7:0]
26117   attribute \src "libresoc.v:18634.3-18652.6"
26118   wire $1\dec31_dec_sub0_br[0:0]
26119   attribute \src "libresoc.v:18881.3-18899.6"
26120   wire width 3 $1\dec31_dec_sub0_cr_in[2:0]
26121   attribute \src "libresoc.v:18900.3-18918.6"
26122   wire width 3 $1\dec31_dec_sub0_cr_out[2:0]
26123   attribute \src "libresoc.v:18539.3-18557.6"
26124   wire width 2 $1\dec31_dec_sub0_cry_in[1:0]
26125   attribute \src "libresoc.v:18615.3-18633.6"
26126   wire $1\dec31_dec_sub0_cry_out[0:0]
26127   attribute \src "libresoc.v:18786.3-18804.6"
26128   wire width 5 $1\dec31_dec_sub0_form[4:0]
26129   attribute \src "libresoc.v:18463.3-18481.6"
26130   wire width 12 $1\dec31_dec_sub0_function_unit[11:0]
26131   attribute \src "libresoc.v:18805.3-18823.6"
26132   wire width 3 $1\dec31_dec_sub0_in1_sel[2:0]
26133   attribute \src "libresoc.v:18824.3-18842.6"
26134   wire width 4 $1\dec31_dec_sub0_in2_sel[3:0]
26135   attribute \src "libresoc.v:18843.3-18861.6"
26136   wire width 2 $1\dec31_dec_sub0_in3_sel[1:0]
26137   attribute \src "libresoc.v:18672.3-18690.6"
26138   wire width 7 $1\dec31_dec_sub0_internal_op[6:0]
26139   attribute \src "libresoc.v:18577.3-18595.6"
26140   wire $1\dec31_dec_sub0_inv_a[0:0]
26141   attribute \src "libresoc.v:18596.3-18614.6"
26142   wire $1\dec31_dec_sub0_inv_out[0:0]
26143   attribute \src "libresoc.v:18710.3-18728.6"
26144   wire $1\dec31_dec_sub0_is_32b[0:0]
26145   attribute \src "libresoc.v:18482.3-18500.6"
26146   wire width 4 $1\dec31_dec_sub0_ldst_len[3:0]
26147   attribute \src "libresoc.v:18748.3-18766.6"
26148   wire $1\dec31_dec_sub0_lk[0:0]
26149   attribute \src "libresoc.v:18862.3-18880.6"
26150   wire width 2 $1\dec31_dec_sub0_out_sel[1:0]
26151   attribute \src "libresoc.v:18520.3-18538.6"
26152   wire width 2 $1\dec31_dec_sub0_rc_sel[1:0]
26153   attribute \src "libresoc.v:18691.3-18709.6"
26154   wire $1\dec31_dec_sub0_rsrv[0:0]
26155   attribute \src "libresoc.v:18767.3-18785.6"
26156   wire $1\dec31_dec_sub0_sgl_pipe[0:0]
26157   attribute \src "libresoc.v:18729.3-18747.6"
26158   wire $1\dec31_dec_sub0_sgn[0:0]
26159   attribute \src "libresoc.v:18653.3-18671.6"
26160   wire $1\dec31_dec_sub0_sgn_ext[0:0]
26161   attribute \src "libresoc.v:18501.3-18519.6"
26162   wire width 2 $1\dec31_dec_sub0_upd[1:0]
26163   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26164   wire width 8 output 4 \dec31_dec_sub0_asmcode
26165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26166   wire output 18 \dec31_dec_sub0_br
26167   attribute \enum_base_type "CRInSel"
26168   attribute \enum_value_000 "NONE"
26169   attribute \enum_value_001 "CR0"
26170   attribute \enum_value_010 "BI"
26171   attribute \enum_value_011 "BFA"
26172   attribute \enum_value_100 "BA_BB"
26173   attribute \enum_value_101 "BC"
26174   attribute \enum_value_110 "WHOLE_REG"
26175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26176   wire width 3 output 9 \dec31_dec_sub0_cr_in
26177   attribute \enum_base_type "CROutSel"
26178   attribute \enum_value_000 "NONE"
26179   attribute \enum_value_001 "CR0"
26180   attribute \enum_value_010 "BF"
26181   attribute \enum_value_011 "BT"
26182   attribute \enum_value_100 "WHOLE_REG"
26183   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26184   wire width 3 output 10 \dec31_dec_sub0_cr_out
26185   attribute \enum_base_type "CryIn"
26186   attribute \enum_value_00 "ZERO"
26187   attribute \enum_value_01 "ONE"
26188   attribute \enum_value_10 "CA"
26189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26190   wire width 2 output 14 \dec31_dec_sub0_cry_in
26191   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26192   wire output 17 \dec31_dec_sub0_cry_out
26193   attribute \enum_base_type "Form"
26194   attribute \enum_value_00000 "NONE"
26195   attribute \enum_value_00001 "I"
26196   attribute \enum_value_00010 "B"
26197   attribute \enum_value_00011 "SC"
26198   attribute \enum_value_00100 "D"
26199   attribute \enum_value_00101 "DS"
26200   attribute \enum_value_00110 "DQ"
26201   attribute \enum_value_00111 "DX"
26202   attribute \enum_value_01000 "X"
26203   attribute \enum_value_01001 "XL"
26204   attribute \enum_value_01010 "XFX"
26205   attribute \enum_value_01011 "XFL"
26206   attribute \enum_value_01100 "XX1"
26207   attribute \enum_value_01101 "XX2"
26208   attribute \enum_value_01110 "XX3"
26209   attribute \enum_value_01111 "XX4"
26210   attribute \enum_value_10000 "XS"
26211   attribute \enum_value_10001 "XO"
26212   attribute \enum_value_10010 "A"
26213   attribute \enum_value_10011 "M"
26214   attribute \enum_value_10100 "MD"
26215   attribute \enum_value_10101 "MDS"
26216   attribute \enum_value_10110 "VA"
26217   attribute \enum_value_10111 "VC"
26218   attribute \enum_value_11000 "VX"
26219   attribute \enum_value_11001 "EVX"
26220   attribute \enum_value_11010 "EVS"
26221   attribute \enum_value_11011 "Z22"
26222   attribute \enum_value_11100 "Z23"
26223   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26224   wire width 5 output 3 \dec31_dec_sub0_form
26225   attribute \enum_base_type "Function"
26226   attribute \enum_value_000000000000 "NONE"
26227   attribute \enum_value_000000000010 "ALU"
26228   attribute \enum_value_000000000100 "LDST"
26229   attribute \enum_value_000000001000 "SHIFT_ROT"
26230   attribute \enum_value_000000010000 "LOGICAL"
26231   attribute \enum_value_000000100000 "BRANCH"
26232   attribute \enum_value_000001000000 "CR"
26233   attribute \enum_value_000010000000 "TRAP"
26234   attribute \enum_value_000100000000 "MUL"
26235   attribute \enum_value_001000000000 "DIV"
26236   attribute \enum_value_010000000000 "SPR"
26237   attribute \enum_value_100000000000 "MMU"
26238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26239   wire width 12 output 1 \dec31_dec_sub0_function_unit
26240   attribute \enum_base_type "In1Sel"
26241   attribute \enum_value_000 "NONE"
26242   attribute \enum_value_001 "RA"
26243   attribute \enum_value_010 "RA_OR_ZERO"
26244   attribute \enum_value_011 "SPR"
26245   attribute \enum_value_100 "RS"
26246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26247   wire width 3 output 5 \dec31_dec_sub0_in1_sel
26248   attribute \enum_base_type "In2Sel"
26249   attribute \enum_value_0000 "NONE"
26250   attribute \enum_value_0001 "RB"
26251   attribute \enum_value_0010 "CONST_UI"
26252   attribute \enum_value_0011 "CONST_SI"
26253   attribute \enum_value_0100 "CONST_UI_HI"
26254   attribute \enum_value_0101 "CONST_SI_HI"
26255   attribute \enum_value_0110 "CONST_LI"
26256   attribute \enum_value_0111 "CONST_BD"
26257   attribute \enum_value_1000 "CONST_DS"
26258   attribute \enum_value_1001 "CONST_M1"
26259   attribute \enum_value_1010 "CONST_SH"
26260   attribute \enum_value_1011 "CONST_SH32"
26261   attribute \enum_value_1100 "SPR"
26262   attribute \enum_value_1101 "RS"
26263   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26264   wire width 4 output 6 \dec31_dec_sub0_in2_sel
26265   attribute \enum_base_type "In3Sel"
26266   attribute \enum_value_00 "NONE"
26267   attribute \enum_value_01 "RS"
26268   attribute \enum_value_10 "RB"
26269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26270   wire width 2 output 7 \dec31_dec_sub0_in3_sel
26271   attribute \enum_base_type "MicrOp"
26272   attribute \enum_value_0000000 "OP_ILLEGAL"
26273   attribute \enum_value_0000001 "OP_NOP"
26274   attribute \enum_value_0000010 "OP_ADD"
26275   attribute \enum_value_0000011 "OP_ADDPCIS"
26276   attribute \enum_value_0000100 "OP_AND"
26277   attribute \enum_value_0000101 "OP_ATTN"
26278   attribute \enum_value_0000110 "OP_B"
26279   attribute \enum_value_0000111 "OP_BC"
26280   attribute \enum_value_0001000 "OP_BCREG"
26281   attribute \enum_value_0001001 "OP_BPERM"
26282   attribute \enum_value_0001010 "OP_CMP"
26283   attribute \enum_value_0001011 "OP_CMPB"
26284   attribute \enum_value_0001100 "OP_CMPEQB"
26285   attribute \enum_value_0001101 "OP_CMPRB"
26286   attribute \enum_value_0001110 "OP_CNTZ"
26287   attribute \enum_value_0001111 "OP_CRAND"
26288   attribute \enum_value_0010000 "OP_CRANDC"
26289   attribute \enum_value_0010001 "OP_CREQV"
26290   attribute \enum_value_0010010 "OP_CRNAND"
26291   attribute \enum_value_0010011 "OP_CRNOR"
26292   attribute \enum_value_0010100 "OP_CROR"
26293   attribute \enum_value_0010101 "OP_CRORC"
26294   attribute \enum_value_0010110 "OP_CRXOR"
26295   attribute \enum_value_0010111 "OP_DARN"
26296   attribute \enum_value_0011000 "OP_DCBF"
26297   attribute \enum_value_0011001 "OP_DCBST"
26298   attribute \enum_value_0011010 "OP_DCBT"
26299   attribute \enum_value_0011011 "OP_DCBTST"
26300   attribute \enum_value_0011100 "OP_DCBZ"
26301   attribute \enum_value_0011101 "OP_DIV"
26302   attribute \enum_value_0011110 "OP_DIVE"
26303   attribute \enum_value_0011111 "OP_EXTS"
26304   attribute \enum_value_0100000 "OP_EXTSWSLI"
26305   attribute \enum_value_0100001 "OP_ICBI"
26306   attribute \enum_value_0100010 "OP_ICBT"
26307   attribute \enum_value_0100011 "OP_ISEL"
26308   attribute \enum_value_0100100 "OP_ISYNC"
26309   attribute \enum_value_0100101 "OP_LOAD"
26310   attribute \enum_value_0100110 "OP_STORE"
26311   attribute \enum_value_0100111 "OP_MADDHD"
26312   attribute \enum_value_0101000 "OP_MADDHDU"
26313   attribute \enum_value_0101001 "OP_MADDLD"
26314   attribute \enum_value_0101010 "OP_MCRF"
26315   attribute \enum_value_0101011 "OP_MCRXR"
26316   attribute \enum_value_0101100 "OP_MCRXRX"
26317   attribute \enum_value_0101101 "OP_MFCR"
26318   attribute \enum_value_0101110 "OP_MFSPR"
26319   attribute \enum_value_0101111 "OP_MOD"
26320   attribute \enum_value_0110000 "OP_MTCRF"
26321   attribute \enum_value_0110001 "OP_MTSPR"
26322   attribute \enum_value_0110010 "OP_MUL_L64"
26323   attribute \enum_value_0110011 "OP_MUL_H64"
26324   attribute \enum_value_0110100 "OP_MUL_H32"
26325   attribute \enum_value_0110101 "OP_OR"
26326   attribute \enum_value_0110110 "OP_POPCNT"
26327   attribute \enum_value_0110111 "OP_PRTY"
26328   attribute \enum_value_0111000 "OP_RLC"
26329   attribute \enum_value_0111001 "OP_RLCL"
26330   attribute \enum_value_0111010 "OP_RLCR"
26331   attribute \enum_value_0111011 "OP_SETB"
26332   attribute \enum_value_0111100 "OP_SHL"
26333   attribute \enum_value_0111101 "OP_SHR"
26334   attribute \enum_value_0111110 "OP_SYNC"
26335   attribute \enum_value_0111111 "OP_TRAP"
26336   attribute \enum_value_1000011 "OP_XOR"
26337   attribute \enum_value_1000100 "OP_SIM_CONFIG"
26338   attribute \enum_value_1000101 "OP_CROP"
26339   attribute \enum_value_1000110 "OP_RFID"
26340   attribute \enum_value_1000111 "OP_MFMSR"
26341   attribute \enum_value_1001000 "OP_MTMSRD"
26342   attribute \enum_value_1001001 "OP_SC"
26343   attribute \enum_value_1001010 "OP_MTMSR"
26344   attribute \enum_value_1001011 "OP_TLBIE"
26345   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26346   wire width 7 output 2 \dec31_dec_sub0_internal_op
26347   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26348   wire output 15 \dec31_dec_sub0_inv_a
26349   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26350   wire output 16 \dec31_dec_sub0_inv_out
26351   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26352   wire output 21 \dec31_dec_sub0_is_32b
26353   attribute \enum_base_type "LdstLen"
26354   attribute \enum_value_0000 "NONE"
26355   attribute \enum_value_0001 "is1B"
26356   attribute \enum_value_0010 "is2B"
26357   attribute \enum_value_0100 "is4B"
26358   attribute \enum_value_1000 "is8B"
26359   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26360   wire width 4 output 11 \dec31_dec_sub0_ldst_len
26361   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26362   wire output 23 \dec31_dec_sub0_lk
26363   attribute \enum_base_type "OutSel"
26364   attribute \enum_value_00 "NONE"
26365   attribute \enum_value_01 "RT"
26366   attribute \enum_value_10 "RA"
26367   attribute \enum_value_11 "SPR"
26368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26369   wire width 2 output 8 \dec31_dec_sub0_out_sel
26370   attribute \enum_base_type "RC"
26371   attribute \enum_value_00 "NONE"
26372   attribute \enum_value_01 "ONE"
26373   attribute \enum_value_10 "RC"
26374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26375   wire width 2 output 13 \dec31_dec_sub0_rc_sel
26376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26377   wire output 20 \dec31_dec_sub0_rsrv
26378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26379   wire output 24 \dec31_dec_sub0_sgl_pipe
26380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26381   wire output 22 \dec31_dec_sub0_sgn
26382   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
26383   wire output 19 \dec31_dec_sub0_sgn_ext
26384   attribute \enum_base_type "LDSTMode"
26385   attribute \enum_value_00 "NONE"
26386   attribute \enum_value_01 "update"
26387   attribute \enum_value_10 "cix"
26388   attribute \enum_value_11 "cx"
26389   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
26390   wire width 2 output 12 \dec31_dec_sub0_upd
26391   attribute \src "libresoc.v:18206.7-18206.15"
26392   wire \initial
26393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
26394   wire width 32 input 25 \opcode_in
26395   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
26396   wire width 5 \opcode_switch
26397   attribute \src "libresoc.v:18206.7-18206.20"
26398   process $proc$libresoc.v:18206$431
26399     assign { } { }
26400     assign $0\initial[0:0] 1'0
26401     sync always
26402       update \initial $0\initial[0:0]
26403     sync init
26404   end
26405   attribute \src "libresoc.v:18463.3-18481.6"
26406   process $proc$libresoc.v:18463$407
26407     assign { } { }
26408     assign { } { }
26409     assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0]
26410     attribute \src "libresoc.v:18464.5-18464.29"
26411     switch \initial
26412       attribute \src "libresoc.v:18464.9-18464.17"
26413       case 1'1
26414       case
26415     end
26416     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26417     switch \opcode_switch
26418       attribute \src "libresoc.v:0.0-0.0"
26419       case 5'00000
26420         assign { } { }
26421         assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010
26422       attribute \src "libresoc.v:0.0-0.0"
26423       case 5'00111
26424         assign { } { }
26425         assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010
26426       attribute \src "libresoc.v:0.0-0.0"
26427       case 5'00001
26428         assign { } { }
26429         assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010
26430       attribute \src "libresoc.v:0.0-0.0"
26431       case 5'00100
26432         assign { } { }
26433         assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000
26434       case
26435         assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000
26436     end
26437     sync always
26438       update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0]
26439   end
26440   attribute \src "libresoc.v:18482.3-18500.6"
26441   process $proc$libresoc.v:18482$408
26442     assign { } { }
26443     assign { } { }
26444     assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0]
26445     attribute \src "libresoc.v:18483.5-18483.29"
26446     switch \initial
26447       attribute \src "libresoc.v:18483.9-18483.17"
26448       case 1'1
26449       case
26450     end
26451     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26452     switch \opcode_switch
26453       attribute \src "libresoc.v:0.0-0.0"
26454       case 5'00000
26455         assign { } { }
26456         assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000
26457       attribute \src "libresoc.v:0.0-0.0"
26458       case 5'00111
26459         assign { } { }
26460         assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000
26461       attribute \src "libresoc.v:0.0-0.0"
26462       case 5'00001
26463         assign { } { }
26464         assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000
26465       attribute \src "libresoc.v:0.0-0.0"
26466       case 5'00100
26467         assign { } { }
26468         assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000
26469       case
26470         assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000
26471     end
26472     sync always
26473       update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0]
26474   end
26475   attribute \src "libresoc.v:18501.3-18519.6"
26476   process $proc$libresoc.v:18501$409
26477     assign { } { }
26478     assign { } { }
26479     assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0]
26480     attribute \src "libresoc.v:18502.5-18502.29"
26481     switch \initial
26482       attribute \src "libresoc.v:18502.9-18502.17"
26483       case 1'1
26484       case
26485     end
26486     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26487     switch \opcode_switch
26488       attribute \src "libresoc.v:0.0-0.0"
26489       case 5'00000
26490         assign { } { }
26491         assign $1\dec31_dec_sub0_upd[1:0] 2'00
26492       attribute \src "libresoc.v:0.0-0.0"
26493       case 5'00111
26494         assign { } { }
26495         assign $1\dec31_dec_sub0_upd[1:0] 2'00
26496       attribute \src "libresoc.v:0.0-0.0"
26497       case 5'00001
26498         assign { } { }
26499         assign $1\dec31_dec_sub0_upd[1:0] 2'00
26500       attribute \src "libresoc.v:0.0-0.0"
26501       case 5'00100
26502         assign { } { }
26503         assign $1\dec31_dec_sub0_upd[1:0] 2'00
26504       case
26505         assign $1\dec31_dec_sub0_upd[1:0] 2'00
26506     end
26507     sync always
26508       update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0]
26509   end
26510   attribute \src "libresoc.v:18520.3-18538.6"
26511   process $proc$libresoc.v:18520$410
26512     assign { } { }
26513     assign { } { }
26514     assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0]
26515     attribute \src "libresoc.v:18521.5-18521.29"
26516     switch \initial
26517       attribute \src "libresoc.v:18521.9-18521.17"
26518       case 1'1
26519       case
26520     end
26521     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26522     switch \opcode_switch
26523       attribute \src "libresoc.v:0.0-0.0"
26524       case 5'00000
26525         assign { } { }
26526         assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00
26527       attribute \src "libresoc.v:0.0-0.0"
26528       case 5'00111
26529         assign { } { }
26530         assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00
26531       attribute \src "libresoc.v:0.0-0.0"
26532       case 5'00001
26533         assign { } { }
26534         assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00
26535       attribute \src "libresoc.v:0.0-0.0"
26536       case 5'00100
26537         assign { } { }
26538         assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00
26539       case
26540         assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00
26541     end
26542     sync always
26543       update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0]
26544   end
26545   attribute \src "libresoc.v:18539.3-18557.6"
26546   process $proc$libresoc.v:18539$411
26547     assign { } { }
26548     assign { } { }
26549     assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0]
26550     attribute \src "libresoc.v:18540.5-18540.29"
26551     switch \initial
26552       attribute \src "libresoc.v:18540.9-18540.17"
26553       case 1'1
26554       case
26555     end
26556     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26557     switch \opcode_switch
26558       attribute \src "libresoc.v:0.0-0.0"
26559       case 5'00000
26560         assign { } { }
26561         assign $1\dec31_dec_sub0_cry_in[1:0] 2'01
26562       attribute \src "libresoc.v:0.0-0.0"
26563       case 5'00111
26564         assign { } { }
26565         assign $1\dec31_dec_sub0_cry_in[1:0] 2'00
26566       attribute \src "libresoc.v:0.0-0.0"
26567       case 5'00001
26568         assign { } { }
26569         assign $1\dec31_dec_sub0_cry_in[1:0] 2'01
26570       attribute \src "libresoc.v:0.0-0.0"
26571       case 5'00100
26572         assign { } { }
26573         assign $1\dec31_dec_sub0_cry_in[1:0] 2'00
26574       case
26575         assign $1\dec31_dec_sub0_cry_in[1:0] 2'00
26576     end
26577     sync always
26578       update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0]
26579   end
26580   attribute \src "libresoc.v:18558.3-18576.6"
26581   process $proc$libresoc.v:18558$412
26582     assign { } { }
26583     assign { } { }
26584     assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0]
26585     attribute \src "libresoc.v:18559.5-18559.29"
26586     switch \initial
26587       attribute \src "libresoc.v:18559.9-18559.17"
26588       case 1'1
26589       case
26590     end
26591     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26592     switch \opcode_switch
26593       attribute \src "libresoc.v:0.0-0.0"
26594       case 5'00000
26595         assign { } { }
26596         assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010
26597       attribute \src "libresoc.v:0.0-0.0"
26598       case 5'00111
26599         assign { } { }
26600         assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100
26601       attribute \src "libresoc.v:0.0-0.0"
26602       case 5'00001
26603         assign { } { }
26604         assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110
26605       attribute \src "libresoc.v:0.0-0.0"
26606       case 5'00100
26607         assign { } { }
26608         assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011
26609       case
26610         assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000
26611     end
26612     sync always
26613       update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0]
26614   end
26615   attribute \src "libresoc.v:18577.3-18595.6"
26616   process $proc$libresoc.v:18577$413
26617     assign { } { }
26618     assign { } { }
26619     assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0]
26620     attribute \src "libresoc.v:18578.5-18578.29"
26621     switch \initial
26622       attribute \src "libresoc.v:18578.9-18578.17"
26623       case 1'1
26624       case
26625     end
26626     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26627     switch \opcode_switch
26628       attribute \src "libresoc.v:0.0-0.0"
26629       case 5'00000
26630         assign { } { }
26631         assign $1\dec31_dec_sub0_inv_a[0:0] 1'1
26632       attribute \src "libresoc.v:0.0-0.0"
26633       case 5'00111
26634         assign { } { }
26635         assign $1\dec31_dec_sub0_inv_a[0:0] 1'0
26636       attribute \src "libresoc.v:0.0-0.0"
26637       case 5'00001
26638         assign { } { }
26639         assign $1\dec31_dec_sub0_inv_a[0:0] 1'1
26640       attribute \src "libresoc.v:0.0-0.0"
26641       case 5'00100
26642         assign { } { }
26643         assign $1\dec31_dec_sub0_inv_a[0:0] 1'0
26644       case
26645         assign $1\dec31_dec_sub0_inv_a[0:0] 1'0
26646     end
26647     sync always
26648       update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0]
26649   end
26650   attribute \src "libresoc.v:18596.3-18614.6"
26651   process $proc$libresoc.v:18596$414
26652     assign { } { }
26653     assign { } { }
26654     assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0]
26655     attribute \src "libresoc.v:18597.5-18597.29"
26656     switch \initial
26657       attribute \src "libresoc.v:18597.9-18597.17"
26658       case 1'1
26659       case
26660     end
26661     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26662     switch \opcode_switch
26663       attribute \src "libresoc.v:0.0-0.0"
26664       case 5'00000
26665         assign { } { }
26666         assign $1\dec31_dec_sub0_inv_out[0:0] 1'0
26667       attribute \src "libresoc.v:0.0-0.0"
26668       case 5'00111
26669         assign { } { }
26670         assign $1\dec31_dec_sub0_inv_out[0:0] 1'0
26671       attribute \src "libresoc.v:0.0-0.0"
26672       case 5'00001
26673         assign { } { }
26674         assign $1\dec31_dec_sub0_inv_out[0:0] 1'0
26675       attribute \src "libresoc.v:0.0-0.0"
26676       case 5'00100
26677         assign { } { }
26678         assign $1\dec31_dec_sub0_inv_out[0:0] 1'0
26679       case
26680         assign $1\dec31_dec_sub0_inv_out[0:0] 1'0
26681     end
26682     sync always
26683       update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0]
26684   end
26685   attribute \src "libresoc.v:18615.3-18633.6"
26686   process $proc$libresoc.v:18615$415
26687     assign { } { }
26688     assign { } { }
26689     assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0]
26690     attribute \src "libresoc.v:18616.5-18616.29"
26691     switch \initial
26692       attribute \src "libresoc.v:18616.9-18616.17"
26693       case 1'1
26694       case
26695     end
26696     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26697     switch \opcode_switch
26698       attribute \src "libresoc.v:0.0-0.0"
26699       case 5'00000
26700         assign { } { }
26701         assign $1\dec31_dec_sub0_cry_out[0:0] 1'0
26702       attribute \src "libresoc.v:0.0-0.0"
26703       case 5'00111
26704         assign { } { }
26705         assign $1\dec31_dec_sub0_cry_out[0:0] 1'0
26706       attribute \src "libresoc.v:0.0-0.0"
26707       case 5'00001
26708         assign { } { }
26709         assign $1\dec31_dec_sub0_cry_out[0:0] 1'0
26710       attribute \src "libresoc.v:0.0-0.0"
26711       case 5'00100
26712         assign { } { }
26713         assign $1\dec31_dec_sub0_cry_out[0:0] 1'0
26714       case
26715         assign $1\dec31_dec_sub0_cry_out[0:0] 1'0
26716     end
26717     sync always
26718       update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0]
26719   end
26720   attribute \src "libresoc.v:18634.3-18652.6"
26721   process $proc$libresoc.v:18634$416
26722     assign { } { }
26723     assign { } { }
26724     assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0]
26725     attribute \src "libresoc.v:18635.5-18635.29"
26726     switch \initial
26727       attribute \src "libresoc.v:18635.9-18635.17"
26728       case 1'1
26729       case
26730     end
26731     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26732     switch \opcode_switch
26733       attribute \src "libresoc.v:0.0-0.0"
26734       case 5'00000
26735         assign { } { }
26736         assign $1\dec31_dec_sub0_br[0:0] 1'0
26737       attribute \src "libresoc.v:0.0-0.0"
26738       case 5'00111
26739         assign { } { }
26740         assign $1\dec31_dec_sub0_br[0:0] 1'0
26741       attribute \src "libresoc.v:0.0-0.0"
26742       case 5'00001
26743         assign { } { }
26744         assign $1\dec31_dec_sub0_br[0:0] 1'0
26745       attribute \src "libresoc.v:0.0-0.0"
26746       case 5'00100
26747         assign { } { }
26748         assign $1\dec31_dec_sub0_br[0:0] 1'0
26749       case
26750         assign $1\dec31_dec_sub0_br[0:0] 1'0
26751     end
26752     sync always
26753       update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0]
26754   end
26755   attribute \src "libresoc.v:18653.3-18671.6"
26756   process $proc$libresoc.v:18653$417
26757     assign { } { }
26758     assign { } { }
26759     assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0]
26760     attribute \src "libresoc.v:18654.5-18654.29"
26761     switch \initial
26762       attribute \src "libresoc.v:18654.9-18654.17"
26763       case 1'1
26764       case
26765     end
26766     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26767     switch \opcode_switch
26768       attribute \src "libresoc.v:0.0-0.0"
26769       case 5'00000
26770         assign { } { }
26771         assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0
26772       attribute \src "libresoc.v:0.0-0.0"
26773       case 5'00111
26774         assign { } { }
26775         assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0
26776       attribute \src "libresoc.v:0.0-0.0"
26777       case 5'00001
26778         assign { } { }
26779         assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0
26780       attribute \src "libresoc.v:0.0-0.0"
26781       case 5'00100
26782         assign { } { }
26783         assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0
26784       case
26785         assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0
26786     end
26787     sync always
26788       update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0]
26789   end
26790   attribute \src "libresoc.v:18672.3-18690.6"
26791   process $proc$libresoc.v:18672$418
26792     assign { } { }
26793     assign { } { }
26794     assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0]
26795     attribute \src "libresoc.v:18673.5-18673.29"
26796     switch \initial
26797       attribute \src "libresoc.v:18673.9-18673.17"
26798       case 1'1
26799       case
26800     end
26801     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26802     switch \opcode_switch
26803       attribute \src "libresoc.v:0.0-0.0"
26804       case 5'00000
26805         assign { } { }
26806         assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010
26807       attribute \src "libresoc.v:0.0-0.0"
26808       case 5'00111
26809         assign { } { }
26810         assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100
26811       attribute \src "libresoc.v:0.0-0.0"
26812       case 5'00001
26813         assign { } { }
26814         assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010
26815       attribute \src "libresoc.v:0.0-0.0"
26816       case 5'00100
26817         assign { } { }
26818         assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011
26819       case
26820         assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000
26821     end
26822     sync always
26823       update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0]
26824   end
26825   attribute \src "libresoc.v:18691.3-18709.6"
26826   process $proc$libresoc.v:18691$419
26827     assign { } { }
26828     assign { } { }
26829     assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0]
26830     attribute \src "libresoc.v:18692.5-18692.29"
26831     switch \initial
26832       attribute \src "libresoc.v:18692.9-18692.17"
26833       case 1'1
26834       case
26835     end
26836     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26837     switch \opcode_switch
26838       attribute \src "libresoc.v:0.0-0.0"
26839       case 5'00000
26840         assign { } { }
26841         assign $1\dec31_dec_sub0_rsrv[0:0] 1'0
26842       attribute \src "libresoc.v:0.0-0.0"
26843       case 5'00111
26844         assign { } { }
26845         assign $1\dec31_dec_sub0_rsrv[0:0] 1'0
26846       attribute \src "libresoc.v:0.0-0.0"
26847       case 5'00001
26848         assign { } { }
26849         assign $1\dec31_dec_sub0_rsrv[0:0] 1'0
26850       attribute \src "libresoc.v:0.0-0.0"
26851       case 5'00100
26852         assign { } { }
26853         assign $1\dec31_dec_sub0_rsrv[0:0] 1'0
26854       case
26855         assign $1\dec31_dec_sub0_rsrv[0:0] 1'0
26856     end
26857     sync always
26858       update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0]
26859   end
26860   attribute \src "libresoc.v:18710.3-18728.6"
26861   process $proc$libresoc.v:18710$420
26862     assign { } { }
26863     assign { } { }
26864     assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0]
26865     attribute \src "libresoc.v:18711.5-18711.29"
26866     switch \initial
26867       attribute \src "libresoc.v:18711.9-18711.17"
26868       case 1'1
26869       case
26870     end
26871     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26872     switch \opcode_switch
26873       attribute \src "libresoc.v:0.0-0.0"
26874       case 5'00000
26875         assign { } { }
26876         assign $1\dec31_dec_sub0_is_32b[0:0] 1'0
26877       attribute \src "libresoc.v:0.0-0.0"
26878       case 5'00111
26879         assign { } { }
26880         assign $1\dec31_dec_sub0_is_32b[0:0] 1'0
26881       attribute \src "libresoc.v:0.0-0.0"
26882       case 5'00001
26883         assign { } { }
26884         assign $1\dec31_dec_sub0_is_32b[0:0] 1'0
26885       attribute \src "libresoc.v:0.0-0.0"
26886       case 5'00100
26887         assign { } { }
26888         assign $1\dec31_dec_sub0_is_32b[0:0] 1'0
26889       case
26890         assign $1\dec31_dec_sub0_is_32b[0:0] 1'0
26891     end
26892     sync always
26893       update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0]
26894   end
26895   attribute \src "libresoc.v:18729.3-18747.6"
26896   process $proc$libresoc.v:18729$421
26897     assign { } { }
26898     assign { } { }
26899     assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0]
26900     attribute \src "libresoc.v:18730.5-18730.29"
26901     switch \initial
26902       attribute \src "libresoc.v:18730.9-18730.17"
26903       case 1'1
26904       case
26905     end
26906     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26907     switch \opcode_switch
26908       attribute \src "libresoc.v:0.0-0.0"
26909       case 5'00000
26910         assign { } { }
26911         assign $1\dec31_dec_sub0_sgn[0:0] 1'1
26912       attribute \src "libresoc.v:0.0-0.0"
26913       case 5'00111
26914         assign { } { }
26915         assign $1\dec31_dec_sub0_sgn[0:0] 1'0
26916       attribute \src "libresoc.v:0.0-0.0"
26917       case 5'00001
26918         assign { } { }
26919         assign $1\dec31_dec_sub0_sgn[0:0] 1'0
26920       attribute \src "libresoc.v:0.0-0.0"
26921       case 5'00100
26922         assign { } { }
26923         assign $1\dec31_dec_sub0_sgn[0:0] 1'0
26924       case
26925         assign $1\dec31_dec_sub0_sgn[0:0] 1'0
26926     end
26927     sync always
26928       update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0]
26929   end
26930   attribute \src "libresoc.v:18748.3-18766.6"
26931   process $proc$libresoc.v:18748$422
26932     assign { } { }
26933     assign { } { }
26934     assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0]
26935     attribute \src "libresoc.v:18749.5-18749.29"
26936     switch \initial
26937       attribute \src "libresoc.v:18749.9-18749.17"
26938       case 1'1
26939       case
26940     end
26941     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26942     switch \opcode_switch
26943       attribute \src "libresoc.v:0.0-0.0"
26944       case 5'00000
26945         assign { } { }
26946         assign $1\dec31_dec_sub0_lk[0:0] 1'0
26947       attribute \src "libresoc.v:0.0-0.0"
26948       case 5'00111
26949         assign { } { }
26950         assign $1\dec31_dec_sub0_lk[0:0] 1'0
26951       attribute \src "libresoc.v:0.0-0.0"
26952       case 5'00001
26953         assign { } { }
26954         assign $1\dec31_dec_sub0_lk[0:0] 1'0
26955       attribute \src "libresoc.v:0.0-0.0"
26956       case 5'00100
26957         assign { } { }
26958         assign $1\dec31_dec_sub0_lk[0:0] 1'0
26959       case
26960         assign $1\dec31_dec_sub0_lk[0:0] 1'0
26961     end
26962     sync always
26963       update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0]
26964   end
26965   attribute \src "libresoc.v:18767.3-18785.6"
26966   process $proc$libresoc.v:18767$423
26967     assign { } { }
26968     assign { } { }
26969     assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0]
26970     attribute \src "libresoc.v:18768.5-18768.29"
26971     switch \initial
26972       attribute \src "libresoc.v:18768.9-18768.17"
26973       case 1'1
26974       case
26975     end
26976     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
26977     switch \opcode_switch
26978       attribute \src "libresoc.v:0.0-0.0"
26979       case 5'00000
26980         assign { } { }
26981         assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0
26982       attribute \src "libresoc.v:0.0-0.0"
26983       case 5'00111
26984         assign { } { }
26985         assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0
26986       attribute \src "libresoc.v:0.0-0.0"
26987       case 5'00001
26988         assign { } { }
26989         assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0
26990       attribute \src "libresoc.v:0.0-0.0"
26991       case 5'00100
26992         assign { } { }
26993         assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0
26994       case
26995         assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0
26996     end
26997     sync always
26998       update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0]
26999   end
27000   attribute \src "libresoc.v:18786.3-18804.6"
27001   process $proc$libresoc.v:18786$424
27002     assign { } { }
27003     assign { } { }
27004     assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0]
27005     attribute \src "libresoc.v:18787.5-18787.29"
27006     switch \initial
27007       attribute \src "libresoc.v:18787.9-18787.17"
27008       case 1'1
27009       case
27010     end
27011     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27012     switch \opcode_switch
27013       attribute \src "libresoc.v:0.0-0.0"
27014       case 5'00000
27015         assign { } { }
27016         assign $1\dec31_dec_sub0_form[4:0] 5'01000
27017       attribute \src "libresoc.v:0.0-0.0"
27018       case 5'00111
27019         assign { } { }
27020         assign $1\dec31_dec_sub0_form[4:0] 5'01000
27021       attribute \src "libresoc.v:0.0-0.0"
27022       case 5'00001
27023         assign { } { }
27024         assign $1\dec31_dec_sub0_form[4:0] 5'01000
27025       attribute \src "libresoc.v:0.0-0.0"
27026       case 5'00100
27027         assign { } { }
27028         assign $1\dec31_dec_sub0_form[4:0] 5'11000
27029       case
27030         assign $1\dec31_dec_sub0_form[4:0] 5'00000
27031     end
27032     sync always
27033       update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0]
27034   end
27035   attribute \src "libresoc.v:18805.3-18823.6"
27036   process $proc$libresoc.v:18805$425
27037     assign { } { }
27038     assign { } { }
27039     assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0]
27040     attribute \src "libresoc.v:18806.5-18806.29"
27041     switch \initial
27042       attribute \src "libresoc.v:18806.9-18806.17"
27043       case 1'1
27044       case
27045     end
27046     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27047     switch \opcode_switch
27048       attribute \src "libresoc.v:0.0-0.0"
27049       case 5'00000
27050         assign { } { }
27051         assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001
27052       attribute \src "libresoc.v:0.0-0.0"
27053       case 5'00111
27054         assign { } { }
27055         assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001
27056       attribute \src "libresoc.v:0.0-0.0"
27057       case 5'00001
27058         assign { } { }
27059         assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001
27060       attribute \src "libresoc.v:0.0-0.0"
27061       case 5'00100
27062         assign { } { }
27063         assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000
27064       case
27065         assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000
27066     end
27067     sync always
27068       update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0]
27069   end
27070   attribute \src "libresoc.v:18824.3-18842.6"
27071   process $proc$libresoc.v:18824$426
27072     assign { } { }
27073     assign { } { }
27074     assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0]
27075     attribute \src "libresoc.v:18825.5-18825.29"
27076     switch \initial
27077       attribute \src "libresoc.v:18825.9-18825.17"
27078       case 1'1
27079       case
27080     end
27081     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27082     switch \opcode_switch
27083       attribute \src "libresoc.v:0.0-0.0"
27084       case 5'00000
27085         assign { } { }
27086         assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001
27087       attribute \src "libresoc.v:0.0-0.0"
27088       case 5'00111
27089         assign { } { }
27090         assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001
27091       attribute \src "libresoc.v:0.0-0.0"
27092       case 5'00001
27093         assign { } { }
27094         assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001
27095       attribute \src "libresoc.v:0.0-0.0"
27096       case 5'00100
27097         assign { } { }
27098         assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000
27099       case
27100         assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000
27101     end
27102     sync always
27103       update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0]
27104   end
27105   attribute \src "libresoc.v:18843.3-18861.6"
27106   process $proc$libresoc.v:18843$427
27107     assign { } { }
27108     assign { } { }
27109     assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0]
27110     attribute \src "libresoc.v:18844.5-18844.29"
27111     switch \initial
27112       attribute \src "libresoc.v:18844.9-18844.17"
27113       case 1'1
27114       case
27115     end
27116     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27117     switch \opcode_switch
27118       attribute \src "libresoc.v:0.0-0.0"
27119       case 5'00000
27120         assign { } { }
27121         assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00
27122       attribute \src "libresoc.v:0.0-0.0"
27123       case 5'00111
27124         assign { } { }
27125         assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00
27126       attribute \src "libresoc.v:0.0-0.0"
27127       case 5'00001
27128         assign { } { }
27129         assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00
27130       attribute \src "libresoc.v:0.0-0.0"
27131       case 5'00100
27132         assign { } { }
27133         assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00
27134       case
27135         assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00
27136     end
27137     sync always
27138       update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0]
27139   end
27140   attribute \src "libresoc.v:18862.3-18880.6"
27141   process $proc$libresoc.v:18862$428
27142     assign { } { }
27143     assign { } { }
27144     assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0]
27145     attribute \src "libresoc.v:18863.5-18863.29"
27146     switch \initial
27147       attribute \src "libresoc.v:18863.9-18863.17"
27148       case 1'1
27149       case
27150     end
27151     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27152     switch \opcode_switch
27153       attribute \src "libresoc.v:0.0-0.0"
27154       case 5'00000
27155         assign { } { }
27156         assign $1\dec31_dec_sub0_out_sel[1:0] 2'00
27157       attribute \src "libresoc.v:0.0-0.0"
27158       case 5'00111
27159         assign { } { }
27160         assign $1\dec31_dec_sub0_out_sel[1:0] 2'00
27161       attribute \src "libresoc.v:0.0-0.0"
27162       case 5'00001
27163         assign { } { }
27164         assign $1\dec31_dec_sub0_out_sel[1:0] 2'00
27165       attribute \src "libresoc.v:0.0-0.0"
27166       case 5'00100
27167         assign { } { }
27168         assign $1\dec31_dec_sub0_out_sel[1:0] 2'01
27169       case
27170         assign $1\dec31_dec_sub0_out_sel[1:0] 2'00
27171     end
27172     sync always
27173       update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0]
27174   end
27175   attribute \src "libresoc.v:18881.3-18899.6"
27176   process $proc$libresoc.v:18881$429
27177     assign { } { }
27178     assign { } { }
27179     assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0]
27180     attribute \src "libresoc.v:18882.5-18882.29"
27181     switch \initial
27182       attribute \src "libresoc.v:18882.9-18882.17"
27183       case 1'1
27184       case
27185     end
27186     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27187     switch \opcode_switch
27188       attribute \src "libresoc.v:0.0-0.0"
27189       case 5'00000
27190         assign { } { }
27191         assign $1\dec31_dec_sub0_cr_in[2:0] 3'000
27192       attribute \src "libresoc.v:0.0-0.0"
27193       case 5'00111
27194         assign { } { }
27195         assign $1\dec31_dec_sub0_cr_in[2:0] 3'000
27196       attribute \src "libresoc.v:0.0-0.0"
27197       case 5'00001
27198         assign { } { }
27199         assign $1\dec31_dec_sub0_cr_in[2:0] 3'000
27200       attribute \src "libresoc.v:0.0-0.0"
27201       case 5'00100
27202         assign { } { }
27203         assign $1\dec31_dec_sub0_cr_in[2:0] 3'011
27204       case
27205         assign $1\dec31_dec_sub0_cr_in[2:0] 3'000
27206     end
27207     sync always
27208       update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0]
27209   end
27210   attribute \src "libresoc.v:18900.3-18918.6"
27211   process $proc$libresoc.v:18900$430
27212     assign { } { }
27213     assign { } { }
27214     assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0]
27215     attribute \src "libresoc.v:18901.5-18901.29"
27216     switch \initial
27217       attribute \src "libresoc.v:18901.9-18901.17"
27218       case 1'1
27219       case
27220     end
27221     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27222     switch \opcode_switch
27223       attribute \src "libresoc.v:0.0-0.0"
27224       case 5'00000
27225         assign { } { }
27226         assign $1\dec31_dec_sub0_cr_out[2:0] 3'010
27227       attribute \src "libresoc.v:0.0-0.0"
27228       case 5'00111
27229         assign { } { }
27230         assign $1\dec31_dec_sub0_cr_out[2:0] 3'010
27231       attribute \src "libresoc.v:0.0-0.0"
27232       case 5'00001
27233         assign { } { }
27234         assign $1\dec31_dec_sub0_cr_out[2:0] 3'010
27235       attribute \src "libresoc.v:0.0-0.0"
27236       case 5'00100
27237         assign { } { }
27238         assign $1\dec31_dec_sub0_cr_out[2:0] 3'000
27239       case
27240         assign $1\dec31_dec_sub0_cr_out[2:0] 3'000
27241     end
27242     sync always
27243       update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0]
27244   end
27245   connect \opcode_switch \opcode_in [10:6]
27246 end
27247 attribute \src "libresoc.v:18924.1-20071.10"
27248 attribute \cells_not_processed 1
27249 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10"
27250 attribute \generator "nMigen"
27251 module \dec31_dec_sub10
27252   attribute \src "libresoc.v:19367.3-19403.6"
27253   wire width 8 $0\dec31_dec_sub10_asmcode[7:0]
27254   attribute \src "libresoc.v:19515.3-19551.6"
27255   wire $0\dec31_dec_sub10_br[0:0]
27256   attribute \src "libresoc.v:19996.3-20032.6"
27257   wire width 3 $0\dec31_dec_sub10_cr_in[2:0]
27258   attribute \src "libresoc.v:20033.3-20069.6"
27259   wire width 3 $0\dec31_dec_sub10_cr_out[2:0]
27260   attribute \src "libresoc.v:19330.3-19366.6"
27261   wire width 2 $0\dec31_dec_sub10_cry_in[1:0]
27262   attribute \src "libresoc.v:19478.3-19514.6"
27263   wire $0\dec31_dec_sub10_cry_out[0:0]
27264   attribute \src "libresoc.v:19811.3-19847.6"
27265   wire width 5 $0\dec31_dec_sub10_form[4:0]
27266   attribute \src "libresoc.v:19182.3-19218.6"
27267   wire width 12 $0\dec31_dec_sub10_function_unit[11:0]
27268   attribute \src "libresoc.v:19848.3-19884.6"
27269   wire width 3 $0\dec31_dec_sub10_in1_sel[2:0]
27270   attribute \src "libresoc.v:19885.3-19921.6"
27271   wire width 4 $0\dec31_dec_sub10_in2_sel[3:0]
27272   attribute \src "libresoc.v:19922.3-19958.6"
27273   wire width 2 $0\dec31_dec_sub10_in3_sel[1:0]
27274   attribute \src "libresoc.v:19589.3-19625.6"
27275   wire width 7 $0\dec31_dec_sub10_internal_op[6:0]
27276   attribute \src "libresoc.v:19404.3-19440.6"
27277   wire $0\dec31_dec_sub10_inv_a[0:0]
27278   attribute \src "libresoc.v:19441.3-19477.6"
27279   wire $0\dec31_dec_sub10_inv_out[0:0]
27280   attribute \src "libresoc.v:19663.3-19699.6"
27281   wire $0\dec31_dec_sub10_is_32b[0:0]
27282   attribute \src "libresoc.v:19219.3-19255.6"
27283   wire width 4 $0\dec31_dec_sub10_ldst_len[3:0]
27284   attribute \src "libresoc.v:19737.3-19773.6"
27285   wire $0\dec31_dec_sub10_lk[0:0]
27286   attribute \src "libresoc.v:19959.3-19995.6"
27287   wire width 2 $0\dec31_dec_sub10_out_sel[1:0]
27288   attribute \src "libresoc.v:19293.3-19329.6"
27289   wire width 2 $0\dec31_dec_sub10_rc_sel[1:0]
27290   attribute \src "libresoc.v:19626.3-19662.6"
27291   wire $0\dec31_dec_sub10_rsrv[0:0]
27292   attribute \src "libresoc.v:19774.3-19810.6"
27293   wire $0\dec31_dec_sub10_sgl_pipe[0:0]
27294   attribute \src "libresoc.v:19700.3-19736.6"
27295   wire $0\dec31_dec_sub10_sgn[0:0]
27296   attribute \src "libresoc.v:19552.3-19588.6"
27297   wire $0\dec31_dec_sub10_sgn_ext[0:0]
27298   attribute \src "libresoc.v:19256.3-19292.6"
27299   wire width 2 $0\dec31_dec_sub10_upd[1:0]
27300   attribute \src "libresoc.v:18925.7-18925.20"
27301   wire $0\initial[0:0]
27302   attribute \src "libresoc.v:19367.3-19403.6"
27303   wire width 8 $1\dec31_dec_sub10_asmcode[7:0]
27304   attribute \src "libresoc.v:19515.3-19551.6"
27305   wire $1\dec31_dec_sub10_br[0:0]
27306   attribute \src "libresoc.v:19996.3-20032.6"
27307   wire width 3 $1\dec31_dec_sub10_cr_in[2:0]
27308   attribute \src "libresoc.v:20033.3-20069.6"
27309   wire width 3 $1\dec31_dec_sub10_cr_out[2:0]
27310   attribute \src "libresoc.v:19330.3-19366.6"
27311   wire width 2 $1\dec31_dec_sub10_cry_in[1:0]
27312   attribute \src "libresoc.v:19478.3-19514.6"
27313   wire $1\dec31_dec_sub10_cry_out[0:0]
27314   attribute \src "libresoc.v:19811.3-19847.6"
27315   wire width 5 $1\dec31_dec_sub10_form[4:0]
27316   attribute \src "libresoc.v:19182.3-19218.6"
27317   wire width 12 $1\dec31_dec_sub10_function_unit[11:0]
27318   attribute \src "libresoc.v:19848.3-19884.6"
27319   wire width 3 $1\dec31_dec_sub10_in1_sel[2:0]
27320   attribute \src "libresoc.v:19885.3-19921.6"
27321   wire width 4 $1\dec31_dec_sub10_in2_sel[3:0]
27322   attribute \src "libresoc.v:19922.3-19958.6"
27323   wire width 2 $1\dec31_dec_sub10_in3_sel[1:0]
27324   attribute \src "libresoc.v:19589.3-19625.6"
27325   wire width 7 $1\dec31_dec_sub10_internal_op[6:0]
27326   attribute \src "libresoc.v:19404.3-19440.6"
27327   wire $1\dec31_dec_sub10_inv_a[0:0]
27328   attribute \src "libresoc.v:19441.3-19477.6"
27329   wire $1\dec31_dec_sub10_inv_out[0:0]
27330   attribute \src "libresoc.v:19663.3-19699.6"
27331   wire $1\dec31_dec_sub10_is_32b[0:0]
27332   attribute \src "libresoc.v:19219.3-19255.6"
27333   wire width 4 $1\dec31_dec_sub10_ldst_len[3:0]
27334   attribute \src "libresoc.v:19737.3-19773.6"
27335   wire $1\dec31_dec_sub10_lk[0:0]
27336   attribute \src "libresoc.v:19959.3-19995.6"
27337   wire width 2 $1\dec31_dec_sub10_out_sel[1:0]
27338   attribute \src "libresoc.v:19293.3-19329.6"
27339   wire width 2 $1\dec31_dec_sub10_rc_sel[1:0]
27340   attribute \src "libresoc.v:19626.3-19662.6"
27341   wire $1\dec31_dec_sub10_rsrv[0:0]
27342   attribute \src "libresoc.v:19774.3-19810.6"
27343   wire $1\dec31_dec_sub10_sgl_pipe[0:0]
27344   attribute \src "libresoc.v:19700.3-19736.6"
27345   wire $1\dec31_dec_sub10_sgn[0:0]
27346   attribute \src "libresoc.v:19552.3-19588.6"
27347   wire $1\dec31_dec_sub10_sgn_ext[0:0]
27348   attribute \src "libresoc.v:19256.3-19292.6"
27349   wire width 2 $1\dec31_dec_sub10_upd[1:0]
27350   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27351   wire width 8 output 4 \dec31_dec_sub10_asmcode
27352   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27353   wire output 18 \dec31_dec_sub10_br
27354   attribute \enum_base_type "CRInSel"
27355   attribute \enum_value_000 "NONE"
27356   attribute \enum_value_001 "CR0"
27357   attribute \enum_value_010 "BI"
27358   attribute \enum_value_011 "BFA"
27359   attribute \enum_value_100 "BA_BB"
27360   attribute \enum_value_101 "BC"
27361   attribute \enum_value_110 "WHOLE_REG"
27362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27363   wire width 3 output 9 \dec31_dec_sub10_cr_in
27364   attribute \enum_base_type "CROutSel"
27365   attribute \enum_value_000 "NONE"
27366   attribute \enum_value_001 "CR0"
27367   attribute \enum_value_010 "BF"
27368   attribute \enum_value_011 "BT"
27369   attribute \enum_value_100 "WHOLE_REG"
27370   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27371   wire width 3 output 10 \dec31_dec_sub10_cr_out
27372   attribute \enum_base_type "CryIn"
27373   attribute \enum_value_00 "ZERO"
27374   attribute \enum_value_01 "ONE"
27375   attribute \enum_value_10 "CA"
27376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27377   wire width 2 output 14 \dec31_dec_sub10_cry_in
27378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27379   wire output 17 \dec31_dec_sub10_cry_out
27380   attribute \enum_base_type "Form"
27381   attribute \enum_value_00000 "NONE"
27382   attribute \enum_value_00001 "I"
27383   attribute \enum_value_00010 "B"
27384   attribute \enum_value_00011 "SC"
27385   attribute \enum_value_00100 "D"
27386   attribute \enum_value_00101 "DS"
27387   attribute \enum_value_00110 "DQ"
27388   attribute \enum_value_00111 "DX"
27389   attribute \enum_value_01000 "X"
27390   attribute \enum_value_01001 "XL"
27391   attribute \enum_value_01010 "XFX"
27392   attribute \enum_value_01011 "XFL"
27393   attribute \enum_value_01100 "XX1"
27394   attribute \enum_value_01101 "XX2"
27395   attribute \enum_value_01110 "XX3"
27396   attribute \enum_value_01111 "XX4"
27397   attribute \enum_value_10000 "XS"
27398   attribute \enum_value_10001 "XO"
27399   attribute \enum_value_10010 "A"
27400   attribute \enum_value_10011 "M"
27401   attribute \enum_value_10100 "MD"
27402   attribute \enum_value_10101 "MDS"
27403   attribute \enum_value_10110 "VA"
27404   attribute \enum_value_10111 "VC"
27405   attribute \enum_value_11000 "VX"
27406   attribute \enum_value_11001 "EVX"
27407   attribute \enum_value_11010 "EVS"
27408   attribute \enum_value_11011 "Z22"
27409   attribute \enum_value_11100 "Z23"
27410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27411   wire width 5 output 3 \dec31_dec_sub10_form
27412   attribute \enum_base_type "Function"
27413   attribute \enum_value_000000000000 "NONE"
27414   attribute \enum_value_000000000010 "ALU"
27415   attribute \enum_value_000000000100 "LDST"
27416   attribute \enum_value_000000001000 "SHIFT_ROT"
27417   attribute \enum_value_000000010000 "LOGICAL"
27418   attribute \enum_value_000000100000 "BRANCH"
27419   attribute \enum_value_000001000000 "CR"
27420   attribute \enum_value_000010000000 "TRAP"
27421   attribute \enum_value_000100000000 "MUL"
27422   attribute \enum_value_001000000000 "DIV"
27423   attribute \enum_value_010000000000 "SPR"
27424   attribute \enum_value_100000000000 "MMU"
27425   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27426   wire width 12 output 1 \dec31_dec_sub10_function_unit
27427   attribute \enum_base_type "In1Sel"
27428   attribute \enum_value_000 "NONE"
27429   attribute \enum_value_001 "RA"
27430   attribute \enum_value_010 "RA_OR_ZERO"
27431   attribute \enum_value_011 "SPR"
27432   attribute \enum_value_100 "RS"
27433   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27434   wire width 3 output 5 \dec31_dec_sub10_in1_sel
27435   attribute \enum_base_type "In2Sel"
27436   attribute \enum_value_0000 "NONE"
27437   attribute \enum_value_0001 "RB"
27438   attribute \enum_value_0010 "CONST_UI"
27439   attribute \enum_value_0011 "CONST_SI"
27440   attribute \enum_value_0100 "CONST_UI_HI"
27441   attribute \enum_value_0101 "CONST_SI_HI"
27442   attribute \enum_value_0110 "CONST_LI"
27443   attribute \enum_value_0111 "CONST_BD"
27444   attribute \enum_value_1000 "CONST_DS"
27445   attribute \enum_value_1001 "CONST_M1"
27446   attribute \enum_value_1010 "CONST_SH"
27447   attribute \enum_value_1011 "CONST_SH32"
27448   attribute \enum_value_1100 "SPR"
27449   attribute \enum_value_1101 "RS"
27450   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27451   wire width 4 output 6 \dec31_dec_sub10_in2_sel
27452   attribute \enum_base_type "In3Sel"
27453   attribute \enum_value_00 "NONE"
27454   attribute \enum_value_01 "RS"
27455   attribute \enum_value_10 "RB"
27456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27457   wire width 2 output 7 \dec31_dec_sub10_in3_sel
27458   attribute \enum_base_type "MicrOp"
27459   attribute \enum_value_0000000 "OP_ILLEGAL"
27460   attribute \enum_value_0000001 "OP_NOP"
27461   attribute \enum_value_0000010 "OP_ADD"
27462   attribute \enum_value_0000011 "OP_ADDPCIS"
27463   attribute \enum_value_0000100 "OP_AND"
27464   attribute \enum_value_0000101 "OP_ATTN"
27465   attribute \enum_value_0000110 "OP_B"
27466   attribute \enum_value_0000111 "OP_BC"
27467   attribute \enum_value_0001000 "OP_BCREG"
27468   attribute \enum_value_0001001 "OP_BPERM"
27469   attribute \enum_value_0001010 "OP_CMP"
27470   attribute \enum_value_0001011 "OP_CMPB"
27471   attribute \enum_value_0001100 "OP_CMPEQB"
27472   attribute \enum_value_0001101 "OP_CMPRB"
27473   attribute \enum_value_0001110 "OP_CNTZ"
27474   attribute \enum_value_0001111 "OP_CRAND"
27475   attribute \enum_value_0010000 "OP_CRANDC"
27476   attribute \enum_value_0010001 "OP_CREQV"
27477   attribute \enum_value_0010010 "OP_CRNAND"
27478   attribute \enum_value_0010011 "OP_CRNOR"
27479   attribute \enum_value_0010100 "OP_CROR"
27480   attribute \enum_value_0010101 "OP_CRORC"
27481   attribute \enum_value_0010110 "OP_CRXOR"
27482   attribute \enum_value_0010111 "OP_DARN"
27483   attribute \enum_value_0011000 "OP_DCBF"
27484   attribute \enum_value_0011001 "OP_DCBST"
27485   attribute \enum_value_0011010 "OP_DCBT"
27486   attribute \enum_value_0011011 "OP_DCBTST"
27487   attribute \enum_value_0011100 "OP_DCBZ"
27488   attribute \enum_value_0011101 "OP_DIV"
27489   attribute \enum_value_0011110 "OP_DIVE"
27490   attribute \enum_value_0011111 "OP_EXTS"
27491   attribute \enum_value_0100000 "OP_EXTSWSLI"
27492   attribute \enum_value_0100001 "OP_ICBI"
27493   attribute \enum_value_0100010 "OP_ICBT"
27494   attribute \enum_value_0100011 "OP_ISEL"
27495   attribute \enum_value_0100100 "OP_ISYNC"
27496   attribute \enum_value_0100101 "OP_LOAD"
27497   attribute \enum_value_0100110 "OP_STORE"
27498   attribute \enum_value_0100111 "OP_MADDHD"
27499   attribute \enum_value_0101000 "OP_MADDHDU"
27500   attribute \enum_value_0101001 "OP_MADDLD"
27501   attribute \enum_value_0101010 "OP_MCRF"
27502   attribute \enum_value_0101011 "OP_MCRXR"
27503   attribute \enum_value_0101100 "OP_MCRXRX"
27504   attribute \enum_value_0101101 "OP_MFCR"
27505   attribute \enum_value_0101110 "OP_MFSPR"
27506   attribute \enum_value_0101111 "OP_MOD"
27507   attribute \enum_value_0110000 "OP_MTCRF"
27508   attribute \enum_value_0110001 "OP_MTSPR"
27509   attribute \enum_value_0110010 "OP_MUL_L64"
27510   attribute \enum_value_0110011 "OP_MUL_H64"
27511   attribute \enum_value_0110100 "OP_MUL_H32"
27512   attribute \enum_value_0110101 "OP_OR"
27513   attribute \enum_value_0110110 "OP_POPCNT"
27514   attribute \enum_value_0110111 "OP_PRTY"
27515   attribute \enum_value_0111000 "OP_RLC"
27516   attribute \enum_value_0111001 "OP_RLCL"
27517   attribute \enum_value_0111010 "OP_RLCR"
27518   attribute \enum_value_0111011 "OP_SETB"
27519   attribute \enum_value_0111100 "OP_SHL"
27520   attribute \enum_value_0111101 "OP_SHR"
27521   attribute \enum_value_0111110 "OP_SYNC"
27522   attribute \enum_value_0111111 "OP_TRAP"
27523   attribute \enum_value_1000011 "OP_XOR"
27524   attribute \enum_value_1000100 "OP_SIM_CONFIG"
27525   attribute \enum_value_1000101 "OP_CROP"
27526   attribute \enum_value_1000110 "OP_RFID"
27527   attribute \enum_value_1000111 "OP_MFMSR"
27528   attribute \enum_value_1001000 "OP_MTMSRD"
27529   attribute \enum_value_1001001 "OP_SC"
27530   attribute \enum_value_1001010 "OP_MTMSR"
27531   attribute \enum_value_1001011 "OP_TLBIE"
27532   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27533   wire width 7 output 2 \dec31_dec_sub10_internal_op
27534   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27535   wire output 15 \dec31_dec_sub10_inv_a
27536   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27537   wire output 16 \dec31_dec_sub10_inv_out
27538   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27539   wire output 21 \dec31_dec_sub10_is_32b
27540   attribute \enum_base_type "LdstLen"
27541   attribute \enum_value_0000 "NONE"
27542   attribute \enum_value_0001 "is1B"
27543   attribute \enum_value_0010 "is2B"
27544   attribute \enum_value_0100 "is4B"
27545   attribute \enum_value_1000 "is8B"
27546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27547   wire width 4 output 11 \dec31_dec_sub10_ldst_len
27548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27549   wire output 23 \dec31_dec_sub10_lk
27550   attribute \enum_base_type "OutSel"
27551   attribute \enum_value_00 "NONE"
27552   attribute \enum_value_01 "RT"
27553   attribute \enum_value_10 "RA"
27554   attribute \enum_value_11 "SPR"
27555   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27556   wire width 2 output 8 \dec31_dec_sub10_out_sel
27557   attribute \enum_base_type "RC"
27558   attribute \enum_value_00 "NONE"
27559   attribute \enum_value_01 "ONE"
27560   attribute \enum_value_10 "RC"
27561   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27562   wire width 2 output 13 \dec31_dec_sub10_rc_sel
27563   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27564   wire output 20 \dec31_dec_sub10_rsrv
27565   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27566   wire output 24 \dec31_dec_sub10_sgl_pipe
27567   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27568   wire output 22 \dec31_dec_sub10_sgn
27569   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
27570   wire output 19 \dec31_dec_sub10_sgn_ext
27571   attribute \enum_base_type "LDSTMode"
27572   attribute \enum_value_00 "NONE"
27573   attribute \enum_value_01 "update"
27574   attribute \enum_value_10 "cix"
27575   attribute \enum_value_11 "cx"
27576   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
27577   wire width 2 output 12 \dec31_dec_sub10_upd
27578   attribute \src "libresoc.v:18925.7-18925.15"
27579   wire \initial
27580   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
27581   wire width 32 input 25 \opcode_in
27582   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
27583   wire width 5 \opcode_switch
27584   attribute \src "libresoc.v:18925.7-18925.20"
27585   process $proc$libresoc.v:18925$456
27586     assign { } { }
27587     assign $0\initial[0:0] 1'0
27588     sync always
27589       update \initial $0\initial[0:0]
27590     sync init
27591   end
27592   attribute \src "libresoc.v:19182.3-19218.6"
27593   process $proc$libresoc.v:19182$432
27594     assign { } { }
27595     assign { } { }
27596     assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0]
27597     attribute \src "libresoc.v:19183.5-19183.29"
27598     switch \initial
27599       attribute \src "libresoc.v:19183.9-19183.17"
27600       case 1'1
27601       case
27602     end
27603     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27604     switch \opcode_switch
27605       attribute \src "libresoc.v:0.0-0.0"
27606       case 5'01000
27607         assign { } { }
27608         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27609       attribute \src "libresoc.v:0.0-0.0"
27610       case 5'11000
27611         assign { } { }
27612         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27613       attribute \src "libresoc.v:0.0-0.0"
27614       case 5'00000
27615         assign { } { }
27616         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27617       attribute \src "libresoc.v:0.0-0.0"
27618       case 5'10000
27619         assign { } { }
27620         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27621       attribute \src "libresoc.v:0.0-0.0"
27622       case 5'00100
27623         assign { } { }
27624         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27625       attribute \src "libresoc.v:0.0-0.0"
27626       case 5'10100
27627         assign { } { }
27628         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27629       attribute \src "libresoc.v:0.0-0.0"
27630       case 5'00111
27631         assign { } { }
27632         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27633       attribute \src "libresoc.v:0.0-0.0"
27634       case 5'10111
27635         assign { } { }
27636         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27637       attribute \src "libresoc.v:0.0-0.0"
27638       case 5'00110
27639         assign { } { }
27640         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27641       attribute \src "libresoc.v:0.0-0.0"
27642       case 5'10110
27643         assign { } { }
27644         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010
27645       case
27646         assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000
27647     end
27648     sync always
27649       update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0]
27650   end
27651   attribute \src "libresoc.v:19219.3-19255.6"
27652   process $proc$libresoc.v:19219$433
27653     assign { } { }
27654     assign { } { }
27655     assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0]
27656     attribute \src "libresoc.v:19220.5-19220.29"
27657     switch \initial
27658       attribute \src "libresoc.v:19220.9-19220.17"
27659       case 1'1
27660       case
27661     end
27662     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27663     switch \opcode_switch
27664       attribute \src "libresoc.v:0.0-0.0"
27665       case 5'01000
27666         assign { } { }
27667         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27668       attribute \src "libresoc.v:0.0-0.0"
27669       case 5'11000
27670         assign { } { }
27671         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27672       attribute \src "libresoc.v:0.0-0.0"
27673       case 5'00000
27674         assign { } { }
27675         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27676       attribute \src "libresoc.v:0.0-0.0"
27677       case 5'10000
27678         assign { } { }
27679         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27680       attribute \src "libresoc.v:0.0-0.0"
27681       case 5'00100
27682         assign { } { }
27683         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27684       attribute \src "libresoc.v:0.0-0.0"
27685       case 5'10100
27686         assign { } { }
27687         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27688       attribute \src "libresoc.v:0.0-0.0"
27689       case 5'00111
27690         assign { } { }
27691         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27692       attribute \src "libresoc.v:0.0-0.0"
27693       case 5'10111
27694         assign { } { }
27695         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27696       attribute \src "libresoc.v:0.0-0.0"
27697       case 5'00110
27698         assign { } { }
27699         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27700       attribute \src "libresoc.v:0.0-0.0"
27701       case 5'10110
27702         assign { } { }
27703         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27704       case
27705         assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000
27706     end
27707     sync always
27708       update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0]
27709   end
27710   attribute \src "libresoc.v:19256.3-19292.6"
27711   process $proc$libresoc.v:19256$434
27712     assign { } { }
27713     assign { } { }
27714     assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0]
27715     attribute \src "libresoc.v:19257.5-19257.29"
27716     switch \initial
27717       attribute \src "libresoc.v:19257.9-19257.17"
27718       case 1'1
27719       case
27720     end
27721     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27722     switch \opcode_switch
27723       attribute \src "libresoc.v:0.0-0.0"
27724       case 5'01000
27725         assign { } { }
27726         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27727       attribute \src "libresoc.v:0.0-0.0"
27728       case 5'11000
27729         assign { } { }
27730         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27731       attribute \src "libresoc.v:0.0-0.0"
27732       case 5'00000
27733         assign { } { }
27734         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27735       attribute \src "libresoc.v:0.0-0.0"
27736       case 5'10000
27737         assign { } { }
27738         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27739       attribute \src "libresoc.v:0.0-0.0"
27740       case 5'00100
27741         assign { } { }
27742         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27743       attribute \src "libresoc.v:0.0-0.0"
27744       case 5'10100
27745         assign { } { }
27746         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27747       attribute \src "libresoc.v:0.0-0.0"
27748       case 5'00111
27749         assign { } { }
27750         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27751       attribute \src "libresoc.v:0.0-0.0"
27752       case 5'10111
27753         assign { } { }
27754         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27755       attribute \src "libresoc.v:0.0-0.0"
27756       case 5'00110
27757         assign { } { }
27758         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27759       attribute \src "libresoc.v:0.0-0.0"
27760       case 5'10110
27761         assign { } { }
27762         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27763       case
27764         assign $1\dec31_dec_sub10_upd[1:0] 2'00
27765     end
27766     sync always
27767       update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0]
27768   end
27769   attribute \src "libresoc.v:19293.3-19329.6"
27770   process $proc$libresoc.v:19293$435
27771     assign { } { }
27772     assign { } { }
27773     assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0]
27774     attribute \src "libresoc.v:19294.5-19294.29"
27775     switch \initial
27776       attribute \src "libresoc.v:19294.9-19294.17"
27777       case 1'1
27778       case
27779     end
27780     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27781     switch \opcode_switch
27782       attribute \src "libresoc.v:0.0-0.0"
27783       case 5'01000
27784         assign { } { }
27785         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27786       attribute \src "libresoc.v:0.0-0.0"
27787       case 5'11000
27788         assign { } { }
27789         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27790       attribute \src "libresoc.v:0.0-0.0"
27791       case 5'00000
27792         assign { } { }
27793         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27794       attribute \src "libresoc.v:0.0-0.0"
27795       case 5'10000
27796         assign { } { }
27797         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27798       attribute \src "libresoc.v:0.0-0.0"
27799       case 5'00100
27800         assign { } { }
27801         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27802       attribute \src "libresoc.v:0.0-0.0"
27803       case 5'10100
27804         assign { } { }
27805         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27806       attribute \src "libresoc.v:0.0-0.0"
27807       case 5'00111
27808         assign { } { }
27809         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27810       attribute \src "libresoc.v:0.0-0.0"
27811       case 5'10111
27812         assign { } { }
27813         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27814       attribute \src "libresoc.v:0.0-0.0"
27815       case 5'00110
27816         assign { } { }
27817         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27818       attribute \src "libresoc.v:0.0-0.0"
27819       case 5'10110
27820         assign { } { }
27821         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10
27822       case
27823         assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00
27824     end
27825     sync always
27826       update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0]
27827   end
27828   attribute \src "libresoc.v:19330.3-19366.6"
27829   process $proc$libresoc.v:19330$436
27830     assign { } { }
27831     assign { } { }
27832     assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0]
27833     attribute \src "libresoc.v:19331.5-19331.29"
27834     switch \initial
27835       attribute \src "libresoc.v:19331.9-19331.17"
27836       case 1'1
27837       case
27838     end
27839     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27840     switch \opcode_switch
27841       attribute \src "libresoc.v:0.0-0.0"
27842       case 5'01000
27843         assign { } { }
27844         assign $1\dec31_dec_sub10_cry_in[1:0] 2'00
27845       attribute \src "libresoc.v:0.0-0.0"
27846       case 5'11000
27847         assign { } { }
27848         assign $1\dec31_dec_sub10_cry_in[1:0] 2'00
27849       attribute \src "libresoc.v:0.0-0.0"
27850       case 5'00000
27851         assign { } { }
27852         assign $1\dec31_dec_sub10_cry_in[1:0] 2'00
27853       attribute \src "libresoc.v:0.0-0.0"
27854       case 5'10000
27855         assign { } { }
27856         assign $1\dec31_dec_sub10_cry_in[1:0] 2'00
27857       attribute \src "libresoc.v:0.0-0.0"
27858       case 5'00100
27859         assign { } { }
27860         assign $1\dec31_dec_sub10_cry_in[1:0] 2'10
27861       attribute \src "libresoc.v:0.0-0.0"
27862       case 5'10100
27863         assign { } { }
27864         assign $1\dec31_dec_sub10_cry_in[1:0] 2'10
27865       attribute \src "libresoc.v:0.0-0.0"
27866       case 5'00111
27867         assign { } { }
27868         assign $1\dec31_dec_sub10_cry_in[1:0] 2'10
27869       attribute \src "libresoc.v:0.0-0.0"
27870       case 5'10111
27871         assign { } { }
27872         assign $1\dec31_dec_sub10_cry_in[1:0] 2'10
27873       attribute \src "libresoc.v:0.0-0.0"
27874       case 5'00110
27875         assign { } { }
27876         assign $1\dec31_dec_sub10_cry_in[1:0] 2'10
27877       attribute \src "libresoc.v:0.0-0.0"
27878       case 5'10110
27879         assign { } { }
27880         assign $1\dec31_dec_sub10_cry_in[1:0] 2'10
27881       case
27882         assign $1\dec31_dec_sub10_cry_in[1:0] 2'00
27883     end
27884     sync always
27885       update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0]
27886   end
27887   attribute \src "libresoc.v:19367.3-19403.6"
27888   process $proc$libresoc.v:19367$437
27889     assign { } { }
27890     assign { } { }
27891     assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0]
27892     attribute \src "libresoc.v:19368.5-19368.29"
27893     switch \initial
27894       attribute \src "libresoc.v:19368.9-19368.17"
27895       case 1'1
27896       case
27897     end
27898     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27899     switch \opcode_switch
27900       attribute \src "libresoc.v:0.0-0.0"
27901       case 5'01000
27902         assign { } { }
27903         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001
27904       attribute \src "libresoc.v:0.0-0.0"
27905       case 5'11000
27906         assign { } { }
27907         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100
27908       attribute \src "libresoc.v:0.0-0.0"
27909       case 5'00000
27910         assign { } { }
27911         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010
27912       attribute \src "libresoc.v:0.0-0.0"
27913       case 5'10000
27914         assign { } { }
27915         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011
27916       attribute \src "libresoc.v:0.0-0.0"
27917       case 5'00100
27918         assign { } { }
27919         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100
27920       attribute \src "libresoc.v:0.0-0.0"
27921       case 5'10100
27922         assign { } { }
27923         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101
27924       attribute \src "libresoc.v:0.0-0.0"
27925       case 5'00111
27926         assign { } { }
27927         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010
27928       attribute \src "libresoc.v:0.0-0.0"
27929       case 5'10111
27930         assign { } { }
27931         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011
27932       attribute \src "libresoc.v:0.0-0.0"
27933       case 5'00110
27934         assign { } { }
27935         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101
27936       attribute \src "libresoc.v:0.0-0.0"
27937       case 5'10110
27938         assign { } { }
27939         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110
27940       case
27941         assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000
27942     end
27943     sync always
27944       update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0]
27945   end
27946   attribute \src "libresoc.v:19404.3-19440.6"
27947   process $proc$libresoc.v:19404$438
27948     assign { } { }
27949     assign { } { }
27950     assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0]
27951     attribute \src "libresoc.v:19405.5-19405.29"
27952     switch \initial
27953       attribute \src "libresoc.v:19405.9-19405.17"
27954       case 1'1
27955       case
27956     end
27957     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
27958     switch \opcode_switch
27959       attribute \src "libresoc.v:0.0-0.0"
27960       case 5'01000
27961         assign { } { }
27962         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27963       attribute \src "libresoc.v:0.0-0.0"
27964       case 5'11000
27965         assign { } { }
27966         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27967       attribute \src "libresoc.v:0.0-0.0"
27968       case 5'00000
27969         assign { } { }
27970         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27971       attribute \src "libresoc.v:0.0-0.0"
27972       case 5'10000
27973         assign { } { }
27974         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27975       attribute \src "libresoc.v:0.0-0.0"
27976       case 5'00100
27977         assign { } { }
27978         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27979       attribute \src "libresoc.v:0.0-0.0"
27980       case 5'10100
27981         assign { } { }
27982         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27983       attribute \src "libresoc.v:0.0-0.0"
27984       case 5'00111
27985         assign { } { }
27986         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27987       attribute \src "libresoc.v:0.0-0.0"
27988       case 5'10111
27989         assign { } { }
27990         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27991       attribute \src "libresoc.v:0.0-0.0"
27992       case 5'00110
27993         assign { } { }
27994         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27995       attribute \src "libresoc.v:0.0-0.0"
27996       case 5'10110
27997         assign { } { }
27998         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
27999       case
28000         assign $1\dec31_dec_sub10_inv_a[0:0] 1'0
28001     end
28002     sync always
28003       update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0]
28004   end
28005   attribute \src "libresoc.v:19441.3-19477.6"
28006   process $proc$libresoc.v:19441$439
28007     assign { } { }
28008     assign { } { }
28009     assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0]
28010     attribute \src "libresoc.v:19442.5-19442.29"
28011     switch \initial
28012       attribute \src "libresoc.v:19442.9-19442.17"
28013       case 1'1
28014       case
28015     end
28016     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28017     switch \opcode_switch
28018       attribute \src "libresoc.v:0.0-0.0"
28019       case 5'01000
28020         assign { } { }
28021         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28022       attribute \src "libresoc.v:0.0-0.0"
28023       case 5'11000
28024         assign { } { }
28025         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28026       attribute \src "libresoc.v:0.0-0.0"
28027       case 5'00000
28028         assign { } { }
28029         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28030       attribute \src "libresoc.v:0.0-0.0"
28031       case 5'10000
28032         assign { } { }
28033         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28034       attribute \src "libresoc.v:0.0-0.0"
28035       case 5'00100
28036         assign { } { }
28037         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28038       attribute \src "libresoc.v:0.0-0.0"
28039       case 5'10100
28040         assign { } { }
28041         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28042       attribute \src "libresoc.v:0.0-0.0"
28043       case 5'00111
28044         assign { } { }
28045         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28046       attribute \src "libresoc.v:0.0-0.0"
28047       case 5'10111
28048         assign { } { }
28049         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28050       attribute \src "libresoc.v:0.0-0.0"
28051       case 5'00110
28052         assign { } { }
28053         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28054       attribute \src "libresoc.v:0.0-0.0"
28055       case 5'10110
28056         assign { } { }
28057         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28058       case
28059         assign $1\dec31_dec_sub10_inv_out[0:0] 1'0
28060     end
28061     sync always
28062       update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0]
28063   end
28064   attribute \src "libresoc.v:19478.3-19514.6"
28065   process $proc$libresoc.v:19478$440
28066     assign { } { }
28067     assign { } { }
28068     assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0]
28069     attribute \src "libresoc.v:19479.5-19479.29"
28070     switch \initial
28071       attribute \src "libresoc.v:19479.9-19479.17"
28072       case 1'1
28073       case
28074     end
28075     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28076     switch \opcode_switch
28077       attribute \src "libresoc.v:0.0-0.0"
28078       case 5'01000
28079         assign { } { }
28080         assign $1\dec31_dec_sub10_cry_out[0:0] 1'0
28081       attribute \src "libresoc.v:0.0-0.0"
28082       case 5'11000
28083         assign { } { }
28084         assign $1\dec31_dec_sub10_cry_out[0:0] 1'0
28085       attribute \src "libresoc.v:0.0-0.0"
28086       case 5'00000
28087         assign { } { }
28088         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28089       attribute \src "libresoc.v:0.0-0.0"
28090       case 5'10000
28091         assign { } { }
28092         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28093       attribute \src "libresoc.v:0.0-0.0"
28094       case 5'00100
28095         assign { } { }
28096         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28097       attribute \src "libresoc.v:0.0-0.0"
28098       case 5'10100
28099         assign { } { }
28100         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28101       attribute \src "libresoc.v:0.0-0.0"
28102       case 5'00111
28103         assign { } { }
28104         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28105       attribute \src "libresoc.v:0.0-0.0"
28106       case 5'10111
28107         assign { } { }
28108         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28109       attribute \src "libresoc.v:0.0-0.0"
28110       case 5'00110
28111         assign { } { }
28112         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28113       attribute \src "libresoc.v:0.0-0.0"
28114       case 5'10110
28115         assign { } { }
28116         assign $1\dec31_dec_sub10_cry_out[0:0] 1'1
28117       case
28118         assign $1\dec31_dec_sub10_cry_out[0:0] 1'0
28119     end
28120     sync always
28121       update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0]
28122   end
28123   attribute \src "libresoc.v:19515.3-19551.6"
28124   process $proc$libresoc.v:19515$441
28125     assign { } { }
28126     assign { } { }
28127     assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0]
28128     attribute \src "libresoc.v:19516.5-19516.29"
28129     switch \initial
28130       attribute \src "libresoc.v:19516.9-19516.17"
28131       case 1'1
28132       case
28133     end
28134     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28135     switch \opcode_switch
28136       attribute \src "libresoc.v:0.0-0.0"
28137       case 5'01000
28138         assign { } { }
28139         assign $1\dec31_dec_sub10_br[0:0] 1'0
28140       attribute \src "libresoc.v:0.0-0.0"
28141       case 5'11000
28142         assign { } { }
28143         assign $1\dec31_dec_sub10_br[0:0] 1'0
28144       attribute \src "libresoc.v:0.0-0.0"
28145       case 5'00000
28146         assign { } { }
28147         assign $1\dec31_dec_sub10_br[0:0] 1'0
28148       attribute \src "libresoc.v:0.0-0.0"
28149       case 5'10000
28150         assign { } { }
28151         assign $1\dec31_dec_sub10_br[0:0] 1'0
28152       attribute \src "libresoc.v:0.0-0.0"
28153       case 5'00100
28154         assign { } { }
28155         assign $1\dec31_dec_sub10_br[0:0] 1'0
28156       attribute \src "libresoc.v:0.0-0.0"
28157       case 5'10100
28158         assign { } { }
28159         assign $1\dec31_dec_sub10_br[0:0] 1'0
28160       attribute \src "libresoc.v:0.0-0.0"
28161       case 5'00111
28162         assign { } { }
28163         assign $1\dec31_dec_sub10_br[0:0] 1'0
28164       attribute \src "libresoc.v:0.0-0.0"
28165       case 5'10111
28166         assign { } { }
28167         assign $1\dec31_dec_sub10_br[0:0] 1'0
28168       attribute \src "libresoc.v:0.0-0.0"
28169       case 5'00110
28170         assign { } { }
28171         assign $1\dec31_dec_sub10_br[0:0] 1'0
28172       attribute \src "libresoc.v:0.0-0.0"
28173       case 5'10110
28174         assign { } { }
28175         assign $1\dec31_dec_sub10_br[0:0] 1'0
28176       case
28177         assign $1\dec31_dec_sub10_br[0:0] 1'0
28178     end
28179     sync always
28180       update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0]
28181   end
28182   attribute \src "libresoc.v:19552.3-19588.6"
28183   process $proc$libresoc.v:19552$442
28184     assign { } { }
28185     assign { } { }
28186     assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0]
28187     attribute \src "libresoc.v:19553.5-19553.29"
28188     switch \initial
28189       attribute \src "libresoc.v:19553.9-19553.17"
28190       case 1'1
28191       case
28192     end
28193     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28194     switch \opcode_switch
28195       attribute \src "libresoc.v:0.0-0.0"
28196       case 5'01000
28197         assign { } { }
28198         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28199       attribute \src "libresoc.v:0.0-0.0"
28200       case 5'11000
28201         assign { } { }
28202         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28203       attribute \src "libresoc.v:0.0-0.0"
28204       case 5'00000
28205         assign { } { }
28206         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28207       attribute \src "libresoc.v:0.0-0.0"
28208       case 5'10000
28209         assign { } { }
28210         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28211       attribute \src "libresoc.v:0.0-0.0"
28212       case 5'00100
28213         assign { } { }
28214         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28215       attribute \src "libresoc.v:0.0-0.0"
28216       case 5'10100
28217         assign { } { }
28218         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28219       attribute \src "libresoc.v:0.0-0.0"
28220       case 5'00111
28221         assign { } { }
28222         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28223       attribute \src "libresoc.v:0.0-0.0"
28224       case 5'10111
28225         assign { } { }
28226         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28227       attribute \src "libresoc.v:0.0-0.0"
28228       case 5'00110
28229         assign { } { }
28230         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28231       attribute \src "libresoc.v:0.0-0.0"
28232       case 5'10110
28233         assign { } { }
28234         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28235       case
28236         assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0
28237     end
28238     sync always
28239       update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0]
28240   end
28241   attribute \src "libresoc.v:19589.3-19625.6"
28242   process $proc$libresoc.v:19589$443
28243     assign { } { }
28244     assign { } { }
28245     assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0]
28246     attribute \src "libresoc.v:19590.5-19590.29"
28247     switch \initial
28248       attribute \src "libresoc.v:19590.9-19590.17"
28249       case 1'1
28250       case
28251     end
28252     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28253     switch \opcode_switch
28254       attribute \src "libresoc.v:0.0-0.0"
28255       case 5'01000
28256         assign { } { }
28257         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28258       attribute \src "libresoc.v:0.0-0.0"
28259       case 5'11000
28260         assign { } { }
28261         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28262       attribute \src "libresoc.v:0.0-0.0"
28263       case 5'00000
28264         assign { } { }
28265         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28266       attribute \src "libresoc.v:0.0-0.0"
28267       case 5'10000
28268         assign { } { }
28269         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28270       attribute \src "libresoc.v:0.0-0.0"
28271       case 5'00100
28272         assign { } { }
28273         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28274       attribute \src "libresoc.v:0.0-0.0"
28275       case 5'10100
28276         assign { } { }
28277         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28278       attribute \src "libresoc.v:0.0-0.0"
28279       case 5'00111
28280         assign { } { }
28281         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28282       attribute \src "libresoc.v:0.0-0.0"
28283       case 5'10111
28284         assign { } { }
28285         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28286       attribute \src "libresoc.v:0.0-0.0"
28287       case 5'00110
28288         assign { } { }
28289         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28290       attribute \src "libresoc.v:0.0-0.0"
28291       case 5'10110
28292         assign { } { }
28293         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010
28294       case
28295         assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000
28296     end
28297     sync always
28298       update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0]
28299   end
28300   attribute \src "libresoc.v:19626.3-19662.6"
28301   process $proc$libresoc.v:19626$444
28302     assign { } { }
28303     assign { } { }
28304     assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0]
28305     attribute \src "libresoc.v:19627.5-19627.29"
28306     switch \initial
28307       attribute \src "libresoc.v:19627.9-19627.17"
28308       case 1'1
28309       case
28310     end
28311     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28312     switch \opcode_switch
28313       attribute \src "libresoc.v:0.0-0.0"
28314       case 5'01000
28315         assign { } { }
28316         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28317       attribute \src "libresoc.v:0.0-0.0"
28318       case 5'11000
28319         assign { } { }
28320         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28321       attribute \src "libresoc.v:0.0-0.0"
28322       case 5'00000
28323         assign { } { }
28324         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28325       attribute \src "libresoc.v:0.0-0.0"
28326       case 5'10000
28327         assign { } { }
28328         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28329       attribute \src "libresoc.v:0.0-0.0"
28330       case 5'00100
28331         assign { } { }
28332         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28333       attribute \src "libresoc.v:0.0-0.0"
28334       case 5'10100
28335         assign { } { }
28336         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28337       attribute \src "libresoc.v:0.0-0.0"
28338       case 5'00111
28339         assign { } { }
28340         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28341       attribute \src "libresoc.v:0.0-0.0"
28342       case 5'10111
28343         assign { } { }
28344         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28345       attribute \src "libresoc.v:0.0-0.0"
28346       case 5'00110
28347         assign { } { }
28348         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28349       attribute \src "libresoc.v:0.0-0.0"
28350       case 5'10110
28351         assign { } { }
28352         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28353       case
28354         assign $1\dec31_dec_sub10_rsrv[0:0] 1'0
28355     end
28356     sync always
28357       update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0]
28358   end
28359   attribute \src "libresoc.v:19663.3-19699.6"
28360   process $proc$libresoc.v:19663$445
28361     assign { } { }
28362     assign { } { }
28363     assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0]
28364     attribute \src "libresoc.v:19664.5-19664.29"
28365     switch \initial
28366       attribute \src "libresoc.v:19664.9-19664.17"
28367       case 1'1
28368       case
28369     end
28370     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28371     switch \opcode_switch
28372       attribute \src "libresoc.v:0.0-0.0"
28373       case 5'01000
28374         assign { } { }
28375         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28376       attribute \src "libresoc.v:0.0-0.0"
28377       case 5'11000
28378         assign { } { }
28379         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28380       attribute \src "libresoc.v:0.0-0.0"
28381       case 5'00000
28382         assign { } { }
28383         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28384       attribute \src "libresoc.v:0.0-0.0"
28385       case 5'10000
28386         assign { } { }
28387         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28388       attribute \src "libresoc.v:0.0-0.0"
28389       case 5'00100
28390         assign { } { }
28391         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28392       attribute \src "libresoc.v:0.0-0.0"
28393       case 5'10100
28394         assign { } { }
28395         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28396       attribute \src "libresoc.v:0.0-0.0"
28397       case 5'00111
28398         assign { } { }
28399         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28400       attribute \src "libresoc.v:0.0-0.0"
28401       case 5'10111
28402         assign { } { }
28403         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28404       attribute \src "libresoc.v:0.0-0.0"
28405       case 5'00110
28406         assign { } { }
28407         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28408       attribute \src "libresoc.v:0.0-0.0"
28409       case 5'10110
28410         assign { } { }
28411         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28412       case
28413         assign $1\dec31_dec_sub10_is_32b[0:0] 1'0
28414     end
28415     sync always
28416       update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0]
28417   end
28418   attribute \src "libresoc.v:19700.3-19736.6"
28419   process $proc$libresoc.v:19700$446
28420     assign { } { }
28421     assign { } { }
28422     assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0]
28423     attribute \src "libresoc.v:19701.5-19701.29"
28424     switch \initial
28425       attribute \src "libresoc.v:19701.9-19701.17"
28426       case 1'1
28427       case
28428     end
28429     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28430     switch \opcode_switch
28431       attribute \src "libresoc.v:0.0-0.0"
28432       case 5'01000
28433         assign { } { }
28434         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28435       attribute \src "libresoc.v:0.0-0.0"
28436       case 5'11000
28437         assign { } { }
28438         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28439       attribute \src "libresoc.v:0.0-0.0"
28440       case 5'00000
28441         assign { } { }
28442         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28443       attribute \src "libresoc.v:0.0-0.0"
28444       case 5'10000
28445         assign { } { }
28446         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28447       attribute \src "libresoc.v:0.0-0.0"
28448       case 5'00100
28449         assign { } { }
28450         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28451       attribute \src "libresoc.v:0.0-0.0"
28452       case 5'10100
28453         assign { } { }
28454         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28455       attribute \src "libresoc.v:0.0-0.0"
28456       case 5'00111
28457         assign { } { }
28458         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28459       attribute \src "libresoc.v:0.0-0.0"
28460       case 5'10111
28461         assign { } { }
28462         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28463       attribute \src "libresoc.v:0.0-0.0"
28464       case 5'00110
28465         assign { } { }
28466         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28467       attribute \src "libresoc.v:0.0-0.0"
28468       case 5'10110
28469         assign { } { }
28470         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28471       case
28472         assign $1\dec31_dec_sub10_sgn[0:0] 1'0
28473     end
28474     sync always
28475       update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0]
28476   end
28477   attribute \src "libresoc.v:19737.3-19773.6"
28478   process $proc$libresoc.v:19737$447
28479     assign { } { }
28480     assign { } { }
28481     assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0]
28482     attribute \src "libresoc.v:19738.5-19738.29"
28483     switch \initial
28484       attribute \src "libresoc.v:19738.9-19738.17"
28485       case 1'1
28486       case
28487     end
28488     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28489     switch \opcode_switch
28490       attribute \src "libresoc.v:0.0-0.0"
28491       case 5'01000
28492         assign { } { }
28493         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28494       attribute \src "libresoc.v:0.0-0.0"
28495       case 5'11000
28496         assign { } { }
28497         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28498       attribute \src "libresoc.v:0.0-0.0"
28499       case 5'00000
28500         assign { } { }
28501         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28502       attribute \src "libresoc.v:0.0-0.0"
28503       case 5'10000
28504         assign { } { }
28505         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28506       attribute \src "libresoc.v:0.0-0.0"
28507       case 5'00100
28508         assign { } { }
28509         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28510       attribute \src "libresoc.v:0.0-0.0"
28511       case 5'10100
28512         assign { } { }
28513         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28514       attribute \src "libresoc.v:0.0-0.0"
28515       case 5'00111
28516         assign { } { }
28517         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28518       attribute \src "libresoc.v:0.0-0.0"
28519       case 5'10111
28520         assign { } { }
28521         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28522       attribute \src "libresoc.v:0.0-0.0"
28523       case 5'00110
28524         assign { } { }
28525         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28526       attribute \src "libresoc.v:0.0-0.0"
28527       case 5'10110
28528         assign { } { }
28529         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28530       case
28531         assign $1\dec31_dec_sub10_lk[0:0] 1'0
28532     end
28533     sync always
28534       update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0]
28535   end
28536   attribute \src "libresoc.v:19774.3-19810.6"
28537   process $proc$libresoc.v:19774$448
28538     assign { } { }
28539     assign { } { }
28540     assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0]
28541     attribute \src "libresoc.v:19775.5-19775.29"
28542     switch \initial
28543       attribute \src "libresoc.v:19775.9-19775.17"
28544       case 1'1
28545       case
28546     end
28547     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28548     switch \opcode_switch
28549       attribute \src "libresoc.v:0.0-0.0"
28550       case 5'01000
28551         assign { } { }
28552         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28553       attribute \src "libresoc.v:0.0-0.0"
28554       case 5'11000
28555         assign { } { }
28556         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28557       attribute \src "libresoc.v:0.0-0.0"
28558       case 5'00000
28559         assign { } { }
28560         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28561       attribute \src "libresoc.v:0.0-0.0"
28562       case 5'10000
28563         assign { } { }
28564         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28565       attribute \src "libresoc.v:0.0-0.0"
28566       case 5'00100
28567         assign { } { }
28568         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28569       attribute \src "libresoc.v:0.0-0.0"
28570       case 5'10100
28571         assign { } { }
28572         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28573       attribute \src "libresoc.v:0.0-0.0"
28574       case 5'00111
28575         assign { } { }
28576         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28577       attribute \src "libresoc.v:0.0-0.0"
28578       case 5'10111
28579         assign { } { }
28580         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28581       attribute \src "libresoc.v:0.0-0.0"
28582       case 5'00110
28583         assign { } { }
28584         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28585       attribute \src "libresoc.v:0.0-0.0"
28586       case 5'10110
28587         assign { } { }
28588         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28589       case
28590         assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0
28591     end
28592     sync always
28593       update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0]
28594   end
28595   attribute \src "libresoc.v:19811.3-19847.6"
28596   process $proc$libresoc.v:19811$449
28597     assign { } { }
28598     assign { } { }
28599     assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0]
28600     attribute \src "libresoc.v:19812.5-19812.29"
28601     switch \initial
28602       attribute \src "libresoc.v:19812.9-19812.17"
28603       case 1'1
28604       case
28605     end
28606     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28607     switch \opcode_switch
28608       attribute \src "libresoc.v:0.0-0.0"
28609       case 5'01000
28610         assign { } { }
28611         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28612       attribute \src "libresoc.v:0.0-0.0"
28613       case 5'11000
28614         assign { } { }
28615         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28616       attribute \src "libresoc.v:0.0-0.0"
28617       case 5'00000
28618         assign { } { }
28619         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28620       attribute \src "libresoc.v:0.0-0.0"
28621       case 5'10000
28622         assign { } { }
28623         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28624       attribute \src "libresoc.v:0.0-0.0"
28625       case 5'00100
28626         assign { } { }
28627         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28628       attribute \src "libresoc.v:0.0-0.0"
28629       case 5'10100
28630         assign { } { }
28631         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28632       attribute \src "libresoc.v:0.0-0.0"
28633       case 5'00111
28634         assign { } { }
28635         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28636       attribute \src "libresoc.v:0.0-0.0"
28637       case 5'10111
28638         assign { } { }
28639         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28640       attribute \src "libresoc.v:0.0-0.0"
28641       case 5'00110
28642         assign { } { }
28643         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28644       attribute \src "libresoc.v:0.0-0.0"
28645       case 5'10110
28646         assign { } { }
28647         assign $1\dec31_dec_sub10_form[4:0] 5'10001
28648       case
28649         assign $1\dec31_dec_sub10_form[4:0] 5'00000
28650     end
28651     sync always
28652       update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0]
28653   end
28654   attribute \src "libresoc.v:19848.3-19884.6"
28655   process $proc$libresoc.v:19848$450
28656     assign { } { }
28657     assign { } { }
28658     assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0]
28659     attribute \src "libresoc.v:19849.5-19849.29"
28660     switch \initial
28661       attribute \src "libresoc.v:19849.9-19849.17"
28662       case 1'1
28663       case
28664     end
28665     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28666     switch \opcode_switch
28667       attribute \src "libresoc.v:0.0-0.0"
28668       case 5'01000
28669         assign { } { }
28670         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28671       attribute \src "libresoc.v:0.0-0.0"
28672       case 5'11000
28673         assign { } { }
28674         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28675       attribute \src "libresoc.v:0.0-0.0"
28676       case 5'00000
28677         assign { } { }
28678         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28679       attribute \src "libresoc.v:0.0-0.0"
28680       case 5'10000
28681         assign { } { }
28682         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28683       attribute \src "libresoc.v:0.0-0.0"
28684       case 5'00100
28685         assign { } { }
28686         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28687       attribute \src "libresoc.v:0.0-0.0"
28688       case 5'10100
28689         assign { } { }
28690         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28691       attribute \src "libresoc.v:0.0-0.0"
28692       case 5'00111
28693         assign { } { }
28694         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28695       attribute \src "libresoc.v:0.0-0.0"
28696       case 5'10111
28697         assign { } { }
28698         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28699       attribute \src "libresoc.v:0.0-0.0"
28700       case 5'00110
28701         assign { } { }
28702         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28703       attribute \src "libresoc.v:0.0-0.0"
28704       case 5'10110
28705         assign { } { }
28706         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001
28707       case
28708         assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000
28709     end
28710     sync always
28711       update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0]
28712   end
28713   attribute \src "libresoc.v:19885.3-19921.6"
28714   process $proc$libresoc.v:19885$451
28715     assign { } { }
28716     assign { } { }
28717     assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0]
28718     attribute \src "libresoc.v:19886.5-19886.29"
28719     switch \initial
28720       attribute \src "libresoc.v:19886.9-19886.17"
28721       case 1'1
28722       case
28723     end
28724     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28725     switch \opcode_switch
28726       attribute \src "libresoc.v:0.0-0.0"
28727       case 5'01000
28728         assign { } { }
28729         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001
28730       attribute \src "libresoc.v:0.0-0.0"
28731       case 5'11000
28732         assign { } { }
28733         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001
28734       attribute \src "libresoc.v:0.0-0.0"
28735       case 5'00000
28736         assign { } { }
28737         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001
28738       attribute \src "libresoc.v:0.0-0.0"
28739       case 5'10000
28740         assign { } { }
28741         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001
28742       attribute \src "libresoc.v:0.0-0.0"
28743       case 5'00100
28744         assign { } { }
28745         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001
28746       attribute \src "libresoc.v:0.0-0.0"
28747       case 5'10100
28748         assign { } { }
28749         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001
28750       attribute \src "libresoc.v:0.0-0.0"
28751       case 5'00111
28752         assign { } { }
28753         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001
28754       attribute \src "libresoc.v:0.0-0.0"
28755       case 5'10111
28756         assign { } { }
28757         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001
28758       attribute \src "libresoc.v:0.0-0.0"
28759       case 5'00110
28760         assign { } { }
28761         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000
28762       attribute \src "libresoc.v:0.0-0.0"
28763       case 5'10110
28764         assign { } { }
28765         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000
28766       case
28767         assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000
28768     end
28769     sync always
28770       update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0]
28771   end
28772   attribute \src "libresoc.v:19922.3-19958.6"
28773   process $proc$libresoc.v:19922$452
28774     assign { } { }
28775     assign { } { }
28776     assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0]
28777     attribute \src "libresoc.v:19923.5-19923.29"
28778     switch \initial
28779       attribute \src "libresoc.v:19923.9-19923.17"
28780       case 1'1
28781       case
28782     end
28783     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28784     switch \opcode_switch
28785       attribute \src "libresoc.v:0.0-0.0"
28786       case 5'01000
28787         assign { } { }
28788         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28789       attribute \src "libresoc.v:0.0-0.0"
28790       case 5'11000
28791         assign { } { }
28792         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28793       attribute \src "libresoc.v:0.0-0.0"
28794       case 5'00000
28795         assign { } { }
28796         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28797       attribute \src "libresoc.v:0.0-0.0"
28798       case 5'10000
28799         assign { } { }
28800         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28801       attribute \src "libresoc.v:0.0-0.0"
28802       case 5'00100
28803         assign { } { }
28804         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28805       attribute \src "libresoc.v:0.0-0.0"
28806       case 5'10100
28807         assign { } { }
28808         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28809       attribute \src "libresoc.v:0.0-0.0"
28810       case 5'00111
28811         assign { } { }
28812         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28813       attribute \src "libresoc.v:0.0-0.0"
28814       case 5'10111
28815         assign { } { }
28816         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28817       attribute \src "libresoc.v:0.0-0.0"
28818       case 5'00110
28819         assign { } { }
28820         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28821       attribute \src "libresoc.v:0.0-0.0"
28822       case 5'10110
28823         assign { } { }
28824         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28825       case
28826         assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00
28827     end
28828     sync always
28829       update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0]
28830   end
28831   attribute \src "libresoc.v:19959.3-19995.6"
28832   process $proc$libresoc.v:19959$453
28833     assign { } { }
28834     assign { } { }
28835     assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0]
28836     attribute \src "libresoc.v:19960.5-19960.29"
28837     switch \initial
28838       attribute \src "libresoc.v:19960.9-19960.17"
28839       case 1'1
28840       case
28841     end
28842     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28843     switch \opcode_switch
28844       attribute \src "libresoc.v:0.0-0.0"
28845       case 5'01000
28846         assign { } { }
28847         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28848       attribute \src "libresoc.v:0.0-0.0"
28849       case 5'11000
28850         assign { } { }
28851         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28852       attribute \src "libresoc.v:0.0-0.0"
28853       case 5'00000
28854         assign { } { }
28855         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28856       attribute \src "libresoc.v:0.0-0.0"
28857       case 5'10000
28858         assign { } { }
28859         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28860       attribute \src "libresoc.v:0.0-0.0"
28861       case 5'00100
28862         assign { } { }
28863         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28864       attribute \src "libresoc.v:0.0-0.0"
28865       case 5'10100
28866         assign { } { }
28867         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28868       attribute \src "libresoc.v:0.0-0.0"
28869       case 5'00111
28870         assign { } { }
28871         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28872       attribute \src "libresoc.v:0.0-0.0"
28873       case 5'10111
28874         assign { } { }
28875         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28876       attribute \src "libresoc.v:0.0-0.0"
28877       case 5'00110
28878         assign { } { }
28879         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28880       attribute \src "libresoc.v:0.0-0.0"
28881       case 5'10110
28882         assign { } { }
28883         assign $1\dec31_dec_sub10_out_sel[1:0] 2'01
28884       case
28885         assign $1\dec31_dec_sub10_out_sel[1:0] 2'00
28886     end
28887     sync always
28888       update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0]
28889   end
28890   attribute \src "libresoc.v:19996.3-20032.6"
28891   process $proc$libresoc.v:19996$454
28892     assign { } { }
28893     assign { } { }
28894     assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0]
28895     attribute \src "libresoc.v:19997.5-19997.29"
28896     switch \initial
28897       attribute \src "libresoc.v:19997.9-19997.17"
28898       case 1'1
28899       case
28900     end
28901     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28902     switch \opcode_switch
28903       attribute \src "libresoc.v:0.0-0.0"
28904       case 5'01000
28905         assign { } { }
28906         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28907       attribute \src "libresoc.v:0.0-0.0"
28908       case 5'11000
28909         assign { } { }
28910         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28911       attribute \src "libresoc.v:0.0-0.0"
28912       case 5'00000
28913         assign { } { }
28914         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28915       attribute \src "libresoc.v:0.0-0.0"
28916       case 5'10000
28917         assign { } { }
28918         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28919       attribute \src "libresoc.v:0.0-0.0"
28920       case 5'00100
28921         assign { } { }
28922         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28923       attribute \src "libresoc.v:0.0-0.0"
28924       case 5'10100
28925         assign { } { }
28926         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28927       attribute \src "libresoc.v:0.0-0.0"
28928       case 5'00111
28929         assign { } { }
28930         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28931       attribute \src "libresoc.v:0.0-0.0"
28932       case 5'10111
28933         assign { } { }
28934         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28935       attribute \src "libresoc.v:0.0-0.0"
28936       case 5'00110
28937         assign { } { }
28938         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28939       attribute \src "libresoc.v:0.0-0.0"
28940       case 5'10110
28941         assign { } { }
28942         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28943       case
28944         assign $1\dec31_dec_sub10_cr_in[2:0] 3'000
28945     end
28946     sync always
28947       update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0]
28948   end
28949   attribute \src "libresoc.v:20033.3-20069.6"
28950   process $proc$libresoc.v:20033$455
28951     assign { } { }
28952     assign { } { }
28953     assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0]
28954     attribute \src "libresoc.v:20034.5-20034.29"
28955     switch \initial
28956       attribute \src "libresoc.v:20034.9-20034.17"
28957       case 1'1
28958       case
28959     end
28960     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
28961     switch \opcode_switch
28962       attribute \src "libresoc.v:0.0-0.0"
28963       case 5'01000
28964         assign { } { }
28965         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28966       attribute \src "libresoc.v:0.0-0.0"
28967       case 5'11000
28968         assign { } { }
28969         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28970       attribute \src "libresoc.v:0.0-0.0"
28971       case 5'00000
28972         assign { } { }
28973         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28974       attribute \src "libresoc.v:0.0-0.0"
28975       case 5'10000
28976         assign { } { }
28977         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28978       attribute \src "libresoc.v:0.0-0.0"
28979       case 5'00100
28980         assign { } { }
28981         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28982       attribute \src "libresoc.v:0.0-0.0"
28983       case 5'10100
28984         assign { } { }
28985         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28986       attribute \src "libresoc.v:0.0-0.0"
28987       case 5'00111
28988         assign { } { }
28989         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28990       attribute \src "libresoc.v:0.0-0.0"
28991       case 5'10111
28992         assign { } { }
28993         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28994       attribute \src "libresoc.v:0.0-0.0"
28995       case 5'00110
28996         assign { } { }
28997         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
28998       attribute \src "libresoc.v:0.0-0.0"
28999       case 5'10110
29000         assign { } { }
29001         assign $1\dec31_dec_sub10_cr_out[2:0] 3'001
29002       case
29003         assign $1\dec31_dec_sub10_cr_out[2:0] 3'000
29004     end
29005     sync always
29006       update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0]
29007   end
29008   connect \opcode_switch \opcode_in [10:6]
29009 end
29010 attribute \src "libresoc.v:20075.1-21654.10"
29011 attribute \cells_not_processed 1
29012 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11"
29013 attribute \generator "nMigen"
29014 module \dec31_dec_sub11
29015   attribute \src "libresoc.v:20608.3-20662.6"
29016   wire width 8 $0\dec31_dec_sub11_asmcode[7:0]
29017   attribute \src "libresoc.v:20828.3-20882.6"
29018   wire $0\dec31_dec_sub11_br[0:0]
29019   attribute \src "libresoc.v:21543.3-21597.6"
29020   wire width 3 $0\dec31_dec_sub11_cr_in[2:0]
29021   attribute \src "libresoc.v:21598.3-21652.6"
29022   wire width 3 $0\dec31_dec_sub11_cr_out[2:0]
29023   attribute \src "libresoc.v:20553.3-20607.6"
29024   wire width 2 $0\dec31_dec_sub11_cry_in[1:0]
29025   attribute \src "libresoc.v:20773.3-20827.6"
29026   wire $0\dec31_dec_sub11_cry_out[0:0]
29027   attribute \src "libresoc.v:21268.3-21322.6"
29028   wire width 5 $0\dec31_dec_sub11_form[4:0]
29029   attribute \src "libresoc.v:20333.3-20387.6"
29030   wire width 12 $0\dec31_dec_sub11_function_unit[11:0]
29031   attribute \src "libresoc.v:21323.3-21377.6"
29032   wire width 3 $0\dec31_dec_sub11_in1_sel[2:0]
29033   attribute \src "libresoc.v:21378.3-21432.6"
29034   wire width 4 $0\dec31_dec_sub11_in2_sel[3:0]
29035   attribute \src "libresoc.v:21433.3-21487.6"
29036   wire width 2 $0\dec31_dec_sub11_in3_sel[1:0]
29037   attribute \src "libresoc.v:20938.3-20992.6"
29038   wire width 7 $0\dec31_dec_sub11_internal_op[6:0]
29039   attribute \src "libresoc.v:20663.3-20717.6"
29040   wire $0\dec31_dec_sub11_inv_a[0:0]
29041   attribute \src "libresoc.v:20718.3-20772.6"
29042   wire $0\dec31_dec_sub11_inv_out[0:0]
29043   attribute \src "libresoc.v:21048.3-21102.6"
29044   wire $0\dec31_dec_sub11_is_32b[0:0]
29045   attribute \src "libresoc.v:20388.3-20442.6"
29046   wire width 4 $0\dec31_dec_sub11_ldst_len[3:0]
29047   attribute \src "libresoc.v:21158.3-21212.6"
29048   wire $0\dec31_dec_sub11_lk[0:0]
29049   attribute \src "libresoc.v:21488.3-21542.6"
29050   wire width 2 $0\dec31_dec_sub11_out_sel[1:0]
29051   attribute \src "libresoc.v:20498.3-20552.6"
29052   wire width 2 $0\dec31_dec_sub11_rc_sel[1:0]
29053   attribute \src "libresoc.v:20993.3-21047.6"
29054   wire $0\dec31_dec_sub11_rsrv[0:0]
29055   attribute \src "libresoc.v:21213.3-21267.6"
29056   wire $0\dec31_dec_sub11_sgl_pipe[0:0]
29057   attribute \src "libresoc.v:21103.3-21157.6"
29058   wire $0\dec31_dec_sub11_sgn[0:0]
29059   attribute \src "libresoc.v:20883.3-20937.6"
29060   wire $0\dec31_dec_sub11_sgn_ext[0:0]
29061   attribute \src "libresoc.v:20443.3-20497.6"
29062   wire width 2 $0\dec31_dec_sub11_upd[1:0]
29063   attribute \src "libresoc.v:20076.7-20076.20"
29064   wire $0\initial[0:0]
29065   attribute \src "libresoc.v:20608.3-20662.6"
29066   wire width 8 $1\dec31_dec_sub11_asmcode[7:0]
29067   attribute \src "libresoc.v:20828.3-20882.6"
29068   wire $1\dec31_dec_sub11_br[0:0]
29069   attribute \src "libresoc.v:21543.3-21597.6"
29070   wire width 3 $1\dec31_dec_sub11_cr_in[2:0]
29071   attribute \src "libresoc.v:21598.3-21652.6"
29072   wire width 3 $1\dec31_dec_sub11_cr_out[2:0]
29073   attribute \src "libresoc.v:20553.3-20607.6"
29074   wire width 2 $1\dec31_dec_sub11_cry_in[1:0]
29075   attribute \src "libresoc.v:20773.3-20827.6"
29076   wire $1\dec31_dec_sub11_cry_out[0:0]
29077   attribute \src "libresoc.v:21268.3-21322.6"
29078   wire width 5 $1\dec31_dec_sub11_form[4:0]
29079   attribute \src "libresoc.v:20333.3-20387.6"
29080   wire width 12 $1\dec31_dec_sub11_function_unit[11:0]
29081   attribute \src "libresoc.v:21323.3-21377.6"
29082   wire width 3 $1\dec31_dec_sub11_in1_sel[2:0]
29083   attribute \src "libresoc.v:21378.3-21432.6"
29084   wire width 4 $1\dec31_dec_sub11_in2_sel[3:0]
29085   attribute \src "libresoc.v:21433.3-21487.6"
29086   wire width 2 $1\dec31_dec_sub11_in3_sel[1:0]
29087   attribute \src "libresoc.v:20938.3-20992.6"
29088   wire width 7 $1\dec31_dec_sub11_internal_op[6:0]
29089   attribute \src "libresoc.v:20663.3-20717.6"
29090   wire $1\dec31_dec_sub11_inv_a[0:0]
29091   attribute \src "libresoc.v:20718.3-20772.6"
29092   wire $1\dec31_dec_sub11_inv_out[0:0]
29093   attribute \src "libresoc.v:21048.3-21102.6"
29094   wire $1\dec31_dec_sub11_is_32b[0:0]
29095   attribute \src "libresoc.v:20388.3-20442.6"
29096   wire width 4 $1\dec31_dec_sub11_ldst_len[3:0]
29097   attribute \src "libresoc.v:21158.3-21212.6"
29098   wire $1\dec31_dec_sub11_lk[0:0]
29099   attribute \src "libresoc.v:21488.3-21542.6"
29100   wire width 2 $1\dec31_dec_sub11_out_sel[1:0]
29101   attribute \src "libresoc.v:20498.3-20552.6"
29102   wire width 2 $1\dec31_dec_sub11_rc_sel[1:0]
29103   attribute \src "libresoc.v:20993.3-21047.6"
29104   wire $1\dec31_dec_sub11_rsrv[0:0]
29105   attribute \src "libresoc.v:21213.3-21267.6"
29106   wire $1\dec31_dec_sub11_sgl_pipe[0:0]
29107   attribute \src "libresoc.v:21103.3-21157.6"
29108   wire $1\dec31_dec_sub11_sgn[0:0]
29109   attribute \src "libresoc.v:20883.3-20937.6"
29110   wire $1\dec31_dec_sub11_sgn_ext[0:0]
29111   attribute \src "libresoc.v:20443.3-20497.6"
29112   wire width 2 $1\dec31_dec_sub11_upd[1:0]
29113   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29114   wire width 8 output 4 \dec31_dec_sub11_asmcode
29115   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29116   wire output 18 \dec31_dec_sub11_br
29117   attribute \enum_base_type "CRInSel"
29118   attribute \enum_value_000 "NONE"
29119   attribute \enum_value_001 "CR0"
29120   attribute \enum_value_010 "BI"
29121   attribute \enum_value_011 "BFA"
29122   attribute \enum_value_100 "BA_BB"
29123   attribute \enum_value_101 "BC"
29124   attribute \enum_value_110 "WHOLE_REG"
29125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29126   wire width 3 output 9 \dec31_dec_sub11_cr_in
29127   attribute \enum_base_type "CROutSel"
29128   attribute \enum_value_000 "NONE"
29129   attribute \enum_value_001 "CR0"
29130   attribute \enum_value_010 "BF"
29131   attribute \enum_value_011 "BT"
29132   attribute \enum_value_100 "WHOLE_REG"
29133   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29134   wire width 3 output 10 \dec31_dec_sub11_cr_out
29135   attribute \enum_base_type "CryIn"
29136   attribute \enum_value_00 "ZERO"
29137   attribute \enum_value_01 "ONE"
29138   attribute \enum_value_10 "CA"
29139   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29140   wire width 2 output 14 \dec31_dec_sub11_cry_in
29141   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29142   wire output 17 \dec31_dec_sub11_cry_out
29143   attribute \enum_base_type "Form"
29144   attribute \enum_value_00000 "NONE"
29145   attribute \enum_value_00001 "I"
29146   attribute \enum_value_00010 "B"
29147   attribute \enum_value_00011 "SC"
29148   attribute \enum_value_00100 "D"
29149   attribute \enum_value_00101 "DS"
29150   attribute \enum_value_00110 "DQ"
29151   attribute \enum_value_00111 "DX"
29152   attribute \enum_value_01000 "X"
29153   attribute \enum_value_01001 "XL"
29154   attribute \enum_value_01010 "XFX"
29155   attribute \enum_value_01011 "XFL"
29156   attribute \enum_value_01100 "XX1"
29157   attribute \enum_value_01101 "XX2"
29158   attribute \enum_value_01110 "XX3"
29159   attribute \enum_value_01111 "XX4"
29160   attribute \enum_value_10000 "XS"
29161   attribute \enum_value_10001 "XO"
29162   attribute \enum_value_10010 "A"
29163   attribute \enum_value_10011 "M"
29164   attribute \enum_value_10100 "MD"
29165   attribute \enum_value_10101 "MDS"
29166   attribute \enum_value_10110 "VA"
29167   attribute \enum_value_10111 "VC"
29168   attribute \enum_value_11000 "VX"
29169   attribute \enum_value_11001 "EVX"
29170   attribute \enum_value_11010 "EVS"
29171   attribute \enum_value_11011 "Z22"
29172   attribute \enum_value_11100 "Z23"
29173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29174   wire width 5 output 3 \dec31_dec_sub11_form
29175   attribute \enum_base_type "Function"
29176   attribute \enum_value_000000000000 "NONE"
29177   attribute \enum_value_000000000010 "ALU"
29178   attribute \enum_value_000000000100 "LDST"
29179   attribute \enum_value_000000001000 "SHIFT_ROT"
29180   attribute \enum_value_000000010000 "LOGICAL"
29181   attribute \enum_value_000000100000 "BRANCH"
29182   attribute \enum_value_000001000000 "CR"
29183   attribute \enum_value_000010000000 "TRAP"
29184   attribute \enum_value_000100000000 "MUL"
29185   attribute \enum_value_001000000000 "DIV"
29186   attribute \enum_value_010000000000 "SPR"
29187   attribute \enum_value_100000000000 "MMU"
29188   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29189   wire width 12 output 1 \dec31_dec_sub11_function_unit
29190   attribute \enum_base_type "In1Sel"
29191   attribute \enum_value_000 "NONE"
29192   attribute \enum_value_001 "RA"
29193   attribute \enum_value_010 "RA_OR_ZERO"
29194   attribute \enum_value_011 "SPR"
29195   attribute \enum_value_100 "RS"
29196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29197   wire width 3 output 5 \dec31_dec_sub11_in1_sel
29198   attribute \enum_base_type "In2Sel"
29199   attribute \enum_value_0000 "NONE"
29200   attribute \enum_value_0001 "RB"
29201   attribute \enum_value_0010 "CONST_UI"
29202   attribute \enum_value_0011 "CONST_SI"
29203   attribute \enum_value_0100 "CONST_UI_HI"
29204   attribute \enum_value_0101 "CONST_SI_HI"
29205   attribute \enum_value_0110 "CONST_LI"
29206   attribute \enum_value_0111 "CONST_BD"
29207   attribute \enum_value_1000 "CONST_DS"
29208   attribute \enum_value_1001 "CONST_M1"
29209   attribute \enum_value_1010 "CONST_SH"
29210   attribute \enum_value_1011 "CONST_SH32"
29211   attribute \enum_value_1100 "SPR"
29212   attribute \enum_value_1101 "RS"
29213   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29214   wire width 4 output 6 \dec31_dec_sub11_in2_sel
29215   attribute \enum_base_type "In3Sel"
29216   attribute \enum_value_00 "NONE"
29217   attribute \enum_value_01 "RS"
29218   attribute \enum_value_10 "RB"
29219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29220   wire width 2 output 7 \dec31_dec_sub11_in3_sel
29221   attribute \enum_base_type "MicrOp"
29222   attribute \enum_value_0000000 "OP_ILLEGAL"
29223   attribute \enum_value_0000001 "OP_NOP"
29224   attribute \enum_value_0000010 "OP_ADD"
29225   attribute \enum_value_0000011 "OP_ADDPCIS"
29226   attribute \enum_value_0000100 "OP_AND"
29227   attribute \enum_value_0000101 "OP_ATTN"
29228   attribute \enum_value_0000110 "OP_B"
29229   attribute \enum_value_0000111 "OP_BC"
29230   attribute \enum_value_0001000 "OP_BCREG"
29231   attribute \enum_value_0001001 "OP_BPERM"
29232   attribute \enum_value_0001010 "OP_CMP"
29233   attribute \enum_value_0001011 "OP_CMPB"
29234   attribute \enum_value_0001100 "OP_CMPEQB"
29235   attribute \enum_value_0001101 "OP_CMPRB"
29236   attribute \enum_value_0001110 "OP_CNTZ"
29237   attribute \enum_value_0001111 "OP_CRAND"
29238   attribute \enum_value_0010000 "OP_CRANDC"
29239   attribute \enum_value_0010001 "OP_CREQV"
29240   attribute \enum_value_0010010 "OP_CRNAND"
29241   attribute \enum_value_0010011 "OP_CRNOR"
29242   attribute \enum_value_0010100 "OP_CROR"
29243   attribute \enum_value_0010101 "OP_CRORC"
29244   attribute \enum_value_0010110 "OP_CRXOR"
29245   attribute \enum_value_0010111 "OP_DARN"
29246   attribute \enum_value_0011000 "OP_DCBF"
29247   attribute \enum_value_0011001 "OP_DCBST"
29248   attribute \enum_value_0011010 "OP_DCBT"
29249   attribute \enum_value_0011011 "OP_DCBTST"
29250   attribute \enum_value_0011100 "OP_DCBZ"
29251   attribute \enum_value_0011101 "OP_DIV"
29252   attribute \enum_value_0011110 "OP_DIVE"
29253   attribute \enum_value_0011111 "OP_EXTS"
29254   attribute \enum_value_0100000 "OP_EXTSWSLI"
29255   attribute \enum_value_0100001 "OP_ICBI"
29256   attribute \enum_value_0100010 "OP_ICBT"
29257   attribute \enum_value_0100011 "OP_ISEL"
29258   attribute \enum_value_0100100 "OP_ISYNC"
29259   attribute \enum_value_0100101 "OP_LOAD"
29260   attribute \enum_value_0100110 "OP_STORE"
29261   attribute \enum_value_0100111 "OP_MADDHD"
29262   attribute \enum_value_0101000 "OP_MADDHDU"
29263   attribute \enum_value_0101001 "OP_MADDLD"
29264   attribute \enum_value_0101010 "OP_MCRF"
29265   attribute \enum_value_0101011 "OP_MCRXR"
29266   attribute \enum_value_0101100 "OP_MCRXRX"
29267   attribute \enum_value_0101101 "OP_MFCR"
29268   attribute \enum_value_0101110 "OP_MFSPR"
29269   attribute \enum_value_0101111 "OP_MOD"
29270   attribute \enum_value_0110000 "OP_MTCRF"
29271   attribute \enum_value_0110001 "OP_MTSPR"
29272   attribute \enum_value_0110010 "OP_MUL_L64"
29273   attribute \enum_value_0110011 "OP_MUL_H64"
29274   attribute \enum_value_0110100 "OP_MUL_H32"
29275   attribute \enum_value_0110101 "OP_OR"
29276   attribute \enum_value_0110110 "OP_POPCNT"
29277   attribute \enum_value_0110111 "OP_PRTY"
29278   attribute \enum_value_0111000 "OP_RLC"
29279   attribute \enum_value_0111001 "OP_RLCL"
29280   attribute \enum_value_0111010 "OP_RLCR"
29281   attribute \enum_value_0111011 "OP_SETB"
29282   attribute \enum_value_0111100 "OP_SHL"
29283   attribute \enum_value_0111101 "OP_SHR"
29284   attribute \enum_value_0111110 "OP_SYNC"
29285   attribute \enum_value_0111111 "OP_TRAP"
29286   attribute \enum_value_1000011 "OP_XOR"
29287   attribute \enum_value_1000100 "OP_SIM_CONFIG"
29288   attribute \enum_value_1000101 "OP_CROP"
29289   attribute \enum_value_1000110 "OP_RFID"
29290   attribute \enum_value_1000111 "OP_MFMSR"
29291   attribute \enum_value_1001000 "OP_MTMSRD"
29292   attribute \enum_value_1001001 "OP_SC"
29293   attribute \enum_value_1001010 "OP_MTMSR"
29294   attribute \enum_value_1001011 "OP_TLBIE"
29295   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29296   wire width 7 output 2 \dec31_dec_sub11_internal_op
29297   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29298   wire output 15 \dec31_dec_sub11_inv_a
29299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29300   wire output 16 \dec31_dec_sub11_inv_out
29301   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29302   wire output 21 \dec31_dec_sub11_is_32b
29303   attribute \enum_base_type "LdstLen"
29304   attribute \enum_value_0000 "NONE"
29305   attribute \enum_value_0001 "is1B"
29306   attribute \enum_value_0010 "is2B"
29307   attribute \enum_value_0100 "is4B"
29308   attribute \enum_value_1000 "is8B"
29309   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29310   wire width 4 output 11 \dec31_dec_sub11_ldst_len
29311   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29312   wire output 23 \dec31_dec_sub11_lk
29313   attribute \enum_base_type "OutSel"
29314   attribute \enum_value_00 "NONE"
29315   attribute \enum_value_01 "RT"
29316   attribute \enum_value_10 "RA"
29317   attribute \enum_value_11 "SPR"
29318   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29319   wire width 2 output 8 \dec31_dec_sub11_out_sel
29320   attribute \enum_base_type "RC"
29321   attribute \enum_value_00 "NONE"
29322   attribute \enum_value_01 "ONE"
29323   attribute \enum_value_10 "RC"
29324   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29325   wire width 2 output 13 \dec31_dec_sub11_rc_sel
29326   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29327   wire output 20 \dec31_dec_sub11_rsrv
29328   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29329   wire output 24 \dec31_dec_sub11_sgl_pipe
29330   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29331   wire output 22 \dec31_dec_sub11_sgn
29332   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
29333   wire output 19 \dec31_dec_sub11_sgn_ext
29334   attribute \enum_base_type "LDSTMode"
29335   attribute \enum_value_00 "NONE"
29336   attribute \enum_value_01 "update"
29337   attribute \enum_value_10 "cix"
29338   attribute \enum_value_11 "cx"
29339   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
29340   wire width 2 output 12 \dec31_dec_sub11_upd
29341   attribute \src "libresoc.v:20076.7-20076.15"
29342   wire \initial
29343   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
29344   wire width 32 input 25 \opcode_in
29345   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
29346   wire width 5 \opcode_switch
29347   attribute \src "libresoc.v:20076.7-20076.20"
29348   process $proc$libresoc.v:20076$481
29349     assign { } { }
29350     assign $0\initial[0:0] 1'0
29351     sync always
29352       update \initial $0\initial[0:0]
29353     sync init
29354   end
29355   attribute \src "libresoc.v:20333.3-20387.6"
29356   process $proc$libresoc.v:20333$457
29357     assign { } { }
29358     assign { } { }
29359     assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0]
29360     attribute \src "libresoc.v:20334.5-20334.29"
29361     switch \initial
29362       attribute \src "libresoc.v:20334.9-20334.17"
29363       case 1'1
29364       case
29365     end
29366     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29367     switch \opcode_switch
29368       attribute \src "libresoc.v:0.0-0.0"
29369       case 5'01100
29370         assign { } { }
29371         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29372       attribute \src "libresoc.v:0.0-0.0"
29373       case 5'11100
29374         assign { } { }
29375         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29376       attribute \src "libresoc.v:0.0-0.0"
29377       case 5'01101
29378         assign { } { }
29379         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29380       attribute \src "libresoc.v:0.0-0.0"
29381       case 5'11101
29382         assign { } { }
29383         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29384       attribute \src "libresoc.v:0.0-0.0"
29385       case 5'01110
29386         assign { } { }
29387         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29388       attribute \src "libresoc.v:0.0-0.0"
29389       case 5'11110
29390         assign { } { }
29391         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29392       attribute \src "libresoc.v:0.0-0.0"
29393       case 5'01111
29394         assign { } { }
29395         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29396       attribute \src "libresoc.v:0.0-0.0"
29397       case 5'11111
29398         assign { } { }
29399         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29400       attribute \src "libresoc.v:0.0-0.0"
29401       case 5'01000
29402         assign { } { }
29403         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29404       attribute \src "libresoc.v:0.0-0.0"
29405       case 5'11000
29406         assign { } { }
29407         assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000
29408       attribute \src "libresoc.v:0.0-0.0"
29409       case 5'00010
29410         assign { } { }
29411         assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000
29412       attribute \src "libresoc.v:0.0-0.0"
29413       case 5'00000
29414         assign { } { }
29415         assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000
29416       attribute \src "libresoc.v:0.0-0.0"
29417       case 5'10010
29418         assign { } { }
29419         assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000
29420       attribute \src "libresoc.v:0.0-0.0"
29421       case 5'10000
29422         assign { } { }
29423         assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000
29424       attribute \src "libresoc.v:0.0-0.0"
29425       case 5'00111
29426         assign { } { }
29427         assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000
29428       attribute \src "libresoc.v:0.0-0.0"
29429       case 5'10111
29430         assign { } { }
29431         assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000
29432       case
29433         assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000
29434     end
29435     sync always
29436       update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0]
29437   end
29438   attribute \src "libresoc.v:20388.3-20442.6"
29439   process $proc$libresoc.v:20388$458
29440     assign { } { }
29441     assign { } { }
29442     assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0]
29443     attribute \src "libresoc.v:20389.5-20389.29"
29444     switch \initial
29445       attribute \src "libresoc.v:20389.9-20389.17"
29446       case 1'1
29447       case
29448     end
29449     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29450     switch \opcode_switch
29451       attribute \src "libresoc.v:0.0-0.0"
29452       case 5'01100
29453         assign { } { }
29454         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29455       attribute \src "libresoc.v:0.0-0.0"
29456       case 5'11100
29457         assign { } { }
29458         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29459       attribute \src "libresoc.v:0.0-0.0"
29460       case 5'01101
29461         assign { } { }
29462         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29463       attribute \src "libresoc.v:0.0-0.0"
29464       case 5'11101
29465         assign { } { }
29466         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29467       attribute \src "libresoc.v:0.0-0.0"
29468       case 5'01110
29469         assign { } { }
29470         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29471       attribute \src "libresoc.v:0.0-0.0"
29472       case 5'11110
29473         assign { } { }
29474         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29475       attribute \src "libresoc.v:0.0-0.0"
29476       case 5'01111
29477         assign { } { }
29478         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29479       attribute \src "libresoc.v:0.0-0.0"
29480       case 5'11111
29481         assign { } { }
29482         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29483       attribute \src "libresoc.v:0.0-0.0"
29484       case 5'01000
29485         assign { } { }
29486         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29487       attribute \src "libresoc.v:0.0-0.0"
29488       case 5'11000
29489         assign { } { }
29490         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29491       attribute \src "libresoc.v:0.0-0.0"
29492       case 5'00010
29493         assign { } { }
29494         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29495       attribute \src "libresoc.v:0.0-0.0"
29496       case 5'00000
29497         assign { } { }
29498         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29499       attribute \src "libresoc.v:0.0-0.0"
29500       case 5'10010
29501         assign { } { }
29502         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29503       attribute \src "libresoc.v:0.0-0.0"
29504       case 5'10000
29505         assign { } { }
29506         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29507       attribute \src "libresoc.v:0.0-0.0"
29508       case 5'00111
29509         assign { } { }
29510         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29511       attribute \src "libresoc.v:0.0-0.0"
29512       case 5'10111
29513         assign { } { }
29514         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29515       case
29516         assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000
29517     end
29518     sync always
29519       update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0]
29520   end
29521   attribute \src "libresoc.v:20443.3-20497.6"
29522   process $proc$libresoc.v:20443$459
29523     assign { } { }
29524     assign { } { }
29525     assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0]
29526     attribute \src "libresoc.v:20444.5-20444.29"
29527     switch \initial
29528       attribute \src "libresoc.v:20444.9-20444.17"
29529       case 1'1
29530       case
29531     end
29532     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29533     switch \opcode_switch
29534       attribute \src "libresoc.v:0.0-0.0"
29535       case 5'01100
29536         assign { } { }
29537         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29538       attribute \src "libresoc.v:0.0-0.0"
29539       case 5'11100
29540         assign { } { }
29541         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29542       attribute \src "libresoc.v:0.0-0.0"
29543       case 5'01101
29544         assign { } { }
29545         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29546       attribute \src "libresoc.v:0.0-0.0"
29547       case 5'11101
29548         assign { } { }
29549         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29550       attribute \src "libresoc.v:0.0-0.0"
29551       case 5'01110
29552         assign { } { }
29553         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29554       attribute \src "libresoc.v:0.0-0.0"
29555       case 5'11110
29556         assign { } { }
29557         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29558       attribute \src "libresoc.v:0.0-0.0"
29559       case 5'01111
29560         assign { } { }
29561         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29562       attribute \src "libresoc.v:0.0-0.0"
29563       case 5'11111
29564         assign { } { }
29565         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29566       attribute \src "libresoc.v:0.0-0.0"
29567       case 5'01000
29568         assign { } { }
29569         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29570       attribute \src "libresoc.v:0.0-0.0"
29571       case 5'11000
29572         assign { } { }
29573         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29574       attribute \src "libresoc.v:0.0-0.0"
29575       case 5'00010
29576         assign { } { }
29577         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29578       attribute \src "libresoc.v:0.0-0.0"
29579       case 5'00000
29580         assign { } { }
29581         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29582       attribute \src "libresoc.v:0.0-0.0"
29583       case 5'10010
29584         assign { } { }
29585         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29586       attribute \src "libresoc.v:0.0-0.0"
29587       case 5'10000
29588         assign { } { }
29589         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29590       attribute \src "libresoc.v:0.0-0.0"
29591       case 5'00111
29592         assign { } { }
29593         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29594       attribute \src "libresoc.v:0.0-0.0"
29595       case 5'10111
29596         assign { } { }
29597         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29598       case
29599         assign $1\dec31_dec_sub11_upd[1:0] 2'00
29600     end
29601     sync always
29602       update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0]
29603   end
29604   attribute \src "libresoc.v:20498.3-20552.6"
29605   process $proc$libresoc.v:20498$460
29606     assign { } { }
29607     assign { } { }
29608     assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0]
29609     attribute \src "libresoc.v:20499.5-20499.29"
29610     switch \initial
29611       attribute \src "libresoc.v:20499.9-20499.17"
29612       case 1'1
29613       case
29614     end
29615     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29616     switch \opcode_switch
29617       attribute \src "libresoc.v:0.0-0.0"
29618       case 5'01100
29619         assign { } { }
29620         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29621       attribute \src "libresoc.v:0.0-0.0"
29622       case 5'11100
29623         assign { } { }
29624         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29625       attribute \src "libresoc.v:0.0-0.0"
29626       case 5'01101
29627         assign { } { }
29628         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29629       attribute \src "libresoc.v:0.0-0.0"
29630       case 5'11101
29631         assign { } { }
29632         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29633       attribute \src "libresoc.v:0.0-0.0"
29634       case 5'01110
29635         assign { } { }
29636         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29637       attribute \src "libresoc.v:0.0-0.0"
29638       case 5'11110
29639         assign { } { }
29640         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29641       attribute \src "libresoc.v:0.0-0.0"
29642       case 5'01111
29643         assign { } { }
29644         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29645       attribute \src "libresoc.v:0.0-0.0"
29646       case 5'11111
29647         assign { } { }
29648         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29649       attribute \src "libresoc.v:0.0-0.0"
29650       case 5'01000
29651         assign { } { }
29652         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00
29653       attribute \src "libresoc.v:0.0-0.0"
29654       case 5'11000
29655         assign { } { }
29656         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00
29657       attribute \src "libresoc.v:0.0-0.0"
29658       case 5'00010
29659         assign { } { }
29660         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29661       attribute \src "libresoc.v:0.0-0.0"
29662       case 5'00000
29663         assign { } { }
29664         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29665       attribute \src "libresoc.v:0.0-0.0"
29666       case 5'10010
29667         assign { } { }
29668         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29669       attribute \src "libresoc.v:0.0-0.0"
29670       case 5'10000
29671         assign { } { }
29672         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29673       attribute \src "libresoc.v:0.0-0.0"
29674       case 5'00111
29675         assign { } { }
29676         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29677       attribute \src "libresoc.v:0.0-0.0"
29678       case 5'10111
29679         assign { } { }
29680         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10
29681       case
29682         assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00
29683     end
29684     sync always
29685       update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0]
29686   end
29687   attribute \src "libresoc.v:20553.3-20607.6"
29688   process $proc$libresoc.v:20553$461
29689     assign { } { }
29690     assign { } { }
29691     assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0]
29692     attribute \src "libresoc.v:20554.5-20554.29"
29693     switch \initial
29694       attribute \src "libresoc.v:20554.9-20554.17"
29695       case 1'1
29696       case
29697     end
29698     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29699     switch \opcode_switch
29700       attribute \src "libresoc.v:0.0-0.0"
29701       case 5'01100
29702         assign { } { }
29703         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29704       attribute \src "libresoc.v:0.0-0.0"
29705       case 5'11100
29706         assign { } { }
29707         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29708       attribute \src "libresoc.v:0.0-0.0"
29709       case 5'01101
29710         assign { } { }
29711         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29712       attribute \src "libresoc.v:0.0-0.0"
29713       case 5'11101
29714         assign { } { }
29715         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29716       attribute \src "libresoc.v:0.0-0.0"
29717       case 5'01110
29718         assign { } { }
29719         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29720       attribute \src "libresoc.v:0.0-0.0"
29721       case 5'11110
29722         assign { } { }
29723         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29724       attribute \src "libresoc.v:0.0-0.0"
29725       case 5'01111
29726         assign { } { }
29727         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29728       attribute \src "libresoc.v:0.0-0.0"
29729       case 5'11111
29730         assign { } { }
29731         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29732       attribute \src "libresoc.v:0.0-0.0"
29733       case 5'01000
29734         assign { } { }
29735         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29736       attribute \src "libresoc.v:0.0-0.0"
29737       case 5'11000
29738         assign { } { }
29739         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29740       attribute \src "libresoc.v:0.0-0.0"
29741       case 5'00010
29742         assign { } { }
29743         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29744       attribute \src "libresoc.v:0.0-0.0"
29745       case 5'00000
29746         assign { } { }
29747         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29748       attribute \src "libresoc.v:0.0-0.0"
29749       case 5'10010
29750         assign { } { }
29751         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29752       attribute \src "libresoc.v:0.0-0.0"
29753       case 5'10000
29754         assign { } { }
29755         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29756       attribute \src "libresoc.v:0.0-0.0"
29757       case 5'00111
29758         assign { } { }
29759         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29760       attribute \src "libresoc.v:0.0-0.0"
29761       case 5'10111
29762         assign { } { }
29763         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29764       case
29765         assign $1\dec31_dec_sub11_cry_in[1:0] 2'00
29766     end
29767     sync always
29768       update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0]
29769   end
29770   attribute \src "libresoc.v:20608.3-20662.6"
29771   process $proc$libresoc.v:20608$462
29772     assign { } { }
29773     assign { } { }
29774     assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0]
29775     attribute \src "libresoc.v:20609.5-20609.29"
29776     switch \initial
29777       attribute \src "libresoc.v:20609.9-20609.17"
29778       case 1'1
29779       case
29780     end
29781     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29782     switch \opcode_switch
29783       attribute \src "libresoc.v:0.0-0.0"
29784       case 5'01100
29785         assign { } { }
29786         assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110
29787       attribute \src "libresoc.v:0.0-0.0"
29788       case 5'11100
29789         assign { } { }
29790         assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111
29791       attribute \src "libresoc.v:0.0-0.0"
29792       case 5'01101
29793         assign { } { }
29794         assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100
29795       attribute \src "libresoc.v:0.0-0.0"
29796       case 5'11101
29797         assign { } { }
29798         assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101
29799       attribute \src "libresoc.v:0.0-0.0"
29800       case 5'01110
29801         assign { } { }
29802         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001
29803       attribute \src "libresoc.v:0.0-0.0"
29804       case 5'11110
29805         assign { } { }
29806         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010
29807       attribute \src "libresoc.v:0.0-0.0"
29808       case 5'01111
29809         assign { } { }
29810         assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011
29811       attribute \src "libresoc.v:0.0-0.0"
29812       case 5'11111
29813         assign { } { }
29814         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000
29815       attribute \src "libresoc.v:0.0-0.0"
29816       case 5'01000
29817         assign { } { }
29818         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101
29819       attribute \src "libresoc.v:0.0-0.0"
29820       case 5'11000
29821         assign { } { }
29822         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011
29823       attribute \src "libresoc.v:0.0-0.0"
29824       case 5'00010
29825         assign { } { }
29826         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100
29827       attribute \src "libresoc.v:0.0-0.0"
29828       case 5'00000
29829         assign { } { }
29830         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101
29831       attribute \src "libresoc.v:0.0-0.0"
29832       case 5'10010
29833         assign { } { }
29834         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100
29835       attribute \src "libresoc.v:0.0-0.0"
29836       case 5'10000
29837         assign { } { }
29838         assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101
29839       attribute \src "libresoc.v:0.0-0.0"
29840       case 5'00111
29841         assign { } { }
29842         assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001
29843       attribute \src "libresoc.v:0.0-0.0"
29844       case 5'10111
29845         assign { } { }
29846         assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010
29847       case
29848         assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000
29849     end
29850     sync always
29851       update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0]
29852   end
29853   attribute \src "libresoc.v:20663.3-20717.6"
29854   process $proc$libresoc.v:20663$463
29855     assign { } { }
29856     assign { } { }
29857     assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0]
29858     attribute \src "libresoc.v:20664.5-20664.29"
29859     switch \initial
29860       attribute \src "libresoc.v:20664.9-20664.17"
29861       case 1'1
29862       case
29863     end
29864     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29865     switch \opcode_switch
29866       attribute \src "libresoc.v:0.0-0.0"
29867       case 5'01100
29868         assign { } { }
29869         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29870       attribute \src "libresoc.v:0.0-0.0"
29871       case 5'11100
29872         assign { } { }
29873         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29874       attribute \src "libresoc.v:0.0-0.0"
29875       case 5'01101
29876         assign { } { }
29877         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29878       attribute \src "libresoc.v:0.0-0.0"
29879       case 5'11101
29880         assign { } { }
29881         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29882       attribute \src "libresoc.v:0.0-0.0"
29883       case 5'01110
29884         assign { } { }
29885         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29886       attribute \src "libresoc.v:0.0-0.0"
29887       case 5'11110
29888         assign { } { }
29889         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29890       attribute \src "libresoc.v:0.0-0.0"
29891       case 5'01111
29892         assign { } { }
29893         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29894       attribute \src "libresoc.v:0.0-0.0"
29895       case 5'11111
29896         assign { } { }
29897         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29898       attribute \src "libresoc.v:0.0-0.0"
29899       case 5'01000
29900         assign { } { }
29901         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29902       attribute \src "libresoc.v:0.0-0.0"
29903       case 5'11000
29904         assign { } { }
29905         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29906       attribute \src "libresoc.v:0.0-0.0"
29907       case 5'00010
29908         assign { } { }
29909         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29910       attribute \src "libresoc.v:0.0-0.0"
29911       case 5'00000
29912         assign { } { }
29913         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29914       attribute \src "libresoc.v:0.0-0.0"
29915       case 5'10010
29916         assign { } { }
29917         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29918       attribute \src "libresoc.v:0.0-0.0"
29919       case 5'10000
29920         assign { } { }
29921         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29922       attribute \src "libresoc.v:0.0-0.0"
29923       case 5'00111
29924         assign { } { }
29925         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29926       attribute \src "libresoc.v:0.0-0.0"
29927       case 5'10111
29928         assign { } { }
29929         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29930       case
29931         assign $1\dec31_dec_sub11_inv_a[0:0] 1'0
29932     end
29933     sync always
29934       update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0]
29935   end
29936   attribute \src "libresoc.v:20718.3-20772.6"
29937   process $proc$libresoc.v:20718$464
29938     assign { } { }
29939     assign { } { }
29940     assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0]
29941     attribute \src "libresoc.v:20719.5-20719.29"
29942     switch \initial
29943       attribute \src "libresoc.v:20719.9-20719.17"
29944       case 1'1
29945       case
29946     end
29947     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
29948     switch \opcode_switch
29949       attribute \src "libresoc.v:0.0-0.0"
29950       case 5'01100
29951         assign { } { }
29952         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29953       attribute \src "libresoc.v:0.0-0.0"
29954       case 5'11100
29955         assign { } { }
29956         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29957       attribute \src "libresoc.v:0.0-0.0"
29958       case 5'01101
29959         assign { } { }
29960         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29961       attribute \src "libresoc.v:0.0-0.0"
29962       case 5'11101
29963         assign { } { }
29964         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29965       attribute \src "libresoc.v:0.0-0.0"
29966       case 5'01110
29967         assign { } { }
29968         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29969       attribute \src "libresoc.v:0.0-0.0"
29970       case 5'11110
29971         assign { } { }
29972         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29973       attribute \src "libresoc.v:0.0-0.0"
29974       case 5'01111
29975         assign { } { }
29976         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29977       attribute \src "libresoc.v:0.0-0.0"
29978       case 5'11111
29979         assign { } { }
29980         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29981       attribute \src "libresoc.v:0.0-0.0"
29982       case 5'01000
29983         assign { } { }
29984         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29985       attribute \src "libresoc.v:0.0-0.0"
29986       case 5'11000
29987         assign { } { }
29988         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29989       attribute \src "libresoc.v:0.0-0.0"
29990       case 5'00010
29991         assign { } { }
29992         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29993       attribute \src "libresoc.v:0.0-0.0"
29994       case 5'00000
29995         assign { } { }
29996         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
29997       attribute \src "libresoc.v:0.0-0.0"
29998       case 5'10010
29999         assign { } { }
30000         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
30001       attribute \src "libresoc.v:0.0-0.0"
30002       case 5'10000
30003         assign { } { }
30004         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
30005       attribute \src "libresoc.v:0.0-0.0"
30006       case 5'00111
30007         assign { } { }
30008         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
30009       attribute \src "libresoc.v:0.0-0.0"
30010       case 5'10111
30011         assign { } { }
30012         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
30013       case
30014         assign $1\dec31_dec_sub11_inv_out[0:0] 1'0
30015     end
30016     sync always
30017       update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0]
30018   end
30019   attribute \src "libresoc.v:20773.3-20827.6"
30020   process $proc$libresoc.v:20773$465
30021     assign { } { }
30022     assign { } { }
30023     assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0]
30024     attribute \src "libresoc.v:20774.5-20774.29"
30025     switch \initial
30026       attribute \src "libresoc.v:20774.9-20774.17"
30027       case 1'1
30028       case
30029     end
30030     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30031     switch \opcode_switch
30032       attribute \src "libresoc.v:0.0-0.0"
30033       case 5'01100
30034         assign { } { }
30035         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30036       attribute \src "libresoc.v:0.0-0.0"
30037       case 5'11100
30038         assign { } { }
30039         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30040       attribute \src "libresoc.v:0.0-0.0"
30041       case 5'01101
30042         assign { } { }
30043         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30044       attribute \src "libresoc.v:0.0-0.0"
30045       case 5'11101
30046         assign { } { }
30047         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30048       attribute \src "libresoc.v:0.0-0.0"
30049       case 5'01110
30050         assign { } { }
30051         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30052       attribute \src "libresoc.v:0.0-0.0"
30053       case 5'11110
30054         assign { } { }
30055         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30056       attribute \src "libresoc.v:0.0-0.0"
30057       case 5'01111
30058         assign { } { }
30059         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30060       attribute \src "libresoc.v:0.0-0.0"
30061       case 5'11111
30062         assign { } { }
30063         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30064       attribute \src "libresoc.v:0.0-0.0"
30065       case 5'01000
30066         assign { } { }
30067         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30068       attribute \src "libresoc.v:0.0-0.0"
30069       case 5'11000
30070         assign { } { }
30071         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30072       attribute \src "libresoc.v:0.0-0.0"
30073       case 5'00010
30074         assign { } { }
30075         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30076       attribute \src "libresoc.v:0.0-0.0"
30077       case 5'00000
30078         assign { } { }
30079         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30080       attribute \src "libresoc.v:0.0-0.0"
30081       case 5'10010
30082         assign { } { }
30083         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30084       attribute \src "libresoc.v:0.0-0.0"
30085       case 5'10000
30086         assign { } { }
30087         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30088       attribute \src "libresoc.v:0.0-0.0"
30089       case 5'00111
30090         assign { } { }
30091         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30092       attribute \src "libresoc.v:0.0-0.0"
30093       case 5'10111
30094         assign { } { }
30095         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30096       case
30097         assign $1\dec31_dec_sub11_cry_out[0:0] 1'0
30098     end
30099     sync always
30100       update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0]
30101   end
30102   attribute \src "libresoc.v:20828.3-20882.6"
30103   process $proc$libresoc.v:20828$466
30104     assign { } { }
30105     assign { } { }
30106     assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0]
30107     attribute \src "libresoc.v:20829.5-20829.29"
30108     switch \initial
30109       attribute \src "libresoc.v:20829.9-20829.17"
30110       case 1'1
30111       case
30112     end
30113     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30114     switch \opcode_switch
30115       attribute \src "libresoc.v:0.0-0.0"
30116       case 5'01100
30117         assign { } { }
30118         assign $1\dec31_dec_sub11_br[0:0] 1'0
30119       attribute \src "libresoc.v:0.0-0.0"
30120       case 5'11100
30121         assign { } { }
30122         assign $1\dec31_dec_sub11_br[0:0] 1'0
30123       attribute \src "libresoc.v:0.0-0.0"
30124       case 5'01101
30125         assign { } { }
30126         assign $1\dec31_dec_sub11_br[0:0] 1'0
30127       attribute \src "libresoc.v:0.0-0.0"
30128       case 5'11101
30129         assign { } { }
30130         assign $1\dec31_dec_sub11_br[0:0] 1'0
30131       attribute \src "libresoc.v:0.0-0.0"
30132       case 5'01110
30133         assign { } { }
30134         assign $1\dec31_dec_sub11_br[0:0] 1'0
30135       attribute \src "libresoc.v:0.0-0.0"
30136       case 5'11110
30137         assign { } { }
30138         assign $1\dec31_dec_sub11_br[0:0] 1'0
30139       attribute \src "libresoc.v:0.0-0.0"
30140       case 5'01111
30141         assign { } { }
30142         assign $1\dec31_dec_sub11_br[0:0] 1'0
30143       attribute \src "libresoc.v:0.0-0.0"
30144       case 5'11111
30145         assign { } { }
30146         assign $1\dec31_dec_sub11_br[0:0] 1'0
30147       attribute \src "libresoc.v:0.0-0.0"
30148       case 5'01000
30149         assign { } { }
30150         assign $1\dec31_dec_sub11_br[0:0] 1'0
30151       attribute \src "libresoc.v:0.0-0.0"
30152       case 5'11000
30153         assign { } { }
30154         assign $1\dec31_dec_sub11_br[0:0] 1'0
30155       attribute \src "libresoc.v:0.0-0.0"
30156       case 5'00010
30157         assign { } { }
30158         assign $1\dec31_dec_sub11_br[0:0] 1'0
30159       attribute \src "libresoc.v:0.0-0.0"
30160       case 5'00000
30161         assign { } { }
30162         assign $1\dec31_dec_sub11_br[0:0] 1'0
30163       attribute \src "libresoc.v:0.0-0.0"
30164       case 5'10010
30165         assign { } { }
30166         assign $1\dec31_dec_sub11_br[0:0] 1'0
30167       attribute \src "libresoc.v:0.0-0.0"
30168       case 5'10000
30169         assign { } { }
30170         assign $1\dec31_dec_sub11_br[0:0] 1'0
30171       attribute \src "libresoc.v:0.0-0.0"
30172       case 5'00111
30173         assign { } { }
30174         assign $1\dec31_dec_sub11_br[0:0] 1'0
30175       attribute \src "libresoc.v:0.0-0.0"
30176       case 5'10111
30177         assign { } { }
30178         assign $1\dec31_dec_sub11_br[0:0] 1'0
30179       case
30180         assign $1\dec31_dec_sub11_br[0:0] 1'0
30181     end
30182     sync always
30183       update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0]
30184   end
30185   attribute \src "libresoc.v:20883.3-20937.6"
30186   process $proc$libresoc.v:20883$467
30187     assign { } { }
30188     assign { } { }
30189     assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0]
30190     attribute \src "libresoc.v:20884.5-20884.29"
30191     switch \initial
30192       attribute \src "libresoc.v:20884.9-20884.17"
30193       case 1'1
30194       case
30195     end
30196     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30197     switch \opcode_switch
30198       attribute \src "libresoc.v:0.0-0.0"
30199       case 5'01100
30200         assign { } { }
30201         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30202       attribute \src "libresoc.v:0.0-0.0"
30203       case 5'11100
30204         assign { } { }
30205         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30206       attribute \src "libresoc.v:0.0-0.0"
30207       case 5'01101
30208         assign { } { }
30209         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30210       attribute \src "libresoc.v:0.0-0.0"
30211       case 5'11101
30212         assign { } { }
30213         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30214       attribute \src "libresoc.v:0.0-0.0"
30215       case 5'01110
30216         assign { } { }
30217         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30218       attribute \src "libresoc.v:0.0-0.0"
30219       case 5'11110
30220         assign { } { }
30221         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30222       attribute \src "libresoc.v:0.0-0.0"
30223       case 5'01111
30224         assign { } { }
30225         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30226       attribute \src "libresoc.v:0.0-0.0"
30227       case 5'11111
30228         assign { } { }
30229         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30230       attribute \src "libresoc.v:0.0-0.0"
30231       case 5'01000
30232         assign { } { }
30233         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30234       attribute \src "libresoc.v:0.0-0.0"
30235       case 5'11000
30236         assign { } { }
30237         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30238       attribute \src "libresoc.v:0.0-0.0"
30239       case 5'00010
30240         assign { } { }
30241         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30242       attribute \src "libresoc.v:0.0-0.0"
30243       case 5'00000
30244         assign { } { }
30245         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30246       attribute \src "libresoc.v:0.0-0.0"
30247       case 5'10010
30248         assign { } { }
30249         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30250       attribute \src "libresoc.v:0.0-0.0"
30251       case 5'10000
30252         assign { } { }
30253         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30254       attribute \src "libresoc.v:0.0-0.0"
30255       case 5'00111
30256         assign { } { }
30257         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30258       attribute \src "libresoc.v:0.0-0.0"
30259       case 5'10111
30260         assign { } { }
30261         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30262       case
30263         assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0
30264     end
30265     sync always
30266       update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0]
30267   end
30268   attribute \src "libresoc.v:20938.3-20992.6"
30269   process $proc$libresoc.v:20938$468
30270     assign { } { }
30271     assign { } { }
30272     assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0]
30273     attribute \src "libresoc.v:20939.5-20939.29"
30274     switch \initial
30275       attribute \src "libresoc.v:20939.9-20939.17"
30276       case 1'1
30277       case
30278     end
30279     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30280     switch \opcode_switch
30281       attribute \src "libresoc.v:0.0-0.0"
30282       case 5'01100
30283         assign { } { }
30284         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110
30285       attribute \src "libresoc.v:0.0-0.0"
30286       case 5'11100
30287         assign { } { }
30288         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110
30289       attribute \src "libresoc.v:0.0-0.0"
30290       case 5'01101
30291         assign { } { }
30292         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110
30293       attribute \src "libresoc.v:0.0-0.0"
30294       case 5'11101
30295         assign { } { }
30296         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110
30297       attribute \src "libresoc.v:0.0-0.0"
30298       case 5'01110
30299         assign { } { }
30300         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101
30301       attribute \src "libresoc.v:0.0-0.0"
30302       case 5'11110
30303         assign { } { }
30304         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101
30305       attribute \src "libresoc.v:0.0-0.0"
30306       case 5'01111
30307         assign { } { }
30308         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101
30309       attribute \src "libresoc.v:0.0-0.0"
30310       case 5'11111
30311         assign { } { }
30312         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101
30313       attribute \src "libresoc.v:0.0-0.0"
30314       case 5'01000
30315         assign { } { }
30316         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111
30317       attribute \src "libresoc.v:0.0-0.0"
30318       case 5'11000
30319         assign { } { }
30320         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111
30321       attribute \src "libresoc.v:0.0-0.0"
30322       case 5'00010
30323         assign { } { }
30324         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100
30325       attribute \src "libresoc.v:0.0-0.0"
30326       case 5'00000
30327         assign { } { }
30328         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100
30329       attribute \src "libresoc.v:0.0-0.0"
30330       case 5'10010
30331         assign { } { }
30332         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100
30333       attribute \src "libresoc.v:0.0-0.0"
30334       case 5'10000
30335         assign { } { }
30336         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100
30337       attribute \src "libresoc.v:0.0-0.0"
30338       case 5'00111
30339         assign { } { }
30340         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010
30341       attribute \src "libresoc.v:0.0-0.0"
30342       case 5'10111
30343         assign { } { }
30344         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010
30345       case
30346         assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000
30347     end
30348     sync always
30349       update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0]
30350   end
30351   attribute \src "libresoc.v:20993.3-21047.6"
30352   process $proc$libresoc.v:20993$469
30353     assign { } { }
30354     assign { } { }
30355     assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0]
30356     attribute \src "libresoc.v:20994.5-20994.29"
30357     switch \initial
30358       attribute \src "libresoc.v:20994.9-20994.17"
30359       case 1'1
30360       case
30361     end
30362     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30363     switch \opcode_switch
30364       attribute \src "libresoc.v:0.0-0.0"
30365       case 5'01100
30366         assign { } { }
30367         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30368       attribute \src "libresoc.v:0.0-0.0"
30369       case 5'11100
30370         assign { } { }
30371         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30372       attribute \src "libresoc.v:0.0-0.0"
30373       case 5'01101
30374         assign { } { }
30375         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30376       attribute \src "libresoc.v:0.0-0.0"
30377       case 5'11101
30378         assign { } { }
30379         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30380       attribute \src "libresoc.v:0.0-0.0"
30381       case 5'01110
30382         assign { } { }
30383         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30384       attribute \src "libresoc.v:0.0-0.0"
30385       case 5'11110
30386         assign { } { }
30387         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30388       attribute \src "libresoc.v:0.0-0.0"
30389       case 5'01111
30390         assign { } { }
30391         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30392       attribute \src "libresoc.v:0.0-0.0"
30393       case 5'11111
30394         assign { } { }
30395         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30396       attribute \src "libresoc.v:0.0-0.0"
30397       case 5'01000
30398         assign { } { }
30399         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30400       attribute \src "libresoc.v:0.0-0.0"
30401       case 5'11000
30402         assign { } { }
30403         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30404       attribute \src "libresoc.v:0.0-0.0"
30405       case 5'00010
30406         assign { } { }
30407         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30408       attribute \src "libresoc.v:0.0-0.0"
30409       case 5'00000
30410         assign { } { }
30411         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30412       attribute \src "libresoc.v:0.0-0.0"
30413       case 5'10010
30414         assign { } { }
30415         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30416       attribute \src "libresoc.v:0.0-0.0"
30417       case 5'10000
30418         assign { } { }
30419         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30420       attribute \src "libresoc.v:0.0-0.0"
30421       case 5'00111
30422         assign { } { }
30423         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30424       attribute \src "libresoc.v:0.0-0.0"
30425       case 5'10111
30426         assign { } { }
30427         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30428       case
30429         assign $1\dec31_dec_sub11_rsrv[0:0] 1'0
30430     end
30431     sync always
30432       update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0]
30433   end
30434   attribute \src "libresoc.v:21048.3-21102.6"
30435   process $proc$libresoc.v:21048$470
30436     assign { } { }
30437     assign { } { }
30438     assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0]
30439     attribute \src "libresoc.v:21049.5-21049.29"
30440     switch \initial
30441       attribute \src "libresoc.v:21049.9-21049.17"
30442       case 1'1
30443       case
30444     end
30445     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30446     switch \opcode_switch
30447       attribute \src "libresoc.v:0.0-0.0"
30448       case 5'01100
30449         assign { } { }
30450         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30451       attribute \src "libresoc.v:0.0-0.0"
30452       case 5'11100
30453         assign { } { }
30454         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30455       attribute \src "libresoc.v:0.0-0.0"
30456       case 5'01101
30457         assign { } { }
30458         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30459       attribute \src "libresoc.v:0.0-0.0"
30460       case 5'11101
30461         assign { } { }
30462         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30463       attribute \src "libresoc.v:0.0-0.0"
30464       case 5'01110
30465         assign { } { }
30466         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30467       attribute \src "libresoc.v:0.0-0.0"
30468       case 5'11110
30469         assign { } { }
30470         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30471       attribute \src "libresoc.v:0.0-0.0"
30472       case 5'01111
30473         assign { } { }
30474         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30475       attribute \src "libresoc.v:0.0-0.0"
30476       case 5'11111
30477         assign { } { }
30478         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30479       attribute \src "libresoc.v:0.0-0.0"
30480       case 5'01000
30481         assign { } { }
30482         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30483       attribute \src "libresoc.v:0.0-0.0"
30484       case 5'11000
30485         assign { } { }
30486         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30487       attribute \src "libresoc.v:0.0-0.0"
30488       case 5'00010
30489         assign { } { }
30490         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30491       attribute \src "libresoc.v:0.0-0.0"
30492       case 5'00000
30493         assign { } { }
30494         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30495       attribute \src "libresoc.v:0.0-0.0"
30496       case 5'10010
30497         assign { } { }
30498         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30499       attribute \src "libresoc.v:0.0-0.0"
30500       case 5'10000
30501         assign { } { }
30502         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30503       attribute \src "libresoc.v:0.0-0.0"
30504       case 5'00111
30505         assign { } { }
30506         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30507       attribute \src "libresoc.v:0.0-0.0"
30508       case 5'10111
30509         assign { } { }
30510         assign $1\dec31_dec_sub11_is_32b[0:0] 1'1
30511       case
30512         assign $1\dec31_dec_sub11_is_32b[0:0] 1'0
30513     end
30514     sync always
30515       update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0]
30516   end
30517   attribute \src "libresoc.v:21103.3-21157.6"
30518   process $proc$libresoc.v:21103$471
30519     assign { } { }
30520     assign { } { }
30521     assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0]
30522     attribute \src "libresoc.v:21104.5-21104.29"
30523     switch \initial
30524       attribute \src "libresoc.v:21104.9-21104.17"
30525       case 1'1
30526       case
30527     end
30528     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30529     switch \opcode_switch
30530       attribute \src "libresoc.v:0.0-0.0"
30531       case 5'01100
30532         assign { } { }
30533         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30534       attribute \src "libresoc.v:0.0-0.0"
30535       case 5'11100
30536         assign { } { }
30537         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30538       attribute \src "libresoc.v:0.0-0.0"
30539       case 5'01101
30540         assign { } { }
30541         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30542       attribute \src "libresoc.v:0.0-0.0"
30543       case 5'11101
30544         assign { } { }
30545         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30546       attribute \src "libresoc.v:0.0-0.0"
30547       case 5'01110
30548         assign { } { }
30549         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30550       attribute \src "libresoc.v:0.0-0.0"
30551       case 5'11110
30552         assign { } { }
30553         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30554       attribute \src "libresoc.v:0.0-0.0"
30555       case 5'01111
30556         assign { } { }
30557         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30558       attribute \src "libresoc.v:0.0-0.0"
30559       case 5'11111
30560         assign { } { }
30561         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30562       attribute \src "libresoc.v:0.0-0.0"
30563       case 5'01000
30564         assign { } { }
30565         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30566       attribute \src "libresoc.v:0.0-0.0"
30567       case 5'11000
30568         assign { } { }
30569         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30570       attribute \src "libresoc.v:0.0-0.0"
30571       case 5'00010
30572         assign { } { }
30573         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30574       attribute \src "libresoc.v:0.0-0.0"
30575       case 5'00000
30576         assign { } { }
30577         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30578       attribute \src "libresoc.v:0.0-0.0"
30579       case 5'10010
30580         assign { } { }
30581         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30582       attribute \src "libresoc.v:0.0-0.0"
30583       case 5'10000
30584         assign { } { }
30585         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30586       attribute \src "libresoc.v:0.0-0.0"
30587       case 5'00111
30588         assign { } { }
30589         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30590       attribute \src "libresoc.v:0.0-0.0"
30591       case 5'10111
30592         assign { } { }
30593         assign $1\dec31_dec_sub11_sgn[0:0] 1'1
30594       case
30595         assign $1\dec31_dec_sub11_sgn[0:0] 1'0
30596     end
30597     sync always
30598       update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0]
30599   end
30600   attribute \src "libresoc.v:21158.3-21212.6"
30601   process $proc$libresoc.v:21158$472
30602     assign { } { }
30603     assign { } { }
30604     assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0]
30605     attribute \src "libresoc.v:21159.5-21159.29"
30606     switch \initial
30607       attribute \src "libresoc.v:21159.9-21159.17"
30608       case 1'1
30609       case
30610     end
30611     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30612     switch \opcode_switch
30613       attribute \src "libresoc.v:0.0-0.0"
30614       case 5'01100
30615         assign { } { }
30616         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30617       attribute \src "libresoc.v:0.0-0.0"
30618       case 5'11100
30619         assign { } { }
30620         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30621       attribute \src "libresoc.v:0.0-0.0"
30622       case 5'01101
30623         assign { } { }
30624         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30625       attribute \src "libresoc.v:0.0-0.0"
30626       case 5'11101
30627         assign { } { }
30628         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30629       attribute \src "libresoc.v:0.0-0.0"
30630       case 5'01110
30631         assign { } { }
30632         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30633       attribute \src "libresoc.v:0.0-0.0"
30634       case 5'11110
30635         assign { } { }
30636         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30637       attribute \src "libresoc.v:0.0-0.0"
30638       case 5'01111
30639         assign { } { }
30640         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30641       attribute \src "libresoc.v:0.0-0.0"
30642       case 5'11111
30643         assign { } { }
30644         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30645       attribute \src "libresoc.v:0.0-0.0"
30646       case 5'01000
30647         assign { } { }
30648         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30649       attribute \src "libresoc.v:0.0-0.0"
30650       case 5'11000
30651         assign { } { }
30652         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30653       attribute \src "libresoc.v:0.0-0.0"
30654       case 5'00010
30655         assign { } { }
30656         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30657       attribute \src "libresoc.v:0.0-0.0"
30658       case 5'00000
30659         assign { } { }
30660         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30661       attribute \src "libresoc.v:0.0-0.0"
30662       case 5'10010
30663         assign { } { }
30664         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30665       attribute \src "libresoc.v:0.0-0.0"
30666       case 5'10000
30667         assign { } { }
30668         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30669       attribute \src "libresoc.v:0.0-0.0"
30670       case 5'00111
30671         assign { } { }
30672         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30673       attribute \src "libresoc.v:0.0-0.0"
30674       case 5'10111
30675         assign { } { }
30676         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30677       case
30678         assign $1\dec31_dec_sub11_lk[0:0] 1'0
30679     end
30680     sync always
30681       update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0]
30682   end
30683   attribute \src "libresoc.v:21213.3-21267.6"
30684   process $proc$libresoc.v:21213$473
30685     assign { } { }
30686     assign { } { }
30687     assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0]
30688     attribute \src "libresoc.v:21214.5-21214.29"
30689     switch \initial
30690       attribute \src "libresoc.v:21214.9-21214.17"
30691       case 1'1
30692       case
30693     end
30694     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30695     switch \opcode_switch
30696       attribute \src "libresoc.v:0.0-0.0"
30697       case 5'01100
30698         assign { } { }
30699         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30700       attribute \src "libresoc.v:0.0-0.0"
30701       case 5'11100
30702         assign { } { }
30703         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30704       attribute \src "libresoc.v:0.0-0.0"
30705       case 5'01101
30706         assign { } { }
30707         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30708       attribute \src "libresoc.v:0.0-0.0"
30709       case 5'11101
30710         assign { } { }
30711         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30712       attribute \src "libresoc.v:0.0-0.0"
30713       case 5'01110
30714         assign { } { }
30715         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30716       attribute \src "libresoc.v:0.0-0.0"
30717       case 5'11110
30718         assign { } { }
30719         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30720       attribute \src "libresoc.v:0.0-0.0"
30721       case 5'01111
30722         assign { } { }
30723         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30724       attribute \src "libresoc.v:0.0-0.0"
30725       case 5'11111
30726         assign { } { }
30727         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30728       attribute \src "libresoc.v:0.0-0.0"
30729       case 5'01000
30730         assign { } { }
30731         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30732       attribute \src "libresoc.v:0.0-0.0"
30733       case 5'11000
30734         assign { } { }
30735         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30736       attribute \src "libresoc.v:0.0-0.0"
30737       case 5'00010
30738         assign { } { }
30739         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30740       attribute \src "libresoc.v:0.0-0.0"
30741       case 5'00000
30742         assign { } { }
30743         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30744       attribute \src "libresoc.v:0.0-0.0"
30745       case 5'10010
30746         assign { } { }
30747         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30748       attribute \src "libresoc.v:0.0-0.0"
30749       case 5'10000
30750         assign { } { }
30751         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30752       attribute \src "libresoc.v:0.0-0.0"
30753       case 5'00111
30754         assign { } { }
30755         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30756       attribute \src "libresoc.v:0.0-0.0"
30757       case 5'10111
30758         assign { } { }
30759         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30760       case
30761         assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0
30762     end
30763     sync always
30764       update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0]
30765   end
30766   attribute \src "libresoc.v:21268.3-21322.6"
30767   process $proc$libresoc.v:21268$474
30768     assign { } { }
30769     assign { } { }
30770     assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0]
30771     attribute \src "libresoc.v:21269.5-21269.29"
30772     switch \initial
30773       attribute \src "libresoc.v:21269.9-21269.17"
30774       case 1'1
30775       case
30776     end
30777     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30778     switch \opcode_switch
30779       attribute \src "libresoc.v:0.0-0.0"
30780       case 5'01100
30781         assign { } { }
30782         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30783       attribute \src "libresoc.v:0.0-0.0"
30784       case 5'11100
30785         assign { } { }
30786         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30787       attribute \src "libresoc.v:0.0-0.0"
30788       case 5'01101
30789         assign { } { }
30790         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30791       attribute \src "libresoc.v:0.0-0.0"
30792       case 5'11101
30793         assign { } { }
30794         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30795       attribute \src "libresoc.v:0.0-0.0"
30796       case 5'01110
30797         assign { } { }
30798         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30799       attribute \src "libresoc.v:0.0-0.0"
30800       case 5'11110
30801         assign { } { }
30802         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30803       attribute \src "libresoc.v:0.0-0.0"
30804       case 5'01111
30805         assign { } { }
30806         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30807       attribute \src "libresoc.v:0.0-0.0"
30808       case 5'11111
30809         assign { } { }
30810         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30811       attribute \src "libresoc.v:0.0-0.0"
30812       case 5'01000
30813         assign { } { }
30814         assign $1\dec31_dec_sub11_form[4:0] 5'01000
30815       attribute \src "libresoc.v:0.0-0.0"
30816       case 5'11000
30817         assign { } { }
30818         assign $1\dec31_dec_sub11_form[4:0] 5'01000
30819       attribute \src "libresoc.v:0.0-0.0"
30820       case 5'00010
30821         assign { } { }
30822         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30823       attribute \src "libresoc.v:0.0-0.0"
30824       case 5'00000
30825         assign { } { }
30826         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30827       attribute \src "libresoc.v:0.0-0.0"
30828       case 5'10010
30829         assign { } { }
30830         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30831       attribute \src "libresoc.v:0.0-0.0"
30832       case 5'10000
30833         assign { } { }
30834         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30835       attribute \src "libresoc.v:0.0-0.0"
30836       case 5'00111
30837         assign { } { }
30838         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30839       attribute \src "libresoc.v:0.0-0.0"
30840       case 5'10111
30841         assign { } { }
30842         assign $1\dec31_dec_sub11_form[4:0] 5'10001
30843       case
30844         assign $1\dec31_dec_sub11_form[4:0] 5'00000
30845     end
30846     sync always
30847       update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0]
30848   end
30849   attribute \src "libresoc.v:21323.3-21377.6"
30850   process $proc$libresoc.v:21323$475
30851     assign { } { }
30852     assign { } { }
30853     assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0]
30854     attribute \src "libresoc.v:21324.5-21324.29"
30855     switch \initial
30856       attribute \src "libresoc.v:21324.9-21324.17"
30857       case 1'1
30858       case
30859     end
30860     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30861     switch \opcode_switch
30862       attribute \src "libresoc.v:0.0-0.0"
30863       case 5'01100
30864         assign { } { }
30865         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30866       attribute \src "libresoc.v:0.0-0.0"
30867       case 5'11100
30868         assign { } { }
30869         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30870       attribute \src "libresoc.v:0.0-0.0"
30871       case 5'01101
30872         assign { } { }
30873         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30874       attribute \src "libresoc.v:0.0-0.0"
30875       case 5'11101
30876         assign { } { }
30877         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30878       attribute \src "libresoc.v:0.0-0.0"
30879       case 5'01110
30880         assign { } { }
30881         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30882       attribute \src "libresoc.v:0.0-0.0"
30883       case 5'11110
30884         assign { } { }
30885         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30886       attribute \src "libresoc.v:0.0-0.0"
30887       case 5'01111
30888         assign { } { }
30889         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30890       attribute \src "libresoc.v:0.0-0.0"
30891       case 5'11111
30892         assign { } { }
30893         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30894       attribute \src "libresoc.v:0.0-0.0"
30895       case 5'01000
30896         assign { } { }
30897         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30898       attribute \src "libresoc.v:0.0-0.0"
30899       case 5'11000
30900         assign { } { }
30901         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30902       attribute \src "libresoc.v:0.0-0.0"
30903       case 5'00010
30904         assign { } { }
30905         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30906       attribute \src "libresoc.v:0.0-0.0"
30907       case 5'00000
30908         assign { } { }
30909         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30910       attribute \src "libresoc.v:0.0-0.0"
30911       case 5'10010
30912         assign { } { }
30913         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30914       attribute \src "libresoc.v:0.0-0.0"
30915       case 5'10000
30916         assign { } { }
30917         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30918       attribute \src "libresoc.v:0.0-0.0"
30919       case 5'00111
30920         assign { } { }
30921         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30922       attribute \src "libresoc.v:0.0-0.0"
30923       case 5'10111
30924         assign { } { }
30925         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001
30926       case
30927         assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000
30928     end
30929     sync always
30930       update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0]
30931   end
30932   attribute \src "libresoc.v:21378.3-21432.6"
30933   process $proc$libresoc.v:21378$476
30934     assign { } { }
30935     assign { } { }
30936     assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0]
30937     attribute \src "libresoc.v:21379.5-21379.29"
30938     switch \initial
30939       attribute \src "libresoc.v:21379.9-21379.17"
30940       case 1'1
30941       case
30942     end
30943     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
30944     switch \opcode_switch
30945       attribute \src "libresoc.v:0.0-0.0"
30946       case 5'01100
30947         assign { } { }
30948         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30949       attribute \src "libresoc.v:0.0-0.0"
30950       case 5'11100
30951         assign { } { }
30952         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30953       attribute \src "libresoc.v:0.0-0.0"
30954       case 5'01101
30955         assign { } { }
30956         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30957       attribute \src "libresoc.v:0.0-0.0"
30958       case 5'11101
30959         assign { } { }
30960         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30961       attribute \src "libresoc.v:0.0-0.0"
30962       case 5'01110
30963         assign { } { }
30964         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30965       attribute \src "libresoc.v:0.0-0.0"
30966       case 5'11110
30967         assign { } { }
30968         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30969       attribute \src "libresoc.v:0.0-0.0"
30970       case 5'01111
30971         assign { } { }
30972         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30973       attribute \src "libresoc.v:0.0-0.0"
30974       case 5'11111
30975         assign { } { }
30976         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30977       attribute \src "libresoc.v:0.0-0.0"
30978       case 5'01000
30979         assign { } { }
30980         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30981       attribute \src "libresoc.v:0.0-0.0"
30982       case 5'11000
30983         assign { } { }
30984         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30985       attribute \src "libresoc.v:0.0-0.0"
30986       case 5'00010
30987         assign { } { }
30988         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30989       attribute \src "libresoc.v:0.0-0.0"
30990       case 5'00000
30991         assign { } { }
30992         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30993       attribute \src "libresoc.v:0.0-0.0"
30994       case 5'10010
30995         assign { } { }
30996         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
30997       attribute \src "libresoc.v:0.0-0.0"
30998       case 5'10000
30999         assign { } { }
31000         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
31001       attribute \src "libresoc.v:0.0-0.0"
31002       case 5'00111
31003         assign { } { }
31004         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
31005       attribute \src "libresoc.v:0.0-0.0"
31006       case 5'10111
31007         assign { } { }
31008         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001
31009       case
31010         assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000
31011     end
31012     sync always
31013       update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0]
31014   end
31015   attribute \src "libresoc.v:21433.3-21487.6"
31016   process $proc$libresoc.v:21433$477
31017     assign { } { }
31018     assign { } { }
31019     assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0]
31020     attribute \src "libresoc.v:21434.5-21434.29"
31021     switch \initial
31022       attribute \src "libresoc.v:21434.9-21434.17"
31023       case 1'1
31024       case
31025     end
31026     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
31027     switch \opcode_switch
31028       attribute \src "libresoc.v:0.0-0.0"
31029       case 5'01100
31030         assign { } { }
31031         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31032       attribute \src "libresoc.v:0.0-0.0"
31033       case 5'11100
31034         assign { } { }
31035         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31036       attribute \src "libresoc.v:0.0-0.0"
31037       case 5'01101
31038         assign { } { }
31039         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31040       attribute \src "libresoc.v:0.0-0.0"
31041       case 5'11101
31042         assign { } { }
31043         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31044       attribute \src "libresoc.v:0.0-0.0"
31045       case 5'01110
31046         assign { } { }
31047         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31048       attribute \src "libresoc.v:0.0-0.0"
31049       case 5'11110
31050         assign { } { }
31051         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31052       attribute \src "libresoc.v:0.0-0.0"
31053       case 5'01111
31054         assign { } { }
31055         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31056       attribute \src "libresoc.v:0.0-0.0"
31057       case 5'11111
31058         assign { } { }
31059         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31060       attribute \src "libresoc.v:0.0-0.0"
31061       case 5'01000
31062         assign { } { }
31063         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31064       attribute \src "libresoc.v:0.0-0.0"
31065       case 5'11000
31066         assign { } { }
31067         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31068       attribute \src "libresoc.v:0.0-0.0"
31069       case 5'00010
31070         assign { } { }
31071         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31072       attribute \src "libresoc.v:0.0-0.0"
31073       case 5'00000
31074         assign { } { }
31075         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31076       attribute \src "libresoc.v:0.0-0.0"
31077       case 5'10010
31078         assign { } { }
31079         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31080       attribute \src "libresoc.v:0.0-0.0"
31081       case 5'10000
31082         assign { } { }
31083         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31084       attribute \src "libresoc.v:0.0-0.0"
31085       case 5'00111
31086         assign { } { }
31087         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31088       attribute \src "libresoc.v:0.0-0.0"
31089       case 5'10111
31090         assign { } { }
31091         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31092       case
31093         assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00
31094     end
31095     sync always
31096       update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0]
31097   end
31098   attribute \src "libresoc.v:21488.3-21542.6"
31099   process $proc$libresoc.v:21488$478
31100     assign { } { }
31101     assign { } { }
31102     assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0]
31103     attribute \src "libresoc.v:21489.5-21489.29"
31104     switch \initial
31105       attribute \src "libresoc.v:21489.9-21489.17"
31106       case 1'1
31107       case
31108     end
31109     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
31110     switch \opcode_switch
31111       attribute \src "libresoc.v:0.0-0.0"
31112       case 5'01100
31113         assign { } { }
31114         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31115       attribute \src "libresoc.v:0.0-0.0"
31116       case 5'11100
31117         assign { } { }
31118         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31119       attribute \src "libresoc.v:0.0-0.0"
31120       case 5'01101
31121         assign { } { }
31122         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31123       attribute \src "libresoc.v:0.0-0.0"
31124       case 5'11101
31125         assign { } { }
31126         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31127       attribute \src "libresoc.v:0.0-0.0"
31128       case 5'01110
31129         assign { } { }
31130         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31131       attribute \src "libresoc.v:0.0-0.0"
31132       case 5'11110
31133         assign { } { }
31134         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31135       attribute \src "libresoc.v:0.0-0.0"
31136       case 5'01111
31137         assign { } { }
31138         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31139       attribute \src "libresoc.v:0.0-0.0"
31140       case 5'11111
31141         assign { } { }
31142         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31143       attribute \src "libresoc.v:0.0-0.0"
31144       case 5'01000
31145         assign { } { }
31146         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31147       attribute \src "libresoc.v:0.0-0.0"
31148       case 5'11000
31149         assign { } { }
31150         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31151       attribute \src "libresoc.v:0.0-0.0"
31152       case 5'00010
31153         assign { } { }
31154         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31155       attribute \src "libresoc.v:0.0-0.0"
31156       case 5'00000
31157         assign { } { }
31158         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31159       attribute \src "libresoc.v:0.0-0.0"
31160       case 5'10010
31161         assign { } { }
31162         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31163       attribute \src "libresoc.v:0.0-0.0"
31164       case 5'10000
31165         assign { } { }
31166         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31167       attribute \src "libresoc.v:0.0-0.0"
31168       case 5'00111
31169         assign { } { }
31170         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31171       attribute \src "libresoc.v:0.0-0.0"
31172       case 5'10111
31173         assign { } { }
31174         assign $1\dec31_dec_sub11_out_sel[1:0] 2'01
31175       case
31176         assign $1\dec31_dec_sub11_out_sel[1:0] 2'00
31177     end
31178     sync always
31179       update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0]
31180   end
31181   attribute \src "libresoc.v:21543.3-21597.6"
31182   process $proc$libresoc.v:21543$479
31183     assign { } { }
31184     assign { } { }
31185     assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0]
31186     attribute \src "libresoc.v:21544.5-21544.29"
31187     switch \initial
31188       attribute \src "libresoc.v:21544.9-21544.17"
31189       case 1'1
31190       case
31191     end
31192     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
31193     switch \opcode_switch
31194       attribute \src "libresoc.v:0.0-0.0"
31195       case 5'01100
31196         assign { } { }
31197         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31198       attribute \src "libresoc.v:0.0-0.0"
31199       case 5'11100
31200         assign { } { }
31201         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31202       attribute \src "libresoc.v:0.0-0.0"
31203       case 5'01101
31204         assign { } { }
31205         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31206       attribute \src "libresoc.v:0.0-0.0"
31207       case 5'11101
31208         assign { } { }
31209         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31210       attribute \src "libresoc.v:0.0-0.0"
31211       case 5'01110
31212         assign { } { }
31213         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31214       attribute \src "libresoc.v:0.0-0.0"
31215       case 5'11110
31216         assign { } { }
31217         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31218       attribute \src "libresoc.v:0.0-0.0"
31219       case 5'01111
31220         assign { } { }
31221         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31222       attribute \src "libresoc.v:0.0-0.0"
31223       case 5'11111
31224         assign { } { }
31225         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31226       attribute \src "libresoc.v:0.0-0.0"
31227       case 5'01000
31228         assign { } { }
31229         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31230       attribute \src "libresoc.v:0.0-0.0"
31231       case 5'11000
31232         assign { } { }
31233         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31234       attribute \src "libresoc.v:0.0-0.0"
31235       case 5'00010
31236         assign { } { }
31237         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31238       attribute \src "libresoc.v:0.0-0.0"
31239       case 5'00000
31240         assign { } { }
31241         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31242       attribute \src "libresoc.v:0.0-0.0"
31243       case 5'10010
31244         assign { } { }
31245         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31246       attribute \src "libresoc.v:0.0-0.0"
31247       case 5'10000
31248         assign { } { }
31249         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31250       attribute \src "libresoc.v:0.0-0.0"
31251       case 5'00111
31252         assign { } { }
31253         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31254       attribute \src "libresoc.v:0.0-0.0"
31255       case 5'10111
31256         assign { } { }
31257         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31258       case
31259         assign $1\dec31_dec_sub11_cr_in[2:0] 3'000
31260     end
31261     sync always
31262       update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0]
31263   end
31264   attribute \src "libresoc.v:21598.3-21652.6"
31265   process $proc$libresoc.v:21598$480
31266     assign { } { }
31267     assign { } { }
31268     assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0]
31269     attribute \src "libresoc.v:21599.5-21599.29"
31270     switch \initial
31271       attribute \src "libresoc.v:21599.9-21599.17"
31272       case 1'1
31273       case
31274     end
31275     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
31276     switch \opcode_switch
31277       attribute \src "libresoc.v:0.0-0.0"
31278       case 5'01100
31279         assign { } { }
31280         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31281       attribute \src "libresoc.v:0.0-0.0"
31282       case 5'11100
31283         assign { } { }
31284         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31285       attribute \src "libresoc.v:0.0-0.0"
31286       case 5'01101
31287         assign { } { }
31288         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31289       attribute \src "libresoc.v:0.0-0.0"
31290       case 5'11101
31291         assign { } { }
31292         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31293       attribute \src "libresoc.v:0.0-0.0"
31294       case 5'01110
31295         assign { } { }
31296         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31297       attribute \src "libresoc.v:0.0-0.0"
31298       case 5'11110
31299         assign { } { }
31300         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31301       attribute \src "libresoc.v:0.0-0.0"
31302       case 5'01111
31303         assign { } { }
31304         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31305       attribute \src "libresoc.v:0.0-0.0"
31306       case 5'11111
31307         assign { } { }
31308         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31309       attribute \src "libresoc.v:0.0-0.0"
31310       case 5'01000
31311         assign { } { }
31312         assign $1\dec31_dec_sub11_cr_out[2:0] 3'000
31313       attribute \src "libresoc.v:0.0-0.0"
31314       case 5'11000
31315         assign { } { }
31316         assign $1\dec31_dec_sub11_cr_out[2:0] 3'000
31317       attribute \src "libresoc.v:0.0-0.0"
31318       case 5'00010
31319         assign { } { }
31320         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31321       attribute \src "libresoc.v:0.0-0.0"
31322       case 5'00000
31323         assign { } { }
31324         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31325       attribute \src "libresoc.v:0.0-0.0"
31326       case 5'10010
31327         assign { } { }
31328         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31329       attribute \src "libresoc.v:0.0-0.0"
31330       case 5'10000
31331         assign { } { }
31332         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31333       attribute \src "libresoc.v:0.0-0.0"
31334       case 5'00111
31335         assign { } { }
31336         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31337       attribute \src "libresoc.v:0.0-0.0"
31338       case 5'10111
31339         assign { } { }
31340         assign $1\dec31_dec_sub11_cr_out[2:0] 3'001
31341       case
31342         assign $1\dec31_dec_sub11_cr_out[2:0] 3'000
31343     end
31344     sync always
31345       update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0]
31346   end
31347   connect \opcode_switch \opcode_in [10:6]
31348 end
31349 attribute \src "libresoc.v:21658.1-24389.10"
31350 attribute \cells_not_processed 1
31351 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15"
31352 attribute \generator "nMigen"
31353 module \dec31_dec_sub15
31354   attribute \src "libresoc.v:22431.3-22533.6"
31355   wire width 8 $0\dec31_dec_sub15_asmcode[7:0]
31356   attribute \src "libresoc.v:22843.3-22945.6"
31357   wire $0\dec31_dec_sub15_br[0:0]
31358   attribute \src "libresoc.v:24182.3-24284.6"
31359   wire width 3 $0\dec31_dec_sub15_cr_in[2:0]
31360   attribute \src "libresoc.v:24285.3-24387.6"
31361   wire width 3 $0\dec31_dec_sub15_cr_out[2:0]
31362   attribute \src "libresoc.v:22328.3-22430.6"
31363   wire width 2 $0\dec31_dec_sub15_cry_in[1:0]
31364   attribute \src "libresoc.v:22740.3-22842.6"
31365   wire $0\dec31_dec_sub15_cry_out[0:0]
31366   attribute \src "libresoc.v:23667.3-23769.6"
31367   wire width 5 $0\dec31_dec_sub15_form[4:0]
31368   attribute \src "libresoc.v:21916.3-22018.6"
31369   wire width 12 $0\dec31_dec_sub15_function_unit[11:0]
31370   attribute \src "libresoc.v:23770.3-23872.6"
31371   wire width 3 $0\dec31_dec_sub15_in1_sel[2:0]
31372   attribute \src "libresoc.v:23873.3-23975.6"
31373   wire width 4 $0\dec31_dec_sub15_in2_sel[3:0]
31374   attribute \src "libresoc.v:23976.3-24078.6"
31375   wire width 2 $0\dec31_dec_sub15_in3_sel[1:0]
31376   attribute \src "libresoc.v:23049.3-23151.6"
31377   wire width 7 $0\dec31_dec_sub15_internal_op[6:0]
31378   attribute \src "libresoc.v:22534.3-22636.6"
31379   wire $0\dec31_dec_sub15_inv_a[0:0]
31380   attribute \src "libresoc.v:22637.3-22739.6"
31381   wire $0\dec31_dec_sub15_inv_out[0:0]
31382   attribute \src "libresoc.v:23255.3-23357.6"
31383   wire $0\dec31_dec_sub15_is_32b[0:0]
31384   attribute \src "libresoc.v:22019.3-22121.6"
31385   wire width 4 $0\dec31_dec_sub15_ldst_len[3:0]
31386   attribute \src "libresoc.v:23461.3-23563.6"
31387   wire $0\dec31_dec_sub15_lk[0:0]
31388   attribute \src "libresoc.v:24079.3-24181.6"
31389   wire width 2 $0\dec31_dec_sub15_out_sel[1:0]
31390   attribute \src "libresoc.v:22225.3-22327.6"
31391   wire width 2 $0\dec31_dec_sub15_rc_sel[1:0]
31392   attribute \src "libresoc.v:23152.3-23254.6"
31393   wire $0\dec31_dec_sub15_rsrv[0:0]
31394   attribute \src "libresoc.v:23564.3-23666.6"
31395   wire $0\dec31_dec_sub15_sgl_pipe[0:0]
31396   attribute \src "libresoc.v:23358.3-23460.6"
31397   wire $0\dec31_dec_sub15_sgn[0:0]
31398   attribute \src "libresoc.v:22946.3-23048.6"
31399   wire $0\dec31_dec_sub15_sgn_ext[0:0]
31400   attribute \src "libresoc.v:22122.3-22224.6"
31401   wire width 2 $0\dec31_dec_sub15_upd[1:0]
31402   attribute \src "libresoc.v:21659.7-21659.20"
31403   wire $0\initial[0:0]
31404   attribute \src "libresoc.v:22431.3-22533.6"
31405   wire width 8 $1\dec31_dec_sub15_asmcode[7:0]
31406   attribute \src "libresoc.v:22843.3-22945.6"
31407   wire $1\dec31_dec_sub15_br[0:0]
31408   attribute \src "libresoc.v:24182.3-24284.6"
31409   wire width 3 $1\dec31_dec_sub15_cr_in[2:0]
31410   attribute \src "libresoc.v:24285.3-24387.6"
31411   wire width 3 $1\dec31_dec_sub15_cr_out[2:0]
31412   attribute \src "libresoc.v:22328.3-22430.6"
31413   wire width 2 $1\dec31_dec_sub15_cry_in[1:0]
31414   attribute \src "libresoc.v:22740.3-22842.6"
31415   wire $1\dec31_dec_sub15_cry_out[0:0]
31416   attribute \src "libresoc.v:23667.3-23769.6"
31417   wire width 5 $1\dec31_dec_sub15_form[4:0]
31418   attribute \src "libresoc.v:21916.3-22018.6"
31419   wire width 12 $1\dec31_dec_sub15_function_unit[11:0]
31420   attribute \src "libresoc.v:23770.3-23872.6"
31421   wire width 3 $1\dec31_dec_sub15_in1_sel[2:0]
31422   attribute \src "libresoc.v:23873.3-23975.6"
31423   wire width 4 $1\dec31_dec_sub15_in2_sel[3:0]
31424   attribute \src "libresoc.v:23976.3-24078.6"
31425   wire width 2 $1\dec31_dec_sub15_in3_sel[1:0]
31426   attribute \src "libresoc.v:23049.3-23151.6"
31427   wire width 7 $1\dec31_dec_sub15_internal_op[6:0]
31428   attribute \src "libresoc.v:22534.3-22636.6"
31429   wire $1\dec31_dec_sub15_inv_a[0:0]
31430   attribute \src "libresoc.v:22637.3-22739.6"
31431   wire $1\dec31_dec_sub15_inv_out[0:0]
31432   attribute \src "libresoc.v:23255.3-23357.6"
31433   wire $1\dec31_dec_sub15_is_32b[0:0]
31434   attribute \src "libresoc.v:22019.3-22121.6"
31435   wire width 4 $1\dec31_dec_sub15_ldst_len[3:0]
31436   attribute \src "libresoc.v:23461.3-23563.6"
31437   wire $1\dec31_dec_sub15_lk[0:0]
31438   attribute \src "libresoc.v:24079.3-24181.6"
31439   wire width 2 $1\dec31_dec_sub15_out_sel[1:0]
31440   attribute \src "libresoc.v:22225.3-22327.6"
31441   wire width 2 $1\dec31_dec_sub15_rc_sel[1:0]
31442   attribute \src "libresoc.v:23152.3-23254.6"
31443   wire $1\dec31_dec_sub15_rsrv[0:0]
31444   attribute \src "libresoc.v:23564.3-23666.6"
31445   wire $1\dec31_dec_sub15_sgl_pipe[0:0]
31446   attribute \src "libresoc.v:23358.3-23460.6"
31447   wire $1\dec31_dec_sub15_sgn[0:0]
31448   attribute \src "libresoc.v:22946.3-23048.6"
31449   wire $1\dec31_dec_sub15_sgn_ext[0:0]
31450   attribute \src "libresoc.v:22122.3-22224.6"
31451   wire width 2 $1\dec31_dec_sub15_upd[1:0]
31452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31453   wire width 8 output 4 \dec31_dec_sub15_asmcode
31454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31455   wire output 18 \dec31_dec_sub15_br
31456   attribute \enum_base_type "CRInSel"
31457   attribute \enum_value_000 "NONE"
31458   attribute \enum_value_001 "CR0"
31459   attribute \enum_value_010 "BI"
31460   attribute \enum_value_011 "BFA"
31461   attribute \enum_value_100 "BA_BB"
31462   attribute \enum_value_101 "BC"
31463   attribute \enum_value_110 "WHOLE_REG"
31464   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31465   wire width 3 output 9 \dec31_dec_sub15_cr_in
31466   attribute \enum_base_type "CROutSel"
31467   attribute \enum_value_000 "NONE"
31468   attribute \enum_value_001 "CR0"
31469   attribute \enum_value_010 "BF"
31470   attribute \enum_value_011 "BT"
31471   attribute \enum_value_100 "WHOLE_REG"
31472   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31473   wire width 3 output 10 \dec31_dec_sub15_cr_out
31474   attribute \enum_base_type "CryIn"
31475   attribute \enum_value_00 "ZERO"
31476   attribute \enum_value_01 "ONE"
31477   attribute \enum_value_10 "CA"
31478   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31479   wire width 2 output 14 \dec31_dec_sub15_cry_in
31480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31481   wire output 17 \dec31_dec_sub15_cry_out
31482   attribute \enum_base_type "Form"
31483   attribute \enum_value_00000 "NONE"
31484   attribute \enum_value_00001 "I"
31485   attribute \enum_value_00010 "B"
31486   attribute \enum_value_00011 "SC"
31487   attribute \enum_value_00100 "D"
31488   attribute \enum_value_00101 "DS"
31489   attribute \enum_value_00110 "DQ"
31490   attribute \enum_value_00111 "DX"
31491   attribute \enum_value_01000 "X"
31492   attribute \enum_value_01001 "XL"
31493   attribute \enum_value_01010 "XFX"
31494   attribute \enum_value_01011 "XFL"
31495   attribute \enum_value_01100 "XX1"
31496   attribute \enum_value_01101 "XX2"
31497   attribute \enum_value_01110 "XX3"
31498   attribute \enum_value_01111 "XX4"
31499   attribute \enum_value_10000 "XS"
31500   attribute \enum_value_10001 "XO"
31501   attribute \enum_value_10010 "A"
31502   attribute \enum_value_10011 "M"
31503   attribute \enum_value_10100 "MD"
31504   attribute \enum_value_10101 "MDS"
31505   attribute \enum_value_10110 "VA"
31506   attribute \enum_value_10111 "VC"
31507   attribute \enum_value_11000 "VX"
31508   attribute \enum_value_11001 "EVX"
31509   attribute \enum_value_11010 "EVS"
31510   attribute \enum_value_11011 "Z22"
31511   attribute \enum_value_11100 "Z23"
31512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31513   wire width 5 output 3 \dec31_dec_sub15_form
31514   attribute \enum_base_type "Function"
31515   attribute \enum_value_000000000000 "NONE"
31516   attribute \enum_value_000000000010 "ALU"
31517   attribute \enum_value_000000000100 "LDST"
31518   attribute \enum_value_000000001000 "SHIFT_ROT"
31519   attribute \enum_value_000000010000 "LOGICAL"
31520   attribute \enum_value_000000100000 "BRANCH"
31521   attribute \enum_value_000001000000 "CR"
31522   attribute \enum_value_000010000000 "TRAP"
31523   attribute \enum_value_000100000000 "MUL"
31524   attribute \enum_value_001000000000 "DIV"
31525   attribute \enum_value_010000000000 "SPR"
31526   attribute \enum_value_100000000000 "MMU"
31527   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31528   wire width 12 output 1 \dec31_dec_sub15_function_unit
31529   attribute \enum_base_type "In1Sel"
31530   attribute \enum_value_000 "NONE"
31531   attribute \enum_value_001 "RA"
31532   attribute \enum_value_010 "RA_OR_ZERO"
31533   attribute \enum_value_011 "SPR"
31534   attribute \enum_value_100 "RS"
31535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31536   wire width 3 output 5 \dec31_dec_sub15_in1_sel
31537   attribute \enum_base_type "In2Sel"
31538   attribute \enum_value_0000 "NONE"
31539   attribute \enum_value_0001 "RB"
31540   attribute \enum_value_0010 "CONST_UI"
31541   attribute \enum_value_0011 "CONST_SI"
31542   attribute \enum_value_0100 "CONST_UI_HI"
31543   attribute \enum_value_0101 "CONST_SI_HI"
31544   attribute \enum_value_0110 "CONST_LI"
31545   attribute \enum_value_0111 "CONST_BD"
31546   attribute \enum_value_1000 "CONST_DS"
31547   attribute \enum_value_1001 "CONST_M1"
31548   attribute \enum_value_1010 "CONST_SH"
31549   attribute \enum_value_1011 "CONST_SH32"
31550   attribute \enum_value_1100 "SPR"
31551   attribute \enum_value_1101 "RS"
31552   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31553   wire width 4 output 6 \dec31_dec_sub15_in2_sel
31554   attribute \enum_base_type "In3Sel"
31555   attribute \enum_value_00 "NONE"
31556   attribute \enum_value_01 "RS"
31557   attribute \enum_value_10 "RB"
31558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31559   wire width 2 output 7 \dec31_dec_sub15_in3_sel
31560   attribute \enum_base_type "MicrOp"
31561   attribute \enum_value_0000000 "OP_ILLEGAL"
31562   attribute \enum_value_0000001 "OP_NOP"
31563   attribute \enum_value_0000010 "OP_ADD"
31564   attribute \enum_value_0000011 "OP_ADDPCIS"
31565   attribute \enum_value_0000100 "OP_AND"
31566   attribute \enum_value_0000101 "OP_ATTN"
31567   attribute \enum_value_0000110 "OP_B"
31568   attribute \enum_value_0000111 "OP_BC"
31569   attribute \enum_value_0001000 "OP_BCREG"
31570   attribute \enum_value_0001001 "OP_BPERM"
31571   attribute \enum_value_0001010 "OP_CMP"
31572   attribute \enum_value_0001011 "OP_CMPB"
31573   attribute \enum_value_0001100 "OP_CMPEQB"
31574   attribute \enum_value_0001101 "OP_CMPRB"
31575   attribute \enum_value_0001110 "OP_CNTZ"
31576   attribute \enum_value_0001111 "OP_CRAND"
31577   attribute \enum_value_0010000 "OP_CRANDC"
31578   attribute \enum_value_0010001 "OP_CREQV"
31579   attribute \enum_value_0010010 "OP_CRNAND"
31580   attribute \enum_value_0010011 "OP_CRNOR"
31581   attribute \enum_value_0010100 "OP_CROR"
31582   attribute \enum_value_0010101 "OP_CRORC"
31583   attribute \enum_value_0010110 "OP_CRXOR"
31584   attribute \enum_value_0010111 "OP_DARN"
31585   attribute \enum_value_0011000 "OP_DCBF"
31586   attribute \enum_value_0011001 "OP_DCBST"
31587   attribute \enum_value_0011010 "OP_DCBT"
31588   attribute \enum_value_0011011 "OP_DCBTST"
31589   attribute \enum_value_0011100 "OP_DCBZ"
31590   attribute \enum_value_0011101 "OP_DIV"
31591   attribute \enum_value_0011110 "OP_DIVE"
31592   attribute \enum_value_0011111 "OP_EXTS"
31593   attribute \enum_value_0100000 "OP_EXTSWSLI"
31594   attribute \enum_value_0100001 "OP_ICBI"
31595   attribute \enum_value_0100010 "OP_ICBT"
31596   attribute \enum_value_0100011 "OP_ISEL"
31597   attribute \enum_value_0100100 "OP_ISYNC"
31598   attribute \enum_value_0100101 "OP_LOAD"
31599   attribute \enum_value_0100110 "OP_STORE"
31600   attribute \enum_value_0100111 "OP_MADDHD"
31601   attribute \enum_value_0101000 "OP_MADDHDU"
31602   attribute \enum_value_0101001 "OP_MADDLD"
31603   attribute \enum_value_0101010 "OP_MCRF"
31604   attribute \enum_value_0101011 "OP_MCRXR"
31605   attribute \enum_value_0101100 "OP_MCRXRX"
31606   attribute \enum_value_0101101 "OP_MFCR"
31607   attribute \enum_value_0101110 "OP_MFSPR"
31608   attribute \enum_value_0101111 "OP_MOD"
31609   attribute \enum_value_0110000 "OP_MTCRF"
31610   attribute \enum_value_0110001 "OP_MTSPR"
31611   attribute \enum_value_0110010 "OP_MUL_L64"
31612   attribute \enum_value_0110011 "OP_MUL_H64"
31613   attribute \enum_value_0110100 "OP_MUL_H32"
31614   attribute \enum_value_0110101 "OP_OR"
31615   attribute \enum_value_0110110 "OP_POPCNT"
31616   attribute \enum_value_0110111 "OP_PRTY"
31617   attribute \enum_value_0111000 "OP_RLC"
31618   attribute \enum_value_0111001 "OP_RLCL"
31619   attribute \enum_value_0111010 "OP_RLCR"
31620   attribute \enum_value_0111011 "OP_SETB"
31621   attribute \enum_value_0111100 "OP_SHL"
31622   attribute \enum_value_0111101 "OP_SHR"
31623   attribute \enum_value_0111110 "OP_SYNC"
31624   attribute \enum_value_0111111 "OP_TRAP"
31625   attribute \enum_value_1000011 "OP_XOR"
31626   attribute \enum_value_1000100 "OP_SIM_CONFIG"
31627   attribute \enum_value_1000101 "OP_CROP"
31628   attribute \enum_value_1000110 "OP_RFID"
31629   attribute \enum_value_1000111 "OP_MFMSR"
31630   attribute \enum_value_1001000 "OP_MTMSRD"
31631   attribute \enum_value_1001001 "OP_SC"
31632   attribute \enum_value_1001010 "OP_MTMSR"
31633   attribute \enum_value_1001011 "OP_TLBIE"
31634   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31635   wire width 7 output 2 \dec31_dec_sub15_internal_op
31636   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31637   wire output 15 \dec31_dec_sub15_inv_a
31638   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31639   wire output 16 \dec31_dec_sub15_inv_out
31640   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31641   wire output 21 \dec31_dec_sub15_is_32b
31642   attribute \enum_base_type "LdstLen"
31643   attribute \enum_value_0000 "NONE"
31644   attribute \enum_value_0001 "is1B"
31645   attribute \enum_value_0010 "is2B"
31646   attribute \enum_value_0100 "is4B"
31647   attribute \enum_value_1000 "is8B"
31648   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31649   wire width 4 output 11 \dec31_dec_sub15_ldst_len
31650   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31651   wire output 23 \dec31_dec_sub15_lk
31652   attribute \enum_base_type "OutSel"
31653   attribute \enum_value_00 "NONE"
31654   attribute \enum_value_01 "RT"
31655   attribute \enum_value_10 "RA"
31656   attribute \enum_value_11 "SPR"
31657   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31658   wire width 2 output 8 \dec31_dec_sub15_out_sel
31659   attribute \enum_base_type "RC"
31660   attribute \enum_value_00 "NONE"
31661   attribute \enum_value_01 "ONE"
31662   attribute \enum_value_10 "RC"
31663   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31664   wire width 2 output 13 \dec31_dec_sub15_rc_sel
31665   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31666   wire output 20 \dec31_dec_sub15_rsrv
31667   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31668   wire output 24 \dec31_dec_sub15_sgl_pipe
31669   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31670   wire output 22 \dec31_dec_sub15_sgn
31671   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
31672   wire output 19 \dec31_dec_sub15_sgn_ext
31673   attribute \enum_base_type "LDSTMode"
31674   attribute \enum_value_00 "NONE"
31675   attribute \enum_value_01 "update"
31676   attribute \enum_value_10 "cix"
31677   attribute \enum_value_11 "cx"
31678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
31679   wire width 2 output 12 \dec31_dec_sub15_upd
31680   attribute \src "libresoc.v:21659.7-21659.15"
31681   wire \initial
31682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
31683   wire width 32 input 25 \opcode_in
31684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
31685   wire width 5 \opcode_switch
31686   attribute \src "libresoc.v:21659.7-21659.20"
31687   process $proc$libresoc.v:21659$506
31688     assign { } { }
31689     assign $0\initial[0:0] 1'0
31690     sync always
31691       update \initial $0\initial[0:0]
31692     sync init
31693   end
31694   attribute \src "libresoc.v:21916.3-22018.6"
31695   process $proc$libresoc.v:21916$482
31696     assign { } { }
31697     assign { } { }
31698     assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0]
31699     attribute \src "libresoc.v:21917.5-21917.29"
31700     switch \initial
31701       attribute \src "libresoc.v:21917.9-21917.17"
31702       case 1'1
31703       case
31704     end
31705     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
31706     switch \opcode_switch
31707       attribute \src "libresoc.v:0.0-0.0"
31708       case 5'00000
31709         assign { } { }
31710         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31711       attribute \src "libresoc.v:0.0-0.0"
31712       case 5'00001
31713         assign { } { }
31714         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31715       attribute \src "libresoc.v:0.0-0.0"
31716       case 5'00010
31717         assign { } { }
31718         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31719       attribute \src "libresoc.v:0.0-0.0"
31720       case 5'00011
31721         assign { } { }
31722         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31723       attribute \src "libresoc.v:0.0-0.0"
31724       case 5'00100
31725         assign { } { }
31726         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31727       attribute \src "libresoc.v:0.0-0.0"
31728       case 5'00101
31729         assign { } { }
31730         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31731       attribute \src "libresoc.v:0.0-0.0"
31732       case 5'00110
31733         assign { } { }
31734         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31735       attribute \src "libresoc.v:0.0-0.0"
31736       case 5'00111
31737         assign { } { }
31738         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31739       attribute \src "libresoc.v:0.0-0.0"
31740       case 5'01000
31741         assign { } { }
31742         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31743       attribute \src "libresoc.v:0.0-0.0"
31744       case 5'01001
31745         assign { } { }
31746         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31747       attribute \src "libresoc.v:0.0-0.0"
31748       case 5'01010
31749         assign { } { }
31750         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31751       attribute \src "libresoc.v:0.0-0.0"
31752       case 5'01011
31753         assign { } { }
31754         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31755       attribute \src "libresoc.v:0.0-0.0"
31756       case 5'01100
31757         assign { } { }
31758         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31759       attribute \src "libresoc.v:0.0-0.0"
31760       case 5'01101
31761         assign { } { }
31762         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31763       attribute \src "libresoc.v:0.0-0.0"
31764       case 5'01110
31765         assign { } { }
31766         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31767       attribute \src "libresoc.v:0.0-0.0"
31768       case 5'01111
31769         assign { } { }
31770         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31771       attribute \src "libresoc.v:0.0-0.0"
31772       case 5'10000
31773         assign { } { }
31774         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31775       attribute \src "libresoc.v:0.0-0.0"
31776       case 5'10001
31777         assign { } { }
31778         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31779       attribute \src "libresoc.v:0.0-0.0"
31780       case 5'10010
31781         assign { } { }
31782         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31783       attribute \src "libresoc.v:0.0-0.0"
31784       case 5'10011
31785         assign { } { }
31786         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31787       attribute \src "libresoc.v:0.0-0.0"
31788       case 5'10100
31789         assign { } { }
31790         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31791       attribute \src "libresoc.v:0.0-0.0"
31792       case 5'10101
31793         assign { } { }
31794         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31795       attribute \src "libresoc.v:0.0-0.0"
31796       case 5'10110
31797         assign { } { }
31798         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31799       attribute \src "libresoc.v:0.0-0.0"
31800       case 5'10111
31801         assign { } { }
31802         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31803       attribute \src "libresoc.v:0.0-0.0"
31804       case 5'11000
31805         assign { } { }
31806         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31807       attribute \src "libresoc.v:0.0-0.0"
31808       case 5'11001
31809         assign { } { }
31810         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31811       attribute \src "libresoc.v:0.0-0.0"
31812       case 5'11010
31813         assign { } { }
31814         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31815       attribute \src "libresoc.v:0.0-0.0"
31816       case 5'11011
31817         assign { } { }
31818         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31819       attribute \src "libresoc.v:0.0-0.0"
31820       case 5'11100
31821         assign { } { }
31822         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31823       attribute \src "libresoc.v:0.0-0.0"
31824       case 5'11101
31825         assign { } { }
31826         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31827       attribute \src "libresoc.v:0.0-0.0"
31828       case 5'11110
31829         assign { } { }
31830         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31831       attribute \src "libresoc.v:0.0-0.0"
31832       case 5'11111
31833         assign { } { }
31834         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000
31835       case
31836         assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000
31837     end
31838     sync always
31839       update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0]
31840   end
31841   attribute \src "libresoc.v:22019.3-22121.6"
31842   process $proc$libresoc.v:22019$483
31843     assign { } { }
31844     assign { } { }
31845     assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0]
31846     attribute \src "libresoc.v:22020.5-22020.29"
31847     switch \initial
31848       attribute \src "libresoc.v:22020.9-22020.17"
31849       case 1'1
31850       case
31851     end
31852     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
31853     switch \opcode_switch
31854       attribute \src "libresoc.v:0.0-0.0"
31855       case 5'00000
31856         assign { } { }
31857         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31858       attribute \src "libresoc.v:0.0-0.0"
31859       case 5'00001
31860         assign { } { }
31861         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31862       attribute \src "libresoc.v:0.0-0.0"
31863       case 5'00010
31864         assign { } { }
31865         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31866       attribute \src "libresoc.v:0.0-0.0"
31867       case 5'00011
31868         assign { } { }
31869         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31870       attribute \src "libresoc.v:0.0-0.0"
31871       case 5'00100
31872         assign { } { }
31873         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31874       attribute \src "libresoc.v:0.0-0.0"
31875       case 5'00101
31876         assign { } { }
31877         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31878       attribute \src "libresoc.v:0.0-0.0"
31879       case 5'00110
31880         assign { } { }
31881         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31882       attribute \src "libresoc.v:0.0-0.0"
31883       case 5'00111
31884         assign { } { }
31885         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31886       attribute \src "libresoc.v:0.0-0.0"
31887       case 5'01000
31888         assign { } { }
31889         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31890       attribute \src "libresoc.v:0.0-0.0"
31891       case 5'01001
31892         assign { } { }
31893         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31894       attribute \src "libresoc.v:0.0-0.0"
31895       case 5'01010
31896         assign { } { }
31897         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31898       attribute \src "libresoc.v:0.0-0.0"
31899       case 5'01011
31900         assign { } { }
31901         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31902       attribute \src "libresoc.v:0.0-0.0"
31903       case 5'01100
31904         assign { } { }
31905         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31906       attribute \src "libresoc.v:0.0-0.0"
31907       case 5'01101
31908         assign { } { }
31909         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31910       attribute \src "libresoc.v:0.0-0.0"
31911       case 5'01110
31912         assign { } { }
31913         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31914       attribute \src "libresoc.v:0.0-0.0"
31915       case 5'01111
31916         assign { } { }
31917         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31918       attribute \src "libresoc.v:0.0-0.0"
31919       case 5'10000
31920         assign { } { }
31921         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31922       attribute \src "libresoc.v:0.0-0.0"
31923       case 5'10001
31924         assign { } { }
31925         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31926       attribute \src "libresoc.v:0.0-0.0"
31927       case 5'10010
31928         assign { } { }
31929         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31930       attribute \src "libresoc.v:0.0-0.0"
31931       case 5'10011
31932         assign { } { }
31933         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31934       attribute \src "libresoc.v:0.0-0.0"
31935       case 5'10100
31936         assign { } { }
31937         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31938       attribute \src "libresoc.v:0.0-0.0"
31939       case 5'10101
31940         assign { } { }
31941         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31942       attribute \src "libresoc.v:0.0-0.0"
31943       case 5'10110
31944         assign { } { }
31945         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31946       attribute \src "libresoc.v:0.0-0.0"
31947       case 5'10111
31948         assign { } { }
31949         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31950       attribute \src "libresoc.v:0.0-0.0"
31951       case 5'11000
31952         assign { } { }
31953         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31954       attribute \src "libresoc.v:0.0-0.0"
31955       case 5'11001
31956         assign { } { }
31957         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31958       attribute \src "libresoc.v:0.0-0.0"
31959       case 5'11010
31960         assign { } { }
31961         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31962       attribute \src "libresoc.v:0.0-0.0"
31963       case 5'11011
31964         assign { } { }
31965         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31966       attribute \src "libresoc.v:0.0-0.0"
31967       case 5'11100
31968         assign { } { }
31969         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31970       attribute \src "libresoc.v:0.0-0.0"
31971       case 5'11101
31972         assign { } { }
31973         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31974       attribute \src "libresoc.v:0.0-0.0"
31975       case 5'11110
31976         assign { } { }
31977         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31978       attribute \src "libresoc.v:0.0-0.0"
31979       case 5'11111
31980         assign { } { }
31981         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31982       case
31983         assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000
31984     end
31985     sync always
31986       update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0]
31987   end
31988   attribute \src "libresoc.v:22122.3-22224.6"
31989   process $proc$libresoc.v:22122$484
31990     assign { } { }
31991     assign { } { }
31992     assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0]
31993     attribute \src "libresoc.v:22123.5-22123.29"
31994     switch \initial
31995       attribute \src "libresoc.v:22123.9-22123.17"
31996       case 1'1
31997       case
31998     end
31999     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
32000     switch \opcode_switch
32001       attribute \src "libresoc.v:0.0-0.0"
32002       case 5'00000
32003         assign { } { }
32004         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32005       attribute \src "libresoc.v:0.0-0.0"
32006       case 5'00001
32007         assign { } { }
32008         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32009       attribute \src "libresoc.v:0.0-0.0"
32010       case 5'00010
32011         assign { } { }
32012         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32013       attribute \src "libresoc.v:0.0-0.0"
32014       case 5'00011
32015         assign { } { }
32016         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32017       attribute \src "libresoc.v:0.0-0.0"
32018       case 5'00100
32019         assign { } { }
32020         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32021       attribute \src "libresoc.v:0.0-0.0"
32022       case 5'00101
32023         assign { } { }
32024         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32025       attribute \src "libresoc.v:0.0-0.0"
32026       case 5'00110
32027         assign { } { }
32028         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32029       attribute \src "libresoc.v:0.0-0.0"
32030       case 5'00111
32031         assign { } { }
32032         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32033       attribute \src "libresoc.v:0.0-0.0"
32034       case 5'01000
32035         assign { } { }
32036         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32037       attribute \src "libresoc.v:0.0-0.0"
32038       case 5'01001
32039         assign { } { }
32040         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32041       attribute \src "libresoc.v:0.0-0.0"
32042       case 5'01010
32043         assign { } { }
32044         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32045       attribute \src "libresoc.v:0.0-0.0"
32046       case 5'01011
32047         assign { } { }
32048         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32049       attribute \src "libresoc.v:0.0-0.0"
32050       case 5'01100
32051         assign { } { }
32052         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32053       attribute \src "libresoc.v:0.0-0.0"
32054       case 5'01101
32055         assign { } { }
32056         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32057       attribute \src "libresoc.v:0.0-0.0"
32058       case 5'01110
32059         assign { } { }
32060         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32061       attribute \src "libresoc.v:0.0-0.0"
32062       case 5'01111
32063         assign { } { }
32064         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32065       attribute \src "libresoc.v:0.0-0.0"
32066       case 5'10000
32067         assign { } { }
32068         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32069       attribute \src "libresoc.v:0.0-0.0"
32070       case 5'10001
32071         assign { } { }
32072         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32073       attribute \src "libresoc.v:0.0-0.0"
32074       case 5'10010
32075         assign { } { }
32076         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32077       attribute \src "libresoc.v:0.0-0.0"
32078       case 5'10011
32079         assign { } { }
32080         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32081       attribute \src "libresoc.v:0.0-0.0"
32082       case 5'10100
32083         assign { } { }
32084         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32085       attribute \src "libresoc.v:0.0-0.0"
32086       case 5'10101
32087         assign { } { }
32088         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32089       attribute \src "libresoc.v:0.0-0.0"
32090       case 5'10110
32091         assign { } { }
32092         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32093       attribute \src "libresoc.v:0.0-0.0"
32094       case 5'10111
32095         assign { } { }
32096         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32097       attribute \src "libresoc.v:0.0-0.0"
32098       case 5'11000
32099         assign { } { }
32100         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32101       attribute \src "libresoc.v:0.0-0.0"
32102       case 5'11001
32103         assign { } { }
32104         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32105       attribute \src "libresoc.v:0.0-0.0"
32106       case 5'11010
32107         assign { } { }
32108         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32109       attribute \src "libresoc.v:0.0-0.0"
32110       case 5'11011
32111         assign { } { }
32112         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32113       attribute \src "libresoc.v:0.0-0.0"
32114       case 5'11100
32115         assign { } { }
32116         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32117       attribute \src "libresoc.v:0.0-0.0"
32118       case 5'11101
32119         assign { } { }
32120         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32121       attribute \src "libresoc.v:0.0-0.0"
32122       case 5'11110
32123         assign { } { }
32124         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32125       attribute \src "libresoc.v:0.0-0.0"
32126       case 5'11111
32127         assign { } { }
32128         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32129       case
32130         assign $1\dec31_dec_sub15_upd[1:0] 2'00
32131     end
32132     sync always
32133       update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0]
32134   end
32135   attribute \src "libresoc.v:22225.3-22327.6"
32136   process $proc$libresoc.v:22225$485
32137     assign { } { }
32138     assign { } { }
32139     assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0]
32140     attribute \src "libresoc.v:22226.5-22226.29"
32141     switch \initial
32142       attribute \src "libresoc.v:22226.9-22226.17"
32143       case 1'1
32144       case
32145     end
32146     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
32147     switch \opcode_switch
32148       attribute \src "libresoc.v:0.0-0.0"
32149       case 5'00000
32150         assign { } { }
32151         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32152       attribute \src "libresoc.v:0.0-0.0"
32153       case 5'00001
32154         assign { } { }
32155         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32156       attribute \src "libresoc.v:0.0-0.0"
32157       case 5'00010
32158         assign { } { }
32159         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32160       attribute \src "libresoc.v:0.0-0.0"
32161       case 5'00011
32162         assign { } { }
32163         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32164       attribute \src "libresoc.v:0.0-0.0"
32165       case 5'00100
32166         assign { } { }
32167         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32168       attribute \src "libresoc.v:0.0-0.0"
32169       case 5'00101
32170         assign { } { }
32171         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32172       attribute \src "libresoc.v:0.0-0.0"
32173       case 5'00110
32174         assign { } { }
32175         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32176       attribute \src "libresoc.v:0.0-0.0"
32177       case 5'00111
32178         assign { } { }
32179         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32180       attribute \src "libresoc.v:0.0-0.0"
32181       case 5'01000
32182         assign { } { }
32183         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32184       attribute \src "libresoc.v:0.0-0.0"
32185       case 5'01001
32186         assign { } { }
32187         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32188       attribute \src "libresoc.v:0.0-0.0"
32189       case 5'01010
32190         assign { } { }
32191         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32192       attribute \src "libresoc.v:0.0-0.0"
32193       case 5'01011
32194         assign { } { }
32195         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32196       attribute \src "libresoc.v:0.0-0.0"
32197       case 5'01100
32198         assign { } { }
32199         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32200       attribute \src "libresoc.v:0.0-0.0"
32201       case 5'01101
32202         assign { } { }
32203         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32204       attribute \src "libresoc.v:0.0-0.0"
32205       case 5'01110
32206         assign { } { }
32207         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32208       attribute \src "libresoc.v:0.0-0.0"
32209       case 5'01111
32210         assign { } { }
32211         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32212       attribute \src "libresoc.v:0.0-0.0"
32213       case 5'10000
32214         assign { } { }
32215         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32216       attribute \src "libresoc.v:0.0-0.0"
32217       case 5'10001
32218         assign { } { }
32219         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32220       attribute \src "libresoc.v:0.0-0.0"
32221       case 5'10010
32222         assign { } { }
32223         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32224       attribute \src "libresoc.v:0.0-0.0"
32225       case 5'10011
32226         assign { } { }
32227         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32228       attribute \src "libresoc.v:0.0-0.0"
32229       case 5'10100
32230         assign { } { }
32231         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32232       attribute \src "libresoc.v:0.0-0.0"
32233       case 5'10101
32234         assign { } { }
32235         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32236       attribute \src "libresoc.v:0.0-0.0"
32237       case 5'10110
32238         assign { } { }
32239         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32240       attribute \src "libresoc.v:0.0-0.0"
32241       case 5'10111
32242         assign { } { }
32243         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32244       attribute \src "libresoc.v:0.0-0.0"
32245       case 5'11000
32246         assign { } { }
32247         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32248       attribute \src "libresoc.v:0.0-0.0"
32249       case 5'11001
32250         assign { } { }
32251         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32252       attribute \src "libresoc.v:0.0-0.0"
32253       case 5'11010
32254         assign { } { }
32255         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32256       attribute \src "libresoc.v:0.0-0.0"
32257       case 5'11011
32258         assign { } { }
32259         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32260       attribute \src "libresoc.v:0.0-0.0"
32261       case 5'11100
32262         assign { } { }
32263         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32264       attribute \src "libresoc.v:0.0-0.0"
32265       case 5'11101
32266         assign { } { }
32267         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32268       attribute \src "libresoc.v:0.0-0.0"
32269       case 5'11110
32270         assign { } { }
32271         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32272       attribute \src "libresoc.v:0.0-0.0"
32273       case 5'11111
32274         assign { } { }
32275         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32276       case
32277         assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00
32278     end
32279     sync always
32280       update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0]
32281   end
32282   attribute \src "libresoc.v:22328.3-22430.6"
32283   process $proc$libresoc.v:22328$486
32284     assign { } { }
32285     assign { } { }
32286     assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0]
32287     attribute \src "libresoc.v:22329.5-22329.29"
32288     switch \initial
32289       attribute \src "libresoc.v:22329.9-22329.17"
32290       case 1'1
32291       case
32292     end
32293     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
32294     switch \opcode_switch
32295       attribute \src "libresoc.v:0.0-0.0"
32296       case 5'00000
32297         assign { } { }
32298         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32299       attribute \src "libresoc.v:0.0-0.0"
32300       case 5'00001
32301         assign { } { }
32302         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32303       attribute \src "libresoc.v:0.0-0.0"
32304       case 5'00010
32305         assign { } { }
32306         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32307       attribute \src "libresoc.v:0.0-0.0"
32308       case 5'00011
32309         assign { } { }
32310         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32311       attribute \src "libresoc.v:0.0-0.0"
32312       case 5'00100
32313         assign { } { }
32314         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32315       attribute \src "libresoc.v:0.0-0.0"
32316       case 5'00101
32317         assign { } { }
32318         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32319       attribute \src "libresoc.v:0.0-0.0"
32320       case 5'00110
32321         assign { } { }
32322         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32323       attribute \src "libresoc.v:0.0-0.0"
32324       case 5'00111
32325         assign { } { }
32326         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32327       attribute \src "libresoc.v:0.0-0.0"
32328       case 5'01000
32329         assign { } { }
32330         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32331       attribute \src "libresoc.v:0.0-0.0"
32332       case 5'01001
32333         assign { } { }
32334         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32335       attribute \src "libresoc.v:0.0-0.0"
32336       case 5'01010
32337         assign { } { }
32338         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32339       attribute \src "libresoc.v:0.0-0.0"
32340       case 5'01011
32341         assign { } { }
32342         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32343       attribute \src "libresoc.v:0.0-0.0"
32344       case 5'01100
32345         assign { } { }
32346         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32347       attribute \src "libresoc.v:0.0-0.0"
32348       case 5'01101
32349         assign { } { }
32350         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32351       attribute \src "libresoc.v:0.0-0.0"
32352       case 5'01110
32353         assign { } { }
32354         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32355       attribute \src "libresoc.v:0.0-0.0"
32356       case 5'01111
32357         assign { } { }
32358         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32359       attribute \src "libresoc.v:0.0-0.0"
32360       case 5'10000
32361         assign { } { }
32362         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32363       attribute \src "libresoc.v:0.0-0.0"
32364       case 5'10001
32365         assign { } { }
32366         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32367       attribute \src "libresoc.v:0.0-0.0"
32368       case 5'10010
32369         assign { } { }
32370         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32371       attribute \src "libresoc.v:0.0-0.0"
32372       case 5'10011
32373         assign { } { }
32374         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32375       attribute \src "libresoc.v:0.0-0.0"
32376       case 5'10100
32377         assign { } { }
32378         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32379       attribute \src "libresoc.v:0.0-0.0"
32380       case 5'10101
32381         assign { } { }
32382         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32383       attribute \src "libresoc.v:0.0-0.0"
32384       case 5'10110
32385         assign { } { }
32386         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32387       attribute \src "libresoc.v:0.0-0.0"
32388       case 5'10111
32389         assign { } { }
32390         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32391       attribute \src "libresoc.v:0.0-0.0"
32392       case 5'11000
32393         assign { } { }
32394         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32395       attribute \src "libresoc.v:0.0-0.0"
32396       case 5'11001
32397         assign { } { }
32398         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32399       attribute \src "libresoc.v:0.0-0.0"
32400       case 5'11010
32401         assign { } { }
32402         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32403       attribute \src "libresoc.v:0.0-0.0"
32404       case 5'11011
32405         assign { } { }
32406         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32407       attribute \src "libresoc.v:0.0-0.0"
32408       case 5'11100
32409         assign { } { }
32410         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32411       attribute \src "libresoc.v:0.0-0.0"
32412       case 5'11101
32413         assign { } { }
32414         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32415       attribute \src "libresoc.v:0.0-0.0"
32416       case 5'11110
32417         assign { } { }
32418         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32419       attribute \src "libresoc.v:0.0-0.0"
32420       case 5'11111
32421         assign { } { }
32422         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32423       case
32424         assign $1\dec31_dec_sub15_cry_in[1:0] 2'00
32425     end
32426     sync always
32427       update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0]
32428   end
32429   attribute \src "libresoc.v:22431.3-22533.6"
32430   process $proc$libresoc.v:22431$487
32431     assign { } { }
32432     assign { } { }
32433     assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0]
32434     attribute \src "libresoc.v:22432.5-22432.29"
32435     switch \initial
32436       attribute \src "libresoc.v:22432.9-22432.17"
32437       case 1'1
32438       case
32439     end
32440     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
32441     switch \opcode_switch
32442       attribute \src "libresoc.v:0.0-0.0"
32443       case 5'00000
32444         assign { } { }
32445         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32446       attribute \src "libresoc.v:0.0-0.0"
32447       case 5'00001
32448         assign { } { }
32449         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32450       attribute \src "libresoc.v:0.0-0.0"
32451       case 5'00010
32452         assign { } { }
32453         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32454       attribute \src "libresoc.v:0.0-0.0"
32455       case 5'00011
32456         assign { } { }
32457         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32458       attribute \src "libresoc.v:0.0-0.0"
32459       case 5'00100
32460         assign { } { }
32461         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32462       attribute \src "libresoc.v:0.0-0.0"
32463       case 5'00101
32464         assign { } { }
32465         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32466       attribute \src "libresoc.v:0.0-0.0"
32467       case 5'00110
32468         assign { } { }
32469         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32470       attribute \src "libresoc.v:0.0-0.0"
32471       case 5'00111
32472         assign { } { }
32473         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32474       attribute \src "libresoc.v:0.0-0.0"
32475       case 5'01000
32476         assign { } { }
32477         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32478       attribute \src "libresoc.v:0.0-0.0"
32479       case 5'01001
32480         assign { } { }
32481         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32482       attribute \src "libresoc.v:0.0-0.0"
32483       case 5'01010
32484         assign { } { }
32485         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32486       attribute \src "libresoc.v:0.0-0.0"
32487       case 5'01011
32488         assign { } { }
32489         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32490       attribute \src "libresoc.v:0.0-0.0"
32491       case 5'01100
32492         assign { } { }
32493         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32494       attribute \src "libresoc.v:0.0-0.0"
32495       case 5'01101
32496         assign { } { }
32497         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32498       attribute \src "libresoc.v:0.0-0.0"
32499       case 5'01110
32500         assign { } { }
32501         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32502       attribute \src "libresoc.v:0.0-0.0"
32503       case 5'01111
32504         assign { } { }
32505         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32506       attribute \src "libresoc.v:0.0-0.0"
32507       case 5'10000
32508         assign { } { }
32509         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32510       attribute \src "libresoc.v:0.0-0.0"
32511       case 5'10001
32512         assign { } { }
32513         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32514       attribute \src "libresoc.v:0.0-0.0"
32515       case 5'10010
32516         assign { } { }
32517         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32518       attribute \src "libresoc.v:0.0-0.0"
32519       case 5'10011
32520         assign { } { }
32521         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32522       attribute \src "libresoc.v:0.0-0.0"
32523       case 5'10100
32524         assign { } { }
32525         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32526       attribute \src "libresoc.v:0.0-0.0"
32527       case 5'10101
32528         assign { } { }
32529         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32530       attribute \src "libresoc.v:0.0-0.0"
32531       case 5'10110
32532         assign { } { }
32533         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32534       attribute \src "libresoc.v:0.0-0.0"
32535       case 5'10111
32536         assign { } { }
32537         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32538       attribute \src "libresoc.v:0.0-0.0"
32539       case 5'11000
32540         assign { } { }
32541         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32542       attribute \src "libresoc.v:0.0-0.0"
32543       case 5'11001
32544         assign { } { }
32545         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32546       attribute \src "libresoc.v:0.0-0.0"
32547       case 5'11010
32548         assign { } { }
32549         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32550       attribute \src "libresoc.v:0.0-0.0"
32551       case 5'11011
32552         assign { } { }
32553         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32554       attribute \src "libresoc.v:0.0-0.0"
32555       case 5'11100
32556         assign { } { }
32557         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32558       attribute \src "libresoc.v:0.0-0.0"
32559       case 5'11101
32560         assign { } { }
32561         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32562       attribute \src "libresoc.v:0.0-0.0"
32563       case 5'11110
32564         assign { } { }
32565         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32566       attribute \src "libresoc.v:0.0-0.0"
32567       case 5'11111
32568         assign { } { }
32569         assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011
32570       case
32571         assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000
32572     end
32573     sync always
32574       update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0]
32575   end
32576   attribute \src "libresoc.v:22534.3-22636.6"
32577   process $proc$libresoc.v:22534$488
32578     assign { } { }
32579     assign { } { }
32580     assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0]
32581     attribute \src "libresoc.v:22535.5-22535.29"
32582     switch \initial
32583       attribute \src "libresoc.v:22535.9-22535.17"
32584       case 1'1
32585       case
32586     end
32587     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
32588     switch \opcode_switch
32589       attribute \src "libresoc.v:0.0-0.0"
32590       case 5'00000
32591         assign { } { }
32592         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32593       attribute \src "libresoc.v:0.0-0.0"
32594       case 5'00001
32595         assign { } { }
32596         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32597       attribute \src "libresoc.v:0.0-0.0"
32598       case 5'00010
32599         assign { } { }
32600         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32601       attribute \src "libresoc.v:0.0-0.0"
32602       case 5'00011
32603         assign { } { }
32604         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32605       attribute \src "libresoc.v:0.0-0.0"
32606       case 5'00100
32607         assign { } { }
32608         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32609       attribute \src "libresoc.v:0.0-0.0"
32610       case 5'00101
32611         assign { } { }
32612         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32613       attribute \src "libresoc.v:0.0-0.0"
32614       case 5'00110
32615         assign { } { }
32616         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32617       attribute \src "libresoc.v:0.0-0.0"
32618       case 5'00111
32619         assign { } { }
32620         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32621       attribute \src "libresoc.v:0.0-0.0"
32622       case 5'01000
32623         assign { } { }
32624         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32625       attribute \src "libresoc.v:0.0-0.0"
32626       case 5'01001
32627         assign { } { }
32628         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32629       attribute \src "libresoc.v:0.0-0.0"
32630       case 5'01010
32631         assign { } { }
32632         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32633       attribute \src "libresoc.v:0.0-0.0"
32634       case 5'01011
32635         assign { } { }
32636         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32637       attribute \src "libresoc.v:0.0-0.0"
32638       case 5'01100
32639         assign { } { }
32640         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32641       attribute \src "libresoc.v:0.0-0.0"
32642       case 5'01101
32643         assign { } { }
32644         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32645       attribute \src "libresoc.v:0.0-0.0"
32646       case 5'01110
32647         assign { } { }
32648         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32649       attribute \src "libresoc.v:0.0-0.0"
32650       case 5'01111
32651         assign { } { }
32652         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32653       attribute \src "libresoc.v:0.0-0.0"
32654       case 5'10000
32655         assign { } { }
32656         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32657       attribute \src "libresoc.v:0.0-0.0"
32658       case 5'10001
32659         assign { } { }
32660         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32661       attribute \src "libresoc.v:0.0-0.0"
32662       case 5'10010
32663         assign { } { }
32664         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32665       attribute \src "libresoc.v:0.0-0.0"
32666       case 5'10011
32667         assign { } { }
32668         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32669       attribute \src "libresoc.v:0.0-0.0"
32670       case 5'10100
32671         assign { } { }
32672         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32673       attribute \src "libresoc.v:0.0-0.0"
32674       case 5'10101
32675         assign { } { }
32676         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32677       attribute \src "libresoc.v:0.0-0.0"
32678       case 5'10110
32679         assign { } { }
32680         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32681       attribute \src "libresoc.v:0.0-0.0"
32682       case 5'10111
32683         assign { } { }
32684         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32685       attribute \src "libresoc.v:0.0-0.0"
32686       case 5'11000
32687         assign { } { }
32688         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32689       attribute \src "libresoc.v:0.0-0.0"
32690       case 5'11001
32691         assign { } { }
32692         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32693       attribute \src "libresoc.v:0.0-0.0"
32694       case 5'11010
32695         assign { } { }
32696         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32697       attribute \src "libresoc.v:0.0-0.0"
32698       case 5'11011
32699         assign { } { }
32700         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32701       attribute \src "libresoc.v:0.0-0.0"
32702       case 5'11100
32703         assign { } { }
32704         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32705       attribute \src "libresoc.v:0.0-0.0"
32706       case 5'11101
32707         assign { } { }
32708         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32709       attribute \src "libresoc.v:0.0-0.0"
32710       case 5'11110
32711         assign { } { }
32712         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32713       attribute \src "libresoc.v:0.0-0.0"
32714       case 5'11111
32715         assign { } { }
32716         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32717       case
32718         assign $1\dec31_dec_sub15_inv_a[0:0] 1'0
32719     end
32720     sync always
32721       update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0]
32722   end
32723   attribute \src "libresoc.v:22637.3-22739.6"
32724   process $proc$libresoc.v:22637$489
32725     assign { } { }
32726     assign { } { }
32727     assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0]
32728     attribute \src "libresoc.v:22638.5-22638.29"
32729     switch \initial
32730       attribute \src "libresoc.v:22638.9-22638.17"
32731       case 1'1
32732       case
32733     end
32734     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
32735     switch \opcode_switch
32736       attribute \src "libresoc.v:0.0-0.0"
32737       case 5'00000
32738         assign { } { }
32739         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32740       attribute \src "libresoc.v:0.0-0.0"
32741       case 5'00001
32742         assign { } { }
32743         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32744       attribute \src "libresoc.v:0.0-0.0"
32745       case 5'00010
32746         assign { } { }
32747         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32748       attribute \src "libresoc.v:0.0-0.0"
32749       case 5'00011
32750         assign { } { }
32751         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32752       attribute \src "libresoc.v:0.0-0.0"
32753       case 5'00100
32754         assign { } { }
32755         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32756       attribute \src "libresoc.v:0.0-0.0"
32757       case 5'00101
32758         assign { } { }
32759         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32760       attribute \src "libresoc.v:0.0-0.0"
32761       case 5'00110
32762         assign { } { }
32763         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32764       attribute \src "libresoc.v:0.0-0.0"
32765       case 5'00111
32766         assign { } { }
32767         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32768       attribute \src "libresoc.v:0.0-0.0"
32769       case 5'01000
32770         assign { } { }
32771         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32772       attribute \src "libresoc.v:0.0-0.0"
32773       case 5'01001
32774         assign { } { }
32775         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32776       attribute \src "libresoc.v:0.0-0.0"
32777       case 5'01010
32778         assign { } { }
32779         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32780       attribute \src "libresoc.v:0.0-0.0"
32781       case 5'01011
32782         assign { } { }
32783         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32784       attribute \src "libresoc.v:0.0-0.0"
32785       case 5'01100
32786         assign { } { }
32787         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32788       attribute \src "libresoc.v:0.0-0.0"
32789       case 5'01101
32790         assign { } { }
32791         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32792       attribute \src "libresoc.v:0.0-0.0"
32793       case 5'01110
32794         assign { } { }
32795         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32796       attribute \src "libresoc.v:0.0-0.0"
32797       case 5'01111
32798         assign { } { }
32799         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32800       attribute \src "libresoc.v:0.0-0.0"
32801       case 5'10000
32802         assign { } { }
32803         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32804       attribute \src "libresoc.v:0.0-0.0"
32805       case 5'10001
32806         assign { } { }
32807         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32808       attribute \src "libresoc.v:0.0-0.0"
32809       case 5'10010
32810         assign { } { }
32811         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32812       attribute \src "libresoc.v:0.0-0.0"
32813       case 5'10011
32814         assign { } { }
32815         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32816       attribute \src "libresoc.v:0.0-0.0"
32817       case 5'10100
32818         assign { } { }
32819         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32820       attribute \src "libresoc.v:0.0-0.0"
32821       case 5'10101
32822         assign { } { }
32823         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32824       attribute \src "libresoc.v:0.0-0.0"
32825       case 5'10110
32826         assign { } { }
32827         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32828       attribute \src "libresoc.v:0.0-0.0"
32829       case 5'10111
32830         assign { } { }
32831         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32832       attribute \src "libresoc.v:0.0-0.0"
32833       case 5'11000
32834         assign { } { }
32835         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32836       attribute \src "libresoc.v:0.0-0.0"
32837       case 5'11001
32838         assign { } { }
32839         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32840       attribute \src "libresoc.v:0.0-0.0"
32841       case 5'11010
32842         assign { } { }
32843         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32844       attribute \src "libresoc.v:0.0-0.0"
32845       case 5'11011
32846         assign { } { }
32847         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32848       attribute \src "libresoc.v:0.0-0.0"
32849       case 5'11100
32850         assign { } { }
32851         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32852       attribute \src "libresoc.v:0.0-0.0"
32853       case 5'11101
32854         assign { } { }
32855         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32856       attribute \src "libresoc.v:0.0-0.0"
32857       case 5'11110
32858         assign { } { }
32859         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32860       attribute \src "libresoc.v:0.0-0.0"
32861       case 5'11111
32862         assign { } { }
32863         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32864       case
32865         assign $1\dec31_dec_sub15_inv_out[0:0] 1'0
32866     end
32867     sync always
32868       update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0]
32869   end
32870   attribute \src "libresoc.v:22740.3-22842.6"
32871   process $proc$libresoc.v:22740$490
32872     assign { } { }
32873     assign { } { }
32874     assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0]
32875     attribute \src "libresoc.v:22741.5-22741.29"
32876     switch \initial
32877       attribute \src "libresoc.v:22741.9-22741.17"
32878       case 1'1
32879       case
32880     end
32881     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
32882     switch \opcode_switch
32883       attribute \src "libresoc.v:0.0-0.0"
32884       case 5'00000
32885         assign { } { }
32886         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32887       attribute \src "libresoc.v:0.0-0.0"
32888       case 5'00001
32889         assign { } { }
32890         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32891       attribute \src "libresoc.v:0.0-0.0"
32892       case 5'00010
32893         assign { } { }
32894         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32895       attribute \src "libresoc.v:0.0-0.0"
32896       case 5'00011
32897         assign { } { }
32898         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32899       attribute \src "libresoc.v:0.0-0.0"
32900       case 5'00100
32901         assign { } { }
32902         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32903       attribute \src "libresoc.v:0.0-0.0"
32904       case 5'00101
32905         assign { } { }
32906         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32907       attribute \src "libresoc.v:0.0-0.0"
32908       case 5'00110
32909         assign { } { }
32910         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32911       attribute \src "libresoc.v:0.0-0.0"
32912       case 5'00111
32913         assign { } { }
32914         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32915       attribute \src "libresoc.v:0.0-0.0"
32916       case 5'01000
32917         assign { } { }
32918         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32919       attribute \src "libresoc.v:0.0-0.0"
32920       case 5'01001
32921         assign { } { }
32922         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32923       attribute \src "libresoc.v:0.0-0.0"
32924       case 5'01010
32925         assign { } { }
32926         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32927       attribute \src "libresoc.v:0.0-0.0"
32928       case 5'01011
32929         assign { } { }
32930         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32931       attribute \src "libresoc.v:0.0-0.0"
32932       case 5'01100
32933         assign { } { }
32934         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32935       attribute \src "libresoc.v:0.0-0.0"
32936       case 5'01101
32937         assign { } { }
32938         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32939       attribute \src "libresoc.v:0.0-0.0"
32940       case 5'01110
32941         assign { } { }
32942         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32943       attribute \src "libresoc.v:0.0-0.0"
32944       case 5'01111
32945         assign { } { }
32946         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32947       attribute \src "libresoc.v:0.0-0.0"
32948       case 5'10000
32949         assign { } { }
32950         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32951       attribute \src "libresoc.v:0.0-0.0"
32952       case 5'10001
32953         assign { } { }
32954         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32955       attribute \src "libresoc.v:0.0-0.0"
32956       case 5'10010
32957         assign { } { }
32958         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32959       attribute \src "libresoc.v:0.0-0.0"
32960       case 5'10011
32961         assign { } { }
32962         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32963       attribute \src "libresoc.v:0.0-0.0"
32964       case 5'10100
32965         assign { } { }
32966         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32967       attribute \src "libresoc.v:0.0-0.0"
32968       case 5'10101
32969         assign { } { }
32970         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32971       attribute \src "libresoc.v:0.0-0.0"
32972       case 5'10110
32973         assign { } { }
32974         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32975       attribute \src "libresoc.v:0.0-0.0"
32976       case 5'10111
32977         assign { } { }
32978         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32979       attribute \src "libresoc.v:0.0-0.0"
32980       case 5'11000
32981         assign { } { }
32982         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32983       attribute \src "libresoc.v:0.0-0.0"
32984       case 5'11001
32985         assign { } { }
32986         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32987       attribute \src "libresoc.v:0.0-0.0"
32988       case 5'11010
32989         assign { } { }
32990         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32991       attribute \src "libresoc.v:0.0-0.0"
32992       case 5'11011
32993         assign { } { }
32994         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32995       attribute \src "libresoc.v:0.0-0.0"
32996       case 5'11100
32997         assign { } { }
32998         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
32999       attribute \src "libresoc.v:0.0-0.0"
33000       case 5'11101
33001         assign { } { }
33002         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
33003       attribute \src "libresoc.v:0.0-0.0"
33004       case 5'11110
33005         assign { } { }
33006         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
33007       attribute \src "libresoc.v:0.0-0.0"
33008       case 5'11111
33009         assign { } { }
33010         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
33011       case
33012         assign $1\dec31_dec_sub15_cry_out[0:0] 1'0
33013     end
33014     sync always
33015       update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0]
33016   end
33017   attribute \src "libresoc.v:22843.3-22945.6"
33018   process $proc$libresoc.v:22843$491
33019     assign { } { }
33020     assign { } { }
33021     assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0]
33022     attribute \src "libresoc.v:22844.5-22844.29"
33023     switch \initial
33024       attribute \src "libresoc.v:22844.9-22844.17"
33025       case 1'1
33026       case
33027     end
33028     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
33029     switch \opcode_switch
33030       attribute \src "libresoc.v:0.0-0.0"
33031       case 5'00000
33032         assign { } { }
33033         assign $1\dec31_dec_sub15_br[0:0] 1'0
33034       attribute \src "libresoc.v:0.0-0.0"
33035       case 5'00001
33036         assign { } { }
33037         assign $1\dec31_dec_sub15_br[0:0] 1'0
33038       attribute \src "libresoc.v:0.0-0.0"
33039       case 5'00010
33040         assign { } { }
33041         assign $1\dec31_dec_sub15_br[0:0] 1'0
33042       attribute \src "libresoc.v:0.0-0.0"
33043       case 5'00011
33044         assign { } { }
33045         assign $1\dec31_dec_sub15_br[0:0] 1'0
33046       attribute \src "libresoc.v:0.0-0.0"
33047       case 5'00100
33048         assign { } { }
33049         assign $1\dec31_dec_sub15_br[0:0] 1'0
33050       attribute \src "libresoc.v:0.0-0.0"
33051       case 5'00101
33052         assign { } { }
33053         assign $1\dec31_dec_sub15_br[0:0] 1'0
33054       attribute \src "libresoc.v:0.0-0.0"
33055       case 5'00110
33056         assign { } { }
33057         assign $1\dec31_dec_sub15_br[0:0] 1'0
33058       attribute \src "libresoc.v:0.0-0.0"
33059       case 5'00111
33060         assign { } { }
33061         assign $1\dec31_dec_sub15_br[0:0] 1'0
33062       attribute \src "libresoc.v:0.0-0.0"
33063       case 5'01000
33064         assign { } { }
33065         assign $1\dec31_dec_sub15_br[0:0] 1'0
33066       attribute \src "libresoc.v:0.0-0.0"
33067       case 5'01001
33068         assign { } { }
33069         assign $1\dec31_dec_sub15_br[0:0] 1'0
33070       attribute \src "libresoc.v:0.0-0.0"
33071       case 5'01010
33072         assign { } { }
33073         assign $1\dec31_dec_sub15_br[0:0] 1'0
33074       attribute \src "libresoc.v:0.0-0.0"
33075       case 5'01011
33076         assign { } { }
33077         assign $1\dec31_dec_sub15_br[0:0] 1'0
33078       attribute \src "libresoc.v:0.0-0.0"
33079       case 5'01100
33080         assign { } { }
33081         assign $1\dec31_dec_sub15_br[0:0] 1'0
33082       attribute \src "libresoc.v:0.0-0.0"
33083       case 5'01101
33084         assign { } { }
33085         assign $1\dec31_dec_sub15_br[0:0] 1'0
33086       attribute \src "libresoc.v:0.0-0.0"
33087       case 5'01110
33088         assign { } { }
33089         assign $1\dec31_dec_sub15_br[0:0] 1'0
33090       attribute \src "libresoc.v:0.0-0.0"
33091       case 5'01111
33092         assign { } { }
33093         assign $1\dec31_dec_sub15_br[0:0] 1'0
33094       attribute \src "libresoc.v:0.0-0.0"
33095       case 5'10000
33096         assign { } { }
33097         assign $1\dec31_dec_sub15_br[0:0] 1'0
33098       attribute \src "libresoc.v:0.0-0.0"
33099       case 5'10001
33100         assign { } { }
33101         assign $1\dec31_dec_sub15_br[0:0] 1'0
33102       attribute \src "libresoc.v:0.0-0.0"
33103       case 5'10010
33104         assign { } { }
33105         assign $1\dec31_dec_sub15_br[0:0] 1'0
33106       attribute \src "libresoc.v:0.0-0.0"
33107       case 5'10011
33108         assign { } { }
33109         assign $1\dec31_dec_sub15_br[0:0] 1'0
33110       attribute \src "libresoc.v:0.0-0.0"
33111       case 5'10100
33112         assign { } { }
33113         assign $1\dec31_dec_sub15_br[0:0] 1'0
33114       attribute \src "libresoc.v:0.0-0.0"
33115       case 5'10101
33116         assign { } { }
33117         assign $1\dec31_dec_sub15_br[0:0] 1'0
33118       attribute \src "libresoc.v:0.0-0.0"
33119       case 5'10110
33120         assign { } { }
33121         assign $1\dec31_dec_sub15_br[0:0] 1'0
33122       attribute \src "libresoc.v:0.0-0.0"
33123       case 5'10111
33124         assign { } { }
33125         assign $1\dec31_dec_sub15_br[0:0] 1'0
33126       attribute \src "libresoc.v:0.0-0.0"
33127       case 5'11000
33128         assign { } { }
33129         assign $1\dec31_dec_sub15_br[0:0] 1'0
33130       attribute \src "libresoc.v:0.0-0.0"
33131       case 5'11001
33132         assign { } { }
33133         assign $1\dec31_dec_sub15_br[0:0] 1'0
33134       attribute \src "libresoc.v:0.0-0.0"
33135       case 5'11010
33136         assign { } { }
33137         assign $1\dec31_dec_sub15_br[0:0] 1'0
33138       attribute \src "libresoc.v:0.0-0.0"
33139       case 5'11011
33140         assign { } { }
33141         assign $1\dec31_dec_sub15_br[0:0] 1'0
33142       attribute \src "libresoc.v:0.0-0.0"
33143       case 5'11100
33144         assign { } { }
33145         assign $1\dec31_dec_sub15_br[0:0] 1'0
33146       attribute \src "libresoc.v:0.0-0.0"
33147       case 5'11101
33148         assign { } { }
33149         assign $1\dec31_dec_sub15_br[0:0] 1'0
33150       attribute \src "libresoc.v:0.0-0.0"
33151       case 5'11110
33152         assign { } { }
33153         assign $1\dec31_dec_sub15_br[0:0] 1'0
33154       attribute \src "libresoc.v:0.0-0.0"
33155       case 5'11111
33156         assign { } { }
33157         assign $1\dec31_dec_sub15_br[0:0] 1'0
33158       case
33159         assign $1\dec31_dec_sub15_br[0:0] 1'0
33160     end
33161     sync always
33162       update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0]
33163   end
33164   attribute \src "libresoc.v:22946.3-23048.6"
33165   process $proc$libresoc.v:22946$492
33166     assign { } { }
33167     assign { } { }
33168     assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0]
33169     attribute \src "libresoc.v:22947.5-22947.29"
33170     switch \initial
33171       attribute \src "libresoc.v:22947.9-22947.17"
33172       case 1'1
33173       case
33174     end
33175     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
33176     switch \opcode_switch
33177       attribute \src "libresoc.v:0.0-0.0"
33178       case 5'00000
33179         assign { } { }
33180         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33181       attribute \src "libresoc.v:0.0-0.0"
33182       case 5'00001
33183         assign { } { }
33184         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33185       attribute \src "libresoc.v:0.0-0.0"
33186       case 5'00010
33187         assign { } { }
33188         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33189       attribute \src "libresoc.v:0.0-0.0"
33190       case 5'00011
33191         assign { } { }
33192         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33193       attribute \src "libresoc.v:0.0-0.0"
33194       case 5'00100
33195         assign { } { }
33196         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33197       attribute \src "libresoc.v:0.0-0.0"
33198       case 5'00101
33199         assign { } { }
33200         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33201       attribute \src "libresoc.v:0.0-0.0"
33202       case 5'00110
33203         assign { } { }
33204         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33205       attribute \src "libresoc.v:0.0-0.0"
33206       case 5'00111
33207         assign { } { }
33208         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33209       attribute \src "libresoc.v:0.0-0.0"
33210       case 5'01000
33211         assign { } { }
33212         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33213       attribute \src "libresoc.v:0.0-0.0"
33214       case 5'01001
33215         assign { } { }
33216         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33217       attribute \src "libresoc.v:0.0-0.0"
33218       case 5'01010
33219         assign { } { }
33220         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33221       attribute \src "libresoc.v:0.0-0.0"
33222       case 5'01011
33223         assign { } { }
33224         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33225       attribute \src "libresoc.v:0.0-0.0"
33226       case 5'01100
33227         assign { } { }
33228         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33229       attribute \src "libresoc.v:0.0-0.0"
33230       case 5'01101
33231         assign { } { }
33232         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33233       attribute \src "libresoc.v:0.0-0.0"
33234       case 5'01110
33235         assign { } { }
33236         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33237       attribute \src "libresoc.v:0.0-0.0"
33238       case 5'01111
33239         assign { } { }
33240         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33241       attribute \src "libresoc.v:0.0-0.0"
33242       case 5'10000
33243         assign { } { }
33244         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33245       attribute \src "libresoc.v:0.0-0.0"
33246       case 5'10001
33247         assign { } { }
33248         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33249       attribute \src "libresoc.v:0.0-0.0"
33250       case 5'10010
33251         assign { } { }
33252         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33253       attribute \src "libresoc.v:0.0-0.0"
33254       case 5'10011
33255         assign { } { }
33256         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33257       attribute \src "libresoc.v:0.0-0.0"
33258       case 5'10100
33259         assign { } { }
33260         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33261       attribute \src "libresoc.v:0.0-0.0"
33262       case 5'10101
33263         assign { } { }
33264         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33265       attribute \src "libresoc.v:0.0-0.0"
33266       case 5'10110
33267         assign { } { }
33268         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33269       attribute \src "libresoc.v:0.0-0.0"
33270       case 5'10111
33271         assign { } { }
33272         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33273       attribute \src "libresoc.v:0.0-0.0"
33274       case 5'11000
33275         assign { } { }
33276         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33277       attribute \src "libresoc.v:0.0-0.0"
33278       case 5'11001
33279         assign { } { }
33280         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33281       attribute \src "libresoc.v:0.0-0.0"
33282       case 5'11010
33283         assign { } { }
33284         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33285       attribute \src "libresoc.v:0.0-0.0"
33286       case 5'11011
33287         assign { } { }
33288         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33289       attribute \src "libresoc.v:0.0-0.0"
33290       case 5'11100
33291         assign { } { }
33292         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33293       attribute \src "libresoc.v:0.0-0.0"
33294       case 5'11101
33295         assign { } { }
33296         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33297       attribute \src "libresoc.v:0.0-0.0"
33298       case 5'11110
33299         assign { } { }
33300         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33301       attribute \src "libresoc.v:0.0-0.0"
33302       case 5'11111
33303         assign { } { }
33304         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33305       case
33306         assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0
33307     end
33308     sync always
33309       update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0]
33310   end
33311   attribute \src "libresoc.v:23049.3-23151.6"
33312   process $proc$libresoc.v:23049$493
33313     assign { } { }
33314     assign { } { }
33315     assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0]
33316     attribute \src "libresoc.v:23050.5-23050.29"
33317     switch \initial
33318       attribute \src "libresoc.v:23050.9-23050.17"
33319       case 1'1
33320       case
33321     end
33322     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
33323     switch \opcode_switch
33324       attribute \src "libresoc.v:0.0-0.0"
33325       case 5'00000
33326         assign { } { }
33327         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33328       attribute \src "libresoc.v:0.0-0.0"
33329       case 5'00001
33330         assign { } { }
33331         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33332       attribute \src "libresoc.v:0.0-0.0"
33333       case 5'00010
33334         assign { } { }
33335         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33336       attribute \src "libresoc.v:0.0-0.0"
33337       case 5'00011
33338         assign { } { }
33339         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33340       attribute \src "libresoc.v:0.0-0.0"
33341       case 5'00100
33342         assign { } { }
33343         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33344       attribute \src "libresoc.v:0.0-0.0"
33345       case 5'00101
33346         assign { } { }
33347         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33348       attribute \src "libresoc.v:0.0-0.0"
33349       case 5'00110
33350         assign { } { }
33351         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33352       attribute \src "libresoc.v:0.0-0.0"
33353       case 5'00111
33354         assign { } { }
33355         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33356       attribute \src "libresoc.v:0.0-0.0"
33357       case 5'01000
33358         assign { } { }
33359         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33360       attribute \src "libresoc.v:0.0-0.0"
33361       case 5'01001
33362         assign { } { }
33363         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33364       attribute \src "libresoc.v:0.0-0.0"
33365       case 5'01010
33366         assign { } { }
33367         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33368       attribute \src "libresoc.v:0.0-0.0"
33369       case 5'01011
33370         assign { } { }
33371         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33372       attribute \src "libresoc.v:0.0-0.0"
33373       case 5'01100
33374         assign { } { }
33375         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33376       attribute \src "libresoc.v:0.0-0.0"
33377       case 5'01101
33378         assign { } { }
33379         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33380       attribute \src "libresoc.v:0.0-0.0"
33381       case 5'01110
33382         assign { } { }
33383         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33384       attribute \src "libresoc.v:0.0-0.0"
33385       case 5'01111
33386         assign { } { }
33387         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33388       attribute \src "libresoc.v:0.0-0.0"
33389       case 5'10000
33390         assign { } { }
33391         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33392       attribute \src "libresoc.v:0.0-0.0"
33393       case 5'10001
33394         assign { } { }
33395         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33396       attribute \src "libresoc.v:0.0-0.0"
33397       case 5'10010
33398         assign { } { }
33399         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33400       attribute \src "libresoc.v:0.0-0.0"
33401       case 5'10011
33402         assign { } { }
33403         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33404       attribute \src "libresoc.v:0.0-0.0"
33405       case 5'10100
33406         assign { } { }
33407         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33408       attribute \src "libresoc.v:0.0-0.0"
33409       case 5'10101
33410         assign { } { }
33411         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33412       attribute \src "libresoc.v:0.0-0.0"
33413       case 5'10110
33414         assign { } { }
33415         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33416       attribute \src "libresoc.v:0.0-0.0"
33417       case 5'10111
33418         assign { } { }
33419         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33420       attribute \src "libresoc.v:0.0-0.0"
33421       case 5'11000
33422         assign { } { }
33423         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33424       attribute \src "libresoc.v:0.0-0.0"
33425       case 5'11001
33426         assign { } { }
33427         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33428       attribute \src "libresoc.v:0.0-0.0"
33429       case 5'11010
33430         assign { } { }
33431         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33432       attribute \src "libresoc.v:0.0-0.0"
33433       case 5'11011
33434         assign { } { }
33435         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33436       attribute \src "libresoc.v:0.0-0.0"
33437       case 5'11100
33438         assign { } { }
33439         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33440       attribute \src "libresoc.v:0.0-0.0"
33441       case 5'11101
33442         assign { } { }
33443         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33444       attribute \src "libresoc.v:0.0-0.0"
33445       case 5'11110
33446         assign { } { }
33447         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33448       attribute \src "libresoc.v:0.0-0.0"
33449       case 5'11111
33450         assign { } { }
33451         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011
33452       case
33453         assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000
33454     end
33455     sync always
33456       update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0]
33457   end
33458   attribute \src "libresoc.v:23152.3-23254.6"
33459   process $proc$libresoc.v:23152$494
33460     assign { } { }
33461     assign { } { }
33462     assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0]
33463     attribute \src "libresoc.v:23153.5-23153.29"
33464     switch \initial
33465       attribute \src "libresoc.v:23153.9-23153.17"
33466       case 1'1
33467       case
33468     end
33469     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
33470     switch \opcode_switch
33471       attribute \src "libresoc.v:0.0-0.0"
33472       case 5'00000
33473         assign { } { }
33474         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33475       attribute \src "libresoc.v:0.0-0.0"
33476       case 5'00001
33477         assign { } { }
33478         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33479       attribute \src "libresoc.v:0.0-0.0"
33480       case 5'00010
33481         assign { } { }
33482         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33483       attribute \src "libresoc.v:0.0-0.0"
33484       case 5'00011
33485         assign { } { }
33486         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33487       attribute \src "libresoc.v:0.0-0.0"
33488       case 5'00100
33489         assign { } { }
33490         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33491       attribute \src "libresoc.v:0.0-0.0"
33492       case 5'00101
33493         assign { } { }
33494         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33495       attribute \src "libresoc.v:0.0-0.0"
33496       case 5'00110
33497         assign { } { }
33498         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33499       attribute \src "libresoc.v:0.0-0.0"
33500       case 5'00111
33501         assign { } { }
33502         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33503       attribute \src "libresoc.v:0.0-0.0"
33504       case 5'01000
33505         assign { } { }
33506         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33507       attribute \src "libresoc.v:0.0-0.0"
33508       case 5'01001
33509         assign { } { }
33510         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33511       attribute \src "libresoc.v:0.0-0.0"
33512       case 5'01010
33513         assign { } { }
33514         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33515       attribute \src "libresoc.v:0.0-0.0"
33516       case 5'01011
33517         assign { } { }
33518         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33519       attribute \src "libresoc.v:0.0-0.0"
33520       case 5'01100
33521         assign { } { }
33522         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33523       attribute \src "libresoc.v:0.0-0.0"
33524       case 5'01101
33525         assign { } { }
33526         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33527       attribute \src "libresoc.v:0.0-0.0"
33528       case 5'01110
33529         assign { } { }
33530         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33531       attribute \src "libresoc.v:0.0-0.0"
33532       case 5'01111
33533         assign { } { }
33534         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33535       attribute \src "libresoc.v:0.0-0.0"
33536       case 5'10000
33537         assign { } { }
33538         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33539       attribute \src "libresoc.v:0.0-0.0"
33540       case 5'10001
33541         assign { } { }
33542         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33543       attribute \src "libresoc.v:0.0-0.0"
33544       case 5'10010
33545         assign { } { }
33546         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33547       attribute \src "libresoc.v:0.0-0.0"
33548       case 5'10011
33549         assign { } { }
33550         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33551       attribute \src "libresoc.v:0.0-0.0"
33552       case 5'10100
33553         assign { } { }
33554         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33555       attribute \src "libresoc.v:0.0-0.0"
33556       case 5'10101
33557         assign { } { }
33558         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33559       attribute \src "libresoc.v:0.0-0.0"
33560       case 5'10110
33561         assign { } { }
33562         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33563       attribute \src "libresoc.v:0.0-0.0"
33564       case 5'10111
33565         assign { } { }
33566         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33567       attribute \src "libresoc.v:0.0-0.0"
33568       case 5'11000
33569         assign { } { }
33570         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33571       attribute \src "libresoc.v:0.0-0.0"
33572       case 5'11001
33573         assign { } { }
33574         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33575       attribute \src "libresoc.v:0.0-0.0"
33576       case 5'11010
33577         assign { } { }
33578         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33579       attribute \src "libresoc.v:0.0-0.0"
33580       case 5'11011
33581         assign { } { }
33582         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33583       attribute \src "libresoc.v:0.0-0.0"
33584       case 5'11100
33585         assign { } { }
33586         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33587       attribute \src "libresoc.v:0.0-0.0"
33588       case 5'11101
33589         assign { } { }
33590         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33591       attribute \src "libresoc.v:0.0-0.0"
33592       case 5'11110
33593         assign { } { }
33594         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33595       attribute \src "libresoc.v:0.0-0.0"
33596       case 5'11111
33597         assign { } { }
33598         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33599       case
33600         assign $1\dec31_dec_sub15_rsrv[0:0] 1'0
33601     end
33602     sync always
33603       update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0]
33604   end
33605   attribute \src "libresoc.v:23255.3-23357.6"
33606   process $proc$libresoc.v:23255$495
33607     assign { } { }
33608     assign { } { }
33609     assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0]
33610     attribute \src "libresoc.v:23256.5-23256.29"
33611     switch \initial
33612       attribute \src "libresoc.v:23256.9-23256.17"
33613       case 1'1
33614       case
33615     end
33616     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
33617     switch \opcode_switch
33618       attribute \src "libresoc.v:0.0-0.0"
33619       case 5'00000
33620         assign { } { }
33621         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33622       attribute \src "libresoc.v:0.0-0.0"
33623       case 5'00001
33624         assign { } { }
33625         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33626       attribute \src "libresoc.v:0.0-0.0"
33627       case 5'00010
33628         assign { } { }
33629         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33630       attribute \src "libresoc.v:0.0-0.0"
33631       case 5'00011
33632         assign { } { }
33633         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33634       attribute \src "libresoc.v:0.0-0.0"
33635       case 5'00100
33636         assign { } { }
33637         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33638       attribute \src "libresoc.v:0.0-0.0"
33639       case 5'00101
33640         assign { } { }
33641         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33642       attribute \src "libresoc.v:0.0-0.0"
33643       case 5'00110
33644         assign { } { }
33645         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33646       attribute \src "libresoc.v:0.0-0.0"
33647       case 5'00111
33648         assign { } { }
33649         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33650       attribute \src "libresoc.v:0.0-0.0"
33651       case 5'01000
33652         assign { } { }
33653         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33654       attribute \src "libresoc.v:0.0-0.0"
33655       case 5'01001
33656         assign { } { }
33657         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33658       attribute \src "libresoc.v:0.0-0.0"
33659       case 5'01010
33660         assign { } { }
33661         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33662       attribute \src "libresoc.v:0.0-0.0"
33663       case 5'01011
33664         assign { } { }
33665         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33666       attribute \src "libresoc.v:0.0-0.0"
33667       case 5'01100
33668         assign { } { }
33669         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33670       attribute \src "libresoc.v:0.0-0.0"
33671       case 5'01101
33672         assign { } { }
33673         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33674       attribute \src "libresoc.v:0.0-0.0"
33675       case 5'01110
33676         assign { } { }
33677         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33678       attribute \src "libresoc.v:0.0-0.0"
33679       case 5'01111
33680         assign { } { }
33681         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33682       attribute \src "libresoc.v:0.0-0.0"
33683       case 5'10000
33684         assign { } { }
33685         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33686       attribute \src "libresoc.v:0.0-0.0"
33687       case 5'10001
33688         assign { } { }
33689         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33690       attribute \src "libresoc.v:0.0-0.0"
33691       case 5'10010
33692         assign { } { }
33693         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33694       attribute \src "libresoc.v:0.0-0.0"
33695       case 5'10011
33696         assign { } { }
33697         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33698       attribute \src "libresoc.v:0.0-0.0"
33699       case 5'10100
33700         assign { } { }
33701         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33702       attribute \src "libresoc.v:0.0-0.0"
33703       case 5'10101
33704         assign { } { }
33705         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33706       attribute \src "libresoc.v:0.0-0.0"
33707       case 5'10110
33708         assign { } { }
33709         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33710       attribute \src "libresoc.v:0.0-0.0"
33711       case 5'10111
33712         assign { } { }
33713         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33714       attribute \src "libresoc.v:0.0-0.0"
33715       case 5'11000
33716         assign { } { }
33717         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33718       attribute \src "libresoc.v:0.0-0.0"
33719       case 5'11001
33720         assign { } { }
33721         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33722       attribute \src "libresoc.v:0.0-0.0"
33723       case 5'11010
33724         assign { } { }
33725         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33726       attribute \src "libresoc.v:0.0-0.0"
33727       case 5'11011
33728         assign { } { }
33729         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33730       attribute \src "libresoc.v:0.0-0.0"
33731       case 5'11100
33732         assign { } { }
33733         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33734       attribute \src "libresoc.v:0.0-0.0"
33735       case 5'11101
33736         assign { } { }
33737         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33738       attribute \src "libresoc.v:0.0-0.0"
33739       case 5'11110
33740         assign { } { }
33741         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33742       attribute \src "libresoc.v:0.0-0.0"
33743       case 5'11111
33744         assign { } { }
33745         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33746       case
33747         assign $1\dec31_dec_sub15_is_32b[0:0] 1'0
33748     end
33749     sync always
33750       update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0]
33751   end
33752   attribute \src "libresoc.v:23358.3-23460.6"
33753   process $proc$libresoc.v:23358$496
33754     assign { } { }
33755     assign { } { }
33756     assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0]
33757     attribute \src "libresoc.v:23359.5-23359.29"
33758     switch \initial
33759       attribute \src "libresoc.v:23359.9-23359.17"
33760       case 1'1
33761       case
33762     end
33763     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
33764     switch \opcode_switch
33765       attribute \src "libresoc.v:0.0-0.0"
33766       case 5'00000
33767         assign { } { }
33768         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33769       attribute \src "libresoc.v:0.0-0.0"
33770       case 5'00001
33771         assign { } { }
33772         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33773       attribute \src "libresoc.v:0.0-0.0"
33774       case 5'00010
33775         assign { } { }
33776         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33777       attribute \src "libresoc.v:0.0-0.0"
33778       case 5'00011
33779         assign { } { }
33780         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33781       attribute \src "libresoc.v:0.0-0.0"
33782       case 5'00100
33783         assign { } { }
33784         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33785       attribute \src "libresoc.v:0.0-0.0"
33786       case 5'00101
33787         assign { } { }
33788         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33789       attribute \src "libresoc.v:0.0-0.0"
33790       case 5'00110
33791         assign { } { }
33792         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33793       attribute \src "libresoc.v:0.0-0.0"
33794       case 5'00111
33795         assign { } { }
33796         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33797       attribute \src "libresoc.v:0.0-0.0"
33798       case 5'01000
33799         assign { } { }
33800         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33801       attribute \src "libresoc.v:0.0-0.0"
33802       case 5'01001
33803         assign { } { }
33804         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33805       attribute \src "libresoc.v:0.0-0.0"
33806       case 5'01010
33807         assign { } { }
33808         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33809       attribute \src "libresoc.v:0.0-0.0"
33810       case 5'01011
33811         assign { } { }
33812         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33813       attribute \src "libresoc.v:0.0-0.0"
33814       case 5'01100
33815         assign { } { }
33816         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33817       attribute \src "libresoc.v:0.0-0.0"
33818       case 5'01101
33819         assign { } { }
33820         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33821       attribute \src "libresoc.v:0.0-0.0"
33822       case 5'01110
33823         assign { } { }
33824         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33825       attribute \src "libresoc.v:0.0-0.0"
33826       case 5'01111
33827         assign { } { }
33828         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33829       attribute \src "libresoc.v:0.0-0.0"
33830       case 5'10000
33831         assign { } { }
33832         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33833       attribute \src "libresoc.v:0.0-0.0"
33834       case 5'10001
33835         assign { } { }
33836         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33837       attribute \src "libresoc.v:0.0-0.0"
33838       case 5'10010
33839         assign { } { }
33840         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33841       attribute \src "libresoc.v:0.0-0.0"
33842       case 5'10011
33843         assign { } { }
33844         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33845       attribute \src "libresoc.v:0.0-0.0"
33846       case 5'10100
33847         assign { } { }
33848         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33849       attribute \src "libresoc.v:0.0-0.0"
33850       case 5'10101
33851         assign { } { }
33852         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33853       attribute \src "libresoc.v:0.0-0.0"
33854       case 5'10110
33855         assign { } { }
33856         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33857       attribute \src "libresoc.v:0.0-0.0"
33858       case 5'10111
33859         assign { } { }
33860         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33861       attribute \src "libresoc.v:0.0-0.0"
33862       case 5'11000
33863         assign { } { }
33864         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33865       attribute \src "libresoc.v:0.0-0.0"
33866       case 5'11001
33867         assign { } { }
33868         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33869       attribute \src "libresoc.v:0.0-0.0"
33870       case 5'11010
33871         assign { } { }
33872         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33873       attribute \src "libresoc.v:0.0-0.0"
33874       case 5'11011
33875         assign { } { }
33876         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33877       attribute \src "libresoc.v:0.0-0.0"
33878       case 5'11100
33879         assign { } { }
33880         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33881       attribute \src "libresoc.v:0.0-0.0"
33882       case 5'11101
33883         assign { } { }
33884         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33885       attribute \src "libresoc.v:0.0-0.0"
33886       case 5'11110
33887         assign { } { }
33888         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33889       attribute \src "libresoc.v:0.0-0.0"
33890       case 5'11111
33891         assign { } { }
33892         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33893       case
33894         assign $1\dec31_dec_sub15_sgn[0:0] 1'0
33895     end
33896     sync always
33897       update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0]
33898   end
33899   attribute \src "libresoc.v:23461.3-23563.6"
33900   process $proc$libresoc.v:23461$497
33901     assign { } { }
33902     assign { } { }
33903     assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0]
33904     attribute \src "libresoc.v:23462.5-23462.29"
33905     switch \initial
33906       attribute \src "libresoc.v:23462.9-23462.17"
33907       case 1'1
33908       case
33909     end
33910     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
33911     switch \opcode_switch
33912       attribute \src "libresoc.v:0.0-0.0"
33913       case 5'00000
33914         assign { } { }
33915         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33916       attribute \src "libresoc.v:0.0-0.0"
33917       case 5'00001
33918         assign { } { }
33919         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33920       attribute \src "libresoc.v:0.0-0.0"
33921       case 5'00010
33922         assign { } { }
33923         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33924       attribute \src "libresoc.v:0.0-0.0"
33925       case 5'00011
33926         assign { } { }
33927         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33928       attribute \src "libresoc.v:0.0-0.0"
33929       case 5'00100
33930         assign { } { }
33931         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33932       attribute \src "libresoc.v:0.0-0.0"
33933       case 5'00101
33934         assign { } { }
33935         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33936       attribute \src "libresoc.v:0.0-0.0"
33937       case 5'00110
33938         assign { } { }
33939         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33940       attribute \src "libresoc.v:0.0-0.0"
33941       case 5'00111
33942         assign { } { }
33943         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33944       attribute \src "libresoc.v:0.0-0.0"
33945       case 5'01000
33946         assign { } { }
33947         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33948       attribute \src "libresoc.v:0.0-0.0"
33949       case 5'01001
33950         assign { } { }
33951         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33952       attribute \src "libresoc.v:0.0-0.0"
33953       case 5'01010
33954         assign { } { }
33955         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33956       attribute \src "libresoc.v:0.0-0.0"
33957       case 5'01011
33958         assign { } { }
33959         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33960       attribute \src "libresoc.v:0.0-0.0"
33961       case 5'01100
33962         assign { } { }
33963         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33964       attribute \src "libresoc.v:0.0-0.0"
33965       case 5'01101
33966         assign { } { }
33967         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33968       attribute \src "libresoc.v:0.0-0.0"
33969       case 5'01110
33970         assign { } { }
33971         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33972       attribute \src "libresoc.v:0.0-0.0"
33973       case 5'01111
33974         assign { } { }
33975         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33976       attribute \src "libresoc.v:0.0-0.0"
33977       case 5'10000
33978         assign { } { }
33979         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33980       attribute \src "libresoc.v:0.0-0.0"
33981       case 5'10001
33982         assign { } { }
33983         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33984       attribute \src "libresoc.v:0.0-0.0"
33985       case 5'10010
33986         assign { } { }
33987         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33988       attribute \src "libresoc.v:0.0-0.0"
33989       case 5'10011
33990         assign { } { }
33991         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33992       attribute \src "libresoc.v:0.0-0.0"
33993       case 5'10100
33994         assign { } { }
33995         assign $1\dec31_dec_sub15_lk[0:0] 1'0
33996       attribute \src "libresoc.v:0.0-0.0"
33997       case 5'10101
33998         assign { } { }
33999         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34000       attribute \src "libresoc.v:0.0-0.0"
34001       case 5'10110
34002         assign { } { }
34003         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34004       attribute \src "libresoc.v:0.0-0.0"
34005       case 5'10111
34006         assign { } { }
34007         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34008       attribute \src "libresoc.v:0.0-0.0"
34009       case 5'11000
34010         assign { } { }
34011         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34012       attribute \src "libresoc.v:0.0-0.0"
34013       case 5'11001
34014         assign { } { }
34015         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34016       attribute \src "libresoc.v:0.0-0.0"
34017       case 5'11010
34018         assign { } { }
34019         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34020       attribute \src "libresoc.v:0.0-0.0"
34021       case 5'11011
34022         assign { } { }
34023         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34024       attribute \src "libresoc.v:0.0-0.0"
34025       case 5'11100
34026         assign { } { }
34027         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34028       attribute \src "libresoc.v:0.0-0.0"
34029       case 5'11101
34030         assign { } { }
34031         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34032       attribute \src "libresoc.v:0.0-0.0"
34033       case 5'11110
34034         assign { } { }
34035         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34036       attribute \src "libresoc.v:0.0-0.0"
34037       case 5'11111
34038         assign { } { }
34039         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34040       case
34041         assign $1\dec31_dec_sub15_lk[0:0] 1'0
34042     end
34043     sync always
34044       update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0]
34045   end
34046   attribute \src "libresoc.v:23564.3-23666.6"
34047   process $proc$libresoc.v:23564$498
34048     assign { } { }
34049     assign { } { }
34050     assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0]
34051     attribute \src "libresoc.v:23565.5-23565.29"
34052     switch \initial
34053       attribute \src "libresoc.v:23565.9-23565.17"
34054       case 1'1
34055       case
34056     end
34057     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
34058     switch \opcode_switch
34059       attribute \src "libresoc.v:0.0-0.0"
34060       case 5'00000
34061         assign { } { }
34062         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34063       attribute \src "libresoc.v:0.0-0.0"
34064       case 5'00001
34065         assign { } { }
34066         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34067       attribute \src "libresoc.v:0.0-0.0"
34068       case 5'00010
34069         assign { } { }
34070         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34071       attribute \src "libresoc.v:0.0-0.0"
34072       case 5'00011
34073         assign { } { }
34074         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34075       attribute \src "libresoc.v:0.0-0.0"
34076       case 5'00100
34077         assign { } { }
34078         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34079       attribute \src "libresoc.v:0.0-0.0"
34080       case 5'00101
34081         assign { } { }
34082         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34083       attribute \src "libresoc.v:0.0-0.0"
34084       case 5'00110
34085         assign { } { }
34086         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34087       attribute \src "libresoc.v:0.0-0.0"
34088       case 5'00111
34089         assign { } { }
34090         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34091       attribute \src "libresoc.v:0.0-0.0"
34092       case 5'01000
34093         assign { } { }
34094         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34095       attribute \src "libresoc.v:0.0-0.0"
34096       case 5'01001
34097         assign { } { }
34098         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34099       attribute \src "libresoc.v:0.0-0.0"
34100       case 5'01010
34101         assign { } { }
34102         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34103       attribute \src "libresoc.v:0.0-0.0"
34104       case 5'01011
34105         assign { } { }
34106         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34107       attribute \src "libresoc.v:0.0-0.0"
34108       case 5'01100
34109         assign { } { }
34110         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34111       attribute \src "libresoc.v:0.0-0.0"
34112       case 5'01101
34113         assign { } { }
34114         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34115       attribute \src "libresoc.v:0.0-0.0"
34116       case 5'01110
34117         assign { } { }
34118         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34119       attribute \src "libresoc.v:0.0-0.0"
34120       case 5'01111
34121         assign { } { }
34122         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34123       attribute \src "libresoc.v:0.0-0.0"
34124       case 5'10000
34125         assign { } { }
34126         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34127       attribute \src "libresoc.v:0.0-0.0"
34128       case 5'10001
34129         assign { } { }
34130         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34131       attribute \src "libresoc.v:0.0-0.0"
34132       case 5'10010
34133         assign { } { }
34134         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34135       attribute \src "libresoc.v:0.0-0.0"
34136       case 5'10011
34137         assign { } { }
34138         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34139       attribute \src "libresoc.v:0.0-0.0"
34140       case 5'10100
34141         assign { } { }
34142         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34143       attribute \src "libresoc.v:0.0-0.0"
34144       case 5'10101
34145         assign { } { }
34146         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34147       attribute \src "libresoc.v:0.0-0.0"
34148       case 5'10110
34149         assign { } { }
34150         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34151       attribute \src "libresoc.v:0.0-0.0"
34152       case 5'10111
34153         assign { } { }
34154         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34155       attribute \src "libresoc.v:0.0-0.0"
34156       case 5'11000
34157         assign { } { }
34158         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34159       attribute \src "libresoc.v:0.0-0.0"
34160       case 5'11001
34161         assign { } { }
34162         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34163       attribute \src "libresoc.v:0.0-0.0"
34164       case 5'11010
34165         assign { } { }
34166         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34167       attribute \src "libresoc.v:0.0-0.0"
34168       case 5'11011
34169         assign { } { }
34170         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34171       attribute \src "libresoc.v:0.0-0.0"
34172       case 5'11100
34173         assign { } { }
34174         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34175       attribute \src "libresoc.v:0.0-0.0"
34176       case 5'11101
34177         assign { } { }
34178         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34179       attribute \src "libresoc.v:0.0-0.0"
34180       case 5'11110
34181         assign { } { }
34182         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34183       attribute \src "libresoc.v:0.0-0.0"
34184       case 5'11111
34185         assign { } { }
34186         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1
34187       case
34188         assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0
34189     end
34190     sync always
34191       update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0]
34192   end
34193   attribute \src "libresoc.v:23667.3-23769.6"
34194   process $proc$libresoc.v:23667$499
34195     assign { } { }
34196     assign { } { }
34197     assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0]
34198     attribute \src "libresoc.v:23668.5-23668.29"
34199     switch \initial
34200       attribute \src "libresoc.v:23668.9-23668.17"
34201       case 1'1
34202       case
34203     end
34204     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
34205     switch \opcode_switch
34206       attribute \src "libresoc.v:0.0-0.0"
34207       case 5'00000
34208         assign { } { }
34209         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34210       attribute \src "libresoc.v:0.0-0.0"
34211       case 5'00001
34212         assign { } { }
34213         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34214       attribute \src "libresoc.v:0.0-0.0"
34215       case 5'00010
34216         assign { } { }
34217         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34218       attribute \src "libresoc.v:0.0-0.0"
34219       case 5'00011
34220         assign { } { }
34221         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34222       attribute \src "libresoc.v:0.0-0.0"
34223       case 5'00100
34224         assign { } { }
34225         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34226       attribute \src "libresoc.v:0.0-0.0"
34227       case 5'00101
34228         assign { } { }
34229         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34230       attribute \src "libresoc.v:0.0-0.0"
34231       case 5'00110
34232         assign { } { }
34233         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34234       attribute \src "libresoc.v:0.0-0.0"
34235       case 5'00111
34236         assign { } { }
34237         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34238       attribute \src "libresoc.v:0.0-0.0"
34239       case 5'01000
34240         assign { } { }
34241         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34242       attribute \src "libresoc.v:0.0-0.0"
34243       case 5'01001
34244         assign { } { }
34245         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34246       attribute \src "libresoc.v:0.0-0.0"
34247       case 5'01010
34248         assign { } { }
34249         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34250       attribute \src "libresoc.v:0.0-0.0"
34251       case 5'01011
34252         assign { } { }
34253         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34254       attribute \src "libresoc.v:0.0-0.0"
34255       case 5'01100
34256         assign { } { }
34257         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34258       attribute \src "libresoc.v:0.0-0.0"
34259       case 5'01101
34260         assign { } { }
34261         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34262       attribute \src "libresoc.v:0.0-0.0"
34263       case 5'01110
34264         assign { } { }
34265         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34266       attribute \src "libresoc.v:0.0-0.0"
34267       case 5'01111
34268         assign { } { }
34269         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34270       attribute \src "libresoc.v:0.0-0.0"
34271       case 5'10000
34272         assign { } { }
34273         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34274       attribute \src "libresoc.v:0.0-0.0"
34275       case 5'10001
34276         assign { } { }
34277         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34278       attribute \src "libresoc.v:0.0-0.0"
34279       case 5'10010
34280         assign { } { }
34281         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34282       attribute \src "libresoc.v:0.0-0.0"
34283       case 5'10011
34284         assign { } { }
34285         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34286       attribute \src "libresoc.v:0.0-0.0"
34287       case 5'10100
34288         assign { } { }
34289         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34290       attribute \src "libresoc.v:0.0-0.0"
34291       case 5'10101
34292         assign { } { }
34293         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34294       attribute \src "libresoc.v:0.0-0.0"
34295       case 5'10110
34296         assign { } { }
34297         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34298       attribute \src "libresoc.v:0.0-0.0"
34299       case 5'10111
34300         assign { } { }
34301         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34302       attribute \src "libresoc.v:0.0-0.0"
34303       case 5'11000
34304         assign { } { }
34305         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34306       attribute \src "libresoc.v:0.0-0.0"
34307       case 5'11001
34308         assign { } { }
34309         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34310       attribute \src "libresoc.v:0.0-0.0"
34311       case 5'11010
34312         assign { } { }
34313         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34314       attribute \src "libresoc.v:0.0-0.0"
34315       case 5'11011
34316         assign { } { }
34317         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34318       attribute \src "libresoc.v:0.0-0.0"
34319       case 5'11100
34320         assign { } { }
34321         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34322       attribute \src "libresoc.v:0.0-0.0"
34323       case 5'11101
34324         assign { } { }
34325         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34326       attribute \src "libresoc.v:0.0-0.0"
34327       case 5'11110
34328         assign { } { }
34329         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34330       attribute \src "libresoc.v:0.0-0.0"
34331       case 5'11111
34332         assign { } { }
34333         assign $1\dec31_dec_sub15_form[4:0] 5'10010
34334       case
34335         assign $1\dec31_dec_sub15_form[4:0] 5'00000
34336     end
34337     sync always
34338       update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0]
34339   end
34340   attribute \src "libresoc.v:23770.3-23872.6"
34341   process $proc$libresoc.v:23770$500
34342     assign { } { }
34343     assign { } { }
34344     assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0]
34345     attribute \src "libresoc.v:23771.5-23771.29"
34346     switch \initial
34347       attribute \src "libresoc.v:23771.9-23771.17"
34348       case 1'1
34349       case
34350     end
34351     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
34352     switch \opcode_switch
34353       attribute \src "libresoc.v:0.0-0.0"
34354       case 5'00000
34355         assign { } { }
34356         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34357       attribute \src "libresoc.v:0.0-0.0"
34358       case 5'00001
34359         assign { } { }
34360         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34361       attribute \src "libresoc.v:0.0-0.0"
34362       case 5'00010
34363         assign { } { }
34364         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34365       attribute \src "libresoc.v:0.0-0.0"
34366       case 5'00011
34367         assign { } { }
34368         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34369       attribute \src "libresoc.v:0.0-0.0"
34370       case 5'00100
34371         assign { } { }
34372         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34373       attribute \src "libresoc.v:0.0-0.0"
34374       case 5'00101
34375         assign { } { }
34376         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34377       attribute \src "libresoc.v:0.0-0.0"
34378       case 5'00110
34379         assign { } { }
34380         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34381       attribute \src "libresoc.v:0.0-0.0"
34382       case 5'00111
34383         assign { } { }
34384         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34385       attribute \src "libresoc.v:0.0-0.0"
34386       case 5'01000
34387         assign { } { }
34388         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34389       attribute \src "libresoc.v:0.0-0.0"
34390       case 5'01001
34391         assign { } { }
34392         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34393       attribute \src "libresoc.v:0.0-0.0"
34394       case 5'01010
34395         assign { } { }
34396         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34397       attribute \src "libresoc.v:0.0-0.0"
34398       case 5'01011
34399         assign { } { }
34400         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34401       attribute \src "libresoc.v:0.0-0.0"
34402       case 5'01100
34403         assign { } { }
34404         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34405       attribute \src "libresoc.v:0.0-0.0"
34406       case 5'01101
34407         assign { } { }
34408         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34409       attribute \src "libresoc.v:0.0-0.0"
34410       case 5'01110
34411         assign { } { }
34412         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34413       attribute \src "libresoc.v:0.0-0.0"
34414       case 5'01111
34415         assign { } { }
34416         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34417       attribute \src "libresoc.v:0.0-0.0"
34418       case 5'10000
34419         assign { } { }
34420         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34421       attribute \src "libresoc.v:0.0-0.0"
34422       case 5'10001
34423         assign { } { }
34424         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34425       attribute \src "libresoc.v:0.0-0.0"
34426       case 5'10010
34427         assign { } { }
34428         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34429       attribute \src "libresoc.v:0.0-0.0"
34430       case 5'10011
34431         assign { } { }
34432         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34433       attribute \src "libresoc.v:0.0-0.0"
34434       case 5'10100
34435         assign { } { }
34436         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34437       attribute \src "libresoc.v:0.0-0.0"
34438       case 5'10101
34439         assign { } { }
34440         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34441       attribute \src "libresoc.v:0.0-0.0"
34442       case 5'10110
34443         assign { } { }
34444         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34445       attribute \src "libresoc.v:0.0-0.0"
34446       case 5'10111
34447         assign { } { }
34448         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34449       attribute \src "libresoc.v:0.0-0.0"
34450       case 5'11000
34451         assign { } { }
34452         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34453       attribute \src "libresoc.v:0.0-0.0"
34454       case 5'11001
34455         assign { } { }
34456         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34457       attribute \src "libresoc.v:0.0-0.0"
34458       case 5'11010
34459         assign { } { }
34460         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34461       attribute \src "libresoc.v:0.0-0.0"
34462       case 5'11011
34463         assign { } { }
34464         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34465       attribute \src "libresoc.v:0.0-0.0"
34466       case 5'11100
34467         assign { } { }
34468         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34469       attribute \src "libresoc.v:0.0-0.0"
34470       case 5'11101
34471         assign { } { }
34472         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34473       attribute \src "libresoc.v:0.0-0.0"
34474       case 5'11110
34475         assign { } { }
34476         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34477       attribute \src "libresoc.v:0.0-0.0"
34478       case 5'11111
34479         assign { } { }
34480         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010
34481       case
34482         assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000
34483     end
34484     sync always
34485       update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0]
34486   end
34487   attribute \src "libresoc.v:23873.3-23975.6"
34488   process $proc$libresoc.v:23873$501
34489     assign { } { }
34490     assign { } { }
34491     assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0]
34492     attribute \src "libresoc.v:23874.5-23874.29"
34493     switch \initial
34494       attribute \src "libresoc.v:23874.9-23874.17"
34495       case 1'1
34496       case
34497     end
34498     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
34499     switch \opcode_switch
34500       attribute \src "libresoc.v:0.0-0.0"
34501       case 5'00000
34502         assign { } { }
34503         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34504       attribute \src "libresoc.v:0.0-0.0"
34505       case 5'00001
34506         assign { } { }
34507         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34508       attribute \src "libresoc.v:0.0-0.0"
34509       case 5'00010
34510         assign { } { }
34511         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34512       attribute \src "libresoc.v:0.0-0.0"
34513       case 5'00011
34514         assign { } { }
34515         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34516       attribute \src "libresoc.v:0.0-0.0"
34517       case 5'00100
34518         assign { } { }
34519         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34520       attribute \src "libresoc.v:0.0-0.0"
34521       case 5'00101
34522         assign { } { }
34523         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34524       attribute \src "libresoc.v:0.0-0.0"
34525       case 5'00110
34526         assign { } { }
34527         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34528       attribute \src "libresoc.v:0.0-0.0"
34529       case 5'00111
34530         assign { } { }
34531         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34532       attribute \src "libresoc.v:0.0-0.0"
34533       case 5'01000
34534         assign { } { }
34535         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34536       attribute \src "libresoc.v:0.0-0.0"
34537       case 5'01001
34538         assign { } { }
34539         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34540       attribute \src "libresoc.v:0.0-0.0"
34541       case 5'01010
34542         assign { } { }
34543         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34544       attribute \src "libresoc.v:0.0-0.0"
34545       case 5'01011
34546         assign { } { }
34547         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34548       attribute \src "libresoc.v:0.0-0.0"
34549       case 5'01100
34550         assign { } { }
34551         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34552       attribute \src "libresoc.v:0.0-0.0"
34553       case 5'01101
34554         assign { } { }
34555         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34556       attribute \src "libresoc.v:0.0-0.0"
34557       case 5'01110
34558         assign { } { }
34559         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34560       attribute \src "libresoc.v:0.0-0.0"
34561       case 5'01111
34562         assign { } { }
34563         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34564       attribute \src "libresoc.v:0.0-0.0"
34565       case 5'10000
34566         assign { } { }
34567         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34568       attribute \src "libresoc.v:0.0-0.0"
34569       case 5'10001
34570         assign { } { }
34571         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34572       attribute \src "libresoc.v:0.0-0.0"
34573       case 5'10010
34574         assign { } { }
34575         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34576       attribute \src "libresoc.v:0.0-0.0"
34577       case 5'10011
34578         assign { } { }
34579         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34580       attribute \src "libresoc.v:0.0-0.0"
34581       case 5'10100
34582         assign { } { }
34583         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34584       attribute \src "libresoc.v:0.0-0.0"
34585       case 5'10101
34586         assign { } { }
34587         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34588       attribute \src "libresoc.v:0.0-0.0"
34589       case 5'10110
34590         assign { } { }
34591         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34592       attribute \src "libresoc.v:0.0-0.0"
34593       case 5'10111
34594         assign { } { }
34595         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34596       attribute \src "libresoc.v:0.0-0.0"
34597       case 5'11000
34598         assign { } { }
34599         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34600       attribute \src "libresoc.v:0.0-0.0"
34601       case 5'11001
34602         assign { } { }
34603         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34604       attribute \src "libresoc.v:0.0-0.0"
34605       case 5'11010
34606         assign { } { }
34607         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34608       attribute \src "libresoc.v:0.0-0.0"
34609       case 5'11011
34610         assign { } { }
34611         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34612       attribute \src "libresoc.v:0.0-0.0"
34613       case 5'11100
34614         assign { } { }
34615         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34616       attribute \src "libresoc.v:0.0-0.0"
34617       case 5'11101
34618         assign { } { }
34619         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34620       attribute \src "libresoc.v:0.0-0.0"
34621       case 5'11110
34622         assign { } { }
34623         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34624       attribute \src "libresoc.v:0.0-0.0"
34625       case 5'11111
34626         assign { } { }
34627         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001
34628       case
34629         assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000
34630     end
34631     sync always
34632       update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0]
34633   end
34634   attribute \src "libresoc.v:23976.3-24078.6"
34635   process $proc$libresoc.v:23976$502
34636     assign { } { }
34637     assign { } { }
34638     assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0]
34639     attribute \src "libresoc.v:23977.5-23977.29"
34640     switch \initial
34641       attribute \src "libresoc.v:23977.9-23977.17"
34642       case 1'1
34643       case
34644     end
34645     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
34646     switch \opcode_switch
34647       attribute \src "libresoc.v:0.0-0.0"
34648       case 5'00000
34649         assign { } { }
34650         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34651       attribute \src "libresoc.v:0.0-0.0"
34652       case 5'00001
34653         assign { } { }
34654         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34655       attribute \src "libresoc.v:0.0-0.0"
34656       case 5'00010
34657         assign { } { }
34658         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34659       attribute \src "libresoc.v:0.0-0.0"
34660       case 5'00011
34661         assign { } { }
34662         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34663       attribute \src "libresoc.v:0.0-0.0"
34664       case 5'00100
34665         assign { } { }
34666         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34667       attribute \src "libresoc.v:0.0-0.0"
34668       case 5'00101
34669         assign { } { }
34670         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34671       attribute \src "libresoc.v:0.0-0.0"
34672       case 5'00110
34673         assign { } { }
34674         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34675       attribute \src "libresoc.v:0.0-0.0"
34676       case 5'00111
34677         assign { } { }
34678         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34679       attribute \src "libresoc.v:0.0-0.0"
34680       case 5'01000
34681         assign { } { }
34682         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34683       attribute \src "libresoc.v:0.0-0.0"
34684       case 5'01001
34685         assign { } { }
34686         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34687       attribute \src "libresoc.v:0.0-0.0"
34688       case 5'01010
34689         assign { } { }
34690         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34691       attribute \src "libresoc.v:0.0-0.0"
34692       case 5'01011
34693         assign { } { }
34694         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34695       attribute \src "libresoc.v:0.0-0.0"
34696       case 5'01100
34697         assign { } { }
34698         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34699       attribute \src "libresoc.v:0.0-0.0"
34700       case 5'01101
34701         assign { } { }
34702         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34703       attribute \src "libresoc.v:0.0-0.0"
34704       case 5'01110
34705         assign { } { }
34706         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34707       attribute \src "libresoc.v:0.0-0.0"
34708       case 5'01111
34709         assign { } { }
34710         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34711       attribute \src "libresoc.v:0.0-0.0"
34712       case 5'10000
34713         assign { } { }
34714         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34715       attribute \src "libresoc.v:0.0-0.0"
34716       case 5'10001
34717         assign { } { }
34718         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34719       attribute \src "libresoc.v:0.0-0.0"
34720       case 5'10010
34721         assign { } { }
34722         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34723       attribute \src "libresoc.v:0.0-0.0"
34724       case 5'10011
34725         assign { } { }
34726         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34727       attribute \src "libresoc.v:0.0-0.0"
34728       case 5'10100
34729         assign { } { }
34730         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34731       attribute \src "libresoc.v:0.0-0.0"
34732       case 5'10101
34733         assign { } { }
34734         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34735       attribute \src "libresoc.v:0.0-0.0"
34736       case 5'10110
34737         assign { } { }
34738         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34739       attribute \src "libresoc.v:0.0-0.0"
34740       case 5'10111
34741         assign { } { }
34742         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34743       attribute \src "libresoc.v:0.0-0.0"
34744       case 5'11000
34745         assign { } { }
34746         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34747       attribute \src "libresoc.v:0.0-0.0"
34748       case 5'11001
34749         assign { } { }
34750         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34751       attribute \src "libresoc.v:0.0-0.0"
34752       case 5'11010
34753         assign { } { }
34754         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34755       attribute \src "libresoc.v:0.0-0.0"
34756       case 5'11011
34757         assign { } { }
34758         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34759       attribute \src "libresoc.v:0.0-0.0"
34760       case 5'11100
34761         assign { } { }
34762         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34763       attribute \src "libresoc.v:0.0-0.0"
34764       case 5'11101
34765         assign { } { }
34766         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34767       attribute \src "libresoc.v:0.0-0.0"
34768       case 5'11110
34769         assign { } { }
34770         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34771       attribute \src "libresoc.v:0.0-0.0"
34772       case 5'11111
34773         assign { } { }
34774         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34775       case
34776         assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00
34777     end
34778     sync always
34779       update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0]
34780   end
34781   attribute \src "libresoc.v:24079.3-24181.6"
34782   process $proc$libresoc.v:24079$503
34783     assign { } { }
34784     assign { } { }
34785     assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0]
34786     attribute \src "libresoc.v:24080.5-24080.29"
34787     switch \initial
34788       attribute \src "libresoc.v:24080.9-24080.17"
34789       case 1'1
34790       case
34791     end
34792     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
34793     switch \opcode_switch
34794       attribute \src "libresoc.v:0.0-0.0"
34795       case 5'00000
34796         assign { } { }
34797         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34798       attribute \src "libresoc.v:0.0-0.0"
34799       case 5'00001
34800         assign { } { }
34801         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34802       attribute \src "libresoc.v:0.0-0.0"
34803       case 5'00010
34804         assign { } { }
34805         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34806       attribute \src "libresoc.v:0.0-0.0"
34807       case 5'00011
34808         assign { } { }
34809         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34810       attribute \src "libresoc.v:0.0-0.0"
34811       case 5'00100
34812         assign { } { }
34813         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34814       attribute \src "libresoc.v:0.0-0.0"
34815       case 5'00101
34816         assign { } { }
34817         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34818       attribute \src "libresoc.v:0.0-0.0"
34819       case 5'00110
34820         assign { } { }
34821         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34822       attribute \src "libresoc.v:0.0-0.0"
34823       case 5'00111
34824         assign { } { }
34825         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34826       attribute \src "libresoc.v:0.0-0.0"
34827       case 5'01000
34828         assign { } { }
34829         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34830       attribute \src "libresoc.v:0.0-0.0"
34831       case 5'01001
34832         assign { } { }
34833         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34834       attribute \src "libresoc.v:0.0-0.0"
34835       case 5'01010
34836         assign { } { }
34837         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34838       attribute \src "libresoc.v:0.0-0.0"
34839       case 5'01011
34840         assign { } { }
34841         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34842       attribute \src "libresoc.v:0.0-0.0"
34843       case 5'01100
34844         assign { } { }
34845         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34846       attribute \src "libresoc.v:0.0-0.0"
34847       case 5'01101
34848         assign { } { }
34849         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34850       attribute \src "libresoc.v:0.0-0.0"
34851       case 5'01110
34852         assign { } { }
34853         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34854       attribute \src "libresoc.v:0.0-0.0"
34855       case 5'01111
34856         assign { } { }
34857         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34858       attribute \src "libresoc.v:0.0-0.0"
34859       case 5'10000
34860         assign { } { }
34861         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34862       attribute \src "libresoc.v:0.0-0.0"
34863       case 5'10001
34864         assign { } { }
34865         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34866       attribute \src "libresoc.v:0.0-0.0"
34867       case 5'10010
34868         assign { } { }
34869         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34870       attribute \src "libresoc.v:0.0-0.0"
34871       case 5'10011
34872         assign { } { }
34873         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34874       attribute \src "libresoc.v:0.0-0.0"
34875       case 5'10100
34876         assign { } { }
34877         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34878       attribute \src "libresoc.v:0.0-0.0"
34879       case 5'10101
34880         assign { } { }
34881         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34882       attribute \src "libresoc.v:0.0-0.0"
34883       case 5'10110
34884         assign { } { }
34885         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34886       attribute \src "libresoc.v:0.0-0.0"
34887       case 5'10111
34888         assign { } { }
34889         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34890       attribute \src "libresoc.v:0.0-0.0"
34891       case 5'11000
34892         assign { } { }
34893         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34894       attribute \src "libresoc.v:0.0-0.0"
34895       case 5'11001
34896         assign { } { }
34897         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34898       attribute \src "libresoc.v:0.0-0.0"
34899       case 5'11010
34900         assign { } { }
34901         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34902       attribute \src "libresoc.v:0.0-0.0"
34903       case 5'11011
34904         assign { } { }
34905         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34906       attribute \src "libresoc.v:0.0-0.0"
34907       case 5'11100
34908         assign { } { }
34909         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34910       attribute \src "libresoc.v:0.0-0.0"
34911       case 5'11101
34912         assign { } { }
34913         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34914       attribute \src "libresoc.v:0.0-0.0"
34915       case 5'11110
34916         assign { } { }
34917         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34918       attribute \src "libresoc.v:0.0-0.0"
34919       case 5'11111
34920         assign { } { }
34921         assign $1\dec31_dec_sub15_out_sel[1:0] 2'01
34922       case
34923         assign $1\dec31_dec_sub15_out_sel[1:0] 2'00
34924     end
34925     sync always
34926       update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0]
34927   end
34928   attribute \src "libresoc.v:24182.3-24284.6"
34929   process $proc$libresoc.v:24182$504
34930     assign { } { }
34931     assign { } { }
34932     assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0]
34933     attribute \src "libresoc.v:24183.5-24183.29"
34934     switch \initial
34935       attribute \src "libresoc.v:24183.9-24183.17"
34936       case 1'1
34937       case
34938     end
34939     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
34940     switch \opcode_switch
34941       attribute \src "libresoc.v:0.0-0.0"
34942       case 5'00000
34943         assign { } { }
34944         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34945       attribute \src "libresoc.v:0.0-0.0"
34946       case 5'00001
34947         assign { } { }
34948         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34949       attribute \src "libresoc.v:0.0-0.0"
34950       case 5'00010
34951         assign { } { }
34952         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34953       attribute \src "libresoc.v:0.0-0.0"
34954       case 5'00011
34955         assign { } { }
34956         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34957       attribute \src "libresoc.v:0.0-0.0"
34958       case 5'00100
34959         assign { } { }
34960         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34961       attribute \src "libresoc.v:0.0-0.0"
34962       case 5'00101
34963         assign { } { }
34964         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34965       attribute \src "libresoc.v:0.0-0.0"
34966       case 5'00110
34967         assign { } { }
34968         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34969       attribute \src "libresoc.v:0.0-0.0"
34970       case 5'00111
34971         assign { } { }
34972         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34973       attribute \src "libresoc.v:0.0-0.0"
34974       case 5'01000
34975         assign { } { }
34976         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34977       attribute \src "libresoc.v:0.0-0.0"
34978       case 5'01001
34979         assign { } { }
34980         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34981       attribute \src "libresoc.v:0.0-0.0"
34982       case 5'01010
34983         assign { } { }
34984         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34985       attribute \src "libresoc.v:0.0-0.0"
34986       case 5'01011
34987         assign { } { }
34988         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34989       attribute \src "libresoc.v:0.0-0.0"
34990       case 5'01100
34991         assign { } { }
34992         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34993       attribute \src "libresoc.v:0.0-0.0"
34994       case 5'01101
34995         assign { } { }
34996         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
34997       attribute \src "libresoc.v:0.0-0.0"
34998       case 5'01110
34999         assign { } { }
35000         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35001       attribute \src "libresoc.v:0.0-0.0"
35002       case 5'01111
35003         assign { } { }
35004         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35005       attribute \src "libresoc.v:0.0-0.0"
35006       case 5'10000
35007         assign { } { }
35008         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35009       attribute \src "libresoc.v:0.0-0.0"
35010       case 5'10001
35011         assign { } { }
35012         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35013       attribute \src "libresoc.v:0.0-0.0"
35014       case 5'10010
35015         assign { } { }
35016         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35017       attribute \src "libresoc.v:0.0-0.0"
35018       case 5'10011
35019         assign { } { }
35020         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35021       attribute \src "libresoc.v:0.0-0.0"
35022       case 5'10100
35023         assign { } { }
35024         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35025       attribute \src "libresoc.v:0.0-0.0"
35026       case 5'10101
35027         assign { } { }
35028         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35029       attribute \src "libresoc.v:0.0-0.0"
35030       case 5'10110
35031         assign { } { }
35032         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35033       attribute \src "libresoc.v:0.0-0.0"
35034       case 5'10111
35035         assign { } { }
35036         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35037       attribute \src "libresoc.v:0.0-0.0"
35038       case 5'11000
35039         assign { } { }
35040         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35041       attribute \src "libresoc.v:0.0-0.0"
35042       case 5'11001
35043         assign { } { }
35044         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35045       attribute \src "libresoc.v:0.0-0.0"
35046       case 5'11010
35047         assign { } { }
35048         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35049       attribute \src "libresoc.v:0.0-0.0"
35050       case 5'11011
35051         assign { } { }
35052         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35053       attribute \src "libresoc.v:0.0-0.0"
35054       case 5'11100
35055         assign { } { }
35056         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35057       attribute \src "libresoc.v:0.0-0.0"
35058       case 5'11101
35059         assign { } { }
35060         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35061       attribute \src "libresoc.v:0.0-0.0"
35062       case 5'11110
35063         assign { } { }
35064         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35065       attribute \src "libresoc.v:0.0-0.0"
35066       case 5'11111
35067         assign { } { }
35068         assign $1\dec31_dec_sub15_cr_in[2:0] 3'101
35069       case
35070         assign $1\dec31_dec_sub15_cr_in[2:0] 3'000
35071     end
35072     sync always
35073       update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0]
35074   end
35075   attribute \src "libresoc.v:24285.3-24387.6"
35076   process $proc$libresoc.v:24285$505
35077     assign { } { }
35078     assign { } { }
35079     assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0]
35080     attribute \src "libresoc.v:24286.5-24286.29"
35081     switch \initial
35082       attribute \src "libresoc.v:24286.9-24286.17"
35083       case 1'1
35084       case
35085     end
35086     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35087     switch \opcode_switch
35088       attribute \src "libresoc.v:0.0-0.0"
35089       case 5'00000
35090         assign { } { }
35091         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35092       attribute \src "libresoc.v:0.0-0.0"
35093       case 5'00001
35094         assign { } { }
35095         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35096       attribute \src "libresoc.v:0.0-0.0"
35097       case 5'00010
35098         assign { } { }
35099         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35100       attribute \src "libresoc.v:0.0-0.0"
35101       case 5'00011
35102         assign { } { }
35103         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35104       attribute \src "libresoc.v:0.0-0.0"
35105       case 5'00100
35106         assign { } { }
35107         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35108       attribute \src "libresoc.v:0.0-0.0"
35109       case 5'00101
35110         assign { } { }
35111         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35112       attribute \src "libresoc.v:0.0-0.0"
35113       case 5'00110
35114         assign { } { }
35115         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35116       attribute \src "libresoc.v:0.0-0.0"
35117       case 5'00111
35118         assign { } { }
35119         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35120       attribute \src "libresoc.v:0.0-0.0"
35121       case 5'01000
35122         assign { } { }
35123         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35124       attribute \src "libresoc.v:0.0-0.0"
35125       case 5'01001
35126         assign { } { }
35127         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35128       attribute \src "libresoc.v:0.0-0.0"
35129       case 5'01010
35130         assign { } { }
35131         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35132       attribute \src "libresoc.v:0.0-0.0"
35133       case 5'01011
35134         assign { } { }
35135         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35136       attribute \src "libresoc.v:0.0-0.0"
35137       case 5'01100
35138         assign { } { }
35139         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35140       attribute \src "libresoc.v:0.0-0.0"
35141       case 5'01101
35142         assign { } { }
35143         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35144       attribute \src "libresoc.v:0.0-0.0"
35145       case 5'01110
35146         assign { } { }
35147         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35148       attribute \src "libresoc.v:0.0-0.0"
35149       case 5'01111
35150         assign { } { }
35151         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35152       attribute \src "libresoc.v:0.0-0.0"
35153       case 5'10000
35154         assign { } { }
35155         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35156       attribute \src "libresoc.v:0.0-0.0"
35157       case 5'10001
35158         assign { } { }
35159         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35160       attribute \src "libresoc.v:0.0-0.0"
35161       case 5'10010
35162         assign { } { }
35163         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35164       attribute \src "libresoc.v:0.0-0.0"
35165       case 5'10011
35166         assign { } { }
35167         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35168       attribute \src "libresoc.v:0.0-0.0"
35169       case 5'10100
35170         assign { } { }
35171         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35172       attribute \src "libresoc.v:0.0-0.0"
35173       case 5'10101
35174         assign { } { }
35175         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35176       attribute \src "libresoc.v:0.0-0.0"
35177       case 5'10110
35178         assign { } { }
35179         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35180       attribute \src "libresoc.v:0.0-0.0"
35181       case 5'10111
35182         assign { } { }
35183         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35184       attribute \src "libresoc.v:0.0-0.0"
35185       case 5'11000
35186         assign { } { }
35187         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35188       attribute \src "libresoc.v:0.0-0.0"
35189       case 5'11001
35190         assign { } { }
35191         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35192       attribute \src "libresoc.v:0.0-0.0"
35193       case 5'11010
35194         assign { } { }
35195         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35196       attribute \src "libresoc.v:0.0-0.0"
35197       case 5'11011
35198         assign { } { }
35199         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35200       attribute \src "libresoc.v:0.0-0.0"
35201       case 5'11100
35202         assign { } { }
35203         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35204       attribute \src "libresoc.v:0.0-0.0"
35205       case 5'11101
35206         assign { } { }
35207         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35208       attribute \src "libresoc.v:0.0-0.0"
35209       case 5'11110
35210         assign { } { }
35211         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35212       attribute \src "libresoc.v:0.0-0.0"
35213       case 5'11111
35214         assign { } { }
35215         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35216       case
35217         assign $1\dec31_dec_sub15_cr_out[2:0] 3'000
35218     end
35219     sync always
35220       update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0]
35221   end
35222   connect \opcode_switch \opcode_in [10:6]
35223 end
35224 attribute \src "libresoc.v:24393.1-24892.10"
35225 attribute \cells_not_processed 1
35226 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16"
35227 attribute \generator "nMigen"
35228 module \dec31_dec_sub16
35229   attribute \src "libresoc.v:24701.3-24710.6"
35230   wire width 8 $0\dec31_dec_sub16_asmcode[7:0]
35231   attribute \src "libresoc.v:24741.3-24750.6"
35232   wire $0\dec31_dec_sub16_br[0:0]
35233   attribute \src "libresoc.v:24871.3-24880.6"
35234   wire width 3 $0\dec31_dec_sub16_cr_in[2:0]
35235   attribute \src "libresoc.v:24881.3-24890.6"
35236   wire width 3 $0\dec31_dec_sub16_cr_out[2:0]
35237   attribute \src "libresoc.v:24691.3-24700.6"
35238   wire width 2 $0\dec31_dec_sub16_cry_in[1:0]
35239   attribute \src "libresoc.v:24731.3-24740.6"
35240   wire $0\dec31_dec_sub16_cry_out[0:0]
35241   attribute \src "libresoc.v:24821.3-24830.6"
35242   wire width 5 $0\dec31_dec_sub16_form[4:0]
35243   attribute \src "libresoc.v:24651.3-24660.6"
35244   wire width 12 $0\dec31_dec_sub16_function_unit[11:0]
35245   attribute \src "libresoc.v:24831.3-24840.6"
35246   wire width 3 $0\dec31_dec_sub16_in1_sel[2:0]
35247   attribute \src "libresoc.v:24841.3-24850.6"
35248   wire width 4 $0\dec31_dec_sub16_in2_sel[3:0]
35249   attribute \src "libresoc.v:24851.3-24860.6"
35250   wire width 2 $0\dec31_dec_sub16_in3_sel[1:0]
35251   attribute \src "libresoc.v:24761.3-24770.6"
35252   wire width 7 $0\dec31_dec_sub16_internal_op[6:0]
35253   attribute \src "libresoc.v:24711.3-24720.6"
35254   wire $0\dec31_dec_sub16_inv_a[0:0]
35255   attribute \src "libresoc.v:24721.3-24730.6"
35256   wire $0\dec31_dec_sub16_inv_out[0:0]
35257   attribute \src "libresoc.v:24781.3-24790.6"
35258   wire $0\dec31_dec_sub16_is_32b[0:0]
35259   attribute \src "libresoc.v:24661.3-24670.6"
35260   wire width 4 $0\dec31_dec_sub16_ldst_len[3:0]
35261   attribute \src "libresoc.v:24801.3-24810.6"
35262   wire $0\dec31_dec_sub16_lk[0:0]
35263   attribute \src "libresoc.v:24861.3-24870.6"
35264   wire width 2 $0\dec31_dec_sub16_out_sel[1:0]
35265   attribute \src "libresoc.v:24681.3-24690.6"
35266   wire width 2 $0\dec31_dec_sub16_rc_sel[1:0]
35267   attribute \src "libresoc.v:24771.3-24780.6"
35268   wire $0\dec31_dec_sub16_rsrv[0:0]
35269   attribute \src "libresoc.v:24811.3-24820.6"
35270   wire $0\dec31_dec_sub16_sgl_pipe[0:0]
35271   attribute \src "libresoc.v:24791.3-24800.6"
35272   wire $0\dec31_dec_sub16_sgn[0:0]
35273   attribute \src "libresoc.v:24751.3-24760.6"
35274   wire $0\dec31_dec_sub16_sgn_ext[0:0]
35275   attribute \src "libresoc.v:24671.3-24680.6"
35276   wire width 2 $0\dec31_dec_sub16_upd[1:0]
35277   attribute \src "libresoc.v:24394.7-24394.20"
35278   wire $0\initial[0:0]
35279   attribute \src "libresoc.v:24701.3-24710.6"
35280   wire width 8 $1\dec31_dec_sub16_asmcode[7:0]
35281   attribute \src "libresoc.v:24741.3-24750.6"
35282   wire $1\dec31_dec_sub16_br[0:0]
35283   attribute \src "libresoc.v:24871.3-24880.6"
35284   wire width 3 $1\dec31_dec_sub16_cr_in[2:0]
35285   attribute \src "libresoc.v:24881.3-24890.6"
35286   wire width 3 $1\dec31_dec_sub16_cr_out[2:0]
35287   attribute \src "libresoc.v:24691.3-24700.6"
35288   wire width 2 $1\dec31_dec_sub16_cry_in[1:0]
35289   attribute \src "libresoc.v:24731.3-24740.6"
35290   wire $1\dec31_dec_sub16_cry_out[0:0]
35291   attribute \src "libresoc.v:24821.3-24830.6"
35292   wire width 5 $1\dec31_dec_sub16_form[4:0]
35293   attribute \src "libresoc.v:24651.3-24660.6"
35294   wire width 12 $1\dec31_dec_sub16_function_unit[11:0]
35295   attribute \src "libresoc.v:24831.3-24840.6"
35296   wire width 3 $1\dec31_dec_sub16_in1_sel[2:0]
35297   attribute \src "libresoc.v:24841.3-24850.6"
35298   wire width 4 $1\dec31_dec_sub16_in2_sel[3:0]
35299   attribute \src "libresoc.v:24851.3-24860.6"
35300   wire width 2 $1\dec31_dec_sub16_in3_sel[1:0]
35301   attribute \src "libresoc.v:24761.3-24770.6"
35302   wire width 7 $1\dec31_dec_sub16_internal_op[6:0]
35303   attribute \src "libresoc.v:24711.3-24720.6"
35304   wire $1\dec31_dec_sub16_inv_a[0:0]
35305   attribute \src "libresoc.v:24721.3-24730.6"
35306   wire $1\dec31_dec_sub16_inv_out[0:0]
35307   attribute \src "libresoc.v:24781.3-24790.6"
35308   wire $1\dec31_dec_sub16_is_32b[0:0]
35309   attribute \src "libresoc.v:24661.3-24670.6"
35310   wire width 4 $1\dec31_dec_sub16_ldst_len[3:0]
35311   attribute \src "libresoc.v:24801.3-24810.6"
35312   wire $1\dec31_dec_sub16_lk[0:0]
35313   attribute \src "libresoc.v:24861.3-24870.6"
35314   wire width 2 $1\dec31_dec_sub16_out_sel[1:0]
35315   attribute \src "libresoc.v:24681.3-24690.6"
35316   wire width 2 $1\dec31_dec_sub16_rc_sel[1:0]
35317   attribute \src "libresoc.v:24771.3-24780.6"
35318   wire $1\dec31_dec_sub16_rsrv[0:0]
35319   attribute \src "libresoc.v:24811.3-24820.6"
35320   wire $1\dec31_dec_sub16_sgl_pipe[0:0]
35321   attribute \src "libresoc.v:24791.3-24800.6"
35322   wire $1\dec31_dec_sub16_sgn[0:0]
35323   attribute \src "libresoc.v:24751.3-24760.6"
35324   wire $1\dec31_dec_sub16_sgn_ext[0:0]
35325   attribute \src "libresoc.v:24671.3-24680.6"
35326   wire width 2 $1\dec31_dec_sub16_upd[1:0]
35327   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35328   wire width 8 output 4 \dec31_dec_sub16_asmcode
35329   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35330   wire output 18 \dec31_dec_sub16_br
35331   attribute \enum_base_type "CRInSel"
35332   attribute \enum_value_000 "NONE"
35333   attribute \enum_value_001 "CR0"
35334   attribute \enum_value_010 "BI"
35335   attribute \enum_value_011 "BFA"
35336   attribute \enum_value_100 "BA_BB"
35337   attribute \enum_value_101 "BC"
35338   attribute \enum_value_110 "WHOLE_REG"
35339   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35340   wire width 3 output 9 \dec31_dec_sub16_cr_in
35341   attribute \enum_base_type "CROutSel"
35342   attribute \enum_value_000 "NONE"
35343   attribute \enum_value_001 "CR0"
35344   attribute \enum_value_010 "BF"
35345   attribute \enum_value_011 "BT"
35346   attribute \enum_value_100 "WHOLE_REG"
35347   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35348   wire width 3 output 10 \dec31_dec_sub16_cr_out
35349   attribute \enum_base_type "CryIn"
35350   attribute \enum_value_00 "ZERO"
35351   attribute \enum_value_01 "ONE"
35352   attribute \enum_value_10 "CA"
35353   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35354   wire width 2 output 14 \dec31_dec_sub16_cry_in
35355   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35356   wire output 17 \dec31_dec_sub16_cry_out
35357   attribute \enum_base_type "Form"
35358   attribute \enum_value_00000 "NONE"
35359   attribute \enum_value_00001 "I"
35360   attribute \enum_value_00010 "B"
35361   attribute \enum_value_00011 "SC"
35362   attribute \enum_value_00100 "D"
35363   attribute \enum_value_00101 "DS"
35364   attribute \enum_value_00110 "DQ"
35365   attribute \enum_value_00111 "DX"
35366   attribute \enum_value_01000 "X"
35367   attribute \enum_value_01001 "XL"
35368   attribute \enum_value_01010 "XFX"
35369   attribute \enum_value_01011 "XFL"
35370   attribute \enum_value_01100 "XX1"
35371   attribute \enum_value_01101 "XX2"
35372   attribute \enum_value_01110 "XX3"
35373   attribute \enum_value_01111 "XX4"
35374   attribute \enum_value_10000 "XS"
35375   attribute \enum_value_10001 "XO"
35376   attribute \enum_value_10010 "A"
35377   attribute \enum_value_10011 "M"
35378   attribute \enum_value_10100 "MD"
35379   attribute \enum_value_10101 "MDS"
35380   attribute \enum_value_10110 "VA"
35381   attribute \enum_value_10111 "VC"
35382   attribute \enum_value_11000 "VX"
35383   attribute \enum_value_11001 "EVX"
35384   attribute \enum_value_11010 "EVS"
35385   attribute \enum_value_11011 "Z22"
35386   attribute \enum_value_11100 "Z23"
35387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35388   wire width 5 output 3 \dec31_dec_sub16_form
35389   attribute \enum_base_type "Function"
35390   attribute \enum_value_000000000000 "NONE"
35391   attribute \enum_value_000000000010 "ALU"
35392   attribute \enum_value_000000000100 "LDST"
35393   attribute \enum_value_000000001000 "SHIFT_ROT"
35394   attribute \enum_value_000000010000 "LOGICAL"
35395   attribute \enum_value_000000100000 "BRANCH"
35396   attribute \enum_value_000001000000 "CR"
35397   attribute \enum_value_000010000000 "TRAP"
35398   attribute \enum_value_000100000000 "MUL"
35399   attribute \enum_value_001000000000 "DIV"
35400   attribute \enum_value_010000000000 "SPR"
35401   attribute \enum_value_100000000000 "MMU"
35402   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35403   wire width 12 output 1 \dec31_dec_sub16_function_unit
35404   attribute \enum_base_type "In1Sel"
35405   attribute \enum_value_000 "NONE"
35406   attribute \enum_value_001 "RA"
35407   attribute \enum_value_010 "RA_OR_ZERO"
35408   attribute \enum_value_011 "SPR"
35409   attribute \enum_value_100 "RS"
35410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35411   wire width 3 output 5 \dec31_dec_sub16_in1_sel
35412   attribute \enum_base_type "In2Sel"
35413   attribute \enum_value_0000 "NONE"
35414   attribute \enum_value_0001 "RB"
35415   attribute \enum_value_0010 "CONST_UI"
35416   attribute \enum_value_0011 "CONST_SI"
35417   attribute \enum_value_0100 "CONST_UI_HI"
35418   attribute \enum_value_0101 "CONST_SI_HI"
35419   attribute \enum_value_0110 "CONST_LI"
35420   attribute \enum_value_0111 "CONST_BD"
35421   attribute \enum_value_1000 "CONST_DS"
35422   attribute \enum_value_1001 "CONST_M1"
35423   attribute \enum_value_1010 "CONST_SH"
35424   attribute \enum_value_1011 "CONST_SH32"
35425   attribute \enum_value_1100 "SPR"
35426   attribute \enum_value_1101 "RS"
35427   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35428   wire width 4 output 6 \dec31_dec_sub16_in2_sel
35429   attribute \enum_base_type "In3Sel"
35430   attribute \enum_value_00 "NONE"
35431   attribute \enum_value_01 "RS"
35432   attribute \enum_value_10 "RB"
35433   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35434   wire width 2 output 7 \dec31_dec_sub16_in3_sel
35435   attribute \enum_base_type "MicrOp"
35436   attribute \enum_value_0000000 "OP_ILLEGAL"
35437   attribute \enum_value_0000001 "OP_NOP"
35438   attribute \enum_value_0000010 "OP_ADD"
35439   attribute \enum_value_0000011 "OP_ADDPCIS"
35440   attribute \enum_value_0000100 "OP_AND"
35441   attribute \enum_value_0000101 "OP_ATTN"
35442   attribute \enum_value_0000110 "OP_B"
35443   attribute \enum_value_0000111 "OP_BC"
35444   attribute \enum_value_0001000 "OP_BCREG"
35445   attribute \enum_value_0001001 "OP_BPERM"
35446   attribute \enum_value_0001010 "OP_CMP"
35447   attribute \enum_value_0001011 "OP_CMPB"
35448   attribute \enum_value_0001100 "OP_CMPEQB"
35449   attribute \enum_value_0001101 "OP_CMPRB"
35450   attribute \enum_value_0001110 "OP_CNTZ"
35451   attribute \enum_value_0001111 "OP_CRAND"
35452   attribute \enum_value_0010000 "OP_CRANDC"
35453   attribute \enum_value_0010001 "OP_CREQV"
35454   attribute \enum_value_0010010 "OP_CRNAND"
35455   attribute \enum_value_0010011 "OP_CRNOR"
35456   attribute \enum_value_0010100 "OP_CROR"
35457   attribute \enum_value_0010101 "OP_CRORC"
35458   attribute \enum_value_0010110 "OP_CRXOR"
35459   attribute \enum_value_0010111 "OP_DARN"
35460   attribute \enum_value_0011000 "OP_DCBF"
35461   attribute \enum_value_0011001 "OP_DCBST"
35462   attribute \enum_value_0011010 "OP_DCBT"
35463   attribute \enum_value_0011011 "OP_DCBTST"
35464   attribute \enum_value_0011100 "OP_DCBZ"
35465   attribute \enum_value_0011101 "OP_DIV"
35466   attribute \enum_value_0011110 "OP_DIVE"
35467   attribute \enum_value_0011111 "OP_EXTS"
35468   attribute \enum_value_0100000 "OP_EXTSWSLI"
35469   attribute \enum_value_0100001 "OP_ICBI"
35470   attribute \enum_value_0100010 "OP_ICBT"
35471   attribute \enum_value_0100011 "OP_ISEL"
35472   attribute \enum_value_0100100 "OP_ISYNC"
35473   attribute \enum_value_0100101 "OP_LOAD"
35474   attribute \enum_value_0100110 "OP_STORE"
35475   attribute \enum_value_0100111 "OP_MADDHD"
35476   attribute \enum_value_0101000 "OP_MADDHDU"
35477   attribute \enum_value_0101001 "OP_MADDLD"
35478   attribute \enum_value_0101010 "OP_MCRF"
35479   attribute \enum_value_0101011 "OP_MCRXR"
35480   attribute \enum_value_0101100 "OP_MCRXRX"
35481   attribute \enum_value_0101101 "OP_MFCR"
35482   attribute \enum_value_0101110 "OP_MFSPR"
35483   attribute \enum_value_0101111 "OP_MOD"
35484   attribute \enum_value_0110000 "OP_MTCRF"
35485   attribute \enum_value_0110001 "OP_MTSPR"
35486   attribute \enum_value_0110010 "OP_MUL_L64"
35487   attribute \enum_value_0110011 "OP_MUL_H64"
35488   attribute \enum_value_0110100 "OP_MUL_H32"
35489   attribute \enum_value_0110101 "OP_OR"
35490   attribute \enum_value_0110110 "OP_POPCNT"
35491   attribute \enum_value_0110111 "OP_PRTY"
35492   attribute \enum_value_0111000 "OP_RLC"
35493   attribute \enum_value_0111001 "OP_RLCL"
35494   attribute \enum_value_0111010 "OP_RLCR"
35495   attribute \enum_value_0111011 "OP_SETB"
35496   attribute \enum_value_0111100 "OP_SHL"
35497   attribute \enum_value_0111101 "OP_SHR"
35498   attribute \enum_value_0111110 "OP_SYNC"
35499   attribute \enum_value_0111111 "OP_TRAP"
35500   attribute \enum_value_1000011 "OP_XOR"
35501   attribute \enum_value_1000100 "OP_SIM_CONFIG"
35502   attribute \enum_value_1000101 "OP_CROP"
35503   attribute \enum_value_1000110 "OP_RFID"
35504   attribute \enum_value_1000111 "OP_MFMSR"
35505   attribute \enum_value_1001000 "OP_MTMSRD"
35506   attribute \enum_value_1001001 "OP_SC"
35507   attribute \enum_value_1001010 "OP_MTMSR"
35508   attribute \enum_value_1001011 "OP_TLBIE"
35509   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35510   wire width 7 output 2 \dec31_dec_sub16_internal_op
35511   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35512   wire output 15 \dec31_dec_sub16_inv_a
35513   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35514   wire output 16 \dec31_dec_sub16_inv_out
35515   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35516   wire output 21 \dec31_dec_sub16_is_32b
35517   attribute \enum_base_type "LdstLen"
35518   attribute \enum_value_0000 "NONE"
35519   attribute \enum_value_0001 "is1B"
35520   attribute \enum_value_0010 "is2B"
35521   attribute \enum_value_0100 "is4B"
35522   attribute \enum_value_1000 "is8B"
35523   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35524   wire width 4 output 11 \dec31_dec_sub16_ldst_len
35525   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35526   wire output 23 \dec31_dec_sub16_lk
35527   attribute \enum_base_type "OutSel"
35528   attribute \enum_value_00 "NONE"
35529   attribute \enum_value_01 "RT"
35530   attribute \enum_value_10 "RA"
35531   attribute \enum_value_11 "SPR"
35532   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35533   wire width 2 output 8 \dec31_dec_sub16_out_sel
35534   attribute \enum_base_type "RC"
35535   attribute \enum_value_00 "NONE"
35536   attribute \enum_value_01 "ONE"
35537   attribute \enum_value_10 "RC"
35538   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35539   wire width 2 output 13 \dec31_dec_sub16_rc_sel
35540   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35541   wire output 20 \dec31_dec_sub16_rsrv
35542   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35543   wire output 24 \dec31_dec_sub16_sgl_pipe
35544   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35545   wire output 22 \dec31_dec_sub16_sgn
35546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
35547   wire output 19 \dec31_dec_sub16_sgn_ext
35548   attribute \enum_base_type "LDSTMode"
35549   attribute \enum_value_00 "NONE"
35550   attribute \enum_value_01 "update"
35551   attribute \enum_value_10 "cix"
35552   attribute \enum_value_11 "cx"
35553   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
35554   wire width 2 output 12 \dec31_dec_sub16_upd
35555   attribute \src "libresoc.v:24394.7-24394.15"
35556   wire \initial
35557   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
35558   wire width 32 input 25 \opcode_in
35559   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
35560   wire width 5 \opcode_switch
35561   attribute \src "libresoc.v:24394.7-24394.20"
35562   process $proc$libresoc.v:24394$531
35563     assign { } { }
35564     assign $0\initial[0:0] 1'0
35565     sync always
35566       update \initial $0\initial[0:0]
35567     sync init
35568   end
35569   attribute \src "libresoc.v:24651.3-24660.6"
35570   process $proc$libresoc.v:24651$507
35571     assign { } { }
35572     assign { } { }
35573     assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0]
35574     attribute \src "libresoc.v:24652.5-24652.29"
35575     switch \initial
35576       attribute \src "libresoc.v:24652.9-24652.17"
35577       case 1'1
35578       case
35579     end
35580     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35581     switch \opcode_switch
35582       attribute \src "libresoc.v:0.0-0.0"
35583       case 5'00100
35584         assign { } { }
35585         assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000
35586       case
35587         assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000
35588     end
35589     sync always
35590       update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0]
35591   end
35592   attribute \src "libresoc.v:24661.3-24670.6"
35593   process $proc$libresoc.v:24661$508
35594     assign { } { }
35595     assign { } { }
35596     assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0]
35597     attribute \src "libresoc.v:24662.5-24662.29"
35598     switch \initial
35599       attribute \src "libresoc.v:24662.9-24662.17"
35600       case 1'1
35601       case
35602     end
35603     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35604     switch \opcode_switch
35605       attribute \src "libresoc.v:0.0-0.0"
35606       case 5'00100
35607         assign { } { }
35608         assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000
35609       case
35610         assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000
35611     end
35612     sync always
35613       update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0]
35614   end
35615   attribute \src "libresoc.v:24671.3-24680.6"
35616   process $proc$libresoc.v:24671$509
35617     assign { } { }
35618     assign { } { }
35619     assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0]
35620     attribute \src "libresoc.v:24672.5-24672.29"
35621     switch \initial
35622       attribute \src "libresoc.v:24672.9-24672.17"
35623       case 1'1
35624       case
35625     end
35626     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35627     switch \opcode_switch
35628       attribute \src "libresoc.v:0.0-0.0"
35629       case 5'00100
35630         assign { } { }
35631         assign $1\dec31_dec_sub16_upd[1:0] 2'00
35632       case
35633         assign $1\dec31_dec_sub16_upd[1:0] 2'00
35634     end
35635     sync always
35636       update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0]
35637   end
35638   attribute \src "libresoc.v:24681.3-24690.6"
35639   process $proc$libresoc.v:24681$510
35640     assign { } { }
35641     assign { } { }
35642     assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0]
35643     attribute \src "libresoc.v:24682.5-24682.29"
35644     switch \initial
35645       attribute \src "libresoc.v:24682.9-24682.17"
35646       case 1'1
35647       case
35648     end
35649     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35650     switch \opcode_switch
35651       attribute \src "libresoc.v:0.0-0.0"
35652       case 5'00100
35653         assign { } { }
35654         assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00
35655       case
35656         assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00
35657     end
35658     sync always
35659       update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0]
35660   end
35661   attribute \src "libresoc.v:24691.3-24700.6"
35662   process $proc$libresoc.v:24691$511
35663     assign { } { }
35664     assign { } { }
35665     assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0]
35666     attribute \src "libresoc.v:24692.5-24692.29"
35667     switch \initial
35668       attribute \src "libresoc.v:24692.9-24692.17"
35669       case 1'1
35670       case
35671     end
35672     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35673     switch \opcode_switch
35674       attribute \src "libresoc.v:0.0-0.0"
35675       case 5'00100
35676         assign { } { }
35677         assign $1\dec31_dec_sub16_cry_in[1:0] 2'00
35678       case
35679         assign $1\dec31_dec_sub16_cry_in[1:0] 2'00
35680     end
35681     sync always
35682       update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0]
35683   end
35684   attribute \src "libresoc.v:24701.3-24710.6"
35685   process $proc$libresoc.v:24701$512
35686     assign { } { }
35687     assign { } { }
35688     assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0]
35689     attribute \src "libresoc.v:24702.5-24702.29"
35690     switch \initial
35691       attribute \src "libresoc.v:24702.9-24702.17"
35692       case 1'1
35693       case
35694     end
35695     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35696     switch \opcode_switch
35697       attribute \src "libresoc.v:0.0-0.0"
35698       case 5'00100
35699         assign { } { }
35700         assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110
35701       case
35702         assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000
35703     end
35704     sync always
35705       update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0]
35706   end
35707   attribute \src "libresoc.v:24711.3-24720.6"
35708   process $proc$libresoc.v:24711$513
35709     assign { } { }
35710     assign { } { }
35711     assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0]
35712     attribute \src "libresoc.v:24712.5-24712.29"
35713     switch \initial
35714       attribute \src "libresoc.v:24712.9-24712.17"
35715       case 1'1
35716       case
35717     end
35718     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35719     switch \opcode_switch
35720       attribute \src "libresoc.v:0.0-0.0"
35721       case 5'00100
35722         assign { } { }
35723         assign $1\dec31_dec_sub16_inv_a[0:0] 1'0
35724       case
35725         assign $1\dec31_dec_sub16_inv_a[0:0] 1'0
35726     end
35727     sync always
35728       update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0]
35729   end
35730   attribute \src "libresoc.v:24721.3-24730.6"
35731   process $proc$libresoc.v:24721$514
35732     assign { } { }
35733     assign { } { }
35734     assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0]
35735     attribute \src "libresoc.v:24722.5-24722.29"
35736     switch \initial
35737       attribute \src "libresoc.v:24722.9-24722.17"
35738       case 1'1
35739       case
35740     end
35741     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35742     switch \opcode_switch
35743       attribute \src "libresoc.v:0.0-0.0"
35744       case 5'00100
35745         assign { } { }
35746         assign $1\dec31_dec_sub16_inv_out[0:0] 1'0
35747       case
35748         assign $1\dec31_dec_sub16_inv_out[0:0] 1'0
35749     end
35750     sync always
35751       update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0]
35752   end
35753   attribute \src "libresoc.v:24731.3-24740.6"
35754   process $proc$libresoc.v:24731$515
35755     assign { } { }
35756     assign { } { }
35757     assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0]
35758     attribute \src "libresoc.v:24732.5-24732.29"
35759     switch \initial
35760       attribute \src "libresoc.v:24732.9-24732.17"
35761       case 1'1
35762       case
35763     end
35764     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35765     switch \opcode_switch
35766       attribute \src "libresoc.v:0.0-0.0"
35767       case 5'00100
35768         assign { } { }
35769         assign $1\dec31_dec_sub16_cry_out[0:0] 1'0
35770       case
35771         assign $1\dec31_dec_sub16_cry_out[0:0] 1'0
35772     end
35773     sync always
35774       update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0]
35775   end
35776   attribute \src "libresoc.v:24741.3-24750.6"
35777   process $proc$libresoc.v:24741$516
35778     assign { } { }
35779     assign { } { }
35780     assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0]
35781     attribute \src "libresoc.v:24742.5-24742.29"
35782     switch \initial
35783       attribute \src "libresoc.v:24742.9-24742.17"
35784       case 1'1
35785       case
35786     end
35787     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35788     switch \opcode_switch
35789       attribute \src "libresoc.v:0.0-0.0"
35790       case 5'00100
35791         assign { } { }
35792         assign $1\dec31_dec_sub16_br[0:0] 1'0
35793       case
35794         assign $1\dec31_dec_sub16_br[0:0] 1'0
35795     end
35796     sync always
35797       update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0]
35798   end
35799   attribute \src "libresoc.v:24751.3-24760.6"
35800   process $proc$libresoc.v:24751$517
35801     assign { } { }
35802     assign { } { }
35803     assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0]
35804     attribute \src "libresoc.v:24752.5-24752.29"
35805     switch \initial
35806       attribute \src "libresoc.v:24752.9-24752.17"
35807       case 1'1
35808       case
35809     end
35810     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35811     switch \opcode_switch
35812       attribute \src "libresoc.v:0.0-0.0"
35813       case 5'00100
35814         assign { } { }
35815         assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0
35816       case
35817         assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0
35818     end
35819     sync always
35820       update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0]
35821   end
35822   attribute \src "libresoc.v:24761.3-24770.6"
35823   process $proc$libresoc.v:24761$518
35824     assign { } { }
35825     assign { } { }
35826     assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0]
35827     attribute \src "libresoc.v:24762.5-24762.29"
35828     switch \initial
35829       attribute \src "libresoc.v:24762.9-24762.17"
35830       case 1'1
35831       case
35832     end
35833     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35834     switch \opcode_switch
35835       attribute \src "libresoc.v:0.0-0.0"
35836       case 5'00100
35837         assign { } { }
35838         assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000
35839       case
35840         assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000
35841     end
35842     sync always
35843       update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0]
35844   end
35845   attribute \src "libresoc.v:24771.3-24780.6"
35846   process $proc$libresoc.v:24771$519
35847     assign { } { }
35848     assign { } { }
35849     assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0]
35850     attribute \src "libresoc.v:24772.5-24772.29"
35851     switch \initial
35852       attribute \src "libresoc.v:24772.9-24772.17"
35853       case 1'1
35854       case
35855     end
35856     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35857     switch \opcode_switch
35858       attribute \src "libresoc.v:0.0-0.0"
35859       case 5'00100
35860         assign { } { }
35861         assign $1\dec31_dec_sub16_rsrv[0:0] 1'0
35862       case
35863         assign $1\dec31_dec_sub16_rsrv[0:0] 1'0
35864     end
35865     sync always
35866       update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0]
35867   end
35868   attribute \src "libresoc.v:24781.3-24790.6"
35869   process $proc$libresoc.v:24781$520
35870     assign { } { }
35871     assign { } { }
35872     assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0]
35873     attribute \src "libresoc.v:24782.5-24782.29"
35874     switch \initial
35875       attribute \src "libresoc.v:24782.9-24782.17"
35876       case 1'1
35877       case
35878     end
35879     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35880     switch \opcode_switch
35881       attribute \src "libresoc.v:0.0-0.0"
35882       case 5'00100
35883         assign { } { }
35884         assign $1\dec31_dec_sub16_is_32b[0:0] 1'0
35885       case
35886         assign $1\dec31_dec_sub16_is_32b[0:0] 1'0
35887     end
35888     sync always
35889       update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0]
35890   end
35891   attribute \src "libresoc.v:24791.3-24800.6"
35892   process $proc$libresoc.v:24791$521
35893     assign { } { }
35894     assign { } { }
35895     assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0]
35896     attribute \src "libresoc.v:24792.5-24792.29"
35897     switch \initial
35898       attribute \src "libresoc.v:24792.9-24792.17"
35899       case 1'1
35900       case
35901     end
35902     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35903     switch \opcode_switch
35904       attribute \src "libresoc.v:0.0-0.0"
35905       case 5'00100
35906         assign { } { }
35907         assign $1\dec31_dec_sub16_sgn[0:0] 1'0
35908       case
35909         assign $1\dec31_dec_sub16_sgn[0:0] 1'0
35910     end
35911     sync always
35912       update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0]
35913   end
35914   attribute \src "libresoc.v:24801.3-24810.6"
35915   process $proc$libresoc.v:24801$522
35916     assign { } { }
35917     assign { } { }
35918     assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0]
35919     attribute \src "libresoc.v:24802.5-24802.29"
35920     switch \initial
35921       attribute \src "libresoc.v:24802.9-24802.17"
35922       case 1'1
35923       case
35924     end
35925     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35926     switch \opcode_switch
35927       attribute \src "libresoc.v:0.0-0.0"
35928       case 5'00100
35929         assign { } { }
35930         assign $1\dec31_dec_sub16_lk[0:0] 1'0
35931       case
35932         assign $1\dec31_dec_sub16_lk[0:0] 1'0
35933     end
35934     sync always
35935       update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0]
35936   end
35937   attribute \src "libresoc.v:24811.3-24820.6"
35938   process $proc$libresoc.v:24811$523
35939     assign { } { }
35940     assign { } { }
35941     assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0]
35942     attribute \src "libresoc.v:24812.5-24812.29"
35943     switch \initial
35944       attribute \src "libresoc.v:24812.9-24812.17"
35945       case 1'1
35946       case
35947     end
35948     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35949     switch \opcode_switch
35950       attribute \src "libresoc.v:0.0-0.0"
35951       case 5'00100
35952         assign { } { }
35953         assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0
35954       case
35955         assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0
35956     end
35957     sync always
35958       update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0]
35959   end
35960   attribute \src "libresoc.v:24821.3-24830.6"
35961   process $proc$libresoc.v:24821$524
35962     assign { } { }
35963     assign { } { }
35964     assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0]
35965     attribute \src "libresoc.v:24822.5-24822.29"
35966     switch \initial
35967       attribute \src "libresoc.v:24822.9-24822.17"
35968       case 1'1
35969       case
35970     end
35971     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35972     switch \opcode_switch
35973       attribute \src "libresoc.v:0.0-0.0"
35974       case 5'00100
35975         assign { } { }
35976         assign $1\dec31_dec_sub16_form[4:0] 5'01010
35977       case
35978         assign $1\dec31_dec_sub16_form[4:0] 5'00000
35979     end
35980     sync always
35981       update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0]
35982   end
35983   attribute \src "libresoc.v:24831.3-24840.6"
35984   process $proc$libresoc.v:24831$525
35985     assign { } { }
35986     assign { } { }
35987     assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0]
35988     attribute \src "libresoc.v:24832.5-24832.29"
35989     switch \initial
35990       attribute \src "libresoc.v:24832.9-24832.17"
35991       case 1'1
35992       case
35993     end
35994     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
35995     switch \opcode_switch
35996       attribute \src "libresoc.v:0.0-0.0"
35997       case 5'00100
35998         assign { } { }
35999         assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100
36000       case
36001         assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000
36002     end
36003     sync always
36004       update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0]
36005   end
36006   attribute \src "libresoc.v:24841.3-24850.6"
36007   process $proc$libresoc.v:24841$526
36008     assign { } { }
36009     assign { } { }
36010     assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0]
36011     attribute \src "libresoc.v:24842.5-24842.29"
36012     switch \initial
36013       attribute \src "libresoc.v:24842.9-24842.17"
36014       case 1'1
36015       case
36016     end
36017     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36018     switch \opcode_switch
36019       attribute \src "libresoc.v:0.0-0.0"
36020       case 5'00100
36021         assign { } { }
36022         assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000
36023       case
36024         assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000
36025     end
36026     sync always
36027       update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0]
36028   end
36029   attribute \src "libresoc.v:24851.3-24860.6"
36030   process $proc$libresoc.v:24851$527
36031     assign { } { }
36032     assign { } { }
36033     assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0]
36034     attribute \src "libresoc.v:24852.5-24852.29"
36035     switch \initial
36036       attribute \src "libresoc.v:24852.9-24852.17"
36037       case 1'1
36038       case
36039     end
36040     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36041     switch \opcode_switch
36042       attribute \src "libresoc.v:0.0-0.0"
36043       case 5'00100
36044         assign { } { }
36045         assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00
36046       case
36047         assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00
36048     end
36049     sync always
36050       update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0]
36051   end
36052   attribute \src "libresoc.v:24861.3-24870.6"
36053   process $proc$libresoc.v:24861$528
36054     assign { } { }
36055     assign { } { }
36056     assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0]
36057     attribute \src "libresoc.v:24862.5-24862.29"
36058     switch \initial
36059       attribute \src "libresoc.v:24862.9-24862.17"
36060       case 1'1
36061       case
36062     end
36063     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36064     switch \opcode_switch
36065       attribute \src "libresoc.v:0.0-0.0"
36066       case 5'00100
36067         assign { } { }
36068         assign $1\dec31_dec_sub16_out_sel[1:0] 2'00
36069       case
36070         assign $1\dec31_dec_sub16_out_sel[1:0] 2'00
36071     end
36072     sync always
36073       update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0]
36074   end
36075   attribute \src "libresoc.v:24871.3-24880.6"
36076   process $proc$libresoc.v:24871$529
36077     assign { } { }
36078     assign { } { }
36079     assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0]
36080     attribute \src "libresoc.v:24872.5-24872.29"
36081     switch \initial
36082       attribute \src "libresoc.v:24872.9-24872.17"
36083       case 1'1
36084       case
36085     end
36086     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36087     switch \opcode_switch
36088       attribute \src "libresoc.v:0.0-0.0"
36089       case 5'00100
36090         assign { } { }
36091         assign $1\dec31_dec_sub16_cr_in[2:0] 3'110
36092       case
36093         assign $1\dec31_dec_sub16_cr_in[2:0] 3'000
36094     end
36095     sync always
36096       update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0]
36097   end
36098   attribute \src "libresoc.v:24881.3-24890.6"
36099   process $proc$libresoc.v:24881$530
36100     assign { } { }
36101     assign { } { }
36102     assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0]
36103     attribute \src "libresoc.v:24882.5-24882.29"
36104     switch \initial
36105       attribute \src "libresoc.v:24882.9-24882.17"
36106       case 1'1
36107       case
36108     end
36109     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36110     switch \opcode_switch
36111       attribute \src "libresoc.v:0.0-0.0"
36112       case 5'00100
36113         assign { } { }
36114         assign $1\dec31_dec_sub16_cr_out[2:0] 3'100
36115       case
36116         assign $1\dec31_dec_sub16_cr_out[2:0] 3'000
36117     end
36118     sync always
36119       update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0]
36120   end
36121   connect \opcode_switch \opcode_in [10:6]
36122 end
36123 attribute \src "libresoc.v:24896.1-25683.10"
36124 attribute \cells_not_processed 1
36125 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18"
36126 attribute \generator "nMigen"
36127 module \dec31_dec_sub18
36128   attribute \src "libresoc.v:25264.3-25285.6"
36129   wire width 8 $0\dec31_dec_sub18_asmcode[7:0]
36130   attribute \src "libresoc.v:25352.3-25373.6"
36131   wire $0\dec31_dec_sub18_br[0:0]
36132   attribute \src "libresoc.v:25638.3-25659.6"
36133   wire width 3 $0\dec31_dec_sub18_cr_in[2:0]
36134   attribute \src "libresoc.v:25660.3-25681.6"
36135   wire width 3 $0\dec31_dec_sub18_cr_out[2:0]
36136   attribute \src "libresoc.v:25242.3-25263.6"
36137   wire width 2 $0\dec31_dec_sub18_cry_in[1:0]
36138   attribute \src "libresoc.v:25330.3-25351.6"
36139   wire $0\dec31_dec_sub18_cry_out[0:0]
36140   attribute \src "libresoc.v:25528.3-25549.6"
36141   wire width 5 $0\dec31_dec_sub18_form[4:0]
36142   attribute \src "libresoc.v:25154.3-25175.6"
36143   wire width 12 $0\dec31_dec_sub18_function_unit[11:0]
36144   attribute \src "libresoc.v:25550.3-25571.6"
36145   wire width 3 $0\dec31_dec_sub18_in1_sel[2:0]
36146   attribute \src "libresoc.v:25572.3-25593.6"
36147   wire width 4 $0\dec31_dec_sub18_in2_sel[3:0]
36148   attribute \src "libresoc.v:25594.3-25615.6"
36149   wire width 2 $0\dec31_dec_sub18_in3_sel[1:0]
36150   attribute \src "libresoc.v:25396.3-25417.6"
36151   wire width 7 $0\dec31_dec_sub18_internal_op[6:0]
36152   attribute \src "libresoc.v:25286.3-25307.6"
36153   wire $0\dec31_dec_sub18_inv_a[0:0]
36154   attribute \src "libresoc.v:25308.3-25329.6"
36155   wire $0\dec31_dec_sub18_inv_out[0:0]
36156   attribute \src "libresoc.v:25440.3-25461.6"
36157   wire $0\dec31_dec_sub18_is_32b[0:0]
36158   attribute \src "libresoc.v:25176.3-25197.6"
36159   wire width 4 $0\dec31_dec_sub18_ldst_len[3:0]
36160   attribute \src "libresoc.v:25484.3-25505.6"
36161   wire $0\dec31_dec_sub18_lk[0:0]
36162   attribute \src "libresoc.v:25616.3-25637.6"
36163   wire width 2 $0\dec31_dec_sub18_out_sel[1:0]
36164   attribute \src "libresoc.v:25220.3-25241.6"
36165   wire width 2 $0\dec31_dec_sub18_rc_sel[1:0]
36166   attribute \src "libresoc.v:25418.3-25439.6"
36167   wire $0\dec31_dec_sub18_rsrv[0:0]
36168   attribute \src "libresoc.v:25506.3-25527.6"
36169   wire $0\dec31_dec_sub18_sgl_pipe[0:0]
36170   attribute \src "libresoc.v:25462.3-25483.6"
36171   wire $0\dec31_dec_sub18_sgn[0:0]
36172   attribute \src "libresoc.v:25374.3-25395.6"
36173   wire $0\dec31_dec_sub18_sgn_ext[0:0]
36174   attribute \src "libresoc.v:25198.3-25219.6"
36175   wire width 2 $0\dec31_dec_sub18_upd[1:0]
36176   attribute \src "libresoc.v:24897.7-24897.20"
36177   wire $0\initial[0:0]
36178   attribute \src "libresoc.v:25264.3-25285.6"
36179   wire width 8 $1\dec31_dec_sub18_asmcode[7:0]
36180   attribute \src "libresoc.v:25352.3-25373.6"
36181   wire $1\dec31_dec_sub18_br[0:0]
36182   attribute \src "libresoc.v:25638.3-25659.6"
36183   wire width 3 $1\dec31_dec_sub18_cr_in[2:0]
36184   attribute \src "libresoc.v:25660.3-25681.6"
36185   wire width 3 $1\dec31_dec_sub18_cr_out[2:0]
36186   attribute \src "libresoc.v:25242.3-25263.6"
36187   wire width 2 $1\dec31_dec_sub18_cry_in[1:0]
36188   attribute \src "libresoc.v:25330.3-25351.6"
36189   wire $1\dec31_dec_sub18_cry_out[0:0]
36190   attribute \src "libresoc.v:25528.3-25549.6"
36191   wire width 5 $1\dec31_dec_sub18_form[4:0]
36192   attribute \src "libresoc.v:25154.3-25175.6"
36193   wire width 12 $1\dec31_dec_sub18_function_unit[11:0]
36194   attribute \src "libresoc.v:25550.3-25571.6"
36195   wire width 3 $1\dec31_dec_sub18_in1_sel[2:0]
36196   attribute \src "libresoc.v:25572.3-25593.6"
36197   wire width 4 $1\dec31_dec_sub18_in2_sel[3:0]
36198   attribute \src "libresoc.v:25594.3-25615.6"
36199   wire width 2 $1\dec31_dec_sub18_in3_sel[1:0]
36200   attribute \src "libresoc.v:25396.3-25417.6"
36201   wire width 7 $1\dec31_dec_sub18_internal_op[6:0]
36202   attribute \src "libresoc.v:25286.3-25307.6"
36203   wire $1\dec31_dec_sub18_inv_a[0:0]
36204   attribute \src "libresoc.v:25308.3-25329.6"
36205   wire $1\dec31_dec_sub18_inv_out[0:0]
36206   attribute \src "libresoc.v:25440.3-25461.6"
36207   wire $1\dec31_dec_sub18_is_32b[0:0]
36208   attribute \src "libresoc.v:25176.3-25197.6"
36209   wire width 4 $1\dec31_dec_sub18_ldst_len[3:0]
36210   attribute \src "libresoc.v:25484.3-25505.6"
36211   wire $1\dec31_dec_sub18_lk[0:0]
36212   attribute \src "libresoc.v:25616.3-25637.6"
36213   wire width 2 $1\dec31_dec_sub18_out_sel[1:0]
36214   attribute \src "libresoc.v:25220.3-25241.6"
36215   wire width 2 $1\dec31_dec_sub18_rc_sel[1:0]
36216   attribute \src "libresoc.v:25418.3-25439.6"
36217   wire $1\dec31_dec_sub18_rsrv[0:0]
36218   attribute \src "libresoc.v:25506.3-25527.6"
36219   wire $1\dec31_dec_sub18_sgl_pipe[0:0]
36220   attribute \src "libresoc.v:25462.3-25483.6"
36221   wire $1\dec31_dec_sub18_sgn[0:0]
36222   attribute \src "libresoc.v:25374.3-25395.6"
36223   wire $1\dec31_dec_sub18_sgn_ext[0:0]
36224   attribute \src "libresoc.v:25198.3-25219.6"
36225   wire width 2 $1\dec31_dec_sub18_upd[1:0]
36226   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36227   wire width 8 output 4 \dec31_dec_sub18_asmcode
36228   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36229   wire output 18 \dec31_dec_sub18_br
36230   attribute \enum_base_type "CRInSel"
36231   attribute \enum_value_000 "NONE"
36232   attribute \enum_value_001 "CR0"
36233   attribute \enum_value_010 "BI"
36234   attribute \enum_value_011 "BFA"
36235   attribute \enum_value_100 "BA_BB"
36236   attribute \enum_value_101 "BC"
36237   attribute \enum_value_110 "WHOLE_REG"
36238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36239   wire width 3 output 9 \dec31_dec_sub18_cr_in
36240   attribute \enum_base_type "CROutSel"
36241   attribute \enum_value_000 "NONE"
36242   attribute \enum_value_001 "CR0"
36243   attribute \enum_value_010 "BF"
36244   attribute \enum_value_011 "BT"
36245   attribute \enum_value_100 "WHOLE_REG"
36246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36247   wire width 3 output 10 \dec31_dec_sub18_cr_out
36248   attribute \enum_base_type "CryIn"
36249   attribute \enum_value_00 "ZERO"
36250   attribute \enum_value_01 "ONE"
36251   attribute \enum_value_10 "CA"
36252   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36253   wire width 2 output 14 \dec31_dec_sub18_cry_in
36254   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36255   wire output 17 \dec31_dec_sub18_cry_out
36256   attribute \enum_base_type "Form"
36257   attribute \enum_value_00000 "NONE"
36258   attribute \enum_value_00001 "I"
36259   attribute \enum_value_00010 "B"
36260   attribute \enum_value_00011 "SC"
36261   attribute \enum_value_00100 "D"
36262   attribute \enum_value_00101 "DS"
36263   attribute \enum_value_00110 "DQ"
36264   attribute \enum_value_00111 "DX"
36265   attribute \enum_value_01000 "X"
36266   attribute \enum_value_01001 "XL"
36267   attribute \enum_value_01010 "XFX"
36268   attribute \enum_value_01011 "XFL"
36269   attribute \enum_value_01100 "XX1"
36270   attribute \enum_value_01101 "XX2"
36271   attribute \enum_value_01110 "XX3"
36272   attribute \enum_value_01111 "XX4"
36273   attribute \enum_value_10000 "XS"
36274   attribute \enum_value_10001 "XO"
36275   attribute \enum_value_10010 "A"
36276   attribute \enum_value_10011 "M"
36277   attribute \enum_value_10100 "MD"
36278   attribute \enum_value_10101 "MDS"
36279   attribute \enum_value_10110 "VA"
36280   attribute \enum_value_10111 "VC"
36281   attribute \enum_value_11000 "VX"
36282   attribute \enum_value_11001 "EVX"
36283   attribute \enum_value_11010 "EVS"
36284   attribute \enum_value_11011 "Z22"
36285   attribute \enum_value_11100 "Z23"
36286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36287   wire width 5 output 3 \dec31_dec_sub18_form
36288   attribute \enum_base_type "Function"
36289   attribute \enum_value_000000000000 "NONE"
36290   attribute \enum_value_000000000010 "ALU"
36291   attribute \enum_value_000000000100 "LDST"
36292   attribute \enum_value_000000001000 "SHIFT_ROT"
36293   attribute \enum_value_000000010000 "LOGICAL"
36294   attribute \enum_value_000000100000 "BRANCH"
36295   attribute \enum_value_000001000000 "CR"
36296   attribute \enum_value_000010000000 "TRAP"
36297   attribute \enum_value_000100000000 "MUL"
36298   attribute \enum_value_001000000000 "DIV"
36299   attribute \enum_value_010000000000 "SPR"
36300   attribute \enum_value_100000000000 "MMU"
36301   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36302   wire width 12 output 1 \dec31_dec_sub18_function_unit
36303   attribute \enum_base_type "In1Sel"
36304   attribute \enum_value_000 "NONE"
36305   attribute \enum_value_001 "RA"
36306   attribute \enum_value_010 "RA_OR_ZERO"
36307   attribute \enum_value_011 "SPR"
36308   attribute \enum_value_100 "RS"
36309   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36310   wire width 3 output 5 \dec31_dec_sub18_in1_sel
36311   attribute \enum_base_type "In2Sel"
36312   attribute \enum_value_0000 "NONE"
36313   attribute \enum_value_0001 "RB"
36314   attribute \enum_value_0010 "CONST_UI"
36315   attribute \enum_value_0011 "CONST_SI"
36316   attribute \enum_value_0100 "CONST_UI_HI"
36317   attribute \enum_value_0101 "CONST_SI_HI"
36318   attribute \enum_value_0110 "CONST_LI"
36319   attribute \enum_value_0111 "CONST_BD"
36320   attribute \enum_value_1000 "CONST_DS"
36321   attribute \enum_value_1001 "CONST_M1"
36322   attribute \enum_value_1010 "CONST_SH"
36323   attribute \enum_value_1011 "CONST_SH32"
36324   attribute \enum_value_1100 "SPR"
36325   attribute \enum_value_1101 "RS"
36326   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36327   wire width 4 output 6 \dec31_dec_sub18_in2_sel
36328   attribute \enum_base_type "In3Sel"
36329   attribute \enum_value_00 "NONE"
36330   attribute \enum_value_01 "RS"
36331   attribute \enum_value_10 "RB"
36332   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36333   wire width 2 output 7 \dec31_dec_sub18_in3_sel
36334   attribute \enum_base_type "MicrOp"
36335   attribute \enum_value_0000000 "OP_ILLEGAL"
36336   attribute \enum_value_0000001 "OP_NOP"
36337   attribute \enum_value_0000010 "OP_ADD"
36338   attribute \enum_value_0000011 "OP_ADDPCIS"
36339   attribute \enum_value_0000100 "OP_AND"
36340   attribute \enum_value_0000101 "OP_ATTN"
36341   attribute \enum_value_0000110 "OP_B"
36342   attribute \enum_value_0000111 "OP_BC"
36343   attribute \enum_value_0001000 "OP_BCREG"
36344   attribute \enum_value_0001001 "OP_BPERM"
36345   attribute \enum_value_0001010 "OP_CMP"
36346   attribute \enum_value_0001011 "OP_CMPB"
36347   attribute \enum_value_0001100 "OP_CMPEQB"
36348   attribute \enum_value_0001101 "OP_CMPRB"
36349   attribute \enum_value_0001110 "OP_CNTZ"
36350   attribute \enum_value_0001111 "OP_CRAND"
36351   attribute \enum_value_0010000 "OP_CRANDC"
36352   attribute \enum_value_0010001 "OP_CREQV"
36353   attribute \enum_value_0010010 "OP_CRNAND"
36354   attribute \enum_value_0010011 "OP_CRNOR"
36355   attribute \enum_value_0010100 "OP_CROR"
36356   attribute \enum_value_0010101 "OP_CRORC"
36357   attribute \enum_value_0010110 "OP_CRXOR"
36358   attribute \enum_value_0010111 "OP_DARN"
36359   attribute \enum_value_0011000 "OP_DCBF"
36360   attribute \enum_value_0011001 "OP_DCBST"
36361   attribute \enum_value_0011010 "OP_DCBT"
36362   attribute \enum_value_0011011 "OP_DCBTST"
36363   attribute \enum_value_0011100 "OP_DCBZ"
36364   attribute \enum_value_0011101 "OP_DIV"
36365   attribute \enum_value_0011110 "OP_DIVE"
36366   attribute \enum_value_0011111 "OP_EXTS"
36367   attribute \enum_value_0100000 "OP_EXTSWSLI"
36368   attribute \enum_value_0100001 "OP_ICBI"
36369   attribute \enum_value_0100010 "OP_ICBT"
36370   attribute \enum_value_0100011 "OP_ISEL"
36371   attribute \enum_value_0100100 "OP_ISYNC"
36372   attribute \enum_value_0100101 "OP_LOAD"
36373   attribute \enum_value_0100110 "OP_STORE"
36374   attribute \enum_value_0100111 "OP_MADDHD"
36375   attribute \enum_value_0101000 "OP_MADDHDU"
36376   attribute \enum_value_0101001 "OP_MADDLD"
36377   attribute \enum_value_0101010 "OP_MCRF"
36378   attribute \enum_value_0101011 "OP_MCRXR"
36379   attribute \enum_value_0101100 "OP_MCRXRX"
36380   attribute \enum_value_0101101 "OP_MFCR"
36381   attribute \enum_value_0101110 "OP_MFSPR"
36382   attribute \enum_value_0101111 "OP_MOD"
36383   attribute \enum_value_0110000 "OP_MTCRF"
36384   attribute \enum_value_0110001 "OP_MTSPR"
36385   attribute \enum_value_0110010 "OP_MUL_L64"
36386   attribute \enum_value_0110011 "OP_MUL_H64"
36387   attribute \enum_value_0110100 "OP_MUL_H32"
36388   attribute \enum_value_0110101 "OP_OR"
36389   attribute \enum_value_0110110 "OP_POPCNT"
36390   attribute \enum_value_0110111 "OP_PRTY"
36391   attribute \enum_value_0111000 "OP_RLC"
36392   attribute \enum_value_0111001 "OP_RLCL"
36393   attribute \enum_value_0111010 "OP_RLCR"
36394   attribute \enum_value_0111011 "OP_SETB"
36395   attribute \enum_value_0111100 "OP_SHL"
36396   attribute \enum_value_0111101 "OP_SHR"
36397   attribute \enum_value_0111110 "OP_SYNC"
36398   attribute \enum_value_0111111 "OP_TRAP"
36399   attribute \enum_value_1000011 "OP_XOR"
36400   attribute \enum_value_1000100 "OP_SIM_CONFIG"
36401   attribute \enum_value_1000101 "OP_CROP"
36402   attribute \enum_value_1000110 "OP_RFID"
36403   attribute \enum_value_1000111 "OP_MFMSR"
36404   attribute \enum_value_1001000 "OP_MTMSRD"
36405   attribute \enum_value_1001001 "OP_SC"
36406   attribute \enum_value_1001010 "OP_MTMSR"
36407   attribute \enum_value_1001011 "OP_TLBIE"
36408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36409   wire width 7 output 2 \dec31_dec_sub18_internal_op
36410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36411   wire output 15 \dec31_dec_sub18_inv_a
36412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36413   wire output 16 \dec31_dec_sub18_inv_out
36414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36415   wire output 21 \dec31_dec_sub18_is_32b
36416   attribute \enum_base_type "LdstLen"
36417   attribute \enum_value_0000 "NONE"
36418   attribute \enum_value_0001 "is1B"
36419   attribute \enum_value_0010 "is2B"
36420   attribute \enum_value_0100 "is4B"
36421   attribute \enum_value_1000 "is8B"
36422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36423   wire width 4 output 11 \dec31_dec_sub18_ldst_len
36424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36425   wire output 23 \dec31_dec_sub18_lk
36426   attribute \enum_base_type "OutSel"
36427   attribute \enum_value_00 "NONE"
36428   attribute \enum_value_01 "RT"
36429   attribute \enum_value_10 "RA"
36430   attribute \enum_value_11 "SPR"
36431   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36432   wire width 2 output 8 \dec31_dec_sub18_out_sel
36433   attribute \enum_base_type "RC"
36434   attribute \enum_value_00 "NONE"
36435   attribute \enum_value_01 "ONE"
36436   attribute \enum_value_10 "RC"
36437   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36438   wire width 2 output 13 \dec31_dec_sub18_rc_sel
36439   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36440   wire output 20 \dec31_dec_sub18_rsrv
36441   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36442   wire output 24 \dec31_dec_sub18_sgl_pipe
36443   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36444   wire output 22 \dec31_dec_sub18_sgn
36445   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
36446   wire output 19 \dec31_dec_sub18_sgn_ext
36447   attribute \enum_base_type "LDSTMode"
36448   attribute \enum_value_00 "NONE"
36449   attribute \enum_value_01 "update"
36450   attribute \enum_value_10 "cix"
36451   attribute \enum_value_11 "cx"
36452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
36453   wire width 2 output 12 \dec31_dec_sub18_upd
36454   attribute \src "libresoc.v:24897.7-24897.15"
36455   wire \initial
36456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
36457   wire width 32 input 25 \opcode_in
36458   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
36459   wire width 5 \opcode_switch
36460   attribute \src "libresoc.v:24897.7-24897.20"
36461   process $proc$libresoc.v:24897$556
36462     assign { } { }
36463     assign $0\initial[0:0] 1'0
36464     sync always
36465       update \initial $0\initial[0:0]
36466     sync init
36467   end
36468   attribute \src "libresoc.v:25154.3-25175.6"
36469   process $proc$libresoc.v:25154$532
36470     assign { } { }
36471     assign { } { }
36472     assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0]
36473     attribute \src "libresoc.v:25155.5-25155.29"
36474     switch \initial
36475       attribute \src "libresoc.v:25155.9-25155.17"
36476       case 1'1
36477       case
36478     end
36479     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36480     switch \opcode_switch
36481       attribute \src "libresoc.v:0.0-0.0"
36482       case 5'00101
36483         assign { } { }
36484         assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000
36485       attribute \src "libresoc.v:0.0-0.0"
36486       case 5'00100
36487         assign { } { }
36488         assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000
36489       attribute \src "libresoc.v:0.0-0.0"
36490       case 5'01111
36491         assign { } { }
36492         assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000
36493       attribute \src "libresoc.v:0.0-0.0"
36494       case 5'01001
36495         assign { } { }
36496         assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000
36497       attribute \src "libresoc.v:0.0-0.0"
36498       case 5'01000
36499         assign { } { }
36500         assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000
36501       case
36502         assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000
36503     end
36504     sync always
36505       update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0]
36506   end
36507   attribute \src "libresoc.v:25176.3-25197.6"
36508   process $proc$libresoc.v:25176$533
36509     assign { } { }
36510     assign { } { }
36511     assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0]
36512     attribute \src "libresoc.v:25177.5-25177.29"
36513     switch \initial
36514       attribute \src "libresoc.v:25177.9-25177.17"
36515       case 1'1
36516       case
36517     end
36518     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36519     switch \opcode_switch
36520       attribute \src "libresoc.v:0.0-0.0"
36521       case 5'00101
36522         assign { } { }
36523         assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000
36524       attribute \src "libresoc.v:0.0-0.0"
36525       case 5'00100
36526         assign { } { }
36527         assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000
36528       attribute \src "libresoc.v:0.0-0.0"
36529       case 5'01111
36530         assign { } { }
36531         assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000
36532       attribute \src "libresoc.v:0.0-0.0"
36533       case 5'01001
36534         assign { } { }
36535         assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000
36536       attribute \src "libresoc.v:0.0-0.0"
36537       case 5'01000
36538         assign { } { }
36539         assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000
36540       case
36541         assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000
36542     end
36543     sync always
36544       update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0]
36545   end
36546   attribute \src "libresoc.v:25198.3-25219.6"
36547   process $proc$libresoc.v:25198$534
36548     assign { } { }
36549     assign { } { }
36550     assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0]
36551     attribute \src "libresoc.v:25199.5-25199.29"
36552     switch \initial
36553       attribute \src "libresoc.v:25199.9-25199.17"
36554       case 1'1
36555       case
36556     end
36557     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36558     switch \opcode_switch
36559       attribute \src "libresoc.v:0.0-0.0"
36560       case 5'00101
36561         assign { } { }
36562         assign $1\dec31_dec_sub18_upd[1:0] 2'00
36563       attribute \src "libresoc.v:0.0-0.0"
36564       case 5'00100
36565         assign { } { }
36566         assign $1\dec31_dec_sub18_upd[1:0] 2'00
36567       attribute \src "libresoc.v:0.0-0.0"
36568       case 5'01111
36569         assign { } { }
36570         assign $1\dec31_dec_sub18_upd[1:0] 2'00
36571       attribute \src "libresoc.v:0.0-0.0"
36572       case 5'01001
36573         assign { } { }
36574         assign $1\dec31_dec_sub18_upd[1:0] 2'00
36575       attribute \src "libresoc.v:0.0-0.0"
36576       case 5'01000
36577         assign { } { }
36578         assign $1\dec31_dec_sub18_upd[1:0] 2'00
36579       case
36580         assign $1\dec31_dec_sub18_upd[1:0] 2'00
36581     end
36582     sync always
36583       update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0]
36584   end
36585   attribute \src "libresoc.v:25220.3-25241.6"
36586   process $proc$libresoc.v:25220$535
36587     assign { } { }
36588     assign { } { }
36589     assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0]
36590     attribute \src "libresoc.v:25221.5-25221.29"
36591     switch \initial
36592       attribute \src "libresoc.v:25221.9-25221.17"
36593       case 1'1
36594       case
36595     end
36596     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36597     switch \opcode_switch
36598       attribute \src "libresoc.v:0.0-0.0"
36599       case 5'00101
36600         assign { } { }
36601         assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00
36602       attribute \src "libresoc.v:0.0-0.0"
36603       case 5'00100
36604         assign { } { }
36605         assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00
36606       attribute \src "libresoc.v:0.0-0.0"
36607       case 5'01111
36608         assign { } { }
36609         assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00
36610       attribute \src "libresoc.v:0.0-0.0"
36611       case 5'01001
36612         assign { } { }
36613         assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00
36614       attribute \src "libresoc.v:0.0-0.0"
36615       case 5'01000
36616         assign { } { }
36617         assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00
36618       case
36619         assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00
36620     end
36621     sync always
36622       update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0]
36623   end
36624   attribute \src "libresoc.v:25242.3-25263.6"
36625   process $proc$libresoc.v:25242$536
36626     assign { } { }
36627     assign { } { }
36628     assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0]
36629     attribute \src "libresoc.v:25243.5-25243.29"
36630     switch \initial
36631       attribute \src "libresoc.v:25243.9-25243.17"
36632       case 1'1
36633       case
36634     end
36635     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36636     switch \opcode_switch
36637       attribute \src "libresoc.v:0.0-0.0"
36638       case 5'00101
36639         assign { } { }
36640         assign $1\dec31_dec_sub18_cry_in[1:0] 2'00
36641       attribute \src "libresoc.v:0.0-0.0"
36642       case 5'00100
36643         assign { } { }
36644         assign $1\dec31_dec_sub18_cry_in[1:0] 2'00
36645       attribute \src "libresoc.v:0.0-0.0"
36646       case 5'01111
36647         assign { } { }
36648         assign $1\dec31_dec_sub18_cry_in[1:0] 2'00
36649       attribute \src "libresoc.v:0.0-0.0"
36650       case 5'01001
36651         assign { } { }
36652         assign $1\dec31_dec_sub18_cry_in[1:0] 2'00
36653       attribute \src "libresoc.v:0.0-0.0"
36654       case 5'01000
36655         assign { } { }
36656         assign $1\dec31_dec_sub18_cry_in[1:0] 2'00
36657       case
36658         assign $1\dec31_dec_sub18_cry_in[1:0] 2'00
36659     end
36660     sync always
36661       update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0]
36662   end
36663   attribute \src "libresoc.v:25264.3-25285.6"
36664   process $proc$libresoc.v:25264$537
36665     assign { } { }
36666     assign { } { }
36667     assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0]
36668     attribute \src "libresoc.v:25265.5-25265.29"
36669     switch \initial
36670       attribute \src "libresoc.v:25265.9-25265.17"
36671       case 1'1
36672       case
36673     end
36674     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36675     switch \opcode_switch
36676       attribute \src "libresoc.v:0.0-0.0"
36677       case 5'00101
36678         assign { } { }
36679         assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000
36680       attribute \src "libresoc.v:0.0-0.0"
36681       case 5'00100
36682         assign { } { }
36683         assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111
36684       attribute \src "libresoc.v:0.0-0.0"
36685       case 5'01111
36686         assign { } { }
36687         assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101
36688       attribute \src "libresoc.v:0.0-0.0"
36689       case 5'01001
36690         assign { } { }
36691         assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100
36692       attribute \src "libresoc.v:0.0-0.0"
36693       case 5'01000
36694         assign { } { }
36695         assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101
36696       case
36697         assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000
36698     end
36699     sync always
36700       update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0]
36701   end
36702   attribute \src "libresoc.v:25286.3-25307.6"
36703   process $proc$libresoc.v:25286$538
36704     assign { } { }
36705     assign { } { }
36706     assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0]
36707     attribute \src "libresoc.v:25287.5-25287.29"
36708     switch \initial
36709       attribute \src "libresoc.v:25287.9-25287.17"
36710       case 1'1
36711       case
36712     end
36713     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36714     switch \opcode_switch
36715       attribute \src "libresoc.v:0.0-0.0"
36716       case 5'00101
36717         assign { } { }
36718         assign $1\dec31_dec_sub18_inv_a[0:0] 1'0
36719       attribute \src "libresoc.v:0.0-0.0"
36720       case 5'00100
36721         assign { } { }
36722         assign $1\dec31_dec_sub18_inv_a[0:0] 1'0
36723       attribute \src "libresoc.v:0.0-0.0"
36724       case 5'01111
36725         assign { } { }
36726         assign $1\dec31_dec_sub18_inv_a[0:0] 1'0
36727       attribute \src "libresoc.v:0.0-0.0"
36728       case 5'01001
36729         assign { } { }
36730         assign $1\dec31_dec_sub18_inv_a[0:0] 1'0
36731       attribute \src "libresoc.v:0.0-0.0"
36732       case 5'01000
36733         assign { } { }
36734         assign $1\dec31_dec_sub18_inv_a[0:0] 1'0
36735       case
36736         assign $1\dec31_dec_sub18_inv_a[0:0] 1'0
36737     end
36738     sync always
36739       update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0]
36740   end
36741   attribute \src "libresoc.v:25308.3-25329.6"
36742   process $proc$libresoc.v:25308$539
36743     assign { } { }
36744     assign { } { }
36745     assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0]
36746     attribute \src "libresoc.v:25309.5-25309.29"
36747     switch \initial
36748       attribute \src "libresoc.v:25309.9-25309.17"
36749       case 1'1
36750       case
36751     end
36752     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36753     switch \opcode_switch
36754       attribute \src "libresoc.v:0.0-0.0"
36755       case 5'00101
36756         assign { } { }
36757         assign $1\dec31_dec_sub18_inv_out[0:0] 1'0
36758       attribute \src "libresoc.v:0.0-0.0"
36759       case 5'00100
36760         assign { } { }
36761         assign $1\dec31_dec_sub18_inv_out[0:0] 1'0
36762       attribute \src "libresoc.v:0.0-0.0"
36763       case 5'01111
36764         assign { } { }
36765         assign $1\dec31_dec_sub18_inv_out[0:0] 1'0
36766       attribute \src "libresoc.v:0.0-0.0"
36767       case 5'01001
36768         assign { } { }
36769         assign $1\dec31_dec_sub18_inv_out[0:0] 1'0
36770       attribute \src "libresoc.v:0.0-0.0"
36771       case 5'01000
36772         assign { } { }
36773         assign $1\dec31_dec_sub18_inv_out[0:0] 1'0
36774       case
36775         assign $1\dec31_dec_sub18_inv_out[0:0] 1'0
36776     end
36777     sync always
36778       update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0]
36779   end
36780   attribute \src "libresoc.v:25330.3-25351.6"
36781   process $proc$libresoc.v:25330$540
36782     assign { } { }
36783     assign { } { }
36784     assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0]
36785     attribute \src "libresoc.v:25331.5-25331.29"
36786     switch \initial
36787       attribute \src "libresoc.v:25331.9-25331.17"
36788       case 1'1
36789       case
36790     end
36791     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36792     switch \opcode_switch
36793       attribute \src "libresoc.v:0.0-0.0"
36794       case 5'00101
36795         assign { } { }
36796         assign $1\dec31_dec_sub18_cry_out[0:0] 1'0
36797       attribute \src "libresoc.v:0.0-0.0"
36798       case 5'00100
36799         assign { } { }
36800         assign $1\dec31_dec_sub18_cry_out[0:0] 1'0
36801       attribute \src "libresoc.v:0.0-0.0"
36802       case 5'01111
36803         assign { } { }
36804         assign $1\dec31_dec_sub18_cry_out[0:0] 1'0
36805       attribute \src "libresoc.v:0.0-0.0"
36806       case 5'01001
36807         assign { } { }
36808         assign $1\dec31_dec_sub18_cry_out[0:0] 1'0
36809       attribute \src "libresoc.v:0.0-0.0"
36810       case 5'01000
36811         assign { } { }
36812         assign $1\dec31_dec_sub18_cry_out[0:0] 1'0
36813       case
36814         assign $1\dec31_dec_sub18_cry_out[0:0] 1'0
36815     end
36816     sync always
36817       update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0]
36818   end
36819   attribute \src "libresoc.v:25352.3-25373.6"
36820   process $proc$libresoc.v:25352$541
36821     assign { } { }
36822     assign { } { }
36823     assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0]
36824     attribute \src "libresoc.v:25353.5-25353.29"
36825     switch \initial
36826       attribute \src "libresoc.v:25353.9-25353.17"
36827       case 1'1
36828       case
36829     end
36830     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36831     switch \opcode_switch
36832       attribute \src "libresoc.v:0.0-0.0"
36833       case 5'00101
36834         assign { } { }
36835         assign $1\dec31_dec_sub18_br[0:0] 1'0
36836       attribute \src "libresoc.v:0.0-0.0"
36837       case 5'00100
36838         assign { } { }
36839         assign $1\dec31_dec_sub18_br[0:0] 1'0
36840       attribute \src "libresoc.v:0.0-0.0"
36841       case 5'01111
36842         assign { } { }
36843         assign $1\dec31_dec_sub18_br[0:0] 1'0
36844       attribute \src "libresoc.v:0.0-0.0"
36845       case 5'01001
36846         assign { } { }
36847         assign $1\dec31_dec_sub18_br[0:0] 1'0
36848       attribute \src "libresoc.v:0.0-0.0"
36849       case 5'01000
36850         assign { } { }
36851         assign $1\dec31_dec_sub18_br[0:0] 1'0
36852       case
36853         assign $1\dec31_dec_sub18_br[0:0] 1'0
36854     end
36855     sync always
36856       update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0]
36857   end
36858   attribute \src "libresoc.v:25374.3-25395.6"
36859   process $proc$libresoc.v:25374$542
36860     assign { } { }
36861     assign { } { }
36862     assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0]
36863     attribute \src "libresoc.v:25375.5-25375.29"
36864     switch \initial
36865       attribute \src "libresoc.v:25375.9-25375.17"
36866       case 1'1
36867       case
36868     end
36869     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36870     switch \opcode_switch
36871       attribute \src "libresoc.v:0.0-0.0"
36872       case 5'00101
36873         assign { } { }
36874         assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0
36875       attribute \src "libresoc.v:0.0-0.0"
36876       case 5'00100
36877         assign { } { }
36878         assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0
36879       attribute \src "libresoc.v:0.0-0.0"
36880       case 5'01111
36881         assign { } { }
36882         assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0
36883       attribute \src "libresoc.v:0.0-0.0"
36884       case 5'01001
36885         assign { } { }
36886         assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0
36887       attribute \src "libresoc.v:0.0-0.0"
36888       case 5'01000
36889         assign { } { }
36890         assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0
36891       case
36892         assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0
36893     end
36894     sync always
36895       update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0]
36896   end
36897   attribute \src "libresoc.v:25396.3-25417.6"
36898   process $proc$libresoc.v:25396$543
36899     assign { } { }
36900     assign { } { }
36901     assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0]
36902     attribute \src "libresoc.v:25397.5-25397.29"
36903     switch \initial
36904       attribute \src "libresoc.v:25397.9-25397.17"
36905       case 1'1
36906       case
36907     end
36908     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36909     switch \opcode_switch
36910       attribute \src "libresoc.v:0.0-0.0"
36911       case 5'00101
36912         assign { } { }
36913         assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000
36914       attribute \src "libresoc.v:0.0-0.0"
36915       case 5'00100
36916         assign { } { }
36917         assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010
36918       attribute \src "libresoc.v:0.0-0.0"
36919       case 5'01111
36920         assign { } { }
36921         assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011
36922       attribute \src "libresoc.v:0.0-0.0"
36923       case 5'01001
36924         assign { } { }
36925         assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011
36926       attribute \src "libresoc.v:0.0-0.0"
36927       case 5'01000
36928         assign { } { }
36929         assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011
36930       case
36931         assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000
36932     end
36933     sync always
36934       update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0]
36935   end
36936   attribute \src "libresoc.v:25418.3-25439.6"
36937   process $proc$libresoc.v:25418$544
36938     assign { } { }
36939     assign { } { }
36940     assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0]
36941     attribute \src "libresoc.v:25419.5-25419.29"
36942     switch \initial
36943       attribute \src "libresoc.v:25419.9-25419.17"
36944       case 1'1
36945       case
36946     end
36947     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36948     switch \opcode_switch
36949       attribute \src "libresoc.v:0.0-0.0"
36950       case 5'00101
36951         assign { } { }
36952         assign $1\dec31_dec_sub18_rsrv[0:0] 1'0
36953       attribute \src "libresoc.v:0.0-0.0"
36954       case 5'00100
36955         assign { } { }
36956         assign $1\dec31_dec_sub18_rsrv[0:0] 1'0
36957       attribute \src "libresoc.v:0.0-0.0"
36958       case 5'01111
36959         assign { } { }
36960         assign $1\dec31_dec_sub18_rsrv[0:0] 1'0
36961       attribute \src "libresoc.v:0.0-0.0"
36962       case 5'01001
36963         assign { } { }
36964         assign $1\dec31_dec_sub18_rsrv[0:0] 1'0
36965       attribute \src "libresoc.v:0.0-0.0"
36966       case 5'01000
36967         assign { } { }
36968         assign $1\dec31_dec_sub18_rsrv[0:0] 1'0
36969       case
36970         assign $1\dec31_dec_sub18_rsrv[0:0] 1'0
36971     end
36972     sync always
36973       update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0]
36974   end
36975   attribute \src "libresoc.v:25440.3-25461.6"
36976   process $proc$libresoc.v:25440$545
36977     assign { } { }
36978     assign { } { }
36979     assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0]
36980     attribute \src "libresoc.v:25441.5-25441.29"
36981     switch \initial
36982       attribute \src "libresoc.v:25441.9-25441.17"
36983       case 1'1
36984       case
36985     end
36986     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
36987     switch \opcode_switch
36988       attribute \src "libresoc.v:0.0-0.0"
36989       case 5'00101
36990         assign { } { }
36991         assign $1\dec31_dec_sub18_is_32b[0:0] 1'0
36992       attribute \src "libresoc.v:0.0-0.0"
36993       case 5'00100
36994         assign { } { }
36995         assign $1\dec31_dec_sub18_is_32b[0:0] 1'0
36996       attribute \src "libresoc.v:0.0-0.0"
36997       case 5'01111
36998         assign { } { }
36999         assign $1\dec31_dec_sub18_is_32b[0:0] 1'0
37000       attribute \src "libresoc.v:0.0-0.0"
37001       case 5'01001
37002         assign { } { }
37003         assign $1\dec31_dec_sub18_is_32b[0:0] 1'0
37004       attribute \src "libresoc.v:0.0-0.0"
37005       case 5'01000
37006         assign { } { }
37007         assign $1\dec31_dec_sub18_is_32b[0:0] 1'0
37008       case
37009         assign $1\dec31_dec_sub18_is_32b[0:0] 1'0
37010     end
37011     sync always
37012       update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0]
37013   end
37014   attribute \src "libresoc.v:25462.3-25483.6"
37015   process $proc$libresoc.v:25462$546
37016     assign { } { }
37017     assign { } { }
37018     assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0]
37019     attribute \src "libresoc.v:25463.5-25463.29"
37020     switch \initial
37021       attribute \src "libresoc.v:25463.9-25463.17"
37022       case 1'1
37023       case
37024     end
37025     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37026     switch \opcode_switch
37027       attribute \src "libresoc.v:0.0-0.0"
37028       case 5'00101
37029         assign { } { }
37030         assign $1\dec31_dec_sub18_sgn[0:0] 1'0
37031       attribute \src "libresoc.v:0.0-0.0"
37032       case 5'00100
37033         assign { } { }
37034         assign $1\dec31_dec_sub18_sgn[0:0] 1'0
37035       attribute \src "libresoc.v:0.0-0.0"
37036       case 5'01111
37037         assign { } { }
37038         assign $1\dec31_dec_sub18_sgn[0:0] 1'0
37039       attribute \src "libresoc.v:0.0-0.0"
37040       case 5'01001
37041         assign { } { }
37042         assign $1\dec31_dec_sub18_sgn[0:0] 1'0
37043       attribute \src "libresoc.v:0.0-0.0"
37044       case 5'01000
37045         assign { } { }
37046         assign $1\dec31_dec_sub18_sgn[0:0] 1'0
37047       case
37048         assign $1\dec31_dec_sub18_sgn[0:0] 1'0
37049     end
37050     sync always
37051       update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0]
37052   end
37053   attribute \src "libresoc.v:25484.3-25505.6"
37054   process $proc$libresoc.v:25484$547
37055     assign { } { }
37056     assign { } { }
37057     assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0]
37058     attribute \src "libresoc.v:25485.5-25485.29"
37059     switch \initial
37060       attribute \src "libresoc.v:25485.9-25485.17"
37061       case 1'1
37062       case
37063     end
37064     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37065     switch \opcode_switch
37066       attribute \src "libresoc.v:0.0-0.0"
37067       case 5'00101
37068         assign { } { }
37069         assign $1\dec31_dec_sub18_lk[0:0] 1'0
37070       attribute \src "libresoc.v:0.0-0.0"
37071       case 5'00100
37072         assign { } { }
37073         assign $1\dec31_dec_sub18_lk[0:0] 1'0
37074       attribute \src "libresoc.v:0.0-0.0"
37075       case 5'01111
37076         assign { } { }
37077         assign $1\dec31_dec_sub18_lk[0:0] 1'0
37078       attribute \src "libresoc.v:0.0-0.0"
37079       case 5'01001
37080         assign { } { }
37081         assign $1\dec31_dec_sub18_lk[0:0] 1'0
37082       attribute \src "libresoc.v:0.0-0.0"
37083       case 5'01000
37084         assign { } { }
37085         assign $1\dec31_dec_sub18_lk[0:0] 1'0
37086       case
37087         assign $1\dec31_dec_sub18_lk[0:0] 1'0
37088     end
37089     sync always
37090       update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0]
37091   end
37092   attribute \src "libresoc.v:25506.3-25527.6"
37093   process $proc$libresoc.v:25506$548
37094     assign { } { }
37095     assign { } { }
37096     assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0]
37097     attribute \src "libresoc.v:25507.5-25507.29"
37098     switch \initial
37099       attribute \src "libresoc.v:25507.9-25507.17"
37100       case 1'1
37101       case
37102     end
37103     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37104     switch \opcode_switch
37105       attribute \src "libresoc.v:0.0-0.0"
37106       case 5'00101
37107         assign { } { }
37108         assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1
37109       attribute \src "libresoc.v:0.0-0.0"
37110       case 5'00100
37111         assign { } { }
37112         assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1
37113       attribute \src "libresoc.v:0.0-0.0"
37114       case 5'01111
37115         assign { } { }
37116         assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0
37117       attribute \src "libresoc.v:0.0-0.0"
37118       case 5'01001
37119         assign { } { }
37120         assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0
37121       attribute \src "libresoc.v:0.0-0.0"
37122       case 5'01000
37123         assign { } { }
37124         assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0
37125       case
37126         assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0
37127     end
37128     sync always
37129       update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0]
37130   end
37131   attribute \src "libresoc.v:25528.3-25549.6"
37132   process $proc$libresoc.v:25528$549
37133     assign { } { }
37134     assign { } { }
37135     assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0]
37136     attribute \src "libresoc.v:25529.5-25529.29"
37137     switch \initial
37138       attribute \src "libresoc.v:25529.9-25529.17"
37139       case 1'1
37140       case
37141     end
37142     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37143     switch \opcode_switch
37144       attribute \src "libresoc.v:0.0-0.0"
37145       case 5'00101
37146         assign { } { }
37147         assign $1\dec31_dec_sub18_form[4:0] 5'01000
37148       attribute \src "libresoc.v:0.0-0.0"
37149       case 5'00100
37150         assign { } { }
37151         assign $1\dec31_dec_sub18_form[4:0] 5'01000
37152       attribute \src "libresoc.v:0.0-0.0"
37153       case 5'01111
37154         assign { } { }
37155         assign $1\dec31_dec_sub18_form[4:0] 5'01000
37156       attribute \src "libresoc.v:0.0-0.0"
37157       case 5'01001
37158         assign { } { }
37159         assign $1\dec31_dec_sub18_form[4:0] 5'01000
37160       attribute \src "libresoc.v:0.0-0.0"
37161       case 5'01000
37162         assign { } { }
37163         assign $1\dec31_dec_sub18_form[4:0] 5'01000
37164       case
37165         assign $1\dec31_dec_sub18_form[4:0] 5'00000
37166     end
37167     sync always
37168       update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0]
37169   end
37170   attribute \src "libresoc.v:25550.3-25571.6"
37171   process $proc$libresoc.v:25550$550
37172     assign { } { }
37173     assign { } { }
37174     assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0]
37175     attribute \src "libresoc.v:25551.5-25551.29"
37176     switch \initial
37177       attribute \src "libresoc.v:25551.9-25551.17"
37178       case 1'1
37179       case
37180     end
37181     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37182     switch \opcode_switch
37183       attribute \src "libresoc.v:0.0-0.0"
37184       case 5'00101
37185         assign { } { }
37186         assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100
37187       attribute \src "libresoc.v:0.0-0.0"
37188       case 5'00100
37189         assign { } { }
37190         assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100
37191       attribute \src "libresoc.v:0.0-0.0"
37192       case 5'01111
37193         assign { } { }
37194         assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000
37195       attribute \src "libresoc.v:0.0-0.0"
37196       case 5'01001
37197         assign { } { }
37198         assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000
37199       attribute \src "libresoc.v:0.0-0.0"
37200       case 5'01000
37201         assign { } { }
37202         assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000
37203       case
37204         assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000
37205     end
37206     sync always
37207       update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0]
37208   end
37209   attribute \src "libresoc.v:25572.3-25593.6"
37210   process $proc$libresoc.v:25572$551
37211     assign { } { }
37212     assign { } { }
37213     assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0]
37214     attribute \src "libresoc.v:25573.5-25573.29"
37215     switch \initial
37216       attribute \src "libresoc.v:25573.9-25573.17"
37217       case 1'1
37218       case
37219     end
37220     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37221     switch \opcode_switch
37222       attribute \src "libresoc.v:0.0-0.0"
37223       case 5'00101
37224         assign { } { }
37225         assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000
37226       attribute \src "libresoc.v:0.0-0.0"
37227       case 5'00100
37228         assign { } { }
37229         assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000
37230       attribute \src "libresoc.v:0.0-0.0"
37231       case 5'01111
37232         assign { } { }
37233         assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000
37234       attribute \src "libresoc.v:0.0-0.0"
37235       case 5'01001
37236         assign { } { }
37237         assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001
37238       attribute \src "libresoc.v:0.0-0.0"
37239       case 5'01000
37240         assign { } { }
37241         assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001
37242       case
37243         assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000
37244     end
37245     sync always
37246       update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0]
37247   end
37248   attribute \src "libresoc.v:25594.3-25615.6"
37249   process $proc$libresoc.v:25594$552
37250     assign { } { }
37251     assign { } { }
37252     assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0]
37253     attribute \src "libresoc.v:25595.5-25595.29"
37254     switch \initial
37255       attribute \src "libresoc.v:25595.9-25595.17"
37256       case 1'1
37257       case
37258     end
37259     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37260     switch \opcode_switch
37261       attribute \src "libresoc.v:0.0-0.0"
37262       case 5'00101
37263         assign { } { }
37264         assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00
37265       attribute \src "libresoc.v:0.0-0.0"
37266       case 5'00100
37267         assign { } { }
37268         assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00
37269       attribute \src "libresoc.v:0.0-0.0"
37270       case 5'01111
37271         assign { } { }
37272         assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00
37273       attribute \src "libresoc.v:0.0-0.0"
37274       case 5'01001
37275         assign { } { }
37276         assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00
37277       attribute \src "libresoc.v:0.0-0.0"
37278       case 5'01000
37279         assign { } { }
37280         assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00
37281       case
37282         assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00
37283     end
37284     sync always
37285       update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0]
37286   end
37287   attribute \src "libresoc.v:25616.3-25637.6"
37288   process $proc$libresoc.v:25616$553
37289     assign { } { }
37290     assign { } { }
37291     assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0]
37292     attribute \src "libresoc.v:25617.5-25617.29"
37293     switch \initial
37294       attribute \src "libresoc.v:25617.9-25617.17"
37295       case 1'1
37296       case
37297     end
37298     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37299     switch \opcode_switch
37300       attribute \src "libresoc.v:0.0-0.0"
37301       case 5'00101
37302         assign { } { }
37303         assign $1\dec31_dec_sub18_out_sel[1:0] 2'00
37304       attribute \src "libresoc.v:0.0-0.0"
37305       case 5'00100
37306         assign { } { }
37307         assign $1\dec31_dec_sub18_out_sel[1:0] 2'00
37308       attribute \src "libresoc.v:0.0-0.0"
37309       case 5'01111
37310         assign { } { }
37311         assign $1\dec31_dec_sub18_out_sel[1:0] 2'00
37312       attribute \src "libresoc.v:0.0-0.0"
37313       case 5'01001
37314         assign { } { }
37315         assign $1\dec31_dec_sub18_out_sel[1:0] 2'00
37316       attribute \src "libresoc.v:0.0-0.0"
37317       case 5'01000
37318         assign { } { }
37319         assign $1\dec31_dec_sub18_out_sel[1:0] 2'00
37320       case
37321         assign $1\dec31_dec_sub18_out_sel[1:0] 2'00
37322     end
37323     sync always
37324       update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0]
37325   end
37326   attribute \src "libresoc.v:25638.3-25659.6"
37327   process $proc$libresoc.v:25638$554
37328     assign { } { }
37329     assign { } { }
37330     assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0]
37331     attribute \src "libresoc.v:25639.5-25639.29"
37332     switch \initial
37333       attribute \src "libresoc.v:25639.9-25639.17"
37334       case 1'1
37335       case
37336     end
37337     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37338     switch \opcode_switch
37339       attribute \src "libresoc.v:0.0-0.0"
37340       case 5'00101
37341         assign { } { }
37342         assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
37343       attribute \src "libresoc.v:0.0-0.0"
37344       case 5'00100
37345         assign { } { }
37346         assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
37347       attribute \src "libresoc.v:0.0-0.0"
37348       case 5'01111
37349         assign { } { }
37350         assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
37351       attribute \src "libresoc.v:0.0-0.0"
37352       case 5'01001
37353         assign { } { }
37354         assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
37355       attribute \src "libresoc.v:0.0-0.0"
37356       case 5'01000
37357         assign { } { }
37358         assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
37359       case
37360         assign $1\dec31_dec_sub18_cr_in[2:0] 3'000
37361     end
37362     sync always
37363       update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0]
37364   end
37365   attribute \src "libresoc.v:25660.3-25681.6"
37366   process $proc$libresoc.v:25660$555
37367     assign { } { }
37368     assign { } { }
37369     assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0]
37370     attribute \src "libresoc.v:25661.5-25661.29"
37371     switch \initial
37372       attribute \src "libresoc.v:25661.9-25661.17"
37373       case 1'1
37374       case
37375     end
37376     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37377     switch \opcode_switch
37378       attribute \src "libresoc.v:0.0-0.0"
37379       case 5'00101
37380         assign { } { }
37381         assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
37382       attribute \src "libresoc.v:0.0-0.0"
37383       case 5'00100
37384         assign { } { }
37385         assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
37386       attribute \src "libresoc.v:0.0-0.0"
37387       case 5'01111
37388         assign { } { }
37389         assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
37390       attribute \src "libresoc.v:0.0-0.0"
37391       case 5'01001
37392         assign { } { }
37393         assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
37394       attribute \src "libresoc.v:0.0-0.0"
37395       case 5'01000
37396         assign { } { }
37397         assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
37398       case
37399         assign $1\dec31_dec_sub18_cr_out[2:0] 3'000
37400     end
37401     sync always
37402       update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0]
37403   end
37404   connect \opcode_switch \opcode_in [10:6]
37405 end
37406 attribute \src "libresoc.v:25687.1-26402.10"
37407 attribute \cells_not_processed 1
37408 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19"
37409 attribute \generator "nMigen"
37410 module \dec31_dec_sub19
37411   attribute \src "libresoc.v:26040.3-26058.6"
37412   wire width 8 $0\dec31_dec_sub19_asmcode[7:0]
37413   attribute \src "libresoc.v:26116.3-26134.6"
37414   wire $0\dec31_dec_sub19_br[0:0]
37415   attribute \src "libresoc.v:26363.3-26381.6"
37416   wire width 3 $0\dec31_dec_sub19_cr_in[2:0]
37417   attribute \src "libresoc.v:26382.3-26400.6"
37418   wire width 3 $0\dec31_dec_sub19_cr_out[2:0]
37419   attribute \src "libresoc.v:26021.3-26039.6"
37420   wire width 2 $0\dec31_dec_sub19_cry_in[1:0]
37421   attribute \src "libresoc.v:26097.3-26115.6"
37422   wire $0\dec31_dec_sub19_cry_out[0:0]
37423   attribute \src "libresoc.v:26268.3-26286.6"
37424   wire width 5 $0\dec31_dec_sub19_form[4:0]
37425   attribute \src "libresoc.v:25945.3-25963.6"
37426   wire width 12 $0\dec31_dec_sub19_function_unit[11:0]
37427   attribute \src "libresoc.v:26287.3-26305.6"
37428   wire width 3 $0\dec31_dec_sub19_in1_sel[2:0]
37429   attribute \src "libresoc.v:26306.3-26324.6"
37430   wire width 4 $0\dec31_dec_sub19_in2_sel[3:0]
37431   attribute \src "libresoc.v:26325.3-26343.6"
37432   wire width 2 $0\dec31_dec_sub19_in3_sel[1:0]
37433   attribute \src "libresoc.v:26154.3-26172.6"
37434   wire width 7 $0\dec31_dec_sub19_internal_op[6:0]
37435   attribute \src "libresoc.v:26059.3-26077.6"
37436   wire $0\dec31_dec_sub19_inv_a[0:0]
37437   attribute \src "libresoc.v:26078.3-26096.6"
37438   wire $0\dec31_dec_sub19_inv_out[0:0]
37439   attribute \src "libresoc.v:26192.3-26210.6"
37440   wire $0\dec31_dec_sub19_is_32b[0:0]
37441   attribute \src "libresoc.v:25964.3-25982.6"
37442   wire width 4 $0\dec31_dec_sub19_ldst_len[3:0]
37443   attribute \src "libresoc.v:26230.3-26248.6"
37444   wire $0\dec31_dec_sub19_lk[0:0]
37445   attribute \src "libresoc.v:26344.3-26362.6"
37446   wire width 2 $0\dec31_dec_sub19_out_sel[1:0]
37447   attribute \src "libresoc.v:26002.3-26020.6"
37448   wire width 2 $0\dec31_dec_sub19_rc_sel[1:0]
37449   attribute \src "libresoc.v:26173.3-26191.6"
37450   wire $0\dec31_dec_sub19_rsrv[0:0]
37451   attribute \src "libresoc.v:26249.3-26267.6"
37452   wire $0\dec31_dec_sub19_sgl_pipe[0:0]
37453   attribute \src "libresoc.v:26211.3-26229.6"
37454   wire $0\dec31_dec_sub19_sgn[0:0]
37455   attribute \src "libresoc.v:26135.3-26153.6"
37456   wire $0\dec31_dec_sub19_sgn_ext[0:0]
37457   attribute \src "libresoc.v:25983.3-26001.6"
37458   wire width 2 $0\dec31_dec_sub19_upd[1:0]
37459   attribute \src "libresoc.v:25688.7-25688.20"
37460   wire $0\initial[0:0]
37461   attribute \src "libresoc.v:26040.3-26058.6"
37462   wire width 8 $1\dec31_dec_sub19_asmcode[7:0]
37463   attribute \src "libresoc.v:26116.3-26134.6"
37464   wire $1\dec31_dec_sub19_br[0:0]
37465   attribute \src "libresoc.v:26363.3-26381.6"
37466   wire width 3 $1\dec31_dec_sub19_cr_in[2:0]
37467   attribute \src "libresoc.v:26382.3-26400.6"
37468   wire width 3 $1\dec31_dec_sub19_cr_out[2:0]
37469   attribute \src "libresoc.v:26021.3-26039.6"
37470   wire width 2 $1\dec31_dec_sub19_cry_in[1:0]
37471   attribute \src "libresoc.v:26097.3-26115.6"
37472   wire $1\dec31_dec_sub19_cry_out[0:0]
37473   attribute \src "libresoc.v:26268.3-26286.6"
37474   wire width 5 $1\dec31_dec_sub19_form[4:0]
37475   attribute \src "libresoc.v:25945.3-25963.6"
37476   wire width 12 $1\dec31_dec_sub19_function_unit[11:0]
37477   attribute \src "libresoc.v:26287.3-26305.6"
37478   wire width 3 $1\dec31_dec_sub19_in1_sel[2:0]
37479   attribute \src "libresoc.v:26306.3-26324.6"
37480   wire width 4 $1\dec31_dec_sub19_in2_sel[3:0]
37481   attribute \src "libresoc.v:26325.3-26343.6"
37482   wire width 2 $1\dec31_dec_sub19_in3_sel[1:0]
37483   attribute \src "libresoc.v:26154.3-26172.6"
37484   wire width 7 $1\dec31_dec_sub19_internal_op[6:0]
37485   attribute \src "libresoc.v:26059.3-26077.6"
37486   wire $1\dec31_dec_sub19_inv_a[0:0]
37487   attribute \src "libresoc.v:26078.3-26096.6"
37488   wire $1\dec31_dec_sub19_inv_out[0:0]
37489   attribute \src "libresoc.v:26192.3-26210.6"
37490   wire $1\dec31_dec_sub19_is_32b[0:0]
37491   attribute \src "libresoc.v:25964.3-25982.6"
37492   wire width 4 $1\dec31_dec_sub19_ldst_len[3:0]
37493   attribute \src "libresoc.v:26230.3-26248.6"
37494   wire $1\dec31_dec_sub19_lk[0:0]
37495   attribute \src "libresoc.v:26344.3-26362.6"
37496   wire width 2 $1\dec31_dec_sub19_out_sel[1:0]
37497   attribute \src "libresoc.v:26002.3-26020.6"
37498   wire width 2 $1\dec31_dec_sub19_rc_sel[1:0]
37499   attribute \src "libresoc.v:26173.3-26191.6"
37500   wire $1\dec31_dec_sub19_rsrv[0:0]
37501   attribute \src "libresoc.v:26249.3-26267.6"
37502   wire $1\dec31_dec_sub19_sgl_pipe[0:0]
37503   attribute \src "libresoc.v:26211.3-26229.6"
37504   wire $1\dec31_dec_sub19_sgn[0:0]
37505   attribute \src "libresoc.v:26135.3-26153.6"
37506   wire $1\dec31_dec_sub19_sgn_ext[0:0]
37507   attribute \src "libresoc.v:25983.3-26001.6"
37508   wire width 2 $1\dec31_dec_sub19_upd[1:0]
37509   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37510   wire width 8 output 4 \dec31_dec_sub19_asmcode
37511   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37512   wire output 18 \dec31_dec_sub19_br
37513   attribute \enum_base_type "CRInSel"
37514   attribute \enum_value_000 "NONE"
37515   attribute \enum_value_001 "CR0"
37516   attribute \enum_value_010 "BI"
37517   attribute \enum_value_011 "BFA"
37518   attribute \enum_value_100 "BA_BB"
37519   attribute \enum_value_101 "BC"
37520   attribute \enum_value_110 "WHOLE_REG"
37521   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37522   wire width 3 output 9 \dec31_dec_sub19_cr_in
37523   attribute \enum_base_type "CROutSel"
37524   attribute \enum_value_000 "NONE"
37525   attribute \enum_value_001 "CR0"
37526   attribute \enum_value_010 "BF"
37527   attribute \enum_value_011 "BT"
37528   attribute \enum_value_100 "WHOLE_REG"
37529   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37530   wire width 3 output 10 \dec31_dec_sub19_cr_out
37531   attribute \enum_base_type "CryIn"
37532   attribute \enum_value_00 "ZERO"
37533   attribute \enum_value_01 "ONE"
37534   attribute \enum_value_10 "CA"
37535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37536   wire width 2 output 14 \dec31_dec_sub19_cry_in
37537   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37538   wire output 17 \dec31_dec_sub19_cry_out
37539   attribute \enum_base_type "Form"
37540   attribute \enum_value_00000 "NONE"
37541   attribute \enum_value_00001 "I"
37542   attribute \enum_value_00010 "B"
37543   attribute \enum_value_00011 "SC"
37544   attribute \enum_value_00100 "D"
37545   attribute \enum_value_00101 "DS"
37546   attribute \enum_value_00110 "DQ"
37547   attribute \enum_value_00111 "DX"
37548   attribute \enum_value_01000 "X"
37549   attribute \enum_value_01001 "XL"
37550   attribute \enum_value_01010 "XFX"
37551   attribute \enum_value_01011 "XFL"
37552   attribute \enum_value_01100 "XX1"
37553   attribute \enum_value_01101 "XX2"
37554   attribute \enum_value_01110 "XX3"
37555   attribute \enum_value_01111 "XX4"
37556   attribute \enum_value_10000 "XS"
37557   attribute \enum_value_10001 "XO"
37558   attribute \enum_value_10010 "A"
37559   attribute \enum_value_10011 "M"
37560   attribute \enum_value_10100 "MD"
37561   attribute \enum_value_10101 "MDS"
37562   attribute \enum_value_10110 "VA"
37563   attribute \enum_value_10111 "VC"
37564   attribute \enum_value_11000 "VX"
37565   attribute \enum_value_11001 "EVX"
37566   attribute \enum_value_11010 "EVS"
37567   attribute \enum_value_11011 "Z22"
37568   attribute \enum_value_11100 "Z23"
37569   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37570   wire width 5 output 3 \dec31_dec_sub19_form
37571   attribute \enum_base_type "Function"
37572   attribute \enum_value_000000000000 "NONE"
37573   attribute \enum_value_000000000010 "ALU"
37574   attribute \enum_value_000000000100 "LDST"
37575   attribute \enum_value_000000001000 "SHIFT_ROT"
37576   attribute \enum_value_000000010000 "LOGICAL"
37577   attribute \enum_value_000000100000 "BRANCH"
37578   attribute \enum_value_000001000000 "CR"
37579   attribute \enum_value_000010000000 "TRAP"
37580   attribute \enum_value_000100000000 "MUL"
37581   attribute \enum_value_001000000000 "DIV"
37582   attribute \enum_value_010000000000 "SPR"
37583   attribute \enum_value_100000000000 "MMU"
37584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37585   wire width 12 output 1 \dec31_dec_sub19_function_unit
37586   attribute \enum_base_type "In1Sel"
37587   attribute \enum_value_000 "NONE"
37588   attribute \enum_value_001 "RA"
37589   attribute \enum_value_010 "RA_OR_ZERO"
37590   attribute \enum_value_011 "SPR"
37591   attribute \enum_value_100 "RS"
37592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37593   wire width 3 output 5 \dec31_dec_sub19_in1_sel
37594   attribute \enum_base_type "In2Sel"
37595   attribute \enum_value_0000 "NONE"
37596   attribute \enum_value_0001 "RB"
37597   attribute \enum_value_0010 "CONST_UI"
37598   attribute \enum_value_0011 "CONST_SI"
37599   attribute \enum_value_0100 "CONST_UI_HI"
37600   attribute \enum_value_0101 "CONST_SI_HI"
37601   attribute \enum_value_0110 "CONST_LI"
37602   attribute \enum_value_0111 "CONST_BD"
37603   attribute \enum_value_1000 "CONST_DS"
37604   attribute \enum_value_1001 "CONST_M1"
37605   attribute \enum_value_1010 "CONST_SH"
37606   attribute \enum_value_1011 "CONST_SH32"
37607   attribute \enum_value_1100 "SPR"
37608   attribute \enum_value_1101 "RS"
37609   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37610   wire width 4 output 6 \dec31_dec_sub19_in2_sel
37611   attribute \enum_base_type "In3Sel"
37612   attribute \enum_value_00 "NONE"
37613   attribute \enum_value_01 "RS"
37614   attribute \enum_value_10 "RB"
37615   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37616   wire width 2 output 7 \dec31_dec_sub19_in3_sel
37617   attribute \enum_base_type "MicrOp"
37618   attribute \enum_value_0000000 "OP_ILLEGAL"
37619   attribute \enum_value_0000001 "OP_NOP"
37620   attribute \enum_value_0000010 "OP_ADD"
37621   attribute \enum_value_0000011 "OP_ADDPCIS"
37622   attribute \enum_value_0000100 "OP_AND"
37623   attribute \enum_value_0000101 "OP_ATTN"
37624   attribute \enum_value_0000110 "OP_B"
37625   attribute \enum_value_0000111 "OP_BC"
37626   attribute \enum_value_0001000 "OP_BCREG"
37627   attribute \enum_value_0001001 "OP_BPERM"
37628   attribute \enum_value_0001010 "OP_CMP"
37629   attribute \enum_value_0001011 "OP_CMPB"
37630   attribute \enum_value_0001100 "OP_CMPEQB"
37631   attribute \enum_value_0001101 "OP_CMPRB"
37632   attribute \enum_value_0001110 "OP_CNTZ"
37633   attribute \enum_value_0001111 "OP_CRAND"
37634   attribute \enum_value_0010000 "OP_CRANDC"
37635   attribute \enum_value_0010001 "OP_CREQV"
37636   attribute \enum_value_0010010 "OP_CRNAND"
37637   attribute \enum_value_0010011 "OP_CRNOR"
37638   attribute \enum_value_0010100 "OP_CROR"
37639   attribute \enum_value_0010101 "OP_CRORC"
37640   attribute \enum_value_0010110 "OP_CRXOR"
37641   attribute \enum_value_0010111 "OP_DARN"
37642   attribute \enum_value_0011000 "OP_DCBF"
37643   attribute \enum_value_0011001 "OP_DCBST"
37644   attribute \enum_value_0011010 "OP_DCBT"
37645   attribute \enum_value_0011011 "OP_DCBTST"
37646   attribute \enum_value_0011100 "OP_DCBZ"
37647   attribute \enum_value_0011101 "OP_DIV"
37648   attribute \enum_value_0011110 "OP_DIVE"
37649   attribute \enum_value_0011111 "OP_EXTS"
37650   attribute \enum_value_0100000 "OP_EXTSWSLI"
37651   attribute \enum_value_0100001 "OP_ICBI"
37652   attribute \enum_value_0100010 "OP_ICBT"
37653   attribute \enum_value_0100011 "OP_ISEL"
37654   attribute \enum_value_0100100 "OP_ISYNC"
37655   attribute \enum_value_0100101 "OP_LOAD"
37656   attribute \enum_value_0100110 "OP_STORE"
37657   attribute \enum_value_0100111 "OP_MADDHD"
37658   attribute \enum_value_0101000 "OP_MADDHDU"
37659   attribute \enum_value_0101001 "OP_MADDLD"
37660   attribute \enum_value_0101010 "OP_MCRF"
37661   attribute \enum_value_0101011 "OP_MCRXR"
37662   attribute \enum_value_0101100 "OP_MCRXRX"
37663   attribute \enum_value_0101101 "OP_MFCR"
37664   attribute \enum_value_0101110 "OP_MFSPR"
37665   attribute \enum_value_0101111 "OP_MOD"
37666   attribute \enum_value_0110000 "OP_MTCRF"
37667   attribute \enum_value_0110001 "OP_MTSPR"
37668   attribute \enum_value_0110010 "OP_MUL_L64"
37669   attribute \enum_value_0110011 "OP_MUL_H64"
37670   attribute \enum_value_0110100 "OP_MUL_H32"
37671   attribute \enum_value_0110101 "OP_OR"
37672   attribute \enum_value_0110110 "OP_POPCNT"
37673   attribute \enum_value_0110111 "OP_PRTY"
37674   attribute \enum_value_0111000 "OP_RLC"
37675   attribute \enum_value_0111001 "OP_RLCL"
37676   attribute \enum_value_0111010 "OP_RLCR"
37677   attribute \enum_value_0111011 "OP_SETB"
37678   attribute \enum_value_0111100 "OP_SHL"
37679   attribute \enum_value_0111101 "OP_SHR"
37680   attribute \enum_value_0111110 "OP_SYNC"
37681   attribute \enum_value_0111111 "OP_TRAP"
37682   attribute \enum_value_1000011 "OP_XOR"
37683   attribute \enum_value_1000100 "OP_SIM_CONFIG"
37684   attribute \enum_value_1000101 "OP_CROP"
37685   attribute \enum_value_1000110 "OP_RFID"
37686   attribute \enum_value_1000111 "OP_MFMSR"
37687   attribute \enum_value_1001000 "OP_MTMSRD"
37688   attribute \enum_value_1001001 "OP_SC"
37689   attribute \enum_value_1001010 "OP_MTMSR"
37690   attribute \enum_value_1001011 "OP_TLBIE"
37691   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37692   wire width 7 output 2 \dec31_dec_sub19_internal_op
37693   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37694   wire output 15 \dec31_dec_sub19_inv_a
37695   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37696   wire output 16 \dec31_dec_sub19_inv_out
37697   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37698   wire output 21 \dec31_dec_sub19_is_32b
37699   attribute \enum_base_type "LdstLen"
37700   attribute \enum_value_0000 "NONE"
37701   attribute \enum_value_0001 "is1B"
37702   attribute \enum_value_0010 "is2B"
37703   attribute \enum_value_0100 "is4B"
37704   attribute \enum_value_1000 "is8B"
37705   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37706   wire width 4 output 11 \dec31_dec_sub19_ldst_len
37707   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37708   wire output 23 \dec31_dec_sub19_lk
37709   attribute \enum_base_type "OutSel"
37710   attribute \enum_value_00 "NONE"
37711   attribute \enum_value_01 "RT"
37712   attribute \enum_value_10 "RA"
37713   attribute \enum_value_11 "SPR"
37714   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37715   wire width 2 output 8 \dec31_dec_sub19_out_sel
37716   attribute \enum_base_type "RC"
37717   attribute \enum_value_00 "NONE"
37718   attribute \enum_value_01 "ONE"
37719   attribute \enum_value_10 "RC"
37720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37721   wire width 2 output 13 \dec31_dec_sub19_rc_sel
37722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37723   wire output 20 \dec31_dec_sub19_rsrv
37724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37725   wire output 24 \dec31_dec_sub19_sgl_pipe
37726   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37727   wire output 22 \dec31_dec_sub19_sgn
37728   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
37729   wire output 19 \dec31_dec_sub19_sgn_ext
37730   attribute \enum_base_type "LDSTMode"
37731   attribute \enum_value_00 "NONE"
37732   attribute \enum_value_01 "update"
37733   attribute \enum_value_10 "cix"
37734   attribute \enum_value_11 "cx"
37735   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
37736   wire width 2 output 12 \dec31_dec_sub19_upd
37737   attribute \src "libresoc.v:25688.7-25688.15"
37738   wire \initial
37739   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
37740   wire width 32 input 25 \opcode_in
37741   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
37742   wire width 5 \opcode_switch
37743   attribute \src "libresoc.v:25688.7-25688.20"
37744   process $proc$libresoc.v:25688$581
37745     assign { } { }
37746     assign $0\initial[0:0] 1'0
37747     sync always
37748       update \initial $0\initial[0:0]
37749     sync init
37750   end
37751   attribute \src "libresoc.v:25945.3-25963.6"
37752   process $proc$libresoc.v:25945$557
37753     assign { } { }
37754     assign { } { }
37755     assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0]
37756     attribute \src "libresoc.v:25946.5-25946.29"
37757     switch \initial
37758       attribute \src "libresoc.v:25946.9-25946.17"
37759       case 1'1
37760       case
37761     end
37762     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37763     switch \opcode_switch
37764       attribute \src "libresoc.v:0.0-0.0"
37765       case 5'00000
37766         assign { } { }
37767         assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000
37768       attribute \src "libresoc.v:0.0-0.0"
37769       case 5'00010
37770         assign { } { }
37771         assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000
37772       attribute \src "libresoc.v:0.0-0.0"
37773       case 5'01010
37774         assign { } { }
37775         assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000
37776       attribute \src "libresoc.v:0.0-0.0"
37777       case 5'01110
37778         assign { } { }
37779         assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000
37780       case
37781         assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000
37782     end
37783     sync always
37784       update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0]
37785   end
37786   attribute \src "libresoc.v:25964.3-25982.6"
37787   process $proc$libresoc.v:25964$558
37788     assign { } { }
37789     assign { } { }
37790     assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0]
37791     attribute \src "libresoc.v:25965.5-25965.29"
37792     switch \initial
37793       attribute \src "libresoc.v:25965.9-25965.17"
37794       case 1'1
37795       case
37796     end
37797     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37798     switch \opcode_switch
37799       attribute \src "libresoc.v:0.0-0.0"
37800       case 5'00000
37801         assign { } { }
37802         assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
37803       attribute \src "libresoc.v:0.0-0.0"
37804       case 5'00010
37805         assign { } { }
37806         assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
37807       attribute \src "libresoc.v:0.0-0.0"
37808       case 5'01010
37809         assign { } { }
37810         assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
37811       attribute \src "libresoc.v:0.0-0.0"
37812       case 5'01110
37813         assign { } { }
37814         assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
37815       case
37816         assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000
37817     end
37818     sync always
37819       update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0]
37820   end
37821   attribute \src "libresoc.v:25983.3-26001.6"
37822   process $proc$libresoc.v:25983$559
37823     assign { } { }
37824     assign { } { }
37825     assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0]
37826     attribute \src "libresoc.v:25984.5-25984.29"
37827     switch \initial
37828       attribute \src "libresoc.v:25984.9-25984.17"
37829       case 1'1
37830       case
37831     end
37832     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37833     switch \opcode_switch
37834       attribute \src "libresoc.v:0.0-0.0"
37835       case 5'00000
37836         assign { } { }
37837         assign $1\dec31_dec_sub19_upd[1:0] 2'00
37838       attribute \src "libresoc.v:0.0-0.0"
37839       case 5'00010
37840         assign { } { }
37841         assign $1\dec31_dec_sub19_upd[1:0] 2'00
37842       attribute \src "libresoc.v:0.0-0.0"
37843       case 5'01010
37844         assign { } { }
37845         assign $1\dec31_dec_sub19_upd[1:0] 2'00
37846       attribute \src "libresoc.v:0.0-0.0"
37847       case 5'01110
37848         assign { } { }
37849         assign $1\dec31_dec_sub19_upd[1:0] 2'00
37850       case
37851         assign $1\dec31_dec_sub19_upd[1:0] 2'00
37852     end
37853     sync always
37854       update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0]
37855   end
37856   attribute \src "libresoc.v:26002.3-26020.6"
37857   process $proc$libresoc.v:26002$560
37858     assign { } { }
37859     assign { } { }
37860     assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0]
37861     attribute \src "libresoc.v:26003.5-26003.29"
37862     switch \initial
37863       attribute \src "libresoc.v:26003.9-26003.17"
37864       case 1'1
37865       case
37866     end
37867     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37868     switch \opcode_switch
37869       attribute \src "libresoc.v:0.0-0.0"
37870       case 5'00000
37871         assign { } { }
37872         assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
37873       attribute \src "libresoc.v:0.0-0.0"
37874       case 5'00010
37875         assign { } { }
37876         assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
37877       attribute \src "libresoc.v:0.0-0.0"
37878       case 5'01010
37879         assign { } { }
37880         assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
37881       attribute \src "libresoc.v:0.0-0.0"
37882       case 5'01110
37883         assign { } { }
37884         assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
37885       case
37886         assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00
37887     end
37888     sync always
37889       update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0]
37890   end
37891   attribute \src "libresoc.v:26021.3-26039.6"
37892   process $proc$libresoc.v:26021$561
37893     assign { } { }
37894     assign { } { }
37895     assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0]
37896     attribute \src "libresoc.v:26022.5-26022.29"
37897     switch \initial
37898       attribute \src "libresoc.v:26022.9-26022.17"
37899       case 1'1
37900       case
37901     end
37902     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37903     switch \opcode_switch
37904       attribute \src "libresoc.v:0.0-0.0"
37905       case 5'00000
37906         assign { } { }
37907         assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
37908       attribute \src "libresoc.v:0.0-0.0"
37909       case 5'00010
37910         assign { } { }
37911         assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
37912       attribute \src "libresoc.v:0.0-0.0"
37913       case 5'01010
37914         assign { } { }
37915         assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
37916       attribute \src "libresoc.v:0.0-0.0"
37917       case 5'01110
37918         assign { } { }
37919         assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
37920       case
37921         assign $1\dec31_dec_sub19_cry_in[1:0] 2'00
37922     end
37923     sync always
37924       update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0]
37925   end
37926   attribute \src "libresoc.v:26040.3-26058.6"
37927   process $proc$libresoc.v:26040$562
37928     assign { } { }
37929     assign { } { }
37930     assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0]
37931     attribute \src "libresoc.v:26041.5-26041.29"
37932     switch \initial
37933       attribute \src "libresoc.v:26041.9-26041.17"
37934       case 1'1
37935       case
37936     end
37937     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37938     switch \opcode_switch
37939       attribute \src "libresoc.v:0.0-0.0"
37940       case 5'00000
37941         assign { } { }
37942         assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111
37943       attribute \src "libresoc.v:0.0-0.0"
37944       case 5'00010
37945         assign { } { }
37946         assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000
37947       attribute \src "libresoc.v:0.0-0.0"
37948       case 5'01010
37949         assign { } { }
37950         assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001
37951       attribute \src "libresoc.v:0.0-0.0"
37952       case 5'01110
37953         assign { } { }
37954         assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001
37955       case
37956         assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000
37957     end
37958     sync always
37959       update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0]
37960   end
37961   attribute \src "libresoc.v:26059.3-26077.6"
37962   process $proc$libresoc.v:26059$563
37963     assign { } { }
37964     assign { } { }
37965     assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0]
37966     attribute \src "libresoc.v:26060.5-26060.29"
37967     switch \initial
37968       attribute \src "libresoc.v:26060.9-26060.17"
37969       case 1'1
37970       case
37971     end
37972     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
37973     switch \opcode_switch
37974       attribute \src "libresoc.v:0.0-0.0"
37975       case 5'00000
37976         assign { } { }
37977         assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
37978       attribute \src "libresoc.v:0.0-0.0"
37979       case 5'00010
37980         assign { } { }
37981         assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
37982       attribute \src "libresoc.v:0.0-0.0"
37983       case 5'01010
37984         assign { } { }
37985         assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
37986       attribute \src "libresoc.v:0.0-0.0"
37987       case 5'01110
37988         assign { } { }
37989         assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
37990       case
37991         assign $1\dec31_dec_sub19_inv_a[0:0] 1'0
37992     end
37993     sync always
37994       update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0]
37995   end
37996   attribute \src "libresoc.v:26078.3-26096.6"
37997   process $proc$libresoc.v:26078$564
37998     assign { } { }
37999     assign { } { }
38000     assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0]
38001     attribute \src "libresoc.v:26079.5-26079.29"
38002     switch \initial
38003       attribute \src "libresoc.v:26079.9-26079.17"
38004       case 1'1
38005       case
38006     end
38007     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38008     switch \opcode_switch
38009       attribute \src "libresoc.v:0.0-0.0"
38010       case 5'00000
38011         assign { } { }
38012         assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
38013       attribute \src "libresoc.v:0.0-0.0"
38014       case 5'00010
38015         assign { } { }
38016         assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
38017       attribute \src "libresoc.v:0.0-0.0"
38018       case 5'01010
38019         assign { } { }
38020         assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
38021       attribute \src "libresoc.v:0.0-0.0"
38022       case 5'01110
38023         assign { } { }
38024         assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
38025       case
38026         assign $1\dec31_dec_sub19_inv_out[0:0] 1'0
38027     end
38028     sync always
38029       update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0]
38030   end
38031   attribute \src "libresoc.v:26097.3-26115.6"
38032   process $proc$libresoc.v:26097$565
38033     assign { } { }
38034     assign { } { }
38035     assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0]
38036     attribute \src "libresoc.v:26098.5-26098.29"
38037     switch \initial
38038       attribute \src "libresoc.v:26098.9-26098.17"
38039       case 1'1
38040       case
38041     end
38042     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38043     switch \opcode_switch
38044       attribute \src "libresoc.v:0.0-0.0"
38045       case 5'00000
38046         assign { } { }
38047         assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
38048       attribute \src "libresoc.v:0.0-0.0"
38049       case 5'00010
38050         assign { } { }
38051         assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
38052       attribute \src "libresoc.v:0.0-0.0"
38053       case 5'01010
38054         assign { } { }
38055         assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
38056       attribute \src "libresoc.v:0.0-0.0"
38057       case 5'01110
38058         assign { } { }
38059         assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
38060       case
38061         assign $1\dec31_dec_sub19_cry_out[0:0] 1'0
38062     end
38063     sync always
38064       update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0]
38065   end
38066   attribute \src "libresoc.v:26116.3-26134.6"
38067   process $proc$libresoc.v:26116$566
38068     assign { } { }
38069     assign { } { }
38070     assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0]
38071     attribute \src "libresoc.v:26117.5-26117.29"
38072     switch \initial
38073       attribute \src "libresoc.v:26117.9-26117.17"
38074       case 1'1
38075       case
38076     end
38077     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38078     switch \opcode_switch
38079       attribute \src "libresoc.v:0.0-0.0"
38080       case 5'00000
38081         assign { } { }
38082         assign $1\dec31_dec_sub19_br[0:0] 1'0
38083       attribute \src "libresoc.v:0.0-0.0"
38084       case 5'00010
38085         assign { } { }
38086         assign $1\dec31_dec_sub19_br[0:0] 1'0
38087       attribute \src "libresoc.v:0.0-0.0"
38088       case 5'01010
38089         assign { } { }
38090         assign $1\dec31_dec_sub19_br[0:0] 1'0
38091       attribute \src "libresoc.v:0.0-0.0"
38092       case 5'01110
38093         assign { } { }
38094         assign $1\dec31_dec_sub19_br[0:0] 1'0
38095       case
38096         assign $1\dec31_dec_sub19_br[0:0] 1'0
38097     end
38098     sync always
38099       update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0]
38100   end
38101   attribute \src "libresoc.v:26135.3-26153.6"
38102   process $proc$libresoc.v:26135$567
38103     assign { } { }
38104     assign { } { }
38105     assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0]
38106     attribute \src "libresoc.v:26136.5-26136.29"
38107     switch \initial
38108       attribute \src "libresoc.v:26136.9-26136.17"
38109       case 1'1
38110       case
38111     end
38112     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38113     switch \opcode_switch
38114       attribute \src "libresoc.v:0.0-0.0"
38115       case 5'00000
38116         assign { } { }
38117         assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
38118       attribute \src "libresoc.v:0.0-0.0"
38119       case 5'00010
38120         assign { } { }
38121         assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
38122       attribute \src "libresoc.v:0.0-0.0"
38123       case 5'01010
38124         assign { } { }
38125         assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
38126       attribute \src "libresoc.v:0.0-0.0"
38127       case 5'01110
38128         assign { } { }
38129         assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
38130       case
38131         assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0
38132     end
38133     sync always
38134       update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0]
38135   end
38136   attribute \src "libresoc.v:26154.3-26172.6"
38137   process $proc$libresoc.v:26154$568
38138     assign { } { }
38139     assign { } { }
38140     assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0]
38141     attribute \src "libresoc.v:26155.5-26155.29"
38142     switch \initial
38143       attribute \src "libresoc.v:26155.9-26155.17"
38144       case 1'1
38145       case
38146     end
38147     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38148     switch \opcode_switch
38149       attribute \src "libresoc.v:0.0-0.0"
38150       case 5'00000
38151         assign { } { }
38152         assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101
38153       attribute \src "libresoc.v:0.0-0.0"
38154       case 5'00010
38155         assign { } { }
38156         assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111
38157       attribute \src "libresoc.v:0.0-0.0"
38158       case 5'01010
38159         assign { } { }
38160         assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110
38161       attribute \src "libresoc.v:0.0-0.0"
38162       case 5'01110
38163         assign { } { }
38164         assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001
38165       case
38166         assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000
38167     end
38168     sync always
38169       update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0]
38170   end
38171   attribute \src "libresoc.v:26173.3-26191.6"
38172   process $proc$libresoc.v:26173$569
38173     assign { } { }
38174     assign { } { }
38175     assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0]
38176     attribute \src "libresoc.v:26174.5-26174.29"
38177     switch \initial
38178       attribute \src "libresoc.v:26174.9-26174.17"
38179       case 1'1
38180       case
38181     end
38182     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38183     switch \opcode_switch
38184       attribute \src "libresoc.v:0.0-0.0"
38185       case 5'00000
38186         assign { } { }
38187         assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
38188       attribute \src "libresoc.v:0.0-0.0"
38189       case 5'00010
38190         assign { } { }
38191         assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
38192       attribute \src "libresoc.v:0.0-0.0"
38193       case 5'01010
38194         assign { } { }
38195         assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
38196       attribute \src "libresoc.v:0.0-0.0"
38197       case 5'01110
38198         assign { } { }
38199         assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
38200       case
38201         assign $1\dec31_dec_sub19_rsrv[0:0] 1'0
38202     end
38203     sync always
38204       update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0]
38205   end
38206   attribute \src "libresoc.v:26192.3-26210.6"
38207   process $proc$libresoc.v:26192$570
38208     assign { } { }
38209     assign { } { }
38210     assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0]
38211     attribute \src "libresoc.v:26193.5-26193.29"
38212     switch \initial
38213       attribute \src "libresoc.v:26193.9-26193.17"
38214       case 1'1
38215       case
38216     end
38217     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38218     switch \opcode_switch
38219       attribute \src "libresoc.v:0.0-0.0"
38220       case 5'00000
38221         assign { } { }
38222         assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
38223       attribute \src "libresoc.v:0.0-0.0"
38224       case 5'00010
38225         assign { } { }
38226         assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
38227       attribute \src "libresoc.v:0.0-0.0"
38228       case 5'01010
38229         assign { } { }
38230         assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
38231       attribute \src "libresoc.v:0.0-0.0"
38232       case 5'01110
38233         assign { } { }
38234         assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
38235       case
38236         assign $1\dec31_dec_sub19_is_32b[0:0] 1'0
38237     end
38238     sync always
38239       update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0]
38240   end
38241   attribute \src "libresoc.v:26211.3-26229.6"
38242   process $proc$libresoc.v:26211$571
38243     assign { } { }
38244     assign { } { }
38245     assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0]
38246     attribute \src "libresoc.v:26212.5-26212.29"
38247     switch \initial
38248       attribute \src "libresoc.v:26212.9-26212.17"
38249       case 1'1
38250       case
38251     end
38252     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38253     switch \opcode_switch
38254       attribute \src "libresoc.v:0.0-0.0"
38255       case 5'00000
38256         assign { } { }
38257         assign $1\dec31_dec_sub19_sgn[0:0] 1'0
38258       attribute \src "libresoc.v:0.0-0.0"
38259       case 5'00010
38260         assign { } { }
38261         assign $1\dec31_dec_sub19_sgn[0:0] 1'0
38262       attribute \src "libresoc.v:0.0-0.0"
38263       case 5'01010
38264         assign { } { }
38265         assign $1\dec31_dec_sub19_sgn[0:0] 1'0
38266       attribute \src "libresoc.v:0.0-0.0"
38267       case 5'01110
38268         assign { } { }
38269         assign $1\dec31_dec_sub19_sgn[0:0] 1'0
38270       case
38271         assign $1\dec31_dec_sub19_sgn[0:0] 1'0
38272     end
38273     sync always
38274       update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0]
38275   end
38276   attribute \src "libresoc.v:26230.3-26248.6"
38277   process $proc$libresoc.v:26230$572
38278     assign { } { }
38279     assign { } { }
38280     assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0]
38281     attribute \src "libresoc.v:26231.5-26231.29"
38282     switch \initial
38283       attribute \src "libresoc.v:26231.9-26231.17"
38284       case 1'1
38285       case
38286     end
38287     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38288     switch \opcode_switch
38289       attribute \src "libresoc.v:0.0-0.0"
38290       case 5'00000
38291         assign { } { }
38292         assign $1\dec31_dec_sub19_lk[0:0] 1'0
38293       attribute \src "libresoc.v:0.0-0.0"
38294       case 5'00010
38295         assign { } { }
38296         assign $1\dec31_dec_sub19_lk[0:0] 1'0
38297       attribute \src "libresoc.v:0.0-0.0"
38298       case 5'01010
38299         assign { } { }
38300         assign $1\dec31_dec_sub19_lk[0:0] 1'0
38301       attribute \src "libresoc.v:0.0-0.0"
38302       case 5'01110
38303         assign { } { }
38304         assign $1\dec31_dec_sub19_lk[0:0] 1'0
38305       case
38306         assign $1\dec31_dec_sub19_lk[0:0] 1'0
38307     end
38308     sync always
38309       update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0]
38310   end
38311   attribute \src "libresoc.v:26249.3-26267.6"
38312   process $proc$libresoc.v:26249$573
38313     assign { } { }
38314     assign { } { }
38315     assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0]
38316     attribute \src "libresoc.v:26250.5-26250.29"
38317     switch \initial
38318       attribute \src "libresoc.v:26250.9-26250.17"
38319       case 1'1
38320       case
38321     end
38322     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38323     switch \opcode_switch
38324       attribute \src "libresoc.v:0.0-0.0"
38325       case 5'00000
38326         assign { } { }
38327         assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
38328       attribute \src "libresoc.v:0.0-0.0"
38329       case 5'00010
38330         assign { } { }
38331         assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1
38332       attribute \src "libresoc.v:0.0-0.0"
38333       case 5'01010
38334         assign { } { }
38335         assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
38336       attribute \src "libresoc.v:0.0-0.0"
38337       case 5'01110
38338         assign { } { }
38339         assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
38340       case
38341         assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0
38342     end
38343     sync always
38344       update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0]
38345   end
38346   attribute \src "libresoc.v:26268.3-26286.6"
38347   process $proc$libresoc.v:26268$574
38348     assign { } { }
38349     assign { } { }
38350     assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0]
38351     attribute \src "libresoc.v:26269.5-26269.29"
38352     switch \initial
38353       attribute \src "libresoc.v:26269.9-26269.17"
38354       case 1'1
38355       case
38356     end
38357     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38358     switch \opcode_switch
38359       attribute \src "libresoc.v:0.0-0.0"
38360       case 5'00000
38361         assign { } { }
38362         assign $1\dec31_dec_sub19_form[4:0] 5'01010
38363       attribute \src "libresoc.v:0.0-0.0"
38364       case 5'00010
38365         assign { } { }
38366         assign $1\dec31_dec_sub19_form[4:0] 5'01000
38367       attribute \src "libresoc.v:0.0-0.0"
38368       case 5'01010
38369         assign { } { }
38370         assign $1\dec31_dec_sub19_form[4:0] 5'01010
38371       attribute \src "libresoc.v:0.0-0.0"
38372       case 5'01110
38373         assign { } { }
38374         assign $1\dec31_dec_sub19_form[4:0] 5'01010
38375       case
38376         assign $1\dec31_dec_sub19_form[4:0] 5'00000
38377     end
38378     sync always
38379       update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0]
38380   end
38381   attribute \src "libresoc.v:26287.3-26305.6"
38382   process $proc$libresoc.v:26287$575
38383     assign { } { }
38384     assign { } { }
38385     assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0]
38386     attribute \src "libresoc.v:26288.5-26288.29"
38387     switch \initial
38388       attribute \src "libresoc.v:26288.9-26288.17"
38389       case 1'1
38390       case
38391     end
38392     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38393     switch \opcode_switch
38394       attribute \src "libresoc.v:0.0-0.0"
38395       case 5'00000
38396         assign { } { }
38397         assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
38398       attribute \src "libresoc.v:0.0-0.0"
38399       case 5'00010
38400         assign { } { }
38401         assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
38402       attribute \src "libresoc.v:0.0-0.0"
38403       case 5'01010
38404         assign { } { }
38405         assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011
38406       attribute \src "libresoc.v:0.0-0.0"
38407       case 5'01110
38408         assign { } { }
38409         assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100
38410       case
38411         assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000
38412     end
38413     sync always
38414       update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0]
38415   end
38416   attribute \src "libresoc.v:26306.3-26324.6"
38417   process $proc$libresoc.v:26306$576
38418     assign { } { }
38419     assign { } { }
38420     assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0]
38421     attribute \src "libresoc.v:26307.5-26307.29"
38422     switch \initial
38423       attribute \src "libresoc.v:26307.9-26307.17"
38424       case 1'1
38425       case
38426     end
38427     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38428     switch \opcode_switch
38429       attribute \src "libresoc.v:0.0-0.0"
38430       case 5'00000
38431         assign { } { }
38432         assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
38433       attribute \src "libresoc.v:0.0-0.0"
38434       case 5'00010
38435         assign { } { }
38436         assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
38437       attribute \src "libresoc.v:0.0-0.0"
38438       case 5'01010
38439         assign { } { }
38440         assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
38441       attribute \src "libresoc.v:0.0-0.0"
38442       case 5'01110
38443         assign { } { }
38444         assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
38445       case
38446         assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000
38447     end
38448     sync always
38449       update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0]
38450   end
38451   attribute \src "libresoc.v:26325.3-26343.6"
38452   process $proc$libresoc.v:26325$577
38453     assign { } { }
38454     assign { } { }
38455     assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0]
38456     attribute \src "libresoc.v:26326.5-26326.29"
38457     switch \initial
38458       attribute \src "libresoc.v:26326.9-26326.17"
38459       case 1'1
38460       case
38461     end
38462     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38463     switch \opcode_switch
38464       attribute \src "libresoc.v:0.0-0.0"
38465       case 5'00000
38466         assign { } { }
38467         assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
38468       attribute \src "libresoc.v:0.0-0.0"
38469       case 5'00010
38470         assign { } { }
38471         assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
38472       attribute \src "libresoc.v:0.0-0.0"
38473       case 5'01010
38474         assign { } { }
38475         assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
38476       attribute \src "libresoc.v:0.0-0.0"
38477       case 5'01110
38478         assign { } { }
38479         assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
38480       case
38481         assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00
38482     end
38483     sync always
38484       update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0]
38485   end
38486   attribute \src "libresoc.v:26344.3-26362.6"
38487   process $proc$libresoc.v:26344$578
38488     assign { } { }
38489     assign { } { }
38490     assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0]
38491     attribute \src "libresoc.v:26345.5-26345.29"
38492     switch \initial
38493       attribute \src "libresoc.v:26345.9-26345.17"
38494       case 1'1
38495       case
38496     end
38497     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38498     switch \opcode_switch
38499       attribute \src "libresoc.v:0.0-0.0"
38500       case 5'00000
38501         assign { } { }
38502         assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
38503       attribute \src "libresoc.v:0.0-0.0"
38504       case 5'00010
38505         assign { } { }
38506         assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
38507       attribute \src "libresoc.v:0.0-0.0"
38508       case 5'01010
38509         assign { } { }
38510         assign $1\dec31_dec_sub19_out_sel[1:0] 2'01
38511       attribute \src "libresoc.v:0.0-0.0"
38512       case 5'01110
38513         assign { } { }
38514         assign $1\dec31_dec_sub19_out_sel[1:0] 2'11
38515       case
38516         assign $1\dec31_dec_sub19_out_sel[1:0] 2'00
38517     end
38518     sync always
38519       update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0]
38520   end
38521   attribute \src "libresoc.v:26363.3-26381.6"
38522   process $proc$libresoc.v:26363$579
38523     assign { } { }
38524     assign { } { }
38525     assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0]
38526     attribute \src "libresoc.v:26364.5-26364.29"
38527     switch \initial
38528       attribute \src "libresoc.v:26364.9-26364.17"
38529       case 1'1
38530       case
38531     end
38532     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38533     switch \opcode_switch
38534       attribute \src "libresoc.v:0.0-0.0"
38535       case 5'00000
38536         assign { } { }
38537         assign $1\dec31_dec_sub19_cr_in[2:0] 3'110
38538       attribute \src "libresoc.v:0.0-0.0"
38539       case 5'00010
38540         assign { } { }
38541         assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
38542       attribute \src "libresoc.v:0.0-0.0"
38543       case 5'01010
38544         assign { } { }
38545         assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
38546       attribute \src "libresoc.v:0.0-0.0"
38547       case 5'01110
38548         assign { } { }
38549         assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
38550       case
38551         assign $1\dec31_dec_sub19_cr_in[2:0] 3'000
38552     end
38553     sync always
38554       update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0]
38555   end
38556   attribute \src "libresoc.v:26382.3-26400.6"
38557   process $proc$libresoc.v:26382$580
38558     assign { } { }
38559     assign { } { }
38560     assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0]
38561     attribute \src "libresoc.v:26383.5-26383.29"
38562     switch \initial
38563       attribute \src "libresoc.v:26383.9-26383.17"
38564       case 1'1
38565       case
38566     end
38567     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38568     switch \opcode_switch
38569       attribute \src "libresoc.v:0.0-0.0"
38570       case 5'00000
38571         assign { } { }
38572         assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
38573       attribute \src "libresoc.v:0.0-0.0"
38574       case 5'00010
38575         assign { } { }
38576         assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
38577       attribute \src "libresoc.v:0.0-0.0"
38578       case 5'01010
38579         assign { } { }
38580         assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
38581       attribute \src "libresoc.v:0.0-0.0"
38582       case 5'01110
38583         assign { } { }
38584         assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
38585       case
38586         assign $1\dec31_dec_sub19_cr_out[2:0] 3'000
38587     end
38588     sync always
38589       update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0]
38590   end
38591   connect \opcode_switch \opcode_in [10:6]
38592 end
38593 attribute \src "libresoc.v:26406.1-27265.10"
38594 attribute \cells_not_processed 1
38595 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20"
38596 attribute \generator "nMigen"
38597 module \dec31_dec_sub20
38598   attribute \src "libresoc.v:26789.3-26813.6"
38599   wire width 8 $0\dec31_dec_sub20_asmcode[7:0]
38600   attribute \src "libresoc.v:26889.3-26913.6"
38601   wire $0\dec31_dec_sub20_br[0:0]
38602   attribute \src "libresoc.v:27214.3-27238.6"
38603   wire width 3 $0\dec31_dec_sub20_cr_in[2:0]
38604   attribute \src "libresoc.v:27239.3-27263.6"
38605   wire width 3 $0\dec31_dec_sub20_cr_out[2:0]
38606   attribute \src "libresoc.v:26764.3-26788.6"
38607   wire width 2 $0\dec31_dec_sub20_cry_in[1:0]
38608   attribute \src "libresoc.v:26864.3-26888.6"
38609   wire $0\dec31_dec_sub20_cry_out[0:0]
38610   attribute \src "libresoc.v:27089.3-27113.6"
38611   wire width 5 $0\dec31_dec_sub20_form[4:0]
38612   attribute \src "libresoc.v:26664.3-26688.6"
38613   wire width 12 $0\dec31_dec_sub20_function_unit[11:0]
38614   attribute \src "libresoc.v:27114.3-27138.6"
38615   wire width 3 $0\dec31_dec_sub20_in1_sel[2:0]
38616   attribute \src "libresoc.v:27139.3-27163.6"
38617   wire width 4 $0\dec31_dec_sub20_in2_sel[3:0]
38618   attribute \src "libresoc.v:27164.3-27188.6"
38619   wire width 2 $0\dec31_dec_sub20_in3_sel[1:0]
38620   attribute \src "libresoc.v:26939.3-26963.6"
38621   wire width 7 $0\dec31_dec_sub20_internal_op[6:0]
38622   attribute \src "libresoc.v:26814.3-26838.6"
38623   wire $0\dec31_dec_sub20_inv_a[0:0]
38624   attribute \src "libresoc.v:26839.3-26863.6"
38625   wire $0\dec31_dec_sub20_inv_out[0:0]
38626   attribute \src "libresoc.v:26989.3-27013.6"
38627   wire $0\dec31_dec_sub20_is_32b[0:0]
38628   attribute \src "libresoc.v:26689.3-26713.6"
38629   wire width 4 $0\dec31_dec_sub20_ldst_len[3:0]
38630   attribute \src "libresoc.v:27039.3-27063.6"
38631   wire $0\dec31_dec_sub20_lk[0:0]
38632   attribute \src "libresoc.v:27189.3-27213.6"
38633   wire width 2 $0\dec31_dec_sub20_out_sel[1:0]
38634   attribute \src "libresoc.v:26739.3-26763.6"
38635   wire width 2 $0\dec31_dec_sub20_rc_sel[1:0]
38636   attribute \src "libresoc.v:26964.3-26988.6"
38637   wire $0\dec31_dec_sub20_rsrv[0:0]
38638   attribute \src "libresoc.v:27064.3-27088.6"
38639   wire $0\dec31_dec_sub20_sgl_pipe[0:0]
38640   attribute \src "libresoc.v:27014.3-27038.6"
38641   wire $0\dec31_dec_sub20_sgn[0:0]
38642   attribute \src "libresoc.v:26914.3-26938.6"
38643   wire $0\dec31_dec_sub20_sgn_ext[0:0]
38644   attribute \src "libresoc.v:26714.3-26738.6"
38645   wire width 2 $0\dec31_dec_sub20_upd[1:0]
38646   attribute \src "libresoc.v:26407.7-26407.20"
38647   wire $0\initial[0:0]
38648   attribute \src "libresoc.v:26789.3-26813.6"
38649   wire width 8 $1\dec31_dec_sub20_asmcode[7:0]
38650   attribute \src "libresoc.v:26889.3-26913.6"
38651   wire $1\dec31_dec_sub20_br[0:0]
38652   attribute \src "libresoc.v:27214.3-27238.6"
38653   wire width 3 $1\dec31_dec_sub20_cr_in[2:0]
38654   attribute \src "libresoc.v:27239.3-27263.6"
38655   wire width 3 $1\dec31_dec_sub20_cr_out[2:0]
38656   attribute \src "libresoc.v:26764.3-26788.6"
38657   wire width 2 $1\dec31_dec_sub20_cry_in[1:0]
38658   attribute \src "libresoc.v:26864.3-26888.6"
38659   wire $1\dec31_dec_sub20_cry_out[0:0]
38660   attribute \src "libresoc.v:27089.3-27113.6"
38661   wire width 5 $1\dec31_dec_sub20_form[4:0]
38662   attribute \src "libresoc.v:26664.3-26688.6"
38663   wire width 12 $1\dec31_dec_sub20_function_unit[11:0]
38664   attribute \src "libresoc.v:27114.3-27138.6"
38665   wire width 3 $1\dec31_dec_sub20_in1_sel[2:0]
38666   attribute \src "libresoc.v:27139.3-27163.6"
38667   wire width 4 $1\dec31_dec_sub20_in2_sel[3:0]
38668   attribute \src "libresoc.v:27164.3-27188.6"
38669   wire width 2 $1\dec31_dec_sub20_in3_sel[1:0]
38670   attribute \src "libresoc.v:26939.3-26963.6"
38671   wire width 7 $1\dec31_dec_sub20_internal_op[6:0]
38672   attribute \src "libresoc.v:26814.3-26838.6"
38673   wire $1\dec31_dec_sub20_inv_a[0:0]
38674   attribute \src "libresoc.v:26839.3-26863.6"
38675   wire $1\dec31_dec_sub20_inv_out[0:0]
38676   attribute \src "libresoc.v:26989.3-27013.6"
38677   wire $1\dec31_dec_sub20_is_32b[0:0]
38678   attribute \src "libresoc.v:26689.3-26713.6"
38679   wire width 4 $1\dec31_dec_sub20_ldst_len[3:0]
38680   attribute \src "libresoc.v:27039.3-27063.6"
38681   wire $1\dec31_dec_sub20_lk[0:0]
38682   attribute \src "libresoc.v:27189.3-27213.6"
38683   wire width 2 $1\dec31_dec_sub20_out_sel[1:0]
38684   attribute \src "libresoc.v:26739.3-26763.6"
38685   wire width 2 $1\dec31_dec_sub20_rc_sel[1:0]
38686   attribute \src "libresoc.v:26964.3-26988.6"
38687   wire $1\dec31_dec_sub20_rsrv[0:0]
38688   attribute \src "libresoc.v:27064.3-27088.6"
38689   wire $1\dec31_dec_sub20_sgl_pipe[0:0]
38690   attribute \src "libresoc.v:27014.3-27038.6"
38691   wire $1\dec31_dec_sub20_sgn[0:0]
38692   attribute \src "libresoc.v:26914.3-26938.6"
38693   wire $1\dec31_dec_sub20_sgn_ext[0:0]
38694   attribute \src "libresoc.v:26714.3-26738.6"
38695   wire width 2 $1\dec31_dec_sub20_upd[1:0]
38696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38697   wire width 8 output 4 \dec31_dec_sub20_asmcode
38698   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38699   wire output 18 \dec31_dec_sub20_br
38700   attribute \enum_base_type "CRInSel"
38701   attribute \enum_value_000 "NONE"
38702   attribute \enum_value_001 "CR0"
38703   attribute \enum_value_010 "BI"
38704   attribute \enum_value_011 "BFA"
38705   attribute \enum_value_100 "BA_BB"
38706   attribute \enum_value_101 "BC"
38707   attribute \enum_value_110 "WHOLE_REG"
38708   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38709   wire width 3 output 9 \dec31_dec_sub20_cr_in
38710   attribute \enum_base_type "CROutSel"
38711   attribute \enum_value_000 "NONE"
38712   attribute \enum_value_001 "CR0"
38713   attribute \enum_value_010 "BF"
38714   attribute \enum_value_011 "BT"
38715   attribute \enum_value_100 "WHOLE_REG"
38716   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38717   wire width 3 output 10 \dec31_dec_sub20_cr_out
38718   attribute \enum_base_type "CryIn"
38719   attribute \enum_value_00 "ZERO"
38720   attribute \enum_value_01 "ONE"
38721   attribute \enum_value_10 "CA"
38722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38723   wire width 2 output 14 \dec31_dec_sub20_cry_in
38724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38725   wire output 17 \dec31_dec_sub20_cry_out
38726   attribute \enum_base_type "Form"
38727   attribute \enum_value_00000 "NONE"
38728   attribute \enum_value_00001 "I"
38729   attribute \enum_value_00010 "B"
38730   attribute \enum_value_00011 "SC"
38731   attribute \enum_value_00100 "D"
38732   attribute \enum_value_00101 "DS"
38733   attribute \enum_value_00110 "DQ"
38734   attribute \enum_value_00111 "DX"
38735   attribute \enum_value_01000 "X"
38736   attribute \enum_value_01001 "XL"
38737   attribute \enum_value_01010 "XFX"
38738   attribute \enum_value_01011 "XFL"
38739   attribute \enum_value_01100 "XX1"
38740   attribute \enum_value_01101 "XX2"
38741   attribute \enum_value_01110 "XX3"
38742   attribute \enum_value_01111 "XX4"
38743   attribute \enum_value_10000 "XS"
38744   attribute \enum_value_10001 "XO"
38745   attribute \enum_value_10010 "A"
38746   attribute \enum_value_10011 "M"
38747   attribute \enum_value_10100 "MD"
38748   attribute \enum_value_10101 "MDS"
38749   attribute \enum_value_10110 "VA"
38750   attribute \enum_value_10111 "VC"
38751   attribute \enum_value_11000 "VX"
38752   attribute \enum_value_11001 "EVX"
38753   attribute \enum_value_11010 "EVS"
38754   attribute \enum_value_11011 "Z22"
38755   attribute \enum_value_11100 "Z23"
38756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38757   wire width 5 output 3 \dec31_dec_sub20_form
38758   attribute \enum_base_type "Function"
38759   attribute \enum_value_000000000000 "NONE"
38760   attribute \enum_value_000000000010 "ALU"
38761   attribute \enum_value_000000000100 "LDST"
38762   attribute \enum_value_000000001000 "SHIFT_ROT"
38763   attribute \enum_value_000000010000 "LOGICAL"
38764   attribute \enum_value_000000100000 "BRANCH"
38765   attribute \enum_value_000001000000 "CR"
38766   attribute \enum_value_000010000000 "TRAP"
38767   attribute \enum_value_000100000000 "MUL"
38768   attribute \enum_value_001000000000 "DIV"
38769   attribute \enum_value_010000000000 "SPR"
38770   attribute \enum_value_100000000000 "MMU"
38771   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38772   wire width 12 output 1 \dec31_dec_sub20_function_unit
38773   attribute \enum_base_type "In1Sel"
38774   attribute \enum_value_000 "NONE"
38775   attribute \enum_value_001 "RA"
38776   attribute \enum_value_010 "RA_OR_ZERO"
38777   attribute \enum_value_011 "SPR"
38778   attribute \enum_value_100 "RS"
38779   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38780   wire width 3 output 5 \dec31_dec_sub20_in1_sel
38781   attribute \enum_base_type "In2Sel"
38782   attribute \enum_value_0000 "NONE"
38783   attribute \enum_value_0001 "RB"
38784   attribute \enum_value_0010 "CONST_UI"
38785   attribute \enum_value_0011 "CONST_SI"
38786   attribute \enum_value_0100 "CONST_UI_HI"
38787   attribute \enum_value_0101 "CONST_SI_HI"
38788   attribute \enum_value_0110 "CONST_LI"
38789   attribute \enum_value_0111 "CONST_BD"
38790   attribute \enum_value_1000 "CONST_DS"
38791   attribute \enum_value_1001 "CONST_M1"
38792   attribute \enum_value_1010 "CONST_SH"
38793   attribute \enum_value_1011 "CONST_SH32"
38794   attribute \enum_value_1100 "SPR"
38795   attribute \enum_value_1101 "RS"
38796   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38797   wire width 4 output 6 \dec31_dec_sub20_in2_sel
38798   attribute \enum_base_type "In3Sel"
38799   attribute \enum_value_00 "NONE"
38800   attribute \enum_value_01 "RS"
38801   attribute \enum_value_10 "RB"
38802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38803   wire width 2 output 7 \dec31_dec_sub20_in3_sel
38804   attribute \enum_base_type "MicrOp"
38805   attribute \enum_value_0000000 "OP_ILLEGAL"
38806   attribute \enum_value_0000001 "OP_NOP"
38807   attribute \enum_value_0000010 "OP_ADD"
38808   attribute \enum_value_0000011 "OP_ADDPCIS"
38809   attribute \enum_value_0000100 "OP_AND"
38810   attribute \enum_value_0000101 "OP_ATTN"
38811   attribute \enum_value_0000110 "OP_B"
38812   attribute \enum_value_0000111 "OP_BC"
38813   attribute \enum_value_0001000 "OP_BCREG"
38814   attribute \enum_value_0001001 "OP_BPERM"
38815   attribute \enum_value_0001010 "OP_CMP"
38816   attribute \enum_value_0001011 "OP_CMPB"
38817   attribute \enum_value_0001100 "OP_CMPEQB"
38818   attribute \enum_value_0001101 "OP_CMPRB"
38819   attribute \enum_value_0001110 "OP_CNTZ"
38820   attribute \enum_value_0001111 "OP_CRAND"
38821   attribute \enum_value_0010000 "OP_CRANDC"
38822   attribute \enum_value_0010001 "OP_CREQV"
38823   attribute \enum_value_0010010 "OP_CRNAND"
38824   attribute \enum_value_0010011 "OP_CRNOR"
38825   attribute \enum_value_0010100 "OP_CROR"
38826   attribute \enum_value_0010101 "OP_CRORC"
38827   attribute \enum_value_0010110 "OP_CRXOR"
38828   attribute \enum_value_0010111 "OP_DARN"
38829   attribute \enum_value_0011000 "OP_DCBF"
38830   attribute \enum_value_0011001 "OP_DCBST"
38831   attribute \enum_value_0011010 "OP_DCBT"
38832   attribute \enum_value_0011011 "OP_DCBTST"
38833   attribute \enum_value_0011100 "OP_DCBZ"
38834   attribute \enum_value_0011101 "OP_DIV"
38835   attribute \enum_value_0011110 "OP_DIVE"
38836   attribute \enum_value_0011111 "OP_EXTS"
38837   attribute \enum_value_0100000 "OP_EXTSWSLI"
38838   attribute \enum_value_0100001 "OP_ICBI"
38839   attribute \enum_value_0100010 "OP_ICBT"
38840   attribute \enum_value_0100011 "OP_ISEL"
38841   attribute \enum_value_0100100 "OP_ISYNC"
38842   attribute \enum_value_0100101 "OP_LOAD"
38843   attribute \enum_value_0100110 "OP_STORE"
38844   attribute \enum_value_0100111 "OP_MADDHD"
38845   attribute \enum_value_0101000 "OP_MADDHDU"
38846   attribute \enum_value_0101001 "OP_MADDLD"
38847   attribute \enum_value_0101010 "OP_MCRF"
38848   attribute \enum_value_0101011 "OP_MCRXR"
38849   attribute \enum_value_0101100 "OP_MCRXRX"
38850   attribute \enum_value_0101101 "OP_MFCR"
38851   attribute \enum_value_0101110 "OP_MFSPR"
38852   attribute \enum_value_0101111 "OP_MOD"
38853   attribute \enum_value_0110000 "OP_MTCRF"
38854   attribute \enum_value_0110001 "OP_MTSPR"
38855   attribute \enum_value_0110010 "OP_MUL_L64"
38856   attribute \enum_value_0110011 "OP_MUL_H64"
38857   attribute \enum_value_0110100 "OP_MUL_H32"
38858   attribute \enum_value_0110101 "OP_OR"
38859   attribute \enum_value_0110110 "OP_POPCNT"
38860   attribute \enum_value_0110111 "OP_PRTY"
38861   attribute \enum_value_0111000 "OP_RLC"
38862   attribute \enum_value_0111001 "OP_RLCL"
38863   attribute \enum_value_0111010 "OP_RLCR"
38864   attribute \enum_value_0111011 "OP_SETB"
38865   attribute \enum_value_0111100 "OP_SHL"
38866   attribute \enum_value_0111101 "OP_SHR"
38867   attribute \enum_value_0111110 "OP_SYNC"
38868   attribute \enum_value_0111111 "OP_TRAP"
38869   attribute \enum_value_1000011 "OP_XOR"
38870   attribute \enum_value_1000100 "OP_SIM_CONFIG"
38871   attribute \enum_value_1000101 "OP_CROP"
38872   attribute \enum_value_1000110 "OP_RFID"
38873   attribute \enum_value_1000111 "OP_MFMSR"
38874   attribute \enum_value_1001000 "OP_MTMSRD"
38875   attribute \enum_value_1001001 "OP_SC"
38876   attribute \enum_value_1001010 "OP_MTMSR"
38877   attribute \enum_value_1001011 "OP_TLBIE"
38878   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38879   wire width 7 output 2 \dec31_dec_sub20_internal_op
38880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38881   wire output 15 \dec31_dec_sub20_inv_a
38882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38883   wire output 16 \dec31_dec_sub20_inv_out
38884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38885   wire output 21 \dec31_dec_sub20_is_32b
38886   attribute \enum_base_type "LdstLen"
38887   attribute \enum_value_0000 "NONE"
38888   attribute \enum_value_0001 "is1B"
38889   attribute \enum_value_0010 "is2B"
38890   attribute \enum_value_0100 "is4B"
38891   attribute \enum_value_1000 "is8B"
38892   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38893   wire width 4 output 11 \dec31_dec_sub20_ldst_len
38894   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38895   wire output 23 \dec31_dec_sub20_lk
38896   attribute \enum_base_type "OutSel"
38897   attribute \enum_value_00 "NONE"
38898   attribute \enum_value_01 "RT"
38899   attribute \enum_value_10 "RA"
38900   attribute \enum_value_11 "SPR"
38901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38902   wire width 2 output 8 \dec31_dec_sub20_out_sel
38903   attribute \enum_base_type "RC"
38904   attribute \enum_value_00 "NONE"
38905   attribute \enum_value_01 "ONE"
38906   attribute \enum_value_10 "RC"
38907   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38908   wire width 2 output 13 \dec31_dec_sub20_rc_sel
38909   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38910   wire output 20 \dec31_dec_sub20_rsrv
38911   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38912   wire output 24 \dec31_dec_sub20_sgl_pipe
38913   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38914   wire output 22 \dec31_dec_sub20_sgn
38915   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
38916   wire output 19 \dec31_dec_sub20_sgn_ext
38917   attribute \enum_base_type "LDSTMode"
38918   attribute \enum_value_00 "NONE"
38919   attribute \enum_value_01 "update"
38920   attribute \enum_value_10 "cix"
38921   attribute \enum_value_11 "cx"
38922   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
38923   wire width 2 output 12 \dec31_dec_sub20_upd
38924   attribute \src "libresoc.v:26407.7-26407.15"
38925   wire \initial
38926   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
38927   wire width 32 input 25 \opcode_in
38928   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
38929   wire width 5 \opcode_switch
38930   attribute \src "libresoc.v:26407.7-26407.20"
38931   process $proc$libresoc.v:26407$606
38932     assign { } { }
38933     assign $0\initial[0:0] 1'0
38934     sync always
38935       update \initial $0\initial[0:0]
38936     sync init
38937   end
38938   attribute \src "libresoc.v:26664.3-26688.6"
38939   process $proc$libresoc.v:26664$582
38940     assign { } { }
38941     assign { } { }
38942     assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0]
38943     attribute \src "libresoc.v:26665.5-26665.29"
38944     switch \initial
38945       attribute \src "libresoc.v:26665.9-26665.17"
38946       case 1'1
38947       case
38948     end
38949     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38950     switch \opcode_switch
38951       attribute \src "libresoc.v:0.0-0.0"
38952       case 5'00001
38953         assign { } { }
38954         assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100
38955       attribute \src "libresoc.v:0.0-0.0"
38956       case 5'00010
38957         assign { } { }
38958         assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100
38959       attribute \src "libresoc.v:0.0-0.0"
38960       case 5'10000
38961         assign { } { }
38962         assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100
38963       attribute \src "libresoc.v:0.0-0.0"
38964       case 5'00011
38965         assign { } { }
38966         assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100
38967       attribute \src "libresoc.v:0.0-0.0"
38968       case 5'00000
38969         assign { } { }
38970         assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100
38971       attribute \src "libresoc.v:0.0-0.0"
38972       case 5'10100
38973         assign { } { }
38974         assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100
38975       case
38976         assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000
38977     end
38978     sync always
38979       update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0]
38980   end
38981   attribute \src "libresoc.v:26689.3-26713.6"
38982   process $proc$libresoc.v:26689$583
38983     assign { } { }
38984     assign { } { }
38985     assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0]
38986     attribute \src "libresoc.v:26690.5-26690.29"
38987     switch \initial
38988       attribute \src "libresoc.v:26690.9-26690.17"
38989       case 1'1
38990       case
38991     end
38992     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
38993     switch \opcode_switch
38994       attribute \src "libresoc.v:0.0-0.0"
38995       case 5'00001
38996         assign { } { }
38997         assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001
38998       attribute \src "libresoc.v:0.0-0.0"
38999       case 5'00010
39000         assign { } { }
39001         assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000
39002       attribute \src "libresoc.v:0.0-0.0"
39003       case 5'10000
39004         assign { } { }
39005         assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000
39006       attribute \src "libresoc.v:0.0-0.0"
39007       case 5'00011
39008         assign { } { }
39009         assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010
39010       attribute \src "libresoc.v:0.0-0.0"
39011       case 5'00000
39012         assign { } { }
39013         assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100
39014       attribute \src "libresoc.v:0.0-0.0"
39015       case 5'10100
39016         assign { } { }
39017         assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000
39018       case
39019         assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000
39020     end
39021     sync always
39022       update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0]
39023   end
39024   attribute \src "libresoc.v:26714.3-26738.6"
39025   process $proc$libresoc.v:26714$584
39026     assign { } { }
39027     assign { } { }
39028     assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0]
39029     attribute \src "libresoc.v:26715.5-26715.29"
39030     switch \initial
39031       attribute \src "libresoc.v:26715.9-26715.17"
39032       case 1'1
39033       case
39034     end
39035     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39036     switch \opcode_switch
39037       attribute \src "libresoc.v:0.0-0.0"
39038       case 5'00001
39039         assign { } { }
39040         assign $1\dec31_dec_sub20_upd[1:0] 2'00
39041       attribute \src "libresoc.v:0.0-0.0"
39042       case 5'00010
39043         assign { } { }
39044         assign $1\dec31_dec_sub20_upd[1:0] 2'00
39045       attribute \src "libresoc.v:0.0-0.0"
39046       case 5'10000
39047         assign { } { }
39048         assign $1\dec31_dec_sub20_upd[1:0] 2'00
39049       attribute \src "libresoc.v:0.0-0.0"
39050       case 5'00011
39051         assign { } { }
39052         assign $1\dec31_dec_sub20_upd[1:0] 2'00
39053       attribute \src "libresoc.v:0.0-0.0"
39054       case 5'00000
39055         assign { } { }
39056         assign $1\dec31_dec_sub20_upd[1:0] 2'00
39057       attribute \src "libresoc.v:0.0-0.0"
39058       case 5'10100
39059         assign { } { }
39060         assign $1\dec31_dec_sub20_upd[1:0] 2'00
39061       case
39062         assign $1\dec31_dec_sub20_upd[1:0] 2'00
39063     end
39064     sync always
39065       update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0]
39066   end
39067   attribute \src "libresoc.v:26739.3-26763.6"
39068   process $proc$libresoc.v:26739$585
39069     assign { } { }
39070     assign { } { }
39071     assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0]
39072     attribute \src "libresoc.v:26740.5-26740.29"
39073     switch \initial
39074       attribute \src "libresoc.v:26740.9-26740.17"
39075       case 1'1
39076       case
39077     end
39078     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39079     switch \opcode_switch
39080       attribute \src "libresoc.v:0.0-0.0"
39081       case 5'00001
39082         assign { } { }
39083         assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00
39084       attribute \src "libresoc.v:0.0-0.0"
39085       case 5'00010
39086         assign { } { }
39087         assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00
39088       attribute \src "libresoc.v:0.0-0.0"
39089       case 5'10000
39090         assign { } { }
39091         assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00
39092       attribute \src "libresoc.v:0.0-0.0"
39093       case 5'00011
39094         assign { } { }
39095         assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00
39096       attribute \src "libresoc.v:0.0-0.0"
39097       case 5'00000
39098         assign { } { }
39099         assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00
39100       attribute \src "libresoc.v:0.0-0.0"
39101       case 5'10100
39102         assign { } { }
39103         assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00
39104       case
39105         assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00
39106     end
39107     sync always
39108       update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0]
39109   end
39110   attribute \src "libresoc.v:26764.3-26788.6"
39111   process $proc$libresoc.v:26764$586
39112     assign { } { }
39113     assign { } { }
39114     assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0]
39115     attribute \src "libresoc.v:26765.5-26765.29"
39116     switch \initial
39117       attribute \src "libresoc.v:26765.9-26765.17"
39118       case 1'1
39119       case
39120     end
39121     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39122     switch \opcode_switch
39123       attribute \src "libresoc.v:0.0-0.0"
39124       case 5'00001
39125         assign { } { }
39126         assign $1\dec31_dec_sub20_cry_in[1:0] 2'00
39127       attribute \src "libresoc.v:0.0-0.0"
39128       case 5'00010
39129         assign { } { }
39130         assign $1\dec31_dec_sub20_cry_in[1:0] 2'00
39131       attribute \src "libresoc.v:0.0-0.0"
39132       case 5'10000
39133         assign { } { }
39134         assign $1\dec31_dec_sub20_cry_in[1:0] 2'00
39135       attribute \src "libresoc.v:0.0-0.0"
39136       case 5'00011
39137         assign { } { }
39138         assign $1\dec31_dec_sub20_cry_in[1:0] 2'00
39139       attribute \src "libresoc.v:0.0-0.0"
39140       case 5'00000
39141         assign { } { }
39142         assign $1\dec31_dec_sub20_cry_in[1:0] 2'00
39143       attribute \src "libresoc.v:0.0-0.0"
39144       case 5'10100
39145         assign { } { }
39146         assign $1\dec31_dec_sub20_cry_in[1:0] 2'00
39147       case
39148         assign $1\dec31_dec_sub20_cry_in[1:0] 2'00
39149     end
39150     sync always
39151       update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0]
39152   end
39153   attribute \src "libresoc.v:26789.3-26813.6"
39154   process $proc$libresoc.v:26789$587
39155     assign { } { }
39156     assign { } { }
39157     assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0]
39158     attribute \src "libresoc.v:26790.5-26790.29"
39159     switch \initial
39160       attribute \src "libresoc.v:26790.9-26790.17"
39161       case 1'1
39162       case
39163     end
39164     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39165     switch \opcode_switch
39166       attribute \src "libresoc.v:0.0-0.0"
39167       case 5'00001
39168         assign { } { }
39169         assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101
39170       attribute \src "libresoc.v:0.0-0.0"
39171       case 5'00010
39172         assign { } { }
39173         assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011
39174       attribute \src "libresoc.v:0.0-0.0"
39175       case 5'10000
39176         assign { } { }
39177         assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100
39178       attribute \src "libresoc.v:0.0-0.0"
39179       case 5'00011
39180         assign { } { }
39181         assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001
39182       attribute \src "libresoc.v:0.0-0.0"
39183       case 5'00000
39184         assign { } { }
39185         assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011
39186       attribute \src "libresoc.v:0.0-0.0"
39187       case 5'10100
39188         assign { } { }
39189         assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101
39190       case
39191         assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000
39192     end
39193     sync always
39194       update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0]
39195   end
39196   attribute \src "libresoc.v:26814.3-26838.6"
39197   process $proc$libresoc.v:26814$588
39198     assign { } { }
39199     assign { } { }
39200     assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0]
39201     attribute \src "libresoc.v:26815.5-26815.29"
39202     switch \initial
39203       attribute \src "libresoc.v:26815.9-26815.17"
39204       case 1'1
39205       case
39206     end
39207     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39208     switch \opcode_switch
39209       attribute \src "libresoc.v:0.0-0.0"
39210       case 5'00001
39211         assign { } { }
39212         assign $1\dec31_dec_sub20_inv_a[0:0] 1'0
39213       attribute \src "libresoc.v:0.0-0.0"
39214       case 5'00010
39215         assign { } { }
39216         assign $1\dec31_dec_sub20_inv_a[0:0] 1'0
39217       attribute \src "libresoc.v:0.0-0.0"
39218       case 5'10000
39219         assign { } { }
39220         assign $1\dec31_dec_sub20_inv_a[0:0] 1'0
39221       attribute \src "libresoc.v:0.0-0.0"
39222       case 5'00011
39223         assign { } { }
39224         assign $1\dec31_dec_sub20_inv_a[0:0] 1'0
39225       attribute \src "libresoc.v:0.0-0.0"
39226       case 5'00000
39227         assign { } { }
39228         assign $1\dec31_dec_sub20_inv_a[0:0] 1'0
39229       attribute \src "libresoc.v:0.0-0.0"
39230       case 5'10100
39231         assign { } { }
39232         assign $1\dec31_dec_sub20_inv_a[0:0] 1'0
39233       case
39234         assign $1\dec31_dec_sub20_inv_a[0:0] 1'0
39235     end
39236     sync always
39237       update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0]
39238   end
39239   attribute \src "libresoc.v:26839.3-26863.6"
39240   process $proc$libresoc.v:26839$589
39241     assign { } { }
39242     assign { } { }
39243     assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0]
39244     attribute \src "libresoc.v:26840.5-26840.29"
39245     switch \initial
39246       attribute \src "libresoc.v:26840.9-26840.17"
39247       case 1'1
39248       case
39249     end
39250     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39251     switch \opcode_switch
39252       attribute \src "libresoc.v:0.0-0.0"
39253       case 5'00001
39254         assign { } { }
39255         assign $1\dec31_dec_sub20_inv_out[0:0] 1'0
39256       attribute \src "libresoc.v:0.0-0.0"
39257       case 5'00010
39258         assign { } { }
39259         assign $1\dec31_dec_sub20_inv_out[0:0] 1'0
39260       attribute \src "libresoc.v:0.0-0.0"
39261       case 5'10000
39262         assign { } { }
39263         assign $1\dec31_dec_sub20_inv_out[0:0] 1'0
39264       attribute \src "libresoc.v:0.0-0.0"
39265       case 5'00011
39266         assign { } { }
39267         assign $1\dec31_dec_sub20_inv_out[0:0] 1'0
39268       attribute \src "libresoc.v:0.0-0.0"
39269       case 5'00000
39270         assign { } { }
39271         assign $1\dec31_dec_sub20_inv_out[0:0] 1'0
39272       attribute \src "libresoc.v:0.0-0.0"
39273       case 5'10100
39274         assign { } { }
39275         assign $1\dec31_dec_sub20_inv_out[0:0] 1'0
39276       case
39277         assign $1\dec31_dec_sub20_inv_out[0:0] 1'0
39278     end
39279     sync always
39280       update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0]
39281   end
39282   attribute \src "libresoc.v:26864.3-26888.6"
39283   process $proc$libresoc.v:26864$590
39284     assign { } { }
39285     assign { } { }
39286     assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0]
39287     attribute \src "libresoc.v:26865.5-26865.29"
39288     switch \initial
39289       attribute \src "libresoc.v:26865.9-26865.17"
39290       case 1'1
39291       case
39292     end
39293     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39294     switch \opcode_switch
39295       attribute \src "libresoc.v:0.0-0.0"
39296       case 5'00001
39297         assign { } { }
39298         assign $1\dec31_dec_sub20_cry_out[0:0] 1'0
39299       attribute \src "libresoc.v:0.0-0.0"
39300       case 5'00010
39301         assign { } { }
39302         assign $1\dec31_dec_sub20_cry_out[0:0] 1'0
39303       attribute \src "libresoc.v:0.0-0.0"
39304       case 5'10000
39305         assign { } { }
39306         assign $1\dec31_dec_sub20_cry_out[0:0] 1'0
39307       attribute \src "libresoc.v:0.0-0.0"
39308       case 5'00011
39309         assign { } { }
39310         assign $1\dec31_dec_sub20_cry_out[0:0] 1'0
39311       attribute \src "libresoc.v:0.0-0.0"
39312       case 5'00000
39313         assign { } { }
39314         assign $1\dec31_dec_sub20_cry_out[0:0] 1'0
39315       attribute \src "libresoc.v:0.0-0.0"
39316       case 5'10100
39317         assign { } { }
39318         assign $1\dec31_dec_sub20_cry_out[0:0] 1'0
39319       case
39320         assign $1\dec31_dec_sub20_cry_out[0:0] 1'0
39321     end
39322     sync always
39323       update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0]
39324   end
39325   attribute \src "libresoc.v:26889.3-26913.6"
39326   process $proc$libresoc.v:26889$591
39327     assign { } { }
39328     assign { } { }
39329     assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0]
39330     attribute \src "libresoc.v:26890.5-26890.29"
39331     switch \initial
39332       attribute \src "libresoc.v:26890.9-26890.17"
39333       case 1'1
39334       case
39335     end
39336     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39337     switch \opcode_switch
39338       attribute \src "libresoc.v:0.0-0.0"
39339       case 5'00001
39340         assign { } { }
39341         assign $1\dec31_dec_sub20_br[0:0] 1'0
39342       attribute \src "libresoc.v:0.0-0.0"
39343       case 5'00010
39344         assign { } { }
39345         assign $1\dec31_dec_sub20_br[0:0] 1'0
39346       attribute \src "libresoc.v:0.0-0.0"
39347       case 5'10000
39348         assign { } { }
39349         assign $1\dec31_dec_sub20_br[0:0] 1'1
39350       attribute \src "libresoc.v:0.0-0.0"
39351       case 5'00011
39352         assign { } { }
39353         assign $1\dec31_dec_sub20_br[0:0] 1'0
39354       attribute \src "libresoc.v:0.0-0.0"
39355       case 5'00000
39356         assign { } { }
39357         assign $1\dec31_dec_sub20_br[0:0] 1'0
39358       attribute \src "libresoc.v:0.0-0.0"
39359       case 5'10100
39360         assign { } { }
39361         assign $1\dec31_dec_sub20_br[0:0] 1'1
39362       case
39363         assign $1\dec31_dec_sub20_br[0:0] 1'0
39364     end
39365     sync always
39366       update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0]
39367   end
39368   attribute \src "libresoc.v:26914.3-26938.6"
39369   process $proc$libresoc.v:26914$592
39370     assign { } { }
39371     assign { } { }
39372     assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0]
39373     attribute \src "libresoc.v:26915.5-26915.29"
39374     switch \initial
39375       attribute \src "libresoc.v:26915.9-26915.17"
39376       case 1'1
39377       case
39378     end
39379     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39380     switch \opcode_switch
39381       attribute \src "libresoc.v:0.0-0.0"
39382       case 5'00001
39383         assign { } { }
39384         assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0
39385       attribute \src "libresoc.v:0.0-0.0"
39386       case 5'00010
39387         assign { } { }
39388         assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0
39389       attribute \src "libresoc.v:0.0-0.0"
39390       case 5'10000
39391         assign { } { }
39392         assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0
39393       attribute \src "libresoc.v:0.0-0.0"
39394       case 5'00011
39395         assign { } { }
39396         assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0
39397       attribute \src "libresoc.v:0.0-0.0"
39398       case 5'00000
39399         assign { } { }
39400         assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0
39401       attribute \src "libresoc.v:0.0-0.0"
39402       case 5'10100
39403         assign { } { }
39404         assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0
39405       case
39406         assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0
39407     end
39408     sync always
39409       update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0]
39410   end
39411   attribute \src "libresoc.v:26939.3-26963.6"
39412   process $proc$libresoc.v:26939$593
39413     assign { } { }
39414     assign { } { }
39415     assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0]
39416     attribute \src "libresoc.v:26940.5-26940.29"
39417     switch \initial
39418       attribute \src "libresoc.v:26940.9-26940.17"
39419       case 1'1
39420       case
39421     end
39422     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39423     switch \opcode_switch
39424       attribute \src "libresoc.v:0.0-0.0"
39425       case 5'00001
39426         assign { } { }
39427         assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101
39428       attribute \src "libresoc.v:0.0-0.0"
39429       case 5'00010
39430         assign { } { }
39431         assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101
39432       attribute \src "libresoc.v:0.0-0.0"
39433       case 5'10000
39434         assign { } { }
39435         assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101
39436       attribute \src "libresoc.v:0.0-0.0"
39437       case 5'00011
39438         assign { } { }
39439         assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101
39440       attribute \src "libresoc.v:0.0-0.0"
39441       case 5'00000
39442         assign { } { }
39443         assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101
39444       attribute \src "libresoc.v:0.0-0.0"
39445       case 5'10100
39446         assign { } { }
39447         assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110
39448       case
39449         assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000
39450     end
39451     sync always
39452       update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0]
39453   end
39454   attribute \src "libresoc.v:26964.3-26988.6"
39455   process $proc$libresoc.v:26964$594
39456     assign { } { }
39457     assign { } { }
39458     assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0]
39459     attribute \src "libresoc.v:26965.5-26965.29"
39460     switch \initial
39461       attribute \src "libresoc.v:26965.9-26965.17"
39462       case 1'1
39463       case
39464     end
39465     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39466     switch \opcode_switch
39467       attribute \src "libresoc.v:0.0-0.0"
39468       case 5'00001
39469         assign { } { }
39470         assign $1\dec31_dec_sub20_rsrv[0:0] 1'1
39471       attribute \src "libresoc.v:0.0-0.0"
39472       case 5'00010
39473         assign { } { }
39474         assign $1\dec31_dec_sub20_rsrv[0:0] 1'1
39475       attribute \src "libresoc.v:0.0-0.0"
39476       case 5'10000
39477         assign { } { }
39478         assign $1\dec31_dec_sub20_rsrv[0:0] 1'0
39479       attribute \src "libresoc.v:0.0-0.0"
39480       case 5'00011
39481         assign { } { }
39482         assign $1\dec31_dec_sub20_rsrv[0:0] 1'1
39483       attribute \src "libresoc.v:0.0-0.0"
39484       case 5'00000
39485         assign { } { }
39486         assign $1\dec31_dec_sub20_rsrv[0:0] 1'1
39487       attribute \src "libresoc.v:0.0-0.0"
39488       case 5'10100
39489         assign { } { }
39490         assign $1\dec31_dec_sub20_rsrv[0:0] 1'0
39491       case
39492         assign $1\dec31_dec_sub20_rsrv[0:0] 1'0
39493     end
39494     sync always
39495       update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0]
39496   end
39497   attribute \src "libresoc.v:26989.3-27013.6"
39498   process $proc$libresoc.v:26989$595
39499     assign { } { }
39500     assign { } { }
39501     assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0]
39502     attribute \src "libresoc.v:26990.5-26990.29"
39503     switch \initial
39504       attribute \src "libresoc.v:26990.9-26990.17"
39505       case 1'1
39506       case
39507     end
39508     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39509     switch \opcode_switch
39510       attribute \src "libresoc.v:0.0-0.0"
39511       case 5'00001
39512         assign { } { }
39513         assign $1\dec31_dec_sub20_is_32b[0:0] 1'0
39514       attribute \src "libresoc.v:0.0-0.0"
39515       case 5'00010
39516         assign { } { }
39517         assign $1\dec31_dec_sub20_is_32b[0:0] 1'0
39518       attribute \src "libresoc.v:0.0-0.0"
39519       case 5'10000
39520         assign { } { }
39521         assign $1\dec31_dec_sub20_is_32b[0:0] 1'0
39522       attribute \src "libresoc.v:0.0-0.0"
39523       case 5'00011
39524         assign { } { }
39525         assign $1\dec31_dec_sub20_is_32b[0:0] 1'0
39526       attribute \src "libresoc.v:0.0-0.0"
39527       case 5'00000
39528         assign { } { }
39529         assign $1\dec31_dec_sub20_is_32b[0:0] 1'0
39530       attribute \src "libresoc.v:0.0-0.0"
39531       case 5'10100
39532         assign { } { }
39533         assign $1\dec31_dec_sub20_is_32b[0:0] 1'0
39534       case
39535         assign $1\dec31_dec_sub20_is_32b[0:0] 1'0
39536     end
39537     sync always
39538       update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0]
39539   end
39540   attribute \src "libresoc.v:27014.3-27038.6"
39541   process $proc$libresoc.v:27014$596
39542     assign { } { }
39543     assign { } { }
39544     assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0]
39545     attribute \src "libresoc.v:27015.5-27015.29"
39546     switch \initial
39547       attribute \src "libresoc.v:27015.9-27015.17"
39548       case 1'1
39549       case
39550     end
39551     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39552     switch \opcode_switch
39553       attribute \src "libresoc.v:0.0-0.0"
39554       case 5'00001
39555         assign { } { }
39556         assign $1\dec31_dec_sub20_sgn[0:0] 1'0
39557       attribute \src "libresoc.v:0.0-0.0"
39558       case 5'00010
39559         assign { } { }
39560         assign $1\dec31_dec_sub20_sgn[0:0] 1'0
39561       attribute \src "libresoc.v:0.0-0.0"
39562       case 5'10000
39563         assign { } { }
39564         assign $1\dec31_dec_sub20_sgn[0:0] 1'0
39565       attribute \src "libresoc.v:0.0-0.0"
39566       case 5'00011
39567         assign { } { }
39568         assign $1\dec31_dec_sub20_sgn[0:0] 1'0
39569       attribute \src "libresoc.v:0.0-0.0"
39570       case 5'00000
39571         assign { } { }
39572         assign $1\dec31_dec_sub20_sgn[0:0] 1'0
39573       attribute \src "libresoc.v:0.0-0.0"
39574       case 5'10100
39575         assign { } { }
39576         assign $1\dec31_dec_sub20_sgn[0:0] 1'0
39577       case
39578         assign $1\dec31_dec_sub20_sgn[0:0] 1'0
39579     end
39580     sync always
39581       update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0]
39582   end
39583   attribute \src "libresoc.v:27039.3-27063.6"
39584   process $proc$libresoc.v:27039$597
39585     assign { } { }
39586     assign { } { }
39587     assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0]
39588     attribute \src "libresoc.v:27040.5-27040.29"
39589     switch \initial
39590       attribute \src "libresoc.v:27040.9-27040.17"
39591       case 1'1
39592       case
39593     end
39594     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39595     switch \opcode_switch
39596       attribute \src "libresoc.v:0.0-0.0"
39597       case 5'00001
39598         assign { } { }
39599         assign $1\dec31_dec_sub20_lk[0:0] 1'0
39600       attribute \src "libresoc.v:0.0-0.0"
39601       case 5'00010
39602         assign { } { }
39603         assign $1\dec31_dec_sub20_lk[0:0] 1'0
39604       attribute \src "libresoc.v:0.0-0.0"
39605       case 5'10000
39606         assign { } { }
39607         assign $1\dec31_dec_sub20_lk[0:0] 1'0
39608       attribute \src "libresoc.v:0.0-0.0"
39609       case 5'00011
39610         assign { } { }
39611         assign $1\dec31_dec_sub20_lk[0:0] 1'0
39612       attribute \src "libresoc.v:0.0-0.0"
39613       case 5'00000
39614         assign { } { }
39615         assign $1\dec31_dec_sub20_lk[0:0] 1'0
39616       attribute \src "libresoc.v:0.0-0.0"
39617       case 5'10100
39618         assign { } { }
39619         assign $1\dec31_dec_sub20_lk[0:0] 1'0
39620       case
39621         assign $1\dec31_dec_sub20_lk[0:0] 1'0
39622     end
39623     sync always
39624       update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0]
39625   end
39626   attribute \src "libresoc.v:27064.3-27088.6"
39627   process $proc$libresoc.v:27064$598
39628     assign { } { }
39629     assign { } { }
39630     assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0]
39631     attribute \src "libresoc.v:27065.5-27065.29"
39632     switch \initial
39633       attribute \src "libresoc.v:27065.9-27065.17"
39634       case 1'1
39635       case
39636     end
39637     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39638     switch \opcode_switch
39639       attribute \src "libresoc.v:0.0-0.0"
39640       case 5'00001
39641         assign { } { }
39642         assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
39643       attribute \src "libresoc.v:0.0-0.0"
39644       case 5'00010
39645         assign { } { }
39646         assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
39647       attribute \src "libresoc.v:0.0-0.0"
39648       case 5'10000
39649         assign { } { }
39650         assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
39651       attribute \src "libresoc.v:0.0-0.0"
39652       case 5'00011
39653         assign { } { }
39654         assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
39655       attribute \src "libresoc.v:0.0-0.0"
39656       case 5'00000
39657         assign { } { }
39658         assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
39659       attribute \src "libresoc.v:0.0-0.0"
39660       case 5'10100
39661         assign { } { }
39662         assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1
39663       case
39664         assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0
39665     end
39666     sync always
39667       update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0]
39668   end
39669   attribute \src "libresoc.v:27089.3-27113.6"
39670   process $proc$libresoc.v:27089$599
39671     assign { } { }
39672     assign { } { }
39673     assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0]
39674     attribute \src "libresoc.v:27090.5-27090.29"
39675     switch \initial
39676       attribute \src "libresoc.v:27090.9-27090.17"
39677       case 1'1
39678       case
39679     end
39680     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39681     switch \opcode_switch
39682       attribute \src "libresoc.v:0.0-0.0"
39683       case 5'00001
39684         assign { } { }
39685         assign $1\dec31_dec_sub20_form[4:0] 5'01000
39686       attribute \src "libresoc.v:0.0-0.0"
39687       case 5'00010
39688         assign { } { }
39689         assign $1\dec31_dec_sub20_form[4:0] 5'01000
39690       attribute \src "libresoc.v:0.0-0.0"
39691       case 5'10000
39692         assign { } { }
39693         assign $1\dec31_dec_sub20_form[4:0] 5'01000
39694       attribute \src "libresoc.v:0.0-0.0"
39695       case 5'00011
39696         assign { } { }
39697         assign $1\dec31_dec_sub20_form[4:0] 5'01000
39698       attribute \src "libresoc.v:0.0-0.0"
39699       case 5'00000
39700         assign { } { }
39701         assign $1\dec31_dec_sub20_form[4:0] 5'01000
39702       attribute \src "libresoc.v:0.0-0.0"
39703       case 5'10100
39704         assign { } { }
39705         assign $1\dec31_dec_sub20_form[4:0] 5'01000
39706       case
39707         assign $1\dec31_dec_sub20_form[4:0] 5'00000
39708     end
39709     sync always
39710       update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0]
39711   end
39712   attribute \src "libresoc.v:27114.3-27138.6"
39713   process $proc$libresoc.v:27114$600
39714     assign { } { }
39715     assign { } { }
39716     assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0]
39717     attribute \src "libresoc.v:27115.5-27115.29"
39718     switch \initial
39719       attribute \src "libresoc.v:27115.9-27115.17"
39720       case 1'1
39721       case
39722     end
39723     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39724     switch \opcode_switch
39725       attribute \src "libresoc.v:0.0-0.0"
39726       case 5'00001
39727         assign { } { }
39728         assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
39729       attribute \src "libresoc.v:0.0-0.0"
39730       case 5'00010
39731         assign { } { }
39732         assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
39733       attribute \src "libresoc.v:0.0-0.0"
39734       case 5'10000
39735         assign { } { }
39736         assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
39737       attribute \src "libresoc.v:0.0-0.0"
39738       case 5'00011
39739         assign { } { }
39740         assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
39741       attribute \src "libresoc.v:0.0-0.0"
39742       case 5'00000
39743         assign { } { }
39744         assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
39745       attribute \src "libresoc.v:0.0-0.0"
39746       case 5'10100
39747         assign { } { }
39748         assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010
39749       case
39750         assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000
39751     end
39752     sync always
39753       update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0]
39754   end
39755   attribute \src "libresoc.v:27139.3-27163.6"
39756   process $proc$libresoc.v:27139$601
39757     assign { } { }
39758     assign { } { }
39759     assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0]
39760     attribute \src "libresoc.v:27140.5-27140.29"
39761     switch \initial
39762       attribute \src "libresoc.v:27140.9-27140.17"
39763       case 1'1
39764       case
39765     end
39766     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39767     switch \opcode_switch
39768       attribute \src "libresoc.v:0.0-0.0"
39769       case 5'00001
39770         assign { } { }
39771         assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
39772       attribute \src "libresoc.v:0.0-0.0"
39773       case 5'00010
39774         assign { } { }
39775         assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
39776       attribute \src "libresoc.v:0.0-0.0"
39777       case 5'10000
39778         assign { } { }
39779         assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
39780       attribute \src "libresoc.v:0.0-0.0"
39781       case 5'00011
39782         assign { } { }
39783         assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
39784       attribute \src "libresoc.v:0.0-0.0"
39785       case 5'00000
39786         assign { } { }
39787         assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
39788       attribute \src "libresoc.v:0.0-0.0"
39789       case 5'10100
39790         assign { } { }
39791         assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001
39792       case
39793         assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000
39794     end
39795     sync always
39796       update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0]
39797   end
39798   attribute \src "libresoc.v:27164.3-27188.6"
39799   process $proc$libresoc.v:27164$602
39800     assign { } { }
39801     assign { } { }
39802     assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0]
39803     attribute \src "libresoc.v:27165.5-27165.29"
39804     switch \initial
39805       attribute \src "libresoc.v:27165.9-27165.17"
39806       case 1'1
39807       case
39808     end
39809     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39810     switch \opcode_switch
39811       attribute \src "libresoc.v:0.0-0.0"
39812       case 5'00001
39813         assign { } { }
39814         assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
39815       attribute \src "libresoc.v:0.0-0.0"
39816       case 5'00010
39817         assign { } { }
39818         assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
39819       attribute \src "libresoc.v:0.0-0.0"
39820       case 5'10000
39821         assign { } { }
39822         assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
39823       attribute \src "libresoc.v:0.0-0.0"
39824       case 5'00011
39825         assign { } { }
39826         assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
39827       attribute \src "libresoc.v:0.0-0.0"
39828       case 5'00000
39829         assign { } { }
39830         assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
39831       attribute \src "libresoc.v:0.0-0.0"
39832       case 5'10100
39833         assign { } { }
39834         assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01
39835       case
39836         assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00
39837     end
39838     sync always
39839       update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0]
39840   end
39841   attribute \src "libresoc.v:27189.3-27213.6"
39842   process $proc$libresoc.v:27189$603
39843     assign { } { }
39844     assign { } { }
39845     assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0]
39846     attribute \src "libresoc.v:27190.5-27190.29"
39847     switch \initial
39848       attribute \src "libresoc.v:27190.9-27190.17"
39849       case 1'1
39850       case
39851     end
39852     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39853     switch \opcode_switch
39854       attribute \src "libresoc.v:0.0-0.0"
39855       case 5'00001
39856         assign { } { }
39857         assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
39858       attribute \src "libresoc.v:0.0-0.0"
39859       case 5'00010
39860         assign { } { }
39861         assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
39862       attribute \src "libresoc.v:0.0-0.0"
39863       case 5'10000
39864         assign { } { }
39865         assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
39866       attribute \src "libresoc.v:0.0-0.0"
39867       case 5'00011
39868         assign { } { }
39869         assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
39870       attribute \src "libresoc.v:0.0-0.0"
39871       case 5'00000
39872         assign { } { }
39873         assign $1\dec31_dec_sub20_out_sel[1:0] 2'01
39874       attribute \src "libresoc.v:0.0-0.0"
39875       case 5'10100
39876         assign { } { }
39877         assign $1\dec31_dec_sub20_out_sel[1:0] 2'00
39878       case
39879         assign $1\dec31_dec_sub20_out_sel[1:0] 2'00
39880     end
39881     sync always
39882       update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0]
39883   end
39884   attribute \src "libresoc.v:27214.3-27238.6"
39885   process $proc$libresoc.v:27214$604
39886     assign { } { }
39887     assign { } { }
39888     assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0]
39889     attribute \src "libresoc.v:27215.5-27215.29"
39890     switch \initial
39891       attribute \src "libresoc.v:27215.9-27215.17"
39892       case 1'1
39893       case
39894     end
39895     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39896     switch \opcode_switch
39897       attribute \src "libresoc.v:0.0-0.0"
39898       case 5'00001
39899         assign { } { }
39900         assign $1\dec31_dec_sub20_cr_in[2:0] 3'000
39901       attribute \src "libresoc.v:0.0-0.0"
39902       case 5'00010
39903         assign { } { }
39904         assign $1\dec31_dec_sub20_cr_in[2:0] 3'000
39905       attribute \src "libresoc.v:0.0-0.0"
39906       case 5'10000
39907         assign { } { }
39908         assign $1\dec31_dec_sub20_cr_in[2:0] 3'000
39909       attribute \src "libresoc.v:0.0-0.0"
39910       case 5'00011
39911         assign { } { }
39912         assign $1\dec31_dec_sub20_cr_in[2:0] 3'000
39913       attribute \src "libresoc.v:0.0-0.0"
39914       case 5'00000
39915         assign { } { }
39916         assign $1\dec31_dec_sub20_cr_in[2:0] 3'000
39917       attribute \src "libresoc.v:0.0-0.0"
39918       case 5'10100
39919         assign { } { }
39920         assign $1\dec31_dec_sub20_cr_in[2:0] 3'000
39921       case
39922         assign $1\dec31_dec_sub20_cr_in[2:0] 3'000
39923     end
39924     sync always
39925       update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0]
39926   end
39927   attribute \src "libresoc.v:27239.3-27263.6"
39928   process $proc$libresoc.v:27239$605
39929     assign { } { }
39930     assign { } { }
39931     assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0]
39932     attribute \src "libresoc.v:27240.5-27240.29"
39933     switch \initial
39934       attribute \src "libresoc.v:27240.9-27240.17"
39935       case 1'1
39936       case
39937     end
39938     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
39939     switch \opcode_switch
39940       attribute \src "libresoc.v:0.0-0.0"
39941       case 5'00001
39942         assign { } { }
39943         assign $1\dec31_dec_sub20_cr_out[2:0] 3'000
39944       attribute \src "libresoc.v:0.0-0.0"
39945       case 5'00010
39946         assign { } { }
39947         assign $1\dec31_dec_sub20_cr_out[2:0] 3'000
39948       attribute \src "libresoc.v:0.0-0.0"
39949       case 5'10000
39950         assign { } { }
39951         assign $1\dec31_dec_sub20_cr_out[2:0] 3'000
39952       attribute \src "libresoc.v:0.0-0.0"
39953       case 5'00011
39954         assign { } { }
39955         assign $1\dec31_dec_sub20_cr_out[2:0] 3'000
39956       attribute \src "libresoc.v:0.0-0.0"
39957       case 5'00000
39958         assign { } { }
39959         assign $1\dec31_dec_sub20_cr_out[2:0] 3'000
39960       attribute \src "libresoc.v:0.0-0.0"
39961       case 5'10100
39962         assign { } { }
39963         assign $1\dec31_dec_sub20_cr_out[2:0] 3'000
39964       case
39965         assign $1\dec31_dec_sub20_cr_out[2:0] 3'000
39966     end
39967     sync always
39968       update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0]
39969   end
39970   connect \opcode_switch \opcode_in [10:6]
39971 end
39972 attribute \src "libresoc.v:27269.1-28686.10"
39973 attribute \cells_not_processed 1
39974 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21"
39975 attribute \generator "nMigen"
39976 module \dec31_dec_sub21
39977   attribute \src "libresoc.v:28311.3-28341.6"
39978   wire width 8 $0\dec31_dec_sub21_asmcode[7:0]
39979   attribute \src "libresoc.v:27919.3-27967.6"
39980   wire $0\dec31_dec_sub21_br[0:0]
39981   attribute \src "libresoc.v:28587.3-28635.6"
39982   wire width 3 $0\dec31_dec_sub21_cr_in[2:0]
39983   attribute \src "libresoc.v:28636.3-28684.6"
39984   wire width 3 $0\dec31_dec_sub21_cr_out[2:0]
39985   attribute \src "libresoc.v:27723.3-27771.6"
39986   wire width 2 $0\dec31_dec_sub21_cry_in[1:0]
39987   attribute \src "libresoc.v:27870.3-27918.6"
39988   wire $0\dec31_dec_sub21_cry_out[0:0]
39989   attribute \src "libresoc.v:28342.3-28390.6"
39990   wire width 5 $0\dec31_dec_sub21_form[4:0]
39991   attribute \src "libresoc.v:27527.3-27575.6"
39992   wire width 12 $0\dec31_dec_sub21_function_unit[11:0]
39993   attribute \src "libresoc.v:28391.3-28439.6"
39994   wire width 3 $0\dec31_dec_sub21_in1_sel[2:0]
39995   attribute \src "libresoc.v:28440.3-28488.6"
39996   wire width 4 $0\dec31_dec_sub21_in2_sel[3:0]
39997   attribute \src "libresoc.v:28489.3-28537.6"
39998   wire width 2 $0\dec31_dec_sub21_in3_sel[1:0]
39999   attribute \src "libresoc.v:28066.3-28114.6"
40000   wire width 7 $0\dec31_dec_sub21_internal_op[6:0]
40001   attribute \src "libresoc.v:27772.3-27820.6"
40002   wire $0\dec31_dec_sub21_inv_a[0:0]
40003   attribute \src "libresoc.v:27821.3-27869.6"
40004   wire $0\dec31_dec_sub21_inv_out[0:0]
40005   attribute \src "libresoc.v:28115.3-28163.6"
40006   wire $0\dec31_dec_sub21_is_32b[0:0]
40007   attribute \src "libresoc.v:27576.3-27624.6"
40008   wire width 4 $0\dec31_dec_sub21_ldst_len[3:0]
40009   attribute \src "libresoc.v:28213.3-28261.6"
40010   wire $0\dec31_dec_sub21_lk[0:0]
40011   attribute \src "libresoc.v:28538.3-28586.6"
40012   wire width 2 $0\dec31_dec_sub21_out_sel[1:0]
40013   attribute \src "libresoc.v:27674.3-27722.6"
40014   wire width 2 $0\dec31_dec_sub21_rc_sel[1:0]
40015   attribute \src "libresoc.v:28017.3-28065.6"
40016   wire $0\dec31_dec_sub21_rsrv[0:0]
40017   attribute \src "libresoc.v:28262.3-28310.6"
40018   wire $0\dec31_dec_sub21_sgl_pipe[0:0]
40019   attribute \src "libresoc.v:28164.3-28212.6"
40020   wire $0\dec31_dec_sub21_sgn[0:0]
40021   attribute \src "libresoc.v:27968.3-28016.6"
40022   wire $0\dec31_dec_sub21_sgn_ext[0:0]
40023   attribute \src "libresoc.v:27625.3-27673.6"
40024   wire width 2 $0\dec31_dec_sub21_upd[1:0]
40025   attribute \src "libresoc.v:27270.7-27270.20"
40026   wire $0\initial[0:0]
40027   attribute \src "libresoc.v:28311.3-28341.6"
40028   wire width 8 $1\dec31_dec_sub21_asmcode[7:0]
40029   attribute \src "libresoc.v:27919.3-27967.6"
40030   wire $1\dec31_dec_sub21_br[0:0]
40031   attribute \src "libresoc.v:28587.3-28635.6"
40032   wire width 3 $1\dec31_dec_sub21_cr_in[2:0]
40033   attribute \src "libresoc.v:28636.3-28684.6"
40034   wire width 3 $1\dec31_dec_sub21_cr_out[2:0]
40035   attribute \src "libresoc.v:27723.3-27771.6"
40036   wire width 2 $1\dec31_dec_sub21_cry_in[1:0]
40037   attribute \src "libresoc.v:27870.3-27918.6"
40038   wire $1\dec31_dec_sub21_cry_out[0:0]
40039   attribute \src "libresoc.v:28342.3-28390.6"
40040   wire width 5 $1\dec31_dec_sub21_form[4:0]
40041   attribute \src "libresoc.v:27527.3-27575.6"
40042   wire width 12 $1\dec31_dec_sub21_function_unit[11:0]
40043   attribute \src "libresoc.v:28391.3-28439.6"
40044   wire width 3 $1\dec31_dec_sub21_in1_sel[2:0]
40045   attribute \src "libresoc.v:28440.3-28488.6"
40046   wire width 4 $1\dec31_dec_sub21_in2_sel[3:0]
40047   attribute \src "libresoc.v:28489.3-28537.6"
40048   wire width 2 $1\dec31_dec_sub21_in3_sel[1:0]
40049   attribute \src "libresoc.v:28066.3-28114.6"
40050   wire width 7 $1\dec31_dec_sub21_internal_op[6:0]
40051   attribute \src "libresoc.v:27772.3-27820.6"
40052   wire $1\dec31_dec_sub21_inv_a[0:0]
40053   attribute \src "libresoc.v:27821.3-27869.6"
40054   wire $1\dec31_dec_sub21_inv_out[0:0]
40055   attribute \src "libresoc.v:28115.3-28163.6"
40056   wire $1\dec31_dec_sub21_is_32b[0:0]
40057   attribute \src "libresoc.v:27576.3-27624.6"
40058   wire width 4 $1\dec31_dec_sub21_ldst_len[3:0]
40059   attribute \src "libresoc.v:28213.3-28261.6"
40060   wire $1\dec31_dec_sub21_lk[0:0]
40061   attribute \src "libresoc.v:28538.3-28586.6"
40062   wire width 2 $1\dec31_dec_sub21_out_sel[1:0]
40063   attribute \src "libresoc.v:27674.3-27722.6"
40064   wire width 2 $1\dec31_dec_sub21_rc_sel[1:0]
40065   attribute \src "libresoc.v:28017.3-28065.6"
40066   wire $1\dec31_dec_sub21_rsrv[0:0]
40067   attribute \src "libresoc.v:28262.3-28310.6"
40068   wire $1\dec31_dec_sub21_sgl_pipe[0:0]
40069   attribute \src "libresoc.v:28164.3-28212.6"
40070   wire $1\dec31_dec_sub21_sgn[0:0]
40071   attribute \src "libresoc.v:27968.3-28016.6"
40072   wire $1\dec31_dec_sub21_sgn_ext[0:0]
40073   attribute \src "libresoc.v:27625.3-27673.6"
40074   wire width 2 $1\dec31_dec_sub21_upd[1:0]
40075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40076   wire width 8 output 4 \dec31_dec_sub21_asmcode
40077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40078   wire output 18 \dec31_dec_sub21_br
40079   attribute \enum_base_type "CRInSel"
40080   attribute \enum_value_000 "NONE"
40081   attribute \enum_value_001 "CR0"
40082   attribute \enum_value_010 "BI"
40083   attribute \enum_value_011 "BFA"
40084   attribute \enum_value_100 "BA_BB"
40085   attribute \enum_value_101 "BC"
40086   attribute \enum_value_110 "WHOLE_REG"
40087   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40088   wire width 3 output 9 \dec31_dec_sub21_cr_in
40089   attribute \enum_base_type "CROutSel"
40090   attribute \enum_value_000 "NONE"
40091   attribute \enum_value_001 "CR0"
40092   attribute \enum_value_010 "BF"
40093   attribute \enum_value_011 "BT"
40094   attribute \enum_value_100 "WHOLE_REG"
40095   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40096   wire width 3 output 10 \dec31_dec_sub21_cr_out
40097   attribute \enum_base_type "CryIn"
40098   attribute \enum_value_00 "ZERO"
40099   attribute \enum_value_01 "ONE"
40100   attribute \enum_value_10 "CA"
40101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40102   wire width 2 output 14 \dec31_dec_sub21_cry_in
40103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40104   wire output 17 \dec31_dec_sub21_cry_out
40105   attribute \enum_base_type "Form"
40106   attribute \enum_value_00000 "NONE"
40107   attribute \enum_value_00001 "I"
40108   attribute \enum_value_00010 "B"
40109   attribute \enum_value_00011 "SC"
40110   attribute \enum_value_00100 "D"
40111   attribute \enum_value_00101 "DS"
40112   attribute \enum_value_00110 "DQ"
40113   attribute \enum_value_00111 "DX"
40114   attribute \enum_value_01000 "X"
40115   attribute \enum_value_01001 "XL"
40116   attribute \enum_value_01010 "XFX"
40117   attribute \enum_value_01011 "XFL"
40118   attribute \enum_value_01100 "XX1"
40119   attribute \enum_value_01101 "XX2"
40120   attribute \enum_value_01110 "XX3"
40121   attribute \enum_value_01111 "XX4"
40122   attribute \enum_value_10000 "XS"
40123   attribute \enum_value_10001 "XO"
40124   attribute \enum_value_10010 "A"
40125   attribute \enum_value_10011 "M"
40126   attribute \enum_value_10100 "MD"
40127   attribute \enum_value_10101 "MDS"
40128   attribute \enum_value_10110 "VA"
40129   attribute \enum_value_10111 "VC"
40130   attribute \enum_value_11000 "VX"
40131   attribute \enum_value_11001 "EVX"
40132   attribute \enum_value_11010 "EVS"
40133   attribute \enum_value_11011 "Z22"
40134   attribute \enum_value_11100 "Z23"
40135   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40136   wire width 5 output 3 \dec31_dec_sub21_form
40137   attribute \enum_base_type "Function"
40138   attribute \enum_value_000000000000 "NONE"
40139   attribute \enum_value_000000000010 "ALU"
40140   attribute \enum_value_000000000100 "LDST"
40141   attribute \enum_value_000000001000 "SHIFT_ROT"
40142   attribute \enum_value_000000010000 "LOGICAL"
40143   attribute \enum_value_000000100000 "BRANCH"
40144   attribute \enum_value_000001000000 "CR"
40145   attribute \enum_value_000010000000 "TRAP"
40146   attribute \enum_value_000100000000 "MUL"
40147   attribute \enum_value_001000000000 "DIV"
40148   attribute \enum_value_010000000000 "SPR"
40149   attribute \enum_value_100000000000 "MMU"
40150   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40151   wire width 12 output 1 \dec31_dec_sub21_function_unit
40152   attribute \enum_base_type "In1Sel"
40153   attribute \enum_value_000 "NONE"
40154   attribute \enum_value_001 "RA"
40155   attribute \enum_value_010 "RA_OR_ZERO"
40156   attribute \enum_value_011 "SPR"
40157   attribute \enum_value_100 "RS"
40158   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40159   wire width 3 output 5 \dec31_dec_sub21_in1_sel
40160   attribute \enum_base_type "In2Sel"
40161   attribute \enum_value_0000 "NONE"
40162   attribute \enum_value_0001 "RB"
40163   attribute \enum_value_0010 "CONST_UI"
40164   attribute \enum_value_0011 "CONST_SI"
40165   attribute \enum_value_0100 "CONST_UI_HI"
40166   attribute \enum_value_0101 "CONST_SI_HI"
40167   attribute \enum_value_0110 "CONST_LI"
40168   attribute \enum_value_0111 "CONST_BD"
40169   attribute \enum_value_1000 "CONST_DS"
40170   attribute \enum_value_1001 "CONST_M1"
40171   attribute \enum_value_1010 "CONST_SH"
40172   attribute \enum_value_1011 "CONST_SH32"
40173   attribute \enum_value_1100 "SPR"
40174   attribute \enum_value_1101 "RS"
40175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40176   wire width 4 output 6 \dec31_dec_sub21_in2_sel
40177   attribute \enum_base_type "In3Sel"
40178   attribute \enum_value_00 "NONE"
40179   attribute \enum_value_01 "RS"
40180   attribute \enum_value_10 "RB"
40181   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40182   wire width 2 output 7 \dec31_dec_sub21_in3_sel
40183   attribute \enum_base_type "MicrOp"
40184   attribute \enum_value_0000000 "OP_ILLEGAL"
40185   attribute \enum_value_0000001 "OP_NOP"
40186   attribute \enum_value_0000010 "OP_ADD"
40187   attribute \enum_value_0000011 "OP_ADDPCIS"
40188   attribute \enum_value_0000100 "OP_AND"
40189   attribute \enum_value_0000101 "OP_ATTN"
40190   attribute \enum_value_0000110 "OP_B"
40191   attribute \enum_value_0000111 "OP_BC"
40192   attribute \enum_value_0001000 "OP_BCREG"
40193   attribute \enum_value_0001001 "OP_BPERM"
40194   attribute \enum_value_0001010 "OP_CMP"
40195   attribute \enum_value_0001011 "OP_CMPB"
40196   attribute \enum_value_0001100 "OP_CMPEQB"
40197   attribute \enum_value_0001101 "OP_CMPRB"
40198   attribute \enum_value_0001110 "OP_CNTZ"
40199   attribute \enum_value_0001111 "OP_CRAND"
40200   attribute \enum_value_0010000 "OP_CRANDC"
40201   attribute \enum_value_0010001 "OP_CREQV"
40202   attribute \enum_value_0010010 "OP_CRNAND"
40203   attribute \enum_value_0010011 "OP_CRNOR"
40204   attribute \enum_value_0010100 "OP_CROR"
40205   attribute \enum_value_0010101 "OP_CRORC"
40206   attribute \enum_value_0010110 "OP_CRXOR"
40207   attribute \enum_value_0010111 "OP_DARN"
40208   attribute \enum_value_0011000 "OP_DCBF"
40209   attribute \enum_value_0011001 "OP_DCBST"
40210   attribute \enum_value_0011010 "OP_DCBT"
40211   attribute \enum_value_0011011 "OP_DCBTST"
40212   attribute \enum_value_0011100 "OP_DCBZ"
40213   attribute \enum_value_0011101 "OP_DIV"
40214   attribute \enum_value_0011110 "OP_DIVE"
40215   attribute \enum_value_0011111 "OP_EXTS"
40216   attribute \enum_value_0100000 "OP_EXTSWSLI"
40217   attribute \enum_value_0100001 "OP_ICBI"
40218   attribute \enum_value_0100010 "OP_ICBT"
40219   attribute \enum_value_0100011 "OP_ISEL"
40220   attribute \enum_value_0100100 "OP_ISYNC"
40221   attribute \enum_value_0100101 "OP_LOAD"
40222   attribute \enum_value_0100110 "OP_STORE"
40223   attribute \enum_value_0100111 "OP_MADDHD"
40224   attribute \enum_value_0101000 "OP_MADDHDU"
40225   attribute \enum_value_0101001 "OP_MADDLD"
40226   attribute \enum_value_0101010 "OP_MCRF"
40227   attribute \enum_value_0101011 "OP_MCRXR"
40228   attribute \enum_value_0101100 "OP_MCRXRX"
40229   attribute \enum_value_0101101 "OP_MFCR"
40230   attribute \enum_value_0101110 "OP_MFSPR"
40231   attribute \enum_value_0101111 "OP_MOD"
40232   attribute \enum_value_0110000 "OP_MTCRF"
40233   attribute \enum_value_0110001 "OP_MTSPR"
40234   attribute \enum_value_0110010 "OP_MUL_L64"
40235   attribute \enum_value_0110011 "OP_MUL_H64"
40236   attribute \enum_value_0110100 "OP_MUL_H32"
40237   attribute \enum_value_0110101 "OP_OR"
40238   attribute \enum_value_0110110 "OP_POPCNT"
40239   attribute \enum_value_0110111 "OP_PRTY"
40240   attribute \enum_value_0111000 "OP_RLC"
40241   attribute \enum_value_0111001 "OP_RLCL"
40242   attribute \enum_value_0111010 "OP_RLCR"
40243   attribute \enum_value_0111011 "OP_SETB"
40244   attribute \enum_value_0111100 "OP_SHL"
40245   attribute \enum_value_0111101 "OP_SHR"
40246   attribute \enum_value_0111110 "OP_SYNC"
40247   attribute \enum_value_0111111 "OP_TRAP"
40248   attribute \enum_value_1000011 "OP_XOR"
40249   attribute \enum_value_1000100 "OP_SIM_CONFIG"
40250   attribute \enum_value_1000101 "OP_CROP"
40251   attribute \enum_value_1000110 "OP_RFID"
40252   attribute \enum_value_1000111 "OP_MFMSR"
40253   attribute \enum_value_1001000 "OP_MTMSRD"
40254   attribute \enum_value_1001001 "OP_SC"
40255   attribute \enum_value_1001010 "OP_MTMSR"
40256   attribute \enum_value_1001011 "OP_TLBIE"
40257   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40258   wire width 7 output 2 \dec31_dec_sub21_internal_op
40259   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40260   wire output 15 \dec31_dec_sub21_inv_a
40261   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40262   wire output 16 \dec31_dec_sub21_inv_out
40263   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40264   wire output 21 \dec31_dec_sub21_is_32b
40265   attribute \enum_base_type "LdstLen"
40266   attribute \enum_value_0000 "NONE"
40267   attribute \enum_value_0001 "is1B"
40268   attribute \enum_value_0010 "is2B"
40269   attribute \enum_value_0100 "is4B"
40270   attribute \enum_value_1000 "is8B"
40271   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40272   wire width 4 output 11 \dec31_dec_sub21_ldst_len
40273   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40274   wire output 23 \dec31_dec_sub21_lk
40275   attribute \enum_base_type "OutSel"
40276   attribute \enum_value_00 "NONE"
40277   attribute \enum_value_01 "RT"
40278   attribute \enum_value_10 "RA"
40279   attribute \enum_value_11 "SPR"
40280   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40281   wire width 2 output 8 \dec31_dec_sub21_out_sel
40282   attribute \enum_base_type "RC"
40283   attribute \enum_value_00 "NONE"
40284   attribute \enum_value_01 "ONE"
40285   attribute \enum_value_10 "RC"
40286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40287   wire width 2 output 13 \dec31_dec_sub21_rc_sel
40288   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40289   wire output 20 \dec31_dec_sub21_rsrv
40290   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40291   wire output 24 \dec31_dec_sub21_sgl_pipe
40292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40293   wire output 22 \dec31_dec_sub21_sgn
40294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
40295   wire output 19 \dec31_dec_sub21_sgn_ext
40296   attribute \enum_base_type "LDSTMode"
40297   attribute \enum_value_00 "NONE"
40298   attribute \enum_value_01 "update"
40299   attribute \enum_value_10 "cix"
40300   attribute \enum_value_11 "cx"
40301   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
40302   wire width 2 output 12 \dec31_dec_sub21_upd
40303   attribute \src "libresoc.v:27270.7-27270.15"
40304   wire \initial
40305   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
40306   wire width 32 input 25 \opcode_in
40307   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
40308   wire width 5 \opcode_switch
40309   attribute \src "libresoc.v:27270.7-27270.20"
40310   process $proc$libresoc.v:27270$631
40311     assign { } { }
40312     assign $0\initial[0:0] 1'0
40313     sync always
40314       update \initial $0\initial[0:0]
40315     sync init
40316   end
40317   attribute \src "libresoc.v:27527.3-27575.6"
40318   process $proc$libresoc.v:27527$607
40319     assign { } { }
40320     assign { } { }
40321     assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0]
40322     attribute \src "libresoc.v:27528.5-27528.29"
40323     switch \initial
40324       attribute \src "libresoc.v:27528.9-27528.17"
40325       case 1'1
40326       case
40327     end
40328     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40329     switch \opcode_switch
40330       attribute \src "libresoc.v:0.0-0.0"
40331       case 5'11010
40332         assign { } { }
40333         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40334       attribute \src "libresoc.v:0.0-0.0"
40335       case 5'11011
40336         assign { } { }
40337         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40338       attribute \src "libresoc.v:0.0-0.0"
40339       case 5'00001
40340         assign { } { }
40341         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40342       attribute \src "libresoc.v:0.0-0.0"
40343       case 5'00000
40344         assign { } { }
40345         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40346       attribute \src "libresoc.v:0.0-0.0"
40347       case 5'11001
40348         assign { } { }
40349         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40350       attribute \src "libresoc.v:0.0-0.0"
40351       case 5'01011
40352         assign { } { }
40353         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40354       attribute \src "libresoc.v:0.0-0.0"
40355       case 5'01010
40356         assign { } { }
40357         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40358       attribute \src "libresoc.v:0.0-0.0"
40359       case 5'11000
40360         assign { } { }
40361         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40362       attribute \src "libresoc.v:0.0-0.0"
40363       case 5'11110
40364         assign { } { }
40365         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40366       attribute \src "libresoc.v:0.0-0.0"
40367       case 5'11111
40368         assign { } { }
40369         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40370       attribute \src "libresoc.v:0.0-0.0"
40371       case 5'00101
40372         assign { } { }
40373         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40374       attribute \src "libresoc.v:0.0-0.0"
40375       case 5'00100
40376         assign { } { }
40377         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40378       attribute \src "libresoc.v:0.0-0.0"
40379       case 5'11101
40380         assign { } { }
40381         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40382       attribute \src "libresoc.v:0.0-0.0"
40383       case 5'11100
40384         assign { } { }
40385         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100
40386       case
40387         assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000
40388     end
40389     sync always
40390       update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0]
40391   end
40392   attribute \src "libresoc.v:27576.3-27624.6"
40393   process $proc$libresoc.v:27576$608
40394     assign { } { }
40395     assign { } { }
40396     assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0]
40397     attribute \src "libresoc.v:27577.5-27577.29"
40398     switch \initial
40399       attribute \src "libresoc.v:27577.9-27577.17"
40400       case 1'1
40401       case
40402     end
40403     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40404     switch \opcode_switch
40405       attribute \src "libresoc.v:0.0-0.0"
40406       case 5'11010
40407         assign { } { }
40408         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001
40409       attribute \src "libresoc.v:0.0-0.0"
40410       case 5'11011
40411         assign { } { }
40412         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000
40413       attribute \src "libresoc.v:0.0-0.0"
40414       case 5'00001
40415         assign { } { }
40416         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000
40417       attribute \src "libresoc.v:0.0-0.0"
40418       case 5'00000
40419         assign { } { }
40420         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000
40421       attribute \src "libresoc.v:0.0-0.0"
40422       case 5'11001
40423         assign { } { }
40424         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010
40425       attribute \src "libresoc.v:0.0-0.0"
40426       case 5'01011
40427         assign { } { }
40428         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100
40429       attribute \src "libresoc.v:0.0-0.0"
40430       case 5'01010
40431         assign { } { }
40432         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100
40433       attribute \src "libresoc.v:0.0-0.0"
40434       case 5'11000
40435         assign { } { }
40436         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100
40437       attribute \src "libresoc.v:0.0-0.0"
40438       case 5'11110
40439         assign { } { }
40440         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001
40441       attribute \src "libresoc.v:0.0-0.0"
40442       case 5'11111
40443         assign { } { }
40444         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000
40445       attribute \src "libresoc.v:0.0-0.0"
40446       case 5'00101
40447         assign { } { }
40448         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000
40449       attribute \src "libresoc.v:0.0-0.0"
40450       case 5'00100
40451         assign { } { }
40452         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000
40453       attribute \src "libresoc.v:0.0-0.0"
40454       case 5'11101
40455         assign { } { }
40456         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010
40457       attribute \src "libresoc.v:0.0-0.0"
40458       case 5'11100
40459         assign { } { }
40460         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100
40461       case
40462         assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000
40463     end
40464     sync always
40465       update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0]
40466   end
40467   attribute \src "libresoc.v:27625.3-27673.6"
40468   process $proc$libresoc.v:27625$609
40469     assign { } { }
40470     assign { } { }
40471     assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0]
40472     attribute \src "libresoc.v:27626.5-27626.29"
40473     switch \initial
40474       attribute \src "libresoc.v:27626.9-27626.17"
40475       case 1'1
40476       case
40477     end
40478     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40479     switch \opcode_switch
40480       attribute \src "libresoc.v:0.0-0.0"
40481       case 5'11010
40482         assign { } { }
40483         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40484       attribute \src "libresoc.v:0.0-0.0"
40485       case 5'11011
40486         assign { } { }
40487         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40488       attribute \src "libresoc.v:0.0-0.0"
40489       case 5'00001
40490         assign { } { }
40491         assign $1\dec31_dec_sub21_upd[1:0] 2'01
40492       attribute \src "libresoc.v:0.0-0.0"
40493       case 5'00000
40494         assign { } { }
40495         assign $1\dec31_dec_sub21_upd[1:0] 2'00
40496       attribute \src "libresoc.v:0.0-0.0"
40497       case 5'11001
40498         assign { } { }
40499         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40500       attribute \src "libresoc.v:0.0-0.0"
40501       case 5'01011
40502         assign { } { }
40503         assign $1\dec31_dec_sub21_upd[1:0] 2'01
40504       attribute \src "libresoc.v:0.0-0.0"
40505       case 5'01010
40506         assign { } { }
40507         assign $1\dec31_dec_sub21_upd[1:0] 2'00
40508       attribute \src "libresoc.v:0.0-0.0"
40509       case 5'11000
40510         assign { } { }
40511         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40512       attribute \src "libresoc.v:0.0-0.0"
40513       case 5'11110
40514         assign { } { }
40515         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40516       attribute \src "libresoc.v:0.0-0.0"
40517       case 5'11111
40518         assign { } { }
40519         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40520       attribute \src "libresoc.v:0.0-0.0"
40521       case 5'00101
40522         assign { } { }
40523         assign $1\dec31_dec_sub21_upd[1:0] 2'01
40524       attribute \src "libresoc.v:0.0-0.0"
40525       case 5'00100
40526         assign { } { }
40527         assign $1\dec31_dec_sub21_upd[1:0] 2'00
40528       attribute \src "libresoc.v:0.0-0.0"
40529       case 5'11101
40530         assign { } { }
40531         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40532       attribute \src "libresoc.v:0.0-0.0"
40533       case 5'11100
40534         assign { } { }
40535         assign $1\dec31_dec_sub21_upd[1:0] 2'10
40536       case
40537         assign $1\dec31_dec_sub21_upd[1:0] 2'00
40538     end
40539     sync always
40540       update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0]
40541   end
40542   attribute \src "libresoc.v:27674.3-27722.6"
40543   process $proc$libresoc.v:27674$610
40544     assign { } { }
40545     assign { } { }
40546     assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0]
40547     attribute \src "libresoc.v:27675.5-27675.29"
40548     switch \initial
40549       attribute \src "libresoc.v:27675.9-27675.17"
40550       case 1'1
40551       case
40552     end
40553     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40554     switch \opcode_switch
40555       attribute \src "libresoc.v:0.0-0.0"
40556       case 5'11010
40557         assign { } { }
40558         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40559       attribute \src "libresoc.v:0.0-0.0"
40560       case 5'11011
40561         assign { } { }
40562         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40563       attribute \src "libresoc.v:0.0-0.0"
40564       case 5'00001
40565         assign { } { }
40566         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40567       attribute \src "libresoc.v:0.0-0.0"
40568       case 5'00000
40569         assign { } { }
40570         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40571       attribute \src "libresoc.v:0.0-0.0"
40572       case 5'11001
40573         assign { } { }
40574         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40575       attribute \src "libresoc.v:0.0-0.0"
40576       case 5'01011
40577         assign { } { }
40578         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40579       attribute \src "libresoc.v:0.0-0.0"
40580       case 5'01010
40581         assign { } { }
40582         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40583       attribute \src "libresoc.v:0.0-0.0"
40584       case 5'11000
40585         assign { } { }
40586         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40587       attribute \src "libresoc.v:0.0-0.0"
40588       case 5'11110
40589         assign { } { }
40590         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40591       attribute \src "libresoc.v:0.0-0.0"
40592       case 5'11111
40593         assign { } { }
40594         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40595       attribute \src "libresoc.v:0.0-0.0"
40596       case 5'00101
40597         assign { } { }
40598         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40599       attribute \src "libresoc.v:0.0-0.0"
40600       case 5'00100
40601         assign { } { }
40602         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40603       attribute \src "libresoc.v:0.0-0.0"
40604       case 5'11101
40605         assign { } { }
40606         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40607       attribute \src "libresoc.v:0.0-0.0"
40608       case 5'11100
40609         assign { } { }
40610         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40611       case
40612         assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00
40613     end
40614     sync always
40615       update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0]
40616   end
40617   attribute \src "libresoc.v:27723.3-27771.6"
40618   process $proc$libresoc.v:27723$611
40619     assign { } { }
40620     assign { } { }
40621     assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0]
40622     attribute \src "libresoc.v:27724.5-27724.29"
40623     switch \initial
40624       attribute \src "libresoc.v:27724.9-27724.17"
40625       case 1'1
40626       case
40627     end
40628     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40629     switch \opcode_switch
40630       attribute \src "libresoc.v:0.0-0.0"
40631       case 5'11010
40632         assign { } { }
40633         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40634       attribute \src "libresoc.v:0.0-0.0"
40635       case 5'11011
40636         assign { } { }
40637         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40638       attribute \src "libresoc.v:0.0-0.0"
40639       case 5'00001
40640         assign { } { }
40641         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40642       attribute \src "libresoc.v:0.0-0.0"
40643       case 5'00000
40644         assign { } { }
40645         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40646       attribute \src "libresoc.v:0.0-0.0"
40647       case 5'11001
40648         assign { } { }
40649         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40650       attribute \src "libresoc.v:0.0-0.0"
40651       case 5'01011
40652         assign { } { }
40653         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40654       attribute \src "libresoc.v:0.0-0.0"
40655       case 5'01010
40656         assign { } { }
40657         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40658       attribute \src "libresoc.v:0.0-0.0"
40659       case 5'11000
40660         assign { } { }
40661         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40662       attribute \src "libresoc.v:0.0-0.0"
40663       case 5'11110
40664         assign { } { }
40665         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40666       attribute \src "libresoc.v:0.0-0.0"
40667       case 5'11111
40668         assign { } { }
40669         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40670       attribute \src "libresoc.v:0.0-0.0"
40671       case 5'00101
40672         assign { } { }
40673         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40674       attribute \src "libresoc.v:0.0-0.0"
40675       case 5'00100
40676         assign { } { }
40677         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40678       attribute \src "libresoc.v:0.0-0.0"
40679       case 5'11101
40680         assign { } { }
40681         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40682       attribute \src "libresoc.v:0.0-0.0"
40683       case 5'11100
40684         assign { } { }
40685         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40686       case
40687         assign $1\dec31_dec_sub21_cry_in[1:0] 2'00
40688     end
40689     sync always
40690       update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0]
40691   end
40692   attribute \src "libresoc.v:27772.3-27820.6"
40693   process $proc$libresoc.v:27772$612
40694     assign { } { }
40695     assign { } { }
40696     assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0]
40697     attribute \src "libresoc.v:27773.5-27773.29"
40698     switch \initial
40699       attribute \src "libresoc.v:27773.9-27773.17"
40700       case 1'1
40701       case
40702     end
40703     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40704     switch \opcode_switch
40705       attribute \src "libresoc.v:0.0-0.0"
40706       case 5'11010
40707         assign { } { }
40708         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40709       attribute \src "libresoc.v:0.0-0.0"
40710       case 5'11011
40711         assign { } { }
40712         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40713       attribute \src "libresoc.v:0.0-0.0"
40714       case 5'00001
40715         assign { } { }
40716         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40717       attribute \src "libresoc.v:0.0-0.0"
40718       case 5'00000
40719         assign { } { }
40720         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40721       attribute \src "libresoc.v:0.0-0.0"
40722       case 5'11001
40723         assign { } { }
40724         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40725       attribute \src "libresoc.v:0.0-0.0"
40726       case 5'01011
40727         assign { } { }
40728         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40729       attribute \src "libresoc.v:0.0-0.0"
40730       case 5'01010
40731         assign { } { }
40732         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40733       attribute \src "libresoc.v:0.0-0.0"
40734       case 5'11000
40735         assign { } { }
40736         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40737       attribute \src "libresoc.v:0.0-0.0"
40738       case 5'11110
40739         assign { } { }
40740         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40741       attribute \src "libresoc.v:0.0-0.0"
40742       case 5'11111
40743         assign { } { }
40744         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40745       attribute \src "libresoc.v:0.0-0.0"
40746       case 5'00101
40747         assign { } { }
40748         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40749       attribute \src "libresoc.v:0.0-0.0"
40750       case 5'00100
40751         assign { } { }
40752         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40753       attribute \src "libresoc.v:0.0-0.0"
40754       case 5'11101
40755         assign { } { }
40756         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40757       attribute \src "libresoc.v:0.0-0.0"
40758       case 5'11100
40759         assign { } { }
40760         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40761       case
40762         assign $1\dec31_dec_sub21_inv_a[0:0] 1'0
40763     end
40764     sync always
40765       update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0]
40766   end
40767   attribute \src "libresoc.v:27821.3-27869.6"
40768   process $proc$libresoc.v:27821$613
40769     assign { } { }
40770     assign { } { }
40771     assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0]
40772     attribute \src "libresoc.v:27822.5-27822.29"
40773     switch \initial
40774       attribute \src "libresoc.v:27822.9-27822.17"
40775       case 1'1
40776       case
40777     end
40778     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40779     switch \opcode_switch
40780       attribute \src "libresoc.v:0.0-0.0"
40781       case 5'11010
40782         assign { } { }
40783         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40784       attribute \src "libresoc.v:0.0-0.0"
40785       case 5'11011
40786         assign { } { }
40787         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40788       attribute \src "libresoc.v:0.0-0.0"
40789       case 5'00001
40790         assign { } { }
40791         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40792       attribute \src "libresoc.v:0.0-0.0"
40793       case 5'00000
40794         assign { } { }
40795         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40796       attribute \src "libresoc.v:0.0-0.0"
40797       case 5'11001
40798         assign { } { }
40799         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40800       attribute \src "libresoc.v:0.0-0.0"
40801       case 5'01011
40802         assign { } { }
40803         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40804       attribute \src "libresoc.v:0.0-0.0"
40805       case 5'01010
40806         assign { } { }
40807         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40808       attribute \src "libresoc.v:0.0-0.0"
40809       case 5'11000
40810         assign { } { }
40811         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40812       attribute \src "libresoc.v:0.0-0.0"
40813       case 5'11110
40814         assign { } { }
40815         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40816       attribute \src "libresoc.v:0.0-0.0"
40817       case 5'11111
40818         assign { } { }
40819         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40820       attribute \src "libresoc.v:0.0-0.0"
40821       case 5'00101
40822         assign { } { }
40823         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40824       attribute \src "libresoc.v:0.0-0.0"
40825       case 5'00100
40826         assign { } { }
40827         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40828       attribute \src "libresoc.v:0.0-0.0"
40829       case 5'11101
40830         assign { } { }
40831         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40832       attribute \src "libresoc.v:0.0-0.0"
40833       case 5'11100
40834         assign { } { }
40835         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40836       case
40837         assign $1\dec31_dec_sub21_inv_out[0:0] 1'0
40838     end
40839     sync always
40840       update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0]
40841   end
40842   attribute \src "libresoc.v:27870.3-27918.6"
40843   process $proc$libresoc.v:27870$614
40844     assign { } { }
40845     assign { } { }
40846     assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0]
40847     attribute \src "libresoc.v:27871.5-27871.29"
40848     switch \initial
40849       attribute \src "libresoc.v:27871.9-27871.17"
40850       case 1'1
40851       case
40852     end
40853     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40854     switch \opcode_switch
40855       attribute \src "libresoc.v:0.0-0.0"
40856       case 5'11010
40857         assign { } { }
40858         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40859       attribute \src "libresoc.v:0.0-0.0"
40860       case 5'11011
40861         assign { } { }
40862         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40863       attribute \src "libresoc.v:0.0-0.0"
40864       case 5'00001
40865         assign { } { }
40866         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40867       attribute \src "libresoc.v:0.0-0.0"
40868       case 5'00000
40869         assign { } { }
40870         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40871       attribute \src "libresoc.v:0.0-0.0"
40872       case 5'11001
40873         assign { } { }
40874         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40875       attribute \src "libresoc.v:0.0-0.0"
40876       case 5'01011
40877         assign { } { }
40878         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40879       attribute \src "libresoc.v:0.0-0.0"
40880       case 5'01010
40881         assign { } { }
40882         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40883       attribute \src "libresoc.v:0.0-0.0"
40884       case 5'11000
40885         assign { } { }
40886         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40887       attribute \src "libresoc.v:0.0-0.0"
40888       case 5'11110
40889         assign { } { }
40890         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40891       attribute \src "libresoc.v:0.0-0.0"
40892       case 5'11111
40893         assign { } { }
40894         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40895       attribute \src "libresoc.v:0.0-0.0"
40896       case 5'00101
40897         assign { } { }
40898         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40899       attribute \src "libresoc.v:0.0-0.0"
40900       case 5'00100
40901         assign { } { }
40902         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40903       attribute \src "libresoc.v:0.0-0.0"
40904       case 5'11101
40905         assign { } { }
40906         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40907       attribute \src "libresoc.v:0.0-0.0"
40908       case 5'11100
40909         assign { } { }
40910         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40911       case
40912         assign $1\dec31_dec_sub21_cry_out[0:0] 1'0
40913     end
40914     sync always
40915       update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0]
40916   end
40917   attribute \src "libresoc.v:27919.3-27967.6"
40918   process $proc$libresoc.v:27919$615
40919     assign { } { }
40920     assign { } { }
40921     assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0]
40922     attribute \src "libresoc.v:27920.5-27920.29"
40923     switch \initial
40924       attribute \src "libresoc.v:27920.9-27920.17"
40925       case 1'1
40926       case
40927     end
40928     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
40929     switch \opcode_switch
40930       attribute \src "libresoc.v:0.0-0.0"
40931       case 5'11010
40932         assign { } { }
40933         assign $1\dec31_dec_sub21_br[0:0] 1'0
40934       attribute \src "libresoc.v:0.0-0.0"
40935       case 5'11011
40936         assign { } { }
40937         assign $1\dec31_dec_sub21_br[0:0] 1'0
40938       attribute \src "libresoc.v:0.0-0.0"
40939       case 5'00001
40940         assign { } { }
40941         assign $1\dec31_dec_sub21_br[0:0] 1'0
40942       attribute \src "libresoc.v:0.0-0.0"
40943       case 5'00000
40944         assign { } { }
40945         assign $1\dec31_dec_sub21_br[0:0] 1'0
40946       attribute \src "libresoc.v:0.0-0.0"
40947       case 5'11001
40948         assign { } { }
40949         assign $1\dec31_dec_sub21_br[0:0] 1'0
40950       attribute \src "libresoc.v:0.0-0.0"
40951       case 5'01011
40952         assign { } { }
40953         assign $1\dec31_dec_sub21_br[0:0] 1'0
40954       attribute \src "libresoc.v:0.0-0.0"
40955       case 5'01010
40956         assign { } { }
40957         assign $1\dec31_dec_sub21_br[0:0] 1'0
40958       attribute \src "libresoc.v:0.0-0.0"
40959       case 5'11000
40960         assign { } { }
40961         assign $1\dec31_dec_sub21_br[0:0] 1'0
40962       attribute \src "libresoc.v:0.0-0.0"
40963       case 5'11110
40964         assign { } { }
40965         assign $1\dec31_dec_sub21_br[0:0] 1'0
40966       attribute \src "libresoc.v:0.0-0.0"
40967       case 5'11111
40968         assign { } { }
40969         assign $1\dec31_dec_sub21_br[0:0] 1'0
40970       attribute \src "libresoc.v:0.0-0.0"
40971       case 5'00101
40972         assign { } { }
40973         assign $1\dec31_dec_sub21_br[0:0] 1'0
40974       attribute \src "libresoc.v:0.0-0.0"
40975       case 5'00100
40976         assign { } { }
40977         assign $1\dec31_dec_sub21_br[0:0] 1'0
40978       attribute \src "libresoc.v:0.0-0.0"
40979       case 5'11101
40980         assign { } { }
40981         assign $1\dec31_dec_sub21_br[0:0] 1'0
40982       attribute \src "libresoc.v:0.0-0.0"
40983       case 5'11100
40984         assign { } { }
40985         assign $1\dec31_dec_sub21_br[0:0] 1'0
40986       case
40987         assign $1\dec31_dec_sub21_br[0:0] 1'0
40988     end
40989     sync always
40990       update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0]
40991   end
40992   attribute \src "libresoc.v:27968.3-28016.6"
40993   process $proc$libresoc.v:27968$616
40994     assign { } { }
40995     assign { } { }
40996     assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0]
40997     attribute \src "libresoc.v:27969.5-27969.29"
40998     switch \initial
40999       attribute \src "libresoc.v:27969.9-27969.17"
41000       case 1'1
41001       case
41002     end
41003     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41004     switch \opcode_switch
41005       attribute \src "libresoc.v:0.0-0.0"
41006       case 5'11010
41007         assign { } { }
41008         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41009       attribute \src "libresoc.v:0.0-0.0"
41010       case 5'11011
41011         assign { } { }
41012         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41013       attribute \src "libresoc.v:0.0-0.0"
41014       case 5'00001
41015         assign { } { }
41016         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41017       attribute \src "libresoc.v:0.0-0.0"
41018       case 5'00000
41019         assign { } { }
41020         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41021       attribute \src "libresoc.v:0.0-0.0"
41022       case 5'11001
41023         assign { } { }
41024         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41025       attribute \src "libresoc.v:0.0-0.0"
41026       case 5'01011
41027         assign { } { }
41028         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1
41029       attribute \src "libresoc.v:0.0-0.0"
41030       case 5'01010
41031         assign { } { }
41032         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1
41033       attribute \src "libresoc.v:0.0-0.0"
41034       case 5'11000
41035         assign { } { }
41036         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41037       attribute \src "libresoc.v:0.0-0.0"
41038       case 5'11110
41039         assign { } { }
41040         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41041       attribute \src "libresoc.v:0.0-0.0"
41042       case 5'11111
41043         assign { } { }
41044         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41045       attribute \src "libresoc.v:0.0-0.0"
41046       case 5'00101
41047         assign { } { }
41048         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41049       attribute \src "libresoc.v:0.0-0.0"
41050       case 5'00100
41051         assign { } { }
41052         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41053       attribute \src "libresoc.v:0.0-0.0"
41054       case 5'11101
41055         assign { } { }
41056         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41057       attribute \src "libresoc.v:0.0-0.0"
41058       case 5'11100
41059         assign { } { }
41060         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41061       case
41062         assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0
41063     end
41064     sync always
41065       update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0]
41066   end
41067   attribute \src "libresoc.v:28017.3-28065.6"
41068   process $proc$libresoc.v:28017$617
41069     assign { } { }
41070     assign { } { }
41071     assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0]
41072     attribute \src "libresoc.v:28018.5-28018.29"
41073     switch \initial
41074       attribute \src "libresoc.v:28018.9-28018.17"
41075       case 1'1
41076       case
41077     end
41078     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41079     switch \opcode_switch
41080       attribute \src "libresoc.v:0.0-0.0"
41081       case 5'11010
41082         assign { } { }
41083         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41084       attribute \src "libresoc.v:0.0-0.0"
41085       case 5'11011
41086         assign { } { }
41087         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41088       attribute \src "libresoc.v:0.0-0.0"
41089       case 5'00001
41090         assign { } { }
41091         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41092       attribute \src "libresoc.v:0.0-0.0"
41093       case 5'00000
41094         assign { } { }
41095         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41096       attribute \src "libresoc.v:0.0-0.0"
41097       case 5'11001
41098         assign { } { }
41099         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41100       attribute \src "libresoc.v:0.0-0.0"
41101       case 5'01011
41102         assign { } { }
41103         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41104       attribute \src "libresoc.v:0.0-0.0"
41105       case 5'01010
41106         assign { } { }
41107         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41108       attribute \src "libresoc.v:0.0-0.0"
41109       case 5'11000
41110         assign { } { }
41111         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41112       attribute \src "libresoc.v:0.0-0.0"
41113       case 5'11110
41114         assign { } { }
41115         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41116       attribute \src "libresoc.v:0.0-0.0"
41117       case 5'11111
41118         assign { } { }
41119         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41120       attribute \src "libresoc.v:0.0-0.0"
41121       case 5'00101
41122         assign { } { }
41123         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41124       attribute \src "libresoc.v:0.0-0.0"
41125       case 5'00100
41126         assign { } { }
41127         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41128       attribute \src "libresoc.v:0.0-0.0"
41129       case 5'11101
41130         assign { } { }
41131         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41132       attribute \src "libresoc.v:0.0-0.0"
41133       case 5'11100
41134         assign { } { }
41135         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41136       case
41137         assign $1\dec31_dec_sub21_rsrv[0:0] 1'0
41138     end
41139     sync always
41140       update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0]
41141   end
41142   attribute \src "libresoc.v:28066.3-28114.6"
41143   process $proc$libresoc.v:28066$618
41144     assign { } { }
41145     assign { } { }
41146     assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0]
41147     attribute \src "libresoc.v:28067.5-28067.29"
41148     switch \initial
41149       attribute \src "libresoc.v:28067.9-28067.17"
41150       case 1'1
41151       case
41152     end
41153     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41154     switch \opcode_switch
41155       attribute \src "libresoc.v:0.0-0.0"
41156       case 5'11010
41157         assign { } { }
41158         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41159       attribute \src "libresoc.v:0.0-0.0"
41160       case 5'11011
41161         assign { } { }
41162         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41163       attribute \src "libresoc.v:0.0-0.0"
41164       case 5'00001
41165         assign { } { }
41166         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41167       attribute \src "libresoc.v:0.0-0.0"
41168       case 5'00000
41169         assign { } { }
41170         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41171       attribute \src "libresoc.v:0.0-0.0"
41172       case 5'11001
41173         assign { } { }
41174         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41175       attribute \src "libresoc.v:0.0-0.0"
41176       case 5'01011
41177         assign { } { }
41178         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41179       attribute \src "libresoc.v:0.0-0.0"
41180       case 5'01010
41181         assign { } { }
41182         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41183       attribute \src "libresoc.v:0.0-0.0"
41184       case 5'11000
41185         assign { } { }
41186         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101
41187       attribute \src "libresoc.v:0.0-0.0"
41188       case 5'11110
41189         assign { } { }
41190         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110
41191       attribute \src "libresoc.v:0.0-0.0"
41192       case 5'11111
41193         assign { } { }
41194         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110
41195       attribute \src "libresoc.v:0.0-0.0"
41196       case 5'00101
41197         assign { } { }
41198         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110
41199       attribute \src "libresoc.v:0.0-0.0"
41200       case 5'00100
41201         assign { } { }
41202         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110
41203       attribute \src "libresoc.v:0.0-0.0"
41204       case 5'11101
41205         assign { } { }
41206         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110
41207       attribute \src "libresoc.v:0.0-0.0"
41208       case 5'11100
41209         assign { } { }
41210         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110
41211       case
41212         assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000
41213     end
41214     sync always
41215       update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0]
41216   end
41217   attribute \src "libresoc.v:28115.3-28163.6"
41218   process $proc$libresoc.v:28115$619
41219     assign { } { }
41220     assign { } { }
41221     assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0]
41222     attribute \src "libresoc.v:28116.5-28116.29"
41223     switch \initial
41224       attribute \src "libresoc.v:28116.9-28116.17"
41225       case 1'1
41226       case
41227     end
41228     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41229     switch \opcode_switch
41230       attribute \src "libresoc.v:0.0-0.0"
41231       case 5'11010
41232         assign { } { }
41233         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41234       attribute \src "libresoc.v:0.0-0.0"
41235       case 5'11011
41236         assign { } { }
41237         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41238       attribute \src "libresoc.v:0.0-0.0"
41239       case 5'00001
41240         assign { } { }
41241         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41242       attribute \src "libresoc.v:0.0-0.0"
41243       case 5'00000
41244         assign { } { }
41245         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41246       attribute \src "libresoc.v:0.0-0.0"
41247       case 5'11001
41248         assign { } { }
41249         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41250       attribute \src "libresoc.v:0.0-0.0"
41251       case 5'01011
41252         assign { } { }
41253         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41254       attribute \src "libresoc.v:0.0-0.0"
41255       case 5'01010
41256         assign { } { }
41257         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41258       attribute \src "libresoc.v:0.0-0.0"
41259       case 5'11000
41260         assign { } { }
41261         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41262       attribute \src "libresoc.v:0.0-0.0"
41263       case 5'11110
41264         assign { } { }
41265         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41266       attribute \src "libresoc.v:0.0-0.0"
41267       case 5'11111
41268         assign { } { }
41269         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41270       attribute \src "libresoc.v:0.0-0.0"
41271       case 5'00101
41272         assign { } { }
41273         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41274       attribute \src "libresoc.v:0.0-0.0"
41275       case 5'00100
41276         assign { } { }
41277         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41278       attribute \src "libresoc.v:0.0-0.0"
41279       case 5'11101
41280         assign { } { }
41281         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41282       attribute \src "libresoc.v:0.0-0.0"
41283       case 5'11100
41284         assign { } { }
41285         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41286       case
41287         assign $1\dec31_dec_sub21_is_32b[0:0] 1'0
41288     end
41289     sync always
41290       update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0]
41291   end
41292   attribute \src "libresoc.v:28164.3-28212.6"
41293   process $proc$libresoc.v:28164$620
41294     assign { } { }
41295     assign { } { }
41296     assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0]
41297     attribute \src "libresoc.v:28165.5-28165.29"
41298     switch \initial
41299       attribute \src "libresoc.v:28165.9-28165.17"
41300       case 1'1
41301       case
41302     end
41303     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41304     switch \opcode_switch
41305       attribute \src "libresoc.v:0.0-0.0"
41306       case 5'11010
41307         assign { } { }
41308         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41309       attribute \src "libresoc.v:0.0-0.0"
41310       case 5'11011
41311         assign { } { }
41312         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41313       attribute \src "libresoc.v:0.0-0.0"
41314       case 5'00001
41315         assign { } { }
41316         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41317       attribute \src "libresoc.v:0.0-0.0"
41318       case 5'00000
41319         assign { } { }
41320         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41321       attribute \src "libresoc.v:0.0-0.0"
41322       case 5'11001
41323         assign { } { }
41324         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41325       attribute \src "libresoc.v:0.0-0.0"
41326       case 5'01011
41327         assign { } { }
41328         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41329       attribute \src "libresoc.v:0.0-0.0"
41330       case 5'01010
41331         assign { } { }
41332         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41333       attribute \src "libresoc.v:0.0-0.0"
41334       case 5'11000
41335         assign { } { }
41336         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41337       attribute \src "libresoc.v:0.0-0.0"
41338       case 5'11110
41339         assign { } { }
41340         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41341       attribute \src "libresoc.v:0.0-0.0"
41342       case 5'11111
41343         assign { } { }
41344         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41345       attribute \src "libresoc.v:0.0-0.0"
41346       case 5'00101
41347         assign { } { }
41348         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41349       attribute \src "libresoc.v:0.0-0.0"
41350       case 5'00100
41351         assign { } { }
41352         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41353       attribute \src "libresoc.v:0.0-0.0"
41354       case 5'11101
41355         assign { } { }
41356         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41357       attribute \src "libresoc.v:0.0-0.0"
41358       case 5'11100
41359         assign { } { }
41360         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41361       case
41362         assign $1\dec31_dec_sub21_sgn[0:0] 1'0
41363     end
41364     sync always
41365       update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0]
41366   end
41367   attribute \src "libresoc.v:28213.3-28261.6"
41368   process $proc$libresoc.v:28213$621
41369     assign { } { }
41370     assign { } { }
41371     assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0]
41372     attribute \src "libresoc.v:28214.5-28214.29"
41373     switch \initial
41374       attribute \src "libresoc.v:28214.9-28214.17"
41375       case 1'1
41376       case
41377     end
41378     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41379     switch \opcode_switch
41380       attribute \src "libresoc.v:0.0-0.0"
41381       case 5'11010
41382         assign { } { }
41383         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41384       attribute \src "libresoc.v:0.0-0.0"
41385       case 5'11011
41386         assign { } { }
41387         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41388       attribute \src "libresoc.v:0.0-0.0"
41389       case 5'00001
41390         assign { } { }
41391         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41392       attribute \src "libresoc.v:0.0-0.0"
41393       case 5'00000
41394         assign { } { }
41395         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41396       attribute \src "libresoc.v:0.0-0.0"
41397       case 5'11001
41398         assign { } { }
41399         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41400       attribute \src "libresoc.v:0.0-0.0"
41401       case 5'01011
41402         assign { } { }
41403         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41404       attribute \src "libresoc.v:0.0-0.0"
41405       case 5'01010
41406         assign { } { }
41407         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41408       attribute \src "libresoc.v:0.0-0.0"
41409       case 5'11000
41410         assign { } { }
41411         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41412       attribute \src "libresoc.v:0.0-0.0"
41413       case 5'11110
41414         assign { } { }
41415         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41416       attribute \src "libresoc.v:0.0-0.0"
41417       case 5'11111
41418         assign { } { }
41419         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41420       attribute \src "libresoc.v:0.0-0.0"
41421       case 5'00101
41422         assign { } { }
41423         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41424       attribute \src "libresoc.v:0.0-0.0"
41425       case 5'00100
41426         assign { } { }
41427         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41428       attribute \src "libresoc.v:0.0-0.0"
41429       case 5'11101
41430         assign { } { }
41431         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41432       attribute \src "libresoc.v:0.0-0.0"
41433       case 5'11100
41434         assign { } { }
41435         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41436       case
41437         assign $1\dec31_dec_sub21_lk[0:0] 1'0
41438     end
41439     sync always
41440       update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0]
41441   end
41442   attribute \src "libresoc.v:28262.3-28310.6"
41443   process $proc$libresoc.v:28262$622
41444     assign { } { }
41445     assign { } { }
41446     assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0]
41447     attribute \src "libresoc.v:28263.5-28263.29"
41448     switch \initial
41449       attribute \src "libresoc.v:28263.9-28263.17"
41450       case 1'1
41451       case
41452     end
41453     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41454     switch \opcode_switch
41455       attribute \src "libresoc.v:0.0-0.0"
41456       case 5'11010
41457         assign { } { }
41458         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0
41459       attribute \src "libresoc.v:0.0-0.0"
41460       case 5'11011
41461         assign { } { }
41462         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0
41463       attribute \src "libresoc.v:0.0-0.0"
41464       case 5'00001
41465         assign { } { }
41466         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41467       attribute \src "libresoc.v:0.0-0.0"
41468       case 5'00000
41469         assign { } { }
41470         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41471       attribute \src "libresoc.v:0.0-0.0"
41472       case 5'11001
41473         assign { } { }
41474         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0
41475       attribute \src "libresoc.v:0.0-0.0"
41476       case 5'01011
41477         assign { } { }
41478         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41479       attribute \src "libresoc.v:0.0-0.0"
41480       case 5'01010
41481         assign { } { }
41482         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41483       attribute \src "libresoc.v:0.0-0.0"
41484       case 5'11000
41485         assign { } { }
41486         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0
41487       attribute \src "libresoc.v:0.0-0.0"
41488       case 5'11110
41489         assign { } { }
41490         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41491       attribute \src "libresoc.v:0.0-0.0"
41492       case 5'11111
41493         assign { } { }
41494         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41495       attribute \src "libresoc.v:0.0-0.0"
41496       case 5'00101
41497         assign { } { }
41498         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41499       attribute \src "libresoc.v:0.0-0.0"
41500       case 5'00100
41501         assign { } { }
41502         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41503       attribute \src "libresoc.v:0.0-0.0"
41504       case 5'11101
41505         assign { } { }
41506         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41507       attribute \src "libresoc.v:0.0-0.0"
41508       case 5'11100
41509         assign { } { }
41510         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1
41511       case
41512         assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0
41513     end
41514     sync always
41515       update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0]
41516   end
41517   attribute \src "libresoc.v:28311.3-28341.6"
41518   process $proc$libresoc.v:28311$623
41519     assign { } { }
41520     assign { } { }
41521     assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0]
41522     attribute \src "libresoc.v:28312.5-28312.29"
41523     switch \initial
41524       attribute \src "libresoc.v:28312.9-28312.17"
41525       case 1'1
41526       case
41527     end
41528     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41529     switch \opcode_switch
41530       attribute \src "libresoc.v:0.0-0.0"
41531       case 5'00001
41532         assign { } { }
41533         assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110
41534       attribute \src "libresoc.v:0.0-0.0"
41535       case 5'00000
41536         assign { } { }
41537         assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111
41538       attribute \src "libresoc.v:0.0-0.0"
41539       case 5'01011
41540         assign { } { }
41541         assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100
41542       attribute \src "libresoc.v:0.0-0.0"
41543       case 5'01010
41544         assign { } { }
41545         assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101
41546       attribute \src "libresoc.v:0.0-0.0"
41547       case 5'11000
41548         assign { } { }
41549         assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000
41550       attribute \src "libresoc.v:0.0-0.0"
41551       case 5'11110
41552         assign { } { }
41553         assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111
41554       attribute \src "libresoc.v:0.0-0.0"
41555       case 5'00101
41556         assign { } { }
41557         assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000
41558       attribute \src "libresoc.v:0.0-0.0"
41559       case 5'00100
41560         assign { } { }
41561         assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001
41562       case
41563         assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000
41564     end
41565     sync always
41566       update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0]
41567   end
41568   attribute \src "libresoc.v:28342.3-28390.6"
41569   process $proc$libresoc.v:28342$624
41570     assign { } { }
41571     assign { } { }
41572     assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0]
41573     attribute \src "libresoc.v:28343.5-28343.29"
41574     switch \initial
41575       attribute \src "libresoc.v:28343.9-28343.17"
41576       case 1'1
41577       case
41578     end
41579     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41580     switch \opcode_switch
41581       attribute \src "libresoc.v:0.0-0.0"
41582       case 5'11010
41583         assign { } { }
41584         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41585       attribute \src "libresoc.v:0.0-0.0"
41586       case 5'11011
41587         assign { } { }
41588         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41589       attribute \src "libresoc.v:0.0-0.0"
41590       case 5'00001
41591         assign { } { }
41592         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41593       attribute \src "libresoc.v:0.0-0.0"
41594       case 5'00000
41595         assign { } { }
41596         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41597       attribute \src "libresoc.v:0.0-0.0"
41598       case 5'11001
41599         assign { } { }
41600         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41601       attribute \src "libresoc.v:0.0-0.0"
41602       case 5'01011
41603         assign { } { }
41604         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41605       attribute \src "libresoc.v:0.0-0.0"
41606       case 5'01010
41607         assign { } { }
41608         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41609       attribute \src "libresoc.v:0.0-0.0"
41610       case 5'11000
41611         assign { } { }
41612         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41613       attribute \src "libresoc.v:0.0-0.0"
41614       case 5'11110
41615         assign { } { }
41616         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41617       attribute \src "libresoc.v:0.0-0.0"
41618       case 5'11111
41619         assign { } { }
41620         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41621       attribute \src "libresoc.v:0.0-0.0"
41622       case 5'00101
41623         assign { } { }
41624         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41625       attribute \src "libresoc.v:0.0-0.0"
41626       case 5'00100
41627         assign { } { }
41628         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41629       attribute \src "libresoc.v:0.0-0.0"
41630       case 5'11101
41631         assign { } { }
41632         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41633       attribute \src "libresoc.v:0.0-0.0"
41634       case 5'11100
41635         assign { } { }
41636         assign $1\dec31_dec_sub21_form[4:0] 5'01000
41637       case
41638         assign $1\dec31_dec_sub21_form[4:0] 5'00000
41639     end
41640     sync always
41641       update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0]
41642   end
41643   attribute \src "libresoc.v:28391.3-28439.6"
41644   process $proc$libresoc.v:28391$625
41645     assign { } { }
41646     assign { } { }
41647     assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0]
41648     attribute \src "libresoc.v:28392.5-28392.29"
41649     switch \initial
41650       attribute \src "libresoc.v:28392.9-28392.17"
41651       case 1'1
41652       case
41653     end
41654     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41655     switch \opcode_switch
41656       attribute \src "libresoc.v:0.0-0.0"
41657       case 5'11010
41658         assign { } { }
41659         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41660       attribute \src "libresoc.v:0.0-0.0"
41661       case 5'11011
41662         assign { } { }
41663         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41664       attribute \src "libresoc.v:0.0-0.0"
41665       case 5'00001
41666         assign { } { }
41667         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41668       attribute \src "libresoc.v:0.0-0.0"
41669       case 5'00000
41670         assign { } { }
41671         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41672       attribute \src "libresoc.v:0.0-0.0"
41673       case 5'11001
41674         assign { } { }
41675         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41676       attribute \src "libresoc.v:0.0-0.0"
41677       case 5'01011
41678         assign { } { }
41679         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41680       attribute \src "libresoc.v:0.0-0.0"
41681       case 5'01010
41682         assign { } { }
41683         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41684       attribute \src "libresoc.v:0.0-0.0"
41685       case 5'11000
41686         assign { } { }
41687         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41688       attribute \src "libresoc.v:0.0-0.0"
41689       case 5'11110
41690         assign { } { }
41691         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41692       attribute \src "libresoc.v:0.0-0.0"
41693       case 5'11111
41694         assign { } { }
41695         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41696       attribute \src "libresoc.v:0.0-0.0"
41697       case 5'00101
41698         assign { } { }
41699         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41700       attribute \src "libresoc.v:0.0-0.0"
41701       case 5'00100
41702         assign { } { }
41703         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41704       attribute \src "libresoc.v:0.0-0.0"
41705       case 5'11101
41706         assign { } { }
41707         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41708       attribute \src "libresoc.v:0.0-0.0"
41709       case 5'11100
41710         assign { } { }
41711         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010
41712       case
41713         assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000
41714     end
41715     sync always
41716       update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0]
41717   end
41718   attribute \src "libresoc.v:28440.3-28488.6"
41719   process $proc$libresoc.v:28440$626
41720     assign { } { }
41721     assign { } { }
41722     assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0]
41723     attribute \src "libresoc.v:28441.5-28441.29"
41724     switch \initial
41725       attribute \src "libresoc.v:28441.9-28441.17"
41726       case 1'1
41727       case
41728     end
41729     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41730     switch \opcode_switch
41731       attribute \src "libresoc.v:0.0-0.0"
41732       case 5'11010
41733         assign { } { }
41734         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41735       attribute \src "libresoc.v:0.0-0.0"
41736       case 5'11011
41737         assign { } { }
41738         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41739       attribute \src "libresoc.v:0.0-0.0"
41740       case 5'00001
41741         assign { } { }
41742         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41743       attribute \src "libresoc.v:0.0-0.0"
41744       case 5'00000
41745         assign { } { }
41746         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41747       attribute \src "libresoc.v:0.0-0.0"
41748       case 5'11001
41749         assign { } { }
41750         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41751       attribute \src "libresoc.v:0.0-0.0"
41752       case 5'01011
41753         assign { } { }
41754         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41755       attribute \src "libresoc.v:0.0-0.0"
41756       case 5'01010
41757         assign { } { }
41758         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41759       attribute \src "libresoc.v:0.0-0.0"
41760       case 5'11000
41761         assign { } { }
41762         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41763       attribute \src "libresoc.v:0.0-0.0"
41764       case 5'11110
41765         assign { } { }
41766         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41767       attribute \src "libresoc.v:0.0-0.0"
41768       case 5'11111
41769         assign { } { }
41770         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41771       attribute \src "libresoc.v:0.0-0.0"
41772       case 5'00101
41773         assign { } { }
41774         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41775       attribute \src "libresoc.v:0.0-0.0"
41776       case 5'00100
41777         assign { } { }
41778         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41779       attribute \src "libresoc.v:0.0-0.0"
41780       case 5'11101
41781         assign { } { }
41782         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41783       attribute \src "libresoc.v:0.0-0.0"
41784       case 5'11100
41785         assign { } { }
41786         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001
41787       case
41788         assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000
41789     end
41790     sync always
41791       update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0]
41792   end
41793   attribute \src "libresoc.v:28489.3-28537.6"
41794   process $proc$libresoc.v:28489$627
41795     assign { } { }
41796     assign { } { }
41797     assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0]
41798     attribute \src "libresoc.v:28490.5-28490.29"
41799     switch \initial
41800       attribute \src "libresoc.v:28490.9-28490.17"
41801       case 1'1
41802       case
41803     end
41804     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41805     switch \opcode_switch
41806       attribute \src "libresoc.v:0.0-0.0"
41807       case 5'11010
41808         assign { } { }
41809         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41810       attribute \src "libresoc.v:0.0-0.0"
41811       case 5'11011
41812         assign { } { }
41813         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41814       attribute \src "libresoc.v:0.0-0.0"
41815       case 5'00001
41816         assign { } { }
41817         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41818       attribute \src "libresoc.v:0.0-0.0"
41819       case 5'00000
41820         assign { } { }
41821         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41822       attribute \src "libresoc.v:0.0-0.0"
41823       case 5'11001
41824         assign { } { }
41825         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41826       attribute \src "libresoc.v:0.0-0.0"
41827       case 5'01011
41828         assign { } { }
41829         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41830       attribute \src "libresoc.v:0.0-0.0"
41831       case 5'01010
41832         assign { } { }
41833         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41834       attribute \src "libresoc.v:0.0-0.0"
41835       case 5'11000
41836         assign { } { }
41837         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41838       attribute \src "libresoc.v:0.0-0.0"
41839       case 5'11110
41840         assign { } { }
41841         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01
41842       attribute \src "libresoc.v:0.0-0.0"
41843       case 5'11111
41844         assign { } { }
41845         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01
41846       attribute \src "libresoc.v:0.0-0.0"
41847       case 5'00101
41848         assign { } { }
41849         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01
41850       attribute \src "libresoc.v:0.0-0.0"
41851       case 5'00100
41852         assign { } { }
41853         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01
41854       attribute \src "libresoc.v:0.0-0.0"
41855       case 5'11101
41856         assign { } { }
41857         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01
41858       attribute \src "libresoc.v:0.0-0.0"
41859       case 5'11100
41860         assign { } { }
41861         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01
41862       case
41863         assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00
41864     end
41865     sync always
41866       update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0]
41867   end
41868   attribute \src "libresoc.v:28538.3-28586.6"
41869   process $proc$libresoc.v:28538$628
41870     assign { } { }
41871     assign { } { }
41872     assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0]
41873     attribute \src "libresoc.v:28539.5-28539.29"
41874     switch \initial
41875       attribute \src "libresoc.v:28539.9-28539.17"
41876       case 1'1
41877       case
41878     end
41879     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41880     switch \opcode_switch
41881       attribute \src "libresoc.v:0.0-0.0"
41882       case 5'11010
41883         assign { } { }
41884         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41885       attribute \src "libresoc.v:0.0-0.0"
41886       case 5'11011
41887         assign { } { }
41888         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41889       attribute \src "libresoc.v:0.0-0.0"
41890       case 5'00001
41891         assign { } { }
41892         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41893       attribute \src "libresoc.v:0.0-0.0"
41894       case 5'00000
41895         assign { } { }
41896         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41897       attribute \src "libresoc.v:0.0-0.0"
41898       case 5'11001
41899         assign { } { }
41900         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41901       attribute \src "libresoc.v:0.0-0.0"
41902       case 5'01011
41903         assign { } { }
41904         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41905       attribute \src "libresoc.v:0.0-0.0"
41906       case 5'01010
41907         assign { } { }
41908         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41909       attribute \src "libresoc.v:0.0-0.0"
41910       case 5'11000
41911         assign { } { }
41912         assign $1\dec31_dec_sub21_out_sel[1:0] 2'01
41913       attribute \src "libresoc.v:0.0-0.0"
41914       case 5'11110
41915         assign { } { }
41916         assign $1\dec31_dec_sub21_out_sel[1:0] 2'00
41917       attribute \src "libresoc.v:0.0-0.0"
41918       case 5'11111
41919         assign { } { }
41920         assign $1\dec31_dec_sub21_out_sel[1:0] 2'00
41921       attribute \src "libresoc.v:0.0-0.0"
41922       case 5'00101
41923         assign { } { }
41924         assign $1\dec31_dec_sub21_out_sel[1:0] 2'00
41925       attribute \src "libresoc.v:0.0-0.0"
41926       case 5'00100
41927         assign { } { }
41928         assign $1\dec31_dec_sub21_out_sel[1:0] 2'00
41929       attribute \src "libresoc.v:0.0-0.0"
41930       case 5'11101
41931         assign { } { }
41932         assign $1\dec31_dec_sub21_out_sel[1:0] 2'00
41933       attribute \src "libresoc.v:0.0-0.0"
41934       case 5'11100
41935         assign { } { }
41936         assign $1\dec31_dec_sub21_out_sel[1:0] 2'00
41937       case
41938         assign $1\dec31_dec_sub21_out_sel[1:0] 2'00
41939     end
41940     sync always
41941       update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0]
41942   end
41943   attribute \src "libresoc.v:28587.3-28635.6"
41944   process $proc$libresoc.v:28587$629
41945     assign { } { }
41946     assign { } { }
41947     assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0]
41948     attribute \src "libresoc.v:28588.5-28588.29"
41949     switch \initial
41950       attribute \src "libresoc.v:28588.9-28588.17"
41951       case 1'1
41952       case
41953     end
41954     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
41955     switch \opcode_switch
41956       attribute \src "libresoc.v:0.0-0.0"
41957       case 5'11010
41958         assign { } { }
41959         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41960       attribute \src "libresoc.v:0.0-0.0"
41961       case 5'11011
41962         assign { } { }
41963         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41964       attribute \src "libresoc.v:0.0-0.0"
41965       case 5'00001
41966         assign { } { }
41967         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41968       attribute \src "libresoc.v:0.0-0.0"
41969       case 5'00000
41970         assign { } { }
41971         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41972       attribute \src "libresoc.v:0.0-0.0"
41973       case 5'11001
41974         assign { } { }
41975         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41976       attribute \src "libresoc.v:0.0-0.0"
41977       case 5'01011
41978         assign { } { }
41979         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41980       attribute \src "libresoc.v:0.0-0.0"
41981       case 5'01010
41982         assign { } { }
41983         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41984       attribute \src "libresoc.v:0.0-0.0"
41985       case 5'11000
41986         assign { } { }
41987         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41988       attribute \src "libresoc.v:0.0-0.0"
41989       case 5'11110
41990         assign { } { }
41991         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41992       attribute \src "libresoc.v:0.0-0.0"
41993       case 5'11111
41994         assign { } { }
41995         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
41996       attribute \src "libresoc.v:0.0-0.0"
41997       case 5'00101
41998         assign { } { }
41999         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
42000       attribute \src "libresoc.v:0.0-0.0"
42001       case 5'00100
42002         assign { } { }
42003         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
42004       attribute \src "libresoc.v:0.0-0.0"
42005       case 5'11101
42006         assign { } { }
42007         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
42008       attribute \src "libresoc.v:0.0-0.0"
42009       case 5'11100
42010         assign { } { }
42011         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
42012       case
42013         assign $1\dec31_dec_sub21_cr_in[2:0] 3'000
42014     end
42015     sync always
42016       update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0]
42017   end
42018   attribute \src "libresoc.v:28636.3-28684.6"
42019   process $proc$libresoc.v:28636$630
42020     assign { } { }
42021     assign { } { }
42022     assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0]
42023     attribute \src "libresoc.v:28637.5-28637.29"
42024     switch \initial
42025       attribute \src "libresoc.v:28637.9-28637.17"
42026       case 1'1
42027       case
42028     end
42029     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42030     switch \opcode_switch
42031       attribute \src "libresoc.v:0.0-0.0"
42032       case 5'11010
42033         assign { } { }
42034         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42035       attribute \src "libresoc.v:0.0-0.0"
42036       case 5'11011
42037         assign { } { }
42038         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42039       attribute \src "libresoc.v:0.0-0.0"
42040       case 5'00001
42041         assign { } { }
42042         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42043       attribute \src "libresoc.v:0.0-0.0"
42044       case 5'00000
42045         assign { } { }
42046         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42047       attribute \src "libresoc.v:0.0-0.0"
42048       case 5'11001
42049         assign { } { }
42050         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42051       attribute \src "libresoc.v:0.0-0.0"
42052       case 5'01011
42053         assign { } { }
42054         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42055       attribute \src "libresoc.v:0.0-0.0"
42056       case 5'01010
42057         assign { } { }
42058         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42059       attribute \src "libresoc.v:0.0-0.0"
42060       case 5'11000
42061         assign { } { }
42062         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42063       attribute \src "libresoc.v:0.0-0.0"
42064       case 5'11110
42065         assign { } { }
42066         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42067       attribute \src "libresoc.v:0.0-0.0"
42068       case 5'11111
42069         assign { } { }
42070         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42071       attribute \src "libresoc.v:0.0-0.0"
42072       case 5'00101
42073         assign { } { }
42074         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42075       attribute \src "libresoc.v:0.0-0.0"
42076       case 5'00100
42077         assign { } { }
42078         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42079       attribute \src "libresoc.v:0.0-0.0"
42080       case 5'11101
42081         assign { } { }
42082         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42083       attribute \src "libresoc.v:0.0-0.0"
42084       case 5'11100
42085         assign { } { }
42086         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42087       case
42088         assign $1\dec31_dec_sub21_cr_out[2:0] 3'000
42089     end
42090     sync always
42091       update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0]
42092   end
42093   connect \opcode_switch \opcode_in [10:6]
42094 end
42095 attribute \src "libresoc.v:28690.1-30269.10"
42096 attribute \cells_not_processed 1
42097 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22"
42098 attribute \generator "nMigen"
42099 module \dec31_dec_sub22
42100   attribute \src "libresoc.v:29223.3-29277.6"
42101   wire width 8 $0\dec31_dec_sub22_asmcode[7:0]
42102   attribute \src "libresoc.v:29443.3-29497.6"
42103   wire $0\dec31_dec_sub22_br[0:0]
42104   attribute \src "libresoc.v:30158.3-30212.6"
42105   wire width 3 $0\dec31_dec_sub22_cr_in[2:0]
42106   attribute \src "libresoc.v:30213.3-30267.6"
42107   wire width 3 $0\dec31_dec_sub22_cr_out[2:0]
42108   attribute \src "libresoc.v:29168.3-29222.6"
42109   wire width 2 $0\dec31_dec_sub22_cry_in[1:0]
42110   attribute \src "libresoc.v:29388.3-29442.6"
42111   wire $0\dec31_dec_sub22_cry_out[0:0]
42112   attribute \src "libresoc.v:29883.3-29937.6"
42113   wire width 5 $0\dec31_dec_sub22_form[4:0]
42114   attribute \src "libresoc.v:28948.3-29002.6"
42115   wire width 12 $0\dec31_dec_sub22_function_unit[11:0]
42116   attribute \src "libresoc.v:29938.3-29992.6"
42117   wire width 3 $0\dec31_dec_sub22_in1_sel[2:0]
42118   attribute \src "libresoc.v:29993.3-30047.6"
42119   wire width 4 $0\dec31_dec_sub22_in2_sel[3:0]
42120   attribute \src "libresoc.v:30048.3-30102.6"
42121   wire width 2 $0\dec31_dec_sub22_in3_sel[1:0]
42122   attribute \src "libresoc.v:29553.3-29607.6"
42123   wire width 7 $0\dec31_dec_sub22_internal_op[6:0]
42124   attribute \src "libresoc.v:29278.3-29332.6"
42125   wire $0\dec31_dec_sub22_inv_a[0:0]
42126   attribute \src "libresoc.v:29333.3-29387.6"
42127   wire $0\dec31_dec_sub22_inv_out[0:0]
42128   attribute \src "libresoc.v:29663.3-29717.6"
42129   wire $0\dec31_dec_sub22_is_32b[0:0]
42130   attribute \src "libresoc.v:29003.3-29057.6"
42131   wire width 4 $0\dec31_dec_sub22_ldst_len[3:0]
42132   attribute \src "libresoc.v:29773.3-29827.6"
42133   wire $0\dec31_dec_sub22_lk[0:0]
42134   attribute \src "libresoc.v:30103.3-30157.6"
42135   wire width 2 $0\dec31_dec_sub22_out_sel[1:0]
42136   attribute \src "libresoc.v:29113.3-29167.6"
42137   wire width 2 $0\dec31_dec_sub22_rc_sel[1:0]
42138   attribute \src "libresoc.v:29608.3-29662.6"
42139   wire $0\dec31_dec_sub22_rsrv[0:0]
42140   attribute \src "libresoc.v:29828.3-29882.6"
42141   wire $0\dec31_dec_sub22_sgl_pipe[0:0]
42142   attribute \src "libresoc.v:29718.3-29772.6"
42143   wire $0\dec31_dec_sub22_sgn[0:0]
42144   attribute \src "libresoc.v:29498.3-29552.6"
42145   wire $0\dec31_dec_sub22_sgn_ext[0:0]
42146   attribute \src "libresoc.v:29058.3-29112.6"
42147   wire width 2 $0\dec31_dec_sub22_upd[1:0]
42148   attribute \src "libresoc.v:28691.7-28691.20"
42149   wire $0\initial[0:0]
42150   attribute \src "libresoc.v:29223.3-29277.6"
42151   wire width 8 $1\dec31_dec_sub22_asmcode[7:0]
42152   attribute \src "libresoc.v:29443.3-29497.6"
42153   wire $1\dec31_dec_sub22_br[0:0]
42154   attribute \src "libresoc.v:30158.3-30212.6"
42155   wire width 3 $1\dec31_dec_sub22_cr_in[2:0]
42156   attribute \src "libresoc.v:30213.3-30267.6"
42157   wire width 3 $1\dec31_dec_sub22_cr_out[2:0]
42158   attribute \src "libresoc.v:29168.3-29222.6"
42159   wire width 2 $1\dec31_dec_sub22_cry_in[1:0]
42160   attribute \src "libresoc.v:29388.3-29442.6"
42161   wire $1\dec31_dec_sub22_cry_out[0:0]
42162   attribute \src "libresoc.v:29883.3-29937.6"
42163   wire width 5 $1\dec31_dec_sub22_form[4:0]
42164   attribute \src "libresoc.v:28948.3-29002.6"
42165   wire width 12 $1\dec31_dec_sub22_function_unit[11:0]
42166   attribute \src "libresoc.v:29938.3-29992.6"
42167   wire width 3 $1\dec31_dec_sub22_in1_sel[2:0]
42168   attribute \src "libresoc.v:29993.3-30047.6"
42169   wire width 4 $1\dec31_dec_sub22_in2_sel[3:0]
42170   attribute \src "libresoc.v:30048.3-30102.6"
42171   wire width 2 $1\dec31_dec_sub22_in3_sel[1:0]
42172   attribute \src "libresoc.v:29553.3-29607.6"
42173   wire width 7 $1\dec31_dec_sub22_internal_op[6:0]
42174   attribute \src "libresoc.v:29278.3-29332.6"
42175   wire $1\dec31_dec_sub22_inv_a[0:0]
42176   attribute \src "libresoc.v:29333.3-29387.6"
42177   wire $1\dec31_dec_sub22_inv_out[0:0]
42178   attribute \src "libresoc.v:29663.3-29717.6"
42179   wire $1\dec31_dec_sub22_is_32b[0:0]
42180   attribute \src "libresoc.v:29003.3-29057.6"
42181   wire width 4 $1\dec31_dec_sub22_ldst_len[3:0]
42182   attribute \src "libresoc.v:29773.3-29827.6"
42183   wire $1\dec31_dec_sub22_lk[0:0]
42184   attribute \src "libresoc.v:30103.3-30157.6"
42185   wire width 2 $1\dec31_dec_sub22_out_sel[1:0]
42186   attribute \src "libresoc.v:29113.3-29167.6"
42187   wire width 2 $1\dec31_dec_sub22_rc_sel[1:0]
42188   attribute \src "libresoc.v:29608.3-29662.6"
42189   wire $1\dec31_dec_sub22_rsrv[0:0]
42190   attribute \src "libresoc.v:29828.3-29882.6"
42191   wire $1\dec31_dec_sub22_sgl_pipe[0:0]
42192   attribute \src "libresoc.v:29718.3-29772.6"
42193   wire $1\dec31_dec_sub22_sgn[0:0]
42194   attribute \src "libresoc.v:29498.3-29552.6"
42195   wire $1\dec31_dec_sub22_sgn_ext[0:0]
42196   attribute \src "libresoc.v:29058.3-29112.6"
42197   wire width 2 $1\dec31_dec_sub22_upd[1:0]
42198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42199   wire width 8 output 4 \dec31_dec_sub22_asmcode
42200   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42201   wire output 18 \dec31_dec_sub22_br
42202   attribute \enum_base_type "CRInSel"
42203   attribute \enum_value_000 "NONE"
42204   attribute \enum_value_001 "CR0"
42205   attribute \enum_value_010 "BI"
42206   attribute \enum_value_011 "BFA"
42207   attribute \enum_value_100 "BA_BB"
42208   attribute \enum_value_101 "BC"
42209   attribute \enum_value_110 "WHOLE_REG"
42210   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42211   wire width 3 output 9 \dec31_dec_sub22_cr_in
42212   attribute \enum_base_type "CROutSel"
42213   attribute \enum_value_000 "NONE"
42214   attribute \enum_value_001 "CR0"
42215   attribute \enum_value_010 "BF"
42216   attribute \enum_value_011 "BT"
42217   attribute \enum_value_100 "WHOLE_REG"
42218   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42219   wire width 3 output 10 \dec31_dec_sub22_cr_out
42220   attribute \enum_base_type "CryIn"
42221   attribute \enum_value_00 "ZERO"
42222   attribute \enum_value_01 "ONE"
42223   attribute \enum_value_10 "CA"
42224   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42225   wire width 2 output 14 \dec31_dec_sub22_cry_in
42226   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42227   wire output 17 \dec31_dec_sub22_cry_out
42228   attribute \enum_base_type "Form"
42229   attribute \enum_value_00000 "NONE"
42230   attribute \enum_value_00001 "I"
42231   attribute \enum_value_00010 "B"
42232   attribute \enum_value_00011 "SC"
42233   attribute \enum_value_00100 "D"
42234   attribute \enum_value_00101 "DS"
42235   attribute \enum_value_00110 "DQ"
42236   attribute \enum_value_00111 "DX"
42237   attribute \enum_value_01000 "X"
42238   attribute \enum_value_01001 "XL"
42239   attribute \enum_value_01010 "XFX"
42240   attribute \enum_value_01011 "XFL"
42241   attribute \enum_value_01100 "XX1"
42242   attribute \enum_value_01101 "XX2"
42243   attribute \enum_value_01110 "XX3"
42244   attribute \enum_value_01111 "XX4"
42245   attribute \enum_value_10000 "XS"
42246   attribute \enum_value_10001 "XO"
42247   attribute \enum_value_10010 "A"
42248   attribute \enum_value_10011 "M"
42249   attribute \enum_value_10100 "MD"
42250   attribute \enum_value_10101 "MDS"
42251   attribute \enum_value_10110 "VA"
42252   attribute \enum_value_10111 "VC"
42253   attribute \enum_value_11000 "VX"
42254   attribute \enum_value_11001 "EVX"
42255   attribute \enum_value_11010 "EVS"
42256   attribute \enum_value_11011 "Z22"
42257   attribute \enum_value_11100 "Z23"
42258   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42259   wire width 5 output 3 \dec31_dec_sub22_form
42260   attribute \enum_base_type "Function"
42261   attribute \enum_value_000000000000 "NONE"
42262   attribute \enum_value_000000000010 "ALU"
42263   attribute \enum_value_000000000100 "LDST"
42264   attribute \enum_value_000000001000 "SHIFT_ROT"
42265   attribute \enum_value_000000010000 "LOGICAL"
42266   attribute \enum_value_000000100000 "BRANCH"
42267   attribute \enum_value_000001000000 "CR"
42268   attribute \enum_value_000010000000 "TRAP"
42269   attribute \enum_value_000100000000 "MUL"
42270   attribute \enum_value_001000000000 "DIV"
42271   attribute \enum_value_010000000000 "SPR"
42272   attribute \enum_value_100000000000 "MMU"
42273   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42274   wire width 12 output 1 \dec31_dec_sub22_function_unit
42275   attribute \enum_base_type "In1Sel"
42276   attribute \enum_value_000 "NONE"
42277   attribute \enum_value_001 "RA"
42278   attribute \enum_value_010 "RA_OR_ZERO"
42279   attribute \enum_value_011 "SPR"
42280   attribute \enum_value_100 "RS"
42281   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42282   wire width 3 output 5 \dec31_dec_sub22_in1_sel
42283   attribute \enum_base_type "In2Sel"
42284   attribute \enum_value_0000 "NONE"
42285   attribute \enum_value_0001 "RB"
42286   attribute \enum_value_0010 "CONST_UI"
42287   attribute \enum_value_0011 "CONST_SI"
42288   attribute \enum_value_0100 "CONST_UI_HI"
42289   attribute \enum_value_0101 "CONST_SI_HI"
42290   attribute \enum_value_0110 "CONST_LI"
42291   attribute \enum_value_0111 "CONST_BD"
42292   attribute \enum_value_1000 "CONST_DS"
42293   attribute \enum_value_1001 "CONST_M1"
42294   attribute \enum_value_1010 "CONST_SH"
42295   attribute \enum_value_1011 "CONST_SH32"
42296   attribute \enum_value_1100 "SPR"
42297   attribute \enum_value_1101 "RS"
42298   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42299   wire width 4 output 6 \dec31_dec_sub22_in2_sel
42300   attribute \enum_base_type "In3Sel"
42301   attribute \enum_value_00 "NONE"
42302   attribute \enum_value_01 "RS"
42303   attribute \enum_value_10 "RB"
42304   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42305   wire width 2 output 7 \dec31_dec_sub22_in3_sel
42306   attribute \enum_base_type "MicrOp"
42307   attribute \enum_value_0000000 "OP_ILLEGAL"
42308   attribute \enum_value_0000001 "OP_NOP"
42309   attribute \enum_value_0000010 "OP_ADD"
42310   attribute \enum_value_0000011 "OP_ADDPCIS"
42311   attribute \enum_value_0000100 "OP_AND"
42312   attribute \enum_value_0000101 "OP_ATTN"
42313   attribute \enum_value_0000110 "OP_B"
42314   attribute \enum_value_0000111 "OP_BC"
42315   attribute \enum_value_0001000 "OP_BCREG"
42316   attribute \enum_value_0001001 "OP_BPERM"
42317   attribute \enum_value_0001010 "OP_CMP"
42318   attribute \enum_value_0001011 "OP_CMPB"
42319   attribute \enum_value_0001100 "OP_CMPEQB"
42320   attribute \enum_value_0001101 "OP_CMPRB"
42321   attribute \enum_value_0001110 "OP_CNTZ"
42322   attribute \enum_value_0001111 "OP_CRAND"
42323   attribute \enum_value_0010000 "OP_CRANDC"
42324   attribute \enum_value_0010001 "OP_CREQV"
42325   attribute \enum_value_0010010 "OP_CRNAND"
42326   attribute \enum_value_0010011 "OP_CRNOR"
42327   attribute \enum_value_0010100 "OP_CROR"
42328   attribute \enum_value_0010101 "OP_CRORC"
42329   attribute \enum_value_0010110 "OP_CRXOR"
42330   attribute \enum_value_0010111 "OP_DARN"
42331   attribute \enum_value_0011000 "OP_DCBF"
42332   attribute \enum_value_0011001 "OP_DCBST"
42333   attribute \enum_value_0011010 "OP_DCBT"
42334   attribute \enum_value_0011011 "OP_DCBTST"
42335   attribute \enum_value_0011100 "OP_DCBZ"
42336   attribute \enum_value_0011101 "OP_DIV"
42337   attribute \enum_value_0011110 "OP_DIVE"
42338   attribute \enum_value_0011111 "OP_EXTS"
42339   attribute \enum_value_0100000 "OP_EXTSWSLI"
42340   attribute \enum_value_0100001 "OP_ICBI"
42341   attribute \enum_value_0100010 "OP_ICBT"
42342   attribute \enum_value_0100011 "OP_ISEL"
42343   attribute \enum_value_0100100 "OP_ISYNC"
42344   attribute \enum_value_0100101 "OP_LOAD"
42345   attribute \enum_value_0100110 "OP_STORE"
42346   attribute \enum_value_0100111 "OP_MADDHD"
42347   attribute \enum_value_0101000 "OP_MADDHDU"
42348   attribute \enum_value_0101001 "OP_MADDLD"
42349   attribute \enum_value_0101010 "OP_MCRF"
42350   attribute \enum_value_0101011 "OP_MCRXR"
42351   attribute \enum_value_0101100 "OP_MCRXRX"
42352   attribute \enum_value_0101101 "OP_MFCR"
42353   attribute \enum_value_0101110 "OP_MFSPR"
42354   attribute \enum_value_0101111 "OP_MOD"
42355   attribute \enum_value_0110000 "OP_MTCRF"
42356   attribute \enum_value_0110001 "OP_MTSPR"
42357   attribute \enum_value_0110010 "OP_MUL_L64"
42358   attribute \enum_value_0110011 "OP_MUL_H64"
42359   attribute \enum_value_0110100 "OP_MUL_H32"
42360   attribute \enum_value_0110101 "OP_OR"
42361   attribute \enum_value_0110110 "OP_POPCNT"
42362   attribute \enum_value_0110111 "OP_PRTY"
42363   attribute \enum_value_0111000 "OP_RLC"
42364   attribute \enum_value_0111001 "OP_RLCL"
42365   attribute \enum_value_0111010 "OP_RLCR"
42366   attribute \enum_value_0111011 "OP_SETB"
42367   attribute \enum_value_0111100 "OP_SHL"
42368   attribute \enum_value_0111101 "OP_SHR"
42369   attribute \enum_value_0111110 "OP_SYNC"
42370   attribute \enum_value_0111111 "OP_TRAP"
42371   attribute \enum_value_1000011 "OP_XOR"
42372   attribute \enum_value_1000100 "OP_SIM_CONFIG"
42373   attribute \enum_value_1000101 "OP_CROP"
42374   attribute \enum_value_1000110 "OP_RFID"
42375   attribute \enum_value_1000111 "OP_MFMSR"
42376   attribute \enum_value_1001000 "OP_MTMSRD"
42377   attribute \enum_value_1001001 "OP_SC"
42378   attribute \enum_value_1001010 "OP_MTMSR"
42379   attribute \enum_value_1001011 "OP_TLBIE"
42380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42381   wire width 7 output 2 \dec31_dec_sub22_internal_op
42382   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42383   wire output 15 \dec31_dec_sub22_inv_a
42384   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42385   wire output 16 \dec31_dec_sub22_inv_out
42386   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42387   wire output 21 \dec31_dec_sub22_is_32b
42388   attribute \enum_base_type "LdstLen"
42389   attribute \enum_value_0000 "NONE"
42390   attribute \enum_value_0001 "is1B"
42391   attribute \enum_value_0010 "is2B"
42392   attribute \enum_value_0100 "is4B"
42393   attribute \enum_value_1000 "is8B"
42394   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42395   wire width 4 output 11 \dec31_dec_sub22_ldst_len
42396   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42397   wire output 23 \dec31_dec_sub22_lk
42398   attribute \enum_base_type "OutSel"
42399   attribute \enum_value_00 "NONE"
42400   attribute \enum_value_01 "RT"
42401   attribute \enum_value_10 "RA"
42402   attribute \enum_value_11 "SPR"
42403   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42404   wire width 2 output 8 \dec31_dec_sub22_out_sel
42405   attribute \enum_base_type "RC"
42406   attribute \enum_value_00 "NONE"
42407   attribute \enum_value_01 "ONE"
42408   attribute \enum_value_10 "RC"
42409   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42410   wire width 2 output 13 \dec31_dec_sub22_rc_sel
42411   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42412   wire output 20 \dec31_dec_sub22_rsrv
42413   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42414   wire output 24 \dec31_dec_sub22_sgl_pipe
42415   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42416   wire output 22 \dec31_dec_sub22_sgn
42417   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
42418   wire output 19 \dec31_dec_sub22_sgn_ext
42419   attribute \enum_base_type "LDSTMode"
42420   attribute \enum_value_00 "NONE"
42421   attribute \enum_value_01 "update"
42422   attribute \enum_value_10 "cix"
42423   attribute \enum_value_11 "cx"
42424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
42425   wire width 2 output 12 \dec31_dec_sub22_upd
42426   attribute \src "libresoc.v:28691.7-28691.15"
42427   wire \initial
42428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
42429   wire width 32 input 25 \opcode_in
42430   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
42431   wire width 5 \opcode_switch
42432   attribute \src "libresoc.v:28691.7-28691.20"
42433   process $proc$libresoc.v:28691$656
42434     assign { } { }
42435     assign $0\initial[0:0] 1'0
42436     sync always
42437       update \initial $0\initial[0:0]
42438     sync init
42439   end
42440   attribute \src "libresoc.v:28948.3-29002.6"
42441   process $proc$libresoc.v:28948$632
42442     assign { } { }
42443     assign { } { }
42444     assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0]
42445     attribute \src "libresoc.v:28949.5-28949.29"
42446     switch \initial
42447       attribute \src "libresoc.v:28949.9-28949.17"
42448       case 1'1
42449       case
42450     end
42451     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42452     switch \opcode_switch
42453       attribute \src "libresoc.v:0.0-0.0"
42454       case 5'00010
42455         assign { } { }
42456         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010
42457       attribute \src "libresoc.v:0.0-0.0"
42458       case 5'00001
42459         assign { } { }
42460         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010
42461       attribute \src "libresoc.v:0.0-0.0"
42462       case 5'01000
42463         assign { } { }
42464         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010
42465       attribute \src "libresoc.v:0.0-0.0"
42466       case 5'00111
42467         assign { } { }
42468         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010
42469       attribute \src "libresoc.v:0.0-0.0"
42470       case 5'11111
42471         assign { } { }
42472         assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000
42473       attribute \src "libresoc.v:0.0-0.0"
42474       case 5'11110
42475         assign { } { }
42476         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010
42477       attribute \src "libresoc.v:0.0-0.0"
42478       case 5'00000
42479         assign { } { }
42480         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010
42481       attribute \src "libresoc.v:0.0-0.0"
42482       case 5'11000
42483         assign { } { }
42484         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42485       attribute \src "libresoc.v:0.0-0.0"
42486       case 5'10000
42487         assign { } { }
42488         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42489       attribute \src "libresoc.v:0.0-0.0"
42490       case 5'10101
42491         assign { } { }
42492         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42493       attribute \src "libresoc.v:0.0-0.0"
42494       case 5'00110
42495         assign { } { }
42496         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42497       attribute \src "libresoc.v:0.0-0.0"
42498       case 5'11100
42499         assign { } { }
42500         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42501       attribute \src "libresoc.v:0.0-0.0"
42502       case 5'10110
42503         assign { } { }
42504         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42505       attribute \src "libresoc.v:0.0-0.0"
42506       case 5'10100
42507         assign { } { }
42508         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42509       attribute \src "libresoc.v:0.0-0.0"
42510       case 5'00100
42511         assign { } { }
42512         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100
42513       attribute \src "libresoc.v:0.0-0.0"
42514       case 5'10010
42515         assign { } { }
42516         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010
42517       case
42518         assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000
42519     end
42520     sync always
42521       update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0]
42522   end
42523   attribute \src "libresoc.v:29003.3-29057.6"
42524   process $proc$libresoc.v:29003$633
42525     assign { } { }
42526     assign { } { }
42527     assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0]
42528     attribute \src "libresoc.v:29004.5-29004.29"
42529     switch \initial
42530       attribute \src "libresoc.v:29004.9-29004.17"
42531       case 1'1
42532       case
42533     end
42534     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42535     switch \opcode_switch
42536       attribute \src "libresoc.v:0.0-0.0"
42537       case 5'00010
42538         assign { } { }
42539         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42540       attribute \src "libresoc.v:0.0-0.0"
42541       case 5'00001
42542         assign { } { }
42543         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42544       attribute \src "libresoc.v:0.0-0.0"
42545       case 5'01000
42546         assign { } { }
42547         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42548       attribute \src "libresoc.v:0.0-0.0"
42549       case 5'00111
42550         assign { } { }
42551         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42552       attribute \src "libresoc.v:0.0-0.0"
42553       case 5'11111
42554         assign { } { }
42555         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42556       attribute \src "libresoc.v:0.0-0.0"
42557       case 5'11110
42558         assign { } { }
42559         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42560       attribute \src "libresoc.v:0.0-0.0"
42561       case 5'00000
42562         assign { } { }
42563         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42564       attribute \src "libresoc.v:0.0-0.0"
42565       case 5'11000
42566         assign { } { }
42567         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010
42568       attribute \src "libresoc.v:0.0-0.0"
42569       case 5'10000
42570         assign { } { }
42571         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100
42572       attribute \src "libresoc.v:0.0-0.0"
42573       case 5'10101
42574         assign { } { }
42575         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001
42576       attribute \src "libresoc.v:0.0-0.0"
42577       case 5'00110
42578         assign { } { }
42579         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000
42580       attribute \src "libresoc.v:0.0-0.0"
42581       case 5'11100
42582         assign { } { }
42583         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010
42584       attribute \src "libresoc.v:0.0-0.0"
42585       case 5'10110
42586         assign { } { }
42587         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010
42588       attribute \src "libresoc.v:0.0-0.0"
42589       case 5'10100
42590         assign { } { }
42591         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100
42592       attribute \src "libresoc.v:0.0-0.0"
42593       case 5'00100
42594         assign { } { }
42595         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100
42596       attribute \src "libresoc.v:0.0-0.0"
42597       case 5'10010
42598         assign { } { }
42599         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42600       case
42601         assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000
42602     end
42603     sync always
42604       update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0]
42605   end
42606   attribute \src "libresoc.v:29058.3-29112.6"
42607   process $proc$libresoc.v:29058$634
42608     assign { } { }
42609     assign { } { }
42610     assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0]
42611     attribute \src "libresoc.v:29059.5-29059.29"
42612     switch \initial
42613       attribute \src "libresoc.v:29059.9-29059.17"
42614       case 1'1
42615       case
42616     end
42617     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42618     switch \opcode_switch
42619       attribute \src "libresoc.v:0.0-0.0"
42620       case 5'00010
42621         assign { } { }
42622         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42623       attribute \src "libresoc.v:0.0-0.0"
42624       case 5'00001
42625         assign { } { }
42626         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42627       attribute \src "libresoc.v:0.0-0.0"
42628       case 5'01000
42629         assign { } { }
42630         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42631       attribute \src "libresoc.v:0.0-0.0"
42632       case 5'00111
42633         assign { } { }
42634         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42635       attribute \src "libresoc.v:0.0-0.0"
42636       case 5'11111
42637         assign { } { }
42638         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42639       attribute \src "libresoc.v:0.0-0.0"
42640       case 5'11110
42641         assign { } { }
42642         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42643       attribute \src "libresoc.v:0.0-0.0"
42644       case 5'00000
42645         assign { } { }
42646         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42647       attribute \src "libresoc.v:0.0-0.0"
42648       case 5'11000
42649         assign { } { }
42650         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42651       attribute \src "libresoc.v:0.0-0.0"
42652       case 5'10000
42653         assign { } { }
42654         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42655       attribute \src "libresoc.v:0.0-0.0"
42656       case 5'10101
42657         assign { } { }
42658         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42659       attribute \src "libresoc.v:0.0-0.0"
42660       case 5'00110
42661         assign { } { }
42662         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42663       attribute \src "libresoc.v:0.0-0.0"
42664       case 5'11100
42665         assign { } { }
42666         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42667       attribute \src "libresoc.v:0.0-0.0"
42668       case 5'10110
42669         assign { } { }
42670         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42671       attribute \src "libresoc.v:0.0-0.0"
42672       case 5'10100
42673         assign { } { }
42674         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42675       attribute \src "libresoc.v:0.0-0.0"
42676       case 5'00100
42677         assign { } { }
42678         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42679       attribute \src "libresoc.v:0.0-0.0"
42680       case 5'10010
42681         assign { } { }
42682         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42683       case
42684         assign $1\dec31_dec_sub22_upd[1:0] 2'00
42685     end
42686     sync always
42687       update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0]
42688   end
42689   attribute \src "libresoc.v:29113.3-29167.6"
42690   process $proc$libresoc.v:29113$635
42691     assign { } { }
42692     assign { } { }
42693     assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0]
42694     attribute \src "libresoc.v:29114.5-29114.29"
42695     switch \initial
42696       attribute \src "libresoc.v:29114.9-29114.17"
42697       case 1'1
42698       case
42699     end
42700     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42701     switch \opcode_switch
42702       attribute \src "libresoc.v:0.0-0.0"
42703       case 5'00010
42704         assign { } { }
42705         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42706       attribute \src "libresoc.v:0.0-0.0"
42707       case 5'00001
42708         assign { } { }
42709         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42710       attribute \src "libresoc.v:0.0-0.0"
42711       case 5'01000
42712         assign { } { }
42713         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42714       attribute \src "libresoc.v:0.0-0.0"
42715       case 5'00111
42716         assign { } { }
42717         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42718       attribute \src "libresoc.v:0.0-0.0"
42719       case 5'11111
42720         assign { } { }
42721         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42722       attribute \src "libresoc.v:0.0-0.0"
42723       case 5'11110
42724         assign { } { }
42725         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42726       attribute \src "libresoc.v:0.0-0.0"
42727       case 5'00000
42728         assign { } { }
42729         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42730       attribute \src "libresoc.v:0.0-0.0"
42731       case 5'11000
42732         assign { } { }
42733         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42734       attribute \src "libresoc.v:0.0-0.0"
42735       case 5'10000
42736         assign { } { }
42737         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42738       attribute \src "libresoc.v:0.0-0.0"
42739       case 5'10101
42740         assign { } { }
42741         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10
42742       attribute \src "libresoc.v:0.0-0.0"
42743       case 5'00110
42744         assign { } { }
42745         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42746       attribute \src "libresoc.v:0.0-0.0"
42747       case 5'11100
42748         assign { } { }
42749         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42750       attribute \src "libresoc.v:0.0-0.0"
42751       case 5'10110
42752         assign { } { }
42753         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42754       attribute \src "libresoc.v:0.0-0.0"
42755       case 5'10100
42756         assign { } { }
42757         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42758       attribute \src "libresoc.v:0.0-0.0"
42759       case 5'00100
42760         assign { } { }
42761         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42762       attribute \src "libresoc.v:0.0-0.0"
42763       case 5'10010
42764         assign { } { }
42765         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42766       case
42767         assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00
42768     end
42769     sync always
42770       update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0]
42771   end
42772   attribute \src "libresoc.v:29168.3-29222.6"
42773   process $proc$libresoc.v:29168$636
42774     assign { } { }
42775     assign { } { }
42776     assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0]
42777     attribute \src "libresoc.v:29169.5-29169.29"
42778     switch \initial
42779       attribute \src "libresoc.v:29169.9-29169.17"
42780       case 1'1
42781       case
42782     end
42783     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42784     switch \opcode_switch
42785       attribute \src "libresoc.v:0.0-0.0"
42786       case 5'00010
42787         assign { } { }
42788         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42789       attribute \src "libresoc.v:0.0-0.0"
42790       case 5'00001
42791         assign { } { }
42792         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42793       attribute \src "libresoc.v:0.0-0.0"
42794       case 5'01000
42795         assign { } { }
42796         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42797       attribute \src "libresoc.v:0.0-0.0"
42798       case 5'00111
42799         assign { } { }
42800         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42801       attribute \src "libresoc.v:0.0-0.0"
42802       case 5'11111
42803         assign { } { }
42804         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42805       attribute \src "libresoc.v:0.0-0.0"
42806       case 5'11110
42807         assign { } { }
42808         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42809       attribute \src "libresoc.v:0.0-0.0"
42810       case 5'00000
42811         assign { } { }
42812         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42813       attribute \src "libresoc.v:0.0-0.0"
42814       case 5'11000
42815         assign { } { }
42816         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42817       attribute \src "libresoc.v:0.0-0.0"
42818       case 5'10000
42819         assign { } { }
42820         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42821       attribute \src "libresoc.v:0.0-0.0"
42822       case 5'10101
42823         assign { } { }
42824         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42825       attribute \src "libresoc.v:0.0-0.0"
42826       case 5'00110
42827         assign { } { }
42828         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42829       attribute \src "libresoc.v:0.0-0.0"
42830       case 5'11100
42831         assign { } { }
42832         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42833       attribute \src "libresoc.v:0.0-0.0"
42834       case 5'10110
42835         assign { } { }
42836         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42837       attribute \src "libresoc.v:0.0-0.0"
42838       case 5'10100
42839         assign { } { }
42840         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42841       attribute \src "libresoc.v:0.0-0.0"
42842       case 5'00100
42843         assign { } { }
42844         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42845       attribute \src "libresoc.v:0.0-0.0"
42846       case 5'10010
42847         assign { } { }
42848         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42849       case
42850         assign $1\dec31_dec_sub22_cry_in[1:0] 2'00
42851     end
42852     sync always
42853       update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0]
42854   end
42855   attribute \src "libresoc.v:29223.3-29277.6"
42856   process $proc$libresoc.v:29223$637
42857     assign { } { }
42858     assign { } { }
42859     assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0]
42860     attribute \src "libresoc.v:29224.5-29224.29"
42861     switch \initial
42862       attribute \src "libresoc.v:29224.9-29224.17"
42863       case 1'1
42864       case
42865     end
42866     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42867     switch \opcode_switch
42868       attribute \src "libresoc.v:0.0-0.0"
42869       case 5'00010
42870         assign { } { }
42871         assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110
42872       attribute \src "libresoc.v:0.0-0.0"
42873       case 5'00001
42874         assign { } { }
42875         assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111
42876       attribute \src "libresoc.v:0.0-0.0"
42877       case 5'01000
42878         assign { } { }
42879         assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000
42880       attribute \src "libresoc.v:0.0-0.0"
42881       case 5'00111
42882         assign { } { }
42883         assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001
42884       attribute \src "libresoc.v:0.0-0.0"
42885       case 5'11111
42886         assign { } { }
42887         assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010
42888       attribute \src "libresoc.v:0.0-0.0"
42889       case 5'11110
42890         assign { } { }
42891         assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001
42892       attribute \src "libresoc.v:0.0-0.0"
42893       case 5'00000
42894         assign { } { }
42895         assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010
42896       attribute \src "libresoc.v:0.0-0.0"
42897       case 5'11000
42898         assign { } { }
42899         assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101
42900       attribute \src "libresoc.v:0.0-0.0"
42901       case 5'10000
42902         assign { } { }
42903         assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110
42904       attribute \src "libresoc.v:0.0-0.0"
42905       case 5'10101
42906         assign { } { }
42907         assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000
42908       attribute \src "libresoc.v:0.0-0.0"
42909       case 5'00110
42910         assign { } { }
42911         assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110
42912       attribute \src "libresoc.v:0.0-0.0"
42913       case 5'11100
42914         assign { } { }
42915         assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011
42916       attribute \src "libresoc.v:0.0-0.0"
42917       case 5'10110
42918         assign { } { }
42919         assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100
42920       attribute \src "libresoc.v:0.0-0.0"
42921       case 5'10100
42922         assign { } { }
42923         assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001
42924       attribute \src "libresoc.v:0.0-0.0"
42925       case 5'00100
42926         assign { } { }
42927         assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010
42928       attribute \src "libresoc.v:0.0-0.0"
42929       case 5'10010
42930         assign { } { }
42931         assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001
42932       case
42933         assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000
42934     end
42935     sync always
42936       update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0]
42937   end
42938   attribute \src "libresoc.v:29278.3-29332.6"
42939   process $proc$libresoc.v:29278$638
42940     assign { } { }
42941     assign { } { }
42942     assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0]
42943     attribute \src "libresoc.v:29279.5-29279.29"
42944     switch \initial
42945       attribute \src "libresoc.v:29279.9-29279.17"
42946       case 1'1
42947       case
42948     end
42949     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
42950     switch \opcode_switch
42951       attribute \src "libresoc.v:0.0-0.0"
42952       case 5'00010
42953         assign { } { }
42954         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42955       attribute \src "libresoc.v:0.0-0.0"
42956       case 5'00001
42957         assign { } { }
42958         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42959       attribute \src "libresoc.v:0.0-0.0"
42960       case 5'01000
42961         assign { } { }
42962         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42963       attribute \src "libresoc.v:0.0-0.0"
42964       case 5'00111
42965         assign { } { }
42966         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42967       attribute \src "libresoc.v:0.0-0.0"
42968       case 5'11111
42969         assign { } { }
42970         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42971       attribute \src "libresoc.v:0.0-0.0"
42972       case 5'11110
42973         assign { } { }
42974         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42975       attribute \src "libresoc.v:0.0-0.0"
42976       case 5'00000
42977         assign { } { }
42978         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42979       attribute \src "libresoc.v:0.0-0.0"
42980       case 5'11000
42981         assign { } { }
42982         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42983       attribute \src "libresoc.v:0.0-0.0"
42984       case 5'10000
42985         assign { } { }
42986         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42987       attribute \src "libresoc.v:0.0-0.0"
42988       case 5'10101
42989         assign { } { }
42990         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42991       attribute \src "libresoc.v:0.0-0.0"
42992       case 5'00110
42993         assign { } { }
42994         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42995       attribute \src "libresoc.v:0.0-0.0"
42996       case 5'11100
42997         assign { } { }
42998         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
42999       attribute \src "libresoc.v:0.0-0.0"
43000       case 5'10110
43001         assign { } { }
43002         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
43003       attribute \src "libresoc.v:0.0-0.0"
43004       case 5'10100
43005         assign { } { }
43006         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
43007       attribute \src "libresoc.v:0.0-0.0"
43008       case 5'00100
43009         assign { } { }
43010         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
43011       attribute \src "libresoc.v:0.0-0.0"
43012       case 5'10010
43013         assign { } { }
43014         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
43015       case
43016         assign $1\dec31_dec_sub22_inv_a[0:0] 1'0
43017     end
43018     sync always
43019       update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0]
43020   end
43021   attribute \src "libresoc.v:29333.3-29387.6"
43022   process $proc$libresoc.v:29333$639
43023     assign { } { }
43024     assign { } { }
43025     assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0]
43026     attribute \src "libresoc.v:29334.5-29334.29"
43027     switch \initial
43028       attribute \src "libresoc.v:29334.9-29334.17"
43029       case 1'1
43030       case
43031     end
43032     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43033     switch \opcode_switch
43034       attribute \src "libresoc.v:0.0-0.0"
43035       case 5'00010
43036         assign { } { }
43037         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43038       attribute \src "libresoc.v:0.0-0.0"
43039       case 5'00001
43040         assign { } { }
43041         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43042       attribute \src "libresoc.v:0.0-0.0"
43043       case 5'01000
43044         assign { } { }
43045         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43046       attribute \src "libresoc.v:0.0-0.0"
43047       case 5'00111
43048         assign { } { }
43049         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43050       attribute \src "libresoc.v:0.0-0.0"
43051       case 5'11111
43052         assign { } { }
43053         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43054       attribute \src "libresoc.v:0.0-0.0"
43055       case 5'11110
43056         assign { } { }
43057         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43058       attribute \src "libresoc.v:0.0-0.0"
43059       case 5'00000
43060         assign { } { }
43061         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43062       attribute \src "libresoc.v:0.0-0.0"
43063       case 5'11000
43064         assign { } { }
43065         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43066       attribute \src "libresoc.v:0.0-0.0"
43067       case 5'10000
43068         assign { } { }
43069         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43070       attribute \src "libresoc.v:0.0-0.0"
43071       case 5'10101
43072         assign { } { }
43073         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43074       attribute \src "libresoc.v:0.0-0.0"
43075       case 5'00110
43076         assign { } { }
43077         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43078       attribute \src "libresoc.v:0.0-0.0"
43079       case 5'11100
43080         assign { } { }
43081         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43082       attribute \src "libresoc.v:0.0-0.0"
43083       case 5'10110
43084         assign { } { }
43085         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43086       attribute \src "libresoc.v:0.0-0.0"
43087       case 5'10100
43088         assign { } { }
43089         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43090       attribute \src "libresoc.v:0.0-0.0"
43091       case 5'00100
43092         assign { } { }
43093         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43094       attribute \src "libresoc.v:0.0-0.0"
43095       case 5'10010
43096         assign { } { }
43097         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43098       case
43099         assign $1\dec31_dec_sub22_inv_out[0:0] 1'0
43100     end
43101     sync always
43102       update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0]
43103   end
43104   attribute \src "libresoc.v:29388.3-29442.6"
43105   process $proc$libresoc.v:29388$640
43106     assign { } { }
43107     assign { } { }
43108     assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0]
43109     attribute \src "libresoc.v:29389.5-29389.29"
43110     switch \initial
43111       attribute \src "libresoc.v:29389.9-29389.17"
43112       case 1'1
43113       case
43114     end
43115     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43116     switch \opcode_switch
43117       attribute \src "libresoc.v:0.0-0.0"
43118       case 5'00010
43119         assign { } { }
43120         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43121       attribute \src "libresoc.v:0.0-0.0"
43122       case 5'00001
43123         assign { } { }
43124         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43125       attribute \src "libresoc.v:0.0-0.0"
43126       case 5'01000
43127         assign { } { }
43128         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43129       attribute \src "libresoc.v:0.0-0.0"
43130       case 5'00111
43131         assign { } { }
43132         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43133       attribute \src "libresoc.v:0.0-0.0"
43134       case 5'11111
43135         assign { } { }
43136         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43137       attribute \src "libresoc.v:0.0-0.0"
43138       case 5'11110
43139         assign { } { }
43140         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43141       attribute \src "libresoc.v:0.0-0.0"
43142       case 5'00000
43143         assign { } { }
43144         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43145       attribute \src "libresoc.v:0.0-0.0"
43146       case 5'11000
43147         assign { } { }
43148         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43149       attribute \src "libresoc.v:0.0-0.0"
43150       case 5'10000
43151         assign { } { }
43152         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43153       attribute \src "libresoc.v:0.0-0.0"
43154       case 5'10101
43155         assign { } { }
43156         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43157       attribute \src "libresoc.v:0.0-0.0"
43158       case 5'00110
43159         assign { } { }
43160         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43161       attribute \src "libresoc.v:0.0-0.0"
43162       case 5'11100
43163         assign { } { }
43164         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43165       attribute \src "libresoc.v:0.0-0.0"
43166       case 5'10110
43167         assign { } { }
43168         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43169       attribute \src "libresoc.v:0.0-0.0"
43170       case 5'10100
43171         assign { } { }
43172         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43173       attribute \src "libresoc.v:0.0-0.0"
43174       case 5'00100
43175         assign { } { }
43176         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43177       attribute \src "libresoc.v:0.0-0.0"
43178       case 5'10010
43179         assign { } { }
43180         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43181       case
43182         assign $1\dec31_dec_sub22_cry_out[0:0] 1'0
43183     end
43184     sync always
43185       update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0]
43186   end
43187   attribute \src "libresoc.v:29443.3-29497.6"
43188   process $proc$libresoc.v:29443$641
43189     assign { } { }
43190     assign { } { }
43191     assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0]
43192     attribute \src "libresoc.v:29444.5-29444.29"
43193     switch \initial
43194       attribute \src "libresoc.v:29444.9-29444.17"
43195       case 1'1
43196       case
43197     end
43198     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43199     switch \opcode_switch
43200       attribute \src "libresoc.v:0.0-0.0"
43201       case 5'00010
43202         assign { } { }
43203         assign $1\dec31_dec_sub22_br[0:0] 1'0
43204       attribute \src "libresoc.v:0.0-0.0"
43205       case 5'00001
43206         assign { } { }
43207         assign $1\dec31_dec_sub22_br[0:0] 1'0
43208       attribute \src "libresoc.v:0.0-0.0"
43209       case 5'01000
43210         assign { } { }
43211         assign $1\dec31_dec_sub22_br[0:0] 1'0
43212       attribute \src "libresoc.v:0.0-0.0"
43213       case 5'00111
43214         assign { } { }
43215         assign $1\dec31_dec_sub22_br[0:0] 1'0
43216       attribute \src "libresoc.v:0.0-0.0"
43217       case 5'11111
43218         assign { } { }
43219         assign $1\dec31_dec_sub22_br[0:0] 1'0
43220       attribute \src "libresoc.v:0.0-0.0"
43221       case 5'11110
43222         assign { } { }
43223         assign $1\dec31_dec_sub22_br[0:0] 1'0
43224       attribute \src "libresoc.v:0.0-0.0"
43225       case 5'00000
43226         assign { } { }
43227         assign $1\dec31_dec_sub22_br[0:0] 1'0
43228       attribute \src "libresoc.v:0.0-0.0"
43229       case 5'11000
43230         assign { } { }
43231         assign $1\dec31_dec_sub22_br[0:0] 1'1
43232       attribute \src "libresoc.v:0.0-0.0"
43233       case 5'10000
43234         assign { } { }
43235         assign $1\dec31_dec_sub22_br[0:0] 1'1
43236       attribute \src "libresoc.v:0.0-0.0"
43237       case 5'10101
43238         assign { } { }
43239         assign $1\dec31_dec_sub22_br[0:0] 1'0
43240       attribute \src "libresoc.v:0.0-0.0"
43241       case 5'00110
43242         assign { } { }
43243         assign $1\dec31_dec_sub22_br[0:0] 1'0
43244       attribute \src "libresoc.v:0.0-0.0"
43245       case 5'11100
43246         assign { } { }
43247         assign $1\dec31_dec_sub22_br[0:0] 1'1
43248       attribute \src "libresoc.v:0.0-0.0"
43249       case 5'10110
43250         assign { } { }
43251         assign $1\dec31_dec_sub22_br[0:0] 1'0
43252       attribute \src "libresoc.v:0.0-0.0"
43253       case 5'10100
43254         assign { } { }
43255         assign $1\dec31_dec_sub22_br[0:0] 1'1
43256       attribute \src "libresoc.v:0.0-0.0"
43257       case 5'00100
43258         assign { } { }
43259         assign $1\dec31_dec_sub22_br[0:0] 1'0
43260       attribute \src "libresoc.v:0.0-0.0"
43261       case 5'10010
43262         assign { } { }
43263         assign $1\dec31_dec_sub22_br[0:0] 1'0
43264       case
43265         assign $1\dec31_dec_sub22_br[0:0] 1'0
43266     end
43267     sync always
43268       update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0]
43269   end
43270   attribute \src "libresoc.v:29498.3-29552.6"
43271   process $proc$libresoc.v:29498$642
43272     assign { } { }
43273     assign { } { }
43274     assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0]
43275     attribute \src "libresoc.v:29499.5-29499.29"
43276     switch \initial
43277       attribute \src "libresoc.v:29499.9-29499.17"
43278       case 1'1
43279       case
43280     end
43281     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43282     switch \opcode_switch
43283       attribute \src "libresoc.v:0.0-0.0"
43284       case 5'00010
43285         assign { } { }
43286         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43287       attribute \src "libresoc.v:0.0-0.0"
43288       case 5'00001
43289         assign { } { }
43290         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43291       attribute \src "libresoc.v:0.0-0.0"
43292       case 5'01000
43293         assign { } { }
43294         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43295       attribute \src "libresoc.v:0.0-0.0"
43296       case 5'00111
43297         assign { } { }
43298         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43299       attribute \src "libresoc.v:0.0-0.0"
43300       case 5'11111
43301         assign { } { }
43302         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43303       attribute \src "libresoc.v:0.0-0.0"
43304       case 5'11110
43305         assign { } { }
43306         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43307       attribute \src "libresoc.v:0.0-0.0"
43308       case 5'00000
43309         assign { } { }
43310         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43311       attribute \src "libresoc.v:0.0-0.0"
43312       case 5'11000
43313         assign { } { }
43314         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43315       attribute \src "libresoc.v:0.0-0.0"
43316       case 5'10000
43317         assign { } { }
43318         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43319       attribute \src "libresoc.v:0.0-0.0"
43320       case 5'10101
43321         assign { } { }
43322         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43323       attribute \src "libresoc.v:0.0-0.0"
43324       case 5'00110
43325         assign { } { }
43326         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43327       attribute \src "libresoc.v:0.0-0.0"
43328       case 5'11100
43329         assign { } { }
43330         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43331       attribute \src "libresoc.v:0.0-0.0"
43332       case 5'10110
43333         assign { } { }
43334         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43335       attribute \src "libresoc.v:0.0-0.0"
43336       case 5'10100
43337         assign { } { }
43338         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43339       attribute \src "libresoc.v:0.0-0.0"
43340       case 5'00100
43341         assign { } { }
43342         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43343       attribute \src "libresoc.v:0.0-0.0"
43344       case 5'10010
43345         assign { } { }
43346         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43347       case
43348         assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0
43349     end
43350     sync always
43351       update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0]
43352   end
43353   attribute \src "libresoc.v:29553.3-29607.6"
43354   process $proc$libresoc.v:29553$643
43355     assign { } { }
43356     assign { } { }
43357     assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0]
43358     attribute \src "libresoc.v:29554.5-29554.29"
43359     switch \initial
43360       attribute \src "libresoc.v:29554.9-29554.17"
43361       case 1'1
43362       case
43363     end
43364     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43365     switch \opcode_switch
43366       attribute \src "libresoc.v:0.0-0.0"
43367       case 5'00010
43368         assign { } { }
43369         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001
43370       attribute \src "libresoc.v:0.0-0.0"
43371       case 5'00001
43372         assign { } { }
43373         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001
43374       attribute \src "libresoc.v:0.0-0.0"
43375       case 5'01000
43376         assign { } { }
43377         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001
43378       attribute \src "libresoc.v:0.0-0.0"
43379       case 5'00111
43380         assign { } { }
43381         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001
43382       attribute \src "libresoc.v:0.0-0.0"
43383       case 5'11111
43384         assign { } { }
43385         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100
43386       attribute \src "libresoc.v:0.0-0.0"
43387       case 5'11110
43388         assign { } { }
43389         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001
43390       attribute \src "libresoc.v:0.0-0.0"
43391       case 5'00000
43392         assign { } { }
43393         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001
43394       attribute \src "libresoc.v:0.0-0.0"
43395       case 5'11000
43396         assign { } { }
43397         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101
43398       attribute \src "libresoc.v:0.0-0.0"
43399       case 5'10000
43400         assign { } { }
43401         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101
43402       attribute \src "libresoc.v:0.0-0.0"
43403       case 5'10101
43404         assign { } { }
43405         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110
43406       attribute \src "libresoc.v:0.0-0.0"
43407       case 5'00110
43408         assign { } { }
43409         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110
43410       attribute \src "libresoc.v:0.0-0.0"
43411       case 5'11100
43412         assign { } { }
43413         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110
43414       attribute \src "libresoc.v:0.0-0.0"
43415       case 5'10110
43416         assign { } { }
43417         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110
43418       attribute \src "libresoc.v:0.0-0.0"
43419       case 5'10100
43420         assign { } { }
43421         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110
43422       attribute \src "libresoc.v:0.0-0.0"
43423       case 5'00100
43424         assign { } { }
43425         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110
43426       attribute \src "libresoc.v:0.0-0.0"
43427       case 5'10010
43428         assign { } { }
43429         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001
43430       case
43431         assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000
43432     end
43433     sync always
43434       update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0]
43435   end
43436   attribute \src "libresoc.v:29608.3-29662.6"
43437   process $proc$libresoc.v:29608$644
43438     assign { } { }
43439     assign { } { }
43440     assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0]
43441     attribute \src "libresoc.v:29609.5-29609.29"
43442     switch \initial
43443       attribute \src "libresoc.v:29609.9-29609.17"
43444       case 1'1
43445       case
43446     end
43447     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43448     switch \opcode_switch
43449       attribute \src "libresoc.v:0.0-0.0"
43450       case 5'00010
43451         assign { } { }
43452         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43453       attribute \src "libresoc.v:0.0-0.0"
43454       case 5'00001
43455         assign { } { }
43456         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43457       attribute \src "libresoc.v:0.0-0.0"
43458       case 5'01000
43459         assign { } { }
43460         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43461       attribute \src "libresoc.v:0.0-0.0"
43462       case 5'00111
43463         assign { } { }
43464         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43465       attribute \src "libresoc.v:0.0-0.0"
43466       case 5'11111
43467         assign { } { }
43468         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43469       attribute \src "libresoc.v:0.0-0.0"
43470       case 5'11110
43471         assign { } { }
43472         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43473       attribute \src "libresoc.v:0.0-0.0"
43474       case 5'00000
43475         assign { } { }
43476         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43477       attribute \src "libresoc.v:0.0-0.0"
43478       case 5'11000
43479         assign { } { }
43480         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43481       attribute \src "libresoc.v:0.0-0.0"
43482       case 5'10000
43483         assign { } { }
43484         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43485       attribute \src "libresoc.v:0.0-0.0"
43486       case 5'10101
43487         assign { } { }
43488         assign $1\dec31_dec_sub22_rsrv[0:0] 1'1
43489       attribute \src "libresoc.v:0.0-0.0"
43490       case 5'00110
43491         assign { } { }
43492         assign $1\dec31_dec_sub22_rsrv[0:0] 1'1
43493       attribute \src "libresoc.v:0.0-0.0"
43494       case 5'11100
43495         assign { } { }
43496         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43497       attribute \src "libresoc.v:0.0-0.0"
43498       case 5'10110
43499         assign { } { }
43500         assign $1\dec31_dec_sub22_rsrv[0:0] 1'1
43501       attribute \src "libresoc.v:0.0-0.0"
43502       case 5'10100
43503         assign { } { }
43504         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43505       attribute \src "libresoc.v:0.0-0.0"
43506       case 5'00100
43507         assign { } { }
43508         assign $1\dec31_dec_sub22_rsrv[0:0] 1'1
43509       attribute \src "libresoc.v:0.0-0.0"
43510       case 5'10010
43511         assign { } { }
43512         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43513       case
43514         assign $1\dec31_dec_sub22_rsrv[0:0] 1'0
43515     end
43516     sync always
43517       update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0]
43518   end
43519   attribute \src "libresoc.v:29663.3-29717.6"
43520   process $proc$libresoc.v:29663$645
43521     assign { } { }
43522     assign { } { }
43523     assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0]
43524     attribute \src "libresoc.v:29664.5-29664.29"
43525     switch \initial
43526       attribute \src "libresoc.v:29664.9-29664.17"
43527       case 1'1
43528       case
43529     end
43530     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43531     switch \opcode_switch
43532       attribute \src "libresoc.v:0.0-0.0"
43533       case 5'00010
43534         assign { } { }
43535         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43536       attribute \src "libresoc.v:0.0-0.0"
43537       case 5'00001
43538         assign { } { }
43539         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43540       attribute \src "libresoc.v:0.0-0.0"
43541       case 5'01000
43542         assign { } { }
43543         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43544       attribute \src "libresoc.v:0.0-0.0"
43545       case 5'00111
43546         assign { } { }
43547         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43548       attribute \src "libresoc.v:0.0-0.0"
43549       case 5'11111
43550         assign { } { }
43551         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43552       attribute \src "libresoc.v:0.0-0.0"
43553       case 5'11110
43554         assign { } { }
43555         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43556       attribute \src "libresoc.v:0.0-0.0"
43557       case 5'00000
43558         assign { } { }
43559         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43560       attribute \src "libresoc.v:0.0-0.0"
43561       case 5'11000
43562         assign { } { }
43563         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43564       attribute \src "libresoc.v:0.0-0.0"
43565       case 5'10000
43566         assign { } { }
43567         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43568       attribute \src "libresoc.v:0.0-0.0"
43569       case 5'10101
43570         assign { } { }
43571         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43572       attribute \src "libresoc.v:0.0-0.0"
43573       case 5'00110
43574         assign { } { }
43575         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43576       attribute \src "libresoc.v:0.0-0.0"
43577       case 5'11100
43578         assign { } { }
43579         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43580       attribute \src "libresoc.v:0.0-0.0"
43581       case 5'10110
43582         assign { } { }
43583         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43584       attribute \src "libresoc.v:0.0-0.0"
43585       case 5'10100
43586         assign { } { }
43587         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43588       attribute \src "libresoc.v:0.0-0.0"
43589       case 5'00100
43590         assign { } { }
43591         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43592       attribute \src "libresoc.v:0.0-0.0"
43593       case 5'10010
43594         assign { } { }
43595         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43596       case
43597         assign $1\dec31_dec_sub22_is_32b[0:0] 1'0
43598     end
43599     sync always
43600       update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0]
43601   end
43602   attribute \src "libresoc.v:29718.3-29772.6"
43603   process $proc$libresoc.v:29718$646
43604     assign { } { }
43605     assign { } { }
43606     assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0]
43607     attribute \src "libresoc.v:29719.5-29719.29"
43608     switch \initial
43609       attribute \src "libresoc.v:29719.9-29719.17"
43610       case 1'1
43611       case
43612     end
43613     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43614     switch \opcode_switch
43615       attribute \src "libresoc.v:0.0-0.0"
43616       case 5'00010
43617         assign { } { }
43618         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43619       attribute \src "libresoc.v:0.0-0.0"
43620       case 5'00001
43621         assign { } { }
43622         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43623       attribute \src "libresoc.v:0.0-0.0"
43624       case 5'01000
43625         assign { } { }
43626         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43627       attribute \src "libresoc.v:0.0-0.0"
43628       case 5'00111
43629         assign { } { }
43630         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43631       attribute \src "libresoc.v:0.0-0.0"
43632       case 5'11111
43633         assign { } { }
43634         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43635       attribute \src "libresoc.v:0.0-0.0"
43636       case 5'11110
43637         assign { } { }
43638         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43639       attribute \src "libresoc.v:0.0-0.0"
43640       case 5'00000
43641         assign { } { }
43642         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43643       attribute \src "libresoc.v:0.0-0.0"
43644       case 5'11000
43645         assign { } { }
43646         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43647       attribute \src "libresoc.v:0.0-0.0"
43648       case 5'10000
43649         assign { } { }
43650         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43651       attribute \src "libresoc.v:0.0-0.0"
43652       case 5'10101
43653         assign { } { }
43654         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43655       attribute \src "libresoc.v:0.0-0.0"
43656       case 5'00110
43657         assign { } { }
43658         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43659       attribute \src "libresoc.v:0.0-0.0"
43660       case 5'11100
43661         assign { } { }
43662         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43663       attribute \src "libresoc.v:0.0-0.0"
43664       case 5'10110
43665         assign { } { }
43666         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43667       attribute \src "libresoc.v:0.0-0.0"
43668       case 5'10100
43669         assign { } { }
43670         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43671       attribute \src "libresoc.v:0.0-0.0"
43672       case 5'00100
43673         assign { } { }
43674         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43675       attribute \src "libresoc.v:0.0-0.0"
43676       case 5'10010
43677         assign { } { }
43678         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43679       case
43680         assign $1\dec31_dec_sub22_sgn[0:0] 1'0
43681     end
43682     sync always
43683       update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0]
43684   end
43685   attribute \src "libresoc.v:29773.3-29827.6"
43686   process $proc$libresoc.v:29773$647
43687     assign { } { }
43688     assign { } { }
43689     assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0]
43690     attribute \src "libresoc.v:29774.5-29774.29"
43691     switch \initial
43692       attribute \src "libresoc.v:29774.9-29774.17"
43693       case 1'1
43694       case
43695     end
43696     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43697     switch \opcode_switch
43698       attribute \src "libresoc.v:0.0-0.0"
43699       case 5'00010
43700         assign { } { }
43701         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43702       attribute \src "libresoc.v:0.0-0.0"
43703       case 5'00001
43704         assign { } { }
43705         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43706       attribute \src "libresoc.v:0.0-0.0"
43707       case 5'01000
43708         assign { } { }
43709         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43710       attribute \src "libresoc.v:0.0-0.0"
43711       case 5'00111
43712         assign { } { }
43713         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43714       attribute \src "libresoc.v:0.0-0.0"
43715       case 5'11111
43716         assign { } { }
43717         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43718       attribute \src "libresoc.v:0.0-0.0"
43719       case 5'11110
43720         assign { } { }
43721         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43722       attribute \src "libresoc.v:0.0-0.0"
43723       case 5'00000
43724         assign { } { }
43725         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43726       attribute \src "libresoc.v:0.0-0.0"
43727       case 5'11000
43728         assign { } { }
43729         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43730       attribute \src "libresoc.v:0.0-0.0"
43731       case 5'10000
43732         assign { } { }
43733         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43734       attribute \src "libresoc.v:0.0-0.0"
43735       case 5'10101
43736         assign { } { }
43737         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43738       attribute \src "libresoc.v:0.0-0.0"
43739       case 5'00110
43740         assign { } { }
43741         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43742       attribute \src "libresoc.v:0.0-0.0"
43743       case 5'11100
43744         assign { } { }
43745         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43746       attribute \src "libresoc.v:0.0-0.0"
43747       case 5'10110
43748         assign { } { }
43749         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43750       attribute \src "libresoc.v:0.0-0.0"
43751       case 5'10100
43752         assign { } { }
43753         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43754       attribute \src "libresoc.v:0.0-0.0"
43755       case 5'00100
43756         assign { } { }
43757         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43758       attribute \src "libresoc.v:0.0-0.0"
43759       case 5'10010
43760         assign { } { }
43761         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43762       case
43763         assign $1\dec31_dec_sub22_lk[0:0] 1'0
43764     end
43765     sync always
43766       update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0]
43767   end
43768   attribute \src "libresoc.v:29828.3-29882.6"
43769   process $proc$libresoc.v:29828$648
43770     assign { } { }
43771     assign { } { }
43772     assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0]
43773     attribute \src "libresoc.v:29829.5-29829.29"
43774     switch \initial
43775       attribute \src "libresoc.v:29829.9-29829.17"
43776       case 1'1
43777       case
43778     end
43779     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43780     switch \opcode_switch
43781       attribute \src "libresoc.v:0.0-0.0"
43782       case 5'00010
43783         assign { } { }
43784         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43785       attribute \src "libresoc.v:0.0-0.0"
43786       case 5'00001
43787         assign { } { }
43788         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43789       attribute \src "libresoc.v:0.0-0.0"
43790       case 5'01000
43791         assign { } { }
43792         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43793       attribute \src "libresoc.v:0.0-0.0"
43794       case 5'00111
43795         assign { } { }
43796         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43797       attribute \src "libresoc.v:0.0-0.0"
43798       case 5'11111
43799         assign { } { }
43800         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0
43801       attribute \src "libresoc.v:0.0-0.0"
43802       case 5'11110
43803         assign { } { }
43804         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43805       attribute \src "libresoc.v:0.0-0.0"
43806       case 5'00000
43807         assign { } { }
43808         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43809       attribute \src "libresoc.v:0.0-0.0"
43810       case 5'11000
43811         assign { } { }
43812         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43813       attribute \src "libresoc.v:0.0-0.0"
43814       case 5'10000
43815         assign { } { }
43816         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43817       attribute \src "libresoc.v:0.0-0.0"
43818       case 5'10101
43819         assign { } { }
43820         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43821       attribute \src "libresoc.v:0.0-0.0"
43822       case 5'00110
43823         assign { } { }
43824         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43825       attribute \src "libresoc.v:0.0-0.0"
43826       case 5'11100
43827         assign { } { }
43828         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43829       attribute \src "libresoc.v:0.0-0.0"
43830       case 5'10110
43831         assign { } { }
43832         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43833       attribute \src "libresoc.v:0.0-0.0"
43834       case 5'10100
43835         assign { } { }
43836         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43837       attribute \src "libresoc.v:0.0-0.0"
43838       case 5'00100
43839         assign { } { }
43840         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43841       attribute \src "libresoc.v:0.0-0.0"
43842       case 5'10010
43843         assign { } { }
43844         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1
43845       case
43846         assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0
43847     end
43848     sync always
43849       update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0]
43850   end
43851   attribute \src "libresoc.v:29883.3-29937.6"
43852   process $proc$libresoc.v:29883$649
43853     assign { } { }
43854     assign { } { }
43855     assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0]
43856     attribute \src "libresoc.v:29884.5-29884.29"
43857     switch \initial
43858       attribute \src "libresoc.v:29884.9-29884.17"
43859       case 1'1
43860       case
43861     end
43862     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43863     switch \opcode_switch
43864       attribute \src "libresoc.v:0.0-0.0"
43865       case 5'00010
43866         assign { } { }
43867         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43868       attribute \src "libresoc.v:0.0-0.0"
43869       case 5'00001
43870         assign { } { }
43871         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43872       attribute \src "libresoc.v:0.0-0.0"
43873       case 5'01000
43874         assign { } { }
43875         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43876       attribute \src "libresoc.v:0.0-0.0"
43877       case 5'00111
43878         assign { } { }
43879         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43880       attribute \src "libresoc.v:0.0-0.0"
43881       case 5'11111
43882         assign { } { }
43883         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43884       attribute \src "libresoc.v:0.0-0.0"
43885       case 5'11110
43886         assign { } { }
43887         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43888       attribute \src "libresoc.v:0.0-0.0"
43889       case 5'00000
43890         assign { } { }
43891         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43892       attribute \src "libresoc.v:0.0-0.0"
43893       case 5'11000
43894         assign { } { }
43895         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43896       attribute \src "libresoc.v:0.0-0.0"
43897       case 5'10000
43898         assign { } { }
43899         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43900       attribute \src "libresoc.v:0.0-0.0"
43901       case 5'10101
43902         assign { } { }
43903         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43904       attribute \src "libresoc.v:0.0-0.0"
43905       case 5'00110
43906         assign { } { }
43907         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43908       attribute \src "libresoc.v:0.0-0.0"
43909       case 5'11100
43910         assign { } { }
43911         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43912       attribute \src "libresoc.v:0.0-0.0"
43913       case 5'10110
43914         assign { } { }
43915         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43916       attribute \src "libresoc.v:0.0-0.0"
43917       case 5'10100
43918         assign { } { }
43919         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43920       attribute \src "libresoc.v:0.0-0.0"
43921       case 5'00100
43922         assign { } { }
43923         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43924       attribute \src "libresoc.v:0.0-0.0"
43925       case 5'10010
43926         assign { } { }
43927         assign $1\dec31_dec_sub22_form[4:0] 5'01000
43928       case
43929         assign $1\dec31_dec_sub22_form[4:0] 5'00000
43930     end
43931     sync always
43932       update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0]
43933   end
43934   attribute \src "libresoc.v:29938.3-29992.6"
43935   process $proc$libresoc.v:29938$650
43936     assign { } { }
43937     assign { } { }
43938     assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0]
43939     attribute \src "libresoc.v:29939.5-29939.29"
43940     switch \initial
43941       attribute \src "libresoc.v:29939.9-29939.17"
43942       case 1'1
43943       case
43944     end
43945     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
43946     switch \opcode_switch
43947       attribute \src "libresoc.v:0.0-0.0"
43948       case 5'00010
43949         assign { } { }
43950         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
43951       attribute \src "libresoc.v:0.0-0.0"
43952       case 5'00001
43953         assign { } { }
43954         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
43955       attribute \src "libresoc.v:0.0-0.0"
43956       case 5'01000
43957         assign { } { }
43958         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
43959       attribute \src "libresoc.v:0.0-0.0"
43960       case 5'00111
43961         assign { } { }
43962         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
43963       attribute \src "libresoc.v:0.0-0.0"
43964       case 5'11111
43965         assign { } { }
43966         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
43967       attribute \src "libresoc.v:0.0-0.0"
43968       case 5'11110
43969         assign { } { }
43970         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
43971       attribute \src "libresoc.v:0.0-0.0"
43972       case 5'00000
43973         assign { } { }
43974         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
43975       attribute \src "libresoc.v:0.0-0.0"
43976       case 5'11000
43977         assign { } { }
43978         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
43979       attribute \src "libresoc.v:0.0-0.0"
43980       case 5'10000
43981         assign { } { }
43982         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
43983       attribute \src "libresoc.v:0.0-0.0"
43984       case 5'10101
43985         assign { } { }
43986         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
43987       attribute \src "libresoc.v:0.0-0.0"
43988       case 5'00110
43989         assign { } { }
43990         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
43991       attribute \src "libresoc.v:0.0-0.0"
43992       case 5'11100
43993         assign { } { }
43994         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
43995       attribute \src "libresoc.v:0.0-0.0"
43996       case 5'10110
43997         assign { } { }
43998         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
43999       attribute \src "libresoc.v:0.0-0.0"
44000       case 5'10100
44001         assign { } { }
44002         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
44003       attribute \src "libresoc.v:0.0-0.0"
44004       case 5'00100
44005         assign { } { }
44006         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010
44007       attribute \src "libresoc.v:0.0-0.0"
44008       case 5'10010
44009         assign { } { }
44010         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
44011       case
44012         assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000
44013     end
44014     sync always
44015       update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0]
44016   end
44017   attribute \src "libresoc.v:29993.3-30047.6"
44018   process $proc$libresoc.v:29993$651
44019     assign { } { }
44020     assign { } { }
44021     assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0]
44022     attribute \src "libresoc.v:29994.5-29994.29"
44023     switch \initial
44024       attribute \src "libresoc.v:29994.9-29994.17"
44025       case 1'1
44026       case
44027     end
44028     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44029     switch \opcode_switch
44030       attribute \src "libresoc.v:0.0-0.0"
44031       case 5'00010
44032         assign { } { }
44033         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44034       attribute \src "libresoc.v:0.0-0.0"
44035       case 5'00001
44036         assign { } { }
44037         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44038       attribute \src "libresoc.v:0.0-0.0"
44039       case 5'01000
44040         assign { } { }
44041         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44042       attribute \src "libresoc.v:0.0-0.0"
44043       case 5'00111
44044         assign { } { }
44045         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44046       attribute \src "libresoc.v:0.0-0.0"
44047       case 5'11111
44048         assign { } { }
44049         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44050       attribute \src "libresoc.v:0.0-0.0"
44051       case 5'11110
44052         assign { } { }
44053         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44054       attribute \src "libresoc.v:0.0-0.0"
44055       case 5'00000
44056         assign { } { }
44057         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44058       attribute \src "libresoc.v:0.0-0.0"
44059       case 5'11000
44060         assign { } { }
44061         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44062       attribute \src "libresoc.v:0.0-0.0"
44063       case 5'10000
44064         assign { } { }
44065         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44066       attribute \src "libresoc.v:0.0-0.0"
44067       case 5'10101
44068         assign { } { }
44069         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44070       attribute \src "libresoc.v:0.0-0.0"
44071       case 5'00110
44072         assign { } { }
44073         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44074       attribute \src "libresoc.v:0.0-0.0"
44075       case 5'11100
44076         assign { } { }
44077         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44078       attribute \src "libresoc.v:0.0-0.0"
44079       case 5'10110
44080         assign { } { }
44081         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44082       attribute \src "libresoc.v:0.0-0.0"
44083       case 5'10100
44084         assign { } { }
44085         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44086       attribute \src "libresoc.v:0.0-0.0"
44087       case 5'00100
44088         assign { } { }
44089         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001
44090       attribute \src "libresoc.v:0.0-0.0"
44091       case 5'10010
44092         assign { } { }
44093         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44094       case
44095         assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000
44096     end
44097     sync always
44098       update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0]
44099   end
44100   attribute \src "libresoc.v:30048.3-30102.6"
44101   process $proc$libresoc.v:30048$652
44102     assign { } { }
44103     assign { } { }
44104     assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0]
44105     attribute \src "libresoc.v:30049.5-30049.29"
44106     switch \initial
44107       attribute \src "libresoc.v:30049.9-30049.17"
44108       case 1'1
44109       case
44110     end
44111     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44112     switch \opcode_switch
44113       attribute \src "libresoc.v:0.0-0.0"
44114       case 5'00010
44115         assign { } { }
44116         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44117       attribute \src "libresoc.v:0.0-0.0"
44118       case 5'00001
44119         assign { } { }
44120         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44121       attribute \src "libresoc.v:0.0-0.0"
44122       case 5'01000
44123         assign { } { }
44124         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44125       attribute \src "libresoc.v:0.0-0.0"
44126       case 5'00111
44127         assign { } { }
44128         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44129       attribute \src "libresoc.v:0.0-0.0"
44130       case 5'11111
44131         assign { } { }
44132         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44133       attribute \src "libresoc.v:0.0-0.0"
44134       case 5'11110
44135         assign { } { }
44136         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44137       attribute \src "libresoc.v:0.0-0.0"
44138       case 5'00000
44139         assign { } { }
44140         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44141       attribute \src "libresoc.v:0.0-0.0"
44142       case 5'11000
44143         assign { } { }
44144         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44145       attribute \src "libresoc.v:0.0-0.0"
44146       case 5'10000
44147         assign { } { }
44148         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44149       attribute \src "libresoc.v:0.0-0.0"
44150       case 5'10101
44151         assign { } { }
44152         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01
44153       attribute \src "libresoc.v:0.0-0.0"
44154       case 5'00110
44155         assign { } { }
44156         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01
44157       attribute \src "libresoc.v:0.0-0.0"
44158       case 5'11100
44159         assign { } { }
44160         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01
44161       attribute \src "libresoc.v:0.0-0.0"
44162       case 5'10110
44163         assign { } { }
44164         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01
44165       attribute \src "libresoc.v:0.0-0.0"
44166       case 5'10100
44167         assign { } { }
44168         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01
44169       attribute \src "libresoc.v:0.0-0.0"
44170       case 5'00100
44171         assign { } { }
44172         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01
44173       attribute \src "libresoc.v:0.0-0.0"
44174       case 5'10010
44175         assign { } { }
44176         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44177       case
44178         assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00
44179     end
44180     sync always
44181       update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0]
44182   end
44183   attribute \src "libresoc.v:30103.3-30157.6"
44184   process $proc$libresoc.v:30103$653
44185     assign { } { }
44186     assign { } { }
44187     assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0]
44188     attribute \src "libresoc.v:30104.5-30104.29"
44189     switch \initial
44190       attribute \src "libresoc.v:30104.9-30104.17"
44191       case 1'1
44192       case
44193     end
44194     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44195     switch \opcode_switch
44196       attribute \src "libresoc.v:0.0-0.0"
44197       case 5'00010
44198         assign { } { }
44199         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44200       attribute \src "libresoc.v:0.0-0.0"
44201       case 5'00001
44202         assign { } { }
44203         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44204       attribute \src "libresoc.v:0.0-0.0"
44205       case 5'01000
44206         assign { } { }
44207         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44208       attribute \src "libresoc.v:0.0-0.0"
44209       case 5'00111
44210         assign { } { }
44211         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44212       attribute \src "libresoc.v:0.0-0.0"
44213       case 5'11111
44214         assign { } { }
44215         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44216       attribute \src "libresoc.v:0.0-0.0"
44217       case 5'11110
44218         assign { } { }
44219         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44220       attribute \src "libresoc.v:0.0-0.0"
44221       case 5'00000
44222         assign { } { }
44223         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44224       attribute \src "libresoc.v:0.0-0.0"
44225       case 5'11000
44226         assign { } { }
44227         assign $1\dec31_dec_sub22_out_sel[1:0] 2'01
44228       attribute \src "libresoc.v:0.0-0.0"
44229       case 5'10000
44230         assign { } { }
44231         assign $1\dec31_dec_sub22_out_sel[1:0] 2'01
44232       attribute \src "libresoc.v:0.0-0.0"
44233       case 5'10101
44234         assign { } { }
44235         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44236       attribute \src "libresoc.v:0.0-0.0"
44237       case 5'00110
44238         assign { } { }
44239         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44240       attribute \src "libresoc.v:0.0-0.0"
44241       case 5'11100
44242         assign { } { }
44243         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44244       attribute \src "libresoc.v:0.0-0.0"
44245       case 5'10110
44246         assign { } { }
44247         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44248       attribute \src "libresoc.v:0.0-0.0"
44249       case 5'10100
44250         assign { } { }
44251         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44252       attribute \src "libresoc.v:0.0-0.0"
44253       case 5'00100
44254         assign { } { }
44255         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44256       attribute \src "libresoc.v:0.0-0.0"
44257       case 5'10010
44258         assign { } { }
44259         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44260       case
44261         assign $1\dec31_dec_sub22_out_sel[1:0] 2'00
44262     end
44263     sync always
44264       update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0]
44265   end
44266   attribute \src "libresoc.v:30158.3-30212.6"
44267   process $proc$libresoc.v:30158$654
44268     assign { } { }
44269     assign { } { }
44270     assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0]
44271     attribute \src "libresoc.v:30159.5-30159.29"
44272     switch \initial
44273       attribute \src "libresoc.v:30159.9-30159.17"
44274       case 1'1
44275       case
44276     end
44277     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44278     switch \opcode_switch
44279       attribute \src "libresoc.v:0.0-0.0"
44280       case 5'00010
44281         assign { } { }
44282         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44283       attribute \src "libresoc.v:0.0-0.0"
44284       case 5'00001
44285         assign { } { }
44286         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44287       attribute \src "libresoc.v:0.0-0.0"
44288       case 5'01000
44289         assign { } { }
44290         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44291       attribute \src "libresoc.v:0.0-0.0"
44292       case 5'00111
44293         assign { } { }
44294         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44295       attribute \src "libresoc.v:0.0-0.0"
44296       case 5'11111
44297         assign { } { }
44298         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44299       attribute \src "libresoc.v:0.0-0.0"
44300       case 5'11110
44301         assign { } { }
44302         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44303       attribute \src "libresoc.v:0.0-0.0"
44304       case 5'00000
44305         assign { } { }
44306         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44307       attribute \src "libresoc.v:0.0-0.0"
44308       case 5'11000
44309         assign { } { }
44310         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44311       attribute \src "libresoc.v:0.0-0.0"
44312       case 5'10000
44313         assign { } { }
44314         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44315       attribute \src "libresoc.v:0.0-0.0"
44316       case 5'10101
44317         assign { } { }
44318         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44319       attribute \src "libresoc.v:0.0-0.0"
44320       case 5'00110
44321         assign { } { }
44322         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44323       attribute \src "libresoc.v:0.0-0.0"
44324       case 5'11100
44325         assign { } { }
44326         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44327       attribute \src "libresoc.v:0.0-0.0"
44328       case 5'10110
44329         assign { } { }
44330         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44331       attribute \src "libresoc.v:0.0-0.0"
44332       case 5'10100
44333         assign { } { }
44334         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44335       attribute \src "libresoc.v:0.0-0.0"
44336       case 5'00100
44337         assign { } { }
44338         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44339       attribute \src "libresoc.v:0.0-0.0"
44340       case 5'10010
44341         assign { } { }
44342         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44343       case
44344         assign $1\dec31_dec_sub22_cr_in[2:0] 3'000
44345     end
44346     sync always
44347       update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0]
44348   end
44349   attribute \src "libresoc.v:30213.3-30267.6"
44350   process $proc$libresoc.v:30213$655
44351     assign { } { }
44352     assign { } { }
44353     assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0]
44354     attribute \src "libresoc.v:30214.5-30214.29"
44355     switch \initial
44356       attribute \src "libresoc.v:30214.9-30214.17"
44357       case 1'1
44358       case
44359     end
44360     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44361     switch \opcode_switch
44362       attribute \src "libresoc.v:0.0-0.0"
44363       case 5'00010
44364         assign { } { }
44365         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44366       attribute \src "libresoc.v:0.0-0.0"
44367       case 5'00001
44368         assign { } { }
44369         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44370       attribute \src "libresoc.v:0.0-0.0"
44371       case 5'01000
44372         assign { } { }
44373         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44374       attribute \src "libresoc.v:0.0-0.0"
44375       case 5'00111
44376         assign { } { }
44377         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44378       attribute \src "libresoc.v:0.0-0.0"
44379       case 5'11111
44380         assign { } { }
44381         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44382       attribute \src "libresoc.v:0.0-0.0"
44383       case 5'11110
44384         assign { } { }
44385         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44386       attribute \src "libresoc.v:0.0-0.0"
44387       case 5'00000
44388         assign { } { }
44389         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44390       attribute \src "libresoc.v:0.0-0.0"
44391       case 5'11000
44392         assign { } { }
44393         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44394       attribute \src "libresoc.v:0.0-0.0"
44395       case 5'10000
44396         assign { } { }
44397         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44398       attribute \src "libresoc.v:0.0-0.0"
44399       case 5'10101
44400         assign { } { }
44401         assign $1\dec31_dec_sub22_cr_out[2:0] 3'001
44402       attribute \src "libresoc.v:0.0-0.0"
44403       case 5'00110
44404         assign { } { }
44405         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44406       attribute \src "libresoc.v:0.0-0.0"
44407       case 5'11100
44408         assign { } { }
44409         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44410       attribute \src "libresoc.v:0.0-0.0"
44411       case 5'10110
44412         assign { } { }
44413         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44414       attribute \src "libresoc.v:0.0-0.0"
44415       case 5'10100
44416         assign { } { }
44417         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44418       attribute \src "libresoc.v:0.0-0.0"
44419       case 5'00100
44420         assign { } { }
44421         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44422       attribute \src "libresoc.v:0.0-0.0"
44423       case 5'10010
44424         assign { } { }
44425         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44426       case
44427         assign $1\dec31_dec_sub22_cr_out[2:0] 3'000
44428     end
44429     sync always
44430       update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0]
44431   end
44432   connect \opcode_switch \opcode_in [10:6]
44433 end
44434 attribute \src "libresoc.v:30273.1-31708.10"
44435 attribute \cells_not_processed 1
44436 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23"
44437 attribute \generator "nMigen"
44438 module \dec31_dec_sub23
44439   attribute \src "libresoc.v:30776.3-30824.6"
44440   wire width 8 $0\dec31_dec_sub23_asmcode[7:0]
44441   attribute \src "libresoc.v:30972.3-31020.6"
44442   wire $0\dec31_dec_sub23_br[0:0]
44443   attribute \src "libresoc.v:31609.3-31657.6"
44444   wire width 3 $0\dec31_dec_sub23_cr_in[2:0]
44445   attribute \src "libresoc.v:31658.3-31706.6"
44446   wire width 3 $0\dec31_dec_sub23_cr_out[2:0]
44447   attribute \src "libresoc.v:30727.3-30775.6"
44448   wire width 2 $0\dec31_dec_sub23_cry_in[1:0]
44449   attribute \src "libresoc.v:30923.3-30971.6"
44450   wire $0\dec31_dec_sub23_cry_out[0:0]
44451   attribute \src "libresoc.v:31364.3-31412.6"
44452   wire width 5 $0\dec31_dec_sub23_form[4:0]
44453   attribute \src "libresoc.v:30531.3-30579.6"
44454   wire width 12 $0\dec31_dec_sub23_function_unit[11:0]
44455   attribute \src "libresoc.v:31413.3-31461.6"
44456   wire width 3 $0\dec31_dec_sub23_in1_sel[2:0]
44457   attribute \src "libresoc.v:31462.3-31510.6"
44458   wire width 4 $0\dec31_dec_sub23_in2_sel[3:0]
44459   attribute \src "libresoc.v:31511.3-31559.6"
44460   wire width 2 $0\dec31_dec_sub23_in3_sel[1:0]
44461   attribute \src "libresoc.v:31070.3-31118.6"
44462   wire width 7 $0\dec31_dec_sub23_internal_op[6:0]
44463   attribute \src "libresoc.v:30825.3-30873.6"
44464   wire $0\dec31_dec_sub23_inv_a[0:0]
44465   attribute \src "libresoc.v:30874.3-30922.6"
44466   wire $0\dec31_dec_sub23_inv_out[0:0]
44467   attribute \src "libresoc.v:31168.3-31216.6"
44468   wire $0\dec31_dec_sub23_is_32b[0:0]
44469   attribute \src "libresoc.v:30580.3-30628.6"
44470   wire width 4 $0\dec31_dec_sub23_ldst_len[3:0]
44471   attribute \src "libresoc.v:31266.3-31314.6"
44472   wire $0\dec31_dec_sub23_lk[0:0]
44473   attribute \src "libresoc.v:31560.3-31608.6"
44474   wire width 2 $0\dec31_dec_sub23_out_sel[1:0]
44475   attribute \src "libresoc.v:30678.3-30726.6"
44476   wire width 2 $0\dec31_dec_sub23_rc_sel[1:0]
44477   attribute \src "libresoc.v:31119.3-31167.6"
44478   wire $0\dec31_dec_sub23_rsrv[0:0]
44479   attribute \src "libresoc.v:31315.3-31363.6"
44480   wire $0\dec31_dec_sub23_sgl_pipe[0:0]
44481   attribute \src "libresoc.v:31217.3-31265.6"
44482   wire $0\dec31_dec_sub23_sgn[0:0]
44483   attribute \src "libresoc.v:31021.3-31069.6"
44484   wire $0\dec31_dec_sub23_sgn_ext[0:0]
44485   attribute \src "libresoc.v:30629.3-30677.6"
44486   wire width 2 $0\dec31_dec_sub23_upd[1:0]
44487   attribute \src "libresoc.v:30274.7-30274.20"
44488   wire $0\initial[0:0]
44489   attribute \src "libresoc.v:30776.3-30824.6"
44490   wire width 8 $1\dec31_dec_sub23_asmcode[7:0]
44491   attribute \src "libresoc.v:30972.3-31020.6"
44492   wire $1\dec31_dec_sub23_br[0:0]
44493   attribute \src "libresoc.v:31609.3-31657.6"
44494   wire width 3 $1\dec31_dec_sub23_cr_in[2:0]
44495   attribute \src "libresoc.v:31658.3-31706.6"
44496   wire width 3 $1\dec31_dec_sub23_cr_out[2:0]
44497   attribute \src "libresoc.v:30727.3-30775.6"
44498   wire width 2 $1\dec31_dec_sub23_cry_in[1:0]
44499   attribute \src "libresoc.v:30923.3-30971.6"
44500   wire $1\dec31_dec_sub23_cry_out[0:0]
44501   attribute \src "libresoc.v:31364.3-31412.6"
44502   wire width 5 $1\dec31_dec_sub23_form[4:0]
44503   attribute \src "libresoc.v:30531.3-30579.6"
44504   wire width 12 $1\dec31_dec_sub23_function_unit[11:0]
44505   attribute \src "libresoc.v:31413.3-31461.6"
44506   wire width 3 $1\dec31_dec_sub23_in1_sel[2:0]
44507   attribute \src "libresoc.v:31462.3-31510.6"
44508   wire width 4 $1\dec31_dec_sub23_in2_sel[3:0]
44509   attribute \src "libresoc.v:31511.3-31559.6"
44510   wire width 2 $1\dec31_dec_sub23_in3_sel[1:0]
44511   attribute \src "libresoc.v:31070.3-31118.6"
44512   wire width 7 $1\dec31_dec_sub23_internal_op[6:0]
44513   attribute \src "libresoc.v:30825.3-30873.6"
44514   wire $1\dec31_dec_sub23_inv_a[0:0]
44515   attribute \src "libresoc.v:30874.3-30922.6"
44516   wire $1\dec31_dec_sub23_inv_out[0:0]
44517   attribute \src "libresoc.v:31168.3-31216.6"
44518   wire $1\dec31_dec_sub23_is_32b[0:0]
44519   attribute \src "libresoc.v:30580.3-30628.6"
44520   wire width 4 $1\dec31_dec_sub23_ldst_len[3:0]
44521   attribute \src "libresoc.v:31266.3-31314.6"
44522   wire $1\dec31_dec_sub23_lk[0:0]
44523   attribute \src "libresoc.v:31560.3-31608.6"
44524   wire width 2 $1\dec31_dec_sub23_out_sel[1:0]
44525   attribute \src "libresoc.v:30678.3-30726.6"
44526   wire width 2 $1\dec31_dec_sub23_rc_sel[1:0]
44527   attribute \src "libresoc.v:31119.3-31167.6"
44528   wire $1\dec31_dec_sub23_rsrv[0:0]
44529   attribute \src "libresoc.v:31315.3-31363.6"
44530   wire $1\dec31_dec_sub23_sgl_pipe[0:0]
44531   attribute \src "libresoc.v:31217.3-31265.6"
44532   wire $1\dec31_dec_sub23_sgn[0:0]
44533   attribute \src "libresoc.v:31021.3-31069.6"
44534   wire $1\dec31_dec_sub23_sgn_ext[0:0]
44535   attribute \src "libresoc.v:30629.3-30677.6"
44536   wire width 2 $1\dec31_dec_sub23_upd[1:0]
44537   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44538   wire width 8 output 4 \dec31_dec_sub23_asmcode
44539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44540   wire output 18 \dec31_dec_sub23_br
44541   attribute \enum_base_type "CRInSel"
44542   attribute \enum_value_000 "NONE"
44543   attribute \enum_value_001 "CR0"
44544   attribute \enum_value_010 "BI"
44545   attribute \enum_value_011 "BFA"
44546   attribute \enum_value_100 "BA_BB"
44547   attribute \enum_value_101 "BC"
44548   attribute \enum_value_110 "WHOLE_REG"
44549   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44550   wire width 3 output 9 \dec31_dec_sub23_cr_in
44551   attribute \enum_base_type "CROutSel"
44552   attribute \enum_value_000 "NONE"
44553   attribute \enum_value_001 "CR0"
44554   attribute \enum_value_010 "BF"
44555   attribute \enum_value_011 "BT"
44556   attribute \enum_value_100 "WHOLE_REG"
44557   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44558   wire width 3 output 10 \dec31_dec_sub23_cr_out
44559   attribute \enum_base_type "CryIn"
44560   attribute \enum_value_00 "ZERO"
44561   attribute \enum_value_01 "ONE"
44562   attribute \enum_value_10 "CA"
44563   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44564   wire width 2 output 14 \dec31_dec_sub23_cry_in
44565   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44566   wire output 17 \dec31_dec_sub23_cry_out
44567   attribute \enum_base_type "Form"
44568   attribute \enum_value_00000 "NONE"
44569   attribute \enum_value_00001 "I"
44570   attribute \enum_value_00010 "B"
44571   attribute \enum_value_00011 "SC"
44572   attribute \enum_value_00100 "D"
44573   attribute \enum_value_00101 "DS"
44574   attribute \enum_value_00110 "DQ"
44575   attribute \enum_value_00111 "DX"
44576   attribute \enum_value_01000 "X"
44577   attribute \enum_value_01001 "XL"
44578   attribute \enum_value_01010 "XFX"
44579   attribute \enum_value_01011 "XFL"
44580   attribute \enum_value_01100 "XX1"
44581   attribute \enum_value_01101 "XX2"
44582   attribute \enum_value_01110 "XX3"
44583   attribute \enum_value_01111 "XX4"
44584   attribute \enum_value_10000 "XS"
44585   attribute \enum_value_10001 "XO"
44586   attribute \enum_value_10010 "A"
44587   attribute \enum_value_10011 "M"
44588   attribute \enum_value_10100 "MD"
44589   attribute \enum_value_10101 "MDS"
44590   attribute \enum_value_10110 "VA"
44591   attribute \enum_value_10111 "VC"
44592   attribute \enum_value_11000 "VX"
44593   attribute \enum_value_11001 "EVX"
44594   attribute \enum_value_11010 "EVS"
44595   attribute \enum_value_11011 "Z22"
44596   attribute \enum_value_11100 "Z23"
44597   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44598   wire width 5 output 3 \dec31_dec_sub23_form
44599   attribute \enum_base_type "Function"
44600   attribute \enum_value_000000000000 "NONE"
44601   attribute \enum_value_000000000010 "ALU"
44602   attribute \enum_value_000000000100 "LDST"
44603   attribute \enum_value_000000001000 "SHIFT_ROT"
44604   attribute \enum_value_000000010000 "LOGICAL"
44605   attribute \enum_value_000000100000 "BRANCH"
44606   attribute \enum_value_000001000000 "CR"
44607   attribute \enum_value_000010000000 "TRAP"
44608   attribute \enum_value_000100000000 "MUL"
44609   attribute \enum_value_001000000000 "DIV"
44610   attribute \enum_value_010000000000 "SPR"
44611   attribute \enum_value_100000000000 "MMU"
44612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44613   wire width 12 output 1 \dec31_dec_sub23_function_unit
44614   attribute \enum_base_type "In1Sel"
44615   attribute \enum_value_000 "NONE"
44616   attribute \enum_value_001 "RA"
44617   attribute \enum_value_010 "RA_OR_ZERO"
44618   attribute \enum_value_011 "SPR"
44619   attribute \enum_value_100 "RS"
44620   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44621   wire width 3 output 5 \dec31_dec_sub23_in1_sel
44622   attribute \enum_base_type "In2Sel"
44623   attribute \enum_value_0000 "NONE"
44624   attribute \enum_value_0001 "RB"
44625   attribute \enum_value_0010 "CONST_UI"
44626   attribute \enum_value_0011 "CONST_SI"
44627   attribute \enum_value_0100 "CONST_UI_HI"
44628   attribute \enum_value_0101 "CONST_SI_HI"
44629   attribute \enum_value_0110 "CONST_LI"
44630   attribute \enum_value_0111 "CONST_BD"
44631   attribute \enum_value_1000 "CONST_DS"
44632   attribute \enum_value_1001 "CONST_M1"
44633   attribute \enum_value_1010 "CONST_SH"
44634   attribute \enum_value_1011 "CONST_SH32"
44635   attribute \enum_value_1100 "SPR"
44636   attribute \enum_value_1101 "RS"
44637   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44638   wire width 4 output 6 \dec31_dec_sub23_in2_sel
44639   attribute \enum_base_type "In3Sel"
44640   attribute \enum_value_00 "NONE"
44641   attribute \enum_value_01 "RS"
44642   attribute \enum_value_10 "RB"
44643   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44644   wire width 2 output 7 \dec31_dec_sub23_in3_sel
44645   attribute \enum_base_type "MicrOp"
44646   attribute \enum_value_0000000 "OP_ILLEGAL"
44647   attribute \enum_value_0000001 "OP_NOP"
44648   attribute \enum_value_0000010 "OP_ADD"
44649   attribute \enum_value_0000011 "OP_ADDPCIS"
44650   attribute \enum_value_0000100 "OP_AND"
44651   attribute \enum_value_0000101 "OP_ATTN"
44652   attribute \enum_value_0000110 "OP_B"
44653   attribute \enum_value_0000111 "OP_BC"
44654   attribute \enum_value_0001000 "OP_BCREG"
44655   attribute \enum_value_0001001 "OP_BPERM"
44656   attribute \enum_value_0001010 "OP_CMP"
44657   attribute \enum_value_0001011 "OP_CMPB"
44658   attribute \enum_value_0001100 "OP_CMPEQB"
44659   attribute \enum_value_0001101 "OP_CMPRB"
44660   attribute \enum_value_0001110 "OP_CNTZ"
44661   attribute \enum_value_0001111 "OP_CRAND"
44662   attribute \enum_value_0010000 "OP_CRANDC"
44663   attribute \enum_value_0010001 "OP_CREQV"
44664   attribute \enum_value_0010010 "OP_CRNAND"
44665   attribute \enum_value_0010011 "OP_CRNOR"
44666   attribute \enum_value_0010100 "OP_CROR"
44667   attribute \enum_value_0010101 "OP_CRORC"
44668   attribute \enum_value_0010110 "OP_CRXOR"
44669   attribute \enum_value_0010111 "OP_DARN"
44670   attribute \enum_value_0011000 "OP_DCBF"
44671   attribute \enum_value_0011001 "OP_DCBST"
44672   attribute \enum_value_0011010 "OP_DCBT"
44673   attribute \enum_value_0011011 "OP_DCBTST"
44674   attribute \enum_value_0011100 "OP_DCBZ"
44675   attribute \enum_value_0011101 "OP_DIV"
44676   attribute \enum_value_0011110 "OP_DIVE"
44677   attribute \enum_value_0011111 "OP_EXTS"
44678   attribute \enum_value_0100000 "OP_EXTSWSLI"
44679   attribute \enum_value_0100001 "OP_ICBI"
44680   attribute \enum_value_0100010 "OP_ICBT"
44681   attribute \enum_value_0100011 "OP_ISEL"
44682   attribute \enum_value_0100100 "OP_ISYNC"
44683   attribute \enum_value_0100101 "OP_LOAD"
44684   attribute \enum_value_0100110 "OP_STORE"
44685   attribute \enum_value_0100111 "OP_MADDHD"
44686   attribute \enum_value_0101000 "OP_MADDHDU"
44687   attribute \enum_value_0101001 "OP_MADDLD"
44688   attribute \enum_value_0101010 "OP_MCRF"
44689   attribute \enum_value_0101011 "OP_MCRXR"
44690   attribute \enum_value_0101100 "OP_MCRXRX"
44691   attribute \enum_value_0101101 "OP_MFCR"
44692   attribute \enum_value_0101110 "OP_MFSPR"
44693   attribute \enum_value_0101111 "OP_MOD"
44694   attribute \enum_value_0110000 "OP_MTCRF"
44695   attribute \enum_value_0110001 "OP_MTSPR"
44696   attribute \enum_value_0110010 "OP_MUL_L64"
44697   attribute \enum_value_0110011 "OP_MUL_H64"
44698   attribute \enum_value_0110100 "OP_MUL_H32"
44699   attribute \enum_value_0110101 "OP_OR"
44700   attribute \enum_value_0110110 "OP_POPCNT"
44701   attribute \enum_value_0110111 "OP_PRTY"
44702   attribute \enum_value_0111000 "OP_RLC"
44703   attribute \enum_value_0111001 "OP_RLCL"
44704   attribute \enum_value_0111010 "OP_RLCR"
44705   attribute \enum_value_0111011 "OP_SETB"
44706   attribute \enum_value_0111100 "OP_SHL"
44707   attribute \enum_value_0111101 "OP_SHR"
44708   attribute \enum_value_0111110 "OP_SYNC"
44709   attribute \enum_value_0111111 "OP_TRAP"
44710   attribute \enum_value_1000011 "OP_XOR"
44711   attribute \enum_value_1000100 "OP_SIM_CONFIG"
44712   attribute \enum_value_1000101 "OP_CROP"
44713   attribute \enum_value_1000110 "OP_RFID"
44714   attribute \enum_value_1000111 "OP_MFMSR"
44715   attribute \enum_value_1001000 "OP_MTMSRD"
44716   attribute \enum_value_1001001 "OP_SC"
44717   attribute \enum_value_1001010 "OP_MTMSR"
44718   attribute \enum_value_1001011 "OP_TLBIE"
44719   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44720   wire width 7 output 2 \dec31_dec_sub23_internal_op
44721   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44722   wire output 15 \dec31_dec_sub23_inv_a
44723   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44724   wire output 16 \dec31_dec_sub23_inv_out
44725   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44726   wire output 21 \dec31_dec_sub23_is_32b
44727   attribute \enum_base_type "LdstLen"
44728   attribute \enum_value_0000 "NONE"
44729   attribute \enum_value_0001 "is1B"
44730   attribute \enum_value_0010 "is2B"
44731   attribute \enum_value_0100 "is4B"
44732   attribute \enum_value_1000 "is8B"
44733   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44734   wire width 4 output 11 \dec31_dec_sub23_ldst_len
44735   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44736   wire output 23 \dec31_dec_sub23_lk
44737   attribute \enum_base_type "OutSel"
44738   attribute \enum_value_00 "NONE"
44739   attribute \enum_value_01 "RT"
44740   attribute \enum_value_10 "RA"
44741   attribute \enum_value_11 "SPR"
44742   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44743   wire width 2 output 8 \dec31_dec_sub23_out_sel
44744   attribute \enum_base_type "RC"
44745   attribute \enum_value_00 "NONE"
44746   attribute \enum_value_01 "ONE"
44747   attribute \enum_value_10 "RC"
44748   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44749   wire width 2 output 13 \dec31_dec_sub23_rc_sel
44750   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44751   wire output 20 \dec31_dec_sub23_rsrv
44752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44753   wire output 24 \dec31_dec_sub23_sgl_pipe
44754   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44755   wire output 22 \dec31_dec_sub23_sgn
44756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
44757   wire output 19 \dec31_dec_sub23_sgn_ext
44758   attribute \enum_base_type "LDSTMode"
44759   attribute \enum_value_00 "NONE"
44760   attribute \enum_value_01 "update"
44761   attribute \enum_value_10 "cix"
44762   attribute \enum_value_11 "cx"
44763   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
44764   wire width 2 output 12 \dec31_dec_sub23_upd
44765   attribute \src "libresoc.v:30274.7-30274.15"
44766   wire \initial
44767   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
44768   wire width 32 input 25 \opcode_in
44769   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
44770   wire width 5 \opcode_switch
44771   attribute \src "libresoc.v:30274.7-30274.20"
44772   process $proc$libresoc.v:30274$681
44773     assign { } { }
44774     assign $0\initial[0:0] 1'0
44775     sync always
44776       update \initial $0\initial[0:0]
44777     sync init
44778   end
44779   attribute \src "libresoc.v:30531.3-30579.6"
44780   process $proc$libresoc.v:30531$657
44781     assign { } { }
44782     assign { } { }
44783     assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0]
44784     attribute \src "libresoc.v:30532.5-30532.29"
44785     switch \initial
44786       attribute \src "libresoc.v:30532.9-30532.17"
44787       case 1'1
44788       case
44789     end
44790     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44791     switch \opcode_switch
44792       attribute \src "libresoc.v:0.0-0.0"
44793       case 5'00011
44794         assign { } { }
44795         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44796       attribute \src "libresoc.v:0.0-0.0"
44797       case 5'00010
44798         assign { } { }
44799         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44800       attribute \src "libresoc.v:0.0-0.0"
44801       case 5'01011
44802         assign { } { }
44803         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44804       attribute \src "libresoc.v:0.0-0.0"
44805       case 5'01010
44806         assign { } { }
44807         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44808       attribute \src "libresoc.v:0.0-0.0"
44809       case 5'01001
44810         assign { } { }
44811         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44812       attribute \src "libresoc.v:0.0-0.0"
44813       case 5'01000
44814         assign { } { }
44815         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44816       attribute \src "libresoc.v:0.0-0.0"
44817       case 5'00001
44818         assign { } { }
44819         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44820       attribute \src "libresoc.v:0.0-0.0"
44821       case 5'00000
44822         assign { } { }
44823         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44824       attribute \src "libresoc.v:0.0-0.0"
44825       case 5'00111
44826         assign { } { }
44827         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44828       attribute \src "libresoc.v:0.0-0.0"
44829       case 5'00110
44830         assign { } { }
44831         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44832       attribute \src "libresoc.v:0.0-0.0"
44833       case 5'01101
44834         assign { } { }
44835         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44836       attribute \src "libresoc.v:0.0-0.0"
44837       case 5'01100
44838         assign { } { }
44839         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44840       attribute \src "libresoc.v:0.0-0.0"
44841       case 5'00101
44842         assign { } { }
44843         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44844       attribute \src "libresoc.v:0.0-0.0"
44845       case 5'00100
44846         assign { } { }
44847         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100
44848       case
44849         assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000
44850     end
44851     sync always
44852       update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0]
44853   end
44854   attribute \src "libresoc.v:30580.3-30628.6"
44855   process $proc$libresoc.v:30580$658
44856     assign { } { }
44857     assign { } { }
44858     assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0]
44859     attribute \src "libresoc.v:30581.5-30581.29"
44860     switch \initial
44861       attribute \src "libresoc.v:30581.9-30581.17"
44862       case 1'1
44863       case
44864     end
44865     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44866     switch \opcode_switch
44867       attribute \src "libresoc.v:0.0-0.0"
44868       case 5'00011
44869         assign { } { }
44870         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001
44871       attribute \src "libresoc.v:0.0-0.0"
44872       case 5'00010
44873         assign { } { }
44874         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001
44875       attribute \src "libresoc.v:0.0-0.0"
44876       case 5'01011
44877         assign { } { }
44878         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010
44879       attribute \src "libresoc.v:0.0-0.0"
44880       case 5'01010
44881         assign { } { }
44882         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010
44883       attribute \src "libresoc.v:0.0-0.0"
44884       case 5'01001
44885         assign { } { }
44886         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010
44887       attribute \src "libresoc.v:0.0-0.0"
44888       case 5'01000
44889         assign { } { }
44890         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010
44891       attribute \src "libresoc.v:0.0-0.0"
44892       case 5'00001
44893         assign { } { }
44894         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100
44895       attribute \src "libresoc.v:0.0-0.0"
44896       case 5'00000
44897         assign { } { }
44898         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100
44899       attribute \src "libresoc.v:0.0-0.0"
44900       case 5'00111
44901         assign { } { }
44902         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001
44903       attribute \src "libresoc.v:0.0-0.0"
44904       case 5'00110
44905         assign { } { }
44906         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001
44907       attribute \src "libresoc.v:0.0-0.0"
44908       case 5'01101
44909         assign { } { }
44910         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010
44911       attribute \src "libresoc.v:0.0-0.0"
44912       case 5'01100
44913         assign { } { }
44914         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010
44915       attribute \src "libresoc.v:0.0-0.0"
44916       case 5'00101
44917         assign { } { }
44918         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100
44919       attribute \src "libresoc.v:0.0-0.0"
44920       case 5'00100
44921         assign { } { }
44922         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100
44923       case
44924         assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000
44925     end
44926     sync always
44927       update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0]
44928   end
44929   attribute \src "libresoc.v:30629.3-30677.6"
44930   process $proc$libresoc.v:30629$659
44931     assign { } { }
44932     assign { } { }
44933     assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0]
44934     attribute \src "libresoc.v:30630.5-30630.29"
44935     switch \initial
44936       attribute \src "libresoc.v:30630.9-30630.17"
44937       case 1'1
44938       case
44939     end
44940     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
44941     switch \opcode_switch
44942       attribute \src "libresoc.v:0.0-0.0"
44943       case 5'00011
44944         assign { } { }
44945         assign $1\dec31_dec_sub23_upd[1:0] 2'01
44946       attribute \src "libresoc.v:0.0-0.0"
44947       case 5'00010
44948         assign { } { }
44949         assign $1\dec31_dec_sub23_upd[1:0] 2'00
44950       attribute \src "libresoc.v:0.0-0.0"
44951       case 5'01011
44952         assign { } { }
44953         assign $1\dec31_dec_sub23_upd[1:0] 2'01
44954       attribute \src "libresoc.v:0.0-0.0"
44955       case 5'01010
44956         assign { } { }
44957         assign $1\dec31_dec_sub23_upd[1:0] 2'00
44958       attribute \src "libresoc.v:0.0-0.0"
44959       case 5'01001
44960         assign { } { }
44961         assign $1\dec31_dec_sub23_upd[1:0] 2'01
44962       attribute \src "libresoc.v:0.0-0.0"
44963       case 5'01000
44964         assign { } { }
44965         assign $1\dec31_dec_sub23_upd[1:0] 2'00
44966       attribute \src "libresoc.v:0.0-0.0"
44967       case 5'00001
44968         assign { } { }
44969         assign $1\dec31_dec_sub23_upd[1:0] 2'01
44970       attribute \src "libresoc.v:0.0-0.0"
44971       case 5'00000
44972         assign { } { }
44973         assign $1\dec31_dec_sub23_upd[1:0] 2'00
44974       attribute \src "libresoc.v:0.0-0.0"
44975       case 5'00111
44976         assign { } { }
44977         assign $1\dec31_dec_sub23_upd[1:0] 2'01
44978       attribute \src "libresoc.v:0.0-0.0"
44979       case 5'00110
44980         assign { } { }
44981         assign $1\dec31_dec_sub23_upd[1:0] 2'00
44982       attribute \src "libresoc.v:0.0-0.0"
44983       case 5'01101
44984         assign { } { }
44985         assign $1\dec31_dec_sub23_upd[1:0] 2'01
44986       attribute \src "libresoc.v:0.0-0.0"
44987       case 5'01100
44988         assign { } { }
44989         assign $1\dec31_dec_sub23_upd[1:0] 2'00
44990       attribute \src "libresoc.v:0.0-0.0"
44991       case 5'00101
44992         assign { } { }
44993         assign $1\dec31_dec_sub23_upd[1:0] 2'01
44994       attribute \src "libresoc.v:0.0-0.0"
44995       case 5'00100
44996         assign { } { }
44997         assign $1\dec31_dec_sub23_upd[1:0] 2'00
44998       case
44999         assign $1\dec31_dec_sub23_upd[1:0] 2'00
45000     end
45001     sync always
45002       update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0]
45003   end
45004   attribute \src "libresoc.v:30678.3-30726.6"
45005   process $proc$libresoc.v:30678$660
45006     assign { } { }
45007     assign { } { }
45008     assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0]
45009     attribute \src "libresoc.v:30679.5-30679.29"
45010     switch \initial
45011       attribute \src "libresoc.v:30679.9-30679.17"
45012       case 1'1
45013       case
45014     end
45015     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45016     switch \opcode_switch
45017       attribute \src "libresoc.v:0.0-0.0"
45018       case 5'00011
45019         assign { } { }
45020         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45021       attribute \src "libresoc.v:0.0-0.0"
45022       case 5'00010
45023         assign { } { }
45024         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45025       attribute \src "libresoc.v:0.0-0.0"
45026       case 5'01011
45027         assign { } { }
45028         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45029       attribute \src "libresoc.v:0.0-0.0"
45030       case 5'01010
45031         assign { } { }
45032         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45033       attribute \src "libresoc.v:0.0-0.0"
45034       case 5'01001
45035         assign { } { }
45036         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45037       attribute \src "libresoc.v:0.0-0.0"
45038       case 5'01000
45039         assign { } { }
45040         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45041       attribute \src "libresoc.v:0.0-0.0"
45042       case 5'00001
45043         assign { } { }
45044         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45045       attribute \src "libresoc.v:0.0-0.0"
45046       case 5'00000
45047         assign { } { }
45048         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45049       attribute \src "libresoc.v:0.0-0.0"
45050       case 5'00111
45051         assign { } { }
45052         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10
45053       attribute \src "libresoc.v:0.0-0.0"
45054       case 5'00110
45055         assign { } { }
45056         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10
45057       attribute \src "libresoc.v:0.0-0.0"
45058       case 5'01101
45059         assign { } { }
45060         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45061       attribute \src "libresoc.v:0.0-0.0"
45062       case 5'01100
45063         assign { } { }
45064         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45065       attribute \src "libresoc.v:0.0-0.0"
45066       case 5'00101
45067         assign { } { }
45068         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45069       attribute \src "libresoc.v:0.0-0.0"
45070       case 5'00100
45071         assign { } { }
45072         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45073       case
45074         assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00
45075     end
45076     sync always
45077       update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0]
45078   end
45079   attribute \src "libresoc.v:30727.3-30775.6"
45080   process $proc$libresoc.v:30727$661
45081     assign { } { }
45082     assign { } { }
45083     assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0]
45084     attribute \src "libresoc.v:30728.5-30728.29"
45085     switch \initial
45086       attribute \src "libresoc.v:30728.9-30728.17"
45087       case 1'1
45088       case
45089     end
45090     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45091     switch \opcode_switch
45092       attribute \src "libresoc.v:0.0-0.0"
45093       case 5'00011
45094         assign { } { }
45095         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45096       attribute \src "libresoc.v:0.0-0.0"
45097       case 5'00010
45098         assign { } { }
45099         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45100       attribute \src "libresoc.v:0.0-0.0"
45101       case 5'01011
45102         assign { } { }
45103         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45104       attribute \src "libresoc.v:0.0-0.0"
45105       case 5'01010
45106         assign { } { }
45107         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45108       attribute \src "libresoc.v:0.0-0.0"
45109       case 5'01001
45110         assign { } { }
45111         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45112       attribute \src "libresoc.v:0.0-0.0"
45113       case 5'01000
45114         assign { } { }
45115         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45116       attribute \src "libresoc.v:0.0-0.0"
45117       case 5'00001
45118         assign { } { }
45119         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45120       attribute \src "libresoc.v:0.0-0.0"
45121       case 5'00000
45122         assign { } { }
45123         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45124       attribute \src "libresoc.v:0.0-0.0"
45125       case 5'00111
45126         assign { } { }
45127         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45128       attribute \src "libresoc.v:0.0-0.0"
45129       case 5'00110
45130         assign { } { }
45131         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45132       attribute \src "libresoc.v:0.0-0.0"
45133       case 5'01101
45134         assign { } { }
45135         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45136       attribute \src "libresoc.v:0.0-0.0"
45137       case 5'01100
45138         assign { } { }
45139         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45140       attribute \src "libresoc.v:0.0-0.0"
45141       case 5'00101
45142         assign { } { }
45143         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45144       attribute \src "libresoc.v:0.0-0.0"
45145       case 5'00100
45146         assign { } { }
45147         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45148       case
45149         assign $1\dec31_dec_sub23_cry_in[1:0] 2'00
45150     end
45151     sync always
45152       update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0]
45153   end
45154   attribute \src "libresoc.v:30776.3-30824.6"
45155   process $proc$libresoc.v:30776$662
45156     assign { } { }
45157     assign { } { }
45158     assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0]
45159     attribute \src "libresoc.v:30777.5-30777.29"
45160     switch \initial
45161       attribute \src "libresoc.v:30777.9-30777.17"
45162       case 1'1
45163       case
45164     end
45165     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45166     switch \opcode_switch
45167       attribute \src "libresoc.v:0.0-0.0"
45168       case 5'00011
45169         assign { } { }
45170         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000
45171       attribute \src "libresoc.v:0.0-0.0"
45172       case 5'00010
45173         assign { } { }
45174         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001
45175       attribute \src "libresoc.v:0.0-0.0"
45176       case 5'01011
45177         assign { } { }
45178         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011
45179       attribute \src "libresoc.v:0.0-0.0"
45180       case 5'01010
45181         assign { } { }
45182         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100
45183       attribute \src "libresoc.v:0.0-0.0"
45184       case 5'01001
45185         assign { } { }
45186         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000
45187       attribute \src "libresoc.v:0.0-0.0"
45188       case 5'01000
45189         assign { } { }
45190         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001
45191       attribute \src "libresoc.v:0.0-0.0"
45192       case 5'00001
45193         assign { } { }
45194         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010
45195       attribute \src "libresoc.v:0.0-0.0"
45196       case 5'00000
45197         assign { } { }
45198         assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011
45199       attribute \src "libresoc.v:0.0-0.0"
45200       case 5'00111
45201         assign { } { }
45202         assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010
45203       attribute \src "libresoc.v:0.0-0.0"
45204       case 5'00110
45205         assign { } { }
45206         assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011
45207       attribute \src "libresoc.v:0.0-0.0"
45208       case 5'01101
45209         assign { } { }
45210         assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110
45211       attribute \src "libresoc.v:0.0-0.0"
45212       case 5'01100
45213         assign { } { }
45214         assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111
45215       attribute \src "libresoc.v:0.0-0.0"
45216       case 5'00101
45217         assign { } { }
45218         assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100
45219       attribute \src "libresoc.v:0.0-0.0"
45220       case 5'00100
45221         assign { } { }
45222         assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101
45223       case
45224         assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000
45225     end
45226     sync always
45227       update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0]
45228   end
45229   attribute \src "libresoc.v:30825.3-30873.6"
45230   process $proc$libresoc.v:30825$663
45231     assign { } { }
45232     assign { } { }
45233     assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0]
45234     attribute \src "libresoc.v:30826.5-30826.29"
45235     switch \initial
45236       attribute \src "libresoc.v:30826.9-30826.17"
45237       case 1'1
45238       case
45239     end
45240     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45241     switch \opcode_switch
45242       attribute \src "libresoc.v:0.0-0.0"
45243       case 5'00011
45244         assign { } { }
45245         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45246       attribute \src "libresoc.v:0.0-0.0"
45247       case 5'00010
45248         assign { } { }
45249         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45250       attribute \src "libresoc.v:0.0-0.0"
45251       case 5'01011
45252         assign { } { }
45253         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45254       attribute \src "libresoc.v:0.0-0.0"
45255       case 5'01010
45256         assign { } { }
45257         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45258       attribute \src "libresoc.v:0.0-0.0"
45259       case 5'01001
45260         assign { } { }
45261         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45262       attribute \src "libresoc.v:0.0-0.0"
45263       case 5'01000
45264         assign { } { }
45265         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45266       attribute \src "libresoc.v:0.0-0.0"
45267       case 5'00001
45268         assign { } { }
45269         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45270       attribute \src "libresoc.v:0.0-0.0"
45271       case 5'00000
45272         assign { } { }
45273         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45274       attribute \src "libresoc.v:0.0-0.0"
45275       case 5'00111
45276         assign { } { }
45277         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45278       attribute \src "libresoc.v:0.0-0.0"
45279       case 5'00110
45280         assign { } { }
45281         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45282       attribute \src "libresoc.v:0.0-0.0"
45283       case 5'01101
45284         assign { } { }
45285         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45286       attribute \src "libresoc.v:0.0-0.0"
45287       case 5'01100
45288         assign { } { }
45289         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45290       attribute \src "libresoc.v:0.0-0.0"
45291       case 5'00101
45292         assign { } { }
45293         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45294       attribute \src "libresoc.v:0.0-0.0"
45295       case 5'00100
45296         assign { } { }
45297         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45298       case
45299         assign $1\dec31_dec_sub23_inv_a[0:0] 1'0
45300     end
45301     sync always
45302       update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0]
45303   end
45304   attribute \src "libresoc.v:30874.3-30922.6"
45305   process $proc$libresoc.v:30874$664
45306     assign { } { }
45307     assign { } { }
45308     assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0]
45309     attribute \src "libresoc.v:30875.5-30875.29"
45310     switch \initial
45311       attribute \src "libresoc.v:30875.9-30875.17"
45312       case 1'1
45313       case
45314     end
45315     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45316     switch \opcode_switch
45317       attribute \src "libresoc.v:0.0-0.0"
45318       case 5'00011
45319         assign { } { }
45320         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45321       attribute \src "libresoc.v:0.0-0.0"
45322       case 5'00010
45323         assign { } { }
45324         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45325       attribute \src "libresoc.v:0.0-0.0"
45326       case 5'01011
45327         assign { } { }
45328         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45329       attribute \src "libresoc.v:0.0-0.0"
45330       case 5'01010
45331         assign { } { }
45332         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45333       attribute \src "libresoc.v:0.0-0.0"
45334       case 5'01001
45335         assign { } { }
45336         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45337       attribute \src "libresoc.v:0.0-0.0"
45338       case 5'01000
45339         assign { } { }
45340         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45341       attribute \src "libresoc.v:0.0-0.0"
45342       case 5'00001
45343         assign { } { }
45344         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45345       attribute \src "libresoc.v:0.0-0.0"
45346       case 5'00000
45347         assign { } { }
45348         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45349       attribute \src "libresoc.v:0.0-0.0"
45350       case 5'00111
45351         assign { } { }
45352         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45353       attribute \src "libresoc.v:0.0-0.0"
45354       case 5'00110
45355         assign { } { }
45356         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45357       attribute \src "libresoc.v:0.0-0.0"
45358       case 5'01101
45359         assign { } { }
45360         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45361       attribute \src "libresoc.v:0.0-0.0"
45362       case 5'01100
45363         assign { } { }
45364         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45365       attribute \src "libresoc.v:0.0-0.0"
45366       case 5'00101
45367         assign { } { }
45368         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45369       attribute \src "libresoc.v:0.0-0.0"
45370       case 5'00100
45371         assign { } { }
45372         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45373       case
45374         assign $1\dec31_dec_sub23_inv_out[0:0] 1'0
45375     end
45376     sync always
45377       update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0]
45378   end
45379   attribute \src "libresoc.v:30923.3-30971.6"
45380   process $proc$libresoc.v:30923$665
45381     assign { } { }
45382     assign { } { }
45383     assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0]
45384     attribute \src "libresoc.v:30924.5-30924.29"
45385     switch \initial
45386       attribute \src "libresoc.v:30924.9-30924.17"
45387       case 1'1
45388       case
45389     end
45390     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45391     switch \opcode_switch
45392       attribute \src "libresoc.v:0.0-0.0"
45393       case 5'00011
45394         assign { } { }
45395         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45396       attribute \src "libresoc.v:0.0-0.0"
45397       case 5'00010
45398         assign { } { }
45399         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45400       attribute \src "libresoc.v:0.0-0.0"
45401       case 5'01011
45402         assign { } { }
45403         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45404       attribute \src "libresoc.v:0.0-0.0"
45405       case 5'01010
45406         assign { } { }
45407         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45408       attribute \src "libresoc.v:0.0-0.0"
45409       case 5'01001
45410         assign { } { }
45411         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45412       attribute \src "libresoc.v:0.0-0.0"
45413       case 5'01000
45414         assign { } { }
45415         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45416       attribute \src "libresoc.v:0.0-0.0"
45417       case 5'00001
45418         assign { } { }
45419         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45420       attribute \src "libresoc.v:0.0-0.0"
45421       case 5'00000
45422         assign { } { }
45423         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45424       attribute \src "libresoc.v:0.0-0.0"
45425       case 5'00111
45426         assign { } { }
45427         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45428       attribute \src "libresoc.v:0.0-0.0"
45429       case 5'00110
45430         assign { } { }
45431         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45432       attribute \src "libresoc.v:0.0-0.0"
45433       case 5'01101
45434         assign { } { }
45435         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45436       attribute \src "libresoc.v:0.0-0.0"
45437       case 5'01100
45438         assign { } { }
45439         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45440       attribute \src "libresoc.v:0.0-0.0"
45441       case 5'00101
45442         assign { } { }
45443         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45444       attribute \src "libresoc.v:0.0-0.0"
45445       case 5'00100
45446         assign { } { }
45447         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45448       case
45449         assign $1\dec31_dec_sub23_cry_out[0:0] 1'0
45450     end
45451     sync always
45452       update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0]
45453   end
45454   attribute \src "libresoc.v:30972.3-31020.6"
45455   process $proc$libresoc.v:30972$666
45456     assign { } { }
45457     assign { } { }
45458     assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0]
45459     attribute \src "libresoc.v:30973.5-30973.29"
45460     switch \initial
45461       attribute \src "libresoc.v:30973.9-30973.17"
45462       case 1'1
45463       case
45464     end
45465     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45466     switch \opcode_switch
45467       attribute \src "libresoc.v:0.0-0.0"
45468       case 5'00011
45469         assign { } { }
45470         assign $1\dec31_dec_sub23_br[0:0] 1'0
45471       attribute \src "libresoc.v:0.0-0.0"
45472       case 5'00010
45473         assign { } { }
45474         assign $1\dec31_dec_sub23_br[0:0] 1'0
45475       attribute \src "libresoc.v:0.0-0.0"
45476       case 5'01011
45477         assign { } { }
45478         assign $1\dec31_dec_sub23_br[0:0] 1'0
45479       attribute \src "libresoc.v:0.0-0.0"
45480       case 5'01010
45481         assign { } { }
45482         assign $1\dec31_dec_sub23_br[0:0] 1'0
45483       attribute \src "libresoc.v:0.0-0.0"
45484       case 5'01001
45485         assign { } { }
45486         assign $1\dec31_dec_sub23_br[0:0] 1'0
45487       attribute \src "libresoc.v:0.0-0.0"
45488       case 5'01000
45489         assign { } { }
45490         assign $1\dec31_dec_sub23_br[0:0] 1'0
45491       attribute \src "libresoc.v:0.0-0.0"
45492       case 5'00001
45493         assign { } { }
45494         assign $1\dec31_dec_sub23_br[0:0] 1'0
45495       attribute \src "libresoc.v:0.0-0.0"
45496       case 5'00000
45497         assign { } { }
45498         assign $1\dec31_dec_sub23_br[0:0] 1'0
45499       attribute \src "libresoc.v:0.0-0.0"
45500       case 5'00111
45501         assign { } { }
45502         assign $1\dec31_dec_sub23_br[0:0] 1'0
45503       attribute \src "libresoc.v:0.0-0.0"
45504       case 5'00110
45505         assign { } { }
45506         assign $1\dec31_dec_sub23_br[0:0] 1'0
45507       attribute \src "libresoc.v:0.0-0.0"
45508       case 5'01101
45509         assign { } { }
45510         assign $1\dec31_dec_sub23_br[0:0] 1'0
45511       attribute \src "libresoc.v:0.0-0.0"
45512       case 5'01100
45513         assign { } { }
45514         assign $1\dec31_dec_sub23_br[0:0] 1'0
45515       attribute \src "libresoc.v:0.0-0.0"
45516       case 5'00101
45517         assign { } { }
45518         assign $1\dec31_dec_sub23_br[0:0] 1'0
45519       attribute \src "libresoc.v:0.0-0.0"
45520       case 5'00100
45521         assign { } { }
45522         assign $1\dec31_dec_sub23_br[0:0] 1'0
45523       case
45524         assign $1\dec31_dec_sub23_br[0:0] 1'0
45525     end
45526     sync always
45527       update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0]
45528   end
45529   attribute \src "libresoc.v:31021.3-31069.6"
45530   process $proc$libresoc.v:31021$667
45531     assign { } { }
45532     assign { } { }
45533     assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0]
45534     attribute \src "libresoc.v:31022.5-31022.29"
45535     switch \initial
45536       attribute \src "libresoc.v:31022.9-31022.17"
45537       case 1'1
45538       case
45539     end
45540     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45541     switch \opcode_switch
45542       attribute \src "libresoc.v:0.0-0.0"
45543       case 5'00011
45544         assign { } { }
45545         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45546       attribute \src "libresoc.v:0.0-0.0"
45547       case 5'00010
45548         assign { } { }
45549         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45550       attribute \src "libresoc.v:0.0-0.0"
45551       case 5'01011
45552         assign { } { }
45553         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1
45554       attribute \src "libresoc.v:0.0-0.0"
45555       case 5'01010
45556         assign { } { }
45557         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1
45558       attribute \src "libresoc.v:0.0-0.0"
45559       case 5'01001
45560         assign { } { }
45561         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45562       attribute \src "libresoc.v:0.0-0.0"
45563       case 5'01000
45564         assign { } { }
45565         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45566       attribute \src "libresoc.v:0.0-0.0"
45567       case 5'00001
45568         assign { } { }
45569         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45570       attribute \src "libresoc.v:0.0-0.0"
45571       case 5'00000
45572         assign { } { }
45573         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45574       attribute \src "libresoc.v:0.0-0.0"
45575       case 5'00111
45576         assign { } { }
45577         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45578       attribute \src "libresoc.v:0.0-0.0"
45579       case 5'00110
45580         assign { } { }
45581         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45582       attribute \src "libresoc.v:0.0-0.0"
45583       case 5'01101
45584         assign { } { }
45585         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45586       attribute \src "libresoc.v:0.0-0.0"
45587       case 5'01100
45588         assign { } { }
45589         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45590       attribute \src "libresoc.v:0.0-0.0"
45591       case 5'00101
45592         assign { } { }
45593         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45594       attribute \src "libresoc.v:0.0-0.0"
45595       case 5'00100
45596         assign { } { }
45597         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45598       case
45599         assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0
45600     end
45601     sync always
45602       update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0]
45603   end
45604   attribute \src "libresoc.v:31070.3-31118.6"
45605   process $proc$libresoc.v:31070$668
45606     assign { } { }
45607     assign { } { }
45608     assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0]
45609     attribute \src "libresoc.v:31071.5-31071.29"
45610     switch \initial
45611       attribute \src "libresoc.v:31071.9-31071.17"
45612       case 1'1
45613       case
45614     end
45615     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45616     switch \opcode_switch
45617       attribute \src "libresoc.v:0.0-0.0"
45618       case 5'00011
45619         assign { } { }
45620         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45621       attribute \src "libresoc.v:0.0-0.0"
45622       case 5'00010
45623         assign { } { }
45624         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45625       attribute \src "libresoc.v:0.0-0.0"
45626       case 5'01011
45627         assign { } { }
45628         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45629       attribute \src "libresoc.v:0.0-0.0"
45630       case 5'01010
45631         assign { } { }
45632         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45633       attribute \src "libresoc.v:0.0-0.0"
45634       case 5'01001
45635         assign { } { }
45636         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45637       attribute \src "libresoc.v:0.0-0.0"
45638       case 5'01000
45639         assign { } { }
45640         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45641       attribute \src "libresoc.v:0.0-0.0"
45642       case 5'00001
45643         assign { } { }
45644         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45645       attribute \src "libresoc.v:0.0-0.0"
45646       case 5'00000
45647         assign { } { }
45648         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101
45649       attribute \src "libresoc.v:0.0-0.0"
45650       case 5'00111
45651         assign { } { }
45652         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110
45653       attribute \src "libresoc.v:0.0-0.0"
45654       case 5'00110
45655         assign { } { }
45656         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110
45657       attribute \src "libresoc.v:0.0-0.0"
45658       case 5'01101
45659         assign { } { }
45660         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110
45661       attribute \src "libresoc.v:0.0-0.0"
45662       case 5'01100
45663         assign { } { }
45664         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110
45665       attribute \src "libresoc.v:0.0-0.0"
45666       case 5'00101
45667         assign { } { }
45668         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110
45669       attribute \src "libresoc.v:0.0-0.0"
45670       case 5'00100
45671         assign { } { }
45672         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110
45673       case
45674         assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000
45675     end
45676     sync always
45677       update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0]
45678   end
45679   attribute \src "libresoc.v:31119.3-31167.6"
45680   process $proc$libresoc.v:31119$669
45681     assign { } { }
45682     assign { } { }
45683     assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0]
45684     attribute \src "libresoc.v:31120.5-31120.29"
45685     switch \initial
45686       attribute \src "libresoc.v:31120.9-31120.17"
45687       case 1'1
45688       case
45689     end
45690     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45691     switch \opcode_switch
45692       attribute \src "libresoc.v:0.0-0.0"
45693       case 5'00011
45694         assign { } { }
45695         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45696       attribute \src "libresoc.v:0.0-0.0"
45697       case 5'00010
45698         assign { } { }
45699         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45700       attribute \src "libresoc.v:0.0-0.0"
45701       case 5'01011
45702         assign { } { }
45703         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45704       attribute \src "libresoc.v:0.0-0.0"
45705       case 5'01010
45706         assign { } { }
45707         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45708       attribute \src "libresoc.v:0.0-0.0"
45709       case 5'01001
45710         assign { } { }
45711         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45712       attribute \src "libresoc.v:0.0-0.0"
45713       case 5'01000
45714         assign { } { }
45715         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45716       attribute \src "libresoc.v:0.0-0.0"
45717       case 5'00001
45718         assign { } { }
45719         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45720       attribute \src "libresoc.v:0.0-0.0"
45721       case 5'00000
45722         assign { } { }
45723         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45724       attribute \src "libresoc.v:0.0-0.0"
45725       case 5'00111
45726         assign { } { }
45727         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45728       attribute \src "libresoc.v:0.0-0.0"
45729       case 5'00110
45730         assign { } { }
45731         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45732       attribute \src "libresoc.v:0.0-0.0"
45733       case 5'01101
45734         assign { } { }
45735         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45736       attribute \src "libresoc.v:0.0-0.0"
45737       case 5'01100
45738         assign { } { }
45739         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45740       attribute \src "libresoc.v:0.0-0.0"
45741       case 5'00101
45742         assign { } { }
45743         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45744       attribute \src "libresoc.v:0.0-0.0"
45745       case 5'00100
45746         assign { } { }
45747         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45748       case
45749         assign $1\dec31_dec_sub23_rsrv[0:0] 1'0
45750     end
45751     sync always
45752       update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0]
45753   end
45754   attribute \src "libresoc.v:31168.3-31216.6"
45755   process $proc$libresoc.v:31168$670
45756     assign { } { }
45757     assign { } { }
45758     assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0]
45759     attribute \src "libresoc.v:31169.5-31169.29"
45760     switch \initial
45761       attribute \src "libresoc.v:31169.9-31169.17"
45762       case 1'1
45763       case
45764     end
45765     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45766     switch \opcode_switch
45767       attribute \src "libresoc.v:0.0-0.0"
45768       case 5'00011
45769         assign { } { }
45770         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45771       attribute \src "libresoc.v:0.0-0.0"
45772       case 5'00010
45773         assign { } { }
45774         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45775       attribute \src "libresoc.v:0.0-0.0"
45776       case 5'01011
45777         assign { } { }
45778         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45779       attribute \src "libresoc.v:0.0-0.0"
45780       case 5'01010
45781         assign { } { }
45782         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45783       attribute \src "libresoc.v:0.0-0.0"
45784       case 5'01001
45785         assign { } { }
45786         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45787       attribute \src "libresoc.v:0.0-0.0"
45788       case 5'01000
45789         assign { } { }
45790         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45791       attribute \src "libresoc.v:0.0-0.0"
45792       case 5'00001
45793         assign { } { }
45794         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45795       attribute \src "libresoc.v:0.0-0.0"
45796       case 5'00000
45797         assign { } { }
45798         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45799       attribute \src "libresoc.v:0.0-0.0"
45800       case 5'00111
45801         assign { } { }
45802         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45803       attribute \src "libresoc.v:0.0-0.0"
45804       case 5'00110
45805         assign { } { }
45806         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45807       attribute \src "libresoc.v:0.0-0.0"
45808       case 5'01101
45809         assign { } { }
45810         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45811       attribute \src "libresoc.v:0.0-0.0"
45812       case 5'01100
45813         assign { } { }
45814         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45815       attribute \src "libresoc.v:0.0-0.0"
45816       case 5'00101
45817         assign { } { }
45818         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45819       attribute \src "libresoc.v:0.0-0.0"
45820       case 5'00100
45821         assign { } { }
45822         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45823       case
45824         assign $1\dec31_dec_sub23_is_32b[0:0] 1'0
45825     end
45826     sync always
45827       update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0]
45828   end
45829   attribute \src "libresoc.v:31217.3-31265.6"
45830   process $proc$libresoc.v:31217$671
45831     assign { } { }
45832     assign { } { }
45833     assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0]
45834     attribute \src "libresoc.v:31218.5-31218.29"
45835     switch \initial
45836       attribute \src "libresoc.v:31218.9-31218.17"
45837       case 1'1
45838       case
45839     end
45840     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45841     switch \opcode_switch
45842       attribute \src "libresoc.v:0.0-0.0"
45843       case 5'00011
45844         assign { } { }
45845         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45846       attribute \src "libresoc.v:0.0-0.0"
45847       case 5'00010
45848         assign { } { }
45849         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45850       attribute \src "libresoc.v:0.0-0.0"
45851       case 5'01011
45852         assign { } { }
45853         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45854       attribute \src "libresoc.v:0.0-0.0"
45855       case 5'01010
45856         assign { } { }
45857         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45858       attribute \src "libresoc.v:0.0-0.0"
45859       case 5'01001
45860         assign { } { }
45861         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45862       attribute \src "libresoc.v:0.0-0.0"
45863       case 5'01000
45864         assign { } { }
45865         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45866       attribute \src "libresoc.v:0.0-0.0"
45867       case 5'00001
45868         assign { } { }
45869         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45870       attribute \src "libresoc.v:0.0-0.0"
45871       case 5'00000
45872         assign { } { }
45873         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45874       attribute \src "libresoc.v:0.0-0.0"
45875       case 5'00111
45876         assign { } { }
45877         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45878       attribute \src "libresoc.v:0.0-0.0"
45879       case 5'00110
45880         assign { } { }
45881         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45882       attribute \src "libresoc.v:0.0-0.0"
45883       case 5'01101
45884         assign { } { }
45885         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45886       attribute \src "libresoc.v:0.0-0.0"
45887       case 5'01100
45888         assign { } { }
45889         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45890       attribute \src "libresoc.v:0.0-0.0"
45891       case 5'00101
45892         assign { } { }
45893         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45894       attribute \src "libresoc.v:0.0-0.0"
45895       case 5'00100
45896         assign { } { }
45897         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45898       case
45899         assign $1\dec31_dec_sub23_sgn[0:0] 1'0
45900     end
45901     sync always
45902       update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0]
45903   end
45904   attribute \src "libresoc.v:31266.3-31314.6"
45905   process $proc$libresoc.v:31266$672
45906     assign { } { }
45907     assign { } { }
45908     assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0]
45909     attribute \src "libresoc.v:31267.5-31267.29"
45910     switch \initial
45911       attribute \src "libresoc.v:31267.9-31267.17"
45912       case 1'1
45913       case
45914     end
45915     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45916     switch \opcode_switch
45917       attribute \src "libresoc.v:0.0-0.0"
45918       case 5'00011
45919         assign { } { }
45920         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45921       attribute \src "libresoc.v:0.0-0.0"
45922       case 5'00010
45923         assign { } { }
45924         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45925       attribute \src "libresoc.v:0.0-0.0"
45926       case 5'01011
45927         assign { } { }
45928         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45929       attribute \src "libresoc.v:0.0-0.0"
45930       case 5'01010
45931         assign { } { }
45932         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45933       attribute \src "libresoc.v:0.0-0.0"
45934       case 5'01001
45935         assign { } { }
45936         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45937       attribute \src "libresoc.v:0.0-0.0"
45938       case 5'01000
45939         assign { } { }
45940         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45941       attribute \src "libresoc.v:0.0-0.0"
45942       case 5'00001
45943         assign { } { }
45944         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45945       attribute \src "libresoc.v:0.0-0.0"
45946       case 5'00000
45947         assign { } { }
45948         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45949       attribute \src "libresoc.v:0.0-0.0"
45950       case 5'00111
45951         assign { } { }
45952         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45953       attribute \src "libresoc.v:0.0-0.0"
45954       case 5'00110
45955         assign { } { }
45956         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45957       attribute \src "libresoc.v:0.0-0.0"
45958       case 5'01101
45959         assign { } { }
45960         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45961       attribute \src "libresoc.v:0.0-0.0"
45962       case 5'01100
45963         assign { } { }
45964         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45965       attribute \src "libresoc.v:0.0-0.0"
45966       case 5'00101
45967         assign { } { }
45968         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45969       attribute \src "libresoc.v:0.0-0.0"
45970       case 5'00100
45971         assign { } { }
45972         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45973       case
45974         assign $1\dec31_dec_sub23_lk[0:0] 1'0
45975     end
45976     sync always
45977       update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0]
45978   end
45979   attribute \src "libresoc.v:31315.3-31363.6"
45980   process $proc$libresoc.v:31315$673
45981     assign { } { }
45982     assign { } { }
45983     assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0]
45984     attribute \src "libresoc.v:31316.5-31316.29"
45985     switch \initial
45986       attribute \src "libresoc.v:31316.9-31316.17"
45987       case 1'1
45988       case
45989     end
45990     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
45991     switch \opcode_switch
45992       attribute \src "libresoc.v:0.0-0.0"
45993       case 5'00011
45994         assign { } { }
45995         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
45996       attribute \src "libresoc.v:0.0-0.0"
45997       case 5'00010
45998         assign { } { }
45999         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46000       attribute \src "libresoc.v:0.0-0.0"
46001       case 5'01011
46002         assign { } { }
46003         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46004       attribute \src "libresoc.v:0.0-0.0"
46005       case 5'01010
46006         assign { } { }
46007         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46008       attribute \src "libresoc.v:0.0-0.0"
46009       case 5'01001
46010         assign { } { }
46011         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46012       attribute \src "libresoc.v:0.0-0.0"
46013       case 5'01000
46014         assign { } { }
46015         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46016       attribute \src "libresoc.v:0.0-0.0"
46017       case 5'00001
46018         assign { } { }
46019         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46020       attribute \src "libresoc.v:0.0-0.0"
46021       case 5'00000
46022         assign { } { }
46023         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46024       attribute \src "libresoc.v:0.0-0.0"
46025       case 5'00111
46026         assign { } { }
46027         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46028       attribute \src "libresoc.v:0.0-0.0"
46029       case 5'00110
46030         assign { } { }
46031         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46032       attribute \src "libresoc.v:0.0-0.0"
46033       case 5'01101
46034         assign { } { }
46035         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46036       attribute \src "libresoc.v:0.0-0.0"
46037       case 5'01100
46038         assign { } { }
46039         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46040       attribute \src "libresoc.v:0.0-0.0"
46041       case 5'00101
46042         assign { } { }
46043         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46044       attribute \src "libresoc.v:0.0-0.0"
46045       case 5'00100
46046         assign { } { }
46047         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1
46048       case
46049         assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0
46050     end
46051     sync always
46052       update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0]
46053   end
46054   attribute \src "libresoc.v:31364.3-31412.6"
46055   process $proc$libresoc.v:31364$674
46056     assign { } { }
46057     assign { } { }
46058     assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0]
46059     attribute \src "libresoc.v:31365.5-31365.29"
46060     switch \initial
46061       attribute \src "libresoc.v:31365.9-31365.17"
46062       case 1'1
46063       case
46064     end
46065     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46066     switch \opcode_switch
46067       attribute \src "libresoc.v:0.0-0.0"
46068       case 5'00011
46069         assign { } { }
46070         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46071       attribute \src "libresoc.v:0.0-0.0"
46072       case 5'00010
46073         assign { } { }
46074         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46075       attribute \src "libresoc.v:0.0-0.0"
46076       case 5'01011
46077         assign { } { }
46078         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46079       attribute \src "libresoc.v:0.0-0.0"
46080       case 5'01010
46081         assign { } { }
46082         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46083       attribute \src "libresoc.v:0.0-0.0"
46084       case 5'01001
46085         assign { } { }
46086         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46087       attribute \src "libresoc.v:0.0-0.0"
46088       case 5'01000
46089         assign { } { }
46090         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46091       attribute \src "libresoc.v:0.0-0.0"
46092       case 5'00001
46093         assign { } { }
46094         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46095       attribute \src "libresoc.v:0.0-0.0"
46096       case 5'00000
46097         assign { } { }
46098         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46099       attribute \src "libresoc.v:0.0-0.0"
46100       case 5'00111
46101         assign { } { }
46102         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46103       attribute \src "libresoc.v:0.0-0.0"
46104       case 5'00110
46105         assign { } { }
46106         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46107       attribute \src "libresoc.v:0.0-0.0"
46108       case 5'01101
46109         assign { } { }
46110         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46111       attribute \src "libresoc.v:0.0-0.0"
46112       case 5'01100
46113         assign { } { }
46114         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46115       attribute \src "libresoc.v:0.0-0.0"
46116       case 5'00101
46117         assign { } { }
46118         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46119       attribute \src "libresoc.v:0.0-0.0"
46120       case 5'00100
46121         assign { } { }
46122         assign $1\dec31_dec_sub23_form[4:0] 5'01000
46123       case
46124         assign $1\dec31_dec_sub23_form[4:0] 5'00000
46125     end
46126     sync always
46127       update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0]
46128   end
46129   attribute \src "libresoc.v:31413.3-31461.6"
46130   process $proc$libresoc.v:31413$675
46131     assign { } { }
46132     assign { } { }
46133     assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0]
46134     attribute \src "libresoc.v:31414.5-31414.29"
46135     switch \initial
46136       attribute \src "libresoc.v:31414.9-31414.17"
46137       case 1'1
46138       case
46139     end
46140     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46141     switch \opcode_switch
46142       attribute \src "libresoc.v:0.0-0.0"
46143       case 5'00011
46144         assign { } { }
46145         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46146       attribute \src "libresoc.v:0.0-0.0"
46147       case 5'00010
46148         assign { } { }
46149         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46150       attribute \src "libresoc.v:0.0-0.0"
46151       case 5'01011
46152         assign { } { }
46153         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46154       attribute \src "libresoc.v:0.0-0.0"
46155       case 5'01010
46156         assign { } { }
46157         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46158       attribute \src "libresoc.v:0.0-0.0"
46159       case 5'01001
46160         assign { } { }
46161         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46162       attribute \src "libresoc.v:0.0-0.0"
46163       case 5'01000
46164         assign { } { }
46165         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46166       attribute \src "libresoc.v:0.0-0.0"
46167       case 5'00001
46168         assign { } { }
46169         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46170       attribute \src "libresoc.v:0.0-0.0"
46171       case 5'00000
46172         assign { } { }
46173         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46174       attribute \src "libresoc.v:0.0-0.0"
46175       case 5'00111
46176         assign { } { }
46177         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46178       attribute \src "libresoc.v:0.0-0.0"
46179       case 5'00110
46180         assign { } { }
46181         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46182       attribute \src "libresoc.v:0.0-0.0"
46183       case 5'01101
46184         assign { } { }
46185         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46186       attribute \src "libresoc.v:0.0-0.0"
46187       case 5'01100
46188         assign { } { }
46189         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46190       attribute \src "libresoc.v:0.0-0.0"
46191       case 5'00101
46192         assign { } { }
46193         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46194       attribute \src "libresoc.v:0.0-0.0"
46195       case 5'00100
46196         assign { } { }
46197         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010
46198       case
46199         assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000
46200     end
46201     sync always
46202       update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0]
46203   end
46204   attribute \src "libresoc.v:31462.3-31510.6"
46205   process $proc$libresoc.v:31462$676
46206     assign { } { }
46207     assign { } { }
46208     assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0]
46209     attribute \src "libresoc.v:31463.5-31463.29"
46210     switch \initial
46211       attribute \src "libresoc.v:31463.9-31463.17"
46212       case 1'1
46213       case
46214     end
46215     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46216     switch \opcode_switch
46217       attribute \src "libresoc.v:0.0-0.0"
46218       case 5'00011
46219         assign { } { }
46220         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46221       attribute \src "libresoc.v:0.0-0.0"
46222       case 5'00010
46223         assign { } { }
46224         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46225       attribute \src "libresoc.v:0.0-0.0"
46226       case 5'01011
46227         assign { } { }
46228         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46229       attribute \src "libresoc.v:0.0-0.0"
46230       case 5'01010
46231         assign { } { }
46232         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46233       attribute \src "libresoc.v:0.0-0.0"
46234       case 5'01001
46235         assign { } { }
46236         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46237       attribute \src "libresoc.v:0.0-0.0"
46238       case 5'01000
46239         assign { } { }
46240         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46241       attribute \src "libresoc.v:0.0-0.0"
46242       case 5'00001
46243         assign { } { }
46244         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46245       attribute \src "libresoc.v:0.0-0.0"
46246       case 5'00000
46247         assign { } { }
46248         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46249       attribute \src "libresoc.v:0.0-0.0"
46250       case 5'00111
46251         assign { } { }
46252         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46253       attribute \src "libresoc.v:0.0-0.0"
46254       case 5'00110
46255         assign { } { }
46256         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46257       attribute \src "libresoc.v:0.0-0.0"
46258       case 5'01101
46259         assign { } { }
46260         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46261       attribute \src "libresoc.v:0.0-0.0"
46262       case 5'01100
46263         assign { } { }
46264         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46265       attribute \src "libresoc.v:0.0-0.0"
46266       case 5'00101
46267         assign { } { }
46268         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46269       attribute \src "libresoc.v:0.0-0.0"
46270       case 5'00100
46271         assign { } { }
46272         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001
46273       case
46274         assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000
46275     end
46276     sync always
46277       update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0]
46278   end
46279   attribute \src "libresoc.v:31511.3-31559.6"
46280   process $proc$libresoc.v:31511$677
46281     assign { } { }
46282     assign { } { }
46283     assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0]
46284     attribute \src "libresoc.v:31512.5-31512.29"
46285     switch \initial
46286       attribute \src "libresoc.v:31512.9-31512.17"
46287       case 1'1
46288       case
46289     end
46290     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46291     switch \opcode_switch
46292       attribute \src "libresoc.v:0.0-0.0"
46293       case 5'00011
46294         assign { } { }
46295         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46296       attribute \src "libresoc.v:0.0-0.0"
46297       case 5'00010
46298         assign { } { }
46299         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46300       attribute \src "libresoc.v:0.0-0.0"
46301       case 5'01011
46302         assign { } { }
46303         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46304       attribute \src "libresoc.v:0.0-0.0"
46305       case 5'01010
46306         assign { } { }
46307         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46308       attribute \src "libresoc.v:0.0-0.0"
46309       case 5'01001
46310         assign { } { }
46311         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46312       attribute \src "libresoc.v:0.0-0.0"
46313       case 5'01000
46314         assign { } { }
46315         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46316       attribute \src "libresoc.v:0.0-0.0"
46317       case 5'00001
46318         assign { } { }
46319         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46320       attribute \src "libresoc.v:0.0-0.0"
46321       case 5'00000
46322         assign { } { }
46323         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46324       attribute \src "libresoc.v:0.0-0.0"
46325       case 5'00111
46326         assign { } { }
46327         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01
46328       attribute \src "libresoc.v:0.0-0.0"
46329       case 5'00110
46330         assign { } { }
46331         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01
46332       attribute \src "libresoc.v:0.0-0.0"
46333       case 5'01101
46334         assign { } { }
46335         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01
46336       attribute \src "libresoc.v:0.0-0.0"
46337       case 5'01100
46338         assign { } { }
46339         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01
46340       attribute \src "libresoc.v:0.0-0.0"
46341       case 5'00101
46342         assign { } { }
46343         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01
46344       attribute \src "libresoc.v:0.0-0.0"
46345       case 5'00100
46346         assign { } { }
46347         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01
46348       case
46349         assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00
46350     end
46351     sync always
46352       update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0]
46353   end
46354   attribute \src "libresoc.v:31560.3-31608.6"
46355   process $proc$libresoc.v:31560$678
46356     assign { } { }
46357     assign { } { }
46358     assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0]
46359     attribute \src "libresoc.v:31561.5-31561.29"
46360     switch \initial
46361       attribute \src "libresoc.v:31561.9-31561.17"
46362       case 1'1
46363       case
46364     end
46365     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46366     switch \opcode_switch
46367       attribute \src "libresoc.v:0.0-0.0"
46368       case 5'00011
46369         assign { } { }
46370         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46371       attribute \src "libresoc.v:0.0-0.0"
46372       case 5'00010
46373         assign { } { }
46374         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46375       attribute \src "libresoc.v:0.0-0.0"
46376       case 5'01011
46377         assign { } { }
46378         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46379       attribute \src "libresoc.v:0.0-0.0"
46380       case 5'01010
46381         assign { } { }
46382         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46383       attribute \src "libresoc.v:0.0-0.0"
46384       case 5'01001
46385         assign { } { }
46386         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46387       attribute \src "libresoc.v:0.0-0.0"
46388       case 5'01000
46389         assign { } { }
46390         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46391       attribute \src "libresoc.v:0.0-0.0"
46392       case 5'00001
46393         assign { } { }
46394         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46395       attribute \src "libresoc.v:0.0-0.0"
46396       case 5'00000
46397         assign { } { }
46398         assign $1\dec31_dec_sub23_out_sel[1:0] 2'01
46399       attribute \src "libresoc.v:0.0-0.0"
46400       case 5'00111
46401         assign { } { }
46402         assign $1\dec31_dec_sub23_out_sel[1:0] 2'00
46403       attribute \src "libresoc.v:0.0-0.0"
46404       case 5'00110
46405         assign { } { }
46406         assign $1\dec31_dec_sub23_out_sel[1:0] 2'00
46407       attribute \src "libresoc.v:0.0-0.0"
46408       case 5'01101
46409         assign { } { }
46410         assign $1\dec31_dec_sub23_out_sel[1:0] 2'00
46411       attribute \src "libresoc.v:0.0-0.0"
46412       case 5'01100
46413         assign { } { }
46414         assign $1\dec31_dec_sub23_out_sel[1:0] 2'00
46415       attribute \src "libresoc.v:0.0-0.0"
46416       case 5'00101
46417         assign { } { }
46418         assign $1\dec31_dec_sub23_out_sel[1:0] 2'00
46419       attribute \src "libresoc.v:0.0-0.0"
46420       case 5'00100
46421         assign { } { }
46422         assign $1\dec31_dec_sub23_out_sel[1:0] 2'00
46423       case
46424         assign $1\dec31_dec_sub23_out_sel[1:0] 2'00
46425     end
46426     sync always
46427       update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0]
46428   end
46429   attribute \src "libresoc.v:31609.3-31657.6"
46430   process $proc$libresoc.v:31609$679
46431     assign { } { }
46432     assign { } { }
46433     assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0]
46434     attribute \src "libresoc.v:31610.5-31610.29"
46435     switch \initial
46436       attribute \src "libresoc.v:31610.9-31610.17"
46437       case 1'1
46438       case
46439     end
46440     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46441     switch \opcode_switch
46442       attribute \src "libresoc.v:0.0-0.0"
46443       case 5'00011
46444         assign { } { }
46445         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46446       attribute \src "libresoc.v:0.0-0.0"
46447       case 5'00010
46448         assign { } { }
46449         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46450       attribute \src "libresoc.v:0.0-0.0"
46451       case 5'01011
46452         assign { } { }
46453         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46454       attribute \src "libresoc.v:0.0-0.0"
46455       case 5'01010
46456         assign { } { }
46457         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46458       attribute \src "libresoc.v:0.0-0.0"
46459       case 5'01001
46460         assign { } { }
46461         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46462       attribute \src "libresoc.v:0.0-0.0"
46463       case 5'01000
46464         assign { } { }
46465         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46466       attribute \src "libresoc.v:0.0-0.0"
46467       case 5'00001
46468         assign { } { }
46469         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46470       attribute \src "libresoc.v:0.0-0.0"
46471       case 5'00000
46472         assign { } { }
46473         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46474       attribute \src "libresoc.v:0.0-0.0"
46475       case 5'00111
46476         assign { } { }
46477         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46478       attribute \src "libresoc.v:0.0-0.0"
46479       case 5'00110
46480         assign { } { }
46481         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46482       attribute \src "libresoc.v:0.0-0.0"
46483       case 5'01101
46484         assign { } { }
46485         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46486       attribute \src "libresoc.v:0.0-0.0"
46487       case 5'01100
46488         assign { } { }
46489         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46490       attribute \src "libresoc.v:0.0-0.0"
46491       case 5'00101
46492         assign { } { }
46493         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46494       attribute \src "libresoc.v:0.0-0.0"
46495       case 5'00100
46496         assign { } { }
46497         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46498       case
46499         assign $1\dec31_dec_sub23_cr_in[2:0] 3'000
46500     end
46501     sync always
46502       update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0]
46503   end
46504   attribute \src "libresoc.v:31658.3-31706.6"
46505   process $proc$libresoc.v:31658$680
46506     assign { } { }
46507     assign { } { }
46508     assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0]
46509     attribute \src "libresoc.v:31659.5-31659.29"
46510     switch \initial
46511       attribute \src "libresoc.v:31659.9-31659.17"
46512       case 1'1
46513       case
46514     end
46515     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46516     switch \opcode_switch
46517       attribute \src "libresoc.v:0.0-0.0"
46518       case 5'00011
46519         assign { } { }
46520         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46521       attribute \src "libresoc.v:0.0-0.0"
46522       case 5'00010
46523         assign { } { }
46524         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46525       attribute \src "libresoc.v:0.0-0.0"
46526       case 5'01011
46527         assign { } { }
46528         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46529       attribute \src "libresoc.v:0.0-0.0"
46530       case 5'01010
46531         assign { } { }
46532         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46533       attribute \src "libresoc.v:0.0-0.0"
46534       case 5'01001
46535         assign { } { }
46536         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46537       attribute \src "libresoc.v:0.0-0.0"
46538       case 5'01000
46539         assign { } { }
46540         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46541       attribute \src "libresoc.v:0.0-0.0"
46542       case 5'00001
46543         assign { } { }
46544         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46545       attribute \src "libresoc.v:0.0-0.0"
46546       case 5'00000
46547         assign { } { }
46548         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46549       attribute \src "libresoc.v:0.0-0.0"
46550       case 5'00111
46551         assign { } { }
46552         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46553       attribute \src "libresoc.v:0.0-0.0"
46554       case 5'00110
46555         assign { } { }
46556         assign $1\dec31_dec_sub23_cr_out[2:0] 3'001
46557       attribute \src "libresoc.v:0.0-0.0"
46558       case 5'01101
46559         assign { } { }
46560         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46561       attribute \src "libresoc.v:0.0-0.0"
46562       case 5'01100
46563         assign { } { }
46564         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46565       attribute \src "libresoc.v:0.0-0.0"
46566       case 5'00101
46567         assign { } { }
46568         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46569       attribute \src "libresoc.v:0.0-0.0"
46570       case 5'00100
46571         assign { } { }
46572         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46573       case
46574         assign $1\dec31_dec_sub23_cr_out[2:0] 3'000
46575     end
46576     sync always
46577       update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0]
46578   end
46579   connect \opcode_switch \opcode_in [10:6]
46580 end
46581 attribute \src "libresoc.v:31712.1-32427.10"
46582 attribute \cells_not_processed 1
46583 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24"
46584 attribute \generator "nMigen"
46585 module \dec31_dec_sub24
46586   attribute \src "libresoc.v:32065.3-32083.6"
46587   wire width 8 $0\dec31_dec_sub24_asmcode[7:0]
46588   attribute \src "libresoc.v:32141.3-32159.6"
46589   wire $0\dec31_dec_sub24_br[0:0]
46590   attribute \src "libresoc.v:32388.3-32406.6"
46591   wire width 3 $0\dec31_dec_sub24_cr_in[2:0]
46592   attribute \src "libresoc.v:32407.3-32425.6"
46593   wire width 3 $0\dec31_dec_sub24_cr_out[2:0]
46594   attribute \src "libresoc.v:32046.3-32064.6"
46595   wire width 2 $0\dec31_dec_sub24_cry_in[1:0]
46596   attribute \src "libresoc.v:32122.3-32140.6"
46597   wire $0\dec31_dec_sub24_cry_out[0:0]
46598   attribute \src "libresoc.v:32293.3-32311.6"
46599   wire width 5 $0\dec31_dec_sub24_form[4:0]
46600   attribute \src "libresoc.v:31970.3-31988.6"
46601   wire width 12 $0\dec31_dec_sub24_function_unit[11:0]
46602   attribute \src "libresoc.v:32312.3-32330.6"
46603   wire width 3 $0\dec31_dec_sub24_in1_sel[2:0]
46604   attribute \src "libresoc.v:32331.3-32349.6"
46605   wire width 4 $0\dec31_dec_sub24_in2_sel[3:0]
46606   attribute \src "libresoc.v:32350.3-32368.6"
46607   wire width 2 $0\dec31_dec_sub24_in3_sel[1:0]
46608   attribute \src "libresoc.v:32179.3-32197.6"
46609   wire width 7 $0\dec31_dec_sub24_internal_op[6:0]
46610   attribute \src "libresoc.v:32084.3-32102.6"
46611   wire $0\dec31_dec_sub24_inv_a[0:0]
46612   attribute \src "libresoc.v:32103.3-32121.6"
46613   wire $0\dec31_dec_sub24_inv_out[0:0]
46614   attribute \src "libresoc.v:32217.3-32235.6"
46615   wire $0\dec31_dec_sub24_is_32b[0:0]
46616   attribute \src "libresoc.v:31989.3-32007.6"
46617   wire width 4 $0\dec31_dec_sub24_ldst_len[3:0]
46618   attribute \src "libresoc.v:32255.3-32273.6"
46619   wire $0\dec31_dec_sub24_lk[0:0]
46620   attribute \src "libresoc.v:32369.3-32387.6"
46621   wire width 2 $0\dec31_dec_sub24_out_sel[1:0]
46622   attribute \src "libresoc.v:32027.3-32045.6"
46623   wire width 2 $0\dec31_dec_sub24_rc_sel[1:0]
46624   attribute \src "libresoc.v:32198.3-32216.6"
46625   wire $0\dec31_dec_sub24_rsrv[0:0]
46626   attribute \src "libresoc.v:32274.3-32292.6"
46627   wire $0\dec31_dec_sub24_sgl_pipe[0:0]
46628   attribute \src "libresoc.v:32236.3-32254.6"
46629   wire $0\dec31_dec_sub24_sgn[0:0]
46630   attribute \src "libresoc.v:32160.3-32178.6"
46631   wire $0\dec31_dec_sub24_sgn_ext[0:0]
46632   attribute \src "libresoc.v:32008.3-32026.6"
46633   wire width 2 $0\dec31_dec_sub24_upd[1:0]
46634   attribute \src "libresoc.v:31713.7-31713.20"
46635   wire $0\initial[0:0]
46636   attribute \src "libresoc.v:32065.3-32083.6"
46637   wire width 8 $1\dec31_dec_sub24_asmcode[7:0]
46638   attribute \src "libresoc.v:32141.3-32159.6"
46639   wire $1\dec31_dec_sub24_br[0:0]
46640   attribute \src "libresoc.v:32388.3-32406.6"
46641   wire width 3 $1\dec31_dec_sub24_cr_in[2:0]
46642   attribute \src "libresoc.v:32407.3-32425.6"
46643   wire width 3 $1\dec31_dec_sub24_cr_out[2:0]
46644   attribute \src "libresoc.v:32046.3-32064.6"
46645   wire width 2 $1\dec31_dec_sub24_cry_in[1:0]
46646   attribute \src "libresoc.v:32122.3-32140.6"
46647   wire $1\dec31_dec_sub24_cry_out[0:0]
46648   attribute \src "libresoc.v:32293.3-32311.6"
46649   wire width 5 $1\dec31_dec_sub24_form[4:0]
46650   attribute \src "libresoc.v:31970.3-31988.6"
46651   wire width 12 $1\dec31_dec_sub24_function_unit[11:0]
46652   attribute \src "libresoc.v:32312.3-32330.6"
46653   wire width 3 $1\dec31_dec_sub24_in1_sel[2:0]
46654   attribute \src "libresoc.v:32331.3-32349.6"
46655   wire width 4 $1\dec31_dec_sub24_in2_sel[3:0]
46656   attribute \src "libresoc.v:32350.3-32368.6"
46657   wire width 2 $1\dec31_dec_sub24_in3_sel[1:0]
46658   attribute \src "libresoc.v:32179.3-32197.6"
46659   wire width 7 $1\dec31_dec_sub24_internal_op[6:0]
46660   attribute \src "libresoc.v:32084.3-32102.6"
46661   wire $1\dec31_dec_sub24_inv_a[0:0]
46662   attribute \src "libresoc.v:32103.3-32121.6"
46663   wire $1\dec31_dec_sub24_inv_out[0:0]
46664   attribute \src "libresoc.v:32217.3-32235.6"
46665   wire $1\dec31_dec_sub24_is_32b[0:0]
46666   attribute \src "libresoc.v:31989.3-32007.6"
46667   wire width 4 $1\dec31_dec_sub24_ldst_len[3:0]
46668   attribute \src "libresoc.v:32255.3-32273.6"
46669   wire $1\dec31_dec_sub24_lk[0:0]
46670   attribute \src "libresoc.v:32369.3-32387.6"
46671   wire width 2 $1\dec31_dec_sub24_out_sel[1:0]
46672   attribute \src "libresoc.v:32027.3-32045.6"
46673   wire width 2 $1\dec31_dec_sub24_rc_sel[1:0]
46674   attribute \src "libresoc.v:32198.3-32216.6"
46675   wire $1\dec31_dec_sub24_rsrv[0:0]
46676   attribute \src "libresoc.v:32274.3-32292.6"
46677   wire $1\dec31_dec_sub24_sgl_pipe[0:0]
46678   attribute \src "libresoc.v:32236.3-32254.6"
46679   wire $1\dec31_dec_sub24_sgn[0:0]
46680   attribute \src "libresoc.v:32160.3-32178.6"
46681   wire $1\dec31_dec_sub24_sgn_ext[0:0]
46682   attribute \src "libresoc.v:32008.3-32026.6"
46683   wire width 2 $1\dec31_dec_sub24_upd[1:0]
46684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46685   wire width 8 output 4 \dec31_dec_sub24_asmcode
46686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46687   wire output 18 \dec31_dec_sub24_br
46688   attribute \enum_base_type "CRInSel"
46689   attribute \enum_value_000 "NONE"
46690   attribute \enum_value_001 "CR0"
46691   attribute \enum_value_010 "BI"
46692   attribute \enum_value_011 "BFA"
46693   attribute \enum_value_100 "BA_BB"
46694   attribute \enum_value_101 "BC"
46695   attribute \enum_value_110 "WHOLE_REG"
46696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46697   wire width 3 output 9 \dec31_dec_sub24_cr_in
46698   attribute \enum_base_type "CROutSel"
46699   attribute \enum_value_000 "NONE"
46700   attribute \enum_value_001 "CR0"
46701   attribute \enum_value_010 "BF"
46702   attribute \enum_value_011 "BT"
46703   attribute \enum_value_100 "WHOLE_REG"
46704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46705   wire width 3 output 10 \dec31_dec_sub24_cr_out
46706   attribute \enum_base_type "CryIn"
46707   attribute \enum_value_00 "ZERO"
46708   attribute \enum_value_01 "ONE"
46709   attribute \enum_value_10 "CA"
46710   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46711   wire width 2 output 14 \dec31_dec_sub24_cry_in
46712   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46713   wire output 17 \dec31_dec_sub24_cry_out
46714   attribute \enum_base_type "Form"
46715   attribute \enum_value_00000 "NONE"
46716   attribute \enum_value_00001 "I"
46717   attribute \enum_value_00010 "B"
46718   attribute \enum_value_00011 "SC"
46719   attribute \enum_value_00100 "D"
46720   attribute \enum_value_00101 "DS"
46721   attribute \enum_value_00110 "DQ"
46722   attribute \enum_value_00111 "DX"
46723   attribute \enum_value_01000 "X"
46724   attribute \enum_value_01001 "XL"
46725   attribute \enum_value_01010 "XFX"
46726   attribute \enum_value_01011 "XFL"
46727   attribute \enum_value_01100 "XX1"
46728   attribute \enum_value_01101 "XX2"
46729   attribute \enum_value_01110 "XX3"
46730   attribute \enum_value_01111 "XX4"
46731   attribute \enum_value_10000 "XS"
46732   attribute \enum_value_10001 "XO"
46733   attribute \enum_value_10010 "A"
46734   attribute \enum_value_10011 "M"
46735   attribute \enum_value_10100 "MD"
46736   attribute \enum_value_10101 "MDS"
46737   attribute \enum_value_10110 "VA"
46738   attribute \enum_value_10111 "VC"
46739   attribute \enum_value_11000 "VX"
46740   attribute \enum_value_11001 "EVX"
46741   attribute \enum_value_11010 "EVS"
46742   attribute \enum_value_11011 "Z22"
46743   attribute \enum_value_11100 "Z23"
46744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46745   wire width 5 output 3 \dec31_dec_sub24_form
46746   attribute \enum_base_type "Function"
46747   attribute \enum_value_000000000000 "NONE"
46748   attribute \enum_value_000000000010 "ALU"
46749   attribute \enum_value_000000000100 "LDST"
46750   attribute \enum_value_000000001000 "SHIFT_ROT"
46751   attribute \enum_value_000000010000 "LOGICAL"
46752   attribute \enum_value_000000100000 "BRANCH"
46753   attribute \enum_value_000001000000 "CR"
46754   attribute \enum_value_000010000000 "TRAP"
46755   attribute \enum_value_000100000000 "MUL"
46756   attribute \enum_value_001000000000 "DIV"
46757   attribute \enum_value_010000000000 "SPR"
46758   attribute \enum_value_100000000000 "MMU"
46759   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46760   wire width 12 output 1 \dec31_dec_sub24_function_unit
46761   attribute \enum_base_type "In1Sel"
46762   attribute \enum_value_000 "NONE"
46763   attribute \enum_value_001 "RA"
46764   attribute \enum_value_010 "RA_OR_ZERO"
46765   attribute \enum_value_011 "SPR"
46766   attribute \enum_value_100 "RS"
46767   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46768   wire width 3 output 5 \dec31_dec_sub24_in1_sel
46769   attribute \enum_base_type "In2Sel"
46770   attribute \enum_value_0000 "NONE"
46771   attribute \enum_value_0001 "RB"
46772   attribute \enum_value_0010 "CONST_UI"
46773   attribute \enum_value_0011 "CONST_SI"
46774   attribute \enum_value_0100 "CONST_UI_HI"
46775   attribute \enum_value_0101 "CONST_SI_HI"
46776   attribute \enum_value_0110 "CONST_LI"
46777   attribute \enum_value_0111 "CONST_BD"
46778   attribute \enum_value_1000 "CONST_DS"
46779   attribute \enum_value_1001 "CONST_M1"
46780   attribute \enum_value_1010 "CONST_SH"
46781   attribute \enum_value_1011 "CONST_SH32"
46782   attribute \enum_value_1100 "SPR"
46783   attribute \enum_value_1101 "RS"
46784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46785   wire width 4 output 6 \dec31_dec_sub24_in2_sel
46786   attribute \enum_base_type "In3Sel"
46787   attribute \enum_value_00 "NONE"
46788   attribute \enum_value_01 "RS"
46789   attribute \enum_value_10 "RB"
46790   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46791   wire width 2 output 7 \dec31_dec_sub24_in3_sel
46792   attribute \enum_base_type "MicrOp"
46793   attribute \enum_value_0000000 "OP_ILLEGAL"
46794   attribute \enum_value_0000001 "OP_NOP"
46795   attribute \enum_value_0000010 "OP_ADD"
46796   attribute \enum_value_0000011 "OP_ADDPCIS"
46797   attribute \enum_value_0000100 "OP_AND"
46798   attribute \enum_value_0000101 "OP_ATTN"
46799   attribute \enum_value_0000110 "OP_B"
46800   attribute \enum_value_0000111 "OP_BC"
46801   attribute \enum_value_0001000 "OP_BCREG"
46802   attribute \enum_value_0001001 "OP_BPERM"
46803   attribute \enum_value_0001010 "OP_CMP"
46804   attribute \enum_value_0001011 "OP_CMPB"
46805   attribute \enum_value_0001100 "OP_CMPEQB"
46806   attribute \enum_value_0001101 "OP_CMPRB"
46807   attribute \enum_value_0001110 "OP_CNTZ"
46808   attribute \enum_value_0001111 "OP_CRAND"
46809   attribute \enum_value_0010000 "OP_CRANDC"
46810   attribute \enum_value_0010001 "OP_CREQV"
46811   attribute \enum_value_0010010 "OP_CRNAND"
46812   attribute \enum_value_0010011 "OP_CRNOR"
46813   attribute \enum_value_0010100 "OP_CROR"
46814   attribute \enum_value_0010101 "OP_CRORC"
46815   attribute \enum_value_0010110 "OP_CRXOR"
46816   attribute \enum_value_0010111 "OP_DARN"
46817   attribute \enum_value_0011000 "OP_DCBF"
46818   attribute \enum_value_0011001 "OP_DCBST"
46819   attribute \enum_value_0011010 "OP_DCBT"
46820   attribute \enum_value_0011011 "OP_DCBTST"
46821   attribute \enum_value_0011100 "OP_DCBZ"
46822   attribute \enum_value_0011101 "OP_DIV"
46823   attribute \enum_value_0011110 "OP_DIVE"
46824   attribute \enum_value_0011111 "OP_EXTS"
46825   attribute \enum_value_0100000 "OP_EXTSWSLI"
46826   attribute \enum_value_0100001 "OP_ICBI"
46827   attribute \enum_value_0100010 "OP_ICBT"
46828   attribute \enum_value_0100011 "OP_ISEL"
46829   attribute \enum_value_0100100 "OP_ISYNC"
46830   attribute \enum_value_0100101 "OP_LOAD"
46831   attribute \enum_value_0100110 "OP_STORE"
46832   attribute \enum_value_0100111 "OP_MADDHD"
46833   attribute \enum_value_0101000 "OP_MADDHDU"
46834   attribute \enum_value_0101001 "OP_MADDLD"
46835   attribute \enum_value_0101010 "OP_MCRF"
46836   attribute \enum_value_0101011 "OP_MCRXR"
46837   attribute \enum_value_0101100 "OP_MCRXRX"
46838   attribute \enum_value_0101101 "OP_MFCR"
46839   attribute \enum_value_0101110 "OP_MFSPR"
46840   attribute \enum_value_0101111 "OP_MOD"
46841   attribute \enum_value_0110000 "OP_MTCRF"
46842   attribute \enum_value_0110001 "OP_MTSPR"
46843   attribute \enum_value_0110010 "OP_MUL_L64"
46844   attribute \enum_value_0110011 "OP_MUL_H64"
46845   attribute \enum_value_0110100 "OP_MUL_H32"
46846   attribute \enum_value_0110101 "OP_OR"
46847   attribute \enum_value_0110110 "OP_POPCNT"
46848   attribute \enum_value_0110111 "OP_PRTY"
46849   attribute \enum_value_0111000 "OP_RLC"
46850   attribute \enum_value_0111001 "OP_RLCL"
46851   attribute \enum_value_0111010 "OP_RLCR"
46852   attribute \enum_value_0111011 "OP_SETB"
46853   attribute \enum_value_0111100 "OP_SHL"
46854   attribute \enum_value_0111101 "OP_SHR"
46855   attribute \enum_value_0111110 "OP_SYNC"
46856   attribute \enum_value_0111111 "OP_TRAP"
46857   attribute \enum_value_1000011 "OP_XOR"
46858   attribute \enum_value_1000100 "OP_SIM_CONFIG"
46859   attribute \enum_value_1000101 "OP_CROP"
46860   attribute \enum_value_1000110 "OP_RFID"
46861   attribute \enum_value_1000111 "OP_MFMSR"
46862   attribute \enum_value_1001000 "OP_MTMSRD"
46863   attribute \enum_value_1001001 "OP_SC"
46864   attribute \enum_value_1001010 "OP_MTMSR"
46865   attribute \enum_value_1001011 "OP_TLBIE"
46866   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46867   wire width 7 output 2 \dec31_dec_sub24_internal_op
46868   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46869   wire output 15 \dec31_dec_sub24_inv_a
46870   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46871   wire output 16 \dec31_dec_sub24_inv_out
46872   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46873   wire output 21 \dec31_dec_sub24_is_32b
46874   attribute \enum_base_type "LdstLen"
46875   attribute \enum_value_0000 "NONE"
46876   attribute \enum_value_0001 "is1B"
46877   attribute \enum_value_0010 "is2B"
46878   attribute \enum_value_0100 "is4B"
46879   attribute \enum_value_1000 "is8B"
46880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46881   wire width 4 output 11 \dec31_dec_sub24_ldst_len
46882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46883   wire output 23 \dec31_dec_sub24_lk
46884   attribute \enum_base_type "OutSel"
46885   attribute \enum_value_00 "NONE"
46886   attribute \enum_value_01 "RT"
46887   attribute \enum_value_10 "RA"
46888   attribute \enum_value_11 "SPR"
46889   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46890   wire width 2 output 8 \dec31_dec_sub24_out_sel
46891   attribute \enum_base_type "RC"
46892   attribute \enum_value_00 "NONE"
46893   attribute \enum_value_01 "ONE"
46894   attribute \enum_value_10 "RC"
46895   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46896   wire width 2 output 13 \dec31_dec_sub24_rc_sel
46897   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46898   wire output 20 \dec31_dec_sub24_rsrv
46899   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46900   wire output 24 \dec31_dec_sub24_sgl_pipe
46901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46902   wire output 22 \dec31_dec_sub24_sgn
46903   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
46904   wire output 19 \dec31_dec_sub24_sgn_ext
46905   attribute \enum_base_type "LDSTMode"
46906   attribute \enum_value_00 "NONE"
46907   attribute \enum_value_01 "update"
46908   attribute \enum_value_10 "cix"
46909   attribute \enum_value_11 "cx"
46910   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
46911   wire width 2 output 12 \dec31_dec_sub24_upd
46912   attribute \src "libresoc.v:31713.7-31713.15"
46913   wire \initial
46914   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
46915   wire width 32 input 25 \opcode_in
46916   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
46917   wire width 5 \opcode_switch
46918   attribute \src "libresoc.v:31713.7-31713.20"
46919   process $proc$libresoc.v:31713$706
46920     assign { } { }
46921     assign $0\initial[0:0] 1'0
46922     sync always
46923       update \initial $0\initial[0:0]
46924     sync init
46925   end
46926   attribute \src "libresoc.v:31970.3-31988.6"
46927   process $proc$libresoc.v:31970$682
46928     assign { } { }
46929     assign { } { }
46930     assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0]
46931     attribute \src "libresoc.v:31971.5-31971.29"
46932     switch \initial
46933       attribute \src "libresoc.v:31971.9-31971.17"
46934       case 1'1
46935       case
46936     end
46937     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46938     switch \opcode_switch
46939       attribute \src "libresoc.v:0.0-0.0"
46940       case 5'00000
46941         assign { } { }
46942         assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000
46943       attribute \src "libresoc.v:0.0-0.0"
46944       case 5'11000
46945         assign { } { }
46946         assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000
46947       attribute \src "libresoc.v:0.0-0.0"
46948       case 5'11001
46949         assign { } { }
46950         assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000
46951       attribute \src "libresoc.v:0.0-0.0"
46952       case 5'10000
46953         assign { } { }
46954         assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000
46955       case
46956         assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000
46957     end
46958     sync always
46959       update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0]
46960   end
46961   attribute \src "libresoc.v:31989.3-32007.6"
46962   process $proc$libresoc.v:31989$683
46963     assign { } { }
46964     assign { } { }
46965     assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0]
46966     attribute \src "libresoc.v:31990.5-31990.29"
46967     switch \initial
46968       attribute \src "libresoc.v:31990.9-31990.17"
46969       case 1'1
46970       case
46971     end
46972     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
46973     switch \opcode_switch
46974       attribute \src "libresoc.v:0.0-0.0"
46975       case 5'00000
46976         assign { } { }
46977         assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000
46978       attribute \src "libresoc.v:0.0-0.0"
46979       case 5'11000
46980         assign { } { }
46981         assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000
46982       attribute \src "libresoc.v:0.0-0.0"
46983       case 5'11001
46984         assign { } { }
46985         assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000
46986       attribute \src "libresoc.v:0.0-0.0"
46987       case 5'10000
46988         assign { } { }
46989         assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000
46990       case
46991         assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000
46992     end
46993     sync always
46994       update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0]
46995   end
46996   attribute \src "libresoc.v:32008.3-32026.6"
46997   process $proc$libresoc.v:32008$684
46998     assign { } { }
46999     assign { } { }
47000     assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0]
47001     attribute \src "libresoc.v:32009.5-32009.29"
47002     switch \initial
47003       attribute \src "libresoc.v:32009.9-32009.17"
47004       case 1'1
47005       case
47006     end
47007     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47008     switch \opcode_switch
47009       attribute \src "libresoc.v:0.0-0.0"
47010       case 5'00000
47011         assign { } { }
47012         assign $1\dec31_dec_sub24_upd[1:0] 2'00
47013       attribute \src "libresoc.v:0.0-0.0"
47014       case 5'11000
47015         assign { } { }
47016         assign $1\dec31_dec_sub24_upd[1:0] 2'00
47017       attribute \src "libresoc.v:0.0-0.0"
47018       case 5'11001
47019         assign { } { }
47020         assign $1\dec31_dec_sub24_upd[1:0] 2'00
47021       attribute \src "libresoc.v:0.0-0.0"
47022       case 5'10000
47023         assign { } { }
47024         assign $1\dec31_dec_sub24_upd[1:0] 2'00
47025       case
47026         assign $1\dec31_dec_sub24_upd[1:0] 2'00
47027     end
47028     sync always
47029       update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0]
47030   end
47031   attribute \src "libresoc.v:32027.3-32045.6"
47032   process $proc$libresoc.v:32027$685
47033     assign { } { }
47034     assign { } { }
47035     assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0]
47036     attribute \src "libresoc.v:32028.5-32028.29"
47037     switch \initial
47038       attribute \src "libresoc.v:32028.9-32028.17"
47039       case 1'1
47040       case
47041     end
47042     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47043     switch \opcode_switch
47044       attribute \src "libresoc.v:0.0-0.0"
47045       case 5'00000
47046         assign { } { }
47047         assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10
47048       attribute \src "libresoc.v:0.0-0.0"
47049       case 5'11000
47050         assign { } { }
47051         assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10
47052       attribute \src "libresoc.v:0.0-0.0"
47053       case 5'11001
47054         assign { } { }
47055         assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10
47056       attribute \src "libresoc.v:0.0-0.0"
47057       case 5'10000
47058         assign { } { }
47059         assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10
47060       case
47061         assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00
47062     end
47063     sync always
47064       update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0]
47065   end
47066   attribute \src "libresoc.v:32046.3-32064.6"
47067   process $proc$libresoc.v:32046$686
47068     assign { } { }
47069     assign { } { }
47070     assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0]
47071     attribute \src "libresoc.v:32047.5-32047.29"
47072     switch \initial
47073       attribute \src "libresoc.v:32047.9-32047.17"
47074       case 1'1
47075       case
47076     end
47077     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47078     switch \opcode_switch
47079       attribute \src "libresoc.v:0.0-0.0"
47080       case 5'00000
47081         assign { } { }
47082         assign $1\dec31_dec_sub24_cry_in[1:0] 2'00
47083       attribute \src "libresoc.v:0.0-0.0"
47084       case 5'11000
47085         assign { } { }
47086         assign $1\dec31_dec_sub24_cry_in[1:0] 2'00
47087       attribute \src "libresoc.v:0.0-0.0"
47088       case 5'11001
47089         assign { } { }
47090         assign $1\dec31_dec_sub24_cry_in[1:0] 2'00
47091       attribute \src "libresoc.v:0.0-0.0"
47092       case 5'10000
47093         assign { } { }
47094         assign $1\dec31_dec_sub24_cry_in[1:0] 2'00
47095       case
47096         assign $1\dec31_dec_sub24_cry_in[1:0] 2'00
47097     end
47098     sync always
47099       update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0]
47100   end
47101   attribute \src "libresoc.v:32065.3-32083.6"
47102   process $proc$libresoc.v:32065$687
47103     assign { } { }
47104     assign { } { }
47105     assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0]
47106     attribute \src "libresoc.v:32066.5-32066.29"
47107     switch \initial
47108       attribute \src "libresoc.v:32066.9-32066.17"
47109       case 1'1
47110       case
47111     end
47112     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47113     switch \opcode_switch
47114       attribute \src "libresoc.v:0.0-0.0"
47115       case 5'00000
47116         assign { } { }
47117         assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111
47118       attribute \src "libresoc.v:0.0-0.0"
47119       case 5'11000
47120         assign { } { }
47121         assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010
47122       attribute \src "libresoc.v:0.0-0.0"
47123       case 5'11001
47124         assign { } { }
47125         assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011
47126       attribute \src "libresoc.v:0.0-0.0"
47127       case 5'10000
47128         assign { } { }
47129         assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101
47130       case
47131         assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000
47132     end
47133     sync always
47134       update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0]
47135   end
47136   attribute \src "libresoc.v:32084.3-32102.6"
47137   process $proc$libresoc.v:32084$688
47138     assign { } { }
47139     assign { } { }
47140     assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0]
47141     attribute \src "libresoc.v:32085.5-32085.29"
47142     switch \initial
47143       attribute \src "libresoc.v:32085.9-32085.17"
47144       case 1'1
47145       case
47146     end
47147     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47148     switch \opcode_switch
47149       attribute \src "libresoc.v:0.0-0.0"
47150       case 5'00000
47151         assign { } { }
47152         assign $1\dec31_dec_sub24_inv_a[0:0] 1'0
47153       attribute \src "libresoc.v:0.0-0.0"
47154       case 5'11000
47155         assign { } { }
47156         assign $1\dec31_dec_sub24_inv_a[0:0] 1'0
47157       attribute \src "libresoc.v:0.0-0.0"
47158       case 5'11001
47159         assign { } { }
47160         assign $1\dec31_dec_sub24_inv_a[0:0] 1'0
47161       attribute \src "libresoc.v:0.0-0.0"
47162       case 5'10000
47163         assign { } { }
47164         assign $1\dec31_dec_sub24_inv_a[0:0] 1'0
47165       case
47166         assign $1\dec31_dec_sub24_inv_a[0:0] 1'0
47167     end
47168     sync always
47169       update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0]
47170   end
47171   attribute \src "libresoc.v:32103.3-32121.6"
47172   process $proc$libresoc.v:32103$689
47173     assign { } { }
47174     assign { } { }
47175     assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0]
47176     attribute \src "libresoc.v:32104.5-32104.29"
47177     switch \initial
47178       attribute \src "libresoc.v:32104.9-32104.17"
47179       case 1'1
47180       case
47181     end
47182     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47183     switch \opcode_switch
47184       attribute \src "libresoc.v:0.0-0.0"
47185       case 5'00000
47186         assign { } { }
47187         assign $1\dec31_dec_sub24_inv_out[0:0] 1'0
47188       attribute \src "libresoc.v:0.0-0.0"
47189       case 5'11000
47190         assign { } { }
47191         assign $1\dec31_dec_sub24_inv_out[0:0] 1'0
47192       attribute \src "libresoc.v:0.0-0.0"
47193       case 5'11001
47194         assign { } { }
47195         assign $1\dec31_dec_sub24_inv_out[0:0] 1'0
47196       attribute \src "libresoc.v:0.0-0.0"
47197       case 5'10000
47198         assign { } { }
47199         assign $1\dec31_dec_sub24_inv_out[0:0] 1'0
47200       case
47201         assign $1\dec31_dec_sub24_inv_out[0:0] 1'0
47202     end
47203     sync always
47204       update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0]
47205   end
47206   attribute \src "libresoc.v:32122.3-32140.6"
47207   process $proc$libresoc.v:32122$690
47208     assign { } { }
47209     assign { } { }
47210     assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0]
47211     attribute \src "libresoc.v:32123.5-32123.29"
47212     switch \initial
47213       attribute \src "libresoc.v:32123.9-32123.17"
47214       case 1'1
47215       case
47216     end
47217     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47218     switch \opcode_switch
47219       attribute \src "libresoc.v:0.0-0.0"
47220       case 5'00000
47221         assign { } { }
47222         assign $1\dec31_dec_sub24_cry_out[0:0] 1'0
47223       attribute \src "libresoc.v:0.0-0.0"
47224       case 5'11000
47225         assign { } { }
47226         assign $1\dec31_dec_sub24_cry_out[0:0] 1'1
47227       attribute \src "libresoc.v:0.0-0.0"
47228       case 5'11001
47229         assign { } { }
47230         assign $1\dec31_dec_sub24_cry_out[0:0] 1'1
47231       attribute \src "libresoc.v:0.0-0.0"
47232       case 5'10000
47233         assign { } { }
47234         assign $1\dec31_dec_sub24_cry_out[0:0] 1'0
47235       case
47236         assign $1\dec31_dec_sub24_cry_out[0:0] 1'0
47237     end
47238     sync always
47239       update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0]
47240   end
47241   attribute \src "libresoc.v:32141.3-32159.6"
47242   process $proc$libresoc.v:32141$691
47243     assign { } { }
47244     assign { } { }
47245     assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0]
47246     attribute \src "libresoc.v:32142.5-32142.29"
47247     switch \initial
47248       attribute \src "libresoc.v:32142.9-32142.17"
47249       case 1'1
47250       case
47251     end
47252     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47253     switch \opcode_switch
47254       attribute \src "libresoc.v:0.0-0.0"
47255       case 5'00000
47256         assign { } { }
47257         assign $1\dec31_dec_sub24_br[0:0] 1'0
47258       attribute \src "libresoc.v:0.0-0.0"
47259       case 5'11000
47260         assign { } { }
47261         assign $1\dec31_dec_sub24_br[0:0] 1'0
47262       attribute \src "libresoc.v:0.0-0.0"
47263       case 5'11001
47264         assign { } { }
47265         assign $1\dec31_dec_sub24_br[0:0] 1'0
47266       attribute \src "libresoc.v:0.0-0.0"
47267       case 5'10000
47268         assign { } { }
47269         assign $1\dec31_dec_sub24_br[0:0] 1'0
47270       case
47271         assign $1\dec31_dec_sub24_br[0:0] 1'0
47272     end
47273     sync always
47274       update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0]
47275   end
47276   attribute \src "libresoc.v:32160.3-32178.6"
47277   process $proc$libresoc.v:32160$692
47278     assign { } { }
47279     assign { } { }
47280     assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0]
47281     attribute \src "libresoc.v:32161.5-32161.29"
47282     switch \initial
47283       attribute \src "libresoc.v:32161.9-32161.17"
47284       case 1'1
47285       case
47286     end
47287     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47288     switch \opcode_switch
47289       attribute \src "libresoc.v:0.0-0.0"
47290       case 5'00000
47291         assign { } { }
47292         assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0
47293       attribute \src "libresoc.v:0.0-0.0"
47294       case 5'11000
47295         assign { } { }
47296         assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0
47297       attribute \src "libresoc.v:0.0-0.0"
47298       case 5'11001
47299         assign { } { }
47300         assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0
47301       attribute \src "libresoc.v:0.0-0.0"
47302       case 5'10000
47303         assign { } { }
47304         assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0
47305       case
47306         assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0
47307     end
47308     sync always
47309       update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0]
47310   end
47311   attribute \src "libresoc.v:32179.3-32197.6"
47312   process $proc$libresoc.v:32179$693
47313     assign { } { }
47314     assign { } { }
47315     assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0]
47316     attribute \src "libresoc.v:32180.5-32180.29"
47317     switch \initial
47318       attribute \src "libresoc.v:32180.9-32180.17"
47319       case 1'1
47320       case
47321     end
47322     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47323     switch \opcode_switch
47324       attribute \src "libresoc.v:0.0-0.0"
47325       case 5'00000
47326         assign { } { }
47327         assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100
47328       attribute \src "libresoc.v:0.0-0.0"
47329       case 5'11000
47330         assign { } { }
47331         assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101
47332       attribute \src "libresoc.v:0.0-0.0"
47333       case 5'11001
47334         assign { } { }
47335         assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101
47336       attribute \src "libresoc.v:0.0-0.0"
47337       case 5'10000
47338         assign { } { }
47339         assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101
47340       case
47341         assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000
47342     end
47343     sync always
47344       update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0]
47345   end
47346   attribute \src "libresoc.v:32198.3-32216.6"
47347   process $proc$libresoc.v:32198$694
47348     assign { } { }
47349     assign { } { }
47350     assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0]
47351     attribute \src "libresoc.v:32199.5-32199.29"
47352     switch \initial
47353       attribute \src "libresoc.v:32199.9-32199.17"
47354       case 1'1
47355       case
47356     end
47357     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47358     switch \opcode_switch
47359       attribute \src "libresoc.v:0.0-0.0"
47360       case 5'00000
47361         assign { } { }
47362         assign $1\dec31_dec_sub24_rsrv[0:0] 1'0
47363       attribute \src "libresoc.v:0.0-0.0"
47364       case 5'11000
47365         assign { } { }
47366         assign $1\dec31_dec_sub24_rsrv[0:0] 1'0
47367       attribute \src "libresoc.v:0.0-0.0"
47368       case 5'11001
47369         assign { } { }
47370         assign $1\dec31_dec_sub24_rsrv[0:0] 1'0
47371       attribute \src "libresoc.v:0.0-0.0"
47372       case 5'10000
47373         assign { } { }
47374         assign $1\dec31_dec_sub24_rsrv[0:0] 1'0
47375       case
47376         assign $1\dec31_dec_sub24_rsrv[0:0] 1'0
47377     end
47378     sync always
47379       update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0]
47380   end
47381   attribute \src "libresoc.v:32217.3-32235.6"
47382   process $proc$libresoc.v:32217$695
47383     assign { } { }
47384     assign { } { }
47385     assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0]
47386     attribute \src "libresoc.v:32218.5-32218.29"
47387     switch \initial
47388       attribute \src "libresoc.v:32218.9-32218.17"
47389       case 1'1
47390       case
47391     end
47392     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47393     switch \opcode_switch
47394       attribute \src "libresoc.v:0.0-0.0"
47395       case 5'00000
47396         assign { } { }
47397         assign $1\dec31_dec_sub24_is_32b[0:0] 1'1
47398       attribute \src "libresoc.v:0.0-0.0"
47399       case 5'11000
47400         assign { } { }
47401         assign $1\dec31_dec_sub24_is_32b[0:0] 1'1
47402       attribute \src "libresoc.v:0.0-0.0"
47403       case 5'11001
47404         assign { } { }
47405         assign $1\dec31_dec_sub24_is_32b[0:0] 1'1
47406       attribute \src "libresoc.v:0.0-0.0"
47407       case 5'10000
47408         assign { } { }
47409         assign $1\dec31_dec_sub24_is_32b[0:0] 1'1
47410       case
47411         assign $1\dec31_dec_sub24_is_32b[0:0] 1'0
47412     end
47413     sync always
47414       update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0]
47415   end
47416   attribute \src "libresoc.v:32236.3-32254.6"
47417   process $proc$libresoc.v:32236$696
47418     assign { } { }
47419     assign { } { }
47420     assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0]
47421     attribute \src "libresoc.v:32237.5-32237.29"
47422     switch \initial
47423       attribute \src "libresoc.v:32237.9-32237.17"
47424       case 1'1
47425       case
47426     end
47427     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47428     switch \opcode_switch
47429       attribute \src "libresoc.v:0.0-0.0"
47430       case 5'00000
47431         assign { } { }
47432         assign $1\dec31_dec_sub24_sgn[0:0] 1'0
47433       attribute \src "libresoc.v:0.0-0.0"
47434       case 5'11000
47435         assign { } { }
47436         assign $1\dec31_dec_sub24_sgn[0:0] 1'1
47437       attribute \src "libresoc.v:0.0-0.0"
47438       case 5'11001
47439         assign { } { }
47440         assign $1\dec31_dec_sub24_sgn[0:0] 1'1
47441       attribute \src "libresoc.v:0.0-0.0"
47442       case 5'10000
47443         assign { } { }
47444         assign $1\dec31_dec_sub24_sgn[0:0] 1'0
47445       case
47446         assign $1\dec31_dec_sub24_sgn[0:0] 1'0
47447     end
47448     sync always
47449       update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0]
47450   end
47451   attribute \src "libresoc.v:32255.3-32273.6"
47452   process $proc$libresoc.v:32255$697
47453     assign { } { }
47454     assign { } { }
47455     assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0]
47456     attribute \src "libresoc.v:32256.5-32256.29"
47457     switch \initial
47458       attribute \src "libresoc.v:32256.9-32256.17"
47459       case 1'1
47460       case
47461     end
47462     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47463     switch \opcode_switch
47464       attribute \src "libresoc.v:0.0-0.0"
47465       case 5'00000
47466         assign { } { }
47467         assign $1\dec31_dec_sub24_lk[0:0] 1'0
47468       attribute \src "libresoc.v:0.0-0.0"
47469       case 5'11000
47470         assign { } { }
47471         assign $1\dec31_dec_sub24_lk[0:0] 1'0
47472       attribute \src "libresoc.v:0.0-0.0"
47473       case 5'11001
47474         assign { } { }
47475         assign $1\dec31_dec_sub24_lk[0:0] 1'0
47476       attribute \src "libresoc.v:0.0-0.0"
47477       case 5'10000
47478         assign { } { }
47479         assign $1\dec31_dec_sub24_lk[0:0] 1'0
47480       case
47481         assign $1\dec31_dec_sub24_lk[0:0] 1'0
47482     end
47483     sync always
47484       update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0]
47485   end
47486   attribute \src "libresoc.v:32274.3-32292.6"
47487   process $proc$libresoc.v:32274$698
47488     assign { } { }
47489     assign { } { }
47490     assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0]
47491     attribute \src "libresoc.v:32275.5-32275.29"
47492     switch \initial
47493       attribute \src "libresoc.v:32275.9-32275.17"
47494       case 1'1
47495       case
47496     end
47497     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47498     switch \opcode_switch
47499       attribute \src "libresoc.v:0.0-0.0"
47500       case 5'00000
47501         assign { } { }
47502         assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0
47503       attribute \src "libresoc.v:0.0-0.0"
47504       case 5'11000
47505         assign { } { }
47506         assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0
47507       attribute \src "libresoc.v:0.0-0.0"
47508       case 5'11001
47509         assign { } { }
47510         assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0
47511       attribute \src "libresoc.v:0.0-0.0"
47512       case 5'10000
47513         assign { } { }
47514         assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0
47515       case
47516         assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0
47517     end
47518     sync always
47519       update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0]
47520   end
47521   attribute \src "libresoc.v:32293.3-32311.6"
47522   process $proc$libresoc.v:32293$699
47523     assign { } { }
47524     assign { } { }
47525     assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0]
47526     attribute \src "libresoc.v:32294.5-32294.29"
47527     switch \initial
47528       attribute \src "libresoc.v:32294.9-32294.17"
47529       case 1'1
47530       case
47531     end
47532     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47533     switch \opcode_switch
47534       attribute \src "libresoc.v:0.0-0.0"
47535       case 5'00000
47536         assign { } { }
47537         assign $1\dec31_dec_sub24_form[4:0] 5'01000
47538       attribute \src "libresoc.v:0.0-0.0"
47539       case 5'11000
47540         assign { } { }
47541         assign $1\dec31_dec_sub24_form[4:0] 5'01000
47542       attribute \src "libresoc.v:0.0-0.0"
47543       case 5'11001
47544         assign { } { }
47545         assign $1\dec31_dec_sub24_form[4:0] 5'01000
47546       attribute \src "libresoc.v:0.0-0.0"
47547       case 5'10000
47548         assign { } { }
47549         assign $1\dec31_dec_sub24_form[4:0] 5'01000
47550       case
47551         assign $1\dec31_dec_sub24_form[4:0] 5'00000
47552     end
47553     sync always
47554       update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0]
47555   end
47556   attribute \src "libresoc.v:32312.3-32330.6"
47557   process $proc$libresoc.v:32312$700
47558     assign { } { }
47559     assign { } { }
47560     assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0]
47561     attribute \src "libresoc.v:32313.5-32313.29"
47562     switch \initial
47563       attribute \src "libresoc.v:32313.9-32313.17"
47564       case 1'1
47565       case
47566     end
47567     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47568     switch \opcode_switch
47569       attribute \src "libresoc.v:0.0-0.0"
47570       case 5'00000
47571         assign { } { }
47572         assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000
47573       attribute \src "libresoc.v:0.0-0.0"
47574       case 5'11000
47575         assign { } { }
47576         assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000
47577       attribute \src "libresoc.v:0.0-0.0"
47578       case 5'11001
47579         assign { } { }
47580         assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000
47581       attribute \src "libresoc.v:0.0-0.0"
47582       case 5'10000
47583         assign { } { }
47584         assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000
47585       case
47586         assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000
47587     end
47588     sync always
47589       update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0]
47590   end
47591   attribute \src "libresoc.v:32331.3-32349.6"
47592   process $proc$libresoc.v:32331$701
47593     assign { } { }
47594     assign { } { }
47595     assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0]
47596     attribute \src "libresoc.v:32332.5-32332.29"
47597     switch \initial
47598       attribute \src "libresoc.v:32332.9-32332.17"
47599       case 1'1
47600       case
47601     end
47602     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47603     switch \opcode_switch
47604       attribute \src "libresoc.v:0.0-0.0"
47605       case 5'00000
47606         assign { } { }
47607         assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001
47608       attribute \src "libresoc.v:0.0-0.0"
47609       case 5'11000
47610         assign { } { }
47611         assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001
47612       attribute \src "libresoc.v:0.0-0.0"
47613       case 5'11001
47614         assign { } { }
47615         assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011
47616       attribute \src "libresoc.v:0.0-0.0"
47617       case 5'10000
47618         assign { } { }
47619         assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001
47620       case
47621         assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000
47622     end
47623     sync always
47624       update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0]
47625   end
47626   attribute \src "libresoc.v:32350.3-32368.6"
47627   process $proc$libresoc.v:32350$702
47628     assign { } { }
47629     assign { } { }
47630     assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0]
47631     attribute \src "libresoc.v:32351.5-32351.29"
47632     switch \initial
47633       attribute \src "libresoc.v:32351.9-32351.17"
47634       case 1'1
47635       case
47636     end
47637     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47638     switch \opcode_switch
47639       attribute \src "libresoc.v:0.0-0.0"
47640       case 5'00000
47641         assign { } { }
47642         assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01
47643       attribute \src "libresoc.v:0.0-0.0"
47644       case 5'11000
47645         assign { } { }
47646         assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01
47647       attribute \src "libresoc.v:0.0-0.0"
47648       case 5'11001
47649         assign { } { }
47650         assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01
47651       attribute \src "libresoc.v:0.0-0.0"
47652       case 5'10000
47653         assign { } { }
47654         assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01
47655       case
47656         assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00
47657     end
47658     sync always
47659       update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0]
47660   end
47661   attribute \src "libresoc.v:32369.3-32387.6"
47662   process $proc$libresoc.v:32369$703
47663     assign { } { }
47664     assign { } { }
47665     assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0]
47666     attribute \src "libresoc.v:32370.5-32370.29"
47667     switch \initial
47668       attribute \src "libresoc.v:32370.9-32370.17"
47669       case 1'1
47670       case
47671     end
47672     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47673     switch \opcode_switch
47674       attribute \src "libresoc.v:0.0-0.0"
47675       case 5'00000
47676         assign { } { }
47677         assign $1\dec31_dec_sub24_out_sel[1:0] 2'10
47678       attribute \src "libresoc.v:0.0-0.0"
47679       case 5'11000
47680         assign { } { }
47681         assign $1\dec31_dec_sub24_out_sel[1:0] 2'10
47682       attribute \src "libresoc.v:0.0-0.0"
47683       case 5'11001
47684         assign { } { }
47685         assign $1\dec31_dec_sub24_out_sel[1:0] 2'10
47686       attribute \src "libresoc.v:0.0-0.0"
47687       case 5'10000
47688         assign { } { }
47689         assign $1\dec31_dec_sub24_out_sel[1:0] 2'10
47690       case
47691         assign $1\dec31_dec_sub24_out_sel[1:0] 2'00
47692     end
47693     sync always
47694       update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0]
47695   end
47696   attribute \src "libresoc.v:32388.3-32406.6"
47697   process $proc$libresoc.v:32388$704
47698     assign { } { }
47699     assign { } { }
47700     assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0]
47701     attribute \src "libresoc.v:32389.5-32389.29"
47702     switch \initial
47703       attribute \src "libresoc.v:32389.9-32389.17"
47704       case 1'1
47705       case
47706     end
47707     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47708     switch \opcode_switch
47709       attribute \src "libresoc.v:0.0-0.0"
47710       case 5'00000
47711         assign { } { }
47712         assign $1\dec31_dec_sub24_cr_in[2:0] 3'000
47713       attribute \src "libresoc.v:0.0-0.0"
47714       case 5'11000
47715         assign { } { }
47716         assign $1\dec31_dec_sub24_cr_in[2:0] 3'000
47717       attribute \src "libresoc.v:0.0-0.0"
47718       case 5'11001
47719         assign { } { }
47720         assign $1\dec31_dec_sub24_cr_in[2:0] 3'000
47721       attribute \src "libresoc.v:0.0-0.0"
47722       case 5'10000
47723         assign { } { }
47724         assign $1\dec31_dec_sub24_cr_in[2:0] 3'000
47725       case
47726         assign $1\dec31_dec_sub24_cr_in[2:0] 3'000
47727     end
47728     sync always
47729       update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0]
47730   end
47731   attribute \src "libresoc.v:32407.3-32425.6"
47732   process $proc$libresoc.v:32407$705
47733     assign { } { }
47734     assign { } { }
47735     assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0]
47736     attribute \src "libresoc.v:32408.5-32408.29"
47737     switch \initial
47738       attribute \src "libresoc.v:32408.9-32408.17"
47739       case 1'1
47740       case
47741     end
47742     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
47743     switch \opcode_switch
47744       attribute \src "libresoc.v:0.0-0.0"
47745       case 5'00000
47746         assign { } { }
47747         assign $1\dec31_dec_sub24_cr_out[2:0] 3'001
47748       attribute \src "libresoc.v:0.0-0.0"
47749       case 5'11000
47750         assign { } { }
47751         assign $1\dec31_dec_sub24_cr_out[2:0] 3'001
47752       attribute \src "libresoc.v:0.0-0.0"
47753       case 5'11001
47754         assign { } { }
47755         assign $1\dec31_dec_sub24_cr_out[2:0] 3'001
47756       attribute \src "libresoc.v:0.0-0.0"
47757       case 5'10000
47758         assign { } { }
47759         assign $1\dec31_dec_sub24_cr_out[2:0] 3'001
47760       case
47761         assign $1\dec31_dec_sub24_cr_out[2:0] 3'000
47762     end
47763     sync always
47764       update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0]
47765   end
47766   connect \opcode_switch \opcode_in [10:6]
47767 end
47768 attribute \src "libresoc.v:32431.1-33938.10"
47769 attribute \cells_not_processed 1
47770 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26"
47771 attribute \generator "nMigen"
47772 module \dec31_dec_sub26
47773   attribute \src "libresoc.v:32949.3-33000.6"
47774   wire width 8 $0\dec31_dec_sub26_asmcode[7:0]
47775   attribute \src "libresoc.v:33157.3-33208.6"
47776   wire $0\dec31_dec_sub26_br[0:0]
47777   attribute \src "libresoc.v:33833.3-33884.6"
47778   wire width 3 $0\dec31_dec_sub26_cr_in[2:0]
47779   attribute \src "libresoc.v:33885.3-33936.6"
47780   wire width 3 $0\dec31_dec_sub26_cr_out[2:0]
47781   attribute \src "libresoc.v:32897.3-32948.6"
47782   wire width 2 $0\dec31_dec_sub26_cry_in[1:0]
47783   attribute \src "libresoc.v:33105.3-33156.6"
47784   wire $0\dec31_dec_sub26_cry_out[0:0]
47785   attribute \src "libresoc.v:33573.3-33624.6"
47786   wire width 5 $0\dec31_dec_sub26_form[4:0]
47787   attribute \src "libresoc.v:32689.3-32740.6"
47788   wire width 12 $0\dec31_dec_sub26_function_unit[11:0]
47789   attribute \src "libresoc.v:33625.3-33676.6"
47790   wire width 3 $0\dec31_dec_sub26_in1_sel[2:0]
47791   attribute \src "libresoc.v:33677.3-33728.6"
47792   wire width 4 $0\dec31_dec_sub26_in2_sel[3:0]
47793   attribute \src "libresoc.v:33729.3-33780.6"
47794   wire width 2 $0\dec31_dec_sub26_in3_sel[1:0]
47795   attribute \src "libresoc.v:33261.3-33312.6"
47796   wire width 7 $0\dec31_dec_sub26_internal_op[6:0]
47797   attribute \src "libresoc.v:33001.3-33052.6"
47798   wire $0\dec31_dec_sub26_inv_a[0:0]
47799   attribute \src "libresoc.v:33053.3-33104.6"
47800   wire $0\dec31_dec_sub26_inv_out[0:0]
47801   attribute \src "libresoc.v:33365.3-33416.6"
47802   wire $0\dec31_dec_sub26_is_32b[0:0]
47803   attribute \src "libresoc.v:32741.3-32792.6"
47804   wire width 4 $0\dec31_dec_sub26_ldst_len[3:0]
47805   attribute \src "libresoc.v:33469.3-33520.6"
47806   wire $0\dec31_dec_sub26_lk[0:0]
47807   attribute \src "libresoc.v:33781.3-33832.6"
47808   wire width 2 $0\dec31_dec_sub26_out_sel[1:0]
47809   attribute \src "libresoc.v:32845.3-32896.6"
47810   wire width 2 $0\dec31_dec_sub26_rc_sel[1:0]
47811   attribute \src "libresoc.v:33313.3-33364.6"
47812   wire $0\dec31_dec_sub26_rsrv[0:0]
47813   attribute \src "libresoc.v:33521.3-33572.6"
47814   wire $0\dec31_dec_sub26_sgl_pipe[0:0]
47815   attribute \src "libresoc.v:33417.3-33468.6"
47816   wire $0\dec31_dec_sub26_sgn[0:0]
47817   attribute \src "libresoc.v:33209.3-33260.6"
47818   wire $0\dec31_dec_sub26_sgn_ext[0:0]
47819   attribute \src "libresoc.v:32793.3-32844.6"
47820   wire width 2 $0\dec31_dec_sub26_upd[1:0]
47821   attribute \src "libresoc.v:32432.7-32432.20"
47822   wire $0\initial[0:0]
47823   attribute \src "libresoc.v:32949.3-33000.6"
47824   wire width 8 $1\dec31_dec_sub26_asmcode[7:0]
47825   attribute \src "libresoc.v:33157.3-33208.6"
47826   wire $1\dec31_dec_sub26_br[0:0]
47827   attribute \src "libresoc.v:33833.3-33884.6"
47828   wire width 3 $1\dec31_dec_sub26_cr_in[2:0]
47829   attribute \src "libresoc.v:33885.3-33936.6"
47830   wire width 3 $1\dec31_dec_sub26_cr_out[2:0]
47831   attribute \src "libresoc.v:32897.3-32948.6"
47832   wire width 2 $1\dec31_dec_sub26_cry_in[1:0]
47833   attribute \src "libresoc.v:33105.3-33156.6"
47834   wire $1\dec31_dec_sub26_cry_out[0:0]
47835   attribute \src "libresoc.v:33573.3-33624.6"
47836   wire width 5 $1\dec31_dec_sub26_form[4:0]
47837   attribute \src "libresoc.v:32689.3-32740.6"
47838   wire width 12 $1\dec31_dec_sub26_function_unit[11:0]
47839   attribute \src "libresoc.v:33625.3-33676.6"
47840   wire width 3 $1\dec31_dec_sub26_in1_sel[2:0]
47841   attribute \src "libresoc.v:33677.3-33728.6"
47842   wire width 4 $1\dec31_dec_sub26_in2_sel[3:0]
47843   attribute \src "libresoc.v:33729.3-33780.6"
47844   wire width 2 $1\dec31_dec_sub26_in3_sel[1:0]
47845   attribute \src "libresoc.v:33261.3-33312.6"
47846   wire width 7 $1\dec31_dec_sub26_internal_op[6:0]
47847   attribute \src "libresoc.v:33001.3-33052.6"
47848   wire $1\dec31_dec_sub26_inv_a[0:0]
47849   attribute \src "libresoc.v:33053.3-33104.6"
47850   wire $1\dec31_dec_sub26_inv_out[0:0]
47851   attribute \src "libresoc.v:33365.3-33416.6"
47852   wire $1\dec31_dec_sub26_is_32b[0:0]
47853   attribute \src "libresoc.v:32741.3-32792.6"
47854   wire width 4 $1\dec31_dec_sub26_ldst_len[3:0]
47855   attribute \src "libresoc.v:33469.3-33520.6"
47856   wire $1\dec31_dec_sub26_lk[0:0]
47857   attribute \src "libresoc.v:33781.3-33832.6"
47858   wire width 2 $1\dec31_dec_sub26_out_sel[1:0]
47859   attribute \src "libresoc.v:32845.3-32896.6"
47860   wire width 2 $1\dec31_dec_sub26_rc_sel[1:0]
47861   attribute \src "libresoc.v:33313.3-33364.6"
47862   wire $1\dec31_dec_sub26_rsrv[0:0]
47863   attribute \src "libresoc.v:33521.3-33572.6"
47864   wire $1\dec31_dec_sub26_sgl_pipe[0:0]
47865   attribute \src "libresoc.v:33417.3-33468.6"
47866   wire $1\dec31_dec_sub26_sgn[0:0]
47867   attribute \src "libresoc.v:33209.3-33260.6"
47868   wire $1\dec31_dec_sub26_sgn_ext[0:0]
47869   attribute \src "libresoc.v:32793.3-32844.6"
47870   wire width 2 $1\dec31_dec_sub26_upd[1:0]
47871   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47872   wire width 8 output 4 \dec31_dec_sub26_asmcode
47873   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
47874   wire output 18 \dec31_dec_sub26_br
47875   attribute \enum_base_type "CRInSel"
47876   attribute \enum_value_000 "NONE"
47877   attribute \enum_value_001 "CR0"
47878   attribute \enum_value_010 "BI"
47879   attribute \enum_value_011 "BFA"
47880   attribute \enum_value_100 "BA_BB"
47881   attribute \enum_value_101 "BC"
47882   attribute \enum_value_110 "WHOLE_REG"
47883   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47884   wire width 3 output 9 \dec31_dec_sub26_cr_in
47885   attribute \enum_base_type "CROutSel"
47886   attribute \enum_value_000 "NONE"
47887   attribute \enum_value_001 "CR0"
47888   attribute \enum_value_010 "BF"
47889   attribute \enum_value_011 "BT"
47890   attribute \enum_value_100 "WHOLE_REG"
47891   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47892   wire width 3 output 10 \dec31_dec_sub26_cr_out
47893   attribute \enum_base_type "CryIn"
47894   attribute \enum_value_00 "ZERO"
47895   attribute \enum_value_01 "ONE"
47896   attribute \enum_value_10 "CA"
47897   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47898   wire width 2 output 14 \dec31_dec_sub26_cry_in
47899   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
47900   wire output 17 \dec31_dec_sub26_cry_out
47901   attribute \enum_base_type "Form"
47902   attribute \enum_value_00000 "NONE"
47903   attribute \enum_value_00001 "I"
47904   attribute \enum_value_00010 "B"
47905   attribute \enum_value_00011 "SC"
47906   attribute \enum_value_00100 "D"
47907   attribute \enum_value_00101 "DS"
47908   attribute \enum_value_00110 "DQ"
47909   attribute \enum_value_00111 "DX"
47910   attribute \enum_value_01000 "X"
47911   attribute \enum_value_01001 "XL"
47912   attribute \enum_value_01010 "XFX"
47913   attribute \enum_value_01011 "XFL"
47914   attribute \enum_value_01100 "XX1"
47915   attribute \enum_value_01101 "XX2"
47916   attribute \enum_value_01110 "XX3"
47917   attribute \enum_value_01111 "XX4"
47918   attribute \enum_value_10000 "XS"
47919   attribute \enum_value_10001 "XO"
47920   attribute \enum_value_10010 "A"
47921   attribute \enum_value_10011 "M"
47922   attribute \enum_value_10100 "MD"
47923   attribute \enum_value_10101 "MDS"
47924   attribute \enum_value_10110 "VA"
47925   attribute \enum_value_10111 "VC"
47926   attribute \enum_value_11000 "VX"
47927   attribute \enum_value_11001 "EVX"
47928   attribute \enum_value_11010 "EVS"
47929   attribute \enum_value_11011 "Z22"
47930   attribute \enum_value_11100 "Z23"
47931   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47932   wire width 5 output 3 \dec31_dec_sub26_form
47933   attribute \enum_base_type "Function"
47934   attribute \enum_value_000000000000 "NONE"
47935   attribute \enum_value_000000000010 "ALU"
47936   attribute \enum_value_000000000100 "LDST"
47937   attribute \enum_value_000000001000 "SHIFT_ROT"
47938   attribute \enum_value_000000010000 "LOGICAL"
47939   attribute \enum_value_000000100000 "BRANCH"
47940   attribute \enum_value_000001000000 "CR"
47941   attribute \enum_value_000010000000 "TRAP"
47942   attribute \enum_value_000100000000 "MUL"
47943   attribute \enum_value_001000000000 "DIV"
47944   attribute \enum_value_010000000000 "SPR"
47945   attribute \enum_value_100000000000 "MMU"
47946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47947   wire width 12 output 1 \dec31_dec_sub26_function_unit
47948   attribute \enum_base_type "In1Sel"
47949   attribute \enum_value_000 "NONE"
47950   attribute \enum_value_001 "RA"
47951   attribute \enum_value_010 "RA_OR_ZERO"
47952   attribute \enum_value_011 "SPR"
47953   attribute \enum_value_100 "RS"
47954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47955   wire width 3 output 5 \dec31_dec_sub26_in1_sel
47956   attribute \enum_base_type "In2Sel"
47957   attribute \enum_value_0000 "NONE"
47958   attribute \enum_value_0001 "RB"
47959   attribute \enum_value_0010 "CONST_UI"
47960   attribute \enum_value_0011 "CONST_SI"
47961   attribute \enum_value_0100 "CONST_UI_HI"
47962   attribute \enum_value_0101 "CONST_SI_HI"
47963   attribute \enum_value_0110 "CONST_LI"
47964   attribute \enum_value_0111 "CONST_BD"
47965   attribute \enum_value_1000 "CONST_DS"
47966   attribute \enum_value_1001 "CONST_M1"
47967   attribute \enum_value_1010 "CONST_SH"
47968   attribute \enum_value_1011 "CONST_SH32"
47969   attribute \enum_value_1100 "SPR"
47970   attribute \enum_value_1101 "RS"
47971   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47972   wire width 4 output 6 \dec31_dec_sub26_in2_sel
47973   attribute \enum_base_type "In3Sel"
47974   attribute \enum_value_00 "NONE"
47975   attribute \enum_value_01 "RS"
47976   attribute \enum_value_10 "RB"
47977   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
47978   wire width 2 output 7 \dec31_dec_sub26_in3_sel
47979   attribute \enum_base_type "MicrOp"
47980   attribute \enum_value_0000000 "OP_ILLEGAL"
47981   attribute \enum_value_0000001 "OP_NOP"
47982   attribute \enum_value_0000010 "OP_ADD"
47983   attribute \enum_value_0000011 "OP_ADDPCIS"
47984   attribute \enum_value_0000100 "OP_AND"
47985   attribute \enum_value_0000101 "OP_ATTN"
47986   attribute \enum_value_0000110 "OP_B"
47987   attribute \enum_value_0000111 "OP_BC"
47988   attribute \enum_value_0001000 "OP_BCREG"
47989   attribute \enum_value_0001001 "OP_BPERM"
47990   attribute \enum_value_0001010 "OP_CMP"
47991   attribute \enum_value_0001011 "OP_CMPB"
47992   attribute \enum_value_0001100 "OP_CMPEQB"
47993   attribute \enum_value_0001101 "OP_CMPRB"
47994   attribute \enum_value_0001110 "OP_CNTZ"
47995   attribute \enum_value_0001111 "OP_CRAND"
47996   attribute \enum_value_0010000 "OP_CRANDC"
47997   attribute \enum_value_0010001 "OP_CREQV"
47998   attribute \enum_value_0010010 "OP_CRNAND"
47999   attribute \enum_value_0010011 "OP_CRNOR"
48000   attribute \enum_value_0010100 "OP_CROR"
48001   attribute \enum_value_0010101 "OP_CRORC"
48002   attribute \enum_value_0010110 "OP_CRXOR"
48003   attribute \enum_value_0010111 "OP_DARN"
48004   attribute \enum_value_0011000 "OP_DCBF"
48005   attribute \enum_value_0011001 "OP_DCBST"
48006   attribute \enum_value_0011010 "OP_DCBT"
48007   attribute \enum_value_0011011 "OP_DCBTST"
48008   attribute \enum_value_0011100 "OP_DCBZ"
48009   attribute \enum_value_0011101 "OP_DIV"
48010   attribute \enum_value_0011110 "OP_DIVE"
48011   attribute \enum_value_0011111 "OP_EXTS"
48012   attribute \enum_value_0100000 "OP_EXTSWSLI"
48013   attribute \enum_value_0100001 "OP_ICBI"
48014   attribute \enum_value_0100010 "OP_ICBT"
48015   attribute \enum_value_0100011 "OP_ISEL"
48016   attribute \enum_value_0100100 "OP_ISYNC"
48017   attribute \enum_value_0100101 "OP_LOAD"
48018   attribute \enum_value_0100110 "OP_STORE"
48019   attribute \enum_value_0100111 "OP_MADDHD"
48020   attribute \enum_value_0101000 "OP_MADDHDU"
48021   attribute \enum_value_0101001 "OP_MADDLD"
48022   attribute \enum_value_0101010 "OP_MCRF"
48023   attribute \enum_value_0101011 "OP_MCRXR"
48024   attribute \enum_value_0101100 "OP_MCRXRX"
48025   attribute \enum_value_0101101 "OP_MFCR"
48026   attribute \enum_value_0101110 "OP_MFSPR"
48027   attribute \enum_value_0101111 "OP_MOD"
48028   attribute \enum_value_0110000 "OP_MTCRF"
48029   attribute \enum_value_0110001 "OP_MTSPR"
48030   attribute \enum_value_0110010 "OP_MUL_L64"
48031   attribute \enum_value_0110011 "OP_MUL_H64"
48032   attribute \enum_value_0110100 "OP_MUL_H32"
48033   attribute \enum_value_0110101 "OP_OR"
48034   attribute \enum_value_0110110 "OP_POPCNT"
48035   attribute \enum_value_0110111 "OP_PRTY"
48036   attribute \enum_value_0111000 "OP_RLC"
48037   attribute \enum_value_0111001 "OP_RLCL"
48038   attribute \enum_value_0111010 "OP_RLCR"
48039   attribute \enum_value_0111011 "OP_SETB"
48040   attribute \enum_value_0111100 "OP_SHL"
48041   attribute \enum_value_0111101 "OP_SHR"
48042   attribute \enum_value_0111110 "OP_SYNC"
48043   attribute \enum_value_0111111 "OP_TRAP"
48044   attribute \enum_value_1000011 "OP_XOR"
48045   attribute \enum_value_1000100 "OP_SIM_CONFIG"
48046   attribute \enum_value_1000101 "OP_CROP"
48047   attribute \enum_value_1000110 "OP_RFID"
48048   attribute \enum_value_1000111 "OP_MFMSR"
48049   attribute \enum_value_1001000 "OP_MTMSRD"
48050   attribute \enum_value_1001001 "OP_SC"
48051   attribute \enum_value_1001010 "OP_MTMSR"
48052   attribute \enum_value_1001011 "OP_TLBIE"
48053   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
48054   wire width 7 output 2 \dec31_dec_sub26_internal_op
48055   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48056   wire output 15 \dec31_dec_sub26_inv_a
48057   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48058   wire output 16 \dec31_dec_sub26_inv_out
48059   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48060   wire output 21 \dec31_dec_sub26_is_32b
48061   attribute \enum_base_type "LdstLen"
48062   attribute \enum_value_0000 "NONE"
48063   attribute \enum_value_0001 "is1B"
48064   attribute \enum_value_0010 "is2B"
48065   attribute \enum_value_0100 "is4B"
48066   attribute \enum_value_1000 "is8B"
48067   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
48068   wire width 4 output 11 \dec31_dec_sub26_ldst_len
48069   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48070   wire output 23 \dec31_dec_sub26_lk
48071   attribute \enum_base_type "OutSel"
48072   attribute \enum_value_00 "NONE"
48073   attribute \enum_value_01 "RT"
48074   attribute \enum_value_10 "RA"
48075   attribute \enum_value_11 "SPR"
48076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
48077   wire width 2 output 8 \dec31_dec_sub26_out_sel
48078   attribute \enum_base_type "RC"
48079   attribute \enum_value_00 "NONE"
48080   attribute \enum_value_01 "ONE"
48081   attribute \enum_value_10 "RC"
48082   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
48083   wire width 2 output 13 \dec31_dec_sub26_rc_sel
48084   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48085   wire output 20 \dec31_dec_sub26_rsrv
48086   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48087   wire output 24 \dec31_dec_sub26_sgl_pipe
48088   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48089   wire output 22 \dec31_dec_sub26_sgn
48090   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
48091   wire output 19 \dec31_dec_sub26_sgn_ext
48092   attribute \enum_base_type "LDSTMode"
48093   attribute \enum_value_00 "NONE"
48094   attribute \enum_value_01 "update"
48095   attribute \enum_value_10 "cix"
48096   attribute \enum_value_11 "cx"
48097   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
48098   wire width 2 output 12 \dec31_dec_sub26_upd
48099   attribute \src "libresoc.v:32432.7-32432.15"
48100   wire \initial
48101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
48102   wire width 32 input 25 \opcode_in
48103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
48104   wire width 5 \opcode_switch
48105   attribute \src "libresoc.v:32432.7-32432.20"
48106   process $proc$libresoc.v:32432$731
48107     assign { } { }
48108     assign $0\initial[0:0] 1'0
48109     sync always
48110       update \initial $0\initial[0:0]
48111     sync init
48112   end
48113   attribute \src "libresoc.v:32689.3-32740.6"
48114   process $proc$libresoc.v:32689$707
48115     assign { } { }
48116     assign { } { }
48117     assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0]
48118     attribute \src "libresoc.v:32690.5-32690.29"
48119     switch \initial
48120       attribute \src "libresoc.v:32690.9-32690.17"
48121       case 1'1
48122       case
48123     end
48124     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48125     switch \opcode_switch
48126       attribute \src "libresoc.v:0.0-0.0"
48127       case 5'00001
48128         assign { } { }
48129         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48130       attribute \src "libresoc.v:0.0-0.0"
48131       case 5'00000
48132         assign { } { }
48133         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48134       attribute \src "libresoc.v:0.0-0.0"
48135       case 5'10001
48136         assign { } { }
48137         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48138       attribute \src "libresoc.v:0.0-0.0"
48139       case 5'10000
48140         assign { } { }
48141         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48142       attribute \src "libresoc.v:0.0-0.0"
48143       case 5'11101
48144         assign { } { }
48145         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010
48146       attribute \src "libresoc.v:0.0-0.0"
48147       case 5'11100
48148         assign { } { }
48149         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010
48150       attribute \src "libresoc.v:0.0-0.0"
48151       case 5'11110
48152         assign { } { }
48153         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010
48154       attribute \src "libresoc.v:0.0-0.0"
48155       case 5'11011
48156         assign { } { }
48157         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000
48158       attribute \src "libresoc.v:0.0-0.0"
48159       case 5'00011
48160         assign { } { }
48161         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48162       attribute \src "libresoc.v:0.0-0.0"
48163       case 5'01111
48164         assign { } { }
48165         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48166       attribute \src "libresoc.v:0.0-0.0"
48167       case 5'01011
48168         assign { } { }
48169         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48170       attribute \src "libresoc.v:0.0-0.0"
48171       case 5'00101
48172         assign { } { }
48173         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48174       attribute \src "libresoc.v:0.0-0.0"
48175       case 5'00100
48176         assign { } { }
48177         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000
48178       attribute \src "libresoc.v:0.0-0.0"
48179       case 5'11000
48180         assign { } { }
48181         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000
48182       attribute \src "libresoc.v:0.0-0.0"
48183       case 5'11001
48184         assign { } { }
48185         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000
48186       case
48187         assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000
48188     end
48189     sync always
48190       update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0]
48191   end
48192   attribute \src "libresoc.v:32741.3-32792.6"
48193   process $proc$libresoc.v:32741$708
48194     assign { } { }
48195     assign { } { }
48196     assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0]
48197     attribute \src "libresoc.v:32742.5-32742.29"
48198     switch \initial
48199       attribute \src "libresoc.v:32742.9-32742.17"
48200       case 1'1
48201       case
48202     end
48203     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48204     switch \opcode_switch
48205       attribute \src "libresoc.v:0.0-0.0"
48206       case 5'00001
48207         assign { } { }
48208         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48209       attribute \src "libresoc.v:0.0-0.0"
48210       case 5'00000
48211         assign { } { }
48212         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48213       attribute \src "libresoc.v:0.0-0.0"
48214       case 5'10001
48215         assign { } { }
48216         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48217       attribute \src "libresoc.v:0.0-0.0"
48218       case 5'10000
48219         assign { } { }
48220         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48221       attribute \src "libresoc.v:0.0-0.0"
48222       case 5'11101
48223         assign { } { }
48224         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001
48225       attribute \src "libresoc.v:0.0-0.0"
48226       case 5'11100
48227         assign { } { }
48228         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010
48229       attribute \src "libresoc.v:0.0-0.0"
48230       case 5'11110
48231         assign { } { }
48232         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100
48233       attribute \src "libresoc.v:0.0-0.0"
48234       case 5'11011
48235         assign { } { }
48236         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48237       attribute \src "libresoc.v:0.0-0.0"
48238       case 5'00011
48239         assign { } { }
48240         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001
48241       attribute \src "libresoc.v:0.0-0.0"
48242       case 5'01111
48243         assign { } { }
48244         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000
48245       attribute \src "libresoc.v:0.0-0.0"
48246       case 5'01011
48247         assign { } { }
48248         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100
48249       attribute \src "libresoc.v:0.0-0.0"
48250       case 5'00101
48251         assign { } { }
48252         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000
48253       attribute \src "libresoc.v:0.0-0.0"
48254       case 5'00100
48255         assign { } { }
48256         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100
48257       attribute \src "libresoc.v:0.0-0.0"
48258       case 5'11000
48259         assign { } { }
48260         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48261       attribute \src "libresoc.v:0.0-0.0"
48262       case 5'11001
48263         assign { } { }
48264         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48265       case
48266         assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000
48267     end
48268     sync always
48269       update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0]
48270   end
48271   attribute \src "libresoc.v:32793.3-32844.6"
48272   process $proc$libresoc.v:32793$709
48273     assign { } { }
48274     assign { } { }
48275     assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0]
48276     attribute \src "libresoc.v:32794.5-32794.29"
48277     switch \initial
48278       attribute \src "libresoc.v:32794.9-32794.17"
48279       case 1'1
48280       case
48281     end
48282     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48283     switch \opcode_switch
48284       attribute \src "libresoc.v:0.0-0.0"
48285       case 5'00001
48286         assign { } { }
48287         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48288       attribute \src "libresoc.v:0.0-0.0"
48289       case 5'00000
48290         assign { } { }
48291         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48292       attribute \src "libresoc.v:0.0-0.0"
48293       case 5'10001
48294         assign { } { }
48295         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48296       attribute \src "libresoc.v:0.0-0.0"
48297       case 5'10000
48298         assign { } { }
48299         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48300       attribute \src "libresoc.v:0.0-0.0"
48301       case 5'11101
48302         assign { } { }
48303         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48304       attribute \src "libresoc.v:0.0-0.0"
48305       case 5'11100
48306         assign { } { }
48307         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48308       attribute \src "libresoc.v:0.0-0.0"
48309       case 5'11110
48310         assign { } { }
48311         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48312       attribute \src "libresoc.v:0.0-0.0"
48313       case 5'11011
48314         assign { } { }
48315         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48316       attribute \src "libresoc.v:0.0-0.0"
48317       case 5'00011
48318         assign { } { }
48319         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48320       attribute \src "libresoc.v:0.0-0.0"
48321       case 5'01111
48322         assign { } { }
48323         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48324       attribute \src "libresoc.v:0.0-0.0"
48325       case 5'01011
48326         assign { } { }
48327         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48328       attribute \src "libresoc.v:0.0-0.0"
48329       case 5'00101
48330         assign { } { }
48331         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48332       attribute \src "libresoc.v:0.0-0.0"
48333       case 5'00100
48334         assign { } { }
48335         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48336       attribute \src "libresoc.v:0.0-0.0"
48337       case 5'11000
48338         assign { } { }
48339         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48340       attribute \src "libresoc.v:0.0-0.0"
48341       case 5'11001
48342         assign { } { }
48343         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48344       case
48345         assign $1\dec31_dec_sub26_upd[1:0] 2'00
48346     end
48347     sync always
48348       update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0]
48349   end
48350   attribute \src "libresoc.v:32845.3-32896.6"
48351   process $proc$libresoc.v:32845$710
48352     assign { } { }
48353     assign { } { }
48354     assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0]
48355     attribute \src "libresoc.v:32846.5-32846.29"
48356     switch \initial
48357       attribute \src "libresoc.v:32846.9-32846.17"
48358       case 1'1
48359       case
48360     end
48361     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48362     switch \opcode_switch
48363       attribute \src "libresoc.v:0.0-0.0"
48364       case 5'00001
48365         assign { } { }
48366         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48367       attribute \src "libresoc.v:0.0-0.0"
48368       case 5'00000
48369         assign { } { }
48370         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48371       attribute \src "libresoc.v:0.0-0.0"
48372       case 5'10001
48373         assign { } { }
48374         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48375       attribute \src "libresoc.v:0.0-0.0"
48376       case 5'10000
48377         assign { } { }
48378         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48379       attribute \src "libresoc.v:0.0-0.0"
48380       case 5'11101
48381         assign { } { }
48382         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48383       attribute \src "libresoc.v:0.0-0.0"
48384       case 5'11100
48385         assign { } { }
48386         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48387       attribute \src "libresoc.v:0.0-0.0"
48388       case 5'11110
48389         assign { } { }
48390         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48391       attribute \src "libresoc.v:0.0-0.0"
48392       case 5'11011
48393         assign { } { }
48394         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48395       attribute \src "libresoc.v:0.0-0.0"
48396       case 5'00011
48397         assign { } { }
48398         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00
48399       attribute \src "libresoc.v:0.0-0.0"
48400       case 5'01111
48401         assign { } { }
48402         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00
48403       attribute \src "libresoc.v:0.0-0.0"
48404       case 5'01011
48405         assign { } { }
48406         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00
48407       attribute \src "libresoc.v:0.0-0.0"
48408       case 5'00101
48409         assign { } { }
48410         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00
48411       attribute \src "libresoc.v:0.0-0.0"
48412       case 5'00100
48413         assign { } { }
48414         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00
48415       attribute \src "libresoc.v:0.0-0.0"
48416       case 5'11000
48417         assign { } { }
48418         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48419       attribute \src "libresoc.v:0.0-0.0"
48420       case 5'11001
48421         assign { } { }
48422         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10
48423       case
48424         assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00
48425     end
48426     sync always
48427       update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0]
48428   end
48429   attribute \src "libresoc.v:32897.3-32948.6"
48430   process $proc$libresoc.v:32897$711
48431     assign { } { }
48432     assign { } { }
48433     assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0]
48434     attribute \src "libresoc.v:32898.5-32898.29"
48435     switch \initial
48436       attribute \src "libresoc.v:32898.9-32898.17"
48437       case 1'1
48438       case
48439     end
48440     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48441     switch \opcode_switch
48442       attribute \src "libresoc.v:0.0-0.0"
48443       case 5'00001
48444         assign { } { }
48445         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48446       attribute \src "libresoc.v:0.0-0.0"
48447       case 5'00000
48448         assign { } { }
48449         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48450       attribute \src "libresoc.v:0.0-0.0"
48451       case 5'10001
48452         assign { } { }
48453         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48454       attribute \src "libresoc.v:0.0-0.0"
48455       case 5'10000
48456         assign { } { }
48457         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48458       attribute \src "libresoc.v:0.0-0.0"
48459       case 5'11101
48460         assign { } { }
48461         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48462       attribute \src "libresoc.v:0.0-0.0"
48463       case 5'11100
48464         assign { } { }
48465         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48466       attribute \src "libresoc.v:0.0-0.0"
48467       case 5'11110
48468         assign { } { }
48469         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48470       attribute \src "libresoc.v:0.0-0.0"
48471       case 5'11011
48472         assign { } { }
48473         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48474       attribute \src "libresoc.v:0.0-0.0"
48475       case 5'00011
48476         assign { } { }
48477         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48478       attribute \src "libresoc.v:0.0-0.0"
48479       case 5'01111
48480         assign { } { }
48481         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48482       attribute \src "libresoc.v:0.0-0.0"
48483       case 5'01011
48484         assign { } { }
48485         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48486       attribute \src "libresoc.v:0.0-0.0"
48487       case 5'00101
48488         assign { } { }
48489         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48490       attribute \src "libresoc.v:0.0-0.0"
48491       case 5'00100
48492         assign { } { }
48493         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48494       attribute \src "libresoc.v:0.0-0.0"
48495       case 5'11000
48496         assign { } { }
48497         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48498       attribute \src "libresoc.v:0.0-0.0"
48499       case 5'11001
48500         assign { } { }
48501         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48502       case
48503         assign $1\dec31_dec_sub26_cry_in[1:0] 2'00
48504     end
48505     sync always
48506       update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0]
48507   end
48508   attribute \src "libresoc.v:32949.3-33000.6"
48509   process $proc$libresoc.v:32949$712
48510     assign { } { }
48511     assign { } { }
48512     assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0]
48513     attribute \src "libresoc.v:32950.5-32950.29"
48514     switch \initial
48515       attribute \src "libresoc.v:32950.9-32950.17"
48516       case 1'1
48517       case
48518     end
48519     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48520     switch \opcode_switch
48521       attribute \src "libresoc.v:0.0-0.0"
48522       case 5'00001
48523         assign { } { }
48524         assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001
48525       attribute \src "libresoc.v:0.0-0.0"
48526       case 5'00000
48527         assign { } { }
48528         assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010
48529       attribute \src "libresoc.v:0.0-0.0"
48530       case 5'10001
48531         assign { } { }
48532         assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011
48533       attribute \src "libresoc.v:0.0-0.0"
48534       case 5'10000
48535         assign { } { }
48536         assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100
48537       attribute \src "libresoc.v:0.0-0.0"
48538       case 5'11101
48539         assign { } { }
48540         assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100
48541       attribute \src "libresoc.v:0.0-0.0"
48542       case 5'11100
48543         assign { } { }
48544         assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101
48545       attribute \src "libresoc.v:0.0-0.0"
48546       case 5'11110
48547         assign { } { }
48548         assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110
48549       attribute \src "libresoc.v:0.0-0.0"
48550       case 5'11011
48551         assign { } { }
48552         assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111
48553       attribute \src "libresoc.v:0.0-0.0"
48554       case 5'00011
48555         assign { } { }
48556         assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100
48557       attribute \src "libresoc.v:0.0-0.0"
48558       case 5'01111
48559         assign { } { }
48560         assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101
48561       attribute \src "libresoc.v:0.0-0.0"
48562       case 5'01011
48563         assign { } { }
48564         assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110
48565       attribute \src "libresoc.v:0.0-0.0"
48566       case 5'00101
48567         assign { } { }
48568         assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111
48569       attribute \src "libresoc.v:0.0-0.0"
48570       case 5'00100
48571         assign { } { }
48572         assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000
48573       attribute \src "libresoc.v:0.0-0.0"
48574       case 5'11000
48575         assign { } { }
48576         assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000
48577       attribute \src "libresoc.v:0.0-0.0"
48578       case 5'11001
48579         assign { } { }
48580         assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001
48581       case
48582         assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000
48583     end
48584     sync always
48585       update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0]
48586   end
48587   attribute \src "libresoc.v:33001.3-33052.6"
48588   process $proc$libresoc.v:33001$713
48589     assign { } { }
48590     assign { } { }
48591     assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0]
48592     attribute \src "libresoc.v:33002.5-33002.29"
48593     switch \initial
48594       attribute \src "libresoc.v:33002.9-33002.17"
48595       case 1'1
48596       case
48597     end
48598     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48599     switch \opcode_switch
48600       attribute \src "libresoc.v:0.0-0.0"
48601       case 5'00001
48602         assign { } { }
48603         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48604       attribute \src "libresoc.v:0.0-0.0"
48605       case 5'00000
48606         assign { } { }
48607         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48608       attribute \src "libresoc.v:0.0-0.0"
48609       case 5'10001
48610         assign { } { }
48611         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48612       attribute \src "libresoc.v:0.0-0.0"
48613       case 5'10000
48614         assign { } { }
48615         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48616       attribute \src "libresoc.v:0.0-0.0"
48617       case 5'11101
48618         assign { } { }
48619         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48620       attribute \src "libresoc.v:0.0-0.0"
48621       case 5'11100
48622         assign { } { }
48623         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48624       attribute \src "libresoc.v:0.0-0.0"
48625       case 5'11110
48626         assign { } { }
48627         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48628       attribute \src "libresoc.v:0.0-0.0"
48629       case 5'11011
48630         assign { } { }
48631         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48632       attribute \src "libresoc.v:0.0-0.0"
48633       case 5'00011
48634         assign { } { }
48635         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48636       attribute \src "libresoc.v:0.0-0.0"
48637       case 5'01111
48638         assign { } { }
48639         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48640       attribute \src "libresoc.v:0.0-0.0"
48641       case 5'01011
48642         assign { } { }
48643         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48644       attribute \src "libresoc.v:0.0-0.0"
48645       case 5'00101
48646         assign { } { }
48647         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48648       attribute \src "libresoc.v:0.0-0.0"
48649       case 5'00100
48650         assign { } { }
48651         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48652       attribute \src "libresoc.v:0.0-0.0"
48653       case 5'11000
48654         assign { } { }
48655         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48656       attribute \src "libresoc.v:0.0-0.0"
48657       case 5'11001
48658         assign { } { }
48659         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48660       case
48661         assign $1\dec31_dec_sub26_inv_a[0:0] 1'0
48662     end
48663     sync always
48664       update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0]
48665   end
48666   attribute \src "libresoc.v:33053.3-33104.6"
48667   process $proc$libresoc.v:33053$714
48668     assign { } { }
48669     assign { } { }
48670     assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0]
48671     attribute \src "libresoc.v:33054.5-33054.29"
48672     switch \initial
48673       attribute \src "libresoc.v:33054.9-33054.17"
48674       case 1'1
48675       case
48676     end
48677     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48678     switch \opcode_switch
48679       attribute \src "libresoc.v:0.0-0.0"
48680       case 5'00001
48681         assign { } { }
48682         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48683       attribute \src "libresoc.v:0.0-0.0"
48684       case 5'00000
48685         assign { } { }
48686         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48687       attribute \src "libresoc.v:0.0-0.0"
48688       case 5'10001
48689         assign { } { }
48690         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48691       attribute \src "libresoc.v:0.0-0.0"
48692       case 5'10000
48693         assign { } { }
48694         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48695       attribute \src "libresoc.v:0.0-0.0"
48696       case 5'11101
48697         assign { } { }
48698         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48699       attribute \src "libresoc.v:0.0-0.0"
48700       case 5'11100
48701         assign { } { }
48702         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48703       attribute \src "libresoc.v:0.0-0.0"
48704       case 5'11110
48705         assign { } { }
48706         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48707       attribute \src "libresoc.v:0.0-0.0"
48708       case 5'11011
48709         assign { } { }
48710         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48711       attribute \src "libresoc.v:0.0-0.0"
48712       case 5'00011
48713         assign { } { }
48714         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48715       attribute \src "libresoc.v:0.0-0.0"
48716       case 5'01111
48717         assign { } { }
48718         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48719       attribute \src "libresoc.v:0.0-0.0"
48720       case 5'01011
48721         assign { } { }
48722         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48723       attribute \src "libresoc.v:0.0-0.0"
48724       case 5'00101
48725         assign { } { }
48726         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48727       attribute \src "libresoc.v:0.0-0.0"
48728       case 5'00100
48729         assign { } { }
48730         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48731       attribute \src "libresoc.v:0.0-0.0"
48732       case 5'11000
48733         assign { } { }
48734         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48735       attribute \src "libresoc.v:0.0-0.0"
48736       case 5'11001
48737         assign { } { }
48738         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48739       case
48740         assign $1\dec31_dec_sub26_inv_out[0:0] 1'0
48741     end
48742     sync always
48743       update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0]
48744   end
48745   attribute \src "libresoc.v:33105.3-33156.6"
48746   process $proc$libresoc.v:33105$715
48747     assign { } { }
48748     assign { } { }
48749     assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0]
48750     attribute \src "libresoc.v:33106.5-33106.29"
48751     switch \initial
48752       attribute \src "libresoc.v:33106.9-33106.17"
48753       case 1'1
48754       case
48755     end
48756     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48757     switch \opcode_switch
48758       attribute \src "libresoc.v:0.0-0.0"
48759       case 5'00001
48760         assign { } { }
48761         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48762       attribute \src "libresoc.v:0.0-0.0"
48763       case 5'00000
48764         assign { } { }
48765         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48766       attribute \src "libresoc.v:0.0-0.0"
48767       case 5'10001
48768         assign { } { }
48769         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48770       attribute \src "libresoc.v:0.0-0.0"
48771       case 5'10000
48772         assign { } { }
48773         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48774       attribute \src "libresoc.v:0.0-0.0"
48775       case 5'11101
48776         assign { } { }
48777         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48778       attribute \src "libresoc.v:0.0-0.0"
48779       case 5'11100
48780         assign { } { }
48781         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48782       attribute \src "libresoc.v:0.0-0.0"
48783       case 5'11110
48784         assign { } { }
48785         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48786       attribute \src "libresoc.v:0.0-0.0"
48787       case 5'11011
48788         assign { } { }
48789         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48790       attribute \src "libresoc.v:0.0-0.0"
48791       case 5'00011
48792         assign { } { }
48793         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48794       attribute \src "libresoc.v:0.0-0.0"
48795       case 5'01111
48796         assign { } { }
48797         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48798       attribute \src "libresoc.v:0.0-0.0"
48799       case 5'01011
48800         assign { } { }
48801         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48802       attribute \src "libresoc.v:0.0-0.0"
48803       case 5'00101
48804         assign { } { }
48805         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48806       attribute \src "libresoc.v:0.0-0.0"
48807       case 5'00100
48808         assign { } { }
48809         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48810       attribute \src "libresoc.v:0.0-0.0"
48811       case 5'11000
48812         assign { } { }
48813         assign $1\dec31_dec_sub26_cry_out[0:0] 1'1
48814       attribute \src "libresoc.v:0.0-0.0"
48815       case 5'11001
48816         assign { } { }
48817         assign $1\dec31_dec_sub26_cry_out[0:0] 1'1
48818       case
48819         assign $1\dec31_dec_sub26_cry_out[0:0] 1'0
48820     end
48821     sync always
48822       update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0]
48823   end
48824   attribute \src "libresoc.v:33157.3-33208.6"
48825   process $proc$libresoc.v:33157$716
48826     assign { } { }
48827     assign { } { }
48828     assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0]
48829     attribute \src "libresoc.v:33158.5-33158.29"
48830     switch \initial
48831       attribute \src "libresoc.v:33158.9-33158.17"
48832       case 1'1
48833       case
48834     end
48835     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48836     switch \opcode_switch
48837       attribute \src "libresoc.v:0.0-0.0"
48838       case 5'00001
48839         assign { } { }
48840         assign $1\dec31_dec_sub26_br[0:0] 1'0
48841       attribute \src "libresoc.v:0.0-0.0"
48842       case 5'00000
48843         assign { } { }
48844         assign $1\dec31_dec_sub26_br[0:0] 1'0
48845       attribute \src "libresoc.v:0.0-0.0"
48846       case 5'10001
48847         assign { } { }
48848         assign $1\dec31_dec_sub26_br[0:0] 1'0
48849       attribute \src "libresoc.v:0.0-0.0"
48850       case 5'10000
48851         assign { } { }
48852         assign $1\dec31_dec_sub26_br[0:0] 1'0
48853       attribute \src "libresoc.v:0.0-0.0"
48854       case 5'11101
48855         assign { } { }
48856         assign $1\dec31_dec_sub26_br[0:0] 1'0
48857       attribute \src "libresoc.v:0.0-0.0"
48858       case 5'11100
48859         assign { } { }
48860         assign $1\dec31_dec_sub26_br[0:0] 1'0
48861       attribute \src "libresoc.v:0.0-0.0"
48862       case 5'11110
48863         assign { } { }
48864         assign $1\dec31_dec_sub26_br[0:0] 1'0
48865       attribute \src "libresoc.v:0.0-0.0"
48866       case 5'11011
48867         assign { } { }
48868         assign $1\dec31_dec_sub26_br[0:0] 1'0
48869       attribute \src "libresoc.v:0.0-0.0"
48870       case 5'00011
48871         assign { } { }
48872         assign $1\dec31_dec_sub26_br[0:0] 1'0
48873       attribute \src "libresoc.v:0.0-0.0"
48874       case 5'01111
48875         assign { } { }
48876         assign $1\dec31_dec_sub26_br[0:0] 1'0
48877       attribute \src "libresoc.v:0.0-0.0"
48878       case 5'01011
48879         assign { } { }
48880         assign $1\dec31_dec_sub26_br[0:0] 1'0
48881       attribute \src "libresoc.v:0.0-0.0"
48882       case 5'00101
48883         assign { } { }
48884         assign $1\dec31_dec_sub26_br[0:0] 1'0
48885       attribute \src "libresoc.v:0.0-0.0"
48886       case 5'00100
48887         assign { } { }
48888         assign $1\dec31_dec_sub26_br[0:0] 1'0
48889       attribute \src "libresoc.v:0.0-0.0"
48890       case 5'11000
48891         assign { } { }
48892         assign $1\dec31_dec_sub26_br[0:0] 1'0
48893       attribute \src "libresoc.v:0.0-0.0"
48894       case 5'11001
48895         assign { } { }
48896         assign $1\dec31_dec_sub26_br[0:0] 1'0
48897       case
48898         assign $1\dec31_dec_sub26_br[0:0] 1'0
48899     end
48900     sync always
48901       update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0]
48902   end
48903   attribute \src "libresoc.v:33209.3-33260.6"
48904   process $proc$libresoc.v:33209$717
48905     assign { } { }
48906     assign { } { }
48907     assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0]
48908     attribute \src "libresoc.v:33210.5-33210.29"
48909     switch \initial
48910       attribute \src "libresoc.v:33210.9-33210.17"
48911       case 1'1
48912       case
48913     end
48914     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48915     switch \opcode_switch
48916       attribute \src "libresoc.v:0.0-0.0"
48917       case 5'00001
48918         assign { } { }
48919         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48920       attribute \src "libresoc.v:0.0-0.0"
48921       case 5'00000
48922         assign { } { }
48923         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48924       attribute \src "libresoc.v:0.0-0.0"
48925       case 5'10001
48926         assign { } { }
48927         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48928       attribute \src "libresoc.v:0.0-0.0"
48929       case 5'10000
48930         assign { } { }
48931         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48932       attribute \src "libresoc.v:0.0-0.0"
48933       case 5'11101
48934         assign { } { }
48935         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48936       attribute \src "libresoc.v:0.0-0.0"
48937       case 5'11100
48938         assign { } { }
48939         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48940       attribute \src "libresoc.v:0.0-0.0"
48941       case 5'11110
48942         assign { } { }
48943         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48944       attribute \src "libresoc.v:0.0-0.0"
48945       case 5'11011
48946         assign { } { }
48947         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48948       attribute \src "libresoc.v:0.0-0.0"
48949       case 5'00011
48950         assign { } { }
48951         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48952       attribute \src "libresoc.v:0.0-0.0"
48953       case 5'01111
48954         assign { } { }
48955         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48956       attribute \src "libresoc.v:0.0-0.0"
48957       case 5'01011
48958         assign { } { }
48959         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48960       attribute \src "libresoc.v:0.0-0.0"
48961       case 5'00101
48962         assign { } { }
48963         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48964       attribute \src "libresoc.v:0.0-0.0"
48965       case 5'00100
48966         assign { } { }
48967         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48968       attribute \src "libresoc.v:0.0-0.0"
48969       case 5'11000
48970         assign { } { }
48971         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48972       attribute \src "libresoc.v:0.0-0.0"
48973       case 5'11001
48974         assign { } { }
48975         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48976       case
48977         assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0
48978     end
48979     sync always
48980       update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0]
48981   end
48982   attribute \src "libresoc.v:33261.3-33312.6"
48983   process $proc$libresoc.v:33261$718
48984     assign { } { }
48985     assign { } { }
48986     assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0]
48987     attribute \src "libresoc.v:33262.5-33262.29"
48988     switch \initial
48989       attribute \src "libresoc.v:33262.9-33262.17"
48990       case 1'1
48991       case
48992     end
48993     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
48994     switch \opcode_switch
48995       attribute \src "libresoc.v:0.0-0.0"
48996       case 5'00001
48997         assign { } { }
48998         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110
48999       attribute \src "libresoc.v:0.0-0.0"
49000       case 5'00000
49001         assign { } { }
49002         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110
49003       attribute \src "libresoc.v:0.0-0.0"
49004       case 5'10001
49005         assign { } { }
49006         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110
49007       attribute \src "libresoc.v:0.0-0.0"
49008       case 5'10000
49009         assign { } { }
49010         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110
49011       attribute \src "libresoc.v:0.0-0.0"
49012       case 5'11101
49013         assign { } { }
49014         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111
49015       attribute \src "libresoc.v:0.0-0.0"
49016       case 5'11100
49017         assign { } { }
49018         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111
49019       attribute \src "libresoc.v:0.0-0.0"
49020       case 5'11110
49021         assign { } { }
49022         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111
49023       attribute \src "libresoc.v:0.0-0.0"
49024       case 5'11011
49025         assign { } { }
49026         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000
49027       attribute \src "libresoc.v:0.0-0.0"
49028       case 5'00011
49029         assign { } { }
49030         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110
49031       attribute \src "libresoc.v:0.0-0.0"
49032       case 5'01111
49033         assign { } { }
49034         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110
49035       attribute \src "libresoc.v:0.0-0.0"
49036       case 5'01011
49037         assign { } { }
49038         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110
49039       attribute \src "libresoc.v:0.0-0.0"
49040       case 5'00101
49041         assign { } { }
49042         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111
49043       attribute \src "libresoc.v:0.0-0.0"
49044       case 5'00100
49045         assign { } { }
49046         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111
49047       attribute \src "libresoc.v:0.0-0.0"
49048       case 5'11000
49049         assign { } { }
49050         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101
49051       attribute \src "libresoc.v:0.0-0.0"
49052       case 5'11001
49053         assign { } { }
49054         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101
49055       case
49056         assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000
49057     end
49058     sync always
49059       update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0]
49060   end
49061   attribute \src "libresoc.v:33313.3-33364.6"
49062   process $proc$libresoc.v:33313$719
49063     assign { } { }
49064     assign { } { }
49065     assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0]
49066     attribute \src "libresoc.v:33314.5-33314.29"
49067     switch \initial
49068       attribute \src "libresoc.v:33314.9-33314.17"
49069       case 1'1
49070       case
49071     end
49072     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49073     switch \opcode_switch
49074       attribute \src "libresoc.v:0.0-0.0"
49075       case 5'00001
49076         assign { } { }
49077         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49078       attribute \src "libresoc.v:0.0-0.0"
49079       case 5'00000
49080         assign { } { }
49081         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49082       attribute \src "libresoc.v:0.0-0.0"
49083       case 5'10001
49084         assign { } { }
49085         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49086       attribute \src "libresoc.v:0.0-0.0"
49087       case 5'10000
49088         assign { } { }
49089         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49090       attribute \src "libresoc.v:0.0-0.0"
49091       case 5'11101
49092         assign { } { }
49093         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49094       attribute \src "libresoc.v:0.0-0.0"
49095       case 5'11100
49096         assign { } { }
49097         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49098       attribute \src "libresoc.v:0.0-0.0"
49099       case 5'11110
49100         assign { } { }
49101         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49102       attribute \src "libresoc.v:0.0-0.0"
49103       case 5'11011
49104         assign { } { }
49105         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49106       attribute \src "libresoc.v:0.0-0.0"
49107       case 5'00011
49108         assign { } { }
49109         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49110       attribute \src "libresoc.v:0.0-0.0"
49111       case 5'01111
49112         assign { } { }
49113         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49114       attribute \src "libresoc.v:0.0-0.0"
49115       case 5'01011
49116         assign { } { }
49117         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49118       attribute \src "libresoc.v:0.0-0.0"
49119       case 5'00101
49120         assign { } { }
49121         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49122       attribute \src "libresoc.v:0.0-0.0"
49123       case 5'00100
49124         assign { } { }
49125         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49126       attribute \src "libresoc.v:0.0-0.0"
49127       case 5'11000
49128         assign { } { }
49129         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49130       attribute \src "libresoc.v:0.0-0.0"
49131       case 5'11001
49132         assign { } { }
49133         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49134       case
49135         assign $1\dec31_dec_sub26_rsrv[0:0] 1'0
49136     end
49137     sync always
49138       update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0]
49139   end
49140   attribute \src "libresoc.v:33365.3-33416.6"
49141   process $proc$libresoc.v:33365$720
49142     assign { } { }
49143     assign { } { }
49144     assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0]
49145     attribute \src "libresoc.v:33366.5-33366.29"
49146     switch \initial
49147       attribute \src "libresoc.v:33366.9-33366.17"
49148       case 1'1
49149       case
49150     end
49151     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49152     switch \opcode_switch
49153       attribute \src "libresoc.v:0.0-0.0"
49154       case 5'00001
49155         assign { } { }
49156         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49157       attribute \src "libresoc.v:0.0-0.0"
49158       case 5'00000
49159         assign { } { }
49160         assign $1\dec31_dec_sub26_is_32b[0:0] 1'1
49161       attribute \src "libresoc.v:0.0-0.0"
49162       case 5'10001
49163         assign { } { }
49164         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49165       attribute \src "libresoc.v:0.0-0.0"
49166       case 5'10000
49167         assign { } { }
49168         assign $1\dec31_dec_sub26_is_32b[0:0] 1'1
49169       attribute \src "libresoc.v:0.0-0.0"
49170       case 5'11101
49171         assign { } { }
49172         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49173       attribute \src "libresoc.v:0.0-0.0"
49174       case 5'11100
49175         assign { } { }
49176         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49177       attribute \src "libresoc.v:0.0-0.0"
49178       case 5'11110
49179         assign { } { }
49180         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49181       attribute \src "libresoc.v:0.0-0.0"
49182       case 5'11011
49183         assign { } { }
49184         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49185       attribute \src "libresoc.v:0.0-0.0"
49186       case 5'00011
49187         assign { } { }
49188         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49189       attribute \src "libresoc.v:0.0-0.0"
49190       case 5'01111
49191         assign { } { }
49192         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49193       attribute \src "libresoc.v:0.0-0.0"
49194       case 5'01011
49195         assign { } { }
49196         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49197       attribute \src "libresoc.v:0.0-0.0"
49198       case 5'00101
49199         assign { } { }
49200         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49201       attribute \src "libresoc.v:0.0-0.0"
49202       case 5'00100
49203         assign { } { }
49204         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49205       attribute \src "libresoc.v:0.0-0.0"
49206       case 5'11000
49207         assign { } { }
49208         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49209       attribute \src "libresoc.v:0.0-0.0"
49210       case 5'11001
49211         assign { } { }
49212         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49213       case
49214         assign $1\dec31_dec_sub26_is_32b[0:0] 1'0
49215     end
49216     sync always
49217       update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0]
49218   end
49219   attribute \src "libresoc.v:33417.3-33468.6"
49220   process $proc$libresoc.v:33417$721
49221     assign { } { }
49222     assign { } { }
49223     assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0]
49224     attribute \src "libresoc.v:33418.5-33418.29"
49225     switch \initial
49226       attribute \src "libresoc.v:33418.9-33418.17"
49227       case 1'1
49228       case
49229     end
49230     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49231     switch \opcode_switch
49232       attribute \src "libresoc.v:0.0-0.0"
49233       case 5'00001
49234         assign { } { }
49235         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49236       attribute \src "libresoc.v:0.0-0.0"
49237       case 5'00000
49238         assign { } { }
49239         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49240       attribute \src "libresoc.v:0.0-0.0"
49241       case 5'10001
49242         assign { } { }
49243         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49244       attribute \src "libresoc.v:0.0-0.0"
49245       case 5'10000
49246         assign { } { }
49247         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49248       attribute \src "libresoc.v:0.0-0.0"
49249       case 5'11101
49250         assign { } { }
49251         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49252       attribute \src "libresoc.v:0.0-0.0"
49253       case 5'11100
49254         assign { } { }
49255         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49256       attribute \src "libresoc.v:0.0-0.0"
49257       case 5'11110
49258         assign { } { }
49259         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49260       attribute \src "libresoc.v:0.0-0.0"
49261       case 5'11011
49262         assign { } { }
49263         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49264       attribute \src "libresoc.v:0.0-0.0"
49265       case 5'00011
49266         assign { } { }
49267         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49268       attribute \src "libresoc.v:0.0-0.0"
49269       case 5'01111
49270         assign { } { }
49271         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49272       attribute \src "libresoc.v:0.0-0.0"
49273       case 5'01011
49274         assign { } { }
49275         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49276       attribute \src "libresoc.v:0.0-0.0"
49277       case 5'00101
49278         assign { } { }
49279         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49280       attribute \src "libresoc.v:0.0-0.0"
49281       case 5'00100
49282         assign { } { }
49283         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49284       attribute \src "libresoc.v:0.0-0.0"
49285       case 5'11000
49286         assign { } { }
49287         assign $1\dec31_dec_sub26_sgn[0:0] 1'1
49288       attribute \src "libresoc.v:0.0-0.0"
49289       case 5'11001
49290         assign { } { }
49291         assign $1\dec31_dec_sub26_sgn[0:0] 1'1
49292       case
49293         assign $1\dec31_dec_sub26_sgn[0:0] 1'0
49294     end
49295     sync always
49296       update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0]
49297   end
49298   attribute \src "libresoc.v:33469.3-33520.6"
49299   process $proc$libresoc.v:33469$722
49300     assign { } { }
49301     assign { } { }
49302     assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0]
49303     attribute \src "libresoc.v:33470.5-33470.29"
49304     switch \initial
49305       attribute \src "libresoc.v:33470.9-33470.17"
49306       case 1'1
49307       case
49308     end
49309     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49310     switch \opcode_switch
49311       attribute \src "libresoc.v:0.0-0.0"
49312       case 5'00001
49313         assign { } { }
49314         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49315       attribute \src "libresoc.v:0.0-0.0"
49316       case 5'00000
49317         assign { } { }
49318         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49319       attribute \src "libresoc.v:0.0-0.0"
49320       case 5'10001
49321         assign { } { }
49322         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49323       attribute \src "libresoc.v:0.0-0.0"
49324       case 5'10000
49325         assign { } { }
49326         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49327       attribute \src "libresoc.v:0.0-0.0"
49328       case 5'11101
49329         assign { } { }
49330         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49331       attribute \src "libresoc.v:0.0-0.0"
49332       case 5'11100
49333         assign { } { }
49334         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49335       attribute \src "libresoc.v:0.0-0.0"
49336       case 5'11110
49337         assign { } { }
49338         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49339       attribute \src "libresoc.v:0.0-0.0"
49340       case 5'11011
49341         assign { } { }
49342         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49343       attribute \src "libresoc.v:0.0-0.0"
49344       case 5'00011
49345         assign { } { }
49346         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49347       attribute \src "libresoc.v:0.0-0.0"
49348       case 5'01111
49349         assign { } { }
49350         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49351       attribute \src "libresoc.v:0.0-0.0"
49352       case 5'01011
49353         assign { } { }
49354         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49355       attribute \src "libresoc.v:0.0-0.0"
49356       case 5'00101
49357         assign { } { }
49358         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49359       attribute \src "libresoc.v:0.0-0.0"
49360       case 5'00100
49361         assign { } { }
49362         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49363       attribute \src "libresoc.v:0.0-0.0"
49364       case 5'11000
49365         assign { } { }
49366         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49367       attribute \src "libresoc.v:0.0-0.0"
49368       case 5'11001
49369         assign { } { }
49370         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49371       case
49372         assign $1\dec31_dec_sub26_lk[0:0] 1'0
49373     end
49374     sync always
49375       update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0]
49376   end
49377   attribute \src "libresoc.v:33521.3-33572.6"
49378   process $proc$libresoc.v:33521$723
49379     assign { } { }
49380     assign { } { }
49381     assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0]
49382     attribute \src "libresoc.v:33522.5-33522.29"
49383     switch \initial
49384       attribute \src "libresoc.v:33522.9-33522.17"
49385       case 1'1
49386       case
49387     end
49388     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49389     switch \opcode_switch
49390       attribute \src "libresoc.v:0.0-0.0"
49391       case 5'00001
49392         assign { } { }
49393         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49394       attribute \src "libresoc.v:0.0-0.0"
49395       case 5'00000
49396         assign { } { }
49397         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49398       attribute \src "libresoc.v:0.0-0.0"
49399       case 5'10001
49400         assign { } { }
49401         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49402       attribute \src "libresoc.v:0.0-0.0"
49403       case 5'10000
49404         assign { } { }
49405         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49406       attribute \src "libresoc.v:0.0-0.0"
49407       case 5'11101
49408         assign { } { }
49409         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49410       attribute \src "libresoc.v:0.0-0.0"
49411       case 5'11100
49412         assign { } { }
49413         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49414       attribute \src "libresoc.v:0.0-0.0"
49415       case 5'11110
49416         assign { } { }
49417         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49418       attribute \src "libresoc.v:0.0-0.0"
49419       case 5'11011
49420         assign { } { }
49421         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49422       attribute \src "libresoc.v:0.0-0.0"
49423       case 5'00011
49424         assign { } { }
49425         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49426       attribute \src "libresoc.v:0.0-0.0"
49427       case 5'01111
49428         assign { } { }
49429         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49430       attribute \src "libresoc.v:0.0-0.0"
49431       case 5'01011
49432         assign { } { }
49433         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49434       attribute \src "libresoc.v:0.0-0.0"
49435       case 5'00101
49436         assign { } { }
49437         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49438       attribute \src "libresoc.v:0.0-0.0"
49439       case 5'00100
49440         assign { } { }
49441         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49442       attribute \src "libresoc.v:0.0-0.0"
49443       case 5'11000
49444         assign { } { }
49445         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49446       attribute \src "libresoc.v:0.0-0.0"
49447       case 5'11001
49448         assign { } { }
49449         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49450       case
49451         assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0
49452     end
49453     sync always
49454       update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0]
49455   end
49456   attribute \src "libresoc.v:33573.3-33624.6"
49457   process $proc$libresoc.v:33573$724
49458     assign { } { }
49459     assign { } { }
49460     assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0]
49461     attribute \src "libresoc.v:33574.5-33574.29"
49462     switch \initial
49463       attribute \src "libresoc.v:33574.9-33574.17"
49464       case 1'1
49465       case
49466     end
49467     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49468     switch \opcode_switch
49469       attribute \src "libresoc.v:0.0-0.0"
49470       case 5'00001
49471         assign { } { }
49472         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49473       attribute \src "libresoc.v:0.0-0.0"
49474       case 5'00000
49475         assign { } { }
49476         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49477       attribute \src "libresoc.v:0.0-0.0"
49478       case 5'10001
49479         assign { } { }
49480         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49481       attribute \src "libresoc.v:0.0-0.0"
49482       case 5'10000
49483         assign { } { }
49484         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49485       attribute \src "libresoc.v:0.0-0.0"
49486       case 5'11101
49487         assign { } { }
49488         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49489       attribute \src "libresoc.v:0.0-0.0"
49490       case 5'11100
49491         assign { } { }
49492         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49493       attribute \src "libresoc.v:0.0-0.0"
49494       case 5'11110
49495         assign { } { }
49496         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49497       attribute \src "libresoc.v:0.0-0.0"
49498       case 5'11011
49499         assign { } { }
49500         assign $1\dec31_dec_sub26_form[4:0] 5'10000
49501       attribute \src "libresoc.v:0.0-0.0"
49502       case 5'00011
49503         assign { } { }
49504         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49505       attribute \src "libresoc.v:0.0-0.0"
49506       case 5'01111
49507         assign { } { }
49508         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49509       attribute \src "libresoc.v:0.0-0.0"
49510       case 5'01011
49511         assign { } { }
49512         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49513       attribute \src "libresoc.v:0.0-0.0"
49514       case 5'00101
49515         assign { } { }
49516         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49517       attribute \src "libresoc.v:0.0-0.0"
49518       case 5'00100
49519         assign { } { }
49520         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49521       attribute \src "libresoc.v:0.0-0.0"
49522       case 5'11000
49523         assign { } { }
49524         assign $1\dec31_dec_sub26_form[4:0] 5'01000
49525       attribute \src "libresoc.v:0.0-0.0"
49526       case 5'11001
49527         assign { } { }
49528         assign $1\dec31_dec_sub26_form[4:0] 5'10000
49529       case
49530         assign $1\dec31_dec_sub26_form[4:0] 5'00000
49531     end
49532     sync always
49533       update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0]
49534   end
49535   attribute \src "libresoc.v:33625.3-33676.6"
49536   process $proc$libresoc.v:33625$725
49537     assign { } { }
49538     assign { } { }
49539     assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0]
49540     attribute \src "libresoc.v:33626.5-33626.29"
49541     switch \initial
49542       attribute \src "libresoc.v:33626.9-33626.17"
49543       case 1'1
49544       case
49545     end
49546     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49547     switch \opcode_switch
49548       attribute \src "libresoc.v:0.0-0.0"
49549       case 5'00001
49550         assign { } { }
49551         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49552       attribute \src "libresoc.v:0.0-0.0"
49553       case 5'00000
49554         assign { } { }
49555         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49556       attribute \src "libresoc.v:0.0-0.0"
49557       case 5'10001
49558         assign { } { }
49559         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49560       attribute \src "libresoc.v:0.0-0.0"
49561       case 5'10000
49562         assign { } { }
49563         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49564       attribute \src "libresoc.v:0.0-0.0"
49565       case 5'11101
49566         assign { } { }
49567         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49568       attribute \src "libresoc.v:0.0-0.0"
49569       case 5'11100
49570         assign { } { }
49571         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49572       attribute \src "libresoc.v:0.0-0.0"
49573       case 5'11110
49574         assign { } { }
49575         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49576       attribute \src "libresoc.v:0.0-0.0"
49577       case 5'11011
49578         assign { } { }
49579         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000
49580       attribute \src "libresoc.v:0.0-0.0"
49581       case 5'00011
49582         assign { } { }
49583         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49584       attribute \src "libresoc.v:0.0-0.0"
49585       case 5'01111
49586         assign { } { }
49587         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49588       attribute \src "libresoc.v:0.0-0.0"
49589       case 5'01011
49590         assign { } { }
49591         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49592       attribute \src "libresoc.v:0.0-0.0"
49593       case 5'00101
49594         assign { } { }
49595         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49596       attribute \src "libresoc.v:0.0-0.0"
49597       case 5'00100
49598         assign { } { }
49599         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100
49600       attribute \src "libresoc.v:0.0-0.0"
49601       case 5'11000
49602         assign { } { }
49603         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000
49604       attribute \src "libresoc.v:0.0-0.0"
49605       case 5'11001
49606         assign { } { }
49607         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000
49608       case
49609         assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000
49610     end
49611     sync always
49612       update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0]
49613   end
49614   attribute \src "libresoc.v:33677.3-33728.6"
49615   process $proc$libresoc.v:33677$726
49616     assign { } { }
49617     assign { } { }
49618     assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0]
49619     attribute \src "libresoc.v:33678.5-33678.29"
49620     switch \initial
49621       attribute \src "libresoc.v:33678.9-33678.17"
49622       case 1'1
49623       case
49624     end
49625     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49626     switch \opcode_switch
49627       attribute \src "libresoc.v:0.0-0.0"
49628       case 5'00001
49629         assign { } { }
49630         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49631       attribute \src "libresoc.v:0.0-0.0"
49632       case 5'00000
49633         assign { } { }
49634         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49635       attribute \src "libresoc.v:0.0-0.0"
49636       case 5'10001
49637         assign { } { }
49638         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49639       attribute \src "libresoc.v:0.0-0.0"
49640       case 5'10000
49641         assign { } { }
49642         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49643       attribute \src "libresoc.v:0.0-0.0"
49644       case 5'11101
49645         assign { } { }
49646         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49647       attribute \src "libresoc.v:0.0-0.0"
49648       case 5'11100
49649         assign { } { }
49650         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49651       attribute \src "libresoc.v:0.0-0.0"
49652       case 5'11110
49653         assign { } { }
49654         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49655       attribute \src "libresoc.v:0.0-0.0"
49656       case 5'11011
49657         assign { } { }
49658         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010
49659       attribute \src "libresoc.v:0.0-0.0"
49660       case 5'00011
49661         assign { } { }
49662         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49663       attribute \src "libresoc.v:0.0-0.0"
49664       case 5'01111
49665         assign { } { }
49666         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49667       attribute \src "libresoc.v:0.0-0.0"
49668       case 5'01011
49669         assign { } { }
49670         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49671       attribute \src "libresoc.v:0.0-0.0"
49672       case 5'00101
49673         assign { } { }
49674         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49675       attribute \src "libresoc.v:0.0-0.0"
49676       case 5'00100
49677         assign { } { }
49678         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49679       attribute \src "libresoc.v:0.0-0.0"
49680       case 5'11000
49681         assign { } { }
49682         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001
49683       attribute \src "libresoc.v:0.0-0.0"
49684       case 5'11001
49685         assign { } { }
49686         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010
49687       case
49688         assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000
49689     end
49690     sync always
49691       update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0]
49692   end
49693   attribute \src "libresoc.v:33729.3-33780.6"
49694   process $proc$libresoc.v:33729$727
49695     assign { } { }
49696     assign { } { }
49697     assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0]
49698     attribute \src "libresoc.v:33730.5-33730.29"
49699     switch \initial
49700       attribute \src "libresoc.v:33730.9-33730.17"
49701       case 1'1
49702       case
49703     end
49704     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49705     switch \opcode_switch
49706       attribute \src "libresoc.v:0.0-0.0"
49707       case 5'00001
49708         assign { } { }
49709         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49710       attribute \src "libresoc.v:0.0-0.0"
49711       case 5'00000
49712         assign { } { }
49713         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49714       attribute \src "libresoc.v:0.0-0.0"
49715       case 5'10001
49716         assign { } { }
49717         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49718       attribute \src "libresoc.v:0.0-0.0"
49719       case 5'10000
49720         assign { } { }
49721         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49722       attribute \src "libresoc.v:0.0-0.0"
49723       case 5'11101
49724         assign { } { }
49725         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49726       attribute \src "libresoc.v:0.0-0.0"
49727       case 5'11100
49728         assign { } { }
49729         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49730       attribute \src "libresoc.v:0.0-0.0"
49731       case 5'11110
49732         assign { } { }
49733         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49734       attribute \src "libresoc.v:0.0-0.0"
49735       case 5'11011
49736         assign { } { }
49737         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01
49738       attribute \src "libresoc.v:0.0-0.0"
49739       case 5'00011
49740         assign { } { }
49741         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49742       attribute \src "libresoc.v:0.0-0.0"
49743       case 5'01111
49744         assign { } { }
49745         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49746       attribute \src "libresoc.v:0.0-0.0"
49747       case 5'01011
49748         assign { } { }
49749         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49750       attribute \src "libresoc.v:0.0-0.0"
49751       case 5'00101
49752         assign { } { }
49753         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49754       attribute \src "libresoc.v:0.0-0.0"
49755       case 5'00100
49756         assign { } { }
49757         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49758       attribute \src "libresoc.v:0.0-0.0"
49759       case 5'11000
49760         assign { } { }
49761         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01
49762       attribute \src "libresoc.v:0.0-0.0"
49763       case 5'11001
49764         assign { } { }
49765         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01
49766       case
49767         assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00
49768     end
49769     sync always
49770       update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0]
49771   end
49772   attribute \src "libresoc.v:33781.3-33832.6"
49773   process $proc$libresoc.v:33781$728
49774     assign { } { }
49775     assign { } { }
49776     assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0]
49777     attribute \src "libresoc.v:33782.5-33782.29"
49778     switch \initial
49779       attribute \src "libresoc.v:33782.9-33782.17"
49780       case 1'1
49781       case
49782     end
49783     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49784     switch \opcode_switch
49785       attribute \src "libresoc.v:0.0-0.0"
49786       case 5'00001
49787         assign { } { }
49788         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49789       attribute \src "libresoc.v:0.0-0.0"
49790       case 5'00000
49791         assign { } { }
49792         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49793       attribute \src "libresoc.v:0.0-0.0"
49794       case 5'10001
49795         assign { } { }
49796         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49797       attribute \src "libresoc.v:0.0-0.0"
49798       case 5'10000
49799         assign { } { }
49800         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49801       attribute \src "libresoc.v:0.0-0.0"
49802       case 5'11101
49803         assign { } { }
49804         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49805       attribute \src "libresoc.v:0.0-0.0"
49806       case 5'11100
49807         assign { } { }
49808         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49809       attribute \src "libresoc.v:0.0-0.0"
49810       case 5'11110
49811         assign { } { }
49812         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49813       attribute \src "libresoc.v:0.0-0.0"
49814       case 5'11011
49815         assign { } { }
49816         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49817       attribute \src "libresoc.v:0.0-0.0"
49818       case 5'00011
49819         assign { } { }
49820         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49821       attribute \src "libresoc.v:0.0-0.0"
49822       case 5'01111
49823         assign { } { }
49824         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49825       attribute \src "libresoc.v:0.0-0.0"
49826       case 5'01011
49827         assign { } { }
49828         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49829       attribute \src "libresoc.v:0.0-0.0"
49830       case 5'00101
49831         assign { } { }
49832         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49833       attribute \src "libresoc.v:0.0-0.0"
49834       case 5'00100
49835         assign { } { }
49836         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49837       attribute \src "libresoc.v:0.0-0.0"
49838       case 5'11000
49839         assign { } { }
49840         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49841       attribute \src "libresoc.v:0.0-0.0"
49842       case 5'11001
49843         assign { } { }
49844         assign $1\dec31_dec_sub26_out_sel[1:0] 2'10
49845       case
49846         assign $1\dec31_dec_sub26_out_sel[1:0] 2'00
49847     end
49848     sync always
49849       update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0]
49850   end
49851   attribute \src "libresoc.v:33833.3-33884.6"
49852   process $proc$libresoc.v:33833$729
49853     assign { } { }
49854     assign { } { }
49855     assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0]
49856     attribute \src "libresoc.v:33834.5-33834.29"
49857     switch \initial
49858       attribute \src "libresoc.v:33834.9-33834.17"
49859       case 1'1
49860       case
49861     end
49862     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49863     switch \opcode_switch
49864       attribute \src "libresoc.v:0.0-0.0"
49865       case 5'00001
49866         assign { } { }
49867         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49868       attribute \src "libresoc.v:0.0-0.0"
49869       case 5'00000
49870         assign { } { }
49871         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49872       attribute \src "libresoc.v:0.0-0.0"
49873       case 5'10001
49874         assign { } { }
49875         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49876       attribute \src "libresoc.v:0.0-0.0"
49877       case 5'10000
49878         assign { } { }
49879         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49880       attribute \src "libresoc.v:0.0-0.0"
49881       case 5'11101
49882         assign { } { }
49883         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49884       attribute \src "libresoc.v:0.0-0.0"
49885       case 5'11100
49886         assign { } { }
49887         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49888       attribute \src "libresoc.v:0.0-0.0"
49889       case 5'11110
49890         assign { } { }
49891         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49892       attribute \src "libresoc.v:0.0-0.0"
49893       case 5'11011
49894         assign { } { }
49895         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49896       attribute \src "libresoc.v:0.0-0.0"
49897       case 5'00011
49898         assign { } { }
49899         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49900       attribute \src "libresoc.v:0.0-0.0"
49901       case 5'01111
49902         assign { } { }
49903         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49904       attribute \src "libresoc.v:0.0-0.0"
49905       case 5'01011
49906         assign { } { }
49907         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49908       attribute \src "libresoc.v:0.0-0.0"
49909       case 5'00101
49910         assign { } { }
49911         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49912       attribute \src "libresoc.v:0.0-0.0"
49913       case 5'00100
49914         assign { } { }
49915         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49916       attribute \src "libresoc.v:0.0-0.0"
49917       case 5'11000
49918         assign { } { }
49919         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49920       attribute \src "libresoc.v:0.0-0.0"
49921       case 5'11001
49922         assign { } { }
49923         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49924       case
49925         assign $1\dec31_dec_sub26_cr_in[2:0] 3'000
49926     end
49927     sync always
49928       update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0]
49929   end
49930   attribute \src "libresoc.v:33885.3-33936.6"
49931   process $proc$libresoc.v:33885$730
49932     assign { } { }
49933     assign { } { }
49934     assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0]
49935     attribute \src "libresoc.v:33886.5-33886.29"
49936     switch \initial
49937       attribute \src "libresoc.v:33886.9-33886.17"
49938       case 1'1
49939       case
49940     end
49941     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
49942     switch \opcode_switch
49943       attribute \src "libresoc.v:0.0-0.0"
49944       case 5'00001
49945         assign { } { }
49946         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49947       attribute \src "libresoc.v:0.0-0.0"
49948       case 5'00000
49949         assign { } { }
49950         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49951       attribute \src "libresoc.v:0.0-0.0"
49952       case 5'10001
49953         assign { } { }
49954         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49955       attribute \src "libresoc.v:0.0-0.0"
49956       case 5'10000
49957         assign { } { }
49958         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49959       attribute \src "libresoc.v:0.0-0.0"
49960       case 5'11101
49961         assign { } { }
49962         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49963       attribute \src "libresoc.v:0.0-0.0"
49964       case 5'11100
49965         assign { } { }
49966         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49967       attribute \src "libresoc.v:0.0-0.0"
49968       case 5'11110
49969         assign { } { }
49970         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49971       attribute \src "libresoc.v:0.0-0.0"
49972       case 5'11011
49973         assign { } { }
49974         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49975       attribute \src "libresoc.v:0.0-0.0"
49976       case 5'00011
49977         assign { } { }
49978         assign $1\dec31_dec_sub26_cr_out[2:0] 3'000
49979       attribute \src "libresoc.v:0.0-0.0"
49980       case 5'01111
49981         assign { } { }
49982         assign $1\dec31_dec_sub26_cr_out[2:0] 3'000
49983       attribute \src "libresoc.v:0.0-0.0"
49984       case 5'01011
49985         assign { } { }
49986         assign $1\dec31_dec_sub26_cr_out[2:0] 3'000
49987       attribute \src "libresoc.v:0.0-0.0"
49988       case 5'00101
49989         assign { } { }
49990         assign $1\dec31_dec_sub26_cr_out[2:0] 3'000
49991       attribute \src "libresoc.v:0.0-0.0"
49992       case 5'00100
49993         assign { } { }
49994         assign $1\dec31_dec_sub26_cr_out[2:0] 3'000
49995       attribute \src "libresoc.v:0.0-0.0"
49996       case 5'11000
49997         assign { } { }
49998         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
49999       attribute \src "libresoc.v:0.0-0.0"
50000       case 5'11001
50001         assign { } { }
50002         assign $1\dec31_dec_sub26_cr_out[2:0] 3'001
50003       case
50004         assign $1\dec31_dec_sub26_cr_out[2:0] 3'000
50005     end
50006     sync always
50007       update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0]
50008   end
50009   connect \opcode_switch \opcode_in [10:6]
50010 end
50011 attribute \src "libresoc.v:33942.1-34657.10"
50012 attribute \cells_not_processed 1
50013 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27"
50014 attribute \generator "nMigen"
50015 module \dec31_dec_sub27
50016   attribute \src "libresoc.v:34295.3-34313.6"
50017   wire width 8 $0\dec31_dec_sub27_asmcode[7:0]
50018   attribute \src "libresoc.v:34371.3-34389.6"
50019   wire $0\dec31_dec_sub27_br[0:0]
50020   attribute \src "libresoc.v:34618.3-34636.6"
50021   wire width 3 $0\dec31_dec_sub27_cr_in[2:0]
50022   attribute \src "libresoc.v:34637.3-34655.6"
50023   wire width 3 $0\dec31_dec_sub27_cr_out[2:0]
50024   attribute \src "libresoc.v:34276.3-34294.6"
50025   wire width 2 $0\dec31_dec_sub27_cry_in[1:0]
50026   attribute \src "libresoc.v:34352.3-34370.6"
50027   wire $0\dec31_dec_sub27_cry_out[0:0]
50028   attribute \src "libresoc.v:34523.3-34541.6"
50029   wire width 5 $0\dec31_dec_sub27_form[4:0]
50030   attribute \src "libresoc.v:34200.3-34218.6"
50031   wire width 12 $0\dec31_dec_sub27_function_unit[11:0]
50032   attribute \src "libresoc.v:34542.3-34560.6"
50033   wire width 3 $0\dec31_dec_sub27_in1_sel[2:0]
50034   attribute \src "libresoc.v:34561.3-34579.6"
50035   wire width 4 $0\dec31_dec_sub27_in2_sel[3:0]
50036   attribute \src "libresoc.v:34580.3-34598.6"
50037   wire width 2 $0\dec31_dec_sub27_in3_sel[1:0]
50038   attribute \src "libresoc.v:34409.3-34427.6"
50039   wire width 7 $0\dec31_dec_sub27_internal_op[6:0]
50040   attribute \src "libresoc.v:34314.3-34332.6"
50041   wire $0\dec31_dec_sub27_inv_a[0:0]
50042   attribute \src "libresoc.v:34333.3-34351.6"
50043   wire $0\dec31_dec_sub27_inv_out[0:0]
50044   attribute \src "libresoc.v:34447.3-34465.6"
50045   wire $0\dec31_dec_sub27_is_32b[0:0]
50046   attribute \src "libresoc.v:34219.3-34237.6"
50047   wire width 4 $0\dec31_dec_sub27_ldst_len[3:0]
50048   attribute \src "libresoc.v:34485.3-34503.6"
50049   wire $0\dec31_dec_sub27_lk[0:0]
50050   attribute \src "libresoc.v:34599.3-34617.6"
50051   wire width 2 $0\dec31_dec_sub27_out_sel[1:0]
50052   attribute \src "libresoc.v:34257.3-34275.6"
50053   wire width 2 $0\dec31_dec_sub27_rc_sel[1:0]
50054   attribute \src "libresoc.v:34428.3-34446.6"
50055   wire $0\dec31_dec_sub27_rsrv[0:0]
50056   attribute \src "libresoc.v:34504.3-34522.6"
50057   wire $0\dec31_dec_sub27_sgl_pipe[0:0]
50058   attribute \src "libresoc.v:34466.3-34484.6"
50059   wire $0\dec31_dec_sub27_sgn[0:0]
50060   attribute \src "libresoc.v:34390.3-34408.6"
50061   wire $0\dec31_dec_sub27_sgn_ext[0:0]
50062   attribute \src "libresoc.v:34238.3-34256.6"
50063   wire width 2 $0\dec31_dec_sub27_upd[1:0]
50064   attribute \src "libresoc.v:33943.7-33943.20"
50065   wire $0\initial[0:0]
50066   attribute \src "libresoc.v:34295.3-34313.6"
50067   wire width 8 $1\dec31_dec_sub27_asmcode[7:0]
50068   attribute \src "libresoc.v:34371.3-34389.6"
50069   wire $1\dec31_dec_sub27_br[0:0]
50070   attribute \src "libresoc.v:34618.3-34636.6"
50071   wire width 3 $1\dec31_dec_sub27_cr_in[2:0]
50072   attribute \src "libresoc.v:34637.3-34655.6"
50073   wire width 3 $1\dec31_dec_sub27_cr_out[2:0]
50074   attribute \src "libresoc.v:34276.3-34294.6"
50075   wire width 2 $1\dec31_dec_sub27_cry_in[1:0]
50076   attribute \src "libresoc.v:34352.3-34370.6"
50077   wire $1\dec31_dec_sub27_cry_out[0:0]
50078   attribute \src "libresoc.v:34523.3-34541.6"
50079   wire width 5 $1\dec31_dec_sub27_form[4:0]
50080   attribute \src "libresoc.v:34200.3-34218.6"
50081   wire width 12 $1\dec31_dec_sub27_function_unit[11:0]
50082   attribute \src "libresoc.v:34542.3-34560.6"
50083   wire width 3 $1\dec31_dec_sub27_in1_sel[2:0]
50084   attribute \src "libresoc.v:34561.3-34579.6"
50085   wire width 4 $1\dec31_dec_sub27_in2_sel[3:0]
50086   attribute \src "libresoc.v:34580.3-34598.6"
50087   wire width 2 $1\dec31_dec_sub27_in3_sel[1:0]
50088   attribute \src "libresoc.v:34409.3-34427.6"
50089   wire width 7 $1\dec31_dec_sub27_internal_op[6:0]
50090   attribute \src "libresoc.v:34314.3-34332.6"
50091   wire $1\dec31_dec_sub27_inv_a[0:0]
50092   attribute \src "libresoc.v:34333.3-34351.6"
50093   wire $1\dec31_dec_sub27_inv_out[0:0]
50094   attribute \src "libresoc.v:34447.3-34465.6"
50095   wire $1\dec31_dec_sub27_is_32b[0:0]
50096   attribute \src "libresoc.v:34219.3-34237.6"
50097   wire width 4 $1\dec31_dec_sub27_ldst_len[3:0]
50098   attribute \src "libresoc.v:34485.3-34503.6"
50099   wire $1\dec31_dec_sub27_lk[0:0]
50100   attribute \src "libresoc.v:34599.3-34617.6"
50101   wire width 2 $1\dec31_dec_sub27_out_sel[1:0]
50102   attribute \src "libresoc.v:34257.3-34275.6"
50103   wire width 2 $1\dec31_dec_sub27_rc_sel[1:0]
50104   attribute \src "libresoc.v:34428.3-34446.6"
50105   wire $1\dec31_dec_sub27_rsrv[0:0]
50106   attribute \src "libresoc.v:34504.3-34522.6"
50107   wire $1\dec31_dec_sub27_sgl_pipe[0:0]
50108   attribute \src "libresoc.v:34466.3-34484.6"
50109   wire $1\dec31_dec_sub27_sgn[0:0]
50110   attribute \src "libresoc.v:34390.3-34408.6"
50111   wire $1\dec31_dec_sub27_sgn_ext[0:0]
50112   attribute \src "libresoc.v:34238.3-34256.6"
50113   wire width 2 $1\dec31_dec_sub27_upd[1:0]
50114   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50115   wire width 8 output 4 \dec31_dec_sub27_asmcode
50116   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50117   wire output 18 \dec31_dec_sub27_br
50118   attribute \enum_base_type "CRInSel"
50119   attribute \enum_value_000 "NONE"
50120   attribute \enum_value_001 "CR0"
50121   attribute \enum_value_010 "BI"
50122   attribute \enum_value_011 "BFA"
50123   attribute \enum_value_100 "BA_BB"
50124   attribute \enum_value_101 "BC"
50125   attribute \enum_value_110 "WHOLE_REG"
50126   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50127   wire width 3 output 9 \dec31_dec_sub27_cr_in
50128   attribute \enum_base_type "CROutSel"
50129   attribute \enum_value_000 "NONE"
50130   attribute \enum_value_001 "CR0"
50131   attribute \enum_value_010 "BF"
50132   attribute \enum_value_011 "BT"
50133   attribute \enum_value_100 "WHOLE_REG"
50134   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50135   wire width 3 output 10 \dec31_dec_sub27_cr_out
50136   attribute \enum_base_type "CryIn"
50137   attribute \enum_value_00 "ZERO"
50138   attribute \enum_value_01 "ONE"
50139   attribute \enum_value_10 "CA"
50140   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50141   wire width 2 output 14 \dec31_dec_sub27_cry_in
50142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50143   wire output 17 \dec31_dec_sub27_cry_out
50144   attribute \enum_base_type "Form"
50145   attribute \enum_value_00000 "NONE"
50146   attribute \enum_value_00001 "I"
50147   attribute \enum_value_00010 "B"
50148   attribute \enum_value_00011 "SC"
50149   attribute \enum_value_00100 "D"
50150   attribute \enum_value_00101 "DS"
50151   attribute \enum_value_00110 "DQ"
50152   attribute \enum_value_00111 "DX"
50153   attribute \enum_value_01000 "X"
50154   attribute \enum_value_01001 "XL"
50155   attribute \enum_value_01010 "XFX"
50156   attribute \enum_value_01011 "XFL"
50157   attribute \enum_value_01100 "XX1"
50158   attribute \enum_value_01101 "XX2"
50159   attribute \enum_value_01110 "XX3"
50160   attribute \enum_value_01111 "XX4"
50161   attribute \enum_value_10000 "XS"
50162   attribute \enum_value_10001 "XO"
50163   attribute \enum_value_10010 "A"
50164   attribute \enum_value_10011 "M"
50165   attribute \enum_value_10100 "MD"
50166   attribute \enum_value_10101 "MDS"
50167   attribute \enum_value_10110 "VA"
50168   attribute \enum_value_10111 "VC"
50169   attribute \enum_value_11000 "VX"
50170   attribute \enum_value_11001 "EVX"
50171   attribute \enum_value_11010 "EVS"
50172   attribute \enum_value_11011 "Z22"
50173   attribute \enum_value_11100 "Z23"
50174   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50175   wire width 5 output 3 \dec31_dec_sub27_form
50176   attribute \enum_base_type "Function"
50177   attribute \enum_value_000000000000 "NONE"
50178   attribute \enum_value_000000000010 "ALU"
50179   attribute \enum_value_000000000100 "LDST"
50180   attribute \enum_value_000000001000 "SHIFT_ROT"
50181   attribute \enum_value_000000010000 "LOGICAL"
50182   attribute \enum_value_000000100000 "BRANCH"
50183   attribute \enum_value_000001000000 "CR"
50184   attribute \enum_value_000010000000 "TRAP"
50185   attribute \enum_value_000100000000 "MUL"
50186   attribute \enum_value_001000000000 "DIV"
50187   attribute \enum_value_010000000000 "SPR"
50188   attribute \enum_value_100000000000 "MMU"
50189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50190   wire width 12 output 1 \dec31_dec_sub27_function_unit
50191   attribute \enum_base_type "In1Sel"
50192   attribute \enum_value_000 "NONE"
50193   attribute \enum_value_001 "RA"
50194   attribute \enum_value_010 "RA_OR_ZERO"
50195   attribute \enum_value_011 "SPR"
50196   attribute \enum_value_100 "RS"
50197   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50198   wire width 3 output 5 \dec31_dec_sub27_in1_sel
50199   attribute \enum_base_type "In2Sel"
50200   attribute \enum_value_0000 "NONE"
50201   attribute \enum_value_0001 "RB"
50202   attribute \enum_value_0010 "CONST_UI"
50203   attribute \enum_value_0011 "CONST_SI"
50204   attribute \enum_value_0100 "CONST_UI_HI"
50205   attribute \enum_value_0101 "CONST_SI_HI"
50206   attribute \enum_value_0110 "CONST_LI"
50207   attribute \enum_value_0111 "CONST_BD"
50208   attribute \enum_value_1000 "CONST_DS"
50209   attribute \enum_value_1001 "CONST_M1"
50210   attribute \enum_value_1010 "CONST_SH"
50211   attribute \enum_value_1011 "CONST_SH32"
50212   attribute \enum_value_1100 "SPR"
50213   attribute \enum_value_1101 "RS"
50214   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50215   wire width 4 output 6 \dec31_dec_sub27_in2_sel
50216   attribute \enum_base_type "In3Sel"
50217   attribute \enum_value_00 "NONE"
50218   attribute \enum_value_01 "RS"
50219   attribute \enum_value_10 "RB"
50220   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50221   wire width 2 output 7 \dec31_dec_sub27_in3_sel
50222   attribute \enum_base_type "MicrOp"
50223   attribute \enum_value_0000000 "OP_ILLEGAL"
50224   attribute \enum_value_0000001 "OP_NOP"
50225   attribute \enum_value_0000010 "OP_ADD"
50226   attribute \enum_value_0000011 "OP_ADDPCIS"
50227   attribute \enum_value_0000100 "OP_AND"
50228   attribute \enum_value_0000101 "OP_ATTN"
50229   attribute \enum_value_0000110 "OP_B"
50230   attribute \enum_value_0000111 "OP_BC"
50231   attribute \enum_value_0001000 "OP_BCREG"
50232   attribute \enum_value_0001001 "OP_BPERM"
50233   attribute \enum_value_0001010 "OP_CMP"
50234   attribute \enum_value_0001011 "OP_CMPB"
50235   attribute \enum_value_0001100 "OP_CMPEQB"
50236   attribute \enum_value_0001101 "OP_CMPRB"
50237   attribute \enum_value_0001110 "OP_CNTZ"
50238   attribute \enum_value_0001111 "OP_CRAND"
50239   attribute \enum_value_0010000 "OP_CRANDC"
50240   attribute \enum_value_0010001 "OP_CREQV"
50241   attribute \enum_value_0010010 "OP_CRNAND"
50242   attribute \enum_value_0010011 "OP_CRNOR"
50243   attribute \enum_value_0010100 "OP_CROR"
50244   attribute \enum_value_0010101 "OP_CRORC"
50245   attribute \enum_value_0010110 "OP_CRXOR"
50246   attribute \enum_value_0010111 "OP_DARN"
50247   attribute \enum_value_0011000 "OP_DCBF"
50248   attribute \enum_value_0011001 "OP_DCBST"
50249   attribute \enum_value_0011010 "OP_DCBT"
50250   attribute \enum_value_0011011 "OP_DCBTST"
50251   attribute \enum_value_0011100 "OP_DCBZ"
50252   attribute \enum_value_0011101 "OP_DIV"
50253   attribute \enum_value_0011110 "OP_DIVE"
50254   attribute \enum_value_0011111 "OP_EXTS"
50255   attribute \enum_value_0100000 "OP_EXTSWSLI"
50256   attribute \enum_value_0100001 "OP_ICBI"
50257   attribute \enum_value_0100010 "OP_ICBT"
50258   attribute \enum_value_0100011 "OP_ISEL"
50259   attribute \enum_value_0100100 "OP_ISYNC"
50260   attribute \enum_value_0100101 "OP_LOAD"
50261   attribute \enum_value_0100110 "OP_STORE"
50262   attribute \enum_value_0100111 "OP_MADDHD"
50263   attribute \enum_value_0101000 "OP_MADDHDU"
50264   attribute \enum_value_0101001 "OP_MADDLD"
50265   attribute \enum_value_0101010 "OP_MCRF"
50266   attribute \enum_value_0101011 "OP_MCRXR"
50267   attribute \enum_value_0101100 "OP_MCRXRX"
50268   attribute \enum_value_0101101 "OP_MFCR"
50269   attribute \enum_value_0101110 "OP_MFSPR"
50270   attribute \enum_value_0101111 "OP_MOD"
50271   attribute \enum_value_0110000 "OP_MTCRF"
50272   attribute \enum_value_0110001 "OP_MTSPR"
50273   attribute \enum_value_0110010 "OP_MUL_L64"
50274   attribute \enum_value_0110011 "OP_MUL_H64"
50275   attribute \enum_value_0110100 "OP_MUL_H32"
50276   attribute \enum_value_0110101 "OP_OR"
50277   attribute \enum_value_0110110 "OP_POPCNT"
50278   attribute \enum_value_0110111 "OP_PRTY"
50279   attribute \enum_value_0111000 "OP_RLC"
50280   attribute \enum_value_0111001 "OP_RLCL"
50281   attribute \enum_value_0111010 "OP_RLCR"
50282   attribute \enum_value_0111011 "OP_SETB"
50283   attribute \enum_value_0111100 "OP_SHL"
50284   attribute \enum_value_0111101 "OP_SHR"
50285   attribute \enum_value_0111110 "OP_SYNC"
50286   attribute \enum_value_0111111 "OP_TRAP"
50287   attribute \enum_value_1000011 "OP_XOR"
50288   attribute \enum_value_1000100 "OP_SIM_CONFIG"
50289   attribute \enum_value_1000101 "OP_CROP"
50290   attribute \enum_value_1000110 "OP_RFID"
50291   attribute \enum_value_1000111 "OP_MFMSR"
50292   attribute \enum_value_1001000 "OP_MTMSRD"
50293   attribute \enum_value_1001001 "OP_SC"
50294   attribute \enum_value_1001010 "OP_MTMSR"
50295   attribute \enum_value_1001011 "OP_TLBIE"
50296   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50297   wire width 7 output 2 \dec31_dec_sub27_internal_op
50298   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50299   wire output 15 \dec31_dec_sub27_inv_a
50300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50301   wire output 16 \dec31_dec_sub27_inv_out
50302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50303   wire output 21 \dec31_dec_sub27_is_32b
50304   attribute \enum_base_type "LdstLen"
50305   attribute \enum_value_0000 "NONE"
50306   attribute \enum_value_0001 "is1B"
50307   attribute \enum_value_0010 "is2B"
50308   attribute \enum_value_0100 "is4B"
50309   attribute \enum_value_1000 "is8B"
50310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50311   wire width 4 output 11 \dec31_dec_sub27_ldst_len
50312   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50313   wire output 23 \dec31_dec_sub27_lk
50314   attribute \enum_base_type "OutSel"
50315   attribute \enum_value_00 "NONE"
50316   attribute \enum_value_01 "RT"
50317   attribute \enum_value_10 "RA"
50318   attribute \enum_value_11 "SPR"
50319   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50320   wire width 2 output 8 \dec31_dec_sub27_out_sel
50321   attribute \enum_base_type "RC"
50322   attribute \enum_value_00 "NONE"
50323   attribute \enum_value_01 "ONE"
50324   attribute \enum_value_10 "RC"
50325   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50326   wire width 2 output 13 \dec31_dec_sub27_rc_sel
50327   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50328   wire output 20 \dec31_dec_sub27_rsrv
50329   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50330   wire output 24 \dec31_dec_sub27_sgl_pipe
50331   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50332   wire output 22 \dec31_dec_sub27_sgn
50333   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
50334   wire output 19 \dec31_dec_sub27_sgn_ext
50335   attribute \enum_base_type "LDSTMode"
50336   attribute \enum_value_00 "NONE"
50337   attribute \enum_value_01 "update"
50338   attribute \enum_value_10 "cix"
50339   attribute \enum_value_11 "cx"
50340   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
50341   wire width 2 output 12 \dec31_dec_sub27_upd
50342   attribute \src "libresoc.v:33943.7-33943.15"
50343   wire \initial
50344   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
50345   wire width 32 input 25 \opcode_in
50346   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
50347   wire width 5 \opcode_switch
50348   attribute \src "libresoc.v:33943.7-33943.20"
50349   process $proc$libresoc.v:33943$756
50350     assign { } { }
50351     assign $0\initial[0:0] 1'0
50352     sync always
50353       update \initial $0\initial[0:0]
50354     sync init
50355   end
50356   attribute \src "libresoc.v:34200.3-34218.6"
50357   process $proc$libresoc.v:34200$732
50358     assign { } { }
50359     assign { } { }
50360     assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0]
50361     attribute \src "libresoc.v:34201.5-34201.29"
50362     switch \initial
50363       attribute \src "libresoc.v:34201.9-34201.17"
50364       case 1'1
50365       case
50366     end
50367     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50368     switch \opcode_switch
50369       attribute \src "libresoc.v:0.0-0.0"
50370       case 5'11011
50371         assign { } { }
50372         assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000
50373       attribute \src "libresoc.v:0.0-0.0"
50374       case 5'00000
50375         assign { } { }
50376         assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000
50377       attribute \src "libresoc.v:0.0-0.0"
50378       case 5'11001
50379         assign { } { }
50380         assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000
50381       attribute \src "libresoc.v:0.0-0.0"
50382       case 5'10000
50383         assign { } { }
50384         assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000
50385       case
50386         assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000
50387     end
50388     sync always
50389       update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0]
50390   end
50391   attribute \src "libresoc.v:34219.3-34237.6"
50392   process $proc$libresoc.v:34219$733
50393     assign { } { }
50394     assign { } { }
50395     assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0]
50396     attribute \src "libresoc.v:34220.5-34220.29"
50397     switch \initial
50398       attribute \src "libresoc.v:34220.9-34220.17"
50399       case 1'1
50400       case
50401     end
50402     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50403     switch \opcode_switch
50404       attribute \src "libresoc.v:0.0-0.0"
50405       case 5'11011
50406         assign { } { }
50407         assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000
50408       attribute \src "libresoc.v:0.0-0.0"
50409       case 5'00000
50410         assign { } { }
50411         assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000
50412       attribute \src "libresoc.v:0.0-0.0"
50413       case 5'11001
50414         assign { } { }
50415         assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000
50416       attribute \src "libresoc.v:0.0-0.0"
50417       case 5'10000
50418         assign { } { }
50419         assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000
50420       case
50421         assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000
50422     end
50423     sync always
50424       update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0]
50425   end
50426   attribute \src "libresoc.v:34238.3-34256.6"
50427   process $proc$libresoc.v:34238$734
50428     assign { } { }
50429     assign { } { }
50430     assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0]
50431     attribute \src "libresoc.v:34239.5-34239.29"
50432     switch \initial
50433       attribute \src "libresoc.v:34239.9-34239.17"
50434       case 1'1
50435       case
50436     end
50437     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50438     switch \opcode_switch
50439       attribute \src "libresoc.v:0.0-0.0"
50440       case 5'11011
50441         assign { } { }
50442         assign $1\dec31_dec_sub27_upd[1:0] 2'00
50443       attribute \src "libresoc.v:0.0-0.0"
50444       case 5'00000
50445         assign { } { }
50446         assign $1\dec31_dec_sub27_upd[1:0] 2'00
50447       attribute \src "libresoc.v:0.0-0.0"
50448       case 5'11001
50449         assign { } { }
50450         assign $1\dec31_dec_sub27_upd[1:0] 2'00
50451       attribute \src "libresoc.v:0.0-0.0"
50452       case 5'10000
50453         assign { } { }
50454         assign $1\dec31_dec_sub27_upd[1:0] 2'00
50455       case
50456         assign $1\dec31_dec_sub27_upd[1:0] 2'00
50457     end
50458     sync always
50459       update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0]
50460   end
50461   attribute \src "libresoc.v:34257.3-34275.6"
50462   process $proc$libresoc.v:34257$735
50463     assign { } { }
50464     assign { } { }
50465     assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0]
50466     attribute \src "libresoc.v:34258.5-34258.29"
50467     switch \initial
50468       attribute \src "libresoc.v:34258.9-34258.17"
50469       case 1'1
50470       case
50471     end
50472     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50473     switch \opcode_switch
50474       attribute \src "libresoc.v:0.0-0.0"
50475       case 5'11011
50476         assign { } { }
50477         assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10
50478       attribute \src "libresoc.v:0.0-0.0"
50479       case 5'00000
50480         assign { } { }
50481         assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10
50482       attribute \src "libresoc.v:0.0-0.0"
50483       case 5'11001
50484         assign { } { }
50485         assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10
50486       attribute \src "libresoc.v:0.0-0.0"
50487       case 5'10000
50488         assign { } { }
50489         assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10
50490       case
50491         assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00
50492     end
50493     sync always
50494       update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0]
50495   end
50496   attribute \src "libresoc.v:34276.3-34294.6"
50497   process $proc$libresoc.v:34276$736
50498     assign { } { }
50499     assign { } { }
50500     assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0]
50501     attribute \src "libresoc.v:34277.5-34277.29"
50502     switch \initial
50503       attribute \src "libresoc.v:34277.9-34277.17"
50504       case 1'1
50505       case
50506     end
50507     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50508     switch \opcode_switch
50509       attribute \src "libresoc.v:0.0-0.0"
50510       case 5'11011
50511         assign { } { }
50512         assign $1\dec31_dec_sub27_cry_in[1:0] 2'00
50513       attribute \src "libresoc.v:0.0-0.0"
50514       case 5'00000
50515         assign { } { }
50516         assign $1\dec31_dec_sub27_cry_in[1:0] 2'00
50517       attribute \src "libresoc.v:0.0-0.0"
50518       case 5'11001
50519         assign { } { }
50520         assign $1\dec31_dec_sub27_cry_in[1:0] 2'00
50521       attribute \src "libresoc.v:0.0-0.0"
50522       case 5'10000
50523         assign { } { }
50524         assign $1\dec31_dec_sub27_cry_in[1:0] 2'00
50525       case
50526         assign $1\dec31_dec_sub27_cry_in[1:0] 2'00
50527     end
50528     sync always
50529       update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0]
50530   end
50531   attribute \src "libresoc.v:34295.3-34313.6"
50532   process $proc$libresoc.v:34295$737
50533     assign { } { }
50534     assign { } { }
50535     assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0]
50536     attribute \src "libresoc.v:34296.5-34296.29"
50537     switch \initial
50538       attribute \src "libresoc.v:34296.9-34296.17"
50539       case 1'1
50540       case
50541     end
50542     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50543     switch \opcode_switch
50544       attribute \src "libresoc.v:0.0-0.0"
50545       case 5'11011
50546         assign { } { }
50547         assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111
50548       attribute \src "libresoc.v:0.0-0.0"
50549       case 5'00000
50550         assign { } { }
50551         assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110
50552       attribute \src "libresoc.v:0.0-0.0"
50553       case 5'11001
50554         assign { } { }
50555         assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001
50556       attribute \src "libresoc.v:0.0-0.0"
50557       case 5'10000
50558         assign { } { }
50559         assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100
50560       case
50561         assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000
50562     end
50563     sync always
50564       update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0]
50565   end
50566   attribute \src "libresoc.v:34314.3-34332.6"
50567   process $proc$libresoc.v:34314$738
50568     assign { } { }
50569     assign { } { }
50570     assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0]
50571     attribute \src "libresoc.v:34315.5-34315.29"
50572     switch \initial
50573       attribute \src "libresoc.v:34315.9-34315.17"
50574       case 1'1
50575       case
50576     end
50577     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50578     switch \opcode_switch
50579       attribute \src "libresoc.v:0.0-0.0"
50580       case 5'11011
50581         assign { } { }
50582         assign $1\dec31_dec_sub27_inv_a[0:0] 1'0
50583       attribute \src "libresoc.v:0.0-0.0"
50584       case 5'00000
50585         assign { } { }
50586         assign $1\dec31_dec_sub27_inv_a[0:0] 1'0
50587       attribute \src "libresoc.v:0.0-0.0"
50588       case 5'11001
50589         assign { } { }
50590         assign $1\dec31_dec_sub27_inv_a[0:0] 1'0
50591       attribute \src "libresoc.v:0.0-0.0"
50592       case 5'10000
50593         assign { } { }
50594         assign $1\dec31_dec_sub27_inv_a[0:0] 1'0
50595       case
50596         assign $1\dec31_dec_sub27_inv_a[0:0] 1'0
50597     end
50598     sync always
50599       update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0]
50600   end
50601   attribute \src "libresoc.v:34333.3-34351.6"
50602   process $proc$libresoc.v:34333$739
50603     assign { } { }
50604     assign { } { }
50605     assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0]
50606     attribute \src "libresoc.v:34334.5-34334.29"
50607     switch \initial
50608       attribute \src "libresoc.v:34334.9-34334.17"
50609       case 1'1
50610       case
50611     end
50612     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50613     switch \opcode_switch
50614       attribute \src "libresoc.v:0.0-0.0"
50615       case 5'11011
50616         assign { } { }
50617         assign $1\dec31_dec_sub27_inv_out[0:0] 1'0
50618       attribute \src "libresoc.v:0.0-0.0"
50619       case 5'00000
50620         assign { } { }
50621         assign $1\dec31_dec_sub27_inv_out[0:0] 1'0
50622       attribute \src "libresoc.v:0.0-0.0"
50623       case 5'11001
50624         assign { } { }
50625         assign $1\dec31_dec_sub27_inv_out[0:0] 1'0
50626       attribute \src "libresoc.v:0.0-0.0"
50627       case 5'10000
50628         assign { } { }
50629         assign $1\dec31_dec_sub27_inv_out[0:0] 1'0
50630       case
50631         assign $1\dec31_dec_sub27_inv_out[0:0] 1'0
50632     end
50633     sync always
50634       update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0]
50635   end
50636   attribute \src "libresoc.v:34352.3-34370.6"
50637   process $proc$libresoc.v:34352$740
50638     assign { } { }
50639     assign { } { }
50640     assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0]
50641     attribute \src "libresoc.v:34353.5-34353.29"
50642     switch \initial
50643       attribute \src "libresoc.v:34353.9-34353.17"
50644       case 1'1
50645       case
50646     end
50647     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50648     switch \opcode_switch
50649       attribute \src "libresoc.v:0.0-0.0"
50650       case 5'11011
50651         assign { } { }
50652         assign $1\dec31_dec_sub27_cry_out[0:0] 1'0
50653       attribute \src "libresoc.v:0.0-0.0"
50654       case 5'00000
50655         assign { } { }
50656         assign $1\dec31_dec_sub27_cry_out[0:0] 1'0
50657       attribute \src "libresoc.v:0.0-0.0"
50658       case 5'11001
50659         assign { } { }
50660         assign $1\dec31_dec_sub27_cry_out[0:0] 1'1
50661       attribute \src "libresoc.v:0.0-0.0"
50662       case 5'10000
50663         assign { } { }
50664         assign $1\dec31_dec_sub27_cry_out[0:0] 1'0
50665       case
50666         assign $1\dec31_dec_sub27_cry_out[0:0] 1'0
50667     end
50668     sync always
50669       update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0]
50670   end
50671   attribute \src "libresoc.v:34371.3-34389.6"
50672   process $proc$libresoc.v:34371$741
50673     assign { } { }
50674     assign { } { }
50675     assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0]
50676     attribute \src "libresoc.v:34372.5-34372.29"
50677     switch \initial
50678       attribute \src "libresoc.v:34372.9-34372.17"
50679       case 1'1
50680       case
50681     end
50682     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50683     switch \opcode_switch
50684       attribute \src "libresoc.v:0.0-0.0"
50685       case 5'11011
50686         assign { } { }
50687         assign $1\dec31_dec_sub27_br[0:0] 1'0
50688       attribute \src "libresoc.v:0.0-0.0"
50689       case 5'00000
50690         assign { } { }
50691         assign $1\dec31_dec_sub27_br[0:0] 1'0
50692       attribute \src "libresoc.v:0.0-0.0"
50693       case 5'11001
50694         assign { } { }
50695         assign $1\dec31_dec_sub27_br[0:0] 1'0
50696       attribute \src "libresoc.v:0.0-0.0"
50697       case 5'10000
50698         assign { } { }
50699         assign $1\dec31_dec_sub27_br[0:0] 1'0
50700       case
50701         assign $1\dec31_dec_sub27_br[0:0] 1'0
50702     end
50703     sync always
50704       update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0]
50705   end
50706   attribute \src "libresoc.v:34390.3-34408.6"
50707   process $proc$libresoc.v:34390$742
50708     assign { } { }
50709     assign { } { }
50710     assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0]
50711     attribute \src "libresoc.v:34391.5-34391.29"
50712     switch \initial
50713       attribute \src "libresoc.v:34391.9-34391.17"
50714       case 1'1
50715       case
50716     end
50717     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50718     switch \opcode_switch
50719       attribute \src "libresoc.v:0.0-0.0"
50720       case 5'11011
50721         assign { } { }
50722         assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0
50723       attribute \src "libresoc.v:0.0-0.0"
50724       case 5'00000
50725         assign { } { }
50726         assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0
50727       attribute \src "libresoc.v:0.0-0.0"
50728       case 5'11001
50729         assign { } { }
50730         assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0
50731       attribute \src "libresoc.v:0.0-0.0"
50732       case 5'10000
50733         assign { } { }
50734         assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0
50735       case
50736         assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0
50737     end
50738     sync always
50739       update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0]
50740   end
50741   attribute \src "libresoc.v:34409.3-34427.6"
50742   process $proc$libresoc.v:34409$743
50743     assign { } { }
50744     assign { } { }
50745     assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0]
50746     attribute \src "libresoc.v:34410.5-34410.29"
50747     switch \initial
50748       attribute \src "libresoc.v:34410.9-34410.17"
50749       case 1'1
50750       case
50751     end
50752     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50753     switch \opcode_switch
50754       attribute \src "libresoc.v:0.0-0.0"
50755       case 5'11011
50756         assign { } { }
50757         assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000
50758       attribute \src "libresoc.v:0.0-0.0"
50759       case 5'00000
50760         assign { } { }
50761         assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100
50762       attribute \src "libresoc.v:0.0-0.0"
50763       case 5'11001
50764         assign { } { }
50765         assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101
50766       attribute \src "libresoc.v:0.0-0.0"
50767       case 5'10000
50768         assign { } { }
50769         assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101
50770       case
50771         assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000
50772     end
50773     sync always
50774       update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0]
50775   end
50776   attribute \src "libresoc.v:34428.3-34446.6"
50777   process $proc$libresoc.v:34428$744
50778     assign { } { }
50779     assign { } { }
50780     assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0]
50781     attribute \src "libresoc.v:34429.5-34429.29"
50782     switch \initial
50783       attribute \src "libresoc.v:34429.9-34429.17"
50784       case 1'1
50785       case
50786     end
50787     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50788     switch \opcode_switch
50789       attribute \src "libresoc.v:0.0-0.0"
50790       case 5'11011
50791         assign { } { }
50792         assign $1\dec31_dec_sub27_rsrv[0:0] 1'0
50793       attribute \src "libresoc.v:0.0-0.0"
50794       case 5'00000
50795         assign { } { }
50796         assign $1\dec31_dec_sub27_rsrv[0:0] 1'0
50797       attribute \src "libresoc.v:0.0-0.0"
50798       case 5'11001
50799         assign { } { }
50800         assign $1\dec31_dec_sub27_rsrv[0:0] 1'0
50801       attribute \src "libresoc.v:0.0-0.0"
50802       case 5'10000
50803         assign { } { }
50804         assign $1\dec31_dec_sub27_rsrv[0:0] 1'0
50805       case
50806         assign $1\dec31_dec_sub27_rsrv[0:0] 1'0
50807     end
50808     sync always
50809       update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0]
50810   end
50811   attribute \src "libresoc.v:34447.3-34465.6"
50812   process $proc$libresoc.v:34447$745
50813     assign { } { }
50814     assign { } { }
50815     assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0]
50816     attribute \src "libresoc.v:34448.5-34448.29"
50817     switch \initial
50818       attribute \src "libresoc.v:34448.9-34448.17"
50819       case 1'1
50820       case
50821     end
50822     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50823     switch \opcode_switch
50824       attribute \src "libresoc.v:0.0-0.0"
50825       case 5'11011
50826         assign { } { }
50827         assign $1\dec31_dec_sub27_is_32b[0:0] 1'0
50828       attribute \src "libresoc.v:0.0-0.0"
50829       case 5'00000
50830         assign { } { }
50831         assign $1\dec31_dec_sub27_is_32b[0:0] 1'0
50832       attribute \src "libresoc.v:0.0-0.0"
50833       case 5'11001
50834         assign { } { }
50835         assign $1\dec31_dec_sub27_is_32b[0:0] 1'0
50836       attribute \src "libresoc.v:0.0-0.0"
50837       case 5'10000
50838         assign { } { }
50839         assign $1\dec31_dec_sub27_is_32b[0:0] 1'0
50840       case
50841         assign $1\dec31_dec_sub27_is_32b[0:0] 1'0
50842     end
50843     sync always
50844       update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0]
50845   end
50846   attribute \src "libresoc.v:34466.3-34484.6"
50847   process $proc$libresoc.v:34466$746
50848     assign { } { }
50849     assign { } { }
50850     assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0]
50851     attribute \src "libresoc.v:34467.5-34467.29"
50852     switch \initial
50853       attribute \src "libresoc.v:34467.9-34467.17"
50854       case 1'1
50855       case
50856     end
50857     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50858     switch \opcode_switch
50859       attribute \src "libresoc.v:0.0-0.0"
50860       case 5'11011
50861         assign { } { }
50862         assign $1\dec31_dec_sub27_sgn[0:0] 1'0
50863       attribute \src "libresoc.v:0.0-0.0"
50864       case 5'00000
50865         assign { } { }
50866         assign $1\dec31_dec_sub27_sgn[0:0] 1'0
50867       attribute \src "libresoc.v:0.0-0.0"
50868       case 5'11001
50869         assign { } { }
50870         assign $1\dec31_dec_sub27_sgn[0:0] 1'1
50871       attribute \src "libresoc.v:0.0-0.0"
50872       case 5'10000
50873         assign { } { }
50874         assign $1\dec31_dec_sub27_sgn[0:0] 1'0
50875       case
50876         assign $1\dec31_dec_sub27_sgn[0:0] 1'0
50877     end
50878     sync always
50879       update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0]
50880   end
50881   attribute \src "libresoc.v:34485.3-34503.6"
50882   process $proc$libresoc.v:34485$747
50883     assign { } { }
50884     assign { } { }
50885     assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0]
50886     attribute \src "libresoc.v:34486.5-34486.29"
50887     switch \initial
50888       attribute \src "libresoc.v:34486.9-34486.17"
50889       case 1'1
50890       case
50891     end
50892     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50893     switch \opcode_switch
50894       attribute \src "libresoc.v:0.0-0.0"
50895       case 5'11011
50896         assign { } { }
50897         assign $1\dec31_dec_sub27_lk[0:0] 1'0
50898       attribute \src "libresoc.v:0.0-0.0"
50899       case 5'00000
50900         assign { } { }
50901         assign $1\dec31_dec_sub27_lk[0:0] 1'0
50902       attribute \src "libresoc.v:0.0-0.0"
50903       case 5'11001
50904         assign { } { }
50905         assign $1\dec31_dec_sub27_lk[0:0] 1'0
50906       attribute \src "libresoc.v:0.0-0.0"
50907       case 5'10000
50908         assign { } { }
50909         assign $1\dec31_dec_sub27_lk[0:0] 1'0
50910       case
50911         assign $1\dec31_dec_sub27_lk[0:0] 1'0
50912     end
50913     sync always
50914       update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0]
50915   end
50916   attribute \src "libresoc.v:34504.3-34522.6"
50917   process $proc$libresoc.v:34504$748
50918     assign { } { }
50919     assign { } { }
50920     assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0]
50921     attribute \src "libresoc.v:34505.5-34505.29"
50922     switch \initial
50923       attribute \src "libresoc.v:34505.9-34505.17"
50924       case 1'1
50925       case
50926     end
50927     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50928     switch \opcode_switch
50929       attribute \src "libresoc.v:0.0-0.0"
50930       case 5'11011
50931         assign { } { }
50932         assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0
50933       attribute \src "libresoc.v:0.0-0.0"
50934       case 5'00000
50935         assign { } { }
50936         assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0
50937       attribute \src "libresoc.v:0.0-0.0"
50938       case 5'11001
50939         assign { } { }
50940         assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0
50941       attribute \src "libresoc.v:0.0-0.0"
50942       case 5'10000
50943         assign { } { }
50944         assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0
50945       case
50946         assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0
50947     end
50948     sync always
50949       update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0]
50950   end
50951   attribute \src "libresoc.v:34523.3-34541.6"
50952   process $proc$libresoc.v:34523$749
50953     assign { } { }
50954     assign { } { }
50955     assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0]
50956     attribute \src "libresoc.v:34524.5-34524.29"
50957     switch \initial
50958       attribute \src "libresoc.v:34524.9-34524.17"
50959       case 1'1
50960       case
50961     end
50962     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50963     switch \opcode_switch
50964       attribute \src "libresoc.v:0.0-0.0"
50965       case 5'11011
50966         assign { } { }
50967         assign $1\dec31_dec_sub27_form[4:0] 5'10000
50968       attribute \src "libresoc.v:0.0-0.0"
50969       case 5'00000
50970         assign { } { }
50971         assign $1\dec31_dec_sub27_form[4:0] 5'01000
50972       attribute \src "libresoc.v:0.0-0.0"
50973       case 5'11001
50974         assign { } { }
50975         assign $1\dec31_dec_sub27_form[4:0] 5'10000
50976       attribute \src "libresoc.v:0.0-0.0"
50977       case 5'10000
50978         assign { } { }
50979         assign $1\dec31_dec_sub27_form[4:0] 5'01000
50980       case
50981         assign $1\dec31_dec_sub27_form[4:0] 5'00000
50982     end
50983     sync always
50984       update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0]
50985   end
50986   attribute \src "libresoc.v:34542.3-34560.6"
50987   process $proc$libresoc.v:34542$750
50988     assign { } { }
50989     assign { } { }
50990     assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0]
50991     attribute \src "libresoc.v:34543.5-34543.29"
50992     switch \initial
50993       attribute \src "libresoc.v:34543.9-34543.17"
50994       case 1'1
50995       case
50996     end
50997     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
50998     switch \opcode_switch
50999       attribute \src "libresoc.v:0.0-0.0"
51000       case 5'11011
51001         assign { } { }
51002         assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000
51003       attribute \src "libresoc.v:0.0-0.0"
51004       case 5'00000
51005         assign { } { }
51006         assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000
51007       attribute \src "libresoc.v:0.0-0.0"
51008       case 5'11001
51009         assign { } { }
51010         assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000
51011       attribute \src "libresoc.v:0.0-0.0"
51012       case 5'10000
51013         assign { } { }
51014         assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000
51015       case
51016         assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000
51017     end
51018     sync always
51019       update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0]
51020   end
51021   attribute \src "libresoc.v:34561.3-34579.6"
51022   process $proc$libresoc.v:34561$751
51023     assign { } { }
51024     assign { } { }
51025     assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0]
51026     attribute \src "libresoc.v:34562.5-34562.29"
51027     switch \initial
51028       attribute \src "libresoc.v:34562.9-34562.17"
51029       case 1'1
51030       case
51031     end
51032     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51033     switch \opcode_switch
51034       attribute \src "libresoc.v:0.0-0.0"
51035       case 5'11011
51036         assign { } { }
51037         assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010
51038       attribute \src "libresoc.v:0.0-0.0"
51039       case 5'00000
51040         assign { } { }
51041         assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001
51042       attribute \src "libresoc.v:0.0-0.0"
51043       case 5'11001
51044         assign { } { }
51045         assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010
51046       attribute \src "libresoc.v:0.0-0.0"
51047       case 5'10000
51048         assign { } { }
51049         assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001
51050       case
51051         assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000
51052     end
51053     sync always
51054       update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0]
51055   end
51056   attribute \src "libresoc.v:34580.3-34598.6"
51057   process $proc$libresoc.v:34580$752
51058     assign { } { }
51059     assign { } { }
51060     assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0]
51061     attribute \src "libresoc.v:34581.5-34581.29"
51062     switch \initial
51063       attribute \src "libresoc.v:34581.9-34581.17"
51064       case 1'1
51065       case
51066     end
51067     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51068     switch \opcode_switch
51069       attribute \src "libresoc.v:0.0-0.0"
51070       case 5'11011
51071         assign { } { }
51072         assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01
51073       attribute \src "libresoc.v:0.0-0.0"
51074       case 5'00000
51075         assign { } { }
51076         assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01
51077       attribute \src "libresoc.v:0.0-0.0"
51078       case 5'11001
51079         assign { } { }
51080         assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01
51081       attribute \src "libresoc.v:0.0-0.0"
51082       case 5'10000
51083         assign { } { }
51084         assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01
51085       case
51086         assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00
51087     end
51088     sync always
51089       update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0]
51090   end
51091   attribute \src "libresoc.v:34599.3-34617.6"
51092   process $proc$libresoc.v:34599$753
51093     assign { } { }
51094     assign { } { }
51095     assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0]
51096     attribute \src "libresoc.v:34600.5-34600.29"
51097     switch \initial
51098       attribute \src "libresoc.v:34600.9-34600.17"
51099       case 1'1
51100       case
51101     end
51102     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51103     switch \opcode_switch
51104       attribute \src "libresoc.v:0.0-0.0"
51105       case 5'11011
51106         assign { } { }
51107         assign $1\dec31_dec_sub27_out_sel[1:0] 2'10
51108       attribute \src "libresoc.v:0.0-0.0"
51109       case 5'00000
51110         assign { } { }
51111         assign $1\dec31_dec_sub27_out_sel[1:0] 2'10
51112       attribute \src "libresoc.v:0.0-0.0"
51113       case 5'11001
51114         assign { } { }
51115         assign $1\dec31_dec_sub27_out_sel[1:0] 2'10
51116       attribute \src "libresoc.v:0.0-0.0"
51117       case 5'10000
51118         assign { } { }
51119         assign $1\dec31_dec_sub27_out_sel[1:0] 2'10
51120       case
51121         assign $1\dec31_dec_sub27_out_sel[1:0] 2'00
51122     end
51123     sync always
51124       update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0]
51125   end
51126   attribute \src "libresoc.v:34618.3-34636.6"
51127   process $proc$libresoc.v:34618$754
51128     assign { } { }
51129     assign { } { }
51130     assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0]
51131     attribute \src "libresoc.v:34619.5-34619.29"
51132     switch \initial
51133       attribute \src "libresoc.v:34619.9-34619.17"
51134       case 1'1
51135       case
51136     end
51137     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51138     switch \opcode_switch
51139       attribute \src "libresoc.v:0.0-0.0"
51140       case 5'11011
51141         assign { } { }
51142         assign $1\dec31_dec_sub27_cr_in[2:0] 3'000
51143       attribute \src "libresoc.v:0.0-0.0"
51144       case 5'00000
51145         assign { } { }
51146         assign $1\dec31_dec_sub27_cr_in[2:0] 3'000
51147       attribute \src "libresoc.v:0.0-0.0"
51148       case 5'11001
51149         assign { } { }
51150         assign $1\dec31_dec_sub27_cr_in[2:0] 3'000
51151       attribute \src "libresoc.v:0.0-0.0"
51152       case 5'10000
51153         assign { } { }
51154         assign $1\dec31_dec_sub27_cr_in[2:0] 3'000
51155       case
51156         assign $1\dec31_dec_sub27_cr_in[2:0] 3'000
51157     end
51158     sync always
51159       update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0]
51160   end
51161   attribute \src "libresoc.v:34637.3-34655.6"
51162   process $proc$libresoc.v:34637$755
51163     assign { } { }
51164     assign { } { }
51165     assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0]
51166     attribute \src "libresoc.v:34638.5-34638.29"
51167     switch \initial
51168       attribute \src "libresoc.v:34638.9-34638.17"
51169       case 1'1
51170       case
51171     end
51172     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51173     switch \opcode_switch
51174       attribute \src "libresoc.v:0.0-0.0"
51175       case 5'11011
51176         assign { } { }
51177         assign $1\dec31_dec_sub27_cr_out[2:0] 3'001
51178       attribute \src "libresoc.v:0.0-0.0"
51179       case 5'00000
51180         assign { } { }
51181         assign $1\dec31_dec_sub27_cr_out[2:0] 3'001
51182       attribute \src "libresoc.v:0.0-0.0"
51183       case 5'11001
51184         assign { } { }
51185         assign $1\dec31_dec_sub27_cr_out[2:0] 3'001
51186       attribute \src "libresoc.v:0.0-0.0"
51187       case 5'10000
51188         assign { } { }
51189         assign $1\dec31_dec_sub27_cr_out[2:0] 3'001
51190       case
51191         assign $1\dec31_dec_sub27_cr_out[2:0] 3'000
51192     end
51193     sync always
51194       update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0]
51195   end
51196   connect \opcode_switch \opcode_in [10:6]
51197 end
51198 attribute \src "libresoc.v:34661.1-35808.10"
51199 attribute \cells_not_processed 1
51200 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28"
51201 attribute \generator "nMigen"
51202 module \dec31_dec_sub28
51203   attribute \src "libresoc.v:35104.3-35140.6"
51204   wire width 8 $0\dec31_dec_sub28_asmcode[7:0]
51205   attribute \src "libresoc.v:35252.3-35288.6"
51206   wire $0\dec31_dec_sub28_br[0:0]
51207   attribute \src "libresoc.v:35733.3-35769.6"
51208   wire width 3 $0\dec31_dec_sub28_cr_in[2:0]
51209   attribute \src "libresoc.v:35770.3-35806.6"
51210   wire width 3 $0\dec31_dec_sub28_cr_out[2:0]
51211   attribute \src "libresoc.v:35067.3-35103.6"
51212   wire width 2 $0\dec31_dec_sub28_cry_in[1:0]
51213   attribute \src "libresoc.v:35215.3-35251.6"
51214   wire $0\dec31_dec_sub28_cry_out[0:0]
51215   attribute \src "libresoc.v:35548.3-35584.6"
51216   wire width 5 $0\dec31_dec_sub28_form[4:0]
51217   attribute \src "libresoc.v:34919.3-34955.6"
51218   wire width 12 $0\dec31_dec_sub28_function_unit[11:0]
51219   attribute \src "libresoc.v:35585.3-35621.6"
51220   wire width 3 $0\dec31_dec_sub28_in1_sel[2:0]
51221   attribute \src "libresoc.v:35622.3-35658.6"
51222   wire width 4 $0\dec31_dec_sub28_in2_sel[3:0]
51223   attribute \src "libresoc.v:35659.3-35695.6"
51224   wire width 2 $0\dec31_dec_sub28_in3_sel[1:0]
51225   attribute \src "libresoc.v:35326.3-35362.6"
51226   wire width 7 $0\dec31_dec_sub28_internal_op[6:0]
51227   attribute \src "libresoc.v:35141.3-35177.6"
51228   wire $0\dec31_dec_sub28_inv_a[0:0]
51229   attribute \src "libresoc.v:35178.3-35214.6"
51230   wire $0\dec31_dec_sub28_inv_out[0:0]
51231   attribute \src "libresoc.v:35400.3-35436.6"
51232   wire $0\dec31_dec_sub28_is_32b[0:0]
51233   attribute \src "libresoc.v:34956.3-34992.6"
51234   wire width 4 $0\dec31_dec_sub28_ldst_len[3:0]
51235   attribute \src "libresoc.v:35474.3-35510.6"
51236   wire $0\dec31_dec_sub28_lk[0:0]
51237   attribute \src "libresoc.v:35696.3-35732.6"
51238   wire width 2 $0\dec31_dec_sub28_out_sel[1:0]
51239   attribute \src "libresoc.v:35030.3-35066.6"
51240   wire width 2 $0\dec31_dec_sub28_rc_sel[1:0]
51241   attribute \src "libresoc.v:35363.3-35399.6"
51242   wire $0\dec31_dec_sub28_rsrv[0:0]
51243   attribute \src "libresoc.v:35511.3-35547.6"
51244   wire $0\dec31_dec_sub28_sgl_pipe[0:0]
51245   attribute \src "libresoc.v:35437.3-35473.6"
51246   wire $0\dec31_dec_sub28_sgn[0:0]
51247   attribute \src "libresoc.v:35289.3-35325.6"
51248   wire $0\dec31_dec_sub28_sgn_ext[0:0]
51249   attribute \src "libresoc.v:34993.3-35029.6"
51250   wire width 2 $0\dec31_dec_sub28_upd[1:0]
51251   attribute \src "libresoc.v:34662.7-34662.20"
51252   wire $0\initial[0:0]
51253   attribute \src "libresoc.v:35104.3-35140.6"
51254   wire width 8 $1\dec31_dec_sub28_asmcode[7:0]
51255   attribute \src "libresoc.v:35252.3-35288.6"
51256   wire $1\dec31_dec_sub28_br[0:0]
51257   attribute \src "libresoc.v:35733.3-35769.6"
51258   wire width 3 $1\dec31_dec_sub28_cr_in[2:0]
51259   attribute \src "libresoc.v:35770.3-35806.6"
51260   wire width 3 $1\dec31_dec_sub28_cr_out[2:0]
51261   attribute \src "libresoc.v:35067.3-35103.6"
51262   wire width 2 $1\dec31_dec_sub28_cry_in[1:0]
51263   attribute \src "libresoc.v:35215.3-35251.6"
51264   wire $1\dec31_dec_sub28_cry_out[0:0]
51265   attribute \src "libresoc.v:35548.3-35584.6"
51266   wire width 5 $1\dec31_dec_sub28_form[4:0]
51267   attribute \src "libresoc.v:34919.3-34955.6"
51268   wire width 12 $1\dec31_dec_sub28_function_unit[11:0]
51269   attribute \src "libresoc.v:35585.3-35621.6"
51270   wire width 3 $1\dec31_dec_sub28_in1_sel[2:0]
51271   attribute \src "libresoc.v:35622.3-35658.6"
51272   wire width 4 $1\dec31_dec_sub28_in2_sel[3:0]
51273   attribute \src "libresoc.v:35659.3-35695.6"
51274   wire width 2 $1\dec31_dec_sub28_in3_sel[1:0]
51275   attribute \src "libresoc.v:35326.3-35362.6"
51276   wire width 7 $1\dec31_dec_sub28_internal_op[6:0]
51277   attribute \src "libresoc.v:35141.3-35177.6"
51278   wire $1\dec31_dec_sub28_inv_a[0:0]
51279   attribute \src "libresoc.v:35178.3-35214.6"
51280   wire $1\dec31_dec_sub28_inv_out[0:0]
51281   attribute \src "libresoc.v:35400.3-35436.6"
51282   wire $1\dec31_dec_sub28_is_32b[0:0]
51283   attribute \src "libresoc.v:34956.3-34992.6"
51284   wire width 4 $1\dec31_dec_sub28_ldst_len[3:0]
51285   attribute \src "libresoc.v:35474.3-35510.6"
51286   wire $1\dec31_dec_sub28_lk[0:0]
51287   attribute \src "libresoc.v:35696.3-35732.6"
51288   wire width 2 $1\dec31_dec_sub28_out_sel[1:0]
51289   attribute \src "libresoc.v:35030.3-35066.6"
51290   wire width 2 $1\dec31_dec_sub28_rc_sel[1:0]
51291   attribute \src "libresoc.v:35363.3-35399.6"
51292   wire $1\dec31_dec_sub28_rsrv[0:0]
51293   attribute \src "libresoc.v:35511.3-35547.6"
51294   wire $1\dec31_dec_sub28_sgl_pipe[0:0]
51295   attribute \src "libresoc.v:35437.3-35473.6"
51296   wire $1\dec31_dec_sub28_sgn[0:0]
51297   attribute \src "libresoc.v:35289.3-35325.6"
51298   wire $1\dec31_dec_sub28_sgn_ext[0:0]
51299   attribute \src "libresoc.v:34993.3-35029.6"
51300   wire width 2 $1\dec31_dec_sub28_upd[1:0]
51301   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51302   wire width 8 output 4 \dec31_dec_sub28_asmcode
51303   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51304   wire output 18 \dec31_dec_sub28_br
51305   attribute \enum_base_type "CRInSel"
51306   attribute \enum_value_000 "NONE"
51307   attribute \enum_value_001 "CR0"
51308   attribute \enum_value_010 "BI"
51309   attribute \enum_value_011 "BFA"
51310   attribute \enum_value_100 "BA_BB"
51311   attribute \enum_value_101 "BC"
51312   attribute \enum_value_110 "WHOLE_REG"
51313   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51314   wire width 3 output 9 \dec31_dec_sub28_cr_in
51315   attribute \enum_base_type "CROutSel"
51316   attribute \enum_value_000 "NONE"
51317   attribute \enum_value_001 "CR0"
51318   attribute \enum_value_010 "BF"
51319   attribute \enum_value_011 "BT"
51320   attribute \enum_value_100 "WHOLE_REG"
51321   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51322   wire width 3 output 10 \dec31_dec_sub28_cr_out
51323   attribute \enum_base_type "CryIn"
51324   attribute \enum_value_00 "ZERO"
51325   attribute \enum_value_01 "ONE"
51326   attribute \enum_value_10 "CA"
51327   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51328   wire width 2 output 14 \dec31_dec_sub28_cry_in
51329   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51330   wire output 17 \dec31_dec_sub28_cry_out
51331   attribute \enum_base_type "Form"
51332   attribute \enum_value_00000 "NONE"
51333   attribute \enum_value_00001 "I"
51334   attribute \enum_value_00010 "B"
51335   attribute \enum_value_00011 "SC"
51336   attribute \enum_value_00100 "D"
51337   attribute \enum_value_00101 "DS"
51338   attribute \enum_value_00110 "DQ"
51339   attribute \enum_value_00111 "DX"
51340   attribute \enum_value_01000 "X"
51341   attribute \enum_value_01001 "XL"
51342   attribute \enum_value_01010 "XFX"
51343   attribute \enum_value_01011 "XFL"
51344   attribute \enum_value_01100 "XX1"
51345   attribute \enum_value_01101 "XX2"
51346   attribute \enum_value_01110 "XX3"
51347   attribute \enum_value_01111 "XX4"
51348   attribute \enum_value_10000 "XS"
51349   attribute \enum_value_10001 "XO"
51350   attribute \enum_value_10010 "A"
51351   attribute \enum_value_10011 "M"
51352   attribute \enum_value_10100 "MD"
51353   attribute \enum_value_10101 "MDS"
51354   attribute \enum_value_10110 "VA"
51355   attribute \enum_value_10111 "VC"
51356   attribute \enum_value_11000 "VX"
51357   attribute \enum_value_11001 "EVX"
51358   attribute \enum_value_11010 "EVS"
51359   attribute \enum_value_11011 "Z22"
51360   attribute \enum_value_11100 "Z23"
51361   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51362   wire width 5 output 3 \dec31_dec_sub28_form
51363   attribute \enum_base_type "Function"
51364   attribute \enum_value_000000000000 "NONE"
51365   attribute \enum_value_000000000010 "ALU"
51366   attribute \enum_value_000000000100 "LDST"
51367   attribute \enum_value_000000001000 "SHIFT_ROT"
51368   attribute \enum_value_000000010000 "LOGICAL"
51369   attribute \enum_value_000000100000 "BRANCH"
51370   attribute \enum_value_000001000000 "CR"
51371   attribute \enum_value_000010000000 "TRAP"
51372   attribute \enum_value_000100000000 "MUL"
51373   attribute \enum_value_001000000000 "DIV"
51374   attribute \enum_value_010000000000 "SPR"
51375   attribute \enum_value_100000000000 "MMU"
51376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51377   wire width 12 output 1 \dec31_dec_sub28_function_unit
51378   attribute \enum_base_type "In1Sel"
51379   attribute \enum_value_000 "NONE"
51380   attribute \enum_value_001 "RA"
51381   attribute \enum_value_010 "RA_OR_ZERO"
51382   attribute \enum_value_011 "SPR"
51383   attribute \enum_value_100 "RS"
51384   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51385   wire width 3 output 5 \dec31_dec_sub28_in1_sel
51386   attribute \enum_base_type "In2Sel"
51387   attribute \enum_value_0000 "NONE"
51388   attribute \enum_value_0001 "RB"
51389   attribute \enum_value_0010 "CONST_UI"
51390   attribute \enum_value_0011 "CONST_SI"
51391   attribute \enum_value_0100 "CONST_UI_HI"
51392   attribute \enum_value_0101 "CONST_SI_HI"
51393   attribute \enum_value_0110 "CONST_LI"
51394   attribute \enum_value_0111 "CONST_BD"
51395   attribute \enum_value_1000 "CONST_DS"
51396   attribute \enum_value_1001 "CONST_M1"
51397   attribute \enum_value_1010 "CONST_SH"
51398   attribute \enum_value_1011 "CONST_SH32"
51399   attribute \enum_value_1100 "SPR"
51400   attribute \enum_value_1101 "RS"
51401   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51402   wire width 4 output 6 \dec31_dec_sub28_in2_sel
51403   attribute \enum_base_type "In3Sel"
51404   attribute \enum_value_00 "NONE"
51405   attribute \enum_value_01 "RS"
51406   attribute \enum_value_10 "RB"
51407   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51408   wire width 2 output 7 \dec31_dec_sub28_in3_sel
51409   attribute \enum_base_type "MicrOp"
51410   attribute \enum_value_0000000 "OP_ILLEGAL"
51411   attribute \enum_value_0000001 "OP_NOP"
51412   attribute \enum_value_0000010 "OP_ADD"
51413   attribute \enum_value_0000011 "OP_ADDPCIS"
51414   attribute \enum_value_0000100 "OP_AND"
51415   attribute \enum_value_0000101 "OP_ATTN"
51416   attribute \enum_value_0000110 "OP_B"
51417   attribute \enum_value_0000111 "OP_BC"
51418   attribute \enum_value_0001000 "OP_BCREG"
51419   attribute \enum_value_0001001 "OP_BPERM"
51420   attribute \enum_value_0001010 "OP_CMP"
51421   attribute \enum_value_0001011 "OP_CMPB"
51422   attribute \enum_value_0001100 "OP_CMPEQB"
51423   attribute \enum_value_0001101 "OP_CMPRB"
51424   attribute \enum_value_0001110 "OP_CNTZ"
51425   attribute \enum_value_0001111 "OP_CRAND"
51426   attribute \enum_value_0010000 "OP_CRANDC"
51427   attribute \enum_value_0010001 "OP_CREQV"
51428   attribute \enum_value_0010010 "OP_CRNAND"
51429   attribute \enum_value_0010011 "OP_CRNOR"
51430   attribute \enum_value_0010100 "OP_CROR"
51431   attribute \enum_value_0010101 "OP_CRORC"
51432   attribute \enum_value_0010110 "OP_CRXOR"
51433   attribute \enum_value_0010111 "OP_DARN"
51434   attribute \enum_value_0011000 "OP_DCBF"
51435   attribute \enum_value_0011001 "OP_DCBST"
51436   attribute \enum_value_0011010 "OP_DCBT"
51437   attribute \enum_value_0011011 "OP_DCBTST"
51438   attribute \enum_value_0011100 "OP_DCBZ"
51439   attribute \enum_value_0011101 "OP_DIV"
51440   attribute \enum_value_0011110 "OP_DIVE"
51441   attribute \enum_value_0011111 "OP_EXTS"
51442   attribute \enum_value_0100000 "OP_EXTSWSLI"
51443   attribute \enum_value_0100001 "OP_ICBI"
51444   attribute \enum_value_0100010 "OP_ICBT"
51445   attribute \enum_value_0100011 "OP_ISEL"
51446   attribute \enum_value_0100100 "OP_ISYNC"
51447   attribute \enum_value_0100101 "OP_LOAD"
51448   attribute \enum_value_0100110 "OP_STORE"
51449   attribute \enum_value_0100111 "OP_MADDHD"
51450   attribute \enum_value_0101000 "OP_MADDHDU"
51451   attribute \enum_value_0101001 "OP_MADDLD"
51452   attribute \enum_value_0101010 "OP_MCRF"
51453   attribute \enum_value_0101011 "OP_MCRXR"
51454   attribute \enum_value_0101100 "OP_MCRXRX"
51455   attribute \enum_value_0101101 "OP_MFCR"
51456   attribute \enum_value_0101110 "OP_MFSPR"
51457   attribute \enum_value_0101111 "OP_MOD"
51458   attribute \enum_value_0110000 "OP_MTCRF"
51459   attribute \enum_value_0110001 "OP_MTSPR"
51460   attribute \enum_value_0110010 "OP_MUL_L64"
51461   attribute \enum_value_0110011 "OP_MUL_H64"
51462   attribute \enum_value_0110100 "OP_MUL_H32"
51463   attribute \enum_value_0110101 "OP_OR"
51464   attribute \enum_value_0110110 "OP_POPCNT"
51465   attribute \enum_value_0110111 "OP_PRTY"
51466   attribute \enum_value_0111000 "OP_RLC"
51467   attribute \enum_value_0111001 "OP_RLCL"
51468   attribute \enum_value_0111010 "OP_RLCR"
51469   attribute \enum_value_0111011 "OP_SETB"
51470   attribute \enum_value_0111100 "OP_SHL"
51471   attribute \enum_value_0111101 "OP_SHR"
51472   attribute \enum_value_0111110 "OP_SYNC"
51473   attribute \enum_value_0111111 "OP_TRAP"
51474   attribute \enum_value_1000011 "OP_XOR"
51475   attribute \enum_value_1000100 "OP_SIM_CONFIG"
51476   attribute \enum_value_1000101 "OP_CROP"
51477   attribute \enum_value_1000110 "OP_RFID"
51478   attribute \enum_value_1000111 "OP_MFMSR"
51479   attribute \enum_value_1001000 "OP_MTMSRD"
51480   attribute \enum_value_1001001 "OP_SC"
51481   attribute \enum_value_1001010 "OP_MTMSR"
51482   attribute \enum_value_1001011 "OP_TLBIE"
51483   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51484   wire width 7 output 2 \dec31_dec_sub28_internal_op
51485   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51486   wire output 15 \dec31_dec_sub28_inv_a
51487   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51488   wire output 16 \dec31_dec_sub28_inv_out
51489   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51490   wire output 21 \dec31_dec_sub28_is_32b
51491   attribute \enum_base_type "LdstLen"
51492   attribute \enum_value_0000 "NONE"
51493   attribute \enum_value_0001 "is1B"
51494   attribute \enum_value_0010 "is2B"
51495   attribute \enum_value_0100 "is4B"
51496   attribute \enum_value_1000 "is8B"
51497   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51498   wire width 4 output 11 \dec31_dec_sub28_ldst_len
51499   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51500   wire output 23 \dec31_dec_sub28_lk
51501   attribute \enum_base_type "OutSel"
51502   attribute \enum_value_00 "NONE"
51503   attribute \enum_value_01 "RT"
51504   attribute \enum_value_10 "RA"
51505   attribute \enum_value_11 "SPR"
51506   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51507   wire width 2 output 8 \dec31_dec_sub28_out_sel
51508   attribute \enum_base_type "RC"
51509   attribute \enum_value_00 "NONE"
51510   attribute \enum_value_01 "ONE"
51511   attribute \enum_value_10 "RC"
51512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51513   wire width 2 output 13 \dec31_dec_sub28_rc_sel
51514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51515   wire output 20 \dec31_dec_sub28_rsrv
51516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51517   wire output 24 \dec31_dec_sub28_sgl_pipe
51518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51519   wire output 22 \dec31_dec_sub28_sgn
51520   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
51521   wire output 19 \dec31_dec_sub28_sgn_ext
51522   attribute \enum_base_type "LDSTMode"
51523   attribute \enum_value_00 "NONE"
51524   attribute \enum_value_01 "update"
51525   attribute \enum_value_10 "cix"
51526   attribute \enum_value_11 "cx"
51527   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
51528   wire width 2 output 12 \dec31_dec_sub28_upd
51529   attribute \src "libresoc.v:34662.7-34662.15"
51530   wire \initial
51531   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
51532   wire width 32 input 25 \opcode_in
51533   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
51534   wire width 5 \opcode_switch
51535   attribute \src "libresoc.v:34662.7-34662.20"
51536   process $proc$libresoc.v:34662$781
51537     assign { } { }
51538     assign $0\initial[0:0] 1'0
51539     sync always
51540       update \initial $0\initial[0:0]
51541     sync init
51542   end
51543   attribute \src "libresoc.v:34919.3-34955.6"
51544   process $proc$libresoc.v:34919$757
51545     assign { } { }
51546     assign { } { }
51547     assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0]
51548     attribute \src "libresoc.v:34920.5-34920.29"
51549     switch \initial
51550       attribute \src "libresoc.v:34920.9-34920.17"
51551       case 1'1
51552       case
51553     end
51554     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51555     switch \opcode_switch
51556       attribute \src "libresoc.v:0.0-0.0"
51557       case 5'00000
51558         assign { } { }
51559         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51560       attribute \src "libresoc.v:0.0-0.0"
51561       case 5'00001
51562         assign { } { }
51563         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51564       attribute \src "libresoc.v:0.0-0.0"
51565       case 5'00111
51566         assign { } { }
51567         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51568       attribute \src "libresoc.v:0.0-0.0"
51569       case 5'01111
51570         assign { } { }
51571         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51572       attribute \src "libresoc.v:0.0-0.0"
51573       case 5'01000
51574         assign { } { }
51575         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51576       attribute \src "libresoc.v:0.0-0.0"
51577       case 5'01110
51578         assign { } { }
51579         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51580       attribute \src "libresoc.v:0.0-0.0"
51581       case 5'00011
51582         assign { } { }
51583         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51584       attribute \src "libresoc.v:0.0-0.0"
51585       case 5'01101
51586         assign { } { }
51587         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51588       attribute \src "libresoc.v:0.0-0.0"
51589       case 5'01100
51590         assign { } { }
51591         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51592       attribute \src "libresoc.v:0.0-0.0"
51593       case 5'01001
51594         assign { } { }
51595         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000
51596       case
51597         assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000
51598     end
51599     sync always
51600       update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0]
51601   end
51602   attribute \src "libresoc.v:34956.3-34992.6"
51603   process $proc$libresoc.v:34956$758
51604     assign { } { }
51605     assign { } { }
51606     assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0]
51607     attribute \src "libresoc.v:34957.5-34957.29"
51608     switch \initial
51609       attribute \src "libresoc.v:34957.9-34957.17"
51610       case 1'1
51611       case
51612     end
51613     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51614     switch \opcode_switch
51615       attribute \src "libresoc.v:0.0-0.0"
51616       case 5'00000
51617         assign { } { }
51618         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51619       attribute \src "libresoc.v:0.0-0.0"
51620       case 5'00001
51621         assign { } { }
51622         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51623       attribute \src "libresoc.v:0.0-0.0"
51624       case 5'00111
51625         assign { } { }
51626         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51627       attribute \src "libresoc.v:0.0-0.0"
51628       case 5'01111
51629         assign { } { }
51630         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51631       attribute \src "libresoc.v:0.0-0.0"
51632       case 5'01000
51633         assign { } { }
51634         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51635       attribute \src "libresoc.v:0.0-0.0"
51636       case 5'01110
51637         assign { } { }
51638         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51639       attribute \src "libresoc.v:0.0-0.0"
51640       case 5'00011
51641         assign { } { }
51642         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51643       attribute \src "libresoc.v:0.0-0.0"
51644       case 5'01101
51645         assign { } { }
51646         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51647       attribute \src "libresoc.v:0.0-0.0"
51648       case 5'01100
51649         assign { } { }
51650         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51651       attribute \src "libresoc.v:0.0-0.0"
51652       case 5'01001
51653         assign { } { }
51654         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51655       case
51656         assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000
51657     end
51658     sync always
51659       update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0]
51660   end
51661   attribute \src "libresoc.v:34993.3-35029.6"
51662   process $proc$libresoc.v:34993$759
51663     assign { } { }
51664     assign { } { }
51665     assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0]
51666     attribute \src "libresoc.v:34994.5-34994.29"
51667     switch \initial
51668       attribute \src "libresoc.v:34994.9-34994.17"
51669       case 1'1
51670       case
51671     end
51672     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51673     switch \opcode_switch
51674       attribute \src "libresoc.v:0.0-0.0"
51675       case 5'00000
51676         assign { } { }
51677         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51678       attribute \src "libresoc.v:0.0-0.0"
51679       case 5'00001
51680         assign { } { }
51681         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51682       attribute \src "libresoc.v:0.0-0.0"
51683       case 5'00111
51684         assign { } { }
51685         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51686       attribute \src "libresoc.v:0.0-0.0"
51687       case 5'01111
51688         assign { } { }
51689         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51690       attribute \src "libresoc.v:0.0-0.0"
51691       case 5'01000
51692         assign { } { }
51693         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51694       attribute \src "libresoc.v:0.0-0.0"
51695       case 5'01110
51696         assign { } { }
51697         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51698       attribute \src "libresoc.v:0.0-0.0"
51699       case 5'00011
51700         assign { } { }
51701         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51702       attribute \src "libresoc.v:0.0-0.0"
51703       case 5'01101
51704         assign { } { }
51705         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51706       attribute \src "libresoc.v:0.0-0.0"
51707       case 5'01100
51708         assign { } { }
51709         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51710       attribute \src "libresoc.v:0.0-0.0"
51711       case 5'01001
51712         assign { } { }
51713         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51714       case
51715         assign $1\dec31_dec_sub28_upd[1:0] 2'00
51716     end
51717     sync always
51718       update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0]
51719   end
51720   attribute \src "libresoc.v:35030.3-35066.6"
51721   process $proc$libresoc.v:35030$760
51722     assign { } { }
51723     assign { } { }
51724     assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0]
51725     attribute \src "libresoc.v:35031.5-35031.29"
51726     switch \initial
51727       attribute \src "libresoc.v:35031.9-35031.17"
51728       case 1'1
51729       case
51730     end
51731     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51732     switch \opcode_switch
51733       attribute \src "libresoc.v:0.0-0.0"
51734       case 5'00000
51735         assign { } { }
51736         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51737       attribute \src "libresoc.v:0.0-0.0"
51738       case 5'00001
51739         assign { } { }
51740         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51741       attribute \src "libresoc.v:0.0-0.0"
51742       case 5'00111
51743         assign { } { }
51744         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00
51745       attribute \src "libresoc.v:0.0-0.0"
51746       case 5'01111
51747         assign { } { }
51748         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00
51749       attribute \src "libresoc.v:0.0-0.0"
51750       case 5'01000
51751         assign { } { }
51752         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51753       attribute \src "libresoc.v:0.0-0.0"
51754       case 5'01110
51755         assign { } { }
51756         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51757       attribute \src "libresoc.v:0.0-0.0"
51758       case 5'00011
51759         assign { } { }
51760         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51761       attribute \src "libresoc.v:0.0-0.0"
51762       case 5'01101
51763         assign { } { }
51764         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51765       attribute \src "libresoc.v:0.0-0.0"
51766       case 5'01100
51767         assign { } { }
51768         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51769       attribute \src "libresoc.v:0.0-0.0"
51770       case 5'01001
51771         assign { } { }
51772         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10
51773       case
51774         assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00
51775     end
51776     sync always
51777       update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0]
51778   end
51779   attribute \src "libresoc.v:35067.3-35103.6"
51780   process $proc$libresoc.v:35067$761
51781     assign { } { }
51782     assign { } { }
51783     assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0]
51784     attribute \src "libresoc.v:35068.5-35068.29"
51785     switch \initial
51786       attribute \src "libresoc.v:35068.9-35068.17"
51787       case 1'1
51788       case
51789     end
51790     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51791     switch \opcode_switch
51792       attribute \src "libresoc.v:0.0-0.0"
51793       case 5'00000
51794         assign { } { }
51795         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51796       attribute \src "libresoc.v:0.0-0.0"
51797       case 5'00001
51798         assign { } { }
51799         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51800       attribute \src "libresoc.v:0.0-0.0"
51801       case 5'00111
51802         assign { } { }
51803         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51804       attribute \src "libresoc.v:0.0-0.0"
51805       case 5'01111
51806         assign { } { }
51807         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51808       attribute \src "libresoc.v:0.0-0.0"
51809       case 5'01000
51810         assign { } { }
51811         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51812       attribute \src "libresoc.v:0.0-0.0"
51813       case 5'01110
51814         assign { } { }
51815         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51816       attribute \src "libresoc.v:0.0-0.0"
51817       case 5'00011
51818         assign { } { }
51819         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51820       attribute \src "libresoc.v:0.0-0.0"
51821       case 5'01101
51822         assign { } { }
51823         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51824       attribute \src "libresoc.v:0.0-0.0"
51825       case 5'01100
51826         assign { } { }
51827         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51828       attribute \src "libresoc.v:0.0-0.0"
51829       case 5'01001
51830         assign { } { }
51831         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51832       case
51833         assign $1\dec31_dec_sub28_cry_in[1:0] 2'00
51834     end
51835     sync always
51836       update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0]
51837   end
51838   attribute \src "libresoc.v:35104.3-35140.6"
51839   process $proc$libresoc.v:35104$762
51840     assign { } { }
51841     assign { } { }
51842     assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0]
51843     attribute \src "libresoc.v:35105.5-35105.29"
51844     switch \initial
51845       attribute \src "libresoc.v:35105.9-35105.17"
51846       case 1'1
51847       case
51848     end
51849     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51850     switch \opcode_switch
51851       attribute \src "libresoc.v:0.0-0.0"
51852       case 5'00000
51853         assign { } { }
51854         assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111
51855       attribute \src "libresoc.v:0.0-0.0"
51856       case 5'00001
51857         assign { } { }
51858         assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000
51859       attribute \src "libresoc.v:0.0-0.0"
51860       case 5'00111
51861         assign { } { }
51862         assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001
51863       attribute \src "libresoc.v:0.0-0.0"
51864       case 5'01111
51865         assign { } { }
51866         assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011
51867       attribute \src "libresoc.v:0.0-0.0"
51868       case 5'01000
51869         assign { } { }
51870         assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011
51871       attribute \src "libresoc.v:0.0-0.0"
51872       case 5'01110
51873         assign { } { }
51874         assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011
51875       attribute \src "libresoc.v:0.0-0.0"
51876       case 5'00011
51877         assign { } { }
51878         assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111
51879       attribute \src "libresoc.v:0.0-0.0"
51880       case 5'01101
51881         assign { } { }
51882         assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000
51883       attribute \src "libresoc.v:0.0-0.0"
51884       case 5'01100
51885         assign { } { }
51886         assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001
51887       attribute \src "libresoc.v:0.0-0.0"
51888       case 5'01001
51889         assign { } { }
51890         assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000
51891       case
51892         assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000
51893     end
51894     sync always
51895       update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0]
51896   end
51897   attribute \src "libresoc.v:35141.3-35177.6"
51898   process $proc$libresoc.v:35141$763
51899     assign { } { }
51900     assign { } { }
51901     assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0]
51902     attribute \src "libresoc.v:35142.5-35142.29"
51903     switch \initial
51904       attribute \src "libresoc.v:35142.9-35142.17"
51905       case 1'1
51906       case
51907     end
51908     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51909     switch \opcode_switch
51910       attribute \src "libresoc.v:0.0-0.0"
51911       case 5'00000
51912         assign { } { }
51913         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51914       attribute \src "libresoc.v:0.0-0.0"
51915       case 5'00001
51916         assign { } { }
51917         assign $1\dec31_dec_sub28_inv_a[0:0] 1'1
51918       attribute \src "libresoc.v:0.0-0.0"
51919       case 5'00111
51920         assign { } { }
51921         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51922       attribute \src "libresoc.v:0.0-0.0"
51923       case 5'01111
51924         assign { } { }
51925         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51926       attribute \src "libresoc.v:0.0-0.0"
51927       case 5'01000
51928         assign { } { }
51929         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51930       attribute \src "libresoc.v:0.0-0.0"
51931       case 5'01110
51932         assign { } { }
51933         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51934       attribute \src "libresoc.v:0.0-0.0"
51935       case 5'00011
51936         assign { } { }
51937         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51938       attribute \src "libresoc.v:0.0-0.0"
51939       case 5'01101
51940         assign { } { }
51941         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51942       attribute \src "libresoc.v:0.0-0.0"
51943       case 5'01100
51944         assign { } { }
51945         assign $1\dec31_dec_sub28_inv_a[0:0] 1'1
51946       attribute \src "libresoc.v:0.0-0.0"
51947       case 5'01001
51948         assign { } { }
51949         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51950       case
51951         assign $1\dec31_dec_sub28_inv_a[0:0] 1'0
51952     end
51953     sync always
51954       update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0]
51955   end
51956   attribute \src "libresoc.v:35178.3-35214.6"
51957   process $proc$libresoc.v:35178$764
51958     assign { } { }
51959     assign { } { }
51960     assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0]
51961     attribute \src "libresoc.v:35179.5-35179.29"
51962     switch \initial
51963       attribute \src "libresoc.v:35179.9-35179.17"
51964       case 1'1
51965       case
51966     end
51967     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
51968     switch \opcode_switch
51969       attribute \src "libresoc.v:0.0-0.0"
51970       case 5'00000
51971         assign { } { }
51972         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
51973       attribute \src "libresoc.v:0.0-0.0"
51974       case 5'00001
51975         assign { } { }
51976         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
51977       attribute \src "libresoc.v:0.0-0.0"
51978       case 5'00111
51979         assign { } { }
51980         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
51981       attribute \src "libresoc.v:0.0-0.0"
51982       case 5'01111
51983         assign { } { }
51984         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
51985       attribute \src "libresoc.v:0.0-0.0"
51986       case 5'01000
51987         assign { } { }
51988         assign $1\dec31_dec_sub28_inv_out[0:0] 1'1
51989       attribute \src "libresoc.v:0.0-0.0"
51990       case 5'01110
51991         assign { } { }
51992         assign $1\dec31_dec_sub28_inv_out[0:0] 1'1
51993       attribute \src "libresoc.v:0.0-0.0"
51994       case 5'00011
51995         assign { } { }
51996         assign $1\dec31_dec_sub28_inv_out[0:0] 1'1
51997       attribute \src "libresoc.v:0.0-0.0"
51998       case 5'01101
51999         assign { } { }
52000         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
52001       attribute \src "libresoc.v:0.0-0.0"
52002       case 5'01100
52003         assign { } { }
52004         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
52005       attribute \src "libresoc.v:0.0-0.0"
52006       case 5'01001
52007         assign { } { }
52008         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
52009       case
52010         assign $1\dec31_dec_sub28_inv_out[0:0] 1'0
52011     end
52012     sync always
52013       update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0]
52014   end
52015   attribute \src "libresoc.v:35215.3-35251.6"
52016   process $proc$libresoc.v:35215$765
52017     assign { } { }
52018     assign { } { }
52019     assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0]
52020     attribute \src "libresoc.v:35216.5-35216.29"
52021     switch \initial
52022       attribute \src "libresoc.v:35216.9-35216.17"
52023       case 1'1
52024       case
52025     end
52026     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52027     switch \opcode_switch
52028       attribute \src "libresoc.v:0.0-0.0"
52029       case 5'00000
52030         assign { } { }
52031         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52032       attribute \src "libresoc.v:0.0-0.0"
52033       case 5'00001
52034         assign { } { }
52035         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52036       attribute \src "libresoc.v:0.0-0.0"
52037       case 5'00111
52038         assign { } { }
52039         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52040       attribute \src "libresoc.v:0.0-0.0"
52041       case 5'01111
52042         assign { } { }
52043         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52044       attribute \src "libresoc.v:0.0-0.0"
52045       case 5'01000
52046         assign { } { }
52047         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52048       attribute \src "libresoc.v:0.0-0.0"
52049       case 5'01110
52050         assign { } { }
52051         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52052       attribute \src "libresoc.v:0.0-0.0"
52053       case 5'00011
52054         assign { } { }
52055         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52056       attribute \src "libresoc.v:0.0-0.0"
52057       case 5'01101
52058         assign { } { }
52059         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52060       attribute \src "libresoc.v:0.0-0.0"
52061       case 5'01100
52062         assign { } { }
52063         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52064       attribute \src "libresoc.v:0.0-0.0"
52065       case 5'01001
52066         assign { } { }
52067         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52068       case
52069         assign $1\dec31_dec_sub28_cry_out[0:0] 1'0
52070     end
52071     sync always
52072       update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0]
52073   end
52074   attribute \src "libresoc.v:35252.3-35288.6"
52075   process $proc$libresoc.v:35252$766
52076     assign { } { }
52077     assign { } { }
52078     assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0]
52079     attribute \src "libresoc.v:35253.5-35253.29"
52080     switch \initial
52081       attribute \src "libresoc.v:35253.9-35253.17"
52082       case 1'1
52083       case
52084     end
52085     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52086     switch \opcode_switch
52087       attribute \src "libresoc.v:0.0-0.0"
52088       case 5'00000
52089         assign { } { }
52090         assign $1\dec31_dec_sub28_br[0:0] 1'0
52091       attribute \src "libresoc.v:0.0-0.0"
52092       case 5'00001
52093         assign { } { }
52094         assign $1\dec31_dec_sub28_br[0:0] 1'0
52095       attribute \src "libresoc.v:0.0-0.0"
52096       case 5'00111
52097         assign { } { }
52098         assign $1\dec31_dec_sub28_br[0:0] 1'0
52099       attribute \src "libresoc.v:0.0-0.0"
52100       case 5'01111
52101         assign { } { }
52102         assign $1\dec31_dec_sub28_br[0:0] 1'0
52103       attribute \src "libresoc.v:0.0-0.0"
52104       case 5'01000
52105         assign { } { }
52106         assign $1\dec31_dec_sub28_br[0:0] 1'0
52107       attribute \src "libresoc.v:0.0-0.0"
52108       case 5'01110
52109         assign { } { }
52110         assign $1\dec31_dec_sub28_br[0:0] 1'0
52111       attribute \src "libresoc.v:0.0-0.0"
52112       case 5'00011
52113         assign { } { }
52114         assign $1\dec31_dec_sub28_br[0:0] 1'0
52115       attribute \src "libresoc.v:0.0-0.0"
52116       case 5'01101
52117         assign { } { }
52118         assign $1\dec31_dec_sub28_br[0:0] 1'0
52119       attribute \src "libresoc.v:0.0-0.0"
52120       case 5'01100
52121         assign { } { }
52122         assign $1\dec31_dec_sub28_br[0:0] 1'0
52123       attribute \src "libresoc.v:0.0-0.0"
52124       case 5'01001
52125         assign { } { }
52126         assign $1\dec31_dec_sub28_br[0:0] 1'0
52127       case
52128         assign $1\dec31_dec_sub28_br[0:0] 1'0
52129     end
52130     sync always
52131       update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0]
52132   end
52133   attribute \src "libresoc.v:35289.3-35325.6"
52134   process $proc$libresoc.v:35289$767
52135     assign { } { }
52136     assign { } { }
52137     assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0]
52138     attribute \src "libresoc.v:35290.5-35290.29"
52139     switch \initial
52140       attribute \src "libresoc.v:35290.9-35290.17"
52141       case 1'1
52142       case
52143     end
52144     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52145     switch \opcode_switch
52146       attribute \src "libresoc.v:0.0-0.0"
52147       case 5'00000
52148         assign { } { }
52149         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52150       attribute \src "libresoc.v:0.0-0.0"
52151       case 5'00001
52152         assign { } { }
52153         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52154       attribute \src "libresoc.v:0.0-0.0"
52155       case 5'00111
52156         assign { } { }
52157         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52158       attribute \src "libresoc.v:0.0-0.0"
52159       case 5'01111
52160         assign { } { }
52161         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52162       attribute \src "libresoc.v:0.0-0.0"
52163       case 5'01000
52164         assign { } { }
52165         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52166       attribute \src "libresoc.v:0.0-0.0"
52167       case 5'01110
52168         assign { } { }
52169         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52170       attribute \src "libresoc.v:0.0-0.0"
52171       case 5'00011
52172         assign { } { }
52173         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52174       attribute \src "libresoc.v:0.0-0.0"
52175       case 5'01101
52176         assign { } { }
52177         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52178       attribute \src "libresoc.v:0.0-0.0"
52179       case 5'01100
52180         assign { } { }
52181         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52182       attribute \src "libresoc.v:0.0-0.0"
52183       case 5'01001
52184         assign { } { }
52185         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52186       case
52187         assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0
52188     end
52189     sync always
52190       update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0]
52191   end
52192   attribute \src "libresoc.v:35326.3-35362.6"
52193   process $proc$libresoc.v:35326$768
52194     assign { } { }
52195     assign { } { }
52196     assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0]
52197     attribute \src "libresoc.v:35327.5-35327.29"
52198     switch \initial
52199       attribute \src "libresoc.v:35327.9-35327.17"
52200       case 1'1
52201       case
52202     end
52203     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52204     switch \opcode_switch
52205       attribute \src "libresoc.v:0.0-0.0"
52206       case 5'00000
52207         assign { } { }
52208         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100
52209       attribute \src "libresoc.v:0.0-0.0"
52210       case 5'00001
52211         assign { } { }
52212         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100
52213       attribute \src "libresoc.v:0.0-0.0"
52214       case 5'00111
52215         assign { } { }
52216         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001
52217       attribute \src "libresoc.v:0.0-0.0"
52218       case 5'01111
52219         assign { } { }
52220         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011
52221       attribute \src "libresoc.v:0.0-0.0"
52222       case 5'01000
52223         assign { } { }
52224         assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011
52225       attribute \src "libresoc.v:0.0-0.0"
52226       case 5'01110
52227         assign { } { }
52228         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100
52229       attribute \src "libresoc.v:0.0-0.0"
52230       case 5'00011
52231         assign { } { }
52232         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101
52233       attribute \src "libresoc.v:0.0-0.0"
52234       case 5'01101
52235         assign { } { }
52236         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101
52237       attribute \src "libresoc.v:0.0-0.0"
52238       case 5'01100
52239         assign { } { }
52240         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101
52241       attribute \src "libresoc.v:0.0-0.0"
52242       case 5'01001
52243         assign { } { }
52244         assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011
52245       case
52246         assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000
52247     end
52248     sync always
52249       update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0]
52250   end
52251   attribute \src "libresoc.v:35363.3-35399.6"
52252   process $proc$libresoc.v:35363$769
52253     assign { } { }
52254     assign { } { }
52255     assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0]
52256     attribute \src "libresoc.v:35364.5-35364.29"
52257     switch \initial
52258       attribute \src "libresoc.v:35364.9-35364.17"
52259       case 1'1
52260       case
52261     end
52262     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52263     switch \opcode_switch
52264       attribute \src "libresoc.v:0.0-0.0"
52265       case 5'00000
52266         assign { } { }
52267         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52268       attribute \src "libresoc.v:0.0-0.0"
52269       case 5'00001
52270         assign { } { }
52271         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52272       attribute \src "libresoc.v:0.0-0.0"
52273       case 5'00111
52274         assign { } { }
52275         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52276       attribute \src "libresoc.v:0.0-0.0"
52277       case 5'01111
52278         assign { } { }
52279         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52280       attribute \src "libresoc.v:0.0-0.0"
52281       case 5'01000
52282         assign { } { }
52283         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52284       attribute \src "libresoc.v:0.0-0.0"
52285       case 5'01110
52286         assign { } { }
52287         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52288       attribute \src "libresoc.v:0.0-0.0"
52289       case 5'00011
52290         assign { } { }
52291         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52292       attribute \src "libresoc.v:0.0-0.0"
52293       case 5'01101
52294         assign { } { }
52295         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52296       attribute \src "libresoc.v:0.0-0.0"
52297       case 5'01100
52298         assign { } { }
52299         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52300       attribute \src "libresoc.v:0.0-0.0"
52301       case 5'01001
52302         assign { } { }
52303         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52304       case
52305         assign $1\dec31_dec_sub28_rsrv[0:0] 1'0
52306     end
52307     sync always
52308       update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0]
52309   end
52310   attribute \src "libresoc.v:35400.3-35436.6"
52311   process $proc$libresoc.v:35400$770
52312     assign { } { }
52313     assign { } { }
52314     assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0]
52315     attribute \src "libresoc.v:35401.5-35401.29"
52316     switch \initial
52317       attribute \src "libresoc.v:35401.9-35401.17"
52318       case 1'1
52319       case
52320     end
52321     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52322     switch \opcode_switch
52323       attribute \src "libresoc.v:0.0-0.0"
52324       case 5'00000
52325         assign { } { }
52326         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52327       attribute \src "libresoc.v:0.0-0.0"
52328       case 5'00001
52329         assign { } { }
52330         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52331       attribute \src "libresoc.v:0.0-0.0"
52332       case 5'00111
52333         assign { } { }
52334         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52335       attribute \src "libresoc.v:0.0-0.0"
52336       case 5'01111
52337         assign { } { }
52338         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52339       attribute \src "libresoc.v:0.0-0.0"
52340       case 5'01000
52341         assign { } { }
52342         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52343       attribute \src "libresoc.v:0.0-0.0"
52344       case 5'01110
52345         assign { } { }
52346         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52347       attribute \src "libresoc.v:0.0-0.0"
52348       case 5'00011
52349         assign { } { }
52350         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52351       attribute \src "libresoc.v:0.0-0.0"
52352       case 5'01101
52353         assign { } { }
52354         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52355       attribute \src "libresoc.v:0.0-0.0"
52356       case 5'01100
52357         assign { } { }
52358         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52359       attribute \src "libresoc.v:0.0-0.0"
52360       case 5'01001
52361         assign { } { }
52362         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52363       case
52364         assign $1\dec31_dec_sub28_is_32b[0:0] 1'0
52365     end
52366     sync always
52367       update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0]
52368   end
52369   attribute \src "libresoc.v:35437.3-35473.6"
52370   process $proc$libresoc.v:35437$771
52371     assign { } { }
52372     assign { } { }
52373     assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0]
52374     attribute \src "libresoc.v:35438.5-35438.29"
52375     switch \initial
52376       attribute \src "libresoc.v:35438.9-35438.17"
52377       case 1'1
52378       case
52379     end
52380     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52381     switch \opcode_switch
52382       attribute \src "libresoc.v:0.0-0.0"
52383       case 5'00000
52384         assign { } { }
52385         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52386       attribute \src "libresoc.v:0.0-0.0"
52387       case 5'00001
52388         assign { } { }
52389         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52390       attribute \src "libresoc.v:0.0-0.0"
52391       case 5'00111
52392         assign { } { }
52393         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52394       attribute \src "libresoc.v:0.0-0.0"
52395       case 5'01111
52396         assign { } { }
52397         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52398       attribute \src "libresoc.v:0.0-0.0"
52399       case 5'01000
52400         assign { } { }
52401         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52402       attribute \src "libresoc.v:0.0-0.0"
52403       case 5'01110
52404         assign { } { }
52405         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52406       attribute \src "libresoc.v:0.0-0.0"
52407       case 5'00011
52408         assign { } { }
52409         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52410       attribute \src "libresoc.v:0.0-0.0"
52411       case 5'01101
52412         assign { } { }
52413         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52414       attribute \src "libresoc.v:0.0-0.0"
52415       case 5'01100
52416         assign { } { }
52417         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52418       attribute \src "libresoc.v:0.0-0.0"
52419       case 5'01001
52420         assign { } { }
52421         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52422       case
52423         assign $1\dec31_dec_sub28_sgn[0:0] 1'0
52424     end
52425     sync always
52426       update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0]
52427   end
52428   attribute \src "libresoc.v:35474.3-35510.6"
52429   process $proc$libresoc.v:35474$772
52430     assign { } { }
52431     assign { } { }
52432     assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0]
52433     attribute \src "libresoc.v:35475.5-35475.29"
52434     switch \initial
52435       attribute \src "libresoc.v:35475.9-35475.17"
52436       case 1'1
52437       case
52438     end
52439     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52440     switch \opcode_switch
52441       attribute \src "libresoc.v:0.0-0.0"
52442       case 5'00000
52443         assign { } { }
52444         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52445       attribute \src "libresoc.v:0.0-0.0"
52446       case 5'00001
52447         assign { } { }
52448         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52449       attribute \src "libresoc.v:0.0-0.0"
52450       case 5'00111
52451         assign { } { }
52452         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52453       attribute \src "libresoc.v:0.0-0.0"
52454       case 5'01111
52455         assign { } { }
52456         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52457       attribute \src "libresoc.v:0.0-0.0"
52458       case 5'01000
52459         assign { } { }
52460         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52461       attribute \src "libresoc.v:0.0-0.0"
52462       case 5'01110
52463         assign { } { }
52464         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52465       attribute \src "libresoc.v:0.0-0.0"
52466       case 5'00011
52467         assign { } { }
52468         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52469       attribute \src "libresoc.v:0.0-0.0"
52470       case 5'01101
52471         assign { } { }
52472         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52473       attribute \src "libresoc.v:0.0-0.0"
52474       case 5'01100
52475         assign { } { }
52476         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52477       attribute \src "libresoc.v:0.0-0.0"
52478       case 5'01001
52479         assign { } { }
52480         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52481       case
52482         assign $1\dec31_dec_sub28_lk[0:0] 1'0
52483     end
52484     sync always
52485       update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0]
52486   end
52487   attribute \src "libresoc.v:35511.3-35547.6"
52488   process $proc$libresoc.v:35511$773
52489     assign { } { }
52490     assign { } { }
52491     assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0]
52492     attribute \src "libresoc.v:35512.5-35512.29"
52493     switch \initial
52494       attribute \src "libresoc.v:35512.9-35512.17"
52495       case 1'1
52496       case
52497     end
52498     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52499     switch \opcode_switch
52500       attribute \src "libresoc.v:0.0-0.0"
52501       case 5'00000
52502         assign { } { }
52503         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52504       attribute \src "libresoc.v:0.0-0.0"
52505       case 5'00001
52506         assign { } { }
52507         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52508       attribute \src "libresoc.v:0.0-0.0"
52509       case 5'00111
52510         assign { } { }
52511         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52512       attribute \src "libresoc.v:0.0-0.0"
52513       case 5'01111
52514         assign { } { }
52515         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52516       attribute \src "libresoc.v:0.0-0.0"
52517       case 5'01000
52518         assign { } { }
52519         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52520       attribute \src "libresoc.v:0.0-0.0"
52521       case 5'01110
52522         assign { } { }
52523         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52524       attribute \src "libresoc.v:0.0-0.0"
52525       case 5'00011
52526         assign { } { }
52527         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52528       attribute \src "libresoc.v:0.0-0.0"
52529       case 5'01101
52530         assign { } { }
52531         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52532       attribute \src "libresoc.v:0.0-0.0"
52533       case 5'01100
52534         assign { } { }
52535         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52536       attribute \src "libresoc.v:0.0-0.0"
52537       case 5'01001
52538         assign { } { }
52539         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52540       case
52541         assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0
52542     end
52543     sync always
52544       update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0]
52545   end
52546   attribute \src "libresoc.v:35548.3-35584.6"
52547   process $proc$libresoc.v:35548$774
52548     assign { } { }
52549     assign { } { }
52550     assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0]
52551     attribute \src "libresoc.v:35549.5-35549.29"
52552     switch \initial
52553       attribute \src "libresoc.v:35549.9-35549.17"
52554       case 1'1
52555       case
52556     end
52557     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52558     switch \opcode_switch
52559       attribute \src "libresoc.v:0.0-0.0"
52560       case 5'00000
52561         assign { } { }
52562         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52563       attribute \src "libresoc.v:0.0-0.0"
52564       case 5'00001
52565         assign { } { }
52566         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52567       attribute \src "libresoc.v:0.0-0.0"
52568       case 5'00111
52569         assign { } { }
52570         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52571       attribute \src "libresoc.v:0.0-0.0"
52572       case 5'01111
52573         assign { } { }
52574         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52575       attribute \src "libresoc.v:0.0-0.0"
52576       case 5'01000
52577         assign { } { }
52578         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52579       attribute \src "libresoc.v:0.0-0.0"
52580       case 5'01110
52581         assign { } { }
52582         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52583       attribute \src "libresoc.v:0.0-0.0"
52584       case 5'00011
52585         assign { } { }
52586         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52587       attribute \src "libresoc.v:0.0-0.0"
52588       case 5'01101
52589         assign { } { }
52590         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52591       attribute \src "libresoc.v:0.0-0.0"
52592       case 5'01100
52593         assign { } { }
52594         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52595       attribute \src "libresoc.v:0.0-0.0"
52596       case 5'01001
52597         assign { } { }
52598         assign $1\dec31_dec_sub28_form[4:0] 5'01000
52599       case
52600         assign $1\dec31_dec_sub28_form[4:0] 5'00000
52601     end
52602     sync always
52603       update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0]
52604   end
52605   attribute \src "libresoc.v:35585.3-35621.6"
52606   process $proc$libresoc.v:35585$775
52607     assign { } { }
52608     assign { } { }
52609     assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0]
52610     attribute \src "libresoc.v:35586.5-35586.29"
52611     switch \initial
52612       attribute \src "libresoc.v:35586.9-35586.17"
52613       case 1'1
52614       case
52615     end
52616     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52617     switch \opcode_switch
52618       attribute \src "libresoc.v:0.0-0.0"
52619       case 5'00000
52620         assign { } { }
52621         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52622       attribute \src "libresoc.v:0.0-0.0"
52623       case 5'00001
52624         assign { } { }
52625         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52626       attribute \src "libresoc.v:0.0-0.0"
52627       case 5'00111
52628         assign { } { }
52629         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52630       attribute \src "libresoc.v:0.0-0.0"
52631       case 5'01111
52632         assign { } { }
52633         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52634       attribute \src "libresoc.v:0.0-0.0"
52635       case 5'01000
52636         assign { } { }
52637         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52638       attribute \src "libresoc.v:0.0-0.0"
52639       case 5'01110
52640         assign { } { }
52641         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52642       attribute \src "libresoc.v:0.0-0.0"
52643       case 5'00011
52644         assign { } { }
52645         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52646       attribute \src "libresoc.v:0.0-0.0"
52647       case 5'01101
52648         assign { } { }
52649         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52650       attribute \src "libresoc.v:0.0-0.0"
52651       case 5'01100
52652         assign { } { }
52653         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52654       attribute \src "libresoc.v:0.0-0.0"
52655       case 5'01001
52656         assign { } { }
52657         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100
52658       case
52659         assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000
52660     end
52661     sync always
52662       update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0]
52663   end
52664   attribute \src "libresoc.v:35622.3-35658.6"
52665   process $proc$libresoc.v:35622$776
52666     assign { } { }
52667     assign { } { }
52668     assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0]
52669     attribute \src "libresoc.v:35623.5-35623.29"
52670     switch \initial
52671       attribute \src "libresoc.v:35623.9-35623.17"
52672       case 1'1
52673       case
52674     end
52675     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52676     switch \opcode_switch
52677       attribute \src "libresoc.v:0.0-0.0"
52678       case 5'00000
52679         assign { } { }
52680         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52681       attribute \src "libresoc.v:0.0-0.0"
52682       case 5'00001
52683         assign { } { }
52684         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52685       attribute \src "libresoc.v:0.0-0.0"
52686       case 5'00111
52687         assign { } { }
52688         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52689       attribute \src "libresoc.v:0.0-0.0"
52690       case 5'01111
52691         assign { } { }
52692         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52693       attribute \src "libresoc.v:0.0-0.0"
52694       case 5'01000
52695         assign { } { }
52696         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52697       attribute \src "libresoc.v:0.0-0.0"
52698       case 5'01110
52699         assign { } { }
52700         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52701       attribute \src "libresoc.v:0.0-0.0"
52702       case 5'00011
52703         assign { } { }
52704         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52705       attribute \src "libresoc.v:0.0-0.0"
52706       case 5'01101
52707         assign { } { }
52708         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52709       attribute \src "libresoc.v:0.0-0.0"
52710       case 5'01100
52711         assign { } { }
52712         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52713       attribute \src "libresoc.v:0.0-0.0"
52714       case 5'01001
52715         assign { } { }
52716         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001
52717       case
52718         assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000
52719     end
52720     sync always
52721       update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0]
52722   end
52723   attribute \src "libresoc.v:35659.3-35695.6"
52724   process $proc$libresoc.v:35659$777
52725     assign { } { }
52726     assign { } { }
52727     assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0]
52728     attribute \src "libresoc.v:35660.5-35660.29"
52729     switch \initial
52730       attribute \src "libresoc.v:35660.9-35660.17"
52731       case 1'1
52732       case
52733     end
52734     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52735     switch \opcode_switch
52736       attribute \src "libresoc.v:0.0-0.0"
52737       case 5'00000
52738         assign { } { }
52739         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52740       attribute \src "libresoc.v:0.0-0.0"
52741       case 5'00001
52742         assign { } { }
52743         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52744       attribute \src "libresoc.v:0.0-0.0"
52745       case 5'00111
52746         assign { } { }
52747         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52748       attribute \src "libresoc.v:0.0-0.0"
52749       case 5'01111
52750         assign { } { }
52751         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52752       attribute \src "libresoc.v:0.0-0.0"
52753       case 5'01000
52754         assign { } { }
52755         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52756       attribute \src "libresoc.v:0.0-0.0"
52757       case 5'01110
52758         assign { } { }
52759         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52760       attribute \src "libresoc.v:0.0-0.0"
52761       case 5'00011
52762         assign { } { }
52763         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52764       attribute \src "libresoc.v:0.0-0.0"
52765       case 5'01101
52766         assign { } { }
52767         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52768       attribute \src "libresoc.v:0.0-0.0"
52769       case 5'01100
52770         assign { } { }
52771         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52772       attribute \src "libresoc.v:0.0-0.0"
52773       case 5'01001
52774         assign { } { }
52775         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52776       case
52777         assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00
52778     end
52779     sync always
52780       update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0]
52781   end
52782   attribute \src "libresoc.v:35696.3-35732.6"
52783   process $proc$libresoc.v:35696$778
52784     assign { } { }
52785     assign { } { }
52786     assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0]
52787     attribute \src "libresoc.v:35697.5-35697.29"
52788     switch \initial
52789       attribute \src "libresoc.v:35697.9-35697.17"
52790       case 1'1
52791       case
52792     end
52793     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52794     switch \opcode_switch
52795       attribute \src "libresoc.v:0.0-0.0"
52796       case 5'00000
52797         assign { } { }
52798         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52799       attribute \src "libresoc.v:0.0-0.0"
52800       case 5'00001
52801         assign { } { }
52802         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52803       attribute \src "libresoc.v:0.0-0.0"
52804       case 5'00111
52805         assign { } { }
52806         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52807       attribute \src "libresoc.v:0.0-0.0"
52808       case 5'01111
52809         assign { } { }
52810         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52811       attribute \src "libresoc.v:0.0-0.0"
52812       case 5'01000
52813         assign { } { }
52814         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52815       attribute \src "libresoc.v:0.0-0.0"
52816       case 5'01110
52817         assign { } { }
52818         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52819       attribute \src "libresoc.v:0.0-0.0"
52820       case 5'00011
52821         assign { } { }
52822         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52823       attribute \src "libresoc.v:0.0-0.0"
52824       case 5'01101
52825         assign { } { }
52826         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52827       attribute \src "libresoc.v:0.0-0.0"
52828       case 5'01100
52829         assign { } { }
52830         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52831       attribute \src "libresoc.v:0.0-0.0"
52832       case 5'01001
52833         assign { } { }
52834         assign $1\dec31_dec_sub28_out_sel[1:0] 2'10
52835       case
52836         assign $1\dec31_dec_sub28_out_sel[1:0] 2'00
52837     end
52838     sync always
52839       update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0]
52840   end
52841   attribute \src "libresoc.v:35733.3-35769.6"
52842   process $proc$libresoc.v:35733$779
52843     assign { } { }
52844     assign { } { }
52845     assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0]
52846     attribute \src "libresoc.v:35734.5-35734.29"
52847     switch \initial
52848       attribute \src "libresoc.v:35734.9-35734.17"
52849       case 1'1
52850       case
52851     end
52852     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52853     switch \opcode_switch
52854       attribute \src "libresoc.v:0.0-0.0"
52855       case 5'00000
52856         assign { } { }
52857         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52858       attribute \src "libresoc.v:0.0-0.0"
52859       case 5'00001
52860         assign { } { }
52861         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52862       attribute \src "libresoc.v:0.0-0.0"
52863       case 5'00111
52864         assign { } { }
52865         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52866       attribute \src "libresoc.v:0.0-0.0"
52867       case 5'01111
52868         assign { } { }
52869         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52870       attribute \src "libresoc.v:0.0-0.0"
52871       case 5'01000
52872         assign { } { }
52873         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52874       attribute \src "libresoc.v:0.0-0.0"
52875       case 5'01110
52876         assign { } { }
52877         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52878       attribute \src "libresoc.v:0.0-0.0"
52879       case 5'00011
52880         assign { } { }
52881         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52882       attribute \src "libresoc.v:0.0-0.0"
52883       case 5'01101
52884         assign { } { }
52885         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52886       attribute \src "libresoc.v:0.0-0.0"
52887       case 5'01100
52888         assign { } { }
52889         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52890       attribute \src "libresoc.v:0.0-0.0"
52891       case 5'01001
52892         assign { } { }
52893         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52894       case
52895         assign $1\dec31_dec_sub28_cr_in[2:0] 3'000
52896     end
52897     sync always
52898       update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0]
52899   end
52900   attribute \src "libresoc.v:35770.3-35806.6"
52901   process $proc$libresoc.v:35770$780
52902     assign { } { }
52903     assign { } { }
52904     assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0]
52905     attribute \src "libresoc.v:35771.5-35771.29"
52906     switch \initial
52907       attribute \src "libresoc.v:35771.9-35771.17"
52908       case 1'1
52909       case
52910     end
52911     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
52912     switch \opcode_switch
52913       attribute \src "libresoc.v:0.0-0.0"
52914       case 5'00000
52915         assign { } { }
52916         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52917       attribute \src "libresoc.v:0.0-0.0"
52918       case 5'00001
52919         assign { } { }
52920         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52921       attribute \src "libresoc.v:0.0-0.0"
52922       case 5'00111
52923         assign { } { }
52924         assign $1\dec31_dec_sub28_cr_out[2:0] 3'000
52925       attribute \src "libresoc.v:0.0-0.0"
52926       case 5'01111
52927         assign { } { }
52928         assign $1\dec31_dec_sub28_cr_out[2:0] 3'000
52929       attribute \src "libresoc.v:0.0-0.0"
52930       case 5'01000
52931         assign { } { }
52932         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52933       attribute \src "libresoc.v:0.0-0.0"
52934       case 5'01110
52935         assign { } { }
52936         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52937       attribute \src "libresoc.v:0.0-0.0"
52938       case 5'00011
52939         assign { } { }
52940         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52941       attribute \src "libresoc.v:0.0-0.0"
52942       case 5'01101
52943         assign { } { }
52944         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52945       attribute \src "libresoc.v:0.0-0.0"
52946       case 5'01100
52947         assign { } { }
52948         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52949       attribute \src "libresoc.v:0.0-0.0"
52950       case 5'01001
52951         assign { } { }
52952         assign $1\dec31_dec_sub28_cr_out[2:0] 3'001
52953       case
52954         assign $1\dec31_dec_sub28_cr_out[2:0] 3'000
52955     end
52956     sync always
52957       update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0]
52958   end
52959   connect \opcode_switch \opcode_in [10:6]
52960 end
52961 attribute \src "libresoc.v:35812.1-36383.10"
52962 attribute \cells_not_processed 1
52963 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4"
52964 attribute \generator "nMigen"
52965 module \dec31_dec_sub4
52966   attribute \src "libresoc.v:36135.3-36147.6"
52967   wire width 8 $0\dec31_dec_sub4_asmcode[7:0]
52968   attribute \src "libresoc.v:36187.3-36199.6"
52969   wire $0\dec31_dec_sub4_br[0:0]
52970   attribute \src "libresoc.v:36356.3-36368.6"
52971   wire width 3 $0\dec31_dec_sub4_cr_in[2:0]
52972   attribute \src "libresoc.v:36369.3-36381.6"
52973   wire width 3 $0\dec31_dec_sub4_cr_out[2:0]
52974   attribute \src "libresoc.v:36122.3-36134.6"
52975   wire width 2 $0\dec31_dec_sub4_cry_in[1:0]
52976   attribute \src "libresoc.v:36174.3-36186.6"
52977   wire $0\dec31_dec_sub4_cry_out[0:0]
52978   attribute \src "libresoc.v:36291.3-36303.6"
52979   wire width 5 $0\dec31_dec_sub4_form[4:0]
52980   attribute \src "libresoc.v:36070.3-36082.6"
52981   wire width 12 $0\dec31_dec_sub4_function_unit[11:0]
52982   attribute \src "libresoc.v:36304.3-36316.6"
52983   wire width 3 $0\dec31_dec_sub4_in1_sel[2:0]
52984   attribute \src "libresoc.v:36317.3-36329.6"
52985   wire width 4 $0\dec31_dec_sub4_in2_sel[3:0]
52986   attribute \src "libresoc.v:36330.3-36342.6"
52987   wire width 2 $0\dec31_dec_sub4_in3_sel[1:0]
52988   attribute \src "libresoc.v:36213.3-36225.6"
52989   wire width 7 $0\dec31_dec_sub4_internal_op[6:0]
52990   attribute \src "libresoc.v:36148.3-36160.6"
52991   wire $0\dec31_dec_sub4_inv_a[0:0]
52992   attribute \src "libresoc.v:36161.3-36173.6"
52993   wire $0\dec31_dec_sub4_inv_out[0:0]
52994   attribute \src "libresoc.v:36239.3-36251.6"
52995   wire $0\dec31_dec_sub4_is_32b[0:0]
52996   attribute \src "libresoc.v:36083.3-36095.6"
52997   wire width 4 $0\dec31_dec_sub4_ldst_len[3:0]
52998   attribute \src "libresoc.v:36265.3-36277.6"
52999   wire $0\dec31_dec_sub4_lk[0:0]
53000   attribute \src "libresoc.v:36343.3-36355.6"
53001   wire width 2 $0\dec31_dec_sub4_out_sel[1:0]
53002   attribute \src "libresoc.v:36109.3-36121.6"
53003   wire width 2 $0\dec31_dec_sub4_rc_sel[1:0]
53004   attribute \src "libresoc.v:36226.3-36238.6"
53005   wire $0\dec31_dec_sub4_rsrv[0:0]
53006   attribute \src "libresoc.v:36278.3-36290.6"
53007   wire $0\dec31_dec_sub4_sgl_pipe[0:0]
53008   attribute \src "libresoc.v:36252.3-36264.6"
53009   wire $0\dec31_dec_sub4_sgn[0:0]
53010   attribute \src "libresoc.v:36200.3-36212.6"
53011   wire $0\dec31_dec_sub4_sgn_ext[0:0]
53012   attribute \src "libresoc.v:36096.3-36108.6"
53013   wire width 2 $0\dec31_dec_sub4_upd[1:0]
53014   attribute \src "libresoc.v:35813.7-35813.20"
53015   wire $0\initial[0:0]
53016   attribute \src "libresoc.v:36135.3-36147.6"
53017   wire width 8 $1\dec31_dec_sub4_asmcode[7:0]
53018   attribute \src "libresoc.v:36187.3-36199.6"
53019   wire $1\dec31_dec_sub4_br[0:0]
53020   attribute \src "libresoc.v:36356.3-36368.6"
53021   wire width 3 $1\dec31_dec_sub4_cr_in[2:0]
53022   attribute \src "libresoc.v:36369.3-36381.6"
53023   wire width 3 $1\dec31_dec_sub4_cr_out[2:0]
53024   attribute \src "libresoc.v:36122.3-36134.6"
53025   wire width 2 $1\dec31_dec_sub4_cry_in[1:0]
53026   attribute \src "libresoc.v:36174.3-36186.6"
53027   wire $1\dec31_dec_sub4_cry_out[0:0]
53028   attribute \src "libresoc.v:36291.3-36303.6"
53029   wire width 5 $1\dec31_dec_sub4_form[4:0]
53030   attribute \src "libresoc.v:36070.3-36082.6"
53031   wire width 12 $1\dec31_dec_sub4_function_unit[11:0]
53032   attribute \src "libresoc.v:36304.3-36316.6"
53033   wire width 3 $1\dec31_dec_sub4_in1_sel[2:0]
53034   attribute \src "libresoc.v:36317.3-36329.6"
53035   wire width 4 $1\dec31_dec_sub4_in2_sel[3:0]
53036   attribute \src "libresoc.v:36330.3-36342.6"
53037   wire width 2 $1\dec31_dec_sub4_in3_sel[1:0]
53038   attribute \src "libresoc.v:36213.3-36225.6"
53039   wire width 7 $1\dec31_dec_sub4_internal_op[6:0]
53040   attribute \src "libresoc.v:36148.3-36160.6"
53041   wire $1\dec31_dec_sub4_inv_a[0:0]
53042   attribute \src "libresoc.v:36161.3-36173.6"
53043   wire $1\dec31_dec_sub4_inv_out[0:0]
53044   attribute \src "libresoc.v:36239.3-36251.6"
53045   wire $1\dec31_dec_sub4_is_32b[0:0]
53046   attribute \src "libresoc.v:36083.3-36095.6"
53047   wire width 4 $1\dec31_dec_sub4_ldst_len[3:0]
53048   attribute \src "libresoc.v:36265.3-36277.6"
53049   wire $1\dec31_dec_sub4_lk[0:0]
53050   attribute \src "libresoc.v:36343.3-36355.6"
53051   wire width 2 $1\dec31_dec_sub4_out_sel[1:0]
53052   attribute \src "libresoc.v:36109.3-36121.6"
53053   wire width 2 $1\dec31_dec_sub4_rc_sel[1:0]
53054   attribute \src "libresoc.v:36226.3-36238.6"
53055   wire $1\dec31_dec_sub4_rsrv[0:0]
53056   attribute \src "libresoc.v:36278.3-36290.6"
53057   wire $1\dec31_dec_sub4_sgl_pipe[0:0]
53058   attribute \src "libresoc.v:36252.3-36264.6"
53059   wire $1\dec31_dec_sub4_sgn[0:0]
53060   attribute \src "libresoc.v:36200.3-36212.6"
53061   wire $1\dec31_dec_sub4_sgn_ext[0:0]
53062   attribute \src "libresoc.v:36096.3-36108.6"
53063   wire width 2 $1\dec31_dec_sub4_upd[1:0]
53064   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53065   wire width 8 output 4 \dec31_dec_sub4_asmcode
53066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53067   wire output 18 \dec31_dec_sub4_br
53068   attribute \enum_base_type "CRInSel"
53069   attribute \enum_value_000 "NONE"
53070   attribute \enum_value_001 "CR0"
53071   attribute \enum_value_010 "BI"
53072   attribute \enum_value_011 "BFA"
53073   attribute \enum_value_100 "BA_BB"
53074   attribute \enum_value_101 "BC"
53075   attribute \enum_value_110 "WHOLE_REG"
53076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53077   wire width 3 output 9 \dec31_dec_sub4_cr_in
53078   attribute \enum_base_type "CROutSel"
53079   attribute \enum_value_000 "NONE"
53080   attribute \enum_value_001 "CR0"
53081   attribute \enum_value_010 "BF"
53082   attribute \enum_value_011 "BT"
53083   attribute \enum_value_100 "WHOLE_REG"
53084   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53085   wire width 3 output 10 \dec31_dec_sub4_cr_out
53086   attribute \enum_base_type "CryIn"
53087   attribute \enum_value_00 "ZERO"
53088   attribute \enum_value_01 "ONE"
53089   attribute \enum_value_10 "CA"
53090   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53091   wire width 2 output 14 \dec31_dec_sub4_cry_in
53092   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53093   wire output 17 \dec31_dec_sub4_cry_out
53094   attribute \enum_base_type "Form"
53095   attribute \enum_value_00000 "NONE"
53096   attribute \enum_value_00001 "I"
53097   attribute \enum_value_00010 "B"
53098   attribute \enum_value_00011 "SC"
53099   attribute \enum_value_00100 "D"
53100   attribute \enum_value_00101 "DS"
53101   attribute \enum_value_00110 "DQ"
53102   attribute \enum_value_00111 "DX"
53103   attribute \enum_value_01000 "X"
53104   attribute \enum_value_01001 "XL"
53105   attribute \enum_value_01010 "XFX"
53106   attribute \enum_value_01011 "XFL"
53107   attribute \enum_value_01100 "XX1"
53108   attribute \enum_value_01101 "XX2"
53109   attribute \enum_value_01110 "XX3"
53110   attribute \enum_value_01111 "XX4"
53111   attribute \enum_value_10000 "XS"
53112   attribute \enum_value_10001 "XO"
53113   attribute \enum_value_10010 "A"
53114   attribute \enum_value_10011 "M"
53115   attribute \enum_value_10100 "MD"
53116   attribute \enum_value_10101 "MDS"
53117   attribute \enum_value_10110 "VA"
53118   attribute \enum_value_10111 "VC"
53119   attribute \enum_value_11000 "VX"
53120   attribute \enum_value_11001 "EVX"
53121   attribute \enum_value_11010 "EVS"
53122   attribute \enum_value_11011 "Z22"
53123   attribute \enum_value_11100 "Z23"
53124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53125   wire width 5 output 3 \dec31_dec_sub4_form
53126   attribute \enum_base_type "Function"
53127   attribute \enum_value_000000000000 "NONE"
53128   attribute \enum_value_000000000010 "ALU"
53129   attribute \enum_value_000000000100 "LDST"
53130   attribute \enum_value_000000001000 "SHIFT_ROT"
53131   attribute \enum_value_000000010000 "LOGICAL"
53132   attribute \enum_value_000000100000 "BRANCH"
53133   attribute \enum_value_000001000000 "CR"
53134   attribute \enum_value_000010000000 "TRAP"
53135   attribute \enum_value_000100000000 "MUL"
53136   attribute \enum_value_001000000000 "DIV"
53137   attribute \enum_value_010000000000 "SPR"
53138   attribute \enum_value_100000000000 "MMU"
53139   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53140   wire width 12 output 1 \dec31_dec_sub4_function_unit
53141   attribute \enum_base_type "In1Sel"
53142   attribute \enum_value_000 "NONE"
53143   attribute \enum_value_001 "RA"
53144   attribute \enum_value_010 "RA_OR_ZERO"
53145   attribute \enum_value_011 "SPR"
53146   attribute \enum_value_100 "RS"
53147   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53148   wire width 3 output 5 \dec31_dec_sub4_in1_sel
53149   attribute \enum_base_type "In2Sel"
53150   attribute \enum_value_0000 "NONE"
53151   attribute \enum_value_0001 "RB"
53152   attribute \enum_value_0010 "CONST_UI"
53153   attribute \enum_value_0011 "CONST_SI"
53154   attribute \enum_value_0100 "CONST_UI_HI"
53155   attribute \enum_value_0101 "CONST_SI_HI"
53156   attribute \enum_value_0110 "CONST_LI"
53157   attribute \enum_value_0111 "CONST_BD"
53158   attribute \enum_value_1000 "CONST_DS"
53159   attribute \enum_value_1001 "CONST_M1"
53160   attribute \enum_value_1010 "CONST_SH"
53161   attribute \enum_value_1011 "CONST_SH32"
53162   attribute \enum_value_1100 "SPR"
53163   attribute \enum_value_1101 "RS"
53164   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53165   wire width 4 output 6 \dec31_dec_sub4_in2_sel
53166   attribute \enum_base_type "In3Sel"
53167   attribute \enum_value_00 "NONE"
53168   attribute \enum_value_01 "RS"
53169   attribute \enum_value_10 "RB"
53170   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53171   wire width 2 output 7 \dec31_dec_sub4_in3_sel
53172   attribute \enum_base_type "MicrOp"
53173   attribute \enum_value_0000000 "OP_ILLEGAL"
53174   attribute \enum_value_0000001 "OP_NOP"
53175   attribute \enum_value_0000010 "OP_ADD"
53176   attribute \enum_value_0000011 "OP_ADDPCIS"
53177   attribute \enum_value_0000100 "OP_AND"
53178   attribute \enum_value_0000101 "OP_ATTN"
53179   attribute \enum_value_0000110 "OP_B"
53180   attribute \enum_value_0000111 "OP_BC"
53181   attribute \enum_value_0001000 "OP_BCREG"
53182   attribute \enum_value_0001001 "OP_BPERM"
53183   attribute \enum_value_0001010 "OP_CMP"
53184   attribute \enum_value_0001011 "OP_CMPB"
53185   attribute \enum_value_0001100 "OP_CMPEQB"
53186   attribute \enum_value_0001101 "OP_CMPRB"
53187   attribute \enum_value_0001110 "OP_CNTZ"
53188   attribute \enum_value_0001111 "OP_CRAND"
53189   attribute \enum_value_0010000 "OP_CRANDC"
53190   attribute \enum_value_0010001 "OP_CREQV"
53191   attribute \enum_value_0010010 "OP_CRNAND"
53192   attribute \enum_value_0010011 "OP_CRNOR"
53193   attribute \enum_value_0010100 "OP_CROR"
53194   attribute \enum_value_0010101 "OP_CRORC"
53195   attribute \enum_value_0010110 "OP_CRXOR"
53196   attribute \enum_value_0010111 "OP_DARN"
53197   attribute \enum_value_0011000 "OP_DCBF"
53198   attribute \enum_value_0011001 "OP_DCBST"
53199   attribute \enum_value_0011010 "OP_DCBT"
53200   attribute \enum_value_0011011 "OP_DCBTST"
53201   attribute \enum_value_0011100 "OP_DCBZ"
53202   attribute \enum_value_0011101 "OP_DIV"
53203   attribute \enum_value_0011110 "OP_DIVE"
53204   attribute \enum_value_0011111 "OP_EXTS"
53205   attribute \enum_value_0100000 "OP_EXTSWSLI"
53206   attribute \enum_value_0100001 "OP_ICBI"
53207   attribute \enum_value_0100010 "OP_ICBT"
53208   attribute \enum_value_0100011 "OP_ISEL"
53209   attribute \enum_value_0100100 "OP_ISYNC"
53210   attribute \enum_value_0100101 "OP_LOAD"
53211   attribute \enum_value_0100110 "OP_STORE"
53212   attribute \enum_value_0100111 "OP_MADDHD"
53213   attribute \enum_value_0101000 "OP_MADDHDU"
53214   attribute \enum_value_0101001 "OP_MADDLD"
53215   attribute \enum_value_0101010 "OP_MCRF"
53216   attribute \enum_value_0101011 "OP_MCRXR"
53217   attribute \enum_value_0101100 "OP_MCRXRX"
53218   attribute \enum_value_0101101 "OP_MFCR"
53219   attribute \enum_value_0101110 "OP_MFSPR"
53220   attribute \enum_value_0101111 "OP_MOD"
53221   attribute \enum_value_0110000 "OP_MTCRF"
53222   attribute \enum_value_0110001 "OP_MTSPR"
53223   attribute \enum_value_0110010 "OP_MUL_L64"
53224   attribute \enum_value_0110011 "OP_MUL_H64"
53225   attribute \enum_value_0110100 "OP_MUL_H32"
53226   attribute \enum_value_0110101 "OP_OR"
53227   attribute \enum_value_0110110 "OP_POPCNT"
53228   attribute \enum_value_0110111 "OP_PRTY"
53229   attribute \enum_value_0111000 "OP_RLC"
53230   attribute \enum_value_0111001 "OP_RLCL"
53231   attribute \enum_value_0111010 "OP_RLCR"
53232   attribute \enum_value_0111011 "OP_SETB"
53233   attribute \enum_value_0111100 "OP_SHL"
53234   attribute \enum_value_0111101 "OP_SHR"
53235   attribute \enum_value_0111110 "OP_SYNC"
53236   attribute \enum_value_0111111 "OP_TRAP"
53237   attribute \enum_value_1000011 "OP_XOR"
53238   attribute \enum_value_1000100 "OP_SIM_CONFIG"
53239   attribute \enum_value_1000101 "OP_CROP"
53240   attribute \enum_value_1000110 "OP_RFID"
53241   attribute \enum_value_1000111 "OP_MFMSR"
53242   attribute \enum_value_1001000 "OP_MTMSRD"
53243   attribute \enum_value_1001001 "OP_SC"
53244   attribute \enum_value_1001010 "OP_MTMSR"
53245   attribute \enum_value_1001011 "OP_TLBIE"
53246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53247   wire width 7 output 2 \dec31_dec_sub4_internal_op
53248   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53249   wire output 15 \dec31_dec_sub4_inv_a
53250   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53251   wire output 16 \dec31_dec_sub4_inv_out
53252   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53253   wire output 21 \dec31_dec_sub4_is_32b
53254   attribute \enum_base_type "LdstLen"
53255   attribute \enum_value_0000 "NONE"
53256   attribute \enum_value_0001 "is1B"
53257   attribute \enum_value_0010 "is2B"
53258   attribute \enum_value_0100 "is4B"
53259   attribute \enum_value_1000 "is8B"
53260   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53261   wire width 4 output 11 \dec31_dec_sub4_ldst_len
53262   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53263   wire output 23 \dec31_dec_sub4_lk
53264   attribute \enum_base_type "OutSel"
53265   attribute \enum_value_00 "NONE"
53266   attribute \enum_value_01 "RT"
53267   attribute \enum_value_10 "RA"
53268   attribute \enum_value_11 "SPR"
53269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53270   wire width 2 output 8 \dec31_dec_sub4_out_sel
53271   attribute \enum_base_type "RC"
53272   attribute \enum_value_00 "NONE"
53273   attribute \enum_value_01 "ONE"
53274   attribute \enum_value_10 "RC"
53275   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53276   wire width 2 output 13 \dec31_dec_sub4_rc_sel
53277   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53278   wire output 20 \dec31_dec_sub4_rsrv
53279   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53280   wire output 24 \dec31_dec_sub4_sgl_pipe
53281   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53282   wire output 22 \dec31_dec_sub4_sgn
53283   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
53284   wire output 19 \dec31_dec_sub4_sgn_ext
53285   attribute \enum_base_type "LDSTMode"
53286   attribute \enum_value_00 "NONE"
53287   attribute \enum_value_01 "update"
53288   attribute \enum_value_10 "cix"
53289   attribute \enum_value_11 "cx"
53290   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
53291   wire width 2 output 12 \dec31_dec_sub4_upd
53292   attribute \src "libresoc.v:35813.7-35813.15"
53293   wire \initial
53294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
53295   wire width 32 input 25 \opcode_in
53296   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
53297   wire width 5 \opcode_switch
53298   attribute \src "libresoc.v:35813.7-35813.20"
53299   process $proc$libresoc.v:35813$806
53300     assign { } { }
53301     assign $0\initial[0:0] 1'0
53302     sync always
53303       update \initial $0\initial[0:0]
53304     sync init
53305   end
53306   attribute \src "libresoc.v:36070.3-36082.6"
53307   process $proc$libresoc.v:36070$782
53308     assign { } { }
53309     assign { } { }
53310     assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0]
53311     attribute \src "libresoc.v:36071.5-36071.29"
53312     switch \initial
53313       attribute \src "libresoc.v:36071.9-36071.17"
53314       case 1'1
53315       case
53316     end
53317     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53318     switch \opcode_switch
53319       attribute \src "libresoc.v:0.0-0.0"
53320       case 5'00010
53321         assign { } { }
53322         assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000
53323       attribute \src "libresoc.v:0.0-0.0"
53324       case 5'00000
53325         assign { } { }
53326         assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000
53327       case
53328         assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000
53329     end
53330     sync always
53331       update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0]
53332   end
53333   attribute \src "libresoc.v:36083.3-36095.6"
53334   process $proc$libresoc.v:36083$783
53335     assign { } { }
53336     assign { } { }
53337     assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0]
53338     attribute \src "libresoc.v:36084.5-36084.29"
53339     switch \initial
53340       attribute \src "libresoc.v:36084.9-36084.17"
53341       case 1'1
53342       case
53343     end
53344     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53345     switch \opcode_switch
53346       attribute \src "libresoc.v:0.0-0.0"
53347       case 5'00010
53348         assign { } { }
53349         assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000
53350       attribute \src "libresoc.v:0.0-0.0"
53351       case 5'00000
53352         assign { } { }
53353         assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000
53354       case
53355         assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000
53356     end
53357     sync always
53358       update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0]
53359   end
53360   attribute \src "libresoc.v:36096.3-36108.6"
53361   process $proc$libresoc.v:36096$784
53362     assign { } { }
53363     assign { } { }
53364     assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0]
53365     attribute \src "libresoc.v:36097.5-36097.29"
53366     switch \initial
53367       attribute \src "libresoc.v:36097.9-36097.17"
53368       case 1'1
53369       case
53370     end
53371     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53372     switch \opcode_switch
53373       attribute \src "libresoc.v:0.0-0.0"
53374       case 5'00010
53375         assign { } { }
53376         assign $1\dec31_dec_sub4_upd[1:0] 2'00
53377       attribute \src "libresoc.v:0.0-0.0"
53378       case 5'00000
53379         assign { } { }
53380         assign $1\dec31_dec_sub4_upd[1:0] 2'00
53381       case
53382         assign $1\dec31_dec_sub4_upd[1:0] 2'00
53383     end
53384     sync always
53385       update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0]
53386   end
53387   attribute \src "libresoc.v:36109.3-36121.6"
53388   process $proc$libresoc.v:36109$785
53389     assign { } { }
53390     assign { } { }
53391     assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0]
53392     attribute \src "libresoc.v:36110.5-36110.29"
53393     switch \initial
53394       attribute \src "libresoc.v:36110.9-36110.17"
53395       case 1'1
53396       case
53397     end
53398     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53399     switch \opcode_switch
53400       attribute \src "libresoc.v:0.0-0.0"
53401       case 5'00010
53402         assign { } { }
53403         assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00
53404       attribute \src "libresoc.v:0.0-0.0"
53405       case 5'00000
53406         assign { } { }
53407         assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00
53408       case
53409         assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00
53410     end
53411     sync always
53412       update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0]
53413   end
53414   attribute \src "libresoc.v:36122.3-36134.6"
53415   process $proc$libresoc.v:36122$786
53416     assign { } { }
53417     assign { } { }
53418     assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0]
53419     attribute \src "libresoc.v:36123.5-36123.29"
53420     switch \initial
53421       attribute \src "libresoc.v:36123.9-36123.17"
53422       case 1'1
53423       case
53424     end
53425     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53426     switch \opcode_switch
53427       attribute \src "libresoc.v:0.0-0.0"
53428       case 5'00010
53429         assign { } { }
53430         assign $1\dec31_dec_sub4_cry_in[1:0] 2'00
53431       attribute \src "libresoc.v:0.0-0.0"
53432       case 5'00000
53433         assign { } { }
53434         assign $1\dec31_dec_sub4_cry_in[1:0] 2'00
53435       case
53436         assign $1\dec31_dec_sub4_cry_in[1:0] 2'00
53437     end
53438     sync always
53439       update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0]
53440   end
53441   attribute \src "libresoc.v:36135.3-36147.6"
53442   process $proc$libresoc.v:36135$787
53443     assign { } { }
53444     assign { } { }
53445     assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0]
53446     attribute \src "libresoc.v:36136.5-36136.29"
53447     switch \initial
53448       attribute \src "libresoc.v:36136.9-36136.17"
53449       case 1'1
53450       case
53451     end
53452     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53453     switch \opcode_switch
53454       attribute \src "libresoc.v:0.0-0.0"
53455       case 5'00010
53456         assign { } { }
53457         assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010
53458       attribute \src "libresoc.v:0.0-0.0"
53459       case 5'00000
53460         assign { } { }
53461         assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110
53462       case
53463         assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000
53464     end
53465     sync always
53466       update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0]
53467   end
53468   attribute \src "libresoc.v:36148.3-36160.6"
53469   process $proc$libresoc.v:36148$788
53470     assign { } { }
53471     assign { } { }
53472     assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0]
53473     attribute \src "libresoc.v:36149.5-36149.29"
53474     switch \initial
53475       attribute \src "libresoc.v:36149.9-36149.17"
53476       case 1'1
53477       case
53478     end
53479     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53480     switch \opcode_switch
53481       attribute \src "libresoc.v:0.0-0.0"
53482       case 5'00010
53483         assign { } { }
53484         assign $1\dec31_dec_sub4_inv_a[0:0] 1'0
53485       attribute \src "libresoc.v:0.0-0.0"
53486       case 5'00000
53487         assign { } { }
53488         assign $1\dec31_dec_sub4_inv_a[0:0] 1'0
53489       case
53490         assign $1\dec31_dec_sub4_inv_a[0:0] 1'0
53491     end
53492     sync always
53493       update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0]
53494   end
53495   attribute \src "libresoc.v:36161.3-36173.6"
53496   process $proc$libresoc.v:36161$789
53497     assign { } { }
53498     assign { } { }
53499     assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0]
53500     attribute \src "libresoc.v:36162.5-36162.29"
53501     switch \initial
53502       attribute \src "libresoc.v:36162.9-36162.17"
53503       case 1'1
53504       case
53505     end
53506     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53507     switch \opcode_switch
53508       attribute \src "libresoc.v:0.0-0.0"
53509       case 5'00010
53510         assign { } { }
53511         assign $1\dec31_dec_sub4_inv_out[0:0] 1'0
53512       attribute \src "libresoc.v:0.0-0.0"
53513       case 5'00000
53514         assign { } { }
53515         assign $1\dec31_dec_sub4_inv_out[0:0] 1'0
53516       case
53517         assign $1\dec31_dec_sub4_inv_out[0:0] 1'0
53518     end
53519     sync always
53520       update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0]
53521   end
53522   attribute \src "libresoc.v:36174.3-36186.6"
53523   process $proc$libresoc.v:36174$790
53524     assign { } { }
53525     assign { } { }
53526     assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0]
53527     attribute \src "libresoc.v:36175.5-36175.29"
53528     switch \initial
53529       attribute \src "libresoc.v:36175.9-36175.17"
53530       case 1'1
53531       case
53532     end
53533     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53534     switch \opcode_switch
53535       attribute \src "libresoc.v:0.0-0.0"
53536       case 5'00010
53537         assign { } { }
53538         assign $1\dec31_dec_sub4_cry_out[0:0] 1'0
53539       attribute \src "libresoc.v:0.0-0.0"
53540       case 5'00000
53541         assign { } { }
53542         assign $1\dec31_dec_sub4_cry_out[0:0] 1'0
53543       case
53544         assign $1\dec31_dec_sub4_cry_out[0:0] 1'0
53545     end
53546     sync always
53547       update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0]
53548   end
53549   attribute \src "libresoc.v:36187.3-36199.6"
53550   process $proc$libresoc.v:36187$791
53551     assign { } { }
53552     assign { } { }
53553     assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0]
53554     attribute \src "libresoc.v:36188.5-36188.29"
53555     switch \initial
53556       attribute \src "libresoc.v:36188.9-36188.17"
53557       case 1'1
53558       case
53559     end
53560     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53561     switch \opcode_switch
53562       attribute \src "libresoc.v:0.0-0.0"
53563       case 5'00010
53564         assign { } { }
53565         assign $1\dec31_dec_sub4_br[0:0] 1'0
53566       attribute \src "libresoc.v:0.0-0.0"
53567       case 5'00000
53568         assign { } { }
53569         assign $1\dec31_dec_sub4_br[0:0] 1'0
53570       case
53571         assign $1\dec31_dec_sub4_br[0:0] 1'0
53572     end
53573     sync always
53574       update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0]
53575   end
53576   attribute \src "libresoc.v:36200.3-36212.6"
53577   process $proc$libresoc.v:36200$792
53578     assign { } { }
53579     assign { } { }
53580     assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0]
53581     attribute \src "libresoc.v:36201.5-36201.29"
53582     switch \initial
53583       attribute \src "libresoc.v:36201.9-36201.17"
53584       case 1'1
53585       case
53586     end
53587     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53588     switch \opcode_switch
53589       attribute \src "libresoc.v:0.0-0.0"
53590       case 5'00010
53591         assign { } { }
53592         assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0
53593       attribute \src "libresoc.v:0.0-0.0"
53594       case 5'00000
53595         assign { } { }
53596         assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0
53597       case
53598         assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0
53599     end
53600     sync always
53601       update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0]
53602   end
53603   attribute \src "libresoc.v:36213.3-36225.6"
53604   process $proc$libresoc.v:36213$793
53605     assign { } { }
53606     assign { } { }
53607     assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0]
53608     attribute \src "libresoc.v:36214.5-36214.29"
53609     switch \initial
53610       attribute \src "libresoc.v:36214.9-36214.17"
53611       case 1'1
53612       case
53613     end
53614     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53615     switch \opcode_switch
53616       attribute \src "libresoc.v:0.0-0.0"
53617       case 5'00010
53618         assign { } { }
53619         assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111
53620       attribute \src "libresoc.v:0.0-0.0"
53621       case 5'00000
53622         assign { } { }
53623         assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111
53624       case
53625         assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000
53626     end
53627     sync always
53628       update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0]
53629   end
53630   attribute \src "libresoc.v:36226.3-36238.6"
53631   process $proc$libresoc.v:36226$794
53632     assign { } { }
53633     assign { } { }
53634     assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0]
53635     attribute \src "libresoc.v:36227.5-36227.29"
53636     switch \initial
53637       attribute \src "libresoc.v:36227.9-36227.17"
53638       case 1'1
53639       case
53640     end
53641     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53642     switch \opcode_switch
53643       attribute \src "libresoc.v:0.0-0.0"
53644       case 5'00010
53645         assign { } { }
53646         assign $1\dec31_dec_sub4_rsrv[0:0] 1'0
53647       attribute \src "libresoc.v:0.0-0.0"
53648       case 5'00000
53649         assign { } { }
53650         assign $1\dec31_dec_sub4_rsrv[0:0] 1'0
53651       case
53652         assign $1\dec31_dec_sub4_rsrv[0:0] 1'0
53653     end
53654     sync always
53655       update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0]
53656   end
53657   attribute \src "libresoc.v:36239.3-36251.6"
53658   process $proc$libresoc.v:36239$795
53659     assign { } { }
53660     assign { } { }
53661     assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0]
53662     attribute \src "libresoc.v:36240.5-36240.29"
53663     switch \initial
53664       attribute \src "libresoc.v:36240.9-36240.17"
53665       case 1'1
53666       case
53667     end
53668     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53669     switch \opcode_switch
53670       attribute \src "libresoc.v:0.0-0.0"
53671       case 5'00010
53672         assign { } { }
53673         assign $1\dec31_dec_sub4_is_32b[0:0] 1'0
53674       attribute \src "libresoc.v:0.0-0.0"
53675       case 5'00000
53676         assign { } { }
53677         assign $1\dec31_dec_sub4_is_32b[0:0] 1'1
53678       case
53679         assign $1\dec31_dec_sub4_is_32b[0:0] 1'0
53680     end
53681     sync always
53682       update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0]
53683   end
53684   attribute \src "libresoc.v:36252.3-36264.6"
53685   process $proc$libresoc.v:36252$796
53686     assign { } { }
53687     assign { } { }
53688     assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0]
53689     attribute \src "libresoc.v:36253.5-36253.29"
53690     switch \initial
53691       attribute \src "libresoc.v:36253.9-36253.17"
53692       case 1'1
53693       case
53694     end
53695     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53696     switch \opcode_switch
53697       attribute \src "libresoc.v:0.0-0.0"
53698       case 5'00010
53699         assign { } { }
53700         assign $1\dec31_dec_sub4_sgn[0:0] 1'0
53701       attribute \src "libresoc.v:0.0-0.0"
53702       case 5'00000
53703         assign { } { }
53704         assign $1\dec31_dec_sub4_sgn[0:0] 1'0
53705       case
53706         assign $1\dec31_dec_sub4_sgn[0:0] 1'0
53707     end
53708     sync always
53709       update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0]
53710   end
53711   attribute \src "libresoc.v:36265.3-36277.6"
53712   process $proc$libresoc.v:36265$797
53713     assign { } { }
53714     assign { } { }
53715     assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0]
53716     attribute \src "libresoc.v:36266.5-36266.29"
53717     switch \initial
53718       attribute \src "libresoc.v:36266.9-36266.17"
53719       case 1'1
53720       case
53721     end
53722     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53723     switch \opcode_switch
53724       attribute \src "libresoc.v:0.0-0.0"
53725       case 5'00010
53726         assign { } { }
53727         assign $1\dec31_dec_sub4_lk[0:0] 1'0
53728       attribute \src "libresoc.v:0.0-0.0"
53729       case 5'00000
53730         assign { } { }
53731         assign $1\dec31_dec_sub4_lk[0:0] 1'0
53732       case
53733         assign $1\dec31_dec_sub4_lk[0:0] 1'0
53734     end
53735     sync always
53736       update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0]
53737   end
53738   attribute \src "libresoc.v:36278.3-36290.6"
53739   process $proc$libresoc.v:36278$798
53740     assign { } { }
53741     assign { } { }
53742     assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0]
53743     attribute \src "libresoc.v:36279.5-36279.29"
53744     switch \initial
53745       attribute \src "libresoc.v:36279.9-36279.17"
53746       case 1'1
53747       case
53748     end
53749     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53750     switch \opcode_switch
53751       attribute \src "libresoc.v:0.0-0.0"
53752       case 5'00010
53753         assign { } { }
53754         assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1
53755       attribute \src "libresoc.v:0.0-0.0"
53756       case 5'00000
53757         assign { } { }
53758         assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1
53759       case
53760         assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0
53761     end
53762     sync always
53763       update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0]
53764   end
53765   attribute \src "libresoc.v:36291.3-36303.6"
53766   process $proc$libresoc.v:36291$799
53767     assign { } { }
53768     assign { } { }
53769     assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0]
53770     attribute \src "libresoc.v:36292.5-36292.29"
53771     switch \initial
53772       attribute \src "libresoc.v:36292.9-36292.17"
53773       case 1'1
53774       case
53775     end
53776     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53777     switch \opcode_switch
53778       attribute \src "libresoc.v:0.0-0.0"
53779       case 5'00010
53780         assign { } { }
53781         assign $1\dec31_dec_sub4_form[4:0] 5'01000
53782       attribute \src "libresoc.v:0.0-0.0"
53783       case 5'00000
53784         assign { } { }
53785         assign $1\dec31_dec_sub4_form[4:0] 5'01000
53786       case
53787         assign $1\dec31_dec_sub4_form[4:0] 5'00000
53788     end
53789     sync always
53790       update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0]
53791   end
53792   attribute \src "libresoc.v:36304.3-36316.6"
53793   process $proc$libresoc.v:36304$800
53794     assign { } { }
53795     assign { } { }
53796     assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0]
53797     attribute \src "libresoc.v:36305.5-36305.29"
53798     switch \initial
53799       attribute \src "libresoc.v:36305.9-36305.17"
53800       case 1'1
53801       case
53802     end
53803     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53804     switch \opcode_switch
53805       attribute \src "libresoc.v:0.0-0.0"
53806       case 5'00010
53807         assign { } { }
53808         assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001
53809       attribute \src "libresoc.v:0.0-0.0"
53810       case 5'00000
53811         assign { } { }
53812         assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001
53813       case
53814         assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000
53815     end
53816     sync always
53817       update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0]
53818   end
53819   attribute \src "libresoc.v:36317.3-36329.6"
53820   process $proc$libresoc.v:36317$801
53821     assign { } { }
53822     assign { } { }
53823     assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0]
53824     attribute \src "libresoc.v:36318.5-36318.29"
53825     switch \initial
53826       attribute \src "libresoc.v:36318.9-36318.17"
53827       case 1'1
53828       case
53829     end
53830     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53831     switch \opcode_switch
53832       attribute \src "libresoc.v:0.0-0.0"
53833       case 5'00010
53834         assign { } { }
53835         assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001
53836       attribute \src "libresoc.v:0.0-0.0"
53837       case 5'00000
53838         assign { } { }
53839         assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001
53840       case
53841         assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000
53842     end
53843     sync always
53844       update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0]
53845   end
53846   attribute \src "libresoc.v:36330.3-36342.6"
53847   process $proc$libresoc.v:36330$802
53848     assign { } { }
53849     assign { } { }
53850     assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0]
53851     attribute \src "libresoc.v:36331.5-36331.29"
53852     switch \initial
53853       attribute \src "libresoc.v:36331.9-36331.17"
53854       case 1'1
53855       case
53856     end
53857     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53858     switch \opcode_switch
53859       attribute \src "libresoc.v:0.0-0.0"
53860       case 5'00010
53861         assign { } { }
53862         assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00
53863       attribute \src "libresoc.v:0.0-0.0"
53864       case 5'00000
53865         assign { } { }
53866         assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00
53867       case
53868         assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00
53869     end
53870     sync always
53871       update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0]
53872   end
53873   attribute \src "libresoc.v:36343.3-36355.6"
53874   process $proc$libresoc.v:36343$803
53875     assign { } { }
53876     assign { } { }
53877     assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0]
53878     attribute \src "libresoc.v:36344.5-36344.29"
53879     switch \initial
53880       attribute \src "libresoc.v:36344.9-36344.17"
53881       case 1'1
53882       case
53883     end
53884     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53885     switch \opcode_switch
53886       attribute \src "libresoc.v:0.0-0.0"
53887       case 5'00010
53888         assign { } { }
53889         assign $1\dec31_dec_sub4_out_sel[1:0] 2'00
53890       attribute \src "libresoc.v:0.0-0.0"
53891       case 5'00000
53892         assign { } { }
53893         assign $1\dec31_dec_sub4_out_sel[1:0] 2'00
53894       case
53895         assign $1\dec31_dec_sub4_out_sel[1:0] 2'00
53896     end
53897     sync always
53898       update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0]
53899   end
53900   attribute \src "libresoc.v:36356.3-36368.6"
53901   process $proc$libresoc.v:36356$804
53902     assign { } { }
53903     assign { } { }
53904     assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0]
53905     attribute \src "libresoc.v:36357.5-36357.29"
53906     switch \initial
53907       attribute \src "libresoc.v:36357.9-36357.17"
53908       case 1'1
53909       case
53910     end
53911     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53912     switch \opcode_switch
53913       attribute \src "libresoc.v:0.0-0.0"
53914       case 5'00010
53915         assign { } { }
53916         assign $1\dec31_dec_sub4_cr_in[2:0] 3'000
53917       attribute \src "libresoc.v:0.0-0.0"
53918       case 5'00000
53919         assign { } { }
53920         assign $1\dec31_dec_sub4_cr_in[2:0] 3'000
53921       case
53922         assign $1\dec31_dec_sub4_cr_in[2:0] 3'000
53923     end
53924     sync always
53925       update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0]
53926   end
53927   attribute \src "libresoc.v:36369.3-36381.6"
53928   process $proc$libresoc.v:36369$805
53929     assign { } { }
53930     assign { } { }
53931     assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0]
53932     attribute \src "libresoc.v:36370.5-36370.29"
53933     switch \initial
53934       attribute \src "libresoc.v:36370.9-36370.17"
53935       case 1'1
53936       case
53937     end
53938     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
53939     switch \opcode_switch
53940       attribute \src "libresoc.v:0.0-0.0"
53941       case 5'00010
53942         assign { } { }
53943         assign $1\dec31_dec_sub4_cr_out[2:0] 3'000
53944       attribute \src "libresoc.v:0.0-0.0"
53945       case 5'00000
53946         assign { } { }
53947         assign $1\dec31_dec_sub4_cr_out[2:0] 3'000
53948       case
53949         assign $1\dec31_dec_sub4_cr_out[2:0] 3'000
53950     end
53951     sync always
53952       update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0]
53953   end
53954   connect \opcode_switch \opcode_in [10:6]
53955 end
53956 attribute \src "libresoc.v:36387.1-37678.10"
53957 attribute \cells_not_processed 1
53958 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8"
53959 attribute \generator "nMigen"
53960 module \dec31_dec_sub8
53961   attribute \src "libresoc.v:36860.3-36902.6"
53962   wire width 8 $0\dec31_dec_sub8_asmcode[7:0]
53963   attribute \src "libresoc.v:37032.3-37074.6"
53964   wire $0\dec31_dec_sub8_br[0:0]
53965   attribute \src "libresoc.v:37591.3-37633.6"
53966   wire width 3 $0\dec31_dec_sub8_cr_in[2:0]
53967   attribute \src "libresoc.v:37634.3-37676.6"
53968   wire width 3 $0\dec31_dec_sub8_cr_out[2:0]
53969   attribute \src "libresoc.v:36817.3-36859.6"
53970   wire width 2 $0\dec31_dec_sub8_cry_in[1:0]
53971   attribute \src "libresoc.v:36989.3-37031.6"
53972   wire $0\dec31_dec_sub8_cry_out[0:0]
53973   attribute \src "libresoc.v:37376.3-37418.6"
53974   wire width 5 $0\dec31_dec_sub8_form[4:0]
53975   attribute \src "libresoc.v:36645.3-36687.6"
53976   wire width 12 $0\dec31_dec_sub8_function_unit[11:0]
53977   attribute \src "libresoc.v:37419.3-37461.6"
53978   wire width 3 $0\dec31_dec_sub8_in1_sel[2:0]
53979   attribute \src "libresoc.v:37462.3-37504.6"
53980   wire width 4 $0\dec31_dec_sub8_in2_sel[3:0]
53981   attribute \src "libresoc.v:37505.3-37547.6"
53982   wire width 2 $0\dec31_dec_sub8_in3_sel[1:0]
53983   attribute \src "libresoc.v:37118.3-37160.6"
53984   wire width 7 $0\dec31_dec_sub8_internal_op[6:0]
53985   attribute \src "libresoc.v:36903.3-36945.6"
53986   wire $0\dec31_dec_sub8_inv_a[0:0]
53987   attribute \src "libresoc.v:36946.3-36988.6"
53988   wire $0\dec31_dec_sub8_inv_out[0:0]
53989   attribute \src "libresoc.v:37204.3-37246.6"
53990   wire $0\dec31_dec_sub8_is_32b[0:0]
53991   attribute \src "libresoc.v:36688.3-36730.6"
53992   wire width 4 $0\dec31_dec_sub8_ldst_len[3:0]
53993   attribute \src "libresoc.v:37290.3-37332.6"
53994   wire $0\dec31_dec_sub8_lk[0:0]
53995   attribute \src "libresoc.v:37548.3-37590.6"
53996   wire width 2 $0\dec31_dec_sub8_out_sel[1:0]
53997   attribute \src "libresoc.v:36774.3-36816.6"
53998   wire width 2 $0\dec31_dec_sub8_rc_sel[1:0]
53999   attribute \src "libresoc.v:37161.3-37203.6"
54000   wire $0\dec31_dec_sub8_rsrv[0:0]
54001   attribute \src "libresoc.v:37333.3-37375.6"
54002   wire $0\dec31_dec_sub8_sgl_pipe[0:0]
54003   attribute \src "libresoc.v:37247.3-37289.6"
54004   wire $0\dec31_dec_sub8_sgn[0:0]
54005   attribute \src "libresoc.v:37075.3-37117.6"
54006   wire $0\dec31_dec_sub8_sgn_ext[0:0]
54007   attribute \src "libresoc.v:36731.3-36773.6"
54008   wire width 2 $0\dec31_dec_sub8_upd[1:0]
54009   attribute \src "libresoc.v:36388.7-36388.20"
54010   wire $0\initial[0:0]
54011   attribute \src "libresoc.v:36860.3-36902.6"
54012   wire width 8 $1\dec31_dec_sub8_asmcode[7:0]
54013   attribute \src "libresoc.v:37032.3-37074.6"
54014   wire $1\dec31_dec_sub8_br[0:0]
54015   attribute \src "libresoc.v:37591.3-37633.6"
54016   wire width 3 $1\dec31_dec_sub8_cr_in[2:0]
54017   attribute \src "libresoc.v:37634.3-37676.6"
54018   wire width 3 $1\dec31_dec_sub8_cr_out[2:0]
54019   attribute \src "libresoc.v:36817.3-36859.6"
54020   wire width 2 $1\dec31_dec_sub8_cry_in[1:0]
54021   attribute \src "libresoc.v:36989.3-37031.6"
54022   wire $1\dec31_dec_sub8_cry_out[0:0]
54023   attribute \src "libresoc.v:37376.3-37418.6"
54024   wire width 5 $1\dec31_dec_sub8_form[4:0]
54025   attribute \src "libresoc.v:36645.3-36687.6"
54026   wire width 12 $1\dec31_dec_sub8_function_unit[11:0]
54027   attribute \src "libresoc.v:37419.3-37461.6"
54028   wire width 3 $1\dec31_dec_sub8_in1_sel[2:0]
54029   attribute \src "libresoc.v:37462.3-37504.6"
54030   wire width 4 $1\dec31_dec_sub8_in2_sel[3:0]
54031   attribute \src "libresoc.v:37505.3-37547.6"
54032   wire width 2 $1\dec31_dec_sub8_in3_sel[1:0]
54033   attribute \src "libresoc.v:37118.3-37160.6"
54034   wire width 7 $1\dec31_dec_sub8_internal_op[6:0]
54035   attribute \src "libresoc.v:36903.3-36945.6"
54036   wire $1\dec31_dec_sub8_inv_a[0:0]
54037   attribute \src "libresoc.v:36946.3-36988.6"
54038   wire $1\dec31_dec_sub8_inv_out[0:0]
54039   attribute \src "libresoc.v:37204.3-37246.6"
54040   wire $1\dec31_dec_sub8_is_32b[0:0]
54041   attribute \src "libresoc.v:36688.3-36730.6"
54042   wire width 4 $1\dec31_dec_sub8_ldst_len[3:0]
54043   attribute \src "libresoc.v:37290.3-37332.6"
54044   wire $1\dec31_dec_sub8_lk[0:0]
54045   attribute \src "libresoc.v:37548.3-37590.6"
54046   wire width 2 $1\dec31_dec_sub8_out_sel[1:0]
54047   attribute \src "libresoc.v:36774.3-36816.6"
54048   wire width 2 $1\dec31_dec_sub8_rc_sel[1:0]
54049   attribute \src "libresoc.v:37161.3-37203.6"
54050   wire $1\dec31_dec_sub8_rsrv[0:0]
54051   attribute \src "libresoc.v:37333.3-37375.6"
54052   wire $1\dec31_dec_sub8_sgl_pipe[0:0]
54053   attribute \src "libresoc.v:37247.3-37289.6"
54054   wire $1\dec31_dec_sub8_sgn[0:0]
54055   attribute \src "libresoc.v:37075.3-37117.6"
54056   wire $1\dec31_dec_sub8_sgn_ext[0:0]
54057   attribute \src "libresoc.v:36731.3-36773.6"
54058   wire width 2 $1\dec31_dec_sub8_upd[1:0]
54059   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54060   wire width 8 output 4 \dec31_dec_sub8_asmcode
54061   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54062   wire output 18 \dec31_dec_sub8_br
54063   attribute \enum_base_type "CRInSel"
54064   attribute \enum_value_000 "NONE"
54065   attribute \enum_value_001 "CR0"
54066   attribute \enum_value_010 "BI"
54067   attribute \enum_value_011 "BFA"
54068   attribute \enum_value_100 "BA_BB"
54069   attribute \enum_value_101 "BC"
54070   attribute \enum_value_110 "WHOLE_REG"
54071   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54072   wire width 3 output 9 \dec31_dec_sub8_cr_in
54073   attribute \enum_base_type "CROutSel"
54074   attribute \enum_value_000 "NONE"
54075   attribute \enum_value_001 "CR0"
54076   attribute \enum_value_010 "BF"
54077   attribute \enum_value_011 "BT"
54078   attribute \enum_value_100 "WHOLE_REG"
54079   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54080   wire width 3 output 10 \dec31_dec_sub8_cr_out
54081   attribute \enum_base_type "CryIn"
54082   attribute \enum_value_00 "ZERO"
54083   attribute \enum_value_01 "ONE"
54084   attribute \enum_value_10 "CA"
54085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54086   wire width 2 output 14 \dec31_dec_sub8_cry_in
54087   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54088   wire output 17 \dec31_dec_sub8_cry_out
54089   attribute \enum_base_type "Form"
54090   attribute \enum_value_00000 "NONE"
54091   attribute \enum_value_00001 "I"
54092   attribute \enum_value_00010 "B"
54093   attribute \enum_value_00011 "SC"
54094   attribute \enum_value_00100 "D"
54095   attribute \enum_value_00101 "DS"
54096   attribute \enum_value_00110 "DQ"
54097   attribute \enum_value_00111 "DX"
54098   attribute \enum_value_01000 "X"
54099   attribute \enum_value_01001 "XL"
54100   attribute \enum_value_01010 "XFX"
54101   attribute \enum_value_01011 "XFL"
54102   attribute \enum_value_01100 "XX1"
54103   attribute \enum_value_01101 "XX2"
54104   attribute \enum_value_01110 "XX3"
54105   attribute \enum_value_01111 "XX4"
54106   attribute \enum_value_10000 "XS"
54107   attribute \enum_value_10001 "XO"
54108   attribute \enum_value_10010 "A"
54109   attribute \enum_value_10011 "M"
54110   attribute \enum_value_10100 "MD"
54111   attribute \enum_value_10101 "MDS"
54112   attribute \enum_value_10110 "VA"
54113   attribute \enum_value_10111 "VC"
54114   attribute \enum_value_11000 "VX"
54115   attribute \enum_value_11001 "EVX"
54116   attribute \enum_value_11010 "EVS"
54117   attribute \enum_value_11011 "Z22"
54118   attribute \enum_value_11100 "Z23"
54119   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54120   wire width 5 output 3 \dec31_dec_sub8_form
54121   attribute \enum_base_type "Function"
54122   attribute \enum_value_000000000000 "NONE"
54123   attribute \enum_value_000000000010 "ALU"
54124   attribute \enum_value_000000000100 "LDST"
54125   attribute \enum_value_000000001000 "SHIFT_ROT"
54126   attribute \enum_value_000000010000 "LOGICAL"
54127   attribute \enum_value_000000100000 "BRANCH"
54128   attribute \enum_value_000001000000 "CR"
54129   attribute \enum_value_000010000000 "TRAP"
54130   attribute \enum_value_000100000000 "MUL"
54131   attribute \enum_value_001000000000 "DIV"
54132   attribute \enum_value_010000000000 "SPR"
54133   attribute \enum_value_100000000000 "MMU"
54134   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54135   wire width 12 output 1 \dec31_dec_sub8_function_unit
54136   attribute \enum_base_type "In1Sel"
54137   attribute \enum_value_000 "NONE"
54138   attribute \enum_value_001 "RA"
54139   attribute \enum_value_010 "RA_OR_ZERO"
54140   attribute \enum_value_011 "SPR"
54141   attribute \enum_value_100 "RS"
54142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54143   wire width 3 output 5 \dec31_dec_sub8_in1_sel
54144   attribute \enum_base_type "In2Sel"
54145   attribute \enum_value_0000 "NONE"
54146   attribute \enum_value_0001 "RB"
54147   attribute \enum_value_0010 "CONST_UI"
54148   attribute \enum_value_0011 "CONST_SI"
54149   attribute \enum_value_0100 "CONST_UI_HI"
54150   attribute \enum_value_0101 "CONST_SI_HI"
54151   attribute \enum_value_0110 "CONST_LI"
54152   attribute \enum_value_0111 "CONST_BD"
54153   attribute \enum_value_1000 "CONST_DS"
54154   attribute \enum_value_1001 "CONST_M1"
54155   attribute \enum_value_1010 "CONST_SH"
54156   attribute \enum_value_1011 "CONST_SH32"
54157   attribute \enum_value_1100 "SPR"
54158   attribute \enum_value_1101 "RS"
54159   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54160   wire width 4 output 6 \dec31_dec_sub8_in2_sel
54161   attribute \enum_base_type "In3Sel"
54162   attribute \enum_value_00 "NONE"
54163   attribute \enum_value_01 "RS"
54164   attribute \enum_value_10 "RB"
54165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54166   wire width 2 output 7 \dec31_dec_sub8_in3_sel
54167   attribute \enum_base_type "MicrOp"
54168   attribute \enum_value_0000000 "OP_ILLEGAL"
54169   attribute \enum_value_0000001 "OP_NOP"
54170   attribute \enum_value_0000010 "OP_ADD"
54171   attribute \enum_value_0000011 "OP_ADDPCIS"
54172   attribute \enum_value_0000100 "OP_AND"
54173   attribute \enum_value_0000101 "OP_ATTN"
54174   attribute \enum_value_0000110 "OP_B"
54175   attribute \enum_value_0000111 "OP_BC"
54176   attribute \enum_value_0001000 "OP_BCREG"
54177   attribute \enum_value_0001001 "OP_BPERM"
54178   attribute \enum_value_0001010 "OP_CMP"
54179   attribute \enum_value_0001011 "OP_CMPB"
54180   attribute \enum_value_0001100 "OP_CMPEQB"
54181   attribute \enum_value_0001101 "OP_CMPRB"
54182   attribute \enum_value_0001110 "OP_CNTZ"
54183   attribute \enum_value_0001111 "OP_CRAND"
54184   attribute \enum_value_0010000 "OP_CRANDC"
54185   attribute \enum_value_0010001 "OP_CREQV"
54186   attribute \enum_value_0010010 "OP_CRNAND"
54187   attribute \enum_value_0010011 "OP_CRNOR"
54188   attribute \enum_value_0010100 "OP_CROR"
54189   attribute \enum_value_0010101 "OP_CRORC"
54190   attribute \enum_value_0010110 "OP_CRXOR"
54191   attribute \enum_value_0010111 "OP_DARN"
54192   attribute \enum_value_0011000 "OP_DCBF"
54193   attribute \enum_value_0011001 "OP_DCBST"
54194   attribute \enum_value_0011010 "OP_DCBT"
54195   attribute \enum_value_0011011 "OP_DCBTST"
54196   attribute \enum_value_0011100 "OP_DCBZ"
54197   attribute \enum_value_0011101 "OP_DIV"
54198   attribute \enum_value_0011110 "OP_DIVE"
54199   attribute \enum_value_0011111 "OP_EXTS"
54200   attribute \enum_value_0100000 "OP_EXTSWSLI"
54201   attribute \enum_value_0100001 "OP_ICBI"
54202   attribute \enum_value_0100010 "OP_ICBT"
54203   attribute \enum_value_0100011 "OP_ISEL"
54204   attribute \enum_value_0100100 "OP_ISYNC"
54205   attribute \enum_value_0100101 "OP_LOAD"
54206   attribute \enum_value_0100110 "OP_STORE"
54207   attribute \enum_value_0100111 "OP_MADDHD"
54208   attribute \enum_value_0101000 "OP_MADDHDU"
54209   attribute \enum_value_0101001 "OP_MADDLD"
54210   attribute \enum_value_0101010 "OP_MCRF"
54211   attribute \enum_value_0101011 "OP_MCRXR"
54212   attribute \enum_value_0101100 "OP_MCRXRX"
54213   attribute \enum_value_0101101 "OP_MFCR"
54214   attribute \enum_value_0101110 "OP_MFSPR"
54215   attribute \enum_value_0101111 "OP_MOD"
54216   attribute \enum_value_0110000 "OP_MTCRF"
54217   attribute \enum_value_0110001 "OP_MTSPR"
54218   attribute \enum_value_0110010 "OP_MUL_L64"
54219   attribute \enum_value_0110011 "OP_MUL_H64"
54220   attribute \enum_value_0110100 "OP_MUL_H32"
54221   attribute \enum_value_0110101 "OP_OR"
54222   attribute \enum_value_0110110 "OP_POPCNT"
54223   attribute \enum_value_0110111 "OP_PRTY"
54224   attribute \enum_value_0111000 "OP_RLC"
54225   attribute \enum_value_0111001 "OP_RLCL"
54226   attribute \enum_value_0111010 "OP_RLCR"
54227   attribute \enum_value_0111011 "OP_SETB"
54228   attribute \enum_value_0111100 "OP_SHL"
54229   attribute \enum_value_0111101 "OP_SHR"
54230   attribute \enum_value_0111110 "OP_SYNC"
54231   attribute \enum_value_0111111 "OP_TRAP"
54232   attribute \enum_value_1000011 "OP_XOR"
54233   attribute \enum_value_1000100 "OP_SIM_CONFIG"
54234   attribute \enum_value_1000101 "OP_CROP"
54235   attribute \enum_value_1000110 "OP_RFID"
54236   attribute \enum_value_1000111 "OP_MFMSR"
54237   attribute \enum_value_1001000 "OP_MTMSRD"
54238   attribute \enum_value_1001001 "OP_SC"
54239   attribute \enum_value_1001010 "OP_MTMSR"
54240   attribute \enum_value_1001011 "OP_TLBIE"
54241   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54242   wire width 7 output 2 \dec31_dec_sub8_internal_op
54243   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54244   wire output 15 \dec31_dec_sub8_inv_a
54245   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54246   wire output 16 \dec31_dec_sub8_inv_out
54247   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54248   wire output 21 \dec31_dec_sub8_is_32b
54249   attribute \enum_base_type "LdstLen"
54250   attribute \enum_value_0000 "NONE"
54251   attribute \enum_value_0001 "is1B"
54252   attribute \enum_value_0010 "is2B"
54253   attribute \enum_value_0100 "is4B"
54254   attribute \enum_value_1000 "is8B"
54255   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54256   wire width 4 output 11 \dec31_dec_sub8_ldst_len
54257   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54258   wire output 23 \dec31_dec_sub8_lk
54259   attribute \enum_base_type "OutSel"
54260   attribute \enum_value_00 "NONE"
54261   attribute \enum_value_01 "RT"
54262   attribute \enum_value_10 "RA"
54263   attribute \enum_value_11 "SPR"
54264   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54265   wire width 2 output 8 \dec31_dec_sub8_out_sel
54266   attribute \enum_base_type "RC"
54267   attribute \enum_value_00 "NONE"
54268   attribute \enum_value_01 "ONE"
54269   attribute \enum_value_10 "RC"
54270   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54271   wire width 2 output 13 \dec31_dec_sub8_rc_sel
54272   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54273   wire output 20 \dec31_dec_sub8_rsrv
54274   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54275   wire output 24 \dec31_dec_sub8_sgl_pipe
54276   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54277   wire output 22 \dec31_dec_sub8_sgn
54278   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
54279   wire output 19 \dec31_dec_sub8_sgn_ext
54280   attribute \enum_base_type "LDSTMode"
54281   attribute \enum_value_00 "NONE"
54282   attribute \enum_value_01 "update"
54283   attribute \enum_value_10 "cix"
54284   attribute \enum_value_11 "cx"
54285   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
54286   wire width 2 output 12 \dec31_dec_sub8_upd
54287   attribute \src "libresoc.v:36388.7-36388.15"
54288   wire \initial
54289   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
54290   wire width 32 input 25 \opcode_in
54291   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
54292   wire width 5 \opcode_switch
54293   attribute \src "libresoc.v:36388.7-36388.20"
54294   process $proc$libresoc.v:36388$831
54295     assign { } { }
54296     assign $0\initial[0:0] 1'0
54297     sync always
54298       update \initial $0\initial[0:0]
54299     sync init
54300   end
54301   attribute \src "libresoc.v:36645.3-36687.6"
54302   process $proc$libresoc.v:36645$807
54303     assign { } { }
54304     assign { } { }
54305     assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0]
54306     attribute \src "libresoc.v:36646.5-36646.29"
54307     switch \initial
54308       attribute \src "libresoc.v:36646.9-36646.17"
54309       case 1'1
54310       case
54311     end
54312     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54313     switch \opcode_switch
54314       attribute \src "libresoc.v:0.0-0.0"
54315       case 5'00011
54316         assign { } { }
54317         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54318       attribute \src "libresoc.v:0.0-0.0"
54319       case 5'10011
54320         assign { } { }
54321         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54322       attribute \src "libresoc.v:0.0-0.0"
54323       case 5'00001
54324         assign { } { }
54325         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54326       attribute \src "libresoc.v:0.0-0.0"
54327       case 5'10001
54328         assign { } { }
54329         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54330       attribute \src "libresoc.v:0.0-0.0"
54331       case 5'00000
54332         assign { } { }
54333         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54334       attribute \src "libresoc.v:0.0-0.0"
54335       case 5'10000
54336         assign { } { }
54337         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54338       attribute \src "libresoc.v:0.0-0.0"
54339       case 5'00100
54340         assign { } { }
54341         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54342       attribute \src "libresoc.v:0.0-0.0"
54343       case 5'10100
54344         assign { } { }
54345         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54346       attribute \src "libresoc.v:0.0-0.0"
54347       case 5'00111
54348         assign { } { }
54349         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54350       attribute \src "libresoc.v:0.0-0.0"
54351       case 5'10111
54352         assign { } { }
54353         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54354       attribute \src "libresoc.v:0.0-0.0"
54355       case 5'00110
54356         assign { } { }
54357         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54358       attribute \src "libresoc.v:0.0-0.0"
54359       case 5'10110
54360         assign { } { }
54361         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010
54362       case
54363         assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000
54364     end
54365     sync always
54366       update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0]
54367   end
54368   attribute \src "libresoc.v:36688.3-36730.6"
54369   process $proc$libresoc.v:36688$808
54370     assign { } { }
54371     assign { } { }
54372     assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0]
54373     attribute \src "libresoc.v:36689.5-36689.29"
54374     switch \initial
54375       attribute \src "libresoc.v:36689.9-36689.17"
54376       case 1'1
54377       case
54378     end
54379     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54380     switch \opcode_switch
54381       attribute \src "libresoc.v:0.0-0.0"
54382       case 5'00011
54383         assign { } { }
54384         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54385       attribute \src "libresoc.v:0.0-0.0"
54386       case 5'10011
54387         assign { } { }
54388         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54389       attribute \src "libresoc.v:0.0-0.0"
54390       case 5'00001
54391         assign { } { }
54392         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54393       attribute \src "libresoc.v:0.0-0.0"
54394       case 5'10001
54395         assign { } { }
54396         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54397       attribute \src "libresoc.v:0.0-0.0"
54398       case 5'00000
54399         assign { } { }
54400         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54401       attribute \src "libresoc.v:0.0-0.0"
54402       case 5'10000
54403         assign { } { }
54404         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54405       attribute \src "libresoc.v:0.0-0.0"
54406       case 5'00100
54407         assign { } { }
54408         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54409       attribute \src "libresoc.v:0.0-0.0"
54410       case 5'10100
54411         assign { } { }
54412         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54413       attribute \src "libresoc.v:0.0-0.0"
54414       case 5'00111
54415         assign { } { }
54416         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54417       attribute \src "libresoc.v:0.0-0.0"
54418       case 5'10111
54419         assign { } { }
54420         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54421       attribute \src "libresoc.v:0.0-0.0"
54422       case 5'00110
54423         assign { } { }
54424         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54425       attribute \src "libresoc.v:0.0-0.0"
54426       case 5'10110
54427         assign { } { }
54428         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54429       case
54430         assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000
54431     end
54432     sync always
54433       update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0]
54434   end
54435   attribute \src "libresoc.v:36731.3-36773.6"
54436   process $proc$libresoc.v:36731$809
54437     assign { } { }
54438     assign { } { }
54439     assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0]
54440     attribute \src "libresoc.v:36732.5-36732.29"
54441     switch \initial
54442       attribute \src "libresoc.v:36732.9-36732.17"
54443       case 1'1
54444       case
54445     end
54446     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54447     switch \opcode_switch
54448       attribute \src "libresoc.v:0.0-0.0"
54449       case 5'00011
54450         assign { } { }
54451         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54452       attribute \src "libresoc.v:0.0-0.0"
54453       case 5'10011
54454         assign { } { }
54455         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54456       attribute \src "libresoc.v:0.0-0.0"
54457       case 5'00001
54458         assign { } { }
54459         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54460       attribute \src "libresoc.v:0.0-0.0"
54461       case 5'10001
54462         assign { } { }
54463         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54464       attribute \src "libresoc.v:0.0-0.0"
54465       case 5'00000
54466         assign { } { }
54467         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54468       attribute \src "libresoc.v:0.0-0.0"
54469       case 5'10000
54470         assign { } { }
54471         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54472       attribute \src "libresoc.v:0.0-0.0"
54473       case 5'00100
54474         assign { } { }
54475         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54476       attribute \src "libresoc.v:0.0-0.0"
54477       case 5'10100
54478         assign { } { }
54479         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54480       attribute \src "libresoc.v:0.0-0.0"
54481       case 5'00111
54482         assign { } { }
54483         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54484       attribute \src "libresoc.v:0.0-0.0"
54485       case 5'10111
54486         assign { } { }
54487         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54488       attribute \src "libresoc.v:0.0-0.0"
54489       case 5'00110
54490         assign { } { }
54491         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54492       attribute \src "libresoc.v:0.0-0.0"
54493       case 5'10110
54494         assign { } { }
54495         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54496       case
54497         assign $1\dec31_dec_sub8_upd[1:0] 2'00
54498     end
54499     sync always
54500       update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0]
54501   end
54502   attribute \src "libresoc.v:36774.3-36816.6"
54503   process $proc$libresoc.v:36774$810
54504     assign { } { }
54505     assign { } { }
54506     assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0]
54507     attribute \src "libresoc.v:36775.5-36775.29"
54508     switch \initial
54509       attribute \src "libresoc.v:36775.9-36775.17"
54510       case 1'1
54511       case
54512     end
54513     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54514     switch \opcode_switch
54515       attribute \src "libresoc.v:0.0-0.0"
54516       case 5'00011
54517         assign { } { }
54518         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54519       attribute \src "libresoc.v:0.0-0.0"
54520       case 5'10011
54521         assign { } { }
54522         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54523       attribute \src "libresoc.v:0.0-0.0"
54524       case 5'00001
54525         assign { } { }
54526         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54527       attribute \src "libresoc.v:0.0-0.0"
54528       case 5'10001
54529         assign { } { }
54530         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54531       attribute \src "libresoc.v:0.0-0.0"
54532       case 5'00000
54533         assign { } { }
54534         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54535       attribute \src "libresoc.v:0.0-0.0"
54536       case 5'10000
54537         assign { } { }
54538         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54539       attribute \src "libresoc.v:0.0-0.0"
54540       case 5'00100
54541         assign { } { }
54542         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54543       attribute \src "libresoc.v:0.0-0.0"
54544       case 5'10100
54545         assign { } { }
54546         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54547       attribute \src "libresoc.v:0.0-0.0"
54548       case 5'00111
54549         assign { } { }
54550         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54551       attribute \src "libresoc.v:0.0-0.0"
54552       case 5'10111
54553         assign { } { }
54554         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54555       attribute \src "libresoc.v:0.0-0.0"
54556       case 5'00110
54557         assign { } { }
54558         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54559       attribute \src "libresoc.v:0.0-0.0"
54560       case 5'10110
54561         assign { } { }
54562         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10
54563       case
54564         assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00
54565     end
54566     sync always
54567       update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0]
54568   end
54569   attribute \src "libresoc.v:36817.3-36859.6"
54570   process $proc$libresoc.v:36817$811
54571     assign { } { }
54572     assign { } { }
54573     assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0]
54574     attribute \src "libresoc.v:36818.5-36818.29"
54575     switch \initial
54576       attribute \src "libresoc.v:36818.9-36818.17"
54577       case 1'1
54578       case
54579     end
54580     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54581     switch \opcode_switch
54582       attribute \src "libresoc.v:0.0-0.0"
54583       case 5'00011
54584         assign { } { }
54585         assign $1\dec31_dec_sub8_cry_in[1:0] 2'01
54586       attribute \src "libresoc.v:0.0-0.0"
54587       case 5'10011
54588         assign { } { }
54589         assign $1\dec31_dec_sub8_cry_in[1:0] 2'01
54590       attribute \src "libresoc.v:0.0-0.0"
54591       case 5'00001
54592         assign { } { }
54593         assign $1\dec31_dec_sub8_cry_in[1:0] 2'01
54594       attribute \src "libresoc.v:0.0-0.0"
54595       case 5'10001
54596         assign { } { }
54597         assign $1\dec31_dec_sub8_cry_in[1:0] 2'01
54598       attribute \src "libresoc.v:0.0-0.0"
54599       case 5'00000
54600         assign { } { }
54601         assign $1\dec31_dec_sub8_cry_in[1:0] 2'01
54602       attribute \src "libresoc.v:0.0-0.0"
54603       case 5'10000
54604         assign { } { }
54605         assign $1\dec31_dec_sub8_cry_in[1:0] 2'01
54606       attribute \src "libresoc.v:0.0-0.0"
54607       case 5'00100
54608         assign { } { }
54609         assign $1\dec31_dec_sub8_cry_in[1:0] 2'10
54610       attribute \src "libresoc.v:0.0-0.0"
54611       case 5'10100
54612         assign { } { }
54613         assign $1\dec31_dec_sub8_cry_in[1:0] 2'10
54614       attribute \src "libresoc.v:0.0-0.0"
54615       case 5'00111
54616         assign { } { }
54617         assign $1\dec31_dec_sub8_cry_in[1:0] 2'10
54618       attribute \src "libresoc.v:0.0-0.0"
54619       case 5'10111
54620         assign { } { }
54621         assign $1\dec31_dec_sub8_cry_in[1:0] 2'10
54622       attribute \src "libresoc.v:0.0-0.0"
54623       case 5'00110
54624         assign { } { }
54625         assign $1\dec31_dec_sub8_cry_in[1:0] 2'10
54626       attribute \src "libresoc.v:0.0-0.0"
54627       case 5'10110
54628         assign { } { }
54629         assign $1\dec31_dec_sub8_cry_in[1:0] 2'10
54630       case
54631         assign $1\dec31_dec_sub8_cry_in[1:0] 2'00
54632     end
54633     sync always
54634       update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0]
54635   end
54636   attribute \src "libresoc.v:36860.3-36902.6"
54637   process $proc$libresoc.v:36860$812
54638     assign { } { }
54639     assign { } { }
54640     assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0]
54641     attribute \src "libresoc.v:36861.5-36861.29"
54642     switch \initial
54643       attribute \src "libresoc.v:36861.9-36861.17"
54644       case 1'1
54645       case
54646     end
54647     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54648     switch \opcode_switch
54649       attribute \src "libresoc.v:0.0-0.0"
54650       case 5'00011
54651         assign { } { }
54652         assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100
54653       attribute \src "libresoc.v:0.0-0.0"
54654       case 5'10011
54655         assign { } { }
54656         assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101
54657       attribute \src "libresoc.v:0.0-0.0"
54658       case 5'00001
54659         assign { } { }
54660         assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110
54661       attribute \src "libresoc.v:0.0-0.0"
54662       case 5'10001
54663         assign { } { }
54664         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110
54665       attribute \src "libresoc.v:0.0-0.0"
54666       case 5'00000
54667         assign { } { }
54668         assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111
54669       attribute \src "libresoc.v:0.0-0.0"
54670       case 5'10000
54671         assign { } { }
54672         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000
54673       attribute \src "libresoc.v:0.0-0.0"
54674       case 5'00100
54675         assign { } { }
54676         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001
54677       attribute \src "libresoc.v:0.0-0.0"
54678       case 5'10100
54679         assign { } { }
54680         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010
54681       attribute \src "libresoc.v:0.0-0.0"
54682       case 5'00111
54683         assign { } { }
54684         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100
54685       attribute \src "libresoc.v:0.0-0.0"
54686       case 5'10111
54687         assign { } { }
54688         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101
54689       attribute \src "libresoc.v:0.0-0.0"
54690       case 5'00110
54691         assign { } { }
54692         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111
54693       attribute \src "libresoc.v:0.0-0.0"
54694       case 5'10110
54695         assign { } { }
54696         assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000
54697       case
54698         assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000
54699     end
54700     sync always
54701       update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0]
54702   end
54703   attribute \src "libresoc.v:36903.3-36945.6"
54704   process $proc$libresoc.v:36903$813
54705     assign { } { }
54706     assign { } { }
54707     assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0]
54708     attribute \src "libresoc.v:36904.5-36904.29"
54709     switch \initial
54710       attribute \src "libresoc.v:36904.9-36904.17"
54711       case 1'1
54712       case
54713     end
54714     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54715     switch \opcode_switch
54716       attribute \src "libresoc.v:0.0-0.0"
54717       case 5'00011
54718         assign { } { }
54719         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54720       attribute \src "libresoc.v:0.0-0.0"
54721       case 5'10011
54722         assign { } { }
54723         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54724       attribute \src "libresoc.v:0.0-0.0"
54725       case 5'00001
54726         assign { } { }
54727         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54728       attribute \src "libresoc.v:0.0-0.0"
54729       case 5'10001
54730         assign { } { }
54731         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54732       attribute \src "libresoc.v:0.0-0.0"
54733       case 5'00000
54734         assign { } { }
54735         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54736       attribute \src "libresoc.v:0.0-0.0"
54737       case 5'10000
54738         assign { } { }
54739         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54740       attribute \src "libresoc.v:0.0-0.0"
54741       case 5'00100
54742         assign { } { }
54743         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54744       attribute \src "libresoc.v:0.0-0.0"
54745       case 5'10100
54746         assign { } { }
54747         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54748       attribute \src "libresoc.v:0.0-0.0"
54749       case 5'00111
54750         assign { } { }
54751         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54752       attribute \src "libresoc.v:0.0-0.0"
54753       case 5'10111
54754         assign { } { }
54755         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54756       attribute \src "libresoc.v:0.0-0.0"
54757       case 5'00110
54758         assign { } { }
54759         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54760       attribute \src "libresoc.v:0.0-0.0"
54761       case 5'10110
54762         assign { } { }
54763         assign $1\dec31_dec_sub8_inv_a[0:0] 1'1
54764       case
54765         assign $1\dec31_dec_sub8_inv_a[0:0] 1'0
54766     end
54767     sync always
54768       update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0]
54769   end
54770   attribute \src "libresoc.v:36946.3-36988.6"
54771   process $proc$libresoc.v:36946$814
54772     assign { } { }
54773     assign { } { }
54774     assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0]
54775     attribute \src "libresoc.v:36947.5-36947.29"
54776     switch \initial
54777       attribute \src "libresoc.v:36947.9-36947.17"
54778       case 1'1
54779       case
54780     end
54781     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54782     switch \opcode_switch
54783       attribute \src "libresoc.v:0.0-0.0"
54784       case 5'00011
54785         assign { } { }
54786         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54787       attribute \src "libresoc.v:0.0-0.0"
54788       case 5'10011
54789         assign { } { }
54790         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54791       attribute \src "libresoc.v:0.0-0.0"
54792       case 5'00001
54793         assign { } { }
54794         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54795       attribute \src "libresoc.v:0.0-0.0"
54796       case 5'10001
54797         assign { } { }
54798         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54799       attribute \src "libresoc.v:0.0-0.0"
54800       case 5'00000
54801         assign { } { }
54802         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54803       attribute \src "libresoc.v:0.0-0.0"
54804       case 5'10000
54805         assign { } { }
54806         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54807       attribute \src "libresoc.v:0.0-0.0"
54808       case 5'00100
54809         assign { } { }
54810         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54811       attribute \src "libresoc.v:0.0-0.0"
54812       case 5'10100
54813         assign { } { }
54814         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54815       attribute \src "libresoc.v:0.0-0.0"
54816       case 5'00111
54817         assign { } { }
54818         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54819       attribute \src "libresoc.v:0.0-0.0"
54820       case 5'10111
54821         assign { } { }
54822         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54823       attribute \src "libresoc.v:0.0-0.0"
54824       case 5'00110
54825         assign { } { }
54826         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54827       attribute \src "libresoc.v:0.0-0.0"
54828       case 5'10110
54829         assign { } { }
54830         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54831       case
54832         assign $1\dec31_dec_sub8_inv_out[0:0] 1'0
54833     end
54834     sync always
54835       update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0]
54836   end
54837   attribute \src "libresoc.v:36989.3-37031.6"
54838   process $proc$libresoc.v:36989$815
54839     assign { } { }
54840     assign { } { }
54841     assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0]
54842     attribute \src "libresoc.v:36990.5-36990.29"
54843     switch \initial
54844       attribute \src "libresoc.v:36990.9-36990.17"
54845       case 1'1
54846       case
54847     end
54848     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54849     switch \opcode_switch
54850       attribute \src "libresoc.v:0.0-0.0"
54851       case 5'00011
54852         assign { } { }
54853         assign $1\dec31_dec_sub8_cry_out[0:0] 1'0
54854       attribute \src "libresoc.v:0.0-0.0"
54855       case 5'10011
54856         assign { } { }
54857         assign $1\dec31_dec_sub8_cry_out[0:0] 1'0
54858       attribute \src "libresoc.v:0.0-0.0"
54859       case 5'00001
54860         assign { } { }
54861         assign $1\dec31_dec_sub8_cry_out[0:0] 1'0
54862       attribute \src "libresoc.v:0.0-0.0"
54863       case 5'10001
54864         assign { } { }
54865         assign $1\dec31_dec_sub8_cry_out[0:0] 1'0
54866       attribute \src "libresoc.v:0.0-0.0"
54867       case 5'00000
54868         assign { } { }
54869         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54870       attribute \src "libresoc.v:0.0-0.0"
54871       case 5'10000
54872         assign { } { }
54873         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54874       attribute \src "libresoc.v:0.0-0.0"
54875       case 5'00100
54876         assign { } { }
54877         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54878       attribute \src "libresoc.v:0.0-0.0"
54879       case 5'10100
54880         assign { } { }
54881         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54882       attribute \src "libresoc.v:0.0-0.0"
54883       case 5'00111
54884         assign { } { }
54885         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54886       attribute \src "libresoc.v:0.0-0.0"
54887       case 5'10111
54888         assign { } { }
54889         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54890       attribute \src "libresoc.v:0.0-0.0"
54891       case 5'00110
54892         assign { } { }
54893         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54894       attribute \src "libresoc.v:0.0-0.0"
54895       case 5'10110
54896         assign { } { }
54897         assign $1\dec31_dec_sub8_cry_out[0:0] 1'1
54898       case
54899         assign $1\dec31_dec_sub8_cry_out[0:0] 1'0
54900     end
54901     sync always
54902       update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0]
54903   end
54904   attribute \src "libresoc.v:37032.3-37074.6"
54905   process $proc$libresoc.v:37032$816
54906     assign { } { }
54907     assign { } { }
54908     assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0]
54909     attribute \src "libresoc.v:37033.5-37033.29"
54910     switch \initial
54911       attribute \src "libresoc.v:37033.9-37033.17"
54912       case 1'1
54913       case
54914     end
54915     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54916     switch \opcode_switch
54917       attribute \src "libresoc.v:0.0-0.0"
54918       case 5'00011
54919         assign { } { }
54920         assign $1\dec31_dec_sub8_br[0:0] 1'0
54921       attribute \src "libresoc.v:0.0-0.0"
54922       case 5'10011
54923         assign { } { }
54924         assign $1\dec31_dec_sub8_br[0:0] 1'0
54925       attribute \src "libresoc.v:0.0-0.0"
54926       case 5'00001
54927         assign { } { }
54928         assign $1\dec31_dec_sub8_br[0:0] 1'0
54929       attribute \src "libresoc.v:0.0-0.0"
54930       case 5'10001
54931         assign { } { }
54932         assign $1\dec31_dec_sub8_br[0:0] 1'0
54933       attribute \src "libresoc.v:0.0-0.0"
54934       case 5'00000
54935         assign { } { }
54936         assign $1\dec31_dec_sub8_br[0:0] 1'0
54937       attribute \src "libresoc.v:0.0-0.0"
54938       case 5'10000
54939         assign { } { }
54940         assign $1\dec31_dec_sub8_br[0:0] 1'0
54941       attribute \src "libresoc.v:0.0-0.0"
54942       case 5'00100
54943         assign { } { }
54944         assign $1\dec31_dec_sub8_br[0:0] 1'0
54945       attribute \src "libresoc.v:0.0-0.0"
54946       case 5'10100
54947         assign { } { }
54948         assign $1\dec31_dec_sub8_br[0:0] 1'0
54949       attribute \src "libresoc.v:0.0-0.0"
54950       case 5'00111
54951         assign { } { }
54952         assign $1\dec31_dec_sub8_br[0:0] 1'0
54953       attribute \src "libresoc.v:0.0-0.0"
54954       case 5'10111
54955         assign { } { }
54956         assign $1\dec31_dec_sub8_br[0:0] 1'0
54957       attribute \src "libresoc.v:0.0-0.0"
54958       case 5'00110
54959         assign { } { }
54960         assign $1\dec31_dec_sub8_br[0:0] 1'0
54961       attribute \src "libresoc.v:0.0-0.0"
54962       case 5'10110
54963         assign { } { }
54964         assign $1\dec31_dec_sub8_br[0:0] 1'0
54965       case
54966         assign $1\dec31_dec_sub8_br[0:0] 1'0
54967     end
54968     sync always
54969       update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0]
54970   end
54971   attribute \src "libresoc.v:37075.3-37117.6"
54972   process $proc$libresoc.v:37075$817
54973     assign { } { }
54974     assign { } { }
54975     assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0]
54976     attribute \src "libresoc.v:37076.5-37076.29"
54977     switch \initial
54978       attribute \src "libresoc.v:37076.9-37076.17"
54979       case 1'1
54980       case
54981     end
54982     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
54983     switch \opcode_switch
54984       attribute \src "libresoc.v:0.0-0.0"
54985       case 5'00011
54986         assign { } { }
54987         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
54988       attribute \src "libresoc.v:0.0-0.0"
54989       case 5'10011
54990         assign { } { }
54991         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
54992       attribute \src "libresoc.v:0.0-0.0"
54993       case 5'00001
54994         assign { } { }
54995         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
54996       attribute \src "libresoc.v:0.0-0.0"
54997       case 5'10001
54998         assign { } { }
54999         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55000       attribute \src "libresoc.v:0.0-0.0"
55001       case 5'00000
55002         assign { } { }
55003         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55004       attribute \src "libresoc.v:0.0-0.0"
55005       case 5'10000
55006         assign { } { }
55007         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55008       attribute \src "libresoc.v:0.0-0.0"
55009       case 5'00100
55010         assign { } { }
55011         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55012       attribute \src "libresoc.v:0.0-0.0"
55013       case 5'10100
55014         assign { } { }
55015         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55016       attribute \src "libresoc.v:0.0-0.0"
55017       case 5'00111
55018         assign { } { }
55019         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55020       attribute \src "libresoc.v:0.0-0.0"
55021       case 5'10111
55022         assign { } { }
55023         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55024       attribute \src "libresoc.v:0.0-0.0"
55025       case 5'00110
55026         assign { } { }
55027         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55028       attribute \src "libresoc.v:0.0-0.0"
55029       case 5'10110
55030         assign { } { }
55031         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55032       case
55033         assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0
55034     end
55035     sync always
55036       update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0]
55037   end
55038   attribute \src "libresoc.v:37118.3-37160.6"
55039   process $proc$libresoc.v:37118$818
55040     assign { } { }
55041     assign { } { }
55042     assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0]
55043     attribute \src "libresoc.v:37119.5-37119.29"
55044     switch \initial
55045       attribute \src "libresoc.v:37119.9-37119.17"
55046       case 1'1
55047       case
55048     end
55049     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55050     switch \opcode_switch
55051       attribute \src "libresoc.v:0.0-0.0"
55052       case 5'00011
55053         assign { } { }
55054         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55055       attribute \src "libresoc.v:0.0-0.0"
55056       case 5'10011
55057         assign { } { }
55058         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55059       attribute \src "libresoc.v:0.0-0.0"
55060       case 5'00001
55061         assign { } { }
55062         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55063       attribute \src "libresoc.v:0.0-0.0"
55064       case 5'10001
55065         assign { } { }
55066         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55067       attribute \src "libresoc.v:0.0-0.0"
55068       case 5'00000
55069         assign { } { }
55070         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55071       attribute \src "libresoc.v:0.0-0.0"
55072       case 5'10000
55073         assign { } { }
55074         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55075       attribute \src "libresoc.v:0.0-0.0"
55076       case 5'00100
55077         assign { } { }
55078         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55079       attribute \src "libresoc.v:0.0-0.0"
55080       case 5'10100
55081         assign { } { }
55082         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55083       attribute \src "libresoc.v:0.0-0.0"
55084       case 5'00111
55085         assign { } { }
55086         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55087       attribute \src "libresoc.v:0.0-0.0"
55088       case 5'10111
55089         assign { } { }
55090         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55091       attribute \src "libresoc.v:0.0-0.0"
55092       case 5'00110
55093         assign { } { }
55094         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55095       attribute \src "libresoc.v:0.0-0.0"
55096       case 5'10110
55097         assign { } { }
55098         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010
55099       case
55100         assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000
55101     end
55102     sync always
55103       update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0]
55104   end
55105   attribute \src "libresoc.v:37161.3-37203.6"
55106   process $proc$libresoc.v:37161$819
55107     assign { } { }
55108     assign { } { }
55109     assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0]
55110     attribute \src "libresoc.v:37162.5-37162.29"
55111     switch \initial
55112       attribute \src "libresoc.v:37162.9-37162.17"
55113       case 1'1
55114       case
55115     end
55116     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55117     switch \opcode_switch
55118       attribute \src "libresoc.v:0.0-0.0"
55119       case 5'00011
55120         assign { } { }
55121         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55122       attribute \src "libresoc.v:0.0-0.0"
55123       case 5'10011
55124         assign { } { }
55125         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55126       attribute \src "libresoc.v:0.0-0.0"
55127       case 5'00001
55128         assign { } { }
55129         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55130       attribute \src "libresoc.v:0.0-0.0"
55131       case 5'10001
55132         assign { } { }
55133         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55134       attribute \src "libresoc.v:0.0-0.0"
55135       case 5'00000
55136         assign { } { }
55137         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55138       attribute \src "libresoc.v:0.0-0.0"
55139       case 5'10000
55140         assign { } { }
55141         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55142       attribute \src "libresoc.v:0.0-0.0"
55143       case 5'00100
55144         assign { } { }
55145         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55146       attribute \src "libresoc.v:0.0-0.0"
55147       case 5'10100
55148         assign { } { }
55149         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55150       attribute \src "libresoc.v:0.0-0.0"
55151       case 5'00111
55152         assign { } { }
55153         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55154       attribute \src "libresoc.v:0.0-0.0"
55155       case 5'10111
55156         assign { } { }
55157         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55158       attribute \src "libresoc.v:0.0-0.0"
55159       case 5'00110
55160         assign { } { }
55161         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55162       attribute \src "libresoc.v:0.0-0.0"
55163       case 5'10110
55164         assign { } { }
55165         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55166       case
55167         assign $1\dec31_dec_sub8_rsrv[0:0] 1'0
55168     end
55169     sync always
55170       update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0]
55171   end
55172   attribute \src "libresoc.v:37204.3-37246.6"
55173   process $proc$libresoc.v:37204$820
55174     assign { } { }
55175     assign { } { }
55176     assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0]
55177     attribute \src "libresoc.v:37205.5-37205.29"
55178     switch \initial
55179       attribute \src "libresoc.v:37205.9-37205.17"
55180       case 1'1
55181       case
55182     end
55183     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55184     switch \opcode_switch
55185       attribute \src "libresoc.v:0.0-0.0"
55186       case 5'00011
55187         assign { } { }
55188         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55189       attribute \src "libresoc.v:0.0-0.0"
55190       case 5'10011
55191         assign { } { }
55192         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55193       attribute \src "libresoc.v:0.0-0.0"
55194       case 5'00001
55195         assign { } { }
55196         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55197       attribute \src "libresoc.v:0.0-0.0"
55198       case 5'10001
55199         assign { } { }
55200         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55201       attribute \src "libresoc.v:0.0-0.0"
55202       case 5'00000
55203         assign { } { }
55204         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55205       attribute \src "libresoc.v:0.0-0.0"
55206       case 5'10000
55207         assign { } { }
55208         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55209       attribute \src "libresoc.v:0.0-0.0"
55210       case 5'00100
55211         assign { } { }
55212         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55213       attribute \src "libresoc.v:0.0-0.0"
55214       case 5'10100
55215         assign { } { }
55216         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55217       attribute \src "libresoc.v:0.0-0.0"
55218       case 5'00111
55219         assign { } { }
55220         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55221       attribute \src "libresoc.v:0.0-0.0"
55222       case 5'10111
55223         assign { } { }
55224         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55225       attribute \src "libresoc.v:0.0-0.0"
55226       case 5'00110
55227         assign { } { }
55228         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55229       attribute \src "libresoc.v:0.0-0.0"
55230       case 5'10110
55231         assign { } { }
55232         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55233       case
55234         assign $1\dec31_dec_sub8_is_32b[0:0] 1'0
55235     end
55236     sync always
55237       update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0]
55238   end
55239   attribute \src "libresoc.v:37247.3-37289.6"
55240   process $proc$libresoc.v:37247$821
55241     assign { } { }
55242     assign { } { }
55243     assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0]
55244     attribute \src "libresoc.v:37248.5-37248.29"
55245     switch \initial
55246       attribute \src "libresoc.v:37248.9-37248.17"
55247       case 1'1
55248       case
55249     end
55250     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55251     switch \opcode_switch
55252       attribute \src "libresoc.v:0.0-0.0"
55253       case 5'00011
55254         assign { } { }
55255         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55256       attribute \src "libresoc.v:0.0-0.0"
55257       case 5'10011
55258         assign { } { }
55259         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55260       attribute \src "libresoc.v:0.0-0.0"
55261       case 5'00001
55262         assign { } { }
55263         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55264       attribute \src "libresoc.v:0.0-0.0"
55265       case 5'10001
55266         assign { } { }
55267         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55268       attribute \src "libresoc.v:0.0-0.0"
55269       case 5'00000
55270         assign { } { }
55271         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55272       attribute \src "libresoc.v:0.0-0.0"
55273       case 5'10000
55274         assign { } { }
55275         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55276       attribute \src "libresoc.v:0.0-0.0"
55277       case 5'00100
55278         assign { } { }
55279         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55280       attribute \src "libresoc.v:0.0-0.0"
55281       case 5'10100
55282         assign { } { }
55283         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55284       attribute \src "libresoc.v:0.0-0.0"
55285       case 5'00111
55286         assign { } { }
55287         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55288       attribute \src "libresoc.v:0.0-0.0"
55289       case 5'10111
55290         assign { } { }
55291         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55292       attribute \src "libresoc.v:0.0-0.0"
55293       case 5'00110
55294         assign { } { }
55295         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55296       attribute \src "libresoc.v:0.0-0.0"
55297       case 5'10110
55298         assign { } { }
55299         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55300       case
55301         assign $1\dec31_dec_sub8_sgn[0:0] 1'0
55302     end
55303     sync always
55304       update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0]
55305   end
55306   attribute \src "libresoc.v:37290.3-37332.6"
55307   process $proc$libresoc.v:37290$822
55308     assign { } { }
55309     assign { } { }
55310     assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0]
55311     attribute \src "libresoc.v:37291.5-37291.29"
55312     switch \initial
55313       attribute \src "libresoc.v:37291.9-37291.17"
55314       case 1'1
55315       case
55316     end
55317     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55318     switch \opcode_switch
55319       attribute \src "libresoc.v:0.0-0.0"
55320       case 5'00011
55321         assign { } { }
55322         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55323       attribute \src "libresoc.v:0.0-0.0"
55324       case 5'10011
55325         assign { } { }
55326         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55327       attribute \src "libresoc.v:0.0-0.0"
55328       case 5'00001
55329         assign { } { }
55330         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55331       attribute \src "libresoc.v:0.0-0.0"
55332       case 5'10001
55333         assign { } { }
55334         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55335       attribute \src "libresoc.v:0.0-0.0"
55336       case 5'00000
55337         assign { } { }
55338         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55339       attribute \src "libresoc.v:0.0-0.0"
55340       case 5'10000
55341         assign { } { }
55342         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55343       attribute \src "libresoc.v:0.0-0.0"
55344       case 5'00100
55345         assign { } { }
55346         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55347       attribute \src "libresoc.v:0.0-0.0"
55348       case 5'10100
55349         assign { } { }
55350         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55351       attribute \src "libresoc.v:0.0-0.0"
55352       case 5'00111
55353         assign { } { }
55354         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55355       attribute \src "libresoc.v:0.0-0.0"
55356       case 5'10111
55357         assign { } { }
55358         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55359       attribute \src "libresoc.v:0.0-0.0"
55360       case 5'00110
55361         assign { } { }
55362         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55363       attribute \src "libresoc.v:0.0-0.0"
55364       case 5'10110
55365         assign { } { }
55366         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55367       case
55368         assign $1\dec31_dec_sub8_lk[0:0] 1'0
55369     end
55370     sync always
55371       update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0]
55372   end
55373   attribute \src "libresoc.v:37333.3-37375.6"
55374   process $proc$libresoc.v:37333$823
55375     assign { } { }
55376     assign { } { }
55377     assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0]
55378     attribute \src "libresoc.v:37334.5-37334.29"
55379     switch \initial
55380       attribute \src "libresoc.v:37334.9-37334.17"
55381       case 1'1
55382       case
55383     end
55384     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55385     switch \opcode_switch
55386       attribute \src "libresoc.v:0.0-0.0"
55387       case 5'00011
55388         assign { } { }
55389         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55390       attribute \src "libresoc.v:0.0-0.0"
55391       case 5'10011
55392         assign { } { }
55393         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55394       attribute \src "libresoc.v:0.0-0.0"
55395       case 5'00001
55396         assign { } { }
55397         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55398       attribute \src "libresoc.v:0.0-0.0"
55399       case 5'10001
55400         assign { } { }
55401         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55402       attribute \src "libresoc.v:0.0-0.0"
55403       case 5'00000
55404         assign { } { }
55405         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55406       attribute \src "libresoc.v:0.0-0.0"
55407       case 5'10000
55408         assign { } { }
55409         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55410       attribute \src "libresoc.v:0.0-0.0"
55411       case 5'00100
55412         assign { } { }
55413         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55414       attribute \src "libresoc.v:0.0-0.0"
55415       case 5'10100
55416         assign { } { }
55417         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55418       attribute \src "libresoc.v:0.0-0.0"
55419       case 5'00111
55420         assign { } { }
55421         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55422       attribute \src "libresoc.v:0.0-0.0"
55423       case 5'10111
55424         assign { } { }
55425         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55426       attribute \src "libresoc.v:0.0-0.0"
55427       case 5'00110
55428         assign { } { }
55429         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55430       attribute \src "libresoc.v:0.0-0.0"
55431       case 5'10110
55432         assign { } { }
55433         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55434       case
55435         assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0
55436     end
55437     sync always
55438       update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0]
55439   end
55440   attribute \src "libresoc.v:37376.3-37418.6"
55441   process $proc$libresoc.v:37376$824
55442     assign { } { }
55443     assign { } { }
55444     assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0]
55445     attribute \src "libresoc.v:37377.5-37377.29"
55446     switch \initial
55447       attribute \src "libresoc.v:37377.9-37377.17"
55448       case 1'1
55449       case
55450     end
55451     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55452     switch \opcode_switch
55453       attribute \src "libresoc.v:0.0-0.0"
55454       case 5'00011
55455         assign { } { }
55456         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55457       attribute \src "libresoc.v:0.0-0.0"
55458       case 5'10011
55459         assign { } { }
55460         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55461       attribute \src "libresoc.v:0.0-0.0"
55462       case 5'00001
55463         assign { } { }
55464         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55465       attribute \src "libresoc.v:0.0-0.0"
55466       case 5'10001
55467         assign { } { }
55468         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55469       attribute \src "libresoc.v:0.0-0.0"
55470       case 5'00000
55471         assign { } { }
55472         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55473       attribute \src "libresoc.v:0.0-0.0"
55474       case 5'10000
55475         assign { } { }
55476         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55477       attribute \src "libresoc.v:0.0-0.0"
55478       case 5'00100
55479         assign { } { }
55480         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55481       attribute \src "libresoc.v:0.0-0.0"
55482       case 5'10100
55483         assign { } { }
55484         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55485       attribute \src "libresoc.v:0.0-0.0"
55486       case 5'00111
55487         assign { } { }
55488         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55489       attribute \src "libresoc.v:0.0-0.0"
55490       case 5'10111
55491         assign { } { }
55492         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55493       attribute \src "libresoc.v:0.0-0.0"
55494       case 5'00110
55495         assign { } { }
55496         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55497       attribute \src "libresoc.v:0.0-0.0"
55498       case 5'10110
55499         assign { } { }
55500         assign $1\dec31_dec_sub8_form[4:0] 5'10001
55501       case
55502         assign $1\dec31_dec_sub8_form[4:0] 5'00000
55503     end
55504     sync always
55505       update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0]
55506   end
55507   attribute \src "libresoc.v:37419.3-37461.6"
55508   process $proc$libresoc.v:37419$825
55509     assign { } { }
55510     assign { } { }
55511     assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0]
55512     attribute \src "libresoc.v:37420.5-37420.29"
55513     switch \initial
55514       attribute \src "libresoc.v:37420.9-37420.17"
55515       case 1'1
55516       case
55517     end
55518     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55519     switch \opcode_switch
55520       attribute \src "libresoc.v:0.0-0.0"
55521       case 5'00011
55522         assign { } { }
55523         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55524       attribute \src "libresoc.v:0.0-0.0"
55525       case 5'10011
55526         assign { } { }
55527         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55528       attribute \src "libresoc.v:0.0-0.0"
55529       case 5'00001
55530         assign { } { }
55531         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55532       attribute \src "libresoc.v:0.0-0.0"
55533       case 5'10001
55534         assign { } { }
55535         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55536       attribute \src "libresoc.v:0.0-0.0"
55537       case 5'00000
55538         assign { } { }
55539         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55540       attribute \src "libresoc.v:0.0-0.0"
55541       case 5'10000
55542         assign { } { }
55543         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55544       attribute \src "libresoc.v:0.0-0.0"
55545       case 5'00100
55546         assign { } { }
55547         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55548       attribute \src "libresoc.v:0.0-0.0"
55549       case 5'10100
55550         assign { } { }
55551         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55552       attribute \src "libresoc.v:0.0-0.0"
55553       case 5'00111
55554         assign { } { }
55555         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55556       attribute \src "libresoc.v:0.0-0.0"
55557       case 5'10111
55558         assign { } { }
55559         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55560       attribute \src "libresoc.v:0.0-0.0"
55561       case 5'00110
55562         assign { } { }
55563         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55564       attribute \src "libresoc.v:0.0-0.0"
55565       case 5'10110
55566         assign { } { }
55567         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001
55568       case
55569         assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000
55570     end
55571     sync always
55572       update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0]
55573   end
55574   attribute \src "libresoc.v:37462.3-37504.6"
55575   process $proc$libresoc.v:37462$826
55576     assign { } { }
55577     assign { } { }
55578     assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0]
55579     attribute \src "libresoc.v:37463.5-37463.29"
55580     switch \initial
55581       attribute \src "libresoc.v:37463.9-37463.17"
55582       case 1'1
55583       case
55584     end
55585     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55586     switch \opcode_switch
55587       attribute \src "libresoc.v:0.0-0.0"
55588       case 5'00011
55589         assign { } { }
55590         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000
55591       attribute \src "libresoc.v:0.0-0.0"
55592       case 5'10011
55593         assign { } { }
55594         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000
55595       attribute \src "libresoc.v:0.0-0.0"
55596       case 5'00001
55597         assign { } { }
55598         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001
55599       attribute \src "libresoc.v:0.0-0.0"
55600       case 5'10001
55601         assign { } { }
55602         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001
55603       attribute \src "libresoc.v:0.0-0.0"
55604       case 5'00000
55605         assign { } { }
55606         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001
55607       attribute \src "libresoc.v:0.0-0.0"
55608       case 5'10000
55609         assign { } { }
55610         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001
55611       attribute \src "libresoc.v:0.0-0.0"
55612       case 5'00100
55613         assign { } { }
55614         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001
55615       attribute \src "libresoc.v:0.0-0.0"
55616       case 5'10100
55617         assign { } { }
55618         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001
55619       attribute \src "libresoc.v:0.0-0.0"
55620       case 5'00111
55621         assign { } { }
55622         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001
55623       attribute \src "libresoc.v:0.0-0.0"
55624       case 5'10111
55625         assign { } { }
55626         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001
55627       attribute \src "libresoc.v:0.0-0.0"
55628       case 5'00110
55629         assign { } { }
55630         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000
55631       attribute \src "libresoc.v:0.0-0.0"
55632       case 5'10110
55633         assign { } { }
55634         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000
55635       case
55636         assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000
55637     end
55638     sync always
55639       update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0]
55640   end
55641   attribute \src "libresoc.v:37505.3-37547.6"
55642   process $proc$libresoc.v:37505$827
55643     assign { } { }
55644     assign { } { }
55645     assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0]
55646     attribute \src "libresoc.v:37506.5-37506.29"
55647     switch \initial
55648       attribute \src "libresoc.v:37506.9-37506.17"
55649       case 1'1
55650       case
55651     end
55652     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55653     switch \opcode_switch
55654       attribute \src "libresoc.v:0.0-0.0"
55655       case 5'00011
55656         assign { } { }
55657         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55658       attribute \src "libresoc.v:0.0-0.0"
55659       case 5'10011
55660         assign { } { }
55661         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55662       attribute \src "libresoc.v:0.0-0.0"
55663       case 5'00001
55664         assign { } { }
55665         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55666       attribute \src "libresoc.v:0.0-0.0"
55667       case 5'10001
55668         assign { } { }
55669         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55670       attribute \src "libresoc.v:0.0-0.0"
55671       case 5'00000
55672         assign { } { }
55673         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55674       attribute \src "libresoc.v:0.0-0.0"
55675       case 5'10000
55676         assign { } { }
55677         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55678       attribute \src "libresoc.v:0.0-0.0"
55679       case 5'00100
55680         assign { } { }
55681         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55682       attribute \src "libresoc.v:0.0-0.0"
55683       case 5'10100
55684         assign { } { }
55685         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55686       attribute \src "libresoc.v:0.0-0.0"
55687       case 5'00111
55688         assign { } { }
55689         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55690       attribute \src "libresoc.v:0.0-0.0"
55691       case 5'10111
55692         assign { } { }
55693         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55694       attribute \src "libresoc.v:0.0-0.0"
55695       case 5'00110
55696         assign { } { }
55697         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55698       attribute \src "libresoc.v:0.0-0.0"
55699       case 5'10110
55700         assign { } { }
55701         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55702       case
55703         assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00
55704     end
55705     sync always
55706       update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0]
55707   end
55708   attribute \src "libresoc.v:37548.3-37590.6"
55709   process $proc$libresoc.v:37548$828
55710     assign { } { }
55711     assign { } { }
55712     assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0]
55713     attribute \src "libresoc.v:37549.5-37549.29"
55714     switch \initial
55715       attribute \src "libresoc.v:37549.9-37549.17"
55716       case 1'1
55717       case
55718     end
55719     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55720     switch \opcode_switch
55721       attribute \src "libresoc.v:0.0-0.0"
55722       case 5'00011
55723         assign { } { }
55724         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55725       attribute \src "libresoc.v:0.0-0.0"
55726       case 5'10011
55727         assign { } { }
55728         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55729       attribute \src "libresoc.v:0.0-0.0"
55730       case 5'00001
55731         assign { } { }
55732         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55733       attribute \src "libresoc.v:0.0-0.0"
55734       case 5'10001
55735         assign { } { }
55736         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55737       attribute \src "libresoc.v:0.0-0.0"
55738       case 5'00000
55739         assign { } { }
55740         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55741       attribute \src "libresoc.v:0.0-0.0"
55742       case 5'10000
55743         assign { } { }
55744         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55745       attribute \src "libresoc.v:0.0-0.0"
55746       case 5'00100
55747         assign { } { }
55748         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55749       attribute \src "libresoc.v:0.0-0.0"
55750       case 5'10100
55751         assign { } { }
55752         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55753       attribute \src "libresoc.v:0.0-0.0"
55754       case 5'00111
55755         assign { } { }
55756         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55757       attribute \src "libresoc.v:0.0-0.0"
55758       case 5'10111
55759         assign { } { }
55760         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55761       attribute \src "libresoc.v:0.0-0.0"
55762       case 5'00110
55763         assign { } { }
55764         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55765       attribute \src "libresoc.v:0.0-0.0"
55766       case 5'10110
55767         assign { } { }
55768         assign $1\dec31_dec_sub8_out_sel[1:0] 2'01
55769       case
55770         assign $1\dec31_dec_sub8_out_sel[1:0] 2'00
55771     end
55772     sync always
55773       update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0]
55774   end
55775   attribute \src "libresoc.v:37591.3-37633.6"
55776   process $proc$libresoc.v:37591$829
55777     assign { } { }
55778     assign { } { }
55779     assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0]
55780     attribute \src "libresoc.v:37592.5-37592.29"
55781     switch \initial
55782       attribute \src "libresoc.v:37592.9-37592.17"
55783       case 1'1
55784       case
55785     end
55786     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55787     switch \opcode_switch
55788       attribute \src "libresoc.v:0.0-0.0"
55789       case 5'00011
55790         assign { } { }
55791         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55792       attribute \src "libresoc.v:0.0-0.0"
55793       case 5'10011
55794         assign { } { }
55795         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55796       attribute \src "libresoc.v:0.0-0.0"
55797       case 5'00001
55798         assign { } { }
55799         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55800       attribute \src "libresoc.v:0.0-0.0"
55801       case 5'10001
55802         assign { } { }
55803         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55804       attribute \src "libresoc.v:0.0-0.0"
55805       case 5'00000
55806         assign { } { }
55807         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55808       attribute \src "libresoc.v:0.0-0.0"
55809       case 5'10000
55810         assign { } { }
55811         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55812       attribute \src "libresoc.v:0.0-0.0"
55813       case 5'00100
55814         assign { } { }
55815         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55816       attribute \src "libresoc.v:0.0-0.0"
55817       case 5'10100
55818         assign { } { }
55819         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55820       attribute \src "libresoc.v:0.0-0.0"
55821       case 5'00111
55822         assign { } { }
55823         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55824       attribute \src "libresoc.v:0.0-0.0"
55825       case 5'10111
55826         assign { } { }
55827         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55828       attribute \src "libresoc.v:0.0-0.0"
55829       case 5'00110
55830         assign { } { }
55831         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55832       attribute \src "libresoc.v:0.0-0.0"
55833       case 5'10110
55834         assign { } { }
55835         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55836       case
55837         assign $1\dec31_dec_sub8_cr_in[2:0] 3'000
55838     end
55839     sync always
55840       update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0]
55841   end
55842   attribute \src "libresoc.v:37634.3-37676.6"
55843   process $proc$libresoc.v:37634$830
55844     assign { } { }
55845     assign { } { }
55846     assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0]
55847     attribute \src "libresoc.v:37635.5-37635.29"
55848     switch \initial
55849       attribute \src "libresoc.v:37635.9-37635.17"
55850       case 1'1
55851       case
55852     end
55853     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
55854     switch \opcode_switch
55855       attribute \src "libresoc.v:0.0-0.0"
55856       case 5'00011
55857         assign { } { }
55858         assign $1\dec31_dec_sub8_cr_out[2:0] 3'000
55859       attribute \src "libresoc.v:0.0-0.0"
55860       case 5'10011
55861         assign { } { }
55862         assign $1\dec31_dec_sub8_cr_out[2:0] 3'000
55863       attribute \src "libresoc.v:0.0-0.0"
55864       case 5'00001
55865         assign { } { }
55866         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55867       attribute \src "libresoc.v:0.0-0.0"
55868       case 5'10001
55869         assign { } { }
55870         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55871       attribute \src "libresoc.v:0.0-0.0"
55872       case 5'00000
55873         assign { } { }
55874         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55875       attribute \src "libresoc.v:0.0-0.0"
55876       case 5'10000
55877         assign { } { }
55878         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55879       attribute \src "libresoc.v:0.0-0.0"
55880       case 5'00100
55881         assign { } { }
55882         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55883       attribute \src "libresoc.v:0.0-0.0"
55884       case 5'10100
55885         assign { } { }
55886         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55887       attribute \src "libresoc.v:0.0-0.0"
55888       case 5'00111
55889         assign { } { }
55890         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55891       attribute \src "libresoc.v:0.0-0.0"
55892       case 5'10111
55893         assign { } { }
55894         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55895       attribute \src "libresoc.v:0.0-0.0"
55896       case 5'00110
55897         assign { } { }
55898         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55899       attribute \src "libresoc.v:0.0-0.0"
55900       case 5'10110
55901         assign { } { }
55902         assign $1\dec31_dec_sub8_cr_out[2:0] 3'001
55903       case
55904         assign $1\dec31_dec_sub8_cr_out[2:0] 3'000
55905     end
55906     sync always
55907       update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0]
55908   end
55909   connect \opcode_switch \opcode_in [10:6]
55910 end
55911 attribute \src "libresoc.v:37682.1-39261.10"
55912 attribute \cells_not_processed 1
55913 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9"
55914 attribute \generator "nMigen"
55915 module \dec31_dec_sub9
55916   attribute \src "libresoc.v:38215.3-38269.6"
55917   wire width 8 $0\dec31_dec_sub9_asmcode[7:0]
55918   attribute \src "libresoc.v:38435.3-38489.6"
55919   wire $0\dec31_dec_sub9_br[0:0]
55920   attribute \src "libresoc.v:39150.3-39204.6"
55921   wire width 3 $0\dec31_dec_sub9_cr_in[2:0]
55922   attribute \src "libresoc.v:39205.3-39259.6"
55923   wire width 3 $0\dec31_dec_sub9_cr_out[2:0]
55924   attribute \src "libresoc.v:38160.3-38214.6"
55925   wire width 2 $0\dec31_dec_sub9_cry_in[1:0]
55926   attribute \src "libresoc.v:38380.3-38434.6"
55927   wire $0\dec31_dec_sub9_cry_out[0:0]
55928   attribute \src "libresoc.v:38875.3-38929.6"
55929   wire width 5 $0\dec31_dec_sub9_form[4:0]
55930   attribute \src "libresoc.v:37940.3-37994.6"
55931   wire width 12 $0\dec31_dec_sub9_function_unit[11:0]
55932   attribute \src "libresoc.v:38930.3-38984.6"
55933   wire width 3 $0\dec31_dec_sub9_in1_sel[2:0]
55934   attribute \src "libresoc.v:38985.3-39039.6"
55935   wire width 4 $0\dec31_dec_sub9_in2_sel[3:0]
55936   attribute \src "libresoc.v:39040.3-39094.6"
55937   wire width 2 $0\dec31_dec_sub9_in3_sel[1:0]
55938   attribute \src "libresoc.v:38545.3-38599.6"
55939   wire width 7 $0\dec31_dec_sub9_internal_op[6:0]
55940   attribute \src "libresoc.v:38270.3-38324.6"
55941   wire $0\dec31_dec_sub9_inv_a[0:0]
55942   attribute \src "libresoc.v:38325.3-38379.6"
55943   wire $0\dec31_dec_sub9_inv_out[0:0]
55944   attribute \src "libresoc.v:38655.3-38709.6"
55945   wire $0\dec31_dec_sub9_is_32b[0:0]
55946   attribute \src "libresoc.v:37995.3-38049.6"
55947   wire width 4 $0\dec31_dec_sub9_ldst_len[3:0]
55948   attribute \src "libresoc.v:38765.3-38819.6"
55949   wire $0\dec31_dec_sub9_lk[0:0]
55950   attribute \src "libresoc.v:39095.3-39149.6"
55951   wire width 2 $0\dec31_dec_sub9_out_sel[1:0]
55952   attribute \src "libresoc.v:38105.3-38159.6"
55953   wire width 2 $0\dec31_dec_sub9_rc_sel[1:0]
55954   attribute \src "libresoc.v:38600.3-38654.6"
55955   wire $0\dec31_dec_sub9_rsrv[0:0]
55956   attribute \src "libresoc.v:38820.3-38874.6"
55957   wire $0\dec31_dec_sub9_sgl_pipe[0:0]
55958   attribute \src "libresoc.v:38710.3-38764.6"
55959   wire $0\dec31_dec_sub9_sgn[0:0]
55960   attribute \src "libresoc.v:38490.3-38544.6"
55961   wire $0\dec31_dec_sub9_sgn_ext[0:0]
55962   attribute \src "libresoc.v:38050.3-38104.6"
55963   wire width 2 $0\dec31_dec_sub9_upd[1:0]
55964   attribute \src "libresoc.v:37683.7-37683.20"
55965   wire $0\initial[0:0]
55966   attribute \src "libresoc.v:38215.3-38269.6"
55967   wire width 8 $1\dec31_dec_sub9_asmcode[7:0]
55968   attribute \src "libresoc.v:38435.3-38489.6"
55969   wire $1\dec31_dec_sub9_br[0:0]
55970   attribute \src "libresoc.v:39150.3-39204.6"
55971   wire width 3 $1\dec31_dec_sub9_cr_in[2:0]
55972   attribute \src "libresoc.v:39205.3-39259.6"
55973   wire width 3 $1\dec31_dec_sub9_cr_out[2:0]
55974   attribute \src "libresoc.v:38160.3-38214.6"
55975   wire width 2 $1\dec31_dec_sub9_cry_in[1:0]
55976   attribute \src "libresoc.v:38380.3-38434.6"
55977   wire $1\dec31_dec_sub9_cry_out[0:0]
55978   attribute \src "libresoc.v:38875.3-38929.6"
55979   wire width 5 $1\dec31_dec_sub9_form[4:0]
55980   attribute \src "libresoc.v:37940.3-37994.6"
55981   wire width 12 $1\dec31_dec_sub9_function_unit[11:0]
55982   attribute \src "libresoc.v:38930.3-38984.6"
55983   wire width 3 $1\dec31_dec_sub9_in1_sel[2:0]
55984   attribute \src "libresoc.v:38985.3-39039.6"
55985   wire width 4 $1\dec31_dec_sub9_in2_sel[3:0]
55986   attribute \src "libresoc.v:39040.3-39094.6"
55987   wire width 2 $1\dec31_dec_sub9_in3_sel[1:0]
55988   attribute \src "libresoc.v:38545.3-38599.6"
55989   wire width 7 $1\dec31_dec_sub9_internal_op[6:0]
55990   attribute \src "libresoc.v:38270.3-38324.6"
55991   wire $1\dec31_dec_sub9_inv_a[0:0]
55992   attribute \src "libresoc.v:38325.3-38379.6"
55993   wire $1\dec31_dec_sub9_inv_out[0:0]
55994   attribute \src "libresoc.v:38655.3-38709.6"
55995   wire $1\dec31_dec_sub9_is_32b[0:0]
55996   attribute \src "libresoc.v:37995.3-38049.6"
55997   wire width 4 $1\dec31_dec_sub9_ldst_len[3:0]
55998   attribute \src "libresoc.v:38765.3-38819.6"
55999   wire $1\dec31_dec_sub9_lk[0:0]
56000   attribute \src "libresoc.v:39095.3-39149.6"
56001   wire width 2 $1\dec31_dec_sub9_out_sel[1:0]
56002   attribute \src "libresoc.v:38105.3-38159.6"
56003   wire width 2 $1\dec31_dec_sub9_rc_sel[1:0]
56004   attribute \src "libresoc.v:38600.3-38654.6"
56005   wire $1\dec31_dec_sub9_rsrv[0:0]
56006   attribute \src "libresoc.v:38820.3-38874.6"
56007   wire $1\dec31_dec_sub9_sgl_pipe[0:0]
56008   attribute \src "libresoc.v:38710.3-38764.6"
56009   wire $1\dec31_dec_sub9_sgn[0:0]
56010   attribute \src "libresoc.v:38490.3-38544.6"
56011   wire $1\dec31_dec_sub9_sgn_ext[0:0]
56012   attribute \src "libresoc.v:38050.3-38104.6"
56013   wire width 2 $1\dec31_dec_sub9_upd[1:0]
56014   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56015   wire width 8 output 4 \dec31_dec_sub9_asmcode
56016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56017   wire output 18 \dec31_dec_sub9_br
56018   attribute \enum_base_type "CRInSel"
56019   attribute \enum_value_000 "NONE"
56020   attribute \enum_value_001 "CR0"
56021   attribute \enum_value_010 "BI"
56022   attribute \enum_value_011 "BFA"
56023   attribute \enum_value_100 "BA_BB"
56024   attribute \enum_value_101 "BC"
56025   attribute \enum_value_110 "WHOLE_REG"
56026   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56027   wire width 3 output 9 \dec31_dec_sub9_cr_in
56028   attribute \enum_base_type "CROutSel"
56029   attribute \enum_value_000 "NONE"
56030   attribute \enum_value_001 "CR0"
56031   attribute \enum_value_010 "BF"
56032   attribute \enum_value_011 "BT"
56033   attribute \enum_value_100 "WHOLE_REG"
56034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56035   wire width 3 output 10 \dec31_dec_sub9_cr_out
56036   attribute \enum_base_type "CryIn"
56037   attribute \enum_value_00 "ZERO"
56038   attribute \enum_value_01 "ONE"
56039   attribute \enum_value_10 "CA"
56040   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56041   wire width 2 output 14 \dec31_dec_sub9_cry_in
56042   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56043   wire output 17 \dec31_dec_sub9_cry_out
56044   attribute \enum_base_type "Form"
56045   attribute \enum_value_00000 "NONE"
56046   attribute \enum_value_00001 "I"
56047   attribute \enum_value_00010 "B"
56048   attribute \enum_value_00011 "SC"
56049   attribute \enum_value_00100 "D"
56050   attribute \enum_value_00101 "DS"
56051   attribute \enum_value_00110 "DQ"
56052   attribute \enum_value_00111 "DX"
56053   attribute \enum_value_01000 "X"
56054   attribute \enum_value_01001 "XL"
56055   attribute \enum_value_01010 "XFX"
56056   attribute \enum_value_01011 "XFL"
56057   attribute \enum_value_01100 "XX1"
56058   attribute \enum_value_01101 "XX2"
56059   attribute \enum_value_01110 "XX3"
56060   attribute \enum_value_01111 "XX4"
56061   attribute \enum_value_10000 "XS"
56062   attribute \enum_value_10001 "XO"
56063   attribute \enum_value_10010 "A"
56064   attribute \enum_value_10011 "M"
56065   attribute \enum_value_10100 "MD"
56066   attribute \enum_value_10101 "MDS"
56067   attribute \enum_value_10110 "VA"
56068   attribute \enum_value_10111 "VC"
56069   attribute \enum_value_11000 "VX"
56070   attribute \enum_value_11001 "EVX"
56071   attribute \enum_value_11010 "EVS"
56072   attribute \enum_value_11011 "Z22"
56073   attribute \enum_value_11100 "Z23"
56074   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56075   wire width 5 output 3 \dec31_dec_sub9_form
56076   attribute \enum_base_type "Function"
56077   attribute \enum_value_000000000000 "NONE"
56078   attribute \enum_value_000000000010 "ALU"
56079   attribute \enum_value_000000000100 "LDST"
56080   attribute \enum_value_000000001000 "SHIFT_ROT"
56081   attribute \enum_value_000000010000 "LOGICAL"
56082   attribute \enum_value_000000100000 "BRANCH"
56083   attribute \enum_value_000001000000 "CR"
56084   attribute \enum_value_000010000000 "TRAP"
56085   attribute \enum_value_000100000000 "MUL"
56086   attribute \enum_value_001000000000 "DIV"
56087   attribute \enum_value_010000000000 "SPR"
56088   attribute \enum_value_100000000000 "MMU"
56089   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56090   wire width 12 output 1 \dec31_dec_sub9_function_unit
56091   attribute \enum_base_type "In1Sel"
56092   attribute \enum_value_000 "NONE"
56093   attribute \enum_value_001 "RA"
56094   attribute \enum_value_010 "RA_OR_ZERO"
56095   attribute \enum_value_011 "SPR"
56096   attribute \enum_value_100 "RS"
56097   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56098   wire width 3 output 5 \dec31_dec_sub9_in1_sel
56099   attribute \enum_base_type "In2Sel"
56100   attribute \enum_value_0000 "NONE"
56101   attribute \enum_value_0001 "RB"
56102   attribute \enum_value_0010 "CONST_UI"
56103   attribute \enum_value_0011 "CONST_SI"
56104   attribute \enum_value_0100 "CONST_UI_HI"
56105   attribute \enum_value_0101 "CONST_SI_HI"
56106   attribute \enum_value_0110 "CONST_LI"
56107   attribute \enum_value_0111 "CONST_BD"
56108   attribute \enum_value_1000 "CONST_DS"
56109   attribute \enum_value_1001 "CONST_M1"
56110   attribute \enum_value_1010 "CONST_SH"
56111   attribute \enum_value_1011 "CONST_SH32"
56112   attribute \enum_value_1100 "SPR"
56113   attribute \enum_value_1101 "RS"
56114   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56115   wire width 4 output 6 \dec31_dec_sub9_in2_sel
56116   attribute \enum_base_type "In3Sel"
56117   attribute \enum_value_00 "NONE"
56118   attribute \enum_value_01 "RS"
56119   attribute \enum_value_10 "RB"
56120   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56121   wire width 2 output 7 \dec31_dec_sub9_in3_sel
56122   attribute \enum_base_type "MicrOp"
56123   attribute \enum_value_0000000 "OP_ILLEGAL"
56124   attribute \enum_value_0000001 "OP_NOP"
56125   attribute \enum_value_0000010 "OP_ADD"
56126   attribute \enum_value_0000011 "OP_ADDPCIS"
56127   attribute \enum_value_0000100 "OP_AND"
56128   attribute \enum_value_0000101 "OP_ATTN"
56129   attribute \enum_value_0000110 "OP_B"
56130   attribute \enum_value_0000111 "OP_BC"
56131   attribute \enum_value_0001000 "OP_BCREG"
56132   attribute \enum_value_0001001 "OP_BPERM"
56133   attribute \enum_value_0001010 "OP_CMP"
56134   attribute \enum_value_0001011 "OP_CMPB"
56135   attribute \enum_value_0001100 "OP_CMPEQB"
56136   attribute \enum_value_0001101 "OP_CMPRB"
56137   attribute \enum_value_0001110 "OP_CNTZ"
56138   attribute \enum_value_0001111 "OP_CRAND"
56139   attribute \enum_value_0010000 "OP_CRANDC"
56140   attribute \enum_value_0010001 "OP_CREQV"
56141   attribute \enum_value_0010010 "OP_CRNAND"
56142   attribute \enum_value_0010011 "OP_CRNOR"
56143   attribute \enum_value_0010100 "OP_CROR"
56144   attribute \enum_value_0010101 "OP_CRORC"
56145   attribute \enum_value_0010110 "OP_CRXOR"
56146   attribute \enum_value_0010111 "OP_DARN"
56147   attribute \enum_value_0011000 "OP_DCBF"
56148   attribute \enum_value_0011001 "OP_DCBST"
56149   attribute \enum_value_0011010 "OP_DCBT"
56150   attribute \enum_value_0011011 "OP_DCBTST"
56151   attribute \enum_value_0011100 "OP_DCBZ"
56152   attribute \enum_value_0011101 "OP_DIV"
56153   attribute \enum_value_0011110 "OP_DIVE"
56154   attribute \enum_value_0011111 "OP_EXTS"
56155   attribute \enum_value_0100000 "OP_EXTSWSLI"
56156   attribute \enum_value_0100001 "OP_ICBI"
56157   attribute \enum_value_0100010 "OP_ICBT"
56158   attribute \enum_value_0100011 "OP_ISEL"
56159   attribute \enum_value_0100100 "OP_ISYNC"
56160   attribute \enum_value_0100101 "OP_LOAD"
56161   attribute \enum_value_0100110 "OP_STORE"
56162   attribute \enum_value_0100111 "OP_MADDHD"
56163   attribute \enum_value_0101000 "OP_MADDHDU"
56164   attribute \enum_value_0101001 "OP_MADDLD"
56165   attribute \enum_value_0101010 "OP_MCRF"
56166   attribute \enum_value_0101011 "OP_MCRXR"
56167   attribute \enum_value_0101100 "OP_MCRXRX"
56168   attribute \enum_value_0101101 "OP_MFCR"
56169   attribute \enum_value_0101110 "OP_MFSPR"
56170   attribute \enum_value_0101111 "OP_MOD"
56171   attribute \enum_value_0110000 "OP_MTCRF"
56172   attribute \enum_value_0110001 "OP_MTSPR"
56173   attribute \enum_value_0110010 "OP_MUL_L64"
56174   attribute \enum_value_0110011 "OP_MUL_H64"
56175   attribute \enum_value_0110100 "OP_MUL_H32"
56176   attribute \enum_value_0110101 "OP_OR"
56177   attribute \enum_value_0110110 "OP_POPCNT"
56178   attribute \enum_value_0110111 "OP_PRTY"
56179   attribute \enum_value_0111000 "OP_RLC"
56180   attribute \enum_value_0111001 "OP_RLCL"
56181   attribute \enum_value_0111010 "OP_RLCR"
56182   attribute \enum_value_0111011 "OP_SETB"
56183   attribute \enum_value_0111100 "OP_SHL"
56184   attribute \enum_value_0111101 "OP_SHR"
56185   attribute \enum_value_0111110 "OP_SYNC"
56186   attribute \enum_value_0111111 "OP_TRAP"
56187   attribute \enum_value_1000011 "OP_XOR"
56188   attribute \enum_value_1000100 "OP_SIM_CONFIG"
56189   attribute \enum_value_1000101 "OP_CROP"
56190   attribute \enum_value_1000110 "OP_RFID"
56191   attribute \enum_value_1000111 "OP_MFMSR"
56192   attribute \enum_value_1001000 "OP_MTMSRD"
56193   attribute \enum_value_1001001 "OP_SC"
56194   attribute \enum_value_1001010 "OP_MTMSR"
56195   attribute \enum_value_1001011 "OP_TLBIE"
56196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56197   wire width 7 output 2 \dec31_dec_sub9_internal_op
56198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56199   wire output 15 \dec31_dec_sub9_inv_a
56200   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56201   wire output 16 \dec31_dec_sub9_inv_out
56202   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56203   wire output 21 \dec31_dec_sub9_is_32b
56204   attribute \enum_base_type "LdstLen"
56205   attribute \enum_value_0000 "NONE"
56206   attribute \enum_value_0001 "is1B"
56207   attribute \enum_value_0010 "is2B"
56208   attribute \enum_value_0100 "is4B"
56209   attribute \enum_value_1000 "is8B"
56210   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56211   wire width 4 output 11 \dec31_dec_sub9_ldst_len
56212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56213   wire output 23 \dec31_dec_sub9_lk
56214   attribute \enum_base_type "OutSel"
56215   attribute \enum_value_00 "NONE"
56216   attribute \enum_value_01 "RT"
56217   attribute \enum_value_10 "RA"
56218   attribute \enum_value_11 "SPR"
56219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56220   wire width 2 output 8 \dec31_dec_sub9_out_sel
56221   attribute \enum_base_type "RC"
56222   attribute \enum_value_00 "NONE"
56223   attribute \enum_value_01 "ONE"
56224   attribute \enum_value_10 "RC"
56225   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56226   wire width 2 output 13 \dec31_dec_sub9_rc_sel
56227   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56228   wire output 20 \dec31_dec_sub9_rsrv
56229   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56230   wire output 24 \dec31_dec_sub9_sgl_pipe
56231   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56232   wire output 22 \dec31_dec_sub9_sgn
56233   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
56234   wire output 19 \dec31_dec_sub9_sgn_ext
56235   attribute \enum_base_type "LDSTMode"
56236   attribute \enum_value_00 "NONE"
56237   attribute \enum_value_01 "update"
56238   attribute \enum_value_10 "cix"
56239   attribute \enum_value_11 "cx"
56240   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
56241   wire width 2 output 12 \dec31_dec_sub9_upd
56242   attribute \src "libresoc.v:37683.7-37683.15"
56243   wire \initial
56244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
56245   wire width 32 input 25 \opcode_in
56246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
56247   wire width 5 \opcode_switch
56248   attribute \src "libresoc.v:37683.7-37683.20"
56249   process $proc$libresoc.v:37683$856
56250     assign { } { }
56251     assign $0\initial[0:0] 1'0
56252     sync always
56253       update \initial $0\initial[0:0]
56254     sync init
56255   end
56256   attribute \src "libresoc.v:37940.3-37994.6"
56257   process $proc$libresoc.v:37940$832
56258     assign { } { }
56259     assign { } { }
56260     assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0]
56261     attribute \src "libresoc.v:37941.5-37941.29"
56262     switch \initial
56263       attribute \src "libresoc.v:37941.9-37941.17"
56264       case 1'1
56265       case
56266     end
56267     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56268     switch \opcode_switch
56269       attribute \src "libresoc.v:0.0-0.0"
56270       case 5'01100
56271         assign { } { }
56272         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56273       attribute \src "libresoc.v:0.0-0.0"
56274       case 5'11100
56275         assign { } { }
56276         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56277       attribute \src "libresoc.v:0.0-0.0"
56278       case 5'01101
56279         assign { } { }
56280         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56281       attribute \src "libresoc.v:0.0-0.0"
56282       case 5'11101
56283         assign { } { }
56284         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56285       attribute \src "libresoc.v:0.0-0.0"
56286       case 5'01110
56287         assign { } { }
56288         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56289       attribute \src "libresoc.v:0.0-0.0"
56290       case 5'11110
56291         assign { } { }
56292         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56293       attribute \src "libresoc.v:0.0-0.0"
56294       case 5'01111
56295         assign { } { }
56296         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56297       attribute \src "libresoc.v:0.0-0.0"
56298       case 5'11111
56299         assign { } { }
56300         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56301       attribute \src "libresoc.v:0.0-0.0"
56302       case 5'01000
56303         assign { } { }
56304         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56305       attribute \src "libresoc.v:0.0-0.0"
56306       case 5'11000
56307         assign { } { }
56308         assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000
56309       attribute \src "libresoc.v:0.0-0.0"
56310       case 5'00010
56311         assign { } { }
56312         assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000
56313       attribute \src "libresoc.v:0.0-0.0"
56314       case 5'00000
56315         assign { } { }
56316         assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000
56317       attribute \src "libresoc.v:0.0-0.0"
56318       case 5'10010
56319         assign { } { }
56320         assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000
56321       attribute \src "libresoc.v:0.0-0.0"
56322       case 5'10000
56323         assign { } { }
56324         assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000
56325       attribute \src "libresoc.v:0.0-0.0"
56326       case 5'00111
56327         assign { } { }
56328         assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000
56329       attribute \src "libresoc.v:0.0-0.0"
56330       case 5'10111
56331         assign { } { }
56332         assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000
56333       case
56334         assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000
56335     end
56336     sync always
56337       update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0]
56338   end
56339   attribute \src "libresoc.v:37995.3-38049.6"
56340   process $proc$libresoc.v:37995$833
56341     assign { } { }
56342     assign { } { }
56343     assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0]
56344     attribute \src "libresoc.v:37996.5-37996.29"
56345     switch \initial
56346       attribute \src "libresoc.v:37996.9-37996.17"
56347       case 1'1
56348       case
56349     end
56350     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56351     switch \opcode_switch
56352       attribute \src "libresoc.v:0.0-0.0"
56353       case 5'01100
56354         assign { } { }
56355         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56356       attribute \src "libresoc.v:0.0-0.0"
56357       case 5'11100
56358         assign { } { }
56359         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56360       attribute \src "libresoc.v:0.0-0.0"
56361       case 5'01101
56362         assign { } { }
56363         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56364       attribute \src "libresoc.v:0.0-0.0"
56365       case 5'11101
56366         assign { } { }
56367         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56368       attribute \src "libresoc.v:0.0-0.0"
56369       case 5'01110
56370         assign { } { }
56371         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56372       attribute \src "libresoc.v:0.0-0.0"
56373       case 5'11110
56374         assign { } { }
56375         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56376       attribute \src "libresoc.v:0.0-0.0"
56377       case 5'01111
56378         assign { } { }
56379         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56380       attribute \src "libresoc.v:0.0-0.0"
56381       case 5'11111
56382         assign { } { }
56383         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56384       attribute \src "libresoc.v:0.0-0.0"
56385       case 5'01000
56386         assign { } { }
56387         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56388       attribute \src "libresoc.v:0.0-0.0"
56389       case 5'11000
56390         assign { } { }
56391         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56392       attribute \src "libresoc.v:0.0-0.0"
56393       case 5'00010
56394         assign { } { }
56395         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56396       attribute \src "libresoc.v:0.0-0.0"
56397       case 5'00000
56398         assign { } { }
56399         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56400       attribute \src "libresoc.v:0.0-0.0"
56401       case 5'10010
56402         assign { } { }
56403         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56404       attribute \src "libresoc.v:0.0-0.0"
56405       case 5'10000
56406         assign { } { }
56407         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56408       attribute \src "libresoc.v:0.0-0.0"
56409       case 5'00111
56410         assign { } { }
56411         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56412       attribute \src "libresoc.v:0.0-0.0"
56413       case 5'10111
56414         assign { } { }
56415         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56416       case
56417         assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000
56418     end
56419     sync always
56420       update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0]
56421   end
56422   attribute \src "libresoc.v:38050.3-38104.6"
56423   process $proc$libresoc.v:38050$834
56424     assign { } { }
56425     assign { } { }
56426     assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0]
56427     attribute \src "libresoc.v:38051.5-38051.29"
56428     switch \initial
56429       attribute \src "libresoc.v:38051.9-38051.17"
56430       case 1'1
56431       case
56432     end
56433     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56434     switch \opcode_switch
56435       attribute \src "libresoc.v:0.0-0.0"
56436       case 5'01100
56437         assign { } { }
56438         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56439       attribute \src "libresoc.v:0.0-0.0"
56440       case 5'11100
56441         assign { } { }
56442         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56443       attribute \src "libresoc.v:0.0-0.0"
56444       case 5'01101
56445         assign { } { }
56446         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56447       attribute \src "libresoc.v:0.0-0.0"
56448       case 5'11101
56449         assign { } { }
56450         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56451       attribute \src "libresoc.v:0.0-0.0"
56452       case 5'01110
56453         assign { } { }
56454         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56455       attribute \src "libresoc.v:0.0-0.0"
56456       case 5'11110
56457         assign { } { }
56458         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56459       attribute \src "libresoc.v:0.0-0.0"
56460       case 5'01111
56461         assign { } { }
56462         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56463       attribute \src "libresoc.v:0.0-0.0"
56464       case 5'11111
56465         assign { } { }
56466         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56467       attribute \src "libresoc.v:0.0-0.0"
56468       case 5'01000
56469         assign { } { }
56470         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56471       attribute \src "libresoc.v:0.0-0.0"
56472       case 5'11000
56473         assign { } { }
56474         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56475       attribute \src "libresoc.v:0.0-0.0"
56476       case 5'00010
56477         assign { } { }
56478         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56479       attribute \src "libresoc.v:0.0-0.0"
56480       case 5'00000
56481         assign { } { }
56482         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56483       attribute \src "libresoc.v:0.0-0.0"
56484       case 5'10010
56485         assign { } { }
56486         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56487       attribute \src "libresoc.v:0.0-0.0"
56488       case 5'10000
56489         assign { } { }
56490         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56491       attribute \src "libresoc.v:0.0-0.0"
56492       case 5'00111
56493         assign { } { }
56494         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56495       attribute \src "libresoc.v:0.0-0.0"
56496       case 5'10111
56497         assign { } { }
56498         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56499       case
56500         assign $1\dec31_dec_sub9_upd[1:0] 2'00
56501     end
56502     sync always
56503       update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0]
56504   end
56505   attribute \src "libresoc.v:38105.3-38159.6"
56506   process $proc$libresoc.v:38105$835
56507     assign { } { }
56508     assign { } { }
56509     assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0]
56510     attribute \src "libresoc.v:38106.5-38106.29"
56511     switch \initial
56512       attribute \src "libresoc.v:38106.9-38106.17"
56513       case 1'1
56514       case
56515     end
56516     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56517     switch \opcode_switch
56518       attribute \src "libresoc.v:0.0-0.0"
56519       case 5'01100
56520         assign { } { }
56521         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56522       attribute \src "libresoc.v:0.0-0.0"
56523       case 5'11100
56524         assign { } { }
56525         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56526       attribute \src "libresoc.v:0.0-0.0"
56527       case 5'01101
56528         assign { } { }
56529         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56530       attribute \src "libresoc.v:0.0-0.0"
56531       case 5'11101
56532         assign { } { }
56533         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56534       attribute \src "libresoc.v:0.0-0.0"
56535       case 5'01110
56536         assign { } { }
56537         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56538       attribute \src "libresoc.v:0.0-0.0"
56539       case 5'11110
56540         assign { } { }
56541         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56542       attribute \src "libresoc.v:0.0-0.0"
56543       case 5'01111
56544         assign { } { }
56545         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56546       attribute \src "libresoc.v:0.0-0.0"
56547       case 5'11111
56548         assign { } { }
56549         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56550       attribute \src "libresoc.v:0.0-0.0"
56551       case 5'01000
56552         assign { } { }
56553         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00
56554       attribute \src "libresoc.v:0.0-0.0"
56555       case 5'11000
56556         assign { } { }
56557         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00
56558       attribute \src "libresoc.v:0.0-0.0"
56559       case 5'00010
56560         assign { } { }
56561         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56562       attribute \src "libresoc.v:0.0-0.0"
56563       case 5'00000
56564         assign { } { }
56565         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56566       attribute \src "libresoc.v:0.0-0.0"
56567       case 5'10010
56568         assign { } { }
56569         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56570       attribute \src "libresoc.v:0.0-0.0"
56571       case 5'10000
56572         assign { } { }
56573         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56574       attribute \src "libresoc.v:0.0-0.0"
56575       case 5'00111
56576         assign { } { }
56577         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56578       attribute \src "libresoc.v:0.0-0.0"
56579       case 5'10111
56580         assign { } { }
56581         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10
56582       case
56583         assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00
56584     end
56585     sync always
56586       update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0]
56587   end
56588   attribute \src "libresoc.v:38160.3-38214.6"
56589   process $proc$libresoc.v:38160$836
56590     assign { } { }
56591     assign { } { }
56592     assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0]
56593     attribute \src "libresoc.v:38161.5-38161.29"
56594     switch \initial
56595       attribute \src "libresoc.v:38161.9-38161.17"
56596       case 1'1
56597       case
56598     end
56599     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56600     switch \opcode_switch
56601       attribute \src "libresoc.v:0.0-0.0"
56602       case 5'01100
56603         assign { } { }
56604         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56605       attribute \src "libresoc.v:0.0-0.0"
56606       case 5'11100
56607         assign { } { }
56608         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56609       attribute \src "libresoc.v:0.0-0.0"
56610       case 5'01101
56611         assign { } { }
56612         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56613       attribute \src "libresoc.v:0.0-0.0"
56614       case 5'11101
56615         assign { } { }
56616         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56617       attribute \src "libresoc.v:0.0-0.0"
56618       case 5'01110
56619         assign { } { }
56620         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56621       attribute \src "libresoc.v:0.0-0.0"
56622       case 5'11110
56623         assign { } { }
56624         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56625       attribute \src "libresoc.v:0.0-0.0"
56626       case 5'01111
56627         assign { } { }
56628         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56629       attribute \src "libresoc.v:0.0-0.0"
56630       case 5'11111
56631         assign { } { }
56632         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56633       attribute \src "libresoc.v:0.0-0.0"
56634       case 5'01000
56635         assign { } { }
56636         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56637       attribute \src "libresoc.v:0.0-0.0"
56638       case 5'11000
56639         assign { } { }
56640         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56641       attribute \src "libresoc.v:0.0-0.0"
56642       case 5'00010
56643         assign { } { }
56644         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56645       attribute \src "libresoc.v:0.0-0.0"
56646       case 5'00000
56647         assign { } { }
56648         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56649       attribute \src "libresoc.v:0.0-0.0"
56650       case 5'10010
56651         assign { } { }
56652         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56653       attribute \src "libresoc.v:0.0-0.0"
56654       case 5'10000
56655         assign { } { }
56656         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56657       attribute \src "libresoc.v:0.0-0.0"
56658       case 5'00111
56659         assign { } { }
56660         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56661       attribute \src "libresoc.v:0.0-0.0"
56662       case 5'10111
56663         assign { } { }
56664         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56665       case
56666         assign $1\dec31_dec_sub9_cry_in[1:0] 2'00
56667     end
56668     sync always
56669       update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0]
56670   end
56671   attribute \src "libresoc.v:38215.3-38269.6"
56672   process $proc$libresoc.v:38215$837
56673     assign { } { }
56674     assign { } { }
56675     assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0]
56676     attribute \src "libresoc.v:38216.5-38216.29"
56677     switch \initial
56678       attribute \src "libresoc.v:38216.9-38216.17"
56679       case 1'1
56680       case
56681     end
56682     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56683     switch \opcode_switch
56684       attribute \src "libresoc.v:0.0-0.0"
56685       case 5'01100
56686         assign { } { }
56687         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110
56688       attribute \src "libresoc.v:0.0-0.0"
56689       case 5'11100
56690         assign { } { }
56691         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111
56692       attribute \src "libresoc.v:0.0-0.0"
56693       case 5'01101
56694         assign { } { }
56695         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100
56696       attribute \src "libresoc.v:0.0-0.0"
56697       case 5'11101
56698         assign { } { }
56699         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101
56700       attribute \src "libresoc.v:0.0-0.0"
56701       case 5'01110
56702         assign { } { }
56703         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001
56704       attribute \src "libresoc.v:0.0-0.0"
56705       case 5'11110
56706         assign { } { }
56707         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010
56708       attribute \src "libresoc.v:0.0-0.0"
56709       case 5'01111
56710         assign { } { }
56711         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011
56712       attribute \src "libresoc.v:0.0-0.0"
56713       case 5'11111
56714         assign { } { }
56715         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000
56716       attribute \src "libresoc.v:0.0-0.0"
56717       case 5'01000
56718         assign { } { }
56719         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100
56720       attribute \src "libresoc.v:0.0-0.0"
56721       case 5'11000
56722         assign { } { }
56723         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010
56724       attribute \src "libresoc.v:0.0-0.0"
56725       case 5'00010
56726         assign { } { }
56727         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010
56728       attribute \src "libresoc.v:0.0-0.0"
56729       case 5'00000
56730         assign { } { }
56731         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011
56732       attribute \src "libresoc.v:0.0-0.0"
56733       case 5'10010
56734         assign { } { }
56735         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010
56736       attribute \src "libresoc.v:0.0-0.0"
56737       case 5'10000
56738         assign { } { }
56739         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011
56740       attribute \src "libresoc.v:0.0-0.0"
56741       case 5'00111
56742         assign { } { }
56743         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110
56744       attribute \src "libresoc.v:0.0-0.0"
56745       case 5'10111
56746         assign { } { }
56747         assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111
56748       case
56749         assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000
56750     end
56751     sync always
56752       update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0]
56753   end
56754   attribute \src "libresoc.v:38270.3-38324.6"
56755   process $proc$libresoc.v:38270$838
56756     assign { } { }
56757     assign { } { }
56758     assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0]
56759     attribute \src "libresoc.v:38271.5-38271.29"
56760     switch \initial
56761       attribute \src "libresoc.v:38271.9-38271.17"
56762       case 1'1
56763       case
56764     end
56765     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56766     switch \opcode_switch
56767       attribute \src "libresoc.v:0.0-0.0"
56768       case 5'01100
56769         assign { } { }
56770         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56771       attribute \src "libresoc.v:0.0-0.0"
56772       case 5'11100
56773         assign { } { }
56774         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56775       attribute \src "libresoc.v:0.0-0.0"
56776       case 5'01101
56777         assign { } { }
56778         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56779       attribute \src "libresoc.v:0.0-0.0"
56780       case 5'11101
56781         assign { } { }
56782         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56783       attribute \src "libresoc.v:0.0-0.0"
56784       case 5'01110
56785         assign { } { }
56786         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56787       attribute \src "libresoc.v:0.0-0.0"
56788       case 5'11110
56789         assign { } { }
56790         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56791       attribute \src "libresoc.v:0.0-0.0"
56792       case 5'01111
56793         assign { } { }
56794         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56795       attribute \src "libresoc.v:0.0-0.0"
56796       case 5'11111
56797         assign { } { }
56798         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56799       attribute \src "libresoc.v:0.0-0.0"
56800       case 5'01000
56801         assign { } { }
56802         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56803       attribute \src "libresoc.v:0.0-0.0"
56804       case 5'11000
56805         assign { } { }
56806         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56807       attribute \src "libresoc.v:0.0-0.0"
56808       case 5'00010
56809         assign { } { }
56810         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56811       attribute \src "libresoc.v:0.0-0.0"
56812       case 5'00000
56813         assign { } { }
56814         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56815       attribute \src "libresoc.v:0.0-0.0"
56816       case 5'10010
56817         assign { } { }
56818         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56819       attribute \src "libresoc.v:0.0-0.0"
56820       case 5'10000
56821         assign { } { }
56822         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56823       attribute \src "libresoc.v:0.0-0.0"
56824       case 5'00111
56825         assign { } { }
56826         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56827       attribute \src "libresoc.v:0.0-0.0"
56828       case 5'10111
56829         assign { } { }
56830         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56831       case
56832         assign $1\dec31_dec_sub9_inv_a[0:0] 1'0
56833     end
56834     sync always
56835       update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0]
56836   end
56837   attribute \src "libresoc.v:38325.3-38379.6"
56838   process $proc$libresoc.v:38325$839
56839     assign { } { }
56840     assign { } { }
56841     assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0]
56842     attribute \src "libresoc.v:38326.5-38326.29"
56843     switch \initial
56844       attribute \src "libresoc.v:38326.9-38326.17"
56845       case 1'1
56846       case
56847     end
56848     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56849     switch \opcode_switch
56850       attribute \src "libresoc.v:0.0-0.0"
56851       case 5'01100
56852         assign { } { }
56853         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56854       attribute \src "libresoc.v:0.0-0.0"
56855       case 5'11100
56856         assign { } { }
56857         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56858       attribute \src "libresoc.v:0.0-0.0"
56859       case 5'01101
56860         assign { } { }
56861         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56862       attribute \src "libresoc.v:0.0-0.0"
56863       case 5'11101
56864         assign { } { }
56865         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56866       attribute \src "libresoc.v:0.0-0.0"
56867       case 5'01110
56868         assign { } { }
56869         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56870       attribute \src "libresoc.v:0.0-0.0"
56871       case 5'11110
56872         assign { } { }
56873         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56874       attribute \src "libresoc.v:0.0-0.0"
56875       case 5'01111
56876         assign { } { }
56877         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56878       attribute \src "libresoc.v:0.0-0.0"
56879       case 5'11111
56880         assign { } { }
56881         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56882       attribute \src "libresoc.v:0.0-0.0"
56883       case 5'01000
56884         assign { } { }
56885         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56886       attribute \src "libresoc.v:0.0-0.0"
56887       case 5'11000
56888         assign { } { }
56889         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56890       attribute \src "libresoc.v:0.0-0.0"
56891       case 5'00010
56892         assign { } { }
56893         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56894       attribute \src "libresoc.v:0.0-0.0"
56895       case 5'00000
56896         assign { } { }
56897         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56898       attribute \src "libresoc.v:0.0-0.0"
56899       case 5'10010
56900         assign { } { }
56901         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56902       attribute \src "libresoc.v:0.0-0.0"
56903       case 5'10000
56904         assign { } { }
56905         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56906       attribute \src "libresoc.v:0.0-0.0"
56907       case 5'00111
56908         assign { } { }
56909         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56910       attribute \src "libresoc.v:0.0-0.0"
56911       case 5'10111
56912         assign { } { }
56913         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56914       case
56915         assign $1\dec31_dec_sub9_inv_out[0:0] 1'0
56916     end
56917     sync always
56918       update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0]
56919   end
56920   attribute \src "libresoc.v:38380.3-38434.6"
56921   process $proc$libresoc.v:38380$840
56922     assign { } { }
56923     assign { } { }
56924     assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0]
56925     attribute \src "libresoc.v:38381.5-38381.29"
56926     switch \initial
56927       attribute \src "libresoc.v:38381.9-38381.17"
56928       case 1'1
56929       case
56930     end
56931     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
56932     switch \opcode_switch
56933       attribute \src "libresoc.v:0.0-0.0"
56934       case 5'01100
56935         assign { } { }
56936         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56937       attribute \src "libresoc.v:0.0-0.0"
56938       case 5'11100
56939         assign { } { }
56940         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56941       attribute \src "libresoc.v:0.0-0.0"
56942       case 5'01101
56943         assign { } { }
56944         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56945       attribute \src "libresoc.v:0.0-0.0"
56946       case 5'11101
56947         assign { } { }
56948         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56949       attribute \src "libresoc.v:0.0-0.0"
56950       case 5'01110
56951         assign { } { }
56952         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56953       attribute \src "libresoc.v:0.0-0.0"
56954       case 5'11110
56955         assign { } { }
56956         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56957       attribute \src "libresoc.v:0.0-0.0"
56958       case 5'01111
56959         assign { } { }
56960         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56961       attribute \src "libresoc.v:0.0-0.0"
56962       case 5'11111
56963         assign { } { }
56964         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56965       attribute \src "libresoc.v:0.0-0.0"
56966       case 5'01000
56967         assign { } { }
56968         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56969       attribute \src "libresoc.v:0.0-0.0"
56970       case 5'11000
56971         assign { } { }
56972         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56973       attribute \src "libresoc.v:0.0-0.0"
56974       case 5'00010
56975         assign { } { }
56976         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56977       attribute \src "libresoc.v:0.0-0.0"
56978       case 5'00000
56979         assign { } { }
56980         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56981       attribute \src "libresoc.v:0.0-0.0"
56982       case 5'10010
56983         assign { } { }
56984         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56985       attribute \src "libresoc.v:0.0-0.0"
56986       case 5'10000
56987         assign { } { }
56988         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56989       attribute \src "libresoc.v:0.0-0.0"
56990       case 5'00111
56991         assign { } { }
56992         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56993       attribute \src "libresoc.v:0.0-0.0"
56994       case 5'10111
56995         assign { } { }
56996         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56997       case
56998         assign $1\dec31_dec_sub9_cry_out[0:0] 1'0
56999     end
57000     sync always
57001       update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0]
57002   end
57003   attribute \src "libresoc.v:38435.3-38489.6"
57004   process $proc$libresoc.v:38435$841
57005     assign { } { }
57006     assign { } { }
57007     assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0]
57008     attribute \src "libresoc.v:38436.5-38436.29"
57009     switch \initial
57010       attribute \src "libresoc.v:38436.9-38436.17"
57011       case 1'1
57012       case
57013     end
57014     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57015     switch \opcode_switch
57016       attribute \src "libresoc.v:0.0-0.0"
57017       case 5'01100
57018         assign { } { }
57019         assign $1\dec31_dec_sub9_br[0:0] 1'0
57020       attribute \src "libresoc.v:0.0-0.0"
57021       case 5'11100
57022         assign { } { }
57023         assign $1\dec31_dec_sub9_br[0:0] 1'0
57024       attribute \src "libresoc.v:0.0-0.0"
57025       case 5'01101
57026         assign { } { }
57027         assign $1\dec31_dec_sub9_br[0:0] 1'0
57028       attribute \src "libresoc.v:0.0-0.0"
57029       case 5'11101
57030         assign { } { }
57031         assign $1\dec31_dec_sub9_br[0:0] 1'0
57032       attribute \src "libresoc.v:0.0-0.0"
57033       case 5'01110
57034         assign { } { }
57035         assign $1\dec31_dec_sub9_br[0:0] 1'0
57036       attribute \src "libresoc.v:0.0-0.0"
57037       case 5'11110
57038         assign { } { }
57039         assign $1\dec31_dec_sub9_br[0:0] 1'0
57040       attribute \src "libresoc.v:0.0-0.0"
57041       case 5'01111
57042         assign { } { }
57043         assign $1\dec31_dec_sub9_br[0:0] 1'0
57044       attribute \src "libresoc.v:0.0-0.0"
57045       case 5'11111
57046         assign { } { }
57047         assign $1\dec31_dec_sub9_br[0:0] 1'0
57048       attribute \src "libresoc.v:0.0-0.0"
57049       case 5'01000
57050         assign { } { }
57051         assign $1\dec31_dec_sub9_br[0:0] 1'0
57052       attribute \src "libresoc.v:0.0-0.0"
57053       case 5'11000
57054         assign { } { }
57055         assign $1\dec31_dec_sub9_br[0:0] 1'0
57056       attribute \src "libresoc.v:0.0-0.0"
57057       case 5'00010
57058         assign { } { }
57059         assign $1\dec31_dec_sub9_br[0:0] 1'0
57060       attribute \src "libresoc.v:0.0-0.0"
57061       case 5'00000
57062         assign { } { }
57063         assign $1\dec31_dec_sub9_br[0:0] 1'0
57064       attribute \src "libresoc.v:0.0-0.0"
57065       case 5'10010
57066         assign { } { }
57067         assign $1\dec31_dec_sub9_br[0:0] 1'0
57068       attribute \src "libresoc.v:0.0-0.0"
57069       case 5'10000
57070         assign { } { }
57071         assign $1\dec31_dec_sub9_br[0:0] 1'0
57072       attribute \src "libresoc.v:0.0-0.0"
57073       case 5'00111
57074         assign { } { }
57075         assign $1\dec31_dec_sub9_br[0:0] 1'0
57076       attribute \src "libresoc.v:0.0-0.0"
57077       case 5'10111
57078         assign { } { }
57079         assign $1\dec31_dec_sub9_br[0:0] 1'0
57080       case
57081         assign $1\dec31_dec_sub9_br[0:0] 1'0
57082     end
57083     sync always
57084       update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0]
57085   end
57086   attribute \src "libresoc.v:38490.3-38544.6"
57087   process $proc$libresoc.v:38490$842
57088     assign { } { }
57089     assign { } { }
57090     assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0]
57091     attribute \src "libresoc.v:38491.5-38491.29"
57092     switch \initial
57093       attribute \src "libresoc.v:38491.9-38491.17"
57094       case 1'1
57095       case
57096     end
57097     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57098     switch \opcode_switch
57099       attribute \src "libresoc.v:0.0-0.0"
57100       case 5'01100
57101         assign { } { }
57102         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57103       attribute \src "libresoc.v:0.0-0.0"
57104       case 5'11100
57105         assign { } { }
57106         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57107       attribute \src "libresoc.v:0.0-0.0"
57108       case 5'01101
57109         assign { } { }
57110         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57111       attribute \src "libresoc.v:0.0-0.0"
57112       case 5'11101
57113         assign { } { }
57114         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57115       attribute \src "libresoc.v:0.0-0.0"
57116       case 5'01110
57117         assign { } { }
57118         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57119       attribute \src "libresoc.v:0.0-0.0"
57120       case 5'11110
57121         assign { } { }
57122         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57123       attribute \src "libresoc.v:0.0-0.0"
57124       case 5'01111
57125         assign { } { }
57126         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57127       attribute \src "libresoc.v:0.0-0.0"
57128       case 5'11111
57129         assign { } { }
57130         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57131       attribute \src "libresoc.v:0.0-0.0"
57132       case 5'01000
57133         assign { } { }
57134         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57135       attribute \src "libresoc.v:0.0-0.0"
57136       case 5'11000
57137         assign { } { }
57138         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57139       attribute \src "libresoc.v:0.0-0.0"
57140       case 5'00010
57141         assign { } { }
57142         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57143       attribute \src "libresoc.v:0.0-0.0"
57144       case 5'00000
57145         assign { } { }
57146         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57147       attribute \src "libresoc.v:0.0-0.0"
57148       case 5'10010
57149         assign { } { }
57150         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57151       attribute \src "libresoc.v:0.0-0.0"
57152       case 5'10000
57153         assign { } { }
57154         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57155       attribute \src "libresoc.v:0.0-0.0"
57156       case 5'00111
57157         assign { } { }
57158         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57159       attribute \src "libresoc.v:0.0-0.0"
57160       case 5'10111
57161         assign { } { }
57162         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57163       case
57164         assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0
57165     end
57166     sync always
57167       update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0]
57168   end
57169   attribute \src "libresoc.v:38545.3-38599.6"
57170   process $proc$libresoc.v:38545$843
57171     assign { } { }
57172     assign { } { }
57173     assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0]
57174     attribute \src "libresoc.v:38546.5-38546.29"
57175     switch \initial
57176       attribute \src "libresoc.v:38546.9-38546.17"
57177       case 1'1
57178       case
57179     end
57180     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57181     switch \opcode_switch
57182       attribute \src "libresoc.v:0.0-0.0"
57183       case 5'01100
57184         assign { } { }
57185         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110
57186       attribute \src "libresoc.v:0.0-0.0"
57187       case 5'11100
57188         assign { } { }
57189         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110
57190       attribute \src "libresoc.v:0.0-0.0"
57191       case 5'01101
57192         assign { } { }
57193         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110
57194       attribute \src "libresoc.v:0.0-0.0"
57195       case 5'11101
57196         assign { } { }
57197         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110
57198       attribute \src "libresoc.v:0.0-0.0"
57199       case 5'01110
57200         assign { } { }
57201         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101
57202       attribute \src "libresoc.v:0.0-0.0"
57203       case 5'11110
57204         assign { } { }
57205         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101
57206       attribute \src "libresoc.v:0.0-0.0"
57207       case 5'01111
57208         assign { } { }
57209         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101
57210       attribute \src "libresoc.v:0.0-0.0"
57211       case 5'11111
57212         assign { } { }
57213         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101
57214       attribute \src "libresoc.v:0.0-0.0"
57215       case 5'01000
57216         assign { } { }
57217         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111
57218       attribute \src "libresoc.v:0.0-0.0"
57219       case 5'11000
57220         assign { } { }
57221         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111
57222       attribute \src "libresoc.v:0.0-0.0"
57223       case 5'00010
57224         assign { } { }
57225         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011
57226       attribute \src "libresoc.v:0.0-0.0"
57227       case 5'00000
57228         assign { } { }
57229         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011
57230       attribute \src "libresoc.v:0.0-0.0"
57231       case 5'10010
57232         assign { } { }
57233         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011
57234       attribute \src "libresoc.v:0.0-0.0"
57235       case 5'10000
57236         assign { } { }
57237         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011
57238       attribute \src "libresoc.v:0.0-0.0"
57239       case 5'00111
57240         assign { } { }
57241         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010
57242       attribute \src "libresoc.v:0.0-0.0"
57243       case 5'10111
57244         assign { } { }
57245         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010
57246       case
57247         assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000
57248     end
57249     sync always
57250       update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0]
57251   end
57252   attribute \src "libresoc.v:38600.3-38654.6"
57253   process $proc$libresoc.v:38600$844
57254     assign { } { }
57255     assign { } { }
57256     assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0]
57257     attribute \src "libresoc.v:38601.5-38601.29"
57258     switch \initial
57259       attribute \src "libresoc.v:38601.9-38601.17"
57260       case 1'1
57261       case
57262     end
57263     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57264     switch \opcode_switch
57265       attribute \src "libresoc.v:0.0-0.0"
57266       case 5'01100
57267         assign { } { }
57268         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57269       attribute \src "libresoc.v:0.0-0.0"
57270       case 5'11100
57271         assign { } { }
57272         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57273       attribute \src "libresoc.v:0.0-0.0"
57274       case 5'01101
57275         assign { } { }
57276         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57277       attribute \src "libresoc.v:0.0-0.0"
57278       case 5'11101
57279         assign { } { }
57280         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57281       attribute \src "libresoc.v:0.0-0.0"
57282       case 5'01110
57283         assign { } { }
57284         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57285       attribute \src "libresoc.v:0.0-0.0"
57286       case 5'11110
57287         assign { } { }
57288         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57289       attribute \src "libresoc.v:0.0-0.0"
57290       case 5'01111
57291         assign { } { }
57292         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57293       attribute \src "libresoc.v:0.0-0.0"
57294       case 5'11111
57295         assign { } { }
57296         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57297       attribute \src "libresoc.v:0.0-0.0"
57298       case 5'01000
57299         assign { } { }
57300         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57301       attribute \src "libresoc.v:0.0-0.0"
57302       case 5'11000
57303         assign { } { }
57304         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57305       attribute \src "libresoc.v:0.0-0.0"
57306       case 5'00010
57307         assign { } { }
57308         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57309       attribute \src "libresoc.v:0.0-0.0"
57310       case 5'00000
57311         assign { } { }
57312         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57313       attribute \src "libresoc.v:0.0-0.0"
57314       case 5'10010
57315         assign { } { }
57316         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57317       attribute \src "libresoc.v:0.0-0.0"
57318       case 5'10000
57319         assign { } { }
57320         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57321       attribute \src "libresoc.v:0.0-0.0"
57322       case 5'00111
57323         assign { } { }
57324         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57325       attribute \src "libresoc.v:0.0-0.0"
57326       case 5'10111
57327         assign { } { }
57328         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57329       case
57330         assign $1\dec31_dec_sub9_rsrv[0:0] 1'0
57331     end
57332     sync always
57333       update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0]
57334   end
57335   attribute \src "libresoc.v:38655.3-38709.6"
57336   process $proc$libresoc.v:38655$845
57337     assign { } { }
57338     assign { } { }
57339     assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0]
57340     attribute \src "libresoc.v:38656.5-38656.29"
57341     switch \initial
57342       attribute \src "libresoc.v:38656.9-38656.17"
57343       case 1'1
57344       case
57345     end
57346     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57347     switch \opcode_switch
57348       attribute \src "libresoc.v:0.0-0.0"
57349       case 5'01100
57350         assign { } { }
57351         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57352       attribute \src "libresoc.v:0.0-0.0"
57353       case 5'11100
57354         assign { } { }
57355         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57356       attribute \src "libresoc.v:0.0-0.0"
57357       case 5'01101
57358         assign { } { }
57359         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57360       attribute \src "libresoc.v:0.0-0.0"
57361       case 5'11101
57362         assign { } { }
57363         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57364       attribute \src "libresoc.v:0.0-0.0"
57365       case 5'01110
57366         assign { } { }
57367         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57368       attribute \src "libresoc.v:0.0-0.0"
57369       case 5'11110
57370         assign { } { }
57371         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57372       attribute \src "libresoc.v:0.0-0.0"
57373       case 5'01111
57374         assign { } { }
57375         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57376       attribute \src "libresoc.v:0.0-0.0"
57377       case 5'11111
57378         assign { } { }
57379         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57380       attribute \src "libresoc.v:0.0-0.0"
57381       case 5'01000
57382         assign { } { }
57383         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57384       attribute \src "libresoc.v:0.0-0.0"
57385       case 5'11000
57386         assign { } { }
57387         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57388       attribute \src "libresoc.v:0.0-0.0"
57389       case 5'00010
57390         assign { } { }
57391         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57392       attribute \src "libresoc.v:0.0-0.0"
57393       case 5'00000
57394         assign { } { }
57395         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57396       attribute \src "libresoc.v:0.0-0.0"
57397       case 5'10010
57398         assign { } { }
57399         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57400       attribute \src "libresoc.v:0.0-0.0"
57401       case 5'10000
57402         assign { } { }
57403         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57404       attribute \src "libresoc.v:0.0-0.0"
57405       case 5'00111
57406         assign { } { }
57407         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57408       attribute \src "libresoc.v:0.0-0.0"
57409       case 5'10111
57410         assign { } { }
57411         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57412       case
57413         assign $1\dec31_dec_sub9_is_32b[0:0] 1'0
57414     end
57415     sync always
57416       update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0]
57417   end
57418   attribute \src "libresoc.v:38710.3-38764.6"
57419   process $proc$libresoc.v:38710$846
57420     assign { } { }
57421     assign { } { }
57422     assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0]
57423     attribute \src "libresoc.v:38711.5-38711.29"
57424     switch \initial
57425       attribute \src "libresoc.v:38711.9-38711.17"
57426       case 1'1
57427       case
57428     end
57429     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57430     switch \opcode_switch
57431       attribute \src "libresoc.v:0.0-0.0"
57432       case 5'01100
57433         assign { } { }
57434         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57435       attribute \src "libresoc.v:0.0-0.0"
57436       case 5'11100
57437         assign { } { }
57438         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57439       attribute \src "libresoc.v:0.0-0.0"
57440       case 5'01101
57441         assign { } { }
57442         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57443       attribute \src "libresoc.v:0.0-0.0"
57444       case 5'11101
57445         assign { } { }
57446         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57447       attribute \src "libresoc.v:0.0-0.0"
57448       case 5'01110
57449         assign { } { }
57450         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57451       attribute \src "libresoc.v:0.0-0.0"
57452       case 5'11110
57453         assign { } { }
57454         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57455       attribute \src "libresoc.v:0.0-0.0"
57456       case 5'01111
57457         assign { } { }
57458         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57459       attribute \src "libresoc.v:0.0-0.0"
57460       case 5'11111
57461         assign { } { }
57462         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57463       attribute \src "libresoc.v:0.0-0.0"
57464       case 5'01000
57465         assign { } { }
57466         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57467       attribute \src "libresoc.v:0.0-0.0"
57468       case 5'11000
57469         assign { } { }
57470         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57471       attribute \src "libresoc.v:0.0-0.0"
57472       case 5'00010
57473         assign { } { }
57474         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57475       attribute \src "libresoc.v:0.0-0.0"
57476       case 5'00000
57477         assign { } { }
57478         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57479       attribute \src "libresoc.v:0.0-0.0"
57480       case 5'10010
57481         assign { } { }
57482         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57483       attribute \src "libresoc.v:0.0-0.0"
57484       case 5'10000
57485         assign { } { }
57486         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57487       attribute \src "libresoc.v:0.0-0.0"
57488       case 5'00111
57489         assign { } { }
57490         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57491       attribute \src "libresoc.v:0.0-0.0"
57492       case 5'10111
57493         assign { } { }
57494         assign $1\dec31_dec_sub9_sgn[0:0] 1'1
57495       case
57496         assign $1\dec31_dec_sub9_sgn[0:0] 1'0
57497     end
57498     sync always
57499       update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0]
57500   end
57501   attribute \src "libresoc.v:38765.3-38819.6"
57502   process $proc$libresoc.v:38765$847
57503     assign { } { }
57504     assign { } { }
57505     assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0]
57506     attribute \src "libresoc.v:38766.5-38766.29"
57507     switch \initial
57508       attribute \src "libresoc.v:38766.9-38766.17"
57509       case 1'1
57510       case
57511     end
57512     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57513     switch \opcode_switch
57514       attribute \src "libresoc.v:0.0-0.0"
57515       case 5'01100
57516         assign { } { }
57517         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57518       attribute \src "libresoc.v:0.0-0.0"
57519       case 5'11100
57520         assign { } { }
57521         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57522       attribute \src "libresoc.v:0.0-0.0"
57523       case 5'01101
57524         assign { } { }
57525         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57526       attribute \src "libresoc.v:0.0-0.0"
57527       case 5'11101
57528         assign { } { }
57529         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57530       attribute \src "libresoc.v:0.0-0.0"
57531       case 5'01110
57532         assign { } { }
57533         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57534       attribute \src "libresoc.v:0.0-0.0"
57535       case 5'11110
57536         assign { } { }
57537         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57538       attribute \src "libresoc.v:0.0-0.0"
57539       case 5'01111
57540         assign { } { }
57541         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57542       attribute \src "libresoc.v:0.0-0.0"
57543       case 5'11111
57544         assign { } { }
57545         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57546       attribute \src "libresoc.v:0.0-0.0"
57547       case 5'01000
57548         assign { } { }
57549         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57550       attribute \src "libresoc.v:0.0-0.0"
57551       case 5'11000
57552         assign { } { }
57553         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57554       attribute \src "libresoc.v:0.0-0.0"
57555       case 5'00010
57556         assign { } { }
57557         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57558       attribute \src "libresoc.v:0.0-0.0"
57559       case 5'00000
57560         assign { } { }
57561         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57562       attribute \src "libresoc.v:0.0-0.0"
57563       case 5'10010
57564         assign { } { }
57565         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57566       attribute \src "libresoc.v:0.0-0.0"
57567       case 5'10000
57568         assign { } { }
57569         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57570       attribute \src "libresoc.v:0.0-0.0"
57571       case 5'00111
57572         assign { } { }
57573         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57574       attribute \src "libresoc.v:0.0-0.0"
57575       case 5'10111
57576         assign { } { }
57577         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57578       case
57579         assign $1\dec31_dec_sub9_lk[0:0] 1'0
57580     end
57581     sync always
57582       update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0]
57583   end
57584   attribute \src "libresoc.v:38820.3-38874.6"
57585   process $proc$libresoc.v:38820$848
57586     assign { } { }
57587     assign { } { }
57588     assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0]
57589     attribute \src "libresoc.v:38821.5-38821.29"
57590     switch \initial
57591       attribute \src "libresoc.v:38821.9-38821.17"
57592       case 1'1
57593       case
57594     end
57595     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57596     switch \opcode_switch
57597       attribute \src "libresoc.v:0.0-0.0"
57598       case 5'01100
57599         assign { } { }
57600         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57601       attribute \src "libresoc.v:0.0-0.0"
57602       case 5'11100
57603         assign { } { }
57604         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57605       attribute \src "libresoc.v:0.0-0.0"
57606       case 5'01101
57607         assign { } { }
57608         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57609       attribute \src "libresoc.v:0.0-0.0"
57610       case 5'11101
57611         assign { } { }
57612         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57613       attribute \src "libresoc.v:0.0-0.0"
57614       case 5'01110
57615         assign { } { }
57616         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57617       attribute \src "libresoc.v:0.0-0.0"
57618       case 5'11110
57619         assign { } { }
57620         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57621       attribute \src "libresoc.v:0.0-0.0"
57622       case 5'01111
57623         assign { } { }
57624         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57625       attribute \src "libresoc.v:0.0-0.0"
57626       case 5'11111
57627         assign { } { }
57628         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57629       attribute \src "libresoc.v:0.0-0.0"
57630       case 5'01000
57631         assign { } { }
57632         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57633       attribute \src "libresoc.v:0.0-0.0"
57634       case 5'11000
57635         assign { } { }
57636         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57637       attribute \src "libresoc.v:0.0-0.0"
57638       case 5'00010
57639         assign { } { }
57640         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57641       attribute \src "libresoc.v:0.0-0.0"
57642       case 5'00000
57643         assign { } { }
57644         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57645       attribute \src "libresoc.v:0.0-0.0"
57646       case 5'10010
57647         assign { } { }
57648         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57649       attribute \src "libresoc.v:0.0-0.0"
57650       case 5'10000
57651         assign { } { }
57652         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57653       attribute \src "libresoc.v:0.0-0.0"
57654       case 5'00111
57655         assign { } { }
57656         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57657       attribute \src "libresoc.v:0.0-0.0"
57658       case 5'10111
57659         assign { } { }
57660         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57661       case
57662         assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0
57663     end
57664     sync always
57665       update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0]
57666   end
57667   attribute \src "libresoc.v:38875.3-38929.6"
57668   process $proc$libresoc.v:38875$849
57669     assign { } { }
57670     assign { } { }
57671     assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0]
57672     attribute \src "libresoc.v:38876.5-38876.29"
57673     switch \initial
57674       attribute \src "libresoc.v:38876.9-38876.17"
57675       case 1'1
57676       case
57677     end
57678     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57679     switch \opcode_switch
57680       attribute \src "libresoc.v:0.0-0.0"
57681       case 5'01100
57682         assign { } { }
57683         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57684       attribute \src "libresoc.v:0.0-0.0"
57685       case 5'11100
57686         assign { } { }
57687         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57688       attribute \src "libresoc.v:0.0-0.0"
57689       case 5'01101
57690         assign { } { }
57691         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57692       attribute \src "libresoc.v:0.0-0.0"
57693       case 5'11101
57694         assign { } { }
57695         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57696       attribute \src "libresoc.v:0.0-0.0"
57697       case 5'01110
57698         assign { } { }
57699         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57700       attribute \src "libresoc.v:0.0-0.0"
57701       case 5'11110
57702         assign { } { }
57703         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57704       attribute \src "libresoc.v:0.0-0.0"
57705       case 5'01111
57706         assign { } { }
57707         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57708       attribute \src "libresoc.v:0.0-0.0"
57709       case 5'11111
57710         assign { } { }
57711         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57712       attribute \src "libresoc.v:0.0-0.0"
57713       case 5'01000
57714         assign { } { }
57715         assign $1\dec31_dec_sub9_form[4:0] 5'01000
57716       attribute \src "libresoc.v:0.0-0.0"
57717       case 5'11000
57718         assign { } { }
57719         assign $1\dec31_dec_sub9_form[4:0] 5'01000
57720       attribute \src "libresoc.v:0.0-0.0"
57721       case 5'00010
57722         assign { } { }
57723         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57724       attribute \src "libresoc.v:0.0-0.0"
57725       case 5'00000
57726         assign { } { }
57727         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57728       attribute \src "libresoc.v:0.0-0.0"
57729       case 5'10010
57730         assign { } { }
57731         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57732       attribute \src "libresoc.v:0.0-0.0"
57733       case 5'10000
57734         assign { } { }
57735         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57736       attribute \src "libresoc.v:0.0-0.0"
57737       case 5'00111
57738         assign { } { }
57739         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57740       attribute \src "libresoc.v:0.0-0.0"
57741       case 5'10111
57742         assign { } { }
57743         assign $1\dec31_dec_sub9_form[4:0] 5'10001
57744       case
57745         assign $1\dec31_dec_sub9_form[4:0] 5'00000
57746     end
57747     sync always
57748       update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0]
57749   end
57750   attribute \src "libresoc.v:38930.3-38984.6"
57751   process $proc$libresoc.v:38930$850
57752     assign { } { }
57753     assign { } { }
57754     assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0]
57755     attribute \src "libresoc.v:38931.5-38931.29"
57756     switch \initial
57757       attribute \src "libresoc.v:38931.9-38931.17"
57758       case 1'1
57759       case
57760     end
57761     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57762     switch \opcode_switch
57763       attribute \src "libresoc.v:0.0-0.0"
57764       case 5'01100
57765         assign { } { }
57766         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57767       attribute \src "libresoc.v:0.0-0.0"
57768       case 5'11100
57769         assign { } { }
57770         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57771       attribute \src "libresoc.v:0.0-0.0"
57772       case 5'01101
57773         assign { } { }
57774         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57775       attribute \src "libresoc.v:0.0-0.0"
57776       case 5'11101
57777         assign { } { }
57778         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57779       attribute \src "libresoc.v:0.0-0.0"
57780       case 5'01110
57781         assign { } { }
57782         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57783       attribute \src "libresoc.v:0.0-0.0"
57784       case 5'11110
57785         assign { } { }
57786         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57787       attribute \src "libresoc.v:0.0-0.0"
57788       case 5'01111
57789         assign { } { }
57790         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57791       attribute \src "libresoc.v:0.0-0.0"
57792       case 5'11111
57793         assign { } { }
57794         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57795       attribute \src "libresoc.v:0.0-0.0"
57796       case 5'01000
57797         assign { } { }
57798         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57799       attribute \src "libresoc.v:0.0-0.0"
57800       case 5'11000
57801         assign { } { }
57802         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57803       attribute \src "libresoc.v:0.0-0.0"
57804       case 5'00010
57805         assign { } { }
57806         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57807       attribute \src "libresoc.v:0.0-0.0"
57808       case 5'00000
57809         assign { } { }
57810         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57811       attribute \src "libresoc.v:0.0-0.0"
57812       case 5'10010
57813         assign { } { }
57814         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57815       attribute \src "libresoc.v:0.0-0.0"
57816       case 5'10000
57817         assign { } { }
57818         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57819       attribute \src "libresoc.v:0.0-0.0"
57820       case 5'00111
57821         assign { } { }
57822         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57823       attribute \src "libresoc.v:0.0-0.0"
57824       case 5'10111
57825         assign { } { }
57826         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001
57827       case
57828         assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000
57829     end
57830     sync always
57831       update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0]
57832   end
57833   attribute \src "libresoc.v:38985.3-39039.6"
57834   process $proc$libresoc.v:38985$851
57835     assign { } { }
57836     assign { } { }
57837     assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0]
57838     attribute \src "libresoc.v:38986.5-38986.29"
57839     switch \initial
57840       attribute \src "libresoc.v:38986.9-38986.17"
57841       case 1'1
57842       case
57843     end
57844     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57845     switch \opcode_switch
57846       attribute \src "libresoc.v:0.0-0.0"
57847       case 5'01100
57848         assign { } { }
57849         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57850       attribute \src "libresoc.v:0.0-0.0"
57851       case 5'11100
57852         assign { } { }
57853         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57854       attribute \src "libresoc.v:0.0-0.0"
57855       case 5'01101
57856         assign { } { }
57857         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57858       attribute \src "libresoc.v:0.0-0.0"
57859       case 5'11101
57860         assign { } { }
57861         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57862       attribute \src "libresoc.v:0.0-0.0"
57863       case 5'01110
57864         assign { } { }
57865         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57866       attribute \src "libresoc.v:0.0-0.0"
57867       case 5'11110
57868         assign { } { }
57869         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57870       attribute \src "libresoc.v:0.0-0.0"
57871       case 5'01111
57872         assign { } { }
57873         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57874       attribute \src "libresoc.v:0.0-0.0"
57875       case 5'11111
57876         assign { } { }
57877         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57878       attribute \src "libresoc.v:0.0-0.0"
57879       case 5'01000
57880         assign { } { }
57881         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57882       attribute \src "libresoc.v:0.0-0.0"
57883       case 5'11000
57884         assign { } { }
57885         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57886       attribute \src "libresoc.v:0.0-0.0"
57887       case 5'00010
57888         assign { } { }
57889         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57890       attribute \src "libresoc.v:0.0-0.0"
57891       case 5'00000
57892         assign { } { }
57893         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57894       attribute \src "libresoc.v:0.0-0.0"
57895       case 5'10010
57896         assign { } { }
57897         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57898       attribute \src "libresoc.v:0.0-0.0"
57899       case 5'10000
57900         assign { } { }
57901         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57902       attribute \src "libresoc.v:0.0-0.0"
57903       case 5'00111
57904         assign { } { }
57905         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57906       attribute \src "libresoc.v:0.0-0.0"
57907       case 5'10111
57908         assign { } { }
57909         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001
57910       case
57911         assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000
57912     end
57913     sync always
57914       update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0]
57915   end
57916   attribute \src "libresoc.v:39040.3-39094.6"
57917   process $proc$libresoc.v:39040$852
57918     assign { } { }
57919     assign { } { }
57920     assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0]
57921     attribute \src "libresoc.v:39041.5-39041.29"
57922     switch \initial
57923       attribute \src "libresoc.v:39041.9-39041.17"
57924       case 1'1
57925       case
57926     end
57927     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
57928     switch \opcode_switch
57929       attribute \src "libresoc.v:0.0-0.0"
57930       case 5'01100
57931         assign { } { }
57932         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57933       attribute \src "libresoc.v:0.0-0.0"
57934       case 5'11100
57935         assign { } { }
57936         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57937       attribute \src "libresoc.v:0.0-0.0"
57938       case 5'01101
57939         assign { } { }
57940         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57941       attribute \src "libresoc.v:0.0-0.0"
57942       case 5'11101
57943         assign { } { }
57944         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57945       attribute \src "libresoc.v:0.0-0.0"
57946       case 5'01110
57947         assign { } { }
57948         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57949       attribute \src "libresoc.v:0.0-0.0"
57950       case 5'11110
57951         assign { } { }
57952         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57953       attribute \src "libresoc.v:0.0-0.0"
57954       case 5'01111
57955         assign { } { }
57956         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57957       attribute \src "libresoc.v:0.0-0.0"
57958       case 5'11111
57959         assign { } { }
57960         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57961       attribute \src "libresoc.v:0.0-0.0"
57962       case 5'01000
57963         assign { } { }
57964         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57965       attribute \src "libresoc.v:0.0-0.0"
57966       case 5'11000
57967         assign { } { }
57968         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57969       attribute \src "libresoc.v:0.0-0.0"
57970       case 5'00010
57971         assign { } { }
57972         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57973       attribute \src "libresoc.v:0.0-0.0"
57974       case 5'00000
57975         assign { } { }
57976         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57977       attribute \src "libresoc.v:0.0-0.0"
57978       case 5'10010
57979         assign { } { }
57980         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57981       attribute \src "libresoc.v:0.0-0.0"
57982       case 5'10000
57983         assign { } { }
57984         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57985       attribute \src "libresoc.v:0.0-0.0"
57986       case 5'00111
57987         assign { } { }
57988         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57989       attribute \src "libresoc.v:0.0-0.0"
57990       case 5'10111
57991         assign { } { }
57992         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57993       case
57994         assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00
57995     end
57996     sync always
57997       update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0]
57998   end
57999   attribute \src "libresoc.v:39095.3-39149.6"
58000   process $proc$libresoc.v:39095$853
58001     assign { } { }
58002     assign { } { }
58003     assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0]
58004     attribute \src "libresoc.v:39096.5-39096.29"
58005     switch \initial
58006       attribute \src "libresoc.v:39096.9-39096.17"
58007       case 1'1
58008       case
58009     end
58010     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58011     switch \opcode_switch
58012       attribute \src "libresoc.v:0.0-0.0"
58013       case 5'01100
58014         assign { } { }
58015         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58016       attribute \src "libresoc.v:0.0-0.0"
58017       case 5'11100
58018         assign { } { }
58019         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58020       attribute \src "libresoc.v:0.0-0.0"
58021       case 5'01101
58022         assign { } { }
58023         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58024       attribute \src "libresoc.v:0.0-0.0"
58025       case 5'11101
58026         assign { } { }
58027         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58028       attribute \src "libresoc.v:0.0-0.0"
58029       case 5'01110
58030         assign { } { }
58031         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58032       attribute \src "libresoc.v:0.0-0.0"
58033       case 5'11110
58034         assign { } { }
58035         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58036       attribute \src "libresoc.v:0.0-0.0"
58037       case 5'01111
58038         assign { } { }
58039         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58040       attribute \src "libresoc.v:0.0-0.0"
58041       case 5'11111
58042         assign { } { }
58043         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58044       attribute \src "libresoc.v:0.0-0.0"
58045       case 5'01000
58046         assign { } { }
58047         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58048       attribute \src "libresoc.v:0.0-0.0"
58049       case 5'11000
58050         assign { } { }
58051         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58052       attribute \src "libresoc.v:0.0-0.0"
58053       case 5'00010
58054         assign { } { }
58055         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58056       attribute \src "libresoc.v:0.0-0.0"
58057       case 5'00000
58058         assign { } { }
58059         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58060       attribute \src "libresoc.v:0.0-0.0"
58061       case 5'10010
58062         assign { } { }
58063         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58064       attribute \src "libresoc.v:0.0-0.0"
58065       case 5'10000
58066         assign { } { }
58067         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58068       attribute \src "libresoc.v:0.0-0.0"
58069       case 5'00111
58070         assign { } { }
58071         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58072       attribute \src "libresoc.v:0.0-0.0"
58073       case 5'10111
58074         assign { } { }
58075         assign $1\dec31_dec_sub9_out_sel[1:0] 2'01
58076       case
58077         assign $1\dec31_dec_sub9_out_sel[1:0] 2'00
58078     end
58079     sync always
58080       update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0]
58081   end
58082   attribute \src "libresoc.v:39150.3-39204.6"
58083   process $proc$libresoc.v:39150$854
58084     assign { } { }
58085     assign { } { }
58086     assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0]
58087     attribute \src "libresoc.v:39151.5-39151.29"
58088     switch \initial
58089       attribute \src "libresoc.v:39151.9-39151.17"
58090       case 1'1
58091       case
58092     end
58093     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58094     switch \opcode_switch
58095       attribute \src "libresoc.v:0.0-0.0"
58096       case 5'01100
58097         assign { } { }
58098         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58099       attribute \src "libresoc.v:0.0-0.0"
58100       case 5'11100
58101         assign { } { }
58102         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58103       attribute \src "libresoc.v:0.0-0.0"
58104       case 5'01101
58105         assign { } { }
58106         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58107       attribute \src "libresoc.v:0.0-0.0"
58108       case 5'11101
58109         assign { } { }
58110         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58111       attribute \src "libresoc.v:0.0-0.0"
58112       case 5'01110
58113         assign { } { }
58114         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58115       attribute \src "libresoc.v:0.0-0.0"
58116       case 5'11110
58117         assign { } { }
58118         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58119       attribute \src "libresoc.v:0.0-0.0"
58120       case 5'01111
58121         assign { } { }
58122         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58123       attribute \src "libresoc.v:0.0-0.0"
58124       case 5'11111
58125         assign { } { }
58126         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58127       attribute \src "libresoc.v:0.0-0.0"
58128       case 5'01000
58129         assign { } { }
58130         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58131       attribute \src "libresoc.v:0.0-0.0"
58132       case 5'11000
58133         assign { } { }
58134         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58135       attribute \src "libresoc.v:0.0-0.0"
58136       case 5'00010
58137         assign { } { }
58138         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58139       attribute \src "libresoc.v:0.0-0.0"
58140       case 5'00000
58141         assign { } { }
58142         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58143       attribute \src "libresoc.v:0.0-0.0"
58144       case 5'10010
58145         assign { } { }
58146         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58147       attribute \src "libresoc.v:0.0-0.0"
58148       case 5'10000
58149         assign { } { }
58150         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58151       attribute \src "libresoc.v:0.0-0.0"
58152       case 5'00111
58153         assign { } { }
58154         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58155       attribute \src "libresoc.v:0.0-0.0"
58156       case 5'10111
58157         assign { } { }
58158         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58159       case
58160         assign $1\dec31_dec_sub9_cr_in[2:0] 3'000
58161     end
58162     sync always
58163       update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0]
58164   end
58165   attribute \src "libresoc.v:39205.3-39259.6"
58166   process $proc$libresoc.v:39205$855
58167     assign { } { }
58168     assign { } { }
58169     assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0]
58170     attribute \src "libresoc.v:39206.5-39206.29"
58171     switch \initial
58172       attribute \src "libresoc.v:39206.9-39206.17"
58173       case 1'1
58174       case
58175     end
58176     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58177     switch \opcode_switch
58178       attribute \src "libresoc.v:0.0-0.0"
58179       case 5'01100
58180         assign { } { }
58181         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58182       attribute \src "libresoc.v:0.0-0.0"
58183       case 5'11100
58184         assign { } { }
58185         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58186       attribute \src "libresoc.v:0.0-0.0"
58187       case 5'01101
58188         assign { } { }
58189         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58190       attribute \src "libresoc.v:0.0-0.0"
58191       case 5'11101
58192         assign { } { }
58193         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58194       attribute \src "libresoc.v:0.0-0.0"
58195       case 5'01110
58196         assign { } { }
58197         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58198       attribute \src "libresoc.v:0.0-0.0"
58199       case 5'11110
58200         assign { } { }
58201         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58202       attribute \src "libresoc.v:0.0-0.0"
58203       case 5'01111
58204         assign { } { }
58205         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58206       attribute \src "libresoc.v:0.0-0.0"
58207       case 5'11111
58208         assign { } { }
58209         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58210       attribute \src "libresoc.v:0.0-0.0"
58211       case 5'01000
58212         assign { } { }
58213         assign $1\dec31_dec_sub9_cr_out[2:0] 3'000
58214       attribute \src "libresoc.v:0.0-0.0"
58215       case 5'11000
58216         assign { } { }
58217         assign $1\dec31_dec_sub9_cr_out[2:0] 3'000
58218       attribute \src "libresoc.v:0.0-0.0"
58219       case 5'00010
58220         assign { } { }
58221         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58222       attribute \src "libresoc.v:0.0-0.0"
58223       case 5'00000
58224         assign { } { }
58225         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58226       attribute \src "libresoc.v:0.0-0.0"
58227       case 5'10010
58228         assign { } { }
58229         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58230       attribute \src "libresoc.v:0.0-0.0"
58231       case 5'10000
58232         assign { } { }
58233         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58234       attribute \src "libresoc.v:0.0-0.0"
58235       case 5'00111
58236         assign { } { }
58237         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58238       attribute \src "libresoc.v:0.0-0.0"
58239       case 5'10111
58240         assign { } { }
58241         assign $1\dec31_dec_sub9_cr_out[2:0] 3'001
58242       case
58243         assign $1\dec31_dec_sub9_cr_out[2:0] 3'000
58244     end
58245     sync always
58246       update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0]
58247   end
58248   connect \opcode_switch \opcode_in [10:6]
58249 end
58250 attribute \src "libresoc.v:39265.1-39908.10"
58251 attribute \cells_not_processed 1
58252 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58"
58253 attribute \generator "nMigen"
58254 module \dec58
58255   attribute \src "libresoc.v:39603.3-39618.6"
58256   wire width 8 $0\dec58_asmcode[7:0]
58257   attribute \src "libresoc.v:39667.3-39682.6"
58258   wire $0\dec58_br[0:0]
58259   attribute \src "libresoc.v:39875.3-39890.6"
58260   wire width 3 $0\dec58_cr_in[2:0]
58261   attribute \src "libresoc.v:39891.3-39906.6"
58262   wire width 3 $0\dec58_cr_out[2:0]
58263   attribute \src "libresoc.v:39587.3-39602.6"
58264   wire width 2 $0\dec58_cry_in[1:0]
58265   attribute \src "libresoc.v:39651.3-39666.6"
58266   wire $0\dec58_cry_out[0:0]
58267   attribute \src "libresoc.v:39795.3-39810.6"
58268   wire width 5 $0\dec58_form[4:0]
58269   attribute \src "libresoc.v:39523.3-39538.6"
58270   wire width 12 $0\dec58_function_unit[11:0]
58271   attribute \src "libresoc.v:39811.3-39826.6"
58272   wire width 3 $0\dec58_in1_sel[2:0]
58273   attribute \src "libresoc.v:39827.3-39842.6"
58274   wire width 4 $0\dec58_in2_sel[3:0]
58275   attribute \src "libresoc.v:39843.3-39858.6"
58276   wire width 2 $0\dec58_in3_sel[1:0]
58277   attribute \src "libresoc.v:39699.3-39714.6"
58278   wire width 7 $0\dec58_internal_op[6:0]
58279   attribute \src "libresoc.v:39619.3-39634.6"
58280   wire $0\dec58_inv_a[0:0]
58281   attribute \src "libresoc.v:39635.3-39650.6"
58282   wire $0\dec58_inv_out[0:0]
58283   attribute \src "libresoc.v:39731.3-39746.6"
58284   wire $0\dec58_is_32b[0:0]
58285   attribute \src "libresoc.v:39539.3-39554.6"
58286   wire width 4 $0\dec58_ldst_len[3:0]
58287   attribute \src "libresoc.v:39763.3-39778.6"
58288   wire $0\dec58_lk[0:0]
58289   attribute \src "libresoc.v:39859.3-39874.6"
58290   wire width 2 $0\dec58_out_sel[1:0]
58291   attribute \src "libresoc.v:39571.3-39586.6"
58292   wire width 2 $0\dec58_rc_sel[1:0]
58293   attribute \src "libresoc.v:39715.3-39730.6"
58294   wire $0\dec58_rsrv[0:0]
58295   attribute \src "libresoc.v:39779.3-39794.6"
58296   wire $0\dec58_sgl_pipe[0:0]
58297   attribute \src "libresoc.v:39747.3-39762.6"
58298   wire $0\dec58_sgn[0:0]
58299   attribute \src "libresoc.v:39683.3-39698.6"
58300   wire $0\dec58_sgn_ext[0:0]
58301   attribute \src "libresoc.v:39555.3-39570.6"
58302   wire width 2 $0\dec58_upd[1:0]
58303   attribute \src "libresoc.v:39266.7-39266.20"
58304   wire $0\initial[0:0]
58305   attribute \src "libresoc.v:39603.3-39618.6"
58306   wire width 8 $1\dec58_asmcode[7:0]
58307   attribute \src "libresoc.v:39667.3-39682.6"
58308   wire $1\dec58_br[0:0]
58309   attribute \src "libresoc.v:39875.3-39890.6"
58310   wire width 3 $1\dec58_cr_in[2:0]
58311   attribute \src "libresoc.v:39891.3-39906.6"
58312   wire width 3 $1\dec58_cr_out[2:0]
58313   attribute \src "libresoc.v:39587.3-39602.6"
58314   wire width 2 $1\dec58_cry_in[1:0]
58315   attribute \src "libresoc.v:39651.3-39666.6"
58316   wire $1\dec58_cry_out[0:0]
58317   attribute \src "libresoc.v:39795.3-39810.6"
58318   wire width 5 $1\dec58_form[4:0]
58319   attribute \src "libresoc.v:39523.3-39538.6"
58320   wire width 12 $1\dec58_function_unit[11:0]
58321   attribute \src "libresoc.v:39811.3-39826.6"
58322   wire width 3 $1\dec58_in1_sel[2:0]
58323   attribute \src "libresoc.v:39827.3-39842.6"
58324   wire width 4 $1\dec58_in2_sel[3:0]
58325   attribute \src "libresoc.v:39843.3-39858.6"
58326   wire width 2 $1\dec58_in3_sel[1:0]
58327   attribute \src "libresoc.v:39699.3-39714.6"
58328   wire width 7 $1\dec58_internal_op[6:0]
58329   attribute \src "libresoc.v:39619.3-39634.6"
58330   wire $1\dec58_inv_a[0:0]
58331   attribute \src "libresoc.v:39635.3-39650.6"
58332   wire $1\dec58_inv_out[0:0]
58333   attribute \src "libresoc.v:39731.3-39746.6"
58334   wire $1\dec58_is_32b[0:0]
58335   attribute \src "libresoc.v:39539.3-39554.6"
58336   wire width 4 $1\dec58_ldst_len[3:0]
58337   attribute \src "libresoc.v:39763.3-39778.6"
58338   wire $1\dec58_lk[0:0]
58339   attribute \src "libresoc.v:39859.3-39874.6"
58340   wire width 2 $1\dec58_out_sel[1:0]
58341   attribute \src "libresoc.v:39571.3-39586.6"
58342   wire width 2 $1\dec58_rc_sel[1:0]
58343   attribute \src "libresoc.v:39715.3-39730.6"
58344   wire $1\dec58_rsrv[0:0]
58345   attribute \src "libresoc.v:39779.3-39794.6"
58346   wire $1\dec58_sgl_pipe[0:0]
58347   attribute \src "libresoc.v:39747.3-39762.6"
58348   wire $1\dec58_sgn[0:0]
58349   attribute \src "libresoc.v:39683.3-39698.6"
58350   wire $1\dec58_sgn_ext[0:0]
58351   attribute \src "libresoc.v:39555.3-39570.6"
58352   wire width 2 $1\dec58_upd[1:0]
58353   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58354   wire width 8 output 4 \dec58_asmcode
58355   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58356   wire output 18 \dec58_br
58357   attribute \enum_base_type "CRInSel"
58358   attribute \enum_value_000 "NONE"
58359   attribute \enum_value_001 "CR0"
58360   attribute \enum_value_010 "BI"
58361   attribute \enum_value_011 "BFA"
58362   attribute \enum_value_100 "BA_BB"
58363   attribute \enum_value_101 "BC"
58364   attribute \enum_value_110 "WHOLE_REG"
58365   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58366   wire width 3 output 9 \dec58_cr_in
58367   attribute \enum_base_type "CROutSel"
58368   attribute \enum_value_000 "NONE"
58369   attribute \enum_value_001 "CR0"
58370   attribute \enum_value_010 "BF"
58371   attribute \enum_value_011 "BT"
58372   attribute \enum_value_100 "WHOLE_REG"
58373   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58374   wire width 3 output 10 \dec58_cr_out
58375   attribute \enum_base_type "CryIn"
58376   attribute \enum_value_00 "ZERO"
58377   attribute \enum_value_01 "ONE"
58378   attribute \enum_value_10 "CA"
58379   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58380   wire width 2 output 14 \dec58_cry_in
58381   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58382   wire output 17 \dec58_cry_out
58383   attribute \enum_base_type "Form"
58384   attribute \enum_value_00000 "NONE"
58385   attribute \enum_value_00001 "I"
58386   attribute \enum_value_00010 "B"
58387   attribute \enum_value_00011 "SC"
58388   attribute \enum_value_00100 "D"
58389   attribute \enum_value_00101 "DS"
58390   attribute \enum_value_00110 "DQ"
58391   attribute \enum_value_00111 "DX"
58392   attribute \enum_value_01000 "X"
58393   attribute \enum_value_01001 "XL"
58394   attribute \enum_value_01010 "XFX"
58395   attribute \enum_value_01011 "XFL"
58396   attribute \enum_value_01100 "XX1"
58397   attribute \enum_value_01101 "XX2"
58398   attribute \enum_value_01110 "XX3"
58399   attribute \enum_value_01111 "XX4"
58400   attribute \enum_value_10000 "XS"
58401   attribute \enum_value_10001 "XO"
58402   attribute \enum_value_10010 "A"
58403   attribute \enum_value_10011 "M"
58404   attribute \enum_value_10100 "MD"
58405   attribute \enum_value_10101 "MDS"
58406   attribute \enum_value_10110 "VA"
58407   attribute \enum_value_10111 "VC"
58408   attribute \enum_value_11000 "VX"
58409   attribute \enum_value_11001 "EVX"
58410   attribute \enum_value_11010 "EVS"
58411   attribute \enum_value_11011 "Z22"
58412   attribute \enum_value_11100 "Z23"
58413   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58414   wire width 5 output 3 \dec58_form
58415   attribute \enum_base_type "Function"
58416   attribute \enum_value_000000000000 "NONE"
58417   attribute \enum_value_000000000010 "ALU"
58418   attribute \enum_value_000000000100 "LDST"
58419   attribute \enum_value_000000001000 "SHIFT_ROT"
58420   attribute \enum_value_000000010000 "LOGICAL"
58421   attribute \enum_value_000000100000 "BRANCH"
58422   attribute \enum_value_000001000000 "CR"
58423   attribute \enum_value_000010000000 "TRAP"
58424   attribute \enum_value_000100000000 "MUL"
58425   attribute \enum_value_001000000000 "DIV"
58426   attribute \enum_value_010000000000 "SPR"
58427   attribute \enum_value_100000000000 "MMU"
58428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58429   wire width 12 output 1 \dec58_function_unit
58430   attribute \enum_base_type "In1Sel"
58431   attribute \enum_value_000 "NONE"
58432   attribute \enum_value_001 "RA"
58433   attribute \enum_value_010 "RA_OR_ZERO"
58434   attribute \enum_value_011 "SPR"
58435   attribute \enum_value_100 "RS"
58436   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58437   wire width 3 output 5 \dec58_in1_sel
58438   attribute \enum_base_type "In2Sel"
58439   attribute \enum_value_0000 "NONE"
58440   attribute \enum_value_0001 "RB"
58441   attribute \enum_value_0010 "CONST_UI"
58442   attribute \enum_value_0011 "CONST_SI"
58443   attribute \enum_value_0100 "CONST_UI_HI"
58444   attribute \enum_value_0101 "CONST_SI_HI"
58445   attribute \enum_value_0110 "CONST_LI"
58446   attribute \enum_value_0111 "CONST_BD"
58447   attribute \enum_value_1000 "CONST_DS"
58448   attribute \enum_value_1001 "CONST_M1"
58449   attribute \enum_value_1010 "CONST_SH"
58450   attribute \enum_value_1011 "CONST_SH32"
58451   attribute \enum_value_1100 "SPR"
58452   attribute \enum_value_1101 "RS"
58453   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58454   wire width 4 output 6 \dec58_in2_sel
58455   attribute \enum_base_type "In3Sel"
58456   attribute \enum_value_00 "NONE"
58457   attribute \enum_value_01 "RS"
58458   attribute \enum_value_10 "RB"
58459   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58460   wire width 2 output 7 \dec58_in3_sel
58461   attribute \enum_base_type "MicrOp"
58462   attribute \enum_value_0000000 "OP_ILLEGAL"
58463   attribute \enum_value_0000001 "OP_NOP"
58464   attribute \enum_value_0000010 "OP_ADD"
58465   attribute \enum_value_0000011 "OP_ADDPCIS"
58466   attribute \enum_value_0000100 "OP_AND"
58467   attribute \enum_value_0000101 "OP_ATTN"
58468   attribute \enum_value_0000110 "OP_B"
58469   attribute \enum_value_0000111 "OP_BC"
58470   attribute \enum_value_0001000 "OP_BCREG"
58471   attribute \enum_value_0001001 "OP_BPERM"
58472   attribute \enum_value_0001010 "OP_CMP"
58473   attribute \enum_value_0001011 "OP_CMPB"
58474   attribute \enum_value_0001100 "OP_CMPEQB"
58475   attribute \enum_value_0001101 "OP_CMPRB"
58476   attribute \enum_value_0001110 "OP_CNTZ"
58477   attribute \enum_value_0001111 "OP_CRAND"
58478   attribute \enum_value_0010000 "OP_CRANDC"
58479   attribute \enum_value_0010001 "OP_CREQV"
58480   attribute \enum_value_0010010 "OP_CRNAND"
58481   attribute \enum_value_0010011 "OP_CRNOR"
58482   attribute \enum_value_0010100 "OP_CROR"
58483   attribute \enum_value_0010101 "OP_CRORC"
58484   attribute \enum_value_0010110 "OP_CRXOR"
58485   attribute \enum_value_0010111 "OP_DARN"
58486   attribute \enum_value_0011000 "OP_DCBF"
58487   attribute \enum_value_0011001 "OP_DCBST"
58488   attribute \enum_value_0011010 "OP_DCBT"
58489   attribute \enum_value_0011011 "OP_DCBTST"
58490   attribute \enum_value_0011100 "OP_DCBZ"
58491   attribute \enum_value_0011101 "OP_DIV"
58492   attribute \enum_value_0011110 "OP_DIVE"
58493   attribute \enum_value_0011111 "OP_EXTS"
58494   attribute \enum_value_0100000 "OP_EXTSWSLI"
58495   attribute \enum_value_0100001 "OP_ICBI"
58496   attribute \enum_value_0100010 "OP_ICBT"
58497   attribute \enum_value_0100011 "OP_ISEL"
58498   attribute \enum_value_0100100 "OP_ISYNC"
58499   attribute \enum_value_0100101 "OP_LOAD"
58500   attribute \enum_value_0100110 "OP_STORE"
58501   attribute \enum_value_0100111 "OP_MADDHD"
58502   attribute \enum_value_0101000 "OP_MADDHDU"
58503   attribute \enum_value_0101001 "OP_MADDLD"
58504   attribute \enum_value_0101010 "OP_MCRF"
58505   attribute \enum_value_0101011 "OP_MCRXR"
58506   attribute \enum_value_0101100 "OP_MCRXRX"
58507   attribute \enum_value_0101101 "OP_MFCR"
58508   attribute \enum_value_0101110 "OP_MFSPR"
58509   attribute \enum_value_0101111 "OP_MOD"
58510   attribute \enum_value_0110000 "OP_MTCRF"
58511   attribute \enum_value_0110001 "OP_MTSPR"
58512   attribute \enum_value_0110010 "OP_MUL_L64"
58513   attribute \enum_value_0110011 "OP_MUL_H64"
58514   attribute \enum_value_0110100 "OP_MUL_H32"
58515   attribute \enum_value_0110101 "OP_OR"
58516   attribute \enum_value_0110110 "OP_POPCNT"
58517   attribute \enum_value_0110111 "OP_PRTY"
58518   attribute \enum_value_0111000 "OP_RLC"
58519   attribute \enum_value_0111001 "OP_RLCL"
58520   attribute \enum_value_0111010 "OP_RLCR"
58521   attribute \enum_value_0111011 "OP_SETB"
58522   attribute \enum_value_0111100 "OP_SHL"
58523   attribute \enum_value_0111101 "OP_SHR"
58524   attribute \enum_value_0111110 "OP_SYNC"
58525   attribute \enum_value_0111111 "OP_TRAP"
58526   attribute \enum_value_1000011 "OP_XOR"
58527   attribute \enum_value_1000100 "OP_SIM_CONFIG"
58528   attribute \enum_value_1000101 "OP_CROP"
58529   attribute \enum_value_1000110 "OP_RFID"
58530   attribute \enum_value_1000111 "OP_MFMSR"
58531   attribute \enum_value_1001000 "OP_MTMSRD"
58532   attribute \enum_value_1001001 "OP_SC"
58533   attribute \enum_value_1001010 "OP_MTMSR"
58534   attribute \enum_value_1001011 "OP_TLBIE"
58535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58536   wire width 7 output 2 \dec58_internal_op
58537   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58538   wire output 15 \dec58_inv_a
58539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58540   wire output 16 \dec58_inv_out
58541   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58542   wire output 21 \dec58_is_32b
58543   attribute \enum_base_type "LdstLen"
58544   attribute \enum_value_0000 "NONE"
58545   attribute \enum_value_0001 "is1B"
58546   attribute \enum_value_0010 "is2B"
58547   attribute \enum_value_0100 "is4B"
58548   attribute \enum_value_1000 "is8B"
58549   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58550   wire width 4 output 11 \dec58_ldst_len
58551   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58552   wire output 23 \dec58_lk
58553   attribute \enum_base_type "OutSel"
58554   attribute \enum_value_00 "NONE"
58555   attribute \enum_value_01 "RT"
58556   attribute \enum_value_10 "RA"
58557   attribute \enum_value_11 "SPR"
58558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58559   wire width 2 output 8 \dec58_out_sel
58560   attribute \enum_base_type "RC"
58561   attribute \enum_value_00 "NONE"
58562   attribute \enum_value_01 "ONE"
58563   attribute \enum_value_10 "RC"
58564   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58565   wire width 2 output 13 \dec58_rc_sel
58566   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58567   wire output 20 \dec58_rsrv
58568   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58569   wire output 24 \dec58_sgl_pipe
58570   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58571   wire output 22 \dec58_sgn
58572   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
58573   wire output 19 \dec58_sgn_ext
58574   attribute \enum_base_type "LDSTMode"
58575   attribute \enum_value_00 "NONE"
58576   attribute \enum_value_01 "update"
58577   attribute \enum_value_10 "cix"
58578   attribute \enum_value_11 "cx"
58579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
58580   wire width 2 output 12 \dec58_upd
58581   attribute \src "libresoc.v:39266.7-39266.15"
58582   wire \initial
58583   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
58584   wire width 32 input 25 \opcode_in
58585   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
58586   wire width 2 \opcode_switch
58587   attribute \src "libresoc.v:39266.7-39266.20"
58588   process $proc$libresoc.v:39266$881
58589     assign { } { }
58590     assign $0\initial[0:0] 1'0
58591     sync always
58592       update \initial $0\initial[0:0]
58593     sync init
58594   end
58595   attribute \src "libresoc.v:39523.3-39538.6"
58596   process $proc$libresoc.v:39523$857
58597     assign { } { }
58598     assign { } { }
58599     assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0]
58600     attribute \src "libresoc.v:39524.5-39524.29"
58601     switch \initial
58602       attribute \src "libresoc.v:39524.9-39524.17"
58603       case 1'1
58604       case
58605     end
58606     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58607     switch \opcode_switch
58608       attribute \src "libresoc.v:0.0-0.0"
58609       case 2'00
58610         assign { } { }
58611         assign $1\dec58_function_unit[11:0] 12'000000000100
58612       attribute \src "libresoc.v:0.0-0.0"
58613       case 2'01
58614         assign { } { }
58615         assign $1\dec58_function_unit[11:0] 12'000000000100
58616       attribute \src "libresoc.v:0.0-0.0"
58617       case 2'10
58618         assign { } { }
58619         assign $1\dec58_function_unit[11:0] 12'000000000100
58620       case
58621         assign $1\dec58_function_unit[11:0] 12'000000000000
58622     end
58623     sync always
58624       update \dec58_function_unit $0\dec58_function_unit[11:0]
58625   end
58626   attribute \src "libresoc.v:39539.3-39554.6"
58627   process $proc$libresoc.v:39539$858
58628     assign { } { }
58629     assign { } { }
58630     assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0]
58631     attribute \src "libresoc.v:39540.5-39540.29"
58632     switch \initial
58633       attribute \src "libresoc.v:39540.9-39540.17"
58634       case 1'1
58635       case
58636     end
58637     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58638     switch \opcode_switch
58639       attribute \src "libresoc.v:0.0-0.0"
58640       case 2'00
58641         assign { } { }
58642         assign $1\dec58_ldst_len[3:0] 4'1000
58643       attribute \src "libresoc.v:0.0-0.0"
58644       case 2'01
58645         assign { } { }
58646         assign $1\dec58_ldst_len[3:0] 4'1000
58647       attribute \src "libresoc.v:0.0-0.0"
58648       case 2'10
58649         assign { } { }
58650         assign $1\dec58_ldst_len[3:0] 4'0100
58651       case
58652         assign $1\dec58_ldst_len[3:0] 4'0000
58653     end
58654     sync always
58655       update \dec58_ldst_len $0\dec58_ldst_len[3:0]
58656   end
58657   attribute \src "libresoc.v:39555.3-39570.6"
58658   process $proc$libresoc.v:39555$859
58659     assign { } { }
58660     assign { } { }
58661     assign $0\dec58_upd[1:0] $1\dec58_upd[1:0]
58662     attribute \src "libresoc.v:39556.5-39556.29"
58663     switch \initial
58664       attribute \src "libresoc.v:39556.9-39556.17"
58665       case 1'1
58666       case
58667     end
58668     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58669     switch \opcode_switch
58670       attribute \src "libresoc.v:0.0-0.0"
58671       case 2'00
58672         assign { } { }
58673         assign $1\dec58_upd[1:0] 2'00
58674       attribute \src "libresoc.v:0.0-0.0"
58675       case 2'01
58676         assign { } { }
58677         assign $1\dec58_upd[1:0] 2'01
58678       attribute \src "libresoc.v:0.0-0.0"
58679       case 2'10
58680         assign { } { }
58681         assign $1\dec58_upd[1:0] 2'00
58682       case
58683         assign $1\dec58_upd[1:0] 2'00
58684     end
58685     sync always
58686       update \dec58_upd $0\dec58_upd[1:0]
58687   end
58688   attribute \src "libresoc.v:39571.3-39586.6"
58689   process $proc$libresoc.v:39571$860
58690     assign { } { }
58691     assign { } { }
58692     assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0]
58693     attribute \src "libresoc.v:39572.5-39572.29"
58694     switch \initial
58695       attribute \src "libresoc.v:39572.9-39572.17"
58696       case 1'1
58697       case
58698     end
58699     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58700     switch \opcode_switch
58701       attribute \src "libresoc.v:0.0-0.0"
58702       case 2'00
58703         assign { } { }
58704         assign $1\dec58_rc_sel[1:0] 2'00
58705       attribute \src "libresoc.v:0.0-0.0"
58706       case 2'01
58707         assign { } { }
58708         assign $1\dec58_rc_sel[1:0] 2'00
58709       attribute \src "libresoc.v:0.0-0.0"
58710       case 2'10
58711         assign { } { }
58712         assign $1\dec58_rc_sel[1:0] 2'00
58713       case
58714         assign $1\dec58_rc_sel[1:0] 2'00
58715     end
58716     sync always
58717       update \dec58_rc_sel $0\dec58_rc_sel[1:0]
58718   end
58719   attribute \src "libresoc.v:39587.3-39602.6"
58720   process $proc$libresoc.v:39587$861
58721     assign { } { }
58722     assign { } { }
58723     assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0]
58724     attribute \src "libresoc.v:39588.5-39588.29"
58725     switch \initial
58726       attribute \src "libresoc.v:39588.9-39588.17"
58727       case 1'1
58728       case
58729     end
58730     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58731     switch \opcode_switch
58732       attribute \src "libresoc.v:0.0-0.0"
58733       case 2'00
58734         assign { } { }
58735         assign $1\dec58_cry_in[1:0] 2'00
58736       attribute \src "libresoc.v:0.0-0.0"
58737       case 2'01
58738         assign { } { }
58739         assign $1\dec58_cry_in[1:0] 2'00
58740       attribute \src "libresoc.v:0.0-0.0"
58741       case 2'10
58742         assign { } { }
58743         assign $1\dec58_cry_in[1:0] 2'00
58744       case
58745         assign $1\dec58_cry_in[1:0] 2'00
58746     end
58747     sync always
58748       update \dec58_cry_in $0\dec58_cry_in[1:0]
58749   end
58750   attribute \src "libresoc.v:39603.3-39618.6"
58751   process $proc$libresoc.v:39603$862
58752     assign { } { }
58753     assign { } { }
58754     assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0]
58755     attribute \src "libresoc.v:39604.5-39604.29"
58756     switch \initial
58757       attribute \src "libresoc.v:39604.9-39604.17"
58758       case 1'1
58759       case
58760     end
58761     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58762     switch \opcode_switch
58763       attribute \src "libresoc.v:0.0-0.0"
58764       case 2'00
58765         assign { } { }
58766         assign $1\dec58_asmcode[7:0] 8'01010010
58767       attribute \src "libresoc.v:0.0-0.0"
58768       case 2'01
58769         assign { } { }
58770         assign $1\dec58_asmcode[7:0] 8'01010101
58771       attribute \src "libresoc.v:0.0-0.0"
58772       case 2'10
58773         assign { } { }
58774         assign $1\dec58_asmcode[7:0] 8'01100010
58775       case
58776         assign $1\dec58_asmcode[7:0] 8'00000000
58777     end
58778     sync always
58779       update \dec58_asmcode $0\dec58_asmcode[7:0]
58780   end
58781   attribute \src "libresoc.v:39619.3-39634.6"
58782   process $proc$libresoc.v:39619$863
58783     assign { } { }
58784     assign { } { }
58785     assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0]
58786     attribute \src "libresoc.v:39620.5-39620.29"
58787     switch \initial
58788       attribute \src "libresoc.v:39620.9-39620.17"
58789       case 1'1
58790       case
58791     end
58792     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58793     switch \opcode_switch
58794       attribute \src "libresoc.v:0.0-0.0"
58795       case 2'00
58796         assign { } { }
58797         assign $1\dec58_inv_a[0:0] 1'0
58798       attribute \src "libresoc.v:0.0-0.0"
58799       case 2'01
58800         assign { } { }
58801         assign $1\dec58_inv_a[0:0] 1'0
58802       attribute \src "libresoc.v:0.0-0.0"
58803       case 2'10
58804         assign { } { }
58805         assign $1\dec58_inv_a[0:0] 1'0
58806       case
58807         assign $1\dec58_inv_a[0:0] 1'0
58808     end
58809     sync always
58810       update \dec58_inv_a $0\dec58_inv_a[0:0]
58811   end
58812   attribute \src "libresoc.v:39635.3-39650.6"
58813   process $proc$libresoc.v:39635$864
58814     assign { } { }
58815     assign { } { }
58816     assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0]
58817     attribute \src "libresoc.v:39636.5-39636.29"
58818     switch \initial
58819       attribute \src "libresoc.v:39636.9-39636.17"
58820       case 1'1
58821       case
58822     end
58823     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58824     switch \opcode_switch
58825       attribute \src "libresoc.v:0.0-0.0"
58826       case 2'00
58827         assign { } { }
58828         assign $1\dec58_inv_out[0:0] 1'0
58829       attribute \src "libresoc.v:0.0-0.0"
58830       case 2'01
58831         assign { } { }
58832         assign $1\dec58_inv_out[0:0] 1'0
58833       attribute \src "libresoc.v:0.0-0.0"
58834       case 2'10
58835         assign { } { }
58836         assign $1\dec58_inv_out[0:0] 1'0
58837       case
58838         assign $1\dec58_inv_out[0:0] 1'0
58839     end
58840     sync always
58841       update \dec58_inv_out $0\dec58_inv_out[0:0]
58842   end
58843   attribute \src "libresoc.v:39651.3-39666.6"
58844   process $proc$libresoc.v:39651$865
58845     assign { } { }
58846     assign { } { }
58847     assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0]
58848     attribute \src "libresoc.v:39652.5-39652.29"
58849     switch \initial
58850       attribute \src "libresoc.v:39652.9-39652.17"
58851       case 1'1
58852       case
58853     end
58854     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58855     switch \opcode_switch
58856       attribute \src "libresoc.v:0.0-0.0"
58857       case 2'00
58858         assign { } { }
58859         assign $1\dec58_cry_out[0:0] 1'0
58860       attribute \src "libresoc.v:0.0-0.0"
58861       case 2'01
58862         assign { } { }
58863         assign $1\dec58_cry_out[0:0] 1'0
58864       attribute \src "libresoc.v:0.0-0.0"
58865       case 2'10
58866         assign { } { }
58867         assign $1\dec58_cry_out[0:0] 1'0
58868       case
58869         assign $1\dec58_cry_out[0:0] 1'0
58870     end
58871     sync always
58872       update \dec58_cry_out $0\dec58_cry_out[0:0]
58873   end
58874   attribute \src "libresoc.v:39667.3-39682.6"
58875   process $proc$libresoc.v:39667$866
58876     assign { } { }
58877     assign { } { }
58878     assign $0\dec58_br[0:0] $1\dec58_br[0:0]
58879     attribute \src "libresoc.v:39668.5-39668.29"
58880     switch \initial
58881       attribute \src "libresoc.v:39668.9-39668.17"
58882       case 1'1
58883       case
58884     end
58885     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58886     switch \opcode_switch
58887       attribute \src "libresoc.v:0.0-0.0"
58888       case 2'00
58889         assign { } { }
58890         assign $1\dec58_br[0:0] 1'0
58891       attribute \src "libresoc.v:0.0-0.0"
58892       case 2'01
58893         assign { } { }
58894         assign $1\dec58_br[0:0] 1'0
58895       attribute \src "libresoc.v:0.0-0.0"
58896       case 2'10
58897         assign { } { }
58898         assign $1\dec58_br[0:0] 1'0
58899       case
58900         assign $1\dec58_br[0:0] 1'0
58901     end
58902     sync always
58903       update \dec58_br $0\dec58_br[0:0]
58904   end
58905   attribute \src "libresoc.v:39683.3-39698.6"
58906   process $proc$libresoc.v:39683$867
58907     assign { } { }
58908     assign { } { }
58909     assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0]
58910     attribute \src "libresoc.v:39684.5-39684.29"
58911     switch \initial
58912       attribute \src "libresoc.v:39684.9-39684.17"
58913       case 1'1
58914       case
58915     end
58916     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58917     switch \opcode_switch
58918       attribute \src "libresoc.v:0.0-0.0"
58919       case 2'00
58920         assign { } { }
58921         assign $1\dec58_sgn_ext[0:0] 1'0
58922       attribute \src "libresoc.v:0.0-0.0"
58923       case 2'01
58924         assign { } { }
58925         assign $1\dec58_sgn_ext[0:0] 1'0
58926       attribute \src "libresoc.v:0.0-0.0"
58927       case 2'10
58928         assign { } { }
58929         assign $1\dec58_sgn_ext[0:0] 1'1
58930       case
58931         assign $1\dec58_sgn_ext[0:0] 1'0
58932     end
58933     sync always
58934       update \dec58_sgn_ext $0\dec58_sgn_ext[0:0]
58935   end
58936   attribute \src "libresoc.v:39699.3-39714.6"
58937   process $proc$libresoc.v:39699$868
58938     assign { } { }
58939     assign { } { }
58940     assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0]
58941     attribute \src "libresoc.v:39700.5-39700.29"
58942     switch \initial
58943       attribute \src "libresoc.v:39700.9-39700.17"
58944       case 1'1
58945       case
58946     end
58947     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58948     switch \opcode_switch
58949       attribute \src "libresoc.v:0.0-0.0"
58950       case 2'00
58951         assign { } { }
58952         assign $1\dec58_internal_op[6:0] 7'0100101
58953       attribute \src "libresoc.v:0.0-0.0"
58954       case 2'01
58955         assign { } { }
58956         assign $1\dec58_internal_op[6:0] 7'0100101
58957       attribute \src "libresoc.v:0.0-0.0"
58958       case 2'10
58959         assign { } { }
58960         assign $1\dec58_internal_op[6:0] 7'0100101
58961       case
58962         assign $1\dec58_internal_op[6:0] 7'0000000
58963     end
58964     sync always
58965       update \dec58_internal_op $0\dec58_internal_op[6:0]
58966   end
58967   attribute \src "libresoc.v:39715.3-39730.6"
58968   process $proc$libresoc.v:39715$869
58969     assign { } { }
58970     assign { } { }
58971     assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0]
58972     attribute \src "libresoc.v:39716.5-39716.29"
58973     switch \initial
58974       attribute \src "libresoc.v:39716.9-39716.17"
58975       case 1'1
58976       case
58977     end
58978     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
58979     switch \opcode_switch
58980       attribute \src "libresoc.v:0.0-0.0"
58981       case 2'00
58982         assign { } { }
58983         assign $1\dec58_rsrv[0:0] 1'0
58984       attribute \src "libresoc.v:0.0-0.0"
58985       case 2'01
58986         assign { } { }
58987         assign $1\dec58_rsrv[0:0] 1'0
58988       attribute \src "libresoc.v:0.0-0.0"
58989       case 2'10
58990         assign { } { }
58991         assign $1\dec58_rsrv[0:0] 1'0
58992       case
58993         assign $1\dec58_rsrv[0:0] 1'0
58994     end
58995     sync always
58996       update \dec58_rsrv $0\dec58_rsrv[0:0]
58997   end
58998   attribute \src "libresoc.v:39731.3-39746.6"
58999   process $proc$libresoc.v:39731$870
59000     assign { } { }
59001     assign { } { }
59002     assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0]
59003     attribute \src "libresoc.v:39732.5-39732.29"
59004     switch \initial
59005       attribute \src "libresoc.v:39732.9-39732.17"
59006       case 1'1
59007       case
59008     end
59009     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59010     switch \opcode_switch
59011       attribute \src "libresoc.v:0.0-0.0"
59012       case 2'00
59013         assign { } { }
59014         assign $1\dec58_is_32b[0:0] 1'0
59015       attribute \src "libresoc.v:0.0-0.0"
59016       case 2'01
59017         assign { } { }
59018         assign $1\dec58_is_32b[0:0] 1'0
59019       attribute \src "libresoc.v:0.0-0.0"
59020       case 2'10
59021         assign { } { }
59022         assign $1\dec58_is_32b[0:0] 1'0
59023       case
59024         assign $1\dec58_is_32b[0:0] 1'0
59025     end
59026     sync always
59027       update \dec58_is_32b $0\dec58_is_32b[0:0]
59028   end
59029   attribute \src "libresoc.v:39747.3-39762.6"
59030   process $proc$libresoc.v:39747$871
59031     assign { } { }
59032     assign { } { }
59033     assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0]
59034     attribute \src "libresoc.v:39748.5-39748.29"
59035     switch \initial
59036       attribute \src "libresoc.v:39748.9-39748.17"
59037       case 1'1
59038       case
59039     end
59040     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59041     switch \opcode_switch
59042       attribute \src "libresoc.v:0.0-0.0"
59043       case 2'00
59044         assign { } { }
59045         assign $1\dec58_sgn[0:0] 1'0
59046       attribute \src "libresoc.v:0.0-0.0"
59047       case 2'01
59048         assign { } { }
59049         assign $1\dec58_sgn[0:0] 1'0
59050       attribute \src "libresoc.v:0.0-0.0"
59051       case 2'10
59052         assign { } { }
59053         assign $1\dec58_sgn[0:0] 1'0
59054       case
59055         assign $1\dec58_sgn[0:0] 1'0
59056     end
59057     sync always
59058       update \dec58_sgn $0\dec58_sgn[0:0]
59059   end
59060   attribute \src "libresoc.v:39763.3-39778.6"
59061   process $proc$libresoc.v:39763$872
59062     assign { } { }
59063     assign { } { }
59064     assign $0\dec58_lk[0:0] $1\dec58_lk[0:0]
59065     attribute \src "libresoc.v:39764.5-39764.29"
59066     switch \initial
59067       attribute \src "libresoc.v:39764.9-39764.17"
59068       case 1'1
59069       case
59070     end
59071     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59072     switch \opcode_switch
59073       attribute \src "libresoc.v:0.0-0.0"
59074       case 2'00
59075         assign { } { }
59076         assign $1\dec58_lk[0:0] 1'0
59077       attribute \src "libresoc.v:0.0-0.0"
59078       case 2'01
59079         assign { } { }
59080         assign $1\dec58_lk[0:0] 1'0
59081       attribute \src "libresoc.v:0.0-0.0"
59082       case 2'10
59083         assign { } { }
59084         assign $1\dec58_lk[0:0] 1'0
59085       case
59086         assign $1\dec58_lk[0:0] 1'0
59087     end
59088     sync always
59089       update \dec58_lk $0\dec58_lk[0:0]
59090   end
59091   attribute \src "libresoc.v:39779.3-39794.6"
59092   process $proc$libresoc.v:39779$873
59093     assign { } { }
59094     assign { } { }
59095     assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0]
59096     attribute \src "libresoc.v:39780.5-39780.29"
59097     switch \initial
59098       attribute \src "libresoc.v:39780.9-39780.17"
59099       case 1'1
59100       case
59101     end
59102     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59103     switch \opcode_switch
59104       attribute \src "libresoc.v:0.0-0.0"
59105       case 2'00
59106         assign { } { }
59107         assign $1\dec58_sgl_pipe[0:0] 1'1
59108       attribute \src "libresoc.v:0.0-0.0"
59109       case 2'01
59110         assign { } { }
59111         assign $1\dec58_sgl_pipe[0:0] 1'1
59112       attribute \src "libresoc.v:0.0-0.0"
59113       case 2'10
59114         assign { } { }
59115         assign $1\dec58_sgl_pipe[0:0] 1'1
59116       case
59117         assign $1\dec58_sgl_pipe[0:0] 1'0
59118     end
59119     sync always
59120       update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0]
59121   end
59122   attribute \src "libresoc.v:39795.3-39810.6"
59123   process $proc$libresoc.v:39795$874
59124     assign { } { }
59125     assign { } { }
59126     assign $0\dec58_form[4:0] $1\dec58_form[4:0]
59127     attribute \src "libresoc.v:39796.5-39796.29"
59128     switch \initial
59129       attribute \src "libresoc.v:39796.9-39796.17"
59130       case 1'1
59131       case
59132     end
59133     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59134     switch \opcode_switch
59135       attribute \src "libresoc.v:0.0-0.0"
59136       case 2'00
59137         assign { } { }
59138         assign $1\dec58_form[4:0] 5'00101
59139       attribute \src "libresoc.v:0.0-0.0"
59140       case 2'01
59141         assign { } { }
59142         assign $1\dec58_form[4:0] 5'00101
59143       attribute \src "libresoc.v:0.0-0.0"
59144       case 2'10
59145         assign { } { }
59146         assign $1\dec58_form[4:0] 5'00101
59147       case
59148         assign $1\dec58_form[4:0] 5'00000
59149     end
59150     sync always
59151       update \dec58_form $0\dec58_form[4:0]
59152   end
59153   attribute \src "libresoc.v:39811.3-39826.6"
59154   process $proc$libresoc.v:39811$875
59155     assign { } { }
59156     assign { } { }
59157     assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0]
59158     attribute \src "libresoc.v:39812.5-39812.29"
59159     switch \initial
59160       attribute \src "libresoc.v:39812.9-39812.17"
59161       case 1'1
59162       case
59163     end
59164     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59165     switch \opcode_switch
59166       attribute \src "libresoc.v:0.0-0.0"
59167       case 2'00
59168         assign { } { }
59169         assign $1\dec58_in1_sel[2:0] 3'010
59170       attribute \src "libresoc.v:0.0-0.0"
59171       case 2'01
59172         assign { } { }
59173         assign $1\dec58_in1_sel[2:0] 3'010
59174       attribute \src "libresoc.v:0.0-0.0"
59175       case 2'10
59176         assign { } { }
59177         assign $1\dec58_in1_sel[2:0] 3'010
59178       case
59179         assign $1\dec58_in1_sel[2:0] 3'000
59180     end
59181     sync always
59182       update \dec58_in1_sel $0\dec58_in1_sel[2:0]
59183   end
59184   attribute \src "libresoc.v:39827.3-39842.6"
59185   process $proc$libresoc.v:39827$876
59186     assign { } { }
59187     assign { } { }
59188     assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0]
59189     attribute \src "libresoc.v:39828.5-39828.29"
59190     switch \initial
59191       attribute \src "libresoc.v:39828.9-39828.17"
59192       case 1'1
59193       case
59194     end
59195     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59196     switch \opcode_switch
59197       attribute \src "libresoc.v:0.0-0.0"
59198       case 2'00
59199         assign { } { }
59200         assign $1\dec58_in2_sel[3:0] 4'1000
59201       attribute \src "libresoc.v:0.0-0.0"
59202       case 2'01
59203         assign { } { }
59204         assign $1\dec58_in2_sel[3:0] 4'1000
59205       attribute \src "libresoc.v:0.0-0.0"
59206       case 2'10
59207         assign { } { }
59208         assign $1\dec58_in2_sel[3:0] 4'1000
59209       case
59210         assign $1\dec58_in2_sel[3:0] 4'0000
59211     end
59212     sync always
59213       update \dec58_in2_sel $0\dec58_in2_sel[3:0]
59214   end
59215   attribute \src "libresoc.v:39843.3-39858.6"
59216   process $proc$libresoc.v:39843$877
59217     assign { } { }
59218     assign { } { }
59219     assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0]
59220     attribute \src "libresoc.v:39844.5-39844.29"
59221     switch \initial
59222       attribute \src "libresoc.v:39844.9-39844.17"
59223       case 1'1
59224       case
59225     end
59226     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59227     switch \opcode_switch
59228       attribute \src "libresoc.v:0.0-0.0"
59229       case 2'00
59230         assign { } { }
59231         assign $1\dec58_in3_sel[1:0] 2'00
59232       attribute \src "libresoc.v:0.0-0.0"
59233       case 2'01
59234         assign { } { }
59235         assign $1\dec58_in3_sel[1:0] 2'00
59236       attribute \src "libresoc.v:0.0-0.0"
59237       case 2'10
59238         assign { } { }
59239         assign $1\dec58_in3_sel[1:0] 2'00
59240       case
59241         assign $1\dec58_in3_sel[1:0] 2'00
59242     end
59243     sync always
59244       update \dec58_in3_sel $0\dec58_in3_sel[1:0]
59245   end
59246   attribute \src "libresoc.v:39859.3-39874.6"
59247   process $proc$libresoc.v:39859$878
59248     assign { } { }
59249     assign { } { }
59250     assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0]
59251     attribute \src "libresoc.v:39860.5-39860.29"
59252     switch \initial
59253       attribute \src "libresoc.v:39860.9-39860.17"
59254       case 1'1
59255       case
59256     end
59257     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59258     switch \opcode_switch
59259       attribute \src "libresoc.v:0.0-0.0"
59260       case 2'00
59261         assign { } { }
59262         assign $1\dec58_out_sel[1:0] 2'01
59263       attribute \src "libresoc.v:0.0-0.0"
59264       case 2'01
59265         assign { } { }
59266         assign $1\dec58_out_sel[1:0] 2'01
59267       attribute \src "libresoc.v:0.0-0.0"
59268       case 2'10
59269         assign { } { }
59270         assign $1\dec58_out_sel[1:0] 2'01
59271       case
59272         assign $1\dec58_out_sel[1:0] 2'00
59273     end
59274     sync always
59275       update \dec58_out_sel $0\dec58_out_sel[1:0]
59276   end
59277   attribute \src "libresoc.v:39875.3-39890.6"
59278   process $proc$libresoc.v:39875$879
59279     assign { } { }
59280     assign { } { }
59281     assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0]
59282     attribute \src "libresoc.v:39876.5-39876.29"
59283     switch \initial
59284       attribute \src "libresoc.v:39876.9-39876.17"
59285       case 1'1
59286       case
59287     end
59288     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59289     switch \opcode_switch
59290       attribute \src "libresoc.v:0.0-0.0"
59291       case 2'00
59292         assign { } { }
59293         assign $1\dec58_cr_in[2:0] 3'000
59294       attribute \src "libresoc.v:0.0-0.0"
59295       case 2'01
59296         assign { } { }
59297         assign $1\dec58_cr_in[2:0] 3'000
59298       attribute \src "libresoc.v:0.0-0.0"
59299       case 2'10
59300         assign { } { }
59301         assign $1\dec58_cr_in[2:0] 3'000
59302       case
59303         assign $1\dec58_cr_in[2:0] 3'000
59304     end
59305     sync always
59306       update \dec58_cr_in $0\dec58_cr_in[2:0]
59307   end
59308   attribute \src "libresoc.v:39891.3-39906.6"
59309   process $proc$libresoc.v:39891$880
59310     assign { } { }
59311     assign { } { }
59312     assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0]
59313     attribute \src "libresoc.v:39892.5-39892.29"
59314     switch \initial
59315       attribute \src "libresoc.v:39892.9-39892.17"
59316       case 1'1
59317       case
59318     end
59319     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59320     switch \opcode_switch
59321       attribute \src "libresoc.v:0.0-0.0"
59322       case 2'00
59323         assign { } { }
59324         assign $1\dec58_cr_out[2:0] 3'000
59325       attribute \src "libresoc.v:0.0-0.0"
59326       case 2'01
59327         assign { } { }
59328         assign $1\dec58_cr_out[2:0] 3'000
59329       attribute \src "libresoc.v:0.0-0.0"
59330       case 2'10
59331         assign { } { }
59332         assign $1\dec58_cr_out[2:0] 3'000
59333       case
59334         assign $1\dec58_cr_out[2:0] 3'000
59335     end
59336     sync always
59337       update \dec58_cr_out $0\dec58_cr_out[2:0]
59338   end
59339   connect \opcode_switch \opcode_in [1:0]
59340 end
59341 attribute \src "libresoc.v:39912.1-40483.10"
59342 attribute \cells_not_processed 1
59343 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62"
59344 attribute \generator "nMigen"
59345 module \dec62
59346   attribute \src "libresoc.v:40235.3-40247.6"
59347   wire width 8 $0\dec62_asmcode[7:0]
59348   attribute \src "libresoc.v:40287.3-40299.6"
59349   wire $0\dec62_br[0:0]
59350   attribute \src "libresoc.v:40456.3-40468.6"
59351   wire width 3 $0\dec62_cr_in[2:0]
59352   attribute \src "libresoc.v:40469.3-40481.6"
59353   wire width 3 $0\dec62_cr_out[2:0]
59354   attribute \src "libresoc.v:40222.3-40234.6"
59355   wire width 2 $0\dec62_cry_in[1:0]
59356   attribute \src "libresoc.v:40274.3-40286.6"
59357   wire $0\dec62_cry_out[0:0]
59358   attribute \src "libresoc.v:40391.3-40403.6"
59359   wire width 5 $0\dec62_form[4:0]
59360   attribute \src "libresoc.v:40170.3-40182.6"
59361   wire width 12 $0\dec62_function_unit[11:0]
59362   attribute \src "libresoc.v:40404.3-40416.6"
59363   wire width 3 $0\dec62_in1_sel[2:0]
59364   attribute \src "libresoc.v:40417.3-40429.6"
59365   wire width 4 $0\dec62_in2_sel[3:0]
59366   attribute \src "libresoc.v:40430.3-40442.6"
59367   wire width 2 $0\dec62_in3_sel[1:0]
59368   attribute \src "libresoc.v:40313.3-40325.6"
59369   wire width 7 $0\dec62_internal_op[6:0]
59370   attribute \src "libresoc.v:40248.3-40260.6"
59371   wire $0\dec62_inv_a[0:0]
59372   attribute \src "libresoc.v:40261.3-40273.6"
59373   wire $0\dec62_inv_out[0:0]
59374   attribute \src "libresoc.v:40339.3-40351.6"
59375   wire $0\dec62_is_32b[0:0]
59376   attribute \src "libresoc.v:40183.3-40195.6"
59377   wire width 4 $0\dec62_ldst_len[3:0]
59378   attribute \src "libresoc.v:40365.3-40377.6"
59379   wire $0\dec62_lk[0:0]
59380   attribute \src "libresoc.v:40443.3-40455.6"
59381   wire width 2 $0\dec62_out_sel[1:0]
59382   attribute \src "libresoc.v:40209.3-40221.6"
59383   wire width 2 $0\dec62_rc_sel[1:0]
59384   attribute \src "libresoc.v:40326.3-40338.6"
59385   wire $0\dec62_rsrv[0:0]
59386   attribute \src "libresoc.v:40378.3-40390.6"
59387   wire $0\dec62_sgl_pipe[0:0]
59388   attribute \src "libresoc.v:40352.3-40364.6"
59389   wire $0\dec62_sgn[0:0]
59390   attribute \src "libresoc.v:40300.3-40312.6"
59391   wire $0\dec62_sgn_ext[0:0]
59392   attribute \src "libresoc.v:40196.3-40208.6"
59393   wire width 2 $0\dec62_upd[1:0]
59394   attribute \src "libresoc.v:39913.7-39913.20"
59395   wire $0\initial[0:0]
59396   attribute \src "libresoc.v:40235.3-40247.6"
59397   wire width 8 $1\dec62_asmcode[7:0]
59398   attribute \src "libresoc.v:40287.3-40299.6"
59399   wire $1\dec62_br[0:0]
59400   attribute \src "libresoc.v:40456.3-40468.6"
59401   wire width 3 $1\dec62_cr_in[2:0]
59402   attribute \src "libresoc.v:40469.3-40481.6"
59403   wire width 3 $1\dec62_cr_out[2:0]
59404   attribute \src "libresoc.v:40222.3-40234.6"
59405   wire width 2 $1\dec62_cry_in[1:0]
59406   attribute \src "libresoc.v:40274.3-40286.6"
59407   wire $1\dec62_cry_out[0:0]
59408   attribute \src "libresoc.v:40391.3-40403.6"
59409   wire width 5 $1\dec62_form[4:0]
59410   attribute \src "libresoc.v:40170.3-40182.6"
59411   wire width 12 $1\dec62_function_unit[11:0]
59412   attribute \src "libresoc.v:40404.3-40416.6"
59413   wire width 3 $1\dec62_in1_sel[2:0]
59414   attribute \src "libresoc.v:40417.3-40429.6"
59415   wire width 4 $1\dec62_in2_sel[3:0]
59416   attribute \src "libresoc.v:40430.3-40442.6"
59417   wire width 2 $1\dec62_in3_sel[1:0]
59418   attribute \src "libresoc.v:40313.3-40325.6"
59419   wire width 7 $1\dec62_internal_op[6:0]
59420   attribute \src "libresoc.v:40248.3-40260.6"
59421   wire $1\dec62_inv_a[0:0]
59422   attribute \src "libresoc.v:40261.3-40273.6"
59423   wire $1\dec62_inv_out[0:0]
59424   attribute \src "libresoc.v:40339.3-40351.6"
59425   wire $1\dec62_is_32b[0:0]
59426   attribute \src "libresoc.v:40183.3-40195.6"
59427   wire width 4 $1\dec62_ldst_len[3:0]
59428   attribute \src "libresoc.v:40365.3-40377.6"
59429   wire $1\dec62_lk[0:0]
59430   attribute \src "libresoc.v:40443.3-40455.6"
59431   wire width 2 $1\dec62_out_sel[1:0]
59432   attribute \src "libresoc.v:40209.3-40221.6"
59433   wire width 2 $1\dec62_rc_sel[1:0]
59434   attribute \src "libresoc.v:40326.3-40338.6"
59435   wire $1\dec62_rsrv[0:0]
59436   attribute \src "libresoc.v:40378.3-40390.6"
59437   wire $1\dec62_sgl_pipe[0:0]
59438   attribute \src "libresoc.v:40352.3-40364.6"
59439   wire $1\dec62_sgn[0:0]
59440   attribute \src "libresoc.v:40300.3-40312.6"
59441   wire $1\dec62_sgn_ext[0:0]
59442   attribute \src "libresoc.v:40196.3-40208.6"
59443   wire width 2 $1\dec62_upd[1:0]
59444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59445   wire width 8 output 4 \dec62_asmcode
59446   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59447   wire output 18 \dec62_br
59448   attribute \enum_base_type "CRInSel"
59449   attribute \enum_value_000 "NONE"
59450   attribute \enum_value_001 "CR0"
59451   attribute \enum_value_010 "BI"
59452   attribute \enum_value_011 "BFA"
59453   attribute \enum_value_100 "BA_BB"
59454   attribute \enum_value_101 "BC"
59455   attribute \enum_value_110 "WHOLE_REG"
59456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59457   wire width 3 output 9 \dec62_cr_in
59458   attribute \enum_base_type "CROutSel"
59459   attribute \enum_value_000 "NONE"
59460   attribute \enum_value_001 "CR0"
59461   attribute \enum_value_010 "BF"
59462   attribute \enum_value_011 "BT"
59463   attribute \enum_value_100 "WHOLE_REG"
59464   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59465   wire width 3 output 10 \dec62_cr_out
59466   attribute \enum_base_type "CryIn"
59467   attribute \enum_value_00 "ZERO"
59468   attribute \enum_value_01 "ONE"
59469   attribute \enum_value_10 "CA"
59470   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59471   wire width 2 output 14 \dec62_cry_in
59472   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59473   wire output 17 \dec62_cry_out
59474   attribute \enum_base_type "Form"
59475   attribute \enum_value_00000 "NONE"
59476   attribute \enum_value_00001 "I"
59477   attribute \enum_value_00010 "B"
59478   attribute \enum_value_00011 "SC"
59479   attribute \enum_value_00100 "D"
59480   attribute \enum_value_00101 "DS"
59481   attribute \enum_value_00110 "DQ"
59482   attribute \enum_value_00111 "DX"
59483   attribute \enum_value_01000 "X"
59484   attribute \enum_value_01001 "XL"
59485   attribute \enum_value_01010 "XFX"
59486   attribute \enum_value_01011 "XFL"
59487   attribute \enum_value_01100 "XX1"
59488   attribute \enum_value_01101 "XX2"
59489   attribute \enum_value_01110 "XX3"
59490   attribute \enum_value_01111 "XX4"
59491   attribute \enum_value_10000 "XS"
59492   attribute \enum_value_10001 "XO"
59493   attribute \enum_value_10010 "A"
59494   attribute \enum_value_10011 "M"
59495   attribute \enum_value_10100 "MD"
59496   attribute \enum_value_10101 "MDS"
59497   attribute \enum_value_10110 "VA"
59498   attribute \enum_value_10111 "VC"
59499   attribute \enum_value_11000 "VX"
59500   attribute \enum_value_11001 "EVX"
59501   attribute \enum_value_11010 "EVS"
59502   attribute \enum_value_11011 "Z22"
59503   attribute \enum_value_11100 "Z23"
59504   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59505   wire width 5 output 3 \dec62_form
59506   attribute \enum_base_type "Function"
59507   attribute \enum_value_000000000000 "NONE"
59508   attribute \enum_value_000000000010 "ALU"
59509   attribute \enum_value_000000000100 "LDST"
59510   attribute \enum_value_000000001000 "SHIFT_ROT"
59511   attribute \enum_value_000000010000 "LOGICAL"
59512   attribute \enum_value_000000100000 "BRANCH"
59513   attribute \enum_value_000001000000 "CR"
59514   attribute \enum_value_000010000000 "TRAP"
59515   attribute \enum_value_000100000000 "MUL"
59516   attribute \enum_value_001000000000 "DIV"
59517   attribute \enum_value_010000000000 "SPR"
59518   attribute \enum_value_100000000000 "MMU"
59519   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59520   wire width 12 output 1 \dec62_function_unit
59521   attribute \enum_base_type "In1Sel"
59522   attribute \enum_value_000 "NONE"
59523   attribute \enum_value_001 "RA"
59524   attribute \enum_value_010 "RA_OR_ZERO"
59525   attribute \enum_value_011 "SPR"
59526   attribute \enum_value_100 "RS"
59527   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59528   wire width 3 output 5 \dec62_in1_sel
59529   attribute \enum_base_type "In2Sel"
59530   attribute \enum_value_0000 "NONE"
59531   attribute \enum_value_0001 "RB"
59532   attribute \enum_value_0010 "CONST_UI"
59533   attribute \enum_value_0011 "CONST_SI"
59534   attribute \enum_value_0100 "CONST_UI_HI"
59535   attribute \enum_value_0101 "CONST_SI_HI"
59536   attribute \enum_value_0110 "CONST_LI"
59537   attribute \enum_value_0111 "CONST_BD"
59538   attribute \enum_value_1000 "CONST_DS"
59539   attribute \enum_value_1001 "CONST_M1"
59540   attribute \enum_value_1010 "CONST_SH"
59541   attribute \enum_value_1011 "CONST_SH32"
59542   attribute \enum_value_1100 "SPR"
59543   attribute \enum_value_1101 "RS"
59544   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59545   wire width 4 output 6 \dec62_in2_sel
59546   attribute \enum_base_type "In3Sel"
59547   attribute \enum_value_00 "NONE"
59548   attribute \enum_value_01 "RS"
59549   attribute \enum_value_10 "RB"
59550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59551   wire width 2 output 7 \dec62_in3_sel
59552   attribute \enum_base_type "MicrOp"
59553   attribute \enum_value_0000000 "OP_ILLEGAL"
59554   attribute \enum_value_0000001 "OP_NOP"
59555   attribute \enum_value_0000010 "OP_ADD"
59556   attribute \enum_value_0000011 "OP_ADDPCIS"
59557   attribute \enum_value_0000100 "OP_AND"
59558   attribute \enum_value_0000101 "OP_ATTN"
59559   attribute \enum_value_0000110 "OP_B"
59560   attribute \enum_value_0000111 "OP_BC"
59561   attribute \enum_value_0001000 "OP_BCREG"
59562   attribute \enum_value_0001001 "OP_BPERM"
59563   attribute \enum_value_0001010 "OP_CMP"
59564   attribute \enum_value_0001011 "OP_CMPB"
59565   attribute \enum_value_0001100 "OP_CMPEQB"
59566   attribute \enum_value_0001101 "OP_CMPRB"
59567   attribute \enum_value_0001110 "OP_CNTZ"
59568   attribute \enum_value_0001111 "OP_CRAND"
59569   attribute \enum_value_0010000 "OP_CRANDC"
59570   attribute \enum_value_0010001 "OP_CREQV"
59571   attribute \enum_value_0010010 "OP_CRNAND"
59572   attribute \enum_value_0010011 "OP_CRNOR"
59573   attribute \enum_value_0010100 "OP_CROR"
59574   attribute \enum_value_0010101 "OP_CRORC"
59575   attribute \enum_value_0010110 "OP_CRXOR"
59576   attribute \enum_value_0010111 "OP_DARN"
59577   attribute \enum_value_0011000 "OP_DCBF"
59578   attribute \enum_value_0011001 "OP_DCBST"
59579   attribute \enum_value_0011010 "OP_DCBT"
59580   attribute \enum_value_0011011 "OP_DCBTST"
59581   attribute \enum_value_0011100 "OP_DCBZ"
59582   attribute \enum_value_0011101 "OP_DIV"
59583   attribute \enum_value_0011110 "OP_DIVE"
59584   attribute \enum_value_0011111 "OP_EXTS"
59585   attribute \enum_value_0100000 "OP_EXTSWSLI"
59586   attribute \enum_value_0100001 "OP_ICBI"
59587   attribute \enum_value_0100010 "OP_ICBT"
59588   attribute \enum_value_0100011 "OP_ISEL"
59589   attribute \enum_value_0100100 "OP_ISYNC"
59590   attribute \enum_value_0100101 "OP_LOAD"
59591   attribute \enum_value_0100110 "OP_STORE"
59592   attribute \enum_value_0100111 "OP_MADDHD"
59593   attribute \enum_value_0101000 "OP_MADDHDU"
59594   attribute \enum_value_0101001 "OP_MADDLD"
59595   attribute \enum_value_0101010 "OP_MCRF"
59596   attribute \enum_value_0101011 "OP_MCRXR"
59597   attribute \enum_value_0101100 "OP_MCRXRX"
59598   attribute \enum_value_0101101 "OP_MFCR"
59599   attribute \enum_value_0101110 "OP_MFSPR"
59600   attribute \enum_value_0101111 "OP_MOD"
59601   attribute \enum_value_0110000 "OP_MTCRF"
59602   attribute \enum_value_0110001 "OP_MTSPR"
59603   attribute \enum_value_0110010 "OP_MUL_L64"
59604   attribute \enum_value_0110011 "OP_MUL_H64"
59605   attribute \enum_value_0110100 "OP_MUL_H32"
59606   attribute \enum_value_0110101 "OP_OR"
59607   attribute \enum_value_0110110 "OP_POPCNT"
59608   attribute \enum_value_0110111 "OP_PRTY"
59609   attribute \enum_value_0111000 "OP_RLC"
59610   attribute \enum_value_0111001 "OP_RLCL"
59611   attribute \enum_value_0111010 "OP_RLCR"
59612   attribute \enum_value_0111011 "OP_SETB"
59613   attribute \enum_value_0111100 "OP_SHL"
59614   attribute \enum_value_0111101 "OP_SHR"
59615   attribute \enum_value_0111110 "OP_SYNC"
59616   attribute \enum_value_0111111 "OP_TRAP"
59617   attribute \enum_value_1000011 "OP_XOR"
59618   attribute \enum_value_1000100 "OP_SIM_CONFIG"
59619   attribute \enum_value_1000101 "OP_CROP"
59620   attribute \enum_value_1000110 "OP_RFID"
59621   attribute \enum_value_1000111 "OP_MFMSR"
59622   attribute \enum_value_1001000 "OP_MTMSRD"
59623   attribute \enum_value_1001001 "OP_SC"
59624   attribute \enum_value_1001010 "OP_MTMSR"
59625   attribute \enum_value_1001011 "OP_TLBIE"
59626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59627   wire width 7 output 2 \dec62_internal_op
59628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59629   wire output 15 \dec62_inv_a
59630   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59631   wire output 16 \dec62_inv_out
59632   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59633   wire output 21 \dec62_is_32b
59634   attribute \enum_base_type "LdstLen"
59635   attribute \enum_value_0000 "NONE"
59636   attribute \enum_value_0001 "is1B"
59637   attribute \enum_value_0010 "is2B"
59638   attribute \enum_value_0100 "is4B"
59639   attribute \enum_value_1000 "is8B"
59640   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59641   wire width 4 output 11 \dec62_ldst_len
59642   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59643   wire output 23 \dec62_lk
59644   attribute \enum_base_type "OutSel"
59645   attribute \enum_value_00 "NONE"
59646   attribute \enum_value_01 "RT"
59647   attribute \enum_value_10 "RA"
59648   attribute \enum_value_11 "SPR"
59649   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59650   wire width 2 output 8 \dec62_out_sel
59651   attribute \enum_base_type "RC"
59652   attribute \enum_value_00 "NONE"
59653   attribute \enum_value_01 "ONE"
59654   attribute \enum_value_10 "RC"
59655   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59656   wire width 2 output 13 \dec62_rc_sel
59657   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59658   wire output 20 \dec62_rsrv
59659   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59660   wire output 24 \dec62_sgl_pipe
59661   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59662   wire output 22 \dec62_sgn
59663   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179"
59664   wire output 19 \dec62_sgn_ext
59665   attribute \enum_base_type "LDSTMode"
59666   attribute \enum_value_00 "NONE"
59667   attribute \enum_value_01 "update"
59668   attribute \enum_value_10 "cix"
59669   attribute \enum_value_11 "cx"
59670   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
59671   wire width 2 output 12 \dec62_upd
59672   attribute \src "libresoc.v:39913.7-39913.15"
59673   wire \initial
59674   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285"
59675   wire width 32 input 25 \opcode_in
59676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
59677   wire width 2 \opcode_switch
59678   attribute \src "libresoc.v:39913.7-39913.20"
59679   process $proc$libresoc.v:39913$906
59680     assign { } { }
59681     assign $0\initial[0:0] 1'0
59682     sync always
59683       update \initial $0\initial[0:0]
59684     sync init
59685   end
59686   attribute \src "libresoc.v:40170.3-40182.6"
59687   process $proc$libresoc.v:40170$882
59688     assign { } { }
59689     assign { } { }
59690     assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0]
59691     attribute \src "libresoc.v:40171.5-40171.29"
59692     switch \initial
59693       attribute \src "libresoc.v:40171.9-40171.17"
59694       case 1'1
59695       case
59696     end
59697     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59698     switch \opcode_switch
59699       attribute \src "libresoc.v:0.0-0.0"
59700       case 2'00
59701         assign { } { }
59702         assign $1\dec62_function_unit[11:0] 12'000000000100
59703       attribute \src "libresoc.v:0.0-0.0"
59704       case 2'01
59705         assign { } { }
59706         assign $1\dec62_function_unit[11:0] 12'000000000100
59707       case
59708         assign $1\dec62_function_unit[11:0] 12'000000000000
59709     end
59710     sync always
59711       update \dec62_function_unit $0\dec62_function_unit[11:0]
59712   end
59713   attribute \src "libresoc.v:40183.3-40195.6"
59714   process $proc$libresoc.v:40183$883
59715     assign { } { }
59716     assign { } { }
59717     assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0]
59718     attribute \src "libresoc.v:40184.5-40184.29"
59719     switch \initial
59720       attribute \src "libresoc.v:40184.9-40184.17"
59721       case 1'1
59722       case
59723     end
59724     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59725     switch \opcode_switch
59726       attribute \src "libresoc.v:0.0-0.0"
59727       case 2'00
59728         assign { } { }
59729         assign $1\dec62_ldst_len[3:0] 4'1000
59730       attribute \src "libresoc.v:0.0-0.0"
59731       case 2'01
59732         assign { } { }
59733         assign $1\dec62_ldst_len[3:0] 4'1000
59734       case
59735         assign $1\dec62_ldst_len[3:0] 4'0000
59736     end
59737     sync always
59738       update \dec62_ldst_len $0\dec62_ldst_len[3:0]
59739   end
59740   attribute \src "libresoc.v:40196.3-40208.6"
59741   process $proc$libresoc.v:40196$884
59742     assign { } { }
59743     assign { } { }
59744     assign $0\dec62_upd[1:0] $1\dec62_upd[1:0]
59745     attribute \src "libresoc.v:40197.5-40197.29"
59746     switch \initial
59747       attribute \src "libresoc.v:40197.9-40197.17"
59748       case 1'1
59749       case
59750     end
59751     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59752     switch \opcode_switch
59753       attribute \src "libresoc.v:0.0-0.0"
59754       case 2'00
59755         assign { } { }
59756         assign $1\dec62_upd[1:0] 2'00
59757       attribute \src "libresoc.v:0.0-0.0"
59758       case 2'01
59759         assign { } { }
59760         assign $1\dec62_upd[1:0] 2'01
59761       case
59762         assign $1\dec62_upd[1:0] 2'00
59763     end
59764     sync always
59765       update \dec62_upd $0\dec62_upd[1:0]
59766   end
59767   attribute \src "libresoc.v:40209.3-40221.6"
59768   process $proc$libresoc.v:40209$885
59769     assign { } { }
59770     assign { } { }
59771     assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0]
59772     attribute \src "libresoc.v:40210.5-40210.29"
59773     switch \initial
59774       attribute \src "libresoc.v:40210.9-40210.17"
59775       case 1'1
59776       case
59777     end
59778     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59779     switch \opcode_switch
59780       attribute \src "libresoc.v:0.0-0.0"
59781       case 2'00
59782         assign { } { }
59783         assign $1\dec62_rc_sel[1:0] 2'00
59784       attribute \src "libresoc.v:0.0-0.0"
59785       case 2'01
59786         assign { } { }
59787         assign $1\dec62_rc_sel[1:0] 2'00
59788       case
59789         assign $1\dec62_rc_sel[1:0] 2'00
59790     end
59791     sync always
59792       update \dec62_rc_sel $0\dec62_rc_sel[1:0]
59793   end
59794   attribute \src "libresoc.v:40222.3-40234.6"
59795   process $proc$libresoc.v:40222$886
59796     assign { } { }
59797     assign { } { }
59798     assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0]
59799     attribute \src "libresoc.v:40223.5-40223.29"
59800     switch \initial
59801       attribute \src "libresoc.v:40223.9-40223.17"
59802       case 1'1
59803       case
59804     end
59805     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59806     switch \opcode_switch
59807       attribute \src "libresoc.v:0.0-0.0"
59808       case 2'00
59809         assign { } { }
59810         assign $1\dec62_cry_in[1:0] 2'00
59811       attribute \src "libresoc.v:0.0-0.0"
59812       case 2'01
59813         assign { } { }
59814         assign $1\dec62_cry_in[1:0] 2'00
59815       case
59816         assign $1\dec62_cry_in[1:0] 2'00
59817     end
59818     sync always
59819       update \dec62_cry_in $0\dec62_cry_in[1:0]
59820   end
59821   attribute \src "libresoc.v:40235.3-40247.6"
59822   process $proc$libresoc.v:40235$887
59823     assign { } { }
59824     assign { } { }
59825     assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0]
59826     attribute \src "libresoc.v:40236.5-40236.29"
59827     switch \initial
59828       attribute \src "libresoc.v:40236.9-40236.17"
59829       case 1'1
59830       case
59831     end
59832     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59833     switch \opcode_switch
59834       attribute \src "libresoc.v:0.0-0.0"
59835       case 2'00
59836         assign { } { }
59837         assign $1\dec62_asmcode[7:0] 8'10101100
59838       attribute \src "libresoc.v:0.0-0.0"
59839       case 2'01
59840         assign { } { }
59841         assign $1\dec62_asmcode[7:0] 8'10101111
59842       case
59843         assign $1\dec62_asmcode[7:0] 8'00000000
59844     end
59845     sync always
59846       update \dec62_asmcode $0\dec62_asmcode[7:0]
59847   end
59848   attribute \src "libresoc.v:40248.3-40260.6"
59849   process $proc$libresoc.v:40248$888
59850     assign { } { }
59851     assign { } { }
59852     assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0]
59853     attribute \src "libresoc.v:40249.5-40249.29"
59854     switch \initial
59855       attribute \src "libresoc.v:40249.9-40249.17"
59856       case 1'1
59857       case
59858     end
59859     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59860     switch \opcode_switch
59861       attribute \src "libresoc.v:0.0-0.0"
59862       case 2'00
59863         assign { } { }
59864         assign $1\dec62_inv_a[0:0] 1'0
59865       attribute \src "libresoc.v:0.0-0.0"
59866       case 2'01
59867         assign { } { }
59868         assign $1\dec62_inv_a[0:0] 1'0
59869       case
59870         assign $1\dec62_inv_a[0:0] 1'0
59871     end
59872     sync always
59873       update \dec62_inv_a $0\dec62_inv_a[0:0]
59874   end
59875   attribute \src "libresoc.v:40261.3-40273.6"
59876   process $proc$libresoc.v:40261$889
59877     assign { } { }
59878     assign { } { }
59879     assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0]
59880     attribute \src "libresoc.v:40262.5-40262.29"
59881     switch \initial
59882       attribute \src "libresoc.v:40262.9-40262.17"
59883       case 1'1
59884       case
59885     end
59886     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59887     switch \opcode_switch
59888       attribute \src "libresoc.v:0.0-0.0"
59889       case 2'00
59890         assign { } { }
59891         assign $1\dec62_inv_out[0:0] 1'0
59892       attribute \src "libresoc.v:0.0-0.0"
59893       case 2'01
59894         assign { } { }
59895         assign $1\dec62_inv_out[0:0] 1'0
59896       case
59897         assign $1\dec62_inv_out[0:0] 1'0
59898     end
59899     sync always
59900       update \dec62_inv_out $0\dec62_inv_out[0:0]
59901   end
59902   attribute \src "libresoc.v:40274.3-40286.6"
59903   process $proc$libresoc.v:40274$890
59904     assign { } { }
59905     assign { } { }
59906     assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0]
59907     attribute \src "libresoc.v:40275.5-40275.29"
59908     switch \initial
59909       attribute \src "libresoc.v:40275.9-40275.17"
59910       case 1'1
59911       case
59912     end
59913     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59914     switch \opcode_switch
59915       attribute \src "libresoc.v:0.0-0.0"
59916       case 2'00
59917         assign { } { }
59918         assign $1\dec62_cry_out[0:0] 1'0
59919       attribute \src "libresoc.v:0.0-0.0"
59920       case 2'01
59921         assign { } { }
59922         assign $1\dec62_cry_out[0:0] 1'0
59923       case
59924         assign $1\dec62_cry_out[0:0] 1'0
59925     end
59926     sync always
59927       update \dec62_cry_out $0\dec62_cry_out[0:0]
59928   end
59929   attribute \src "libresoc.v:40287.3-40299.6"
59930   process $proc$libresoc.v:40287$891
59931     assign { } { }
59932     assign { } { }
59933     assign $0\dec62_br[0:0] $1\dec62_br[0:0]
59934     attribute \src "libresoc.v:40288.5-40288.29"
59935     switch \initial
59936       attribute \src "libresoc.v:40288.9-40288.17"
59937       case 1'1
59938       case
59939     end
59940     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59941     switch \opcode_switch
59942       attribute \src "libresoc.v:0.0-0.0"
59943       case 2'00
59944         assign { } { }
59945         assign $1\dec62_br[0:0] 1'0
59946       attribute \src "libresoc.v:0.0-0.0"
59947       case 2'01
59948         assign { } { }
59949         assign $1\dec62_br[0:0] 1'0
59950       case
59951         assign $1\dec62_br[0:0] 1'0
59952     end
59953     sync always
59954       update \dec62_br $0\dec62_br[0:0]
59955   end
59956   attribute \src "libresoc.v:40300.3-40312.6"
59957   process $proc$libresoc.v:40300$892
59958     assign { } { }
59959     assign { } { }
59960     assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0]
59961     attribute \src "libresoc.v:40301.5-40301.29"
59962     switch \initial
59963       attribute \src "libresoc.v:40301.9-40301.17"
59964       case 1'1
59965       case
59966     end
59967     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59968     switch \opcode_switch
59969       attribute \src "libresoc.v:0.0-0.0"
59970       case 2'00
59971         assign { } { }
59972         assign $1\dec62_sgn_ext[0:0] 1'0
59973       attribute \src "libresoc.v:0.0-0.0"
59974       case 2'01
59975         assign { } { }
59976         assign $1\dec62_sgn_ext[0:0] 1'0
59977       case
59978         assign $1\dec62_sgn_ext[0:0] 1'0
59979     end
59980     sync always
59981       update \dec62_sgn_ext $0\dec62_sgn_ext[0:0]
59982   end
59983   attribute \src "libresoc.v:40313.3-40325.6"
59984   process $proc$libresoc.v:40313$893
59985     assign { } { }
59986     assign { } { }
59987     assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0]
59988     attribute \src "libresoc.v:40314.5-40314.29"
59989     switch \initial
59990       attribute \src "libresoc.v:40314.9-40314.17"
59991       case 1'1
59992       case
59993     end
59994     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
59995     switch \opcode_switch
59996       attribute \src "libresoc.v:0.0-0.0"
59997       case 2'00
59998         assign { } { }
59999         assign $1\dec62_internal_op[6:0] 7'0100110
60000       attribute \src "libresoc.v:0.0-0.0"
60001       case 2'01
60002         assign { } { }
60003         assign $1\dec62_internal_op[6:0] 7'0100110
60004       case
60005         assign $1\dec62_internal_op[6:0] 7'0000000
60006     end
60007     sync always
60008       update \dec62_internal_op $0\dec62_internal_op[6:0]
60009   end
60010   attribute \src "libresoc.v:40326.3-40338.6"
60011   process $proc$libresoc.v:40326$894
60012     assign { } { }
60013     assign { } { }
60014     assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0]
60015     attribute \src "libresoc.v:40327.5-40327.29"
60016     switch \initial
60017       attribute \src "libresoc.v:40327.9-40327.17"
60018       case 1'1
60019       case
60020     end
60021     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60022     switch \opcode_switch
60023       attribute \src "libresoc.v:0.0-0.0"
60024       case 2'00
60025         assign { } { }
60026         assign $1\dec62_rsrv[0:0] 1'0
60027       attribute \src "libresoc.v:0.0-0.0"
60028       case 2'01
60029         assign { } { }
60030         assign $1\dec62_rsrv[0:0] 1'0
60031       case
60032         assign $1\dec62_rsrv[0:0] 1'0
60033     end
60034     sync always
60035       update \dec62_rsrv $0\dec62_rsrv[0:0]
60036   end
60037   attribute \src "libresoc.v:40339.3-40351.6"
60038   process $proc$libresoc.v:40339$895
60039     assign { } { }
60040     assign { } { }
60041     assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0]
60042     attribute \src "libresoc.v:40340.5-40340.29"
60043     switch \initial
60044       attribute \src "libresoc.v:40340.9-40340.17"
60045       case 1'1
60046       case
60047     end
60048     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60049     switch \opcode_switch
60050       attribute \src "libresoc.v:0.0-0.0"
60051       case 2'00
60052         assign { } { }
60053         assign $1\dec62_is_32b[0:0] 1'0
60054       attribute \src "libresoc.v:0.0-0.0"
60055       case 2'01
60056         assign { } { }
60057         assign $1\dec62_is_32b[0:0] 1'0
60058       case
60059         assign $1\dec62_is_32b[0:0] 1'0
60060     end
60061     sync always
60062       update \dec62_is_32b $0\dec62_is_32b[0:0]
60063   end
60064   attribute \src "libresoc.v:40352.3-40364.6"
60065   process $proc$libresoc.v:40352$896
60066     assign { } { }
60067     assign { } { }
60068     assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0]
60069     attribute \src "libresoc.v:40353.5-40353.29"
60070     switch \initial
60071       attribute \src "libresoc.v:40353.9-40353.17"
60072       case 1'1
60073       case
60074     end
60075     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60076     switch \opcode_switch
60077       attribute \src "libresoc.v:0.0-0.0"
60078       case 2'00
60079         assign { } { }
60080         assign $1\dec62_sgn[0:0] 1'0
60081       attribute \src "libresoc.v:0.0-0.0"
60082       case 2'01
60083         assign { } { }
60084         assign $1\dec62_sgn[0:0] 1'0
60085       case
60086         assign $1\dec62_sgn[0:0] 1'0
60087     end
60088     sync always
60089       update \dec62_sgn $0\dec62_sgn[0:0]
60090   end
60091   attribute \src "libresoc.v:40365.3-40377.6"
60092   process $proc$libresoc.v:40365$897
60093     assign { } { }
60094     assign { } { }
60095     assign $0\dec62_lk[0:0] $1\dec62_lk[0:0]
60096     attribute \src "libresoc.v:40366.5-40366.29"
60097     switch \initial
60098       attribute \src "libresoc.v:40366.9-40366.17"
60099       case 1'1
60100       case
60101     end
60102     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60103     switch \opcode_switch
60104       attribute \src "libresoc.v:0.0-0.0"
60105       case 2'00
60106         assign { } { }
60107         assign $1\dec62_lk[0:0] 1'0
60108       attribute \src "libresoc.v:0.0-0.0"
60109       case 2'01
60110         assign { } { }
60111         assign $1\dec62_lk[0:0] 1'0
60112       case
60113         assign $1\dec62_lk[0:0] 1'0
60114     end
60115     sync always
60116       update \dec62_lk $0\dec62_lk[0:0]
60117   end
60118   attribute \src "libresoc.v:40378.3-40390.6"
60119   process $proc$libresoc.v:40378$898
60120     assign { } { }
60121     assign { } { }
60122     assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0]
60123     attribute \src "libresoc.v:40379.5-40379.29"
60124     switch \initial
60125       attribute \src "libresoc.v:40379.9-40379.17"
60126       case 1'1
60127       case
60128     end
60129     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60130     switch \opcode_switch
60131       attribute \src "libresoc.v:0.0-0.0"
60132       case 2'00
60133         assign { } { }
60134         assign $1\dec62_sgl_pipe[0:0] 1'1
60135       attribute \src "libresoc.v:0.0-0.0"
60136       case 2'01
60137         assign { } { }
60138         assign $1\dec62_sgl_pipe[0:0] 1'1
60139       case
60140         assign $1\dec62_sgl_pipe[0:0] 1'0
60141     end
60142     sync always
60143       update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0]
60144   end
60145   attribute \src "libresoc.v:40391.3-40403.6"
60146   process $proc$libresoc.v:40391$899
60147     assign { } { }
60148     assign { } { }
60149     assign $0\dec62_form[4:0] $1\dec62_form[4:0]
60150     attribute \src "libresoc.v:40392.5-40392.29"
60151     switch \initial
60152       attribute \src "libresoc.v:40392.9-40392.17"
60153       case 1'1
60154       case
60155     end
60156     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60157     switch \opcode_switch
60158       attribute \src "libresoc.v:0.0-0.0"
60159       case 2'00
60160         assign { } { }
60161         assign $1\dec62_form[4:0] 5'00101
60162       attribute \src "libresoc.v:0.0-0.0"
60163       case 2'01
60164         assign { } { }
60165         assign $1\dec62_form[4:0] 5'00101
60166       case
60167         assign $1\dec62_form[4:0] 5'00000
60168     end
60169     sync always
60170       update \dec62_form $0\dec62_form[4:0]
60171   end
60172   attribute \src "libresoc.v:40404.3-40416.6"
60173   process $proc$libresoc.v:40404$900
60174     assign { } { }
60175     assign { } { }
60176     assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0]
60177     attribute \src "libresoc.v:40405.5-40405.29"
60178     switch \initial
60179       attribute \src "libresoc.v:40405.9-40405.17"
60180       case 1'1
60181       case
60182     end
60183     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60184     switch \opcode_switch
60185       attribute \src "libresoc.v:0.0-0.0"
60186       case 2'00
60187         assign { } { }
60188         assign $1\dec62_in1_sel[2:0] 3'010
60189       attribute \src "libresoc.v:0.0-0.0"
60190       case 2'01
60191         assign { } { }
60192         assign $1\dec62_in1_sel[2:0] 3'010
60193       case
60194         assign $1\dec62_in1_sel[2:0] 3'000
60195     end
60196     sync always
60197       update \dec62_in1_sel $0\dec62_in1_sel[2:0]
60198   end
60199   attribute \src "libresoc.v:40417.3-40429.6"
60200   process $proc$libresoc.v:40417$901
60201     assign { } { }
60202     assign { } { }
60203     assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0]
60204     attribute \src "libresoc.v:40418.5-40418.29"
60205     switch \initial
60206       attribute \src "libresoc.v:40418.9-40418.17"
60207       case 1'1
60208       case
60209     end
60210     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60211     switch \opcode_switch
60212       attribute \src "libresoc.v:0.0-0.0"
60213       case 2'00
60214         assign { } { }
60215         assign $1\dec62_in2_sel[3:0] 4'1000
60216       attribute \src "libresoc.v:0.0-0.0"
60217       case 2'01
60218         assign { } { }
60219         assign $1\dec62_in2_sel[3:0] 4'1000
60220       case
60221         assign $1\dec62_in2_sel[3:0] 4'0000
60222     end
60223     sync always
60224       update \dec62_in2_sel $0\dec62_in2_sel[3:0]
60225   end
60226   attribute \src "libresoc.v:40430.3-40442.6"
60227   process $proc$libresoc.v:40430$902
60228     assign { } { }
60229     assign { } { }
60230     assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0]
60231     attribute \src "libresoc.v:40431.5-40431.29"
60232     switch \initial
60233       attribute \src "libresoc.v:40431.9-40431.17"
60234       case 1'1
60235       case
60236     end
60237     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60238     switch \opcode_switch
60239       attribute \src "libresoc.v:0.0-0.0"
60240       case 2'00
60241         assign { } { }
60242         assign $1\dec62_in3_sel[1:0] 2'01
60243       attribute \src "libresoc.v:0.0-0.0"
60244       case 2'01
60245         assign { } { }
60246         assign $1\dec62_in3_sel[1:0] 2'01
60247       case
60248         assign $1\dec62_in3_sel[1:0] 2'00
60249     end
60250     sync always
60251       update \dec62_in3_sel $0\dec62_in3_sel[1:0]
60252   end
60253   attribute \src "libresoc.v:40443.3-40455.6"
60254   process $proc$libresoc.v:40443$903
60255     assign { } { }
60256     assign { } { }
60257     assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0]
60258     attribute \src "libresoc.v:40444.5-40444.29"
60259     switch \initial
60260       attribute \src "libresoc.v:40444.9-40444.17"
60261       case 1'1
60262       case
60263     end
60264     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60265     switch \opcode_switch
60266       attribute \src "libresoc.v:0.0-0.0"
60267       case 2'00
60268         assign { } { }
60269         assign $1\dec62_out_sel[1:0] 2'00
60270       attribute \src "libresoc.v:0.0-0.0"
60271       case 2'01
60272         assign { } { }
60273         assign $1\dec62_out_sel[1:0] 2'00
60274       case
60275         assign $1\dec62_out_sel[1:0] 2'00
60276     end
60277     sync always
60278       update \dec62_out_sel $0\dec62_out_sel[1:0]
60279   end
60280   attribute \src "libresoc.v:40456.3-40468.6"
60281   process $proc$libresoc.v:40456$904
60282     assign { } { }
60283     assign { } { }
60284     assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0]
60285     attribute \src "libresoc.v:40457.5-40457.29"
60286     switch \initial
60287       attribute \src "libresoc.v:40457.9-40457.17"
60288       case 1'1
60289       case
60290     end
60291     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60292     switch \opcode_switch
60293       attribute \src "libresoc.v:0.0-0.0"
60294       case 2'00
60295         assign { } { }
60296         assign $1\dec62_cr_in[2:0] 3'000
60297       attribute \src "libresoc.v:0.0-0.0"
60298       case 2'01
60299         assign { } { }
60300         assign $1\dec62_cr_in[2:0] 3'000
60301       case
60302         assign $1\dec62_cr_in[2:0] 3'000
60303     end
60304     sync always
60305       update \dec62_cr_in $0\dec62_cr_in[2:0]
60306   end
60307   attribute \src "libresoc.v:40469.3-40481.6"
60308   process $proc$libresoc.v:40469$905
60309     assign { } { }
60310     assign { } { }
60311     assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0]
60312     attribute \src "libresoc.v:40470.5-40470.29"
60313     switch \initial
60314       attribute \src "libresoc.v:40470.9-40470.17"
60315       case 1'1
60316       case
60317     end
60318     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423"
60319     switch \opcode_switch
60320       attribute \src "libresoc.v:0.0-0.0"
60321       case 2'00
60322         assign { } { }
60323         assign $1\dec62_cr_out[2:0] 3'000
60324       attribute \src "libresoc.v:0.0-0.0"
60325       case 2'01
60326         assign { } { }
60327         assign $1\dec62_cr_out[2:0] 3'000
60328       case
60329         assign $1\dec62_cr_out[2:0] 3'000
60330     end
60331     sync always
60332       update \dec62_cr_out $0\dec62_cr_out[2:0]
60333   end
60334   connect \opcode_switch \opcode_in [1:0]
60335 end
60336 attribute \src "libresoc.v:40487.1-40992.10"
60337 attribute \cells_not_processed 1
60338 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a"
60339 attribute \generator "nMigen"
60340 module \dec_a
60341   attribute \src "libresoc.v:40921.3-40956.6"
60342   wire width 3 $0\fast_a[2:0]
60343   attribute \src "libresoc.v:40921.3-40956.6"
60344   wire $0\fast_a_ok[0:0]
60345   attribute \src "libresoc.v:40488.7-40488.20"
60346   wire $0\initial[0:0]
60347   attribute \src "libresoc.v:40889.3-40904.6"
60348   wire width 5 $0\reg_a[4:0]
60349   attribute \src "libresoc.v:40905.3-40920.6"
60350   wire $0\reg_a_ok[0:0]
60351   attribute \src "libresoc.v:40957.3-40967.6"
60352   wire width 10 $0\spr[9:0]
60353   attribute \src "libresoc.v:40979.3-40990.6"
60354   wire width 10 $0\spr_a[9:0]
60355   attribute \src "libresoc.v:40979.3-40990.6"
60356   wire $0\spr_a_ok[0:0]
60357   attribute \src "libresoc.v:40968.3-40978.6"
60358   wire width 10 $0\sprmap_spr_i[9:0]
60359   attribute \src "libresoc.v:40921.3-40956.6"
60360   wire width 3 $1\fast_a[2:0]
60361   attribute \src "libresoc.v:40921.3-40956.6"
60362   wire $1\fast_a_ok[0:0]
60363   attribute \src "libresoc.v:40889.3-40904.6"
60364   wire width 5 $1\reg_a[4:0]
60365   attribute \src "libresoc.v:40905.3-40920.6"
60366   wire $1\reg_a_ok[0:0]
60367   attribute \src "libresoc.v:40957.3-40967.6"
60368   wire width 10 $1\spr[9:0]
60369   attribute \src "libresoc.v:40979.3-40990.6"
60370   wire width 10 $1\spr_a[9:0]
60371   attribute \src "libresoc.v:40979.3-40990.6"
60372   wire $1\spr_a_ok[0:0]
60373   attribute \src "libresoc.v:40968.3-40978.6"
60374   wire width 10 $1\sprmap_spr_i[9:0]
60375   attribute \src "libresoc.v:40921.3-40956.6"
60376   wire width 3 $2\fast_a[2:0]
60377   attribute \src "libresoc.v:40921.3-40956.6"
60378   wire $2\fast_a_ok[0:0]
60379   attribute \src "libresoc.v:40889.3-40904.6"
60380   wire width 5 $2\reg_a[4:0]
60381   attribute \src "libresoc.v:40905.3-40920.6"
60382   wire $2\reg_a_ok[0:0]
60383   attribute \src "libresoc.v:40921.3-40956.6"
60384   wire width 3 $3\fast_a[2:0]
60385   attribute \src "libresoc.v:40921.3-40956.6"
60386   wire $3\fast_a_ok[0:0]
60387   attribute \src "libresoc.v:40873.18-40873.110"
60388   wire $and$libresoc.v:40873$913_Y
60389   attribute \src "libresoc.v:40878.18-40878.113"
60390   wire $and$libresoc.v:40878$918_Y
60391   attribute \src "libresoc.v:40881.17-40881.107"
60392   wire $and$libresoc.v:40881$921_Y
60393   attribute \src "libresoc.v:40868.18-40868.112"
60394   wire $eq$libresoc.v:40868$908_Y
60395   attribute \src "libresoc.v:40869.18-40869.112"
60396   wire $eq$libresoc.v:40869$909_Y
60397   attribute \src "libresoc.v:40870.18-40870.112"
60398   wire $eq$libresoc.v:40870$910_Y
60399   attribute \src "libresoc.v:40872.17-40872.111"
60400   wire $eq$libresoc.v:40872$912_Y
60401   attribute \src "libresoc.v:40875.18-40875.112"
60402   wire $eq$libresoc.v:40875$915_Y
60403   attribute \src "libresoc.v:40879.17-40879.111"
60404   wire $eq$libresoc.v:40879$919_Y
60405   attribute \src "libresoc.v:40871.18-40871.109"
60406   wire $ne$libresoc.v:40871$911_Y
60407   attribute \src "libresoc.v:40880.17-40880.108"
60408   wire $ne$libresoc.v:40880$920_Y
60409   attribute \src "libresoc.v:40876.18-40876.105"
60410   wire $not$libresoc.v:40876$916_Y
60411   attribute \src "libresoc.v:40877.18-40877.108"
60412   wire $not$libresoc.v:40877$917_Y
60413   attribute \src "libresoc.v:40867.17-40867.107"
60414   wire $or$libresoc.v:40867$907_Y
60415   attribute \src "libresoc.v:40874.18-40874.110"
60416   wire $or$libresoc.v:40874$914_Y
60417   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
60418   wire \$1
60419   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
60420   wire \$11
60421   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
60422   wire \$13
60423   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
60424   wire \$15
60425   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60426   wire \$17
60427   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60428   wire \$19
60429   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60430   wire \$21
60431   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
60432   wire \$23
60433   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119"
60434   wire \$25
60435   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
60436   wire \$27
60437   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
60438   wire \$29
60439   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
60440   wire \$3
60441   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60442   wire \$5
60443   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60444   wire \$7
60445   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60446   wire \$9
60447   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
60448   wire width 5 input 10 \BO
60449   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
60450   wire width 5 input 9 \RA
60451   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
60452   wire width 5 input 8 \RS
60453   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
60454   wire width 10 input 11 \SPR
60455   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
60456   wire width 10 input 12 \XL_XO
60457   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60458   wire width 3 output 6 \fast_a
60459   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60460   wire output 7 \fast_a_ok
60461   attribute \src "libresoc.v:40488.7-40488.15"
60462   wire \initial
60463   attribute \enum_base_type "MicrOp"
60464   attribute \enum_value_0000000 "OP_ILLEGAL"
60465   attribute \enum_value_0000001 "OP_NOP"
60466   attribute \enum_value_0000010 "OP_ADD"
60467   attribute \enum_value_0000011 "OP_ADDPCIS"
60468   attribute \enum_value_0000100 "OP_AND"
60469   attribute \enum_value_0000101 "OP_ATTN"
60470   attribute \enum_value_0000110 "OP_B"
60471   attribute \enum_value_0000111 "OP_BC"
60472   attribute \enum_value_0001000 "OP_BCREG"
60473   attribute \enum_value_0001001 "OP_BPERM"
60474   attribute \enum_value_0001010 "OP_CMP"
60475   attribute \enum_value_0001011 "OP_CMPB"
60476   attribute \enum_value_0001100 "OP_CMPEQB"
60477   attribute \enum_value_0001101 "OP_CMPRB"
60478   attribute \enum_value_0001110 "OP_CNTZ"
60479   attribute \enum_value_0001111 "OP_CRAND"
60480   attribute \enum_value_0010000 "OP_CRANDC"
60481   attribute \enum_value_0010001 "OP_CREQV"
60482   attribute \enum_value_0010010 "OP_CRNAND"
60483   attribute \enum_value_0010011 "OP_CRNOR"
60484   attribute \enum_value_0010100 "OP_CROR"
60485   attribute \enum_value_0010101 "OP_CRORC"
60486   attribute \enum_value_0010110 "OP_CRXOR"
60487   attribute \enum_value_0010111 "OP_DARN"
60488   attribute \enum_value_0011000 "OP_DCBF"
60489   attribute \enum_value_0011001 "OP_DCBST"
60490   attribute \enum_value_0011010 "OP_DCBT"
60491   attribute \enum_value_0011011 "OP_DCBTST"
60492   attribute \enum_value_0011100 "OP_DCBZ"
60493   attribute \enum_value_0011101 "OP_DIV"
60494   attribute \enum_value_0011110 "OP_DIVE"
60495   attribute \enum_value_0011111 "OP_EXTS"
60496   attribute \enum_value_0100000 "OP_EXTSWSLI"
60497   attribute \enum_value_0100001 "OP_ICBI"
60498   attribute \enum_value_0100010 "OP_ICBT"
60499   attribute \enum_value_0100011 "OP_ISEL"
60500   attribute \enum_value_0100100 "OP_ISYNC"
60501   attribute \enum_value_0100101 "OP_LOAD"
60502   attribute \enum_value_0100110 "OP_STORE"
60503   attribute \enum_value_0100111 "OP_MADDHD"
60504   attribute \enum_value_0101000 "OP_MADDHDU"
60505   attribute \enum_value_0101001 "OP_MADDLD"
60506   attribute \enum_value_0101010 "OP_MCRF"
60507   attribute \enum_value_0101011 "OP_MCRXR"
60508   attribute \enum_value_0101100 "OP_MCRXRX"
60509   attribute \enum_value_0101101 "OP_MFCR"
60510   attribute \enum_value_0101110 "OP_MFSPR"
60511   attribute \enum_value_0101111 "OP_MOD"
60512   attribute \enum_value_0110000 "OP_MTCRF"
60513   attribute \enum_value_0110001 "OP_MTSPR"
60514   attribute \enum_value_0110010 "OP_MUL_L64"
60515   attribute \enum_value_0110011 "OP_MUL_H64"
60516   attribute \enum_value_0110100 "OP_MUL_H32"
60517   attribute \enum_value_0110101 "OP_OR"
60518   attribute \enum_value_0110110 "OP_POPCNT"
60519   attribute \enum_value_0110111 "OP_PRTY"
60520   attribute \enum_value_0111000 "OP_RLC"
60521   attribute \enum_value_0111001 "OP_RLCL"
60522   attribute \enum_value_0111010 "OP_RLCR"
60523   attribute \enum_value_0111011 "OP_SETB"
60524   attribute \enum_value_0111100 "OP_SHL"
60525   attribute \enum_value_0111101 "OP_SHR"
60526   attribute \enum_value_0111110 "OP_SYNC"
60527   attribute \enum_value_0111111 "OP_TRAP"
60528   attribute \enum_value_1000011 "OP_XOR"
60529   attribute \enum_value_1000100 "OP_SIM_CONFIG"
60530   attribute \enum_value_1000101 "OP_CROP"
60531   attribute \enum_value_1000110 "OP_RFID"
60532   attribute \enum_value_1000111 "OP_MFMSR"
60533   attribute \enum_value_1001000 "OP_MTMSRD"
60534   attribute \enum_value_1001001 "OP_SC"
60535   attribute \enum_value_1001010 "OP_MTMSR"
60536   attribute \enum_value_1001011 "OP_TLBIE"
60537   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
60538   wire width 7 input 13 \internal_op
60539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
60540   wire width 5 \ra
60541   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60542   wire width 5 output 2 \reg_a
60543   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60544   wire output 3 \reg_a_ok
60545   attribute \enum_base_type "In1Sel"
60546   attribute \enum_value_000 "NONE"
60547   attribute \enum_value_001 "RA"
60548   attribute \enum_value_010 "RA_OR_ZERO"
60549   attribute \enum_value_011 "SPR"
60550   attribute \enum_value_100 "RS"
60551   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88"
60552   wire width 3 input 1 \sel_in
60553   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133"
60554   wire width 10 \spr
60555   attribute \enum_base_type "SPR"
60556   attribute \enum_value_0000000001 "XER"
60557   attribute \enum_value_0000000011 "DSCR"
60558   attribute \enum_value_0000001000 "LR"
60559   attribute \enum_value_0000001001 "CTR"
60560   attribute \enum_value_0000001101 "AMR"
60561   attribute \enum_value_0000010001 "DSCR_priv"
60562   attribute \enum_value_0000010010 "DSISR"
60563   attribute \enum_value_0000010011 "DAR"
60564   attribute \enum_value_0000010110 "DEC"
60565   attribute \enum_value_0000011010 "SRR0"
60566   attribute \enum_value_0000011011 "SRR1"
60567   attribute \enum_value_0000011100 "CFAR"
60568   attribute \enum_value_0000011101 "AMR_priv"
60569   attribute \enum_value_0000110000 "PIDR"
60570   attribute \enum_value_0000111101 "IAMR"
60571   attribute \enum_value_0010000000 "TFHAR"
60572   attribute \enum_value_0010000001 "TFIAR"
60573   attribute \enum_value_0010000010 "TEXASR"
60574   attribute \enum_value_0010000011 "TEXASRU"
60575   attribute \enum_value_0010001000 "CTRL"
60576   attribute \enum_value_0010010000 "TIDR"
60577   attribute \enum_value_0010011000 "CTRL_priv"
60578   attribute \enum_value_0010011001 "FSCR"
60579   attribute \enum_value_0010011101 "UAMOR"
60580   attribute \enum_value_0010011110 "GSR"
60581   attribute \enum_value_0010011111 "PSPB"
60582   attribute \enum_value_0010110000 "DPDES"
60583   attribute \enum_value_0010110100 "DAWR0"
60584   attribute \enum_value_0010111010 "RPR"
60585   attribute \enum_value_0010111011 "CIABR"
60586   attribute \enum_value_0010111100 "DAWRX0"
60587   attribute \enum_value_0010111110 "HFSCR"
60588   attribute \enum_value_0100000000 "VRSAVE"
60589   attribute \enum_value_0100000011 "SPRG3"
60590   attribute \enum_value_0100001100 "TB"
60591   attribute \enum_value_0100001101 "TBU"
60592   attribute \enum_value_0100010000 "SPRG0_priv"
60593   attribute \enum_value_0100010001 "SPRG1_priv"
60594   attribute \enum_value_0100010010 "SPRG2_priv"
60595   attribute \enum_value_0100010011 "SPRG3_priv"
60596   attribute \enum_value_0100011011 "CIR"
60597   attribute \enum_value_0100011100 "TBL"
60598   attribute \enum_value_0100011101 "TBU_hypv"
60599   attribute \enum_value_0100011110 "TBU40"
60600   attribute \enum_value_0100011111 "PVR"
60601   attribute \enum_value_0100110000 "HSPRG0"
60602   attribute \enum_value_0100110001 "HSPRG1"
60603   attribute \enum_value_0100110010 "HDSISR"
60604   attribute \enum_value_0100110011 "HDAR"
60605   attribute \enum_value_0100110100 "SPURR"
60606   attribute \enum_value_0100110101 "PURR"
60607   attribute \enum_value_0100110110 "HDEC"
60608   attribute \enum_value_0100111001 "HRMOR"
60609   attribute \enum_value_0100111010 "HSRR0"
60610   attribute \enum_value_0100111011 "HSRR1"
60611   attribute \enum_value_0100111110 "LPCR"
60612   attribute \enum_value_0100111111 "LPIDR"
60613   attribute \enum_value_0101010000 "HMER"
60614   attribute \enum_value_0101010001 "HMEER"
60615   attribute \enum_value_0101010010 "PCR"
60616   attribute \enum_value_0101010011 "HEIR"
60617   attribute \enum_value_0101011101 "AMOR"
60618   attribute \enum_value_0110111110 "TIR"
60619   attribute \enum_value_0111010000 "PTCR"
60620   attribute \enum_value_1100000000 "SIER"
60621   attribute \enum_value_1100000001 "MMCR2"
60622   attribute \enum_value_1100000010 "MMCRA"
60623   attribute \enum_value_1100000011 "PMC1"
60624   attribute \enum_value_1100000100 "PMC2"
60625   attribute \enum_value_1100000101 "PMC3"
60626   attribute \enum_value_1100000110 "PMC4"
60627   attribute \enum_value_1100000111 "PMC5"
60628   attribute \enum_value_1100001000 "PMC6"
60629   attribute \enum_value_1100001011 "MMCR0"
60630   attribute \enum_value_1100001100 "SIAR"
60631   attribute \enum_value_1100001101 "SDAR"
60632   attribute \enum_value_1100001110 "MMCR1"
60633   attribute \enum_value_1100010000 "SIER_priv"
60634   attribute \enum_value_1100010001 "MMCR2_priv"
60635   attribute \enum_value_1100010010 "MMCRA_priv"
60636   attribute \enum_value_1100010011 "PMC1_priv"
60637   attribute \enum_value_1100010100 "PMC2_priv"
60638   attribute \enum_value_1100010101 "PMC3_priv"
60639   attribute \enum_value_1100010110 "PMC4_priv"
60640   attribute \enum_value_1100010111 "PMC5_priv"
60641   attribute \enum_value_1100011000 "PMC6_priv"
60642   attribute \enum_value_1100011011 "MMCR0_priv"
60643   attribute \enum_value_1100011100 "SIAR_priv"
60644   attribute \enum_value_1100011101 "SDAR_priv"
60645   attribute \enum_value_1100011110 "MMCR1_priv"
60646   attribute \enum_value_1100100000 "BESCRS"
60647   attribute \enum_value_1100100001 "BESCRSU"
60648   attribute \enum_value_1100100010 "BESCRR"
60649   attribute \enum_value_1100100011 "BESCRRU"
60650   attribute \enum_value_1100100100 "EBBHR"
60651   attribute \enum_value_1100100101 "EBBRR"
60652   attribute \enum_value_1100100110 "BESCR"
60653   attribute \enum_value_1100101000 "reserved808"
60654   attribute \enum_value_1100101001 "reserved809"
60655   attribute \enum_value_1100101010 "reserved810"
60656   attribute \enum_value_1100101011 "reserved811"
60657   attribute \enum_value_1100101111 "TAR"
60658   attribute \enum_value_1100110000 "ASDR"
60659   attribute \enum_value_1100110111 "PSSCR"
60660   attribute \enum_value_1101010000 "IC"
60661   attribute \enum_value_1101010001 "VTB"
60662   attribute \enum_value_1101010111 "PSSCR_hypv"
60663   attribute \enum_value_1110000000 "PPR"
60664   attribute \enum_value_1110000010 "PPR32"
60665   attribute \enum_value_1111111111 "PIR"
60666   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60667   wire width 10 output 4 \spr_a
60668   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60669   wire output 5 \spr_a_ok
60670   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60671   wire width 3 \sprmap_fast_o
60672   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60673   wire \sprmap_fast_o_ok
60674   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
60675   wire width 10 \sprmap_spr_i
60676   attribute \enum_base_type "SPR"
60677   attribute \enum_value_0000000001 "XER"
60678   attribute \enum_value_0000000011 "DSCR"
60679   attribute \enum_value_0000001000 "LR"
60680   attribute \enum_value_0000001001 "CTR"
60681   attribute \enum_value_0000001101 "AMR"
60682   attribute \enum_value_0000010001 "DSCR_priv"
60683   attribute \enum_value_0000010010 "DSISR"
60684   attribute \enum_value_0000010011 "DAR"
60685   attribute \enum_value_0000010110 "DEC"
60686   attribute \enum_value_0000011010 "SRR0"
60687   attribute \enum_value_0000011011 "SRR1"
60688   attribute \enum_value_0000011100 "CFAR"
60689   attribute \enum_value_0000011101 "AMR_priv"
60690   attribute \enum_value_0000110000 "PIDR"
60691   attribute \enum_value_0000111101 "IAMR"
60692   attribute \enum_value_0010000000 "TFHAR"
60693   attribute \enum_value_0010000001 "TFIAR"
60694   attribute \enum_value_0010000010 "TEXASR"
60695   attribute \enum_value_0010000011 "TEXASRU"
60696   attribute \enum_value_0010001000 "CTRL"
60697   attribute \enum_value_0010010000 "TIDR"
60698   attribute \enum_value_0010011000 "CTRL_priv"
60699   attribute \enum_value_0010011001 "FSCR"
60700   attribute \enum_value_0010011101 "UAMOR"
60701   attribute \enum_value_0010011110 "GSR"
60702   attribute \enum_value_0010011111 "PSPB"
60703   attribute \enum_value_0010110000 "DPDES"
60704   attribute \enum_value_0010110100 "DAWR0"
60705   attribute \enum_value_0010111010 "RPR"
60706   attribute \enum_value_0010111011 "CIABR"
60707   attribute \enum_value_0010111100 "DAWRX0"
60708   attribute \enum_value_0010111110 "HFSCR"
60709   attribute \enum_value_0100000000 "VRSAVE"
60710   attribute \enum_value_0100000011 "SPRG3"
60711   attribute \enum_value_0100001100 "TB"
60712   attribute \enum_value_0100001101 "TBU"
60713   attribute \enum_value_0100010000 "SPRG0_priv"
60714   attribute \enum_value_0100010001 "SPRG1_priv"
60715   attribute \enum_value_0100010010 "SPRG2_priv"
60716   attribute \enum_value_0100010011 "SPRG3_priv"
60717   attribute \enum_value_0100011011 "CIR"
60718   attribute \enum_value_0100011100 "TBL"
60719   attribute \enum_value_0100011101 "TBU_hypv"
60720   attribute \enum_value_0100011110 "TBU40"
60721   attribute \enum_value_0100011111 "PVR"
60722   attribute \enum_value_0100110000 "HSPRG0"
60723   attribute \enum_value_0100110001 "HSPRG1"
60724   attribute \enum_value_0100110010 "HDSISR"
60725   attribute \enum_value_0100110011 "HDAR"
60726   attribute \enum_value_0100110100 "SPURR"
60727   attribute \enum_value_0100110101 "PURR"
60728   attribute \enum_value_0100110110 "HDEC"
60729   attribute \enum_value_0100111001 "HRMOR"
60730   attribute \enum_value_0100111010 "HSRR0"
60731   attribute \enum_value_0100111011 "HSRR1"
60732   attribute \enum_value_0100111110 "LPCR"
60733   attribute \enum_value_0100111111 "LPIDR"
60734   attribute \enum_value_0101010000 "HMER"
60735   attribute \enum_value_0101010001 "HMEER"
60736   attribute \enum_value_0101010010 "PCR"
60737   attribute \enum_value_0101010011 "HEIR"
60738   attribute \enum_value_0101011101 "AMOR"
60739   attribute \enum_value_0110111110 "TIR"
60740   attribute \enum_value_0111010000 "PTCR"
60741   attribute \enum_value_1100000000 "SIER"
60742   attribute \enum_value_1100000001 "MMCR2"
60743   attribute \enum_value_1100000010 "MMCRA"
60744   attribute \enum_value_1100000011 "PMC1"
60745   attribute \enum_value_1100000100 "PMC2"
60746   attribute \enum_value_1100000101 "PMC3"
60747   attribute \enum_value_1100000110 "PMC4"
60748   attribute \enum_value_1100000111 "PMC5"
60749   attribute \enum_value_1100001000 "PMC6"
60750   attribute \enum_value_1100001011 "MMCR0"
60751   attribute \enum_value_1100001100 "SIAR"
60752   attribute \enum_value_1100001101 "SDAR"
60753   attribute \enum_value_1100001110 "MMCR1"
60754   attribute \enum_value_1100010000 "SIER_priv"
60755   attribute \enum_value_1100010001 "MMCR2_priv"
60756   attribute \enum_value_1100010010 "MMCRA_priv"
60757   attribute \enum_value_1100010011 "PMC1_priv"
60758   attribute \enum_value_1100010100 "PMC2_priv"
60759   attribute \enum_value_1100010101 "PMC3_priv"
60760   attribute \enum_value_1100010110 "PMC4_priv"
60761   attribute \enum_value_1100010111 "PMC5_priv"
60762   attribute \enum_value_1100011000 "PMC6_priv"
60763   attribute \enum_value_1100011011 "MMCR0_priv"
60764   attribute \enum_value_1100011100 "SIAR_priv"
60765   attribute \enum_value_1100011101 "SDAR_priv"
60766   attribute \enum_value_1100011110 "MMCR1_priv"
60767   attribute \enum_value_1100100000 "BESCRS"
60768   attribute \enum_value_1100100001 "BESCRSU"
60769   attribute \enum_value_1100100010 "BESCRR"
60770   attribute \enum_value_1100100011 "BESCRRU"
60771   attribute \enum_value_1100100100 "EBBHR"
60772   attribute \enum_value_1100100101 "EBBRR"
60773   attribute \enum_value_1100100110 "BESCR"
60774   attribute \enum_value_1100101000 "reserved808"
60775   attribute \enum_value_1100101001 "reserved809"
60776   attribute \enum_value_1100101010 "reserved810"
60777   attribute \enum_value_1100101011 "reserved811"
60778   attribute \enum_value_1100101111 "TAR"
60779   attribute \enum_value_1100110000 "ASDR"
60780   attribute \enum_value_1100110111 "PSSCR"
60781   attribute \enum_value_1101010000 "IC"
60782   attribute \enum_value_1101010001 "VTB"
60783   attribute \enum_value_1101010111 "PSSCR_hypv"
60784   attribute \enum_value_1110000000 "PPR"
60785   attribute \enum_value_1110000010 "PPR32"
60786   attribute \enum_value_1111111111 "PIR"
60787   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60788   wire width 10 \sprmap_spr_o
60789   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
60790   wire \sprmap_spr_o_ok
60791   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60792   cell $and $and$libresoc.v:40873$913
60793     parameter \A_SIGNED 0
60794     parameter \A_WIDTH 1
60795     parameter \B_SIGNED 0
60796     parameter \B_WIDTH 1
60797     parameter \Y_WIDTH 1
60798     connect \A \$15
60799     connect \B \$17
60800     connect \Y $and$libresoc.v:40873$913_Y
60801   end
60802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
60803   cell $and $and$libresoc.v:40878$918
60804     parameter \A_SIGNED 0
60805     parameter \A_WIDTH 1
60806     parameter \B_SIGNED 0
60807     parameter \B_WIDTH 1
60808     parameter \Y_WIDTH 1
60809     connect \A \XL_XO [9]
60810     connect \B \$27
60811     connect \Y $and$libresoc.v:40878$918_Y
60812   end
60813   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60814   cell $and $and$libresoc.v:40881$921
60815     parameter \A_SIGNED 0
60816     parameter \A_WIDTH 1
60817     parameter \B_SIGNED 0
60818     parameter \B_WIDTH 1
60819     parameter \Y_WIDTH 1
60820     connect \A \$3
60821     connect \B \$5
60822     connect \Y $and$libresoc.v:40881$921_Y
60823   end
60824   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
60825   cell $eq $eq$libresoc.v:40868$908
60826     parameter \A_SIGNED 0
60827     parameter \A_WIDTH 3
60828     parameter \B_SIGNED 0
60829     parameter \B_WIDTH 3
60830     parameter \Y_WIDTH 1
60831     connect \A \sel_in
60832     connect \B 3'100
60833     connect \Y $eq$libresoc.v:40868$908_Y
60834   end
60835   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
60836   cell $eq $eq$libresoc.v:40869$909
60837     parameter \A_SIGNED 0
60838     parameter \A_WIDTH 3
60839     parameter \B_SIGNED 0
60840     parameter \B_WIDTH 3
60841     parameter \Y_WIDTH 1
60842     connect \A \sel_in
60843     connect \B 3'001
60844     connect \Y $eq$libresoc.v:40869$909_Y
60845   end
60846   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
60847   cell $eq $eq$libresoc.v:40870$910
60848     parameter \A_SIGNED 0
60849     parameter \A_WIDTH 3
60850     parameter \B_SIGNED 0
60851     parameter \B_WIDTH 3
60852     parameter \Y_WIDTH 1
60853     connect \A \sel_in
60854     connect \B 3'010
60855     connect \Y $eq$libresoc.v:40870$910_Y
60856   end
60857   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
60858   cell $eq $eq$libresoc.v:40872$912
60859     parameter \A_SIGNED 0
60860     parameter \A_WIDTH 3
60861     parameter \B_SIGNED 0
60862     parameter \B_WIDTH 3
60863     parameter \Y_WIDTH 1
60864     connect \A \sel_in
60865     connect \B 3'001
60866     connect \Y $eq$libresoc.v:40872$912_Y
60867   end
60868   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
60869   cell $eq $eq$libresoc.v:40875$915
60870     parameter \A_SIGNED 0
60871     parameter \A_WIDTH 3
60872     parameter \B_SIGNED 0
60873     parameter \B_WIDTH 3
60874     parameter \Y_WIDTH 1
60875     connect \A \sel_in
60876     connect \B 3'100
60877     connect \Y $eq$libresoc.v:40875$915_Y
60878   end
60879   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
60880   cell $eq $eq$libresoc.v:40879$919
60881     parameter \A_SIGNED 0
60882     parameter \A_WIDTH 3
60883     parameter \B_SIGNED 0
60884     parameter \B_WIDTH 3
60885     parameter \Y_WIDTH 1
60886     connect \A \sel_in
60887     connect \B 3'010
60888     connect \Y $eq$libresoc.v:40879$919_Y
60889   end
60890   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60891   cell $ne $ne$libresoc.v:40871$911
60892     parameter \A_SIGNED 0
60893     parameter \A_WIDTH 5
60894     parameter \B_SIGNED 0
60895     parameter \B_WIDTH 5
60896     parameter \Y_WIDTH 1
60897     connect \A \ra
60898     connect \B 5'00000
60899     connect \Y $ne$libresoc.v:40871$911_Y
60900   end
60901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60902   cell $ne $ne$libresoc.v:40880$920
60903     parameter \A_SIGNED 0
60904     parameter \A_WIDTH 5
60905     parameter \B_SIGNED 0
60906     parameter \B_WIDTH 5
60907     parameter \Y_WIDTH 1
60908     connect \A \ra
60909     connect \B 5'00000
60910     connect \Y $ne$libresoc.v:40880$920_Y
60911   end
60912   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119"
60913   cell $not $not$libresoc.v:40876$916
60914     parameter \A_SIGNED 0
60915     parameter \A_WIDTH 1
60916     parameter \Y_WIDTH 1
60917     connect \A \BO [2]
60918     connect \Y $not$libresoc.v:40876$916_Y
60919   end
60920   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
60921   cell $not $not$libresoc.v:40877$917
60922     parameter \A_SIGNED 0
60923     parameter \A_WIDTH 1
60924     parameter \Y_WIDTH 1
60925     connect \A \XL_XO [5]
60926     connect \Y $not$libresoc.v:40877$917_Y
60927   end
60928   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60929   cell $or $or$libresoc.v:40867$907
60930     parameter \A_SIGNED 0
60931     parameter \A_WIDTH 1
60932     parameter \B_SIGNED 0
60933     parameter \B_WIDTH 1
60934     parameter \Y_WIDTH 1
60935     connect \A \$1
60936     connect \B \$7
60937     connect \Y $or$libresoc.v:40867$907_Y
60938   end
60939   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60940   cell $or $or$libresoc.v:40874$914
60941     parameter \A_SIGNED 0
60942     parameter \A_WIDTH 1
60943     parameter \B_SIGNED 0
60944     parameter \B_WIDTH 1
60945     parameter \Y_WIDTH 1
60946     connect \A \$13
60947     connect \B \$19
60948     connect \Y $or$libresoc.v:40874$914_Y
60949   end
60950   attribute \module_not_derived 1
60951   attribute \src "libresoc.v:40882.10-40888.4"
60952   cell \sprmap \sprmap
60953     connect \fast_o \sprmap_fast_o
60954     connect \fast_o_ok \sprmap_fast_o_ok
60955     connect \spr_i \sprmap_spr_i
60956     connect \spr_o \sprmap_spr_o
60957     connect \spr_o_ok \sprmap_spr_o_ok
60958   end
60959   attribute \src "libresoc.v:40488.7-40488.20"
60960   process $proc$libresoc.v:40488$928
60961     assign { } { }
60962     assign $0\initial[0:0] 1'0
60963     sync always
60964       update \initial $0\initial[0:0]
60965     sync init
60966   end
60967   attribute \src "libresoc.v:40889.3-40904.6"
60968   process $proc$libresoc.v:40889$922
60969     assign { } { }
60970     assign { } { }
60971     assign { } { }
60972     assign $0\reg_a[4:0] $2\reg_a[4:0]
60973     attribute \src "libresoc.v:40890.5-40890.29"
60974     switch \initial
60975       attribute \src "libresoc.v:40890.9-40890.17"
60976       case 1'1
60977       case
60978     end
60979     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
60980     switch \$9
60981       attribute \src "libresoc.v:0.0-0.0"
60982       case 1'1
60983         assign { } { }
60984         assign $1\reg_a[4:0] \ra
60985       case
60986         assign $1\reg_a[4:0] 5'00000
60987     end
60988     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
60989     switch \$11
60990       attribute \src "libresoc.v:0.0-0.0"
60991       case 1'1
60992         assign { } { }
60993         assign $2\reg_a[4:0] \RS
60994       case
60995         assign $2\reg_a[4:0] $1\reg_a[4:0]
60996     end
60997     sync always
60998       update \reg_a $0\reg_a[4:0]
60999   end
61000   attribute \src "libresoc.v:40905.3-40920.6"
61001   process $proc$libresoc.v:40905$923
61002     assign { } { }
61003     assign { } { }
61004     assign { } { }
61005     assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0]
61006     attribute \src "libresoc.v:40906.5-40906.29"
61007     switch \initial
61008       attribute \src "libresoc.v:40906.9-40906.17"
61009       case 1'1
61010       case
61011     end
61012     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
61013     switch \$21
61014       attribute \src "libresoc.v:0.0-0.0"
61015       case 1'1
61016         assign { } { }
61017         assign $1\reg_a_ok[0:0] 1'1
61018       case
61019         assign $1\reg_a_ok[0:0] 1'0
61020     end
61021     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
61022     switch \$23
61023       attribute \src "libresoc.v:0.0-0.0"
61024       case 1'1
61025         assign { } { }
61026         assign $2\reg_a_ok[0:0] 1'1
61027       case
61028         assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0]
61029     end
61030     sync always
61031       update \reg_a_ok $0\reg_a_ok[0:0]
61032   end
61033   attribute \src "libresoc.v:40921.3-40956.6"
61034   process $proc$libresoc.v:40921$924
61035     assign { } { }
61036     assign { } { }
61037     assign { } { }
61038     assign { } { }
61039     assign $0\fast_a[2:0] $1\fast_a[2:0]
61040     assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0]
61041     attribute \src "libresoc.v:40922.5-40922.29"
61042     switch \initial
61043       attribute \src "libresoc.v:40922.9-40922.17"
61044       case 1'1
61045       case
61046     end
61047     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
61048     switch \internal_op
61049       attribute \src "libresoc.v:0.0-0.0"
61050       case 7'0000111
61051         assign { } { }
61052         assign { } { }
61053         assign $1\fast_a[2:0] $2\fast_a[2:0]
61054         assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0]
61055         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119"
61056         switch \$25
61057           attribute \src "libresoc.v:0.0-0.0"
61058           case 1'1
61059             assign { } { }
61060             assign { } { }
61061             assign $2\fast_a[2:0] 3'000
61062             assign $2\fast_a_ok[0:0] 1'1
61063           case
61064             assign $2\fast_a[2:0] 3'000
61065             assign $2\fast_a_ok[0:0] 1'0
61066         end
61067       attribute \src "libresoc.v:0.0-0.0"
61068       case 7'0001000
61069         assign { } { }
61070         assign { } { }
61071         assign $1\fast_a[2:0] $3\fast_a[2:0]
61072         assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0]
61073         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
61074         switch \$29
61075           attribute \src "libresoc.v:0.0-0.0"
61076           case 1'1
61077             assign { } { }
61078             assign { } { }
61079             assign $3\fast_a[2:0] 3'000
61080             assign $3\fast_a_ok[0:0] 1'1
61081           case
61082             assign $3\fast_a[2:0] 3'000
61083             assign $3\fast_a_ok[0:0] 1'0
61084         end
61085       attribute \src "libresoc.v:0.0-0.0"
61086       case 7'0101110
61087         assign { } { }
61088         assign { } { }
61089         assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o }
61090       case
61091         assign $1\fast_a[2:0] 3'000
61092         assign $1\fast_a_ok[0:0] 1'0
61093     end
61094     sync always
61095       update \fast_a $0\fast_a[2:0]
61096       update \fast_a_ok $0\fast_a_ok[0:0]
61097   end
61098   attribute \src "libresoc.v:40957.3-40967.6"
61099   process $proc$libresoc.v:40957$925
61100     assign { } { }
61101     assign { } { }
61102     assign $0\spr[9:0] $1\spr[9:0]
61103     attribute \src "libresoc.v:40958.5-40958.29"
61104     switch \initial
61105       attribute \src "libresoc.v:40958.9-40958.17"
61106       case 1'1
61107       case
61108     end
61109     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
61110     switch \internal_op
61111       attribute \src "libresoc.v:0.0-0.0"
61112       case 7'0101110
61113         assign { } { }
61114         assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] }
61115       case
61116         assign $1\spr[9:0] 10'0000000000
61117     end
61118     sync always
61119       update \spr $0\spr[9:0]
61120   end
61121   attribute \src "libresoc.v:40968.3-40978.6"
61122   process $proc$libresoc.v:40968$926
61123     assign { } { }
61124     assign { } { }
61125     assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
61126     attribute \src "libresoc.v:40969.5-40969.29"
61127     switch \initial
61128       attribute \src "libresoc.v:40969.9-40969.17"
61129       case 1'1
61130       case
61131     end
61132     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
61133     switch \internal_op
61134       attribute \src "libresoc.v:0.0-0.0"
61135       case 7'0101110
61136         assign { } { }
61137         assign $1\sprmap_spr_i[9:0] \spr
61138       case
61139         assign $1\sprmap_spr_i[9:0] 10'0000000000
61140     end
61141     sync always
61142       update \sprmap_spr_i $0\sprmap_spr_i[9:0]
61143   end
61144   attribute \src "libresoc.v:40979.3-40990.6"
61145   process $proc$libresoc.v:40979$927
61146     assign { } { }
61147     assign { } { }
61148     assign { } { }
61149     assign { } { }
61150     assign $0\spr_a[9:0] $1\spr_a[9:0]
61151     assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0]
61152     attribute \src "libresoc.v:40980.5-40980.29"
61153     switch \initial
61154       attribute \src "libresoc.v:40980.9-40980.17"
61155       case 1'1
61156       case
61157     end
61158     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
61159     switch \internal_op
61160       attribute \src "libresoc.v:0.0-0.0"
61161       case 7'0101110
61162         assign { } { }
61163         assign { } { }
61164         assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o }
61165       case
61166         assign $1\spr_a[9:0] 10'0000000000
61167         assign $1\spr_a_ok[0:0] 1'0
61168     end
61169     sync always
61170       update \spr_a $0\spr_a[9:0]
61171       update \spr_a_ok $0\spr_a_ok[0:0]
61172   end
61173   connect \$9 $or$libresoc.v:40867$907_Y
61174   connect \$11 $eq$libresoc.v:40868$908_Y
61175   connect \$13 $eq$libresoc.v:40869$909_Y
61176   connect \$15 $eq$libresoc.v:40870$910_Y
61177   connect \$17 $ne$libresoc.v:40871$911_Y
61178   connect \$1 $eq$libresoc.v:40872$912_Y
61179   connect \$19 $and$libresoc.v:40873$913_Y
61180   connect \$21 $or$libresoc.v:40874$914_Y
61181   connect \$23 $eq$libresoc.v:40875$915_Y
61182   connect \$25 $not$libresoc.v:40876$916_Y
61183   connect \$27 $not$libresoc.v:40877$917_Y
61184   connect \$29 $and$libresoc.v:40878$918_Y
61185   connect \$3 $eq$libresoc.v:40879$919_Y
61186   connect \$5 $ne$libresoc.v:40880$920_Y
61187   connect \$7 $and$libresoc.v:40881$921_Y
61188   connect \ra \RA
61189 end
61190 attribute \src "libresoc.v:40996.1-41187.10"
61191 attribute \cells_not_processed 1
61192 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b"
61193 attribute \generator "nMigen"
61194 module \dec_b
61195   attribute \src "libresoc.v:41151.3-41168.6"
61196   wire width 3 $0\fast_b[2:0]
61197   attribute \src "libresoc.v:41169.3-41186.6"
61198   wire $0\fast_b_ok[0:0]
61199   attribute \src "libresoc.v:40997.7-40997.20"
61200   wire $0\initial[0:0]
61201   attribute \src "libresoc.v:41121.3-41135.6"
61202   wire width 5 $0\reg_b[4:0]
61203   attribute \src "libresoc.v:41136.3-41150.6"
61204   wire $0\reg_b_ok[0:0]
61205   attribute \src "libresoc.v:41151.3-41168.6"
61206   wire width 3 $1\fast_b[2:0]
61207   attribute \src "libresoc.v:41169.3-41186.6"
61208   wire $1\fast_b_ok[0:0]
61209   attribute \src "libresoc.v:41121.3-41135.6"
61210   wire width 5 $1\reg_b[4:0]
61211   attribute \src "libresoc.v:41136.3-41150.6"
61212   wire $1\reg_b_ok[0:0]
61213   attribute \src "libresoc.v:41151.3-41168.6"
61214   wire width 3 $2\fast_b[2:0]
61215   attribute \src "libresoc.v:41169.3-41186.6"
61216   wire $2\fast_b_ok[0:0]
61217   attribute \src "libresoc.v:41117.17-41117.117"
61218   wire $eq$libresoc.v:41117$929_Y
61219   attribute \src "libresoc.v:41119.17-41119.117"
61220   wire $eq$libresoc.v:41119$931_Y
61221   attribute \src "libresoc.v:41118.17-41118.107"
61222   wire $not$libresoc.v:41118$930_Y
61223   attribute \src "libresoc.v:41120.17-41120.107"
61224   wire $not$libresoc.v:41120$932_Y
61225   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
61226   wire \$1
61227   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
61228   wire \$3
61229   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
61230   wire \$5
61231   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
61232   wire \$7
61233   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61234   wire width 5 input 7 \RB
61235   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61236   wire width 5 input 6 \RS
61237   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
61238   wire width 10 input 8 \XL_XO
61239   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61240   wire width 3 output 4 \fast_b
61241   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61242   wire output 5 \fast_b_ok
61243   attribute \src "libresoc.v:40997.7-40997.15"
61244   wire \initial
61245   attribute \enum_base_type "MicrOp"
61246   attribute \enum_value_0000000 "OP_ILLEGAL"
61247   attribute \enum_value_0000001 "OP_NOP"
61248   attribute \enum_value_0000010 "OP_ADD"
61249   attribute \enum_value_0000011 "OP_ADDPCIS"
61250   attribute \enum_value_0000100 "OP_AND"
61251   attribute \enum_value_0000101 "OP_ATTN"
61252   attribute \enum_value_0000110 "OP_B"
61253   attribute \enum_value_0000111 "OP_BC"
61254   attribute \enum_value_0001000 "OP_BCREG"
61255   attribute \enum_value_0001001 "OP_BPERM"
61256   attribute \enum_value_0001010 "OP_CMP"
61257   attribute \enum_value_0001011 "OP_CMPB"
61258   attribute \enum_value_0001100 "OP_CMPEQB"
61259   attribute \enum_value_0001101 "OP_CMPRB"
61260   attribute \enum_value_0001110 "OP_CNTZ"
61261   attribute \enum_value_0001111 "OP_CRAND"
61262   attribute \enum_value_0010000 "OP_CRANDC"
61263   attribute \enum_value_0010001 "OP_CREQV"
61264   attribute \enum_value_0010010 "OP_CRNAND"
61265   attribute \enum_value_0010011 "OP_CRNOR"
61266   attribute \enum_value_0010100 "OP_CROR"
61267   attribute \enum_value_0010101 "OP_CRORC"
61268   attribute \enum_value_0010110 "OP_CRXOR"
61269   attribute \enum_value_0010111 "OP_DARN"
61270   attribute \enum_value_0011000 "OP_DCBF"
61271   attribute \enum_value_0011001 "OP_DCBST"
61272   attribute \enum_value_0011010 "OP_DCBT"
61273   attribute \enum_value_0011011 "OP_DCBTST"
61274   attribute \enum_value_0011100 "OP_DCBZ"
61275   attribute \enum_value_0011101 "OP_DIV"
61276   attribute \enum_value_0011110 "OP_DIVE"
61277   attribute \enum_value_0011111 "OP_EXTS"
61278   attribute \enum_value_0100000 "OP_EXTSWSLI"
61279   attribute \enum_value_0100001 "OP_ICBI"
61280   attribute \enum_value_0100010 "OP_ICBT"
61281   attribute \enum_value_0100011 "OP_ISEL"
61282   attribute \enum_value_0100100 "OP_ISYNC"
61283   attribute \enum_value_0100101 "OP_LOAD"
61284   attribute \enum_value_0100110 "OP_STORE"
61285   attribute \enum_value_0100111 "OP_MADDHD"
61286   attribute \enum_value_0101000 "OP_MADDHDU"
61287   attribute \enum_value_0101001 "OP_MADDLD"
61288   attribute \enum_value_0101010 "OP_MCRF"
61289   attribute \enum_value_0101011 "OP_MCRXR"
61290   attribute \enum_value_0101100 "OP_MCRXRX"
61291   attribute \enum_value_0101101 "OP_MFCR"
61292   attribute \enum_value_0101110 "OP_MFSPR"
61293   attribute \enum_value_0101111 "OP_MOD"
61294   attribute \enum_value_0110000 "OP_MTCRF"
61295   attribute \enum_value_0110001 "OP_MTSPR"
61296   attribute \enum_value_0110010 "OP_MUL_L64"
61297   attribute \enum_value_0110011 "OP_MUL_H64"
61298   attribute \enum_value_0110100 "OP_MUL_H32"
61299   attribute \enum_value_0110101 "OP_OR"
61300   attribute \enum_value_0110110 "OP_POPCNT"
61301   attribute \enum_value_0110111 "OP_PRTY"
61302   attribute \enum_value_0111000 "OP_RLC"
61303   attribute \enum_value_0111001 "OP_RLCL"
61304   attribute \enum_value_0111010 "OP_RLCR"
61305   attribute \enum_value_0111011 "OP_SETB"
61306   attribute \enum_value_0111100 "OP_SHL"
61307   attribute \enum_value_0111101 "OP_SHR"
61308   attribute \enum_value_0111110 "OP_SYNC"
61309   attribute \enum_value_0111111 "OP_TRAP"
61310   attribute \enum_value_1000011 "OP_XOR"
61311   attribute \enum_value_1000100 "OP_SIM_CONFIG"
61312   attribute \enum_value_1000101 "OP_CROP"
61313   attribute \enum_value_1000110 "OP_RFID"
61314   attribute \enum_value_1000111 "OP_MFMSR"
61315   attribute \enum_value_1001000 "OP_MTMSRD"
61316   attribute \enum_value_1001001 "OP_SC"
61317   attribute \enum_value_1001010 "OP_MTMSR"
61318   attribute \enum_value_1001011 "OP_TLBIE"
61319   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
61320   wire width 7 input 9 \internal_op
61321   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61322   wire width 5 output 2 \reg_b
61323   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61324   wire output 3 \reg_b_ok
61325   attribute \enum_base_type "In2Sel"
61326   attribute \enum_value_0000 "NONE"
61327   attribute \enum_value_0001 "RB"
61328   attribute \enum_value_0010 "CONST_UI"
61329   attribute \enum_value_0011 "CONST_SI"
61330   attribute \enum_value_0100 "CONST_UI_HI"
61331   attribute \enum_value_0101 "CONST_SI_HI"
61332   attribute \enum_value_0110 "CONST_LI"
61333   attribute \enum_value_0111 "CONST_BD"
61334   attribute \enum_value_1000 "CONST_DS"
61335   attribute \enum_value_1001 "CONST_M1"
61336   attribute \enum_value_1010 "CONST_SH"
61337   attribute \enum_value_1011 "CONST_SH32"
61338   attribute \enum_value_1100 "SPR"
61339   attribute \enum_value_1101 "RS"
61340   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
61341   wire width 4 input 1 \sel_in
61342   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
61343   cell $eq $eq$libresoc.v:41117$929
61344     parameter \A_SIGNED 0
61345     parameter \A_WIDTH 7
61346     parameter \B_SIGNED 0
61347     parameter \B_WIDTH 7
61348     parameter \Y_WIDTH 1
61349     connect \A \internal_op
61350     connect \B 7'0001000
61351     connect \Y $eq$libresoc.v:41117$929_Y
61352   end
61353   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
61354   cell $eq $eq$libresoc.v:41119$931
61355     parameter \A_SIGNED 0
61356     parameter \A_WIDTH 7
61357     parameter \B_SIGNED 0
61358     parameter \B_WIDTH 7
61359     parameter \Y_WIDTH 1
61360     connect \A \internal_op
61361     connect \B 7'0001000
61362     connect \Y $eq$libresoc.v:41119$931_Y
61363   end
61364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
61365   cell $not $not$libresoc.v:41118$930
61366     parameter \A_SIGNED 0
61367     parameter \A_WIDTH 1
61368     parameter \Y_WIDTH 1
61369     connect \A \XL_XO [9]
61370     connect \Y $not$libresoc.v:41118$930_Y
61371   end
61372   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
61373   cell $not $not$libresoc.v:41120$932
61374     parameter \A_SIGNED 0
61375     parameter \A_WIDTH 1
61376     parameter \Y_WIDTH 1
61377     connect \A \XL_XO [9]
61378     connect \Y $not$libresoc.v:41120$932_Y
61379   end
61380   attribute \src "libresoc.v:40997.7-40997.20"
61381   process $proc$libresoc.v:40997$937
61382     assign { } { }
61383     assign $0\initial[0:0] 1'0
61384     sync always
61385       update \initial $0\initial[0:0]
61386     sync init
61387   end
61388   attribute \src "libresoc.v:41121.3-41135.6"
61389   process $proc$libresoc.v:41121$933
61390     assign { } { }
61391     assign { } { }
61392     assign $0\reg_b[4:0] $1\reg_b[4:0]
61393     attribute \src "libresoc.v:41122.5-41122.29"
61394     switch \initial
61395       attribute \src "libresoc.v:41122.9-41122.17"
61396       case 1'1
61397       case
61398     end
61399     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
61400     switch \sel_in
61401       attribute \src "libresoc.v:0.0-0.0"
61402       case 4'0001
61403         assign { } { }
61404         assign $1\reg_b[4:0] \RB
61405       attribute \src "libresoc.v:0.0-0.0"
61406       case 4'1101
61407         assign { } { }
61408         assign $1\reg_b[4:0] \RS
61409       case
61410         assign $1\reg_b[4:0] 5'00000
61411     end
61412     sync always
61413       update \reg_b $0\reg_b[4:0]
61414   end
61415   attribute \src "libresoc.v:41136.3-41150.6"
61416   process $proc$libresoc.v:41136$934
61417     assign { } { }
61418     assign { } { }
61419     assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0]
61420     attribute \src "libresoc.v:41137.5-41137.29"
61421     switch \initial
61422       attribute \src "libresoc.v:41137.9-41137.17"
61423       case 1'1
61424       case
61425     end
61426     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
61427     switch \sel_in
61428       attribute \src "libresoc.v:0.0-0.0"
61429       case 4'0001
61430         assign { } { }
61431         assign $1\reg_b_ok[0:0] 1'1
61432       attribute \src "libresoc.v:0.0-0.0"
61433       case 4'1101
61434         assign { } { }
61435         assign $1\reg_b_ok[0:0] 1'1
61436       case
61437         assign $1\reg_b_ok[0:0] 1'0
61438     end
61439     sync always
61440       update \reg_b_ok $0\reg_b_ok[0:0]
61441   end
61442   attribute \src "libresoc.v:41151.3-41168.6"
61443   process $proc$libresoc.v:41151$935
61444     assign { } { }
61445     assign { } { }
61446     assign $0\fast_b[2:0] $1\fast_b[2:0]
61447     attribute \src "libresoc.v:41152.5-41152.29"
61448     switch \initial
61449       attribute \src "libresoc.v:41152.9-41152.17"
61450       case 1'1
61451       case
61452     end
61453     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
61454     switch \$1
61455       attribute \src "libresoc.v:0.0-0.0"
61456       case 1'1
61457         assign { } { }
61458         assign $1\fast_b[2:0] $2\fast_b[2:0]
61459         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
61460         switch { \XL_XO [5] \$3 }
61461           attribute \src "libresoc.v:0.0-0.0"
61462           case 2'-1
61463             assign { } { }
61464             assign $2\fast_b[2:0] 3'001
61465           attribute \src "libresoc.v:0.0-0.0"
61466           case 2'1-
61467             assign { } { }
61468             assign $2\fast_b[2:0] 3'010
61469           case
61470             assign $2\fast_b[2:0] 3'000
61471         end
61472       case
61473         assign $1\fast_b[2:0] 3'000
61474     end
61475     sync always
61476       update \fast_b $0\fast_b[2:0]
61477   end
61478   attribute \src "libresoc.v:41169.3-41186.6"
61479   process $proc$libresoc.v:41169$936
61480     assign { } { }
61481     assign { } { }
61482     assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0]
61483     attribute \src "libresoc.v:41170.5-41170.29"
61484     switch \initial
61485       attribute \src "libresoc.v:41170.9-41170.17"
61486       case 1'1
61487       case
61488     end
61489     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
61490     switch \$5
61491       attribute \src "libresoc.v:0.0-0.0"
61492       case 1'1
61493         assign { } { }
61494         assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0]
61495         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
61496         switch { \XL_XO [5] \$7 }
61497           attribute \src "libresoc.v:0.0-0.0"
61498           case 2'-1
61499             assign { } { }
61500             assign $2\fast_b_ok[0:0] 1'1
61501           attribute \src "libresoc.v:0.0-0.0"
61502           case 2'1-
61503             assign { } { }
61504             assign $2\fast_b_ok[0:0] 1'1
61505           case
61506             assign $2\fast_b_ok[0:0] 1'0
61507         end
61508       case
61509         assign $1\fast_b_ok[0:0] 1'0
61510     end
61511     sync always
61512       update \fast_b_ok $0\fast_b_ok[0:0]
61513   end
61514   connect \$1 $eq$libresoc.v:41117$929_Y
61515   connect \$3 $not$libresoc.v:41118$930_Y
61516   connect \$5 $eq$libresoc.v:41119$931_Y
61517   connect \$7 $not$libresoc.v:41120$932_Y
61518 end
61519 attribute \src "libresoc.v:41191.1-41239.10"
61520 attribute \cells_not_processed 1
61521 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c"
61522 attribute \generator "nMigen"
61523 module \dec_c
61524   attribute \src "libresoc.v:41192.7-41192.20"
61525   wire $0\initial[0:0]
61526   attribute \src "libresoc.v:41209.3-41223.6"
61527   wire width 5 $0\reg_c[4:0]
61528   attribute \src "libresoc.v:41224.3-41238.6"
61529   wire $0\reg_c_ok[0:0]
61530   attribute \src "libresoc.v:41209.3-41223.6"
61531   wire width 5 $1\reg_c[4:0]
61532   attribute \src "libresoc.v:41224.3-41238.6"
61533   wire $1\reg_c_ok[0:0]
61534   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61535   wire width 5 input 4 \RB
61536   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61537   wire width 5 input 3 \RS
61538   attribute \src "libresoc.v:41192.7-41192.15"
61539   wire \initial
61540   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61541   wire width 5 output 1 \reg_c
61542   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61543   wire output 2 \reg_c_ok
61544   attribute \enum_base_type "In3Sel"
61545   attribute \enum_value_00 "NONE"
61546   attribute \enum_value_01 "RS"
61547   attribute \enum_value_10 "RB"
61548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282"
61549   wire width 2 input 5 \sel_in
61550   attribute \src "libresoc.v:41192.7-41192.20"
61551   process $proc$libresoc.v:41192$940
61552     assign { } { }
61553     assign $0\initial[0:0] 1'0
61554     sync always
61555       update \initial $0\initial[0:0]
61556     sync init
61557   end
61558   attribute \src "libresoc.v:41209.3-41223.6"
61559   process $proc$libresoc.v:41209$938
61560     assign { } { }
61561     assign { } { }
61562     assign $0\reg_c[4:0] $1\reg_c[4:0]
61563     attribute \src "libresoc.v:41210.5-41210.29"
61564     switch \initial
61565       attribute \src "libresoc.v:41210.9-41210.17"
61566       case 1'1
61567       case
61568     end
61569     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
61570     switch \sel_in
61571       attribute \src "libresoc.v:0.0-0.0"
61572       case 2'10
61573         assign { } { }
61574         assign $1\reg_c[4:0] \RB
61575       attribute \src "libresoc.v:0.0-0.0"
61576       case 2'01
61577         assign { } { }
61578         assign $1\reg_c[4:0] \RS
61579       case
61580         assign $1\reg_c[4:0] 5'00000
61581     end
61582     sync always
61583       update \reg_c $0\reg_c[4:0]
61584   end
61585   attribute \src "libresoc.v:41224.3-41238.6"
61586   process $proc$libresoc.v:41224$939
61587     assign { } { }
61588     assign { } { }
61589     assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0]
61590     attribute \src "libresoc.v:41225.5-41225.29"
61591     switch \initial
61592       attribute \src "libresoc.v:41225.9-41225.17"
61593       case 1'1
61594       case
61595     end
61596     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
61597     switch \sel_in
61598       attribute \src "libresoc.v:0.0-0.0"
61599       case 2'10
61600         assign { } { }
61601         assign $1\reg_c_ok[0:0] 1'1
61602       attribute \src "libresoc.v:0.0-0.0"
61603       case 2'01
61604         assign { } { }
61605         assign $1\reg_c_ok[0:0] 1'1
61606       case
61607         assign $1\reg_c_ok[0:0] 1'0
61608     end
61609     sync always
61610       update \reg_c_ok $0\reg_c_ok[0:0]
61611   end
61612 end
61613 attribute \src "libresoc.v:41243.1-41548.10"
61614 attribute \cells_not_processed 1
61615 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in"
61616 attribute \generator "nMigen"
61617 module \dec_cr_in
61618   attribute \src "libresoc.v:41442.3-41468.6"
61619   wire width 3 $0\cr_bitfield[2:0]
61620   attribute \src "libresoc.v:41469.3-41479.6"
61621   wire width 3 $0\cr_bitfield_b[2:0]
61622   attribute \src "libresoc.v:41420.3-41430.6"
61623   wire $0\cr_bitfield_b_ok[0:0]
61624   attribute \src "libresoc.v:41480.3-41490.6"
61625   wire width 3 $0\cr_bitfield_o[2:0]
61626   attribute \src "libresoc.v:41491.3-41501.6"
61627   wire $0\cr_bitfield_o_ok[0:0]
61628   attribute \src "libresoc.v:41393.3-41419.6"
61629   wire $0\cr_bitfield_ok[0:0]
61630   attribute \src "libresoc.v:41529.3-41547.6"
61631   wire width 8 $0\cr_fxm[7:0]
61632   attribute \src "libresoc.v:41431.3-41441.6"
61633   wire $0\cr_fxm_ok[0:0]
61634   attribute \src "libresoc.v:41244.7-41244.20"
61635   wire $0\initial[0:0]
61636   attribute \src "libresoc.v:41502.3-41512.6"
61637   wire $0\move_one[0:0]
61638   attribute \src "libresoc.v:41513.3-41528.6"
61639   wire width 8 $0\ppick_i[7:0]
61640   attribute \src "libresoc.v:41442.3-41468.6"
61641   wire width 3 $1\cr_bitfield[2:0]
61642   attribute \src "libresoc.v:41469.3-41479.6"
61643   wire width 3 $1\cr_bitfield_b[2:0]
61644   attribute \src "libresoc.v:41420.3-41430.6"
61645   wire $1\cr_bitfield_b_ok[0:0]
61646   attribute \src "libresoc.v:41480.3-41490.6"
61647   wire width 3 $1\cr_bitfield_o[2:0]
61648   attribute \src "libresoc.v:41491.3-41501.6"
61649   wire $1\cr_bitfield_o_ok[0:0]
61650   attribute \src "libresoc.v:41393.3-41419.6"
61651   wire $1\cr_bitfield_ok[0:0]
61652   attribute \src "libresoc.v:41529.3-41547.6"
61653   wire width 8 $1\cr_fxm[7:0]
61654   attribute \src "libresoc.v:41431.3-41441.6"
61655   wire $1\cr_fxm_ok[0:0]
61656   attribute \src "libresoc.v:41502.3-41512.6"
61657   wire $1\move_one[0:0]
61658   attribute \src "libresoc.v:41513.3-41528.6"
61659   wire width 8 $1\ppick_i[7:0]
61660   attribute \src "libresoc.v:41529.3-41547.6"
61661   wire width 8 $2\cr_fxm[7:0]
61662   attribute \src "libresoc.v:41513.3-41528.6"
61663   wire width 8 $2\ppick_i[7:0]
61664   attribute \src "libresoc.v:41386.17-41386.112"
61665   wire $and$libresoc.v:41386$942_Y
61666   attribute \src "libresoc.v:41388.17-41388.112"
61667   wire $and$libresoc.v:41388$944_Y
61668   attribute \src "libresoc.v:41385.17-41385.117"
61669   wire $eq$libresoc.v:41385$941_Y
61670   attribute \src "libresoc.v:41387.17-41387.117"
61671   wire $eq$libresoc.v:41387$943_Y
61672   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61673   wire \$1
61674   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61675   wire \$3
61676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61677   wire \$5
61678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61679   wire \$7
61680   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61681   wire width 5 input 12 \BA
61682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61683   wire width 5 input 11 \BB
61684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61685   wire width 5 input 16 \BC
61686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61687   wire width 5 input 15 \BI
61688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61689   wire width 5 input 13 \BT
61690   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
61691   wire width 8 input 14 \FXM
61692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
61693   wire width 3 input 17 \X_BFA
61694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61695   wire width 3 output 5 \cr_bitfield
61696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61697   wire width 3 output 7 \cr_bitfield_b
61698   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61699   wire output 8 \cr_bitfield_b_ok
61700   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61701   wire width 3 output 9 \cr_bitfield_o
61702   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61703   wire output 10 \cr_bitfield_o_ok
61704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61705   wire output 6 \cr_bitfield_ok
61706   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61707   wire width 8 output 3 \cr_fxm
61708   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
61709   wire output 4 \cr_fxm_ok
61710   attribute \src "libresoc.v:41244.7-41244.15"
61711   wire \initial
61712   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
61713   wire width 32 input 18 \insn_in
61714   attribute \enum_base_type "MicrOp"
61715   attribute \enum_value_0000000 "OP_ILLEGAL"
61716   attribute \enum_value_0000001 "OP_NOP"
61717   attribute \enum_value_0000010 "OP_ADD"
61718   attribute \enum_value_0000011 "OP_ADDPCIS"
61719   attribute \enum_value_0000100 "OP_AND"
61720   attribute \enum_value_0000101 "OP_ATTN"
61721   attribute \enum_value_0000110 "OP_B"
61722   attribute \enum_value_0000111 "OP_BC"
61723   attribute \enum_value_0001000 "OP_BCREG"
61724   attribute \enum_value_0001001 "OP_BPERM"
61725   attribute \enum_value_0001010 "OP_CMP"
61726   attribute \enum_value_0001011 "OP_CMPB"
61727   attribute \enum_value_0001100 "OP_CMPEQB"
61728   attribute \enum_value_0001101 "OP_CMPRB"
61729   attribute \enum_value_0001110 "OP_CNTZ"
61730   attribute \enum_value_0001111 "OP_CRAND"
61731   attribute \enum_value_0010000 "OP_CRANDC"
61732   attribute \enum_value_0010001 "OP_CREQV"
61733   attribute \enum_value_0010010 "OP_CRNAND"
61734   attribute \enum_value_0010011 "OP_CRNOR"
61735   attribute \enum_value_0010100 "OP_CROR"
61736   attribute \enum_value_0010101 "OP_CRORC"
61737   attribute \enum_value_0010110 "OP_CRXOR"
61738   attribute \enum_value_0010111 "OP_DARN"
61739   attribute \enum_value_0011000 "OP_DCBF"
61740   attribute \enum_value_0011001 "OP_DCBST"
61741   attribute \enum_value_0011010 "OP_DCBT"
61742   attribute \enum_value_0011011 "OP_DCBTST"
61743   attribute \enum_value_0011100 "OP_DCBZ"
61744   attribute \enum_value_0011101 "OP_DIV"
61745   attribute \enum_value_0011110 "OP_DIVE"
61746   attribute \enum_value_0011111 "OP_EXTS"
61747   attribute \enum_value_0100000 "OP_EXTSWSLI"
61748   attribute \enum_value_0100001 "OP_ICBI"
61749   attribute \enum_value_0100010 "OP_ICBT"
61750   attribute \enum_value_0100011 "OP_ISEL"
61751   attribute \enum_value_0100100 "OP_ISYNC"
61752   attribute \enum_value_0100101 "OP_LOAD"
61753   attribute \enum_value_0100110 "OP_STORE"
61754   attribute \enum_value_0100111 "OP_MADDHD"
61755   attribute \enum_value_0101000 "OP_MADDHDU"
61756   attribute \enum_value_0101001 "OP_MADDLD"
61757   attribute \enum_value_0101010 "OP_MCRF"
61758   attribute \enum_value_0101011 "OP_MCRXR"
61759   attribute \enum_value_0101100 "OP_MCRXRX"
61760   attribute \enum_value_0101101 "OP_MFCR"
61761   attribute \enum_value_0101110 "OP_MFSPR"
61762   attribute \enum_value_0101111 "OP_MOD"
61763   attribute \enum_value_0110000 "OP_MTCRF"
61764   attribute \enum_value_0110001 "OP_MTSPR"
61765   attribute \enum_value_0110010 "OP_MUL_L64"
61766   attribute \enum_value_0110011 "OP_MUL_H64"
61767   attribute \enum_value_0110100 "OP_MUL_H32"
61768   attribute \enum_value_0110101 "OP_OR"
61769   attribute \enum_value_0110110 "OP_POPCNT"
61770   attribute \enum_value_0110111 "OP_PRTY"
61771   attribute \enum_value_0111000 "OP_RLC"
61772   attribute \enum_value_0111001 "OP_RLCL"
61773   attribute \enum_value_0111010 "OP_RLCR"
61774   attribute \enum_value_0111011 "OP_SETB"
61775   attribute \enum_value_0111100 "OP_SHL"
61776   attribute \enum_value_0111101 "OP_SHR"
61777   attribute \enum_value_0111110 "OP_SYNC"
61778   attribute \enum_value_0111111 "OP_TRAP"
61779   attribute \enum_value_1000011 "OP_XOR"
61780   attribute \enum_value_1000100 "OP_SIM_CONFIG"
61781   attribute \enum_value_1000101 "OP_CROP"
61782   attribute \enum_value_1000110 "OP_RFID"
61783   attribute \enum_value_1000111 "OP_MFMSR"
61784   attribute \enum_value_1001000 "OP_MTMSRD"
61785   attribute \enum_value_1001001 "OP_SC"
61786   attribute \enum_value_1001010 "OP_MTMSR"
61787   attribute \enum_value_1001011 "OP_TLBIE"
61788   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
61789   wire width 7 input 2 \internal_op
61790   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
61791   wire \move_one
61792   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40"
61793   wire width 8 \ppick_i
61794   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41"
61795   wire width 8 \ppick_o
61796   attribute \enum_base_type "CRInSel"
61797   attribute \enum_value_000 "NONE"
61798   attribute \enum_value_001 "CR0"
61799   attribute \enum_value_010 "BI"
61800   attribute \enum_value_011 "BFA"
61801   attribute \enum_value_100 "BA_BB"
61802   attribute \enum_value_101 "BC"
61803   attribute \enum_value_110 "WHOLE_REG"
61804   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488"
61805   wire width 3 input 1 \sel_in
61806   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61807   cell $and $and$libresoc.v:41386$942
61808     parameter \A_SIGNED 0
61809     parameter \A_WIDTH 1
61810     parameter \B_SIGNED 0
61811     parameter \B_WIDTH 1
61812     parameter \Y_WIDTH 1
61813     connect \A \$1
61814     connect \B \move_one
61815     connect \Y $and$libresoc.v:41386$942_Y
61816   end
61817   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61818   cell $and $and$libresoc.v:41388$944
61819     parameter \A_SIGNED 0
61820     parameter \A_WIDTH 1
61821     parameter \B_SIGNED 0
61822     parameter \B_WIDTH 1
61823     parameter \Y_WIDTH 1
61824     connect \A \$5
61825     connect \B \move_one
61826     connect \Y $and$libresoc.v:41388$944_Y
61827   end
61828   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61829   cell $eq $eq$libresoc.v:41385$941
61830     parameter \A_SIGNED 0
61831     parameter \A_WIDTH 7
61832     parameter \B_SIGNED 0
61833     parameter \B_WIDTH 7
61834     parameter \Y_WIDTH 1
61835     connect \A \internal_op
61836     connect \B 7'0101101
61837     connect \Y $eq$libresoc.v:41385$941_Y
61838   end
61839   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
61840   cell $eq $eq$libresoc.v:41387$943
61841     parameter \A_SIGNED 0
61842     parameter \A_WIDTH 7
61843     parameter \B_SIGNED 0
61844     parameter \B_WIDTH 7
61845     parameter \Y_WIDTH 1
61846     connect \A \internal_op
61847     connect \B 7'0101101
61848     connect \Y $eq$libresoc.v:41387$943_Y
61849   end
61850   attribute \module_not_derived 1
61851   attribute \src "libresoc.v:41389.9-41392.4"
61852   cell \ppick \ppick
61853     connect \i \ppick_i
61854     connect \o \ppick_o
61855   end
61856   attribute \src "libresoc.v:41244.7-41244.20"
61857   process $proc$libresoc.v:41244$955
61858     assign { } { }
61859     assign $0\initial[0:0] 1'0
61860     sync always
61861       update \initial $0\initial[0:0]
61862     sync init
61863   end
61864   attribute \src "libresoc.v:41393.3-41419.6"
61865   process $proc$libresoc.v:41393$945
61866     assign { } { }
61867     assign { } { }
61868     assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
61869     attribute \src "libresoc.v:41394.5-41394.29"
61870     switch \initial
61871       attribute \src "libresoc.v:41394.9-41394.17"
61872       case 1'1
61873       case
61874     end
61875     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
61876     switch \sel_in
61877       attribute \src "libresoc.v:0.0-0.0"
61878       case 3'001
61879         assign { } { }
61880         assign $1\cr_bitfield_ok[0:0] 1'1
61881       attribute \src "libresoc.v:0.0-0.0"
61882       case 3'010
61883         assign { } { }
61884         assign $1\cr_bitfield_ok[0:0] 1'1
61885       attribute \src "libresoc.v:0.0-0.0"
61886       case 3'011
61887         assign { } { }
61888         assign $1\cr_bitfield_ok[0:0] 1'1
61889       attribute \src "libresoc.v:0.0-0.0"
61890       case 3'100
61891         assign { } { }
61892         assign $1\cr_bitfield_ok[0:0] 1'1
61893       attribute \src "libresoc.v:0.0-0.0"
61894       case 3'101
61895         assign { } { }
61896         assign $1\cr_bitfield_ok[0:0] 1'1
61897       case
61898         assign $1\cr_bitfield_ok[0:0] 1'0
61899     end
61900     sync always
61901       update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
61902   end
61903   attribute \src "libresoc.v:41420.3-41430.6"
61904   process $proc$libresoc.v:41420$946
61905     assign { } { }
61906     assign { } { }
61907     assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0]
61908     attribute \src "libresoc.v:41421.5-41421.29"
61909     switch \initial
61910       attribute \src "libresoc.v:41421.9-41421.17"
61911       case 1'1
61912       case
61913     end
61914     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
61915     switch \sel_in
61916       attribute \src "libresoc.v:0.0-0.0"
61917       case 3'100
61918         assign { } { }
61919         assign $1\cr_bitfield_b_ok[0:0] 1'1
61920       case
61921         assign $1\cr_bitfield_b_ok[0:0] 1'0
61922     end
61923     sync always
61924       update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0]
61925   end
61926   attribute \src "libresoc.v:41431.3-41441.6"
61927   process $proc$libresoc.v:41431$947
61928     assign { } { }
61929     assign { } { }
61930     assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
61931     attribute \src "libresoc.v:41432.5-41432.29"
61932     switch \initial
61933       attribute \src "libresoc.v:41432.9-41432.17"
61934       case 1'1
61935       case
61936     end
61937     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
61938     switch \sel_in
61939       attribute \src "libresoc.v:0.0-0.0"
61940       case 3'110
61941         assign { } { }
61942         assign $1\cr_fxm_ok[0:0] 1'1
61943       case
61944         assign $1\cr_fxm_ok[0:0] 1'0
61945     end
61946     sync always
61947       update \cr_fxm_ok $0\cr_fxm_ok[0:0]
61948   end
61949   attribute \src "libresoc.v:41442.3-41468.6"
61950   process $proc$libresoc.v:41442$948
61951     assign { } { }
61952     assign { } { }
61953     assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
61954     attribute \src "libresoc.v:41443.5-41443.29"
61955     switch \initial
61956       attribute \src "libresoc.v:41443.9-41443.17"
61957       case 1'1
61958       case
61959     end
61960     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
61961     switch \sel_in
61962       attribute \src "libresoc.v:0.0-0.0"
61963       case 3'001
61964         assign { } { }
61965         assign $1\cr_bitfield[2:0] 3'000
61966       attribute \src "libresoc.v:0.0-0.0"
61967       case 3'010
61968         assign { } { }
61969         assign $1\cr_bitfield[2:0] \BI [4:2]
61970       attribute \src "libresoc.v:0.0-0.0"
61971       case 3'011
61972         assign { } { }
61973         assign $1\cr_bitfield[2:0] \X_BFA
61974       attribute \src "libresoc.v:0.0-0.0"
61975       case 3'100
61976         assign { } { }
61977         assign $1\cr_bitfield[2:0] \BA [4:2]
61978       attribute \src "libresoc.v:0.0-0.0"
61979       case 3'101
61980         assign { } { }
61981         assign $1\cr_bitfield[2:0] \BC [4:2]
61982       case
61983         assign $1\cr_bitfield[2:0] 3'000
61984     end
61985     sync always
61986       update \cr_bitfield $0\cr_bitfield[2:0]
61987   end
61988   attribute \src "libresoc.v:41469.3-41479.6"
61989   process $proc$libresoc.v:41469$949
61990     assign { } { }
61991     assign { } { }
61992     assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0]
61993     attribute \src "libresoc.v:41470.5-41470.29"
61994     switch \initial
61995       attribute \src "libresoc.v:41470.9-41470.17"
61996       case 1'1
61997       case
61998     end
61999     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
62000     switch \sel_in
62001       attribute \src "libresoc.v:0.0-0.0"
62002       case 3'100
62003         assign { } { }
62004         assign $1\cr_bitfield_b[2:0] \BB [4:2]
62005       case
62006         assign $1\cr_bitfield_b[2:0] 3'000
62007     end
62008     sync always
62009       update \cr_bitfield_b $0\cr_bitfield_b[2:0]
62010   end
62011   attribute \src "libresoc.v:41480.3-41490.6"
62012   process $proc$libresoc.v:41480$950
62013     assign { } { }
62014     assign { } { }
62015     assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0]
62016     attribute \src "libresoc.v:41481.5-41481.29"
62017     switch \initial
62018       attribute \src "libresoc.v:41481.9-41481.17"
62019       case 1'1
62020       case
62021     end
62022     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
62023     switch \sel_in
62024       attribute \src "libresoc.v:0.0-0.0"
62025       case 3'100
62026         assign { } { }
62027         assign $1\cr_bitfield_o[2:0] \BT [4:2]
62028       case
62029         assign $1\cr_bitfield_o[2:0] 3'000
62030     end
62031     sync always
62032       update \cr_bitfield_o $0\cr_bitfield_o[2:0]
62033   end
62034   attribute \src "libresoc.v:41491.3-41501.6"
62035   process $proc$libresoc.v:41491$951
62036     assign { } { }
62037     assign { } { }
62038     assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0]
62039     attribute \src "libresoc.v:41492.5-41492.29"
62040     switch \initial
62041       attribute \src "libresoc.v:41492.9-41492.17"
62042       case 1'1
62043       case
62044     end
62045     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
62046     switch \sel_in
62047       attribute \src "libresoc.v:0.0-0.0"
62048       case 3'100
62049         assign { } { }
62050         assign $1\cr_bitfield_o_ok[0:0] 1'1
62051       case
62052         assign $1\cr_bitfield_o_ok[0:0] 1'0
62053     end
62054     sync always
62055       update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0]
62056   end
62057   attribute \src "libresoc.v:41502.3-41512.6"
62058   process $proc$libresoc.v:41502$952
62059     assign { } { }
62060     assign { } { }
62061     assign $0\move_one[0:0] $1\move_one[0:0]
62062     attribute \src "libresoc.v:41503.5-41503.29"
62063     switch \initial
62064       attribute \src "libresoc.v:41503.9-41503.17"
62065       case 1'1
62066       case
62067     end
62068     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
62069     switch \sel_in
62070       attribute \src "libresoc.v:0.0-0.0"
62071       case 3'110
62072         assign { } { }
62073         assign $1\move_one[0:0] \insn_in [20]
62074       case
62075         assign $1\move_one[0:0] 1'0
62076     end
62077     sync always
62078       update \move_one $0\move_one[0:0]
62079   end
62080   attribute \src "libresoc.v:41513.3-41528.6"
62081   process $proc$libresoc.v:41513$953
62082     assign { } { }
62083     assign { } { }
62084     assign $0\ppick_i[7:0] $1\ppick_i[7:0]
62085     attribute \src "libresoc.v:41514.5-41514.29"
62086     switch \initial
62087       attribute \src "libresoc.v:41514.9-41514.17"
62088       case 1'1
62089       case
62090     end
62091     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
62092     switch \sel_in
62093       attribute \src "libresoc.v:0.0-0.0"
62094       case 3'110
62095         assign { } { }
62096         assign $1\ppick_i[7:0] $2\ppick_i[7:0]
62097         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
62098         switch \$3
62099           attribute \src "libresoc.v:0.0-0.0"
62100           case 1'1
62101             assign { } { }
62102             assign $2\ppick_i[7:0] \FXM
62103           case
62104             assign $2\ppick_i[7:0] 8'00000000
62105         end
62106       case
62107         assign $1\ppick_i[7:0] 8'00000000
62108     end
62109     sync always
62110       update \ppick_i $0\ppick_i[7:0]
62111   end
62112   attribute \src "libresoc.v:41529.3-41547.6"
62113   process $proc$libresoc.v:41529$954
62114     assign { } { }
62115     assign { } { }
62116     assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
62117     attribute \src "libresoc.v:41530.5-41530.29"
62118     switch \initial
62119       attribute \src "libresoc.v:41530.9-41530.17"
62120       case 1'1
62121       case
62122     end
62123     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506"
62124     switch \sel_in
62125       attribute \src "libresoc.v:0.0-0.0"
62126       case 3'110
62127         assign { } { }
62128         assign $1\cr_fxm[7:0] $2\cr_fxm[7:0]
62129         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
62130         switch \$7
62131           attribute \src "libresoc.v:0.0-0.0"
62132           case 1'1
62133             assign { } { }
62134             assign $2\cr_fxm[7:0] \ppick_o
62135           attribute \src "libresoc.v:0.0-0.0"
62136           case
62137             assign { } { }
62138             assign $2\cr_fxm[7:0] 8'11111111
62139         end
62140       case
62141         assign $1\cr_fxm[7:0] 8'00000000
62142     end
62143     sync always
62144       update \cr_fxm $0\cr_fxm[7:0]
62145   end
62146   connect \$1 $eq$libresoc.v:41385$941_Y
62147   connect \$3 $and$libresoc.v:41386$942_Y
62148   connect \$5 $eq$libresoc.v:41387$943_Y
62149   connect \$7 $and$libresoc.v:41388$944_Y
62150 end
62151 attribute \src "libresoc.v:41552.1-41795.10"
62152 attribute \cells_not_processed 1
62153 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out"
62154 attribute \generator "nMigen"
62155 module \dec_cr_out
62156   attribute \src "libresoc.v:41709.3-41727.6"
62157   wire width 3 $0\cr_bitfield[2:0]
62158   attribute \src "libresoc.v:41679.3-41697.6"
62159   wire $0\cr_bitfield_ok[0:0]
62160   attribute \src "libresoc.v:41760.3-41794.6"
62161   wire width 8 $0\cr_fxm[7:0]
62162   attribute \src "libresoc.v:41698.3-41708.6"
62163   wire $0\cr_fxm_ok[0:0]
62164   attribute \src "libresoc.v:41553.7-41553.20"
62165   wire $0\initial[0:0]
62166   attribute \src "libresoc.v:41728.3-41738.6"
62167   wire $0\move_one[0:0]
62168   attribute \src "libresoc.v:41739.3-41759.6"
62169   wire width 8 $0\ppick_i[7:0]
62170   attribute \src "libresoc.v:41709.3-41727.6"
62171   wire width 3 $1\cr_bitfield[2:0]
62172   attribute \src "libresoc.v:41679.3-41697.6"
62173   wire $1\cr_bitfield_ok[0:0]
62174   attribute \src "libresoc.v:41760.3-41794.6"
62175   wire width 8 $1\cr_fxm[7:0]
62176   attribute \src "libresoc.v:41698.3-41708.6"
62177   wire $1\cr_fxm_ok[0:0]
62178   attribute \src "libresoc.v:41728.3-41738.6"
62179   wire $1\move_one[0:0]
62180   attribute \src "libresoc.v:41739.3-41759.6"
62181   wire width 8 $1\ppick_i[7:0]
62182   attribute \src "libresoc.v:41760.3-41794.6"
62183   wire width 8 $2\cr_fxm[7:0]
62184   attribute \src "libresoc.v:41739.3-41759.6"
62185   wire width 8 $2\ppick_i[7:0]
62186   attribute \src "libresoc.v:41760.3-41794.6"
62187   wire width 8 $3\cr_fxm[7:0]
62188   attribute \src "libresoc.v:41739.3-41759.6"
62189   wire width 8 $3\ppick_i[7:0]
62190   attribute \src "libresoc.v:41760.3-41794.6"
62191   wire width 8 $4\cr_fxm[7:0]
62192   attribute \src "libresoc.v:41672.17-41672.117"
62193   wire $eq$libresoc.v:41672$956_Y
62194   attribute \src "libresoc.v:41673.17-41673.117"
62195   wire $eq$libresoc.v:41673$957_Y
62196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583"
62197   wire \$1
62198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583"
62199   wire \$3
62200   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
62201   wire width 8 input 8 \FXM
62202   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
62203   wire width 5 input 10 \XL_BT
62204   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463"
62205   wire width 3 input 9 \X_BF
62206   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62207   wire width 3 output 6 \cr_bitfield
62208   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62209   wire output 7 \cr_bitfield_ok
62210   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62211   wire width 8 output 4 \cr_fxm
62212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62213   wire output 5 \cr_fxm_ok
62214   attribute \src "libresoc.v:41553.7-41553.15"
62215   wire \initial
62216   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554"
62217   wire width 32 input 11 \insn_in
62218   attribute \enum_base_type "MicrOp"
62219   attribute \enum_value_0000000 "OP_ILLEGAL"
62220   attribute \enum_value_0000001 "OP_NOP"
62221   attribute \enum_value_0000010 "OP_ADD"
62222   attribute \enum_value_0000011 "OP_ADDPCIS"
62223   attribute \enum_value_0000100 "OP_AND"
62224   attribute \enum_value_0000101 "OP_ATTN"
62225   attribute \enum_value_0000110 "OP_B"
62226   attribute \enum_value_0000111 "OP_BC"
62227   attribute \enum_value_0001000 "OP_BCREG"
62228   attribute \enum_value_0001001 "OP_BPERM"
62229   attribute \enum_value_0001010 "OP_CMP"
62230   attribute \enum_value_0001011 "OP_CMPB"
62231   attribute \enum_value_0001100 "OP_CMPEQB"
62232   attribute \enum_value_0001101 "OP_CMPRB"
62233   attribute \enum_value_0001110 "OP_CNTZ"
62234   attribute \enum_value_0001111 "OP_CRAND"
62235   attribute \enum_value_0010000 "OP_CRANDC"
62236   attribute \enum_value_0010001 "OP_CREQV"
62237   attribute \enum_value_0010010 "OP_CRNAND"
62238   attribute \enum_value_0010011 "OP_CRNOR"
62239   attribute \enum_value_0010100 "OP_CROR"
62240   attribute \enum_value_0010101 "OP_CRORC"
62241   attribute \enum_value_0010110 "OP_CRXOR"
62242   attribute \enum_value_0010111 "OP_DARN"
62243   attribute \enum_value_0011000 "OP_DCBF"
62244   attribute \enum_value_0011001 "OP_DCBST"
62245   attribute \enum_value_0011010 "OP_DCBT"
62246   attribute \enum_value_0011011 "OP_DCBTST"
62247   attribute \enum_value_0011100 "OP_DCBZ"
62248   attribute \enum_value_0011101 "OP_DIV"
62249   attribute \enum_value_0011110 "OP_DIVE"
62250   attribute \enum_value_0011111 "OP_EXTS"
62251   attribute \enum_value_0100000 "OP_EXTSWSLI"
62252   attribute \enum_value_0100001 "OP_ICBI"
62253   attribute \enum_value_0100010 "OP_ICBT"
62254   attribute \enum_value_0100011 "OP_ISEL"
62255   attribute \enum_value_0100100 "OP_ISYNC"
62256   attribute \enum_value_0100101 "OP_LOAD"
62257   attribute \enum_value_0100110 "OP_STORE"
62258   attribute \enum_value_0100111 "OP_MADDHD"
62259   attribute \enum_value_0101000 "OP_MADDHDU"
62260   attribute \enum_value_0101001 "OP_MADDLD"
62261   attribute \enum_value_0101010 "OP_MCRF"
62262   attribute \enum_value_0101011 "OP_MCRXR"
62263   attribute \enum_value_0101100 "OP_MCRXRX"
62264   attribute \enum_value_0101101 "OP_MFCR"
62265   attribute \enum_value_0101110 "OP_MFSPR"
62266   attribute \enum_value_0101111 "OP_MOD"
62267   attribute \enum_value_0110000 "OP_MTCRF"
62268   attribute \enum_value_0110001 "OP_MTSPR"
62269   attribute \enum_value_0110010 "OP_MUL_L64"
62270   attribute \enum_value_0110011 "OP_MUL_H64"
62271   attribute \enum_value_0110100 "OP_MUL_H32"
62272   attribute \enum_value_0110101 "OP_OR"
62273   attribute \enum_value_0110110 "OP_POPCNT"
62274   attribute \enum_value_0110111 "OP_PRTY"
62275   attribute \enum_value_0111000 "OP_RLC"
62276   attribute \enum_value_0111001 "OP_RLCL"
62277   attribute \enum_value_0111010 "OP_RLCR"
62278   attribute \enum_value_0111011 "OP_SETB"
62279   attribute \enum_value_0111100 "OP_SHL"
62280   attribute \enum_value_0111101 "OP_SHR"
62281   attribute \enum_value_0111110 "OP_SYNC"
62282   attribute \enum_value_0111111 "OP_TRAP"
62283   attribute \enum_value_1000011 "OP_XOR"
62284   attribute \enum_value_1000100 "OP_SIM_CONFIG"
62285   attribute \enum_value_1000101 "OP_CROP"
62286   attribute \enum_value_1000110 "OP_RFID"
62287   attribute \enum_value_1000111 "OP_MFMSR"
62288   attribute \enum_value_1001000 "OP_MTMSRD"
62289   attribute \enum_value_1001001 "OP_SC"
62290   attribute \enum_value_1001010 "OP_MTMSR"
62291   attribute \enum_value_1001011 "OP_TLBIE"
62292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
62293   wire width 7 input 3 \internal_op
62294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581"
62295   wire \move_one
62296   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
62297   wire \ppick_en_o
62298   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40"
62299   wire width 8 \ppick_i
62300   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41"
62301   wire width 8 \ppick_o
62302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552"
62303   wire input 2 \rc_in
62304   attribute \enum_base_type "CROutSel"
62305   attribute \enum_value_000 "NONE"
62306   attribute \enum_value_001 "CR0"
62307   attribute \enum_value_010 "BF"
62308   attribute \enum_value_011 "BT"
62309   attribute \enum_value_100 "WHOLE_REG"
62310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553"
62311   wire width 3 input 1 \sel_in
62312   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583"
62313   cell $eq $eq$libresoc.v:41672$956
62314     parameter \A_SIGNED 0
62315     parameter \A_WIDTH 7
62316     parameter \B_SIGNED 0
62317     parameter \B_WIDTH 7
62318     parameter \Y_WIDTH 1
62319     connect \A \internal_op
62320     connect \B 7'0110000
62321     connect \Y $eq$libresoc.v:41672$956_Y
62322   end
62323   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583"
62324   cell $eq $eq$libresoc.v:41673$957
62325     parameter \A_SIGNED 0
62326     parameter \A_WIDTH 7
62327     parameter \B_SIGNED 0
62328     parameter \B_WIDTH 7
62329     parameter \Y_WIDTH 1
62330     connect \A \internal_op
62331     connect \B 7'0110000
62332     connect \Y $eq$libresoc.v:41673$957_Y
62333   end
62334   attribute \module_not_derived 1
62335   attribute \src "libresoc.v:41674.13-41678.4"
62336   cell \ppick$1 \ppick
62337     connect \en_o \ppick_en_o
62338     connect \i \ppick_i
62339     connect \o \ppick_o
62340   end
62341   attribute \src "libresoc.v:41553.7-41553.20"
62342   process $proc$libresoc.v:41553$964
62343     assign { } { }
62344     assign $0\initial[0:0] 1'0
62345     sync always
62346       update \initial $0\initial[0:0]
62347     sync init
62348   end
62349   attribute \src "libresoc.v:41679.3-41697.6"
62350   process $proc$libresoc.v:41679$958
62351     assign { } { }
62352     assign { } { }
62353     assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0]
62354     attribute \src "libresoc.v:41680.5-41680.29"
62355     switch \initial
62356       attribute \src "libresoc.v:41680.9-41680.17"
62357       case 1'1
62358       case
62359     end
62360     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567"
62361     switch \sel_in
62362       attribute \src "libresoc.v:0.0-0.0"
62363       case 3'001
62364         assign { } { }
62365         assign $1\cr_bitfield_ok[0:0] \rc_in
62366       attribute \src "libresoc.v:0.0-0.0"
62367       case 3'010
62368         assign { } { }
62369         assign $1\cr_bitfield_ok[0:0] 1'1
62370       attribute \src "libresoc.v:0.0-0.0"
62371       case 3'011
62372         assign { } { }
62373         assign $1\cr_bitfield_ok[0:0] 1'1
62374       case
62375         assign $1\cr_bitfield_ok[0:0] 1'0
62376     end
62377     sync always
62378       update \cr_bitfield_ok $0\cr_bitfield_ok[0:0]
62379   end
62380   attribute \src "libresoc.v:41698.3-41708.6"
62381   process $proc$libresoc.v:41698$959
62382     assign { } { }
62383     assign { } { }
62384     assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0]
62385     attribute \src "libresoc.v:41699.5-41699.29"
62386     switch \initial
62387       attribute \src "libresoc.v:41699.9-41699.17"
62388       case 1'1
62389       case
62390     end
62391     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567"
62392     switch \sel_in
62393       attribute \src "libresoc.v:0.0-0.0"
62394       case 3'100
62395         assign { } { }
62396         assign $1\cr_fxm_ok[0:0] 1'1
62397       case
62398         assign $1\cr_fxm_ok[0:0] 1'0
62399     end
62400     sync always
62401       update \cr_fxm_ok $0\cr_fxm_ok[0:0]
62402   end
62403   attribute \src "libresoc.v:41709.3-41727.6"
62404   process $proc$libresoc.v:41709$960
62405     assign { } { }
62406     assign { } { }
62407     assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0]
62408     attribute \src "libresoc.v:41710.5-41710.29"
62409     switch \initial
62410       attribute \src "libresoc.v:41710.9-41710.17"
62411       case 1'1
62412       case
62413     end
62414     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567"
62415     switch \sel_in
62416       attribute \src "libresoc.v:0.0-0.0"
62417       case 3'001
62418         assign { } { }
62419         assign $1\cr_bitfield[2:0] 3'000
62420       attribute \src "libresoc.v:0.0-0.0"
62421       case 3'010
62422         assign { } { }
62423         assign $1\cr_bitfield[2:0] \X_BF
62424       attribute \src "libresoc.v:0.0-0.0"
62425       case 3'011
62426         assign { } { }
62427         assign $1\cr_bitfield[2:0] \XL_BT [4:2]
62428       case
62429         assign $1\cr_bitfield[2:0] 3'000
62430     end
62431     sync always
62432       update \cr_bitfield $0\cr_bitfield[2:0]
62433   end
62434   attribute \src "libresoc.v:41728.3-41738.6"
62435   process $proc$libresoc.v:41728$961
62436     assign { } { }
62437     assign { } { }
62438     assign $0\move_one[0:0] $1\move_one[0:0]
62439     attribute \src "libresoc.v:41729.5-41729.29"
62440     switch \initial
62441       attribute \src "libresoc.v:41729.9-41729.17"
62442       case 1'1
62443       case
62444     end
62445     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567"
62446     switch \sel_in
62447       attribute \src "libresoc.v:0.0-0.0"
62448       case 3'100
62449         assign { } { }
62450         assign $1\move_one[0:0] \insn_in [20]
62451       case
62452         assign $1\move_one[0:0] 1'0
62453     end
62454     sync always
62455       update \move_one $0\move_one[0:0]
62456   end
62457   attribute \src "libresoc.v:41739.3-41759.6"
62458   process $proc$libresoc.v:41739$962
62459     assign { } { }
62460     assign { } { }
62461     assign $0\ppick_i[7:0] $1\ppick_i[7:0]
62462     attribute \src "libresoc.v:41740.5-41740.29"
62463     switch \initial
62464       attribute \src "libresoc.v:41740.9-41740.17"
62465       case 1'1
62466       case
62467     end
62468     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567"
62469     switch \sel_in
62470       attribute \src "libresoc.v:0.0-0.0"
62471       case 3'100
62472         assign { } { }
62473         assign $1\ppick_i[7:0] $2\ppick_i[7:0]
62474         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583"
62475         switch \$1
62476           attribute \src "libresoc.v:0.0-0.0"
62477           case 1'1
62478             assign { } { }
62479             assign $2\ppick_i[7:0] $3\ppick_i[7:0]
62480             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584"
62481             switch \move_one
62482               attribute \src "libresoc.v:0.0-0.0"
62483               case 1'1
62484                 assign { } { }
62485                 assign $3\ppick_i[7:0] \FXM
62486               case
62487                 assign $3\ppick_i[7:0] 8'00000000
62488             end
62489           case
62490             assign $2\ppick_i[7:0] 8'00000000
62491         end
62492       case
62493         assign $1\ppick_i[7:0] 8'00000000
62494     end
62495     sync always
62496       update \ppick_i $0\ppick_i[7:0]
62497   end
62498   attribute \src "libresoc.v:41760.3-41794.6"
62499   process $proc$libresoc.v:41760$963
62500     assign { } { }
62501     assign { } { }
62502     assign $0\cr_fxm[7:0] $1\cr_fxm[7:0]
62503     attribute \src "libresoc.v:41761.5-41761.29"
62504     switch \initial
62505       attribute \src "libresoc.v:41761.9-41761.17"
62506       case 1'1
62507       case
62508     end
62509     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567"
62510     switch \sel_in
62511       attribute \src "libresoc.v:0.0-0.0"
62512       case 3'100
62513         assign { } { }
62514         assign $1\cr_fxm[7:0] $2\cr_fxm[7:0]
62515         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583"
62516         switch \$3
62517           attribute \src "libresoc.v:0.0-0.0"
62518           case 1'1
62519             assign { } { }
62520             assign $2\cr_fxm[7:0] $3\cr_fxm[7:0]
62521             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584"
62522             switch \move_one
62523               attribute \src "libresoc.v:0.0-0.0"
62524               case 1'1
62525                 assign { } { }
62526                 assign $3\cr_fxm[7:0] $4\cr_fxm[7:0]
62527                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587"
62528                 switch \ppick_en_o
62529                   attribute \src "libresoc.v:0.0-0.0"
62530                   case 1'1
62531                     assign { } { }
62532                     assign $4\cr_fxm[7:0] \ppick_o
62533                   attribute \src "libresoc.v:0.0-0.0"
62534                   case
62535                     assign { } { }
62536                     assign $4\cr_fxm[7:0] 8'00000001
62537                 end
62538               attribute \src "libresoc.v:0.0-0.0"
62539               case
62540                 assign { } { }
62541                 assign $3\cr_fxm[7:0] \FXM
62542             end
62543           attribute \src "libresoc.v:0.0-0.0"
62544           case
62545             assign { } { }
62546             assign $2\cr_fxm[7:0] 8'11111111
62547         end
62548       case
62549         assign $1\cr_fxm[7:0] 8'00000000
62550     end
62551     sync always
62552       update \cr_fxm $0\cr_fxm[7:0]
62553   end
62554   connect \$1 $eq$libresoc.v:41672$956_Y
62555   connect \$3 $eq$libresoc.v:41673$957_Y
62556 end
62557 attribute \src "libresoc.v:41799.1-42276.10"
62558 attribute \cells_not_processed 1
62559 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o"
62560 attribute \generator "nMigen"
62561 module \dec_o
62562   attribute \src "libresoc.v:42237.3-42275.6"
62563   wire width 3 $0\fast_o[2:0]
62564   attribute \src "libresoc.v:42237.3-42275.6"
62565   wire $0\fast_o_ok[0:0]
62566   attribute \src "libresoc.v:41800.7-41800.20"
62567   wire $0\initial[0:0]
62568   attribute \src "libresoc.v:42163.3-42177.6"
62569   wire width 5 $0\reg_o[4:0]
62570   attribute \src "libresoc.v:42178.3-42192.6"
62571   wire $0\reg_o_ok[0:0]
62572   attribute \src "libresoc.v:42193.3-42203.6"
62573   wire width 10 $0\spr[9:0]
62574   attribute \src "libresoc.v:42220.3-42236.6"
62575   wire width 10 $0\spr_o[9:0]
62576   attribute \src "libresoc.v:42220.3-42236.6"
62577   wire $0\spr_o_ok[0:0]
62578   attribute \src "libresoc.v:42204.3-42219.6"
62579   wire width 10 $0\sprmap_spr_i[9:0]
62580   attribute \src "libresoc.v:42237.3-42275.6"
62581   wire width 3 $1\fast_o[2:0]
62582   attribute \src "libresoc.v:42237.3-42275.6"
62583   wire $1\fast_o_ok[0:0]
62584   attribute \src "libresoc.v:42163.3-42177.6"
62585   wire width 5 $1\reg_o[4:0]
62586   attribute \src "libresoc.v:42178.3-42192.6"
62587   wire $1\reg_o_ok[0:0]
62588   attribute \src "libresoc.v:42193.3-42203.6"
62589   wire width 10 $1\spr[9:0]
62590   attribute \src "libresoc.v:42220.3-42236.6"
62591   wire width 10 $1\spr_o[9:0]
62592   attribute \src "libresoc.v:42220.3-42236.6"
62593   wire $1\spr_o_ok[0:0]
62594   attribute \src "libresoc.v:42204.3-42219.6"
62595   wire width 10 $1\sprmap_spr_i[9:0]
62596   attribute \src "libresoc.v:42237.3-42275.6"
62597   wire width 3 $2\fast_o[2:0]
62598   attribute \src "libresoc.v:42237.3-42275.6"
62599   wire $2\fast_o_ok[0:0]
62600   attribute \src "libresoc.v:42220.3-42236.6"
62601   wire width 10 $2\spr_o[9:0]
62602   attribute \src "libresoc.v:42220.3-42236.6"
62603   wire $2\spr_o_ok[0:0]
62604   attribute \src "libresoc.v:42204.3-42219.6"
62605   wire width 10 $2\sprmap_spr_i[9:0]
62606   attribute \src "libresoc.v:42237.3-42275.6"
62607   wire width 3 $3\fast_o[2:0]
62608   attribute \src "libresoc.v:42237.3-42275.6"
62609   wire $3\fast_o_ok[0:0]
62610   attribute \src "libresoc.v:42237.3-42275.6"
62611   wire width 3 $4\fast_o[2:0]
62612   attribute \src "libresoc.v:42237.3-42275.6"
62613   wire $4\fast_o_ok[0:0]
62614   attribute \src "libresoc.v:42152.17-42152.117"
62615   wire $eq$libresoc.v:42152$965_Y
62616   attribute \src "libresoc.v:42153.17-42153.117"
62617   wire $eq$libresoc.v:42153$966_Y
62618   attribute \src "libresoc.v:42154.17-42154.117"
62619   wire $eq$libresoc.v:42154$967_Y
62620   attribute \src "libresoc.v:42155.17-42155.104"
62621   wire $not$libresoc.v:42155$968_Y
62622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
62623   wire \$1
62624   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
62625   wire \$3
62626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
62627   wire \$5
62628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
62629   wire \$7
62630   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
62631   wire width 5 input 10 \BO
62632   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
62633   wire width 5 input 9 \RA
62634   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
62635   wire width 5 input 8 \RT
62636   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
62637   wire width 10 input 11 \SPR
62638   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62639   wire width 3 output 6 \fast_o
62640   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62641   wire output 7 \fast_o_ok
62642   attribute \src "libresoc.v:41800.7-41800.15"
62643   wire \initial
62644   attribute \enum_base_type "MicrOp"
62645   attribute \enum_value_0000000 "OP_ILLEGAL"
62646   attribute \enum_value_0000001 "OP_NOP"
62647   attribute \enum_value_0000010 "OP_ADD"
62648   attribute \enum_value_0000011 "OP_ADDPCIS"
62649   attribute \enum_value_0000100 "OP_AND"
62650   attribute \enum_value_0000101 "OP_ATTN"
62651   attribute \enum_value_0000110 "OP_B"
62652   attribute \enum_value_0000111 "OP_BC"
62653   attribute \enum_value_0001000 "OP_BCREG"
62654   attribute \enum_value_0001001 "OP_BPERM"
62655   attribute \enum_value_0001010 "OP_CMP"
62656   attribute \enum_value_0001011 "OP_CMPB"
62657   attribute \enum_value_0001100 "OP_CMPEQB"
62658   attribute \enum_value_0001101 "OP_CMPRB"
62659   attribute \enum_value_0001110 "OP_CNTZ"
62660   attribute \enum_value_0001111 "OP_CRAND"
62661   attribute \enum_value_0010000 "OP_CRANDC"
62662   attribute \enum_value_0010001 "OP_CREQV"
62663   attribute \enum_value_0010010 "OP_CRNAND"
62664   attribute \enum_value_0010011 "OP_CRNOR"
62665   attribute \enum_value_0010100 "OP_CROR"
62666   attribute \enum_value_0010101 "OP_CRORC"
62667   attribute \enum_value_0010110 "OP_CRXOR"
62668   attribute \enum_value_0010111 "OP_DARN"
62669   attribute \enum_value_0011000 "OP_DCBF"
62670   attribute \enum_value_0011001 "OP_DCBST"
62671   attribute \enum_value_0011010 "OP_DCBT"
62672   attribute \enum_value_0011011 "OP_DCBTST"
62673   attribute \enum_value_0011100 "OP_DCBZ"
62674   attribute \enum_value_0011101 "OP_DIV"
62675   attribute \enum_value_0011110 "OP_DIVE"
62676   attribute \enum_value_0011111 "OP_EXTS"
62677   attribute \enum_value_0100000 "OP_EXTSWSLI"
62678   attribute \enum_value_0100001 "OP_ICBI"
62679   attribute \enum_value_0100010 "OP_ICBT"
62680   attribute \enum_value_0100011 "OP_ISEL"
62681   attribute \enum_value_0100100 "OP_ISYNC"
62682   attribute \enum_value_0100101 "OP_LOAD"
62683   attribute \enum_value_0100110 "OP_STORE"
62684   attribute \enum_value_0100111 "OP_MADDHD"
62685   attribute \enum_value_0101000 "OP_MADDHDU"
62686   attribute \enum_value_0101001 "OP_MADDLD"
62687   attribute \enum_value_0101010 "OP_MCRF"
62688   attribute \enum_value_0101011 "OP_MCRXR"
62689   attribute \enum_value_0101100 "OP_MCRXRX"
62690   attribute \enum_value_0101101 "OP_MFCR"
62691   attribute \enum_value_0101110 "OP_MFSPR"
62692   attribute \enum_value_0101111 "OP_MOD"
62693   attribute \enum_value_0110000 "OP_MTCRF"
62694   attribute \enum_value_0110001 "OP_MTSPR"
62695   attribute \enum_value_0110010 "OP_MUL_L64"
62696   attribute \enum_value_0110011 "OP_MUL_H64"
62697   attribute \enum_value_0110100 "OP_MUL_H32"
62698   attribute \enum_value_0110101 "OP_OR"
62699   attribute \enum_value_0110110 "OP_POPCNT"
62700   attribute \enum_value_0110111 "OP_PRTY"
62701   attribute \enum_value_0111000 "OP_RLC"
62702   attribute \enum_value_0111001 "OP_RLCL"
62703   attribute \enum_value_0111010 "OP_RLCR"
62704   attribute \enum_value_0111011 "OP_SETB"
62705   attribute \enum_value_0111100 "OP_SHL"
62706   attribute \enum_value_0111101 "OP_SHR"
62707   attribute \enum_value_0111110 "OP_SYNC"
62708   attribute \enum_value_0111111 "OP_TRAP"
62709   attribute \enum_value_1000011 "OP_XOR"
62710   attribute \enum_value_1000100 "OP_SIM_CONFIG"
62711   attribute \enum_value_1000101 "OP_CROP"
62712   attribute \enum_value_1000110 "OP_RFID"
62713   attribute \enum_value_1000111 "OP_MFMSR"
62714   attribute \enum_value_1001000 "OP_MTMSRD"
62715   attribute \enum_value_1001001 "OP_SC"
62716   attribute \enum_value_1001010 "OP_MTMSR"
62717   attribute \enum_value_1001011 "OP_TLBIE"
62718   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
62719   wire width 7 input 12 \internal_op
62720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62721   wire width 5 output 2 \reg_o
62722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62723   wire output 3 \reg_o_ok
62724   attribute \enum_base_type "OutSel"
62725   attribute \enum_value_00 "NONE"
62726   attribute \enum_value_01 "RT"
62727   attribute \enum_value_10 "RA"
62728   attribute \enum_value_11 "SPR"
62729   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
62730   wire width 2 input 1 \sel_in
62731   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
62732   wire width 10 \spr
62733   attribute \enum_base_type "SPR"
62734   attribute \enum_value_0000000001 "XER"
62735   attribute \enum_value_0000000011 "DSCR"
62736   attribute \enum_value_0000001000 "LR"
62737   attribute \enum_value_0000001001 "CTR"
62738   attribute \enum_value_0000001101 "AMR"
62739   attribute \enum_value_0000010001 "DSCR_priv"
62740   attribute \enum_value_0000010010 "DSISR"
62741   attribute \enum_value_0000010011 "DAR"
62742   attribute \enum_value_0000010110 "DEC"
62743   attribute \enum_value_0000011010 "SRR0"
62744   attribute \enum_value_0000011011 "SRR1"
62745   attribute \enum_value_0000011100 "CFAR"
62746   attribute \enum_value_0000011101 "AMR_priv"
62747   attribute \enum_value_0000110000 "PIDR"
62748   attribute \enum_value_0000111101 "IAMR"
62749   attribute \enum_value_0010000000 "TFHAR"
62750   attribute \enum_value_0010000001 "TFIAR"
62751   attribute \enum_value_0010000010 "TEXASR"
62752   attribute \enum_value_0010000011 "TEXASRU"
62753   attribute \enum_value_0010001000 "CTRL"
62754   attribute \enum_value_0010010000 "TIDR"
62755   attribute \enum_value_0010011000 "CTRL_priv"
62756   attribute \enum_value_0010011001 "FSCR"
62757   attribute \enum_value_0010011101 "UAMOR"
62758   attribute \enum_value_0010011110 "GSR"
62759   attribute \enum_value_0010011111 "PSPB"
62760   attribute \enum_value_0010110000 "DPDES"
62761   attribute \enum_value_0010110100 "DAWR0"
62762   attribute \enum_value_0010111010 "RPR"
62763   attribute \enum_value_0010111011 "CIABR"
62764   attribute \enum_value_0010111100 "DAWRX0"
62765   attribute \enum_value_0010111110 "HFSCR"
62766   attribute \enum_value_0100000000 "VRSAVE"
62767   attribute \enum_value_0100000011 "SPRG3"
62768   attribute \enum_value_0100001100 "TB"
62769   attribute \enum_value_0100001101 "TBU"
62770   attribute \enum_value_0100010000 "SPRG0_priv"
62771   attribute \enum_value_0100010001 "SPRG1_priv"
62772   attribute \enum_value_0100010010 "SPRG2_priv"
62773   attribute \enum_value_0100010011 "SPRG3_priv"
62774   attribute \enum_value_0100011011 "CIR"
62775   attribute \enum_value_0100011100 "TBL"
62776   attribute \enum_value_0100011101 "TBU_hypv"
62777   attribute \enum_value_0100011110 "TBU40"
62778   attribute \enum_value_0100011111 "PVR"
62779   attribute \enum_value_0100110000 "HSPRG0"
62780   attribute \enum_value_0100110001 "HSPRG1"
62781   attribute \enum_value_0100110010 "HDSISR"
62782   attribute \enum_value_0100110011 "HDAR"
62783   attribute \enum_value_0100110100 "SPURR"
62784   attribute \enum_value_0100110101 "PURR"
62785   attribute \enum_value_0100110110 "HDEC"
62786   attribute \enum_value_0100111001 "HRMOR"
62787   attribute \enum_value_0100111010 "HSRR0"
62788   attribute \enum_value_0100111011 "HSRR1"
62789   attribute \enum_value_0100111110 "LPCR"
62790   attribute \enum_value_0100111111 "LPIDR"
62791   attribute \enum_value_0101010000 "HMER"
62792   attribute \enum_value_0101010001 "HMEER"
62793   attribute \enum_value_0101010010 "PCR"
62794   attribute \enum_value_0101010011 "HEIR"
62795   attribute \enum_value_0101011101 "AMOR"
62796   attribute \enum_value_0110111110 "TIR"
62797   attribute \enum_value_0111010000 "PTCR"
62798   attribute \enum_value_1100000000 "SIER"
62799   attribute \enum_value_1100000001 "MMCR2"
62800   attribute \enum_value_1100000010 "MMCRA"
62801   attribute \enum_value_1100000011 "PMC1"
62802   attribute \enum_value_1100000100 "PMC2"
62803   attribute \enum_value_1100000101 "PMC3"
62804   attribute \enum_value_1100000110 "PMC4"
62805   attribute \enum_value_1100000111 "PMC5"
62806   attribute \enum_value_1100001000 "PMC6"
62807   attribute \enum_value_1100001011 "MMCR0"
62808   attribute \enum_value_1100001100 "SIAR"
62809   attribute \enum_value_1100001101 "SDAR"
62810   attribute \enum_value_1100001110 "MMCR1"
62811   attribute \enum_value_1100010000 "SIER_priv"
62812   attribute \enum_value_1100010001 "MMCR2_priv"
62813   attribute \enum_value_1100010010 "MMCRA_priv"
62814   attribute \enum_value_1100010011 "PMC1_priv"
62815   attribute \enum_value_1100010100 "PMC2_priv"
62816   attribute \enum_value_1100010101 "PMC3_priv"
62817   attribute \enum_value_1100010110 "PMC4_priv"
62818   attribute \enum_value_1100010111 "PMC5_priv"
62819   attribute \enum_value_1100011000 "PMC6_priv"
62820   attribute \enum_value_1100011011 "MMCR0_priv"
62821   attribute \enum_value_1100011100 "SIAR_priv"
62822   attribute \enum_value_1100011101 "SDAR_priv"
62823   attribute \enum_value_1100011110 "MMCR1_priv"
62824   attribute \enum_value_1100100000 "BESCRS"
62825   attribute \enum_value_1100100001 "BESCRSU"
62826   attribute \enum_value_1100100010 "BESCRR"
62827   attribute \enum_value_1100100011 "BESCRRU"
62828   attribute \enum_value_1100100100 "EBBHR"
62829   attribute \enum_value_1100100101 "EBBRR"
62830   attribute \enum_value_1100100110 "BESCR"
62831   attribute \enum_value_1100101000 "reserved808"
62832   attribute \enum_value_1100101001 "reserved809"
62833   attribute \enum_value_1100101010 "reserved810"
62834   attribute \enum_value_1100101011 "reserved811"
62835   attribute \enum_value_1100101111 "TAR"
62836   attribute \enum_value_1100110000 "ASDR"
62837   attribute \enum_value_1100110111 "PSSCR"
62838   attribute \enum_value_1101010000 "IC"
62839   attribute \enum_value_1101010001 "VTB"
62840   attribute \enum_value_1101010111 "PSSCR_hypv"
62841   attribute \enum_value_1110000000 "PPR"
62842   attribute \enum_value_1110000010 "PPR32"
62843   attribute \enum_value_1111111111 "PIR"
62844   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62845   wire width 10 output 4 \spr_o
62846   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62847   wire output 5 \spr_o_ok
62848   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62849   wire width 3 \sprmap_fast_o
62850   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62851   wire \sprmap_fast_o_ok
62852   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
62853   wire width 10 \sprmap_spr_i
62854   attribute \enum_base_type "SPR"
62855   attribute \enum_value_0000000001 "XER"
62856   attribute \enum_value_0000000011 "DSCR"
62857   attribute \enum_value_0000001000 "LR"
62858   attribute \enum_value_0000001001 "CTR"
62859   attribute \enum_value_0000001101 "AMR"
62860   attribute \enum_value_0000010001 "DSCR_priv"
62861   attribute \enum_value_0000010010 "DSISR"
62862   attribute \enum_value_0000010011 "DAR"
62863   attribute \enum_value_0000010110 "DEC"
62864   attribute \enum_value_0000011010 "SRR0"
62865   attribute \enum_value_0000011011 "SRR1"
62866   attribute \enum_value_0000011100 "CFAR"
62867   attribute \enum_value_0000011101 "AMR_priv"
62868   attribute \enum_value_0000110000 "PIDR"
62869   attribute \enum_value_0000111101 "IAMR"
62870   attribute \enum_value_0010000000 "TFHAR"
62871   attribute \enum_value_0010000001 "TFIAR"
62872   attribute \enum_value_0010000010 "TEXASR"
62873   attribute \enum_value_0010000011 "TEXASRU"
62874   attribute \enum_value_0010001000 "CTRL"
62875   attribute \enum_value_0010010000 "TIDR"
62876   attribute \enum_value_0010011000 "CTRL_priv"
62877   attribute \enum_value_0010011001 "FSCR"
62878   attribute \enum_value_0010011101 "UAMOR"
62879   attribute \enum_value_0010011110 "GSR"
62880   attribute \enum_value_0010011111 "PSPB"
62881   attribute \enum_value_0010110000 "DPDES"
62882   attribute \enum_value_0010110100 "DAWR0"
62883   attribute \enum_value_0010111010 "RPR"
62884   attribute \enum_value_0010111011 "CIABR"
62885   attribute \enum_value_0010111100 "DAWRX0"
62886   attribute \enum_value_0010111110 "HFSCR"
62887   attribute \enum_value_0100000000 "VRSAVE"
62888   attribute \enum_value_0100000011 "SPRG3"
62889   attribute \enum_value_0100001100 "TB"
62890   attribute \enum_value_0100001101 "TBU"
62891   attribute \enum_value_0100010000 "SPRG0_priv"
62892   attribute \enum_value_0100010001 "SPRG1_priv"
62893   attribute \enum_value_0100010010 "SPRG2_priv"
62894   attribute \enum_value_0100010011 "SPRG3_priv"
62895   attribute \enum_value_0100011011 "CIR"
62896   attribute \enum_value_0100011100 "TBL"
62897   attribute \enum_value_0100011101 "TBU_hypv"
62898   attribute \enum_value_0100011110 "TBU40"
62899   attribute \enum_value_0100011111 "PVR"
62900   attribute \enum_value_0100110000 "HSPRG0"
62901   attribute \enum_value_0100110001 "HSPRG1"
62902   attribute \enum_value_0100110010 "HDSISR"
62903   attribute \enum_value_0100110011 "HDAR"
62904   attribute \enum_value_0100110100 "SPURR"
62905   attribute \enum_value_0100110101 "PURR"
62906   attribute \enum_value_0100110110 "HDEC"
62907   attribute \enum_value_0100111001 "HRMOR"
62908   attribute \enum_value_0100111010 "HSRR0"
62909   attribute \enum_value_0100111011 "HSRR1"
62910   attribute \enum_value_0100111110 "LPCR"
62911   attribute \enum_value_0100111111 "LPIDR"
62912   attribute \enum_value_0101010000 "HMER"
62913   attribute \enum_value_0101010001 "HMEER"
62914   attribute \enum_value_0101010010 "PCR"
62915   attribute \enum_value_0101010011 "HEIR"
62916   attribute \enum_value_0101011101 "AMOR"
62917   attribute \enum_value_0110111110 "TIR"
62918   attribute \enum_value_0111010000 "PTCR"
62919   attribute \enum_value_1100000000 "SIER"
62920   attribute \enum_value_1100000001 "MMCR2"
62921   attribute \enum_value_1100000010 "MMCRA"
62922   attribute \enum_value_1100000011 "PMC1"
62923   attribute \enum_value_1100000100 "PMC2"
62924   attribute \enum_value_1100000101 "PMC3"
62925   attribute \enum_value_1100000110 "PMC4"
62926   attribute \enum_value_1100000111 "PMC5"
62927   attribute \enum_value_1100001000 "PMC6"
62928   attribute \enum_value_1100001011 "MMCR0"
62929   attribute \enum_value_1100001100 "SIAR"
62930   attribute \enum_value_1100001101 "SDAR"
62931   attribute \enum_value_1100001110 "MMCR1"
62932   attribute \enum_value_1100010000 "SIER_priv"
62933   attribute \enum_value_1100010001 "MMCR2_priv"
62934   attribute \enum_value_1100010010 "MMCRA_priv"
62935   attribute \enum_value_1100010011 "PMC1_priv"
62936   attribute \enum_value_1100010100 "PMC2_priv"
62937   attribute \enum_value_1100010101 "PMC3_priv"
62938   attribute \enum_value_1100010110 "PMC4_priv"
62939   attribute \enum_value_1100010111 "PMC5_priv"
62940   attribute \enum_value_1100011000 "PMC6_priv"
62941   attribute \enum_value_1100011011 "MMCR0_priv"
62942   attribute \enum_value_1100011100 "SIAR_priv"
62943   attribute \enum_value_1100011101 "SDAR_priv"
62944   attribute \enum_value_1100011110 "MMCR1_priv"
62945   attribute \enum_value_1100100000 "BESCRS"
62946   attribute \enum_value_1100100001 "BESCRSU"
62947   attribute \enum_value_1100100010 "BESCRR"
62948   attribute \enum_value_1100100011 "BESCRRU"
62949   attribute \enum_value_1100100100 "EBBHR"
62950   attribute \enum_value_1100100101 "EBBRR"
62951   attribute \enum_value_1100100110 "BESCR"
62952   attribute \enum_value_1100101000 "reserved808"
62953   attribute \enum_value_1100101001 "reserved809"
62954   attribute \enum_value_1100101010 "reserved810"
62955   attribute \enum_value_1100101011 "reserved811"
62956   attribute \enum_value_1100101111 "TAR"
62957   attribute \enum_value_1100110000 "ASDR"
62958   attribute \enum_value_1100110111 "PSSCR"
62959   attribute \enum_value_1101010000 "IC"
62960   attribute \enum_value_1101010001 "VTB"
62961   attribute \enum_value_1101010111 "PSSCR_hypv"
62962   attribute \enum_value_1110000000 "PPR"
62963   attribute \enum_value_1110000010 "PPR32"
62964   attribute \enum_value_1111111111 "PIR"
62965   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62966   wire width 10 \sprmap_spr_o
62967   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
62968   wire \sprmap_spr_o_ok
62969   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
62970   cell $eq $eq$libresoc.v:42152$965
62971     parameter \A_SIGNED 0
62972     parameter \A_WIDTH 7
62973     parameter \B_SIGNED 0
62974     parameter \B_WIDTH 7
62975     parameter \Y_WIDTH 1
62976     connect \A \internal_op
62977     connect \B 7'0110001
62978     connect \Y $eq$libresoc.v:42152$965_Y
62979   end
62980   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
62981   cell $eq $eq$libresoc.v:42153$966
62982     parameter \A_SIGNED 0
62983     parameter \A_WIDTH 7
62984     parameter \B_SIGNED 0
62985     parameter \B_WIDTH 7
62986     parameter \Y_WIDTH 1
62987     connect \A \internal_op
62988     connect \B 7'0110001
62989     connect \Y $eq$libresoc.v:42153$966_Y
62990   end
62991   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
62992   cell $eq $eq$libresoc.v:42154$967
62993     parameter \A_SIGNED 0
62994     parameter \A_WIDTH 7
62995     parameter \B_SIGNED 0
62996     parameter \B_WIDTH 7
62997     parameter \Y_WIDTH 1
62998     connect \A \internal_op
62999     connect \B 7'0110001
63000     connect \Y $eq$libresoc.v:42154$967_Y
63001   end
63002   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
63003   cell $not $not$libresoc.v:42155$968
63004     parameter \A_SIGNED 0
63005     parameter \A_WIDTH 1
63006     parameter \Y_WIDTH 1
63007     connect \A \BO [2]
63008     connect \Y $not$libresoc.v:42155$968_Y
63009   end
63010   attribute \module_not_derived 1
63011   attribute \src "libresoc.v:42156.14-42162.4"
63012   cell \sprmap$2 \sprmap
63013     connect \fast_o \sprmap_fast_o
63014     connect \fast_o_ok \sprmap_fast_o_ok
63015     connect \spr_i \sprmap_spr_i
63016     connect \spr_o \sprmap_spr_o
63017     connect \spr_o_ok \sprmap_spr_o_ok
63018   end
63019   attribute \src "libresoc.v:41800.7-41800.20"
63020   process $proc$libresoc.v:41800$975
63021     assign { } { }
63022     assign $0\initial[0:0] 1'0
63023     sync always
63024       update \initial $0\initial[0:0]
63025     sync init
63026   end
63027   attribute \src "libresoc.v:42163.3-42177.6"
63028   process $proc$libresoc.v:42163$969
63029     assign { } { }
63030     assign { } { }
63031     assign $0\reg_o[4:0] $1\reg_o[4:0]
63032     attribute \src "libresoc.v:42164.5-42164.29"
63033     switch \initial
63034       attribute \src "libresoc.v:42164.9-42164.17"
63035       case 1'1
63036       case
63037     end
63038     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324"
63039     switch \sel_in
63040       attribute \src "libresoc.v:0.0-0.0"
63041       case 2'01
63042         assign { } { }
63043         assign $1\reg_o[4:0] \RT
63044       attribute \src "libresoc.v:0.0-0.0"
63045       case 2'10
63046         assign { } { }
63047         assign $1\reg_o[4:0] \RA
63048       case
63049         assign $1\reg_o[4:0] 5'00000
63050     end
63051     sync always
63052       update \reg_o $0\reg_o[4:0]
63053   end
63054   attribute \src "libresoc.v:42178.3-42192.6"
63055   process $proc$libresoc.v:42178$970
63056     assign { } { }
63057     assign { } { }
63058     assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0]
63059     attribute \src "libresoc.v:42179.5-42179.29"
63060     switch \initial
63061       attribute \src "libresoc.v:42179.9-42179.17"
63062       case 1'1
63063       case
63064     end
63065     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324"
63066     switch \sel_in
63067       attribute \src "libresoc.v:0.0-0.0"
63068       case 2'01
63069         assign { } { }
63070         assign $1\reg_o_ok[0:0] 1'1
63071       attribute \src "libresoc.v:0.0-0.0"
63072       case 2'10
63073         assign { } { }
63074         assign $1\reg_o_ok[0:0] 1'1
63075       case
63076         assign $1\reg_o_ok[0:0] 1'0
63077     end
63078     sync always
63079       update \reg_o_ok $0\reg_o_ok[0:0]
63080   end
63081   attribute \src "libresoc.v:42193.3-42203.6"
63082   process $proc$libresoc.v:42193$971
63083     assign { } { }
63084     assign { } { }
63085     assign $0\spr[9:0] $1\spr[9:0]
63086     attribute \src "libresoc.v:42194.5-42194.29"
63087     switch \initial
63088       attribute \src "libresoc.v:42194.9-42194.17"
63089       case 1'1
63090       case
63091     end
63092     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324"
63093     switch \sel_in
63094       attribute \src "libresoc.v:0.0-0.0"
63095       case 2'11
63096         assign { } { }
63097         assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] }
63098       case
63099         assign $1\spr[9:0] 10'0000000000
63100     end
63101     sync always
63102       update \spr $0\spr[9:0]
63103   end
63104   attribute \src "libresoc.v:42204.3-42219.6"
63105   process $proc$libresoc.v:42204$972
63106     assign { } { }
63107     assign { } { }
63108     assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0]
63109     attribute \src "libresoc.v:42205.5-42205.29"
63110     switch \initial
63111       attribute \src "libresoc.v:42205.9-42205.17"
63112       case 1'1
63113       case
63114     end
63115     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324"
63116     switch \sel_in
63117       attribute \src "libresoc.v:0.0-0.0"
63118       case 2'11
63119         assign { } { }
63120         assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0]
63121         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
63122         switch \$1
63123           attribute \src "libresoc.v:0.0-0.0"
63124           case 1'1
63125             assign { } { }
63126             assign $2\sprmap_spr_i[9:0] \spr
63127           case
63128             assign $2\sprmap_spr_i[9:0] 10'0000000000
63129         end
63130       case
63131         assign $1\sprmap_spr_i[9:0] 10'0000000000
63132     end
63133     sync always
63134       update \sprmap_spr_i $0\sprmap_spr_i[9:0]
63135   end
63136   attribute \src "libresoc.v:42220.3-42236.6"
63137   process $proc$libresoc.v:42220$973
63138     assign { } { }
63139     assign { } { }
63140     assign { } { }
63141     assign { } { }
63142     assign $0\spr_o[9:0] $1\spr_o[9:0]
63143     assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
63144     attribute \src "libresoc.v:42221.5-42221.29"
63145     switch \initial
63146       attribute \src "libresoc.v:42221.9-42221.17"
63147       case 1'1
63148       case
63149     end
63150     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324"
63151     switch \sel_in
63152       attribute \src "libresoc.v:0.0-0.0"
63153       case 2'11
63154         assign { } { }
63155         assign { } { }
63156         assign $1\spr_o[9:0] $2\spr_o[9:0]
63157         assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0]
63158         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
63159         switch \$3
63160           attribute \src "libresoc.v:0.0-0.0"
63161           case 1'1
63162             assign { } { }
63163             assign { } { }
63164             assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o }
63165           case
63166             assign $2\spr_o[9:0] 10'0000000000
63167             assign $2\spr_o_ok[0:0] 1'0
63168         end
63169       case
63170         assign $1\spr_o[9:0] 10'0000000000
63171         assign $1\spr_o_ok[0:0] 1'0
63172     end
63173     sync always
63174       update \spr_o $0\spr_o[9:0]
63175       update \spr_o_ok $0\spr_o_ok[0:0]
63176   end
63177   attribute \src "libresoc.v:42237.3-42275.6"
63178   process $proc$libresoc.v:42237$974
63179     assign { } { }
63180     assign { } { }
63181     assign { } { }
63182     assign { } { }
63183     assign { } { }
63184     assign { } { }
63185     assign $0\fast_o[2:0] $3\fast_o[2:0]
63186     assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0]
63187     attribute \src "libresoc.v:42238.5-42238.29"
63188     switch \initial
63189       attribute \src "libresoc.v:42238.9-42238.17"
63190       case 1'1
63191       case
63192     end
63193     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324"
63194     switch \sel_in
63195       attribute \src "libresoc.v:0.0-0.0"
63196       case 2'11
63197         assign { } { }
63198         assign { } { }
63199         assign $1\fast_o[2:0] $2\fast_o[2:0]
63200         assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0]
63201         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
63202         switch \$5
63203           attribute \src "libresoc.v:0.0-0.0"
63204           case 1'1
63205             assign { } { }
63206             assign { } { }
63207             assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o }
63208           case
63209             assign $2\fast_o[2:0] 3'000
63210             assign $2\fast_o_ok[0:0] 1'0
63211         end
63212       case
63213         assign $1\fast_o[2:0] 3'000
63214         assign $1\fast_o_ok[0:0] 1'0
63215     end
63216     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340"
63217     switch \internal_op
63218       attribute \src "libresoc.v:0.0-0.0"
63219       case 7'0000111 , 7'0001000
63220         assign { } { }
63221         assign { } { }
63222         assign $3\fast_o[2:0] $4\fast_o[2:0]
63223         assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0]
63224         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
63225         switch \$7
63226           attribute \src "libresoc.v:0.0-0.0"
63227           case 1'1
63228             assign { } { }
63229             assign { } { }
63230             assign $4\fast_o[2:0] 3'000
63231             assign $4\fast_o_ok[0:0] 1'1
63232           case
63233             assign $4\fast_o[2:0] $1\fast_o[2:0]
63234             assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0]
63235         end
63236       attribute \src "libresoc.v:0.0-0.0"
63237       case 7'1000110
63238         assign { } { }
63239         assign { } { }
63240         assign $3\fast_o[2:0] 3'011
63241         assign $3\fast_o_ok[0:0] 1'1
63242       case
63243         assign $3\fast_o[2:0] $1\fast_o[2:0]
63244         assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0]
63245     end
63246     sync always
63247       update \fast_o $0\fast_o[2:0]
63248       update \fast_o_ok $0\fast_o_ok[0:0]
63249   end
63250   connect \$1 $eq$libresoc.v:42152$965_Y
63251   connect \$3 $eq$libresoc.v:42153$966_Y
63252   connect \$5 $eq$libresoc.v:42154$967_Y
63253   connect \$7 $not$libresoc.v:42155$968_Y
63254 end
63255 attribute \src "libresoc.v:42280.1-42441.10"
63256 attribute \cells_not_processed 1
63257 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2"
63258 attribute \generator "nMigen"
63259 module \dec_o2
63260   attribute \src "libresoc.v:42401.3-42420.6"
63261   wire width 3 $0\fast_o[2:0]
63262   attribute \src "libresoc.v:42421.3-42440.6"
63263   wire $0\fast_o_ok[0:0]
63264   attribute \src "libresoc.v:42281.7-42281.20"
63265   wire $0\initial[0:0]
63266   attribute \src "libresoc.v:42387.3-42400.6"
63267   wire width 5 $0\reg_o[4:0]
63268   attribute \src "libresoc.v:42387.3-42400.6"
63269   wire $0\reg_o_ok[0:0]
63270   attribute \src "libresoc.v:42401.3-42420.6"
63271   wire width 3 $1\fast_o[2:0]
63272   attribute \src "libresoc.v:42421.3-42440.6"
63273   wire $1\fast_o_ok[0:0]
63274   attribute \src "libresoc.v:42387.3-42400.6"
63275   wire width 5 $1\reg_o[4:0]
63276   attribute \src "libresoc.v:42387.3-42400.6"
63277   wire $1\reg_o_ok[0:0]
63278   attribute \src "libresoc.v:42401.3-42420.6"
63279   wire width 3 $2\fast_o[2:0]
63280   attribute \src "libresoc.v:42421.3-42440.6"
63281   wire $2\fast_o_ok[0:0]
63282   attribute \src "libresoc.v:42385.17-42385.108"
63283   wire $eq$libresoc.v:42385$976_Y
63284   attribute \src "libresoc.v:42386.17-42386.100"
63285   wire width 6 $extend$libresoc.v:42386$977_Y
63286   attribute \src "libresoc.v:42386.17-42386.100"
63287   wire width 6 $pos$libresoc.v:42386$978_Y
63288   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377"
63289   wire \$1
63290   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
63291   wire width 6 \$3
63292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
63293   wire width 5 input 7 \RA
63294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63295   wire width 3 output 4 \fast_o
63296   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63297   wire output 5 \fast_o_ok
63298   attribute \src "libresoc.v:42281.7-42281.15"
63299   wire \initial
63300   attribute \enum_base_type "MicrOp"
63301   attribute \enum_value_0000000 "OP_ILLEGAL"
63302   attribute \enum_value_0000001 "OP_NOP"
63303   attribute \enum_value_0000010 "OP_ADD"
63304   attribute \enum_value_0000011 "OP_ADDPCIS"
63305   attribute \enum_value_0000100 "OP_AND"
63306   attribute \enum_value_0000101 "OP_ATTN"
63307   attribute \enum_value_0000110 "OP_B"
63308   attribute \enum_value_0000111 "OP_BC"
63309   attribute \enum_value_0001000 "OP_BCREG"
63310   attribute \enum_value_0001001 "OP_BPERM"
63311   attribute \enum_value_0001010 "OP_CMP"
63312   attribute \enum_value_0001011 "OP_CMPB"
63313   attribute \enum_value_0001100 "OP_CMPEQB"
63314   attribute \enum_value_0001101 "OP_CMPRB"
63315   attribute \enum_value_0001110 "OP_CNTZ"
63316   attribute \enum_value_0001111 "OP_CRAND"
63317   attribute \enum_value_0010000 "OP_CRANDC"
63318   attribute \enum_value_0010001 "OP_CREQV"
63319   attribute \enum_value_0010010 "OP_CRNAND"
63320   attribute \enum_value_0010011 "OP_CRNOR"
63321   attribute \enum_value_0010100 "OP_CROR"
63322   attribute \enum_value_0010101 "OP_CRORC"
63323   attribute \enum_value_0010110 "OP_CRXOR"
63324   attribute \enum_value_0010111 "OP_DARN"
63325   attribute \enum_value_0011000 "OP_DCBF"
63326   attribute \enum_value_0011001 "OP_DCBST"
63327   attribute \enum_value_0011010 "OP_DCBT"
63328   attribute \enum_value_0011011 "OP_DCBTST"
63329   attribute \enum_value_0011100 "OP_DCBZ"
63330   attribute \enum_value_0011101 "OP_DIV"
63331   attribute \enum_value_0011110 "OP_DIVE"
63332   attribute \enum_value_0011111 "OP_EXTS"
63333   attribute \enum_value_0100000 "OP_EXTSWSLI"
63334   attribute \enum_value_0100001 "OP_ICBI"
63335   attribute \enum_value_0100010 "OP_ICBT"
63336   attribute \enum_value_0100011 "OP_ISEL"
63337   attribute \enum_value_0100100 "OP_ISYNC"
63338   attribute \enum_value_0100101 "OP_LOAD"
63339   attribute \enum_value_0100110 "OP_STORE"
63340   attribute \enum_value_0100111 "OP_MADDHD"
63341   attribute \enum_value_0101000 "OP_MADDHDU"
63342   attribute \enum_value_0101001 "OP_MADDLD"
63343   attribute \enum_value_0101010 "OP_MCRF"
63344   attribute \enum_value_0101011 "OP_MCRXR"
63345   attribute \enum_value_0101100 "OP_MCRXRX"
63346   attribute \enum_value_0101101 "OP_MFCR"
63347   attribute \enum_value_0101110 "OP_MFSPR"
63348   attribute \enum_value_0101111 "OP_MOD"
63349   attribute \enum_value_0110000 "OP_MTCRF"
63350   attribute \enum_value_0110001 "OP_MTSPR"
63351   attribute \enum_value_0110010 "OP_MUL_L64"
63352   attribute \enum_value_0110011 "OP_MUL_H64"
63353   attribute \enum_value_0110100 "OP_MUL_H32"
63354   attribute \enum_value_0110101 "OP_OR"
63355   attribute \enum_value_0110110 "OP_POPCNT"
63356   attribute \enum_value_0110111 "OP_PRTY"
63357   attribute \enum_value_0111000 "OP_RLC"
63358   attribute \enum_value_0111001 "OP_RLCL"
63359   attribute \enum_value_0111010 "OP_RLCR"
63360   attribute \enum_value_0111011 "OP_SETB"
63361   attribute \enum_value_0111100 "OP_SHL"
63362   attribute \enum_value_0111101 "OP_SHR"
63363   attribute \enum_value_0111110 "OP_SYNC"
63364   attribute \enum_value_0111111 "OP_TRAP"
63365   attribute \enum_value_1000011 "OP_XOR"
63366   attribute \enum_value_1000100 "OP_SIM_CONFIG"
63367   attribute \enum_value_1000101 "OP_CROP"
63368   attribute \enum_value_1000110 "OP_RFID"
63369   attribute \enum_value_1000111 "OP_MFMSR"
63370   attribute \enum_value_1001000 "OP_MTMSRD"
63371   attribute \enum_value_1001001 "OP_SC"
63372   attribute \enum_value_1001010 "OP_MTMSR"
63373   attribute \enum_value_1001011 "OP_TLBIE"
63374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
63375   wire width 7 input 8 \internal_op
63376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366"
63377   wire input 1 \lk
63378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63379   wire width 5 output 2 \reg_o
63380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63381   wire output 3 \reg_o_ok
63382   attribute \enum_base_type "LDSTMode"
63383   attribute \enum_value_00 "NONE"
63384   attribute \enum_value_01 "update"
63385   attribute \enum_value_10 "cix"
63386   attribute \enum_value_11 "cx"
63387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
63388   wire width 2 input 6 \upd
63389   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377"
63390   cell $eq $eq$libresoc.v:42385$976
63391     parameter \A_SIGNED 0
63392     parameter \A_WIDTH 2
63393     parameter \B_SIGNED 0
63394     parameter \B_WIDTH 2
63395     parameter \Y_WIDTH 1
63396     connect \A \upd
63397     connect \B 2'01
63398     connect \Y $eq$libresoc.v:42385$976_Y
63399   end
63400   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
63401   cell $pos $extend$libresoc.v:42386$977
63402     parameter \A_SIGNED 0
63403     parameter \A_WIDTH 5
63404     parameter \Y_WIDTH 6
63405     connect \A \RA
63406     connect \Y $extend$libresoc.v:42386$977_Y
63407   end
63408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
63409   cell $pos $pos$libresoc.v:42386$978
63410     parameter \A_SIGNED 0
63411     parameter \A_WIDTH 6
63412     parameter \Y_WIDTH 6
63413     connect \A $extend$libresoc.v:42386$977_Y
63414     connect \Y $pos$libresoc.v:42386$978_Y
63415   end
63416   attribute \src "libresoc.v:42281.7-42281.20"
63417   process $proc$libresoc.v:42281$982
63418     assign { } { }
63419     assign $0\initial[0:0] 1'0
63420     sync always
63421       update \initial $0\initial[0:0]
63422     sync init
63423   end
63424   attribute \src "libresoc.v:42387.3-42400.6"
63425   process $proc$libresoc.v:42387$979
63426     assign { } { }
63427     assign { } { }
63428     assign { } { }
63429     assign { } { }
63430     assign $0\reg_o[4:0] $1\reg_o[4:0]
63431     assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0]
63432     attribute \src "libresoc.v:42388.5-42388.29"
63433     switch \initial
63434       attribute \src "libresoc.v:42388.9-42388.17"
63435       case 1'1
63436       case
63437     end
63438     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377"
63439     switch \$1
63440       attribute \src "libresoc.v:0.0-0.0"
63441       case 1'1
63442         assign { } { }
63443         assign { } { }
63444         assign $1\reg_o[4:0] \$3 [4:0]
63445         assign $1\reg_o_ok[0:0] 1'1
63446       case
63447         assign $1\reg_o[4:0] 5'00000
63448         assign $1\reg_o_ok[0:0] 1'0
63449     end
63450     sync always
63451       update \reg_o $0\reg_o[4:0]
63452       update \reg_o_ok $0\reg_o_ok[0:0]
63453   end
63454   attribute \src "libresoc.v:42401.3-42420.6"
63455   process $proc$libresoc.v:42401$980
63456     assign { } { }
63457     assign { } { }
63458     assign $0\fast_o[2:0] $1\fast_o[2:0]
63459     attribute \src "libresoc.v:42402.5-42402.29"
63460     switch \initial
63461       attribute \src "libresoc.v:42402.9-42402.17"
63462       case 1'1
63463       case
63464     end
63465     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384"
63466     switch \internal_op
63467       attribute \src "libresoc.v:0.0-0.0"
63468       case 7'0000111 , 7'0000110 , 7'0001000
63469         assign { } { }
63470         assign $1\fast_o[2:0] $2\fast_o[2:0]
63471         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388"
63472         switch \lk
63473           attribute \src "libresoc.v:0.0-0.0"
63474           case 1'1
63475             assign { } { }
63476             assign $2\fast_o[2:0] 3'001
63477           case
63478             assign $2\fast_o[2:0] 3'000
63479         end
63480       attribute \src "libresoc.v:0.0-0.0"
63481       case 7'1000110
63482         assign { } { }
63483         assign $1\fast_o[2:0] 3'100
63484       case
63485         assign $1\fast_o[2:0] 3'000
63486     end
63487     sync always
63488       update \fast_o $0\fast_o[2:0]
63489   end
63490   attribute \src "libresoc.v:42421.3-42440.6"
63491   process $proc$libresoc.v:42421$981
63492     assign { } { }
63493     assign { } { }
63494     assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
63495     attribute \src "libresoc.v:42422.5-42422.29"
63496     switch \initial
63497       attribute \src "libresoc.v:42422.9-42422.17"
63498       case 1'1
63499       case
63500     end
63501     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384"
63502     switch \internal_op
63503       attribute \src "libresoc.v:0.0-0.0"
63504       case 7'0000111 , 7'0000110 , 7'0001000
63505         assign { } { }
63506         assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0]
63507         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388"
63508         switch \lk
63509           attribute \src "libresoc.v:0.0-0.0"
63510           case 1'1
63511             assign { } { }
63512             assign $2\fast_o_ok[0:0] 1'1
63513           case
63514             assign $2\fast_o_ok[0:0] 1'0
63515         end
63516       attribute \src "libresoc.v:0.0-0.0"
63517       case 7'1000110
63518         assign { } { }
63519         assign $1\fast_o_ok[0:0] 1'1
63520       case
63521         assign $1\fast_o_ok[0:0] 1'0
63522     end
63523     sync always
63524       update \fast_o_ok $0\fast_o_ok[0:0]
63525   end
63526   connect \$1 $eq$libresoc.v:42385$976_Y
63527   connect \$3 $pos$libresoc.v:42386$978_Y
63528 end
63529 attribute \src "libresoc.v:42445.1-42579.10"
63530 attribute \cells_not_processed 1
63531 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe"
63532 attribute \generator "nMigen"
63533 module \dec_oe
63534   attribute \src "libresoc.v:42446.7-42446.20"
63535   wire $0\initial[0:0]
63536   attribute \src "libresoc.v:42537.3-42557.6"
63537   wire $0\oe[0:0]
63538   attribute \src "libresoc.v:42558.3-42578.6"
63539   wire $0\oe_ok[0:0]
63540   attribute \src "libresoc.v:42537.3-42557.6"
63541   wire $1\oe[0:0]
63542   attribute \src "libresoc.v:42558.3-42578.6"
63543   wire $1\oe_ok[0:0]
63544   attribute \src "libresoc.v:42537.3-42557.6"
63545   wire $2\oe[0:0]
63546   attribute \src "libresoc.v:42558.3-42578.6"
63547   wire $2\oe_ok[0:0]
63548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
63549   wire input 4 \OE
63550   attribute \src "libresoc.v:42446.7-42446.15"
63551   wire \initial
63552   attribute \enum_base_type "MicrOp"
63553   attribute \enum_value_0000000 "OP_ILLEGAL"
63554   attribute \enum_value_0000001 "OP_NOP"
63555   attribute \enum_value_0000010 "OP_ADD"
63556   attribute \enum_value_0000011 "OP_ADDPCIS"
63557   attribute \enum_value_0000100 "OP_AND"
63558   attribute \enum_value_0000101 "OP_ATTN"
63559   attribute \enum_value_0000110 "OP_B"
63560   attribute \enum_value_0000111 "OP_BC"
63561   attribute \enum_value_0001000 "OP_BCREG"
63562   attribute \enum_value_0001001 "OP_BPERM"
63563   attribute \enum_value_0001010 "OP_CMP"
63564   attribute \enum_value_0001011 "OP_CMPB"
63565   attribute \enum_value_0001100 "OP_CMPEQB"
63566   attribute \enum_value_0001101 "OP_CMPRB"
63567   attribute \enum_value_0001110 "OP_CNTZ"
63568   attribute \enum_value_0001111 "OP_CRAND"
63569   attribute \enum_value_0010000 "OP_CRANDC"
63570   attribute \enum_value_0010001 "OP_CREQV"
63571   attribute \enum_value_0010010 "OP_CRNAND"
63572   attribute \enum_value_0010011 "OP_CRNOR"
63573   attribute \enum_value_0010100 "OP_CROR"
63574   attribute \enum_value_0010101 "OP_CRORC"
63575   attribute \enum_value_0010110 "OP_CRXOR"
63576   attribute \enum_value_0010111 "OP_DARN"
63577   attribute \enum_value_0011000 "OP_DCBF"
63578   attribute \enum_value_0011001 "OP_DCBST"
63579   attribute \enum_value_0011010 "OP_DCBT"
63580   attribute \enum_value_0011011 "OP_DCBTST"
63581   attribute \enum_value_0011100 "OP_DCBZ"
63582   attribute \enum_value_0011101 "OP_DIV"
63583   attribute \enum_value_0011110 "OP_DIVE"
63584   attribute \enum_value_0011111 "OP_EXTS"
63585   attribute \enum_value_0100000 "OP_EXTSWSLI"
63586   attribute \enum_value_0100001 "OP_ICBI"
63587   attribute \enum_value_0100010 "OP_ICBT"
63588   attribute \enum_value_0100011 "OP_ISEL"
63589   attribute \enum_value_0100100 "OP_ISYNC"
63590   attribute \enum_value_0100101 "OP_LOAD"
63591   attribute \enum_value_0100110 "OP_STORE"
63592   attribute \enum_value_0100111 "OP_MADDHD"
63593   attribute \enum_value_0101000 "OP_MADDHDU"
63594   attribute \enum_value_0101001 "OP_MADDLD"
63595   attribute \enum_value_0101010 "OP_MCRF"
63596   attribute \enum_value_0101011 "OP_MCRXR"
63597   attribute \enum_value_0101100 "OP_MCRXRX"
63598   attribute \enum_value_0101101 "OP_MFCR"
63599   attribute \enum_value_0101110 "OP_MFSPR"
63600   attribute \enum_value_0101111 "OP_MOD"
63601   attribute \enum_value_0110000 "OP_MTCRF"
63602   attribute \enum_value_0110001 "OP_MTSPR"
63603   attribute \enum_value_0110010 "OP_MUL_L64"
63604   attribute \enum_value_0110011 "OP_MUL_H64"
63605   attribute \enum_value_0110100 "OP_MUL_H32"
63606   attribute \enum_value_0110101 "OP_OR"
63607   attribute \enum_value_0110110 "OP_POPCNT"
63608   attribute \enum_value_0110111 "OP_PRTY"
63609   attribute \enum_value_0111000 "OP_RLC"
63610   attribute \enum_value_0111001 "OP_RLCL"
63611   attribute \enum_value_0111010 "OP_RLCR"
63612   attribute \enum_value_0111011 "OP_SETB"
63613   attribute \enum_value_0111100 "OP_SHL"
63614   attribute \enum_value_0111101 "OP_SHR"
63615   attribute \enum_value_0111110 "OP_SYNC"
63616   attribute \enum_value_0111111 "OP_TRAP"
63617   attribute \enum_value_1000011 "OP_XOR"
63618   attribute \enum_value_1000100 "OP_SIM_CONFIG"
63619   attribute \enum_value_1000101 "OP_CROP"
63620   attribute \enum_value_1000110 "OP_RFID"
63621   attribute \enum_value_1000111 "OP_MFMSR"
63622   attribute \enum_value_1001000 "OP_MTMSRD"
63623   attribute \enum_value_1001001 "OP_SC"
63624   attribute \enum_value_1001010 "OP_MTMSR"
63625   attribute \enum_value_1001011 "OP_TLBIE"
63626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170"
63627   wire width 7 input 1 \internal_op
63628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63629   wire output 2 \oe
63630   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63631   wire output 3 \oe_ok
63632   attribute \enum_base_type "RC"
63633   attribute \enum_value_00 "NONE"
63634   attribute \enum_value_01 "ONE"
63635   attribute \enum_value_10 "RC"
63636   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445"
63637   wire width 2 input 5 \sel_in
63638   attribute \src "libresoc.v:42446.7-42446.20"
63639   process $proc$libresoc.v:42446$985
63640     assign { } { }
63641     assign $0\initial[0:0] 1'0
63642     sync always
63643       update \initial $0\initial[0:0]
63644     sync init
63645   end
63646   attribute \src "libresoc.v:42537.3-42557.6"
63647   process $proc$libresoc.v:42537$983
63648     assign { } { }
63649     assign { } { }
63650     assign $0\oe[0:0] $1\oe[0:0]
63651     attribute \src "libresoc.v:42538.5-42538.29"
63652     switch \initial
63653       attribute \src "libresoc.v:42538.9-42538.17"
63654       case 1'1
63655       case
63656     end
63657     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454"
63658     switch \internal_op
63659       attribute \src "libresoc.v:0.0-0.0"
63660       case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
63661         assign $1\oe[0:0] 1'0
63662       attribute \src "libresoc.v:0.0-0.0"
63663       case
63664         assign { } { }
63665         assign $1\oe[0:0] $2\oe[0:0]
63666         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
63667         switch \sel_in
63668           attribute \src "libresoc.v:0.0-0.0"
63669           case 2'10
63670             assign { } { }
63671             assign $2\oe[0:0] \OE
63672           case
63673             assign $2\oe[0:0] 1'0
63674         end
63675     end
63676     sync always
63677       update \oe $0\oe[0:0]
63678   end
63679   attribute \src "libresoc.v:42558.3-42578.6"
63680   process $proc$libresoc.v:42558$984
63681     assign { } { }
63682     assign { } { }
63683     assign $0\oe_ok[0:0] $1\oe_ok[0:0]
63684     attribute \src "libresoc.v:42559.5-42559.29"
63685     switch \initial
63686       attribute \src "libresoc.v:42559.9-42559.17"
63687       case 1'1
63688       case
63689     end
63690     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454"
63691     switch \internal_op
63692       attribute \src "libresoc.v:0.0-0.0"
63693       case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
63694         assign $1\oe_ok[0:0] 1'0
63695       attribute \src "libresoc.v:0.0-0.0"
63696       case
63697         assign { } { }
63698         assign $1\oe_ok[0:0] $2\oe_ok[0:0]
63699         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
63700         switch \sel_in
63701           attribute \src "libresoc.v:0.0-0.0"
63702           case 2'10
63703             assign { } { }
63704             assign $2\oe_ok[0:0] 1'1
63705           case
63706             assign $2\oe_ok[0:0] 1'0
63707         end
63708     end
63709     sync always
63710       update \oe_ok $0\oe_ok[0:0]
63711   end
63712 end
63713 attribute \src "libresoc.v:42583.1-42637.10"
63714 attribute \cells_not_processed 1
63715 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc"
63716 attribute \generator "nMigen"
63717 module \dec_rc
63718   attribute \src "libresoc.v:42584.7-42584.20"
63719   wire $0\initial[0:0]
63720   attribute \src "libresoc.v:42599.3-42617.6"
63721   wire $0\rc[0:0]
63722   attribute \src "libresoc.v:42618.3-42636.6"
63723   wire $0\rc_ok[0:0]
63724   attribute \src "libresoc.v:42599.3-42617.6"
63725   wire $1\rc[0:0]
63726   attribute \src "libresoc.v:42618.3-42636.6"
63727   wire $1\rc_ok[0:0]
63728   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450"
63729   wire input 3 \Rc
63730   attribute \src "libresoc.v:42584.7-42584.15"
63731   wire \initial
63732   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63733   wire output 1 \rc
63734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
63735   wire output 2 \rc_ok
63736   attribute \enum_base_type "RC"
63737   attribute \enum_value_00 "NONE"
63738   attribute \enum_value_01 "ONE"
63739   attribute \enum_value_10 "RC"
63740   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408"
63741   wire width 2 input 4 \sel_in
63742   attribute \src "libresoc.v:42584.7-42584.20"
63743   process $proc$libresoc.v:42584$988
63744     assign { } { }
63745     assign $0\initial[0:0] 1'0
63746     sync always
63747       update \initial $0\initial[0:0]
63748     sync init
63749   end
63750   attribute \src "libresoc.v:42599.3-42617.6"
63751   process $proc$libresoc.v:42599$986
63752     assign { } { }
63753     assign { } { }
63754     assign $0\rc[0:0] $1\rc[0:0]
63755     attribute \src "libresoc.v:42600.5-42600.29"
63756     switch \initial
63757       attribute \src "libresoc.v:42600.9-42600.17"
63758       case 1'1
63759       case
63760     end
63761     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417"
63762     switch \sel_in
63763       attribute \src "libresoc.v:0.0-0.0"
63764       case 2'10
63765         assign { } { }
63766         assign $1\rc[0:0] \Rc
63767       attribute \src "libresoc.v:0.0-0.0"
63768       case 2'01
63769         assign { } { }
63770         assign $1\rc[0:0] 1'1
63771       attribute \src "libresoc.v:0.0-0.0"
63772       case 2'00
63773         assign { } { }
63774         assign $1\rc[0:0] 1'0
63775       case
63776         assign $1\rc[0:0] 1'0
63777     end
63778     sync always
63779       update \rc $0\rc[0:0]
63780   end
63781   attribute \src "libresoc.v:42618.3-42636.6"
63782   process $proc$libresoc.v:42618$987
63783     assign { } { }
63784     assign { } { }
63785     assign $0\rc_ok[0:0] $1\rc_ok[0:0]
63786     attribute \src "libresoc.v:42619.5-42619.29"
63787     switch \initial
63788       attribute \src "libresoc.v:42619.9-42619.17"
63789       case 1'1
63790       case
63791     end
63792     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417"
63793     switch \sel_in
63794       attribute \src "libresoc.v:0.0-0.0"
63795       case 2'10
63796         assign { } { }
63797         assign $1\rc_ok[0:0] 1'1
63798       attribute \src "libresoc.v:0.0-0.0"
63799       case 2'01
63800         assign { } { }
63801         assign $1\rc_ok[0:0] 1'1
63802       attribute \src "libresoc.v:0.0-0.0"
63803       case 2'00
63804         assign { } { }
63805         assign $1\rc_ok[0:0] 1'1
63806       case
63807         assign $1\rc_ok[0:0] 1'0
63808     end
63809     sync always
63810       update \rc_ok $0\rc_ok[0:0]
63811   end
63812 end
63813 attribute \src "libresoc.v:42641.1-43020.10"
63814 attribute \cells_not_processed 1
63815 attribute \nmigen.hierarchy "test_issuer.ti.imem"
63816 attribute \generator "nMigen"
63817 module \imem
63818   attribute \src "libresoc.v:42972.3-42981.6"
63819   wire $0\a_busy_o[0:0]
63820   attribute \src "libresoc.v:42952.3-42971.6"
63821   wire width 45 $0\f_badaddr_o$next[44:0]$1057
63822   attribute \src "libresoc.v:42783.3-42784.39"
63823   wire width 45 $0\f_badaddr_o[44:0]
63824   attribute \src "libresoc.v:42982.3-42999.6"
63825   wire $0\f_busy_o[0:0]
63826   attribute \src "libresoc.v:42929.3-42951.6"
63827   wire $0\f_fetch_err_o$next[0:0]$1052
63828   attribute \src "libresoc.v:42785.3-42786.43"
63829   wire $0\f_fetch_err_o[0:0]
63830   attribute \src "libresoc.v:43000.3-43017.6"
63831   wire width 64 $0\f_instr_o[63:0]
63832   attribute \src "libresoc.v:42906.3-42928.6"
63833   wire width 45 $0\ibus__adr$next[44:0]$1047
63834   attribute \src "libresoc.v:42787.3-42788.35"
63835   wire width 45 $0\ibus__adr[44:0]
63836   attribute \src "libresoc.v:42797.3-42824.6"
63837   wire $0\ibus__cyc$next[0:0]$1023
63838   attribute \src "libresoc.v:42795.3-42796.35"
63839   wire $0\ibus__cyc[0:0]
63840   attribute \src "libresoc.v:42853.3-42880.6"
63841   wire width 8 $0\ibus__sel$next[7:0]$1035
63842   attribute \src "libresoc.v:42791.3-42792.35"
63843   wire width 8 $0\ibus__sel[7:0]
63844   attribute \src "libresoc.v:42825.3-42852.6"
63845   wire $0\ibus__stb$next[0:0]$1029
63846   attribute \src "libresoc.v:42793.3-42794.35"
63847   wire $0\ibus__stb[0:0]
63848   attribute \src "libresoc.v:42881.3-42905.6"
63849   wire width 64 $0\ibus_rdata$next[63:0]$1041
63850   attribute \src "libresoc.v:42789.3-42790.37"
63851   wire width 64 $0\ibus_rdata[63:0]
63852   attribute \src "libresoc.v:42642.7-42642.20"
63853   wire $0\initial[0:0]
63854   attribute \src "libresoc.v:42972.3-42981.6"
63855   wire $1\a_busy_o[0:0]
63856   attribute \src "libresoc.v:42952.3-42971.6"
63857   wire width 45 $1\f_badaddr_o$next[44:0]$1058
63858   attribute \src "libresoc.v:42706.14-42706.44"
63859   wire width 45 $1\f_badaddr_o[44:0]
63860   attribute \src "libresoc.v:42982.3-42999.6"
63861   wire $1\f_busy_o[0:0]
63862   attribute \src "libresoc.v:42929.3-42951.6"
63863   wire $1\f_fetch_err_o$next[0:0]$1053
63864   attribute \src "libresoc.v:42713.7-42713.27"
63865   wire $1\f_fetch_err_o[0:0]
63866   attribute \src "libresoc.v:43000.3-43017.6"
63867   wire width 64 $1\f_instr_o[63:0]
63868   attribute \src "libresoc.v:42906.3-42928.6"
63869   wire width 45 $1\ibus__adr$next[44:0]$1048
63870   attribute \src "libresoc.v:42727.14-42727.42"
63871   wire width 45 $1\ibus__adr[44:0]
63872   attribute \src "libresoc.v:42797.3-42824.6"
63873   wire $1\ibus__cyc$next[0:0]$1024
63874   attribute \src "libresoc.v:42732.7-42732.23"
63875   wire $1\ibus__cyc[0:0]
63876   attribute \src "libresoc.v:42853.3-42880.6"
63877   wire width 8 $1\ibus__sel$next[7:0]$1036
63878   attribute \src "libresoc.v:42741.13-42741.30"
63879   wire width 8 $1\ibus__sel[7:0]
63880   attribute \src "libresoc.v:42825.3-42852.6"
63881   wire $1\ibus__stb$next[0:0]$1030
63882   attribute \src "libresoc.v:42746.7-42746.23"
63883   wire $1\ibus__stb[0:0]
63884   attribute \src "libresoc.v:42881.3-42905.6"
63885   wire width 64 $1\ibus_rdata$next[63:0]$1042
63886   attribute \src "libresoc.v:42750.14-42750.47"
63887   wire width 64 $1\ibus_rdata[63:0]
63888   attribute \src "libresoc.v:42952.3-42971.6"
63889   wire width 45 $2\f_badaddr_o$next[44:0]$1059
63890   attribute \src "libresoc.v:42982.3-42999.6"
63891   wire $2\f_busy_o[0:0]
63892   attribute \src "libresoc.v:42929.3-42951.6"
63893   wire $2\f_fetch_err_o$next[0:0]$1054
63894   attribute \src "libresoc.v:43000.3-43017.6"
63895   wire width 64 $2\f_instr_o[63:0]
63896   attribute \src "libresoc.v:42906.3-42928.6"
63897   wire width 45 $2\ibus__adr$next[44:0]$1049
63898   attribute \src "libresoc.v:42797.3-42824.6"
63899   wire $2\ibus__cyc$next[0:0]$1025
63900   attribute \src "libresoc.v:42853.3-42880.6"
63901   wire width 8 $2\ibus__sel$next[7:0]$1037
63902   attribute \src "libresoc.v:42825.3-42852.6"
63903   wire $2\ibus__stb$next[0:0]$1031
63904   attribute \src "libresoc.v:42881.3-42905.6"
63905   wire width 64 $2\ibus_rdata$next[63:0]$1043
63906   attribute \src "libresoc.v:42952.3-42971.6"
63907   wire width 45 $3\f_badaddr_o$next[44:0]$1060
63908   attribute \src "libresoc.v:42929.3-42951.6"
63909   wire $3\f_fetch_err_o$next[0:0]$1055
63910   attribute \src "libresoc.v:42906.3-42928.6"
63911   wire width 45 $3\ibus__adr$next[44:0]$1050
63912   attribute \src "libresoc.v:42797.3-42824.6"
63913   wire $3\ibus__cyc$next[0:0]$1026
63914   attribute \src "libresoc.v:42853.3-42880.6"
63915   wire width 8 $3\ibus__sel$next[7:0]$1038
63916   attribute \src "libresoc.v:42825.3-42852.6"
63917   wire $3\ibus__stb$next[0:0]$1032
63918   attribute \src "libresoc.v:42881.3-42905.6"
63919   wire width 64 $3\ibus_rdata$next[63:0]$1044
63920   attribute \src "libresoc.v:42797.3-42824.6"
63921   wire $4\ibus__cyc$next[0:0]$1027
63922   attribute \src "libresoc.v:42853.3-42880.6"
63923   wire width 8 $4\ibus__sel$next[7:0]$1039
63924   attribute \src "libresoc.v:42825.3-42852.6"
63925   wire $4\ibus__stb$next[0:0]$1033
63926   attribute \src "libresoc.v:42881.3-42905.6"
63927   wire width 64 $4\ibus_rdata$next[63:0]$1045
63928   attribute \src "libresoc.v:42759.18-42759.110"
63929   wire $and$libresoc.v:42759$991_Y
63930   attribute \src "libresoc.v:42765.18-42765.110"
63931   wire $and$libresoc.v:42765$997_Y
63932   attribute \src "libresoc.v:42770.18-42770.110"
63933   wire $and$libresoc.v:42770$1002_Y
63934   attribute \src "libresoc.v:42773.17-42773.108"
63935   wire $and$libresoc.v:42773$1005_Y
63936   attribute \src "libresoc.v:42776.18-42776.110"
63937   wire $and$libresoc.v:42776$1008_Y
63938   attribute \src "libresoc.v:42777.18-42777.115"
63939   wire $and$libresoc.v:42777$1009_Y
63940   attribute \src "libresoc.v:42779.18-42779.115"
63941   wire $and$libresoc.v:42779$1011_Y
63942   attribute \src "libresoc.v:42758.18-42758.105"
63943   wire $not$libresoc.v:42758$990_Y
63944   attribute \src "libresoc.v:42761.18-42761.105"
63945   wire $not$libresoc.v:42761$993_Y
63946   attribute \src "libresoc.v:42762.17-42762.104"
63947   wire $not$libresoc.v:42762$994_Y
63948   attribute \src "libresoc.v:42764.18-42764.105"
63949   wire $not$libresoc.v:42764$996_Y
63950   attribute \src "libresoc.v:42767.18-42767.105"
63951   wire $not$libresoc.v:42767$999_Y
63952   attribute \src "libresoc.v:42769.18-42769.105"
63953   wire $not$libresoc.v:42769$1001_Y
63954   attribute \src "libresoc.v:42772.18-42772.105"
63955   wire $not$libresoc.v:42772$1004_Y
63956   attribute \src "libresoc.v:42775.18-42775.105"
63957   wire $not$libresoc.v:42775$1007_Y
63958   attribute \src "libresoc.v:42778.18-42778.105"
63959   wire $not$libresoc.v:42778$1010_Y
63960   attribute \src "libresoc.v:42780.18-42780.105"
63961   wire $not$libresoc.v:42780$1012_Y
63962   attribute \src "libresoc.v:42782.17-42782.104"
63963   wire $not$libresoc.v:42782$1014_Y
63964   attribute \src "libresoc.v:42757.17-42757.103"
63965   wire $or$libresoc.v:42757$989_Y
63966   attribute \src "libresoc.v:42760.18-42760.115"
63967   wire $or$libresoc.v:42760$992_Y
63968   attribute \src "libresoc.v:42763.18-42763.106"
63969   wire $or$libresoc.v:42763$995_Y
63970   attribute \src "libresoc.v:42766.18-42766.115"
63971   wire $or$libresoc.v:42766$998_Y
63972   attribute \src "libresoc.v:42768.18-42768.106"
63973   wire $or$libresoc.v:42768$1000_Y
63974   attribute \src "libresoc.v:42771.18-42771.115"
63975   wire $or$libresoc.v:42771$1003_Y
63976   attribute \src "libresoc.v:42774.18-42774.106"
63977   wire $or$libresoc.v:42774$1006_Y
63978   attribute \src "libresoc.v:42781.17-42781.114"
63979   wire $or$libresoc.v:42781$1013_Y
63980   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
63981   wire \$1
63982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
63983   wire \$11
63984   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
63985   wire \$13
63986   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
63987   wire \$15
63988   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
63989   wire \$17
63990   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
63991   wire \$19
63992   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
63993   wire \$21
63994   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
63995   wire \$23
63996   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
63997   wire \$25
63998   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
63999   wire \$27
64000   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64001   wire \$29
64002   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64003   wire \$3
64004   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64005   wire \$31
64006   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64007   wire \$33
64008   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64009   wire \$35
64010   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64011   wire \$37
64012   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64013   wire \$39
64014   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64015   wire \$41
64016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64017   wire \$43
64018   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
64019   wire \$45
64020   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
64021   wire \$47
64022   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
64023   wire \$49
64024   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64025   wire \$5
64026   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
64027   wire \$51
64028   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64029   wire \$7
64030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64031   wire \$9
64032   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
64033   wire \a_busy_o
64034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
64035   wire width 48 input 2 \a_pc_i
64036   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
64037   wire \a_stall_i
64038   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
64039   wire input 3 \a_valid_i
64040   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
64041   wire input 15 \clk
64042   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
64043   wire width 45 \f_badaddr_o
64044   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
64045   wire width 45 \f_badaddr_o$next
64046   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
64047   wire output 5 \f_busy_o
64048   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
64049   wire \f_fetch_err_o
64050   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
64051   wire \f_fetch_err_o$next
64052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
64053   wire width 64 output 6 \f_instr_o
64054   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
64055   wire \f_stall_i
64056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
64057   wire input 4 \f_valid_i
64058   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64059   wire input 9 \ibus__ack
64060   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64061   wire width 45 output 14 \ibus__adr
64062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64063   wire width 45 \ibus__adr$next
64064   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64065   wire output 8 \ibus__cyc
64066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64067   wire \ibus__cyc$next
64068   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64069   wire width 64 input 13 \ibus__dat_r
64070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64071   wire input 10 \ibus__err
64072   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64073   wire width 8 output 12 \ibus__sel
64074   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64075   wire width 8 \ibus__sel$next
64076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64077   wire output 11 \ibus__stb
64078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
64079   wire \ibus__stb$next
64080   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69"
64081   wire width 64 \ibus_rdata
64082   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69"
64083   wire width 64 \ibus_rdata$next
64084   attribute \src "libresoc.v:42642.7-42642.15"
64085   wire \initial
64086   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
64087   wire input 1 \rst
64088   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92"
64089   wire input 7 \wb_icache_en
64090   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64091   cell $and $and$libresoc.v:42759$991
64092     parameter \A_SIGNED 0
64093     parameter \A_WIDTH 1
64094     parameter \B_SIGNED 0
64095     parameter \B_WIDTH 1
64096     parameter \Y_WIDTH 1
64097     connect \A \a_valid_i
64098     connect \B \$11
64099     connect \Y $and$libresoc.v:42759$991_Y
64100   end
64101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64102   cell $and $and$libresoc.v:42765$997
64103     parameter \A_SIGNED 0
64104     parameter \A_WIDTH 1
64105     parameter \B_SIGNED 0
64106     parameter \B_WIDTH 1
64107     parameter \Y_WIDTH 1
64108     connect \A \a_valid_i
64109     connect \B \$21
64110     connect \Y $and$libresoc.v:42765$997_Y
64111   end
64112   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64113   cell $and $and$libresoc.v:42770$1002
64114     parameter \A_SIGNED 0
64115     parameter \A_WIDTH 1
64116     parameter \B_SIGNED 0
64117     parameter \B_WIDTH 1
64118     parameter \Y_WIDTH 1
64119     connect \A \a_valid_i
64120     connect \B \$31
64121     connect \Y $and$libresoc.v:42770$1002_Y
64122   end
64123   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64124   cell $and $and$libresoc.v:42773$1005
64125     parameter \A_SIGNED 0
64126     parameter \A_WIDTH 1
64127     parameter \B_SIGNED 0
64128     parameter \B_WIDTH 1
64129     parameter \Y_WIDTH 1
64130     connect \A \a_valid_i
64131     connect \B \$1
64132     connect \Y $and$libresoc.v:42773$1005_Y
64133   end
64134   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64135   cell $and $and$libresoc.v:42776$1008
64136     parameter \A_SIGNED 0
64137     parameter \A_WIDTH 1
64138     parameter \B_SIGNED 0
64139     parameter \B_WIDTH 1
64140     parameter \Y_WIDTH 1
64141     connect \A \a_valid_i
64142     connect \B \$41
64143     connect \Y $and$libresoc.v:42776$1008_Y
64144   end
64145   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
64146   cell $and $and$libresoc.v:42777$1009
64147     parameter \A_SIGNED 0
64148     parameter \A_WIDTH 1
64149     parameter \B_SIGNED 0
64150     parameter \B_WIDTH 1
64151     parameter \Y_WIDTH 1
64152     connect \A \ibus__cyc
64153     connect \B \ibus__err
64154     connect \Y $and$libresoc.v:42777$1009_Y
64155   end
64156   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
64157   cell $and $and$libresoc.v:42779$1011
64158     parameter \A_SIGNED 0
64159     parameter \A_WIDTH 1
64160     parameter \B_SIGNED 0
64161     parameter \B_WIDTH 1
64162     parameter \Y_WIDTH 1
64163     connect \A \ibus__cyc
64164     connect \B \ibus__err
64165     connect \Y $and$libresoc.v:42779$1011_Y
64166   end
64167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64168   cell $not $not$libresoc.v:42758$990
64169     parameter \A_SIGNED 0
64170     parameter \A_WIDTH 1
64171     parameter \Y_WIDTH 1
64172     connect \A \a_stall_i
64173     connect \Y $not$libresoc.v:42758$990_Y
64174   end
64175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64176   cell $not $not$libresoc.v:42761$993
64177     parameter \A_SIGNED 0
64178     parameter \A_WIDTH 1
64179     parameter \Y_WIDTH 1
64180     connect \A \f_valid_i
64181     connect \Y $not$libresoc.v:42761$993_Y
64182   end
64183   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64184   cell $not $not$libresoc.v:42762$994
64185     parameter \A_SIGNED 0
64186     parameter \A_WIDTH 1
64187     parameter \Y_WIDTH 1
64188     connect \A \a_stall_i
64189     connect \Y $not$libresoc.v:42762$994_Y
64190   end
64191   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64192   cell $not $not$libresoc.v:42764$996
64193     parameter \A_SIGNED 0
64194     parameter \A_WIDTH 1
64195     parameter \Y_WIDTH 1
64196     connect \A \a_stall_i
64197     connect \Y $not$libresoc.v:42764$996_Y
64198   end
64199   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64200   cell $not $not$libresoc.v:42767$999
64201     parameter \A_SIGNED 0
64202     parameter \A_WIDTH 1
64203     parameter \Y_WIDTH 1
64204     connect \A \f_valid_i
64205     connect \Y $not$libresoc.v:42767$999_Y
64206   end
64207   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64208   cell $not $not$libresoc.v:42769$1001
64209     parameter \A_SIGNED 0
64210     parameter \A_WIDTH 1
64211     parameter \Y_WIDTH 1
64212     connect \A \a_stall_i
64213     connect \Y $not$libresoc.v:42769$1001_Y
64214   end
64215   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64216   cell $not $not$libresoc.v:42772$1004
64217     parameter \A_SIGNED 0
64218     parameter \A_WIDTH 1
64219     parameter \Y_WIDTH 1
64220     connect \A \f_valid_i
64221     connect \Y $not$libresoc.v:42772$1004_Y
64222   end
64223   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78"
64224   cell $not $not$libresoc.v:42775$1007
64225     parameter \A_SIGNED 0
64226     parameter \A_WIDTH 1
64227     parameter \Y_WIDTH 1
64228     connect \A \a_stall_i
64229     connect \Y $not$libresoc.v:42775$1007_Y
64230   end
64231   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
64232   cell $not $not$libresoc.v:42778$1010
64233     parameter \A_SIGNED 0
64234     parameter \A_WIDTH 1
64235     parameter \Y_WIDTH 1
64236     connect \A \f_stall_i
64237     connect \Y $not$libresoc.v:42778$1010_Y
64238   end
64239   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91"
64240   cell $not $not$libresoc.v:42780$1012
64241     parameter \A_SIGNED 0
64242     parameter \A_WIDTH 1
64243     parameter \Y_WIDTH 1
64244     connect \A \f_stall_i
64245     connect \Y $not$libresoc.v:42780$1012_Y
64246   end
64247   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64248   cell $not $not$libresoc.v:42782$1014
64249     parameter \A_SIGNED 0
64250     parameter \A_WIDTH 1
64251     parameter \Y_WIDTH 1
64252     connect \A \f_valid_i
64253     connect \Y $not$libresoc.v:42782$1014_Y
64254   end
64255   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64256   cell $or $or$libresoc.v:42757$989
64257     parameter \A_SIGNED 0
64258     parameter \A_WIDTH 1
64259     parameter \B_SIGNED 0
64260     parameter \B_WIDTH 1
64261     parameter \Y_WIDTH 1
64262     connect \A \$5
64263     connect \B \$7
64264     connect \Y $or$libresoc.v:42757$989_Y
64265   end
64266   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64267   cell $or $or$libresoc.v:42760$992
64268     parameter \A_SIGNED 0
64269     parameter \A_WIDTH 1
64270     parameter \B_SIGNED 0
64271     parameter \B_WIDTH 1
64272     parameter \Y_WIDTH 1
64273     connect \A \ibus__ack
64274     connect \B \ibus__err
64275     connect \Y $or$libresoc.v:42760$992_Y
64276   end
64277   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64278   cell $or $or$libresoc.v:42763$995
64279     parameter \A_SIGNED 0
64280     parameter \A_WIDTH 1
64281     parameter \B_SIGNED 0
64282     parameter \B_WIDTH 1
64283     parameter \Y_WIDTH 1
64284     connect \A \$15
64285     connect \B \$17
64286     connect \Y $or$libresoc.v:42763$995_Y
64287   end
64288   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64289   cell $or $or$libresoc.v:42766$998
64290     parameter \A_SIGNED 0
64291     parameter \A_WIDTH 1
64292     parameter \B_SIGNED 0
64293     parameter \B_WIDTH 1
64294     parameter \Y_WIDTH 1
64295     connect \A \ibus__ack
64296     connect \B \ibus__err
64297     connect \Y $or$libresoc.v:42766$998_Y
64298   end
64299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64300   cell $or $or$libresoc.v:42768$1000
64301     parameter \A_SIGNED 0
64302     parameter \A_WIDTH 1
64303     parameter \B_SIGNED 0
64304     parameter \B_WIDTH 1
64305     parameter \Y_WIDTH 1
64306     connect \A \$25
64307     connect \B \$27
64308     connect \Y $or$libresoc.v:42768$1000_Y
64309   end
64310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64311   cell $or $or$libresoc.v:42771$1003
64312     parameter \A_SIGNED 0
64313     parameter \A_WIDTH 1
64314     parameter \B_SIGNED 0
64315     parameter \B_WIDTH 1
64316     parameter \Y_WIDTH 1
64317     connect \A \ibus__ack
64318     connect \B \ibus__err
64319     connect \Y $or$libresoc.v:42771$1003_Y
64320   end
64321   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64322   cell $or $or$libresoc.v:42774$1006
64323     parameter \A_SIGNED 0
64324     parameter \A_WIDTH 1
64325     parameter \B_SIGNED 0
64326     parameter \B_WIDTH 1
64327     parameter \Y_WIDTH 1
64328     connect \A \$35
64329     connect \B \$37
64330     connect \Y $or$libresoc.v:42774$1006_Y
64331   end
64332   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64333   cell $or $or$libresoc.v:42781$1013
64334     parameter \A_SIGNED 0
64335     parameter \A_WIDTH 1
64336     parameter \B_SIGNED 0
64337     parameter \B_WIDTH 1
64338     parameter \Y_WIDTH 1
64339     connect \A \ibus__ack
64340     connect \B \ibus__err
64341     connect \Y $or$libresoc.v:42781$1013_Y
64342   end
64343   attribute \src "libresoc.v:42642.7-42642.20"
64344   process $proc$libresoc.v:42642$1064
64345     assign { } { }
64346     assign $0\initial[0:0] 1'0
64347     sync always
64348       update \initial $0\initial[0:0]
64349     sync init
64350   end
64351   attribute \src "libresoc.v:42706.14-42706.44"
64352   process $proc$libresoc.v:42706$1065
64353     assign { } { }
64354     assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000
64355     sync always
64356     sync init
64357       update \f_badaddr_o $1\f_badaddr_o[44:0]
64358   end
64359   attribute \src "libresoc.v:42713.7-42713.27"
64360   process $proc$libresoc.v:42713$1066
64361     assign { } { }
64362     assign $1\f_fetch_err_o[0:0] 1'0
64363     sync always
64364     sync init
64365       update \f_fetch_err_o $1\f_fetch_err_o[0:0]
64366   end
64367   attribute \src "libresoc.v:42727.14-42727.42"
64368   process $proc$libresoc.v:42727$1067
64369     assign { } { }
64370     assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000
64371     sync always
64372     sync init
64373       update \ibus__adr $1\ibus__adr[44:0]
64374   end
64375   attribute \src "libresoc.v:42732.7-42732.23"
64376   process $proc$libresoc.v:42732$1068
64377     assign { } { }
64378     assign $1\ibus__cyc[0:0] 1'0
64379     sync always
64380     sync init
64381       update \ibus__cyc $1\ibus__cyc[0:0]
64382   end
64383   attribute \src "libresoc.v:42741.13-42741.30"
64384   process $proc$libresoc.v:42741$1069
64385     assign { } { }
64386     assign $1\ibus__sel[7:0] 8'00000000
64387     sync always
64388     sync init
64389       update \ibus__sel $1\ibus__sel[7:0]
64390   end
64391   attribute \src "libresoc.v:42746.7-42746.23"
64392   process $proc$libresoc.v:42746$1070
64393     assign { } { }
64394     assign $1\ibus__stb[0:0] 1'0
64395     sync always
64396     sync init
64397       update \ibus__stb $1\ibus__stb[0:0]
64398   end
64399   attribute \src "libresoc.v:42750.14-42750.47"
64400   process $proc$libresoc.v:42750$1071
64401     assign { } { }
64402     assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
64403     sync always
64404     sync init
64405       update \ibus_rdata $1\ibus_rdata[63:0]
64406   end
64407   attribute \src "libresoc.v:42783.3-42784.39"
64408   process $proc$libresoc.v:42783$1015
64409     assign { } { }
64410     assign $0\f_badaddr_o[44:0] \f_badaddr_o$next
64411     sync posedge \clk
64412       update \f_badaddr_o $0\f_badaddr_o[44:0]
64413   end
64414   attribute \src "libresoc.v:42785.3-42786.43"
64415   process $proc$libresoc.v:42785$1016
64416     assign { } { }
64417     assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next
64418     sync posedge \clk
64419       update \f_fetch_err_o $0\f_fetch_err_o[0:0]
64420   end
64421   attribute \src "libresoc.v:42787.3-42788.35"
64422   process $proc$libresoc.v:42787$1017
64423     assign { } { }
64424     assign $0\ibus__adr[44:0] \ibus__adr$next
64425     sync posedge \clk
64426       update \ibus__adr $0\ibus__adr[44:0]
64427   end
64428   attribute \src "libresoc.v:42789.3-42790.37"
64429   process $proc$libresoc.v:42789$1018
64430     assign { } { }
64431     assign $0\ibus_rdata[63:0] \ibus_rdata$next
64432     sync posedge \clk
64433       update \ibus_rdata $0\ibus_rdata[63:0]
64434   end
64435   attribute \src "libresoc.v:42791.3-42792.35"
64436   process $proc$libresoc.v:42791$1019
64437     assign { } { }
64438     assign $0\ibus__sel[7:0] \ibus__sel$next
64439     sync posedge \clk
64440       update \ibus__sel $0\ibus__sel[7:0]
64441   end
64442   attribute \src "libresoc.v:42793.3-42794.35"
64443   process $proc$libresoc.v:42793$1020
64444     assign { } { }
64445     assign $0\ibus__stb[0:0] \ibus__stb$next
64446     sync posedge \clk
64447       update \ibus__stb $0\ibus__stb[0:0]
64448   end
64449   attribute \src "libresoc.v:42795.3-42796.35"
64450   process $proc$libresoc.v:42795$1021
64451     assign { } { }
64452     assign $0\ibus__cyc[0:0] \ibus__cyc$next
64453     sync posedge \clk
64454       update \ibus__cyc $0\ibus__cyc[0:0]
64455   end
64456   attribute \src "libresoc.v:42797.3-42824.6"
64457   process $proc$libresoc.v:42797$1022
64458     assign { } { }
64459     assign { } { }
64460     assign { } { }
64461     assign $0\ibus__cyc$next[0:0]$1023 $4\ibus__cyc$next[0:0]$1027
64462     attribute \src "libresoc.v:42798.5-42798.29"
64463     switch \initial
64464       attribute \src "libresoc.v:42798.9-42798.17"
64465       case 1'1
64466       case
64467     end
64468     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64469     switch \wb_icache_en
64470       attribute \src "libresoc.v:0.0-0.0"
64471       case 1'1
64472         assign { } { }
64473         assign $1\ibus__cyc$next[0:0]$1024 $2\ibus__cyc$next[0:0]$1025
64474         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
64475         switch { \$3 \ibus__cyc }
64476           attribute \src "libresoc.v:0.0-0.0"
64477           case 2'-1
64478             assign { } { }
64479             assign $2\ibus__cyc$next[0:0]$1025 $3\ibus__cyc$next[0:0]$1026
64480             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64481             switch \$9
64482               attribute \src "libresoc.v:0.0-0.0"
64483               case 1'1
64484                 assign { } { }
64485                 assign $3\ibus__cyc$next[0:0]$1026 1'0
64486               case
64487                 assign $3\ibus__cyc$next[0:0]$1026 \ibus__cyc
64488             end
64489           attribute \src "libresoc.v:0.0-0.0"
64490           case 2'1-
64491             assign { } { }
64492             assign $2\ibus__cyc$next[0:0]$1025 1'1
64493           case
64494             assign $2\ibus__cyc$next[0:0]$1025 \ibus__cyc
64495         end
64496       case
64497         assign $1\ibus__cyc$next[0:0]$1024 \ibus__cyc
64498     end
64499     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
64500     switch \rst
64501       attribute \src "libresoc.v:0.0-0.0"
64502       case 1'1
64503         assign { } { }
64504         assign $4\ibus__cyc$next[0:0]$1027 1'0
64505       case
64506         assign $4\ibus__cyc$next[0:0]$1027 $1\ibus__cyc$next[0:0]$1024
64507     end
64508     sync always
64509       update \ibus__cyc$next $0\ibus__cyc$next[0:0]$1023
64510   end
64511   attribute \src "libresoc.v:42825.3-42852.6"
64512   process $proc$libresoc.v:42825$1028
64513     assign { } { }
64514     assign { } { }
64515     assign { } { }
64516     assign $0\ibus__stb$next[0:0]$1029 $4\ibus__stb$next[0:0]$1033
64517     attribute \src "libresoc.v:42826.5-42826.29"
64518     switch \initial
64519       attribute \src "libresoc.v:42826.9-42826.17"
64520       case 1'1
64521       case
64522     end
64523     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64524     switch \wb_icache_en
64525       attribute \src "libresoc.v:0.0-0.0"
64526       case 1'1
64527         assign { } { }
64528         assign $1\ibus__stb$next[0:0]$1030 $2\ibus__stb$next[0:0]$1031
64529         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
64530         switch { \$13 \ibus__cyc }
64531           attribute \src "libresoc.v:0.0-0.0"
64532           case 2'-1
64533             assign { } { }
64534             assign $2\ibus__stb$next[0:0]$1031 $3\ibus__stb$next[0:0]$1032
64535             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64536             switch \$19
64537               attribute \src "libresoc.v:0.0-0.0"
64538               case 1'1
64539                 assign { } { }
64540                 assign $3\ibus__stb$next[0:0]$1032 1'0
64541               case
64542                 assign $3\ibus__stb$next[0:0]$1032 \ibus__stb
64543             end
64544           attribute \src "libresoc.v:0.0-0.0"
64545           case 2'1-
64546             assign { } { }
64547             assign $2\ibus__stb$next[0:0]$1031 1'1
64548           case
64549             assign $2\ibus__stb$next[0:0]$1031 \ibus__stb
64550         end
64551       case
64552         assign $1\ibus__stb$next[0:0]$1030 \ibus__stb
64553     end
64554     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
64555     switch \rst
64556       attribute \src "libresoc.v:0.0-0.0"
64557       case 1'1
64558         assign { } { }
64559         assign $4\ibus__stb$next[0:0]$1033 1'0
64560       case
64561         assign $4\ibus__stb$next[0:0]$1033 $1\ibus__stb$next[0:0]$1030
64562     end
64563     sync always
64564       update \ibus__stb$next $0\ibus__stb$next[0:0]$1029
64565   end
64566   attribute \src "libresoc.v:42853.3-42880.6"
64567   process $proc$libresoc.v:42853$1034
64568     assign { } { }
64569     assign { } { }
64570     assign { } { }
64571     assign $0\ibus__sel$next[7:0]$1035 $4\ibus__sel$next[7:0]$1039
64572     attribute \src "libresoc.v:42854.5-42854.29"
64573     switch \initial
64574       attribute \src "libresoc.v:42854.9-42854.17"
64575       case 1'1
64576       case
64577     end
64578     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64579     switch \wb_icache_en
64580       attribute \src "libresoc.v:0.0-0.0"
64581       case 1'1
64582         assign { } { }
64583         assign $1\ibus__sel$next[7:0]$1036 $2\ibus__sel$next[7:0]$1037
64584         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
64585         switch { \$23 \ibus__cyc }
64586           attribute \src "libresoc.v:0.0-0.0"
64587           case 2'-1
64588             assign { } { }
64589             assign $2\ibus__sel$next[7:0]$1037 $3\ibus__sel$next[7:0]$1038
64590             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64591             switch \$29
64592               attribute \src "libresoc.v:0.0-0.0"
64593               case 1'1
64594                 assign { } { }
64595                 assign $3\ibus__sel$next[7:0]$1038 8'00000000
64596               case
64597                 assign $3\ibus__sel$next[7:0]$1038 \ibus__sel
64598             end
64599           attribute \src "libresoc.v:0.0-0.0"
64600           case 2'1-
64601             assign { } { }
64602             assign $2\ibus__sel$next[7:0]$1037 8'11111111
64603           case
64604             assign $2\ibus__sel$next[7:0]$1037 \ibus__sel
64605         end
64606       case
64607         assign $1\ibus__sel$next[7:0]$1036 \ibus__sel
64608     end
64609     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
64610     switch \rst
64611       attribute \src "libresoc.v:0.0-0.0"
64612       case 1'1
64613         assign { } { }
64614         assign $4\ibus__sel$next[7:0]$1039 8'00000000
64615       case
64616         assign $4\ibus__sel$next[7:0]$1039 $1\ibus__sel$next[7:0]$1036
64617     end
64618     sync always
64619       update \ibus__sel$next $0\ibus__sel$next[7:0]$1035
64620   end
64621   attribute \src "libresoc.v:42881.3-42905.6"
64622   process $proc$libresoc.v:42881$1040
64623     assign { } { }
64624     assign { } { }
64625     assign { } { }
64626     assign $0\ibus_rdata$next[63:0]$1041 $4\ibus_rdata$next[63:0]$1045
64627     attribute \src "libresoc.v:42882.5-42882.29"
64628     switch \initial
64629       attribute \src "libresoc.v:42882.9-42882.17"
64630       case 1'1
64631       case
64632     end
64633     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64634     switch \wb_icache_en
64635       attribute \src "libresoc.v:0.0-0.0"
64636       case 1'1
64637         assign { } { }
64638         assign $1\ibus_rdata$next[63:0]$1042 $2\ibus_rdata$next[63:0]$1043
64639         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
64640         switch { \$33 \ibus__cyc }
64641           attribute \src "libresoc.v:0.0-0.0"
64642           case 2'-1
64643             assign { } { }
64644             assign $2\ibus_rdata$next[63:0]$1043 $3\ibus_rdata$next[63:0]$1044
64645             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
64646             switch \$39
64647               attribute \src "libresoc.v:0.0-0.0"
64648               case 1'1
64649                 assign { } { }
64650                 assign $3\ibus_rdata$next[63:0]$1044 \ibus__dat_r
64651               case
64652                 assign $3\ibus_rdata$next[63:0]$1044 \ibus_rdata
64653             end
64654           case
64655             assign $2\ibus_rdata$next[63:0]$1043 \ibus_rdata
64656         end
64657       case
64658         assign $1\ibus_rdata$next[63:0]$1042 \ibus_rdata
64659     end
64660     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
64661     switch \rst
64662       attribute \src "libresoc.v:0.0-0.0"
64663       case 1'1
64664         assign { } { }
64665         assign $4\ibus_rdata$next[63:0]$1045 64'0000000000000000000000000000000000000000000000000000000000000000
64666       case
64667         assign $4\ibus_rdata$next[63:0]$1045 $1\ibus_rdata$next[63:0]$1042
64668     end
64669     sync always
64670       update \ibus_rdata$next $0\ibus_rdata$next[63:0]$1041
64671   end
64672   attribute \src "libresoc.v:42906.3-42928.6"
64673   process $proc$libresoc.v:42906$1046
64674     assign { } { }
64675     assign { } { }
64676     assign { } { }
64677     assign $0\ibus__adr$next[44:0]$1047 $3\ibus__adr$next[44:0]$1050
64678     attribute \src "libresoc.v:42907.5-42907.29"
64679     switch \initial
64680       attribute \src "libresoc.v:42907.9-42907.17"
64681       case 1'1
64682       case
64683     end
64684     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64685     switch \wb_icache_en
64686       attribute \src "libresoc.v:0.0-0.0"
64687       case 1'1
64688         assign { } { }
64689         assign $1\ibus__adr$next[44:0]$1048 $2\ibus__adr$next[44:0]$1049
64690         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70"
64691         switch { \$43 \ibus__cyc }
64692           attribute \src "libresoc.v:0.0-0.0"
64693           case 2'-1
64694             assign $2\ibus__adr$next[44:0]$1049 \ibus__adr
64695           attribute \src "libresoc.v:0.0-0.0"
64696           case 2'1-
64697             assign { } { }
64698             assign $2\ibus__adr$next[44:0]$1049 \a_pc_i [47:3]
64699           case
64700             assign $2\ibus__adr$next[44:0]$1049 \ibus__adr
64701         end
64702       case
64703         assign $1\ibus__adr$next[44:0]$1048 \ibus__adr
64704     end
64705     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
64706     switch \rst
64707       attribute \src "libresoc.v:0.0-0.0"
64708       case 1'1
64709         assign { } { }
64710         assign $3\ibus__adr$next[44:0]$1050 45'000000000000000000000000000000000000000000000
64711       case
64712         assign $3\ibus__adr$next[44:0]$1050 $1\ibus__adr$next[44:0]$1048
64713     end
64714     sync always
64715       update \ibus__adr$next $0\ibus__adr$next[44:0]$1047
64716   end
64717   attribute \src "libresoc.v:42929.3-42951.6"
64718   process $proc$libresoc.v:42929$1051
64719     assign { } { }
64720     assign { } { }
64721     assign { } { }
64722     assign $0\f_fetch_err_o$next[0:0]$1052 $3\f_fetch_err_o$next[0:0]$1055
64723     attribute \src "libresoc.v:42930.5-42930.29"
64724     switch \initial
64725       attribute \src "libresoc.v:42930.9-42930.17"
64726       case 1'1
64727       case
64728     end
64729     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64730     switch \wb_icache_en
64731       attribute \src "libresoc.v:0.0-0.0"
64732       case 1'1
64733         assign { } { }
64734         assign $1\f_fetch_err_o$next[0:0]$1053 $2\f_fetch_err_o$next[0:0]$1054
64735         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
64736         switch { \$47 \$45 }
64737           attribute \src "libresoc.v:0.0-0.0"
64738           case 2'-1
64739             assign { } { }
64740             assign $2\f_fetch_err_o$next[0:0]$1054 1'1
64741           attribute \src "libresoc.v:0.0-0.0"
64742           case 2'1-
64743             assign { } { }
64744             assign $2\f_fetch_err_o$next[0:0]$1054 1'0
64745           case
64746             assign $2\f_fetch_err_o$next[0:0]$1054 \f_fetch_err_o
64747         end
64748       case
64749         assign $1\f_fetch_err_o$next[0:0]$1053 \f_fetch_err_o
64750     end
64751     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
64752     switch \rst
64753       attribute \src "libresoc.v:0.0-0.0"
64754       case 1'1
64755         assign { } { }
64756         assign $3\f_fetch_err_o$next[0:0]$1055 1'0
64757       case
64758         assign $3\f_fetch_err_o$next[0:0]$1055 $1\f_fetch_err_o$next[0:0]$1053
64759     end
64760     sync always
64761       update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1052
64762   end
64763   attribute \src "libresoc.v:42952.3-42971.6"
64764   process $proc$libresoc.v:42952$1056
64765     assign { } { }
64766     assign { } { }
64767     assign { } { }
64768     assign $0\f_badaddr_o$next[44:0]$1057 $3\f_badaddr_o$next[44:0]$1060
64769     attribute \src "libresoc.v:42953.5-42953.29"
64770     switch \initial
64771       attribute \src "libresoc.v:42953.9-42953.17"
64772       case 1'1
64773       case
64774     end
64775     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64776     switch \wb_icache_en
64777       attribute \src "libresoc.v:0.0-0.0"
64778       case 1'1
64779         assign { } { }
64780         assign $1\f_badaddr_o$next[44:0]$1058 $2\f_badaddr_o$next[44:0]$1059
64781         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
64782         switch { \$51 \$49 }
64783           attribute \src "libresoc.v:0.0-0.0"
64784           case 2'-1
64785             assign { } { }
64786             assign $2\f_badaddr_o$next[44:0]$1059 \ibus__adr
64787           case
64788             assign $2\f_badaddr_o$next[44:0]$1059 \f_badaddr_o
64789         end
64790       case
64791         assign $1\f_badaddr_o$next[44:0]$1058 \f_badaddr_o
64792     end
64793     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
64794     switch \rst
64795       attribute \src "libresoc.v:0.0-0.0"
64796       case 1'1
64797         assign { } { }
64798         assign $3\f_badaddr_o$next[44:0]$1060 45'000000000000000000000000000000000000000000000
64799       case
64800         assign $3\f_badaddr_o$next[44:0]$1060 $1\f_badaddr_o$next[44:0]$1058
64801     end
64802     sync always
64803       update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1057
64804   end
64805   attribute \src "libresoc.v:42972.3-42981.6"
64806   process $proc$libresoc.v:42972$1061
64807     assign { } { }
64808     assign { } { }
64809     assign $0\a_busy_o[0:0] $1\a_busy_o[0:0]
64810     attribute \src "libresoc.v:42973.5-42973.29"
64811     switch \initial
64812       attribute \src "libresoc.v:42973.9-42973.17"
64813       case 1'1
64814       case
64815     end
64816     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64817     switch \wb_icache_en
64818       attribute \src "libresoc.v:0.0-0.0"
64819       case 1'1
64820         assign { } { }
64821         assign $1\a_busy_o[0:0] \ibus__cyc
64822       case
64823         assign $1\a_busy_o[0:0] 1'0
64824     end
64825     sync always
64826       update \a_busy_o $0\a_busy_o[0:0]
64827   end
64828   attribute \src "libresoc.v:42982.3-42999.6"
64829   process $proc$libresoc.v:42982$1062
64830     assign { } { }
64831     assign { } { }
64832     assign $0\f_busy_o[0:0] $1\f_busy_o[0:0]
64833     attribute \src "libresoc.v:42983.5-42983.29"
64834     switch \initial
64835       attribute \src "libresoc.v:42983.9-42983.17"
64836       case 1'1
64837       case
64838     end
64839     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64840     switch \wb_icache_en
64841       attribute \src "libresoc.v:0.0-0.0"
64842       case 1'1
64843         assign { } { }
64844         assign $1\f_busy_o[0:0] $2\f_busy_o[0:0]
64845         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96"
64846         switch \f_fetch_err_o
64847           attribute \src "libresoc.v:0.0-0.0"
64848           case 1'1
64849             assign { } { }
64850             assign $2\f_busy_o[0:0] 1'0
64851           attribute \src "libresoc.v:0.0-0.0"
64852           case
64853             assign { } { }
64854             assign $2\f_busy_o[0:0] \ibus__cyc
64855         end
64856       case
64857         assign $1\f_busy_o[0:0] 1'0
64858     end
64859     sync always
64860       update \f_busy_o $0\f_busy_o[0:0]
64861   end
64862   attribute \src "libresoc.v:43000.3-43017.6"
64863   process $proc$libresoc.v:43000$1063
64864     assign { } { }
64865     assign { } { }
64866     assign $0\f_instr_o[63:0] $1\f_instr_o[63:0]
64867     attribute \src "libresoc.v:43001.5-43001.29"
64868     switch \initial
64869       attribute \src "libresoc.v:43001.9-43001.17"
64870       case 1'1
64871       case
64872     end
64873     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
64874     switch \wb_icache_en
64875       attribute \src "libresoc.v:0.0-0.0"
64876       case 1'1
64877         assign { } { }
64878         assign $1\f_instr_o[63:0] $2\f_instr_o[63:0]
64879         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96"
64880         switch \f_fetch_err_o
64881           attribute \src "libresoc.v:0.0-0.0"
64882           case 1'1
64883             assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
64884           attribute \src "libresoc.v:0.0-0.0"
64885           case
64886             assign { } { }
64887             assign $2\f_instr_o[63:0] \ibus_rdata
64888         end
64889       case
64890         assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
64891     end
64892     sync always
64893       update \f_instr_o $0\f_instr_o[63:0]
64894   end
64895   connect \$9 $or$libresoc.v:42757$989_Y
64896   connect \$11 $not$libresoc.v:42758$990_Y
64897   connect \$13 $and$libresoc.v:42759$991_Y
64898   connect \$15 $or$libresoc.v:42760$992_Y
64899   connect \$17 $not$libresoc.v:42761$993_Y
64900   connect \$1 $not$libresoc.v:42762$994_Y
64901   connect \$19 $or$libresoc.v:42763$995_Y
64902   connect \$21 $not$libresoc.v:42764$996_Y
64903   connect \$23 $and$libresoc.v:42765$997_Y
64904   connect \$25 $or$libresoc.v:42766$998_Y
64905   connect \$27 $not$libresoc.v:42767$999_Y
64906   connect \$29 $or$libresoc.v:42768$1000_Y
64907   connect \$31 $not$libresoc.v:42769$1001_Y
64908   connect \$33 $and$libresoc.v:42770$1002_Y
64909   connect \$35 $or$libresoc.v:42771$1003_Y
64910   connect \$37 $not$libresoc.v:42772$1004_Y
64911   connect \$3 $and$libresoc.v:42773$1005_Y
64912   connect \$39 $or$libresoc.v:42774$1006_Y
64913   connect \$41 $not$libresoc.v:42775$1007_Y
64914   connect \$43 $and$libresoc.v:42776$1008_Y
64915   connect \$45 $and$libresoc.v:42777$1009_Y
64916   connect \$47 $not$libresoc.v:42778$1010_Y
64917   connect \$49 $and$libresoc.v:42779$1011_Y
64918   connect \$51 $not$libresoc.v:42780$1012_Y
64919   connect \$5 $or$libresoc.v:42781$1013_Y
64920   connect \$7 $not$libresoc.v:42782$1014_Y
64921   connect \a_stall_i 1'0
64922   connect \f_stall_i 1'0
64923 end
64924 attribute \src "libresoc.v:43024.1-45737.10"
64925 attribute \cells_not_processed 1
64926 attribute \nmigen.hierarchy "test_issuer.ti.jtag"
64927 attribute \generator "nMigen"
64928 module \jtag
64929   attribute \src "libresoc.v:45169.3-45195.6"
64930   wire $0\TAP_bus__tdo[0:0]
64931   attribute \src "libresoc.v:44817.3-44832.6"
64932   wire $0\TAP_tdo[0:0]
64933   attribute \src "libresoc.v:45330.3-45362.6"
64934   wire width 4 $0\dmi0__addr_i$next[3:0]$1482
64935   attribute \src "libresoc.v:44720.3-44721.41"
64936   wire width 4 $0\dmi0__addr_i[3:0]
64937   attribute \src "libresoc.v:45416.3-45442.6"
64938   wire width 64 $0\dmi0__din$next[63:0]$1495
64939   attribute \src "libresoc.v:44716.3-44717.35"
64940   wire width 64 $0\dmi0__din[63:0]
64941   attribute \src "libresoc.v:45019.3-45035.6"
64942   wire $0\dmi0_addrsr__oe$next[0:0]$1419
64943   attribute \src "libresoc.v:44748.3-44749.47"
64944   wire $0\dmi0_addrsr__oe[0:0]
64945   attribute \src "libresoc.v:45036.3-45056.6"
64946   wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1423
64947   attribute \src "libresoc.v:44746.3-44747.47"
64948   wire width 8 $0\dmi0_addrsr_reg[7:0]
64949   attribute \src "libresoc.v:45001.3-45009.6"
64950   wire $0\dmi0_addrsr_update_core$next[0:0]$1413
64951   attribute \src "libresoc.v:44752.3-44753.63"
64952   wire $0\dmi0_addrsr_update_core[0:0]
64953   attribute \src "libresoc.v:45010.3-45018.6"
64954   wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1416
64955   attribute \src "libresoc.v:44750.3-44751.73"
64956   wire $0\dmi0_addrsr_update_core_prev[0:0]
64957   attribute \src "libresoc.v:45443.3-45463.6"
64958   wire width 64 $0\dmi0_datasr__i$next[63:0]$1500
64959   attribute \src "libresoc.v:44714.3-44715.45"
64960   wire width 64 $0\dmi0_datasr__i[63:0]
64961   attribute \src "libresoc.v:45075.3-45091.6"
64962   wire width 2 $0\dmi0_datasr__oe$next[1:0]$1434
64963   attribute \src "libresoc.v:44740.3-44741.47"
64964   wire width 2 $0\dmi0_datasr__oe[1:0]
64965   attribute \src "libresoc.v:45092.3-45112.6"
64966   wire width 64 $0\dmi0_datasr_reg$next[63:0]$1438
64967   attribute \src "libresoc.v:44738.3-44739.47"
64968   wire width 64 $0\dmi0_datasr_reg[63:0]
64969   attribute \src "libresoc.v:45057.3-45065.6"
64970   wire $0\dmi0_datasr_update_core$next[0:0]$1428
64971   attribute \src "libresoc.v:44744.3-44745.63"
64972   wire $0\dmi0_datasr_update_core[0:0]
64973   attribute \src "libresoc.v:45066.3-45074.6"
64974   wire $0\dmi0_datasr_update_core_prev$next[0:0]$1431
64975   attribute \src "libresoc.v:44742.3-44743.73"
64976   wire $0\dmi0_datasr_update_core_prev[0:0]
64977   attribute \src "libresoc.v:45363.3-45415.6"
64978   wire width 3 $0\fsm_state$503$next[2:0]$1488
64979   attribute \src "libresoc.v:44718.3-44719.45"
64980   wire width 3 $0\fsm_state$503[2:0]$1334
64981   attribute \src "libresoc.v:43670.13-43670.35"
64982   wire width 3 $0\fsm_state$503[2:0]$1534
64983   attribute \src "libresoc.v:45229.3-45281.6"
64984   wire width 3 $0\fsm_state$next[2:0]$1465
64985   attribute \src "libresoc.v:44726.3-44727.35"
64986   wire width 3 $0\fsm_state[2:0]
64987   attribute \src "libresoc.v:43025.7-43025.20"
64988   wire $0\initial[0:0]
64989   attribute \src "libresoc.v:45511.3-45531.6"
64990   wire width 154 $0\io_bd$next[153:0]$1517
64991   attribute \src "libresoc.v:44778.3-44779.27"
64992   wire width 154 $0\io_bd[153:0]
64993   attribute \src "libresoc.v:45493.3-45510.6"
64994   wire width 154 $0\io_sr$next[153:0]$1513
64995   attribute \src "libresoc.v:44780.3-44781.27"
64996   wire width 154 $0\io_sr[153:0]
64997   attribute \src "libresoc.v:45196.3-45228.6"
64998   wire width 29 $0\jtag_wb__adr$next[28:0]$1459
64999   attribute \src "libresoc.v:44728.3-44729.41"
65000   wire width 29 $0\jtag_wb__adr[28:0]
65001   attribute \src "libresoc.v:45282.3-45308.6"
65002   wire width 64 $0\jtag_wb__dat_w$next[63:0]$1472
65003   attribute \src "libresoc.v:44724.3-44725.45"
65004   wire width 64 $0\jtag_wb__dat_w[63:0]
65005   attribute \src "libresoc.v:44907.3-44923.6"
65006   wire $0\jtag_wb_addrsr__oe$next[0:0]$1389
65007   attribute \src "libresoc.v:44764.3-44765.53"
65008   wire $0\jtag_wb_addrsr__oe[0:0]
65009   attribute \src "libresoc.v:44924.3-44944.6"
65010   wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1393
65011   attribute \src "libresoc.v:44762.3-44763.53"
65012   wire width 29 $0\jtag_wb_addrsr_reg[28:0]
65013   attribute \src "libresoc.v:44889.3-44897.6"
65014   wire $0\jtag_wb_addrsr_update_core$next[0:0]$1383
65015   attribute \src "libresoc.v:44768.3-44769.69"
65016   wire $0\jtag_wb_addrsr_update_core[0:0]
65017   attribute \src "libresoc.v:44898.3-44906.6"
65018   wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386
65019   attribute \src "libresoc.v:44766.3-44767.79"
65020   wire $0\jtag_wb_addrsr_update_core_prev[0:0]
65021   attribute \src "libresoc.v:45309.3-45329.6"
65022   wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1477
65023   attribute \src "libresoc.v:44722.3-44723.51"
65024   wire width 64 $0\jtag_wb_datasr__i[63:0]
65025   attribute \src "libresoc.v:44963.3-44979.6"
65026   wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1404
65027   attribute \src "libresoc.v:44756.3-44757.53"
65028   wire width 2 $0\jtag_wb_datasr__oe[1:0]
65029   attribute \src "libresoc.v:44980.3-45000.6"
65030   wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1408
65031   attribute \src "libresoc.v:44754.3-44755.53"
65032   wire width 64 $0\jtag_wb_datasr_reg[63:0]
65033   attribute \src "libresoc.v:44945.3-44953.6"
65034   wire $0\jtag_wb_datasr_update_core$next[0:0]$1398
65035   attribute \src "libresoc.v:44760.3-44761.69"
65036   wire $0\jtag_wb_datasr_update_core[0:0]
65037   attribute \src "libresoc.v:44954.3-44962.6"
65038   wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401
65039   attribute \src "libresoc.v:44758.3-44759.79"
65040   wire $0\jtag_wb_datasr_update_core_prev[0:0]
65041   attribute \src "libresoc.v:44851.3-44867.6"
65042   wire $0\sr0__oe$next[0:0]$1374
65043   attribute \src "libresoc.v:44772.3-44773.31"
65044   wire $0\sr0__oe[0:0]
65045   attribute \src "libresoc.v:44868.3-44888.6"
65046   wire width 3 $0\sr0_reg$next[2:0]$1378
65047   attribute \src "libresoc.v:44770.3-44771.31"
65048   wire width 3 $0\sr0_reg[2:0]
65049   attribute \src "libresoc.v:44833.3-44841.6"
65050   wire $0\sr0_update_core$next[0:0]$1368
65051   attribute \src "libresoc.v:44776.3-44777.47"
65052   wire $0\sr0_update_core[0:0]
65053   attribute \src "libresoc.v:44842.3-44850.6"
65054   wire $0\sr0_update_core_prev$next[0:0]$1371
65055   attribute \src "libresoc.v:44774.3-44775.57"
65056   wire $0\sr0_update_core_prev[0:0]
65057   attribute \src "libresoc.v:45483.3-45492.6"
65058   wire width 2 $0\sr5__i[1:0]
65059   attribute \src "libresoc.v:45131.3-45147.6"
65060   wire $0\sr5__oe$next[0:0]$1449
65061   attribute \src "libresoc.v:44732.3-44733.31"
65062   wire $0\sr5__oe[0:0]
65063   attribute \src "libresoc.v:45148.3-45168.6"
65064   wire width 2 $0\sr5_reg$next[1:0]$1453
65065   attribute \src "libresoc.v:44730.3-44731.31"
65066   wire width 2 $0\sr5_reg[1:0]
65067   attribute \src "libresoc.v:45113.3-45121.6"
65068   wire $0\sr5_update_core$next[0:0]$1443
65069   attribute \src "libresoc.v:44736.3-44737.47"
65070   wire $0\sr5_update_core[0:0]
65071   attribute \src "libresoc.v:45122.3-45130.6"
65072   wire $0\sr5_update_core_prev$next[0:0]$1446
65073   attribute \src "libresoc.v:44734.3-44735.57"
65074   wire $0\sr5_update_core_prev[0:0]
65075   attribute \src "libresoc.v:45464.3-45482.6"
65076   wire $0\wb_dcache_en$next[0:0]$1505
65077   attribute \src "libresoc.v:44712.3-44713.41"
65078   wire $0\wb_dcache_en[0:0]
65079   attribute \src "libresoc.v:45464.3-45482.6"
65080   wire $0\wb_icache_en$next[0:0]$1506
65081   attribute \src "libresoc.v:44710.3-44711.41"
65082   wire $0\wb_icache_en[0:0]
65083   attribute \src "libresoc.v:45169.3-45195.6"
65084   wire $1\TAP_bus__tdo[0:0]
65085   attribute \src "libresoc.v:44817.3-44832.6"
65086   wire $1\TAP_tdo[0:0]
65087   attribute \src "libresoc.v:45330.3-45362.6"
65088   wire width 4 $1\dmi0__addr_i$next[3:0]$1483
65089   attribute \src "libresoc.v:43583.13-43583.32"
65090   wire width 4 $1\dmi0__addr_i[3:0]
65091   attribute \src "libresoc.v:45416.3-45442.6"
65092   wire width 64 $1\dmi0__din$next[63:0]$1496
65093   attribute \src "libresoc.v:43588.14-43588.46"
65094   wire width 64 $1\dmi0__din[63:0]
65095   attribute \src "libresoc.v:45019.3-45035.6"
65096   wire $1\dmi0_addrsr__oe$next[0:0]$1420
65097   attribute \src "libresoc.v:43602.7-43602.29"
65098   wire $1\dmi0_addrsr__oe[0:0]
65099   attribute \src "libresoc.v:45036.3-45056.6"
65100   wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1424
65101   attribute \src "libresoc.v:43610.13-43610.36"
65102   wire width 8 $1\dmi0_addrsr_reg[7:0]
65103   attribute \src "libresoc.v:45001.3-45009.6"
65104   wire $1\dmi0_addrsr_update_core$next[0:0]$1414
65105   attribute \src "libresoc.v:43618.7-43618.37"
65106   wire $1\dmi0_addrsr_update_core[0:0]
65107   attribute \src "libresoc.v:45010.3-45018.6"
65108   wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1417
65109   attribute \src "libresoc.v:43622.7-43622.42"
65110   wire $1\dmi0_addrsr_update_core_prev[0:0]
65111   attribute \src "libresoc.v:45443.3-45463.6"
65112   wire width 64 $1\dmi0_datasr__i$next[63:0]$1501
65113   attribute \src "libresoc.v:43626.14-43626.51"
65114   wire width 64 $1\dmi0_datasr__i[63:0]
65115   attribute \src "libresoc.v:45075.3-45091.6"
65116   wire width 2 $1\dmi0_datasr__oe$next[1:0]$1435
65117   attribute \src "libresoc.v:43632.13-43632.35"
65118   wire width 2 $1\dmi0_datasr__oe[1:0]
65119   attribute \src "libresoc.v:45092.3-45112.6"
65120   wire width 64 $1\dmi0_datasr_reg$next[63:0]$1439
65121   attribute \src "libresoc.v:43640.14-43640.52"
65122   wire width 64 $1\dmi0_datasr_reg[63:0]
65123   attribute \src "libresoc.v:45057.3-45065.6"
65124   wire $1\dmi0_datasr_update_core$next[0:0]$1429
65125   attribute \src "libresoc.v:43648.7-43648.37"
65126   wire $1\dmi0_datasr_update_core[0:0]
65127   attribute \src "libresoc.v:45066.3-45074.6"
65128   wire $1\dmi0_datasr_update_core_prev$next[0:0]$1432
65129   attribute \src "libresoc.v:43652.7-43652.42"
65130   wire $1\dmi0_datasr_update_core_prev[0:0]
65131   attribute \src "libresoc.v:45363.3-45415.6"
65132   wire width 3 $1\fsm_state$503$next[2:0]$1489
65133   attribute \src "libresoc.v:45229.3-45281.6"
65134   wire width 3 $1\fsm_state$next[2:0]$1466
65135   attribute \src "libresoc.v:43668.13-43668.29"
65136   wire width 3 $1\fsm_state[2:0]
65137   attribute \src "libresoc.v:45511.3-45531.6"
65138   wire width 154 $1\io_bd$next[153:0]$1518
65139   attribute \src "libresoc.v:43868.15-43868.67"
65140   wire width 154 $1\io_bd[153:0]
65141   attribute \src "libresoc.v:45493.3-45510.6"
65142   wire width 154 $1\io_sr$next[153:0]$1514
65143   attribute \src "libresoc.v:43880.15-43880.67"
65144   wire width 154 $1\io_sr[153:0]
65145   attribute \src "libresoc.v:45196.3-45228.6"
65146   wire width 29 $1\jtag_wb__adr$next[28:0]$1460
65147   attribute \src "libresoc.v:43889.14-43889.41"
65148   wire width 29 $1\jtag_wb__adr[28:0]
65149   attribute \src "libresoc.v:45282.3-45308.6"
65150   wire width 64 $1\jtag_wb__dat_w$next[63:0]$1473
65151   attribute \src "libresoc.v:43898.14-43898.51"
65152   wire width 64 $1\jtag_wb__dat_w[63:0]
65153   attribute \src "libresoc.v:44907.3-44923.6"
65154   wire $1\jtag_wb_addrsr__oe$next[0:0]$1390
65155   attribute \src "libresoc.v:43912.7-43912.32"
65156   wire $1\jtag_wb_addrsr__oe[0:0]
65157   attribute \src "libresoc.v:44924.3-44944.6"
65158   wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1394
65159   attribute \src "libresoc.v:43920.14-43920.47"
65160   wire width 29 $1\jtag_wb_addrsr_reg[28:0]
65161   attribute \src "libresoc.v:44889.3-44897.6"
65162   wire $1\jtag_wb_addrsr_update_core$next[0:0]$1384
65163   attribute \src "libresoc.v:43928.7-43928.40"
65164   wire $1\jtag_wb_addrsr_update_core[0:0]
65165   attribute \src "libresoc.v:44898.3-44906.6"
65166   wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387
65167   attribute \src "libresoc.v:43932.7-43932.45"
65168   wire $1\jtag_wb_addrsr_update_core_prev[0:0]
65169   attribute \src "libresoc.v:45309.3-45329.6"
65170   wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1478
65171   attribute \src "libresoc.v:43936.14-43936.54"
65172   wire width 64 $1\jtag_wb_datasr__i[63:0]
65173   attribute \src "libresoc.v:44963.3-44979.6"
65174   wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1405
65175   attribute \src "libresoc.v:43942.13-43942.38"
65176   wire width 2 $1\jtag_wb_datasr__oe[1:0]
65177   attribute \src "libresoc.v:44980.3-45000.6"
65178   wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1409
65179   attribute \src "libresoc.v:43950.14-43950.55"
65180   wire width 64 $1\jtag_wb_datasr_reg[63:0]
65181   attribute \src "libresoc.v:44945.3-44953.6"
65182   wire $1\jtag_wb_datasr_update_core$next[0:0]$1399
65183   attribute \src "libresoc.v:43958.7-43958.40"
65184   wire $1\jtag_wb_datasr_update_core[0:0]
65185   attribute \src "libresoc.v:44954.3-44962.6"
65186   wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402
65187   attribute \src "libresoc.v:43962.7-43962.45"
65188   wire $1\jtag_wb_datasr_update_core_prev[0:0]
65189   attribute \src "libresoc.v:44851.3-44867.6"
65190   wire $1\sr0__oe$next[0:0]$1375
65191   attribute \src "libresoc.v:44392.7-44392.21"
65192   wire $1\sr0__oe[0:0]
65193   attribute \src "libresoc.v:44868.3-44888.6"
65194   wire width 3 $1\sr0_reg$next[2:0]$1379
65195   attribute \src "libresoc.v:44400.13-44400.27"
65196   wire width 3 $1\sr0_reg[2:0]
65197   attribute \src "libresoc.v:44833.3-44841.6"
65198   wire $1\sr0_update_core$next[0:0]$1369
65199   attribute \src "libresoc.v:44408.7-44408.29"
65200   wire $1\sr0_update_core[0:0]
65201   attribute \src "libresoc.v:44842.3-44850.6"
65202   wire $1\sr0_update_core_prev$next[0:0]$1372
65203   attribute \src "libresoc.v:44412.7-44412.34"
65204   wire $1\sr0_update_core_prev[0:0]
65205   attribute \src "libresoc.v:45483.3-45492.6"
65206   wire width 2 $1\sr5__i[1:0]
65207   attribute \src "libresoc.v:45131.3-45147.6"
65208   wire $1\sr5__oe$next[0:0]$1450
65209   attribute \src "libresoc.v:44422.7-44422.21"
65210   wire $1\sr5__oe[0:0]
65211   attribute \src "libresoc.v:45148.3-45168.6"
65212   wire width 2 $1\sr5_reg$next[1:0]$1454
65213   attribute \src "libresoc.v:44430.13-44430.27"
65214   wire width 2 $1\sr5_reg[1:0]
65215   attribute \src "libresoc.v:45113.3-45121.6"
65216   wire $1\sr5_update_core$next[0:0]$1444
65217   attribute \src "libresoc.v:44438.7-44438.29"
65218   wire $1\sr5_update_core[0:0]
65219   attribute \src "libresoc.v:45122.3-45130.6"
65220   wire $1\sr5_update_core_prev$next[0:0]$1447
65221   attribute \src "libresoc.v:44442.7-44442.34"
65222   wire $1\sr5_update_core_prev[0:0]
65223   attribute \src "libresoc.v:45464.3-45482.6"
65224   wire $1\wb_dcache_en$next[0:0]$1507
65225   attribute \src "libresoc.v:44446.7-44446.26"
65226   wire $1\wb_dcache_en[0:0]
65227   attribute \src "libresoc.v:45464.3-45482.6"
65228   wire $1\wb_icache_en$next[0:0]$1508
65229   attribute \src "libresoc.v:44451.7-44451.26"
65230   wire $1\wb_icache_en[0:0]
65231   attribute \src "libresoc.v:45330.3-45362.6"
65232   wire width 4 $2\dmi0__addr_i$next[3:0]$1484
65233   attribute \src "libresoc.v:45416.3-45442.6"
65234   wire width 64 $2\dmi0__din$next[63:0]$1497
65235   attribute \src "libresoc.v:45019.3-45035.6"
65236   wire $2\dmi0_addrsr__oe$next[0:0]$1421
65237   attribute \src "libresoc.v:45036.3-45056.6"
65238   wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1425
65239   attribute \src "libresoc.v:45443.3-45463.6"
65240   wire width 64 $2\dmi0_datasr__i$next[63:0]$1502
65241   attribute \src "libresoc.v:45075.3-45091.6"
65242   wire width 2 $2\dmi0_datasr__oe$next[1:0]$1436
65243   attribute \src "libresoc.v:45092.3-45112.6"
65244   wire width 64 $2\dmi0_datasr_reg$next[63:0]$1440
65245   attribute \src "libresoc.v:45363.3-45415.6"
65246   wire width 3 $2\fsm_state$503$next[2:0]$1490
65247   attribute \src "libresoc.v:45229.3-45281.6"
65248   wire width 3 $2\fsm_state$next[2:0]$1467
65249   attribute \src "libresoc.v:45511.3-45531.6"
65250   wire width 154 $2\io_bd$next[153:0]$1519
65251   attribute \src "libresoc.v:45493.3-45510.6"
65252   wire width 154 $2\io_sr$next[153:0]$1515
65253   attribute \src "libresoc.v:45196.3-45228.6"
65254   wire width 29 $2\jtag_wb__adr$next[28:0]$1461
65255   attribute \src "libresoc.v:45282.3-45308.6"
65256   wire width 64 $2\jtag_wb__dat_w$next[63:0]$1474
65257   attribute \src "libresoc.v:44907.3-44923.6"
65258   wire $2\jtag_wb_addrsr__oe$next[0:0]$1391
65259   attribute \src "libresoc.v:44924.3-44944.6"
65260   wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1395
65261   attribute \src "libresoc.v:45309.3-45329.6"
65262   wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1479
65263   attribute \src "libresoc.v:44963.3-44979.6"
65264   wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1406
65265   attribute \src "libresoc.v:44980.3-45000.6"
65266   wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1410
65267   attribute \src "libresoc.v:44851.3-44867.6"
65268   wire $2\sr0__oe$next[0:0]$1376
65269   attribute \src "libresoc.v:44868.3-44888.6"
65270   wire width 3 $2\sr0_reg$next[2:0]$1380
65271   attribute \src "libresoc.v:45131.3-45147.6"
65272   wire $2\sr5__oe$next[0:0]$1451
65273   attribute \src "libresoc.v:45148.3-45168.6"
65274   wire width 2 $2\sr5_reg$next[1:0]$1455
65275   attribute \src "libresoc.v:45464.3-45482.6"
65276   wire $2\wb_dcache_en$next[0:0]$1509
65277   attribute \src "libresoc.v:45464.3-45482.6"
65278   wire $2\wb_icache_en$next[0:0]$1510
65279   attribute \src "libresoc.v:45330.3-45362.6"
65280   wire width 4 $3\dmi0__addr_i$next[3:0]$1485
65281   attribute \src "libresoc.v:45416.3-45442.6"
65282   wire width 64 $3\dmi0__din$next[63:0]$1498
65283   attribute \src "libresoc.v:45036.3-45056.6"
65284   wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1426
65285   attribute \src "libresoc.v:45443.3-45463.6"
65286   wire width 64 $3\dmi0_datasr__i$next[63:0]$1503
65287   attribute \src "libresoc.v:45092.3-45112.6"
65288   wire width 64 $3\dmi0_datasr_reg$next[63:0]$1441
65289   attribute \src "libresoc.v:45363.3-45415.6"
65290   wire width 3 $3\fsm_state$503$next[2:0]$1491
65291   attribute \src "libresoc.v:45229.3-45281.6"
65292   wire width 3 $3\fsm_state$next[2:0]$1468
65293   attribute \src "libresoc.v:45196.3-45228.6"
65294   wire width 29 $3\jtag_wb__adr$next[28:0]$1462
65295   attribute \src "libresoc.v:45282.3-45308.6"
65296   wire width 64 $3\jtag_wb__dat_w$next[63:0]$1475
65297   attribute \src "libresoc.v:44924.3-44944.6"
65298   wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$1396
65299   attribute \src "libresoc.v:45309.3-45329.6"
65300   wire width 64 $3\jtag_wb_datasr__i$next[63:0]$1480
65301   attribute \src "libresoc.v:44980.3-45000.6"
65302   wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$1411
65303   attribute \src "libresoc.v:44868.3-44888.6"
65304   wire width 3 $3\sr0_reg$next[2:0]$1381
65305   attribute \src "libresoc.v:45148.3-45168.6"
65306   wire width 2 $3\sr5_reg$next[1:0]$1456
65307   attribute \src "libresoc.v:45330.3-45362.6"
65308   wire width 4 $4\dmi0__addr_i$next[3:0]$1486
65309   attribute \src "libresoc.v:45363.3-45415.6"
65310   wire width 3 $4\fsm_state$503$next[2:0]$1492
65311   attribute \src "libresoc.v:45229.3-45281.6"
65312   wire width 3 $4\fsm_state$next[2:0]$1469
65313   attribute \src "libresoc.v:45196.3-45228.6"
65314   wire width 29 $4\jtag_wb__adr$next[28:0]$1463
65315   attribute \src "libresoc.v:45363.3-45415.6"
65316   wire width 3 $5\fsm_state$503$next[2:0]$1493
65317   attribute \src "libresoc.v:45229.3-45281.6"
65318   wire width 3 $5\fsm_state$next[2:0]$1470
65319   attribute \src "libresoc.v:44674.19-44674.112"
65320   wire width 30 $add$libresoc.v:44674$1292_Y
65321   attribute \src "libresoc.v:44676.19-44676.112"
65322   wire width 30 $add$libresoc.v:44676$1294_Y
65323   attribute \src "libresoc.v:44682.19-44682.112"
65324   wire width 5 $add$libresoc.v:44682$1301_Y
65325   attribute \src "libresoc.v:44683.19-44683.112"
65326   wire width 5 $add$libresoc.v:44683$1302_Y
65327   attribute \src "libresoc.v:44498.18-44498.112"
65328   wire $and$libresoc.v:44498$1116_Y
65329   attribute \src "libresoc.v:44565.18-44565.108"
65330   wire $and$libresoc.v:44565$1183_Y
65331   attribute \src "libresoc.v:44576.18-44576.110"
65332   wire $and$libresoc.v:44576$1194_Y
65333   attribute \src "libresoc.v:44604.19-44604.110"
65334   wire $and$libresoc.v:44604$1222_Y
65335   attribute \src "libresoc.v:44607.19-44607.114"
65336   wire $and$libresoc.v:44607$1225_Y
65337   attribute \src "libresoc.v:44610.19-44610.112"
65338   wire $and$libresoc.v:44610$1228_Y
65339   attribute \src "libresoc.v:44612.19-44612.113"
65340   wire $and$libresoc.v:44612$1230_Y
65341   attribute \src "libresoc.v:44614.19-44614.121"
65342   wire $and$libresoc.v:44614$1232_Y
65343   attribute \src "libresoc.v:44617.19-44617.114"
65344   wire $and$libresoc.v:44617$1235_Y
65345   attribute \src "libresoc.v:44619.19-44619.112"
65346   wire $and$libresoc.v:44619$1237_Y
65347   attribute \src "libresoc.v:44623.19-44623.113"
65348   wire $and$libresoc.v:44623$1241_Y
65349   attribute \src "libresoc.v:44625.19-44625.132"
65350   wire $and$libresoc.v:44625$1243_Y
65351   attribute \src "libresoc.v:44629.19-44629.114"
65352   wire $and$libresoc.v:44629$1247_Y
65353   attribute \src "libresoc.v:44631.19-44631.112"
65354   wire $and$libresoc.v:44631$1249_Y
65355   attribute \src "libresoc.v:44634.19-44634.113"
65356   wire $and$libresoc.v:44634$1252_Y
65357   attribute \src "libresoc.v:44636.19-44636.132"
65358   wire $and$libresoc.v:44636$1254_Y
65359   attribute \src "libresoc.v:44639.19-44639.114"
65360   wire $and$libresoc.v:44639$1257_Y
65361   attribute \src "libresoc.v:44641.19-44641.112"
65362   wire $and$libresoc.v:44641$1259_Y
65363   attribute \src "libresoc.v:44643.18-44643.108"
65364   wire $and$libresoc.v:44643$1261_Y
65365   attribute \src "libresoc.v:44644.19-44644.113"
65366   wire $and$libresoc.v:44644$1262_Y
65367   attribute \src "libresoc.v:44646.19-44646.129"
65368   wire $and$libresoc.v:44646$1264_Y
65369   attribute \src "libresoc.v:44650.19-44650.114"
65370   wire $and$libresoc.v:44650$1268_Y
65371   attribute \src "libresoc.v:44652.19-44652.112"
65372   wire $and$libresoc.v:44652$1270_Y
65373   attribute \src "libresoc.v:44654.18-44654.111"
65374   wire $and$libresoc.v:44654$1272_Y
65375   attribute \src "libresoc.v:44655.19-44655.113"
65376   wire $and$libresoc.v:44655$1273_Y
65377   attribute \src "libresoc.v:44657.19-44657.129"
65378   wire $and$libresoc.v:44657$1275_Y
65379   attribute \src "libresoc.v:44660.19-44660.114"
65380   wire $and$libresoc.v:44660$1278_Y
65381   attribute \src "libresoc.v:44662.19-44662.112"
65382   wire $and$libresoc.v:44662$1280_Y
65383   attribute \src "libresoc.v:44664.19-44664.113"
65384   wire $and$libresoc.v:44664$1282_Y
65385   attribute \src "libresoc.v:44667.19-44667.121"
65386   wire $and$libresoc.v:44667$1285_Y
65387   attribute \src "libresoc.v:44699.17-44699.106"
65388   wire $and$libresoc.v:44699$1318_Y
65389   attribute \src "libresoc.v:44454.17-44454.110"
65390   wire $eq$libresoc.v:44454$1072_Y
65391   attribute \src "libresoc.v:44465.18-44465.111"
65392   wire $eq$libresoc.v:44465$1083_Y
65393   attribute \src "libresoc.v:44476.18-44476.111"
65394   wire $eq$libresoc.v:44476$1094_Y
65395   attribute \src "libresoc.v:44509.17-44509.110"
65396   wire $eq$libresoc.v:44509$1127_Y
65397   attribute \src "libresoc.v:44510.18-44510.111"
65398   wire $eq$libresoc.v:44510$1128_Y
65399   attribute \src "libresoc.v:44521.18-44521.111"
65400   wire $eq$libresoc.v:44521$1139_Y
65401   attribute \src "libresoc.v:44543.18-44543.111"
65402   wire $eq$libresoc.v:44543$1161_Y
65403   attribute \src "libresoc.v:44587.18-44587.111"
65404   wire $eq$libresoc.v:44587$1205_Y
65405   attribute \src "libresoc.v:44598.18-44598.111"
65406   wire $eq$libresoc.v:44598$1216_Y
65407   attribute \src "libresoc.v:44599.19-44599.112"
65408   wire $eq$libresoc.v:44599$1217_Y
65409   attribute \src "libresoc.v:44600.19-44600.112"
65410   wire $eq$libresoc.v:44600$1218_Y
65411   attribute \src "libresoc.v:44602.19-44602.112"
65412   wire $eq$libresoc.v:44602$1220_Y
65413   attribute \src "libresoc.v:44605.19-44605.112"
65414   wire $eq$libresoc.v:44605$1223_Y
65415   attribute \src "libresoc.v:44615.19-44615.112"
65416   wire $eq$libresoc.v:44615$1233_Y
65417   attribute \src "libresoc.v:44620.17-44620.110"
65418   wire $eq$libresoc.v:44620$1238_Y
65419   attribute \src "libresoc.v:44621.18-44621.111"
65420   wire $eq$libresoc.v:44621$1239_Y
65421   attribute \src "libresoc.v:44626.19-44626.112"
65422   wire $eq$libresoc.v:44626$1244_Y
65423   attribute \src "libresoc.v:44627.19-44627.112"
65424   wire $eq$libresoc.v:44627$1245_Y
65425   attribute \src "libresoc.v:44637.19-44637.112"
65426   wire $eq$libresoc.v:44637$1255_Y
65427   attribute \src "libresoc.v:44647.19-44647.112"
65428   wire $eq$libresoc.v:44647$1265_Y
65429   attribute \src "libresoc.v:44648.19-44648.112"
65430   wire $eq$libresoc.v:44648$1266_Y
65431   attribute \src "libresoc.v:44658.19-44658.112"
65432   wire $eq$libresoc.v:44658$1276_Y
65433   attribute \src "libresoc.v:44665.18-44665.111"
65434   wire $eq$libresoc.v:44665$1283_Y
65435   attribute \src "libresoc.v:44668.19-44668.110"
65436   wire $eq$libresoc.v:44668$1286_Y
65437   attribute \src "libresoc.v:44670.19-44670.110"
65438   wire $eq$libresoc.v:44670$1288_Y
65439   attribute \src "libresoc.v:44671.19-44671.110"
65440   wire $eq$libresoc.v:44671$1289_Y
65441   attribute \src "libresoc.v:44673.19-44673.110"
65442   wire $eq$libresoc.v:44673$1291_Y
65443   attribute \src "libresoc.v:44675.18-44675.111"
65444   wire $eq$libresoc.v:44675$1293_Y
65445   attribute \src "libresoc.v:44678.19-44678.116"
65446   wire $eq$libresoc.v:44678$1297_Y
65447   attribute \src "libresoc.v:44679.19-44679.116"
65448   wire $eq$libresoc.v:44679$1298_Y
65449   attribute \src "libresoc.v:44681.19-44681.116"
65450   wire $eq$libresoc.v:44681$1300_Y
65451   attribute \src "libresoc.v:44677.19-44677.106"
65452   wire width 8 $extend$libresoc.v:44677$1295_Y
65453   attribute \src "libresoc.v:44606.19-44606.109"
65454   wire $ne$libresoc.v:44606$1224_Y
65455   attribute \src "libresoc.v:44608.19-44608.109"
65456   wire $ne$libresoc.v:44608$1226_Y
65457   attribute \src "libresoc.v:44611.19-44611.109"
65458   wire $ne$libresoc.v:44611$1229_Y
65459   attribute \src "libresoc.v:44616.19-44616.120"
65460   wire $ne$libresoc.v:44616$1234_Y
65461   attribute \src "libresoc.v:44618.19-44618.120"
65462   wire $ne$libresoc.v:44618$1236_Y
65463   attribute \src "libresoc.v:44622.19-44622.120"
65464   wire $ne$libresoc.v:44622$1240_Y
65465   attribute \src "libresoc.v:44628.19-44628.120"
65466   wire $ne$libresoc.v:44628$1246_Y
65467   attribute \src "libresoc.v:44630.19-44630.120"
65468   wire $ne$libresoc.v:44630$1248_Y
65469   attribute \src "libresoc.v:44633.19-44633.120"
65470   wire $ne$libresoc.v:44633$1251_Y
65471   attribute \src "libresoc.v:44638.19-44638.117"
65472   wire $ne$libresoc.v:44638$1256_Y
65473   attribute \src "libresoc.v:44640.19-44640.117"
65474   wire $ne$libresoc.v:44640$1258_Y
65475   attribute \src "libresoc.v:44642.19-44642.117"
65476   wire $ne$libresoc.v:44642$1260_Y
65477   attribute \src "libresoc.v:44649.19-44649.117"
65478   wire $ne$libresoc.v:44649$1267_Y
65479   attribute \src "libresoc.v:44651.19-44651.117"
65480   wire $ne$libresoc.v:44651$1269_Y
65481   attribute \src "libresoc.v:44653.19-44653.117"
65482   wire $ne$libresoc.v:44653$1271_Y
65483   attribute \src "libresoc.v:44659.19-44659.109"
65484   wire $ne$libresoc.v:44659$1277_Y
65485   attribute \src "libresoc.v:44661.19-44661.109"
65486   wire $ne$libresoc.v:44661$1279_Y
65487   attribute \src "libresoc.v:44663.19-44663.109"
65488   wire $ne$libresoc.v:44663$1281_Y
65489   attribute \src "libresoc.v:44613.19-44613.110"
65490   wire $not$libresoc.v:44613$1231_Y
65491   attribute \src "libresoc.v:44624.19-44624.121"
65492   wire $not$libresoc.v:44624$1242_Y
65493   attribute \src "libresoc.v:44635.19-44635.121"
65494   wire $not$libresoc.v:44635$1253_Y
65495   attribute \src "libresoc.v:44645.19-44645.118"
65496   wire $not$libresoc.v:44645$1263_Y
65497   attribute \src "libresoc.v:44656.19-44656.118"
65498   wire $not$libresoc.v:44656$1274_Y
65499   attribute \src "libresoc.v:44666.19-44666.110"
65500   wire $not$libresoc.v:44666$1284_Y
65501   attribute \src "libresoc.v:44669.19-44669.100"
65502   wire $not$libresoc.v:44669$1287_Y
65503   attribute \src "libresoc.v:44487.18-44487.104"
65504   wire $or$libresoc.v:44487$1105_Y
65505   attribute \src "libresoc.v:44532.18-44532.104"
65506   wire $or$libresoc.v:44532$1150_Y
65507   attribute \src "libresoc.v:44554.18-44554.104"
65508   wire $or$libresoc.v:44554$1172_Y
65509   attribute \src "libresoc.v:44601.19-44601.107"
65510   wire $or$libresoc.v:44601$1219_Y
65511   attribute \src "libresoc.v:44603.19-44603.107"
65512   wire $or$libresoc.v:44603$1221_Y
65513   attribute \src "libresoc.v:44609.18-44609.104"
65514   wire $or$libresoc.v:44609$1227_Y
65515   attribute \src "libresoc.v:44632.18-44632.104"
65516   wire $or$libresoc.v:44632$1250_Y
65517   attribute \src "libresoc.v:44672.19-44672.107"
65518   wire $or$libresoc.v:44672$1290_Y
65519   attribute \src "libresoc.v:44680.19-44680.107"
65520   wire $or$libresoc.v:44680$1299_Y
65521   attribute \src "libresoc.v:44688.17-44688.101"
65522   wire $or$libresoc.v:44688$1307_Y
65523   attribute \src "libresoc.v:44677.19-44677.106"
65524   wire width 8 $pos$libresoc.v:44677$1296_Y
65525   attribute \src "libresoc.v:44455.18-44455.133"
65526   wire $ternary$libresoc.v:44455$1073_Y
65527   attribute \src "libresoc.v:44456.19-44456.133"
65528   wire $ternary$libresoc.v:44456$1074_Y
65529   attribute \src "libresoc.v:44457.19-44457.134"
65530   wire $ternary$libresoc.v:44457$1075_Y
65531   attribute \src "libresoc.v:44458.19-44458.133"
65532   wire $ternary$libresoc.v:44458$1076_Y
65533   attribute \src "libresoc.v:44459.19-44459.132"
65534   wire $ternary$libresoc.v:44459$1077_Y
65535   attribute \src "libresoc.v:44460.19-44460.133"
65536   wire $ternary$libresoc.v:44460$1078_Y
65537   attribute \src "libresoc.v:44461.19-44461.133"
65538   wire $ternary$libresoc.v:44461$1079_Y
65539   attribute \src "libresoc.v:44462.19-44462.132"
65540   wire $ternary$libresoc.v:44462$1080_Y
65541   attribute \src "libresoc.v:44463.19-44463.133"
65542   wire $ternary$libresoc.v:44463$1081_Y
65543   attribute \src "libresoc.v:44464.19-44464.133"
65544   wire $ternary$libresoc.v:44464$1082_Y
65545   attribute \src "libresoc.v:44466.19-44466.132"
65546   wire $ternary$libresoc.v:44466$1084_Y
65547   attribute \src "libresoc.v:44467.19-44467.133"
65548   wire $ternary$libresoc.v:44467$1085_Y
65549   attribute \src "libresoc.v:44468.19-44468.133"
65550   wire $ternary$libresoc.v:44468$1086_Y
65551   attribute \src "libresoc.v:44469.19-44469.132"
65552   wire $ternary$libresoc.v:44469$1087_Y
65553   attribute \src "libresoc.v:44470.19-44470.133"
65554   wire $ternary$libresoc.v:44470$1088_Y
65555   attribute \src "libresoc.v:44471.19-44471.133"
65556   wire $ternary$libresoc.v:44471$1089_Y
65557   attribute \src "libresoc.v:44472.19-44472.132"
65558   wire $ternary$libresoc.v:44472$1090_Y
65559   attribute \src "libresoc.v:44473.19-44473.133"
65560   wire $ternary$libresoc.v:44473$1091_Y
65561   attribute \src "libresoc.v:44474.19-44474.133"
65562   wire $ternary$libresoc.v:44474$1092_Y
65563   attribute \src "libresoc.v:44475.19-44475.132"
65564   wire $ternary$libresoc.v:44475$1093_Y
65565   attribute \src "libresoc.v:44477.19-44477.133"
65566   wire $ternary$libresoc.v:44477$1095_Y
65567   attribute \src "libresoc.v:44478.19-44478.133"
65568   wire $ternary$libresoc.v:44478$1096_Y
65569   attribute \src "libresoc.v:44479.19-44479.132"
65570   wire $ternary$libresoc.v:44479$1097_Y
65571   attribute \src "libresoc.v:44480.19-44480.133"
65572   wire $ternary$libresoc.v:44480$1098_Y
65573   attribute \src "libresoc.v:44481.19-44481.133"
65574   wire $ternary$libresoc.v:44481$1099_Y
65575   attribute \src "libresoc.v:44482.19-44482.132"
65576   wire $ternary$libresoc.v:44482$1100_Y
65577   attribute \src "libresoc.v:44483.19-44483.133"
65578   wire $ternary$libresoc.v:44483$1101_Y
65579   attribute \src "libresoc.v:44484.19-44484.134"
65580   wire $ternary$libresoc.v:44484$1102_Y
65581   attribute \src "libresoc.v:44485.19-44485.135"
65582   wire $ternary$libresoc.v:44485$1103_Y
65583   attribute \src "libresoc.v:44486.19-44486.135"
65584   wire $ternary$libresoc.v:44486$1104_Y
65585   attribute \src "libresoc.v:44488.19-44488.136"
65586   wire $ternary$libresoc.v:44488$1106_Y
65587   attribute \src "libresoc.v:44489.19-44489.134"
65588   wire $ternary$libresoc.v:44489$1107_Y
65589   attribute \src "libresoc.v:44490.19-44490.135"
65590   wire $ternary$libresoc.v:44490$1108_Y
65591   attribute \src "libresoc.v:44491.19-44491.135"
65592   wire $ternary$libresoc.v:44491$1109_Y
65593   attribute \src "libresoc.v:44492.19-44492.136"
65594   wire $ternary$libresoc.v:44492$1110_Y
65595   attribute \src "libresoc.v:44493.19-44493.134"
65596   wire $ternary$libresoc.v:44493$1111_Y
65597   attribute \src "libresoc.v:44494.19-44494.133"
65598   wire $ternary$libresoc.v:44494$1112_Y
65599   attribute \src "libresoc.v:44495.19-44495.134"
65600   wire $ternary$libresoc.v:44495$1113_Y
65601   attribute \src "libresoc.v:44496.19-44496.133"
65602   wire $ternary$libresoc.v:44496$1114_Y
65603   attribute \src "libresoc.v:44497.19-44497.130"
65604   wire $ternary$libresoc.v:44497$1115_Y
65605   attribute \src "libresoc.v:44499.19-44499.130"
65606   wire $ternary$libresoc.v:44499$1117_Y
65607   attribute \src "libresoc.v:44500.19-44500.133"
65608   wire $ternary$libresoc.v:44500$1118_Y
65609   attribute \src "libresoc.v:44501.19-44501.132"
65610   wire $ternary$libresoc.v:44501$1119_Y
65611   attribute \src "libresoc.v:44502.19-44502.133"
65612   wire $ternary$libresoc.v:44502$1120_Y
65613   attribute \src "libresoc.v:44503.19-44503.132"
65614   wire $ternary$libresoc.v:44503$1121_Y
65615   attribute \src "libresoc.v:44504.19-44504.135"
65616   wire $ternary$libresoc.v:44504$1122_Y
65617   attribute \src "libresoc.v:44505.19-44505.134"
65618   wire $ternary$libresoc.v:44505$1123_Y
65619   attribute \src "libresoc.v:44506.19-44506.135"
65620   wire $ternary$libresoc.v:44506$1124_Y
65621   attribute \src "libresoc.v:44507.19-44507.135"
65622   wire $ternary$libresoc.v:44507$1125_Y
65623   attribute \src "libresoc.v:44508.19-44508.134"
65624   wire $ternary$libresoc.v:44508$1126_Y
65625   attribute \src "libresoc.v:44511.19-44511.135"
65626   wire $ternary$libresoc.v:44511$1129_Y
65627   attribute \src "libresoc.v:44512.19-44512.135"
65628   wire $ternary$libresoc.v:44512$1130_Y
65629   attribute \src "libresoc.v:44513.19-44513.134"
65630   wire $ternary$libresoc.v:44513$1131_Y
65631   attribute \src "libresoc.v:44514.19-44514.135"
65632   wire $ternary$libresoc.v:44514$1132_Y
65633   attribute \src "libresoc.v:44515.19-44515.135"
65634   wire $ternary$libresoc.v:44515$1133_Y
65635   attribute \src "libresoc.v:44516.19-44516.134"
65636   wire $ternary$libresoc.v:44516$1134_Y
65637   attribute \src "libresoc.v:44517.19-44517.135"
65638   wire $ternary$libresoc.v:44517$1135_Y
65639   attribute \src "libresoc.v:44518.19-44518.133"
65640   wire $ternary$libresoc.v:44518$1136_Y
65641   attribute \src "libresoc.v:44519.19-44519.134"
65642   wire $ternary$libresoc.v:44519$1137_Y
65643   attribute \src "libresoc.v:44520.19-44520.133"
65644   wire $ternary$libresoc.v:44520$1138_Y
65645   attribute \src "libresoc.v:44522.19-44522.134"
65646   wire $ternary$libresoc.v:44522$1140_Y
65647   attribute \src "libresoc.v:44523.19-44523.134"
65648   wire $ternary$libresoc.v:44523$1141_Y
65649   attribute \src "libresoc.v:44524.19-44524.133"
65650   wire $ternary$libresoc.v:44524$1142_Y
65651   attribute \src "libresoc.v:44525.19-44525.134"
65652   wire $ternary$libresoc.v:44525$1143_Y
65653   attribute \src "libresoc.v:44526.19-44526.134"
65654   wire $ternary$libresoc.v:44526$1144_Y
65655   attribute \src "libresoc.v:44527.19-44527.133"
65656   wire $ternary$libresoc.v:44527$1145_Y
65657   attribute \src "libresoc.v:44528.19-44528.134"
65658   wire $ternary$libresoc.v:44528$1146_Y
65659   attribute \src "libresoc.v:44529.19-44529.134"
65660   wire $ternary$libresoc.v:44529$1147_Y
65661   attribute \src "libresoc.v:44530.19-44530.133"
65662   wire $ternary$libresoc.v:44530$1148_Y
65663   attribute \src "libresoc.v:44531.19-44531.134"
65664   wire $ternary$libresoc.v:44531$1149_Y
65665   attribute \src "libresoc.v:44533.19-44533.134"
65666   wire $ternary$libresoc.v:44533$1151_Y
65667   attribute \src "libresoc.v:44534.19-44534.133"
65668   wire $ternary$libresoc.v:44534$1152_Y
65669   attribute \src "libresoc.v:44535.19-44535.134"
65670   wire $ternary$libresoc.v:44535$1153_Y
65671   attribute \src "libresoc.v:44536.19-44536.134"
65672   wire $ternary$libresoc.v:44536$1154_Y
65673   attribute \src "libresoc.v:44537.19-44537.133"
65674   wire $ternary$libresoc.v:44537$1155_Y
65675   attribute \src "libresoc.v:44538.19-44538.134"
65676   wire $ternary$libresoc.v:44538$1156_Y
65677   attribute \src "libresoc.v:44539.19-44539.135"
65678   wire $ternary$libresoc.v:44539$1157_Y
65679   attribute \src "libresoc.v:44540.19-44540.134"
65680   wire $ternary$libresoc.v:44540$1158_Y
65681   attribute \src "libresoc.v:44541.19-44541.135"
65682   wire $ternary$libresoc.v:44541$1159_Y
65683   attribute \src "libresoc.v:44542.19-44542.135"
65684   wire $ternary$libresoc.v:44542$1160_Y
65685   attribute \src "libresoc.v:44544.19-44544.134"
65686   wire $ternary$libresoc.v:44544$1162_Y
65687   attribute \src "libresoc.v:44545.19-44545.135"
65688   wire $ternary$libresoc.v:44545$1163_Y
65689   attribute \src "libresoc.v:44546.19-44546.133"
65690   wire $ternary$libresoc.v:44546$1164_Y
65691   attribute \src "libresoc.v:44547.19-44547.133"
65692   wire $ternary$libresoc.v:44547$1165_Y
65693   attribute \src "libresoc.v:44548.19-44548.133"
65694   wire $ternary$libresoc.v:44548$1166_Y
65695   attribute \src "libresoc.v:44549.19-44549.133"
65696   wire $ternary$libresoc.v:44549$1167_Y
65697   attribute \src "libresoc.v:44550.19-44550.133"
65698   wire $ternary$libresoc.v:44550$1168_Y
65699   attribute \src "libresoc.v:44551.19-44551.133"
65700   wire $ternary$libresoc.v:44551$1169_Y
65701   attribute \src "libresoc.v:44552.19-44552.133"
65702   wire $ternary$libresoc.v:44552$1170_Y
65703   attribute \src "libresoc.v:44553.19-44553.133"
65704   wire $ternary$libresoc.v:44553$1171_Y
65705   attribute \src "libresoc.v:44555.19-44555.133"
65706   wire $ternary$libresoc.v:44555$1173_Y
65707   attribute \src "libresoc.v:44556.19-44556.133"
65708   wire $ternary$libresoc.v:44556$1174_Y
65709   attribute \src "libresoc.v:44557.19-44557.134"
65710   wire $ternary$libresoc.v:44557$1175_Y
65711   attribute \src "libresoc.v:44558.19-44558.134"
65712   wire $ternary$libresoc.v:44558$1176_Y
65713   attribute \src "libresoc.v:44559.19-44559.135"
65714   wire $ternary$libresoc.v:44559$1177_Y
65715   attribute \src "libresoc.v:44560.19-44560.133"
65716   wire $ternary$libresoc.v:44560$1178_Y
65717   attribute \src "libresoc.v:44561.19-44561.135"
65718   wire $ternary$libresoc.v:44561$1179_Y
65719   attribute \src "libresoc.v:44562.19-44562.135"
65720   wire $ternary$libresoc.v:44562$1180_Y
65721   attribute \src "libresoc.v:44563.19-44563.134"
65722   wire $ternary$libresoc.v:44563$1181_Y
65723   attribute \src "libresoc.v:44564.19-44564.134"
65724   wire $ternary$libresoc.v:44564$1182_Y
65725   attribute \src "libresoc.v:44566.19-44566.134"
65726   wire $ternary$libresoc.v:44566$1184_Y
65727   attribute \src "libresoc.v:44567.19-44567.134"
65728   wire $ternary$libresoc.v:44567$1185_Y
65729   attribute \src "libresoc.v:44568.19-44568.134"
65730   wire $ternary$libresoc.v:44568$1186_Y
65731   attribute \src "libresoc.v:44569.19-44569.135"
65732   wire $ternary$libresoc.v:44569$1187_Y
65733   attribute \src "libresoc.v:44570.19-44570.134"
65734   wire $ternary$libresoc.v:44570$1188_Y
65735   attribute \src "libresoc.v:44571.19-44571.135"
65736   wire $ternary$libresoc.v:44571$1189_Y
65737   attribute \src "libresoc.v:44572.19-44572.135"
65738   wire $ternary$libresoc.v:44572$1190_Y
65739   attribute \src "libresoc.v:44573.19-44573.134"
65740   wire $ternary$libresoc.v:44573$1191_Y
65741   attribute \src "libresoc.v:44574.19-44574.135"
65742   wire $ternary$libresoc.v:44574$1192_Y
65743   attribute \src "libresoc.v:44575.19-44575.135"
65744   wire $ternary$libresoc.v:44575$1193_Y
65745   attribute \src "libresoc.v:44577.19-44577.134"
65746   wire $ternary$libresoc.v:44577$1195_Y
65747   attribute \src "libresoc.v:44578.19-44578.135"
65748   wire $ternary$libresoc.v:44578$1196_Y
65749   attribute \src "libresoc.v:44579.19-44579.136"
65750   wire $ternary$libresoc.v:44579$1197_Y
65751   attribute \src "libresoc.v:44580.19-44580.135"
65752   wire $ternary$libresoc.v:44580$1198_Y
65753   attribute \src "libresoc.v:44581.19-44581.136"
65754   wire $ternary$libresoc.v:44581$1199_Y
65755   attribute \src "libresoc.v:44582.19-44582.136"
65756   wire $ternary$libresoc.v:44582$1200_Y
65757   attribute \src "libresoc.v:44583.19-44583.135"
65758   wire $ternary$libresoc.v:44583$1201_Y
65759   attribute \src "libresoc.v:44584.19-44584.136"
65760   wire $ternary$libresoc.v:44584$1202_Y
65761   attribute \src "libresoc.v:44585.19-44585.136"
65762   wire $ternary$libresoc.v:44585$1203_Y
65763   attribute \src "libresoc.v:44586.19-44586.135"
65764   wire $ternary$libresoc.v:44586$1204_Y
65765   attribute \src "libresoc.v:44588.19-44588.136"
65766   wire $ternary$libresoc.v:44588$1206_Y
65767   attribute \src "libresoc.v:44589.19-44589.136"
65768   wire $ternary$libresoc.v:44589$1207_Y
65769   attribute \src "libresoc.v:44590.19-44590.135"
65770   wire $ternary$libresoc.v:44590$1208_Y
65771   attribute \src "libresoc.v:44591.19-44591.136"
65772   wire $ternary$libresoc.v:44591$1209_Y
65773   attribute \src "libresoc.v:44592.19-44592.136"
65774   wire $ternary$libresoc.v:44592$1210_Y
65775   attribute \src "libresoc.v:44593.19-44593.135"
65776   wire $ternary$libresoc.v:44593$1211_Y
65777   attribute \src "libresoc.v:44594.19-44594.136"
65778   wire $ternary$libresoc.v:44594$1212_Y
65779   attribute \src "libresoc.v:44595.19-44595.136"
65780   wire $ternary$libresoc.v:44595$1213_Y
65781   attribute \src "libresoc.v:44596.19-44596.135"
65782   wire $ternary$libresoc.v:44596$1214_Y
65783   attribute \src "libresoc.v:44597.19-44597.136"
65784   wire $ternary$libresoc.v:44597$1215_Y
65785   attribute \src "libresoc.v:44684.18-44684.130"
65786   wire $ternary$libresoc.v:44684$1303_Y
65787   attribute \src "libresoc.v:44685.18-44685.130"
65788   wire $ternary$libresoc.v:44685$1304_Y
65789   attribute \src "libresoc.v:44686.18-44686.130"
65790   wire $ternary$libresoc.v:44686$1305_Y
65791   attribute \src "libresoc.v:44687.18-44687.131"
65792   wire $ternary$libresoc.v:44687$1306_Y
65793   attribute \src "libresoc.v:44689.18-44689.130"
65794   wire $ternary$libresoc.v:44689$1308_Y
65795   attribute \src "libresoc.v:44690.18-44690.131"
65796   wire $ternary$libresoc.v:44690$1309_Y
65797   attribute \src "libresoc.v:44691.18-44691.131"
65798   wire $ternary$libresoc.v:44691$1310_Y
65799   attribute \src "libresoc.v:44692.18-44692.130"
65800   wire $ternary$libresoc.v:44692$1311_Y
65801   attribute \src "libresoc.v:44693.18-44693.131"
65802   wire $ternary$libresoc.v:44693$1312_Y
65803   attribute \src "libresoc.v:44694.18-44694.132"
65804   wire $ternary$libresoc.v:44694$1313_Y
65805   attribute \src "libresoc.v:44695.18-44695.132"
65806   wire $ternary$libresoc.v:44695$1314_Y
65807   attribute \src "libresoc.v:44696.18-44696.133"
65808   wire $ternary$libresoc.v:44696$1315_Y
65809   attribute \src "libresoc.v:44697.18-44697.133"
65810   wire $ternary$libresoc.v:44697$1316_Y
65811   attribute \src "libresoc.v:44698.18-44698.132"
65812   wire $ternary$libresoc.v:44698$1317_Y
65813   attribute \src "libresoc.v:44700.18-44700.133"
65814   wire $ternary$libresoc.v:44700$1319_Y
65815   attribute \src "libresoc.v:44701.18-44701.133"
65816   wire $ternary$libresoc.v:44701$1320_Y
65817   attribute \src "libresoc.v:44702.18-44702.132"
65818   wire $ternary$libresoc.v:44702$1321_Y
65819   attribute \src "libresoc.v:44703.18-44703.133"
65820   wire $ternary$libresoc.v:44703$1322_Y
65821   attribute \src "libresoc.v:44704.18-44704.133"
65822   wire $ternary$libresoc.v:44704$1323_Y
65823   attribute \src "libresoc.v:44705.18-44705.132"
65824   wire $ternary$libresoc.v:44705$1324_Y
65825   attribute \src "libresoc.v:44706.18-44706.133"
65826   wire $ternary$libresoc.v:44706$1325_Y
65827   attribute \src "libresoc.v:44707.18-44707.133"
65828   wire $ternary$libresoc.v:44707$1326_Y
65829   attribute \src "libresoc.v:44708.18-44708.132"
65830   wire $ternary$libresoc.v:44708$1327_Y
65831   attribute \src "libresoc.v:44709.18-44709.133"
65832   wire $ternary$libresoc.v:44709$1328_Y
65833   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
65834   wire \$1
65835   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65836   wire \$101
65837   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65838   wire \$103
65839   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65840   wire \$105
65841   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65842   wire \$107
65843   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65844   wire \$109
65845   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
65846   wire \$11
65847   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65848   wire \$111
65849   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65850   wire \$113
65851   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65852   wire \$115
65853   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65854   wire \$117
65855   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65856   wire \$119
65857   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65858   wire \$121
65859   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65860   wire \$123
65861   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65862   wire \$125
65863   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65864   wire \$127
65865   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65866   wire \$129
65867   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
65868   wire \$13
65869   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65870   wire \$131
65871   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65872   wire \$133
65873   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65874   wire \$135
65875   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65876   wire \$137
65877   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65878   wire \$139
65879   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65880   wire \$141
65881   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65882   wire \$143
65883   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65884   wire \$145
65885   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65886   wire \$147
65887   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65888   wire \$149
65889   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
65890   wire \$15
65891   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65892   wire \$151
65893   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65894   wire \$153
65895   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65896   wire \$155
65897   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65898   wire \$157
65899   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
65900   wire \$159
65901   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65902   wire \$161
65903   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65904   wire \$163
65905   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65906   wire \$165
65907   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
65908   wire \$167
65909   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65910   wire \$169
65911   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
65912   wire \$17
65913   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65914   wire \$171
65915   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65916   wire \$173
65917   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65918   wire \$175
65919   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65920   wire \$177
65921   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65922   wire \$179
65923   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65924   wire \$181
65925   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65926   wire \$183
65927   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65928   wire \$185
65929   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65930   wire \$187
65931   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65932   wire \$189
65933   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
65934   wire \$19
65935   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65936   wire \$191
65937   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65938   wire \$193
65939   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65940   wire \$195
65941   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65942   wire \$197
65943   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65944   wire \$199
65945   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65946   wire \$201
65947   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65948   wire \$203
65949   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65950   wire \$205
65951   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65952   wire \$207
65953   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65954   wire \$209
65955   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
65956   wire \$21
65957   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65958   wire \$211
65959   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
65960   wire \$213
65961   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65962   wire \$215
65963   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65964   wire \$217
65965   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65966   wire \$219
65967   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65968   wire \$221
65969   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65970   wire \$223
65971   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65972   wire \$225
65973   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65974   wire \$227
65975   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65976   wire \$229
65977   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
65978   wire \$23
65979   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65980   wire \$231
65981   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65982   wire \$233
65983   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65984   wire \$235
65985   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65986   wire \$237
65987   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65988   wire \$239
65989   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65990   wire \$241
65991   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65992   wire \$243
65993   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
65994   wire \$245
65995   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
65996   wire \$247
65997   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
65998   wire \$249
65999   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
66000   wire \$25
66001   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66002   wire \$251
66003   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66004   wire \$253
66005   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66006   wire \$255
66007   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66008   wire \$257
66009   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66010   wire \$259
66011   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66012   wire \$261
66013   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66014   wire \$263
66015   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66016   wire \$265
66017   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66018   wire \$267
66019   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66020   wire \$269
66021   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
66022   wire \$27
66023   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66024   wire \$271
66025   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66026   wire \$273
66027   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66028   wire \$275
66029   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66030   wire \$277
66031   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66032   wire \$279
66033   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66034   wire \$281
66035   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66036   wire \$283
66037   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66038   wire \$285
66039   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66040   wire \$287
66041   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66042   wire \$289
66043   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
66044   wire \$29
66045   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66046   wire \$291
66047   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66048   wire \$293
66049   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66050   wire \$295
66051   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66052   wire \$297
66053   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66054   wire \$299
66055   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
66056   wire \$3
66057   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66058   wire \$301
66059   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
66060   wire \$303
66061   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66062   wire \$305
66063   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66064   wire \$307
66065   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66066   wire \$309
66067   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402"
66068   wire \$31
66069   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66070   wire \$311
66071   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66072   wire \$313
66073   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66074   wire \$315
66075   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66076   wire \$317
66077   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66078   wire \$319
66079   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66080   wire \$321
66081   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66082   wire \$323
66083   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66084   wire \$325
66085   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66086   wire \$327
66087   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66088   wire \$329
66089   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
66090   wire \$33
66091   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66092   wire \$331
66093   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66094   wire \$333
66095   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66096   wire \$335
66097   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66098   wire \$337
66099   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66100   wire \$339
66101   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66102   wire \$341
66103   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66104   wire \$343
66105   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66106   wire \$345
66107   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66108   wire \$347
66109   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66110   wire \$349
66111   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
66112   wire \$35
66113   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66114   wire \$351
66115   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66116   wire \$353
66117   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66118   wire \$355
66119   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66120   wire \$357
66121   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
66122   wire \$359
66123   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
66124   wire \$361
66125   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
66126   wire \$363
66127   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
66128   wire \$365
66129   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
66130   wire \$367
66131   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
66132   wire \$369
66133   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
66134   wire \$37
66135   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66136   wire \$371
66137   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66138   wire \$373
66139   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66140   wire \$375
66141   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66142   wire \$377
66143   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66144   wire \$379
66145   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66146   wire \$381
66147   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66148   wire \$383
66149   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66150   wire \$385
66151   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66152   wire \$387
66153   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66154   wire \$389
66155   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
66156   wire \$39
66157   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66158   wire \$391
66159   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66160   wire \$393
66161   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66162   wire \$395
66163   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66164   wire \$397
66165   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66166   wire \$399
66167   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66168   wire \$401
66169   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66170   wire \$403
66171   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66172   wire \$405
66173   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66174   wire \$407
66175   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66176   wire \$409
66177   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
66178   wire \$41
66179   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66180   wire \$411
66181   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66182   wire \$413
66183   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66184   wire \$415
66185   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66186   wire \$417
66187   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66188   wire \$419
66189   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66190   wire \$421
66191   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66192   wire \$423
66193   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66194   wire \$425
66195   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66196   wire \$427
66197   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66198   wire \$429
66199   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
66200   wire \$43
66201   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66202   wire \$431
66203   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66204   wire \$433
66205   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66206   wire \$435
66207   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66208   wire \$437
66209   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66210   wire \$439
66211   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66212   wire \$441
66213   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66214   wire \$443
66215   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66216   wire \$445
66217   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66218   wire \$447
66219   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66220   wire \$449
66221   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403"
66222   wire \$45
66223   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66224   wire \$451
66225   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66226   wire \$453
66227   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66228   wire \$455
66229   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66230   wire \$457
66231   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66232   wire \$459
66233   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66234   wire \$461
66235   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66236   wire \$463
66237   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
66238   wire \$465
66239   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66240   wire \$467
66241   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
66242   wire \$469
66243   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404"
66244   wire \$47
66245   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66246   wire \$471
66247   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
66248   wire \$473
66249   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66250   wire \$475
66251   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
66252   wire \$477
66253   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66254   wire \$479
66255   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
66256   wire \$481
66257   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
66258   wire \$483
66259   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
66260   wire \$484
66261   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
66262   wire \$487
66263   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
66264   wire \$489
66265   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405"
66266   wire \$49
66267   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
66268   wire \$491
66269   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792"
66270   wire \$493
66271   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761"
66272   wire width 30 \$495
66273   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761"
66274   wire width 30 \$496
66275   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786"
66276   wire width 30 \$498
66277   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786"
66278   wire width 30 \$499
66279   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
66280   wire \$5
66281   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66282   wire width 8 \$501
66283   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
66284   wire \$504
66285   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
66286   wire \$506
66287   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
66288   wire \$508
66289   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
66290   wire \$51
66291   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524"
66292   wire \$510
66293   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494"
66294   wire width 5 \$512
66295   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494"
66296   wire width 5 \$513
66297   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518"
66298   wire width 5 \$515
66299   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518"
66300   wire width 5 \$516
66301   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
66302   wire \$53
66303   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
66304   wire \$55
66305   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66306   wire \$57
66307   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66308   wire \$59
66309   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66310   wire \$61
66311   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66312   wire \$63
66313   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66314   wire \$65
66315   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66316   wire \$67
66317   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66318   wire \$69
66319   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
66320   wire \$7
66321   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66322   wire \$71
66323   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66324   wire \$73
66325   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66326   wire \$75
66327   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66328   wire \$77
66329   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66330   wire \$79
66331   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66332   wire \$81
66333   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66334   wire \$83
66335   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66336   wire \$85
66337   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66338   wire \$87
66339   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66340   wire \$89
66341   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
66342   wire \$9
66343   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66344   wire \$91
66345   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66346   wire \$93
66347   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
66348   wire \$95
66349   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
66350   wire \$97
66351   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
66352   wire \$99
66353   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
66354   wire input 327 \TAP_bus__tck
66355   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
66356   wire input 163 \TAP_bus__tdi
66357   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
66358   wire output 318 \TAP_bus__tdo
66359   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
66360   wire input 328 \TAP_bus__tms
66361   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414"
66362   wire \TAP_tdo
66363   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
66364   wire \_fsm_capture
66365   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
66366   wire \_fsm_isdr
66367   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
66368   wire \_fsm_isir
66369   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
66370   wire \_fsm_shift
66371   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
66372   wire \_fsm_update
66373   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225"
66374   wire \_idblock_TAP_id_tdo
66375   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375"
66376   wire \_idblock_id_bypass
66377   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
66378   wire \_idblock_select_id
66379   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
66380   wire width 4 \_irblock_ir
66381   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
66382   wire \_irblock_tdo
66383   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
66384   wire input 329 \clk
66385   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66386   wire input 6 \dmi0__ack_o
66387   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66388   wire width 4 output 2 \dmi0__addr_i
66389   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66390   wire width 4 \dmi0__addr_i$next
66391   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66392   wire width 64 output 5 \dmi0__din
66393   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66394   wire width 64 \dmi0__din$next
66395   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66396   wire width 64 input 7 \dmi0__dout
66397   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66398   wire output 3 \dmi0__req_i
66399   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
66400   wire output 4 \dmi0__we_i
66401   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471"
66402   wire width 8 \dmi0_addrsr__i
66403   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471"
66404   wire width 8 \dmi0_addrsr__o
66405   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471"
66406   wire \dmi0_addrsr__oe
66407   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471"
66408   wire \dmi0_addrsr__oe$next
66409   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
66410   wire \dmi0_addrsr_capture
66411   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645"
66412   wire \dmi0_addrsr_isir
66413   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66414   wire width 8 \dmi0_addrsr_reg
66415   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66416   wire width 8 \dmi0_addrsr_reg$next
66417   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
66418   wire \dmi0_addrsr_shift
66419   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
66420   wire \dmi0_addrsr_update
66421   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66422   wire \dmi0_addrsr_update_core
66423   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66424   wire \dmi0_addrsr_update_core$next
66425   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66426   wire \dmi0_addrsr_update_core_prev
66427   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66428   wire \dmi0_addrsr_update_core_prev$next
66429   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473"
66430   wire width 64 \dmi0_datasr__i
66431   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473"
66432   wire width 64 \dmi0_datasr__i$next
66433   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473"
66434   wire width 64 \dmi0_datasr__o
66435   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473"
66436   wire width 2 \dmi0_datasr__oe
66437   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473"
66438   wire width 2 \dmi0_datasr__oe$next
66439   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
66440   wire \dmi0_datasr_capture
66441   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645"
66442   wire width 2 \dmi0_datasr_isir
66443   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66444   wire width 64 \dmi0_datasr_reg
66445   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66446   wire width 64 \dmi0_datasr_reg$next
66447   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
66448   wire \dmi0_datasr_shift
66449   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
66450   wire \dmi0_datasr_update
66451   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66452   wire \dmi0_datasr_update_core
66453   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66454   wire \dmi0_datasr_update_core$next
66455   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66456   wire \dmi0_datasr_update_core_prev
66457   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66458   wire \dmi0_datasr_update_core_prev$next
66459   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66460   wire output 164 \eint_0__core__i
66461   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66462   wire input 9 \eint_0__pad__i
66463   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66464   wire output 165 \eint_1__core__i
66465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66466   wire input 10 \eint_1__pad__i
66467   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66468   wire output 166 \eint_2__core__i
66469   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66470   wire input 11 \eint_2__pad__i
66471   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
66472   wire width 3 \fsm_state
66473   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
66474   wire width 3 \fsm_state$503
66475   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
66476   wire width 3 \fsm_state$503$next
66477   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
66478   wire width 3 \fsm_state$next
66479   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66480   wire output 173 \gpio_e10__core__i
66481   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66482   wire input 19 \gpio_e10__core__o
66483   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66484   wire input 20 \gpio_e10__core__oe
66485   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66486   wire input 18 \gpio_e10__pad__i
66487   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66488   wire output 174 \gpio_e10__pad__o
66489   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66490   wire output 175 \gpio_e10__pad__oe
66491   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66492   wire output 176 \gpio_e11__core__i
66493   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66494   wire input 22 \gpio_e11__core__o
66495   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66496   wire input 23 \gpio_e11__core__oe
66497   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66498   wire input 21 \gpio_e11__pad__i
66499   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66500   wire output 177 \gpio_e11__pad__o
66501   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66502   wire output 178 \gpio_e11__pad__oe
66503   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66504   wire output 179 \gpio_e12__core__i
66505   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66506   wire input 25 \gpio_e12__core__o
66507   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66508   wire input 26 \gpio_e12__core__oe
66509   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66510   wire input 24 \gpio_e12__pad__i
66511   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66512   wire output 180 \gpio_e12__pad__o
66513   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66514   wire output 181 \gpio_e12__pad__oe
66515   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66516   wire output 182 \gpio_e13__core__i
66517   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66518   wire input 28 \gpio_e13__core__o
66519   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66520   wire input 29 \gpio_e13__core__oe
66521   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66522   wire input 27 \gpio_e13__pad__i
66523   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66524   wire output 183 \gpio_e13__pad__o
66525   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66526   wire output 184 \gpio_e13__pad__oe
66527   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66528   wire output 185 \gpio_e14__core__i
66529   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66530   wire input 31 \gpio_e14__core__o
66531   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66532   wire input 32 \gpio_e14__core__oe
66533   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66534   wire input 30 \gpio_e14__pad__i
66535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66536   wire output 186 \gpio_e14__pad__o
66537   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66538   wire output 187 \gpio_e14__pad__oe
66539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66540   wire output 188 \gpio_e15__core__i
66541   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66542   wire input 34 \gpio_e15__core__o
66543   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66544   wire input 35 \gpio_e15__core__oe
66545   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66546   wire input 33 \gpio_e15__pad__i
66547   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66548   wire output 189 \gpio_e15__pad__o
66549   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66550   wire output 190 \gpio_e15__pad__oe
66551   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66552   wire output 167 \gpio_e8__core__i
66553   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66554   wire input 13 \gpio_e8__core__o
66555   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66556   wire input 14 \gpio_e8__core__oe
66557   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66558   wire input 12 \gpio_e8__pad__i
66559   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66560   wire output 168 \gpio_e8__pad__o
66561   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66562   wire output 169 \gpio_e8__pad__oe
66563   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66564   wire output 170 \gpio_e9__core__i
66565   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66566   wire input 16 \gpio_e9__core__o
66567   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66568   wire input 17 \gpio_e9__core__oe
66569   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66570   wire input 15 \gpio_e9__pad__i
66571   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66572   wire output 171 \gpio_e9__pad__o
66573   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66574   wire output 172 \gpio_e9__pad__oe
66575   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66576   wire output 191 \gpio_s0__core__i
66577   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66578   wire input 37 \gpio_s0__core__o
66579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66580   wire input 38 \gpio_s0__core__oe
66581   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66582   wire input 36 \gpio_s0__pad__i
66583   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66584   wire output 192 \gpio_s0__pad__o
66585   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66586   wire output 193 \gpio_s0__pad__oe
66587   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66588   wire output 194 \gpio_s1__core__i
66589   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66590   wire input 40 \gpio_s1__core__o
66591   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66592   wire input 41 \gpio_s1__core__oe
66593   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66594   wire input 39 \gpio_s1__pad__i
66595   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66596   wire output 195 \gpio_s1__pad__o
66597   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66598   wire output 196 \gpio_s1__pad__oe
66599   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66600   wire output 197 \gpio_s2__core__i
66601   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66602   wire input 43 \gpio_s2__core__o
66603   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66604   wire input 44 \gpio_s2__core__oe
66605   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66606   wire input 42 \gpio_s2__pad__i
66607   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66608   wire output 198 \gpio_s2__pad__o
66609   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66610   wire output 199 \gpio_s2__pad__oe
66611   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66612   wire output 200 \gpio_s3__core__i
66613   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66614   wire input 46 \gpio_s3__core__o
66615   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66616   wire input 47 \gpio_s3__core__oe
66617   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66618   wire input 45 \gpio_s3__pad__i
66619   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66620   wire output 201 \gpio_s3__pad__o
66621   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66622   wire output 202 \gpio_s3__pad__oe
66623   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66624   wire output 203 \gpio_s4__core__i
66625   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66626   wire input 49 \gpio_s4__core__o
66627   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66628   wire input 50 \gpio_s4__core__oe
66629   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66630   wire input 48 \gpio_s4__pad__i
66631   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66632   wire output 204 \gpio_s4__pad__o
66633   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66634   wire output 205 \gpio_s4__pad__oe
66635   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66636   wire output 206 \gpio_s5__core__i
66637   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66638   wire input 52 \gpio_s5__core__o
66639   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66640   wire input 53 \gpio_s5__core__oe
66641   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66642   wire input 51 \gpio_s5__pad__i
66643   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66644   wire output 207 \gpio_s5__pad__o
66645   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66646   wire output 208 \gpio_s5__pad__oe
66647   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66648   wire output 209 \gpio_s6__core__i
66649   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66650   wire input 55 \gpio_s6__core__o
66651   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66652   wire input 56 \gpio_s6__core__oe
66653   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66654   wire input 54 \gpio_s6__pad__i
66655   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66656   wire output 210 \gpio_s6__pad__o
66657   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66658   wire output 211 \gpio_s6__pad__oe
66659   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66660   wire output 212 \gpio_s7__core__i
66661   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66662   wire input 58 \gpio_s7__core__o
66663   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66664   wire input 59 \gpio_s7__core__oe
66665   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66666   wire input 57 \gpio_s7__pad__i
66667   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66668   wire output 213 \gpio_s7__pad__o
66669   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66670   wire output 214 \gpio_s7__pad__oe
66671   attribute \src "libresoc.v:43025.7-43025.15"
66672   wire \initial
66673   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549"
66674   wire width 154 \io_bd
66675   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549"
66676   wire width 154 \io_bd$next
66677   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395"
66678   wire \io_bd2core
66679   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
66680   wire \io_bd2io
66681   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391"
66682   wire \io_capture
66683   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
66684   wire \io_shift
66685   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548"
66686   wire width 154 \io_sr
66687   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548"
66688   wire width 154 \io_sr$next
66689   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
66690   wire \io_update
66691   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66692   wire input 325 \jtag_wb__ack
66693   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66694   wire width 29 output 319 \jtag_wb__adr
66695   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66696   wire width 29 \jtag_wb__adr$next
66697   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66698   wire output 321 \jtag_wb__cyc
66699   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66700   wire width 64 input 326 \jtag_wb__dat_r
66701   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66702   wire width 64 output 324 \jtag_wb__dat_w
66703   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66704   wire width 64 \jtag_wb__dat_w$next
66705   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66706   wire output 320 \jtag_wb__sel
66707   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66708   wire output 322 \jtag_wb__stb
66709   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
66710   wire output 323 \jtag_wb__we
66711   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731"
66712   wire width 29 \jtag_wb_addrsr__i
66713   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731"
66714   wire width 29 \jtag_wb_addrsr__o
66715   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731"
66716   wire \jtag_wb_addrsr__oe
66717   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731"
66718   wire \jtag_wb_addrsr__oe$next
66719   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
66720   wire \jtag_wb_addrsr_capture
66721   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645"
66722   wire \jtag_wb_addrsr_isir
66723   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66724   wire width 29 \jtag_wb_addrsr_reg
66725   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66726   wire width 29 \jtag_wb_addrsr_reg$next
66727   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
66728   wire \jtag_wb_addrsr_shift
66729   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
66730   wire \jtag_wb_addrsr_update
66731   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66732   wire \jtag_wb_addrsr_update_core
66733   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66734   wire \jtag_wb_addrsr_update_core$next
66735   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66736   wire \jtag_wb_addrsr_update_core_prev
66737   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66738   wire \jtag_wb_addrsr_update_core_prev$next
66739   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735"
66740   wire width 64 \jtag_wb_datasr__i
66741   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735"
66742   wire width 64 \jtag_wb_datasr__i$next
66743   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735"
66744   wire width 64 \jtag_wb_datasr__o
66745   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735"
66746   wire width 2 \jtag_wb_datasr__oe
66747   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735"
66748   wire width 2 \jtag_wb_datasr__oe$next
66749   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
66750   wire \jtag_wb_datasr_capture
66751   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645"
66752   wire width 2 \jtag_wb_datasr_isir
66753   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66754   wire width 64 \jtag_wb_datasr_reg
66755   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
66756   wire width 64 \jtag_wb_datasr_reg$next
66757   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
66758   wire \jtag_wb_datasr_shift
66759   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
66760   wire \jtag_wb_datasr_update
66761   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66762   wire \jtag_wb_datasr_update_core
66763   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
66764   wire \jtag_wb_datasr_update_core$next
66765   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66766   wire \jtag_wb_datasr_update_core_prev
66767   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
66768   wire \jtag_wb_datasr_update_core_prev$next
66769   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66770   wire input 60 \mspi0_clk__core__o
66771   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66772   wire output 215 \mspi0_clk__pad__o
66773   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66774   wire input 61 \mspi0_cs_n__core__o
66775   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66776   wire output 216 \mspi0_cs_n__pad__o
66777   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66778   wire output 218 \mspi0_miso__core__i
66779   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66780   wire input 63 \mspi0_miso__pad__i
66781   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66782   wire input 62 \mspi0_mosi__core__o
66783   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66784   wire output 217 \mspi0_mosi__pad__o
66785   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66786   wire input 64 \mspi1_clk__core__o
66787   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66788   wire output 219 \mspi1_clk__pad__o
66789   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66790   wire input 65 \mspi1_cs_n__core__o
66791   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66792   wire output 220 \mspi1_cs_n__pad__o
66793   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66794   wire output 222 \mspi1_miso__core__i
66795   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66796   wire input 67 \mspi1_miso__pad__i
66797   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66798   wire input 66 \mspi1_mosi__core__o
66799   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66800   wire output 221 \mspi1_mosi__pad__o
66801   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66802   wire input 71 \mtwi_scl__core__o
66803   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66804   wire output 226 \mtwi_scl__pad__o
66805   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66806   wire output 223 \mtwi_sda__core__i
66807   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66808   wire input 69 \mtwi_sda__core__o
66809   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66810   wire input 70 \mtwi_sda__core__oe
66811   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66812   wire input 68 \mtwi_sda__pad__i
66813   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66814   wire output 224 \mtwi_sda__pad__o
66815   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66816   wire output 225 \mtwi_sda__pad__oe
66817   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
66818   wire \negjtag_clk
66819   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
66820   wire \negjtag_rst
66821   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
66822   wire \posjtag_clk
66823   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
66824   wire \posjtag_rst
66825   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66826   wire input 72 \pwm_0__core__o
66827   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66828   wire output 227 \pwm_0__pad__o
66829   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66830   wire input 73 \pwm_1__core__o
66831   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66832   wire output 228 \pwm_1__pad__o
66833   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
66834   wire input 1 \rst
66835   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66836   wire input 77 \sd0_clk__core__o
66837   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66838   wire output 232 \sd0_clk__pad__o
66839   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66840   wire output 229 \sd0_cmd__core__i
66841   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66842   wire input 75 \sd0_cmd__core__o
66843   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66844   wire input 76 \sd0_cmd__core__oe
66845   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66846   wire input 74 \sd0_cmd__pad__i
66847   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66848   wire output 230 \sd0_cmd__pad__o
66849   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66850   wire output 231 \sd0_cmd__pad__oe
66851   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66852   wire output 233 \sd0_data0__core__i
66853   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66854   wire input 79 \sd0_data0__core__o
66855   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66856   wire input 80 \sd0_data0__core__oe
66857   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66858   wire input 78 \sd0_data0__pad__i
66859   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66860   wire output 234 \sd0_data0__pad__o
66861   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66862   wire output 235 \sd0_data0__pad__oe
66863   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66864   wire output 236 \sd0_data1__core__i
66865   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66866   wire input 82 \sd0_data1__core__o
66867   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66868   wire input 83 \sd0_data1__core__oe
66869   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66870   wire input 81 \sd0_data1__pad__i
66871   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66872   wire output 237 \sd0_data1__pad__o
66873   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66874   wire output 238 \sd0_data1__pad__oe
66875   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66876   wire output 239 \sd0_data2__core__i
66877   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66878   wire input 85 \sd0_data2__core__o
66879   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66880   wire input 86 \sd0_data2__core__oe
66881   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66882   wire input 84 \sd0_data2__pad__i
66883   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66884   wire output 240 \sd0_data2__pad__o
66885   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66886   wire output 241 \sd0_data2__pad__oe
66887   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66888   wire output 242 \sd0_data3__core__i
66889   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66890   wire input 88 \sd0_data3__core__o
66891   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66892   wire input 89 \sd0_data3__core__oe
66893   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66894   wire input 87 \sd0_data3__pad__i
66895   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66896   wire output 243 \sd0_data3__pad__o
66897   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66898   wire output 244 \sd0_data3__pad__oe
66899   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66900   wire input 115 \sdr_a_0__core__o
66901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66902   wire output 270 \sdr_a_0__pad__o
66903   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66904   wire input 133 \sdr_a_10__core__o
66905   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66906   wire output 288 \sdr_a_10__pad__o
66907   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66908   wire input 134 \sdr_a_11__core__o
66909   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66910   wire output 289 \sdr_a_11__pad__o
66911   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66912   wire input 135 \sdr_a_12__core__o
66913   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66914   wire output 290 \sdr_a_12__pad__o
66915   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66916   wire input 116 \sdr_a_1__core__o
66917   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66918   wire output 271 \sdr_a_1__pad__o
66919   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66920   wire input 117 \sdr_a_2__core__o
66921   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66922   wire output 272 \sdr_a_2__pad__o
66923   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66924   wire input 118 \sdr_a_3__core__o
66925   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66926   wire output 273 \sdr_a_3__pad__o
66927   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66928   wire input 119 \sdr_a_4__core__o
66929   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66930   wire output 274 \sdr_a_4__pad__o
66931   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66932   wire input 120 \sdr_a_5__core__o
66933   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66934   wire output 275 \sdr_a_5__pad__o
66935   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66936   wire input 121 \sdr_a_6__core__o
66937   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66938   wire output 276 \sdr_a_6__pad__o
66939   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66940   wire input 122 \sdr_a_7__core__o
66941   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66942   wire output 277 \sdr_a_7__pad__o
66943   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66944   wire input 123 \sdr_a_8__core__o
66945   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66946   wire output 278 \sdr_a_8__pad__o
66947   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66948   wire input 124 \sdr_a_9__core__o
66949   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66950   wire output 279 \sdr_a_9__pad__o
66951   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66952   wire input 125 \sdr_ba_0__core__o
66953   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66954   wire output 280 \sdr_ba_0__pad__o
66955   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66956   wire input 126 \sdr_ba_1__core__o
66957   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66958   wire output 281 \sdr_ba_1__pad__o
66959   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66960   wire input 130 \sdr_cas_n__core__o
66961   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66962   wire output 285 \sdr_cas_n__pad__o
66963   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66964   wire input 128 \sdr_cke__core__o
66965   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66966   wire output 283 \sdr_cke__pad__o
66967   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66968   wire input 127 \sdr_clock__core__o
66969   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66970   wire output 282 \sdr_clock__pad__o
66971   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66972   wire input 132 \sdr_cs_n__core__o
66973   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66974   wire output 287 \sdr_cs_n__pad__o
66975   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66976   wire input 90 \sdr_dm_0__core__o
66977   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66978   wire output 245 \sdr_dm_0__pad__o
66979   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66980   wire output 291 \sdr_dm_1__core__i
66981   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66982   wire input 137 \sdr_dm_1__core__o
66983   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66984   wire input 138 \sdr_dm_1__core__oe
66985   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66986   wire input 136 \sdr_dm_1__pad__i
66987   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66988   wire output 292 \sdr_dm_1__pad__o
66989   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66990   wire output 293 \sdr_dm_1__pad__oe
66991   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66992   wire output 246 \sdr_dq_0__core__i
66993   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66994   wire input 92 \sdr_dq_0__core__o
66995   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66996   wire input 93 \sdr_dq_0__core__oe
66997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
66998   wire input 91 \sdr_dq_0__pad__i
66999   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67000   wire output 247 \sdr_dq_0__pad__o
67001   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67002   wire output 248 \sdr_dq_0__pad__oe
67003   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67004   wire output 300 \sdr_dq_10__core__i
67005   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67006   wire input 146 \sdr_dq_10__core__o
67007   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67008   wire input 147 \sdr_dq_10__core__oe
67009   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67010   wire input 145 \sdr_dq_10__pad__i
67011   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67012   wire output 301 \sdr_dq_10__pad__o
67013   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67014   wire output 302 \sdr_dq_10__pad__oe
67015   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67016   wire output 303 \sdr_dq_11__core__i
67017   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67018   wire input 149 \sdr_dq_11__core__o
67019   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67020   wire input 150 \sdr_dq_11__core__oe
67021   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67022   wire input 148 \sdr_dq_11__pad__i
67023   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67024   wire output 304 \sdr_dq_11__pad__o
67025   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67026   wire output 305 \sdr_dq_11__pad__oe
67027   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67028   wire output 306 \sdr_dq_12__core__i
67029   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67030   wire input 152 \sdr_dq_12__core__o
67031   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67032   wire input 153 \sdr_dq_12__core__oe
67033   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67034   wire input 151 \sdr_dq_12__pad__i
67035   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67036   wire output 307 \sdr_dq_12__pad__o
67037   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67038   wire output 308 \sdr_dq_12__pad__oe
67039   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67040   wire output 309 \sdr_dq_13__core__i
67041   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67042   wire input 155 \sdr_dq_13__core__o
67043   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67044   wire input 156 \sdr_dq_13__core__oe
67045   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67046   wire input 154 \sdr_dq_13__pad__i
67047   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67048   wire output 310 \sdr_dq_13__pad__o
67049   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67050   wire output 311 \sdr_dq_13__pad__oe
67051   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67052   wire output 312 \sdr_dq_14__core__i
67053   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67054   wire input 158 \sdr_dq_14__core__o
67055   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67056   wire input 159 \sdr_dq_14__core__oe
67057   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67058   wire input 157 \sdr_dq_14__pad__i
67059   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67060   wire output 313 \sdr_dq_14__pad__o
67061   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67062   wire output 314 \sdr_dq_14__pad__oe
67063   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67064   wire output 315 \sdr_dq_15__core__i
67065   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67066   wire input 161 \sdr_dq_15__core__o
67067   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67068   wire input 162 \sdr_dq_15__core__oe
67069   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67070   wire input 160 \sdr_dq_15__pad__i
67071   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67072   wire output 316 \sdr_dq_15__pad__o
67073   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67074   wire output 317 \sdr_dq_15__pad__oe
67075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67076   wire output 249 \sdr_dq_1__core__i
67077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67078   wire input 95 \sdr_dq_1__core__o
67079   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67080   wire input 96 \sdr_dq_1__core__oe
67081   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67082   wire input 94 \sdr_dq_1__pad__i
67083   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67084   wire output 250 \sdr_dq_1__pad__o
67085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67086   wire output 251 \sdr_dq_1__pad__oe
67087   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67088   wire output 252 \sdr_dq_2__core__i
67089   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67090   wire input 98 \sdr_dq_2__core__o
67091   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67092   wire input 99 \sdr_dq_2__core__oe
67093   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67094   wire input 97 \sdr_dq_2__pad__i
67095   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67096   wire output 253 \sdr_dq_2__pad__o
67097   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67098   wire output 254 \sdr_dq_2__pad__oe
67099   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67100   wire output 255 \sdr_dq_3__core__i
67101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67102   wire input 101 \sdr_dq_3__core__o
67103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67104   wire input 102 \sdr_dq_3__core__oe
67105   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67106   wire input 100 \sdr_dq_3__pad__i
67107   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67108   wire output 256 \sdr_dq_3__pad__o
67109   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67110   wire output 257 \sdr_dq_3__pad__oe
67111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67112   wire output 258 \sdr_dq_4__core__i
67113   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67114   wire input 104 \sdr_dq_4__core__o
67115   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67116   wire input 105 \sdr_dq_4__core__oe
67117   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67118   wire input 103 \sdr_dq_4__pad__i
67119   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67120   wire output 259 \sdr_dq_4__pad__o
67121   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67122   wire output 260 \sdr_dq_4__pad__oe
67123   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67124   wire output 261 \sdr_dq_5__core__i
67125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67126   wire input 107 \sdr_dq_5__core__o
67127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67128   wire input 108 \sdr_dq_5__core__oe
67129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67130   wire input 106 \sdr_dq_5__pad__i
67131   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67132   wire output 262 \sdr_dq_5__pad__o
67133   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67134   wire output 263 \sdr_dq_5__pad__oe
67135   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67136   wire output 264 \sdr_dq_6__core__i
67137   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67138   wire input 110 \sdr_dq_6__core__o
67139   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67140   wire input 111 \sdr_dq_6__core__oe
67141   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67142   wire input 109 \sdr_dq_6__pad__i
67143   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67144   wire output 265 \sdr_dq_6__pad__o
67145   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67146   wire output 266 \sdr_dq_6__pad__oe
67147   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67148   wire output 267 \sdr_dq_7__core__i
67149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67150   wire input 113 \sdr_dq_7__core__o
67151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67152   wire input 114 \sdr_dq_7__core__oe
67153   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67154   wire input 112 \sdr_dq_7__pad__i
67155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67156   wire output 268 \sdr_dq_7__pad__o
67157   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67158   wire output 269 \sdr_dq_7__pad__oe
67159   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67160   wire output 294 \sdr_dq_8__core__i
67161   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67162   wire input 140 \sdr_dq_8__core__o
67163   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67164   wire input 141 \sdr_dq_8__core__oe
67165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67166   wire input 139 \sdr_dq_8__pad__i
67167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67168   wire output 295 \sdr_dq_8__pad__o
67169   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67170   wire output 296 \sdr_dq_8__pad__oe
67171   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67172   wire output 297 \sdr_dq_9__core__i
67173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67174   wire input 143 \sdr_dq_9__core__o
67175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67176   wire input 144 \sdr_dq_9__core__oe
67177   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67178   wire input 142 \sdr_dq_9__pad__i
67179   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67180   wire output 298 \sdr_dq_9__pad__o
67181   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67182   wire output 299 \sdr_dq_9__pad__oe
67183   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67184   wire input 129 \sdr_ras_n__core__o
67185   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67186   wire output 284 \sdr_ras_n__pad__o
67187   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67188   wire input 131 \sdr_we_n__core__o
67189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
67190   wire output 286 \sdr_we_n__pad__o
67191   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80"
67192   wire width 3 \sr0__i
67193   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80"
67194   wire width 3 \sr0__o
67195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80"
67196   wire \sr0__oe
67197   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80"
67198   wire \sr0__oe$next
67199   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
67200   wire \sr0_capture
67201   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645"
67202   wire \sr0_isir
67203   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
67204   wire width 3 \sr0_reg
67205   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
67206   wire width 3 \sr0_reg$next
67207   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
67208   wire \sr0_shift
67209   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
67210   wire \sr0_update
67211   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
67212   wire \sr0_update_core
67213   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
67214   wire \sr0_update_core$next
67215   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
67216   wire \sr0_update_core_prev
67217   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
67218   wire \sr0_update_core_prev$next
67219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91"
67220   wire width 2 \sr5__i
67221   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91"
67222   wire \sr5__ie
67223   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91"
67224   wire width 2 \sr5__o
67225   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91"
67226   wire \sr5__oe
67227   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91"
67228   wire \sr5__oe$next
67229   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
67230   wire \sr5_capture
67231   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645"
67232   wire \sr5_isir
67233   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
67234   wire width 2 \sr5_reg
67235   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
67236   wire width 2 \sr5_reg$next
67237   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
67238   wire \sr5_shift
67239   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
67240   wire \sr5_update
67241   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
67242   wire \sr5_update_core
67243   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660"
67244   wire \sr5_update_core$next
67245   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
67246   wire \sr5_update_core_prev
67247   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661"
67248   wire \sr5_update_core_prev$next
67249   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
67250   wire \wb_dcache_en
67251   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
67252   wire \wb_dcache_en$next
67253   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92"
67254   wire output 8 \wb_icache_en
67255   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92"
67256   wire \wb_icache_en$next
67257   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761"
67258   cell $add $add$libresoc.v:44674$1292
67259     parameter \A_SIGNED 0
67260     parameter \A_WIDTH 29
67261     parameter \B_SIGNED 0
67262     parameter \B_WIDTH 1
67263     parameter \Y_WIDTH 30
67264     connect \A \jtag_wb__adr
67265     connect \B 1'1
67266     connect \Y $add$libresoc.v:44674$1292_Y
67267   end
67268   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786"
67269   cell $add $add$libresoc.v:44676$1294
67270     parameter \A_SIGNED 0
67271     parameter \A_WIDTH 29
67272     parameter \B_SIGNED 0
67273     parameter \B_WIDTH 1
67274     parameter \Y_WIDTH 30
67275     connect \A \jtag_wb__adr
67276     connect \B 1'1
67277     connect \Y $add$libresoc.v:44676$1294_Y
67278   end
67279   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494"
67280   cell $add $add$libresoc.v:44682$1301
67281     parameter \A_SIGNED 0
67282     parameter \A_WIDTH 4
67283     parameter \B_SIGNED 0
67284     parameter \B_WIDTH 1
67285     parameter \Y_WIDTH 5
67286     connect \A \dmi0__addr_i
67287     connect \B 1'1
67288     connect \Y $add$libresoc.v:44682$1301_Y
67289   end
67290   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518"
67291   cell $add $add$libresoc.v:44683$1302
67292     parameter \A_SIGNED 0
67293     parameter \A_WIDTH 4
67294     parameter \B_SIGNED 0
67295     parameter \B_WIDTH 1
67296     parameter \Y_WIDTH 5
67297     connect \A \dmi0__addr_i
67298     connect \B 1'1
67299     connect \Y $add$libresoc.v:44683$1302_Y
67300   end
67301   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
67302   cell $and $and$libresoc.v:44498$1116
67303     parameter \A_SIGNED 0
67304     parameter \A_WIDTH 1
67305     parameter \B_SIGNED 0
67306     parameter \B_WIDTH 1
67307     parameter \Y_WIDTH 1
67308     connect \A \$15
67309     connect \B \_fsm_capture
67310     connect \Y $and$libresoc.v:44498$1116_Y
67311   end
67312   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
67313   cell $and $and$libresoc.v:44565$1183
67314     parameter \A_SIGNED 0
67315     parameter \A_WIDTH 1
67316     parameter \B_SIGNED 0
67317     parameter \B_WIDTH 1
67318     parameter \Y_WIDTH 1
67319     connect \A \_fsm_isdr
67320     connect \B \$27
67321     connect \Y $and$libresoc.v:44565$1183_Y
67322   end
67323   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402"
67324   cell $and $and$libresoc.v:44576$1194
67325     parameter \A_SIGNED 0
67326     parameter \A_WIDTH 1
67327     parameter \B_SIGNED 0
67328     parameter \B_WIDTH 1
67329     parameter \Y_WIDTH 1
67330     connect \A \$29
67331     connect \B \_fsm_shift
67332     connect \Y $and$libresoc.v:44576$1194_Y
67333   end
67334   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
67335   cell $and $and$libresoc.v:44604$1222
67336     parameter \A_SIGNED 0
67337     parameter \A_WIDTH 1
67338     parameter \B_SIGNED 0
67339     parameter \B_WIDTH 1
67340     parameter \Y_WIDTH 1
67341     connect \A \_fsm_isdr
67342     connect \B \$367
67343     connect \Y $and$libresoc.v:44604$1222_Y
67344   end
67345   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
67346   cell $and $and$libresoc.v:44607$1225
67347     parameter \A_SIGNED 0
67348     parameter \A_WIDTH 1
67349     parameter \B_SIGNED 0
67350     parameter \B_WIDTH 1
67351     parameter \Y_WIDTH 1
67352     connect \A \$373
67353     connect \B \_fsm_capture
67354     connect \Y $and$libresoc.v:44607$1225_Y
67355   end
67356   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
67357   cell $and $and$libresoc.v:44610$1228
67358     parameter \A_SIGNED 0
67359     parameter \A_WIDTH 1
67360     parameter \B_SIGNED 0
67361     parameter \B_WIDTH 1
67362     parameter \Y_WIDTH 1
67363     connect \A \$377
67364     connect \B \_fsm_shift
67365     connect \Y $and$libresoc.v:44610$1228_Y
67366   end
67367   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
67368   cell $and $and$libresoc.v:44612$1230
67369     parameter \A_SIGNED 0
67370     parameter \A_WIDTH 1
67371     parameter \B_SIGNED 0
67372     parameter \B_WIDTH 1
67373     parameter \Y_WIDTH 1
67374     connect \A \$381
67375     connect \B \_fsm_update
67376     connect \Y $and$libresoc.v:44612$1230_Y
67377   end
67378   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
67379   cell $and $and$libresoc.v:44614$1232
67380     parameter \A_SIGNED 0
67381     parameter \A_WIDTH 1
67382     parameter \B_SIGNED 0
67383     parameter \B_WIDTH 1
67384     parameter \Y_WIDTH 1
67385     connect \A \sr0_update_core_prev
67386     connect \B \$385
67387     connect \Y $and$libresoc.v:44614$1232_Y
67388   end
67389   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
67390   cell $and $and$libresoc.v:44617$1235
67391     parameter \A_SIGNED 0
67392     parameter \A_WIDTH 1
67393     parameter \B_SIGNED 0
67394     parameter \B_WIDTH 1
67395     parameter \Y_WIDTH 1
67396     connect \A \$391
67397     connect \B \_fsm_capture
67398     connect \Y $and$libresoc.v:44617$1235_Y
67399   end
67400   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
67401   cell $and $and$libresoc.v:44619$1237
67402     parameter \A_SIGNED 0
67403     parameter \A_WIDTH 1
67404     parameter \B_SIGNED 0
67405     parameter \B_WIDTH 1
67406     parameter \Y_WIDTH 1
67407     connect \A \$395
67408     connect \B \_fsm_shift
67409     connect \Y $and$libresoc.v:44619$1237_Y
67410   end
67411   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
67412   cell $and $and$libresoc.v:44623$1241
67413     parameter \A_SIGNED 0
67414     parameter \A_WIDTH 1
67415     parameter \B_SIGNED 0
67416     parameter \B_WIDTH 1
67417     parameter \Y_WIDTH 1
67418     connect \A \$399
67419     connect \B \_fsm_update
67420     connect \Y $and$libresoc.v:44623$1241_Y
67421   end
67422   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
67423   cell $and $and$libresoc.v:44625$1243
67424     parameter \A_SIGNED 0
67425     parameter \A_WIDTH 1
67426     parameter \B_SIGNED 0
67427     parameter \B_WIDTH 1
67428     parameter \Y_WIDTH 1
67429     connect \A \jtag_wb_addrsr_update_core_prev
67430     connect \B \$403
67431     connect \Y $and$libresoc.v:44625$1243_Y
67432   end
67433   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
67434   cell $and $and$libresoc.v:44629$1247
67435     parameter \A_SIGNED 0
67436     parameter \A_WIDTH 1
67437     parameter \B_SIGNED 0
67438     parameter \B_WIDTH 1
67439     parameter \Y_WIDTH 1
67440     connect \A \$411
67441     connect \B \_fsm_capture
67442     connect \Y $and$libresoc.v:44629$1247_Y
67443   end
67444   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
67445   cell $and $and$libresoc.v:44631$1249
67446     parameter \A_SIGNED 0
67447     parameter \A_WIDTH 1
67448     parameter \B_SIGNED 0
67449     parameter \B_WIDTH 1
67450     parameter \Y_WIDTH 1
67451     connect \A \$415
67452     connect \B \_fsm_shift
67453     connect \Y $and$libresoc.v:44631$1249_Y
67454   end
67455   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
67456   cell $and $and$libresoc.v:44634$1252
67457     parameter \A_SIGNED 0
67458     parameter \A_WIDTH 1
67459     parameter \B_SIGNED 0
67460     parameter \B_WIDTH 1
67461     parameter \Y_WIDTH 1
67462     connect \A \$419
67463     connect \B \_fsm_update
67464     connect \Y $and$libresoc.v:44634$1252_Y
67465   end
67466   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
67467   cell $and $and$libresoc.v:44636$1254
67468     parameter \A_SIGNED 0
67469     parameter \A_WIDTH 1
67470     parameter \B_SIGNED 0
67471     parameter \B_WIDTH 1
67472     parameter \Y_WIDTH 1
67473     connect \A \jtag_wb_datasr_update_core_prev
67474     connect \B \$423
67475     connect \Y $and$libresoc.v:44636$1254_Y
67476   end
67477   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
67478   cell $and $and$libresoc.v:44639$1257
67479     parameter \A_SIGNED 0
67480     parameter \A_WIDTH 1
67481     parameter \B_SIGNED 0
67482     parameter \B_WIDTH 1
67483     parameter \Y_WIDTH 1
67484     connect \A \$429
67485     connect \B \_fsm_capture
67486     connect \Y $and$libresoc.v:44639$1257_Y
67487   end
67488   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
67489   cell $and $and$libresoc.v:44641$1259
67490     parameter \A_SIGNED 0
67491     parameter \A_WIDTH 1
67492     parameter \B_SIGNED 0
67493     parameter \B_WIDTH 1
67494     parameter \Y_WIDTH 1
67495     connect \A \$433
67496     connect \B \_fsm_shift
67497     connect \Y $and$libresoc.v:44641$1259_Y
67498   end
67499   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
67500   cell $and $and$libresoc.v:44643$1261
67501     parameter \A_SIGNED 0
67502     parameter \A_WIDTH 1
67503     parameter \B_SIGNED 0
67504     parameter \B_WIDTH 1
67505     parameter \Y_WIDTH 1
67506     connect \A \_fsm_isdr
67507     connect \B \$41
67508     connect \Y $and$libresoc.v:44643$1261_Y
67509   end
67510   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
67511   cell $and $and$libresoc.v:44644$1262
67512     parameter \A_SIGNED 0
67513     parameter \A_WIDTH 1
67514     parameter \B_SIGNED 0
67515     parameter \B_WIDTH 1
67516     parameter \Y_WIDTH 1
67517     connect \A \$437
67518     connect \B \_fsm_update
67519     connect \Y $and$libresoc.v:44644$1262_Y
67520   end
67521   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
67522   cell $and $and$libresoc.v:44646$1264
67523     parameter \A_SIGNED 0
67524     parameter \A_WIDTH 1
67525     parameter \B_SIGNED 0
67526     parameter \B_WIDTH 1
67527     parameter \Y_WIDTH 1
67528     connect \A \dmi0_addrsr_update_core_prev
67529     connect \B \$441
67530     connect \Y $and$libresoc.v:44646$1264_Y
67531   end
67532   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
67533   cell $and $and$libresoc.v:44650$1268
67534     parameter \A_SIGNED 0
67535     parameter \A_WIDTH 1
67536     parameter \B_SIGNED 0
67537     parameter \B_WIDTH 1
67538     parameter \Y_WIDTH 1
67539     connect \A \$449
67540     connect \B \_fsm_capture
67541     connect \Y $and$libresoc.v:44650$1268_Y
67542   end
67543   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
67544   cell $and $and$libresoc.v:44652$1270
67545     parameter \A_SIGNED 0
67546     parameter \A_WIDTH 1
67547     parameter \B_SIGNED 0
67548     parameter \B_WIDTH 1
67549     parameter \Y_WIDTH 1
67550     connect \A \$453
67551     connect \B \_fsm_shift
67552     connect \Y $and$libresoc.v:44652$1270_Y
67553   end
67554   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403"
67555   cell $and $and$libresoc.v:44654$1272
67556     parameter \A_SIGNED 0
67557     parameter \A_WIDTH 1
67558     parameter \B_SIGNED 0
67559     parameter \B_WIDTH 1
67560     parameter \Y_WIDTH 1
67561     connect \A \$43
67562     connect \B \_fsm_update
67563     connect \Y $and$libresoc.v:44654$1272_Y
67564   end
67565   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
67566   cell $and $and$libresoc.v:44655$1273
67567     parameter \A_SIGNED 0
67568     parameter \A_WIDTH 1
67569     parameter \B_SIGNED 0
67570     parameter \B_WIDTH 1
67571     parameter \Y_WIDTH 1
67572     connect \A \$457
67573     connect \B \_fsm_update
67574     connect \Y $and$libresoc.v:44655$1273_Y
67575   end
67576   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
67577   cell $and $and$libresoc.v:44657$1275
67578     parameter \A_SIGNED 0
67579     parameter \A_WIDTH 1
67580     parameter \B_SIGNED 0
67581     parameter \B_WIDTH 1
67582     parameter \Y_WIDTH 1
67583     connect \A \dmi0_datasr_update_core_prev
67584     connect \B \$461
67585     connect \Y $and$libresoc.v:44657$1275_Y
67586   end
67587   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
67588   cell $and $and$libresoc.v:44660$1278
67589     parameter \A_SIGNED 0
67590     parameter \A_WIDTH 1
67591     parameter \B_SIGNED 0
67592     parameter \B_WIDTH 1
67593     parameter \Y_WIDTH 1
67594     connect \A \$467
67595     connect \B \_fsm_capture
67596     connect \Y $and$libresoc.v:44660$1278_Y
67597   end
67598   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
67599   cell $and $and$libresoc.v:44662$1280
67600     parameter \A_SIGNED 0
67601     parameter \A_WIDTH 1
67602     parameter \B_SIGNED 0
67603     parameter \B_WIDTH 1
67604     parameter \Y_WIDTH 1
67605     connect \A \$471
67606     connect \B \_fsm_shift
67607     connect \Y $and$libresoc.v:44662$1280_Y
67608   end
67609   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
67610   cell $and $and$libresoc.v:44664$1282
67611     parameter \A_SIGNED 0
67612     parameter \A_WIDTH 1
67613     parameter \B_SIGNED 0
67614     parameter \B_WIDTH 1
67615     parameter \Y_WIDTH 1
67616     connect \A \$475
67617     connect \B \_fsm_update
67618     connect \Y $and$libresoc.v:44664$1282_Y
67619   end
67620   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
67621   cell $and $and$libresoc.v:44667$1285
67622     parameter \A_SIGNED 0
67623     parameter \A_WIDTH 1
67624     parameter \B_SIGNED 0
67625     parameter \B_WIDTH 1
67626     parameter \Y_WIDTH 1
67627     connect \A \sr5_update_core_prev
67628     connect \B \$479
67629     connect \Y $and$libresoc.v:44667$1285_Y
67630   end
67631   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
67632   cell $and $and$libresoc.v:44699$1318
67633     parameter \A_SIGNED 0
67634     parameter \A_WIDTH 1
67635     parameter \B_SIGNED 0
67636     parameter \B_WIDTH 1
67637     parameter \Y_WIDTH 1
67638     connect \A \_fsm_isdr
67639     connect \B \$5
67640     connect \Y $and$libresoc.v:44699$1318_Y
67641   end
67642   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378"
67643   cell $eq $eq$libresoc.v:44454$1072
67644     parameter \A_SIGNED 0
67645     parameter \A_WIDTH 4
67646     parameter \B_SIGNED 0
67647     parameter \B_WIDTH 4
67648     parameter \Y_WIDTH 1
67649     connect \A \_irblock_ir
67650     connect \B 4'1111
67651     connect \Y $eq$libresoc.v:44454$1072_Y
67652   end
67653   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67654   cell $eq $eq$libresoc.v:44465$1083
67655     parameter \A_SIGNED 0
67656     parameter \A_WIDTH 4
67657     parameter \B_SIGNED 0
67658     parameter \B_WIDTH 1
67659     parameter \Y_WIDTH 1
67660     connect \A \_irblock_ir
67661     connect \B 1'0
67662     connect \Y $eq$libresoc.v:44465$1083_Y
67663   end
67664   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67665   cell $eq $eq$libresoc.v:44476$1094
67666     parameter \A_SIGNED 0
67667     parameter \A_WIDTH 4
67668     parameter \B_SIGNED 0
67669     parameter \B_WIDTH 2
67670     parameter \Y_WIDTH 1
67671     connect \A \_irblock_ir
67672     connect \B 2'10
67673     connect \Y $eq$libresoc.v:44476$1094_Y
67674   end
67675   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
67676   cell $eq $eq$libresoc.v:44509$1127
67677     parameter \A_SIGNED 0
67678     parameter \A_WIDTH 4
67679     parameter \B_SIGNED 0
67680     parameter \B_WIDTH 1
67681     parameter \Y_WIDTH 1
67682     connect \A \_irblock_ir
67683     connect \B 1'1
67684     connect \Y $eq$libresoc.v:44509$1127_Y
67685   end
67686   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67687   cell $eq $eq$libresoc.v:44510$1128
67688     parameter \A_SIGNED 0
67689     parameter \A_WIDTH 4
67690     parameter \B_SIGNED 0
67691     parameter \B_WIDTH 1
67692     parameter \Y_WIDTH 1
67693     connect \A \_irblock_ir
67694     connect \B 1'0
67695     connect \Y $eq$libresoc.v:44510$1128_Y
67696   end
67697   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67698   cell $eq $eq$libresoc.v:44521$1139
67699     parameter \A_SIGNED 0
67700     parameter \A_WIDTH 4
67701     parameter \B_SIGNED 0
67702     parameter \B_WIDTH 2
67703     parameter \Y_WIDTH 1
67704     connect \A \_irblock_ir
67705     connect \B 2'10
67706     connect \Y $eq$libresoc.v:44521$1139_Y
67707   end
67708   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
67709   cell $eq $eq$libresoc.v:44543$1161
67710     parameter \A_SIGNED 0
67711     parameter \A_WIDTH 4
67712     parameter \B_SIGNED 0
67713     parameter \B_WIDTH 2
67714     parameter \Y_WIDTH 1
67715     connect \A \_irblock_ir
67716     connect \B 2'10
67717     connect \Y $eq$libresoc.v:44543$1161_Y
67718   end
67719   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67720   cell $eq $eq$libresoc.v:44587$1205
67721     parameter \A_SIGNED 0
67722     parameter \A_WIDTH 4
67723     parameter \B_SIGNED 0
67724     parameter \B_WIDTH 1
67725     parameter \Y_WIDTH 1
67726     connect \A \_irblock_ir
67727     connect \B 1'0
67728     connect \Y $eq$libresoc.v:44587$1205_Y
67729   end
67730   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67731   cell $eq $eq$libresoc.v:44598$1216
67732     parameter \A_SIGNED 0
67733     parameter \A_WIDTH 4
67734     parameter \B_SIGNED 0
67735     parameter \B_WIDTH 2
67736     parameter \Y_WIDTH 1
67737     connect \A \_irblock_ir
67738     connect \B 2'10
67739     connect \Y $eq$libresoc.v:44598$1216_Y
67740   end
67741   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67742   cell $eq $eq$libresoc.v:44599$1217
67743     parameter \A_SIGNED 0
67744     parameter \A_WIDTH 4
67745     parameter \B_SIGNED 0
67746     parameter \B_WIDTH 1
67747     parameter \Y_WIDTH 1
67748     connect \A \_irblock_ir
67749     connect \B 1'0
67750     connect \Y $eq$libresoc.v:44599$1217_Y
67751   end
67752   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
67753   cell $eq $eq$libresoc.v:44600$1218
67754     parameter \A_SIGNED 0
67755     parameter \A_WIDTH 4
67756     parameter \B_SIGNED 0
67757     parameter \B_WIDTH 2
67758     parameter \Y_WIDTH 1
67759     connect \A \_irblock_ir
67760     connect \B 2'10
67761     connect \Y $eq$libresoc.v:44600$1218_Y
67762   end
67763   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
67764   cell $eq $eq$libresoc.v:44602$1220
67765     parameter \A_SIGNED 0
67766     parameter \A_WIDTH 4
67767     parameter \B_SIGNED 0
67768     parameter \B_WIDTH 2
67769     parameter \Y_WIDTH 1
67770     connect \A \_irblock_ir
67771     connect \B 2'10
67772     connect \Y $eq$libresoc.v:44602$1220_Y
67773   end
67774   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67775   cell $eq $eq$libresoc.v:44605$1223
67776     parameter \A_SIGNED 0
67777     parameter \A_WIDTH 4
67778     parameter \B_SIGNED 0
67779     parameter \B_WIDTH 3
67780     parameter \Y_WIDTH 1
67781     connect \A \_irblock_ir
67782     connect \B 3'100
67783     connect \Y $eq$libresoc.v:44605$1223_Y
67784   end
67785   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67786   cell $eq $eq$libresoc.v:44615$1233
67787     parameter \A_SIGNED 0
67788     parameter \A_WIDTH 4
67789     parameter \B_SIGNED 0
67790     parameter \B_WIDTH 3
67791     parameter \Y_WIDTH 1
67792     connect \A \_irblock_ir
67793     connect \B 3'101
67794     connect \Y $eq$libresoc.v:44615$1233_Y
67795   end
67796   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
67797   cell $eq $eq$libresoc.v:44620$1238
67798     parameter \A_SIGNED 0
67799     parameter \A_WIDTH 4
67800     parameter \B_SIGNED 0
67801     parameter \B_WIDTH 4
67802     parameter \Y_WIDTH 1
67803     connect \A \_irblock_ir
67804     connect \B 4'1111
67805     connect \Y $eq$libresoc.v:44620$1238_Y
67806   end
67807   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397"
67808   cell $eq $eq$libresoc.v:44621$1239
67809     parameter \A_SIGNED 0
67810     parameter \A_WIDTH 4
67811     parameter \B_SIGNED 0
67812     parameter \B_WIDTH 2
67813     parameter \Y_WIDTH 1
67814     connect \A \_irblock_ir
67815     connect \B 2'10
67816     connect \Y $eq$libresoc.v:44621$1239_Y
67817   end
67818   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67819   cell $eq $eq$libresoc.v:44626$1244
67820     parameter \A_SIGNED 0
67821     parameter \A_WIDTH 4
67822     parameter \B_SIGNED 0
67823     parameter \B_WIDTH 3
67824     parameter \Y_WIDTH 1
67825     connect \A \_irblock_ir
67826     connect \B 3'110
67827     connect \Y $eq$libresoc.v:44626$1244_Y
67828   end
67829   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67830   cell $eq $eq$libresoc.v:44627$1245
67831     parameter \A_SIGNED 0
67832     parameter \A_WIDTH 4
67833     parameter \B_SIGNED 0
67834     parameter \B_WIDTH 3
67835     parameter \Y_WIDTH 1
67836     connect \A \_irblock_ir
67837     connect \B 3'111
67838     connect \Y $eq$libresoc.v:44627$1245_Y
67839   end
67840   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67841   cell $eq $eq$libresoc.v:44637$1255
67842     parameter \A_SIGNED 0
67843     parameter \A_WIDTH 4
67844     parameter \B_SIGNED 0
67845     parameter \B_WIDTH 4
67846     parameter \Y_WIDTH 1
67847     connect \A \_irblock_ir
67848     connect \B 4'1000
67849     connect \Y $eq$libresoc.v:44637$1255_Y
67850   end
67851   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67852   cell $eq $eq$libresoc.v:44647$1265
67853     parameter \A_SIGNED 0
67854     parameter \A_WIDTH 4
67855     parameter \B_SIGNED 0
67856     parameter \B_WIDTH 4
67857     parameter \Y_WIDTH 1
67858     connect \A \_irblock_ir
67859     connect \B 4'1001
67860     connect \Y $eq$libresoc.v:44647$1265_Y
67861   end
67862   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67863   cell $eq $eq$libresoc.v:44648$1266
67864     parameter \A_SIGNED 0
67865     parameter \A_WIDTH 4
67866     parameter \B_SIGNED 0
67867     parameter \B_WIDTH 4
67868     parameter \Y_WIDTH 1
67869     connect \A \_irblock_ir
67870     connect \B 4'1010
67871     connect \Y $eq$libresoc.v:44648$1266_Y
67872   end
67873   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650"
67874   cell $eq $eq$libresoc.v:44658$1276
67875     parameter \A_SIGNED 0
67876     parameter \A_WIDTH 4
67877     parameter \B_SIGNED 0
67878     parameter \B_WIDTH 4
67879     parameter \Y_WIDTH 1
67880     connect \A \_irblock_ir
67881     connect \B 4'1011
67882     connect \Y $eq$libresoc.v:44658$1276_Y
67883   end
67884   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404"
67885   cell $eq $eq$libresoc.v:44665$1283
67886     parameter \A_SIGNED 0
67887     parameter \A_WIDTH 4
67888     parameter \B_SIGNED 0
67889     parameter \B_WIDTH 1
67890     parameter \Y_WIDTH 1
67891     connect \A \_irblock_ir
67892     connect \B 1'0
67893     connect \Y $eq$libresoc.v:44665$1283_Y
67894   end
67895   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
67896   cell $eq $eq$libresoc.v:44668$1286
67897     parameter \A_SIGNED 0
67898     parameter \A_WIDTH 3
67899     parameter \B_SIGNED 0
67900     parameter \B_WIDTH 1
67901     parameter \Y_WIDTH 1
67902     connect \A \fsm_state
67903     connect \B 1'0
67904     connect \Y $eq$libresoc.v:44668$1286_Y
67905   end
67906   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
67907   cell $eq $eq$libresoc.v:44670$1288
67908     parameter \A_SIGNED 0
67909     parameter \A_WIDTH 3
67910     parameter \B_SIGNED 0
67911     parameter \B_WIDTH 1
67912     parameter \Y_WIDTH 1
67913     connect \A \fsm_state
67914     connect \B 1'1
67915     connect \Y $eq$libresoc.v:44670$1288_Y
67916   end
67917   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
67918   cell $eq $eq$libresoc.v:44671$1289
67919     parameter \A_SIGNED 0
67920     parameter \A_WIDTH 3
67921     parameter \B_SIGNED 0
67922     parameter \B_WIDTH 2
67923     parameter \Y_WIDTH 1
67924     connect \A \fsm_state
67925     connect \B 2'10
67926     connect \Y $eq$libresoc.v:44671$1289_Y
67927   end
67928   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792"
67929   cell $eq $eq$libresoc.v:44673$1291
67930     parameter \A_SIGNED 0
67931     parameter \A_WIDTH 3
67932     parameter \B_SIGNED 0
67933     parameter \B_WIDTH 2
67934     parameter \Y_WIDTH 1
67935     connect \A \fsm_state
67936     connect \B 2'10
67937     connect \Y $eq$libresoc.v:44673$1291_Y
67938   end
67939   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405"
67940   cell $eq $eq$libresoc.v:44675$1293
67941     parameter \A_SIGNED 0
67942     parameter \A_WIDTH 4
67943     parameter \B_SIGNED 0
67944     parameter \B_WIDTH 1
67945     parameter \Y_WIDTH 1
67946     connect \A \_irblock_ir
67947     connect \B 1'0
67948     connect \Y $eq$libresoc.v:44675$1293_Y
67949   end
67950   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
67951   cell $eq $eq$libresoc.v:44678$1297
67952     parameter \A_SIGNED 0
67953     parameter \A_WIDTH 3
67954     parameter \B_SIGNED 0
67955     parameter \B_WIDTH 1
67956     parameter \Y_WIDTH 1
67957     connect \A \fsm_state$503
67958     connect \B 1'1
67959     connect \Y $eq$libresoc.v:44678$1297_Y
67960   end
67961   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
67962   cell $eq $eq$libresoc.v:44679$1298
67963     parameter \A_SIGNED 0
67964     parameter \A_WIDTH 3
67965     parameter \B_SIGNED 0
67966     parameter \B_WIDTH 2
67967     parameter \Y_WIDTH 1
67968     connect \A \fsm_state$503
67969     connect \B 2'10
67970     connect \Y $eq$libresoc.v:44679$1298_Y
67971   end
67972   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524"
67973   cell $eq $eq$libresoc.v:44681$1300
67974     parameter \A_SIGNED 0
67975     parameter \A_WIDTH 3
67976     parameter \B_SIGNED 0
67977     parameter \B_WIDTH 2
67978     parameter \Y_WIDTH 1
67979     connect \A \fsm_state$503
67980     connect \B 2'10
67981     connect \Y $eq$libresoc.v:44681$1300_Y
67982   end
67983   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
67984   cell $pos $extend$libresoc.v:44677$1295
67985     parameter \A_SIGNED 0
67986     parameter \A_WIDTH 4
67987     parameter \Y_WIDTH 8
67988     connect \A \dmi0__addr_i
67989     connect \Y $extend$libresoc.v:44677$1295_Y
67990   end
67991   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
67992   cell $ne $ne$libresoc.v:44606$1224
67993     parameter \A_SIGNED 0
67994     parameter \A_WIDTH 1
67995     parameter \B_SIGNED 0
67996     parameter \B_WIDTH 1
67997     parameter \Y_WIDTH 1
67998     connect \A \sr0_isir
67999     connect \B 1'0
68000     connect \Y $ne$libresoc.v:44606$1224_Y
68001   end
68002   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
68003   cell $ne $ne$libresoc.v:44608$1226
68004     parameter \A_SIGNED 0
68005     parameter \A_WIDTH 1
68006     parameter \B_SIGNED 0
68007     parameter \B_WIDTH 1
68008     parameter \Y_WIDTH 1
68009     connect \A \sr0_isir
68010     connect \B 1'0
68011     connect \Y $ne$libresoc.v:44608$1226_Y
68012   end
68013   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
68014   cell $ne $ne$libresoc.v:44611$1229
68015     parameter \A_SIGNED 0
68016     parameter \A_WIDTH 1
68017     parameter \B_SIGNED 0
68018     parameter \B_WIDTH 1
68019     parameter \Y_WIDTH 1
68020     connect \A \sr0_isir
68021     connect \B 1'0
68022     connect \Y $ne$libresoc.v:44611$1229_Y
68023   end
68024   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
68025   cell $ne $ne$libresoc.v:44616$1234
68026     parameter \A_SIGNED 0
68027     parameter \A_WIDTH 1
68028     parameter \B_SIGNED 0
68029     parameter \B_WIDTH 1
68030     parameter \Y_WIDTH 1
68031     connect \A \jtag_wb_addrsr_isir
68032     connect \B 1'0
68033     connect \Y $ne$libresoc.v:44616$1234_Y
68034   end
68035   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
68036   cell $ne $ne$libresoc.v:44618$1236
68037     parameter \A_SIGNED 0
68038     parameter \A_WIDTH 1
68039     parameter \B_SIGNED 0
68040     parameter \B_WIDTH 1
68041     parameter \Y_WIDTH 1
68042     connect \A \jtag_wb_addrsr_isir
68043     connect \B 1'0
68044     connect \Y $ne$libresoc.v:44618$1236_Y
68045   end
68046   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
68047   cell $ne $ne$libresoc.v:44622$1240
68048     parameter \A_SIGNED 0
68049     parameter \A_WIDTH 1
68050     parameter \B_SIGNED 0
68051     parameter \B_WIDTH 1
68052     parameter \Y_WIDTH 1
68053     connect \A \jtag_wb_addrsr_isir
68054     connect \B 1'0
68055     connect \Y $ne$libresoc.v:44622$1240_Y
68056   end
68057   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
68058   cell $ne $ne$libresoc.v:44628$1246
68059     parameter \A_SIGNED 0
68060     parameter \A_WIDTH 2
68061     parameter \B_SIGNED 0
68062     parameter \B_WIDTH 1
68063     parameter \Y_WIDTH 1
68064     connect \A \jtag_wb_datasr_isir
68065     connect \B 1'0
68066     connect \Y $ne$libresoc.v:44628$1246_Y
68067   end
68068   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
68069   cell $ne $ne$libresoc.v:44630$1248
68070     parameter \A_SIGNED 0
68071     parameter \A_WIDTH 2
68072     parameter \B_SIGNED 0
68073     parameter \B_WIDTH 1
68074     parameter \Y_WIDTH 1
68075     connect \A \jtag_wb_datasr_isir
68076     connect \B 1'0
68077     connect \Y $ne$libresoc.v:44630$1248_Y
68078   end
68079   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
68080   cell $ne $ne$libresoc.v:44633$1251
68081     parameter \A_SIGNED 0
68082     parameter \A_WIDTH 2
68083     parameter \B_SIGNED 0
68084     parameter \B_WIDTH 1
68085     parameter \Y_WIDTH 1
68086     connect \A \jtag_wb_datasr_isir
68087     connect \B 1'0
68088     connect \Y $ne$libresoc.v:44633$1251_Y
68089   end
68090   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
68091   cell $ne $ne$libresoc.v:44638$1256
68092     parameter \A_SIGNED 0
68093     parameter \A_WIDTH 1
68094     parameter \B_SIGNED 0
68095     parameter \B_WIDTH 1
68096     parameter \Y_WIDTH 1
68097     connect \A \dmi0_addrsr_isir
68098     connect \B 1'0
68099     connect \Y $ne$libresoc.v:44638$1256_Y
68100   end
68101   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
68102   cell $ne $ne$libresoc.v:44640$1258
68103     parameter \A_SIGNED 0
68104     parameter \A_WIDTH 1
68105     parameter \B_SIGNED 0
68106     parameter \B_WIDTH 1
68107     parameter \Y_WIDTH 1
68108     connect \A \dmi0_addrsr_isir
68109     connect \B 1'0
68110     connect \Y $ne$libresoc.v:44640$1258_Y
68111   end
68112   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
68113   cell $ne $ne$libresoc.v:44642$1260
68114     parameter \A_SIGNED 0
68115     parameter \A_WIDTH 1
68116     parameter \B_SIGNED 0
68117     parameter \B_WIDTH 1
68118     parameter \Y_WIDTH 1
68119     connect \A \dmi0_addrsr_isir
68120     connect \B 1'0
68121     connect \Y $ne$libresoc.v:44642$1260_Y
68122   end
68123   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
68124   cell $ne $ne$libresoc.v:44649$1267
68125     parameter \A_SIGNED 0
68126     parameter \A_WIDTH 2
68127     parameter \B_SIGNED 0
68128     parameter \B_WIDTH 1
68129     parameter \Y_WIDTH 1
68130     connect \A \dmi0_datasr_isir
68131     connect \B 1'0
68132     connect \Y $ne$libresoc.v:44649$1267_Y
68133   end
68134   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
68135   cell $ne $ne$libresoc.v:44651$1269
68136     parameter \A_SIGNED 0
68137     parameter \A_WIDTH 2
68138     parameter \B_SIGNED 0
68139     parameter \B_WIDTH 1
68140     parameter \Y_WIDTH 1
68141     connect \A \dmi0_datasr_isir
68142     connect \B 1'0
68143     connect \Y $ne$libresoc.v:44651$1269_Y
68144   end
68145   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
68146   cell $ne $ne$libresoc.v:44653$1271
68147     parameter \A_SIGNED 0
68148     parameter \A_WIDTH 2
68149     parameter \B_SIGNED 0
68150     parameter \B_WIDTH 1
68151     parameter \Y_WIDTH 1
68152     connect \A \dmi0_datasr_isir
68153     connect \B 1'0
68154     connect \Y $ne$libresoc.v:44653$1271_Y
68155   end
68156   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651"
68157   cell $ne $ne$libresoc.v:44659$1277
68158     parameter \A_SIGNED 0
68159     parameter \A_WIDTH 1
68160     parameter \B_SIGNED 0
68161     parameter \B_WIDTH 1
68162     parameter \Y_WIDTH 1
68163     connect \A \sr5_isir
68164     connect \B 1'0
68165     connect \Y $ne$libresoc.v:44659$1277_Y
68166   end
68167   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652"
68168   cell $ne $ne$libresoc.v:44661$1279
68169     parameter \A_SIGNED 0
68170     parameter \A_WIDTH 1
68171     parameter \B_SIGNED 0
68172     parameter \B_WIDTH 1
68173     parameter \Y_WIDTH 1
68174     connect \A \sr5_isir
68175     connect \B 1'0
68176     connect \Y $ne$libresoc.v:44661$1279_Y
68177   end
68178   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653"
68179   cell $ne $ne$libresoc.v:44663$1281
68180     parameter \A_SIGNED 0
68181     parameter \A_WIDTH 1
68182     parameter \B_SIGNED 0
68183     parameter \B_WIDTH 1
68184     parameter \Y_WIDTH 1
68185     connect \A \sr5_isir
68186     connect \B 1'0
68187     connect \Y $ne$libresoc.v:44663$1281_Y
68188   end
68189   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
68190   cell $not $not$libresoc.v:44613$1231
68191     parameter \A_SIGNED 0
68192     parameter \A_WIDTH 1
68193     parameter \Y_WIDTH 1
68194     connect \A \sr0_update_core
68195     connect \Y $not$libresoc.v:44613$1231_Y
68196   end
68197   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
68198   cell $not $not$libresoc.v:44624$1242
68199     parameter \A_SIGNED 0
68200     parameter \A_WIDTH 1
68201     parameter \Y_WIDTH 1
68202     connect \A \jtag_wb_addrsr_update_core
68203     connect \Y $not$libresoc.v:44624$1242_Y
68204   end
68205   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
68206   cell $not $not$libresoc.v:44635$1253
68207     parameter \A_SIGNED 0
68208     parameter \A_WIDTH 1
68209     parameter \Y_WIDTH 1
68210     connect \A \jtag_wb_datasr_update_core
68211     connect \Y $not$libresoc.v:44635$1253_Y
68212   end
68213   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
68214   cell $not $not$libresoc.v:44645$1263
68215     parameter \A_SIGNED 0
68216     parameter \A_WIDTH 1
68217     parameter \Y_WIDTH 1
68218     connect \A \dmi0_addrsr_update_core
68219     connect \Y $not$libresoc.v:44645$1263_Y
68220   end
68221   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
68222   cell $not $not$libresoc.v:44656$1274
68223     parameter \A_SIGNED 0
68224     parameter \A_WIDTH 1
68225     parameter \Y_WIDTH 1
68226     connect \A \dmi0_datasr_update_core
68227     connect \Y $not$libresoc.v:44656$1274_Y
68228   end
68229   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
68230   cell $not $not$libresoc.v:44666$1284
68231     parameter \A_SIGNED 0
68232     parameter \A_WIDTH 1
68233     parameter \Y_WIDTH 1
68234     connect \A \sr5_update_core
68235     connect \Y $not$libresoc.v:44666$1284_Y
68236   end
68237   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790"
68238   cell $not $not$libresoc.v:44669$1287
68239     parameter \A_SIGNED 0
68240     parameter \A_WIDTH 1
68241     parameter \Y_WIDTH 1
68242     connect \A \$484
68243     connect \Y $not$libresoc.v:44669$1287_Y
68244   end
68245   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
68246   cell $or $or$libresoc.v:44487$1105
68247     parameter \A_SIGNED 0
68248     parameter \A_WIDTH 1
68249     parameter \B_SIGNED 0
68250     parameter \B_WIDTH 1
68251     parameter \Y_WIDTH 1
68252     connect \A \$11
68253     connect \B \$13
68254     connect \Y $or$libresoc.v:44487$1105_Y
68255   end
68256   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
68257   cell $or $or$libresoc.v:44532$1150
68258     parameter \A_SIGNED 0
68259     parameter \A_WIDTH 1
68260     parameter \B_SIGNED 0
68261     parameter \B_WIDTH 1
68262     parameter \Y_WIDTH 1
68263     connect \A \$19
68264     connect \B \$21
68265     connect \Y $or$libresoc.v:44532$1150_Y
68266   end
68267   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
68268   cell $or $or$libresoc.v:44554$1172
68269     parameter \A_SIGNED 0
68270     parameter \A_WIDTH 1
68271     parameter \B_SIGNED 0
68272     parameter \B_WIDTH 1
68273     parameter \Y_WIDTH 1
68274     connect \A \$23
68275     connect \B \$25
68276     connect \Y $or$libresoc.v:44554$1172_Y
68277   end
68278   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
68279   cell $or $or$libresoc.v:44601$1219
68280     parameter \A_SIGNED 0
68281     parameter \A_WIDTH 1
68282     parameter \B_SIGNED 0
68283     parameter \B_WIDTH 1
68284     parameter \Y_WIDTH 1
68285     connect \A \$359
68286     connect \B \$361
68287     connect \Y $or$libresoc.v:44601$1219_Y
68288   end
68289   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
68290   cell $or $or$libresoc.v:44603$1221
68291     parameter \A_SIGNED 0
68292     parameter \A_WIDTH 1
68293     parameter \B_SIGNED 0
68294     parameter \B_WIDTH 1
68295     parameter \Y_WIDTH 1
68296     connect \A \$363
68297     connect \B \$365
68298     connect \Y $or$libresoc.v:44603$1221_Y
68299   end
68300   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
68301   cell $or $or$libresoc.v:44609$1227
68302     parameter \A_SIGNED 0
68303     parameter \A_WIDTH 1
68304     parameter \B_SIGNED 0
68305     parameter \B_WIDTH 1
68306     parameter \Y_WIDTH 1
68307     connect \A \$33
68308     connect \B \$35
68309     connect \Y $or$libresoc.v:44609$1227_Y
68310   end
68311   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
68312   cell $or $or$libresoc.v:44632$1250
68313     parameter \A_SIGNED 0
68314     parameter \A_WIDTH 1
68315     parameter \B_SIGNED 0
68316     parameter \B_WIDTH 1
68317     parameter \Y_WIDTH 1
68318     connect \A \$37
68319     connect \B \$39
68320     connect \Y $or$libresoc.v:44632$1250_Y
68321   end
68322   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791"
68323   cell $or $or$libresoc.v:44672$1290
68324     parameter \A_SIGNED 0
68325     parameter \A_WIDTH 1
68326     parameter \B_SIGNED 0
68327     parameter \B_WIDTH 1
68328     parameter \Y_WIDTH 1
68329     connect \A \$487
68330     connect \B \$489
68331     connect \Y $or$libresoc.v:44672$1290_Y
68332   end
68333   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523"
68334   cell $or $or$libresoc.v:44680$1299
68335     parameter \A_SIGNED 0
68336     parameter \A_WIDTH 1
68337     parameter \B_SIGNED 0
68338     parameter \B_WIDTH 1
68339     parameter \Y_WIDTH 1
68340     connect \A \$504
68341     connect \B \$506
68342     connect \Y $or$libresoc.v:44680$1299_Y
68343   end
68344   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377"
68345   cell $or $or$libresoc.v:44688$1307
68346     parameter \A_SIGNED 0
68347     parameter \A_WIDTH 1
68348     parameter \B_SIGNED 0
68349     parameter \B_WIDTH 1
68350     parameter \Y_WIDTH 1
68351     connect \A \$1
68352     connect \B \$3
68353     connect \Y $or$libresoc.v:44688$1307_Y
68354   end
68355   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
68356   cell $pos $pos$libresoc.v:44677$1296
68357     parameter \A_SIGNED 0
68358     parameter \A_WIDTH 8
68359     parameter \Y_WIDTH 8
68360     connect \A $extend$libresoc.v:44677$1295_Y
68361     connect \Y $pos$libresoc.v:44677$1296_Y
68362   end
68363   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68364   cell $mux $ternary$libresoc.v:44455$1073
68365     parameter \WIDTH 1
68366     connect \A \gpio_e15__pad__i
68367     connect \B \io_bd [24]
68368     connect \S \io_bd2core
68369     connect \Y $ternary$libresoc.v:44455$1073_Y
68370   end
68371   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68372   cell $mux $ternary$libresoc.v:44456$1074
68373     parameter \WIDTH 1
68374     connect \A \gpio_e15__core__o
68375     connect \B \io_bd [25]
68376     connect \S \io_bd2io
68377     connect \Y $ternary$libresoc.v:44456$1074_Y
68378   end
68379   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68380   cell $mux $ternary$libresoc.v:44457$1075
68381     parameter \WIDTH 1
68382     connect \A \gpio_e15__core__oe
68383     connect \B \io_bd [26]
68384     connect \S \io_bd2io
68385     connect \Y $ternary$libresoc.v:44457$1075_Y
68386   end
68387   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68388   cell $mux $ternary$libresoc.v:44458$1076
68389     parameter \WIDTH 1
68390     connect \A \gpio_s0__pad__i
68391     connect \B \io_bd [27]
68392     connect \S \io_bd2core
68393     connect \Y $ternary$libresoc.v:44458$1076_Y
68394   end
68395   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68396   cell $mux $ternary$libresoc.v:44459$1077
68397     parameter \WIDTH 1
68398     connect \A \gpio_s0__core__o
68399     connect \B \io_bd [28]
68400     connect \S \io_bd2io
68401     connect \Y $ternary$libresoc.v:44459$1077_Y
68402   end
68403   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68404   cell $mux $ternary$libresoc.v:44460$1078
68405     parameter \WIDTH 1
68406     connect \A \gpio_s0__core__oe
68407     connect \B \io_bd [29]
68408     connect \S \io_bd2io
68409     connect \Y $ternary$libresoc.v:44460$1078_Y
68410   end
68411   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68412   cell $mux $ternary$libresoc.v:44461$1079
68413     parameter \WIDTH 1
68414     connect \A \gpio_s1__pad__i
68415     connect \B \io_bd [30]
68416     connect \S \io_bd2core
68417     connect \Y $ternary$libresoc.v:44461$1079_Y
68418   end
68419   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68420   cell $mux $ternary$libresoc.v:44462$1080
68421     parameter \WIDTH 1
68422     connect \A \gpio_s1__core__o
68423     connect \B \io_bd [31]
68424     connect \S \io_bd2io
68425     connect \Y $ternary$libresoc.v:44462$1080_Y
68426   end
68427   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68428   cell $mux $ternary$libresoc.v:44463$1081
68429     parameter \WIDTH 1
68430     connect \A \gpio_s1__core__oe
68431     connect \B \io_bd [32]
68432     connect \S \io_bd2io
68433     connect \Y $ternary$libresoc.v:44463$1081_Y
68434   end
68435   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68436   cell $mux $ternary$libresoc.v:44464$1082
68437     parameter \WIDTH 1
68438     connect \A \gpio_s2__pad__i
68439     connect \B \io_bd [33]
68440     connect \S \io_bd2core
68441     connect \Y $ternary$libresoc.v:44464$1082_Y
68442   end
68443   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68444   cell $mux $ternary$libresoc.v:44466$1084
68445     parameter \WIDTH 1
68446     connect \A \gpio_s2__core__o
68447     connect \B \io_bd [34]
68448     connect \S \io_bd2io
68449     connect \Y $ternary$libresoc.v:44466$1084_Y
68450   end
68451   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68452   cell $mux $ternary$libresoc.v:44467$1085
68453     parameter \WIDTH 1
68454     connect \A \gpio_s2__core__oe
68455     connect \B \io_bd [35]
68456     connect \S \io_bd2io
68457     connect \Y $ternary$libresoc.v:44467$1085_Y
68458   end
68459   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68460   cell $mux $ternary$libresoc.v:44468$1086
68461     parameter \WIDTH 1
68462     connect \A \gpio_s3__pad__i
68463     connect \B \io_bd [36]
68464     connect \S \io_bd2core
68465     connect \Y $ternary$libresoc.v:44468$1086_Y
68466   end
68467   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68468   cell $mux $ternary$libresoc.v:44469$1087
68469     parameter \WIDTH 1
68470     connect \A \gpio_s3__core__o
68471     connect \B \io_bd [37]
68472     connect \S \io_bd2io
68473     connect \Y $ternary$libresoc.v:44469$1087_Y
68474   end
68475   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68476   cell $mux $ternary$libresoc.v:44470$1088
68477     parameter \WIDTH 1
68478     connect \A \gpio_s3__core__oe
68479     connect \B \io_bd [38]
68480     connect \S \io_bd2io
68481     connect \Y $ternary$libresoc.v:44470$1088_Y
68482   end
68483   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68484   cell $mux $ternary$libresoc.v:44471$1089
68485     parameter \WIDTH 1
68486     connect \A \gpio_s4__pad__i
68487     connect \B \io_bd [39]
68488     connect \S \io_bd2core
68489     connect \Y $ternary$libresoc.v:44471$1089_Y
68490   end
68491   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68492   cell $mux $ternary$libresoc.v:44472$1090
68493     parameter \WIDTH 1
68494     connect \A \gpio_s4__core__o
68495     connect \B \io_bd [40]
68496     connect \S \io_bd2io
68497     connect \Y $ternary$libresoc.v:44472$1090_Y
68498   end
68499   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68500   cell $mux $ternary$libresoc.v:44473$1091
68501     parameter \WIDTH 1
68502     connect \A \gpio_s4__core__oe
68503     connect \B \io_bd [41]
68504     connect \S \io_bd2io
68505     connect \Y $ternary$libresoc.v:44473$1091_Y
68506   end
68507   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68508   cell $mux $ternary$libresoc.v:44474$1092
68509     parameter \WIDTH 1
68510     connect \A \gpio_s5__pad__i
68511     connect \B \io_bd [42]
68512     connect \S \io_bd2core
68513     connect \Y $ternary$libresoc.v:44474$1092_Y
68514   end
68515   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68516   cell $mux $ternary$libresoc.v:44475$1093
68517     parameter \WIDTH 1
68518     connect \A \gpio_s5__core__o
68519     connect \B \io_bd [43]
68520     connect \S \io_bd2io
68521     connect \Y $ternary$libresoc.v:44475$1093_Y
68522   end
68523   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68524   cell $mux $ternary$libresoc.v:44477$1095
68525     parameter \WIDTH 1
68526     connect \A \gpio_s5__core__oe
68527     connect \B \io_bd [44]
68528     connect \S \io_bd2io
68529     connect \Y $ternary$libresoc.v:44477$1095_Y
68530   end
68531   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68532   cell $mux $ternary$libresoc.v:44478$1096
68533     parameter \WIDTH 1
68534     connect \A \gpio_s6__pad__i
68535     connect \B \io_bd [45]
68536     connect \S \io_bd2core
68537     connect \Y $ternary$libresoc.v:44478$1096_Y
68538   end
68539   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68540   cell $mux $ternary$libresoc.v:44479$1097
68541     parameter \WIDTH 1
68542     connect \A \gpio_s6__core__o
68543     connect \B \io_bd [46]
68544     connect \S \io_bd2io
68545     connect \Y $ternary$libresoc.v:44479$1097_Y
68546   end
68547   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68548   cell $mux $ternary$libresoc.v:44480$1098
68549     parameter \WIDTH 1
68550     connect \A \gpio_s6__core__oe
68551     connect \B \io_bd [47]
68552     connect \S \io_bd2io
68553     connect \Y $ternary$libresoc.v:44480$1098_Y
68554   end
68555   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68556   cell $mux $ternary$libresoc.v:44481$1099
68557     parameter \WIDTH 1
68558     connect \A \gpio_s7__pad__i
68559     connect \B \io_bd [48]
68560     connect \S \io_bd2core
68561     connect \Y $ternary$libresoc.v:44481$1099_Y
68562   end
68563   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68564   cell $mux $ternary$libresoc.v:44482$1100
68565     parameter \WIDTH 1
68566     connect \A \gpio_s7__core__o
68567     connect \B \io_bd [49]
68568     connect \S \io_bd2io
68569     connect \Y $ternary$libresoc.v:44482$1100_Y
68570   end
68571   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68572   cell $mux $ternary$libresoc.v:44483$1101
68573     parameter \WIDTH 1
68574     connect \A \gpio_s7__core__oe
68575     connect \B \io_bd [50]
68576     connect \S \io_bd2io
68577     connect \Y $ternary$libresoc.v:44483$1101_Y
68578   end
68579   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68580   cell $mux $ternary$libresoc.v:44484$1102
68581     parameter \WIDTH 1
68582     connect \A \mspi0_clk__core__o
68583     connect \B \io_bd [51]
68584     connect \S \io_bd2io
68585     connect \Y $ternary$libresoc.v:44484$1102_Y
68586   end
68587   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68588   cell $mux $ternary$libresoc.v:44485$1103
68589     parameter \WIDTH 1
68590     connect \A \mspi0_cs_n__core__o
68591     connect \B \io_bd [52]
68592     connect \S \io_bd2io
68593     connect \Y $ternary$libresoc.v:44485$1103_Y
68594   end
68595   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68596   cell $mux $ternary$libresoc.v:44486$1104
68597     parameter \WIDTH 1
68598     connect \A \mspi0_mosi__core__o
68599     connect \B \io_bd [53]
68600     connect \S \io_bd2io
68601     connect \Y $ternary$libresoc.v:44486$1104_Y
68602   end
68603   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
68604   cell $mux $ternary$libresoc.v:44488$1106
68605     parameter \WIDTH 1
68606     connect \A \mspi0_miso__pad__i
68607     connect \B \io_bd [54]
68608     connect \S \io_bd2core
68609     connect \Y $ternary$libresoc.v:44488$1106_Y
68610   end
68611   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68612   cell $mux $ternary$libresoc.v:44489$1107
68613     parameter \WIDTH 1
68614     connect \A \mspi1_clk__core__o
68615     connect \B \io_bd [55]
68616     connect \S \io_bd2io
68617     connect \Y $ternary$libresoc.v:44489$1107_Y
68618   end
68619   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68620   cell $mux $ternary$libresoc.v:44490$1108
68621     parameter \WIDTH 1
68622     connect \A \mspi1_cs_n__core__o
68623     connect \B \io_bd [56]
68624     connect \S \io_bd2io
68625     connect \Y $ternary$libresoc.v:44490$1108_Y
68626   end
68627   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68628   cell $mux $ternary$libresoc.v:44491$1109
68629     parameter \WIDTH 1
68630     connect \A \mspi1_mosi__core__o
68631     connect \B \io_bd [57]
68632     connect \S \io_bd2io
68633     connect \Y $ternary$libresoc.v:44491$1109_Y
68634   end
68635   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
68636   cell $mux $ternary$libresoc.v:44492$1110
68637     parameter \WIDTH 1
68638     connect \A \mspi1_miso__pad__i
68639     connect \B \io_bd [58]
68640     connect \S \io_bd2core
68641     connect \Y $ternary$libresoc.v:44492$1110_Y
68642   end
68643   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68644   cell $mux $ternary$libresoc.v:44493$1111
68645     parameter \WIDTH 1
68646     connect \A \mtwi_sda__pad__i
68647     connect \B \io_bd [59]
68648     connect \S \io_bd2core
68649     connect \Y $ternary$libresoc.v:44493$1111_Y
68650   end
68651   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68652   cell $mux $ternary$libresoc.v:44494$1112
68653     parameter \WIDTH 1
68654     connect \A \mtwi_sda__core__o
68655     connect \B \io_bd [60]
68656     connect \S \io_bd2io
68657     connect \Y $ternary$libresoc.v:44494$1112_Y
68658   end
68659   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68660   cell $mux $ternary$libresoc.v:44495$1113
68661     parameter \WIDTH 1
68662     connect \A \mtwi_sda__core__oe
68663     connect \B \io_bd [61]
68664     connect \S \io_bd2io
68665     connect \Y $ternary$libresoc.v:44495$1113_Y
68666   end
68667   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68668   cell $mux $ternary$libresoc.v:44496$1114
68669     parameter \WIDTH 1
68670     connect \A \mtwi_scl__core__o
68671     connect \B \io_bd [62]
68672     connect \S \io_bd2io
68673     connect \Y $ternary$libresoc.v:44496$1114_Y
68674   end
68675   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68676   cell $mux $ternary$libresoc.v:44497$1115
68677     parameter \WIDTH 1
68678     connect \A \pwm_0__core__o
68679     connect \B \io_bd [63]
68680     connect \S \io_bd2io
68681     connect \Y $ternary$libresoc.v:44497$1115_Y
68682   end
68683   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68684   cell $mux $ternary$libresoc.v:44499$1117
68685     parameter \WIDTH 1
68686     connect \A \pwm_1__core__o
68687     connect \B \io_bd [64]
68688     connect \S \io_bd2io
68689     connect \Y $ternary$libresoc.v:44499$1117_Y
68690   end
68691   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68692   cell $mux $ternary$libresoc.v:44500$1118
68693     parameter \WIDTH 1
68694     connect \A \sd0_cmd__pad__i
68695     connect \B \io_bd [65]
68696     connect \S \io_bd2core
68697     connect \Y $ternary$libresoc.v:44500$1118_Y
68698   end
68699   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68700   cell $mux $ternary$libresoc.v:44501$1119
68701     parameter \WIDTH 1
68702     connect \A \sd0_cmd__core__o
68703     connect \B \io_bd [66]
68704     connect \S \io_bd2io
68705     connect \Y $ternary$libresoc.v:44501$1119_Y
68706   end
68707   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68708   cell $mux $ternary$libresoc.v:44502$1120
68709     parameter \WIDTH 1
68710     connect \A \sd0_cmd__core__oe
68711     connect \B \io_bd [67]
68712     connect \S \io_bd2io
68713     connect \Y $ternary$libresoc.v:44502$1120_Y
68714   end
68715   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68716   cell $mux $ternary$libresoc.v:44503$1121
68717     parameter \WIDTH 1
68718     connect \A \sd0_clk__core__o
68719     connect \B \io_bd [68]
68720     connect \S \io_bd2io
68721     connect \Y $ternary$libresoc.v:44503$1121_Y
68722   end
68723   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68724   cell $mux $ternary$libresoc.v:44504$1122
68725     parameter \WIDTH 1
68726     connect \A \sd0_data0__pad__i
68727     connect \B \io_bd [69]
68728     connect \S \io_bd2core
68729     connect \Y $ternary$libresoc.v:44504$1122_Y
68730   end
68731   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68732   cell $mux $ternary$libresoc.v:44505$1123
68733     parameter \WIDTH 1
68734     connect \A \sd0_data0__core__o
68735     connect \B \io_bd [70]
68736     connect \S \io_bd2io
68737     connect \Y $ternary$libresoc.v:44505$1123_Y
68738   end
68739   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68740   cell $mux $ternary$libresoc.v:44506$1124
68741     parameter \WIDTH 1
68742     connect \A \sd0_data0__core__oe
68743     connect \B \io_bd [71]
68744     connect \S \io_bd2io
68745     connect \Y $ternary$libresoc.v:44506$1124_Y
68746   end
68747   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68748   cell $mux $ternary$libresoc.v:44507$1125
68749     parameter \WIDTH 1
68750     connect \A \sd0_data1__pad__i
68751     connect \B \io_bd [72]
68752     connect \S \io_bd2core
68753     connect \Y $ternary$libresoc.v:44507$1125_Y
68754   end
68755   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68756   cell $mux $ternary$libresoc.v:44508$1126
68757     parameter \WIDTH 1
68758     connect \A \sd0_data1__core__o
68759     connect \B \io_bd [73]
68760     connect \S \io_bd2io
68761     connect \Y $ternary$libresoc.v:44508$1126_Y
68762   end
68763   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68764   cell $mux $ternary$libresoc.v:44511$1129
68765     parameter \WIDTH 1
68766     connect \A \sd0_data1__core__oe
68767     connect \B \io_bd [74]
68768     connect \S \io_bd2io
68769     connect \Y $ternary$libresoc.v:44511$1129_Y
68770   end
68771   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68772   cell $mux $ternary$libresoc.v:44512$1130
68773     parameter \WIDTH 1
68774     connect \A \sd0_data2__pad__i
68775     connect \B \io_bd [75]
68776     connect \S \io_bd2core
68777     connect \Y $ternary$libresoc.v:44512$1130_Y
68778   end
68779   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68780   cell $mux $ternary$libresoc.v:44513$1131
68781     parameter \WIDTH 1
68782     connect \A \sd0_data2__core__o
68783     connect \B \io_bd [76]
68784     connect \S \io_bd2io
68785     connect \Y $ternary$libresoc.v:44513$1131_Y
68786   end
68787   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68788   cell $mux $ternary$libresoc.v:44514$1132
68789     parameter \WIDTH 1
68790     connect \A \sd0_data2__core__oe
68791     connect \B \io_bd [77]
68792     connect \S \io_bd2io
68793     connect \Y $ternary$libresoc.v:44514$1132_Y
68794   end
68795   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68796   cell $mux $ternary$libresoc.v:44515$1133
68797     parameter \WIDTH 1
68798     connect \A \sd0_data3__pad__i
68799     connect \B \io_bd [78]
68800     connect \S \io_bd2core
68801     connect \Y $ternary$libresoc.v:44515$1133_Y
68802   end
68803   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68804   cell $mux $ternary$libresoc.v:44516$1134
68805     parameter \WIDTH 1
68806     connect \A \sd0_data3__core__o
68807     connect \B \io_bd [79]
68808     connect \S \io_bd2io
68809     connect \Y $ternary$libresoc.v:44516$1134_Y
68810   end
68811   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68812   cell $mux $ternary$libresoc.v:44517$1135
68813     parameter \WIDTH 1
68814     connect \A \sd0_data3__core__oe
68815     connect \B \io_bd [80]
68816     connect \S \io_bd2io
68817     connect \Y $ternary$libresoc.v:44517$1135_Y
68818   end
68819   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
68820   cell $mux $ternary$libresoc.v:44518$1136
68821     parameter \WIDTH 1
68822     connect \A \sdr_dm_0__core__o
68823     connect \B \io_bd [81]
68824     connect \S \io_bd2io
68825     connect \Y $ternary$libresoc.v:44518$1136_Y
68826   end
68827   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68828   cell $mux $ternary$libresoc.v:44519$1137
68829     parameter \WIDTH 1
68830     connect \A \sdr_dq_0__pad__i
68831     connect \B \io_bd [82]
68832     connect \S \io_bd2core
68833     connect \Y $ternary$libresoc.v:44519$1137_Y
68834   end
68835   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68836   cell $mux $ternary$libresoc.v:44520$1138
68837     parameter \WIDTH 1
68838     connect \A \sdr_dq_0__core__o
68839     connect \B \io_bd [83]
68840     connect \S \io_bd2io
68841     connect \Y $ternary$libresoc.v:44520$1138_Y
68842   end
68843   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68844   cell $mux $ternary$libresoc.v:44522$1140
68845     parameter \WIDTH 1
68846     connect \A \sdr_dq_0__core__oe
68847     connect \B \io_bd [84]
68848     connect \S \io_bd2io
68849     connect \Y $ternary$libresoc.v:44522$1140_Y
68850   end
68851   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68852   cell $mux $ternary$libresoc.v:44523$1141
68853     parameter \WIDTH 1
68854     connect \A \sdr_dq_1__pad__i
68855     connect \B \io_bd [85]
68856     connect \S \io_bd2core
68857     connect \Y $ternary$libresoc.v:44523$1141_Y
68858   end
68859   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68860   cell $mux $ternary$libresoc.v:44524$1142
68861     parameter \WIDTH 1
68862     connect \A \sdr_dq_1__core__o
68863     connect \B \io_bd [86]
68864     connect \S \io_bd2io
68865     connect \Y $ternary$libresoc.v:44524$1142_Y
68866   end
68867   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68868   cell $mux $ternary$libresoc.v:44525$1143
68869     parameter \WIDTH 1
68870     connect \A \sdr_dq_1__core__oe
68871     connect \B \io_bd [87]
68872     connect \S \io_bd2io
68873     connect \Y $ternary$libresoc.v:44525$1143_Y
68874   end
68875   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68876   cell $mux $ternary$libresoc.v:44526$1144
68877     parameter \WIDTH 1
68878     connect \A \sdr_dq_2__pad__i
68879     connect \B \io_bd [88]
68880     connect \S \io_bd2core
68881     connect \Y $ternary$libresoc.v:44526$1144_Y
68882   end
68883   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68884   cell $mux $ternary$libresoc.v:44527$1145
68885     parameter \WIDTH 1
68886     connect \A \sdr_dq_2__core__o
68887     connect \B \io_bd [89]
68888     connect \S \io_bd2io
68889     connect \Y $ternary$libresoc.v:44527$1145_Y
68890   end
68891   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68892   cell $mux $ternary$libresoc.v:44528$1146
68893     parameter \WIDTH 1
68894     connect \A \sdr_dq_2__core__oe
68895     connect \B \io_bd [90]
68896     connect \S \io_bd2io
68897     connect \Y $ternary$libresoc.v:44528$1146_Y
68898   end
68899   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68900   cell $mux $ternary$libresoc.v:44529$1147
68901     parameter \WIDTH 1
68902     connect \A \sdr_dq_3__pad__i
68903     connect \B \io_bd [91]
68904     connect \S \io_bd2core
68905     connect \Y $ternary$libresoc.v:44529$1147_Y
68906   end
68907   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68908   cell $mux $ternary$libresoc.v:44530$1148
68909     parameter \WIDTH 1
68910     connect \A \sdr_dq_3__core__o
68911     connect \B \io_bd [92]
68912     connect \S \io_bd2io
68913     connect \Y $ternary$libresoc.v:44530$1148_Y
68914   end
68915   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68916   cell $mux $ternary$libresoc.v:44531$1149
68917     parameter \WIDTH 1
68918     connect \A \sdr_dq_3__core__oe
68919     connect \B \io_bd [93]
68920     connect \S \io_bd2io
68921     connect \Y $ternary$libresoc.v:44531$1149_Y
68922   end
68923   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68924   cell $mux $ternary$libresoc.v:44533$1151
68925     parameter \WIDTH 1
68926     connect \A \sdr_dq_4__pad__i
68927     connect \B \io_bd [94]
68928     connect \S \io_bd2core
68929     connect \Y $ternary$libresoc.v:44533$1151_Y
68930   end
68931   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68932   cell $mux $ternary$libresoc.v:44534$1152
68933     parameter \WIDTH 1
68934     connect \A \sdr_dq_4__core__o
68935     connect \B \io_bd [95]
68936     connect \S \io_bd2io
68937     connect \Y $ternary$libresoc.v:44534$1152_Y
68938   end
68939   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68940   cell $mux $ternary$libresoc.v:44535$1153
68941     parameter \WIDTH 1
68942     connect \A \sdr_dq_4__core__oe
68943     connect \B \io_bd [96]
68944     connect \S \io_bd2io
68945     connect \Y $ternary$libresoc.v:44535$1153_Y
68946   end
68947   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68948   cell $mux $ternary$libresoc.v:44536$1154
68949     parameter \WIDTH 1
68950     connect \A \sdr_dq_5__pad__i
68951     connect \B \io_bd [97]
68952     connect \S \io_bd2core
68953     connect \Y $ternary$libresoc.v:44536$1154_Y
68954   end
68955   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68956   cell $mux $ternary$libresoc.v:44537$1155
68957     parameter \WIDTH 1
68958     connect \A \sdr_dq_5__core__o
68959     connect \B \io_bd [98]
68960     connect \S \io_bd2io
68961     connect \Y $ternary$libresoc.v:44537$1155_Y
68962   end
68963   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68964   cell $mux $ternary$libresoc.v:44538$1156
68965     parameter \WIDTH 1
68966     connect \A \sdr_dq_5__core__oe
68967     connect \B \io_bd [99]
68968     connect \S \io_bd2io
68969     connect \Y $ternary$libresoc.v:44538$1156_Y
68970   end
68971   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68972   cell $mux $ternary$libresoc.v:44539$1157
68973     parameter \WIDTH 1
68974     connect \A \sdr_dq_6__pad__i
68975     connect \B \io_bd [100]
68976     connect \S \io_bd2core
68977     connect \Y $ternary$libresoc.v:44539$1157_Y
68978   end
68979   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
68980   cell $mux $ternary$libresoc.v:44540$1158
68981     parameter \WIDTH 1
68982     connect \A \sdr_dq_6__core__o
68983     connect \B \io_bd [101]
68984     connect \S \io_bd2io
68985     connect \Y $ternary$libresoc.v:44540$1158_Y
68986   end
68987   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
68988   cell $mux $ternary$libresoc.v:44541$1159
68989     parameter \WIDTH 1
68990     connect \A \sdr_dq_6__core__oe
68991     connect \B \io_bd [102]
68992     connect \S \io_bd2io
68993     connect \Y $ternary$libresoc.v:44541$1159_Y
68994   end
68995   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
68996   cell $mux $ternary$libresoc.v:44542$1160
68997     parameter \WIDTH 1
68998     connect \A \sdr_dq_7__pad__i
68999     connect \B \io_bd [103]
69000     connect \S \io_bd2core
69001     connect \Y $ternary$libresoc.v:44542$1160_Y
69002   end
69003   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69004   cell $mux $ternary$libresoc.v:44544$1162
69005     parameter \WIDTH 1
69006     connect \A \sdr_dq_7__core__o
69007     connect \B \io_bd [104]
69008     connect \S \io_bd2io
69009     connect \Y $ternary$libresoc.v:44544$1162_Y
69010   end
69011   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69012   cell $mux $ternary$libresoc.v:44545$1163
69013     parameter \WIDTH 1
69014     connect \A \sdr_dq_7__core__oe
69015     connect \B \io_bd [105]
69016     connect \S \io_bd2io
69017     connect \Y $ternary$libresoc.v:44545$1163_Y
69018   end
69019   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69020   cell $mux $ternary$libresoc.v:44546$1164
69021     parameter \WIDTH 1
69022     connect \A \sdr_a_0__core__o
69023     connect \B \io_bd [106]
69024     connect \S \io_bd2io
69025     connect \Y $ternary$libresoc.v:44546$1164_Y
69026   end
69027   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69028   cell $mux $ternary$libresoc.v:44547$1165
69029     parameter \WIDTH 1
69030     connect \A \sdr_a_1__core__o
69031     connect \B \io_bd [107]
69032     connect \S \io_bd2io
69033     connect \Y $ternary$libresoc.v:44547$1165_Y
69034   end
69035   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69036   cell $mux $ternary$libresoc.v:44548$1166
69037     parameter \WIDTH 1
69038     connect \A \sdr_a_2__core__o
69039     connect \B \io_bd [108]
69040     connect \S \io_bd2io
69041     connect \Y $ternary$libresoc.v:44548$1166_Y
69042   end
69043   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69044   cell $mux $ternary$libresoc.v:44549$1167
69045     parameter \WIDTH 1
69046     connect \A \sdr_a_3__core__o
69047     connect \B \io_bd [109]
69048     connect \S \io_bd2io
69049     connect \Y $ternary$libresoc.v:44549$1167_Y
69050   end
69051   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69052   cell $mux $ternary$libresoc.v:44550$1168
69053     parameter \WIDTH 1
69054     connect \A \sdr_a_4__core__o
69055     connect \B \io_bd [110]
69056     connect \S \io_bd2io
69057     connect \Y $ternary$libresoc.v:44550$1168_Y
69058   end
69059   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69060   cell $mux $ternary$libresoc.v:44551$1169
69061     parameter \WIDTH 1
69062     connect \A \sdr_a_5__core__o
69063     connect \B \io_bd [111]
69064     connect \S \io_bd2io
69065     connect \Y $ternary$libresoc.v:44551$1169_Y
69066   end
69067   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69068   cell $mux $ternary$libresoc.v:44552$1170
69069     parameter \WIDTH 1
69070     connect \A \sdr_a_6__core__o
69071     connect \B \io_bd [112]
69072     connect \S \io_bd2io
69073     connect \Y $ternary$libresoc.v:44552$1170_Y
69074   end
69075   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69076   cell $mux $ternary$libresoc.v:44553$1171
69077     parameter \WIDTH 1
69078     connect \A \sdr_a_7__core__o
69079     connect \B \io_bd [113]
69080     connect \S \io_bd2io
69081     connect \Y $ternary$libresoc.v:44553$1171_Y
69082   end
69083   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69084   cell $mux $ternary$libresoc.v:44555$1173
69085     parameter \WIDTH 1
69086     connect \A \sdr_a_8__core__o
69087     connect \B \io_bd [114]
69088     connect \S \io_bd2io
69089     connect \Y $ternary$libresoc.v:44555$1173_Y
69090   end
69091   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69092   cell $mux $ternary$libresoc.v:44556$1174
69093     parameter \WIDTH 1
69094     connect \A \sdr_a_9__core__o
69095     connect \B \io_bd [115]
69096     connect \S \io_bd2io
69097     connect \Y $ternary$libresoc.v:44556$1174_Y
69098   end
69099   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69100   cell $mux $ternary$libresoc.v:44557$1175
69101     parameter \WIDTH 1
69102     connect \A \sdr_ba_0__core__o
69103     connect \B \io_bd [116]
69104     connect \S \io_bd2io
69105     connect \Y $ternary$libresoc.v:44557$1175_Y
69106   end
69107   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69108   cell $mux $ternary$libresoc.v:44558$1176
69109     parameter \WIDTH 1
69110     connect \A \sdr_ba_1__core__o
69111     connect \B \io_bd [117]
69112     connect \S \io_bd2io
69113     connect \Y $ternary$libresoc.v:44558$1176_Y
69114   end
69115   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69116   cell $mux $ternary$libresoc.v:44559$1177
69117     parameter \WIDTH 1
69118     connect \A \sdr_clock__core__o
69119     connect \B \io_bd [118]
69120     connect \S \io_bd2io
69121     connect \Y $ternary$libresoc.v:44559$1177_Y
69122   end
69123   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69124   cell $mux $ternary$libresoc.v:44560$1178
69125     parameter \WIDTH 1
69126     connect \A \sdr_cke__core__o
69127     connect \B \io_bd [119]
69128     connect \S \io_bd2io
69129     connect \Y $ternary$libresoc.v:44560$1178_Y
69130   end
69131   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69132   cell $mux $ternary$libresoc.v:44561$1179
69133     parameter \WIDTH 1
69134     connect \A \sdr_ras_n__core__o
69135     connect \B \io_bd [120]
69136     connect \S \io_bd2io
69137     connect \Y $ternary$libresoc.v:44561$1179_Y
69138   end
69139   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69140   cell $mux $ternary$libresoc.v:44562$1180
69141     parameter \WIDTH 1
69142     connect \A \sdr_cas_n__core__o
69143     connect \B \io_bd [121]
69144     connect \S \io_bd2io
69145     connect \Y $ternary$libresoc.v:44562$1180_Y
69146   end
69147   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69148   cell $mux $ternary$libresoc.v:44563$1181
69149     parameter \WIDTH 1
69150     connect \A \sdr_we_n__core__o
69151     connect \B \io_bd [122]
69152     connect \S \io_bd2io
69153     connect \Y $ternary$libresoc.v:44563$1181_Y
69154   end
69155   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69156   cell $mux $ternary$libresoc.v:44564$1182
69157     parameter \WIDTH 1
69158     connect \A \sdr_cs_n__core__o
69159     connect \B \io_bd [123]
69160     connect \S \io_bd2io
69161     connect \Y $ternary$libresoc.v:44564$1182_Y
69162   end
69163   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69164   cell $mux $ternary$libresoc.v:44566$1184
69165     parameter \WIDTH 1
69166     connect \A \sdr_a_10__core__o
69167     connect \B \io_bd [124]
69168     connect \S \io_bd2io
69169     connect \Y $ternary$libresoc.v:44566$1184_Y
69170   end
69171   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69172   cell $mux $ternary$libresoc.v:44567$1185
69173     parameter \WIDTH 1
69174     connect \A \sdr_a_11__core__o
69175     connect \B \io_bd [125]
69176     connect \S \io_bd2io
69177     connect \Y $ternary$libresoc.v:44567$1185_Y
69178   end
69179   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585"
69180   cell $mux $ternary$libresoc.v:44568$1186
69181     parameter \WIDTH 1
69182     connect \A \sdr_a_12__core__o
69183     connect \B \io_bd [126]
69184     connect \S \io_bd2io
69185     connect \Y $ternary$libresoc.v:44568$1186_Y
69186   end
69187   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69188   cell $mux $ternary$libresoc.v:44569$1187
69189     parameter \WIDTH 1
69190     connect \A \sdr_dm_1__pad__i
69191     connect \B \io_bd [127]
69192     connect \S \io_bd2core
69193     connect \Y $ternary$libresoc.v:44569$1187_Y
69194   end
69195   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69196   cell $mux $ternary$libresoc.v:44570$1188
69197     parameter \WIDTH 1
69198     connect \A \sdr_dm_1__core__o
69199     connect \B \io_bd [128]
69200     connect \S \io_bd2io
69201     connect \Y $ternary$libresoc.v:44570$1188_Y
69202   end
69203   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69204   cell $mux $ternary$libresoc.v:44571$1189
69205     parameter \WIDTH 1
69206     connect \A \sdr_dm_1__core__oe
69207     connect \B \io_bd [129]
69208     connect \S \io_bd2io
69209     connect \Y $ternary$libresoc.v:44571$1189_Y
69210   end
69211   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69212   cell $mux $ternary$libresoc.v:44572$1190
69213     parameter \WIDTH 1
69214     connect \A \sdr_dq_8__pad__i
69215     connect \B \io_bd [130]
69216     connect \S \io_bd2core
69217     connect \Y $ternary$libresoc.v:44572$1190_Y
69218   end
69219   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69220   cell $mux $ternary$libresoc.v:44573$1191
69221     parameter \WIDTH 1
69222     connect \A \sdr_dq_8__core__o
69223     connect \B \io_bd [131]
69224     connect \S \io_bd2io
69225     connect \Y $ternary$libresoc.v:44573$1191_Y
69226   end
69227   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69228   cell $mux $ternary$libresoc.v:44574$1192
69229     parameter \WIDTH 1
69230     connect \A \sdr_dq_8__core__oe
69231     connect \B \io_bd [132]
69232     connect \S \io_bd2io
69233     connect \Y $ternary$libresoc.v:44574$1192_Y
69234   end
69235   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69236   cell $mux $ternary$libresoc.v:44575$1193
69237     parameter \WIDTH 1
69238     connect \A \sdr_dq_9__pad__i
69239     connect \B \io_bd [133]
69240     connect \S \io_bd2core
69241     connect \Y $ternary$libresoc.v:44575$1193_Y
69242   end
69243   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69244   cell $mux $ternary$libresoc.v:44577$1195
69245     parameter \WIDTH 1
69246     connect \A \sdr_dq_9__core__o
69247     connect \B \io_bd [134]
69248     connect \S \io_bd2io
69249     connect \Y $ternary$libresoc.v:44577$1195_Y
69250   end
69251   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69252   cell $mux $ternary$libresoc.v:44578$1196
69253     parameter \WIDTH 1
69254     connect \A \sdr_dq_9__core__oe
69255     connect \B \io_bd [135]
69256     connect \S \io_bd2io
69257     connect \Y $ternary$libresoc.v:44578$1196_Y
69258   end
69259   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69260   cell $mux $ternary$libresoc.v:44579$1197
69261     parameter \WIDTH 1
69262     connect \A \sdr_dq_10__pad__i
69263     connect \B \io_bd [136]
69264     connect \S \io_bd2core
69265     connect \Y $ternary$libresoc.v:44579$1197_Y
69266   end
69267   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69268   cell $mux $ternary$libresoc.v:44580$1198
69269     parameter \WIDTH 1
69270     connect \A \sdr_dq_10__core__o
69271     connect \B \io_bd [137]
69272     connect \S \io_bd2io
69273     connect \Y $ternary$libresoc.v:44580$1198_Y
69274   end
69275   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69276   cell $mux $ternary$libresoc.v:44581$1199
69277     parameter \WIDTH 1
69278     connect \A \sdr_dq_10__core__oe
69279     connect \B \io_bd [138]
69280     connect \S \io_bd2io
69281     connect \Y $ternary$libresoc.v:44581$1199_Y
69282   end
69283   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69284   cell $mux $ternary$libresoc.v:44582$1200
69285     parameter \WIDTH 1
69286     connect \A \sdr_dq_11__pad__i
69287     connect \B \io_bd [139]
69288     connect \S \io_bd2core
69289     connect \Y $ternary$libresoc.v:44582$1200_Y
69290   end
69291   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69292   cell $mux $ternary$libresoc.v:44583$1201
69293     parameter \WIDTH 1
69294     connect \A \sdr_dq_11__core__o
69295     connect \B \io_bd [140]
69296     connect \S \io_bd2io
69297     connect \Y $ternary$libresoc.v:44583$1201_Y
69298   end
69299   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69300   cell $mux $ternary$libresoc.v:44584$1202
69301     parameter \WIDTH 1
69302     connect \A \sdr_dq_11__core__oe
69303     connect \B \io_bd [141]
69304     connect \S \io_bd2io
69305     connect \Y $ternary$libresoc.v:44584$1202_Y
69306   end
69307   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69308   cell $mux $ternary$libresoc.v:44585$1203
69309     parameter \WIDTH 1
69310     connect \A \sdr_dq_12__pad__i
69311     connect \B \io_bd [142]
69312     connect \S \io_bd2core
69313     connect \Y $ternary$libresoc.v:44585$1203_Y
69314   end
69315   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69316   cell $mux $ternary$libresoc.v:44586$1204
69317     parameter \WIDTH 1
69318     connect \A \sdr_dq_12__core__o
69319     connect \B \io_bd [143]
69320     connect \S \io_bd2io
69321     connect \Y $ternary$libresoc.v:44586$1204_Y
69322   end
69323   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69324   cell $mux $ternary$libresoc.v:44588$1206
69325     parameter \WIDTH 1
69326     connect \A \sdr_dq_12__core__oe
69327     connect \B \io_bd [144]
69328     connect \S \io_bd2io
69329     connect \Y $ternary$libresoc.v:44588$1206_Y
69330   end
69331   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69332   cell $mux $ternary$libresoc.v:44589$1207
69333     parameter \WIDTH 1
69334     connect \A \sdr_dq_13__pad__i
69335     connect \B \io_bd [145]
69336     connect \S \io_bd2core
69337     connect \Y $ternary$libresoc.v:44589$1207_Y
69338   end
69339   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69340   cell $mux $ternary$libresoc.v:44590$1208
69341     parameter \WIDTH 1
69342     connect \A \sdr_dq_13__core__o
69343     connect \B \io_bd [146]
69344     connect \S \io_bd2io
69345     connect \Y $ternary$libresoc.v:44590$1208_Y
69346   end
69347   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69348   cell $mux $ternary$libresoc.v:44591$1209
69349     parameter \WIDTH 1
69350     connect \A \sdr_dq_13__core__oe
69351     connect \B \io_bd [147]
69352     connect \S \io_bd2io
69353     connect \Y $ternary$libresoc.v:44591$1209_Y
69354   end
69355   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69356   cell $mux $ternary$libresoc.v:44592$1210
69357     parameter \WIDTH 1
69358     connect \A \sdr_dq_14__pad__i
69359     connect \B \io_bd [148]
69360     connect \S \io_bd2core
69361     connect \Y $ternary$libresoc.v:44592$1210_Y
69362   end
69363   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69364   cell $mux $ternary$libresoc.v:44593$1211
69365     parameter \WIDTH 1
69366     connect \A \sdr_dq_14__core__o
69367     connect \B \io_bd [149]
69368     connect \S \io_bd2io
69369     connect \Y $ternary$libresoc.v:44593$1211_Y
69370   end
69371   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69372   cell $mux $ternary$libresoc.v:44594$1212
69373     parameter \WIDTH 1
69374     connect \A \sdr_dq_14__core__oe
69375     connect \B \io_bd [150]
69376     connect \S \io_bd2io
69377     connect \Y $ternary$libresoc.v:44594$1212_Y
69378   end
69379   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69380   cell $mux $ternary$libresoc.v:44595$1213
69381     parameter \WIDTH 1
69382     connect \A \sdr_dq_15__pad__i
69383     connect \B \io_bd [151]
69384     connect \S \io_bd2core
69385     connect \Y $ternary$libresoc.v:44595$1213_Y
69386   end
69387   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69388   cell $mux $ternary$libresoc.v:44596$1214
69389     parameter \WIDTH 1
69390     connect \A \sdr_dq_15__core__o
69391     connect \B \io_bd [152]
69392     connect \S \io_bd2io
69393     connect \Y $ternary$libresoc.v:44596$1214_Y
69394   end
69395   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69396   cell $mux $ternary$libresoc.v:44597$1215
69397     parameter \WIDTH 1
69398     connect \A \sdr_dq_15__core__oe
69399     connect \B \io_bd [153]
69400     connect \S \io_bd2io
69401     connect \Y $ternary$libresoc.v:44597$1215_Y
69402   end
69403   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
69404   cell $mux $ternary$libresoc.v:44684$1303
69405     parameter \WIDTH 1
69406     connect \A \eint_0__pad__i
69407     connect \B \io_bd [0]
69408     connect \S \io_bd2core
69409     connect \Y $ternary$libresoc.v:44684$1303_Y
69410   end
69411   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
69412   cell $mux $ternary$libresoc.v:44685$1304
69413     parameter \WIDTH 1
69414     connect \A \eint_1__pad__i
69415     connect \B \io_bd [1]
69416     connect \S \io_bd2core
69417     connect \Y $ternary$libresoc.v:44685$1304_Y
69418   end
69419   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582"
69420   cell $mux $ternary$libresoc.v:44686$1305
69421     parameter \WIDTH 1
69422     connect \A \eint_2__pad__i
69423     connect \B \io_bd [2]
69424     connect \S \io_bd2core
69425     connect \Y $ternary$libresoc.v:44686$1305_Y
69426   end
69427   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69428   cell $mux $ternary$libresoc.v:44687$1306
69429     parameter \WIDTH 1
69430     connect \A \gpio_e8__pad__i
69431     connect \B \io_bd [3]
69432     connect \S \io_bd2core
69433     connect \Y $ternary$libresoc.v:44687$1306_Y
69434   end
69435   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69436   cell $mux $ternary$libresoc.v:44689$1308
69437     parameter \WIDTH 1
69438     connect \A \gpio_e8__core__o
69439     connect \B \io_bd [4]
69440     connect \S \io_bd2io
69441     connect \Y $ternary$libresoc.v:44689$1308_Y
69442   end
69443   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69444   cell $mux $ternary$libresoc.v:44690$1309
69445     parameter \WIDTH 1
69446     connect \A \gpio_e8__core__oe
69447     connect \B \io_bd [5]
69448     connect \S \io_bd2io
69449     connect \Y $ternary$libresoc.v:44690$1309_Y
69450   end
69451   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69452   cell $mux $ternary$libresoc.v:44691$1310
69453     parameter \WIDTH 1
69454     connect \A \gpio_e9__pad__i
69455     connect \B \io_bd [6]
69456     connect \S \io_bd2core
69457     connect \Y $ternary$libresoc.v:44691$1310_Y
69458   end
69459   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69460   cell $mux $ternary$libresoc.v:44692$1311
69461     parameter \WIDTH 1
69462     connect \A \gpio_e9__core__o
69463     connect \B \io_bd [7]
69464     connect \S \io_bd2io
69465     connect \Y $ternary$libresoc.v:44692$1311_Y
69466   end
69467   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69468   cell $mux $ternary$libresoc.v:44693$1312
69469     parameter \WIDTH 1
69470     connect \A \gpio_e9__core__oe
69471     connect \B \io_bd [8]
69472     connect \S \io_bd2io
69473     connect \Y $ternary$libresoc.v:44693$1312_Y
69474   end
69475   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69476   cell $mux $ternary$libresoc.v:44694$1313
69477     parameter \WIDTH 1
69478     connect \A \gpio_e10__pad__i
69479     connect \B \io_bd [9]
69480     connect \S \io_bd2core
69481     connect \Y $ternary$libresoc.v:44694$1313_Y
69482   end
69483   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69484   cell $mux $ternary$libresoc.v:44695$1314
69485     parameter \WIDTH 1
69486     connect \A \gpio_e10__core__o
69487     connect \B \io_bd [10]
69488     connect \S \io_bd2io
69489     connect \Y $ternary$libresoc.v:44695$1314_Y
69490   end
69491   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69492   cell $mux $ternary$libresoc.v:44696$1315
69493     parameter \WIDTH 1
69494     connect \A \gpio_e10__core__oe
69495     connect \B \io_bd [11]
69496     connect \S \io_bd2io
69497     connect \Y $ternary$libresoc.v:44696$1315_Y
69498   end
69499   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69500   cell $mux $ternary$libresoc.v:44697$1316
69501     parameter \WIDTH 1
69502     connect \A \gpio_e11__pad__i
69503     connect \B \io_bd [12]
69504     connect \S \io_bd2core
69505     connect \Y $ternary$libresoc.v:44697$1316_Y
69506   end
69507   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69508   cell $mux $ternary$libresoc.v:44698$1317
69509     parameter \WIDTH 1
69510     connect \A \gpio_e11__core__o
69511     connect \B \io_bd [13]
69512     connect \S \io_bd2io
69513     connect \Y $ternary$libresoc.v:44698$1317_Y
69514   end
69515   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69516   cell $mux $ternary$libresoc.v:44700$1319
69517     parameter \WIDTH 1
69518     connect \A \gpio_e11__core__oe
69519     connect \B \io_bd [14]
69520     connect \S \io_bd2io
69521     connect \Y $ternary$libresoc.v:44700$1319_Y
69522   end
69523   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69524   cell $mux $ternary$libresoc.v:44701$1320
69525     parameter \WIDTH 1
69526     connect \A \gpio_e12__pad__i
69527     connect \B \io_bd [15]
69528     connect \S \io_bd2core
69529     connect \Y $ternary$libresoc.v:44701$1320_Y
69530   end
69531   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69532   cell $mux $ternary$libresoc.v:44702$1321
69533     parameter \WIDTH 1
69534     connect \A \gpio_e12__core__o
69535     connect \B \io_bd [16]
69536     connect \S \io_bd2io
69537     connect \Y $ternary$libresoc.v:44702$1321_Y
69538   end
69539   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69540   cell $mux $ternary$libresoc.v:44703$1322
69541     parameter \WIDTH 1
69542     connect \A \gpio_e12__core__oe
69543     connect \B \io_bd [17]
69544     connect \S \io_bd2io
69545     connect \Y $ternary$libresoc.v:44703$1322_Y
69546   end
69547   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69548   cell $mux $ternary$libresoc.v:44704$1323
69549     parameter \WIDTH 1
69550     connect \A \gpio_e13__pad__i
69551     connect \B \io_bd [18]
69552     connect \S \io_bd2core
69553     connect \Y $ternary$libresoc.v:44704$1323_Y
69554   end
69555   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69556   cell $mux $ternary$libresoc.v:44705$1324
69557     parameter \WIDTH 1
69558     connect \A \gpio_e13__core__o
69559     connect \B \io_bd [19]
69560     connect \S \io_bd2io
69561     connect \Y $ternary$libresoc.v:44705$1324_Y
69562   end
69563   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69564   cell $mux $ternary$libresoc.v:44706$1325
69565     parameter \WIDTH 1
69566     connect \A \gpio_e13__core__oe
69567     connect \B \io_bd [20]
69568     connect \S \io_bd2io
69569     connect \Y $ternary$libresoc.v:44706$1325_Y
69570   end
69571   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595"
69572   cell $mux $ternary$libresoc.v:44707$1326
69573     parameter \WIDTH 1
69574     connect \A \gpio_e14__pad__i
69575     connect \B \io_bd [21]
69576     connect \S \io_bd2core
69577     connect \Y $ternary$libresoc.v:44707$1326_Y
69578   end
69579   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596"
69580   cell $mux $ternary$libresoc.v:44708$1327
69581     parameter \WIDTH 1
69582     connect \A \gpio_e14__core__o
69583     connect \B \io_bd [22]
69584     connect \S \io_bd2io
69585     connect \Y $ternary$libresoc.v:44708$1327_Y
69586   end
69587   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597"
69588   cell $mux $ternary$libresoc.v:44709$1328
69589     parameter \WIDTH 1
69590     connect \A \gpio_e14__core__oe
69591     connect \B \io_bd [23]
69592     connect \S \io_bd2io
69593     connect \Y $ternary$libresoc.v:44709$1328_Y
69594   end
69595   attribute \module_not_derived 1
69596   attribute \src "libresoc.v:44782.8-44794.4"
69597   cell \_fsm \_fsm
69598     connect \TAP_bus__tck \TAP_bus__tck
69599     connect \TAP_bus__tms \TAP_bus__tms
69600     connect \capture \_fsm_capture
69601     connect \isdr \_fsm_isdr
69602     connect \isir \_fsm_isir
69603     connect \negjtag_clk \negjtag_clk
69604     connect \negjtag_rst \negjtag_rst
69605     connect \posjtag_clk \posjtag_clk
69606     connect \posjtag_rst \posjtag_rst
69607     connect \shift \_fsm_shift
69608     connect \update \_fsm_update
69609   end
69610   attribute \module_not_derived 1
69611   attribute \src "libresoc.v:44795.12-44805.4"
69612   cell \_idblock \_idblock
69613     connect \TAP_bus__tdi \TAP_bus__tdi
69614     connect \TAP_id_tdo \_idblock_TAP_id_tdo
69615     connect \capture \_fsm_capture
69616     connect \id_bypass \_idblock_id_bypass
69617     connect \posjtag_clk \posjtag_clk
69618     connect \posjtag_rst \posjtag_rst
69619     connect \select_id \_idblock_select_id
69620     connect \shift \_fsm_shift
69621     connect \update \_fsm_update
69622   end
69623   attribute \module_not_derived 1
69624   attribute \src "libresoc.v:44806.12-44816.4"
69625   cell \_irblock \_irblock
69626     connect \TAP_bus__tdi \TAP_bus__tdi
69627     connect \capture \_fsm_capture
69628     connect \ir \_irblock_ir
69629     connect \isir \_fsm_isir
69630     connect \posjtag_clk \posjtag_clk
69631     connect \posjtag_rst \posjtag_rst
69632     connect \shift \_fsm_shift
69633     connect \tdo \_irblock_tdo
69634     connect \update \_fsm_update
69635   end
69636   attribute \src "libresoc.v:43025.7-43025.20"
69637   process $proc$libresoc.v:43025$1520
69638     assign { } { }
69639     assign $0\initial[0:0] 1'0
69640     sync always
69641       update \initial $0\initial[0:0]
69642     sync init
69643   end
69644   attribute \src "libresoc.v:43583.13-43583.32"
69645   process $proc$libresoc.v:43583$1521
69646     assign { } { }
69647     assign $1\dmi0__addr_i[3:0] 4'0000
69648     sync always
69649     sync init
69650       update \dmi0__addr_i $1\dmi0__addr_i[3:0]
69651   end
69652   attribute \src "libresoc.v:43588.14-43588.46"
69653   process $proc$libresoc.v:43588$1522
69654     assign { } { }
69655     assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
69656     sync always
69657     sync init
69658       update \dmi0__din $1\dmi0__din[63:0]
69659   end
69660   attribute \src "libresoc.v:43602.7-43602.29"
69661   process $proc$libresoc.v:43602$1523
69662     assign { } { }
69663     assign $1\dmi0_addrsr__oe[0:0] 1'0
69664     sync always
69665     sync init
69666       update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0]
69667   end
69668   attribute \src "libresoc.v:43610.13-43610.36"
69669   process $proc$libresoc.v:43610$1524
69670     assign { } { }
69671     assign $1\dmi0_addrsr_reg[7:0] 8'00000000
69672     sync always
69673     sync init
69674       update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0]
69675   end
69676   attribute \src "libresoc.v:43618.7-43618.37"
69677   process $proc$libresoc.v:43618$1525
69678     assign { } { }
69679     assign $1\dmi0_addrsr_update_core[0:0] 1'0
69680     sync always
69681     sync init
69682       update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0]
69683   end
69684   attribute \src "libresoc.v:43622.7-43622.42"
69685   process $proc$libresoc.v:43622$1526
69686     assign { } { }
69687     assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0
69688     sync always
69689     sync init
69690       update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0]
69691   end
69692   attribute \src "libresoc.v:43626.14-43626.51"
69693   process $proc$libresoc.v:43626$1527
69694     assign { } { }
69695     assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
69696     sync always
69697     sync init
69698       update \dmi0_datasr__i $1\dmi0_datasr__i[63:0]
69699   end
69700   attribute \src "libresoc.v:43632.13-43632.35"
69701   process $proc$libresoc.v:43632$1528
69702     assign { } { }
69703     assign $1\dmi0_datasr__oe[1:0] 2'00
69704     sync always
69705     sync init
69706       update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0]
69707   end
69708   attribute \src "libresoc.v:43640.14-43640.52"
69709   process $proc$libresoc.v:43640$1529
69710     assign { } { }
69711     assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
69712     sync always
69713     sync init
69714       update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0]
69715   end
69716   attribute \src "libresoc.v:43648.7-43648.37"
69717   process $proc$libresoc.v:43648$1530
69718     assign { } { }
69719     assign $1\dmi0_datasr_update_core[0:0] 1'0
69720     sync always
69721     sync init
69722       update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0]
69723   end
69724   attribute \src "libresoc.v:43652.7-43652.42"
69725   process $proc$libresoc.v:43652$1531
69726     assign { } { }
69727     assign $1\dmi0_datasr_update_core_prev[0:0] 1'0
69728     sync always
69729     sync init
69730       update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0]
69731   end
69732   attribute \src "libresoc.v:43668.13-43668.29"
69733   process $proc$libresoc.v:43668$1532
69734     assign { } { }
69735     assign $1\fsm_state[2:0] 3'000
69736     sync always
69737     sync init
69738       update \fsm_state $1\fsm_state[2:0]
69739   end
69740   attribute \src "libresoc.v:43670.13-43670.35"
69741   process $proc$libresoc.v:43670$1533
69742     assign { } { }
69743     assign $0\fsm_state$503[2:0]$1534 3'000
69744     sync always
69745     sync init
69746       update \fsm_state$503 $0\fsm_state$503[2:0]$1534
69747   end
69748   attribute \src "libresoc.v:43868.15-43868.67"
69749   process $proc$libresoc.v:43868$1535
69750     assign { } { }
69751     assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
69752     sync always
69753     sync init
69754       update \io_bd $1\io_bd[153:0]
69755   end
69756   attribute \src "libresoc.v:43880.15-43880.67"
69757   process $proc$libresoc.v:43880$1536
69758     assign { } { }
69759     assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
69760     sync always
69761     sync init
69762       update \io_sr $1\io_sr[153:0]
69763   end
69764   attribute \src "libresoc.v:43889.14-43889.41"
69765   process $proc$libresoc.v:43889$1537
69766     assign { } { }
69767     assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000
69768     sync always
69769     sync init
69770       update \jtag_wb__adr $1\jtag_wb__adr[28:0]
69771   end
69772   attribute \src "libresoc.v:43898.14-43898.51"
69773   process $proc$libresoc.v:43898$1538
69774     assign { } { }
69775     assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
69776     sync always
69777     sync init
69778       update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0]
69779   end
69780   attribute \src "libresoc.v:43912.7-43912.32"
69781   process $proc$libresoc.v:43912$1539
69782     assign { } { }
69783     assign $1\jtag_wb_addrsr__oe[0:0] 1'0
69784     sync always
69785     sync init
69786       update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0]
69787   end
69788   attribute \src "libresoc.v:43920.14-43920.47"
69789   process $proc$libresoc.v:43920$1540
69790     assign { } { }
69791     assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000
69792     sync always
69793     sync init
69794       update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0]
69795   end
69796   attribute \src "libresoc.v:43928.7-43928.40"
69797   process $proc$libresoc.v:43928$1541
69798     assign { } { }
69799     assign $1\jtag_wb_addrsr_update_core[0:0] 1'0
69800     sync always
69801     sync init
69802       update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0]
69803   end
69804   attribute \src "libresoc.v:43932.7-43932.45"
69805   process $proc$libresoc.v:43932$1542
69806     assign { } { }
69807     assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0
69808     sync always
69809     sync init
69810       update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0]
69811   end
69812   attribute \src "libresoc.v:43936.14-43936.54"
69813   process $proc$libresoc.v:43936$1543
69814     assign { } { }
69815     assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
69816     sync always
69817     sync init
69818       update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0]
69819   end
69820   attribute \src "libresoc.v:43942.13-43942.38"
69821   process $proc$libresoc.v:43942$1544
69822     assign { } { }
69823     assign $1\jtag_wb_datasr__oe[1:0] 2'00
69824     sync always
69825     sync init
69826       update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0]
69827   end
69828   attribute \src "libresoc.v:43950.14-43950.55"
69829   process $proc$libresoc.v:43950$1545
69830     assign { } { }
69831     assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
69832     sync always
69833     sync init
69834       update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0]
69835   end
69836   attribute \src "libresoc.v:43958.7-43958.40"
69837   process $proc$libresoc.v:43958$1546
69838     assign { } { }
69839     assign $1\jtag_wb_datasr_update_core[0:0] 1'0
69840     sync always
69841     sync init
69842       update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0]
69843   end
69844   attribute \src "libresoc.v:43962.7-43962.45"
69845   process $proc$libresoc.v:43962$1547
69846     assign { } { }
69847     assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0
69848     sync always
69849     sync init
69850       update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0]
69851   end
69852   attribute \src "libresoc.v:44392.7-44392.21"
69853   process $proc$libresoc.v:44392$1548
69854     assign { } { }
69855     assign $1\sr0__oe[0:0] 1'0
69856     sync always
69857     sync init
69858       update \sr0__oe $1\sr0__oe[0:0]
69859   end
69860   attribute \src "libresoc.v:44400.13-44400.27"
69861   process $proc$libresoc.v:44400$1549
69862     assign { } { }
69863     assign $1\sr0_reg[2:0] 3'000
69864     sync always
69865     sync init
69866       update \sr0_reg $1\sr0_reg[2:0]
69867   end
69868   attribute \src "libresoc.v:44408.7-44408.29"
69869   process $proc$libresoc.v:44408$1550
69870     assign { } { }
69871     assign $1\sr0_update_core[0:0] 1'0
69872     sync always
69873     sync init
69874       update \sr0_update_core $1\sr0_update_core[0:0]
69875   end
69876   attribute \src "libresoc.v:44412.7-44412.34"
69877   process $proc$libresoc.v:44412$1551
69878     assign { } { }
69879     assign $1\sr0_update_core_prev[0:0] 1'0
69880     sync always
69881     sync init
69882       update \sr0_update_core_prev $1\sr0_update_core_prev[0:0]
69883   end
69884   attribute \src "libresoc.v:44422.7-44422.21"
69885   process $proc$libresoc.v:44422$1552
69886     assign { } { }
69887     assign $1\sr5__oe[0:0] 1'0
69888     sync always
69889     sync init
69890       update \sr5__oe $1\sr5__oe[0:0]
69891   end
69892   attribute \src "libresoc.v:44430.13-44430.27"
69893   process $proc$libresoc.v:44430$1553
69894     assign { } { }
69895     assign $1\sr5_reg[1:0] 2'00
69896     sync always
69897     sync init
69898       update \sr5_reg $1\sr5_reg[1:0]
69899   end
69900   attribute \src "libresoc.v:44438.7-44438.29"
69901   process $proc$libresoc.v:44438$1554
69902     assign { } { }
69903     assign $1\sr5_update_core[0:0] 1'0
69904     sync always
69905     sync init
69906       update \sr5_update_core $1\sr5_update_core[0:0]
69907   end
69908   attribute \src "libresoc.v:44442.7-44442.34"
69909   process $proc$libresoc.v:44442$1555
69910     assign { } { }
69911     assign $1\sr5_update_core_prev[0:0] 1'0
69912     sync always
69913     sync init
69914       update \sr5_update_core_prev $1\sr5_update_core_prev[0:0]
69915   end
69916   attribute \src "libresoc.v:44446.7-44446.26"
69917   process $proc$libresoc.v:44446$1556
69918     assign { } { }
69919     assign $1\wb_dcache_en[0:0] 1'1
69920     sync always
69921     sync init
69922       update \wb_dcache_en $1\wb_dcache_en[0:0]
69923   end
69924   attribute \src "libresoc.v:44451.7-44451.26"
69925   process $proc$libresoc.v:44451$1557
69926     assign { } { }
69927     assign $1\wb_icache_en[0:0] 1'1
69928     sync always
69929     sync init
69930       update \wb_icache_en $1\wb_icache_en[0:0]
69931   end
69932   attribute \src "libresoc.v:44710.3-44711.41"
69933   process $proc$libresoc.v:44710$1329
69934     assign { } { }
69935     assign $0\wb_icache_en[0:0] \wb_icache_en$next
69936     sync posedge \clk
69937       update \wb_icache_en $0\wb_icache_en[0:0]
69938   end
69939   attribute \src "libresoc.v:44712.3-44713.41"
69940   process $proc$libresoc.v:44712$1330
69941     assign { } { }
69942     assign $0\wb_dcache_en[0:0] \wb_dcache_en$next
69943     sync posedge \clk
69944       update \wb_dcache_en $0\wb_dcache_en[0:0]
69945   end
69946   attribute \src "libresoc.v:44714.3-44715.45"
69947   process $proc$libresoc.v:44714$1331
69948     assign { } { }
69949     assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next
69950     sync posedge \clk
69951       update \dmi0_datasr__i $0\dmi0_datasr__i[63:0]
69952   end
69953   attribute \src "libresoc.v:44716.3-44717.35"
69954   process $proc$libresoc.v:44716$1332
69955     assign { } { }
69956     assign $0\dmi0__din[63:0] \dmi0__din$next
69957     sync posedge \clk
69958       update \dmi0__din $0\dmi0__din[63:0]
69959   end
69960   attribute \src "libresoc.v:44718.3-44719.45"
69961   process $proc$libresoc.v:44718$1333
69962     assign { } { }
69963     assign $0\fsm_state$503[2:0]$1334 \fsm_state$503$next
69964     sync posedge \clk
69965       update \fsm_state$503 $0\fsm_state$503[2:0]$1334
69966   end
69967   attribute \src "libresoc.v:44720.3-44721.41"
69968   process $proc$libresoc.v:44720$1335
69969     assign { } { }
69970     assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next
69971     sync posedge \clk
69972       update \dmi0__addr_i $0\dmi0__addr_i[3:0]
69973   end
69974   attribute \src "libresoc.v:44722.3-44723.51"
69975   process $proc$libresoc.v:44722$1336
69976     assign { } { }
69977     assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next
69978     sync posedge \clk
69979       update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0]
69980   end
69981   attribute \src "libresoc.v:44724.3-44725.45"
69982   process $proc$libresoc.v:44724$1337
69983     assign { } { }
69984     assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next
69985     sync posedge \clk
69986       update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0]
69987   end
69988   attribute \src "libresoc.v:44726.3-44727.35"
69989   process $proc$libresoc.v:44726$1338
69990     assign { } { }
69991     assign $0\fsm_state[2:0] \fsm_state$next
69992     sync posedge \clk
69993       update \fsm_state $0\fsm_state[2:0]
69994   end
69995   attribute \src "libresoc.v:44728.3-44729.41"
69996   process $proc$libresoc.v:44728$1339
69997     assign { } { }
69998     assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next
69999     sync posedge \clk
70000       update \jtag_wb__adr $0\jtag_wb__adr[28:0]
70001   end
70002   attribute \src "libresoc.v:44730.3-44731.31"
70003   process $proc$libresoc.v:44730$1340
70004     assign { } { }
70005     assign $0\sr5_reg[1:0] \sr5_reg$next
70006     sync posedge \posjtag_clk
70007       update \sr5_reg $0\sr5_reg[1:0]
70008   end
70009   attribute \src "libresoc.v:44732.3-44733.31"
70010   process $proc$libresoc.v:44732$1341
70011     assign { } { }
70012     assign $0\sr5__oe[0:0] \sr5__oe$next
70013     sync posedge \clk
70014       update \sr5__oe $0\sr5__oe[0:0]
70015   end
70016   attribute \src "libresoc.v:44734.3-44735.57"
70017   process $proc$libresoc.v:44734$1342
70018     assign { } { }
70019     assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next
70020     sync posedge \clk
70021       update \sr5_update_core_prev $0\sr5_update_core_prev[0:0]
70022   end
70023   attribute \src "libresoc.v:44736.3-44737.47"
70024   process $proc$libresoc.v:44736$1343
70025     assign { } { }
70026     assign $0\sr5_update_core[0:0] \sr5_update_core$next
70027     sync posedge \clk
70028       update \sr5_update_core $0\sr5_update_core[0:0]
70029   end
70030   attribute \src "libresoc.v:44738.3-44739.47"
70031   process $proc$libresoc.v:44738$1344
70032     assign { } { }
70033     assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next
70034     sync posedge \posjtag_clk
70035       update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0]
70036   end
70037   attribute \src "libresoc.v:44740.3-44741.47"
70038   process $proc$libresoc.v:44740$1345
70039     assign { } { }
70040     assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next
70041     sync posedge \clk
70042       update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0]
70043   end
70044   attribute \src "libresoc.v:44742.3-44743.73"
70045   process $proc$libresoc.v:44742$1346
70046     assign { } { }
70047     assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next
70048     sync posedge \clk
70049       update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0]
70050   end
70051   attribute \src "libresoc.v:44744.3-44745.63"
70052   process $proc$libresoc.v:44744$1347
70053     assign { } { }
70054     assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next
70055     sync posedge \clk
70056       update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0]
70057   end
70058   attribute \src "libresoc.v:44746.3-44747.47"
70059   process $proc$libresoc.v:44746$1348
70060     assign { } { }
70061     assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next
70062     sync posedge \posjtag_clk
70063       update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0]
70064   end
70065   attribute \src "libresoc.v:44748.3-44749.47"
70066   process $proc$libresoc.v:44748$1349
70067     assign { } { }
70068     assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next
70069     sync posedge \clk
70070       update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0]
70071   end
70072   attribute \src "libresoc.v:44750.3-44751.73"
70073   process $proc$libresoc.v:44750$1350
70074     assign { } { }
70075     assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next
70076     sync posedge \clk
70077       update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0]
70078   end
70079   attribute \src "libresoc.v:44752.3-44753.63"
70080   process $proc$libresoc.v:44752$1351
70081     assign { } { }
70082     assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next
70083     sync posedge \clk
70084       update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0]
70085   end
70086   attribute \src "libresoc.v:44754.3-44755.53"
70087   process $proc$libresoc.v:44754$1352
70088     assign { } { }
70089     assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next
70090     sync posedge \posjtag_clk
70091       update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0]
70092   end
70093   attribute \src "libresoc.v:44756.3-44757.53"
70094   process $proc$libresoc.v:44756$1353
70095     assign { } { }
70096     assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next
70097     sync posedge \clk
70098       update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0]
70099   end
70100   attribute \src "libresoc.v:44758.3-44759.79"
70101   process $proc$libresoc.v:44758$1354
70102     assign { } { }
70103     assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next
70104     sync posedge \clk
70105       update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0]
70106   end
70107   attribute \src "libresoc.v:44760.3-44761.69"
70108   process $proc$libresoc.v:44760$1355
70109     assign { } { }
70110     assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next
70111     sync posedge \clk
70112       update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0]
70113   end
70114   attribute \src "libresoc.v:44762.3-44763.53"
70115   process $proc$libresoc.v:44762$1356
70116     assign { } { }
70117     assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next
70118     sync posedge \posjtag_clk
70119       update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0]
70120   end
70121   attribute \src "libresoc.v:44764.3-44765.53"
70122   process $proc$libresoc.v:44764$1357
70123     assign { } { }
70124     assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next
70125     sync posedge \clk
70126       update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0]
70127   end
70128   attribute \src "libresoc.v:44766.3-44767.79"
70129   process $proc$libresoc.v:44766$1358
70130     assign { } { }
70131     assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next
70132     sync posedge \clk
70133       update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0]
70134   end
70135   attribute \src "libresoc.v:44768.3-44769.69"
70136   process $proc$libresoc.v:44768$1359
70137     assign { } { }
70138     assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next
70139     sync posedge \clk
70140       update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0]
70141   end
70142   attribute \src "libresoc.v:44770.3-44771.31"
70143   process $proc$libresoc.v:44770$1360
70144     assign { } { }
70145     assign $0\sr0_reg[2:0] \sr0_reg$next
70146     sync posedge \posjtag_clk
70147       update \sr0_reg $0\sr0_reg[2:0]
70148   end
70149   attribute \src "libresoc.v:44772.3-44773.31"
70150   process $proc$libresoc.v:44772$1361
70151     assign { } { }
70152     assign $0\sr0__oe[0:0] \sr0__oe$next
70153     sync posedge \clk
70154       update \sr0__oe $0\sr0__oe[0:0]
70155   end
70156   attribute \src "libresoc.v:44774.3-44775.57"
70157   process $proc$libresoc.v:44774$1362
70158     assign { } { }
70159     assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next
70160     sync posedge \clk
70161       update \sr0_update_core_prev $0\sr0_update_core_prev[0:0]
70162   end
70163   attribute \src "libresoc.v:44776.3-44777.47"
70164   process $proc$libresoc.v:44776$1363
70165     assign { } { }
70166     assign $0\sr0_update_core[0:0] \sr0_update_core$next
70167     sync posedge \clk
70168       update \sr0_update_core $0\sr0_update_core[0:0]
70169   end
70170   attribute \src "libresoc.v:44778.3-44779.27"
70171   process $proc$libresoc.v:44778$1364
70172     assign { } { }
70173     assign $0\io_bd[153:0] \io_bd$next
70174     sync negedge \negjtag_clk
70175       update \io_bd $0\io_bd[153:0]
70176   end
70177   attribute \src "libresoc.v:44780.3-44781.27"
70178   process $proc$libresoc.v:44780$1365
70179     assign { } { }
70180     assign $0\io_sr[153:0] \io_sr$next
70181     sync posedge \posjtag_clk
70182       update \io_sr $0\io_sr[153:0]
70183   end
70184   attribute \src "libresoc.v:44817.3-44832.6"
70185   process $proc$libresoc.v:44817$1366
70186     assign { } { }
70187     assign { } { }
70188     assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0]
70189     attribute \src "libresoc.v:44818.5-44818.29"
70190     switch \initial
70191       attribute \src "libresoc.v:44818.9-44818.17"
70192       case 1'1
70193       case
70194     end
70195     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415"
70196     switch { \$369 \_idblock_select_id \_fsm_isir }
70197       attribute \src "libresoc.v:0.0-0.0"
70198       case 3'--1
70199         assign { } { }
70200         assign $1\TAP_tdo[0:0] \_irblock_tdo
70201       attribute \src "libresoc.v:0.0-0.0"
70202       case 3'-1-
70203         assign { } { }
70204         assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo
70205       attribute \src "libresoc.v:0.0-0.0"
70206       case 3'1--
70207         assign { } { }
70208         assign $1\TAP_tdo[0:0] \io_sr [153]
70209       case
70210         assign $1\TAP_tdo[0:0] 1'0
70211     end
70212     sync always
70213       update \TAP_tdo $0\TAP_tdo[0:0]
70214   end
70215   attribute \src "libresoc.v:44833.3-44841.6"
70216   process $proc$libresoc.v:44833$1367
70217     assign { } { }
70218     assign { } { }
70219     assign $0\sr0_update_core$next[0:0]$1368 $1\sr0_update_core$next[0:0]$1369
70220     attribute \src "libresoc.v:44834.5-44834.29"
70221     switch \initial
70222       attribute \src "libresoc.v:44834.9-44834.17"
70223       case 1'1
70224       case
70225     end
70226     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70227     switch \rst
70228       attribute \src "libresoc.v:0.0-0.0"
70229       case 1'1
70230         assign { } { }
70231         assign $1\sr0_update_core$next[0:0]$1369 1'0
70232       case
70233         assign $1\sr0_update_core$next[0:0]$1369 \sr0_update
70234     end
70235     sync always
70236       update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1368
70237   end
70238   attribute \src "libresoc.v:44842.3-44850.6"
70239   process $proc$libresoc.v:44842$1370
70240     assign { } { }
70241     assign { } { }
70242     assign $0\sr0_update_core_prev$next[0:0]$1371 $1\sr0_update_core_prev$next[0:0]$1372
70243     attribute \src "libresoc.v:44843.5-44843.29"
70244     switch \initial
70245       attribute \src "libresoc.v:44843.9-44843.17"
70246       case 1'1
70247       case
70248     end
70249     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70250     switch \rst
70251       attribute \src "libresoc.v:0.0-0.0"
70252       case 1'1
70253         assign { } { }
70254         assign $1\sr0_update_core_prev$next[0:0]$1372 1'0
70255       case
70256         assign $1\sr0_update_core_prev$next[0:0]$1372 \sr0_update_core
70257     end
70258     sync always
70259       update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1371
70260   end
70261   attribute \src "libresoc.v:44851.3-44867.6"
70262   process $proc$libresoc.v:44851$1373
70263     assign { } { }
70264     assign { } { }
70265     assign $0\sr0__oe$next[0:0]$1374 $2\sr0__oe$next[0:0]$1376
70266     attribute \src "libresoc.v:44852.5-44852.29"
70267     switch \initial
70268       attribute \src "libresoc.v:44852.9-44852.17"
70269       case 1'1
70270       case
70271     end
70272     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
70273     switch \$387
70274       attribute \src "libresoc.v:0.0-0.0"
70275       case 1'1
70276         assign { } { }
70277         assign $1\sr0__oe$next[0:0]$1375 \sr0_isir
70278       attribute \src "libresoc.v:0.0-0.0"
70279       case
70280         assign { } { }
70281         assign $1\sr0__oe$next[0:0]$1375 1'0
70282     end
70283     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70284     switch \rst
70285       attribute \src "libresoc.v:0.0-0.0"
70286       case 1'1
70287         assign { } { }
70288         assign $2\sr0__oe$next[0:0]$1376 1'0
70289       case
70290         assign $2\sr0__oe$next[0:0]$1376 $1\sr0__oe$next[0:0]$1375
70291     end
70292     sync always
70293       update \sr0__oe$next $0\sr0__oe$next[0:0]$1374
70294   end
70295   attribute \src "libresoc.v:44868.3-44888.6"
70296   process $proc$libresoc.v:44868$1377
70297     assign { } { }
70298     assign { } { }
70299     assign { } { }
70300     assign { } { }
70301     assign $0\sr0_reg$next[2:0]$1378 $3\sr0_reg$next[2:0]$1381
70302     attribute \src "libresoc.v:44869.5-44869.29"
70303     switch \initial
70304       attribute \src "libresoc.v:44869.9-44869.17"
70305       case 1'1
70306       case
70307     end
70308     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673"
70309     switch \sr0_shift
70310       attribute \src "libresoc.v:0.0-0.0"
70311       case 1'1
70312         assign { } { }
70313         assign $1\sr0_reg$next[2:0]$1379 { \TAP_bus__tdi \sr0_reg [2:1] }
70314       case
70315         assign $1\sr0_reg$next[2:0]$1379 \sr0_reg
70316     end
70317     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
70318     switch \sr0_capture
70319       attribute \src "libresoc.v:0.0-0.0"
70320       case 1'1
70321         assign { } { }
70322         assign $2\sr0_reg$next[2:0]$1380 \sr0__i
70323       case
70324         assign $2\sr0_reg$next[2:0]$1380 $1\sr0_reg$next[2:0]$1379
70325     end
70326     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70327     switch \posjtag_rst
70328       attribute \src "libresoc.v:0.0-0.0"
70329       case 1'1
70330         assign { } { }
70331         assign $3\sr0_reg$next[2:0]$1381 3'000
70332       case
70333         assign $3\sr0_reg$next[2:0]$1381 $2\sr0_reg$next[2:0]$1380
70334     end
70335     sync always
70336       update \sr0_reg$next $0\sr0_reg$next[2:0]$1378
70337   end
70338   attribute \src "libresoc.v:44889.3-44897.6"
70339   process $proc$libresoc.v:44889$1382
70340     assign { } { }
70341     assign { } { }
70342     assign $0\jtag_wb_addrsr_update_core$next[0:0]$1383 $1\jtag_wb_addrsr_update_core$next[0:0]$1384
70343     attribute \src "libresoc.v:44890.5-44890.29"
70344     switch \initial
70345       attribute \src "libresoc.v:44890.9-44890.17"
70346       case 1'1
70347       case
70348     end
70349     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70350     switch \rst
70351       attribute \src "libresoc.v:0.0-0.0"
70352       case 1'1
70353         assign { } { }
70354         assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 1'0
70355       case
70356         assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 \jtag_wb_addrsr_update
70357     end
70358     sync always
70359       update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1383
70360   end
70361   attribute \src "libresoc.v:44898.3-44906.6"
70362   process $proc$libresoc.v:44898$1385
70363     assign { } { }
70364     assign { } { }
70365     assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387
70366     attribute \src "libresoc.v:44899.5-44899.29"
70367     switch \initial
70368       attribute \src "libresoc.v:44899.9-44899.17"
70369       case 1'1
70370       case
70371     end
70372     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70373     switch \rst
70374       attribute \src "libresoc.v:0.0-0.0"
70375       case 1'1
70376         assign { } { }
70377         assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 1'0
70378       case
70379         assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 \jtag_wb_addrsr_update_core
70380     end
70381     sync always
70382       update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386
70383   end
70384   attribute \src "libresoc.v:44907.3-44923.6"
70385   process $proc$libresoc.v:44907$1388
70386     assign { } { }
70387     assign { } { }
70388     assign $0\jtag_wb_addrsr__oe$next[0:0]$1389 $2\jtag_wb_addrsr__oe$next[0:0]$1391
70389     attribute \src "libresoc.v:44908.5-44908.29"
70390     switch \initial
70391       attribute \src "libresoc.v:44908.9-44908.17"
70392       case 1'1
70393       case
70394     end
70395     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
70396     switch \$405
70397       attribute \src "libresoc.v:0.0-0.0"
70398       case 1'1
70399         assign { } { }
70400         assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 \jtag_wb_addrsr_isir
70401       attribute \src "libresoc.v:0.0-0.0"
70402       case
70403         assign { } { }
70404         assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 1'0
70405     end
70406     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70407     switch \rst
70408       attribute \src "libresoc.v:0.0-0.0"
70409       case 1'1
70410         assign { } { }
70411         assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 1'0
70412       case
70413         assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 $1\jtag_wb_addrsr__oe$next[0:0]$1390
70414     end
70415     sync always
70416       update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1389
70417   end
70418   attribute \src "libresoc.v:44924.3-44944.6"
70419   process $proc$libresoc.v:44924$1392
70420     assign { } { }
70421     assign { } { }
70422     assign { } { }
70423     assign { } { }
70424     assign $0\jtag_wb_addrsr_reg$next[28:0]$1393 $3\jtag_wb_addrsr_reg$next[28:0]$1396
70425     attribute \src "libresoc.v:44925.5-44925.29"
70426     switch \initial
70427       attribute \src "libresoc.v:44925.9-44925.17"
70428       case 1'1
70429       case
70430     end
70431     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673"
70432     switch \jtag_wb_addrsr_shift
70433       attribute \src "libresoc.v:0.0-0.0"
70434       case 1'1
70435         assign { } { }
70436         assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] }
70437       case
70438         assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 \jtag_wb_addrsr_reg
70439     end
70440     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
70441     switch \jtag_wb_addrsr_capture
70442       attribute \src "libresoc.v:0.0-0.0"
70443       case 1'1
70444         assign { } { }
70445         assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 \jtag_wb_addrsr__i
70446       case
70447         assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 $1\jtag_wb_addrsr_reg$next[28:0]$1394
70448     end
70449     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70450     switch \posjtag_rst
70451       attribute \src "libresoc.v:0.0-0.0"
70452       case 1'1
70453         assign { } { }
70454         assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 29'00000000000000000000000000000
70455       case
70456         assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 $2\jtag_wb_addrsr_reg$next[28:0]$1395
70457     end
70458     sync always
70459       update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1393
70460   end
70461   attribute \src "libresoc.v:44945.3-44953.6"
70462   process $proc$libresoc.v:44945$1397
70463     assign { } { }
70464     assign { } { }
70465     assign $0\jtag_wb_datasr_update_core$next[0:0]$1398 $1\jtag_wb_datasr_update_core$next[0:0]$1399
70466     attribute \src "libresoc.v:44946.5-44946.29"
70467     switch \initial
70468       attribute \src "libresoc.v:44946.9-44946.17"
70469       case 1'1
70470       case
70471     end
70472     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70473     switch \rst
70474       attribute \src "libresoc.v:0.0-0.0"
70475       case 1'1
70476         assign { } { }
70477         assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 1'0
70478       case
70479         assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 \jtag_wb_datasr_update
70480     end
70481     sync always
70482       update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1398
70483   end
70484   attribute \src "libresoc.v:44954.3-44962.6"
70485   process $proc$libresoc.v:44954$1400
70486     assign { } { }
70487     assign { } { }
70488     assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402
70489     attribute \src "libresoc.v:44955.5-44955.29"
70490     switch \initial
70491       attribute \src "libresoc.v:44955.9-44955.17"
70492       case 1'1
70493       case
70494     end
70495     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70496     switch \rst
70497       attribute \src "libresoc.v:0.0-0.0"
70498       case 1'1
70499         assign { } { }
70500         assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 1'0
70501       case
70502         assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 \jtag_wb_datasr_update_core
70503     end
70504     sync always
70505       update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401
70506   end
70507   attribute \src "libresoc.v:44963.3-44979.6"
70508   process $proc$libresoc.v:44963$1403
70509     assign { } { }
70510     assign { } { }
70511     assign $0\jtag_wb_datasr__oe$next[1:0]$1404 $2\jtag_wb_datasr__oe$next[1:0]$1406
70512     attribute \src "libresoc.v:44964.5-44964.29"
70513     switch \initial
70514       attribute \src "libresoc.v:44964.9-44964.17"
70515       case 1'1
70516       case
70517     end
70518     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
70519     switch \$425
70520       attribute \src "libresoc.v:0.0-0.0"
70521       case 1'1
70522         assign { } { }
70523         assign $1\jtag_wb_datasr__oe$next[1:0]$1405 \jtag_wb_datasr_isir
70524       attribute \src "libresoc.v:0.0-0.0"
70525       case
70526         assign { } { }
70527         assign $1\jtag_wb_datasr__oe$next[1:0]$1405 2'00
70528     end
70529     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70530     switch \rst
70531       attribute \src "libresoc.v:0.0-0.0"
70532       case 1'1
70533         assign { } { }
70534         assign $2\jtag_wb_datasr__oe$next[1:0]$1406 2'00
70535       case
70536         assign $2\jtag_wb_datasr__oe$next[1:0]$1406 $1\jtag_wb_datasr__oe$next[1:0]$1405
70537     end
70538     sync always
70539       update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1404
70540   end
70541   attribute \src "libresoc.v:44980.3-45000.6"
70542   process $proc$libresoc.v:44980$1407
70543     assign { } { }
70544     assign { } { }
70545     assign { } { }
70546     assign { } { }
70547     assign $0\jtag_wb_datasr_reg$next[63:0]$1408 $3\jtag_wb_datasr_reg$next[63:0]$1411
70548     attribute \src "libresoc.v:44981.5-44981.29"
70549     switch \initial
70550       attribute \src "libresoc.v:44981.9-44981.17"
70551       case 1'1
70552       case
70553     end
70554     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673"
70555     switch \jtag_wb_datasr_shift
70556       attribute \src "libresoc.v:0.0-0.0"
70557       case 1'1
70558         assign { } { }
70559         assign $1\jtag_wb_datasr_reg$next[63:0]$1409 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] }
70560       case
70561         assign $1\jtag_wb_datasr_reg$next[63:0]$1409 \jtag_wb_datasr_reg
70562     end
70563     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
70564     switch \jtag_wb_datasr_capture
70565       attribute \src "libresoc.v:0.0-0.0"
70566       case 1'1
70567         assign { } { }
70568         assign $2\jtag_wb_datasr_reg$next[63:0]$1410 \jtag_wb_datasr__i
70569       case
70570         assign $2\jtag_wb_datasr_reg$next[63:0]$1410 $1\jtag_wb_datasr_reg$next[63:0]$1409
70571     end
70572     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70573     switch \posjtag_rst
70574       attribute \src "libresoc.v:0.0-0.0"
70575       case 1'1
70576         assign { } { }
70577         assign $3\jtag_wb_datasr_reg$next[63:0]$1411 64'0000000000000000000000000000000000000000000000000000000000000000
70578       case
70579         assign $3\jtag_wb_datasr_reg$next[63:0]$1411 $2\jtag_wb_datasr_reg$next[63:0]$1410
70580     end
70581     sync always
70582       update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1408
70583   end
70584   attribute \src "libresoc.v:45001.3-45009.6"
70585   process $proc$libresoc.v:45001$1412
70586     assign { } { }
70587     assign { } { }
70588     assign $0\dmi0_addrsr_update_core$next[0:0]$1413 $1\dmi0_addrsr_update_core$next[0:0]$1414
70589     attribute \src "libresoc.v:45002.5-45002.29"
70590     switch \initial
70591       attribute \src "libresoc.v:45002.9-45002.17"
70592       case 1'1
70593       case
70594     end
70595     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70596     switch \rst
70597       attribute \src "libresoc.v:0.0-0.0"
70598       case 1'1
70599         assign { } { }
70600         assign $1\dmi0_addrsr_update_core$next[0:0]$1414 1'0
70601       case
70602         assign $1\dmi0_addrsr_update_core$next[0:0]$1414 \dmi0_addrsr_update
70603     end
70604     sync always
70605       update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1413
70606   end
70607   attribute \src "libresoc.v:45010.3-45018.6"
70608   process $proc$libresoc.v:45010$1415
70609     assign { } { }
70610     assign { } { }
70611     assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 $1\dmi0_addrsr_update_core_prev$next[0:0]$1417
70612     attribute \src "libresoc.v:45011.5-45011.29"
70613     switch \initial
70614       attribute \src "libresoc.v:45011.9-45011.17"
70615       case 1'1
70616       case
70617     end
70618     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70619     switch \rst
70620       attribute \src "libresoc.v:0.0-0.0"
70621       case 1'1
70622         assign { } { }
70623         assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 1'0
70624       case
70625         assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 \dmi0_addrsr_update_core
70626     end
70627     sync always
70628       update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1416
70629   end
70630   attribute \src "libresoc.v:45019.3-45035.6"
70631   process $proc$libresoc.v:45019$1418
70632     assign { } { }
70633     assign { } { }
70634     assign $0\dmi0_addrsr__oe$next[0:0]$1419 $2\dmi0_addrsr__oe$next[0:0]$1421
70635     attribute \src "libresoc.v:45020.5-45020.29"
70636     switch \initial
70637       attribute \src "libresoc.v:45020.9-45020.17"
70638       case 1'1
70639       case
70640     end
70641     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
70642     switch \$443
70643       attribute \src "libresoc.v:0.0-0.0"
70644       case 1'1
70645         assign { } { }
70646         assign $1\dmi0_addrsr__oe$next[0:0]$1420 \dmi0_addrsr_isir
70647       attribute \src "libresoc.v:0.0-0.0"
70648       case
70649         assign { } { }
70650         assign $1\dmi0_addrsr__oe$next[0:0]$1420 1'0
70651     end
70652     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70653     switch \rst
70654       attribute \src "libresoc.v:0.0-0.0"
70655       case 1'1
70656         assign { } { }
70657         assign $2\dmi0_addrsr__oe$next[0:0]$1421 1'0
70658       case
70659         assign $2\dmi0_addrsr__oe$next[0:0]$1421 $1\dmi0_addrsr__oe$next[0:0]$1420
70660     end
70661     sync always
70662       update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1419
70663   end
70664   attribute \src "libresoc.v:45036.3-45056.6"
70665   process $proc$libresoc.v:45036$1422
70666     assign { } { }
70667     assign { } { }
70668     assign { } { }
70669     assign { } { }
70670     assign $0\dmi0_addrsr_reg$next[7:0]$1423 $3\dmi0_addrsr_reg$next[7:0]$1426
70671     attribute \src "libresoc.v:45037.5-45037.29"
70672     switch \initial
70673       attribute \src "libresoc.v:45037.9-45037.17"
70674       case 1'1
70675       case
70676     end
70677     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673"
70678     switch \dmi0_addrsr_shift
70679       attribute \src "libresoc.v:0.0-0.0"
70680       case 1'1
70681         assign { } { }
70682         assign $1\dmi0_addrsr_reg$next[7:0]$1424 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] }
70683       case
70684         assign $1\dmi0_addrsr_reg$next[7:0]$1424 \dmi0_addrsr_reg
70685     end
70686     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
70687     switch \dmi0_addrsr_capture
70688       attribute \src "libresoc.v:0.0-0.0"
70689       case 1'1
70690         assign { } { }
70691         assign $2\dmi0_addrsr_reg$next[7:0]$1425 \dmi0_addrsr__i
70692       case
70693         assign $2\dmi0_addrsr_reg$next[7:0]$1425 $1\dmi0_addrsr_reg$next[7:0]$1424
70694     end
70695     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70696     switch \posjtag_rst
70697       attribute \src "libresoc.v:0.0-0.0"
70698       case 1'1
70699         assign { } { }
70700         assign $3\dmi0_addrsr_reg$next[7:0]$1426 8'00000000
70701       case
70702         assign $3\dmi0_addrsr_reg$next[7:0]$1426 $2\dmi0_addrsr_reg$next[7:0]$1425
70703     end
70704     sync always
70705       update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1423
70706   end
70707   attribute \src "libresoc.v:45057.3-45065.6"
70708   process $proc$libresoc.v:45057$1427
70709     assign { } { }
70710     assign { } { }
70711     assign $0\dmi0_datasr_update_core$next[0:0]$1428 $1\dmi0_datasr_update_core$next[0:0]$1429
70712     attribute \src "libresoc.v:45058.5-45058.29"
70713     switch \initial
70714       attribute \src "libresoc.v:45058.9-45058.17"
70715       case 1'1
70716       case
70717     end
70718     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70719     switch \rst
70720       attribute \src "libresoc.v:0.0-0.0"
70721       case 1'1
70722         assign { } { }
70723         assign $1\dmi0_datasr_update_core$next[0:0]$1429 1'0
70724       case
70725         assign $1\dmi0_datasr_update_core$next[0:0]$1429 \dmi0_datasr_update
70726     end
70727     sync always
70728       update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1428
70729   end
70730   attribute \src "libresoc.v:45066.3-45074.6"
70731   process $proc$libresoc.v:45066$1430
70732     assign { } { }
70733     assign { } { }
70734     assign $0\dmi0_datasr_update_core_prev$next[0:0]$1431 $1\dmi0_datasr_update_core_prev$next[0:0]$1432
70735     attribute \src "libresoc.v:45067.5-45067.29"
70736     switch \initial
70737       attribute \src "libresoc.v:45067.9-45067.17"
70738       case 1'1
70739       case
70740     end
70741     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70742     switch \rst
70743       attribute \src "libresoc.v:0.0-0.0"
70744       case 1'1
70745         assign { } { }
70746         assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 1'0
70747       case
70748         assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 \dmi0_datasr_update_core
70749     end
70750     sync always
70751       update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1431
70752   end
70753   attribute \src "libresoc.v:45075.3-45091.6"
70754   process $proc$libresoc.v:45075$1433
70755     assign { } { }
70756     assign { } { }
70757     assign $0\dmi0_datasr__oe$next[1:0]$1434 $2\dmi0_datasr__oe$next[1:0]$1436
70758     attribute \src "libresoc.v:45076.5-45076.29"
70759     switch \initial
70760       attribute \src "libresoc.v:45076.9-45076.17"
70761       case 1'1
70762       case
70763     end
70764     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
70765     switch \$463
70766       attribute \src "libresoc.v:0.0-0.0"
70767       case 1'1
70768         assign { } { }
70769         assign $1\dmi0_datasr__oe$next[1:0]$1435 \dmi0_datasr_isir
70770       attribute \src "libresoc.v:0.0-0.0"
70771       case
70772         assign { } { }
70773         assign $1\dmi0_datasr__oe$next[1:0]$1435 2'00
70774     end
70775     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70776     switch \rst
70777       attribute \src "libresoc.v:0.0-0.0"
70778       case 1'1
70779         assign { } { }
70780         assign $2\dmi0_datasr__oe$next[1:0]$1436 2'00
70781       case
70782         assign $2\dmi0_datasr__oe$next[1:0]$1436 $1\dmi0_datasr__oe$next[1:0]$1435
70783     end
70784     sync always
70785       update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1434
70786   end
70787   attribute \src "libresoc.v:45092.3-45112.6"
70788   process $proc$libresoc.v:45092$1437
70789     assign { } { }
70790     assign { } { }
70791     assign { } { }
70792     assign { } { }
70793     assign $0\dmi0_datasr_reg$next[63:0]$1438 $3\dmi0_datasr_reg$next[63:0]$1441
70794     attribute \src "libresoc.v:45093.5-45093.29"
70795     switch \initial
70796       attribute \src "libresoc.v:45093.9-45093.17"
70797       case 1'1
70798       case
70799     end
70800     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673"
70801     switch \dmi0_datasr_shift
70802       attribute \src "libresoc.v:0.0-0.0"
70803       case 1'1
70804         assign { } { }
70805         assign $1\dmi0_datasr_reg$next[63:0]$1439 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] }
70806       case
70807         assign $1\dmi0_datasr_reg$next[63:0]$1439 \dmi0_datasr_reg
70808     end
70809     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
70810     switch \dmi0_datasr_capture
70811       attribute \src "libresoc.v:0.0-0.0"
70812       case 1'1
70813         assign { } { }
70814         assign $2\dmi0_datasr_reg$next[63:0]$1440 \dmi0_datasr__i
70815       case
70816         assign $2\dmi0_datasr_reg$next[63:0]$1440 $1\dmi0_datasr_reg$next[63:0]$1439
70817     end
70818     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70819     switch \posjtag_rst
70820       attribute \src "libresoc.v:0.0-0.0"
70821       case 1'1
70822         assign { } { }
70823         assign $3\dmi0_datasr_reg$next[63:0]$1441 64'0000000000000000000000000000000000000000000000000000000000000000
70824       case
70825         assign $3\dmi0_datasr_reg$next[63:0]$1441 $2\dmi0_datasr_reg$next[63:0]$1440
70826     end
70827     sync always
70828       update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1438
70829   end
70830   attribute \src "libresoc.v:45113.3-45121.6"
70831   process $proc$libresoc.v:45113$1442
70832     assign { } { }
70833     assign { } { }
70834     assign $0\sr5_update_core$next[0:0]$1443 $1\sr5_update_core$next[0:0]$1444
70835     attribute \src "libresoc.v:45114.5-45114.29"
70836     switch \initial
70837       attribute \src "libresoc.v:45114.9-45114.17"
70838       case 1'1
70839       case
70840     end
70841     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70842     switch \rst
70843       attribute \src "libresoc.v:0.0-0.0"
70844       case 1'1
70845         assign { } { }
70846         assign $1\sr5_update_core$next[0:0]$1444 1'0
70847       case
70848         assign $1\sr5_update_core$next[0:0]$1444 \sr5_update
70849     end
70850     sync always
70851       update \sr5_update_core$next $0\sr5_update_core$next[0:0]$1443
70852   end
70853   attribute \src "libresoc.v:45122.3-45130.6"
70854   process $proc$libresoc.v:45122$1445
70855     assign { } { }
70856     assign { } { }
70857     assign $0\sr5_update_core_prev$next[0:0]$1446 $1\sr5_update_core_prev$next[0:0]$1447
70858     attribute \src "libresoc.v:45123.5-45123.29"
70859     switch \initial
70860       attribute \src "libresoc.v:45123.9-45123.17"
70861       case 1'1
70862       case
70863     end
70864     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70865     switch \rst
70866       attribute \src "libresoc.v:0.0-0.0"
70867       case 1'1
70868         assign { } { }
70869         assign $1\sr5_update_core_prev$next[0:0]$1447 1'0
70870       case
70871         assign $1\sr5_update_core_prev$next[0:0]$1447 \sr5_update_core
70872     end
70873     sync always
70874       update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$1446
70875   end
70876   attribute \src "libresoc.v:45131.3-45147.6"
70877   process $proc$libresoc.v:45131$1448
70878     assign { } { }
70879     assign { } { }
70880     assign $0\sr5__oe$next[0:0]$1449 $2\sr5__oe$next[0:0]$1451
70881     attribute \src "libresoc.v:45132.5-45132.29"
70882     switch \initial
70883       attribute \src "libresoc.v:45132.9-45132.17"
70884       case 1'1
70885       case
70886     end
70887     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667"
70888     switch \$481
70889       attribute \src "libresoc.v:0.0-0.0"
70890       case 1'1
70891         assign { } { }
70892         assign $1\sr5__oe$next[0:0]$1450 \sr5_isir
70893       attribute \src "libresoc.v:0.0-0.0"
70894       case
70895         assign { } { }
70896         assign $1\sr5__oe$next[0:0]$1450 1'0
70897     end
70898     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70899     switch \rst
70900       attribute \src "libresoc.v:0.0-0.0"
70901       case 1'1
70902         assign { } { }
70903         assign $2\sr5__oe$next[0:0]$1451 1'0
70904       case
70905         assign $2\sr5__oe$next[0:0]$1451 $1\sr5__oe$next[0:0]$1450
70906     end
70907     sync always
70908       update \sr5__oe$next $0\sr5__oe$next[0:0]$1449
70909   end
70910   attribute \src "libresoc.v:45148.3-45168.6"
70911   process $proc$libresoc.v:45148$1452
70912     assign { } { }
70913     assign { } { }
70914     assign { } { }
70915     assign { } { }
70916     assign $0\sr5_reg$next[1:0]$1453 $3\sr5_reg$next[1:0]$1456
70917     attribute \src "libresoc.v:45149.5-45149.29"
70918     switch \initial
70919       attribute \src "libresoc.v:45149.9-45149.17"
70920       case 1'1
70921       case
70922     end
70923     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673"
70924     switch \sr5_shift
70925       attribute \src "libresoc.v:0.0-0.0"
70926       case 1'1
70927         assign { } { }
70928         assign $1\sr5_reg$next[1:0]$1454 { \TAP_bus__tdi \sr5_reg [1] }
70929       case
70930         assign $1\sr5_reg$next[1:0]$1454 \sr5_reg
70931     end
70932     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675"
70933     switch \sr5_capture
70934       attribute \src "libresoc.v:0.0-0.0"
70935       case 1'1
70936         assign { } { }
70937         assign $2\sr5_reg$next[1:0]$1455 \sr5__i
70938       case
70939         assign $2\sr5_reg$next[1:0]$1455 $1\sr5_reg$next[1:0]$1454
70940     end
70941     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
70942     switch \posjtag_rst
70943       attribute \src "libresoc.v:0.0-0.0"
70944       case 1'1
70945         assign { } { }
70946         assign $3\sr5_reg$next[1:0]$1456 2'00
70947       case
70948         assign $3\sr5_reg$next[1:0]$1456 $2\sr5_reg$next[1:0]$1455
70949     end
70950     sync always
70951       update \sr5_reg$next $0\sr5_reg$next[1:0]$1453
70952   end
70953   attribute \src "libresoc.v:45169.3-45195.6"
70954   process $proc$libresoc.v:45169$1457
70955     assign { } { }
70956     assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0]
70957     attribute \src "libresoc.v:45170.5-45170.29"
70958     switch \initial
70959       attribute \src "libresoc.v:45170.9-45170.17"
70960       case 1'1
70961       case
70962     end
70963     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685"
70964     switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift }
70965       attribute \src "libresoc.v:0.0-0.0"
70966       case 6'-----1
70967         assign { } { }
70968         assign $1\TAP_bus__tdo[0:0] \sr0_reg [0]
70969       attribute \src "libresoc.v:0.0-0.0"
70970       case 6'----1-
70971         assign { } { }
70972         assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0]
70973       attribute \src "libresoc.v:0.0-0.0"
70974       case 6'---1--
70975         assign { } { }
70976         assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0]
70977       attribute \src "libresoc.v:0.0-0.0"
70978       case 6'--1---
70979         assign { } { }
70980         assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0]
70981       attribute \src "libresoc.v:0.0-0.0"
70982       case 6'-1----
70983         assign { } { }
70984         assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0]
70985       attribute \src "libresoc.v:0.0-0.0"
70986       case 6'1-----
70987         assign { } { }
70988         assign $1\TAP_bus__tdo[0:0] \sr5_reg [0]
70989       attribute \src "libresoc.v:0.0-0.0"
70990       case
70991         assign { } { }
70992         assign $1\TAP_bus__tdo[0:0] \TAP_tdo
70993     end
70994     sync always
70995       update \TAP_bus__tdo $0\TAP_bus__tdo[0:0]
70996   end
70997   attribute \src "libresoc.v:45196.3-45228.6"
70998   process $proc$libresoc.v:45196$1458
70999     assign { } { }
71000     assign { } { }
71001     assign { } { }
71002     assign $0\jtag_wb__adr$next[28:0]$1459 $4\jtag_wb__adr$next[28:0]$1463
71003     attribute \src "libresoc.v:45197.5-45197.29"
71004     switch \initial
71005       attribute \src "libresoc.v:45197.9-45197.17"
71006       case 1'1
71007       case
71008     end
71009     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
71010     switch \fsm_state
71011       attribute \src "libresoc.v:0.0-0.0"
71012       case 3'000
71013         assign { } { }
71014         assign $1\jtag_wb__adr$next[28:0]$1460 $2\jtag_wb__adr$next[28:0]$1461
71015         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
71016         switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
71017           attribute \src "libresoc.v:0.0-0.0"
71018           case 3'--1
71019             assign { } { }
71020             assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb_addrsr__o
71021           attribute \src "libresoc.v:0.0-0.0"
71022           case 3'-1-
71023             assign { } { }
71024             assign $2\jtag_wb__adr$next[28:0]$1461 \$495 [28:0]
71025           case
71026             assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb__adr
71027         end
71028       attribute \src "libresoc.v:0.0-0.0"
71029       case 3'100
71030         assign { } { }
71031         assign $1\jtag_wb__adr$next[28:0]$1460 $3\jtag_wb__adr$next[28:0]$1462
71032         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785"
71033         switch \jtag_wb__ack
71034           attribute \src "libresoc.v:0.0-0.0"
71035           case 1'1
71036             assign { } { }
71037             assign $3\jtag_wb__adr$next[28:0]$1462 \$498 [28:0]
71038           case
71039             assign $3\jtag_wb__adr$next[28:0]$1462 \jtag_wb__adr
71040         end
71041       case
71042         assign $1\jtag_wb__adr$next[28:0]$1460 \jtag_wb__adr
71043     end
71044     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71045     switch \rst
71046       attribute \src "libresoc.v:0.0-0.0"
71047       case 1'1
71048         assign { } { }
71049         assign $4\jtag_wb__adr$next[28:0]$1463 29'00000000000000000000000000000
71050       case
71051         assign $4\jtag_wb__adr$next[28:0]$1463 $1\jtag_wb__adr$next[28:0]$1460
71052     end
71053     sync always
71054       update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1459
71055   end
71056   attribute \src "libresoc.v:45229.3-45281.6"
71057   process $proc$libresoc.v:45229$1464
71058     assign { } { }
71059     assign { } { }
71060     assign { } { }
71061     assign $0\fsm_state$next[2:0]$1465 $5\fsm_state$next[2:0]$1470
71062     attribute \src "libresoc.v:45230.5-45230.29"
71063     switch \initial
71064       attribute \src "libresoc.v:45230.9-45230.17"
71065       case 1'1
71066       case
71067     end
71068     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
71069     switch \fsm_state
71070       attribute \src "libresoc.v:0.0-0.0"
71071       case 3'000
71072         assign { } { }
71073         assign $1\fsm_state$next[2:0]$1466 $2\fsm_state$next[2:0]$1467
71074         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
71075         switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
71076           attribute \src "libresoc.v:0.0-0.0"
71077           case 3'--1
71078             assign { } { }
71079             assign $2\fsm_state$next[2:0]$1467 3'001
71080           attribute \src "libresoc.v:0.0-0.0"
71081           case 3'-1-
71082             assign { } { }
71083             assign $2\fsm_state$next[2:0]$1467 3'001
71084           attribute \src "libresoc.v:0.0-0.0"
71085           case 3'1--
71086             assign { } { }
71087             assign $2\fsm_state$next[2:0]$1467 3'010
71088           case
71089             assign $2\fsm_state$next[2:0]$1467 \fsm_state
71090         end
71091       attribute \src "libresoc.v:0.0-0.0"
71092       case 3'001
71093         assign { } { }
71094         assign $1\fsm_state$next[2:0]$1466 3'011
71095       attribute \src "libresoc.v:0.0-0.0"
71096       case 3'011
71097         assign { } { }
71098         assign $1\fsm_state$next[2:0]$1466 $3\fsm_state$next[2:0]$1468
71099         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773"
71100         switch \jtag_wb__ack
71101           attribute \src "libresoc.v:0.0-0.0"
71102           case 1'1
71103             assign { } { }
71104             assign $3\fsm_state$next[2:0]$1468 3'000
71105           case
71106             assign $3\fsm_state$next[2:0]$1468 \fsm_state
71107         end
71108       attribute \src "libresoc.v:0.0-0.0"
71109       case 3'010
71110         assign { } { }
71111         assign $1\fsm_state$next[2:0]$1466 3'100
71112       attribute \src "libresoc.v:0.0-0.0"
71113       case 3'100
71114         assign { } { }
71115         assign $1\fsm_state$next[2:0]$1466 $4\fsm_state$next[2:0]$1469
71116         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785"
71117         switch \jtag_wb__ack
71118           attribute \src "libresoc.v:0.0-0.0"
71119           case 1'1
71120             assign { } { }
71121             assign $4\fsm_state$next[2:0]$1469 3'001
71122           case
71123             assign $4\fsm_state$next[2:0]$1469 \fsm_state
71124         end
71125       case
71126         assign $1\fsm_state$next[2:0]$1466 \fsm_state
71127     end
71128     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71129     switch \rst
71130       attribute \src "libresoc.v:0.0-0.0"
71131       case 1'1
71132         assign { } { }
71133         assign $5\fsm_state$next[2:0]$1470 3'000
71134       case
71135         assign $5\fsm_state$next[2:0]$1470 $1\fsm_state$next[2:0]$1466
71136     end
71137     sync always
71138       update \fsm_state$next $0\fsm_state$next[2:0]$1465
71139   end
71140   attribute \src "libresoc.v:45282.3-45308.6"
71141   process $proc$libresoc.v:45282$1471
71142     assign { } { }
71143     assign { } { }
71144     assign { } { }
71145     assign $0\jtag_wb__dat_w$next[63:0]$1472 $3\jtag_wb__dat_w$next[63:0]$1475
71146     attribute \src "libresoc.v:45283.5-45283.29"
71147     switch \initial
71148       attribute \src "libresoc.v:45283.9-45283.17"
71149       case 1'1
71150       case
71151     end
71152     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
71153     switch \fsm_state
71154       attribute \src "libresoc.v:0.0-0.0"
71155       case 3'000
71156         assign { } { }
71157         assign $1\jtag_wb__dat_w$next[63:0]$1473 $2\jtag_wb__dat_w$next[63:0]$1474
71158         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756"
71159         switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe }
71160           attribute \src "libresoc.v:0.0-0.0"
71161           case 3'--1
71162             assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w
71163           attribute \src "libresoc.v:0.0-0.0"
71164           case 3'-1-
71165             assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w
71166           attribute \src "libresoc.v:0.0-0.0"
71167           case 3'1--
71168             assign { } { }
71169             assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb_datasr__o
71170           case
71171             assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w
71172         end
71173       case
71174         assign $1\jtag_wb__dat_w$next[63:0]$1473 \jtag_wb__dat_w
71175     end
71176     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71177     switch \rst
71178       attribute \src "libresoc.v:0.0-0.0"
71179       case 1'1
71180         assign { } { }
71181         assign $3\jtag_wb__dat_w$next[63:0]$1475 64'0000000000000000000000000000000000000000000000000000000000000000
71182       case
71183         assign $3\jtag_wb__dat_w$next[63:0]$1475 $1\jtag_wb__dat_w$next[63:0]$1473
71184     end
71185     sync always
71186       update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1472
71187   end
71188   attribute \src "libresoc.v:45309.3-45329.6"
71189   process $proc$libresoc.v:45309$1476
71190     assign { } { }
71191     assign { } { }
71192     assign { } { }
71193     assign $0\jtag_wb_datasr__i$next[63:0]$1477 $3\jtag_wb_datasr__i$next[63:0]$1480
71194     attribute \src "libresoc.v:45310.5-45310.29"
71195     switch \initial
71196       attribute \src "libresoc.v:45310.9-45310.17"
71197       case 1'1
71198       case
71199     end
71200     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754"
71201     switch \fsm_state
71202       attribute \src "libresoc.v:0.0-0.0"
71203       case 3'011
71204         assign { } { }
71205         assign $1\jtag_wb_datasr__i$next[63:0]$1478 $2\jtag_wb_datasr__i$next[63:0]$1479
71206         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773"
71207         switch \jtag_wb__ack
71208           attribute \src "libresoc.v:0.0-0.0"
71209           case 1'1
71210             assign { } { }
71211             assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb__dat_r
71212           case
71213             assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb_datasr__i
71214         end
71215       case
71216         assign $1\jtag_wb_datasr__i$next[63:0]$1478 \jtag_wb_datasr__i
71217     end
71218     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71219     switch \rst
71220       attribute \src "libresoc.v:0.0-0.0"
71221       case 1'1
71222         assign { } { }
71223         assign $3\jtag_wb_datasr__i$next[63:0]$1480 64'0000000000000000000000000000000000000000000000000000000000000000
71224       case
71225         assign $3\jtag_wb_datasr__i$next[63:0]$1480 $1\jtag_wb_datasr__i$next[63:0]$1478
71226     end
71227     sync always
71228       update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1477
71229   end
71230   attribute \src "libresoc.v:45330.3-45362.6"
71231   process $proc$libresoc.v:45330$1481
71232     assign { } { }
71233     assign { } { }
71234     assign { } { }
71235     assign $0\dmi0__addr_i$next[3:0]$1482 $4\dmi0__addr_i$next[3:0]$1486
71236     attribute \src "libresoc.v:45331.5-45331.29"
71237     switch \initial
71238       attribute \src "libresoc.v:45331.9-45331.17"
71239       case 1'1
71240       case
71241     end
71242     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
71243     switch \fsm_state$503
71244       attribute \src "libresoc.v:0.0-0.0"
71245       case 3'000
71246         assign { } { }
71247         assign $1\dmi0__addr_i$next[3:0]$1483 $2\dmi0__addr_i$next[3:0]$1484
71248         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
71249         switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
71250           attribute \src "libresoc.v:0.0-0.0"
71251           case 3'--1
71252             assign { } { }
71253             assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0_addrsr__o [3:0]
71254           attribute \src "libresoc.v:0.0-0.0"
71255           case 3'-1-
71256             assign { } { }
71257             assign $2\dmi0__addr_i$next[3:0]$1484 \$512 [3:0]
71258           case
71259             assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0__addr_i
71260         end
71261       attribute \src "libresoc.v:0.0-0.0"
71262       case 3'100
71263         assign { } { }
71264         assign $1\dmi0__addr_i$next[3:0]$1483 $3\dmi0__addr_i$next[3:0]$1485
71265         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517"
71266         switch \dmi0__ack_o
71267           attribute \src "libresoc.v:0.0-0.0"
71268           case 1'1
71269             assign { } { }
71270             assign $3\dmi0__addr_i$next[3:0]$1485 \$515 [3:0]
71271           case
71272             assign $3\dmi0__addr_i$next[3:0]$1485 \dmi0__addr_i
71273         end
71274       case
71275         assign $1\dmi0__addr_i$next[3:0]$1483 \dmi0__addr_i
71276     end
71277     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71278     switch \rst
71279       attribute \src "libresoc.v:0.0-0.0"
71280       case 1'1
71281         assign { } { }
71282         assign $4\dmi0__addr_i$next[3:0]$1486 4'0000
71283       case
71284         assign $4\dmi0__addr_i$next[3:0]$1486 $1\dmi0__addr_i$next[3:0]$1483
71285     end
71286     sync always
71287       update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$1482
71288   end
71289   attribute \src "libresoc.v:45363.3-45415.6"
71290   process $proc$libresoc.v:45363$1487
71291     assign { } { }
71292     assign { } { }
71293     assign { } { }
71294     assign $0\fsm_state$503$next[2:0]$1488 $5\fsm_state$503$next[2:0]$1493
71295     attribute \src "libresoc.v:45364.5-45364.29"
71296     switch \initial
71297       attribute \src "libresoc.v:45364.9-45364.17"
71298       case 1'1
71299       case
71300     end
71301     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
71302     switch \fsm_state$503
71303       attribute \src "libresoc.v:0.0-0.0"
71304       case 3'000
71305         assign { } { }
71306         assign $1\fsm_state$503$next[2:0]$1489 $2\fsm_state$503$next[2:0]$1490
71307         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
71308         switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
71309           attribute \src "libresoc.v:0.0-0.0"
71310           case 3'--1
71311             assign { } { }
71312             assign $2\fsm_state$503$next[2:0]$1490 3'001
71313           attribute \src "libresoc.v:0.0-0.0"
71314           case 3'-1-
71315             assign { } { }
71316             assign $2\fsm_state$503$next[2:0]$1490 3'001
71317           attribute \src "libresoc.v:0.0-0.0"
71318           case 3'1--
71319             assign { } { }
71320             assign $2\fsm_state$503$next[2:0]$1490 3'010
71321           case
71322             assign $2\fsm_state$503$next[2:0]$1490 \fsm_state$503
71323         end
71324       attribute \src "libresoc.v:0.0-0.0"
71325       case 3'001
71326         assign { } { }
71327         assign $1\fsm_state$503$next[2:0]$1489 3'011
71328       attribute \src "libresoc.v:0.0-0.0"
71329       case 3'011
71330         assign { } { }
71331         assign $1\fsm_state$503$next[2:0]$1489 $3\fsm_state$503$next[2:0]$1491
71332         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506"
71333         switch \dmi0__ack_o
71334           attribute \src "libresoc.v:0.0-0.0"
71335           case 1'1
71336             assign { } { }
71337             assign $3\fsm_state$503$next[2:0]$1491 3'000
71338           case
71339             assign $3\fsm_state$503$next[2:0]$1491 \fsm_state$503
71340         end
71341       attribute \src "libresoc.v:0.0-0.0"
71342       case 3'010
71343         assign { } { }
71344         assign $1\fsm_state$503$next[2:0]$1489 3'100
71345       attribute \src "libresoc.v:0.0-0.0"
71346       case 3'100
71347         assign { } { }
71348         assign $1\fsm_state$503$next[2:0]$1489 $4\fsm_state$503$next[2:0]$1492
71349         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517"
71350         switch \dmi0__ack_o
71351           attribute \src "libresoc.v:0.0-0.0"
71352           case 1'1
71353             assign { } { }
71354             assign $4\fsm_state$503$next[2:0]$1492 3'001
71355           case
71356             assign $4\fsm_state$503$next[2:0]$1492 \fsm_state$503
71357         end
71358       case
71359         assign $1\fsm_state$503$next[2:0]$1489 \fsm_state$503
71360     end
71361     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71362     switch \rst
71363       attribute \src "libresoc.v:0.0-0.0"
71364       case 1'1
71365         assign { } { }
71366         assign $5\fsm_state$503$next[2:0]$1493 3'000
71367       case
71368         assign $5\fsm_state$503$next[2:0]$1493 $1\fsm_state$503$next[2:0]$1489
71369     end
71370     sync always
71371       update \fsm_state$503$next $0\fsm_state$503$next[2:0]$1488
71372   end
71373   attribute \src "libresoc.v:45416.3-45442.6"
71374   process $proc$libresoc.v:45416$1494
71375     assign { } { }
71376     assign { } { }
71377     assign { } { }
71378     assign $0\dmi0__din$next[63:0]$1495 $3\dmi0__din$next[63:0]$1498
71379     attribute \src "libresoc.v:45417.5-45417.29"
71380     switch \initial
71381       attribute \src "libresoc.v:45417.9-45417.17"
71382       case 1'1
71383       case
71384     end
71385     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
71386     switch \fsm_state$503
71387       attribute \src "libresoc.v:0.0-0.0"
71388       case 3'000
71389         assign { } { }
71390         assign $1\dmi0__din$next[63:0]$1496 $2\dmi0__din$next[63:0]$1497
71391         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489"
71392         switch { \dmi0_datasr__oe \dmi0_addrsr__oe }
71393           attribute \src "libresoc.v:0.0-0.0"
71394           case 3'--1
71395             assign $2\dmi0__din$next[63:0]$1497 \dmi0__din
71396           attribute \src "libresoc.v:0.0-0.0"
71397           case 3'-1-
71398             assign $2\dmi0__din$next[63:0]$1497 \dmi0__din
71399           attribute \src "libresoc.v:0.0-0.0"
71400           case 3'1--
71401             assign { } { }
71402             assign $2\dmi0__din$next[63:0]$1497 \dmi0_datasr__o
71403           case
71404             assign $2\dmi0__din$next[63:0]$1497 \dmi0__din
71405         end
71406       case
71407         assign $1\dmi0__din$next[63:0]$1496 \dmi0__din
71408     end
71409     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71410     switch \rst
71411       attribute \src "libresoc.v:0.0-0.0"
71412       case 1'1
71413         assign { } { }
71414         assign $3\dmi0__din$next[63:0]$1498 64'0000000000000000000000000000000000000000000000000000000000000000
71415       case
71416         assign $3\dmi0__din$next[63:0]$1498 $1\dmi0__din$next[63:0]$1496
71417     end
71418     sync always
71419       update \dmi0__din$next $0\dmi0__din$next[63:0]$1495
71420   end
71421   attribute \src "libresoc.v:45443.3-45463.6"
71422   process $proc$libresoc.v:45443$1499
71423     assign { } { }
71424     assign { } { }
71425     assign { } { }
71426     assign $0\dmi0_datasr__i$next[63:0]$1500 $3\dmi0_datasr__i$next[63:0]$1503
71427     attribute \src "libresoc.v:45444.5-45444.29"
71428     switch \initial
71429       attribute \src "libresoc.v:45444.9-45444.17"
71430       case 1'1
71431       case
71432     end
71433     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485"
71434     switch \fsm_state$503
71435       attribute \src "libresoc.v:0.0-0.0"
71436       case 3'011
71437         assign { } { }
71438         assign $1\dmi0_datasr__i$next[63:0]$1501 $2\dmi0_datasr__i$next[63:0]$1502
71439         attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506"
71440         switch \dmi0__ack_o
71441           attribute \src "libresoc.v:0.0-0.0"
71442           case 1'1
71443             assign { } { }
71444             assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0__dout
71445           case
71446             assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0_datasr__i
71447         end
71448       case
71449         assign $1\dmi0_datasr__i$next[63:0]$1501 \dmi0_datasr__i
71450     end
71451     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71452     switch \rst
71453       attribute \src "libresoc.v:0.0-0.0"
71454       case 1'1
71455         assign { } { }
71456         assign $3\dmi0_datasr__i$next[63:0]$1503 64'0000000000000000000000000000000000000000000000000000000000000000
71457       case
71458         assign $3\dmi0_datasr__i$next[63:0]$1503 $1\dmi0_datasr__i$next[63:0]$1501
71459     end
71460     sync always
71461       update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1500
71462   end
71463   attribute \src "libresoc.v:45464.3-45482.6"
71464   process $proc$libresoc.v:45464$1504
71465     assign { } { }
71466     assign { } { }
71467     assign { } { }
71468     assign { } { }
71469     assign { } { }
71470     assign { } { }
71471     assign $0\wb_dcache_en$next[0:0]$1505 $2\wb_dcache_en$next[0:0]$1509
71472     assign $0\wb_icache_en$next[0:0]$1506 $2\wb_icache_en$next[0:0]$1510
71473     attribute \src "libresoc.v:45465.5-45465.29"
71474     switch \initial
71475       attribute \src "libresoc.v:45465.9-45465.17"
71476       case 1'1
71477       case
71478     end
71479     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102"
71480     switch \sr5__oe
71481       attribute \src "libresoc.v:0.0-0.0"
71482       case 1'1
71483         assign { } { }
71484         assign { } { }
71485         assign { $1\wb_dcache_en$next[0:0]$1507 $1\wb_icache_en$next[0:0]$1508 } \sr5__o
71486       case
71487         assign $1\wb_dcache_en$next[0:0]$1507 \wb_dcache_en
71488         assign $1\wb_icache_en$next[0:0]$1508 \wb_icache_en
71489     end
71490     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71491     switch \rst
71492       attribute \src "libresoc.v:0.0-0.0"
71493       case 1'1
71494         assign { } { }
71495         assign { } { }
71496         assign $2\wb_icache_en$next[0:0]$1510 1'1
71497         assign $2\wb_dcache_en$next[0:0]$1509 1'1
71498       case
71499         assign $2\wb_dcache_en$next[0:0]$1509 $1\wb_dcache_en$next[0:0]$1507
71500         assign $2\wb_icache_en$next[0:0]$1510 $1\wb_icache_en$next[0:0]$1508
71501     end
71502     sync always
71503       update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$1505
71504       update \wb_icache_en$next $0\wb_icache_en$next[0:0]$1506
71505   end
71506   attribute \src "libresoc.v:45483.3-45492.6"
71507   process $proc$libresoc.v:45483$1511
71508     assign { } { }
71509     assign { } { }
71510     assign $0\sr5__i[1:0] $1\sr5__i[1:0]
71511     attribute \src "libresoc.v:45484.5-45484.29"
71512     switch \initial
71513       attribute \src "libresoc.v:45484.9-45484.17"
71514       case 1'1
71515       case
71516     end
71517     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105"
71518     switch \sr5__ie
71519       attribute \src "libresoc.v:0.0-0.0"
71520       case 1'1
71521         assign { } { }
71522         assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en }
71523       case
71524         assign $1\sr5__i[1:0] 2'00
71525     end
71526     sync always
71527       update \sr5__i $0\sr5__i[1:0]
71528   end
71529   attribute \src "libresoc.v:45493.3-45510.6"
71530   process $proc$libresoc.v:45493$1512
71531     assign { } { }
71532     assign { } { }
71533     assign { } { }
71534     assign $0\io_sr$next[153:0]$1513 $2\io_sr$next[153:0]$1515
71535     attribute \src "libresoc.v:45494.5-45494.29"
71536     switch \initial
71537       attribute \src "libresoc.v:45494.9-45494.17"
71538       case 1'1
71539       case
71540     end
71541     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552"
71542     switch { \io_update \io_shift \io_capture }
71543       attribute \src "libresoc.v:0.0-0.0"
71544       case 3'--1
71545         assign { } { }
71546         assign $1\io_sr$next[153:0]$1514 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i }
71547       attribute \src "libresoc.v:0.0-0.0"
71548       case 3'-1-
71549         assign { } { }
71550         assign $1\io_sr$next[153:0]$1514 { \io_sr [152:0] \TAP_bus__tdi }
71551       case
71552         assign $1\io_sr$next[153:0]$1514 \io_sr
71553     end
71554     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71555     switch \posjtag_rst
71556       attribute \src "libresoc.v:0.0-0.0"
71557       case 1'1
71558         assign { } { }
71559         assign $2\io_sr$next[153:0]$1515 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
71560       case
71561         assign $2\io_sr$next[153:0]$1515 $1\io_sr$next[153:0]$1514
71562     end
71563     sync always
71564       update \io_sr$next $0\io_sr$next[153:0]$1513
71565   end
71566   attribute \src "libresoc.v:45511.3-45531.6"
71567   process $proc$libresoc.v:45511$1516
71568     assign { } { }
71569     assign { } { }
71570     assign { } { }
71571     assign $0\io_bd$next[153:0]$1517 $2\io_bd$next[153:0]$1519
71572     attribute \src "libresoc.v:45512.5-45512.29"
71573     switch \initial
71574       attribute \src "libresoc.v:45512.9-45512.17"
71575       case 1'1
71576       case
71577     end
71578     attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552"
71579     switch { \io_update \io_shift \io_capture }
71580       attribute \src "libresoc.v:0.0-0.0"
71581       case 3'--1
71582         assign $1\io_bd$next[153:0]$1518 \io_bd
71583       attribute \src "libresoc.v:0.0-0.0"
71584       case 3'-1-
71585         assign $1\io_bd$next[153:0]$1518 \io_bd
71586       attribute \src "libresoc.v:0.0-0.0"
71587       case 3'1--
71588         assign { } { }
71589         assign $1\io_bd$next[153:0]$1518 \io_sr
71590       case
71591         assign $1\io_bd$next[153:0]$1518 \io_bd
71592     end
71593     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
71594     switch \negjtag_rst
71595       attribute \src "libresoc.v:0.0-0.0"
71596       case 1'1
71597         assign { } { }
71598         assign $2\io_bd$next[153:0]$1519 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
71599       case
71600         assign $2\io_bd$next[153:0]$1519 $1\io_bd$next[153:0]$1518
71601     end
71602     sync always
71603       update \io_bd$next $0\io_bd$next[153:0]$1517
71604   end
71605   connect \$9 $eq$libresoc.v:44454$1072_Y
71606   connect \$99 $ternary$libresoc.v:44455$1073_Y
71607   connect \$101 $ternary$libresoc.v:44456$1074_Y
71608   connect \$103 $ternary$libresoc.v:44457$1075_Y
71609   connect \$105 $ternary$libresoc.v:44458$1076_Y
71610   connect \$107 $ternary$libresoc.v:44459$1077_Y
71611   connect \$109 $ternary$libresoc.v:44460$1078_Y
71612   connect \$111 $ternary$libresoc.v:44461$1079_Y
71613   connect \$113 $ternary$libresoc.v:44462$1080_Y
71614   connect \$115 $ternary$libresoc.v:44463$1081_Y
71615   connect \$117 $ternary$libresoc.v:44464$1082_Y
71616   connect \$11 $eq$libresoc.v:44465$1083_Y
71617   connect \$119 $ternary$libresoc.v:44466$1084_Y
71618   connect \$121 $ternary$libresoc.v:44467$1085_Y
71619   connect \$123 $ternary$libresoc.v:44468$1086_Y
71620   connect \$125 $ternary$libresoc.v:44469$1087_Y
71621   connect \$127 $ternary$libresoc.v:44470$1088_Y
71622   connect \$129 $ternary$libresoc.v:44471$1089_Y
71623   connect \$131 $ternary$libresoc.v:44472$1090_Y
71624   connect \$133 $ternary$libresoc.v:44473$1091_Y
71625   connect \$135 $ternary$libresoc.v:44474$1092_Y
71626   connect \$137 $ternary$libresoc.v:44475$1093_Y
71627   connect \$13 $eq$libresoc.v:44476$1094_Y
71628   connect \$139 $ternary$libresoc.v:44477$1095_Y
71629   connect \$141 $ternary$libresoc.v:44478$1096_Y
71630   connect \$143 $ternary$libresoc.v:44479$1097_Y
71631   connect \$145 $ternary$libresoc.v:44480$1098_Y
71632   connect \$147 $ternary$libresoc.v:44481$1099_Y
71633   connect \$149 $ternary$libresoc.v:44482$1100_Y
71634   connect \$151 $ternary$libresoc.v:44483$1101_Y
71635   connect \$153 $ternary$libresoc.v:44484$1102_Y
71636   connect \$155 $ternary$libresoc.v:44485$1103_Y
71637   connect \$157 $ternary$libresoc.v:44486$1104_Y
71638   connect \$15 $or$libresoc.v:44487$1105_Y
71639   connect \$159 $ternary$libresoc.v:44488$1106_Y
71640   connect \$161 $ternary$libresoc.v:44489$1107_Y
71641   connect \$163 $ternary$libresoc.v:44490$1108_Y
71642   connect \$165 $ternary$libresoc.v:44491$1109_Y
71643   connect \$167 $ternary$libresoc.v:44492$1110_Y
71644   connect \$169 $ternary$libresoc.v:44493$1111_Y
71645   connect \$171 $ternary$libresoc.v:44494$1112_Y
71646   connect \$173 $ternary$libresoc.v:44495$1113_Y
71647   connect \$175 $ternary$libresoc.v:44496$1114_Y
71648   connect \$177 $ternary$libresoc.v:44497$1115_Y
71649   connect \$17 $and$libresoc.v:44498$1116_Y
71650   connect \$179 $ternary$libresoc.v:44499$1117_Y
71651   connect \$181 $ternary$libresoc.v:44500$1118_Y
71652   connect \$183 $ternary$libresoc.v:44501$1119_Y
71653   connect \$185 $ternary$libresoc.v:44502$1120_Y
71654   connect \$187 $ternary$libresoc.v:44503$1121_Y
71655   connect \$189 $ternary$libresoc.v:44504$1122_Y
71656   connect \$191 $ternary$libresoc.v:44505$1123_Y
71657   connect \$193 $ternary$libresoc.v:44506$1124_Y
71658   connect \$195 $ternary$libresoc.v:44507$1125_Y
71659   connect \$197 $ternary$libresoc.v:44508$1126_Y
71660   connect \$1 $eq$libresoc.v:44509$1127_Y
71661   connect \$19 $eq$libresoc.v:44510$1128_Y
71662   connect \$199 $ternary$libresoc.v:44511$1129_Y
71663   connect \$201 $ternary$libresoc.v:44512$1130_Y
71664   connect \$203 $ternary$libresoc.v:44513$1131_Y
71665   connect \$205 $ternary$libresoc.v:44514$1132_Y
71666   connect \$207 $ternary$libresoc.v:44515$1133_Y
71667   connect \$209 $ternary$libresoc.v:44516$1134_Y
71668   connect \$211 $ternary$libresoc.v:44517$1135_Y
71669   connect \$213 $ternary$libresoc.v:44518$1136_Y
71670   connect \$215 $ternary$libresoc.v:44519$1137_Y
71671   connect \$217 $ternary$libresoc.v:44520$1138_Y
71672   connect \$21 $eq$libresoc.v:44521$1139_Y
71673   connect \$219 $ternary$libresoc.v:44522$1140_Y
71674   connect \$221 $ternary$libresoc.v:44523$1141_Y
71675   connect \$223 $ternary$libresoc.v:44524$1142_Y
71676   connect \$225 $ternary$libresoc.v:44525$1143_Y
71677   connect \$227 $ternary$libresoc.v:44526$1144_Y
71678   connect \$229 $ternary$libresoc.v:44527$1145_Y
71679   connect \$231 $ternary$libresoc.v:44528$1146_Y
71680   connect \$233 $ternary$libresoc.v:44529$1147_Y
71681   connect \$235 $ternary$libresoc.v:44530$1148_Y
71682   connect \$237 $ternary$libresoc.v:44531$1149_Y
71683   connect \$23 $or$libresoc.v:44532$1150_Y
71684   connect \$239 $ternary$libresoc.v:44533$1151_Y
71685   connect \$241 $ternary$libresoc.v:44534$1152_Y
71686   connect \$243 $ternary$libresoc.v:44535$1153_Y
71687   connect \$245 $ternary$libresoc.v:44536$1154_Y
71688   connect \$247 $ternary$libresoc.v:44537$1155_Y
71689   connect \$249 $ternary$libresoc.v:44538$1156_Y
71690   connect \$251 $ternary$libresoc.v:44539$1157_Y
71691   connect \$253 $ternary$libresoc.v:44540$1158_Y
71692   connect \$255 $ternary$libresoc.v:44541$1159_Y
71693   connect \$257 $ternary$libresoc.v:44542$1160_Y
71694   connect \$25 $eq$libresoc.v:44543$1161_Y
71695   connect \$259 $ternary$libresoc.v:44544$1162_Y
71696   connect \$261 $ternary$libresoc.v:44545$1163_Y
71697   connect \$263 $ternary$libresoc.v:44546$1164_Y
71698   connect \$265 $ternary$libresoc.v:44547$1165_Y
71699   connect \$267 $ternary$libresoc.v:44548$1166_Y
71700   connect \$269 $ternary$libresoc.v:44549$1167_Y
71701   connect \$271 $ternary$libresoc.v:44550$1168_Y
71702   connect \$273 $ternary$libresoc.v:44551$1169_Y
71703   connect \$275 $ternary$libresoc.v:44552$1170_Y
71704   connect \$277 $ternary$libresoc.v:44553$1171_Y
71705   connect \$27 $or$libresoc.v:44554$1172_Y
71706   connect \$279 $ternary$libresoc.v:44555$1173_Y
71707   connect \$281 $ternary$libresoc.v:44556$1174_Y
71708   connect \$283 $ternary$libresoc.v:44557$1175_Y
71709   connect \$285 $ternary$libresoc.v:44558$1176_Y
71710   connect \$287 $ternary$libresoc.v:44559$1177_Y
71711   connect \$289 $ternary$libresoc.v:44560$1178_Y
71712   connect \$291 $ternary$libresoc.v:44561$1179_Y
71713   connect \$293 $ternary$libresoc.v:44562$1180_Y
71714   connect \$295 $ternary$libresoc.v:44563$1181_Y
71715   connect \$297 $ternary$libresoc.v:44564$1182_Y
71716   connect \$29 $and$libresoc.v:44565$1183_Y
71717   connect \$299 $ternary$libresoc.v:44566$1184_Y
71718   connect \$301 $ternary$libresoc.v:44567$1185_Y
71719   connect \$303 $ternary$libresoc.v:44568$1186_Y
71720   connect \$305 $ternary$libresoc.v:44569$1187_Y
71721   connect \$307 $ternary$libresoc.v:44570$1188_Y
71722   connect \$309 $ternary$libresoc.v:44571$1189_Y
71723   connect \$311 $ternary$libresoc.v:44572$1190_Y
71724   connect \$313 $ternary$libresoc.v:44573$1191_Y
71725   connect \$315 $ternary$libresoc.v:44574$1192_Y
71726   connect \$317 $ternary$libresoc.v:44575$1193_Y
71727   connect \$31 $and$libresoc.v:44576$1194_Y
71728   connect \$319 $ternary$libresoc.v:44577$1195_Y
71729   connect \$321 $ternary$libresoc.v:44578$1196_Y
71730   connect \$323 $ternary$libresoc.v:44579$1197_Y
71731   connect \$325 $ternary$libresoc.v:44580$1198_Y
71732   connect \$327 $ternary$libresoc.v:44581$1199_Y
71733   connect \$329 $ternary$libresoc.v:44582$1200_Y
71734   connect \$331 $ternary$libresoc.v:44583$1201_Y
71735   connect \$333 $ternary$libresoc.v:44584$1202_Y
71736   connect \$335 $ternary$libresoc.v:44585$1203_Y
71737   connect \$337 $ternary$libresoc.v:44586$1204_Y
71738   connect \$33 $eq$libresoc.v:44587$1205_Y
71739   connect \$339 $ternary$libresoc.v:44588$1206_Y
71740   connect \$341 $ternary$libresoc.v:44589$1207_Y
71741   connect \$343 $ternary$libresoc.v:44590$1208_Y
71742   connect \$345 $ternary$libresoc.v:44591$1209_Y
71743   connect \$347 $ternary$libresoc.v:44592$1210_Y
71744   connect \$349 $ternary$libresoc.v:44593$1211_Y
71745   connect \$351 $ternary$libresoc.v:44594$1212_Y
71746   connect \$353 $ternary$libresoc.v:44595$1213_Y
71747   connect \$355 $ternary$libresoc.v:44596$1214_Y
71748   connect \$357 $ternary$libresoc.v:44597$1215_Y
71749   connect \$35 $eq$libresoc.v:44598$1216_Y
71750   connect \$359 $eq$libresoc.v:44599$1217_Y
71751   connect \$361 $eq$libresoc.v:44600$1218_Y
71752   connect \$363 $or$libresoc.v:44601$1219_Y
71753   connect \$365 $eq$libresoc.v:44602$1220_Y
71754   connect \$367 $or$libresoc.v:44603$1221_Y
71755   connect \$369 $and$libresoc.v:44604$1222_Y
71756   connect \$371 $eq$libresoc.v:44605$1223_Y
71757   connect \$373 $ne$libresoc.v:44606$1224_Y
71758   connect \$375 $and$libresoc.v:44607$1225_Y
71759   connect \$377 $ne$libresoc.v:44608$1226_Y
71760   connect \$37 $or$libresoc.v:44609$1227_Y
71761   connect \$379 $and$libresoc.v:44610$1228_Y
71762   connect \$381 $ne$libresoc.v:44611$1229_Y
71763   connect \$383 $and$libresoc.v:44612$1230_Y
71764   connect \$385 $not$libresoc.v:44613$1231_Y
71765   connect \$387 $and$libresoc.v:44614$1232_Y
71766   connect \$389 $eq$libresoc.v:44615$1233_Y
71767   connect \$391 $ne$libresoc.v:44616$1234_Y
71768   connect \$393 $and$libresoc.v:44617$1235_Y
71769   connect \$395 $ne$libresoc.v:44618$1236_Y
71770   connect \$397 $and$libresoc.v:44619$1237_Y
71771   connect \$3 $eq$libresoc.v:44620$1238_Y
71772   connect \$39 $eq$libresoc.v:44621$1239_Y
71773   connect \$399 $ne$libresoc.v:44622$1240_Y
71774   connect \$401 $and$libresoc.v:44623$1241_Y
71775   connect \$403 $not$libresoc.v:44624$1242_Y
71776   connect \$405 $and$libresoc.v:44625$1243_Y
71777   connect \$407 $eq$libresoc.v:44626$1244_Y
71778   connect \$409 $eq$libresoc.v:44627$1245_Y
71779   connect \$411 $ne$libresoc.v:44628$1246_Y
71780   connect \$413 $and$libresoc.v:44629$1247_Y
71781   connect \$415 $ne$libresoc.v:44630$1248_Y
71782   connect \$417 $and$libresoc.v:44631$1249_Y
71783   connect \$41 $or$libresoc.v:44632$1250_Y
71784   connect \$419 $ne$libresoc.v:44633$1251_Y
71785   connect \$421 $and$libresoc.v:44634$1252_Y
71786   connect \$423 $not$libresoc.v:44635$1253_Y
71787   connect \$425 $and$libresoc.v:44636$1254_Y
71788   connect \$427 $eq$libresoc.v:44637$1255_Y
71789   connect \$429 $ne$libresoc.v:44638$1256_Y
71790   connect \$431 $and$libresoc.v:44639$1257_Y
71791   connect \$433 $ne$libresoc.v:44640$1258_Y
71792   connect \$435 $and$libresoc.v:44641$1259_Y
71793   connect \$437 $ne$libresoc.v:44642$1260_Y
71794   connect \$43 $and$libresoc.v:44643$1261_Y
71795   connect \$439 $and$libresoc.v:44644$1262_Y
71796   connect \$441 $not$libresoc.v:44645$1263_Y
71797   connect \$443 $and$libresoc.v:44646$1264_Y
71798   connect \$445 $eq$libresoc.v:44647$1265_Y
71799   connect \$447 $eq$libresoc.v:44648$1266_Y
71800   connect \$449 $ne$libresoc.v:44649$1267_Y
71801   connect \$451 $and$libresoc.v:44650$1268_Y
71802   connect \$453 $ne$libresoc.v:44651$1269_Y
71803   connect \$455 $and$libresoc.v:44652$1270_Y
71804   connect \$457 $ne$libresoc.v:44653$1271_Y
71805   connect \$45 $and$libresoc.v:44654$1272_Y
71806   connect \$459 $and$libresoc.v:44655$1273_Y
71807   connect \$461 $not$libresoc.v:44656$1274_Y
71808   connect \$463 $and$libresoc.v:44657$1275_Y
71809   connect \$465 $eq$libresoc.v:44658$1276_Y
71810   connect \$467 $ne$libresoc.v:44659$1277_Y
71811   connect \$469 $and$libresoc.v:44660$1278_Y
71812   connect \$471 $ne$libresoc.v:44661$1279_Y
71813   connect \$473 $and$libresoc.v:44662$1280_Y
71814   connect \$475 $ne$libresoc.v:44663$1281_Y
71815   connect \$477 $and$libresoc.v:44664$1282_Y
71816   connect \$47 $eq$libresoc.v:44665$1283_Y
71817   connect \$479 $not$libresoc.v:44666$1284_Y
71818   connect \$481 $and$libresoc.v:44667$1285_Y
71819   connect \$484 $eq$libresoc.v:44668$1286_Y
71820   connect \$483 $not$libresoc.v:44669$1287_Y
71821   connect \$487 $eq$libresoc.v:44670$1288_Y
71822   connect \$489 $eq$libresoc.v:44671$1289_Y
71823   connect \$491 $or$libresoc.v:44672$1290_Y
71824   connect \$493 $eq$libresoc.v:44673$1291_Y
71825   connect \$496 $add$libresoc.v:44674$1292_Y
71826   connect \$49 $eq$libresoc.v:44675$1293_Y
71827   connect \$499 $add$libresoc.v:44676$1294_Y
71828   connect \$501 $pos$libresoc.v:44677$1296_Y
71829   connect \$504 $eq$libresoc.v:44678$1297_Y
71830   connect \$506 $eq$libresoc.v:44679$1298_Y
71831   connect \$508 $or$libresoc.v:44680$1299_Y
71832   connect \$510 $eq$libresoc.v:44681$1300_Y
71833   connect \$513 $add$libresoc.v:44682$1301_Y
71834   connect \$516 $add$libresoc.v:44683$1302_Y
71835   connect \$51 $ternary$libresoc.v:44684$1303_Y
71836   connect \$53 $ternary$libresoc.v:44685$1304_Y
71837   connect \$55 $ternary$libresoc.v:44686$1305_Y
71838   connect \$57 $ternary$libresoc.v:44687$1306_Y
71839   connect \$5 $or$libresoc.v:44688$1307_Y
71840   connect \$59 $ternary$libresoc.v:44689$1308_Y
71841   connect \$61 $ternary$libresoc.v:44690$1309_Y
71842   connect \$63 $ternary$libresoc.v:44691$1310_Y
71843   connect \$65 $ternary$libresoc.v:44692$1311_Y
71844   connect \$67 $ternary$libresoc.v:44693$1312_Y
71845   connect \$69 $ternary$libresoc.v:44694$1313_Y
71846   connect \$71 $ternary$libresoc.v:44695$1314_Y
71847   connect \$73 $ternary$libresoc.v:44696$1315_Y
71848   connect \$75 $ternary$libresoc.v:44697$1316_Y
71849   connect \$77 $ternary$libresoc.v:44698$1317_Y
71850   connect \$7 $and$libresoc.v:44699$1318_Y
71851   connect \$79 $ternary$libresoc.v:44700$1319_Y
71852   connect \$81 $ternary$libresoc.v:44701$1320_Y
71853   connect \$83 $ternary$libresoc.v:44702$1321_Y
71854   connect \$85 $ternary$libresoc.v:44703$1322_Y
71855   connect \$87 $ternary$libresoc.v:44704$1323_Y
71856   connect \$89 $ternary$libresoc.v:44705$1324_Y
71857   connect \$91 $ternary$libresoc.v:44706$1325_Y
71858   connect \$93 $ternary$libresoc.v:44707$1326_Y
71859   connect \$95 $ternary$libresoc.v:44708$1327_Y
71860   connect \$97 $ternary$libresoc.v:44709$1328_Y
71861   connect \$495 \$496
71862   connect \$498 \$499
71863   connect \$512 \$513
71864   connect \$515 \$516
71865   connect \sr5__ie 1'0
71866   connect \sr0__i \sr0__o
71867   connect \dmi0__we_i \$510
71868   connect \dmi0__req_i \$508
71869   connect \dmi0_addrsr__i \$501
71870   connect \jtag_wb__we \$493
71871   connect \jtag_wb__stb \$491
71872   connect \jtag_wb__cyc \$483
71873   connect \jtag_wb__sel 1'1
71874   connect \jtag_wb_addrsr__i \jtag_wb__adr
71875   connect \sr5_update \$477
71876   connect \sr5_shift \$473
71877   connect \sr5_capture \$469
71878   connect \sr5_isir \$465
71879   connect \sr5__o \sr5_reg
71880   connect \dmi0_datasr_update \$459
71881   connect \dmi0_datasr_shift \$455
71882   connect \dmi0_datasr_capture \$451
71883   connect \dmi0_datasr_isir { \$447 \$445 }
71884   connect \dmi0_datasr__o \dmi0_datasr_reg
71885   connect \dmi0_addrsr_update \$439
71886   connect \dmi0_addrsr_shift \$435
71887   connect \dmi0_addrsr_capture \$431
71888   connect \dmi0_addrsr_isir \$427
71889   connect \dmi0_addrsr__o \dmi0_addrsr_reg
71890   connect \jtag_wb_datasr_update \$421
71891   connect \jtag_wb_datasr_shift \$417
71892   connect \jtag_wb_datasr_capture \$413
71893   connect \jtag_wb_datasr_isir { \$409 \$407 }
71894   connect \jtag_wb_datasr__o \jtag_wb_datasr_reg
71895   connect \jtag_wb_addrsr_update \$401
71896   connect \jtag_wb_addrsr_shift \$397
71897   connect \jtag_wb_addrsr_capture \$393
71898   connect \jtag_wb_addrsr_isir \$389
71899   connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg
71900   connect \sr0_update \$383
71901   connect \sr0_shift \$379
71902   connect \sr0_capture \$375
71903   connect \sr0_isir \$371
71904   connect \sr0__o \sr0_reg
71905   connect \sdr_dq_15__pad__oe \$357
71906   connect \sdr_dq_15__pad__o \$355
71907   connect \sdr_dq_15__core__i \$353
71908   connect \sdr_dq_14__pad__oe \$351
71909   connect \sdr_dq_14__pad__o \$349
71910   connect \sdr_dq_14__core__i \$347
71911   connect \sdr_dq_13__pad__oe \$345
71912   connect \sdr_dq_13__pad__o \$343
71913   connect \sdr_dq_13__core__i \$341
71914   connect \sdr_dq_12__pad__oe \$339
71915   connect \sdr_dq_12__pad__o \$337
71916   connect \sdr_dq_12__core__i \$335
71917   connect \sdr_dq_11__pad__oe \$333
71918   connect \sdr_dq_11__pad__o \$331
71919   connect \sdr_dq_11__core__i \$329
71920   connect \sdr_dq_10__pad__oe \$327
71921   connect \sdr_dq_10__pad__o \$325
71922   connect \sdr_dq_10__core__i \$323
71923   connect \sdr_dq_9__pad__oe \$321
71924   connect \sdr_dq_9__pad__o \$319
71925   connect \sdr_dq_9__core__i \$317
71926   connect \sdr_dq_8__pad__oe \$315
71927   connect \sdr_dq_8__pad__o \$313
71928   connect \sdr_dq_8__core__i \$311
71929   connect \sdr_dm_1__pad__oe \$309
71930   connect \sdr_dm_1__pad__o \$307
71931   connect \sdr_dm_1__core__i \$305
71932   connect \sdr_a_12__pad__o \$303
71933   connect \sdr_a_11__pad__o \$301
71934   connect \sdr_a_10__pad__o \$299
71935   connect \sdr_cs_n__pad__o \$297
71936   connect \sdr_we_n__pad__o \$295
71937   connect \sdr_cas_n__pad__o \$293
71938   connect \sdr_ras_n__pad__o \$291
71939   connect \sdr_cke__pad__o \$289
71940   connect \sdr_clock__pad__o \$287
71941   connect \sdr_ba_1__pad__o \$285
71942   connect \sdr_ba_0__pad__o \$283
71943   connect \sdr_a_9__pad__o \$281
71944   connect \sdr_a_8__pad__o \$279
71945   connect \sdr_a_7__pad__o \$277
71946   connect \sdr_a_6__pad__o \$275
71947   connect \sdr_a_5__pad__o \$273
71948   connect \sdr_a_4__pad__o \$271
71949   connect \sdr_a_3__pad__o \$269
71950   connect \sdr_a_2__pad__o \$267
71951   connect \sdr_a_1__pad__o \$265
71952   connect \sdr_a_0__pad__o \$263
71953   connect \sdr_dq_7__pad__oe \$261
71954   connect \sdr_dq_7__pad__o \$259
71955   connect \sdr_dq_7__core__i \$257
71956   connect \sdr_dq_6__pad__oe \$255
71957   connect \sdr_dq_6__pad__o \$253
71958   connect \sdr_dq_6__core__i \$251
71959   connect \sdr_dq_5__pad__oe \$249
71960   connect \sdr_dq_5__pad__o \$247
71961   connect \sdr_dq_5__core__i \$245
71962   connect \sdr_dq_4__pad__oe \$243
71963   connect \sdr_dq_4__pad__o \$241
71964   connect \sdr_dq_4__core__i \$239
71965   connect \sdr_dq_3__pad__oe \$237
71966   connect \sdr_dq_3__pad__o \$235
71967   connect \sdr_dq_3__core__i \$233
71968   connect \sdr_dq_2__pad__oe \$231
71969   connect \sdr_dq_2__pad__o \$229
71970   connect \sdr_dq_2__core__i \$227
71971   connect \sdr_dq_1__pad__oe \$225
71972   connect \sdr_dq_1__pad__o \$223
71973   connect \sdr_dq_1__core__i \$221
71974   connect \sdr_dq_0__pad__oe \$219
71975   connect \sdr_dq_0__pad__o \$217
71976   connect \sdr_dq_0__core__i \$215
71977   connect \sdr_dm_0__pad__o \$213
71978   connect \sd0_data3__pad__oe \$211
71979   connect \sd0_data3__pad__o \$209
71980   connect \sd0_data3__core__i \$207
71981   connect \sd0_data2__pad__oe \$205
71982   connect \sd0_data2__pad__o \$203
71983   connect \sd0_data2__core__i \$201
71984   connect \sd0_data1__pad__oe \$199
71985   connect \sd0_data1__pad__o \$197
71986   connect \sd0_data1__core__i \$195
71987   connect \sd0_data0__pad__oe \$193
71988   connect \sd0_data0__pad__o \$191
71989   connect \sd0_data0__core__i \$189
71990   connect \sd0_clk__pad__o \$187
71991   connect \sd0_cmd__pad__oe \$185
71992   connect \sd0_cmd__pad__o \$183
71993   connect \sd0_cmd__core__i \$181
71994   connect \pwm_1__pad__o \$179
71995   connect \pwm_0__pad__o \$177
71996   connect \mtwi_scl__pad__o \$175
71997   connect \mtwi_sda__pad__oe \$173
71998   connect \mtwi_sda__pad__o \$171
71999   connect \mtwi_sda__core__i \$169
72000   connect \mspi1_miso__core__i \$167
72001   connect \mspi1_mosi__pad__o \$165
72002   connect \mspi1_cs_n__pad__o \$163
72003   connect \mspi1_clk__pad__o \$161
72004   connect \mspi0_miso__core__i \$159
72005   connect \mspi0_mosi__pad__o \$157
72006   connect \mspi0_cs_n__pad__o \$155
72007   connect \mspi0_clk__pad__o \$153
72008   connect \gpio_s7__pad__oe \$151
72009   connect \gpio_s7__pad__o \$149
72010   connect \gpio_s7__core__i \$147
72011   connect \gpio_s6__pad__oe \$145
72012   connect \gpio_s6__pad__o \$143
72013   connect \gpio_s6__core__i \$141
72014   connect \gpio_s5__pad__oe \$139
72015   connect \gpio_s5__pad__o \$137
72016   connect \gpio_s5__core__i \$135
72017   connect \gpio_s4__pad__oe \$133
72018   connect \gpio_s4__pad__o \$131
72019   connect \gpio_s4__core__i \$129
72020   connect \gpio_s3__pad__oe \$127
72021   connect \gpio_s3__pad__o \$125
72022   connect \gpio_s3__core__i \$123
72023   connect \gpio_s2__pad__oe \$121
72024   connect \gpio_s2__pad__o \$119
72025   connect \gpio_s2__core__i \$117
72026   connect \gpio_s1__pad__oe \$115
72027   connect \gpio_s1__pad__o \$113
72028   connect \gpio_s1__core__i \$111
72029   connect \gpio_s0__pad__oe \$109
72030   connect \gpio_s0__pad__o \$107
72031   connect \gpio_s0__core__i \$105
72032   connect \gpio_e15__pad__oe \$103
72033   connect \gpio_e15__pad__o \$101
72034   connect \gpio_e15__core__i \$99
72035   connect \gpio_e14__pad__oe \$97
72036   connect \gpio_e14__pad__o \$95
72037   connect \gpio_e14__core__i \$93
72038   connect \gpio_e13__pad__oe \$91
72039   connect \gpio_e13__pad__o \$89
72040   connect \gpio_e13__core__i \$87
72041   connect \gpio_e12__pad__oe \$85
72042   connect \gpio_e12__pad__o \$83
72043   connect \gpio_e12__core__i \$81
72044   connect \gpio_e11__pad__oe \$79
72045   connect \gpio_e11__pad__o \$77
72046   connect \gpio_e11__core__i \$75
72047   connect \gpio_e10__pad__oe \$73
72048   connect \gpio_e10__pad__o \$71
72049   connect \gpio_e10__core__i \$69
72050   connect \gpio_e9__pad__oe \$67
72051   connect \gpio_e9__pad__o \$65
72052   connect \gpio_e9__core__i \$63
72053   connect \gpio_e8__pad__oe \$61
72054   connect \gpio_e8__pad__o \$59
72055   connect \gpio_e8__core__i \$57
72056   connect \eint_2__core__i \$55
72057   connect \eint_1__core__i \$53
72058   connect \eint_0__core__i \$51
72059   connect \io_bd2core \$49
72060   connect \io_bd2io \$47
72061   connect \io_update \$45
72062   connect \io_shift \$31
72063   connect \io_capture \$17
72064   connect \_idblock_id_bypass \$9
72065   connect \_idblock_select_id \$7
72066 end
72067 attribute \src "ls180.v:4.1-10575.10"
72068 attribute \cells_not_processed 1
72069 module \ls180
72070   attribute \src "ls180.v:10059.1-10069.4"
72071   wire width 7 $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693
72072   attribute \src "ls180.v:10059.1-10069.4"
72073   wire width 32 $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694
72074   attribute \src "ls180.v:10059.1-10069.4"
72075   wire width 32 $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695
72076   attribute \src "ls180.v:10059.1-10069.4"
72077   wire width 7 $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696
72078   attribute \src "ls180.v:10059.1-10069.4"
72079   wire width 32 $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697
72080   attribute \src "ls180.v:10059.1-10069.4"
72081   wire width 32 $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698
72082   attribute \src "ls180.v:10059.1-10069.4"
72083   wire width 7 $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699
72084   attribute \src "ls180.v:10059.1-10069.4"
72085   wire width 32 $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700
72086   attribute \src "ls180.v:10059.1-10069.4"
72087   wire width 32 $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701
72088   attribute \src "ls180.v:10059.1-10069.4"
72089   wire width 7 $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702
72090   attribute \src "ls180.v:10059.1-10069.4"
72091   wire width 32 $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703
72092   attribute \src "ls180.v:10059.1-10069.4"
72093   wire width 32 $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704
72094   attribute \src "ls180.v:10079.1-10083.4"
72095   wire width 3 $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707
72096   attribute \src "ls180.v:10079.1-10083.4"
72097   wire width 25 $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708
72098   attribute \src "ls180.v:10079.1-10083.4"
72099   wire width 25 $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709
72100   attribute \src "ls180.v:10093.1-10097.4"
72101   wire width 3 $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714
72102   attribute \src "ls180.v:10093.1-10097.4"
72103   wire width 25 $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715
72104   attribute \src "ls180.v:10093.1-10097.4"
72105   wire width 25 $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716
72106   attribute \src "ls180.v:10107.1-10111.4"
72107   wire width 3 $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721
72108   attribute \src "ls180.v:10107.1-10111.4"
72109   wire width 25 $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722
72110   attribute \src "ls180.v:10107.1-10111.4"
72111   wire width 25 $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723
72112   attribute \src "ls180.v:10121.1-10125.4"
72113   wire width 3 $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728
72114   attribute \src "ls180.v:10121.1-10125.4"
72115   wire width 25 $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729
72116   attribute \src "ls180.v:10121.1-10125.4"
72117   wire width 25 $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730
72118   attribute \src "ls180.v:10136.1-10140.4"
72119   wire width 4 $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735
72120   attribute \src "ls180.v:10136.1-10140.4"
72121   wire width 10 $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736
72122   attribute \src "ls180.v:10136.1-10140.4"
72123   wire width 10 $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737
72124   attribute \src "ls180.v:10153.1-10157.4"
72125   wire width 4 $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742
72126   attribute \src "ls180.v:10153.1-10157.4"
72127   wire width 10 $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743
72128   attribute \src "ls180.v:10153.1-10157.4"
72129   wire width 10 $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744
72130   attribute \src "ls180.v:10169.1-10173.4"
72131   wire width 5 $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749
72132   attribute \src "ls180.v:10169.1-10173.4"
72133   wire width 10 $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750
72134   attribute \src "ls180.v:10169.1-10173.4"
72135   wire width 10 $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751
72136   attribute \src "ls180.v:10183.1-10187.4"
72137   wire width 5 $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756
72138   attribute \src "ls180.v:10183.1-10187.4"
72139   wire width 10 $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757
72140   attribute \src "ls180.v:10183.1-10187.4"
72141   wire width 10 $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758
72142   attribute \src "ls180.v:3226.1-3319.4"
72143   wire width 3 $0\builder_bankmachine0_next_state[2:0]
72144   attribute \src "ls180.v:7431.1-10055.4"
72145   wire width 3 $0\builder_bankmachine0_state[2:0]
72146   attribute \src "ls180.v:3383.1-3476.4"
72147   wire width 3 $0\builder_bankmachine1_next_state[2:0]
72148   attribute \src "ls180.v:7431.1-10055.4"
72149   wire width 3 $0\builder_bankmachine1_state[2:0]
72150   attribute \src "ls180.v:3540.1-3633.4"
72151   wire width 3 $0\builder_bankmachine2_next_state[2:0]
72152   attribute \src "ls180.v:7431.1-10055.4"
72153   wire width 3 $0\builder_bankmachine2_state[2:0]
72154   attribute \src "ls180.v:3697.1-3790.4"
72155   wire width 3 $0\builder_bankmachine3_next_state[2:0]
72156   attribute \src "ls180.v:7431.1-10055.4"
72157   wire width 3 $0\builder_bankmachine3_state[2:0]
72158   attribute \src "ls180.v:6520.1-6536.4"
72159   wire $0\builder_comb_rhs_array_muxed0[0:0]
72160   attribute \src "ls180.v:6741.1-6757.4"
72161   wire $0\builder_comb_rhs_array_muxed10[0:0]
72162   attribute \src "ls180.v:6758.1-6774.4"
72163   wire $0\builder_comb_rhs_array_muxed11[0:0]
72164   attribute \src "ls180.v:6826.1-6833.4"
72165   wire width 22 $0\builder_comb_rhs_array_muxed12[21:0]
72166   attribute \src "ls180.v:6834.1-6841.4"
72167   wire $0\builder_comb_rhs_array_muxed13[0:0]
72168   attribute \src "ls180.v:6842.1-6849.4"
72169   wire $0\builder_comb_rhs_array_muxed14[0:0]
72170   attribute \src "ls180.v:6850.1-6857.4"
72171   wire width 22 $0\builder_comb_rhs_array_muxed15[21:0]
72172   attribute \src "ls180.v:6858.1-6865.4"
72173   wire $0\builder_comb_rhs_array_muxed16[0:0]
72174   attribute \src "ls180.v:6866.1-6873.4"
72175   wire $0\builder_comb_rhs_array_muxed17[0:0]
72176   attribute \src "ls180.v:6874.1-6881.4"
72177   wire width 22 $0\builder_comb_rhs_array_muxed18[21:0]
72178   attribute \src "ls180.v:6882.1-6889.4"
72179   wire $0\builder_comb_rhs_array_muxed19[0:0]
72180   attribute \src "ls180.v:6537.1-6553.4"
72181   wire width 13 $0\builder_comb_rhs_array_muxed1[12:0]
72182   attribute \src "ls180.v:6890.1-6897.4"
72183   wire $0\builder_comb_rhs_array_muxed20[0:0]
72184   attribute \src "ls180.v:6898.1-6905.4"
72185   wire width 22 $0\builder_comb_rhs_array_muxed21[21:0]
72186   attribute \src "ls180.v:6906.1-6913.4"
72187   wire $0\builder_comb_rhs_array_muxed22[0:0]
72188   attribute \src "ls180.v:6914.1-6921.4"
72189   wire $0\builder_comb_rhs_array_muxed23[0:0]
72190   attribute \src "ls180.v:6922.1-6941.4"
72191   wire width 32 $0\builder_comb_rhs_array_muxed24[31:0]
72192   attribute \src "ls180.v:6942.1-6961.4"
72193   wire width 32 $0\builder_comb_rhs_array_muxed25[31:0]
72194   attribute \src "ls180.v:6962.1-6981.4"
72195   wire width 4 $0\builder_comb_rhs_array_muxed26[3:0]
72196   attribute \src "ls180.v:6982.1-7001.4"
72197   wire $0\builder_comb_rhs_array_muxed27[0:0]
72198   attribute \src "ls180.v:7002.1-7021.4"
72199   wire $0\builder_comb_rhs_array_muxed28[0:0]
72200   attribute \src "ls180.v:7022.1-7041.4"
72201   wire $0\builder_comb_rhs_array_muxed29[0:0]
72202   attribute \src "ls180.v:6554.1-6570.4"
72203   wire width 2 $0\builder_comb_rhs_array_muxed2[1:0]
72204   attribute \src "ls180.v:7042.1-7061.4"
72205   wire width 3 $0\builder_comb_rhs_array_muxed30[2:0]
72206   attribute \src "ls180.v:7062.1-7081.4"
72207   wire width 2 $0\builder_comb_rhs_array_muxed31[1:0]
72208   attribute \src "ls180.v:6571.1-6587.4"
72209   wire $0\builder_comb_rhs_array_muxed3[0:0]
72210   attribute \src "ls180.v:6588.1-6604.4"
72211   wire $0\builder_comb_rhs_array_muxed4[0:0]
72212   attribute \src "ls180.v:6605.1-6621.4"
72213   wire $0\builder_comb_rhs_array_muxed5[0:0]
72214   attribute \src "ls180.v:6673.1-6689.4"
72215   wire $0\builder_comb_rhs_array_muxed6[0:0]
72216   attribute \src "ls180.v:6690.1-6706.4"
72217   wire width 13 $0\builder_comb_rhs_array_muxed7[12:0]
72218   attribute \src "ls180.v:6707.1-6723.4"
72219   wire width 2 $0\builder_comb_rhs_array_muxed8[1:0]
72220   attribute \src "ls180.v:6724.1-6740.4"
72221   wire $0\builder_comb_rhs_array_muxed9[0:0]
72222   attribute \src "ls180.v:6622.1-6638.4"
72223   wire $0\builder_comb_t_array_muxed0[0:0]
72224   attribute \src "ls180.v:6639.1-6655.4"
72225   wire $0\builder_comb_t_array_muxed1[0:0]
72226   attribute \src "ls180.v:6656.1-6672.4"
72227   wire $0\builder_comb_t_array_muxed2[0:0]
72228   attribute \src "ls180.v:6775.1-6791.4"
72229   wire $0\builder_comb_t_array_muxed3[0:0]
72230   attribute \src "ls180.v:6792.1-6808.4"
72231   wire $0\builder_comb_t_array_muxed4[0:0]
72232   attribute \src "ls180.v:6809.1-6825.4"
72233   wire $0\builder_comb_t_array_muxed5[0:0]
72234   attribute \src "ls180.v:2790.1-2836.4"
72235   wire $0\builder_converter0_next_state[0:0]
72236   attribute \src "ls180.v:7431.1-10055.4"
72237   wire $0\builder_converter0_state[0:0]
72238   attribute \src "ls180.v:2850.1-2896.4"
72239   wire $0\builder_converter1_next_state[0:0]
72240   attribute \src "ls180.v:7431.1-10055.4"
72241   wire $0\builder_converter1_state[0:0]
72242   attribute \src "ls180.v:2910.1-2956.4"
72243   wire $0\builder_converter2_next_state[0:0]
72244   attribute \src "ls180.v:7431.1-10055.4"
72245   wire $0\builder_converter2_state[0:0]
72246   attribute \src "ls180.v:4043.1-4089.4"
72247   wire $0\builder_converter_next_state[0:0]
72248   attribute \src "ls180.v:7431.1-10055.4"
72249   wire $0\builder_converter_state[0:0]
72250   attribute \src "ls180.v:7431.1-10055.4"
72251   wire width 20 $0\builder_count[19:0]
72252   attribute \src "ls180.v:5760.1-5771.4"
72253   wire $0\builder_error[0:0]
72254   attribute \src "ls180.v:7431.1-10055.4"
72255   wire width 3 $0\builder_grant[2:0]
72256   attribute \src "ls180.v:7431.1-10055.4"
72257   wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0]
72258   attribute \src "ls180.v:7431.1-10055.4"
72259   wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0]
72260   attribute \src "ls180.v:7431.1-10055.4"
72261   wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0]
72262   attribute \src "ls180.v:7431.1-10055.4"
72263   wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0]
72264   attribute \src "ls180.v:7431.1-10055.4"
72265   wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0]
72266   attribute \src "ls180.v:7431.1-10055.4"
72267   wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0]
72268   attribute \src "ls180.v:7431.1-10055.4"
72269   wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0]
72270   attribute \src "ls180.v:7431.1-10055.4"
72271   wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0]
72272   attribute \src "ls180.v:7431.1-10055.4"
72273   wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0]
72274   attribute \src "ls180.v:7431.1-10055.4"
72275   wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0]
72276   attribute \src "ls180.v:7431.1-10055.4"
72277   wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0]
72278   attribute \src "ls180.v:7431.1-10055.4"
72279   wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0]
72280   attribute \src "ls180.v:7431.1-10055.4"
72281   wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0]
72282   attribute \src "ls180.v:7431.1-10055.4"
72283   wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0]
72284   attribute \src "ls180.v:7431.1-10055.4"
72285   wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0]
72286   attribute \src "ls180.v:7431.1-10055.4"
72287   wire width 14 $0\builder_libresocsim_adr[13:0]
72288   attribute \src "ls180.v:5649.1-5685.4"
72289   wire width 14 $0\builder_libresocsim_adr_next_value1[13:0]
72290   attribute \src "ls180.v:5649.1-5685.4"
72291   wire $0\builder_libresocsim_adr_next_value_ce1[0:0]
72292   attribute \src "ls180.v:7431.1-10055.4"
72293   wire width 8 $0\builder_libresocsim_dat_w[7:0]
72294   attribute \src "ls180.v:5649.1-5685.4"
72295   wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0]
72296   attribute \src "ls180.v:5649.1-5685.4"
72297   wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0]
72298   attribute \src "ls180.v:7431.1-10055.4"
72299   wire $0\builder_libresocsim_we[0:0]
72300   attribute \src "ls180.v:5649.1-5685.4"
72301   wire $0\builder_libresocsim_we_next_value2[0:0]
72302   attribute \src "ls180.v:5649.1-5685.4"
72303   wire $0\builder_libresocsim_we_next_value_ce2[0:0]
72304   attribute \src "ls180.v:5649.1-5685.4"
72305   wire $0\builder_libresocsim_wishbone_ack[0:0]
72306   attribute \src "ls180.v:5649.1-5685.4"
72307   wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0]
72308   attribute \src "ls180.v:1881.5-1881.44"
72309   wire $0\builder_libresocsim_wishbone_err[0:0]
72310   attribute \src "ls180.v:1770.5-1770.27"
72311   wire $0\builder_locked0[0:0]
72312   attribute \src "ls180.v:1771.5-1771.27"
72313   wire $0\builder_locked1[0:0]
72314   attribute \src "ls180.v:1772.5-1772.27"
72315   wire $0\builder_locked2[0:0]
72316   attribute \src "ls180.v:1773.5-1773.27"
72317   wire $0\builder_locked3[0:0]
72318   attribute \src "ls180.v:3915.1-3987.4"
72319   wire width 3 $0\builder_multiplexer_next_state[2:0]
72320   attribute \src "ls180.v:7431.1-10055.4"
72321   wire width 3 $0\builder_multiplexer_state[2:0]
72322   attribute \src "ls180.v:7431.1-10055.4"
72323   wire $0\builder_multiregimpl0_regs0[0:0]
72324   attribute \src "ls180.v:7431.1-10055.4"
72325   wire $0\builder_multiregimpl0_regs1[0:0]
72326   attribute \src "ls180.v:7431.1-10055.4"
72327   wire $0\builder_multiregimpl10_regs0[0:0]
72328   attribute \src "ls180.v:7431.1-10055.4"
72329   wire $0\builder_multiregimpl10_regs1[0:0]
72330   attribute \src "ls180.v:7431.1-10055.4"
72331   wire $0\builder_multiregimpl11_regs0[0:0]
72332   attribute \src "ls180.v:7431.1-10055.4"
72333   wire $0\builder_multiregimpl11_regs1[0:0]
72334   attribute \src "ls180.v:7431.1-10055.4"
72335   wire $0\builder_multiregimpl12_regs0[0:0]
72336   attribute \src "ls180.v:7431.1-10055.4"
72337   wire $0\builder_multiregimpl12_regs1[0:0]
72338   attribute \src "ls180.v:7431.1-10055.4"
72339   wire $0\builder_multiregimpl13_regs0[0:0]
72340   attribute \src "ls180.v:7431.1-10055.4"
72341   wire $0\builder_multiregimpl13_regs1[0:0]
72342   attribute \src "ls180.v:7431.1-10055.4"
72343   wire $0\builder_multiregimpl14_regs0[0:0]
72344   attribute \src "ls180.v:7431.1-10055.4"
72345   wire $0\builder_multiregimpl14_regs1[0:0]
72346   attribute \src "ls180.v:7431.1-10055.4"
72347   wire $0\builder_multiregimpl15_regs0[0:0]
72348   attribute \src "ls180.v:7431.1-10055.4"
72349   wire $0\builder_multiregimpl15_regs1[0:0]
72350   attribute \src "ls180.v:7431.1-10055.4"
72351   wire $0\builder_multiregimpl16_regs0[0:0]
72352   attribute \src "ls180.v:7431.1-10055.4"
72353   wire $0\builder_multiregimpl16_regs1[0:0]
72354   attribute \src "ls180.v:7431.1-10055.4"
72355   wire $0\builder_multiregimpl1_regs0[0:0]
72356   attribute \src "ls180.v:7431.1-10055.4"
72357   wire $0\builder_multiregimpl1_regs1[0:0]
72358   attribute \src "ls180.v:7431.1-10055.4"
72359   wire $0\builder_multiregimpl2_regs0[0:0]
72360   attribute \src "ls180.v:7431.1-10055.4"
72361   wire $0\builder_multiregimpl2_regs1[0:0]
72362   attribute \src "ls180.v:7431.1-10055.4"
72363   wire $0\builder_multiregimpl3_regs0[0:0]
72364   attribute \src "ls180.v:7431.1-10055.4"
72365   wire $0\builder_multiregimpl3_regs1[0:0]
72366   attribute \src "ls180.v:7431.1-10055.4"
72367   wire $0\builder_multiregimpl4_regs0[0:0]
72368   attribute \src "ls180.v:7431.1-10055.4"
72369   wire $0\builder_multiregimpl4_regs1[0:0]
72370   attribute \src "ls180.v:7431.1-10055.4"
72371   wire $0\builder_multiregimpl5_regs0[0:0]
72372   attribute \src "ls180.v:7431.1-10055.4"
72373   wire $0\builder_multiregimpl5_regs1[0:0]
72374   attribute \src "ls180.v:7431.1-10055.4"
72375   wire $0\builder_multiregimpl6_regs0[0:0]
72376   attribute \src "ls180.v:7431.1-10055.4"
72377   wire $0\builder_multiregimpl6_regs1[0:0]
72378   attribute \src "ls180.v:7431.1-10055.4"
72379   wire $0\builder_multiregimpl7_regs0[0:0]
72380   attribute \src "ls180.v:7431.1-10055.4"
72381   wire $0\builder_multiregimpl7_regs1[0:0]
72382   attribute \src "ls180.v:7431.1-10055.4"
72383   wire $0\builder_multiregimpl8_regs0[0:0]
72384   attribute \src "ls180.v:7431.1-10055.4"
72385   wire $0\builder_multiregimpl8_regs1[0:0]
72386   attribute \src "ls180.v:7431.1-10055.4"
72387   wire $0\builder_multiregimpl9_regs0[0:0]
72388   attribute \src "ls180.v:7431.1-10055.4"
72389   wire $0\builder_multiregimpl9_regs1[0:0]
72390   attribute \src "ls180.v:7431.1-10055.4"
72391   wire $0\builder_new_master_rdata_valid0[0:0]
72392   attribute \src "ls180.v:7431.1-10055.4"
72393   wire $0\builder_new_master_rdata_valid1[0:0]
72394   attribute \src "ls180.v:7431.1-10055.4"
72395   wire $0\builder_new_master_rdata_valid2[0:0]
72396   attribute \src "ls180.v:7431.1-10055.4"
72397   wire $0\builder_new_master_rdata_valid3[0:0]
72398   attribute \src "ls180.v:7431.1-10055.4"
72399   wire $0\builder_new_master_wdata_ready[0:0]
72400   attribute \src "ls180.v:5649.1-5685.4"
72401   wire width 2 $0\builder_next_state[1:0]
72402   attribute \src "ls180.v:3132.1-3162.4"
72403   wire width 2 $0\builder_refresher_next_state[1:0]
72404   attribute \src "ls180.v:7431.1-10055.4"
72405   wire width 2 $0\builder_refresher_state[1:0]
72406   attribute \src "ls180.v:5459.1-5498.4"
72407   wire width 2 $0\builder_sdblock2memdma_next_state[1:0]
72408   attribute \src "ls180.v:7431.1-10055.4"
72409   wire width 2 $0\builder_sdblock2memdma_state[1:0]
72410   attribute \src "ls180.v:5026.1-5105.4"
72411   wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0]
72412   attribute \src "ls180.v:7431.1-10055.4"
72413   wire $0\builder_sdcore_crcupstreaminserter_state[0:0]
72414   attribute \src "ls180.v:5208.1-5398.4"
72415   wire width 3 $0\builder_sdcore_fsm_next_state[2:0]
72416   attribute \src "ls180.v:7431.1-10055.4"
72417   wire width 3 $0\builder_sdcore_fsm_state[2:0]
72418   attribute \src "ls180.v:5518.1-5555.4"
72419   wire $0\builder_sdmem2blockdma_fsm_next_state[0:0]
72420   attribute \src "ls180.v:7431.1-10055.4"
72421   wire $0\builder_sdmem2blockdma_fsm_state[0:0]
72422   attribute \src "ls180.v:5556.1-5592.4"
72423   wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0]
72424   attribute \src "ls180.v:7431.1-10055.4"
72425   wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0]
72426   attribute \src "ls180.v:4701.1-4773.4"
72427   wire width 3 $0\builder_sdphy_fsm_next_state[2:0]
72428   attribute \src "ls180.v:7431.1-10055.4"
72429   wire width 3 $0\builder_sdphy_fsm_state[2:0]
72430   attribute \src "ls180.v:4546.1-4639.4"
72431   wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0]
72432   attribute \src "ls180.v:7431.1-10055.4"
72433   wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0]
72434   attribute \src "ls180.v:4436.1-4512.4"
72435   wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0]
72436   attribute \src "ls180.v:7431.1-10055.4"
72437   wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0]
72438   attribute \src "ls180.v:4673.1-4700.4"
72439   wire $0\builder_sdphy_sdphycrcr_next_state[0:0]
72440   attribute \src "ls180.v:7431.1-10055.4"
72441   wire $0\builder_sdphy_sdphycrcr_state[0:0]
72442   attribute \src "ls180.v:4807.1-4908.4"
72443   wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0]
72444   attribute \src "ls180.v:7431.1-10055.4"
72445   wire width 3 $0\builder_sdphy_sdphydatar_state[2:0]
72446   attribute \src "ls180.v:4402.1-4435.4"
72447   wire $0\builder_sdphy_sdphyinit_next_state[0:0]
72448   attribute \src "ls180.v:7431.1-10055.4"
72449   wire $0\builder_sdphy_sdphyinit_state[0:0]
72450   attribute \src "ls180.v:5760.1-5771.4"
72451   wire $0\builder_shared_ack[0:0]
72452   attribute \src "ls180.v:5760.1-5771.4"
72453   wire width 32 $0\builder_shared_dat_r[31:0]
72454   attribute \src "ls180.v:5710.1-5717.4"
72455   wire width 5 $0\builder_slave_sel[4:0]
72456   attribute \src "ls180.v:7431.1-10055.4"
72457   wire width 5 $0\builder_slave_sel_r[4:0]
72458   attribute \src "ls180.v:4233.1-4281.4"
72459   wire width 2 $0\builder_spimaster0_next_state[1:0]
72460   attribute \src "ls180.v:7431.1-10055.4"
72461   wire width 2 $0\builder_spimaster0_state[1:0]
72462   attribute \src "ls180.v:4292.1-4340.4"
72463   wire width 2 $0\builder_spimaster1_next_state[1:0]
72464   attribute \src "ls180.v:7431.1-10055.4"
72465   wire width 2 $0\builder_spimaster1_state[1:0]
72466   attribute \src "ls180.v:7431.1-10055.4"
72467   wire width 2 $0\builder_state[1:0]
72468   attribute \src "ls180.v:7201.1-7229.4"
72469   wire $0\builder_sync_f_array_muxed0[0:0]
72470   attribute \src "ls180.v:7230.1-7258.4"
72471   wire $0\builder_sync_f_array_muxed1[0:0]
72472   attribute \src "ls180.v:7082.1-7098.4"
72473   wire width 2 $0\builder_sync_rhs_array_muxed0[1:0]
72474   attribute \src "ls180.v:7099.1-7115.4"
72475   wire width 13 $0\builder_sync_rhs_array_muxed1[12:0]
72476   attribute \src "ls180.v:7116.1-7132.4"
72477   wire $0\builder_sync_rhs_array_muxed2[0:0]
72478   attribute \src "ls180.v:7133.1-7149.4"
72479   wire $0\builder_sync_rhs_array_muxed3[0:0]
72480   attribute \src "ls180.v:7150.1-7166.4"
72481   wire $0\builder_sync_rhs_array_muxed4[0:0]
72482   attribute \src "ls180.v:7167.1-7183.4"
72483   wire $0\builder_sync_rhs_array_muxed5[0:0]
72484   attribute \src "ls180.v:7184.1-7200.4"
72485   wire $0\builder_sync_rhs_array_muxed6[0:0]
72486   attribute \src "ls180.v:140.11-140.24"
72487   wire width 3 $0\eint_1[2:0]
72488   attribute \src "ls180.v:7431.1-10055.4"
72489   wire $0\main_cmd_consumed[0:0]
72490   attribute \src "ls180.v:7431.1-10055.4"
72491   wire $0\main_converter_counter[0:0]
72492   attribute \src "ls180.v:4043.1-4089.4"
72493   wire $0\main_converter_counter_converter_next_value[0:0]
72494   attribute \src "ls180.v:4043.1-4089.4"
72495   wire $0\main_converter_counter_converter_next_value_ce[0:0]
72496   attribute \src "ls180.v:7431.1-10055.4"
72497   wire width 32 $0\main_converter_dat_r[31:0]
72498   attribute \src "ls180.v:4043.1-4089.4"
72499   wire $0\main_converter_skip[0:0]
72500   attribute \src "ls180.v:7359.1-7429.4"
72501   wire width 16 $0\main_dfi_p0_rddata[15:0]
72502   attribute \src "ls180.v:7431.1-10055.4"
72503   wire $0\main_dfi_p0_rddata_valid[0:0]
72504   attribute \src "ls180.v:7431.1-10055.4"
72505   wire width 36 $0\main_dummy[35:0]
72506   attribute \src "ls180.v:7431.1-10055.4"
72507   wire $0\main_gpio_oe_re[0:0]
72508   attribute \src "ls180.v:7431.1-10055.4"
72509   wire width 16 $0\main_gpio_oe_storage[15:0]
72510   attribute \src "ls180.v:7431.1-10055.4"
72511   wire $0\main_gpio_out_re[0:0]
72512   attribute \src "ls180.v:7431.1-10055.4"
72513   wire width 16 $0\main_gpio_out_storage[15:0]
72514   attribute \src "ls180.v:7316.1-7334.4"
72515   wire width 16 $0\main_gpio_status[15:0]
72516   attribute \src "ls180.v:7431.1-10055.4"
72517   wire $0\main_i2c_re[0:0]
72518   attribute \src "ls180.v:7431.1-10055.4"
72519   wire width 3 $0\main_i2c_storage[2:0]
72520   attribute \src "ls180.v:7355.1-7357.4"
72521   wire $0\main_int_rst[0:0]
72522   attribute \src "ls180.v:1558.11-1558.41"
72523   wire width 2 $0\main_interface0_bus_bte[1:0]
72524   attribute \src "ls180.v:1557.11-1557.41"
72525   wire width 3 $0\main_interface0_bus_cti[2:0]
72526   attribute \src "ls180.v:5518.1-5555.4"
72527   wire width 32 $0\main_interface1_bus_adr[31:0]
72528   attribute \src "ls180.v:1649.11-1649.41"
72529   wire width 2 $0\main_interface1_bus_bte[1:0]
72530   attribute \src "ls180.v:1648.11-1648.41"
72531   wire width 3 $0\main_interface1_bus_cti[2:0]
72532   attribute \src "ls180.v:5518.1-5555.4"
72533   wire $0\main_interface1_bus_cyc[0:0]
72534   attribute \src "ls180.v:1641.12-1641.45"
72535   wire width 32 $0\main_interface1_bus_dat_w[31:0]
72536   attribute \src "ls180.v:5518.1-5555.4"
72537   wire width 4 $0\main_interface1_bus_sel[3:0]
72538   attribute \src "ls180.v:5518.1-5555.4"
72539   wire $0\main_interface1_bus_stb[0:0]
72540   attribute \src "ls180.v:5518.1-5555.4"
72541   wire $0\main_interface1_bus_we[0:0]
72542   attribute \src "ls180.v:7431.1-10055.4"
72543   wire width 32 $0\main_libresocsim_bus_errors[31:0]
72544   attribute \src "ls180.v:7431.1-10055.4"
72545   wire $0\main_libresocsim_converter0_counter[0:0]
72546   attribute \src "ls180.v:2790.1-2836.4"
72547   wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
72548   attribute \src "ls180.v:2790.1-2836.4"
72549   wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
72550   attribute \src "ls180.v:7431.1-10055.4"
72551   wire width 64 $0\main_libresocsim_converter0_dat_r[63:0]
72552   attribute \src "ls180.v:2790.1-2836.4"
72553   wire $0\main_libresocsim_converter0_skip[0:0]
72554   attribute \src "ls180.v:7431.1-10055.4"
72555   wire $0\main_libresocsim_converter1_counter[0:0]
72556   attribute \src "ls180.v:2850.1-2896.4"
72557   wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
72558   attribute \src "ls180.v:2850.1-2896.4"
72559   wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
72560   attribute \src "ls180.v:7431.1-10055.4"
72561   wire width 64 $0\main_libresocsim_converter1_dat_r[63:0]
72562   attribute \src "ls180.v:2850.1-2896.4"
72563   wire $0\main_libresocsim_converter1_skip[0:0]
72564   attribute \src "ls180.v:7431.1-10055.4"
72565   wire $0\main_libresocsim_converter2_counter[0:0]
72566   attribute \src "ls180.v:2910.1-2956.4"
72567   wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
72568   attribute \src "ls180.v:2910.1-2956.4"
72569   wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
72570   attribute \src "ls180.v:7431.1-10055.4"
72571   wire width 64 $0\main_libresocsim_converter2_dat_r[63:0]
72572   attribute \src "ls180.v:2910.1-2956.4"
72573   wire $0\main_libresocsim_converter2_skip[0:0]
72574   attribute \src "ls180.v:7431.1-10055.4"
72575   wire $0\main_libresocsim_en_re[0:0]
72576   attribute \src "ls180.v:7431.1-10055.4"
72577   wire $0\main_libresocsim_en_storage[0:0]
72578   attribute \src "ls180.v:7431.1-10055.4"
72579   wire $0\main_libresocsim_eventmanager_re[0:0]
72580   attribute \src "ls180.v:7431.1-10055.4"
72581   wire $0\main_libresocsim_eventmanager_storage[0:0]
72582   attribute \src "ls180.v:2790.1-2836.4"
72583   wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0]
72584   attribute \src "ls180.v:171.11-171.69"
72585   wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0]
72586   attribute \src "ls180.v:170.11-170.69"
72587   wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0]
72588   attribute \src "ls180.v:2790.1-2836.4"
72589   wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0]
72590   attribute \src "ls180.v:2778.1-2788.4"
72591   wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
72592   attribute \src "ls180.v:2790.1-2836.4"
72593   wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0]
72594   attribute \src "ls180.v:2790.1-2836.4"
72595   wire $0\main_libresocsim_interface0_converted_interface_stb[0:0]
72596   attribute \src "ls180.v:2790.1-2836.4"
72597   wire $0\main_libresocsim_interface0_converted_interface_we[0:0]
72598   attribute \src "ls180.v:2850.1-2896.4"
72599   wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0]
72600   attribute \src "ls180.v:186.11-186.69"
72601   wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0]
72602   attribute \src "ls180.v:185.11-185.69"
72603   wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0]
72604   attribute \src "ls180.v:2850.1-2896.4"
72605   wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0]
72606   attribute \src "ls180.v:2838.1-2848.4"
72607   wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
72608   attribute \src "ls180.v:2850.1-2896.4"
72609   wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0]
72610   attribute \src "ls180.v:2850.1-2896.4"
72611   wire $0\main_libresocsim_interface1_converted_interface_stb[0:0]
72612   attribute \src "ls180.v:2850.1-2896.4"
72613   wire $0\main_libresocsim_interface1_converted_interface_we[0:0]
72614   attribute \src "ls180.v:2910.1-2956.4"
72615   wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0]
72616   attribute \src "ls180.v:201.11-201.69"
72617   wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0]
72618   attribute \src "ls180.v:200.11-200.69"
72619   wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0]
72620   attribute \src "ls180.v:2910.1-2956.4"
72621   wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0]
72622   attribute \src "ls180.v:2898.1-2908.4"
72623   wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
72624   attribute \src "ls180.v:2910.1-2956.4"
72625   wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0]
72626   attribute \src "ls180.v:2910.1-2956.4"
72627   wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
72628   attribute \src "ls180.v:2910.1-2956.4"
72629   wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
72630   attribute \src "ls180.v:129.12-129.74"
72631   wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
72632   attribute \src "ls180.v:159.5-159.69"
72633   wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
72634   attribute \src "ls180.v:137.5-137.72"
72635   wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
72636   attribute \src "ls180.v:147.12-147.78"
72637   wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
72638   attribute \src "ls180.v:145.5-145.74"
72639   wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
72640   attribute \src "ls180.v:135.5-135.74"
72641   wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
72642   attribute \src "ls180.v:2850.1-2896.4"
72643   wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
72644   attribute \src "ls180.v:76.5-76.46"
72645   wire $0\main_libresocsim_libresoc_dbus_err[0:0]
72646   attribute \src "ls180.v:2790.1-2836.4"
72647   wire $0\main_libresocsim_libresoc_ibus_ack[0:0]
72648   attribute \src "ls180.v:87.5-87.46"
72649   wire $0\main_libresocsim_libresoc_ibus_err[0:0]
72650   attribute \src "ls180.v:2771.1-2776.4"
72651   wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0]
72652   attribute \src "ls180.v:2910.1-2956.4"
72653   wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0]
72654   attribute \src "ls180.v:118.5-118.49"
72655   wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
72656   attribute \src "ls180.v:7431.1-10055.4"
72657   wire $0\main_libresocsim_load_re[0:0]
72658   attribute \src "ls180.v:7431.1-10055.4"
72659   wire width 32 $0\main_libresocsim_load_storage[31:0]
72660   attribute \src "ls180.v:7431.1-10055.4"
72661   wire $0\main_libresocsim_ram_bus_ack[0:0]
72662   attribute \src "ls180.v:217.5-217.40"
72663   wire $0\main_libresocsim_ram_bus_err[0:0]
72664   attribute \src "ls180.v:7431.1-10055.4"
72665   wire $0\main_libresocsim_reload_re[0:0]
72666   attribute \src "ls180.v:7431.1-10055.4"
72667   wire width 32 $0\main_libresocsim_reload_storage[31:0]
72668   attribute \src "ls180.v:7431.1-10055.4"
72669   wire $0\main_libresocsim_reset_re[0:0]
72670   attribute \src "ls180.v:7431.1-10055.4"
72671   wire $0\main_libresocsim_reset_storage[0:0]
72672   attribute \src "ls180.v:7431.1-10055.4"
72673   wire $0\main_libresocsim_scratch_re[0:0]
72674   attribute \src "ls180.v:7431.1-10055.4"
72675   wire width 32 $0\main_libresocsim_scratch_storage[31:0]
72676   attribute \src "ls180.v:7431.1-10055.4"
72677   wire $0\main_libresocsim_update_value_re[0:0]
72678   attribute \src "ls180.v:7431.1-10055.4"
72679   wire $0\main_libresocsim_update_value_storage[0:0]
72680   attribute \src "ls180.v:7431.1-10055.4"
72681   wire width 32 $0\main_libresocsim_value[31:0]
72682   attribute \src "ls180.v:7431.1-10055.4"
72683   wire width 32 $0\main_libresocsim_value_status[31:0]
72684   attribute \src "ls180.v:2959.1-2965.4"
72685   wire width 4 $0\main_libresocsim_we[3:0]
72686   attribute \src "ls180.v:2971.1-2976.4"
72687   wire $0\main_libresocsim_zero_clear[0:0]
72688   attribute \src "ls180.v:7431.1-10055.4"
72689   wire $0\main_libresocsim_zero_old_trigger[0:0]
72690   attribute \src "ls180.v:7431.1-10055.4"
72691   wire $0\main_libresocsim_zero_pending[0:0]
72692   attribute \src "ls180.v:4043.1-4089.4"
72693   wire width 30 $0\main_litedram_wb_adr[29:0]
72694   attribute \src "ls180.v:4043.1-4089.4"
72695   wire $0\main_litedram_wb_cyc[0:0]
72696   attribute \src "ls180.v:4031.1-4041.4"
72697   wire width 16 $0\main_litedram_wb_dat_w[15:0]
72698   attribute \src "ls180.v:4043.1-4089.4"
72699   wire width 2 $0\main_litedram_wb_sel[1:0]
72700   attribute \src "ls180.v:4043.1-4089.4"
72701   wire $0\main_litedram_wb_stb[0:0]
72702   attribute \src "ls180.v:4043.1-4089.4"
72703   wire $0\main_litedram_wb_we[0:0]
72704   attribute \src "ls180.v:7431.1-10055.4"
72705   wire width 32 $0\main_pwm0_counter[31:0]
72706   attribute \src "ls180.v:7431.1-10055.4"
72707   wire $0\main_pwm0_enable_re[0:0]
72708   attribute \src "ls180.v:7431.1-10055.4"
72709   wire $0\main_pwm0_enable_storage[0:0]
72710   attribute \src "ls180.v:7431.1-10055.4"
72711   wire $0\main_pwm0_period_re[0:0]
72712   attribute \src "ls180.v:7431.1-10055.4"
72713   wire width 32 $0\main_pwm0_period_storage[31:0]
72714   attribute \src "ls180.v:7431.1-10055.4"
72715   wire $0\main_pwm0_width_re[0:0]
72716   attribute \src "ls180.v:7431.1-10055.4"
72717   wire width 32 $0\main_pwm0_width_storage[31:0]
72718   attribute \src "ls180.v:7431.1-10055.4"
72719   wire width 32 $0\main_pwm1_counter[31:0]
72720   attribute \src "ls180.v:7431.1-10055.4"
72721   wire $0\main_pwm1_enable_re[0:0]
72722   attribute \src "ls180.v:7431.1-10055.4"
72723   wire $0\main_pwm1_enable_storage[0:0]
72724   attribute \src "ls180.v:7431.1-10055.4"
72725   wire $0\main_pwm1_period_re[0:0]
72726   attribute \src "ls180.v:7431.1-10055.4"
72727   wire width 32 $0\main_pwm1_period_storage[31:0]
72728   attribute \src "ls180.v:7431.1-10055.4"
72729   wire $0\main_pwm1_width_re[0:0]
72730   attribute \src "ls180.v:7431.1-10055.4"
72731   wire width 32 $0\main_pwm1_width_storage[31:0]
72732   attribute \src "ls180.v:7431.1-10055.4"
72733   wire width 3 $0\main_rddata_en[2:0]
72734   attribute \src "ls180.v:7431.1-10055.4"
72735   wire width 2 $0\main_sdblock2mem_converter_demux[1:0]
72736   attribute \src "ls180.v:7431.1-10055.4"
72737   wire $0\main_sdblock2mem_converter_source_first[0:0]
72738   attribute \src "ls180.v:7431.1-10055.4"
72739   wire $0\main_sdblock2mem_converter_source_last[0:0]
72740   attribute \src "ls180.v:7431.1-10055.4"
72741   wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0]
72742   attribute \src "ls180.v:7431.1-10055.4"
72743   wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
72744   attribute \src "ls180.v:7431.1-10055.4"
72745   wire $0\main_sdblock2mem_converter_strobe_all[0:0]
72746   attribute \src "ls180.v:7431.1-10055.4"
72747   wire width 5 $0\main_sdblock2mem_fifo_consume[4:0]
72748   attribute \src "ls180.v:7431.1-10055.4"
72749   wire width 6 $0\main_sdblock2mem_fifo_level[5:0]
72750   attribute \src "ls180.v:7431.1-10055.4"
72751   wire width 5 $0\main_sdblock2mem_fifo_produce[4:0]
72752   attribute \src "ls180.v:1582.5-1582.41"
72753   wire $0\main_sdblock2mem_fifo_replace[0:0]
72754   attribute \src "ls180.v:5426.1-5433.4"
72755   wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0]
72756   attribute \src "ls180.v:5459.1-5498.4"
72757   wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0]
72758   attribute \src "ls180.v:5459.1-5498.4"
72759   wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0]
72760   attribute \src "ls180.v:5459.1-5498.4"
72761   wire $0\main_sdblock2mem_sink_sink_valid1[0:0]
72762   attribute \src "ls180.v:7431.1-10055.4"
72763   wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
72764   attribute \src "ls180.v:7431.1-10055.4"
72765   wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
72766   attribute \src "ls180.v:7431.1-10055.4"
72767   wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
72768   attribute \src "ls180.v:7431.1-10055.4"
72769   wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
72770   attribute \src "ls180.v:7431.1-10055.4"
72771   wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
72772   attribute \src "ls180.v:7431.1-10055.4"
72773   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
72774   attribute \src "ls180.v:7431.1-10055.4"
72775   wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
72776   attribute \src "ls180.v:7431.1-10055.4"
72777   wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
72778   attribute \src "ls180.v:7431.1-10055.4"
72779   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0]
72780   attribute \src "ls180.v:5459.1-5498.4"
72781   wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
72782   attribute \src "ls180.v:5459.1-5498.4"
72783   wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
72784   attribute \src "ls180.v:5459.1-5498.4"
72785   wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
72786   attribute \src "ls180.v:5459.1-5498.4"
72787   wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0]
72788   attribute \src "ls180.v:7431.1-10055.4"
72789   wire $0\main_sdcore_block_count_re[0:0]
72790   attribute \src "ls180.v:7431.1-10055.4"
72791   wire width 32 $0\main_sdcore_block_count_storage[31:0]
72792   attribute \src "ls180.v:7431.1-10055.4"
72793   wire $0\main_sdcore_block_length_re[0:0]
72794   attribute \src "ls180.v:7431.1-10055.4"
72795   wire width 10 $0\main_sdcore_block_length_storage[9:0]
72796   attribute \src "ls180.v:7431.1-10055.4"
72797   wire $0\main_sdcore_cmd_argument_re[0:0]
72798   attribute \src "ls180.v:7431.1-10055.4"
72799   wire width 32 $0\main_sdcore_cmd_argument_storage[31:0]
72800   attribute \src "ls180.v:7431.1-10055.4"
72801   wire $0\main_sdcore_cmd_command_re[0:0]
72802   attribute \src "ls180.v:7431.1-10055.4"
72803   wire width 32 $0\main_sdcore_cmd_command_storage[31:0]
72804   attribute \src "ls180.v:7431.1-10055.4"
72805   wire width 3 $0\main_sdcore_cmd_count[2:0]
72806   attribute \src "ls180.v:5208.1-5398.4"
72807   wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
72808   attribute \src "ls180.v:5208.1-5398.4"
72809   wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
72810   attribute \src "ls180.v:7431.1-10055.4"
72811   wire $0\main_sdcore_cmd_done[0:0]
72812   attribute \src "ls180.v:5208.1-5398.4"
72813   wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
72814   attribute \src "ls180.v:5208.1-5398.4"
72815   wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
72816   attribute \src "ls180.v:7431.1-10055.4"
72817   wire $0\main_sdcore_cmd_error[0:0]
72818   attribute \src "ls180.v:5208.1-5398.4"
72819   wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
72820   attribute \src "ls180.v:5208.1-5398.4"
72821   wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
72822   attribute \src "ls180.v:7431.1-10055.4"
72823   wire width 128 $0\main_sdcore_cmd_response_status[127:0]
72824   attribute \src "ls180.v:5208.1-5398.4"
72825   wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
72826   attribute \src "ls180.v:5208.1-5398.4"
72827   wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
72828   attribute \src "ls180.v:1391.5-1391.34"
72829   wire $0\main_sdcore_cmd_send_w[0:0]
72830   attribute \src "ls180.v:7431.1-10055.4"
72831   wire $0\main_sdcore_cmd_timeout[0:0]
72832   attribute \src "ls180.v:5208.1-5398.4"
72833   wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
72834   attribute \src "ls180.v:5208.1-5398.4"
72835   wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
72836   attribute \src "ls180.v:7431.1-10055.4"
72837   wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0]
72838   attribute \src "ls180.v:5114.1-5121.4"
72839   wire $0\main_sdcore_crc16_checker_crc0_clr[0:0]
72840   attribute \src "ls180.v:5170.1-5177.4"
72841   wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0]
72842   attribute \src "ls180.v:7431.1-10055.4"
72843   wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
72844   attribute \src "ls180.v:5124.1-5131.4"
72845   wire $0\main_sdcore_crc16_checker_crc1_clr[0:0]
72846   attribute \src "ls180.v:5180.1-5187.4"
72847   wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0]
72848   attribute \src "ls180.v:7431.1-10055.4"
72849   wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
72850   attribute \src "ls180.v:5134.1-5141.4"
72851   wire $0\main_sdcore_crc16_checker_crc2_clr[0:0]
72852   attribute \src "ls180.v:5190.1-5197.4"
72853   wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0]
72854   attribute \src "ls180.v:7431.1-10055.4"
72855   wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
72856   attribute \src "ls180.v:5144.1-5151.4"
72857   wire $0\main_sdcore_crc16_checker_crc3_clr[0:0]
72858   attribute \src "ls180.v:5200.1-5207.4"
72859   wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0]
72860   attribute \src "ls180.v:7431.1-10055.4"
72861   wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
72862   attribute \src "ls180.v:7431.1-10055.4"
72863   wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0]
72864   attribute \src "ls180.v:7431.1-10055.4"
72865   wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0]
72866   attribute \src "ls180.v:7431.1-10055.4"
72867   wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0]
72868   attribute \src "ls180.v:7431.1-10055.4"
72869   wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0]
72870   attribute \src "ls180.v:7431.1-10055.4"
72871   wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0]
72872   attribute \src "ls180.v:7431.1-10055.4"
72873   wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0]
72874   attribute \src "ls180.v:7431.1-10055.4"
72875   wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0]
72876   attribute \src "ls180.v:7431.1-10055.4"
72877   wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0]
72878   attribute \src "ls180.v:5208.1-5398.4"
72879   wire $0\main_sdcore_crc16_checker_sink_first[0:0]
72880   attribute \src "ls180.v:5208.1-5398.4"
72881   wire $0\main_sdcore_crc16_checker_sink_last[0:0]
72882   attribute \src "ls180.v:5208.1-5398.4"
72883   wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0]
72884   attribute \src "ls180.v:5159.1-5166.4"
72885   wire $0\main_sdcore_crc16_checker_sink_ready[0:0]
72886   attribute \src "ls180.v:5208.1-5398.4"
72887   wire $0\main_sdcore_crc16_checker_sink_valid[0:0]
72888   attribute \src "ls180.v:1497.5-1497.50"
72889   wire $0\main_sdcore_crc16_checker_source_first[0:0]
72890   attribute \src "ls180.v:5153.1-5158.4"
72891   wire $0\main_sdcore_crc16_checker_source_valid[0:0]
72892   attribute \src "ls180.v:7431.1-10055.4"
72893   wire width 8 $0\main_sdcore_crc16_checker_val[7:0]
72894   attribute \src "ls180.v:5106.1-5111.4"
72895   wire $0\main_sdcore_crc16_checker_valid[0:0]
72896   attribute \src "ls180.v:7431.1-10055.4"
72897   wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0]
72898   attribute \src "ls180.v:5026.1-5105.4"
72899   wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
72900   attribute \src "ls180.v:5026.1-5105.4"
72901   wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
72902   attribute \src "ls180.v:4988.1-4995.4"
72903   wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
72904   attribute \src "ls180.v:7431.1-10055.4"
72905   wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
72906   attribute \src "ls180.v:4998.1-5005.4"
72907   wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
72908   attribute \src "ls180.v:7431.1-10055.4"
72909   wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
72910   attribute \src "ls180.v:5008.1-5015.4"
72911   wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
72912   attribute \src "ls180.v:7431.1-10055.4"
72913   wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
72914   attribute \src "ls180.v:5018.1-5025.4"
72915   wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
72916   attribute \src "ls180.v:7431.1-10055.4"
72917   wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
72918   attribute \src "ls180.v:7431.1-10055.4"
72919   wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0]
72920   attribute \src "ls180.v:5026.1-5105.4"
72921   wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
72922   attribute \src "ls180.v:5026.1-5105.4"
72923   wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
72924   attribute \src "ls180.v:7431.1-10055.4"
72925   wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0]
72926   attribute \src "ls180.v:5026.1-5105.4"
72927   wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
72928   attribute \src "ls180.v:5026.1-5105.4"
72929   wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
72930   attribute \src "ls180.v:7431.1-10055.4"
72931   wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0]
72932   attribute \src "ls180.v:5026.1-5105.4"
72933   wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
72934   attribute \src "ls180.v:5026.1-5105.4"
72935   wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
72936   attribute \src "ls180.v:7431.1-10055.4"
72937   wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0]
72938   attribute \src "ls180.v:5026.1-5105.4"
72939   wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
72940   attribute \src "ls180.v:5026.1-5105.4"
72941   wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
72942   attribute \src "ls180.v:5026.1-5105.4"
72943   wire $0\main_sdcore_crc16_inserter_sink_ready[0:0]
72944   attribute \src "ls180.v:1454.5-1454.51"
72945   wire $0\main_sdcore_crc16_inserter_source_first[0:0]
72946   attribute \src "ls180.v:5026.1-5105.4"
72947   wire $0\main_sdcore_crc16_inserter_source_last[0:0]
72948   attribute \src "ls180.v:5026.1-5105.4"
72949   wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0]
72950   attribute \src "ls180.v:5208.1-5398.4"
72951   wire $0\main_sdcore_crc16_inserter_source_ready[0:0]
72952   attribute \src "ls180.v:5026.1-5105.4"
72953   wire $0\main_sdcore_crc16_inserter_source_valid[0:0]
72954   attribute \src "ls180.v:4966.1-4973.4"
72955   wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0]
72956   attribute \src "ls180.v:7431.1-10055.4"
72957   wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0]
72958   attribute \src "ls180.v:7431.1-10055.4"
72959   wire width 32 $0\main_sdcore_data_count[31:0]
72960   attribute \src "ls180.v:5208.1-5398.4"
72961   wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
72962   attribute \src "ls180.v:5208.1-5398.4"
72963   wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
72964   attribute \src "ls180.v:7431.1-10055.4"
72965   wire $0\main_sdcore_data_done[0:0]
72966   attribute \src "ls180.v:5208.1-5398.4"
72967   wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
72968   attribute \src "ls180.v:5208.1-5398.4"
72969   wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
72970   attribute \src "ls180.v:7431.1-10055.4"
72971   wire $0\main_sdcore_data_error[0:0]
72972   attribute \src "ls180.v:5208.1-5398.4"
72973   wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
72974   attribute \src "ls180.v:5208.1-5398.4"
72975   wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
72976   attribute \src "ls180.v:7431.1-10055.4"
72977   wire $0\main_sdcore_data_timeout[0:0]
72978   attribute \src "ls180.v:5208.1-5398.4"
72979   wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
72980   attribute \src "ls180.v:5208.1-5398.4"
72981   wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
72982   attribute \src "ls180.v:7431.1-10055.4"
72983   wire width 2 $0\main_sdmem2block_converter_mux[1:0]
72984   attribute \src "ls180.v:5604.1-5620.4"
72985   wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0]
72986   attribute \src "ls180.v:7431.1-10055.4"
72987   wire $0\main_sdmem2block_dma_base_re[0:0]
72988   attribute \src "ls180.v:7431.1-10055.4"
72989   wire width 64 $0\main_sdmem2block_dma_base_storage[63:0]
72990   attribute \src "ls180.v:7431.1-10055.4"
72991   wire width 32 $0\main_sdmem2block_dma_data[31:0]
72992   attribute \src "ls180.v:5518.1-5555.4"
72993   wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
72994   attribute \src "ls180.v:5518.1-5555.4"
72995   wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
72996   attribute \src "ls180.v:5556.1-5592.4"
72997   wire $0\main_sdmem2block_dma_done_status[0:0]
72998   attribute \src "ls180.v:7431.1-10055.4"
72999   wire $0\main_sdmem2block_dma_enable_re[0:0]
73000   attribute \src "ls180.v:7431.1-10055.4"
73001   wire $0\main_sdmem2block_dma_enable_storage[0:0]
73002   attribute \src "ls180.v:7431.1-10055.4"
73003   wire $0\main_sdmem2block_dma_length_re[0:0]
73004   attribute \src "ls180.v:7431.1-10055.4"
73005   wire width 32 $0\main_sdmem2block_dma_length_storage[31:0]
73006   attribute \src "ls180.v:7431.1-10055.4"
73007   wire $0\main_sdmem2block_dma_loop_re[0:0]
73008   attribute \src "ls180.v:7431.1-10055.4"
73009   wire $0\main_sdmem2block_dma_loop_storage[0:0]
73010   attribute \src "ls180.v:7431.1-10055.4"
73011   wire width 32 $0\main_sdmem2block_dma_offset[31:0]
73012   attribute \src "ls180.v:5556.1-5592.4"
73013   wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
73014   attribute \src "ls180.v:5556.1-5592.4"
73015   wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
73016   attribute \src "ls180.v:5556.1-5592.4"
73017   wire $0\main_sdmem2block_dma_sink_last[0:0]
73018   attribute \src "ls180.v:5556.1-5592.4"
73019   wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0]
73020   attribute \src "ls180.v:5518.1-5555.4"
73021   wire $0\main_sdmem2block_dma_sink_ready[0:0]
73022   attribute \src "ls180.v:5556.1-5592.4"
73023   wire $0\main_sdmem2block_dma_sink_valid[0:0]
73024   attribute \src "ls180.v:1662.5-1662.45"
73025   wire $0\main_sdmem2block_dma_source_first[0:0]
73026   attribute \src "ls180.v:5518.1-5555.4"
73027   wire $0\main_sdmem2block_dma_source_last[0:0]
73028   attribute \src "ls180.v:5518.1-5555.4"
73029   wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0]
73030   attribute \src "ls180.v:5518.1-5555.4"
73031   wire $0\main_sdmem2block_dma_source_valid[0:0]
73032   attribute \src "ls180.v:7431.1-10055.4"
73033   wire width 5 $0\main_sdmem2block_fifo_consume[4:0]
73034   attribute \src "ls180.v:7431.1-10055.4"
73035   wire width 6 $0\main_sdmem2block_fifo_level[5:0]
73036   attribute \src "ls180.v:7431.1-10055.4"
73037   wire width 5 $0\main_sdmem2block_fifo_produce[4:0]
73038   attribute \src "ls180.v:1718.5-1718.41"
73039   wire $0\main_sdmem2block_fifo_replace[0:0]
73040   attribute \src "ls180.v:5634.1-5641.4"
73041   wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0]
73042   attribute \src "ls180.v:7431.1-10055.4"
73043   wire $0\main_sdphy_clocker_clk0[0:0]
73044   attribute \src "ls180.v:4372.1-4400.4"
73045   wire $0\main_sdphy_clocker_clk1[0:0]
73046   attribute \src "ls180.v:7431.1-10055.4"
73047   wire $0\main_sdphy_clocker_clk_d[0:0]
73048   attribute \src "ls180.v:7431.1-10055.4"
73049   wire width 9 $0\main_sdphy_clocker_clks[8:0]
73050   attribute \src "ls180.v:7431.1-10055.4"
73051   wire $0\main_sdphy_clocker_re[0:0]
73052   attribute \src "ls180.v:7431.1-10055.4"
73053   wire width 9 $0\main_sdphy_clocker_storage[8:0]
73054   attribute \src "ls180.v:7431.1-10055.4"
73055   wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
73056   attribute \src "ls180.v:7431.1-10055.4"
73057   wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
73058   attribute \src "ls180.v:7431.1-10055.4"
73059   wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
73060   attribute \src "ls180.v:7431.1-10055.4"
73061   wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
73062   attribute \src "ls180.v:7431.1-10055.4"
73063   wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0]
73064   attribute \src "ls180.v:1183.5-1183.53"
73065   wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
73066   attribute \src "ls180.v:1184.5-1184.52"
73067   wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
73068   attribute \src "ls180.v:7431.1-10055.4"
73069   wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
73070   attribute \src "ls180.v:7431.1-10055.4"
73071   wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
73072   attribute \src "ls180.v:7431.1-10055.4"
73073   wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
73074   attribute \src "ls180.v:7431.1-10055.4"
73075   wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
73076   attribute \src "ls180.v:7431.1-10055.4"
73077   wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
73078   attribute \src "ls180.v:1164.5-1164.46"
73079   wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
73080   attribute \src "ls180.v:7431.1-10055.4"
73081   wire $0\main_sdphy_cmdr_cmdr_reset[0:0]
73082   attribute \src "ls180.v:4546.1-4639.4"
73083   wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
73084   attribute \src "ls180.v:4546.1-4639.4"
73085   wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
73086   attribute \src "ls180.v:7431.1-10055.4"
73087   wire $0\main_sdphy_cmdr_cmdr_run[0:0]
73088   attribute \src "ls180.v:4546.1-4639.4"
73089   wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
73090   attribute \src "ls180.v:7431.1-10055.4"
73091   wire width 8 $0\main_sdphy_cmdr_count[7:0]
73092   attribute \src "ls180.v:4546.1-4639.4"
73093   wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
73094   attribute \src "ls180.v:4546.1-4639.4"
73095   wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
73096   attribute \src "ls180.v:1137.5-1137.49"
73097   wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
73098   attribute \src "ls180.v:1138.5-1138.48"
73099   wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
73100   attribute \src "ls180.v:1139.5-1139.55"
73101   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
73102   attribute \src "ls180.v:1141.5-1141.57"
73103   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
73104   attribute \src "ls180.v:1142.5-1142.58"
73105   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
73106   attribute \src "ls180.v:1144.11-1144.64"
73107   wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
73108   attribute \src "ls180.v:1145.5-1145.59"
73109   wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
73110   attribute \src "ls180.v:4546.1-4639.4"
73111   wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0]
73112   attribute \src "ls180.v:4546.1-4639.4"
73113   wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
73114   attribute \src "ls180.v:4546.1-4639.4"
73115   wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
73116   attribute \src "ls180.v:1150.11-1150.57"
73117   wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
73118   attribute \src "ls180.v:1151.5-1151.52"
73119   wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
73120   attribute \src "ls180.v:5208.1-5398.4"
73121   wire $0\main_sdphy_cmdr_sink_last[0:0]
73122   attribute \src "ls180.v:5208.1-5398.4"
73123   wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0]
73124   attribute \src "ls180.v:4546.1-4639.4"
73125   wire $0\main_sdphy_cmdr_sink_ready[0:0]
73126   attribute \src "ls180.v:5208.1-5398.4"
73127   wire $0\main_sdphy_cmdr_sink_valid[0:0]
73128   attribute \src "ls180.v:4546.1-4639.4"
73129   wire $0\main_sdphy_cmdr_source_last[0:0]
73130   attribute \src "ls180.v:4546.1-4639.4"
73131   wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0]
73132   attribute \src "ls180.v:4546.1-4639.4"
73133   wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0]
73134   attribute \src "ls180.v:5208.1-5398.4"
73135   wire $0\main_sdphy_cmdr_source_ready[0:0]
73136   attribute \src "ls180.v:4546.1-4639.4"
73137   wire $0\main_sdphy_cmdr_source_valid[0:0]
73138   attribute \src "ls180.v:7431.1-10055.4"
73139   wire width 32 $0\main_sdphy_cmdr_timeout[31:0]
73140   attribute \src "ls180.v:4546.1-4639.4"
73141   wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
73142   attribute \src "ls180.v:4546.1-4639.4"
73143   wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
73144   attribute \src "ls180.v:7431.1-10055.4"
73145   wire width 8 $0\main_sdphy_cmdw_count[7:0]
73146   attribute \src "ls180.v:4436.1-4512.4"
73147   wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
73148   attribute \src "ls180.v:4436.1-4512.4"
73149   wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
73150   attribute \src "ls180.v:4436.1-4512.4"
73151   wire $0\main_sdphy_cmdw_done[0:0]
73152   attribute \src "ls180.v:4436.1-4512.4"
73153   wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0]
73154   attribute \src "ls180.v:4436.1-4512.4"
73155   wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
73156   attribute \src "ls180.v:4436.1-4512.4"
73157   wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
73158   attribute \src "ls180.v:1127.11-1127.57"
73159   wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
73160   attribute \src "ls180.v:1128.5-1128.52"
73161   wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
73162   attribute \src "ls180.v:5208.1-5398.4"
73163   wire $0\main_sdphy_cmdw_sink_last[0:0]
73164   attribute \src "ls180.v:5208.1-5398.4"
73165   wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0]
73166   attribute \src "ls180.v:4436.1-4512.4"
73167   wire $0\main_sdphy_cmdw_sink_ready[0:0]
73168   attribute \src "ls180.v:5208.1-5398.4"
73169   wire $0\main_sdphy_cmdw_sink_valid[0:0]
73170   attribute \src "ls180.v:7431.1-10055.4"
73171   wire width 10 $0\main_sdphy_datar_count[9:0]
73172   attribute \src "ls180.v:4807.1-4908.4"
73173   wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
73174   attribute \src "ls180.v:4807.1-4908.4"
73175   wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
73176   attribute \src "ls180.v:7431.1-10055.4"
73177   wire $0\main_sdphy_datar_datar_buf_source_first[0:0]
73178   attribute \src "ls180.v:7431.1-10055.4"
73179   wire $0\main_sdphy_datar_datar_buf_source_last[0:0]
73180   attribute \src "ls180.v:7431.1-10055.4"
73181   wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0]
73182   attribute \src "ls180.v:7431.1-10055.4"
73183   wire $0\main_sdphy_datar_datar_buf_source_valid[0:0]
73184   attribute \src "ls180.v:7431.1-10055.4"
73185   wire $0\main_sdphy_datar_datar_converter_demux[0:0]
73186   attribute \src "ls180.v:1339.5-1339.55"
73187   wire $0\main_sdphy_datar_datar_converter_sink_first[0:0]
73188   attribute \src "ls180.v:1340.5-1340.54"
73189   wire $0\main_sdphy_datar_datar_converter_sink_last[0:0]
73190   attribute \src "ls180.v:7431.1-10055.4"
73191   wire $0\main_sdphy_datar_datar_converter_source_first[0:0]
73192   attribute \src "ls180.v:7431.1-10055.4"
73193   wire $0\main_sdphy_datar_datar_converter_source_last[0:0]
73194   attribute \src "ls180.v:7431.1-10055.4"
73195   wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0]
73196   attribute \src "ls180.v:7431.1-10055.4"
73197   wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
73198   attribute \src "ls180.v:7431.1-10055.4"
73199   wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0]
73200   attribute \src "ls180.v:1320.5-1320.48"
73201   wire $0\main_sdphy_datar_datar_pads_in_ready[0:0]
73202   attribute \src "ls180.v:7431.1-10055.4"
73203   wire $0\main_sdphy_datar_datar_reset[0:0]
73204   attribute \src "ls180.v:4807.1-4908.4"
73205   wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
73206   attribute \src "ls180.v:4807.1-4908.4"
73207   wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
73208   attribute \src "ls180.v:7431.1-10055.4"
73209   wire $0\main_sdphy_datar_datar_run[0:0]
73210   attribute \src "ls180.v:4807.1-4908.4"
73211   wire $0\main_sdphy_datar_datar_source_source_ready0[0:0]
73212   attribute \src "ls180.v:1291.5-1291.50"
73213   wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
73214   attribute \src "ls180.v:1292.5-1292.49"
73215   wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
73216   attribute \src "ls180.v:1293.5-1293.56"
73217   wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
73218   attribute \src "ls180.v:1295.5-1295.58"
73219   wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
73220   attribute \src "ls180.v:1296.5-1296.59"
73221   wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
73222   attribute \src "ls180.v:1298.11-1298.65"
73223   wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
73224   attribute \src "ls180.v:1299.5-1299.60"
73225   wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
73226   attribute \src "ls180.v:4807.1-4908.4"
73227   wire $0\main_sdphy_datar_pads_out_payload_clk[0:0]
73228   attribute \src "ls180.v:1302.5-1302.51"
73229   wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
73230   attribute \src "ls180.v:1303.5-1303.52"
73231   wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
73232   attribute \src "ls180.v:1304.11-1304.58"
73233   wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
73234   attribute \src "ls180.v:1305.5-1305.53"
73235   wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
73236   attribute \src "ls180.v:5208.1-5398.4"
73237   wire $0\main_sdphy_datar_sink_last[0:0]
73238   attribute \src "ls180.v:5208.1-5398.4"
73239   wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0]
73240   attribute \src "ls180.v:4807.1-4908.4"
73241   wire $0\main_sdphy_datar_sink_ready[0:0]
73242   attribute \src "ls180.v:5208.1-5398.4"
73243   wire $0\main_sdphy_datar_sink_valid[0:0]
73244   attribute \src "ls180.v:1312.5-1312.41"
73245   wire $0\main_sdphy_datar_source_first[0:0]
73246   attribute \src "ls180.v:4807.1-4908.4"
73247   wire $0\main_sdphy_datar_source_last[0:0]
73248   attribute \src "ls180.v:4807.1-4908.4"
73249   wire width 8 $0\main_sdphy_datar_source_payload_data[7:0]
73250   attribute \src "ls180.v:4807.1-4908.4"
73251   wire width 3 $0\main_sdphy_datar_source_payload_status[2:0]
73252   attribute \src "ls180.v:5208.1-5398.4"
73253   wire $0\main_sdphy_datar_source_ready[0:0]
73254   attribute \src "ls180.v:4807.1-4908.4"
73255   wire $0\main_sdphy_datar_source_valid[0:0]
73256   attribute \src "ls180.v:4807.1-4908.4"
73257   wire $0\main_sdphy_datar_stop[0:0]
73258   attribute \src "ls180.v:7431.1-10055.4"
73259   wire width 32 $0\main_sdphy_datar_timeout[31:0]
73260   attribute \src "ls180.v:4807.1-4908.4"
73261   wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
73262   attribute \src "ls180.v:4807.1-4908.4"
73263   wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
73264   attribute \src "ls180.v:7431.1-10055.4"
73265   wire width 8 $0\main_sdphy_dataw_count[7:0]
73266   attribute \src "ls180.v:4701.1-4773.4"
73267   wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
73268   attribute \src "ls180.v:4701.1-4773.4"
73269   wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
73270   attribute \src "ls180.v:7431.1-10055.4"
73271   wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0]
73272   attribute \src "ls180.v:7431.1-10055.4"
73273   wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0]
73274   attribute \src "ls180.v:7431.1-10055.4"
73275   wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
73276   attribute \src "ls180.v:7431.1-10055.4"
73277   wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0]
73278   attribute \src "ls180.v:7431.1-10055.4"
73279   wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0]
73280   attribute \src "ls180.v:1261.5-1261.54"
73281   wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
73282   attribute \src "ls180.v:1262.5-1262.53"
73283   wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
73284   attribute \src "ls180.v:7431.1-10055.4"
73285   wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0]
73286   attribute \src "ls180.v:7431.1-10055.4"
73287   wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0]
73288   attribute \src "ls180.v:7431.1-10055.4"
73289   wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
73290   attribute \src "ls180.v:7431.1-10055.4"
73291   wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
73292   attribute \src "ls180.v:7431.1-10055.4"
73293   wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
73294   attribute \src "ls180.v:1242.5-1242.47"
73295   wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
73296   attribute \src "ls180.v:7431.1-10055.4"
73297   wire $0\main_sdphy_dataw_crcr_reset[0:0]
73298   attribute \src "ls180.v:4673.1-4700.4"
73299   wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
73300   attribute \src "ls180.v:4673.1-4700.4"
73301   wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
73302   attribute \src "ls180.v:7431.1-10055.4"
73303   wire $0\main_sdphy_dataw_crcr_run[0:0]
73304   attribute \src "ls180.v:4673.1-4700.4"
73305   wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0]
73306   attribute \src "ls180.v:4673.1-4700.4"
73307   wire $0\main_sdphy_dataw_error[0:0]
73308   attribute \src "ls180.v:1229.5-1229.50"
73309   wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
73310   attribute \src "ls180.v:1230.5-1230.49"
73311   wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
73312   attribute \src "ls180.v:1231.5-1231.56"
73313   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
73314   attribute \src "ls180.v:1232.5-1232.58"
73315   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
73316   attribute \src "ls180.v:1233.5-1233.58"
73317   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
73318   attribute \src "ls180.v:1234.5-1234.59"
73319   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
73320   attribute \src "ls180.v:1235.11-1235.65"
73321   wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
73322   attribute \src "ls180.v:1236.11-1236.65"
73323   wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
73324   attribute \src "ls180.v:1237.5-1237.60"
73325   wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
73326   attribute \src "ls180.v:1227.5-1227.50"
73327   wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
73328   attribute \src "ls180.v:4701.1-4773.4"
73329   wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0]
73330   attribute \src "ls180.v:1216.5-1216.51"
73331   wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
73332   attribute \src "ls180.v:1217.5-1217.52"
73333   wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
73334   attribute \src "ls180.v:4701.1-4773.4"
73335   wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0]
73336   attribute \src "ls180.v:4701.1-4773.4"
73337   wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
73338   attribute \src "ls180.v:5208.1-5398.4"
73339   wire $0\main_sdphy_dataw_sink_first[0:0]
73340   attribute \src "ls180.v:5208.1-5398.4"
73341   wire $0\main_sdphy_dataw_sink_last[0:0]
73342   attribute \src "ls180.v:5208.1-5398.4"
73343   wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0]
73344   attribute \src "ls180.v:4701.1-4773.4"
73345   wire $0\main_sdphy_dataw_sink_ready[0:0]
73346   attribute \src "ls180.v:5208.1-5398.4"
73347   wire $0\main_sdphy_dataw_sink_valid[0:0]
73348   attribute \src "ls180.v:4701.1-4773.4"
73349   wire $0\main_sdphy_dataw_start[0:0]
73350   attribute \src "ls180.v:4701.1-4773.4"
73351   wire $0\main_sdphy_dataw_stop[0:0]
73352   attribute \src "ls180.v:4673.1-4700.4"
73353   wire $0\main_sdphy_dataw_valid[0:0]
73354   attribute \src "ls180.v:7431.1-10055.4"
73355   wire width 8 $0\main_sdphy_init_count[7:0]
73356   attribute \src "ls180.v:4402.1-4435.4"
73357   wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
73358   attribute \src "ls180.v:4402.1-4435.4"
73359   wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
73360   attribute \src "ls180.v:1109.5-1109.40"
73361   wire $0\main_sdphy_init_initialize_w[0:0]
73362   attribute \src "ls180.v:4402.1-4435.4"
73363   wire $0\main_sdphy_init_pads_out_payload_clk[0:0]
73364   attribute \src "ls180.v:4402.1-4435.4"
73365   wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0]
73366   attribute \src "ls180.v:4402.1-4435.4"
73367   wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
73368   attribute \src "ls180.v:4402.1-4435.4"
73369   wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0]
73370   attribute \src "ls180.v:4402.1-4435.4"
73371   wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0]
73372   attribute \src "ls180.v:7359.1-7429.4"
73373   wire $0\main_sdphy_sdpads_cmd_i[0:0]
73374   attribute \src "ls180.v:7359.1-7429.4"
73375   wire width 4 $0\main_sdphy_sdpads_data_i[3:0]
73376   attribute \src "ls180.v:7431.1-10055.4"
73377   wire $0\main_sdram_address_re[0:0]
73378   attribute \src "ls180.v:7431.1-10055.4"
73379   wire width 13 $0\main_sdram_address_storage[12:0]
73380   attribute \src "ls180.v:7431.1-10055.4"
73381   wire $0\main_sdram_baddress_re[0:0]
73382   attribute \src "ls180.v:7431.1-10055.4"
73383   wire width 2 $0\main_sdram_baddress_storage[1:0]
73384   attribute \src "ls180.v:3188.1-3195.4"
73385   wire $0\main_sdram_bankmachine0_auto_precharge[0:0]
73386   attribute \src "ls180.v:7431.1-10055.4"
73387   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
73388   attribute \src "ls180.v:7431.1-10055.4"
73389   wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
73390   attribute \src "ls180.v:7431.1-10055.4"
73391   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
73392   attribute \src "ls180.v:449.5-449.64"
73393   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
73394   attribute \src "ls180.v:432.5-432.67"
73395   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
73396   attribute \src "ls180.v:433.5-433.66"
73397   wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
73398   attribute \src "ls180.v:3210.1-3217.4"
73399   wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
73400   attribute \src "ls180.v:7431.1-10055.4"
73401   wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
73402   attribute \src "ls180.v:7431.1-10055.4"
73403   wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
73404   attribute \src "ls180.v:7431.1-10055.4"
73405   wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
73406   attribute \src "ls180.v:7431.1-10055.4"
73407   wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
73408   attribute \src "ls180.v:7431.1-10055.4"
73409   wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
73410   attribute \src "ls180.v:3177.1-3184.4"
73411   wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
73412   attribute \src "ls180.v:3226.1-3319.4"
73413   wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0]
73414   attribute \src "ls180.v:3226.1-3319.4"
73415   wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
73416   attribute \src "ls180.v:3226.1-3319.4"
73417   wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
73418   attribute \src "ls180.v:3226.1-3319.4"
73419   wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
73420   attribute \src "ls180.v:3226.1-3319.4"
73421   wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0]
73422   attribute \src "ls180.v:3226.1-3319.4"
73423   wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0]
73424   attribute \src "ls180.v:3875.1-3883.4"
73425   wire $0\main_sdram_bankmachine0_cmd_ready[0:0]
73426   attribute \src "ls180.v:3226.1-3319.4"
73427   wire $0\main_sdram_bankmachine0_cmd_valid[0:0]
73428   attribute \src "ls180.v:3226.1-3319.4"
73429   wire $0\main_sdram_bankmachine0_refresh_gnt[0:0]
73430   attribute \src "ls180.v:3226.1-3319.4"
73431   wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0]
73432   attribute \src "ls180.v:3226.1-3319.4"
73433   wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0]
73434   attribute \src "ls180.v:7431.1-10055.4"
73435   wire width 13 $0\main_sdram_bankmachine0_row[12:0]
73436   attribute \src "ls180.v:3226.1-3319.4"
73437   wire $0\main_sdram_bankmachine0_row_close[0:0]
73438   attribute \src "ls180.v:3226.1-3319.4"
73439   wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
73440   attribute \src "ls180.v:3226.1-3319.4"
73441   wire $0\main_sdram_bankmachine0_row_open[0:0]
73442   attribute \src "ls180.v:7431.1-10055.4"
73443   wire $0\main_sdram_bankmachine0_row_opened[0:0]
73444   attribute \src "ls180.v:491.32-491.76"
73445   wire $0\main_sdram_bankmachine0_trascon_ready[0:0]
73446   attribute \src "ls180.v:489.32-489.75"
73447   wire $0\main_sdram_bankmachine0_trccon_ready[0:0]
73448   attribute \src "ls180.v:7431.1-10055.4"
73449   wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0]
73450   attribute \src "ls180.v:7431.1-10055.4"
73451   wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0]
73452   attribute \src "ls180.v:3345.1-3352.4"
73453   wire $0\main_sdram_bankmachine1_auto_precharge[0:0]
73454   attribute \src "ls180.v:7431.1-10055.4"
73455   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
73456   attribute \src "ls180.v:7431.1-10055.4"
73457   wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
73458   attribute \src "ls180.v:7431.1-10055.4"
73459   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
73460   attribute \src "ls180.v:531.5-531.64"
73461   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
73462   attribute \src "ls180.v:514.5-514.67"
73463   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
73464   attribute \src "ls180.v:515.5-515.66"
73465   wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
73466   attribute \src "ls180.v:3367.1-3374.4"
73467   wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
73468   attribute \src "ls180.v:7431.1-10055.4"
73469   wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
73470   attribute \src "ls180.v:7431.1-10055.4"
73471   wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
73472   attribute \src "ls180.v:7431.1-10055.4"
73473   wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
73474   attribute \src "ls180.v:7431.1-10055.4"
73475   wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
73476   attribute \src "ls180.v:7431.1-10055.4"
73477   wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
73478   attribute \src "ls180.v:3334.1-3341.4"
73479   wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
73480   attribute \src "ls180.v:3383.1-3476.4"
73481   wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0]
73482   attribute \src "ls180.v:3383.1-3476.4"
73483   wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
73484   attribute \src "ls180.v:3383.1-3476.4"
73485   wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
73486   attribute \src "ls180.v:3383.1-3476.4"
73487   wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
73488   attribute \src "ls180.v:3383.1-3476.4"
73489   wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0]
73490   attribute \src "ls180.v:3383.1-3476.4"
73491   wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0]
73492   attribute \src "ls180.v:3884.1-3892.4"
73493   wire $0\main_sdram_bankmachine1_cmd_ready[0:0]
73494   attribute \src "ls180.v:3383.1-3476.4"
73495   wire $0\main_sdram_bankmachine1_cmd_valid[0:0]
73496   attribute \src "ls180.v:3383.1-3476.4"
73497   wire $0\main_sdram_bankmachine1_refresh_gnt[0:0]
73498   attribute \src "ls180.v:3383.1-3476.4"
73499   wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0]
73500   attribute \src "ls180.v:3383.1-3476.4"
73501   wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0]
73502   attribute \src "ls180.v:7431.1-10055.4"
73503   wire width 13 $0\main_sdram_bankmachine1_row[12:0]
73504   attribute \src "ls180.v:3383.1-3476.4"
73505   wire $0\main_sdram_bankmachine1_row_close[0:0]
73506   attribute \src "ls180.v:3383.1-3476.4"
73507   wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
73508   attribute \src "ls180.v:3383.1-3476.4"
73509   wire $0\main_sdram_bankmachine1_row_open[0:0]
73510   attribute \src "ls180.v:7431.1-10055.4"
73511   wire $0\main_sdram_bankmachine1_row_opened[0:0]
73512   attribute \src "ls180.v:573.32-573.76"
73513   wire $0\main_sdram_bankmachine1_trascon_ready[0:0]
73514   attribute \src "ls180.v:571.32-571.75"
73515   wire $0\main_sdram_bankmachine1_trccon_ready[0:0]
73516   attribute \src "ls180.v:7431.1-10055.4"
73517   wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0]
73518   attribute \src "ls180.v:7431.1-10055.4"
73519   wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0]
73520   attribute \src "ls180.v:3502.1-3509.4"
73521   wire $0\main_sdram_bankmachine2_auto_precharge[0:0]
73522   attribute \src "ls180.v:7431.1-10055.4"
73523   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
73524   attribute \src "ls180.v:7431.1-10055.4"
73525   wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
73526   attribute \src "ls180.v:7431.1-10055.4"
73527   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
73528   attribute \src "ls180.v:613.5-613.64"
73529   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
73530   attribute \src "ls180.v:596.5-596.67"
73531   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
73532   attribute \src "ls180.v:597.5-597.66"
73533   wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
73534   attribute \src "ls180.v:3524.1-3531.4"
73535   wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
73536   attribute \src "ls180.v:7431.1-10055.4"
73537   wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
73538   attribute \src "ls180.v:7431.1-10055.4"
73539   wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
73540   attribute \src "ls180.v:7431.1-10055.4"
73541   wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
73542   attribute \src "ls180.v:7431.1-10055.4"
73543   wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
73544   attribute \src "ls180.v:7431.1-10055.4"
73545   wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
73546   attribute \src "ls180.v:3491.1-3498.4"
73547   wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
73548   attribute \src "ls180.v:3540.1-3633.4"
73549   wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0]
73550   attribute \src "ls180.v:3540.1-3633.4"
73551   wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
73552   attribute \src "ls180.v:3540.1-3633.4"
73553   wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
73554   attribute \src "ls180.v:3540.1-3633.4"
73555   wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
73556   attribute \src "ls180.v:3540.1-3633.4"
73557   wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0]
73558   attribute \src "ls180.v:3540.1-3633.4"
73559   wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0]
73560   attribute \src "ls180.v:3893.1-3901.4"
73561   wire $0\main_sdram_bankmachine2_cmd_ready[0:0]
73562   attribute \src "ls180.v:3540.1-3633.4"
73563   wire $0\main_sdram_bankmachine2_cmd_valid[0:0]
73564   attribute \src "ls180.v:3540.1-3633.4"
73565   wire $0\main_sdram_bankmachine2_refresh_gnt[0:0]
73566   attribute \src "ls180.v:3540.1-3633.4"
73567   wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0]
73568   attribute \src "ls180.v:3540.1-3633.4"
73569   wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0]
73570   attribute \src "ls180.v:7431.1-10055.4"
73571   wire width 13 $0\main_sdram_bankmachine2_row[12:0]
73572   attribute \src "ls180.v:3540.1-3633.4"
73573   wire $0\main_sdram_bankmachine2_row_close[0:0]
73574   attribute \src "ls180.v:3540.1-3633.4"
73575   wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
73576   attribute \src "ls180.v:3540.1-3633.4"
73577   wire $0\main_sdram_bankmachine2_row_open[0:0]
73578   attribute \src "ls180.v:7431.1-10055.4"
73579   wire $0\main_sdram_bankmachine2_row_opened[0:0]
73580   attribute \src "ls180.v:655.32-655.76"
73581   wire $0\main_sdram_bankmachine2_trascon_ready[0:0]
73582   attribute \src "ls180.v:653.32-653.75"
73583   wire $0\main_sdram_bankmachine2_trccon_ready[0:0]
73584   attribute \src "ls180.v:7431.1-10055.4"
73585   wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0]
73586   attribute \src "ls180.v:7431.1-10055.4"
73587   wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0]
73588   attribute \src "ls180.v:3659.1-3666.4"
73589   wire $0\main_sdram_bankmachine3_auto_precharge[0:0]
73590   attribute \src "ls180.v:7431.1-10055.4"
73591   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
73592   attribute \src "ls180.v:7431.1-10055.4"
73593   wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
73594   attribute \src "ls180.v:7431.1-10055.4"
73595   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
73596   attribute \src "ls180.v:695.5-695.64"
73597   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
73598   attribute \src "ls180.v:678.5-678.67"
73599   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
73600   attribute \src "ls180.v:679.5-679.66"
73601   wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
73602   attribute \src "ls180.v:3681.1-3688.4"
73603   wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
73604   attribute \src "ls180.v:7431.1-10055.4"
73605   wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
73606   attribute \src "ls180.v:7431.1-10055.4"
73607   wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
73608   attribute \src "ls180.v:7431.1-10055.4"
73609   wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
73610   attribute \src "ls180.v:7431.1-10055.4"
73611   wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
73612   attribute \src "ls180.v:7431.1-10055.4"
73613   wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
73614   attribute \src "ls180.v:3648.1-3655.4"
73615   wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
73616   attribute \src "ls180.v:3697.1-3790.4"
73617   wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0]
73618   attribute \src "ls180.v:3697.1-3790.4"
73619   wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
73620   attribute \src "ls180.v:3697.1-3790.4"
73621   wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
73622   attribute \src "ls180.v:3697.1-3790.4"
73623   wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
73624   attribute \src "ls180.v:3697.1-3790.4"
73625   wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0]
73626   attribute \src "ls180.v:3697.1-3790.4"
73627   wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0]
73628   attribute \src "ls180.v:3902.1-3910.4"
73629   wire $0\main_sdram_bankmachine3_cmd_ready[0:0]
73630   attribute \src "ls180.v:3697.1-3790.4"
73631   wire $0\main_sdram_bankmachine3_cmd_valid[0:0]
73632   attribute \src "ls180.v:3697.1-3790.4"
73633   wire $0\main_sdram_bankmachine3_refresh_gnt[0:0]
73634   attribute \src "ls180.v:3697.1-3790.4"
73635   wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0]
73636   attribute \src "ls180.v:3697.1-3790.4"
73637   wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0]
73638   attribute \src "ls180.v:7431.1-10055.4"
73639   wire width 13 $0\main_sdram_bankmachine3_row[12:0]
73640   attribute \src "ls180.v:3697.1-3790.4"
73641   wire $0\main_sdram_bankmachine3_row_close[0:0]
73642   attribute \src "ls180.v:3697.1-3790.4"
73643   wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
73644   attribute \src "ls180.v:3697.1-3790.4"
73645   wire $0\main_sdram_bankmachine3_row_open[0:0]
73646   attribute \src "ls180.v:7431.1-10055.4"
73647   wire $0\main_sdram_bankmachine3_row_opened[0:0]
73648   attribute \src "ls180.v:737.32-737.76"
73649   wire $0\main_sdram_bankmachine3_trascon_ready[0:0]
73650   attribute \src "ls180.v:735.32-735.75"
73651   wire $0\main_sdram_bankmachine3_trccon_ready[0:0]
73652   attribute \src "ls180.v:7431.1-10055.4"
73653   wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0]
73654   attribute \src "ls180.v:7431.1-10055.4"
73655   wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0]
73656   attribute \src "ls180.v:3824.1-3829.4"
73657   wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
73658   attribute \src "ls180.v:3830.1-3835.4"
73659   wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
73660   attribute \src "ls180.v:3836.1-3841.4"
73661   wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
73662   attribute \src "ls180.v:745.5-745.43"
73663   wire $0\main_sdram_choose_cmd_cmd_ready[0:0]
73664   attribute \src "ls180.v:7431.1-10055.4"
73665   wire width 2 $0\main_sdram_choose_cmd_grant[1:0]
73666   attribute \src "ls180.v:3810.1-3816.4"
73667   wire width 4 $0\main_sdram_choose_cmd_valids[3:0]
73668   attribute \src "ls180.v:743.5-743.48"
73669   wire $0\main_sdram_choose_cmd_want_activates[0:0]
73670   attribute \src "ls180.v:742.5-742.43"
73671   wire $0\main_sdram_choose_cmd_want_cmds[0:0]
73672   attribute \src "ls180.v:740.5-740.44"
73673   wire $0\main_sdram_choose_cmd_want_reads[0:0]
73674   attribute \src "ls180.v:741.5-741.45"
73675   wire $0\main_sdram_choose_cmd_want_writes[0:0]
73676   attribute \src "ls180.v:3857.1-3862.4"
73677   wire $0\main_sdram_choose_req_cmd_payload_cas[0:0]
73678   attribute \src "ls180.v:3863.1-3868.4"
73679   wire $0\main_sdram_choose_req_cmd_payload_ras[0:0]
73680   attribute \src "ls180.v:3869.1-3874.4"
73681   wire $0\main_sdram_choose_req_cmd_payload_we[0:0]
73682   attribute \src "ls180.v:3915.1-3987.4"
73683   wire $0\main_sdram_choose_req_cmd_ready[0:0]
73684   attribute \src "ls180.v:7431.1-10055.4"
73685   wire width 2 $0\main_sdram_choose_req_grant[1:0]
73686   attribute \src "ls180.v:3843.1-3849.4"
73687   wire width 4 $0\main_sdram_choose_req_valids[3:0]
73688   attribute \src "ls180.v:3915.1-3987.4"
73689   wire $0\main_sdram_choose_req_want_activates[0:0]
73690   attribute \src "ls180.v:3915.1-3987.4"
73691   wire $0\main_sdram_choose_req_want_reads[0:0]
73692   attribute \src "ls180.v:3915.1-3987.4"
73693   wire $0\main_sdram_choose_req_want_writes[0:0]
73694   attribute \src "ls180.v:3132.1-3162.4"
73695   wire $0\main_sdram_cmd_last[0:0]
73696   attribute \src "ls180.v:7431.1-10055.4"
73697   wire width 13 $0\main_sdram_cmd_payload_a[12:0]
73698   attribute \src "ls180.v:7431.1-10055.4"
73699   wire width 2 $0\main_sdram_cmd_payload_ba[1:0]
73700   attribute \src "ls180.v:7431.1-10055.4"
73701   wire $0\main_sdram_cmd_payload_cas[0:0]
73702   attribute \src "ls180.v:393.5-393.42"
73703   wire $0\main_sdram_cmd_payload_is_read[0:0]
73704   attribute \src "ls180.v:394.5-394.43"
73705   wire $0\main_sdram_cmd_payload_is_write[0:0]
73706   attribute \src "ls180.v:7431.1-10055.4"
73707   wire $0\main_sdram_cmd_payload_ras[0:0]
73708   attribute \src "ls180.v:7431.1-10055.4"
73709   wire $0\main_sdram_cmd_payload_we[0:0]
73710   attribute \src "ls180.v:3915.1-3987.4"
73711   wire $0\main_sdram_cmd_ready[0:0]
73712   attribute \src "ls180.v:3132.1-3162.4"
73713   wire $0\main_sdram_cmd_valid[0:0]
73714   attribute \src "ls180.v:329.5-329.38"
73715   wire $0\main_sdram_command_issue_w[0:0]
73716   attribute \src "ls180.v:7431.1-10055.4"
73717   wire $0\main_sdram_command_re[0:0]
73718   attribute \src "ls180.v:7431.1-10055.4"
73719   wire width 6 $0\main_sdram_command_storage[5:0]
73720   attribute \src "ls180.v:378.5-378.35"
73721   wire $0\main_sdram_dfi_p0_act_n[0:0]
73722   attribute \src "ls180.v:7431.1-10055.4"
73723   wire width 13 $0\main_sdram_dfi_p0_address[12:0]
73724   attribute \src "ls180.v:7431.1-10055.4"
73725   wire width 2 $0\main_sdram_dfi_p0_bank[1:0]
73726   attribute \src "ls180.v:7431.1-10055.4"
73727   wire $0\main_sdram_dfi_p0_cas_n[0:0]
73728   attribute \src "ls180.v:7431.1-10055.4"
73729   wire $0\main_sdram_dfi_p0_cs_n[0:0]
73730   attribute \src "ls180.v:7431.1-10055.4"
73731   wire $0\main_sdram_dfi_p0_ras_n[0:0]
73732   attribute \src "ls180.v:7431.1-10055.4"
73733   wire $0\main_sdram_dfi_p0_rddata_en[0:0]
73734   attribute \src "ls180.v:7431.1-10055.4"
73735   wire $0\main_sdram_dfi_p0_we_n[0:0]
73736   attribute \src "ls180.v:7431.1-10055.4"
73737   wire $0\main_sdram_dfi_p0_wrdata_en[0:0]
73738   attribute \src "ls180.v:3915.1-3987.4"
73739   wire $0\main_sdram_en0[0:0]
73740   attribute \src "ls180.v:3915.1-3987.4"
73741   wire $0\main_sdram_en1[0:0]
73742   attribute \src "ls180.v:4011.1-4024.4"
73743   wire width 16 $0\main_sdram_interface_wdata[15:0]
73744   attribute \src "ls180.v:4011.1-4024.4"
73745   wire width 2 $0\main_sdram_interface_wdata_we[1:0]
73746   attribute \src "ls180.v:279.5-279.36"
73747   wire $0\main_sdram_inti_p0_act_n[0:0]
73748   attribute \src "ls180.v:3073.1-3089.4"
73749   wire $0\main_sdram_inti_p0_cas_n[0:0]
73750   attribute \src "ls180.v:3073.1-3089.4"
73751   wire $0\main_sdram_inti_p0_cs_n[0:0]
73752   attribute \src "ls180.v:3073.1-3089.4"
73753   wire $0\main_sdram_inti_p0_ras_n[0:0]
73754   attribute \src "ls180.v:3015.1-3069.4"
73755   wire width 16 $0\main_sdram_inti_p0_rddata[15:0]
73756   attribute \src "ls180.v:3015.1-3069.4"
73757   wire $0\main_sdram_inti_p0_rddata_valid[0:0]
73758   attribute \src "ls180.v:3073.1-3089.4"
73759   wire $0\main_sdram_inti_p0_we_n[0:0]
73760   attribute \src "ls180.v:3015.1-3069.4"
73761   wire $0\main_sdram_master_p0_act_n[0:0]
73762   attribute \src "ls180.v:3015.1-3069.4"
73763   wire width 13 $0\main_sdram_master_p0_address[12:0]
73764   attribute \src "ls180.v:3015.1-3069.4"
73765   wire width 2 $0\main_sdram_master_p0_bank[1:0]
73766   attribute \src "ls180.v:3015.1-3069.4"
73767   wire $0\main_sdram_master_p0_cas_n[0:0]
73768   attribute \src "ls180.v:3015.1-3069.4"
73769   wire $0\main_sdram_master_p0_cke[0:0]
73770   attribute \src "ls180.v:3015.1-3069.4"
73771   wire $0\main_sdram_master_p0_cs_n[0:0]
73772   attribute \src "ls180.v:3015.1-3069.4"
73773   wire $0\main_sdram_master_p0_odt[0:0]
73774   attribute \src "ls180.v:3015.1-3069.4"
73775   wire $0\main_sdram_master_p0_ras_n[0:0]
73776   attribute \src "ls180.v:3015.1-3069.4"
73777   wire $0\main_sdram_master_p0_rddata_en[0:0]
73778   attribute \src "ls180.v:3015.1-3069.4"
73779   wire $0\main_sdram_master_p0_reset_n[0:0]
73780   attribute \src "ls180.v:3015.1-3069.4"
73781   wire $0\main_sdram_master_p0_we_n[0:0]
73782   attribute \src "ls180.v:3015.1-3069.4"
73783   wire width 16 $0\main_sdram_master_p0_wrdata[15:0]
73784   attribute \src "ls180.v:3015.1-3069.4"
73785   wire $0\main_sdram_master_p0_wrdata_en[0:0]
73786   attribute \src "ls180.v:3015.1-3069.4"
73787   wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0]
73788   attribute \src "ls180.v:776.12-776.36"
73789   wire width 13 $0\main_sdram_nop_a[12:0]
73790   attribute \src "ls180.v:777.11-777.35"
73791   wire width 2 $0\main_sdram_nop_ba[1:0]
73792   attribute \src "ls180.v:7431.1-10055.4"
73793   wire $0\main_sdram_postponer_count[0:0]
73794   attribute \src "ls180.v:7431.1-10055.4"
73795   wire $0\main_sdram_postponer_req_o[0:0]
73796   attribute \src "ls180.v:7431.1-10055.4"
73797   wire $0\main_sdram_re[0:0]
73798   attribute \src "ls180.v:7431.1-10055.4"
73799   wire $0\main_sdram_sequencer_count[0:0]
73800   attribute \src "ls180.v:7431.1-10055.4"
73801   wire width 4 $0\main_sdram_sequencer_counter[3:0]
73802   attribute \src "ls180.v:7431.1-10055.4"
73803   wire $0\main_sdram_sequencer_done1[0:0]
73804   attribute \src "ls180.v:3132.1-3162.4"
73805   wire $0\main_sdram_sequencer_start0[0:0]
73806   attribute \src "ls180.v:3015.1-3069.4"
73807   wire width 16 $0\main_sdram_slave_p0_rddata[15:0]
73808   attribute \src "ls180.v:3015.1-3069.4"
73809   wire $0\main_sdram_slave_p0_rddata_valid[0:0]
73810   attribute \src "ls180.v:7431.1-10055.4"
73811   wire width 16 $0\main_sdram_status[15:0]
73812   attribute \src "ls180.v:779.5-779.31"
73813   wire $0\main_sdram_steerer0[0:0]
73814   attribute \src "ls180.v:780.5-780.31"
73815   wire $0\main_sdram_steerer1[0:0]
73816   attribute \src "ls180.v:3915.1-3987.4"
73817   wire width 2 $0\main_sdram_steerer_sel[1:0]
73818   attribute \src "ls180.v:7431.1-10055.4"
73819   wire width 4 $0\main_sdram_storage[3:0]
73820   attribute \src "ls180.v:7431.1-10055.4"
73821   wire $0\main_sdram_tccdcon_count[0:0]
73822   attribute \src "ls180.v:7431.1-10055.4"
73823   wire $0\main_sdram_tccdcon_ready[0:0]
73824   attribute \src "ls180.v:784.32-784.63"
73825   wire $0\main_sdram_tfawcon_ready[0:0]
73826   attribute \src "ls180.v:7431.1-10055.4"
73827   wire width 5 $0\main_sdram_time0[4:0]
73828   attribute \src "ls180.v:7431.1-10055.4"
73829   wire width 4 $0\main_sdram_time1[3:0]
73830   attribute \src "ls180.v:7431.1-10055.4"
73831   wire width 10 $0\main_sdram_timer_count1[9:0]
73832   attribute \src "ls180.v:782.32-782.63"
73833   wire $0\main_sdram_trrdcon_ready[0:0]
73834   attribute \src "ls180.v:7431.1-10055.4"
73835   wire width 3 $0\main_sdram_twtrcon_count[2:0]
73836   attribute \src "ls180.v:7431.1-10055.4"
73837   wire $0\main_sdram_twtrcon_ready[0:0]
73838   attribute \src "ls180.v:7431.1-10055.4"
73839   wire $0\main_sdram_wrdata_re[0:0]
73840   attribute \src "ls180.v:7431.1-10055.4"
73841   wire width 16 $0\main_sdram_wrdata_storage[15:0]
73842   attribute \src "ls180.v:7431.1-10055.4"
73843   wire width 16 $0\main_spimaster11_storage[15:0]
73844   attribute \src "ls180.v:7431.1-10055.4"
73845   wire $0\main_spimaster12_re[0:0]
73846   attribute \src "ls180.v:7431.1-10055.4"
73847   wire width 8 $0\main_spimaster16_storage[7:0]
73848   attribute \src "ls180.v:7431.1-10055.4"
73849   wire $0\main_spimaster17_re[0:0]
73850   attribute \src "ls180.v:7431.1-10055.4"
73851   wire $0\main_spimaster1_re[0:0]
73852   attribute \src "ls180.v:7431.1-10055.4"
73853   wire width 16 $0\main_spimaster1_storage[15:0]
73854   attribute \src "ls180.v:7431.1-10055.4"
73855   wire $0\main_spimaster21_storage[0:0]
73856   attribute \src "ls180.v:7431.1-10055.4"
73857   wire $0\main_spimaster22_re[0:0]
73858   attribute \src "ls180.v:7431.1-10055.4"
73859   wire $0\main_spimaster23_storage[0:0]
73860   attribute \src "ls180.v:7431.1-10055.4"
73861   wire $0\main_spimaster24_re[0:0]
73862   attribute \src "ls180.v:4233.1-4281.4"
73863   wire $0\main_spimaster25_clk_enable[0:0]
73864   attribute \src "ls180.v:4233.1-4281.4"
73865   wire $0\main_spimaster26_cs_enable[0:0]
73866   attribute \src "ls180.v:7431.1-10055.4"
73867   wire width 3 $0\main_spimaster27_count[2:0]
73868   attribute \src "ls180.v:4233.1-4281.4"
73869   wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0]
73870   attribute \src "ls180.v:4233.1-4281.4"
73871   wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
73872   attribute \src "ls180.v:4233.1-4281.4"
73873   wire $0\main_spimaster28_mosi_latch[0:0]
73874   attribute \src "ls180.v:4233.1-4281.4"
73875   wire $0\main_spimaster29_miso_latch[0:0]
73876   attribute \src "ls180.v:4233.1-4281.4"
73877   wire $0\main_spimaster2_done[0:0]
73878   attribute \src "ls180.v:7431.1-10055.4"
73879   wire width 16 $0\main_spimaster30_clk_divider[15:0]
73880   attribute \src "ls180.v:7431.1-10055.4"
73881   wire width 8 $0\main_spimaster33_mosi_data[7:0]
73882   attribute \src "ls180.v:7431.1-10055.4"
73883   wire width 3 $0\main_spimaster34_mosi_sel[2:0]
73884   attribute \src "ls180.v:7431.1-10055.4"
73885   wire width 8 $0\main_spimaster35_miso_data[7:0]
73886   attribute \src "ls180.v:4233.1-4281.4"
73887   wire $0\main_spimaster3_irq[0:0]
73888   attribute \src "ls180.v:7431.1-10055.4"
73889   wire width 8 $0\main_spimaster5_miso[7:0]
73890   attribute \src "ls180.v:1000.12-1000.47"
73891   wire width 16 $0\main_spimaster8_clk_divider[15:0]
73892   attribute \src "ls180.v:6285.1-6290.4"
73893   wire $0\main_spimaster9_start[0:0]
73894   attribute \src "ls180.v:7431.1-10055.4"
73895   wire width 16 $0\main_spisdcard_clk_divider1[15:0]
73896   attribute \src "ls180.v:4292.1-4340.4"
73897   wire $0\main_spisdcard_clk_enable[0:0]
73898   attribute \src "ls180.v:7431.1-10055.4"
73899   wire $0\main_spisdcard_control_re[0:0]
73900   attribute \src "ls180.v:7431.1-10055.4"
73901   wire width 16 $0\main_spisdcard_control_storage[15:0]
73902   attribute \src "ls180.v:7431.1-10055.4"
73903   wire width 3 $0\main_spisdcard_count[2:0]
73904   attribute \src "ls180.v:4292.1-4340.4"
73905   wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0]
73906   attribute \src "ls180.v:4292.1-4340.4"
73907   wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
73908   attribute \src "ls180.v:4292.1-4340.4"
73909   wire $0\main_spisdcard_cs_enable[0:0]
73910   attribute \src "ls180.v:7431.1-10055.4"
73911   wire $0\main_spisdcard_cs_re[0:0]
73912   attribute \src "ls180.v:7431.1-10055.4"
73913   wire $0\main_spisdcard_cs_storage[0:0]
73914   attribute \src "ls180.v:4292.1-4340.4"
73915   wire $0\main_spisdcard_done0[0:0]
73916   attribute \src "ls180.v:4292.1-4340.4"
73917   wire $0\main_spisdcard_irq[0:0]
73918   attribute \src "ls180.v:7431.1-10055.4"
73919   wire $0\main_spisdcard_loopback_re[0:0]
73920   attribute \src "ls180.v:7431.1-10055.4"
73921   wire $0\main_spisdcard_loopback_storage[0:0]
73922   attribute \src "ls180.v:7431.1-10055.4"
73923   wire width 8 $0\main_spisdcard_miso[7:0]
73924   attribute \src "ls180.v:7431.1-10055.4"
73925   wire width 8 $0\main_spisdcard_miso_data[7:0]
73926   attribute \src "ls180.v:4292.1-4340.4"
73927   wire $0\main_spisdcard_miso_latch[0:0]
73928   attribute \src "ls180.v:7431.1-10055.4"
73929   wire width 8 $0\main_spisdcard_mosi_data[7:0]
73930   attribute \src "ls180.v:4292.1-4340.4"
73931   wire $0\main_spisdcard_mosi_latch[0:0]
73932   attribute \src "ls180.v:7431.1-10055.4"
73933   wire $0\main_spisdcard_mosi_re[0:0]
73934   attribute \src "ls180.v:7431.1-10055.4"
73935   wire width 3 $0\main_spisdcard_mosi_sel[2:0]
73936   attribute \src "ls180.v:7431.1-10055.4"
73937   wire width 8 $0\main_spisdcard_mosi_storage[7:0]
73938   attribute \src "ls180.v:6331.1-6336.4"
73939   wire $0\main_spisdcard_start1[0:0]
73940   attribute \src "ls180.v:4151.1-4155.4"
73941   wire width 2 $0\main_uart_eventmanager_pending_w[1:0]
73942   attribute \src "ls180.v:7431.1-10055.4"
73943   wire $0\main_uart_eventmanager_re[0:0]
73944   attribute \src "ls180.v:4140.1-4144.4"
73945   wire width 2 $0\main_uart_eventmanager_status_w[1:0]
73946   attribute \src "ls180.v:7431.1-10055.4"
73947   wire width 2 $0\main_uart_eventmanager_storage[1:0]
73948   attribute \src "ls180.v:7431.1-10055.4"
73949   wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0]
73950   attribute \src "ls180.v:7431.1-10055.4"
73951   wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0]
73952   attribute \src "ls180.v:7431.1-10055.4"
73953   wire $0\main_uart_phy_re[0:0]
73954   attribute \src "ls180.v:7431.1-10055.4"
73955   wire width 4 $0\main_uart_phy_rx_bitcount[3:0]
73956   attribute \src "ls180.v:7431.1-10055.4"
73957   wire $0\main_uart_phy_rx_busy[0:0]
73958   attribute \src "ls180.v:7431.1-10055.4"
73959   wire $0\main_uart_phy_rx_r[0:0]
73960   attribute \src "ls180.v:7431.1-10055.4"
73961   wire width 8 $0\main_uart_phy_rx_reg[7:0]
73962   attribute \src "ls180.v:7431.1-10055.4"
73963   wire $0\main_uart_phy_sink_ready[0:0]
73964   attribute \src "ls180.v:855.5-855.38"
73965   wire $0\main_uart_phy_source_first[0:0]
73966   attribute \src "ls180.v:856.5-856.37"
73967   wire $0\main_uart_phy_source_last[0:0]
73968   attribute \src "ls180.v:7431.1-10055.4"
73969   wire width 8 $0\main_uart_phy_source_payload_data[7:0]
73970   attribute \src "ls180.v:7431.1-10055.4"
73971   wire $0\main_uart_phy_source_valid[0:0]
73972   attribute \src "ls180.v:7431.1-10055.4"
73973   wire width 32 $0\main_uart_phy_storage[31:0]
73974   attribute \src "ls180.v:7431.1-10055.4"
73975   wire width 4 $0\main_uart_phy_tx_bitcount[3:0]
73976   attribute \src "ls180.v:7431.1-10055.4"
73977   wire $0\main_uart_phy_tx_busy[0:0]
73978   attribute \src "ls180.v:7431.1-10055.4"
73979   wire width 8 $0\main_uart_phy_tx_reg[7:0]
73980   attribute \src "ls180.v:7431.1-10055.4"
73981   wire $0\main_uart_phy_uart_clk_rxen[0:0]
73982   attribute \src "ls180.v:7431.1-10055.4"
73983   wire $0\main_uart_phy_uart_clk_txen[0:0]
73984   attribute \src "ls180.v:982.5-982.27"
73985   wire $0\main_uart_reset[0:0]
73986   attribute \src "ls180.v:4145.1-4150.4"
73987   wire $0\main_uart_rx_clear[0:0]
73988   attribute \src "ls180.v:7431.1-10055.4"
73989   wire width 4 $0\main_uart_rx_fifo_consume[3:0]
73990   attribute \src "ls180.v:7431.1-10055.4"
73991   wire width 5 $0\main_uart_rx_fifo_level0[4:0]
73992   attribute \src "ls180.v:7431.1-10055.4"
73993   wire width 4 $0\main_uart_rx_fifo_produce[3:0]
73994   attribute \src "ls180.v:7431.1-10055.4"
73995   wire $0\main_uart_rx_fifo_readable[0:0]
73996   attribute \src "ls180.v:964.5-964.37"
73997   wire $0\main_uart_rx_fifo_replace[0:0]
73998   attribute \src "ls180.v:4203.1-4210.4"
73999   wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0]
74000   attribute \src "ls180.v:7431.1-10055.4"
74001   wire $0\main_uart_rx_old_trigger[0:0]
74002   attribute \src "ls180.v:7431.1-10055.4"
74003   wire $0\main_uart_rx_pending[0:0]
74004   attribute \src "ls180.v:4134.1-4139.4"
74005   wire $0\main_uart_tx_clear[0:0]
74006   attribute \src "ls180.v:7431.1-10055.4"
74007   wire width 4 $0\main_uart_tx_fifo_consume[3:0]
74008   attribute \src "ls180.v:7431.1-10055.4"
74009   wire width 5 $0\main_uart_tx_fifo_level0[4:0]
74010   attribute \src "ls180.v:7431.1-10055.4"
74011   wire width 4 $0\main_uart_tx_fifo_produce[3:0]
74012   attribute \src "ls180.v:7431.1-10055.4"
74013   wire $0\main_uart_tx_fifo_readable[0:0]
74014   attribute \src "ls180.v:927.5-927.37"
74015   wire $0\main_uart_tx_fifo_replace[0:0]
74016   attribute \src "ls180.v:910.5-910.40"
74017   wire $0\main_uart_tx_fifo_sink_first[0:0]
74018   attribute \src "ls180.v:911.5-911.39"
74019   wire $0\main_uart_tx_fifo_sink_last[0:0]
74020   attribute \src "ls180.v:4173.1-4180.4"
74021   wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0]
74022   attribute \src "ls180.v:7431.1-10055.4"
74023   wire $0\main_uart_tx_old_trigger[0:0]
74024   attribute \src "ls180.v:7431.1-10055.4"
74025   wire $0\main_uart_tx_pending[0:0]
74026   attribute \src "ls180.v:4043.1-4089.4"
74027   wire $0\main_wb_sdram_ack[0:0]
74028   attribute \src "ls180.v:823.5-823.29"
74029   wire $0\main_wb_sdram_err[0:0]
74030   attribute \src "ls180.v:7431.1-10055.4"
74031   wire $0\main_wdata_consumed[0:0]
74032   attribute \src "ls180.v:10059.1-10069.4"
74033   wire width 7 $0\memadr[6:0]
74034   attribute \src "ls180.v:10079.1-10083.4"
74035   wire width 25 $0\memdat[24:0]
74036   attribute \src "ls180.v:10093.1-10097.4"
74037   wire width 25 $0\memdat_1[24:0]
74038   attribute \src "ls180.v:10107.1-10111.4"
74039   wire width 25 $0\memdat_2[24:0]
74040   attribute \src "ls180.v:10121.1-10125.4"
74041   wire width 25 $0\memdat_3[24:0]
74042   attribute \src "ls180.v:10136.1-10140.4"
74043   wire width 10 $0\memdat_4[9:0]
74044   attribute \src "ls180.v:10142.1-10145.4"
74045   wire width 10 $0\memdat_5[9:0]
74046   attribute \src "ls180.v:10153.1-10157.4"
74047   wire width 10 $0\memdat_6[9:0]
74048   attribute \src "ls180.v:10159.1-10162.4"
74049   wire width 10 $0\memdat_7[9:0]
74050   attribute \src "ls180.v:10169.1-10173.4"
74051   wire width 10 $0\memdat_8[9:0]
74052   attribute \src "ls180.v:10183.1-10187.4"
74053   wire width 10 $0\memdat_9[9:0]
74054   attribute \src "ls180.v:7431.1-10055.4"
74055   wire width 2 $0\pwm[1:0]
74056   attribute \src "ls180.v:7359.1-7429.4"
74057   wire $0\sdcard_clk[0:0]
74058   attribute \src "ls180.v:7359.1-7429.4"
74059   wire $0\sdcard_cmd_o[0:0]
74060   attribute \src "ls180.v:7359.1-7429.4"
74061   wire $0\sdcard_cmd_oe[0:0]
74062   attribute \src "ls180.v:7359.1-7429.4"
74063   wire width 4 $0\sdcard_data_o[3:0]
74064   attribute \src "ls180.v:7359.1-7429.4"
74065   wire $0\sdcard_data_oe[0:0]
74066   attribute \src "ls180.v:7359.1-7429.4"
74067   wire width 13 $0\sdram_a[12:0]
74068   attribute \src "ls180.v:7359.1-7429.4"
74069   wire width 2 $0\sdram_ba[1:0]
74070   attribute \src "ls180.v:7359.1-7429.4"
74071   wire $0\sdram_cas_n[0:0]
74072   attribute \src "ls180.v:7359.1-7429.4"
74073   wire $0\sdram_cke[0:0]
74074   attribute \src "ls180.v:7359.1-7429.4"
74075   wire $0\sdram_clock[0:0]
74076   attribute \src "ls180.v:7359.1-7429.4"
74077   wire $0\sdram_cs_n[0:0]
74078   attribute \src "ls180.v:7359.1-7429.4"
74079   wire width 2 $0\sdram_dm[1:0]
74080   attribute \src "ls180.v:7359.1-7429.4"
74081   wire width 16 $0\sdram_dq_o[15:0]
74082   attribute \src "ls180.v:7359.1-7429.4"
74083   wire $0\sdram_dq_oe[0:0]
74084   attribute \src "ls180.v:7359.1-7429.4"
74085   wire $0\sdram_ras_n[0:0]
74086   attribute \src "ls180.v:7359.1-7429.4"
74087   wire $0\sdram_we_n[0:0]
74088   attribute \src "ls180.v:7431.1-10055.4"
74089   wire $0\spimaster_clk[0:0]
74090   attribute \src "ls180.v:7431.1-10055.4"
74091   wire $0\spimaster_cs_n[0:0]
74092   attribute \src "ls180.v:7431.1-10055.4"
74093   wire $0\spimaster_mosi[0:0]
74094   attribute \src "ls180.v:7431.1-10055.4"
74095   wire $0\spisdcard_clk[0:0]
74096   attribute \src "ls180.v:7431.1-10055.4"
74097   wire $0\spisdcard_cs_n[0:0]
74098   attribute \src "ls180.v:7431.1-10055.4"
74099   wire $0\spisdcard_mosi[0:0]
74100   attribute \src "ls180.v:7431.1-10055.4"
74101   wire $0\uart_tx[0:0]
74102   attribute \src "ls180.v:1749.11-1749.49"
74103   wire width 3 $1\builder_bankmachine0_next_state[2:0]
74104   attribute \src "ls180.v:1748.11-1748.44"
74105   wire width 3 $1\builder_bankmachine0_state[2:0]
74106   attribute \src "ls180.v:1751.11-1751.49"
74107   wire width 3 $1\builder_bankmachine1_next_state[2:0]
74108   attribute \src "ls180.v:1750.11-1750.44"
74109   wire width 3 $1\builder_bankmachine1_state[2:0]
74110   attribute \src "ls180.v:1753.11-1753.49"
74111   wire width 3 $1\builder_bankmachine2_next_state[2:0]
74112   attribute \src "ls180.v:1752.11-1752.44"
74113   wire width 3 $1\builder_bankmachine2_state[2:0]
74114   attribute \src "ls180.v:1755.11-1755.49"
74115   wire width 3 $1\builder_bankmachine3_next_state[2:0]
74116   attribute \src "ls180.v:1754.11-1754.44"
74117   wire width 3 $1\builder_bankmachine3_state[2:0]
74118   attribute \src "ls180.v:2600.5-2600.41"
74119   wire $1\builder_comb_rhs_array_muxed0[0:0]
74120   attribute \src "ls180.v:2613.5-2613.42"
74121   wire $1\builder_comb_rhs_array_muxed10[0:0]
74122   attribute \src "ls180.v:2614.5-2614.42"
74123   wire $1\builder_comb_rhs_array_muxed11[0:0]
74124   attribute \src "ls180.v:2618.12-2618.50"
74125   wire width 22 $1\builder_comb_rhs_array_muxed12[21:0]
74126   attribute \src "ls180.v:2619.5-2619.42"
74127   wire $1\builder_comb_rhs_array_muxed13[0:0]
74128   attribute \src "ls180.v:2620.5-2620.42"
74129   wire $1\builder_comb_rhs_array_muxed14[0:0]
74130   attribute \src "ls180.v:2621.12-2621.50"
74131   wire width 22 $1\builder_comb_rhs_array_muxed15[21:0]
74132   attribute \src "ls180.v:2622.5-2622.42"
74133   wire $1\builder_comb_rhs_array_muxed16[0:0]
74134   attribute \src "ls180.v:2623.5-2623.42"
74135   wire $1\builder_comb_rhs_array_muxed17[0:0]
74136   attribute \src "ls180.v:2624.12-2624.50"
74137   wire width 22 $1\builder_comb_rhs_array_muxed18[21:0]
74138   attribute \src "ls180.v:2625.5-2625.42"
74139   wire $1\builder_comb_rhs_array_muxed19[0:0]
74140   attribute \src "ls180.v:2601.12-2601.49"
74141   wire width 13 $1\builder_comb_rhs_array_muxed1[12:0]
74142   attribute \src "ls180.v:2626.5-2626.42"
74143   wire $1\builder_comb_rhs_array_muxed20[0:0]
74144   attribute \src "ls180.v:2627.12-2627.50"
74145   wire width 22 $1\builder_comb_rhs_array_muxed21[21:0]
74146   attribute \src "ls180.v:2628.5-2628.42"
74147   wire $1\builder_comb_rhs_array_muxed22[0:0]
74148   attribute \src "ls180.v:2629.5-2629.42"
74149   wire $1\builder_comb_rhs_array_muxed23[0:0]
74150   attribute \src "ls180.v:2630.12-2630.50"
74151   wire width 32 $1\builder_comb_rhs_array_muxed24[31:0]
74152   attribute \src "ls180.v:2631.12-2631.50"
74153   wire width 32 $1\builder_comb_rhs_array_muxed25[31:0]
74154   attribute \src "ls180.v:2632.11-2632.48"
74155   wire width 4 $1\builder_comb_rhs_array_muxed26[3:0]
74156   attribute \src "ls180.v:2633.5-2633.42"
74157   wire $1\builder_comb_rhs_array_muxed27[0:0]
74158   attribute \src "ls180.v:2634.5-2634.42"
74159   wire $1\builder_comb_rhs_array_muxed28[0:0]
74160   attribute \src "ls180.v:2635.5-2635.42"
74161   wire $1\builder_comb_rhs_array_muxed29[0:0]
74162   attribute \src "ls180.v:2602.11-2602.47"
74163   wire width 2 $1\builder_comb_rhs_array_muxed2[1:0]
74164   attribute \src "ls180.v:2636.11-2636.48"
74165   wire width 3 $1\builder_comb_rhs_array_muxed30[2:0]
74166   attribute \src "ls180.v:2637.11-2637.48"
74167   wire width 2 $1\builder_comb_rhs_array_muxed31[1:0]
74168   attribute \src "ls180.v:2603.5-2603.41"
74169   wire $1\builder_comb_rhs_array_muxed3[0:0]
74170   attribute \src "ls180.v:2604.5-2604.41"
74171   wire $1\builder_comb_rhs_array_muxed4[0:0]
74172   attribute \src "ls180.v:2605.5-2605.41"
74173   wire $1\builder_comb_rhs_array_muxed5[0:0]
74174   attribute \src "ls180.v:2609.5-2609.41"
74175   wire $1\builder_comb_rhs_array_muxed6[0:0]
74176   attribute \src "ls180.v:2610.12-2610.49"
74177   wire width 13 $1\builder_comb_rhs_array_muxed7[12:0]
74178   attribute \src "ls180.v:2611.11-2611.47"
74179   wire width 2 $1\builder_comb_rhs_array_muxed8[1:0]
74180   attribute \src "ls180.v:2612.5-2612.41"
74181   wire $1\builder_comb_rhs_array_muxed9[0:0]
74182   attribute \src "ls180.v:2606.5-2606.39"
74183   wire $1\builder_comb_t_array_muxed0[0:0]
74184   attribute \src "ls180.v:2607.5-2607.39"
74185   wire $1\builder_comb_t_array_muxed1[0:0]
74186   attribute \src "ls180.v:2608.5-2608.39"
74187   wire $1\builder_comb_t_array_muxed2[0:0]
74188   attribute \src "ls180.v:2615.5-2615.39"
74189   wire $1\builder_comb_t_array_muxed3[0:0]
74190   attribute \src "ls180.v:2616.5-2616.39"
74191   wire $1\builder_comb_t_array_muxed4[0:0]
74192   attribute \src "ls180.v:2617.5-2617.39"
74193   wire $1\builder_comb_t_array_muxed5[0:0]
74194   attribute \src "ls180.v:1735.5-1735.41"
74195   wire $1\builder_converter0_next_state[0:0]
74196   attribute \src "ls180.v:1734.5-1734.36"
74197   wire $1\builder_converter0_state[0:0]
74198   attribute \src "ls180.v:1739.5-1739.41"
74199   wire $1\builder_converter1_next_state[0:0]
74200   attribute \src "ls180.v:1738.5-1738.36"
74201   wire $1\builder_converter1_state[0:0]
74202   attribute \src "ls180.v:1743.5-1743.41"
74203   wire $1\builder_converter2_next_state[0:0]
74204   attribute \src "ls180.v:1742.5-1742.36"
74205   wire $1\builder_converter2_state[0:0]
74206   attribute \src "ls180.v:1780.5-1780.40"
74207   wire $1\builder_converter_next_state[0:0]
74208   attribute \src "ls180.v:1779.5-1779.35"
74209   wire $1\builder_converter_state[0:0]
74210   attribute \src "ls180.v:1900.12-1900.39"
74211   wire width 20 $1\builder_count[19:0]
74212   attribute \src "ls180.v:1897.5-1897.25"
74213   wire $1\builder_error[0:0]
74214   attribute \src "ls180.v:1894.11-1894.31"
74215   wire width 3 $1\builder_grant[2:0]
74216   attribute \src "ls180.v:1904.11-1904.51"
74217   wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0]
74218   attribute \src "ls180.v:2406.11-2406.52"
74219   wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0]
74220   attribute \src "ls180.v:2439.11-2439.52"
74221   wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0]
74222   attribute \src "ls180.v:2480.11-2480.52"
74223   wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0]
74224   attribute \src "ls180.v:2545.11-2545.52"
74225   wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0]
74226   attribute \src "ls180.v:2570.11-2570.52"
74227   wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0]
74228   attribute \src "ls180.v:1945.11-1945.51"
74229   wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0]
74230   attribute \src "ls180.v:1974.11-1974.51"
74231   wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0]
74232   attribute \src "ls180.v:1987.11-1987.51"
74233   wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0]
74234   attribute \src "ls180.v:2028.11-2028.51"
74235   wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0]
74236   attribute \src "ls180.v:2069.11-2069.51"
74237   wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0]
74238   attribute \src "ls180.v:2134.11-2134.51"
74239   wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0]
74240   attribute \src "ls180.v:2267.11-2267.51"
74241   wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0]
74242   attribute \src "ls180.v:2348.11-2348.51"
74243   wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0]
74244   attribute \src "ls180.v:2365.11-2365.51"
74245   wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0]
74246   attribute \src "ls180.v:1867.12-1867.43"
74247   wire width 14 $1\builder_libresocsim_adr[13:0]
74248   attribute \src "ls180.v:2596.12-2596.55"
74249   wire width 14 $1\builder_libresocsim_adr_next_value1[13:0]
74250   attribute \src "ls180.v:2597.5-2597.50"
74251   wire $1\builder_libresocsim_adr_next_value_ce1[0:0]
74252   attribute \src "ls180.v:1869.11-1869.43"
74253   wire width 8 $1\builder_libresocsim_dat_w[7:0]
74254   attribute \src "ls180.v:2594.11-2594.55"
74255   wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0]
74256   attribute \src "ls180.v:2595.5-2595.52"
74257   wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
74258   attribute \src "ls180.v:1868.5-1868.34"
74259   wire $1\builder_libresocsim_we[0:0]
74260   attribute \src "ls180.v:2598.5-2598.46"
74261   wire $1\builder_libresocsim_we_next_value2[0:0]
74262   attribute \src "ls180.v:2599.5-2599.49"
74263   wire $1\builder_libresocsim_we_next_value_ce2[0:0]
74264   attribute \src "ls180.v:1877.5-1877.44"
74265   wire $1\builder_libresocsim_wishbone_ack[0:0]
74266   attribute \src "ls180.v:1873.12-1873.54"
74267   wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0]
74268   attribute \src "ls180.v:1757.11-1757.48"
74269   wire width 3 $1\builder_multiplexer_next_state[2:0]
74270   attribute \src "ls180.v:1756.11-1756.43"
74271   wire width 3 $1\builder_multiplexer_state[2:0]
74272   attribute \src "ls180.v:2703.32-2703.66"
74273   wire $1\builder_multiregimpl0_regs0[0:0]
74274   attribute \src "ls180.v:2704.32-2704.66"
74275   wire $1\builder_multiregimpl0_regs1[0:0]
74276   attribute \src "ls180.v:2723.32-2723.67"
74277   wire $1\builder_multiregimpl10_regs0[0:0]
74278   attribute \src "ls180.v:2724.32-2724.67"
74279   wire $1\builder_multiregimpl10_regs1[0:0]
74280   attribute \src "ls180.v:2725.32-2725.67"
74281   wire $1\builder_multiregimpl11_regs0[0:0]
74282   attribute \src "ls180.v:2726.32-2726.67"
74283   wire $1\builder_multiregimpl11_regs1[0:0]
74284   attribute \src "ls180.v:2727.32-2727.67"
74285   wire $1\builder_multiregimpl12_regs0[0:0]
74286   attribute \src "ls180.v:2728.32-2728.67"
74287   wire $1\builder_multiregimpl12_regs1[0:0]
74288   attribute \src "ls180.v:2729.32-2729.67"
74289   wire $1\builder_multiregimpl13_regs0[0:0]
74290   attribute \src "ls180.v:2730.32-2730.67"
74291   wire $1\builder_multiregimpl13_regs1[0:0]
74292   attribute \src "ls180.v:2731.32-2731.67"
74293   wire $1\builder_multiregimpl14_regs0[0:0]
74294   attribute \src "ls180.v:2732.32-2732.67"
74295   wire $1\builder_multiregimpl14_regs1[0:0]
74296   attribute \src "ls180.v:2733.32-2733.67"
74297   wire $1\builder_multiregimpl15_regs0[0:0]
74298   attribute \src "ls180.v:2734.32-2734.67"
74299   wire $1\builder_multiregimpl15_regs1[0:0]
74300   attribute \src "ls180.v:2735.32-2735.67"
74301   wire $1\builder_multiregimpl16_regs0[0:0]
74302   attribute \src "ls180.v:2736.32-2736.67"
74303   wire $1\builder_multiregimpl16_regs1[0:0]
74304   attribute \src "ls180.v:2705.32-2705.66"
74305   wire $1\builder_multiregimpl1_regs0[0:0]
74306   attribute \src "ls180.v:2706.32-2706.66"
74307   wire $1\builder_multiregimpl1_regs1[0:0]
74308   attribute \src "ls180.v:2707.32-2707.66"
74309   wire $1\builder_multiregimpl2_regs0[0:0]
74310   attribute \src "ls180.v:2708.32-2708.66"
74311   wire $1\builder_multiregimpl2_regs1[0:0]
74312   attribute \src "ls180.v:2709.32-2709.66"
74313   wire $1\builder_multiregimpl3_regs0[0:0]
74314   attribute \src "ls180.v:2710.32-2710.66"
74315   wire $1\builder_multiregimpl3_regs1[0:0]
74316   attribute \src "ls180.v:2711.32-2711.66"
74317   wire $1\builder_multiregimpl4_regs0[0:0]
74318   attribute \src "ls180.v:2712.32-2712.66"
74319   wire $1\builder_multiregimpl4_regs1[0:0]
74320   attribute \src "ls180.v:2713.32-2713.66"
74321   wire $1\builder_multiregimpl5_regs0[0:0]
74322   attribute \src "ls180.v:2714.32-2714.66"
74323   wire $1\builder_multiregimpl5_regs1[0:0]
74324   attribute \src "ls180.v:2715.32-2715.66"
74325   wire $1\builder_multiregimpl6_regs0[0:0]
74326   attribute \src "ls180.v:2716.32-2716.66"
74327   wire $1\builder_multiregimpl6_regs1[0:0]
74328   attribute \src "ls180.v:2717.32-2717.66"
74329   wire $1\builder_multiregimpl7_regs0[0:0]
74330   attribute \src "ls180.v:2718.32-2718.66"
74331   wire $1\builder_multiregimpl7_regs1[0:0]
74332   attribute \src "ls180.v:2719.32-2719.66"
74333   wire $1\builder_multiregimpl8_regs0[0:0]
74334   attribute \src "ls180.v:2720.32-2720.66"
74335   wire $1\builder_multiregimpl8_regs1[0:0]
74336   attribute \src "ls180.v:2721.32-2721.66"
74337   wire $1\builder_multiregimpl9_regs0[0:0]
74338   attribute \src "ls180.v:2722.32-2722.66"
74339   wire $1\builder_multiregimpl9_regs1[0:0]
74340   attribute \src "ls180.v:1775.5-1775.43"
74341   wire $1\builder_new_master_rdata_valid0[0:0]
74342   attribute \src "ls180.v:1776.5-1776.43"
74343   wire $1\builder_new_master_rdata_valid1[0:0]
74344   attribute \src "ls180.v:1777.5-1777.43"
74345   wire $1\builder_new_master_rdata_valid2[0:0]
74346   attribute \src "ls180.v:1778.5-1778.43"
74347   wire $1\builder_new_master_rdata_valid3[0:0]
74348   attribute \src "ls180.v:1774.5-1774.42"
74349   wire $1\builder_new_master_wdata_ready[0:0]
74350   attribute \src "ls180.v:2593.11-2593.36"
74351   wire width 2 $1\builder_next_state[1:0]
74352   attribute \src "ls180.v:1747.11-1747.46"
74353   wire width 2 $1\builder_refresher_next_state[1:0]
74354   attribute \src "ls180.v:1746.11-1746.41"
74355   wire width 2 $1\builder_refresher_state[1:0]
74356   attribute \src "ls180.v:1856.11-1856.51"
74357   wire width 2 $1\builder_sdblock2memdma_next_state[1:0]
74358   attribute \src "ls180.v:1855.11-1855.46"
74359   wire width 2 $1\builder_sdblock2memdma_state[1:0]
74360   attribute \src "ls180.v:1824.5-1824.57"
74361   wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
74362   attribute \src "ls180.v:1823.5-1823.52"
74363   wire $1\builder_sdcore_crcupstreaminserter_state[0:0]
74364   attribute \src "ls180.v:1836.11-1836.47"
74365   wire width 3 $1\builder_sdcore_fsm_next_state[2:0]
74366   attribute \src "ls180.v:1835.11-1835.42"
74367   wire width 3 $1\builder_sdcore_fsm_state[2:0]
74368   attribute \src "ls180.v:1860.5-1860.49"
74369   wire $1\builder_sdmem2blockdma_fsm_next_state[0:0]
74370   attribute \src "ls180.v:1859.5-1859.44"
74371   wire $1\builder_sdmem2blockdma_fsm_state[0:0]
74372   attribute \src "ls180.v:1864.11-1864.65"
74373   wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
74374   attribute \src "ls180.v:1863.11-1863.60"
74375   wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0]
74376   attribute \src "ls180.v:1812.11-1812.46"
74377   wire width 3 $1\builder_sdphy_fsm_next_state[2:0]
74378   attribute \src "ls180.v:1811.11-1811.41"
74379   wire width 3 $1\builder_sdphy_fsm_state[2:0]
74380   attribute \src "ls180.v:1800.11-1800.52"
74381   wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0]
74382   attribute \src "ls180.v:1799.11-1799.47"
74383   wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0]
74384   attribute \src "ls180.v:1796.11-1796.52"
74385   wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0]
74386   attribute \src "ls180.v:1795.11-1795.47"
74387   wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0]
74388   attribute \src "ls180.v:1808.5-1808.46"
74389   wire $1\builder_sdphy_sdphycrcr_next_state[0:0]
74390   attribute \src "ls180.v:1807.5-1807.41"
74391   wire $1\builder_sdphy_sdphycrcr_state[0:0]
74392   attribute \src "ls180.v:1816.11-1816.53"
74393   wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0]
74394   attribute \src "ls180.v:1815.11-1815.48"
74395   wire width 3 $1\builder_sdphy_sdphydatar_state[2:0]
74396   attribute \src "ls180.v:1792.5-1792.46"
74397   wire $1\builder_sdphy_sdphyinit_next_state[0:0]
74398   attribute \src "ls180.v:1791.5-1791.41"
74399   wire $1\builder_sdphy_sdphyinit_state[0:0]
74400   attribute \src "ls180.v:1888.5-1888.30"
74401   wire $1\builder_shared_ack[0:0]
74402   attribute \src "ls180.v:1884.12-1884.40"
74403   wire width 32 $1\builder_shared_dat_r[31:0]
74404   attribute \src "ls180.v:1895.11-1895.35"
74405   wire width 5 $1\builder_slave_sel[4:0]
74406   attribute \src "ls180.v:1896.11-1896.37"
74407   wire width 5 $1\builder_slave_sel_r[4:0]
74408   attribute \src "ls180.v:1784.11-1784.47"
74409   wire width 2 $1\builder_spimaster0_next_state[1:0]
74410   attribute \src "ls180.v:1783.11-1783.42"
74411   wire width 2 $1\builder_spimaster0_state[1:0]
74412   attribute \src "ls180.v:1788.11-1788.47"
74413   wire width 2 $1\builder_spimaster1_next_state[1:0]
74414   attribute \src "ls180.v:1787.11-1787.42"
74415   wire width 2 $1\builder_spimaster1_state[1:0]
74416   attribute \src "ls180.v:2592.11-2592.31"
74417   wire width 2 $1\builder_state[1:0]
74418   attribute \src "ls180.v:2645.5-2645.39"
74419   wire $1\builder_sync_f_array_muxed0[0:0]
74420   attribute \src "ls180.v:2646.5-2646.39"
74421   wire $1\builder_sync_f_array_muxed1[0:0]
74422   attribute \src "ls180.v:2638.11-2638.47"
74423   wire width 2 $1\builder_sync_rhs_array_muxed0[1:0]
74424   attribute \src "ls180.v:2639.12-2639.49"
74425   wire width 13 $1\builder_sync_rhs_array_muxed1[12:0]
74426   attribute \src "ls180.v:2640.5-2640.41"
74427   wire $1\builder_sync_rhs_array_muxed2[0:0]
74428   attribute \src "ls180.v:2641.5-2641.41"
74429   wire $1\builder_sync_rhs_array_muxed3[0:0]
74430   attribute \src "ls180.v:2642.5-2642.41"
74431   wire $1\builder_sync_rhs_array_muxed4[0:0]
74432   attribute \src "ls180.v:2643.5-2643.41"
74433   wire $1\builder_sync_rhs_array_muxed5[0:0]
74434   attribute \src "ls180.v:2644.5-2644.41"
74435   wire $1\builder_sync_rhs_array_muxed6[0:0]
74436   attribute \src "ls180.v:836.5-836.29"
74437   wire $1\main_cmd_consumed[0:0]
74438   attribute \src "ls180.v:833.5-833.34"
74439   wire $1\main_converter_counter[0:0]
74440   attribute \src "ls180.v:1781.5-1781.55"
74441   wire $1\main_converter_counter_converter_next_value[0:0]
74442   attribute \src "ls180.v:1782.5-1782.58"
74443   wire $1\main_converter_counter_converter_next_value_ce[0:0]
74444   attribute \src "ls180.v:835.12-835.40"
74445   wire width 32 $1\main_converter_dat_r[31:0]
74446   attribute \src "ls180.v:832.5-832.31"
74447   wire $1\main_converter_skip[0:0]
74448   attribute \src "ls180.v:267.12-267.38"
74449   wire width 16 $1\main_dfi_p0_rddata[15:0]
74450   attribute \src "ls180.v:268.5-268.36"
74451   wire $1\main_dfi_p0_rddata_valid[0:0]
74452   attribute \src "ls180.v:1067.12-1067.30"
74453   wire width 36 $1\main_dummy[35:0]
74454   attribute \src "ls180.v:984.5-984.27"
74455   wire $1\main_gpio_oe_re[0:0]
74456   attribute \src "ls180.v:983.12-983.40"
74457   wire width 16 $1\main_gpio_oe_storage[15:0]
74458   attribute \src "ls180.v:988.5-988.28"
74459   wire $1\main_gpio_out_re[0:0]
74460   attribute \src "ls180.v:987.12-987.41"
74461   wire width 16 $1\main_gpio_out_storage[15:0]
74462   attribute \src "ls180.v:985.12-985.36"
74463   wire width 16 $1\main_gpio_status[15:0]
74464   attribute \src "ls180.v:1092.5-1092.23"
74465   wire $1\main_i2c_re[0:0]
74466   attribute \src "ls180.v:1091.11-1091.34"
74467   wire width 3 $1\main_i2c_storage[2:0]
74468   attribute \src "ls180.v:252.5-252.24"
74469   wire $1\main_int_rst[0:0]
74470   attribute \src "ls180.v:1640.12-1640.43"
74471   wire width 32 $1\main_interface1_bus_adr[31:0]
74472   attribute \src "ls180.v:1644.5-1644.35"
74473   wire $1\main_interface1_bus_cyc[0:0]
74474   attribute \src "ls180.v:1643.11-1643.41"
74475   wire width 4 $1\main_interface1_bus_sel[3:0]
74476   attribute \src "ls180.v:1645.5-1645.35"
74477   wire $1\main_interface1_bus_stb[0:0]
74478   attribute \src "ls180.v:1647.5-1647.34"
74479   wire $1\main_interface1_bus_we[0:0]
74480   attribute \src "ls180.v:63.12-63.47"
74481   wire width 32 $1\main_libresocsim_bus_errors[31:0]
74482   attribute \src "ls180.v:174.5-174.47"
74483   wire $1\main_libresocsim_converter0_counter[0:0]
74484   attribute \src "ls180.v:1736.5-1736.69"
74485   wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
74486   attribute \src "ls180.v:1737.5-1737.72"
74487   wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
74488   attribute \src "ls180.v:176.12-176.53"
74489   wire width 64 $1\main_libresocsim_converter0_dat_r[63:0]
74490   attribute \src "ls180.v:173.5-173.44"
74491   wire $1\main_libresocsim_converter0_skip[0:0]
74492   attribute \src "ls180.v:189.5-189.47"
74493   wire $1\main_libresocsim_converter1_counter[0:0]
74494   attribute \src "ls180.v:1740.5-1740.69"
74495   wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
74496   attribute \src "ls180.v:1741.5-1741.72"
74497   wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
74498   attribute \src "ls180.v:191.12-191.53"
74499   wire width 64 $1\main_libresocsim_converter1_dat_r[63:0]
74500   attribute \src "ls180.v:188.5-188.44"
74501   wire $1\main_libresocsim_converter1_skip[0:0]
74502   attribute \src "ls180.v:204.5-204.47"
74503   wire $1\main_libresocsim_converter2_counter[0:0]
74504   attribute \src "ls180.v:1744.5-1744.69"
74505   wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
74506   attribute \src "ls180.v:1745.5-1745.72"
74507   wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
74508   attribute \src "ls180.v:206.12-206.53"
74509   wire width 64 $1\main_libresocsim_converter2_dat_r[63:0]
74510   attribute \src "ls180.v:203.5-203.44"
74511   wire $1\main_libresocsim_converter2_skip[0:0]
74512   attribute \src "ls180.v:227.5-227.34"
74513   wire $1\main_libresocsim_en_re[0:0]
74514   attribute \src "ls180.v:226.5-226.39"
74515   wire $1\main_libresocsim_en_storage[0:0]
74516   attribute \src "ls180.v:247.5-247.44"
74517   wire $1\main_libresocsim_eventmanager_re[0:0]
74518   attribute \src "ls180.v:246.5-246.49"
74519   wire $1\main_libresocsim_eventmanager_storage[0:0]
74520   attribute \src "ls180.v:162.12-162.71"
74521   wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0]
74522   attribute \src "ls180.v:166.5-166.63"
74523   wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
74524   attribute \src "ls180.v:163.12-163.73"
74525   wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
74526   attribute \src "ls180.v:165.11-165.69"
74527   wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0]
74528   attribute \src "ls180.v:167.5-167.63"
74529   wire $1\main_libresocsim_interface0_converted_interface_stb[0:0]
74530   attribute \src "ls180.v:169.5-169.62"
74531   wire $1\main_libresocsim_interface0_converted_interface_we[0:0]
74532   attribute \src "ls180.v:177.12-177.71"
74533   wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0]
74534   attribute \src "ls180.v:181.5-181.63"
74535   wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
74536   attribute \src "ls180.v:178.12-178.73"
74537   wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
74538   attribute \src "ls180.v:180.11-180.69"
74539   wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0]
74540   attribute \src "ls180.v:182.5-182.63"
74541   wire $1\main_libresocsim_interface1_converted_interface_stb[0:0]
74542   attribute \src "ls180.v:184.5-184.62"
74543   wire $1\main_libresocsim_interface1_converted_interface_we[0:0]
74544   attribute \src "ls180.v:192.12-192.71"
74545   wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0]
74546   attribute \src "ls180.v:196.5-196.63"
74547   wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
74548   attribute \src "ls180.v:193.12-193.73"
74549   wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
74550   attribute \src "ls180.v:195.11-195.69"
74551   wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0]
74552   attribute \src "ls180.v:197.5-197.63"
74553   wire $1\main_libresocsim_interface2_converted_interface_stb[0:0]
74554   attribute \src "ls180.v:199.5-199.62"
74555   wire $1\main_libresocsim_interface2_converted_interface_we[0:0]
74556   attribute \src "ls180.v:72.5-72.46"
74557   wire $1\main_libresocsim_libresoc_dbus_ack[0:0]
74558   attribute \src "ls180.v:83.5-83.46"
74559   wire $1\main_libresocsim_libresoc_ibus_ack[0:0]
74560   attribute \src "ls180.v:65.12-65.55"
74561   wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0]
74562   attribute \src "ls180.v:116.5-116.49"
74563   wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
74564   attribute \src "ls180.v:223.5-223.36"
74565   wire $1\main_libresocsim_load_re[0:0]
74566   attribute \src "ls180.v:222.12-222.49"
74567   wire width 32 $1\main_libresocsim_load_storage[31:0]
74568   attribute \src "ls180.v:213.5-213.40"
74569   wire $1\main_libresocsim_ram_bus_ack[0:0]
74570   attribute \src "ls180.v:225.5-225.38"
74571   wire $1\main_libresocsim_reload_re[0:0]
74572   attribute \src "ls180.v:224.12-224.51"
74573   wire width 32 $1\main_libresocsim_reload_storage[31:0]
74574   attribute \src "ls180.v:56.5-56.37"
74575   wire $1\main_libresocsim_reset_re[0:0]
74576   attribute \src "ls180.v:55.5-55.42"
74577   wire $1\main_libresocsim_reset_storage[0:0]
74578   attribute \src "ls180.v:58.5-58.39"
74579   wire $1\main_libresocsim_scratch_re[0:0]
74580   attribute \src "ls180.v:57.12-57.60"
74581   wire width 32 $1\main_libresocsim_scratch_storage[31:0]
74582   attribute \src "ls180.v:229.5-229.44"
74583   wire $1\main_libresocsim_update_value_re[0:0]
74584   attribute \src "ls180.v:228.5-228.49"
74585   wire $1\main_libresocsim_update_value_storage[0:0]
74586   attribute \src "ls180.v:248.12-248.42"
74587   wire width 32 $1\main_libresocsim_value[31:0]
74588   attribute \src "ls180.v:230.12-230.49"
74589   wire width 32 $1\main_libresocsim_value_status[31:0]
74590   attribute \src "ls180.v:220.11-220.37"
74591   wire width 4 $1\main_libresocsim_we[3:0]
74592   attribute \src "ls180.v:236.5-236.39"
74593   wire $1\main_libresocsim_zero_clear[0:0]
74594   attribute \src "ls180.v:237.5-237.45"
74595   wire $1\main_libresocsim_zero_old_trigger[0:0]
74596   attribute \src "ls180.v:234.5-234.41"
74597   wire $1\main_libresocsim_zero_pending[0:0]
74598   attribute \src "ls180.v:824.12-824.40"
74599   wire width 30 $1\main_litedram_wb_adr[29:0]
74600   attribute \src "ls180.v:828.5-828.32"
74601   wire $1\main_litedram_wb_cyc[0:0]
74602   attribute \src "ls180.v:825.12-825.42"
74603   wire width 16 $1\main_litedram_wb_dat_w[15:0]
74604   attribute \src "ls180.v:827.11-827.38"
74605   wire width 2 $1\main_litedram_wb_sel[1:0]
74606   attribute \src "ls180.v:829.5-829.32"
74607   wire $1\main_litedram_wb_stb[0:0]
74608   attribute \src "ls180.v:831.5-831.31"
74609   wire $1\main_litedram_wb_we[0:0]
74610   attribute \src "ls180.v:1071.12-1071.37"
74611   wire width 32 $1\main_pwm0_counter[31:0]
74612   attribute \src "ls180.v:1073.5-1073.31"
74613   wire $1\main_pwm0_enable_re[0:0]
74614   attribute \src "ls180.v:1072.5-1072.36"
74615   wire $1\main_pwm0_enable_storage[0:0]
74616   attribute \src "ls180.v:1077.5-1077.31"
74617   wire $1\main_pwm0_period_re[0:0]
74618   attribute \src "ls180.v:1076.12-1076.44"
74619   wire width 32 $1\main_pwm0_period_storage[31:0]
74620   attribute \src "ls180.v:1075.5-1075.30"
74621   wire $1\main_pwm0_width_re[0:0]
74622   attribute \src "ls180.v:1074.12-1074.43"
74623   wire width 32 $1\main_pwm0_width_storage[31:0]
74624   attribute \src "ls180.v:1081.12-1081.37"
74625   wire width 32 $1\main_pwm1_counter[31:0]
74626   attribute \src "ls180.v:1083.5-1083.31"
74627   wire $1\main_pwm1_enable_re[0:0]
74628   attribute \src "ls180.v:1082.5-1082.36"
74629   wire $1\main_pwm1_enable_storage[0:0]
74630   attribute \src "ls180.v:1087.5-1087.31"
74631   wire $1\main_pwm1_period_re[0:0]
74632   attribute \src "ls180.v:1086.12-1086.44"
74633   wire width 32 $1\main_pwm1_period_storage[31:0]
74634   attribute \src "ls180.v:1085.5-1085.30"
74635   wire $1\main_pwm1_width_re[0:0]
74636   attribute \src "ls180.v:1084.12-1084.43"
74637   wire width 32 $1\main_pwm1_width_storage[31:0]
74638   attribute \src "ls180.v:269.11-269.32"
74639   wire width 3 $1\main_rddata_en[2:0]
74640   attribute \src "ls180.v:1609.11-1609.50"
74641   wire width 2 $1\main_sdblock2mem_converter_demux[1:0]
74642   attribute \src "ls180.v:1605.5-1605.51"
74643   wire $1\main_sdblock2mem_converter_source_first[0:0]
74644   attribute \src "ls180.v:1606.5-1606.50"
74645   wire $1\main_sdblock2mem_converter_source_last[0:0]
74646   attribute \src "ls180.v:1607.12-1607.66"
74647   wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0]
74648   attribute \src "ls180.v:1608.11-1608.77"
74649   wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
74650   attribute \src "ls180.v:1611.5-1611.49"
74651   wire $1\main_sdblock2mem_converter_strobe_all[0:0]
74652   attribute \src "ls180.v:1584.11-1584.47"
74653   wire width 5 $1\main_sdblock2mem_fifo_consume[4:0]
74654   attribute \src "ls180.v:1581.11-1581.45"
74655   wire width 6 $1\main_sdblock2mem_fifo_level[5:0]
74656   attribute \src "ls180.v:1583.11-1583.47"
74657   wire width 5 $1\main_sdblock2mem_fifo_produce[4:0]
74658   attribute \src "ls180.v:1585.11-1585.50"
74659   wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0]
74660   attribute \src "ls180.v:1619.12-1619.62"
74661   wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0]
74662   attribute \src "ls180.v:1620.12-1620.60"
74663   wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
74664   attribute \src "ls180.v:1617.5-1617.45"
74665   wire $1\main_sdblock2mem_sink_sink_valid1[0:0]
74666   attribute \src "ls180.v:1627.5-1627.54"
74667   wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
74668   attribute \src "ls180.v:1626.12-1626.67"
74669   wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
74670   attribute \src "ls180.v:1631.5-1631.56"
74671   wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
74672   attribute \src "ls180.v:1630.5-1630.61"
74673   wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
74674   attribute \src "ls180.v:1629.5-1629.56"
74675   wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
74676   attribute \src "ls180.v:1628.12-1628.69"
74677   wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
74678   attribute \src "ls180.v:1635.5-1635.54"
74679   wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
74680   attribute \src "ls180.v:1634.5-1634.59"
74681   wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
74682   attribute \src "ls180.v:1637.12-1637.61"
74683   wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
74684   attribute \src "ls180.v:1857.12-1857.87"
74685   wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
74686   attribute \src "ls180.v:1858.5-1858.82"
74687   wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
74688   attribute \src "ls180.v:1622.5-1622.57"
74689   wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
74690   attribute \src "ls180.v:1632.5-1632.53"
74691   wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
74692   attribute \src "ls180.v:1401.5-1401.38"
74693   wire $1\main_sdcore_block_count_re[0:0]
74694   attribute \src "ls180.v:1400.12-1400.51"
74695   wire width 32 $1\main_sdcore_block_count_storage[31:0]
74696   attribute \src "ls180.v:1399.5-1399.39"
74697   wire $1\main_sdcore_block_length_re[0:0]
74698   attribute \src "ls180.v:1398.11-1398.51"
74699   wire width 10 $1\main_sdcore_block_length_storage[9:0]
74700   attribute \src "ls180.v:1385.5-1385.39"
74701   wire $1\main_sdcore_cmd_argument_re[0:0]
74702   attribute \src "ls180.v:1384.12-1384.52"
74703   wire width 32 $1\main_sdcore_cmd_argument_storage[31:0]
74704   attribute \src "ls180.v:1387.5-1387.38"
74705   wire $1\main_sdcore_cmd_command_re[0:0]
74706   attribute \src "ls180.v:1386.12-1386.51"
74707   wire width 32 $1\main_sdcore_cmd_command_storage[31:0]
74708   attribute \src "ls180.v:1540.11-1540.39"
74709   wire width 3 $1\main_sdcore_cmd_count[2:0]
74710   attribute \src "ls180.v:1841.11-1841.62"
74711   wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
74712   attribute \src "ls180.v:1842.5-1842.59"
74713   wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
74714   attribute \src "ls180.v:1541.5-1541.32"
74715   wire $1\main_sdcore_cmd_done[0:0]
74716   attribute \src "ls180.v:1837.5-1837.55"
74717   wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
74718   attribute \src "ls180.v:1838.5-1838.58"
74719   wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
74720   attribute \src "ls180.v:1542.5-1542.33"
74721   wire $1\main_sdcore_cmd_error[0:0]
74722   attribute \src "ls180.v:1845.5-1845.56"
74723   wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
74724   attribute \src "ls180.v:1846.5-1846.59"
74725   wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
74726   attribute \src "ls180.v:1392.13-1392.53"
74727   wire width 128 $1\main_sdcore_cmd_response_status[127:0]
74728   attribute \src "ls180.v:1853.13-1853.76"
74729   wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
74730   attribute \src "ls180.v:1854.5-1854.69"
74731   wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
74732   attribute \src "ls180.v:1543.5-1543.35"
74733   wire $1\main_sdcore_cmd_timeout[0:0]
74734   attribute \src "ls180.v:1847.5-1847.58"
74735   wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
74736   attribute \src "ls180.v:1848.5-1848.61"
74737   wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
74738   attribute \src "ls180.v:1501.11-1501.47"
74739   wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0]
74740   attribute \src "ls180.v:1507.5-1507.46"
74741   wire $1\main_sdcore_crc16_checker_crc0_clr[0:0]
74742   attribute \src "ls180.v:1506.12-1506.54"
74743   wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0]
74744   attribute \src "ls180.v:1502.12-1502.58"
74745   wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
74746   attribute \src "ls180.v:1514.5-1514.46"
74747   wire $1\main_sdcore_crc16_checker_crc1_clr[0:0]
74748   attribute \src "ls180.v:1513.12-1513.54"
74749   wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0]
74750   attribute \src "ls180.v:1509.12-1509.58"
74751   wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
74752   attribute \src "ls180.v:1521.5-1521.46"
74753   wire $1\main_sdcore_crc16_checker_crc2_clr[0:0]
74754   attribute \src "ls180.v:1520.12-1520.54"
74755   wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0]
74756   attribute \src "ls180.v:1516.12-1516.58"
74757   wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
74758   attribute \src "ls180.v:1528.5-1528.46"
74759   wire $1\main_sdcore_crc16_checker_crc3_clr[0:0]
74760   attribute \src "ls180.v:1527.12-1527.54"
74761   wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0]
74762   attribute \src "ls180.v:1523.12-1523.58"
74763   wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
74764   attribute \src "ls180.v:1530.12-1530.53"
74765   wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0]
74766   attribute \src "ls180.v:1531.12-1531.53"
74767   wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0]
74768   attribute \src "ls180.v:1532.12-1532.53"
74769   wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0]
74770   attribute \src "ls180.v:1533.12-1533.53"
74771   wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0]
74772   attribute \src "ls180.v:1535.12-1535.51"
74773   wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0]
74774   attribute \src "ls180.v:1536.12-1536.51"
74775   wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0]
74776   attribute \src "ls180.v:1537.12-1537.51"
74777   wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0]
74778   attribute \src "ls180.v:1538.12-1538.51"
74779   wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0]
74780   attribute \src "ls180.v:1492.5-1492.48"
74781   wire $1\main_sdcore_crc16_checker_sink_first[0:0]
74782   attribute \src "ls180.v:1493.5-1493.47"
74783   wire $1\main_sdcore_crc16_checker_sink_last[0:0]
74784   attribute \src "ls180.v:1494.11-1494.61"
74785   wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
74786   attribute \src "ls180.v:1491.5-1491.48"
74787   wire $1\main_sdcore_crc16_checker_sink_ready[0:0]
74788   attribute \src "ls180.v:1490.5-1490.48"
74789   wire $1\main_sdcore_crc16_checker_sink_valid[0:0]
74790   attribute \src "ls180.v:1495.5-1495.50"
74791   wire $1\main_sdcore_crc16_checker_source_valid[0:0]
74792   attribute \src "ls180.v:1500.11-1500.47"
74793   wire width 8 $1\main_sdcore_crc16_checker_val[7:0]
74794   attribute \src "ls180.v:1534.5-1534.43"
74795   wire $1\main_sdcore_crc16_checker_valid[0:0]
74796   attribute \src "ls180.v:1457.11-1457.48"
74797   wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0]
74798   attribute \src "ls180.v:1833.11-1833.87"
74799   wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
74800   attribute \src "ls180.v:1834.5-1834.84"
74801   wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
74802   attribute \src "ls180.v:1462.12-1462.55"
74803   wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
74804   attribute \src "ls180.v:1458.12-1458.59"
74805   wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
74806   attribute \src "ls180.v:1469.12-1469.55"
74807   wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
74808   attribute \src "ls180.v:1465.12-1465.59"
74809   wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
74810   attribute \src "ls180.v:1476.12-1476.55"
74811   wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
74812   attribute \src "ls180.v:1472.12-1472.59"
74813   wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
74814   attribute \src "ls180.v:1483.12-1483.55"
74815   wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
74816   attribute \src "ls180.v:1479.12-1479.59"
74817   wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
74818   attribute \src "ls180.v:1486.12-1486.54"
74819   wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
74820   attribute \src "ls180.v:1825.12-1825.93"
74821   wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
74822   attribute \src "ls180.v:1826.5-1826.88"
74823   wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
74824   attribute \src "ls180.v:1487.12-1487.54"
74825   wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
74826   attribute \src "ls180.v:1827.12-1827.93"
74827   wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
74828   attribute \src "ls180.v:1828.5-1828.88"
74829   wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
74830   attribute \src "ls180.v:1488.12-1488.54"
74831   wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
74832   attribute \src "ls180.v:1829.12-1829.93"
74833   wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
74834   attribute \src "ls180.v:1830.5-1830.88"
74835   wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
74836   attribute \src "ls180.v:1489.12-1489.54"
74837   wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
74838   attribute \src "ls180.v:1831.12-1831.93"
74839   wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
74840   attribute \src "ls180.v:1832.5-1832.88"
74841   wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
74842   attribute \src "ls180.v:1448.5-1448.49"
74843   wire $1\main_sdcore_crc16_inserter_sink_ready[0:0]
74844   attribute \src "ls180.v:1455.5-1455.50"
74845   wire $1\main_sdcore_crc16_inserter_source_last[0:0]
74846   attribute \src "ls180.v:1456.11-1456.64"
74847   wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
74848   attribute \src "ls180.v:1453.5-1453.51"
74849   wire $1\main_sdcore_crc16_inserter_source_ready[0:0]
74850   attribute \src "ls180.v:1452.5-1452.51"
74851   wire $1\main_sdcore_crc16_inserter_source_valid[0:0]
74852   attribute \src "ls180.v:1444.11-1444.47"
74853   wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0]
74854   attribute \src "ls180.v:1402.11-1402.51"
74855   wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
74856   attribute \src "ls180.v:1545.12-1545.42"
74857   wire width 32 $1\main_sdcore_data_count[31:0]
74858   attribute \src "ls180.v:1843.12-1843.65"
74859   wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
74860   attribute \src "ls180.v:1844.5-1844.60"
74861   wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
74862   attribute \src "ls180.v:1546.5-1546.33"
74863   wire $1\main_sdcore_data_done[0:0]
74864   attribute \src "ls180.v:1839.5-1839.56"
74865   wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
74866   attribute \src "ls180.v:1840.5-1840.59"
74867   wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
74868   attribute \src "ls180.v:1547.5-1547.34"
74869   wire $1\main_sdcore_data_error[0:0]
74870   attribute \src "ls180.v:1849.5-1849.57"
74871   wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
74872   attribute \src "ls180.v:1850.5-1850.60"
74873   wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
74874   attribute \src "ls180.v:1548.5-1548.36"
74875   wire $1\main_sdcore_data_timeout[0:0]
74876   attribute \src "ls180.v:1851.5-1851.59"
74877   wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
74878   attribute \src "ls180.v:1852.5-1852.62"
74879   wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
74880   attribute \src "ls180.v:1693.11-1693.48"
74881   wire width 2 $1\main_sdmem2block_converter_mux[1:0]
74882   attribute \src "ls180.v:1691.11-1691.64"
74883   wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0]
74884   attribute \src "ls180.v:1667.5-1667.40"
74885   wire $1\main_sdmem2block_dma_base_re[0:0]
74886   attribute \src "ls180.v:1666.12-1666.53"
74887   wire width 64 $1\main_sdmem2block_dma_base_storage[63:0]
74888   attribute \src "ls180.v:1665.12-1665.45"
74889   wire width 32 $1\main_sdmem2block_dma_data[31:0]
74890   attribute \src "ls180.v:1861.12-1861.75"
74891   wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
74892   attribute \src "ls180.v:1862.5-1862.70"
74893   wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
74894   attribute \src "ls180.v:1672.5-1672.44"
74895   wire $1\main_sdmem2block_dma_done_status[0:0]
74896   attribute \src "ls180.v:1671.5-1671.42"
74897   wire $1\main_sdmem2block_dma_enable_re[0:0]
74898   attribute \src "ls180.v:1670.5-1670.47"
74899   wire $1\main_sdmem2block_dma_enable_storage[0:0]
74900   attribute \src "ls180.v:1669.5-1669.42"
74901   wire $1\main_sdmem2block_dma_length_re[0:0]
74902   attribute \src "ls180.v:1668.12-1668.55"
74903   wire width 32 $1\main_sdmem2block_dma_length_storage[31:0]
74904   attribute \src "ls180.v:1675.5-1675.40"
74905   wire $1\main_sdmem2block_dma_loop_re[0:0]
74906   attribute \src "ls180.v:1674.5-1674.45"
74907   wire $1\main_sdmem2block_dma_loop_storage[0:0]
74908   attribute \src "ls180.v:1679.12-1679.47"
74909   wire width 32 $1\main_sdmem2block_dma_offset[31:0]
74910   attribute \src "ls180.v:1865.12-1865.87"
74911   wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
74912   attribute \src "ls180.v:1866.5-1866.82"
74913   wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
74914   attribute \src "ls180.v:1658.5-1658.42"
74915   wire $1\main_sdmem2block_dma_sink_last[0:0]
74916   attribute \src "ls180.v:1659.12-1659.61"
74917   wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0]
74918   attribute \src "ls180.v:1657.5-1657.43"
74919   wire $1\main_sdmem2block_dma_sink_ready[0:0]
74920   attribute \src "ls180.v:1656.5-1656.43"
74921   wire $1\main_sdmem2block_dma_sink_valid[0:0]
74922   attribute \src "ls180.v:1663.5-1663.44"
74923   wire $1\main_sdmem2block_dma_source_last[0:0]
74924   attribute \src "ls180.v:1664.12-1664.60"
74925   wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0]
74926   attribute \src "ls180.v:1660.5-1660.45"
74927   wire $1\main_sdmem2block_dma_source_valid[0:0]
74928   attribute \src "ls180.v:1720.11-1720.47"
74929   wire width 5 $1\main_sdmem2block_fifo_consume[4:0]
74930   attribute \src "ls180.v:1717.11-1717.45"
74931   wire width 6 $1\main_sdmem2block_fifo_level[5:0]
74932   attribute \src "ls180.v:1719.11-1719.47"
74933   wire width 5 $1\main_sdmem2block_fifo_produce[4:0]
74934   attribute \src "ls180.v:1721.11-1721.50"
74935   wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0]
74936   attribute \src "ls180.v:1101.5-1101.35"
74937   wire $1\main_sdphy_clocker_clk0[0:0]
74938   attribute \src "ls180.v:1104.5-1104.35"
74939   wire $1\main_sdphy_clocker_clk1[0:0]
74940   attribute \src "ls180.v:1105.5-1105.36"
74941   wire $1\main_sdphy_clocker_clk_d[0:0]
74942   attribute \src "ls180.v:1103.11-1103.41"
74943   wire width 9 $1\main_sdphy_clocker_clks[8:0]
74944   attribute \src "ls180.v:1099.5-1099.33"
74945   wire $1\main_sdphy_clocker_re[0:0]
74946   attribute \src "ls180.v:1098.11-1098.46"
74947   wire width 9 $1\main_sdphy_clocker_storage[8:0]
74948   attribute \src "ls180.v:1207.5-1207.49"
74949   wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
74950   attribute \src "ls180.v:1208.5-1208.48"
74951   wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
74952   attribute \src "ls180.v:1209.11-1209.62"
74953   wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
74954   attribute \src "ls180.v:1205.5-1205.49"
74955   wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
74956   attribute \src "ls180.v:1192.11-1192.54"
74957   wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
74958   attribute \src "ls180.v:1188.5-1188.55"
74959   wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
74960   attribute \src "ls180.v:1189.5-1189.54"
74961   wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
74962   attribute \src "ls180.v:1190.11-1190.68"
74963   wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
74964   attribute \src "ls180.v:1191.11-1191.81"
74965   wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
74966   attribute \src "ls180.v:1194.5-1194.53"
74967   wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
74968   attribute \src "ls180.v:1210.5-1210.38"
74969   wire $1\main_sdphy_cmdr_cmdr_reset[0:0]
74970   attribute \src "ls180.v:1805.5-1805.66"
74971   wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
74972   attribute \src "ls180.v:1806.5-1806.69"
74973   wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
74974   attribute \src "ls180.v:1180.5-1180.36"
74975   wire $1\main_sdphy_cmdr_cmdr_run[0:0]
74976   attribute \src "ls180.v:1175.5-1175.53"
74977   wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
74978   attribute \src "ls180.v:1162.11-1162.39"
74979   wire width 8 $1\main_sdphy_cmdr_count[7:0]
74980   attribute \src "ls180.v:1801.11-1801.67"
74981   wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
74982   attribute \src "ls180.v:1802.5-1802.64"
74983   wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
74984   attribute \src "ls180.v:1147.5-1147.48"
74985   wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
74986   attribute \src "ls180.v:1148.5-1148.50"
74987   wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
74988   attribute \src "ls180.v:1149.5-1149.51"
74989   wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
74990   attribute \src "ls180.v:1154.5-1154.37"
74991   wire $1\main_sdphy_cmdr_sink_last[0:0]
74992   attribute \src "ls180.v:1155.11-1155.53"
74993   wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0]
74994   attribute \src "ls180.v:1153.5-1153.38"
74995   wire $1\main_sdphy_cmdr_sink_ready[0:0]
74996   attribute \src "ls180.v:1152.5-1152.38"
74997   wire $1\main_sdphy_cmdr_sink_valid[0:0]
74998   attribute \src "ls180.v:1158.5-1158.39"
74999   wire $1\main_sdphy_cmdr_source_last[0:0]
75000   attribute \src "ls180.v:1159.11-1159.53"
75001   wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0]
75002   attribute \src "ls180.v:1160.11-1160.55"
75003   wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0]
75004   attribute \src "ls180.v:1157.5-1157.40"
75005   wire $1\main_sdphy_cmdr_source_ready[0:0]
75006   attribute \src "ls180.v:1156.5-1156.40"
75007   wire $1\main_sdphy_cmdr_source_valid[0:0]
75008   attribute \src "ls180.v:1161.12-1161.48"
75009   wire width 32 $1\main_sdphy_cmdr_timeout[31:0]
75010   attribute \src "ls180.v:1803.12-1803.71"
75011   wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
75012   attribute \src "ls180.v:1804.5-1804.66"
75013   wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
75014   attribute \src "ls180.v:1134.11-1134.39"
75015   wire width 8 $1\main_sdphy_cmdw_count[7:0]
75016   attribute \src "ls180.v:1797.11-1797.66"
75017   wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
75018   attribute \src "ls180.v:1798.5-1798.63"
75019   wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
75020   attribute \src "ls180.v:1133.5-1133.32"
75021   wire $1\main_sdphy_cmdw_done[0:0]
75022   attribute \src "ls180.v:1124.5-1124.48"
75023   wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
75024   attribute \src "ls180.v:1125.5-1125.50"
75025   wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
75026   attribute \src "ls180.v:1126.5-1126.51"
75027   wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
75028   attribute \src "ls180.v:1131.5-1131.37"
75029   wire $1\main_sdphy_cmdw_sink_last[0:0]
75030   attribute \src "ls180.v:1132.11-1132.51"
75031   wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0]
75032   attribute \src "ls180.v:1130.5-1130.38"
75033   wire $1\main_sdphy_cmdw_sink_ready[0:0]
75034   attribute \src "ls180.v:1129.5-1129.38"
75035   wire $1\main_sdphy_cmdw_sink_valid[0:0]
75036   attribute \src "ls180.v:1318.11-1318.41"
75037   wire width 10 $1\main_sdphy_datar_count[9:0]
75038   attribute \src "ls180.v:1817.11-1817.70"
75039   wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
75040   attribute \src "ls180.v:1818.5-1818.66"
75041   wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
75042   attribute \src "ls180.v:1363.5-1363.51"
75043   wire $1\main_sdphy_datar_datar_buf_source_first[0:0]
75044   attribute \src "ls180.v:1364.5-1364.50"
75045   wire $1\main_sdphy_datar_datar_buf_source_last[0:0]
75046   attribute \src "ls180.v:1365.11-1365.64"
75047   wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
75048   attribute \src "ls180.v:1361.5-1361.51"
75049   wire $1\main_sdphy_datar_datar_buf_source_valid[0:0]
75050   attribute \src "ls180.v:1348.5-1348.50"
75051   wire $1\main_sdphy_datar_datar_converter_demux[0:0]
75052   attribute \src "ls180.v:1344.5-1344.57"
75053   wire $1\main_sdphy_datar_datar_converter_source_first[0:0]
75054   attribute \src "ls180.v:1345.5-1345.56"
75055   wire $1\main_sdphy_datar_datar_converter_source_last[0:0]
75056   attribute \src "ls180.v:1346.11-1346.70"
75057   wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
75058   attribute \src "ls180.v:1347.11-1347.83"
75059   wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
75060   attribute \src "ls180.v:1350.5-1350.55"
75061   wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
75062   attribute \src "ls180.v:1366.5-1366.40"
75063   wire $1\main_sdphy_datar_datar_reset[0:0]
75064   attribute \src "ls180.v:1821.5-1821.69"
75065   wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
75066   attribute \src "ls180.v:1822.5-1822.72"
75067   wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
75068   attribute \src "ls180.v:1336.5-1336.38"
75069   wire $1\main_sdphy_datar_datar_run[0:0]
75070   attribute \src "ls180.v:1331.5-1331.55"
75071   wire $1\main_sdphy_datar_datar_source_source_ready0[0:0]
75072   attribute \src "ls180.v:1301.5-1301.49"
75073   wire $1\main_sdphy_datar_pads_out_payload_clk[0:0]
75074   attribute \src "ls180.v:1308.5-1308.38"
75075   wire $1\main_sdphy_datar_sink_last[0:0]
75076   attribute \src "ls180.v:1309.11-1309.61"
75077   wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0]
75078   attribute \src "ls180.v:1307.5-1307.39"
75079   wire $1\main_sdphy_datar_sink_ready[0:0]
75080   attribute \src "ls180.v:1306.5-1306.39"
75081   wire $1\main_sdphy_datar_sink_valid[0:0]
75082   attribute \src "ls180.v:1313.5-1313.40"
75083   wire $1\main_sdphy_datar_source_last[0:0]
75084   attribute \src "ls180.v:1314.11-1314.54"
75085   wire width 8 $1\main_sdphy_datar_source_payload_data[7:0]
75086   attribute \src "ls180.v:1315.11-1315.56"
75087   wire width 3 $1\main_sdphy_datar_source_payload_status[2:0]
75088   attribute \src "ls180.v:1311.5-1311.41"
75089   wire $1\main_sdphy_datar_source_ready[0:0]
75090   attribute \src "ls180.v:1310.5-1310.41"
75091   wire $1\main_sdphy_datar_source_valid[0:0]
75092   attribute \src "ls180.v:1316.5-1316.33"
75093   wire $1\main_sdphy_datar_stop[0:0]
75094   attribute \src "ls180.v:1317.12-1317.49"
75095   wire width 32 $1\main_sdphy_datar_timeout[31:0]
75096   attribute \src "ls180.v:1819.12-1819.73"
75097   wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
75098   attribute \src "ls180.v:1820.5-1820.68"
75099   wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
75100   attribute \src "ls180.v:1226.11-1226.40"
75101   wire width 8 $1\main_sdphy_dataw_count[7:0]
75102   attribute \src "ls180.v:1813.11-1813.61"
75103   wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
75104   attribute \src "ls180.v:1814.5-1814.58"
75105   wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
75106   attribute \src "ls180.v:1285.5-1285.50"
75107   wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
75108   attribute \src "ls180.v:1286.5-1286.49"
75109   wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
75110   attribute \src "ls180.v:1287.11-1287.63"
75111   wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
75112   attribute \src "ls180.v:1283.5-1283.50"
75113   wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
75114   attribute \src "ls180.v:1270.11-1270.55"
75115   wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0]
75116   attribute \src "ls180.v:1266.5-1266.56"
75117   wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
75118   attribute \src "ls180.v:1267.5-1267.55"
75119   wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
75120   attribute \src "ls180.v:1268.11-1268.69"
75121   wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
75122   attribute \src "ls180.v:1269.11-1269.82"
75123   wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
75124   attribute \src "ls180.v:1272.5-1272.54"
75125   wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
75126   attribute \src "ls180.v:1288.5-1288.39"
75127   wire $1\main_sdphy_dataw_crcr_reset[0:0]
75128   attribute \src "ls180.v:1809.5-1809.66"
75129   wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
75130   attribute \src "ls180.v:1810.5-1810.69"
75131   wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
75132   attribute \src "ls180.v:1258.5-1258.37"
75133   wire $1\main_sdphy_dataw_crcr_run[0:0]
75134   attribute \src "ls180.v:1253.5-1253.54"
75135   wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
75136   attribute \src "ls180.v:1240.5-1240.34"
75137   wire $1\main_sdphy_dataw_error[0:0]
75138   attribute \src "ls180.v:1215.5-1215.49"
75139   wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
75140   attribute \src "ls180.v:1218.11-1218.58"
75141   wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
75142   attribute \src "ls180.v:1219.5-1219.53"
75143   wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
75144   attribute \src "ls180.v:1222.5-1222.39"
75145   wire $1\main_sdphy_dataw_sink_first[0:0]
75146   attribute \src "ls180.v:1223.5-1223.38"
75147   wire $1\main_sdphy_dataw_sink_last[0:0]
75148   attribute \src "ls180.v:1224.11-1224.52"
75149   wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0]
75150   attribute \src "ls180.v:1221.5-1221.39"
75151   wire $1\main_sdphy_dataw_sink_ready[0:0]
75152   attribute \src "ls180.v:1220.5-1220.39"
75153   wire $1\main_sdphy_dataw_sink_valid[0:0]
75154   attribute \src "ls180.v:1238.5-1238.34"
75155   wire $1\main_sdphy_dataw_start[0:0]
75156   attribute \src "ls180.v:1225.5-1225.33"
75157   wire $1\main_sdphy_dataw_stop[0:0]
75158   attribute \src "ls180.v:1239.5-1239.34"
75159   wire $1\main_sdphy_dataw_valid[0:0]
75160   attribute \src "ls180.v:1119.11-1119.39"
75161   wire width 8 $1\main_sdphy_init_count[7:0]
75162   attribute \src "ls180.v:1793.11-1793.66"
75163   wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
75164   attribute \src "ls180.v:1794.5-1794.63"
75165   wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
75166   attribute \src "ls180.v:1114.5-1114.48"
75167   wire $1\main_sdphy_init_pads_out_payload_clk[0:0]
75168   attribute \src "ls180.v:1115.5-1115.50"
75169   wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
75170   attribute \src "ls180.v:1116.5-1116.51"
75171   wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
75172   attribute \src "ls180.v:1117.11-1117.57"
75173   wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0]
75174   attribute \src "ls180.v:1118.5-1118.52"
75175   wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
75176   attribute \src "ls180.v:1368.5-1368.35"
75177   wire $1\main_sdphy_sdpads_cmd_i[0:0]
75178   attribute \src "ls180.v:1371.11-1371.42"
75179   wire width 4 $1\main_sdphy_sdpads_data_i[3:0]
75180   attribute \src "ls180.v:331.5-331.33"
75181   wire $1\main_sdram_address_re[0:0]
75182   attribute \src "ls180.v:330.12-330.46"
75183   wire width 13 $1\main_sdram_address_storage[12:0]
75184   attribute \src "ls180.v:333.5-333.34"
75185   wire $1\main_sdram_baddress_re[0:0]
75186   attribute \src "ls180.v:332.11-332.45"
75187   wire width 2 $1\main_sdram_baddress_storage[1:0]
75188   attribute \src "ls180.v:429.5-429.50"
75189   wire $1\main_sdram_bankmachine0_auto_precharge[0:0]
75190   attribute \src "ls180.v:451.11-451.70"
75191   wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
75192   attribute \src "ls180.v:448.11-448.68"
75193   wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
75194   attribute \src "ls180.v:450.11-450.70"
75195   wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
75196   attribute \src "ls180.v:452.11-452.73"
75197   wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
75198   attribute \src "ls180.v:475.5-475.59"
75199   wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
75200   attribute \src "ls180.v:476.5-476.58"
75201   wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
75202   attribute \src "ls180.v:478.12-478.74"
75203   wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
75204   attribute \src "ls180.v:477.5-477.64"
75205   wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
75206   attribute \src "ls180.v:473.5-473.59"
75207   wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
75208   attribute \src "ls180.v:421.12-421.57"
75209   wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
75210   attribute \src "ls180.v:423.5-423.51"
75211   wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
75212   attribute \src "ls180.v:426.5-426.54"
75213   wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
75214   attribute \src "ls180.v:427.5-427.55"
75215   wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
75216   attribute \src "ls180.v:428.5-428.56"
75217   wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
75218   attribute \src "ls180.v:424.5-424.51"
75219   wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
75220   attribute \src "ls180.v:425.5-425.50"
75221   wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
75222   attribute \src "ls180.v:420.5-420.45"
75223   wire $1\main_sdram_bankmachine0_cmd_ready[0:0]
75224   attribute \src "ls180.v:419.5-419.45"
75225   wire $1\main_sdram_bankmachine0_cmd_valid[0:0]
75226   attribute \src "ls180.v:418.5-418.47"
75227   wire $1\main_sdram_bankmachine0_refresh_gnt[0:0]
75228   attribute \src "ls180.v:416.5-416.51"
75229   wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
75230   attribute \src "ls180.v:415.5-415.51"
75231   wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
75232   attribute \src "ls180.v:479.12-479.47"
75233   wire width 13 $1\main_sdram_bankmachine0_row[12:0]
75234   attribute \src "ls180.v:483.5-483.45"
75235   wire $1\main_sdram_bankmachine0_row_close[0:0]
75236   attribute \src "ls180.v:484.5-484.54"
75237   wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
75238   attribute \src "ls180.v:482.5-482.44"
75239   wire $1\main_sdram_bankmachine0_row_open[0:0]
75240   attribute \src "ls180.v:480.5-480.46"
75241   wire $1\main_sdram_bankmachine0_row_opened[0:0]
75242   attribute \src "ls180.v:487.11-487.55"
75243   wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0]
75244   attribute \src "ls180.v:486.32-486.76"
75245   wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
75246   attribute \src "ls180.v:511.5-511.50"
75247   wire $1\main_sdram_bankmachine1_auto_precharge[0:0]
75248   attribute \src "ls180.v:533.11-533.70"
75249   wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
75250   attribute \src "ls180.v:530.11-530.68"
75251   wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
75252   attribute \src "ls180.v:532.11-532.70"
75253   wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
75254   attribute \src "ls180.v:534.11-534.73"
75255   wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
75256   attribute \src "ls180.v:557.5-557.59"
75257   wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
75258   attribute \src "ls180.v:558.5-558.58"
75259   wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
75260   attribute \src "ls180.v:560.12-560.74"
75261   wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
75262   attribute \src "ls180.v:559.5-559.64"
75263   wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
75264   attribute \src "ls180.v:555.5-555.59"
75265   wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
75266   attribute \src "ls180.v:503.12-503.57"
75267   wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
75268   attribute \src "ls180.v:505.5-505.51"
75269   wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
75270   attribute \src "ls180.v:508.5-508.54"
75271   wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
75272   attribute \src "ls180.v:509.5-509.55"
75273   wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
75274   attribute \src "ls180.v:510.5-510.56"
75275   wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
75276   attribute \src "ls180.v:506.5-506.51"
75277   wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
75278   attribute \src "ls180.v:507.5-507.50"
75279   wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
75280   attribute \src "ls180.v:502.5-502.45"
75281   wire $1\main_sdram_bankmachine1_cmd_ready[0:0]
75282   attribute \src "ls180.v:501.5-501.45"
75283   wire $1\main_sdram_bankmachine1_cmd_valid[0:0]
75284   attribute \src "ls180.v:500.5-500.47"
75285   wire $1\main_sdram_bankmachine1_refresh_gnt[0:0]
75286   attribute \src "ls180.v:498.5-498.51"
75287   wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
75288   attribute \src "ls180.v:497.5-497.51"
75289   wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
75290   attribute \src "ls180.v:561.12-561.47"
75291   wire width 13 $1\main_sdram_bankmachine1_row[12:0]
75292   attribute \src "ls180.v:565.5-565.45"
75293   wire $1\main_sdram_bankmachine1_row_close[0:0]
75294   attribute \src "ls180.v:566.5-566.54"
75295   wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
75296   attribute \src "ls180.v:564.5-564.44"
75297   wire $1\main_sdram_bankmachine1_row_open[0:0]
75298   attribute \src "ls180.v:562.5-562.46"
75299   wire $1\main_sdram_bankmachine1_row_opened[0:0]
75300   attribute \src "ls180.v:569.11-569.55"
75301   wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0]
75302   attribute \src "ls180.v:568.32-568.76"
75303   wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
75304   attribute \src "ls180.v:593.5-593.50"
75305   wire $1\main_sdram_bankmachine2_auto_precharge[0:0]
75306   attribute \src "ls180.v:615.11-615.70"
75307   wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
75308   attribute \src "ls180.v:612.11-612.68"
75309   wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
75310   attribute \src "ls180.v:614.11-614.70"
75311   wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
75312   attribute \src "ls180.v:616.11-616.73"
75313   wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
75314   attribute \src "ls180.v:639.5-639.59"
75315   wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
75316   attribute \src "ls180.v:640.5-640.58"
75317   wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
75318   attribute \src "ls180.v:642.12-642.74"
75319   wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
75320   attribute \src "ls180.v:641.5-641.64"
75321   wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
75322   attribute \src "ls180.v:637.5-637.59"
75323   wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
75324   attribute \src "ls180.v:585.12-585.57"
75325   wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
75326   attribute \src "ls180.v:587.5-587.51"
75327   wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
75328   attribute \src "ls180.v:590.5-590.54"
75329   wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
75330   attribute \src "ls180.v:591.5-591.55"
75331   wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
75332   attribute \src "ls180.v:592.5-592.56"
75333   wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
75334   attribute \src "ls180.v:588.5-588.51"
75335   wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
75336   attribute \src "ls180.v:589.5-589.50"
75337   wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
75338   attribute \src "ls180.v:584.5-584.45"
75339   wire $1\main_sdram_bankmachine2_cmd_ready[0:0]
75340   attribute \src "ls180.v:583.5-583.45"
75341   wire $1\main_sdram_bankmachine2_cmd_valid[0:0]
75342   attribute \src "ls180.v:582.5-582.47"
75343   wire $1\main_sdram_bankmachine2_refresh_gnt[0:0]
75344   attribute \src "ls180.v:580.5-580.51"
75345   wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
75346   attribute \src "ls180.v:579.5-579.51"
75347   wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
75348   attribute \src "ls180.v:643.12-643.47"
75349   wire width 13 $1\main_sdram_bankmachine2_row[12:0]
75350   attribute \src "ls180.v:647.5-647.45"
75351   wire $1\main_sdram_bankmachine2_row_close[0:0]
75352   attribute \src "ls180.v:648.5-648.54"
75353   wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
75354   attribute \src "ls180.v:646.5-646.44"
75355   wire $1\main_sdram_bankmachine2_row_open[0:0]
75356   attribute \src "ls180.v:644.5-644.46"
75357   wire $1\main_sdram_bankmachine2_row_opened[0:0]
75358   attribute \src "ls180.v:651.11-651.55"
75359   wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0]
75360   attribute \src "ls180.v:650.32-650.76"
75361   wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
75362   attribute \src "ls180.v:675.5-675.50"
75363   wire $1\main_sdram_bankmachine3_auto_precharge[0:0]
75364   attribute \src "ls180.v:697.11-697.70"
75365   wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
75366   attribute \src "ls180.v:694.11-694.68"
75367   wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
75368   attribute \src "ls180.v:696.11-696.70"
75369   wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
75370   attribute \src "ls180.v:698.11-698.73"
75371   wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
75372   attribute \src "ls180.v:721.5-721.59"
75373   wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
75374   attribute \src "ls180.v:722.5-722.58"
75375   wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
75376   attribute \src "ls180.v:724.12-724.74"
75377   wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
75378   attribute \src "ls180.v:723.5-723.64"
75379   wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
75380   attribute \src "ls180.v:719.5-719.59"
75381   wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
75382   attribute \src "ls180.v:667.12-667.57"
75383   wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
75384   attribute \src "ls180.v:669.5-669.51"
75385   wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
75386   attribute \src "ls180.v:672.5-672.54"
75387   wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
75388   attribute \src "ls180.v:673.5-673.55"
75389   wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
75390   attribute \src "ls180.v:674.5-674.56"
75391   wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
75392   attribute \src "ls180.v:670.5-670.51"
75393   wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
75394   attribute \src "ls180.v:671.5-671.50"
75395   wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
75396   attribute \src "ls180.v:666.5-666.45"
75397   wire $1\main_sdram_bankmachine3_cmd_ready[0:0]
75398   attribute \src "ls180.v:665.5-665.45"
75399   wire $1\main_sdram_bankmachine3_cmd_valid[0:0]
75400   attribute \src "ls180.v:664.5-664.47"
75401   wire $1\main_sdram_bankmachine3_refresh_gnt[0:0]
75402   attribute \src "ls180.v:662.5-662.51"
75403   wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
75404   attribute \src "ls180.v:661.5-661.51"
75405   wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
75406   attribute \src "ls180.v:725.12-725.47"
75407   wire width 13 $1\main_sdram_bankmachine3_row[12:0]
75408   attribute \src "ls180.v:729.5-729.45"
75409   wire $1\main_sdram_bankmachine3_row_close[0:0]
75410   attribute \src "ls180.v:730.5-730.54"
75411   wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
75412   attribute \src "ls180.v:728.5-728.44"
75413   wire $1\main_sdram_bankmachine3_row_open[0:0]
75414   attribute \src "ls180.v:726.5-726.46"
75415   wire $1\main_sdram_bankmachine3_row_opened[0:0]
75416   attribute \src "ls180.v:733.11-733.55"
75417   wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0]
75418   attribute \src "ls180.v:732.32-732.76"
75419   wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
75420   attribute \src "ls180.v:748.5-748.49"
75421   wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
75422   attribute \src "ls180.v:749.5-749.49"
75423   wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
75424   attribute \src "ls180.v:750.5-750.48"
75425   wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
75426   attribute \src "ls180.v:756.11-756.45"
75427   wire width 2 $1\main_sdram_choose_cmd_grant[1:0]
75428   attribute \src "ls180.v:754.11-754.46"
75429   wire width 4 $1\main_sdram_choose_cmd_valids[3:0]
75430   attribute \src "ls180.v:766.5-766.49"
75431   wire $1\main_sdram_choose_req_cmd_payload_cas[0:0]
75432   attribute \src "ls180.v:767.5-767.49"
75433   wire $1\main_sdram_choose_req_cmd_payload_ras[0:0]
75434   attribute \src "ls180.v:768.5-768.48"
75435   wire $1\main_sdram_choose_req_cmd_payload_we[0:0]
75436   attribute \src "ls180.v:763.5-763.43"
75437   wire $1\main_sdram_choose_req_cmd_ready[0:0]
75438   attribute \src "ls180.v:774.11-774.45"
75439   wire width 2 $1\main_sdram_choose_req_grant[1:0]
75440   attribute \src "ls180.v:772.11-772.46"
75441   wire width 4 $1\main_sdram_choose_req_valids[3:0]
75442   attribute \src "ls180.v:761.5-761.48"
75443   wire $1\main_sdram_choose_req_want_activates[0:0]
75444   attribute \src "ls180.v:758.5-758.44"
75445   wire $1\main_sdram_choose_req_want_reads[0:0]
75446   attribute \src "ls180.v:759.5-759.45"
75447   wire $1\main_sdram_choose_req_want_writes[0:0]
75448   attribute \src "ls180.v:387.5-387.31"
75449   wire $1\main_sdram_cmd_last[0:0]
75450   attribute \src "ls180.v:388.12-388.44"
75451   wire width 13 $1\main_sdram_cmd_payload_a[12:0]
75452   attribute \src "ls180.v:389.11-389.43"
75453   wire width 2 $1\main_sdram_cmd_payload_ba[1:0]
75454   attribute \src "ls180.v:390.5-390.38"
75455   wire $1\main_sdram_cmd_payload_cas[0:0]
75456   attribute \src "ls180.v:391.5-391.38"
75457   wire $1\main_sdram_cmd_payload_ras[0:0]
75458   attribute \src "ls180.v:392.5-392.37"
75459   wire $1\main_sdram_cmd_payload_we[0:0]
75460   attribute \src "ls180.v:386.5-386.32"
75461   wire $1\main_sdram_cmd_ready[0:0]
75462   attribute \src "ls180.v:385.5-385.32"
75463   wire $1\main_sdram_cmd_valid[0:0]
75464   attribute \src "ls180.v:325.5-325.33"
75465   wire $1\main_sdram_command_re[0:0]
75466   attribute \src "ls180.v:324.11-324.44"
75467   wire width 6 $1\main_sdram_command_storage[5:0]
75468   attribute \src "ls180.v:369.12-369.45"
75469   wire width 13 $1\main_sdram_dfi_p0_address[12:0]
75470   attribute \src "ls180.v:370.11-370.40"
75471   wire width 2 $1\main_sdram_dfi_p0_bank[1:0]
75472   attribute \src "ls180.v:371.5-371.35"
75473   wire $1\main_sdram_dfi_p0_cas_n[0:0]
75474   attribute \src "ls180.v:372.5-372.34"
75475   wire $1\main_sdram_dfi_p0_cs_n[0:0]
75476   attribute \src "ls180.v:373.5-373.35"
75477   wire $1\main_sdram_dfi_p0_ras_n[0:0]
75478   attribute \src "ls180.v:382.5-382.39"
75479   wire $1\main_sdram_dfi_p0_rddata_en[0:0]
75480   attribute \src "ls180.v:374.5-374.34"
75481   wire $1\main_sdram_dfi_p0_we_n[0:0]
75482   attribute \src "ls180.v:380.5-380.39"
75483   wire $1\main_sdram_dfi_p0_wrdata_en[0:0]
75484   attribute \src "ls180.v:793.5-793.26"
75485   wire $1\main_sdram_en0[0:0]
75486   attribute \src "ls180.v:796.5-796.26"
75487   wire $1\main_sdram_en1[0:0]
75488   attribute \src "ls180.v:366.12-366.46"
75489   wire width 16 $1\main_sdram_interface_wdata[15:0]
75490   attribute \src "ls180.v:367.11-367.47"
75491   wire width 2 $1\main_sdram_interface_wdata_we[1:0]
75492   attribute \src "ls180.v:272.5-272.36"
75493   wire $1\main_sdram_inti_p0_cas_n[0:0]
75494   attribute \src "ls180.v:273.5-273.35"
75495   wire $1\main_sdram_inti_p0_cs_n[0:0]
75496   attribute \src "ls180.v:274.5-274.36"
75497   wire $1\main_sdram_inti_p0_ras_n[0:0]
75498   attribute \src "ls180.v:284.12-284.45"
75499   wire width 16 $1\main_sdram_inti_p0_rddata[15:0]
75500   attribute \src "ls180.v:285.5-285.43"
75501   wire $1\main_sdram_inti_p0_rddata_valid[0:0]
75502   attribute \src "ls180.v:275.5-275.35"
75503   wire $1\main_sdram_inti_p0_we_n[0:0]
75504   attribute \src "ls180.v:311.5-311.38"
75505   wire $1\main_sdram_master_p0_act_n[0:0]
75506   attribute \src "ls180.v:302.12-302.48"
75507   wire width 13 $1\main_sdram_master_p0_address[12:0]
75508   attribute \src "ls180.v:303.11-303.43"
75509   wire width 2 $1\main_sdram_master_p0_bank[1:0]
75510   attribute \src "ls180.v:304.5-304.38"
75511   wire $1\main_sdram_master_p0_cas_n[0:0]
75512   attribute \src "ls180.v:308.5-308.36"
75513   wire $1\main_sdram_master_p0_cke[0:0]
75514   attribute \src "ls180.v:305.5-305.37"
75515   wire $1\main_sdram_master_p0_cs_n[0:0]
75516   attribute \src "ls180.v:309.5-309.36"
75517   wire $1\main_sdram_master_p0_odt[0:0]
75518   attribute \src "ls180.v:306.5-306.38"
75519   wire $1\main_sdram_master_p0_ras_n[0:0]
75520   attribute \src "ls180.v:315.5-315.42"
75521   wire $1\main_sdram_master_p0_rddata_en[0:0]
75522   attribute \src "ls180.v:310.5-310.40"
75523   wire $1\main_sdram_master_p0_reset_n[0:0]
75524   attribute \src "ls180.v:307.5-307.37"
75525   wire $1\main_sdram_master_p0_we_n[0:0]
75526   attribute \src "ls180.v:312.12-312.47"
75527   wire width 16 $1\main_sdram_master_p0_wrdata[15:0]
75528   attribute \src "ls180.v:313.5-313.42"
75529   wire $1\main_sdram_master_p0_wrdata_en[0:0]
75530   attribute \src "ls180.v:314.11-314.50"
75531   wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0]
75532   attribute \src "ls180.v:403.5-403.38"
75533   wire $1\main_sdram_postponer_count[0:0]
75534   attribute \src "ls180.v:402.5-402.38"
75535   wire $1\main_sdram_postponer_req_o[0:0]
75536   attribute \src "ls180.v:323.5-323.25"
75537   wire $1\main_sdram_re[0:0]
75538   attribute \src "ls180.v:409.5-409.38"
75539   wire $1\main_sdram_sequencer_count[0:0]
75540   attribute \src "ls180.v:408.11-408.46"
75541   wire width 4 $1\main_sdram_sequencer_counter[3:0]
75542   attribute \src "ls180.v:407.5-407.38"
75543   wire $1\main_sdram_sequencer_done1[0:0]
75544   attribute \src "ls180.v:404.5-404.39"
75545   wire $1\main_sdram_sequencer_start0[0:0]
75546   attribute \src "ls180.v:300.12-300.46"
75547   wire width 16 $1\main_sdram_slave_p0_rddata[15:0]
75548   attribute \src "ls180.v:301.5-301.44"
75549   wire $1\main_sdram_slave_p0_rddata_valid[0:0]
75550   attribute \src "ls180.v:336.12-336.37"
75551   wire width 16 $1\main_sdram_status[15:0]
75552   attribute \src "ls180.v:778.11-778.40"
75553   wire width 2 $1\main_sdram_steerer_sel[1:0]
75554   attribute \src "ls180.v:322.11-322.36"
75555   wire width 4 $1\main_sdram_storage[3:0]
75556   attribute \src "ls180.v:787.5-787.36"
75557   wire $1\main_sdram_tccdcon_count[0:0]
75558   attribute \src "ls180.v:786.32-786.63"
75559   wire $1\main_sdram_tccdcon_ready[0:0]
75560   attribute \src "ls180.v:795.11-795.34"
75561   wire width 5 $1\main_sdram_time0[4:0]
75562   attribute \src "ls180.v:798.11-798.34"
75563   wire width 4 $1\main_sdram_time1[3:0]
75564   attribute \src "ls180.v:400.11-400.44"
75565   wire width 10 $1\main_sdram_timer_count1[9:0]
75566   attribute \src "ls180.v:790.11-790.42"
75567   wire width 3 $1\main_sdram_twtrcon_count[2:0]
75568   attribute \src "ls180.v:789.32-789.63"
75569   wire $1\main_sdram_twtrcon_ready[0:0]
75570   attribute \src "ls180.v:335.5-335.32"
75571   wire $1\main_sdram_wrdata_re[0:0]
75572   attribute \src "ls180.v:334.12-334.45"
75573   wire width 16 $1\main_sdram_wrdata_storage[15:0]
75574   attribute \src "ls180.v:1003.12-1003.44"
75575   wire width 16 $1\main_spimaster11_storage[15:0]
75576   attribute \src "ls180.v:1004.5-1004.31"
75577   wire $1\main_spimaster12_re[0:0]
75578   attribute \src "ls180.v:1008.11-1008.42"
75579   wire width 8 $1\main_spimaster16_storage[7:0]
75580   attribute \src "ls180.v:1009.5-1009.31"
75581   wire $1\main_spimaster17_re[0:0]
75582   attribute \src "ls180.v:1065.5-1065.30"
75583   wire $1\main_spimaster1_re[0:0]
75584   attribute \src "ls180.v:1064.12-1064.45"
75585   wire width 16 $1\main_spimaster1_storage[15:0]
75586   attribute \src "ls180.v:1013.5-1013.36"
75587   wire $1\main_spimaster21_storage[0:0]
75588   attribute \src "ls180.v:1014.5-1014.31"
75589   wire $1\main_spimaster22_re[0:0]
75590   attribute \src "ls180.v:1015.5-1015.36"
75591   wire $1\main_spimaster23_storage[0:0]
75592   attribute \src "ls180.v:1016.5-1016.31"
75593   wire $1\main_spimaster24_re[0:0]
75594   attribute \src "ls180.v:1017.5-1017.39"
75595   wire $1\main_spimaster25_clk_enable[0:0]
75596   attribute \src "ls180.v:1018.5-1018.38"
75597   wire $1\main_spimaster26_cs_enable[0:0]
75598   attribute \src "ls180.v:1019.11-1019.40"
75599   wire width 3 $1\main_spimaster27_count[2:0]
75600   attribute \src "ls180.v:1785.11-1785.62"
75601   wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0]
75602   attribute \src "ls180.v:1786.5-1786.59"
75603   wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
75604   attribute \src "ls180.v:1020.5-1020.39"
75605   wire $1\main_spimaster28_mosi_latch[0:0]
75606   attribute \src "ls180.v:1021.5-1021.39"
75607   wire $1\main_spimaster29_miso_latch[0:0]
75608   attribute \src "ls180.v:994.5-994.32"
75609   wire $1\main_spimaster2_done[0:0]
75610   attribute \src "ls180.v:1022.12-1022.48"
75611   wire width 16 $1\main_spimaster30_clk_divider[15:0]
75612   attribute \src "ls180.v:1025.11-1025.44"
75613   wire width 8 $1\main_spimaster33_mosi_data[7:0]
75614   attribute \src "ls180.v:1026.11-1026.43"
75615   wire width 3 $1\main_spimaster34_mosi_sel[2:0]
75616   attribute \src "ls180.v:1027.11-1027.44"
75617   wire width 8 $1\main_spimaster35_miso_data[7:0]
75618   attribute \src "ls180.v:995.5-995.31"
75619   wire $1\main_spimaster3_irq[0:0]
75620   attribute \src "ls180.v:997.11-997.38"
75621   wire width 8 $1\main_spimaster5_miso[7:0]
75622   attribute \src "ls180.v:1001.5-1001.33"
75623   wire $1\main_spimaster9_start[0:0]
75624   attribute \src "ls180.v:1058.12-1058.47"
75625   wire width 16 $1\main_spisdcard_clk_divider1[15:0]
75626   attribute \src "ls180.v:1053.5-1053.37"
75627   wire $1\main_spisdcard_clk_enable[0:0]
75628   attribute \src "ls180.v:1040.5-1040.37"
75629   wire $1\main_spisdcard_control_re[0:0]
75630   attribute \src "ls180.v:1039.12-1039.50"
75631   wire width 16 $1\main_spisdcard_control_storage[15:0]
75632   attribute \src "ls180.v:1055.11-1055.38"
75633   wire width 3 $1\main_spisdcard_count[2:0]
75634   attribute \src "ls180.v:1789.11-1789.60"
75635   wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0]
75636   attribute \src "ls180.v:1790.5-1790.57"
75637   wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
75638   attribute \src "ls180.v:1054.5-1054.36"
75639   wire $1\main_spisdcard_cs_enable[0:0]
75640   attribute \src "ls180.v:1050.5-1050.32"
75641   wire $1\main_spisdcard_cs_re[0:0]
75642   attribute \src "ls180.v:1049.5-1049.37"
75643   wire $1\main_spisdcard_cs_storage[0:0]
75644   attribute \src "ls180.v:1030.5-1030.32"
75645   wire $1\main_spisdcard_done0[0:0]
75646   attribute \src "ls180.v:1031.5-1031.30"
75647   wire $1\main_spisdcard_irq[0:0]
75648   attribute \src "ls180.v:1052.5-1052.38"
75649   wire $1\main_spisdcard_loopback_re[0:0]
75650   attribute \src "ls180.v:1051.5-1051.43"
75651   wire $1\main_spisdcard_loopback_storage[0:0]
75652   attribute \src "ls180.v:1033.11-1033.37"
75653   wire width 8 $1\main_spisdcard_miso[7:0]
75654   attribute \src "ls180.v:1063.11-1063.42"
75655   wire width 8 $1\main_spisdcard_miso_data[7:0]
75656   attribute \src "ls180.v:1057.5-1057.37"
75657   wire $1\main_spisdcard_miso_latch[0:0]
75658   attribute \src "ls180.v:1061.11-1061.42"
75659   wire width 8 $1\main_spisdcard_mosi_data[7:0]
75660   attribute \src "ls180.v:1056.5-1056.37"
75661   wire $1\main_spisdcard_mosi_latch[0:0]
75662   attribute \src "ls180.v:1045.5-1045.34"
75663   wire $1\main_spisdcard_mosi_re[0:0]
75664   attribute \src "ls180.v:1062.11-1062.41"
75665   wire width 3 $1\main_spisdcard_mosi_sel[2:0]
75666   attribute \src "ls180.v:1044.11-1044.45"
75667   wire width 8 $1\main_spisdcard_mosi_storage[7:0]
75668   attribute \src "ls180.v:1037.5-1037.33"
75669   wire $1\main_spisdcard_start1[0:0]
75670   attribute \src "ls180.v:891.11-891.50"
75671   wire width 2 $1\main_uart_eventmanager_pending_w[1:0]
75672   attribute \src "ls180.v:893.5-893.37"
75673   wire $1\main_uart_eventmanager_re[0:0]
75674   attribute \src "ls180.v:887.11-887.49"
75675   wire width 2 $1\main_uart_eventmanager_status_w[1:0]
75676   attribute \src "ls180.v:892.11-892.48"
75677   wire width 2 $1\main_uart_eventmanager_storage[1:0]
75678   attribute \src "ls180.v:859.12-859.54"
75679   wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0]
75680   attribute \src "ls180.v:849.12-849.54"
75681   wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0]
75682   attribute \src "ls180.v:842.5-842.28"
75683   wire $1\main_uart_phy_re[0:0]
75684   attribute \src "ls180.v:863.11-863.43"
75685   wire width 4 $1\main_uart_phy_rx_bitcount[3:0]
75686   attribute \src "ls180.v:864.5-864.33"
75687   wire $1\main_uart_phy_rx_busy[0:0]
75688   attribute \src "ls180.v:861.5-861.30"
75689   wire $1\main_uart_phy_rx_r[0:0]
75690   attribute \src "ls180.v:862.11-862.38"
75691   wire width 8 $1\main_uart_phy_rx_reg[7:0]
75692   attribute \src "ls180.v:844.5-844.36"
75693   wire $1\main_uart_phy_sink_ready[0:0]
75694   attribute \src "ls180.v:857.11-857.51"
75695   wire width 8 $1\main_uart_phy_source_payload_data[7:0]
75696   attribute \src "ls180.v:853.5-853.38"
75697   wire $1\main_uart_phy_source_valid[0:0]
75698   attribute \src "ls180.v:841.12-841.47"
75699   wire width 32 $1\main_uart_phy_storage[31:0]
75700   attribute \src "ls180.v:851.11-851.43"
75701   wire width 4 $1\main_uart_phy_tx_bitcount[3:0]
75702   attribute \src "ls180.v:852.5-852.33"
75703   wire $1\main_uart_phy_tx_busy[0:0]
75704   attribute \src "ls180.v:850.11-850.38"
75705   wire width 8 $1\main_uart_phy_tx_reg[7:0]
75706   attribute \src "ls180.v:858.5-858.39"
75707   wire $1\main_uart_phy_uart_clk_rxen[0:0]
75708   attribute \src "ls180.v:848.5-848.39"
75709   wire $1\main_uart_phy_uart_clk_txen[0:0]
75710   attribute \src "ls180.v:882.5-882.30"
75711   wire $1\main_uart_rx_clear[0:0]
75712   attribute \src "ls180.v:966.11-966.43"
75713   wire width 4 $1\main_uart_rx_fifo_consume[3:0]
75714   attribute \src "ls180.v:963.11-963.42"
75715   wire width 5 $1\main_uart_rx_fifo_level0[4:0]
75716   attribute \src "ls180.v:965.11-965.43"
75717   wire width 4 $1\main_uart_rx_fifo_produce[3:0]
75718   attribute \src "ls180.v:956.5-956.38"
75719   wire $1\main_uart_rx_fifo_readable[0:0]
75720   attribute \src "ls180.v:967.11-967.46"
75721   wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0]
75722   attribute \src "ls180.v:883.5-883.36"
75723   wire $1\main_uart_rx_old_trigger[0:0]
75724   attribute \src "ls180.v:880.5-880.32"
75725   wire $1\main_uart_rx_pending[0:0]
75726   attribute \src "ls180.v:877.5-877.30"
75727   wire $1\main_uart_tx_clear[0:0]
75728   attribute \src "ls180.v:929.11-929.43"
75729   wire width 4 $1\main_uart_tx_fifo_consume[3:0]
75730   attribute \src "ls180.v:926.11-926.42"
75731   wire width 5 $1\main_uart_tx_fifo_level0[4:0]
75732   attribute \src "ls180.v:928.11-928.43"
75733   wire width 4 $1\main_uart_tx_fifo_produce[3:0]
75734   attribute \src "ls180.v:919.5-919.38"
75735   wire $1\main_uart_tx_fifo_readable[0:0]
75736   attribute \src "ls180.v:930.11-930.46"
75737   wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0]
75738   attribute \src "ls180.v:878.5-878.36"
75739   wire $1\main_uart_tx_old_trigger[0:0]
75740   attribute \src "ls180.v:875.5-875.32"
75741   wire $1\main_uart_tx_pending[0:0]
75742   attribute \src "ls180.v:819.5-819.29"
75743   wire $1\main_wb_sdram_ack[0:0]
75744   attribute \src "ls180.v:837.5-837.31"
75745   wire $1\main_wdata_consumed[0:0]
75746   attribute \src "ls180.v:2819.68-2819.110"
75747   wire $add$ls180.v:2819$22_Y
75748   attribute \src "ls180.v:2879.68-2879.110"
75749   wire $add$ls180.v:2879$33_Y
75750   attribute \src "ls180.v:2939.68-2939.110"
75751   wire $add$ls180.v:2939$44_Y
75752   attribute \src "ls180.v:4072.54-4072.83"
75753   wire $add$ls180.v:4072$537_Y
75754   attribute \src "ls180.v:4172.36-4172.89"
75755   wire width 5 $add$ls180.v:4172$583_Y
75756   attribute \src "ls180.v:4202.36-4202.89"
75757   wire width 5 $add$ls180.v:4202$594_Y
75758   attribute \src "ls180.v:4257.54-4257.83"
75759   wire width 3 $add$ls180.v:4257$607_Y
75760   attribute \src "ls180.v:4316.52-4316.79"
75761   wire width 3 $add$ls180.v:4316$615_Y
75762   attribute \src "ls180.v:4420.58-4420.86"
75763   wire width 8 $add$ls180.v:4420$643_Y
75764   attribute \src "ls180.v:4477.58-4477.86"
75765   wire width 8 $add$ls180.v:4477$646_Y
75766   attribute \src "ls180.v:4494.58-4494.86"
75767   wire width 8 $add$ls180.v:4494$648_Y
75768   attribute \src "ls180.v:4587.59-4587.87"
75769   wire width 8 $add$ls180.v:4587$665_Y
75770   attribute \src "ls180.v:4612.59-4612.87"
75771   wire width 8 $add$ls180.v:4612$668_Y
75772   attribute \src "ls180.v:4734.53-4734.82"
75773   wire width 8 $add$ls180.v:4734$685_Y
75774   attribute \src "ls180.v:4845.65-4845.114"
75775   wire width 10 $add$ls180.v:4845$699_Y
75776   attribute \src "ls180.v:4850.62-4850.91"
75777   wire width 10 $add$ls180.v:4850$702_Y
75778   attribute \src "ls180.v:4876.61-4876.90"
75779   wire width 10 $add$ls180.v:4876$705_Y
75780   attribute \src "ls180.v:5080.80-5080.117"
75781   wire width 3 $add$ls180.v:5080$890_Y
75782   attribute \src "ls180.v:5274.54-5274.82"
75783   wire width 3 $add$ls180.v:5274$965_Y
75784   attribute \src "ls180.v:5326.55-5326.84"
75785   wire width 32 $add$ls180.v:5326$975_Y
75786   attribute \src "ls180.v:5352.57-5352.86"
75787   wire width 32 $add$ls180.v:5352$983_Y
75788   attribute \src "ls180.v:5473.51-5473.134"
75789   wire width 32 $add$ls180.v:5473$999_Y
75790   attribute \src "ls180.v:5476.77-5476.125"
75791   wire width 32 $add$ls180.v:5476$1001_Y
75792   attribute \src "ls180.v:5569.50-5569.105"
75793   wire width 32 $add$ls180.v:5569$1010_Y
75794   attribute \src "ls180.v:5571.77-5571.111"
75795   wire width 32 $add$ls180.v:5571$1011_Y
75796   attribute \src "ls180.v:7503.36-7503.70"
75797   wire width 32 $add$ls180.v:7503$2415_Y
75798   attribute \src "ls180.v:7588.37-7588.72"
75799   wire width 4 $add$ls180.v:7588$2436_Y
75800   attribute \src "ls180.v:7605.60-7605.119"
75801   wire width 3 $add$ls180.v:7605$2440_Y
75802   attribute \src "ls180.v:7608.60-7608.119"
75803   wire width 3 $add$ls180.v:7608$2441_Y
75804   attribute \src "ls180.v:7612.59-7612.116"
75805   wire width 4 $add$ls180.v:7612$2446_Y
75806   attribute \src "ls180.v:7651.60-7651.119"
75807   wire width 3 $add$ls180.v:7651$2456_Y
75808   attribute \src "ls180.v:7654.60-7654.119"
75809   wire width 3 $add$ls180.v:7654$2457_Y
75810   attribute \src "ls180.v:7658.59-7658.116"
75811   wire width 4 $add$ls180.v:7658$2462_Y
75812   attribute \src "ls180.v:7697.60-7697.119"
75813   wire width 3 $add$ls180.v:7697$2472_Y
75814   attribute \src "ls180.v:7700.60-7700.119"
75815   wire width 3 $add$ls180.v:7700$2473_Y
75816   attribute \src "ls180.v:7704.59-7704.116"
75817   wire width 4 $add$ls180.v:7704$2478_Y
75818   attribute \src "ls180.v:7743.60-7743.119"
75819   wire width 3 $add$ls180.v:7743$2488_Y
75820   attribute \src "ls180.v:7746.60-7746.119"
75821   wire width 3 $add$ls180.v:7746$2489_Y
75822   attribute \src "ls180.v:7750.59-7750.116"
75823   wire width 4 $add$ls180.v:7750$2494_Y
75824   attribute \src "ls180.v:7980.34-7980.66"
75825   wire width 4 $add$ls180.v:7980$2548_Y
75826   attribute \src "ls180.v:7996.73-7996.131"
75827   wire width 33 $add$ls180.v:7996$2551_Y
75828   attribute \src "ls180.v:8009.34-8009.66"
75829   wire width 4 $add$ls180.v:8009$2555_Y
75830   attribute \src "ls180.v:8028.73-8028.131"
75831   wire width 33 $add$ls180.v:8028$2558_Y
75832   attribute \src "ls180.v:8054.33-8054.65"
75833   wire width 4 $add$ls180.v:8054$2566_Y
75834   attribute \src "ls180.v:8057.33-8057.65"
75835   wire width 4 $add$ls180.v:8057$2567_Y
75836   attribute \src "ls180.v:8061.33-8061.64"
75837   wire width 5 $add$ls180.v:8061$2572_Y
75838   attribute \src "ls180.v:8076.33-8076.65"
75839   wire width 4 $add$ls180.v:8076$2577_Y
75840   attribute \src "ls180.v:8079.33-8079.65"
75841   wire width 4 $add$ls180.v:8079$2578_Y
75842   attribute \src "ls180.v:8083.33-8083.64"
75843   wire width 5 $add$ls180.v:8083$2583_Y
75844   attribute \src "ls180.v:8104.35-8104.70"
75845   wire width 16 $add$ls180.v:8104$2585_Y
75846   attribute \src "ls180.v:8139.34-8139.68"
75847   wire width 16 $add$ls180.v:8139$2590_Y
75848   attribute \src "ls180.v:8175.25-8175.49"
75849   wire width 32 $add$ls180.v:8175$2595_Y
75850   attribute \src "ls180.v:8189.25-8189.49"
75851   wire width 32 $add$ls180.v:8189$2599_Y
75852   attribute \src "ls180.v:8203.31-8203.61"
75853   wire width 9 $add$ls180.v:8203$2604_Y
75854   attribute \src "ls180.v:8226.45-8226.88"
75855   wire width 3 $add$ls180.v:8226$2608_Y
75856   attribute \src "ls180.v:8272.71-8272.114"
75857   wire width 4 $add$ls180.v:8272$2614_Y
75858   attribute \src "ls180.v:8307.46-8307.90"
75859   wire width 3 $add$ls180.v:8307$2620_Y
75860   attribute \src "ls180.v:8353.72-8353.116"
75861   wire width 4 $add$ls180.v:8353$2626_Y
75862   attribute \src "ls180.v:8386.47-8386.92"
75863   wire $add$ls180.v:8386$2632_Y
75864   attribute \src "ls180.v:8414.73-8414.118"
75865   wire width 2 $add$ls180.v:8414$2638_Y
75866   attribute \src "ls180.v:8526.39-8526.75"
75867   wire width 4 $add$ls180.v:8526$2651_Y
75868   attribute \src "ls180.v:8587.37-8587.73"
75869   wire width 5 $add$ls180.v:8587$2655_Y
75870   attribute \src "ls180.v:8590.37-8590.73"
75871   wire width 5 $add$ls180.v:8590$2656_Y
75872   attribute \src "ls180.v:8594.36-8594.70"
75873   wire width 6 $add$ls180.v:8594$2661_Y
75874   attribute \src "ls180.v:8609.41-8609.80"
75875   wire width 2 $add$ls180.v:8609$2665_Y
75876   attribute \src "ls180.v:8643.67-8643.106"
75877   wire width 3 $add$ls180.v:8643$2671_Y
75878   attribute \src "ls180.v:8669.39-8669.76"
75879   wire width 2 $add$ls180.v:8669$2673_Y
75880   attribute \src "ls180.v:8673.37-8673.73"
75881   wire width 5 $add$ls180.v:8673$2677_Y
75882   attribute \src "ls180.v:8676.37-8676.73"
75883   wire width 5 $add$ls180.v:8676$2678_Y
75884   attribute \src "ls180.v:8680.36-8680.70"
75885   wire width 6 $add$ls180.v:8680$2683_Y
75886   attribute \src "ls180.v:2813.9-2813.80"
75887   wire $and$ls180.v:2813$17_Y
75888   attribute \src "ls180.v:2831.9-2831.80"
75889   wire $and$ls180.v:2831$24_Y
75890   attribute \src "ls180.v:2873.9-2873.80"
75891   wire $and$ls180.v:2873$28_Y
75892   attribute \src "ls180.v:2891.9-2891.80"
75893   wire $and$ls180.v:2891$35_Y
75894   attribute \src "ls180.v:2933.9-2933.86"
75895   wire $and$ls180.v:2933$39_Y
75896   attribute \src "ls180.v:2951.9-2951.86"
75897   wire $and$ls180.v:2951$46_Y
75898   attribute \src "ls180.v:2961.31-2961.90"
75899   wire $and$ls180.v:2961$48_Y
75900   attribute \src "ls180.v:2961.30-2961.121"
75901   wire $and$ls180.v:2961$49_Y
75902   attribute \src "ls180.v:2961.29-2961.156"
75903   wire $and$ls180.v:2961$50_Y
75904   attribute \src "ls180.v:2962.31-2962.90"
75905   wire $and$ls180.v:2962$51_Y
75906   attribute \src "ls180.v:2962.30-2962.121"
75907   wire $and$ls180.v:2962$52_Y
75908   attribute \src "ls180.v:2962.29-2962.156"
75909   wire $and$ls180.v:2962$53_Y
75910   attribute \src "ls180.v:2963.31-2963.90"
75911   wire $and$ls180.v:2963$54_Y
75912   attribute \src "ls180.v:2963.30-2963.121"
75913   wire $and$ls180.v:2963$55_Y
75914   attribute \src "ls180.v:2963.29-2963.156"
75915   wire $and$ls180.v:2963$56_Y
75916   attribute \src "ls180.v:2964.31-2964.90"
75917   wire $and$ls180.v:2964$57_Y
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77389   wire $and$ls180.v:6230$1861_Y
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77392   attribute \src "ls180.v:6232.49-6232.153"
77393   wire $and$ls180.v:6232$1864_Y
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77395   wire $and$ls180.v:6233$1866_Y
77396   attribute \src "ls180.v:6233.49-6233.156"
77397   wire $and$ls180.v:6233$1868_Y
77398   attribute \src "ls180.v:6235.51-6235.104"
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77400   attribute \src "ls180.v:6235.50-6235.154"
77401   wire $and$ls180.v:6235$1871_Y
77402   attribute \src "ls180.v:6236.51-6236.107"
77403   wire $and$ls180.v:6236$1873_Y
77404   attribute \src "ls180.v:6236.50-6236.157"
77405   wire $and$ls180.v:6236$1875_Y
77406   attribute \src "ls180.v:6238.49-6238.102"
77407   wire $and$ls180.v:6238$1876_Y
77408   attribute \src "ls180.v:6238.48-6238.152"
77409   wire $and$ls180.v:6238$1878_Y
77410   attribute \src "ls180.v:6239.49-6239.105"
77411   wire $and$ls180.v:6239$1880_Y
77412   attribute \src "ls180.v:6239.48-6239.155"
77413   wire $and$ls180.v:6239$1882_Y
77414   attribute \src "ls180.v:6241.49-6241.102"
77415   wire $and$ls180.v:6241$1883_Y
77416   attribute \src "ls180.v:6241.48-6241.152"
77417   wire $and$ls180.v:6241$1885_Y
77418   attribute \src "ls180.v:6242.49-6242.105"
77419   wire $and$ls180.v:6242$1887_Y
77420   attribute \src "ls180.v:6242.48-6242.155"
77421   wire $and$ls180.v:6242$1889_Y
77422   attribute \src "ls180.v:6244.49-6244.102"
77423   wire $and$ls180.v:6244$1890_Y
77424   attribute \src "ls180.v:6244.48-6244.152"
77425   wire $and$ls180.v:6244$1892_Y
77426   attribute \src "ls180.v:6245.49-6245.105"
77427   wire $and$ls180.v:6245$1894_Y
77428   attribute \src "ls180.v:6245.48-6245.155"
77429   wire $and$ls180.v:6245$1896_Y
77430   attribute \src "ls180.v:6247.49-6247.102"
77431   wire $and$ls180.v:6247$1897_Y
77432   attribute \src "ls180.v:6247.48-6247.152"
77433   wire $and$ls180.v:6247$1899_Y
77434   attribute \src "ls180.v:6248.49-6248.105"
77435   wire $and$ls180.v:6248$1901_Y
77436   attribute \src "ls180.v:6248.48-6248.155"
77437   wire $and$ls180.v:6248$1903_Y
77438   attribute \src "ls180.v:6265.42-6265.97"
77439   wire $and$ls180.v:6265$1905_Y
77440   attribute \src "ls180.v:6265.41-6265.148"
77441   wire $and$ls180.v:6265$1907_Y
77442   attribute \src "ls180.v:6266.42-6266.100"
77443   wire $and$ls180.v:6266$1909_Y
77444   attribute \src "ls180.v:6266.41-6266.151"
77445   wire $and$ls180.v:6266$1911_Y
77446   attribute \src "ls180.v:6268.42-6268.97"
77447   wire $and$ls180.v:6268$1912_Y
77448   attribute \src "ls180.v:6268.41-6268.148"
77449   wire $and$ls180.v:6268$1914_Y
77450   attribute \src "ls180.v:6269.42-6269.100"
77451   wire $and$ls180.v:6269$1916_Y
77452   attribute \src "ls180.v:6269.41-6269.151"
77453   wire $and$ls180.v:6269$1918_Y
77454   attribute \src "ls180.v:6271.40-6271.95"
77455   wire $and$ls180.v:6271$1919_Y
77456   attribute \src "ls180.v:6271.39-6271.146"
77457   wire $and$ls180.v:6271$1921_Y
77458   attribute \src "ls180.v:6272.40-6272.98"
77459   wire $and$ls180.v:6272$1923_Y
77460   attribute \src "ls180.v:6272.39-6272.149"
77461   wire $and$ls180.v:6272$1925_Y
77462   attribute \src "ls180.v:6274.39-6274.94"
77463   wire $and$ls180.v:6274$1926_Y
77464   attribute \src "ls180.v:6274.38-6274.145"
77465   wire $and$ls180.v:6274$1928_Y
77466   attribute \src "ls180.v:6275.39-6275.97"
77467   wire $and$ls180.v:6275$1930_Y
77468   attribute \src "ls180.v:6275.38-6275.148"
77469   wire $and$ls180.v:6275$1932_Y
77470   attribute \src "ls180.v:6277.38-6277.93"
77471   wire $and$ls180.v:6277$1933_Y
77472   attribute \src "ls180.v:6277.37-6277.144"
77473   wire $and$ls180.v:6277$1935_Y
77474   attribute \src "ls180.v:6278.38-6278.96"
77475   wire $and$ls180.v:6278$1937_Y
77476   attribute \src "ls180.v:6278.37-6278.147"
77477   wire $and$ls180.v:6278$1939_Y
77478   attribute \src "ls180.v:6280.37-6280.92"
77479   wire $and$ls180.v:6280$1940_Y
77480   attribute \src "ls180.v:6280.36-6280.143"
77481   wire $and$ls180.v:6280$1942_Y
77482   attribute \src "ls180.v:6281.37-6281.95"
77483   wire $and$ls180.v:6281$1944_Y
77484   attribute \src "ls180.v:6281.36-6281.146"
77485   wire $and$ls180.v:6281$1946_Y
77486   attribute \src "ls180.v:6283.43-6283.98"
77487   wire $and$ls180.v:6283$1947_Y
77488   attribute \src "ls180.v:6283.42-6283.149"
77489   wire $and$ls180.v:6283$1949_Y
77490   attribute \src "ls180.v:6284.43-6284.101"
77491   wire $and$ls180.v:6284$1951_Y
77492   attribute \src "ls180.v:6284.42-6284.152"
77493   wire $and$ls180.v:6284$1953_Y
77494   attribute \src "ls180.v:6305.42-6305.97"
77495   wire $and$ls180.v:6305$1956_Y
77496   attribute \src "ls180.v:6305.41-6305.148"
77497   wire $and$ls180.v:6305$1958_Y
77498   attribute \src "ls180.v:6306.42-6306.100"
77499   wire $and$ls180.v:6306$1960_Y
77500   attribute \src "ls180.v:6306.41-6306.151"
77501   wire $and$ls180.v:6306$1962_Y
77502   attribute \src "ls180.v:6308.42-6308.97"
77503   wire $and$ls180.v:6308$1963_Y
77504   attribute \src "ls180.v:6308.41-6308.148"
77505   wire $and$ls180.v:6308$1965_Y
77506   attribute \src "ls180.v:6309.42-6309.100"
77507   wire $and$ls180.v:6309$1967_Y
77508   attribute \src "ls180.v:6309.41-6309.151"
77509   wire $and$ls180.v:6309$1969_Y
77510   attribute \src "ls180.v:6311.40-6311.95"
77511   wire $and$ls180.v:6311$1970_Y
77512   attribute \src "ls180.v:6311.39-6311.146"
77513   wire $and$ls180.v:6311$1972_Y
77514   attribute \src "ls180.v:6312.40-6312.98"
77515   wire $and$ls180.v:6312$1974_Y
77516   attribute \src "ls180.v:6312.39-6312.149"
77517   wire $and$ls180.v:6312$1976_Y
77518   attribute \src "ls180.v:6314.39-6314.94"
77519   wire $and$ls180.v:6314$1977_Y
77520   attribute \src "ls180.v:6314.38-6314.145"
77521   wire $and$ls180.v:6314$1979_Y
77522   attribute \src "ls180.v:6315.39-6315.97"
77523   wire $and$ls180.v:6315$1981_Y
77524   attribute \src "ls180.v:6315.38-6315.148"
77525   wire $and$ls180.v:6315$1983_Y
77526   attribute \src "ls180.v:6317.38-6317.93"
77527   wire $and$ls180.v:6317$1984_Y
77528   attribute \src "ls180.v:6317.37-6317.144"
77529   wire $and$ls180.v:6317$1986_Y
77530   attribute \src "ls180.v:6318.38-6318.96"
77531   wire $and$ls180.v:6318$1988_Y
77532   attribute \src "ls180.v:6318.37-6318.147"
77533   wire $and$ls180.v:6318$1990_Y
77534   attribute \src "ls180.v:6320.37-6320.92"
77535   wire $and$ls180.v:6320$1991_Y
77536   attribute \src "ls180.v:6320.36-6320.143"
77537   wire $and$ls180.v:6320$1993_Y
77538   attribute \src "ls180.v:6321.37-6321.95"
77539   wire $and$ls180.v:6321$1995_Y
77540   attribute \src "ls180.v:6321.36-6321.146"
77541   wire $and$ls180.v:6321$1997_Y
77542   attribute \src "ls180.v:6323.43-6323.98"
77543   wire $and$ls180.v:6323$1998_Y
77544   attribute \src "ls180.v:6323.42-6323.149"
77545   wire $and$ls180.v:6323$2000_Y
77546   attribute \src "ls180.v:6324.43-6324.101"
77547   wire $and$ls180.v:6324$2002_Y
77548   attribute \src "ls180.v:6324.42-6324.152"
77549   wire $and$ls180.v:6324$2004_Y
77550   attribute \src "ls180.v:6326.46-6326.101"
77551   wire $and$ls180.v:6326$2005_Y
77552   attribute \src "ls180.v:6326.45-6326.152"
77553   wire $and$ls180.v:6326$2007_Y
77554   attribute \src "ls180.v:6327.46-6327.104"
77555   wire $and$ls180.v:6327$2009_Y
77556   attribute \src "ls180.v:6327.45-6327.155"
77557   wire $and$ls180.v:6327$2011_Y
77558   attribute \src "ls180.v:6329.46-6329.101"
77559   wire $and$ls180.v:6329$2012_Y
77560   attribute \src "ls180.v:6329.45-6329.152"
77561   wire $and$ls180.v:6329$2014_Y
77562   attribute \src "ls180.v:6330.46-6330.104"
77563   wire $and$ls180.v:6330$2016_Y
77564   attribute \src "ls180.v:6330.45-6330.155"
77565   wire $and$ls180.v:6330$2018_Y
77566   attribute \src "ls180.v:6353.39-6353.94"
77567   wire $and$ls180.v:6353$2021_Y
77568   attribute \src "ls180.v:6353.38-6353.145"
77569   wire $and$ls180.v:6353$2023_Y
77570   attribute \src "ls180.v:6354.39-6354.97"
77571   wire $and$ls180.v:6354$2025_Y
77572   attribute \src "ls180.v:6354.38-6354.148"
77573   wire $and$ls180.v:6354$2027_Y
77574   attribute \src "ls180.v:6356.39-6356.94"
77575   wire $and$ls180.v:6356$2028_Y
77576   attribute \src "ls180.v:6356.38-6356.145"
77577   wire $and$ls180.v:6356$2030_Y
77578   attribute \src "ls180.v:6357.39-6357.97"
77579   wire $and$ls180.v:6357$2032_Y
77580   attribute \src "ls180.v:6357.38-6357.148"
77581   wire $and$ls180.v:6357$2034_Y
77582   attribute \src "ls180.v:6359.39-6359.94"
77583   wire $and$ls180.v:6359$2035_Y
77584   attribute \src "ls180.v:6359.38-6359.145"
77585   wire $and$ls180.v:6359$2037_Y
77586   attribute \src "ls180.v:6360.39-6360.97"
77587   wire $and$ls180.v:6360$2039_Y
77588   attribute \src "ls180.v:6360.38-6360.148"
77589   wire $and$ls180.v:6360$2041_Y
77590   attribute \src "ls180.v:6362.39-6362.94"
77591   wire $and$ls180.v:6362$2042_Y
77592   attribute \src "ls180.v:6362.38-6362.145"
77593   wire $and$ls180.v:6362$2044_Y
77594   attribute \src "ls180.v:6363.39-6363.97"
77595   wire $and$ls180.v:6363$2046_Y
77596   attribute \src "ls180.v:6363.38-6363.148"
77597   wire $and$ls180.v:6363$2048_Y
77598   attribute \src "ls180.v:6365.41-6365.96"
77599   wire $and$ls180.v:6365$2049_Y
77600   attribute \src "ls180.v:6365.40-6365.147"
77601   wire $and$ls180.v:6365$2051_Y
77602   attribute \src "ls180.v:6366.41-6366.99"
77603   wire $and$ls180.v:6366$2053_Y
77604   attribute \src "ls180.v:6366.40-6366.150"
77605   wire $and$ls180.v:6366$2055_Y
77606   attribute \src "ls180.v:6368.41-6368.96"
77607   wire $and$ls180.v:6368$2056_Y
77608   attribute \src "ls180.v:6368.40-6368.147"
77609   wire $and$ls180.v:6368$2058_Y
77610   attribute \src "ls180.v:6369.41-6369.99"
77611   wire $and$ls180.v:6369$2060_Y
77612   attribute \src "ls180.v:6369.40-6369.150"
77613   wire $and$ls180.v:6369$2062_Y
77614   attribute \src "ls180.v:6371.41-6371.96"
77615   wire $and$ls180.v:6371$2063_Y
77616   attribute \src "ls180.v:6371.40-6371.147"
77617   wire $and$ls180.v:6371$2065_Y
77618   attribute \src "ls180.v:6372.41-6372.99"
77619   wire $and$ls180.v:6372$2067_Y
77620   attribute \src "ls180.v:6372.40-6372.150"
77621   wire $and$ls180.v:6372$2069_Y
77622   attribute \src "ls180.v:6374.41-6374.96"
77623   wire $and$ls180.v:6374$2070_Y
77624   attribute \src "ls180.v:6374.40-6374.147"
77625   wire $and$ls180.v:6374$2072_Y
77626   attribute \src "ls180.v:6375.41-6375.99"
77627   wire $and$ls180.v:6375$2074_Y
77628   attribute \src "ls180.v:6375.40-6375.150"
77629   wire $and$ls180.v:6375$2076_Y
77630   attribute \src "ls180.v:6377.37-6377.92"
77631   wire $and$ls180.v:6377$2077_Y
77632   attribute \src "ls180.v:6377.36-6377.143"
77633   wire $and$ls180.v:6377$2079_Y
77634   attribute \src "ls180.v:6378.37-6378.95"
77635   wire $and$ls180.v:6378$2081_Y
77636   attribute \src "ls180.v:6378.36-6378.146"
77637   wire $and$ls180.v:6378$2083_Y
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77639   wire $and$ls180.v:6380$2084_Y
77640   attribute \src "ls180.v:6380.46-6380.153"
77641   wire $and$ls180.v:6380$2086_Y
77642   attribute \src "ls180.v:6381.47-6381.105"
77643   wire $and$ls180.v:6381$2088_Y
77644   attribute \src "ls180.v:6381.46-6381.156"
77645   wire $and$ls180.v:6381$2090_Y
77646   attribute \src "ls180.v:6383.40-6383.95"
77647   wire $and$ls180.v:6383$2091_Y
77648   attribute \src "ls180.v:6383.39-6383.147"
77649   wire $and$ls180.v:6383$2093_Y
77650   attribute \src "ls180.v:6384.40-6384.98"
77651   wire $and$ls180.v:6384$2095_Y
77652   attribute \src "ls180.v:6384.39-6384.150"
77653   wire $and$ls180.v:6384$2097_Y
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77655   wire $and$ls180.v:6386$2098_Y
77656   attribute \src "ls180.v:6386.39-6386.147"
77657   wire $and$ls180.v:6386$2100_Y
77658   attribute \src "ls180.v:6387.40-6387.98"
77659   wire $and$ls180.v:6387$2102_Y
77660   attribute \src "ls180.v:6387.39-6387.150"
77661   wire $and$ls180.v:6387$2104_Y
77662   attribute \src "ls180.v:6389.40-6389.95"
77663   wire $and$ls180.v:6389$2105_Y
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77665   wire $and$ls180.v:6389$2107_Y
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77667   wire $and$ls180.v:6390$2109_Y
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77669   wire $and$ls180.v:6390$2111_Y
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77671   wire $and$ls180.v:6392$2112_Y
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77673   wire $and$ls180.v:6392$2114_Y
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77675   wire $and$ls180.v:6393$2116_Y
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77677   wire $and$ls180.v:6393$2118_Y
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77681   wire $and$ls180.v:6395$2121_Y
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77685   wire $and$ls180.v:6396$2125_Y
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77687   wire $and$ls180.v:6398$2126_Y
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77689   wire $and$ls180.v:6398$2128_Y
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77697   wire $and$ls180.v:6401$2135_Y
77698   attribute \src "ls180.v:6402.44-6402.102"
77699   wire $and$ls180.v:6402$2137_Y
77700   attribute \src "ls180.v:6402.43-6402.154"
77701   wire $and$ls180.v:6402$2139_Y
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77703   wire $and$ls180.v:6421$2141_Y
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77705   wire $and$ls180.v:6421$2143_Y
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77707   wire $and$ls180.v:6422$2145_Y
77708   attribute \src "ls180.v:6422.29-6422.139"
77709   wire $and$ls180.v:6422$2147_Y
77710   attribute \src "ls180.v:6424.40-6424.95"
77711   wire $and$ls180.v:6424$2148_Y
77712   attribute \src "ls180.v:6424.39-6424.146"
77713   wire $and$ls180.v:6424$2150_Y
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77715   wire $and$ls180.v:6425$2152_Y
77716   attribute \src "ls180.v:6425.39-6425.149"
77717   wire $and$ls180.v:6425$2154_Y
77718   attribute \src "ls180.v:6427.41-6427.96"
77719   wire $and$ls180.v:6427$2155_Y
77720   attribute \src "ls180.v:6427.40-6427.147"
77721   wire $and$ls180.v:6427$2157_Y
77722   attribute \src "ls180.v:6428.41-6428.99"
77723   wire $and$ls180.v:6428$2159_Y
77724   attribute \src "ls180.v:6428.40-6428.150"
77725   wire $and$ls180.v:6428$2161_Y
77726   attribute \src "ls180.v:6430.45-6430.100"
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78090   attribute \src "ls180.v:3813.339-3813.418"
78091   wire $eq$ls180.v:3813$259_Y
78092   attribute \src "ls180.v:3813.423-3813.504"
78093   wire $eq$ls180.v:3813$260_Y
78094   attribute \src "ls180.v:3814.339-3814.418"
78095   wire $eq$ls180.v:3814$272_Y
78096   attribute \src "ls180.v:3814.423-3814.504"
78097   wire $eq$ls180.v:3814$273_Y
78098   attribute \src "ls180.v:3815.339-3815.418"
78099   wire $eq$ls180.v:3815$285_Y
78100   attribute \src "ls180.v:3815.423-3815.504"
78101   wire $eq$ls180.v:3815$286_Y
78102   attribute \src "ls180.v:3845.339-3845.418"
78103   wire $eq$ls180.v:3845$304_Y
78104   attribute \src "ls180.v:3845.423-3845.504"
78105   wire $eq$ls180.v:3845$305_Y
78106   attribute \src "ls180.v:3846.339-3846.418"
78107   wire $eq$ls180.v:3846$317_Y
78108   attribute \src "ls180.v:3846.423-3846.504"
78109   wire $eq$ls180.v:3846$318_Y
78110   attribute \src "ls180.v:3847.339-3847.418"
78111   wire $eq$ls180.v:3847$330_Y
78112   attribute \src "ls180.v:3847.423-3847.504"
78113   wire $eq$ls180.v:3847$331_Y
78114   attribute \src "ls180.v:3848.339-3848.418"
78115   wire $eq$ls180.v:3848$343_Y
78116   attribute \src "ls180.v:3848.423-3848.504"
78117   wire $eq$ls180.v:3848$344_Y
78118   attribute \src "ls180.v:3877.78-3877.113"
78119   wire $eq$ls180.v:3877$353_Y
78120   attribute \src "ls180.v:3880.78-3880.113"
78121   wire $eq$ls180.v:3880$356_Y
78122   attribute \src "ls180.v:3886.78-3886.113"
78123   wire $eq$ls180.v:3886$360_Y
78124   attribute \src "ls180.v:3889.78-3889.113"
78125   wire $eq$ls180.v:3889$363_Y
78126   attribute \src "ls180.v:3895.78-3895.113"
78127   wire $eq$ls180.v:3895$367_Y
78128   attribute \src "ls180.v:3898.78-3898.113"
78129   wire $eq$ls180.v:3898$370_Y
78130   attribute \src "ls180.v:3904.78-3904.113"
78131   wire $eq$ls180.v:3904$374_Y
78132   attribute \src "ls180.v:3907.78-3907.113"
78133   wire $eq$ls180.v:3907$377_Y
78134   attribute \src "ls180.v:3988.42-3988.82"
78135   wire $eq$ls180.v:3988$400_Y
78136   attribute \src "ls180.v:3988.145-3988.178"
78137   wire $eq$ls180.v:3988$401_Y
78138   attribute \src "ls180.v:3988.220-3988.253"
78139   wire $eq$ls180.v:3988$404_Y
78140   attribute \src "ls180.v:3988.295-3988.328"
78141   wire $eq$ls180.v:3988$407_Y
78142   attribute \src "ls180.v:3993.42-3993.82"
78143   wire $eq$ls180.v:3993$416_Y
78144   attribute \src "ls180.v:3993.145-3993.178"
78145   wire $eq$ls180.v:3993$417_Y
78146   attribute \src "ls180.v:3993.220-3993.253"
78147   wire $eq$ls180.v:3993$420_Y
78148   attribute \src "ls180.v:3993.295-3993.328"
78149   wire $eq$ls180.v:3993$423_Y
78150   attribute \src "ls180.v:3998.42-3998.82"
78151   wire $eq$ls180.v:3998$432_Y
78152   attribute \src "ls180.v:3998.145-3998.178"
78153   wire $eq$ls180.v:3998$433_Y
78154   attribute \src "ls180.v:3998.220-3998.253"
78155   wire $eq$ls180.v:3998$436_Y
78156   attribute \src "ls180.v:3998.295-3998.328"
78157   wire $eq$ls180.v:3998$439_Y
78158   attribute \src "ls180.v:4003.42-4003.82"
78159   wire $eq$ls180.v:4003$448_Y
78160   attribute \src "ls180.v:4003.145-4003.178"
78161   wire $eq$ls180.v:4003$449_Y
78162   attribute \src "ls180.v:4003.220-4003.253"
78163   wire $eq$ls180.v:4003$452_Y
78164   attribute \src "ls180.v:4003.295-4003.328"
78165   wire $eq$ls180.v:4003$455_Y
78166   attribute \src "ls180.v:4008.44-4008.77"
78167   wire $eq$ls180.v:4008$464_Y
78168   attribute \src "ls180.v:4008.83-4008.123"
78169   wire $eq$ls180.v:4008$465_Y
78170   attribute \src "ls180.v:4008.186-4008.219"
78171   wire $eq$ls180.v:4008$466_Y
78172   attribute \src "ls180.v:4008.261-4008.294"
78173   wire $eq$ls180.v:4008$469_Y
78174   attribute \src "ls180.v:4008.336-4008.369"
78175   wire $eq$ls180.v:4008$472_Y
78176   attribute \src "ls180.v:4008.418-4008.451"
78177   wire $eq$ls180.v:4008$480_Y
78178   attribute \src "ls180.v:4008.457-4008.497"
78179   wire $eq$ls180.v:4008$481_Y
78180   attribute \src "ls180.v:4008.560-4008.593"
78181   wire $eq$ls180.v:4008$482_Y
78182   attribute \src "ls180.v:4008.635-4008.668"
78183   wire $eq$ls180.v:4008$485_Y
78184   attribute \src "ls180.v:4008.710-4008.743"
78185   wire $eq$ls180.v:4008$488_Y
78186   attribute \src "ls180.v:4008.792-4008.825"
78187   wire $eq$ls180.v:4008$496_Y
78188   attribute \src "ls180.v:4008.831-4008.871"
78189   wire $eq$ls180.v:4008$497_Y
78190   attribute \src "ls180.v:4008.934-4008.967"
78191   wire $eq$ls180.v:4008$498_Y
78192   attribute \src "ls180.v:4008.1009-4008.1042"
78193   wire $eq$ls180.v:4008$501_Y
78194   attribute \src "ls180.v:4008.1084-4008.1117"
78195   wire $eq$ls180.v:4008$504_Y
78196   attribute \src "ls180.v:4008.1166-4008.1199"
78197   wire $eq$ls180.v:4008$512_Y
78198   attribute \src "ls180.v:4008.1205-4008.1245"
78199   wire $eq$ls180.v:4008$513_Y
78200   attribute \src "ls180.v:4008.1308-4008.1341"
78201   wire $eq$ls180.v:4008$514_Y
78202   attribute \src "ls180.v:4008.1383-4008.1416"
78203   wire $eq$ls180.v:4008$517_Y
78204   attribute \src "ls180.v:4008.1458-4008.1491"
78205   wire $eq$ls180.v:4008$520_Y
78206   attribute \src "ls180.v:4067.29-4067.57"
78207   wire $eq$ls180.v:4067$533_Y
78208   attribute \src "ls180.v:4074.11-4074.41"
78209   wire $eq$ls180.v:4074$538_Y
78210   attribute \src "ls180.v:4231.37-4231.111"
78211   wire $eq$ls180.v:4231$603_Y
78212   attribute \src "ls180.v:4232.37-4232.105"
78213   wire $eq$ls180.v:4232$605_Y
78214   attribute \src "ls180.v:4259.10-4259.67"
78215   wire $eq$ls180.v:4259$609_Y
78216   attribute \src "ls180.v:4289.35-4289.108"
78217   wire $eq$ls180.v:4289$611_Y
78218   attribute \src "ls180.v:4290.35-4290.102"
78219   wire $eq$ls180.v:4290$613_Y
78220   attribute \src "ls180.v:4318.10-4318.65"
78221   wire $eq$ls180.v:4318$617_Y
78222   attribute \src "ls180.v:4422.10-4422.40"
78223   wire $eq$ls180.v:4422$644_Y
78224   attribute \src "ls180.v:4479.10-4479.39"
78225   wire $eq$ls180.v:4479$647_Y
78226   attribute \src "ls180.v:4496.10-4496.39"
78227   wire $eq$ls180.v:4496$649_Y
78228   attribute \src "ls180.v:4524.38-4524.88"
78229   wire $eq$ls180.v:4524$651_Y
78230   attribute \src "ls180.v:4574.9-4574.40"
78231   wire $eq$ls180.v:4574$661_Y
78232   attribute \src "ls180.v:4583.36-4583.105"
78233   wire $eq$ls180.v:4583$663_Y
78234   attribute \src "ls180.v:4602.9-4602.40"
78235   wire $eq$ls180.v:4602$667_Y
78236   attribute \src "ls180.v:4614.10-4614.39"
78237   wire $eq$ls180.v:4614$669_Y
78238   attribute \src "ls180.v:4651.39-4651.94"
78239   wire $eq$ls180.v:4651$673_Y
78240   attribute \src "ls180.v:4688.32-4688.89"
78241   wire $eq$ls180.v:4688$682_Y
78242   attribute \src "ls180.v:4736.10-4736.40"
78243   wire $eq$ls180.v:4736$686_Y
78244   attribute \src "ls180.v:4785.40-4785.98"
78245   wire $eq$ls180.v:4785$688_Y
78246   attribute \src "ls180.v:4836.9-4836.41"
78247   wire $eq$ls180.v:4836$698_Y
78248   attribute \src "ls180.v:4845.37-4845.123"
78249   wire $eq$ls180.v:4845$701_Y
78250   attribute \src "ls180.v:4868.9-4868.41"
78251   wire $eq$ls180.v:4868$704_Y
78252   attribute \src "ls180.v:4878.10-4878.41"
78253   wire $eq$ls180.v:4878$706_Y
78254   attribute \src "ls180.v:5047.9-5047.47"
78255   wire $eq$ls180.v:5047$888_Y
78256   attribute \src "ls180.v:5077.10-5077.48"
78257   wire $eq$ls180.v:5077$889_Y
78258   attribute \src "ls180.v:5108.10-5108.78"
78259   wire $eq$ls180.v:5108$894_Y
78260   attribute \src "ls180.v:5108.83-5108.151"
78261   wire $eq$ls180.v:5108$895_Y
78262   attribute \src "ls180.v:5108.157-5108.225"
78263   wire $eq$ls180.v:5108$897_Y
78264   attribute \src "ls180.v:5108.231-5108.299"
78265   wire $eq$ls180.v:5108$899_Y
78266   attribute \src "ls180.v:5116.7-5116.44"
78267   wire $eq$ls180.v:5116$903_Y
78268   attribute \src "ls180.v:5126.7-5126.44"
78269   wire $eq$ls180.v:5126$906_Y
78270   attribute \src "ls180.v:5136.7-5136.44"
78271   wire $eq$ls180.v:5136$909_Y
78272   attribute \src "ls180.v:5146.7-5146.44"
78273   wire $eq$ls180.v:5146$912_Y
78274   attribute \src "ls180.v:5270.36-5270.64"
78275   wire $eq$ls180.v:5270$963_Y
78276   attribute \src "ls180.v:5276.10-5276.39"
78277   wire $eq$ls180.v:5276$966_Y
78278   attribute \src "ls180.v:5277.11-5277.39"
78279   wire $eq$ls180.v:5277$967_Y
78280   attribute \src "ls180.v:5289.34-5289.63"
78281   wire $eq$ls180.v:5289$968_Y
78282   attribute \src "ls180.v:5290.9-5290.37"
78283   wire $eq$ls180.v:5290$969_Y
78284   attribute \src "ls180.v:5297.10-5297.55"
78285   wire $eq$ls180.v:5297$970_Y
78286   attribute \src "ls180.v:5303.12-5303.41"
78287   wire $eq$ls180.v:5303$971_Y
78288   attribute \src "ls180.v:5306.13-5306.42"
78289   wire $eq$ls180.v:5306$972_Y
78290   attribute \src "ls180.v:5328.10-5328.76"
78291   wire $eq$ls180.v:5328$977_Y
78292   attribute \src "ls180.v:5343.35-5343.101"
78293   wire $eq$ls180.v:5343$980_Y
78294   attribute \src "ls180.v:5345.10-5345.56"
78295   wire $eq$ls180.v:5345$981_Y
78296   attribute \src "ls180.v:5354.12-5354.78"
78297   wire $eq$ls180.v:5354$985_Y
78298   attribute \src "ls180.v:5361.11-5361.57"
78299   wire $eq$ls180.v:5361$986_Y
78300   attribute \src "ls180.v:5478.10-5478.105"
78301   wire $eq$ls180.v:5478$1003_Y
78302   attribute \src "ls180.v:5568.39-5568.106"
78303   wire $eq$ls180.v:5568$1009_Y
78304   attribute \src "ls180.v:5598.44-5598.82"
78305   wire $eq$ls180.v:5598$1012_Y
78306   attribute \src "ls180.v:5599.43-5599.81"
78307   wire $eq$ls180.v:5599$1013_Y
78308   attribute \src "ls180.v:5699.85-5699.106"
78309   wire $eq$ls180.v:5699$1029_Y
78310   attribute \src "ls180.v:5700.85-5700.106"
78311   wire $eq$ls180.v:5700$1031_Y
78312   attribute \src "ls180.v:5701.85-5701.106"
78313   wire $eq$ls180.v:5701$1033_Y
78314   attribute \src "ls180.v:5702.57-5702.78"
78315   wire $eq$ls180.v:5702$1035_Y
78316   attribute \src "ls180.v:5703.57-5703.78"
78317   wire $eq$ls180.v:5703$1037_Y
78318   attribute \src "ls180.v:5704.85-5704.106"
78319   wire $eq$ls180.v:5704$1039_Y
78320   attribute \src "ls180.v:5705.85-5705.106"
78321   wire $eq$ls180.v:5705$1041_Y
78322   attribute \src "ls180.v:5706.85-5706.106"
78323   wire $eq$ls180.v:5706$1043_Y
78324   attribute \src "ls180.v:5707.57-5707.78"
78325   wire $eq$ls180.v:5707$1045_Y
78326   attribute \src "ls180.v:5708.57-5708.78"
78327   wire $eq$ls180.v:5708$1047_Y
78328   attribute \src "ls180.v:5712.27-5712.59"
78329   wire $eq$ls180.v:5712$1050_Y
78330   attribute \src "ls180.v:5713.27-5713.68"
78331   wire $eq$ls180.v:5713$1051_Y
78332   attribute \src "ls180.v:5714.27-5714.66"
78333   wire $eq$ls180.v:5714$1052_Y
78334   attribute \src "ls180.v:5715.27-5715.61"
78335   wire $eq$ls180.v:5715$1053_Y
78336   attribute \src "ls180.v:5716.27-5716.65"
78337   wire $eq$ls180.v:5716$1054_Y
78338   attribute \src "ls180.v:5772.24-5772.45"
78339   wire $eq$ls180.v:5772$1081_Y
78340   attribute \src "ls180.v:5773.32-5773.77"
78341   wire $eq$ls180.v:5773$1082_Y
78342   attribute \src "ls180.v:5775.97-5775.141"
78343   wire $eq$ls180.v:5775$1084_Y
78344   attribute \src "ls180.v:5776.100-5776.144"
78345   wire $eq$ls180.v:5776$1088_Y
78346   attribute \src "ls180.v:5778.99-5778.143"
78347   wire $eq$ls180.v:5778$1091_Y
78348   attribute \src "ls180.v:5779.102-5779.146"
78349   wire $eq$ls180.v:5779$1095_Y
78350   attribute \src "ls180.v:5781.99-5781.143"
78351   wire $eq$ls180.v:5781$1098_Y
78352   attribute \src "ls180.v:5782.102-5782.146"
78353   wire $eq$ls180.v:5782$1102_Y
78354   attribute \src "ls180.v:5784.99-5784.143"
78355   wire $eq$ls180.v:5784$1105_Y
78356   attribute \src "ls180.v:5785.102-5785.146"
78357   wire $eq$ls180.v:5785$1109_Y
78358   attribute \src "ls180.v:5787.99-5787.143"
78359   wire $eq$ls180.v:5787$1112_Y
78360   attribute \src "ls180.v:5788.102-5788.146"
78361   wire $eq$ls180.v:5788$1116_Y
78362   attribute \src "ls180.v:5790.102-5790.146"
78363   wire $eq$ls180.v:5790$1119_Y
78364   attribute \src "ls180.v:5791.105-5791.149"
78365   wire $eq$ls180.v:5791$1123_Y
78366   attribute \src "ls180.v:5793.102-5793.146"
78367   wire $eq$ls180.v:5793$1126_Y
78368   attribute \src "ls180.v:5794.105-5794.149"
78369   wire $eq$ls180.v:5794$1130_Y
78370   attribute \src "ls180.v:5796.102-5796.146"
78371   wire $eq$ls180.v:5796$1133_Y
78372   attribute \src "ls180.v:5797.105-5797.149"
78373   wire $eq$ls180.v:5797$1137_Y
78374   attribute \src "ls180.v:5799.102-5799.146"
78375   wire $eq$ls180.v:5799$1140_Y
78376   attribute \src "ls180.v:5800.105-5800.149"
78377   wire $eq$ls180.v:5800$1144_Y
78378   attribute \src "ls180.v:5811.32-5811.77"
78379   wire $eq$ls180.v:5811$1146_Y
78380   attribute \src "ls180.v:5813.94-5813.138"
78381   wire $eq$ls180.v:5813$1148_Y
78382   attribute \src "ls180.v:5814.97-5814.141"
78383   wire $eq$ls180.v:5814$1152_Y
78384   attribute \src "ls180.v:5816.94-5816.138"
78385   wire $eq$ls180.v:5816$1155_Y
78386   attribute \src "ls180.v:5817.97-5817.141"
78387   wire $eq$ls180.v:5817$1159_Y
78388   attribute \src "ls180.v:5819.94-5819.138"
78389   wire $eq$ls180.v:5819$1162_Y
78390   attribute \src "ls180.v:5820.97-5820.141"
78391   wire $eq$ls180.v:5820$1166_Y
78392   attribute \src "ls180.v:5822.94-5822.138"
78393   wire $eq$ls180.v:5822$1169_Y
78394   attribute \src "ls180.v:5823.97-5823.141"
78395   wire $eq$ls180.v:5823$1173_Y
78396   attribute \src "ls180.v:5825.95-5825.139"
78397   wire $eq$ls180.v:5825$1176_Y
78398   attribute \src "ls180.v:5826.98-5826.142"
78399   wire $eq$ls180.v:5826$1180_Y
78400   attribute \src "ls180.v:5828.95-5828.139"
78401   wire $eq$ls180.v:5828$1183_Y
78402   attribute \src "ls180.v:5829.98-5829.142"
78403   wire $eq$ls180.v:5829$1187_Y
78404   attribute \src "ls180.v:5837.32-5837.78"
78405   wire $eq$ls180.v:5837$1189_Y
78406   attribute \src "ls180.v:5839.93-5839.135"
78407   wire $eq$ls180.v:5839$1191_Y
78408   attribute \src "ls180.v:5840.96-5840.138"
78409   wire $eq$ls180.v:5840$1195_Y
78410   attribute \src "ls180.v:5842.92-5842.134"
78411   wire $eq$ls180.v:5842$1198_Y
78412   attribute \src "ls180.v:5843.95-5843.137"
78413   wire $eq$ls180.v:5843$1202_Y
78414   attribute \src "ls180.v:5851.32-5851.77"
78415   wire $eq$ls180.v:5851$1204_Y
78416   attribute \src "ls180.v:5853.98-5853.142"
78417   wire $eq$ls180.v:5853$1206_Y
78418   attribute \src "ls180.v:5854.101-5854.145"
78419   wire $eq$ls180.v:5854$1210_Y
78420   attribute \src "ls180.v:5856.97-5856.141"
78421   wire $eq$ls180.v:5856$1213_Y
78422   attribute \src "ls180.v:5857.100-5857.144"
78423   wire $eq$ls180.v:5857$1217_Y
78424   attribute \src "ls180.v:5859.97-5859.141"
78425   wire $eq$ls180.v:5859$1220_Y
78426   attribute \src "ls180.v:5860.100-5860.144"
78427   wire $eq$ls180.v:5860$1224_Y
78428   attribute \src "ls180.v:5862.97-5862.141"
78429   wire $eq$ls180.v:5862$1227_Y
78430   attribute \src "ls180.v:5863.100-5863.144"
78431   wire $eq$ls180.v:5863$1231_Y
78432   attribute \src "ls180.v:5865.97-5865.141"
78433   wire $eq$ls180.v:5865$1234_Y
78434   attribute \src "ls180.v:5866.100-5866.144"
78435   wire $eq$ls180.v:5866$1238_Y
78436   attribute \src "ls180.v:5868.98-5868.142"
78437   wire $eq$ls180.v:5868$1241_Y
78438   attribute \src "ls180.v:5869.101-5869.145"
78439   wire $eq$ls180.v:5869$1245_Y
78440   attribute \src "ls180.v:5871.98-5871.142"
78441   wire $eq$ls180.v:5871$1248_Y
78442   attribute \src "ls180.v:5872.101-5872.145"
78443   wire $eq$ls180.v:5872$1252_Y
78444   attribute \src "ls180.v:5874.98-5874.142"
78445   wire $eq$ls180.v:5874$1255_Y
78446   attribute \src "ls180.v:5875.101-5875.145"
78447   wire $eq$ls180.v:5875$1259_Y
78448   attribute \src "ls180.v:5877.98-5877.142"
78449   wire $eq$ls180.v:5877$1262_Y
78450   attribute \src "ls180.v:5878.101-5878.145"
78451   wire $eq$ls180.v:5878$1266_Y
78452   attribute \src "ls180.v:5888.32-5888.78"
78453   wire $eq$ls180.v:5888$1268_Y
78454   attribute \src "ls180.v:5890.98-5890.142"
78455   wire $eq$ls180.v:5890$1270_Y
78456   attribute \src "ls180.v:5891.101-5891.145"
78457   wire $eq$ls180.v:5891$1274_Y
78458   attribute \src "ls180.v:5893.97-5893.141"
78459   wire $eq$ls180.v:5893$1277_Y
78460   attribute \src "ls180.v:5894.100-5894.144"
78461   wire $eq$ls180.v:5894$1281_Y
78462   attribute \src "ls180.v:5896.97-5896.141"
78463   wire $eq$ls180.v:5896$1284_Y
78464   attribute \src "ls180.v:5897.100-5897.144"
78465   wire $eq$ls180.v:5897$1288_Y
78466   attribute \src "ls180.v:5899.97-5899.141"
78467   wire $eq$ls180.v:5899$1291_Y
78468   attribute \src "ls180.v:5900.100-5900.144"
78469   wire $eq$ls180.v:5900$1295_Y
78470   attribute \src "ls180.v:5902.97-5902.141"
78471   wire $eq$ls180.v:5902$1298_Y
78472   attribute \src "ls180.v:5903.100-5903.144"
78473   wire $eq$ls180.v:5903$1302_Y
78474   attribute \src "ls180.v:5905.98-5905.142"
78475   wire $eq$ls180.v:5905$1305_Y
78476   attribute \src "ls180.v:5906.101-5906.145"
78477   wire $eq$ls180.v:5906$1309_Y
78478   attribute \src "ls180.v:5908.98-5908.142"
78479   wire $eq$ls180.v:5908$1312_Y
78480   attribute \src "ls180.v:5909.101-5909.145"
78481   wire $eq$ls180.v:5909$1316_Y
78482   attribute \src "ls180.v:5911.98-5911.142"
78483   wire $eq$ls180.v:5911$1319_Y
78484   attribute \src "ls180.v:5912.101-5912.145"
78485   wire $eq$ls180.v:5912$1323_Y
78486   attribute \src "ls180.v:5914.98-5914.142"
78487   wire $eq$ls180.v:5914$1326_Y
78488   attribute \src "ls180.v:5915.101-5915.145"
78489   wire $eq$ls180.v:5915$1330_Y
78490   attribute \src "ls180.v:5925.32-5925.78"
78491   wire $eq$ls180.v:5925$1332_Y
78492   attribute \src "ls180.v:5927.100-5927.144"
78493   wire $eq$ls180.v:5927$1334_Y
78494   attribute \src "ls180.v:5928.103-5928.147"
78495   wire $eq$ls180.v:5928$1338_Y
78496   attribute \src "ls180.v:5930.100-5930.144"
78497   wire $eq$ls180.v:5930$1341_Y
78498   attribute \src "ls180.v:5931.103-5931.147"
78499   wire $eq$ls180.v:5931$1345_Y
78500   attribute \src "ls180.v:5933.100-5933.144"
78501   wire $eq$ls180.v:5933$1348_Y
78502   attribute \src "ls180.v:5934.103-5934.147"
78503   wire $eq$ls180.v:5934$1352_Y
78504   attribute \src "ls180.v:5936.100-5936.144"
78505   wire $eq$ls180.v:5936$1355_Y
78506   attribute \src "ls180.v:5937.103-5937.147"
78507   wire $eq$ls180.v:5937$1359_Y
78508   attribute \src "ls180.v:5939.100-5939.144"
78509   wire $eq$ls180.v:5939$1362_Y
78510   attribute \src "ls180.v:5940.103-5940.147"
78511   wire $eq$ls180.v:5940$1366_Y
78512   attribute \src "ls180.v:5942.100-5942.144"
78513   wire $eq$ls180.v:5942$1369_Y
78514   attribute \src "ls180.v:5943.103-5943.147"
78515   wire $eq$ls180.v:5943$1373_Y
78516   attribute \src "ls180.v:5945.100-5945.144"
78517   wire $eq$ls180.v:5945$1376_Y
78518   attribute \src "ls180.v:5946.103-5946.147"
78519   wire $eq$ls180.v:5946$1380_Y
78520   attribute \src "ls180.v:5948.100-5948.144"
78521   wire $eq$ls180.v:5948$1383_Y
78522   attribute \src "ls180.v:5949.103-5949.147"
78523   wire $eq$ls180.v:5949$1387_Y
78524   attribute \src "ls180.v:5951.102-5951.146"
78525   wire $eq$ls180.v:5951$1390_Y
78526   attribute \src "ls180.v:5952.105-5952.149"
78527   wire $eq$ls180.v:5952$1394_Y
78528   attribute \src "ls180.v:5954.102-5954.146"
78529   wire $eq$ls180.v:5954$1397_Y
78530   attribute \src "ls180.v:5955.105-5955.149"
78531   wire $eq$ls180.v:5955$1401_Y
78532   attribute \src "ls180.v:5957.102-5957.147"
78533   wire $eq$ls180.v:5957$1404_Y
78534   attribute \src "ls180.v:5958.105-5958.150"
78535   wire $eq$ls180.v:5958$1408_Y
78536   attribute \src "ls180.v:5960.102-5960.147"
78537   wire $eq$ls180.v:5960$1411_Y
78538   attribute \src "ls180.v:5961.105-5961.150"
78539   wire $eq$ls180.v:5961$1415_Y
78540   attribute \src "ls180.v:5963.102-5963.147"
78541   wire $eq$ls180.v:5963$1418_Y
78542   attribute \src "ls180.v:5964.105-5964.150"
78543   wire $eq$ls180.v:5964$1422_Y
78544   attribute \src "ls180.v:5966.99-5966.144"
78545   wire $eq$ls180.v:5966$1425_Y
78546   attribute \src "ls180.v:5967.102-5967.147"
78547   wire $eq$ls180.v:5967$1429_Y
78548   attribute \src "ls180.v:5969.100-5969.145"
78549   wire $eq$ls180.v:5969$1432_Y
78550   attribute \src "ls180.v:5970.103-5970.148"
78551   wire $eq$ls180.v:5970$1436_Y
78552   attribute \src "ls180.v:5987.32-5987.78"
78553   wire $eq$ls180.v:5987$1438_Y
78554   attribute \src "ls180.v:5989.104-5989.148"
78555   wire $eq$ls180.v:5989$1440_Y
78556   attribute \src "ls180.v:5990.107-5990.151"
78557   wire $eq$ls180.v:5990$1444_Y
78558   attribute \src "ls180.v:5992.104-5992.148"
78559   wire $eq$ls180.v:5992$1447_Y
78560   attribute \src "ls180.v:5993.107-5993.151"
78561   wire $eq$ls180.v:5993$1451_Y
78562   attribute \src "ls180.v:5995.104-5995.148"
78563   wire $eq$ls180.v:5995$1454_Y
78564   attribute \src "ls180.v:5996.107-5996.151"
78565   wire $eq$ls180.v:5996$1458_Y
78566   attribute \src "ls180.v:5998.104-5998.148"
78567   wire $eq$ls180.v:5998$1461_Y
78568   attribute \src "ls180.v:5999.107-5999.151"
78569   wire $eq$ls180.v:5999$1465_Y
78570   attribute \src "ls180.v:6001.103-6001.147"
78571   wire $eq$ls180.v:6001$1468_Y
78572   attribute \src "ls180.v:6002.106-6002.150"
78573   wire $eq$ls180.v:6002$1472_Y
78574   attribute \src "ls180.v:6004.103-6004.147"
78575   wire $eq$ls180.v:6004$1475_Y
78576   attribute \src "ls180.v:6005.106-6005.150"
78577   wire $eq$ls180.v:6005$1479_Y
78578   attribute \src "ls180.v:6007.103-6007.147"
78579   wire $eq$ls180.v:6007$1482_Y
78580   attribute \src "ls180.v:6008.106-6008.150"
78581   wire $eq$ls180.v:6008$1486_Y
78582   attribute \src "ls180.v:6010.103-6010.147"
78583   wire $eq$ls180.v:6010$1489_Y
78584   attribute \src "ls180.v:6011.106-6011.150"
78585   wire $eq$ls180.v:6011$1493_Y
78586   attribute \src "ls180.v:6013.94-6013.138"
78587   wire $eq$ls180.v:6013$1496_Y
78588   attribute \src "ls180.v:6014.97-6014.141"
78589   wire $eq$ls180.v:6014$1500_Y
78590   attribute \src "ls180.v:6016.105-6016.149"
78591   wire $eq$ls180.v:6016$1503_Y
78592   attribute \src "ls180.v:6017.108-6017.152"
78593   wire $eq$ls180.v:6017$1507_Y
78594   attribute \src "ls180.v:6019.105-6019.150"
78595   wire $eq$ls180.v:6019$1510_Y
78596   attribute \src "ls180.v:6020.108-6020.153"
78597   wire $eq$ls180.v:6020$1514_Y
78598   attribute \src "ls180.v:6022.105-6022.150"
78599   wire $eq$ls180.v:6022$1517_Y
78600   attribute \src "ls180.v:6023.108-6023.153"
78601   wire $eq$ls180.v:6023$1521_Y
78602   attribute \src "ls180.v:6025.105-6025.150"
78603   wire $eq$ls180.v:6025$1524_Y
78604   attribute \src "ls180.v:6026.108-6026.153"
78605   wire $eq$ls180.v:6026$1528_Y
78606   attribute \src "ls180.v:6028.105-6028.150"
78607   wire $eq$ls180.v:6028$1531_Y
78608   attribute \src "ls180.v:6029.108-6029.153"
78609   wire $eq$ls180.v:6029$1535_Y
78610   attribute \src "ls180.v:6031.105-6031.150"
78611   wire $eq$ls180.v:6031$1538_Y
78612   attribute \src "ls180.v:6032.108-6032.153"
78613   wire $eq$ls180.v:6032$1542_Y
78614   attribute \src "ls180.v:6034.104-6034.149"
78615   wire $eq$ls180.v:6034$1545_Y
78616   attribute \src "ls180.v:6035.107-6035.152"
78617   wire $eq$ls180.v:6035$1549_Y
78618   attribute \src "ls180.v:6037.104-6037.149"
78619   wire $eq$ls180.v:6037$1552_Y
78620   attribute \src "ls180.v:6038.107-6038.152"
78621   wire $eq$ls180.v:6038$1556_Y
78622   attribute \src "ls180.v:6040.104-6040.149"
78623   wire $eq$ls180.v:6040$1559_Y
78624   attribute \src "ls180.v:6041.107-6041.152"
78625   wire $eq$ls180.v:6041$1563_Y
78626   attribute \src "ls180.v:6043.104-6043.149"
78627   wire $eq$ls180.v:6043$1566_Y
78628   attribute \src "ls180.v:6044.107-6044.152"
78629   wire $eq$ls180.v:6044$1570_Y
78630   attribute \src "ls180.v:6046.104-6046.149"
78631   wire $eq$ls180.v:6046$1573_Y
78632   attribute \src "ls180.v:6047.107-6047.152"
78633   wire $eq$ls180.v:6047$1577_Y
78634   attribute \src "ls180.v:6049.104-6049.149"
78635   wire $eq$ls180.v:6049$1580_Y
78636   attribute \src "ls180.v:6050.107-6050.152"
78637   wire $eq$ls180.v:6050$1584_Y
78638   attribute \src "ls180.v:6052.104-6052.149"
78639   wire $eq$ls180.v:6052$1587_Y
78640   attribute \src "ls180.v:6053.107-6053.152"
78641   wire $eq$ls180.v:6053$1591_Y
78642   attribute \src "ls180.v:6055.104-6055.149"
78643   wire $eq$ls180.v:6055$1594_Y
78644   attribute \src "ls180.v:6056.107-6056.152"
78645   wire $eq$ls180.v:6056$1598_Y
78646   attribute \src "ls180.v:6058.104-6058.149"
78647   wire $eq$ls180.v:6058$1601_Y
78648   attribute \src "ls180.v:6059.107-6059.152"
78649   wire $eq$ls180.v:6059$1605_Y
78650   attribute \src "ls180.v:6061.104-6061.149"
78651   wire $eq$ls180.v:6061$1608_Y
78652   attribute \src "ls180.v:6062.107-6062.152"
78653   wire $eq$ls180.v:6062$1612_Y
78654   attribute \src "ls180.v:6064.100-6064.145"
78655   wire $eq$ls180.v:6064$1615_Y
78656   attribute \src "ls180.v:6065.103-6065.148"
78657   wire $eq$ls180.v:6065$1619_Y
78658   attribute \src "ls180.v:6067.101-6067.146"
78659   wire $eq$ls180.v:6067$1622_Y
78660   attribute \src "ls180.v:6068.104-6068.149"
78661   wire $eq$ls180.v:6068$1626_Y
78662   attribute \src "ls180.v:6070.104-6070.149"
78663   wire $eq$ls180.v:6070$1629_Y
78664   attribute \src "ls180.v:6071.107-6071.152"
78665   wire $eq$ls180.v:6071$1633_Y
78666   attribute \src "ls180.v:6073.104-6073.149"
78667   wire $eq$ls180.v:6073$1636_Y
78668   attribute \src "ls180.v:6074.107-6074.152"
78669   wire $eq$ls180.v:6074$1640_Y
78670   attribute \src "ls180.v:6076.103-6076.148"
78671   wire $eq$ls180.v:6076$1643_Y
78672   attribute \src "ls180.v:6077.106-6077.151"
78673   wire $eq$ls180.v:6077$1647_Y
78674   attribute \src "ls180.v:6079.103-6079.148"
78675   wire $eq$ls180.v:6079$1650_Y
78676   attribute \src "ls180.v:6080.106-6080.151"
78677   wire $eq$ls180.v:6080$1654_Y
78678   attribute \src "ls180.v:6082.103-6082.148"
78679   wire $eq$ls180.v:6082$1657_Y
78680   attribute \src "ls180.v:6083.106-6083.151"
78681   wire $eq$ls180.v:6083$1661_Y
78682   attribute \src "ls180.v:6085.103-6085.148"
78683   wire $eq$ls180.v:6085$1664_Y
78684   attribute \src "ls180.v:6086.106-6086.151"
78685   wire $eq$ls180.v:6086$1668_Y
78686   attribute \src "ls180.v:6122.32-6122.78"
78687   wire $eq$ls180.v:6122$1670_Y
78688   attribute \src "ls180.v:6124.100-6124.144"
78689   wire $eq$ls180.v:6124$1672_Y
78690   attribute \src "ls180.v:6125.103-6125.147"
78691   wire $eq$ls180.v:6125$1676_Y
78692   attribute \src "ls180.v:6127.100-6127.144"
78693   wire $eq$ls180.v:6127$1679_Y
78694   attribute \src "ls180.v:6128.103-6128.147"
78695   wire $eq$ls180.v:6128$1683_Y
78696   attribute \src "ls180.v:6130.100-6130.144"
78697   wire $eq$ls180.v:6130$1686_Y
78698   attribute \src "ls180.v:6131.103-6131.147"
78699   wire $eq$ls180.v:6131$1690_Y
78700   attribute \src "ls180.v:6133.100-6133.144"
78701   wire $eq$ls180.v:6133$1693_Y
78702   attribute \src "ls180.v:6134.103-6134.147"
78703   wire $eq$ls180.v:6134$1697_Y
78704   attribute \src "ls180.v:6136.100-6136.144"
78705   wire $eq$ls180.v:6136$1700_Y
78706   attribute \src "ls180.v:6137.103-6137.147"
78707   wire $eq$ls180.v:6137$1704_Y
78708   attribute \src "ls180.v:6139.100-6139.144"
78709   wire $eq$ls180.v:6139$1707_Y
78710   attribute \src "ls180.v:6140.103-6140.147"
78711   wire $eq$ls180.v:6140$1711_Y
78712   attribute \src "ls180.v:6142.100-6142.144"
78713   wire $eq$ls180.v:6142$1714_Y
78714   attribute \src "ls180.v:6143.103-6143.147"
78715   wire $eq$ls180.v:6143$1718_Y
78716   attribute \src "ls180.v:6145.100-6145.144"
78717   wire $eq$ls180.v:6145$1721_Y
78718   attribute \src "ls180.v:6146.103-6146.147"
78719   wire $eq$ls180.v:6146$1725_Y
78720   attribute \src "ls180.v:6148.102-6148.146"
78721   wire $eq$ls180.v:6148$1728_Y
78722   attribute \src "ls180.v:6149.105-6149.149"
78723   wire $eq$ls180.v:6149$1732_Y
78724   attribute \src "ls180.v:6151.102-6151.146"
78725   wire $eq$ls180.v:6151$1735_Y
78726   attribute \src "ls180.v:6152.105-6152.149"
78727   wire $eq$ls180.v:6152$1739_Y
78728   attribute \src "ls180.v:6154.102-6154.147"
78729   wire $eq$ls180.v:6154$1742_Y
78730   attribute \src "ls180.v:6155.105-6155.150"
78731   wire $eq$ls180.v:6155$1746_Y
78732   attribute \src "ls180.v:6157.102-6157.147"
78733   wire $eq$ls180.v:6157$1749_Y
78734   attribute \src "ls180.v:6158.105-6158.150"
78735   wire $eq$ls180.v:6158$1753_Y
78736   attribute \src "ls180.v:6160.102-6160.147"
78737   wire $eq$ls180.v:6160$1756_Y
78738   attribute \src "ls180.v:6161.105-6161.150"
78739   wire $eq$ls180.v:6161$1760_Y
78740   attribute \src "ls180.v:6163.99-6163.144"
78741   wire $eq$ls180.v:6163$1763_Y
78742   attribute \src "ls180.v:6164.102-6164.147"
78743   wire $eq$ls180.v:6164$1767_Y
78744   attribute \src "ls180.v:6166.100-6166.145"
78745   wire $eq$ls180.v:6166$1770_Y
78746   attribute \src "ls180.v:6167.103-6167.148"
78747   wire $eq$ls180.v:6167$1774_Y
78748   attribute \src "ls180.v:6169.102-6169.147"
78749   wire $eq$ls180.v:6169$1777_Y
78750   attribute \src "ls180.v:6170.105-6170.150"
78751   wire $eq$ls180.v:6170$1781_Y
78752   attribute \src "ls180.v:6172.102-6172.147"
78753   wire $eq$ls180.v:6172$1784_Y
78754   attribute \src "ls180.v:6173.105-6173.150"
78755   wire $eq$ls180.v:6173$1788_Y
78756   attribute \src "ls180.v:6175.102-6175.147"
78757   wire $eq$ls180.v:6175$1791_Y
78758   attribute \src "ls180.v:6176.105-6176.150"
78759   wire $eq$ls180.v:6176$1795_Y
78760   attribute \src "ls180.v:6178.102-6178.147"
78761   wire $eq$ls180.v:6178$1798_Y
78762   attribute \src "ls180.v:6179.105-6179.150"
78763   wire $eq$ls180.v:6179$1802_Y
78764   attribute \src "ls180.v:6201.32-6201.78"
78765   wire $eq$ls180.v:6201$1804_Y
78766   attribute \src "ls180.v:6203.102-6203.146"
78767   wire $eq$ls180.v:6203$1806_Y
78768   attribute \src "ls180.v:6204.105-6204.149"
78769   wire $eq$ls180.v:6204$1810_Y
78770   attribute \src "ls180.v:6206.107-6206.151"
78771   wire $eq$ls180.v:6206$1813_Y
78772   attribute \src "ls180.v:6207.110-6207.154"
78773   wire $eq$ls180.v:6207$1817_Y
78774   attribute \src "ls180.v:6209.107-6209.151"
78775   wire $eq$ls180.v:6209$1820_Y
78776   attribute \src "ls180.v:6210.110-6210.154"
78777   wire $eq$ls180.v:6210$1824_Y
78778   attribute \src "ls180.v:6212.100-6212.144"
78779   wire $eq$ls180.v:6212$1827_Y
78780   attribute \src "ls180.v:6213.103-6213.147"
78781   wire $eq$ls180.v:6213$1831_Y
78782   attribute \src "ls180.v:6218.32-6218.77"
78783   wire $eq$ls180.v:6218$1833_Y
78784   attribute \src "ls180.v:6220.104-6220.148"
78785   wire $eq$ls180.v:6220$1835_Y
78786   attribute \src "ls180.v:6221.107-6221.151"
78787   wire $eq$ls180.v:6221$1839_Y
78788   attribute \src "ls180.v:6223.108-6223.152"
78789   wire $eq$ls180.v:6223$1842_Y
78790   attribute \src "ls180.v:6224.111-6224.155"
78791   wire $eq$ls180.v:6224$1846_Y
78792   attribute \src "ls180.v:6226.98-6226.142"
78793   wire $eq$ls180.v:6226$1849_Y
78794   attribute \src "ls180.v:6227.101-6227.145"
78795   wire $eq$ls180.v:6227$1853_Y
78796   attribute \src "ls180.v:6229.108-6229.152"
78797   wire $eq$ls180.v:6229$1856_Y
78798   attribute \src "ls180.v:6230.111-6230.155"
78799   wire $eq$ls180.v:6230$1860_Y
78800   attribute \src "ls180.v:6232.108-6232.152"
78801   wire $eq$ls180.v:6232$1863_Y
78802   attribute \src "ls180.v:6233.111-6233.155"
78803   wire $eq$ls180.v:6233$1867_Y
78804   attribute \src "ls180.v:6235.109-6235.153"
78805   wire $eq$ls180.v:6235$1870_Y
78806   attribute \src "ls180.v:6236.112-6236.156"
78807   wire $eq$ls180.v:6236$1874_Y
78808   attribute \src "ls180.v:6238.107-6238.151"
78809   wire $eq$ls180.v:6238$1877_Y
78810   attribute \src "ls180.v:6239.110-6239.154"
78811   wire $eq$ls180.v:6239$1881_Y
78812   attribute \src "ls180.v:6241.107-6241.151"
78813   wire $eq$ls180.v:6241$1884_Y
78814   attribute \src "ls180.v:6242.110-6242.154"
78815   wire $eq$ls180.v:6242$1888_Y
78816   attribute \src "ls180.v:6244.107-6244.151"
78817   wire $eq$ls180.v:6244$1891_Y
78818   attribute \src "ls180.v:6245.110-6245.154"
78819   wire $eq$ls180.v:6245$1895_Y
78820   attribute \src "ls180.v:6247.107-6247.151"
78821   wire $eq$ls180.v:6247$1898_Y
78822   attribute \src "ls180.v:6248.110-6248.154"
78823   wire $eq$ls180.v:6248$1902_Y
78824   attribute \src "ls180.v:6263.33-6263.79"
78825   wire $eq$ls180.v:6263$1904_Y
78826   attribute \src "ls180.v:6265.102-6265.147"
78827   wire $eq$ls180.v:6265$1906_Y
78828   attribute \src "ls180.v:6266.105-6266.150"
78829   wire $eq$ls180.v:6266$1910_Y
78830   attribute \src "ls180.v:6268.102-6268.147"
78831   wire $eq$ls180.v:6268$1913_Y
78832   attribute \src "ls180.v:6269.105-6269.150"
78833   wire $eq$ls180.v:6269$1917_Y
78834   attribute \src "ls180.v:6271.100-6271.145"
78835   wire $eq$ls180.v:6271$1920_Y
78836   attribute \src "ls180.v:6272.103-6272.148"
78837   wire $eq$ls180.v:6272$1924_Y
78838   attribute \src "ls180.v:6274.99-6274.144"
78839   wire $eq$ls180.v:6274$1927_Y
78840   attribute \src "ls180.v:6275.102-6275.147"
78841   wire $eq$ls180.v:6275$1931_Y
78842   attribute \src "ls180.v:6277.98-6277.143"
78843   wire $eq$ls180.v:6277$1934_Y
78844   attribute \src "ls180.v:6278.101-6278.146"
78845   wire $eq$ls180.v:6278$1938_Y
78846   attribute \src "ls180.v:6280.97-6280.142"
78847   wire $eq$ls180.v:6280$1941_Y
78848   attribute \src "ls180.v:6281.100-6281.145"
78849   wire $eq$ls180.v:6281$1945_Y
78850   attribute \src "ls180.v:6283.103-6283.148"
78851   wire $eq$ls180.v:6283$1948_Y
78852   attribute \src "ls180.v:6284.106-6284.151"
78853   wire $eq$ls180.v:6284$1952_Y
78854   attribute \src "ls180.v:6303.33-6303.79"
78855   wire $eq$ls180.v:6303$1955_Y
78856   attribute \src "ls180.v:6305.102-6305.147"
78857   wire $eq$ls180.v:6305$1957_Y
78858   attribute \src "ls180.v:6306.105-6306.150"
78859   wire $eq$ls180.v:6306$1961_Y
78860   attribute \src "ls180.v:6308.102-6308.147"
78861   wire $eq$ls180.v:6308$1964_Y
78862   attribute \src "ls180.v:6309.105-6309.150"
78863   wire $eq$ls180.v:6309$1968_Y
78864   attribute \src "ls180.v:6311.100-6311.145"
78865   wire $eq$ls180.v:6311$1971_Y
78866   attribute \src "ls180.v:6312.103-6312.148"
78867   wire $eq$ls180.v:6312$1975_Y
78868   attribute \src "ls180.v:6314.99-6314.144"
78869   wire $eq$ls180.v:6314$1978_Y
78870   attribute \src "ls180.v:6315.102-6315.147"
78871   wire $eq$ls180.v:6315$1982_Y
78872   attribute \src "ls180.v:6317.98-6317.143"
78873   wire $eq$ls180.v:6317$1985_Y
78874   attribute \src "ls180.v:6318.101-6318.146"
78875   wire $eq$ls180.v:6318$1989_Y
78876   attribute \src "ls180.v:6320.97-6320.142"
78877   wire $eq$ls180.v:6320$1992_Y
78878   attribute \src "ls180.v:6321.100-6321.145"
78879   wire $eq$ls180.v:6321$1996_Y
78880   attribute \src "ls180.v:6323.103-6323.148"
78881   wire $eq$ls180.v:6323$1999_Y
78882   attribute \src "ls180.v:6324.106-6324.151"
78883   wire $eq$ls180.v:6324$2003_Y
78884   attribute \src "ls180.v:6326.106-6326.151"
78885   wire $eq$ls180.v:6326$2006_Y
78886   attribute \src "ls180.v:6327.109-6327.154"
78887   wire $eq$ls180.v:6327$2010_Y
78888   attribute \src "ls180.v:6329.106-6329.151"
78889   wire $eq$ls180.v:6329$2013_Y
78890   attribute \src "ls180.v:6330.109-6330.154"
78891   wire $eq$ls180.v:6330$2017_Y
78892   attribute \src "ls180.v:6351.33-6351.79"
78893   wire $eq$ls180.v:6351$2020_Y
78894   attribute \src "ls180.v:6353.99-6353.144"
78895   wire $eq$ls180.v:6353$2022_Y
78896   attribute \src "ls180.v:6354.102-6354.147"
78897   wire $eq$ls180.v:6354$2026_Y
78898   attribute \src "ls180.v:6356.99-6356.144"
78899   wire $eq$ls180.v:6356$2029_Y
78900   attribute \src "ls180.v:6357.102-6357.147"
78901   wire $eq$ls180.v:6357$2033_Y
78902   attribute \src "ls180.v:6359.99-6359.144"
78903   wire $eq$ls180.v:6359$2036_Y
78904   attribute \src "ls180.v:6360.102-6360.147"
78905   wire $eq$ls180.v:6360$2040_Y
78906   attribute \src "ls180.v:6362.99-6362.144"
78907   wire $eq$ls180.v:6362$2043_Y
78908   attribute \src "ls180.v:6363.102-6363.147"
78909   wire $eq$ls180.v:6363$2047_Y
78910   attribute \src "ls180.v:6365.101-6365.146"
78911   wire $eq$ls180.v:6365$2050_Y
78912   attribute \src "ls180.v:6366.104-6366.149"
78913   wire $eq$ls180.v:6366$2054_Y
78914   attribute \src "ls180.v:6368.101-6368.146"
78915   wire $eq$ls180.v:6368$2057_Y
78916   attribute \src "ls180.v:6369.104-6369.149"
78917   wire $eq$ls180.v:6369$2061_Y
78918   attribute \src "ls180.v:6371.101-6371.146"
78919   wire $eq$ls180.v:6371$2064_Y
78920   attribute \src "ls180.v:6372.104-6372.149"
78921   wire $eq$ls180.v:6372$2068_Y
78922   attribute \src "ls180.v:6374.101-6374.146"
78923   wire $eq$ls180.v:6374$2071_Y
78924   attribute \src "ls180.v:6375.104-6375.149"
78925   wire $eq$ls180.v:6375$2075_Y
78926   attribute \src "ls180.v:6377.97-6377.142"
78927   wire $eq$ls180.v:6377$2078_Y
78928   attribute \src "ls180.v:6378.100-6378.145"
78929   wire $eq$ls180.v:6378$2082_Y
78930   attribute \src "ls180.v:6380.107-6380.152"
78931   wire $eq$ls180.v:6380$2085_Y
78932   attribute \src "ls180.v:6381.110-6381.155"
78933   wire $eq$ls180.v:6381$2089_Y
78934   attribute \src "ls180.v:6383.100-6383.146"
78935   wire $eq$ls180.v:6383$2092_Y
78936   attribute \src "ls180.v:6384.103-6384.149"
78937   wire $eq$ls180.v:6384$2096_Y
78938   attribute \src "ls180.v:6386.100-6386.146"
78939   wire $eq$ls180.v:6386$2099_Y
78940   attribute \src "ls180.v:6387.103-6387.149"
78941   wire $eq$ls180.v:6387$2103_Y
78942   attribute \src "ls180.v:6389.100-6389.146"
78943   wire $eq$ls180.v:6389$2106_Y
78944   attribute \src "ls180.v:6390.103-6390.149"
78945   wire $eq$ls180.v:6390$2110_Y
78946   attribute \src "ls180.v:6392.100-6392.146"
78947   wire $eq$ls180.v:6392$2113_Y
78948   attribute \src "ls180.v:6393.103-6393.149"
78949   wire $eq$ls180.v:6393$2117_Y
78950   attribute \src "ls180.v:6395.112-6395.158"
78951   wire $eq$ls180.v:6395$2120_Y
78952   attribute \src "ls180.v:6396.115-6396.161"
78953   wire $eq$ls180.v:6396$2124_Y
78954   attribute \src "ls180.v:6398.113-6398.159"
78955   wire $eq$ls180.v:6398$2127_Y
78956   attribute \src "ls180.v:6399.116-6399.162"
78957   wire $eq$ls180.v:6399$2131_Y
78958   attribute \src "ls180.v:6401.104-6401.150"
78959   wire $eq$ls180.v:6401$2134_Y
78960   attribute \src "ls180.v:6402.107-6402.153"
78961   wire $eq$ls180.v:6402$2138_Y
78962   attribute \src "ls180.v:6419.33-6419.79"
78963   wire $eq$ls180.v:6419$2140_Y
78964   attribute \src "ls180.v:6421.90-6421.135"
78965   wire $eq$ls180.v:6421$2142_Y
78966   attribute \src "ls180.v:6422.93-6422.138"
78967   wire $eq$ls180.v:6422$2146_Y
78968   attribute \src "ls180.v:6424.100-6424.145"
78969   wire $eq$ls180.v:6424$2149_Y
78970   attribute \src "ls180.v:6425.103-6425.148"
78971   wire $eq$ls180.v:6425$2153_Y
78972   attribute \src "ls180.v:6427.101-6427.146"
78973   wire $eq$ls180.v:6427$2156_Y
78974   attribute \src "ls180.v:6428.104-6428.149"
78975   wire $eq$ls180.v:6428$2160_Y
78976   attribute \src "ls180.v:6430.105-6430.150"
78977   wire $eq$ls180.v:6430$2163_Y
78978   attribute \src "ls180.v:6431.108-6431.153"
78979   wire $eq$ls180.v:6431$2167_Y
78980   attribute \src "ls180.v:6433.106-6433.151"
78981   wire $eq$ls180.v:6433$2170_Y
78982   attribute \src "ls180.v:6434.109-6434.154"
78983   wire $eq$ls180.v:6434$2174_Y
78984   attribute \src "ls180.v:6436.104-6436.149"
78985   wire $eq$ls180.v:6436$2177_Y
78986   attribute \src "ls180.v:6437.107-6437.152"
78987   wire $eq$ls180.v:6437$2181_Y
78988   attribute \src "ls180.v:6439.101-6439.146"
78989   wire $eq$ls180.v:6439$2184_Y
78990   attribute \src "ls180.v:6440.104-6440.149"
78991   wire $eq$ls180.v:6440$2188_Y
78992   attribute \src "ls180.v:6442.100-6442.145"
78993   wire $eq$ls180.v:6442$2191_Y
78994   attribute \src "ls180.v:6443.103-6443.148"
78995   wire $eq$ls180.v:6443$2195_Y
78996   attribute \src "ls180.v:6453.33-6453.79"
78997   wire $eq$ls180.v:6453$2197_Y
78998   attribute \src "ls180.v:6455.106-6455.151"
78999   wire $eq$ls180.v:6455$2199_Y
79000   attribute \src "ls180.v:6456.109-6456.154"
79001   wire $eq$ls180.v:6456$2203_Y
79002   attribute \src "ls180.v:6458.106-6458.151"
79003   wire $eq$ls180.v:6458$2206_Y
79004   attribute \src "ls180.v:6459.109-6459.154"
79005   wire $eq$ls180.v:6459$2210_Y
79006   attribute \src "ls180.v:6461.106-6461.151"
79007   wire $eq$ls180.v:6461$2213_Y
79008   attribute \src "ls180.v:6462.109-6462.154"
79009   wire $eq$ls180.v:6462$2217_Y
79010   attribute \src "ls180.v:6464.106-6464.151"
79011   wire $eq$ls180.v:6464$2220_Y
79012   attribute \src "ls180.v:6465.109-6465.154"
79013   wire $eq$ls180.v:6465$2224_Y
79014   attribute \src "ls180.v:6846.41-6846.81"
79015   wire $eq$ls180.v:6846$2261_Y
79016   attribute \src "ls180.v:6846.144-6846.177"
79017   wire $eq$ls180.v:6846$2262_Y
79018   attribute \src "ls180.v:6846.219-6846.252"
79019   wire $eq$ls180.v:6846$2265_Y
79020   attribute \src "ls180.v:6846.294-6846.327"
79021   wire $eq$ls180.v:6846$2268_Y
79022   attribute \src "ls180.v:6870.41-6870.81"
79023   wire $eq$ls180.v:6870$2277_Y
79024   attribute \src "ls180.v:6870.144-6870.177"
79025   wire $eq$ls180.v:6870$2278_Y
79026   attribute \src "ls180.v:6870.219-6870.252"
79027   wire $eq$ls180.v:6870$2281_Y
79028   attribute \src "ls180.v:6870.294-6870.327"
79029   wire $eq$ls180.v:6870$2284_Y
79030   attribute \src "ls180.v:6894.41-6894.81"
79031   wire $eq$ls180.v:6894$2293_Y
79032   attribute \src "ls180.v:6894.144-6894.177"
79033   wire $eq$ls180.v:6894$2294_Y
79034   attribute \src "ls180.v:6894.219-6894.252"
79035   wire $eq$ls180.v:6894$2297_Y
79036   attribute \src "ls180.v:6894.294-6894.327"
79037   wire $eq$ls180.v:6894$2300_Y
79038   attribute \src "ls180.v:6918.41-6918.81"
79039   wire $eq$ls180.v:6918$2309_Y
79040   attribute \src "ls180.v:6918.144-6918.177"
79041   wire $eq$ls180.v:6918$2310_Y
79042   attribute \src "ls180.v:6918.219-6918.252"
79043   wire $eq$ls180.v:6918$2313_Y
79044   attribute \src "ls180.v:6918.294-6918.327"
79045   wire $eq$ls180.v:6918$2316_Y
79046   attribute \src "ls180.v:7511.8-7511.38"
79047   wire $eq$ls180.v:7511$2419_Y
79048   attribute \src "ls180.v:7542.8-7542.42"
79049   wire $eq$ls180.v:7542$2427_Y
79050   attribute \src "ls180.v:7562.38-7562.74"
79051   wire $eq$ls180.v:7562$2430_Y
79052   attribute \src "ls180.v:7569.7-7569.43"
79053   wire $eq$ls180.v:7569$2432_Y
79054   attribute \src "ls180.v:7576.7-7576.43"
79055   wire $eq$ls180.v:7576$2433_Y
79056   attribute \src "ls180.v:7584.7-7584.43"
79057   wire $eq$ls180.v:7584$2434_Y
79058   attribute \src "ls180.v:7636.9-7636.54"
79059   wire $eq$ls180.v:7636$2452_Y
79060   attribute \src "ls180.v:7682.9-7682.54"
79061   wire $eq$ls180.v:7682$2468_Y
79062   attribute \src "ls180.v:7728.9-7728.54"
79063   wire $eq$ls180.v:7728$2484_Y
79064   attribute \src "ls180.v:7774.9-7774.54"
79065   wire $eq$ls180.v:7774$2500_Y
79066   attribute \src "ls180.v:7924.9-7924.41"
79067   wire $eq$ls180.v:7924$2512_Y
79068   attribute \src "ls180.v:7939.9-7939.41"
79069   wire $eq$ls180.v:7939$2515_Y
79070   attribute \src "ls180.v:7945.49-7945.82"
79071   wire $eq$ls180.v:7945$2516_Y
79072   attribute \src "ls180.v:7945.131-7945.164"
79073   wire $eq$ls180.v:7945$2519_Y
79074   attribute \src "ls180.v:7945.213-7945.246"
79075   wire $eq$ls180.v:7945$2522_Y
79076   attribute \src "ls180.v:7945.295-7945.328"
79077   wire $eq$ls180.v:7945$2525_Y
79078   attribute \src "ls180.v:7946.50-7946.83"
79079   wire $eq$ls180.v:7946$2528_Y
79080   attribute \src "ls180.v:7946.132-7946.165"
79081   wire $eq$ls180.v:7946$2531_Y
79082   attribute \src "ls180.v:7946.214-7946.247"
79083   wire $eq$ls180.v:7946$2534_Y
79084   attribute \src "ls180.v:7946.296-7946.329"
79085   wire $eq$ls180.v:7946$2537_Y
79086   attribute \src "ls180.v:7981.9-7981.42"
79087   wire $eq$ls180.v:7981$2549_Y
79088   attribute \src "ls180.v:7984.10-7984.43"
79089   wire $eq$ls180.v:7984$2550_Y
79090   attribute \src "ls180.v:8010.9-8010.42"
79091   wire $eq$ls180.v:8010$2556_Y
79092   attribute \src "ls180.v:8015.10-8015.43"
79093   wire $eq$ls180.v:8015$2557_Y
79094   attribute \src "ls180.v:8222.9-8222.53"
79095   wire $eq$ls180.v:8222$2606_Y
79096   attribute \src "ls180.v:8303.9-8303.54"
79097   wire $eq$ls180.v:8303$2618_Y
79098   attribute \src "ls180.v:8382.9-8382.55"
79099   wire $eq$ls180.v:8382$2630_Y
79100   attribute \src "ls180.v:8605.9-8605.49"
79101   wire $eq$ls180.v:8605$2663_Y
79102   attribute \src "ls180.v:8181.8-8181.54"
79103   wire $ge$ls180.v:8181$2598_Y
79104   attribute \src "ls180.v:8195.8-8195.54"
79105   wire $ge$ls180.v:8195$2602_Y
79106   attribute \src "ls180.v:5155.47-5155.83"
79107   wire $gt$ls180.v:5155$914_Y
79108   attribute \src "ls180.v:5161.7-5161.43"
79109   wire $lt$ls180.v:5161$917_Y
79110   attribute \src "ls180.v:8176.8-8176.43"
79111   wire $lt$ls180.v:8176$2596_Y
79112   attribute \src "ls180.v:8190.8-8190.43"
79113   wire $lt$ls180.v:8190$2600_Y
79114   attribute \src "ls180.v:10071.33-10071.36"
79115   wire width 32 $memrd$\mem$ls180.v:10071$2705_DATA
79116   attribute \src "ls180.v:10082.12-10082.19"
79117   wire width 25 $memrd$\storage$ls180.v:10082$2710_DATA
79118   attribute \src "ls180.v:10089.68-10089.75"
79119   wire width 25 $memrd$\storage$ls180.v:10089$2712_DATA
79120   attribute \src "ls180.v:10096.14-10096.23"
79121   wire width 25 $memrd$\storage_1$ls180.v:10096$2717_DATA
79122   attribute \src "ls180.v:10103.68-10103.77"
79123   wire width 25 $memrd$\storage_1$ls180.v:10103$2719_DATA
79124   attribute \src "ls180.v:10110.14-10110.23"
79125   wire width 25 $memrd$\storage_2$ls180.v:10110$2724_DATA
79126   attribute \src "ls180.v:10117.68-10117.77"
79127   wire width 25 $memrd$\storage_2$ls180.v:10117$2726_DATA
79128   attribute \src "ls180.v:10124.14-10124.23"
79129   wire width 25 $memrd$\storage_3$ls180.v:10124$2731_DATA
79130   attribute \src "ls180.v:10131.68-10131.77"
79131   wire width 25 $memrd$\storage_3$ls180.v:10131$2733_DATA
79132   attribute \src "ls180.v:10139.14-10139.23"
79133   wire width 10 $memrd$\storage_4$ls180.v:10139$2738_DATA
79134   attribute \src "ls180.v:10144.15-10144.24"
79135   wire width 10 $memrd$\storage_4$ls180.v:10144$2740_DATA
79136   attribute \src "ls180.v:10156.14-10156.23"
79137   wire width 10 $memrd$\storage_5$ls180.v:10156$2745_DATA
79138   attribute \src "ls180.v:10161.15-10161.24"
79139   wire width 10 $memrd$\storage_5$ls180.v:10161$2747_DATA
79140   attribute \src "ls180.v:10172.14-10172.23"
79141   wire width 10 $memrd$\storage_6$ls180.v:10172$2752_DATA
79142   attribute \src "ls180.v:10179.45-10179.54"
79143   wire width 10 $memrd$\storage_6$ls180.v:10179$2754_DATA
79144   attribute \src "ls180.v:10186.14-10186.23"
79145   wire width 10 $memrd$\storage_7$ls180.v:10186$2759_DATA
79146   attribute \src "ls180.v:10193.45-10193.54"
79147   wire width 10 $memrd$\storage_7$ls180.v:10193$2761_DATA
79148   attribute \src "ls180.v:0.0-0.0"
79149   wire width 7 $memwr$\mem$ls180.v:10061$1_ADDR
79150   attribute \src "ls180.v:0.0-0.0"
79151   wire width 32 $memwr$\mem$ls180.v:10061$1_DATA
79152   attribute \src "ls180.v:0.0-0.0"
79153   wire width 32 $memwr$\mem$ls180.v:10061$1_EN
79154   attribute \src "ls180.v:0.0-0.0"
79155   wire width 7 $memwr$\mem$ls180.v:10063$2_ADDR
79156   attribute \src "ls180.v:0.0-0.0"
79157   wire width 32 $memwr$\mem$ls180.v:10063$2_DATA
79158   attribute \src "ls180.v:0.0-0.0"
79159   wire width 32 $memwr$\mem$ls180.v:10063$2_EN
79160   attribute \src "ls180.v:0.0-0.0"
79161   wire width 7 $memwr$\mem$ls180.v:10065$3_ADDR
79162   attribute \src "ls180.v:0.0-0.0"
79163   wire width 32 $memwr$\mem$ls180.v:10065$3_DATA
79164   attribute \src "ls180.v:0.0-0.0"
79165   wire width 32 $memwr$\mem$ls180.v:10065$3_EN
79166   attribute \src "ls180.v:0.0-0.0"
79167   wire width 7 $memwr$\mem$ls180.v:10067$4_ADDR
79168   attribute \src "ls180.v:0.0-0.0"
79169   wire width 32 $memwr$\mem$ls180.v:10067$4_DATA
79170   attribute \src "ls180.v:0.0-0.0"
79171   wire width 32 $memwr$\mem$ls180.v:10067$4_EN
79172   attribute \src "ls180.v:0.0-0.0"
79173   wire width 3 $memwr$\storage$ls180.v:10081$5_ADDR
79174   attribute \src "ls180.v:0.0-0.0"
79175   wire width 25 $memwr$\storage$ls180.v:10081$5_DATA
79176   attribute \src "ls180.v:0.0-0.0"
79177   wire width 25 $memwr$\storage$ls180.v:10081$5_EN
79178   attribute \src "ls180.v:0.0-0.0"
79179   wire width 3 $memwr$\storage_1$ls180.v:10095$6_ADDR
79180   attribute \src "ls180.v:0.0-0.0"
79181   wire width 25 $memwr$\storage_1$ls180.v:10095$6_DATA
79182   attribute \src "ls180.v:0.0-0.0"
79183   wire width 25 $memwr$\storage_1$ls180.v:10095$6_EN
79184   attribute \src "ls180.v:0.0-0.0"
79185   wire width 3 $memwr$\storage_2$ls180.v:10109$7_ADDR
79186   attribute \src "ls180.v:0.0-0.0"
79187   wire width 25 $memwr$\storage_2$ls180.v:10109$7_DATA
79188   attribute \src "ls180.v:0.0-0.0"
79189   wire width 25 $memwr$\storage_2$ls180.v:10109$7_EN
79190   attribute \src "ls180.v:0.0-0.0"
79191   wire width 3 $memwr$\storage_3$ls180.v:10123$8_ADDR
79192   attribute \src "ls180.v:0.0-0.0"
79193   wire width 25 $memwr$\storage_3$ls180.v:10123$8_DATA
79194   attribute \src "ls180.v:0.0-0.0"
79195   wire width 25 $memwr$\storage_3$ls180.v:10123$8_EN
79196   attribute \src "ls180.v:0.0-0.0"
79197   wire width 4 $memwr$\storage_4$ls180.v:10138$9_ADDR
79198   attribute \src "ls180.v:0.0-0.0"
79199   wire width 10 $memwr$\storage_4$ls180.v:10138$9_DATA
79200   attribute \src "ls180.v:0.0-0.0"
79201   wire width 10 $memwr$\storage_4$ls180.v:10138$9_EN
79202   attribute \src "ls180.v:0.0-0.0"
79203   wire width 4 $memwr$\storage_5$ls180.v:10155$10_ADDR
79204   attribute \src "ls180.v:0.0-0.0"
79205   wire width 10 $memwr$\storage_5$ls180.v:10155$10_DATA
79206   attribute \src "ls180.v:0.0-0.0"
79207   wire width 10 $memwr$\storage_5$ls180.v:10155$10_EN
79208   attribute \src "ls180.v:0.0-0.0"
79209   wire width 5 $memwr$\storage_6$ls180.v:10171$11_ADDR
79210   attribute \src "ls180.v:0.0-0.0"
79211   wire width 10 $memwr$\storage_6$ls180.v:10171$11_DATA
79212   attribute \src "ls180.v:0.0-0.0"
79213   wire width 10 $memwr$\storage_6$ls180.v:10171$11_EN
79214   attribute \src "ls180.v:0.0-0.0"
79215   wire width 5 $memwr$\storage_7$ls180.v:10185$12_ADDR
79216   attribute \src "ls180.v:0.0-0.0"
79217   wire width 10 $memwr$\storage_7$ls180.v:10185$12_DATA
79218   attribute \src "ls180.v:0.0-0.0"
79219   wire width 10 $memwr$\storage_7$ls180.v:10185$12_EN
79220   attribute \src "ls180.v:2969.41-2969.71"
79221   wire $ne$ls180.v:2969$60_Y
79222   attribute \src "ls180.v:3130.70-3130.104"
79223   wire $ne$ls180.v:3130$74_Y
79224   attribute \src "ls180.v:3191.8-3191.142"
79225   wire $ne$ls180.v:3191$93_Y
79226   attribute \src "ls180.v:3223.75-3223.133"
79227   wire $ne$ls180.v:3223$100_Y
79228   attribute \src "ls180.v:3224.75-3224.133"
79229   wire $ne$ls180.v:3224$101_Y
79230   attribute \src "ls180.v:3348.8-3348.142"
79231   wire $ne$ls180.v:3348$123_Y
79232   attribute \src "ls180.v:3380.75-3380.133"
79233   wire $ne$ls180.v:3380$130_Y
79234   attribute \src "ls180.v:3381.75-3381.133"
79235   wire $ne$ls180.v:3381$131_Y
79236   attribute \src "ls180.v:3505.8-3505.142"
79237   wire $ne$ls180.v:3505$153_Y
79238   attribute \src "ls180.v:3537.75-3537.133"
79239   wire $ne$ls180.v:3537$160_Y
79240   attribute \src "ls180.v:3538.75-3538.133"
79241   wire $ne$ls180.v:3538$161_Y
79242   attribute \src "ls180.v:3662.8-3662.142"
79243   wire $ne$ls180.v:3662$183_Y
79244   attribute \src "ls180.v:3694.75-3694.133"
79245   wire $ne$ls180.v:3694$190_Y
79246   attribute \src "ls180.v:3695.75-3695.133"
79247   wire $ne$ls180.v:3695$191_Y
79248   attribute \src "ls180.v:4187.47-4187.80"
79249   wire $ne$ls180.v:4187$589_Y
79250   attribute \src "ls180.v:4188.47-4188.79"
79251   wire $ne$ls180.v:4188$590_Y
79252   attribute \src "ls180.v:4217.47-4217.80"
79253   wire $ne$ls180.v:4217$600_Y
79254   attribute \src "ls180.v:4218.47-4218.79"
79255   wire $ne$ls180.v:4218$601_Y
79256   attribute \src "ls180.v:4687.32-4687.89"
79257   wire $ne$ls180.v:4687$681_Y
79258   attribute \src "ls180.v:5334.10-5334.56"
79259   wire $ne$ls180.v:5334$978_Y
79260   attribute \src "ls180.v:5439.51-5439.87"
79261   wire $ne$ls180.v:5439$992_Y
79262   attribute \src "ls180.v:5440.51-5440.86"
79263   wire $ne$ls180.v:5440$993_Y
79264   attribute \src "ls180.v:5647.51-5647.87"
79265   wire $ne$ls180.v:5647$1023_Y
79266   attribute \src "ls180.v:5648.51-5648.86"
79267   wire $ne$ls180.v:5648$1024_Y
79268   attribute \src "ls180.v:5679.79-5679.119"
79269   wire $ne$ls180.v:5679$1027_Y
79270   attribute \src "ls180.v:7501.7-7501.52"
79271   wire $ne$ls180.v:7501$2414_Y
79272   attribute \src "ls180.v:7551.9-7551.43"
79273   wire $ne$ls180.v:7551$2428_Y
79274   attribute \src "ls180.v:7587.8-7587.44"
79275   wire $ne$ls180.v:7587$2435_Y
79276   attribute \src "ls180.v:8525.9-8525.47"
79277   wire $ne$ls180.v:8525$2650_Y
79278   attribute \src "ls180.v:2777.45-2777.80"
79279   wire $not$ls180.v:2777$14_Y
79280   attribute \src "ls180.v:2816.61-2816.94"
79281   wire $not$ls180.v:2816$19_Y
79282   attribute \src "ls180.v:2817.61-2817.94"
79283   wire $not$ls180.v:2817$20_Y
79284   attribute \src "ls180.v:2837.45-2837.80"
79285   wire $not$ls180.v:2837$25_Y
79286   attribute \src "ls180.v:2876.61-2876.94"
79287   wire $not$ls180.v:2876$30_Y
79288   attribute \src "ls180.v:2877.61-2877.94"
79289   wire $not$ls180.v:2877$31_Y
79290   attribute \src "ls180.v:2897.45-2897.83"
79291   wire $not$ls180.v:2897$36_Y
79292   attribute \src "ls180.v:2936.61-2936.94"
79293   wire $not$ls180.v:2936$41_Y
79294   attribute \src "ls180.v:2937.61-2937.94"
79295   wire $not$ls180.v:2937$42_Y
79296   attribute \src "ls180.v:3079.34-3079.64"
79297   wire $not$ls180.v:3079$66_Y
79298   attribute \src "ls180.v:3080.31-3080.61"
79299   wire $not$ls180.v:3080$67_Y
79300   attribute \src "ls180.v:3081.32-3081.62"
79301   wire $not$ls180.v:3081$68_Y
79302   attribute \src "ls180.v:3082.32-3082.62"
79303   wire $not$ls180.v:3082$69_Y
79304   attribute \src "ls180.v:3124.33-3124.56"
79305   wire $not$ls180.v:3124$72_Y
79306   attribute \src "ls180.v:3225.58-3225.106"
79307   wire $not$ls180.v:3225$102_Y
79308   attribute \src "ls180.v:3279.9-3279.45"
79309   wire $not$ls180.v:3279$107_Y
79310   attribute \src "ls180.v:3382.58-3382.106"
79311   wire $not$ls180.v:3382$132_Y
79312   attribute \src "ls180.v:3436.9-3436.45"
79313   wire $not$ls180.v:3436$137_Y
79314   attribute \src "ls180.v:3539.58-3539.106"
79315   wire $not$ls180.v:3539$162_Y
79316   attribute \src "ls180.v:3593.9-3593.45"
79317   wire $not$ls180.v:3593$167_Y
79318   attribute \src "ls180.v:3696.58-3696.106"
79319   wire $not$ls180.v:3696$192_Y
79320   attribute \src "ls180.v:3750.9-3750.45"
79321   wire $not$ls180.v:3750$197_Y
79322   attribute \src "ls180.v:3792.149-3792.187"
79323   wire $not$ls180.v:3792$200_Y
79324   attribute \src "ls180.v:3792.193-3792.230"
79325   wire $not$ls180.v:3792$202_Y
79326   attribute \src "ls180.v:3793.149-3793.187"
79327   wire $not$ls180.v:3793$206_Y
79328   attribute \src "ls180.v:3793.193-3793.230"
79329   wire $not$ls180.v:3793$208_Y
79330   attribute \src "ls180.v:3809.43-3809.73"
79331   wire width 2 $not$ls180.v:3809$236_Y
79332   attribute \src "ls180.v:3812.205-3812.245"
79333   wire $not$ls180.v:3812$239_Y
79334   attribute \src "ls180.v:3812.251-3812.290"
79335   wire $not$ls180.v:3812$241_Y
79336   attribute \src "ls180.v:3812.159-3812.292"
79337   wire $not$ls180.v:3812$243_Y
79338   attribute \src "ls180.v:3813.205-3813.245"
79339   wire $not$ls180.v:3813$252_Y
79340   attribute \src "ls180.v:3813.251-3813.290"
79341   wire $not$ls180.v:3813$254_Y
79342   attribute \src "ls180.v:3813.159-3813.292"
79343   wire $not$ls180.v:3813$256_Y
79344   attribute \src "ls180.v:3814.205-3814.245"
79345   wire $not$ls180.v:3814$265_Y
79346   attribute \src "ls180.v:3814.251-3814.290"
79347   wire $not$ls180.v:3814$267_Y
79348   attribute \src "ls180.v:3814.159-3814.292"
79349   wire $not$ls180.v:3814$269_Y
79350   attribute \src "ls180.v:3815.205-3815.245"
79351   wire $not$ls180.v:3815$278_Y
79352   attribute \src "ls180.v:3815.251-3815.290"
79353   wire $not$ls180.v:3815$280_Y
79354   attribute \src "ls180.v:3815.159-3815.292"
79355   wire $not$ls180.v:3815$282_Y
79356   attribute \src "ls180.v:3842.71-3842.103"
79357   wire $not$ls180.v:3842$293_Y
79358   attribute \src "ls180.v:3845.205-3845.245"
79359   wire $not$ls180.v:3845$297_Y
79360   attribute \src "ls180.v:3845.251-3845.290"
79361   wire $not$ls180.v:3845$299_Y
79362   attribute \src "ls180.v:3845.159-3845.292"
79363   wire $not$ls180.v:3845$301_Y
79364   attribute \src "ls180.v:3846.205-3846.245"
79365   wire $not$ls180.v:3846$310_Y
79366   attribute \src "ls180.v:3846.251-3846.290"
79367   wire $not$ls180.v:3846$312_Y
79368   attribute \src "ls180.v:3846.159-3846.292"
79369   wire $not$ls180.v:3846$314_Y
79370   attribute \src "ls180.v:3847.205-3847.245"
79371   wire $not$ls180.v:3847$323_Y
79372   attribute \src "ls180.v:3847.251-3847.290"
79373   wire $not$ls180.v:3847$325_Y
79374   attribute \src "ls180.v:3847.159-3847.292"
79375   wire $not$ls180.v:3847$327_Y
79376   attribute \src "ls180.v:3848.205-3848.245"
79377   wire $not$ls180.v:3848$336_Y
79378   attribute \src "ls180.v:3848.251-3848.290"
79379   wire $not$ls180.v:3848$338_Y
79380   attribute \src "ls180.v:3848.159-3848.292"
79381   wire $not$ls180.v:3848$340_Y
79382   attribute \src "ls180.v:3911.71-3911.103"
79383   wire $not$ls180.v:3911$379_Y
79384   attribute \src "ls180.v:3932.112-3932.150"
79385   wire $not$ls180.v:3932$382_Y
79386   attribute \src "ls180.v:3932.156-3932.193"
79387   wire $not$ls180.v:3932$384_Y
79388   attribute \src "ls180.v:3932.68-3932.195"
79389   wire $not$ls180.v:3932$386_Y
79390   attribute \src "ls180.v:3940.11-3940.38"
79391   wire $not$ls180.v:3940$389_Y
79392   attribute \src "ls180.v:3970.112-3970.150"
79393   wire $not$ls180.v:3970$391_Y
79394   attribute \src "ls180.v:3970.156-3970.193"
79395   wire $not$ls180.v:3970$393_Y
79396   attribute \src "ls180.v:3970.68-3970.195"
79397   wire $not$ls180.v:3970$395_Y
79398   attribute \src "ls180.v:3978.11-3978.37"
79399   wire $not$ls180.v:3978$398_Y
79400   attribute \src "ls180.v:3988.87-3988.331"
79401   wire $not$ls180.v:3988$410_Y
79402   attribute \src "ls180.v:3989.35-3989.68"
79403   wire $not$ls180.v:3989$413_Y
79404   attribute \src "ls180.v:3989.73-3989.105"
79405   wire $not$ls180.v:3989$414_Y
79406   attribute \src "ls180.v:3993.87-3993.331"
79407   wire $not$ls180.v:3993$426_Y
79408   attribute \src "ls180.v:3994.35-3994.68"
79409   wire $not$ls180.v:3994$429_Y
79410   attribute \src "ls180.v:3994.73-3994.105"
79411   wire $not$ls180.v:3994$430_Y
79412   attribute \src "ls180.v:3998.87-3998.331"
79413   wire $not$ls180.v:3998$442_Y
79414   attribute \src "ls180.v:3999.35-3999.68"
79415   wire $not$ls180.v:3999$445_Y
79416   attribute \src "ls180.v:3999.73-3999.105"
79417   wire $not$ls180.v:3999$446_Y
79418   attribute \src "ls180.v:4003.87-4003.331"
79419   wire $not$ls180.v:4003$458_Y
79420   attribute \src "ls180.v:4004.35-4004.68"
79421   wire $not$ls180.v:4004$461_Y
79422   attribute \src "ls180.v:4004.73-4004.105"
79423   wire $not$ls180.v:4004$462_Y
79424   attribute \src "ls180.v:4008.128-4008.372"
79425   wire $not$ls180.v:4008$475_Y
79426   attribute \src "ls180.v:4008.502-4008.746"
79427   wire $not$ls180.v:4008$491_Y
79428   attribute \src "ls180.v:4008.876-4008.1120"
79429   wire $not$ls180.v:4008$507_Y
79430   attribute \src "ls180.v:4008.1250-4008.1494"
79431   wire $not$ls180.v:4008$523_Y
79432   attribute \src "ls180.v:4030.32-4030.50"
79433   wire $not$ls180.v:4030$529_Y
79434   attribute \src "ls180.v:4069.30-4069.50"
79435   wire $not$ls180.v:4069$534_Y
79436   attribute \src "ls180.v:4070.30-4070.50"
79437   wire $not$ls180.v:4070$535_Y
79438   attribute \src "ls180.v:4095.27-4095.48"
79439   wire $not$ls180.v:4095$541_Y
79440   attribute \src "ls180.v:4096.30-4096.50"
79441   wire $not$ls180.v:4096$542_Y
79442   attribute \src "ls180.v:4097.80-4097.98"
79443   wire $not$ls180.v:4097$544_Y
79444   attribute \src "ls180.v:4098.107-4098.127"
79445   wire $not$ls180.v:4098$548_Y
79446   attribute \src "ls180.v:4099.78-4099.103"
79447   wire $not$ls180.v:4099$551_Y
79448   attribute \src "ls180.v:4100.91-4100.111"
79449   wire $not$ls180.v:4100$554_Y
79450   attribute \src "ls180.v:4116.35-4116.64"
79451   wire $not$ls180.v:4116$563_Y
79452   attribute \src "ls180.v:4117.36-4117.67"
79453   wire $not$ls180.v:4117$564_Y
79454   attribute \src "ls180.v:4123.32-4123.61"
79455   wire $not$ls180.v:4123$565_Y
79456   attribute \src "ls180.v:4129.36-4129.67"
79457   wire $not$ls180.v:4129$566_Y
79458   attribute \src "ls180.v:4130.35-4130.64"
79459   wire $not$ls180.v:4130$567_Y
79460   attribute \src "ls180.v:4133.32-4133.63"
79461   wire $not$ls180.v:4133$570_Y
79462   attribute \src "ls180.v:4171.81-4171.108"
79463   wire $not$ls180.v:4171$580_Y
79464   attribute \src "ls180.v:4201.81-4201.108"
79465   wire $not$ls180.v:4201$591_Y
79466   attribute \src "ls180.v:4401.60-4401.85"
79467   wire $not$ls180.v:4401$640_Y
79468   attribute \src "ls180.v:4542.54-4542.96"
79469   wire $not$ls180.v:4542$654_Y
79470   attribute \src "ls180.v:4545.48-4545.86"
79471   wire $not$ls180.v:4545$657_Y
79472   attribute \src "ls180.v:4669.55-4669.98"
79473   wire $not$ls180.v:4669$675_Y
79474   attribute \src "ls180.v:4672.49-4672.88"
79475   wire $not$ls180.v:4672$678_Y
79476   attribute \src "ls180.v:4722.30-4722.58"
79477   wire $not$ls180.v:4722$684_Y
79478   attribute \src "ls180.v:4803.56-4803.100"
79479   wire $not$ls180.v:4803$690_Y
79480   attribute \src "ls180.v:4806.50-4806.90"
79481   wire $not$ls180.v:4806$693_Y
79482   attribute \src "ls180.v:4922.42-4922.74"
79483   wire $not$ls180.v:4922$709_Y
79484   attribute \src "ls180.v:5446.50-5446.88"
79485   wire $not$ls180.v:5446$994_Y
79486   attribute \src "ls180.v:5458.52-5458.102"
79487   wire $not$ls180.v:5458$997_Y
79488   attribute \src "ls180.v:5517.38-5517.74"
79489   wire $not$ls180.v:5517$1004_Y
79490   attribute \src "ls180.v:5759.69-5759.88"
79491   wire $not$ls180.v:5759$1065_Y
79492   attribute \src "ls180.v:5776.63-5776.94"
79493   wire $not$ls180.v:5776$1086_Y
79494   attribute \src "ls180.v:5779.65-5779.96"
79495   wire $not$ls180.v:5779$1093_Y
79496   attribute \src "ls180.v:5782.65-5782.96"
79497   wire $not$ls180.v:5782$1100_Y
79498   attribute \src "ls180.v:5785.65-5785.96"
79499   wire $not$ls180.v:5785$1107_Y
79500   attribute \src "ls180.v:5788.65-5788.96"
79501   wire $not$ls180.v:5788$1114_Y
79502   attribute \src "ls180.v:5791.68-5791.99"
79503   wire $not$ls180.v:5791$1121_Y
79504   attribute \src "ls180.v:5794.68-5794.99"
79505   wire $not$ls180.v:5794$1128_Y
79506   attribute \src "ls180.v:5797.68-5797.99"
79507   wire $not$ls180.v:5797$1135_Y
79508   attribute \src "ls180.v:5800.68-5800.99"
79509   wire $not$ls180.v:5800$1142_Y
79510   attribute \src "ls180.v:5814.60-5814.91"
79511   wire $not$ls180.v:5814$1150_Y
79512   attribute \src "ls180.v:5817.60-5817.91"
79513   wire $not$ls180.v:5817$1157_Y
79514   attribute \src "ls180.v:5820.60-5820.91"
79515   wire $not$ls180.v:5820$1164_Y
79516   attribute \src "ls180.v:5823.60-5823.91"
79517   wire $not$ls180.v:5823$1171_Y
79518   attribute \src "ls180.v:5826.61-5826.92"
79519   wire $not$ls180.v:5826$1178_Y
79520   attribute \src "ls180.v:5829.61-5829.92"
79521   wire $not$ls180.v:5829$1185_Y
79522   attribute \src "ls180.v:5840.59-5840.90"
79523   wire $not$ls180.v:5840$1193_Y
79524   attribute \src "ls180.v:5843.58-5843.89"
79525   wire $not$ls180.v:5843$1200_Y
79526   attribute \src "ls180.v:5854.64-5854.95"
79527   wire $not$ls180.v:5854$1208_Y
79528   attribute \src "ls180.v:5857.63-5857.94"
79529   wire $not$ls180.v:5857$1215_Y
79530   attribute \src "ls180.v:5860.63-5860.94"
79531   wire $not$ls180.v:5860$1222_Y
79532   attribute \src "ls180.v:5863.63-5863.94"
79533   wire $not$ls180.v:5863$1229_Y
79534   attribute \src "ls180.v:5866.63-5866.94"
79535   wire $not$ls180.v:5866$1236_Y
79536   attribute \src "ls180.v:5869.64-5869.95"
79537   wire $not$ls180.v:5869$1243_Y
79538   attribute \src "ls180.v:5872.64-5872.95"
79539   wire $not$ls180.v:5872$1250_Y
79540   attribute \src "ls180.v:5875.64-5875.95"
79541   wire $not$ls180.v:5875$1257_Y
79542   attribute \src "ls180.v:5878.64-5878.95"
79543   wire $not$ls180.v:5878$1264_Y
79544   attribute \src "ls180.v:5891.64-5891.95"
79545   wire $not$ls180.v:5891$1272_Y
79546   attribute \src "ls180.v:5894.63-5894.94"
79547   wire $not$ls180.v:5894$1279_Y
79548   attribute \src "ls180.v:5897.63-5897.94"
79549   wire $not$ls180.v:5897$1286_Y
79550   attribute \src "ls180.v:5900.63-5900.94"
79551   wire $not$ls180.v:5900$1293_Y
79552   attribute \src "ls180.v:5903.63-5903.94"
79553   wire $not$ls180.v:5903$1300_Y
79554   attribute \src "ls180.v:5906.64-5906.95"
79555   wire $not$ls180.v:5906$1307_Y
79556   attribute \src "ls180.v:5909.64-5909.95"
79557   wire $not$ls180.v:5909$1314_Y
79558   attribute \src "ls180.v:5912.64-5912.95"
79559   wire $not$ls180.v:5912$1321_Y
79560   attribute \src "ls180.v:5915.64-5915.95"
79561   wire $not$ls180.v:5915$1328_Y
79562   attribute \src "ls180.v:5928.66-5928.97"
79563   wire $not$ls180.v:5928$1336_Y
79564   attribute \src "ls180.v:5931.66-5931.97"
79565   wire $not$ls180.v:5931$1343_Y
79566   attribute \src "ls180.v:5934.66-5934.97"
79567   wire $not$ls180.v:5934$1350_Y
79568   attribute \src "ls180.v:5937.66-5937.97"
79569   wire $not$ls180.v:5937$1357_Y
79570   attribute \src "ls180.v:5940.66-5940.97"
79571   wire $not$ls180.v:5940$1364_Y
79572   attribute \src "ls180.v:5943.66-5943.97"
79573   wire $not$ls180.v:5943$1371_Y
79574   attribute \src "ls180.v:5946.66-5946.97"
79575   wire $not$ls180.v:5946$1378_Y
79576   attribute \src "ls180.v:5949.66-5949.97"
79577   wire $not$ls180.v:5949$1385_Y
79578   attribute \src "ls180.v:5952.68-5952.99"
79579   wire $not$ls180.v:5952$1392_Y
79580   attribute \src "ls180.v:5955.68-5955.99"
79581   wire $not$ls180.v:5955$1399_Y
79582   attribute \src "ls180.v:5958.68-5958.99"
79583   wire $not$ls180.v:5958$1406_Y
79584   attribute \src "ls180.v:5961.68-5961.99"
79585   wire $not$ls180.v:5961$1413_Y
79586   attribute \src "ls180.v:5964.68-5964.99"
79587   wire $not$ls180.v:5964$1420_Y
79588   attribute \src "ls180.v:5967.65-5967.96"
79589   wire $not$ls180.v:5967$1427_Y
79590   attribute \src "ls180.v:5970.66-5970.97"
79591   wire $not$ls180.v:5970$1434_Y
79592   attribute \src "ls180.v:5990.70-5990.101"
79593   wire $not$ls180.v:5990$1442_Y
79594   attribute \src "ls180.v:5993.70-5993.101"
79595   wire $not$ls180.v:5993$1449_Y
79596   attribute \src "ls180.v:5996.70-5996.101"
79597   wire $not$ls180.v:5996$1456_Y
79598   attribute \src "ls180.v:5999.70-5999.101"
79599   wire $not$ls180.v:5999$1463_Y
79600   attribute \src "ls180.v:6002.69-6002.100"
79601   wire $not$ls180.v:6002$1470_Y
79602   attribute \src "ls180.v:6005.69-6005.100"
79603   wire $not$ls180.v:6005$1477_Y
79604   attribute \src "ls180.v:6008.69-6008.100"
79605   wire $not$ls180.v:6008$1484_Y
79606   attribute \src "ls180.v:6011.69-6011.100"
79607   wire $not$ls180.v:6011$1491_Y
79608   attribute \src "ls180.v:6014.60-6014.91"
79609   wire $not$ls180.v:6014$1498_Y
79610   attribute \src "ls180.v:6017.71-6017.102"
79611   wire $not$ls180.v:6017$1505_Y
79612   attribute \src "ls180.v:6020.71-6020.102"
79613   wire $not$ls180.v:6020$1512_Y
79614   attribute \src "ls180.v:6023.71-6023.102"
79615   wire $not$ls180.v:6023$1519_Y
79616   attribute \src "ls180.v:6026.71-6026.102"
79617   wire $not$ls180.v:6026$1526_Y
79618   attribute \src "ls180.v:6029.71-6029.102"
79619   wire $not$ls180.v:6029$1533_Y
79620   attribute \src "ls180.v:6032.71-6032.102"
79621   wire $not$ls180.v:6032$1540_Y
79622   attribute \src "ls180.v:6035.70-6035.101"
79623   wire $not$ls180.v:6035$1547_Y
79624   attribute \src "ls180.v:6038.70-6038.101"
79625   wire $not$ls180.v:6038$1554_Y
79626   attribute \src "ls180.v:6041.70-6041.101"
79627   wire $not$ls180.v:6041$1561_Y
79628   attribute \src "ls180.v:6044.70-6044.101"
79629   wire $not$ls180.v:6044$1568_Y
79630   attribute \src "ls180.v:6047.70-6047.101"
79631   wire $not$ls180.v:6047$1575_Y
79632   attribute \src "ls180.v:6050.70-6050.101"
79633   wire $not$ls180.v:6050$1582_Y
79634   attribute \src "ls180.v:6053.70-6053.101"
79635   wire $not$ls180.v:6053$1589_Y
79636   attribute \src "ls180.v:6056.70-6056.101"
79637   wire $not$ls180.v:6056$1596_Y
79638   attribute \src "ls180.v:6059.70-6059.101"
79639   wire $not$ls180.v:6059$1603_Y
79640   attribute \src "ls180.v:6062.70-6062.101"
79641   wire $not$ls180.v:6062$1610_Y
79642   attribute \src "ls180.v:6065.66-6065.97"
79643   wire $not$ls180.v:6065$1617_Y
79644   attribute \src "ls180.v:6068.67-6068.98"
79645   wire $not$ls180.v:6068$1624_Y
79646   attribute \src "ls180.v:6071.70-6071.101"
79647   wire $not$ls180.v:6071$1631_Y
79648   attribute \src "ls180.v:6074.70-6074.101"
79649   wire $not$ls180.v:6074$1638_Y
79650   attribute \src "ls180.v:6077.69-6077.100"
79651   wire $not$ls180.v:6077$1645_Y
79652   attribute \src "ls180.v:6080.69-6080.100"
79653   wire $not$ls180.v:6080$1652_Y
79654   attribute \src "ls180.v:6083.69-6083.100"
79655   wire $not$ls180.v:6083$1659_Y
79656   attribute \src "ls180.v:6086.69-6086.100"
79657   wire $not$ls180.v:6086$1666_Y
79658   attribute \src "ls180.v:6125.66-6125.97"
79659   wire $not$ls180.v:6125$1674_Y
79660   attribute \src "ls180.v:6128.66-6128.97"
79661   wire $not$ls180.v:6128$1681_Y
79662   attribute \src "ls180.v:6131.66-6131.97"
79663   wire $not$ls180.v:6131$1688_Y
79664   attribute \src "ls180.v:6134.66-6134.97"
79665   wire $not$ls180.v:6134$1695_Y
79666   attribute \src "ls180.v:6137.66-6137.97"
79667   wire $not$ls180.v:6137$1702_Y
79668   attribute \src "ls180.v:6140.66-6140.97"
79669   wire $not$ls180.v:6140$1709_Y
79670   attribute \src "ls180.v:6143.66-6143.97"
79671   wire $not$ls180.v:6143$1716_Y
79672   attribute \src "ls180.v:6146.66-6146.97"
79673   wire $not$ls180.v:6146$1723_Y
79674   attribute \src "ls180.v:6149.68-6149.99"
79675   wire $not$ls180.v:6149$1730_Y
79676   attribute \src "ls180.v:6152.68-6152.99"
79677   wire $not$ls180.v:6152$1737_Y
79678   attribute \src "ls180.v:6155.68-6155.99"
79679   wire $not$ls180.v:6155$1744_Y
79680   attribute \src "ls180.v:6158.68-6158.99"
79681   wire $not$ls180.v:6158$1751_Y
79682   attribute \src "ls180.v:6161.68-6161.99"
79683   wire $not$ls180.v:6161$1758_Y
79684   attribute \src "ls180.v:6164.65-6164.96"
79685   wire $not$ls180.v:6164$1765_Y
79686   attribute \src "ls180.v:6167.66-6167.97"
79687   wire $not$ls180.v:6167$1772_Y
79688   attribute \src "ls180.v:6170.68-6170.99"
79689   wire $not$ls180.v:6170$1779_Y
79690   attribute \src "ls180.v:6173.68-6173.99"
79691   wire $not$ls180.v:6173$1786_Y
79692   attribute \src "ls180.v:6176.68-6176.99"
79693   wire $not$ls180.v:6176$1793_Y
79694   attribute \src "ls180.v:6179.68-6179.99"
79695   wire $not$ls180.v:6179$1800_Y
79696   attribute \src "ls180.v:6204.68-6204.99"
79697   wire $not$ls180.v:6204$1808_Y
79698   attribute \src "ls180.v:6207.73-6207.104"
79699   wire $not$ls180.v:6207$1815_Y
79700   attribute \src "ls180.v:6210.73-6210.104"
79701   wire $not$ls180.v:6210$1822_Y
79702   attribute \src "ls180.v:6213.66-6213.97"
79703   wire $not$ls180.v:6213$1829_Y
79704   attribute \src "ls180.v:6221.70-6221.101"
79705   wire $not$ls180.v:6221$1837_Y
79706   attribute \src "ls180.v:6224.74-6224.105"
79707   wire $not$ls180.v:6224$1844_Y
79708   attribute \src "ls180.v:6227.64-6227.95"
79709   wire $not$ls180.v:6227$1851_Y
79710   attribute \src "ls180.v:6230.74-6230.105"
79711   wire $not$ls180.v:6230$1858_Y
79712   attribute \src "ls180.v:6233.74-6233.105"
79713   wire $not$ls180.v:6233$1865_Y
79714   attribute \src "ls180.v:6236.75-6236.106"
79715   wire $not$ls180.v:6236$1872_Y
79716   attribute \src "ls180.v:6239.73-6239.104"
79717   wire $not$ls180.v:6239$1879_Y
79718   attribute \src "ls180.v:6242.73-6242.104"
79719   wire $not$ls180.v:6242$1886_Y
79720   attribute \src "ls180.v:6245.73-6245.104"
79721   wire $not$ls180.v:6245$1893_Y
79722   attribute \src "ls180.v:6248.73-6248.104"
79723   wire $not$ls180.v:6248$1900_Y
79724   attribute \src "ls180.v:6266.67-6266.99"
79725   wire $not$ls180.v:6266$1908_Y
79726   attribute \src "ls180.v:6269.67-6269.99"
79727   wire $not$ls180.v:6269$1915_Y
79728   attribute \src "ls180.v:6272.65-6272.97"
79729   wire $not$ls180.v:6272$1922_Y
79730   attribute \src "ls180.v:6275.64-6275.96"
79731   wire $not$ls180.v:6275$1929_Y
79732   attribute \src "ls180.v:6278.63-6278.95"
79733   wire $not$ls180.v:6278$1936_Y
79734   attribute \src "ls180.v:6281.62-6281.94"
79735   wire $not$ls180.v:6281$1943_Y
79736   attribute \src "ls180.v:6284.68-6284.100"
79737   wire $not$ls180.v:6284$1950_Y
79738   attribute \src "ls180.v:6306.67-6306.99"
79739   wire $not$ls180.v:6306$1959_Y
79740   attribute \src "ls180.v:6309.67-6309.99"
79741   wire $not$ls180.v:6309$1966_Y
79742   attribute \src "ls180.v:6312.65-6312.97"
79743   wire $not$ls180.v:6312$1973_Y
79744   attribute \src "ls180.v:6315.64-6315.96"
79745   wire $not$ls180.v:6315$1980_Y
79746   attribute \src "ls180.v:6318.63-6318.95"
79747   wire $not$ls180.v:6318$1987_Y
79748   attribute \src "ls180.v:6321.62-6321.94"
79749   wire $not$ls180.v:6321$1994_Y
79750   attribute \src "ls180.v:6324.68-6324.100"
79751   wire $not$ls180.v:6324$2001_Y
79752   attribute \src "ls180.v:6327.71-6327.103"
79753   wire $not$ls180.v:6327$2008_Y
79754   attribute \src "ls180.v:6330.71-6330.103"
79755   wire $not$ls180.v:6330$2015_Y
79756   attribute \src "ls180.v:6354.64-6354.96"
79757   wire $not$ls180.v:6354$2024_Y
79758   attribute \src "ls180.v:6357.64-6357.96"
79759   wire $not$ls180.v:6357$2031_Y
79760   attribute \src "ls180.v:6360.64-6360.96"
79761   wire $not$ls180.v:6360$2038_Y
79762   attribute \src "ls180.v:6363.64-6363.96"
79763   wire $not$ls180.v:6363$2045_Y
79764   attribute \src "ls180.v:6366.66-6366.98"
79765   wire $not$ls180.v:6366$2052_Y
79766   attribute \src "ls180.v:6369.66-6369.98"
79767   wire $not$ls180.v:6369$2059_Y
79768   attribute \src "ls180.v:6372.66-6372.98"
79769   wire $not$ls180.v:6372$2066_Y
79770   attribute \src "ls180.v:6375.66-6375.98"
79771   wire $not$ls180.v:6375$2073_Y
79772   attribute \src "ls180.v:6378.62-6378.94"
79773   wire $not$ls180.v:6378$2080_Y
79774   attribute \src "ls180.v:6381.72-6381.104"
79775   wire $not$ls180.v:6381$2087_Y
79776   attribute \src "ls180.v:6384.65-6384.97"
79777   wire $not$ls180.v:6384$2094_Y
79778   attribute \src "ls180.v:6387.65-6387.97"
79779   wire $not$ls180.v:6387$2101_Y
79780   attribute \src "ls180.v:6390.65-6390.97"
79781   wire $not$ls180.v:6390$2108_Y
79782   attribute \src "ls180.v:6393.65-6393.97"
79783   wire $not$ls180.v:6393$2115_Y
79784   attribute \src "ls180.v:6396.77-6396.109"
79785   wire $not$ls180.v:6396$2122_Y
79786   attribute \src "ls180.v:6399.78-6399.110"
79787   wire $not$ls180.v:6399$2129_Y
79788   attribute \src "ls180.v:6402.69-6402.101"
79789   wire $not$ls180.v:6402$2136_Y
79790   attribute \src "ls180.v:6422.55-6422.87"
79791   wire $not$ls180.v:6422$2144_Y
79792   attribute \src "ls180.v:6425.65-6425.97"
79793   wire $not$ls180.v:6425$2151_Y
79794   attribute \src "ls180.v:6428.66-6428.98"
79795   wire $not$ls180.v:6428$2158_Y
79796   attribute \src "ls180.v:6431.70-6431.102"
79797   wire $not$ls180.v:6431$2165_Y
79798   attribute \src "ls180.v:6434.71-6434.103"
79799   wire $not$ls180.v:6434$2172_Y
79800   attribute \src "ls180.v:6437.69-6437.101"
79801   wire $not$ls180.v:6437$2179_Y
79802   attribute \src "ls180.v:6440.66-6440.98"
79803   wire $not$ls180.v:6440$2186_Y
79804   attribute \src "ls180.v:6443.65-6443.97"
79805   wire $not$ls180.v:6443$2193_Y
79806   attribute \src "ls180.v:6456.71-6456.103"
79807   wire $not$ls180.v:6456$2201_Y
79808   attribute \src "ls180.v:6459.71-6459.103"
79809   wire $not$ls180.v:6459$2208_Y
79810   attribute \src "ls180.v:6462.71-6462.103"
79811   wire $not$ls180.v:6462$2215_Y
79812   attribute \src "ls180.v:6465.71-6465.103"
79813   wire $not$ls180.v:6465$2222_Y
79814   attribute \src "ls180.v:6846.86-6846.330"
79815   wire $not$ls180.v:6846$2271_Y
79816   attribute \src "ls180.v:6870.86-6870.330"
79817   wire $not$ls180.v:6870$2287_Y
79818   attribute \src "ls180.v:6894.86-6894.330"
79819   wire $not$ls180.v:6894$2303_Y
79820   attribute \src "ls180.v:6918.86-6918.330"
79821   wire $not$ls180.v:6918$2319_Y
79822   attribute \src "ls180.v:7416.18-7416.42"
79823   wire $not$ls180.v:7416$2372_Y
79824   attribute \src "ls180.v:7507.72-7507.101"
79825   wire $not$ls180.v:7507$2417_Y
79826   attribute \src "ls180.v:7526.8-7526.38"
79827   wire $not$ls180.v:7526$2421_Y
79828   attribute \src "ls180.v:7534.32-7534.55"
79829   wire $not$ls180.v:7534$2423_Y
79830   attribute \src "ls180.v:7604.136-7604.189"
79831   wire $not$ls180.v:7604$2438_Y
79832   attribute \src "ls180.v:7610.136-7610.189"
79833   wire $not$ls180.v:7610$2443_Y
79834   attribute \src "ls180.v:7611.8-7611.61"
79835   wire $not$ls180.v:7611$2445_Y
79836   attribute \src "ls180.v:7619.8-7619.56"
79837   wire $not$ls180.v:7619$2448_Y
79838   attribute \src "ls180.v:7634.8-7634.46"
79839   wire $not$ls180.v:7634$2450_Y
79840   attribute \src "ls180.v:7650.136-7650.189"
79841   wire $not$ls180.v:7650$2454_Y
79842   attribute \src "ls180.v:7656.136-7656.189"
79843   wire $not$ls180.v:7656$2459_Y
79844   attribute \src "ls180.v:7657.8-7657.61"
79845   wire $not$ls180.v:7657$2461_Y
79846   attribute \src "ls180.v:7665.8-7665.56"
79847   wire $not$ls180.v:7665$2464_Y
79848   attribute \src "ls180.v:7680.8-7680.46"
79849   wire $not$ls180.v:7680$2466_Y
79850   attribute \src "ls180.v:7696.136-7696.189"
79851   wire $not$ls180.v:7696$2470_Y
79852   attribute \src "ls180.v:7702.136-7702.189"
79853   wire $not$ls180.v:7702$2475_Y
79854   attribute \src "ls180.v:7703.8-7703.61"
79855   wire $not$ls180.v:7703$2477_Y
79856   attribute \src "ls180.v:7711.8-7711.56"
79857   wire $not$ls180.v:7711$2480_Y
79858   attribute \src "ls180.v:7726.8-7726.46"
79859   wire $not$ls180.v:7726$2482_Y
79860   attribute \src "ls180.v:7742.136-7742.189"
79861   wire $not$ls180.v:7742$2486_Y
79862   attribute \src "ls180.v:7748.136-7748.189"
79863   wire $not$ls180.v:7748$2491_Y
79864   attribute \src "ls180.v:7749.8-7749.61"
79865   wire $not$ls180.v:7749$2493_Y
79866   attribute \src "ls180.v:7757.8-7757.56"
79867   wire $not$ls180.v:7757$2496_Y
79868   attribute \src "ls180.v:7772.8-7772.46"
79869   wire $not$ls180.v:7772$2498_Y
79870   attribute \src "ls180.v:7780.7-7780.22"
79871   wire $not$ls180.v:7780$2501_Y
79872   attribute \src "ls180.v:7783.8-7783.29"
79873   wire $not$ls180.v:7783$2502_Y
79874   attribute \src "ls180.v:7787.7-7787.22"
79875   wire $not$ls180.v:7787$2504_Y
79876   attribute \src "ls180.v:7790.8-7790.29"
79877   wire $not$ls180.v:7790$2505_Y
79878   attribute \src "ls180.v:7909.30-7909.60"
79879   wire $not$ls180.v:7909$2507_Y
79880   attribute \src "ls180.v:7910.30-7910.60"
79881   wire $not$ls180.v:7910$2508_Y
79882   attribute \src "ls180.v:7911.29-7911.59"
79883   wire $not$ls180.v:7911$2509_Y
79884   attribute \src "ls180.v:7922.8-7922.33"
79885   wire $not$ls180.v:7922$2510_Y
79886   attribute \src "ls180.v:7937.8-7937.33"
79887   wire $not$ls180.v:7937$2513_Y
79888   attribute \src "ls180.v:7973.36-7973.58"
79889   wire $not$ls180.v:7973$2543_Y
79890   attribute \src "ls180.v:7973.64-7973.89"
79891   wire $not$ls180.v:7973$2545_Y
79892   attribute \src "ls180.v:8002.7-8002.29"
79893   wire $not$ls180.v:8002$2552_Y
79894   attribute \src "ls180.v:8003.9-8003.26"
79895   wire $not$ls180.v:8003$2553_Y
79896   attribute \src "ls180.v:8036.8-8036.29"
79897   wire $not$ls180.v:8036$2559_Y
79898   attribute \src "ls180.v:8043.8-8043.29"
79899   wire $not$ls180.v:8043$2561_Y
79900   attribute \src "ls180.v:8053.80-8053.106"
79901   wire $not$ls180.v:8053$2564_Y
79902   attribute \src "ls180.v:8059.80-8059.106"
79903   wire $not$ls180.v:8059$2569_Y
79904   attribute \src "ls180.v:8060.8-8060.34"
79905   wire $not$ls180.v:8060$2571_Y
79906   attribute \src "ls180.v:8075.80-8075.106"
79907   wire $not$ls180.v:8075$2575_Y
79908   attribute \src "ls180.v:8081.80-8081.106"
79909   wire $not$ls180.v:8081$2580_Y
79910   attribute \src "ls180.v:8082.8-8082.34"
79911   wire $not$ls180.v:8082$2582_Y
79912   attribute \src "ls180.v:8113.22-8113.41"
79913   wire $not$ls180.v:8113$2586_Y
79914   attribute \src "ls180.v:8113.46-8113.73"
79915   wire $not$ls180.v:8113$2587_Y
79916   attribute \src "ls180.v:8148.22-8148.40"
79917   wire $not$ls180.v:8148$2591_Y
79918   attribute \src "ls180.v:8148.45-8148.70"
79919   wire $not$ls180.v:8148$2592_Y
79920   attribute \src "ls180.v:8202.7-8202.31"
79921   wire $not$ls180.v:8202$2603_Y
79922   attribute \src "ls180.v:8274.8-8274.46"
79923   wire $not$ls180.v:8274$2615_Y
79924   attribute \src "ls180.v:8355.8-8355.47"
79925   wire $not$ls180.v:8355$2627_Y
79926   attribute \src "ls180.v:8416.8-8416.48"
79927   wire $not$ls180.v:8416$2639_Y
79928   attribute \src "ls180.v:8586.88-8586.118"
79929   wire $not$ls180.v:8586$2653_Y
79930   attribute \src "ls180.v:8592.88-8592.118"
79931   wire $not$ls180.v:8592$2658_Y
79932   attribute \src "ls180.v:8593.8-8593.38"
79933   wire $not$ls180.v:8593$2660_Y
79934   attribute \src "ls180.v:8672.88-8672.118"
79935   wire $not$ls180.v:8672$2675_Y
79936   attribute \src "ls180.v:8678.88-8678.118"
79937   wire $not$ls180.v:8678$2680_Y
79938   attribute \src "ls180.v:8679.8-8679.38"
79939   wire $not$ls180.v:8679$2682_Y
79940   attribute \src "ls180.v:8699.9-8699.28"
79941   wire $not$ls180.v:8699$2685_Y
79942   attribute \src "ls180.v:8718.9-8718.28"
79943   wire $not$ls180.v:8718$2686_Y
79944   attribute \src "ls180.v:8737.9-8737.28"
79945   wire $not$ls180.v:8737$2687_Y
79946   attribute \src "ls180.v:8756.9-8756.28"
79947   wire $not$ls180.v:8756$2688_Y
79948   attribute \src "ls180.v:8775.9-8775.28"
79949   wire $not$ls180.v:8775$2689_Y
79950   attribute \src "ls180.v:8796.8-8796.21"
79951   wire $not$ls180.v:8796$2690_Y
79952   attribute \src "ls180.v:10295.8-10295.51"
79953   wire $or$ls180.v:10295$2762_Y
79954   attribute \src "ls180.v:2818.10-2818.96"
79955   wire $or$ls180.v:2818$21_Y
79956   attribute \src "ls180.v:2878.10-2878.96"
79957   wire $or$ls180.v:2878$32_Y
79958   attribute \src "ls180.v:2938.10-2938.96"
79959   wire $or$ls180.v:2938$43_Y
79960   attribute \src "ls180.v:3130.39-3130.105"
79961   wire $or$ls180.v:3130$75_Y
79962   attribute \src "ls180.v:3173.59-3173.140"
79963   wire $or$ls180.v:3173$79_Y
79964   attribute \src "ls180.v:3174.44-3174.151"
79965   wire $or$ls180.v:3174$80_Y
79966   attribute \src "ls180.v:3182.45-3182.170"
79967   wire width 13 $or$ls180.v:3182$84_Y
79968   attribute \src "ls180.v:3219.127-3219.245"
79969   wire $or$ls180.v:3219$97_Y
79970   attribute \src "ls180.v:3225.57-3225.157"
79971   wire $or$ls180.v:3225$103_Y
79972   attribute \src "ls180.v:3330.59-3330.140"
79973   wire $or$ls180.v:3330$109_Y
79974   attribute \src "ls180.v:3331.44-3331.151"
79975   wire $or$ls180.v:3331$110_Y
79976   attribute \src "ls180.v:3339.45-3339.170"
79977   wire width 13 $or$ls180.v:3339$114_Y
79978   attribute \src "ls180.v:3376.127-3376.245"
79979   wire $or$ls180.v:3376$127_Y
79980   attribute \src "ls180.v:3382.57-3382.157"
79981   wire $or$ls180.v:3382$133_Y
79982   attribute \src "ls180.v:3487.59-3487.140"
79983   wire $or$ls180.v:3487$139_Y
79984   attribute \src "ls180.v:3488.44-3488.151"
79985   wire $or$ls180.v:3488$140_Y
79986   attribute \src "ls180.v:3496.45-3496.170"
79987   wire width 13 $or$ls180.v:3496$144_Y
79988   attribute \src "ls180.v:3533.127-3533.245"
79989   wire $or$ls180.v:3533$157_Y
79990   attribute \src "ls180.v:3539.57-3539.157"
79991   wire $or$ls180.v:3539$163_Y
79992   attribute \src "ls180.v:3644.59-3644.140"
79993   wire $or$ls180.v:3644$169_Y
79994   attribute \src "ls180.v:3645.44-3645.151"
79995   wire $or$ls180.v:3645$170_Y
79996   attribute \src "ls180.v:3653.45-3653.170"
79997   wire width 13 $or$ls180.v:3653$174_Y
79998   attribute \src "ls180.v:3690.127-3690.245"
79999   wire $or$ls180.v:3690$187_Y
80000   attribute \src "ls180.v:3696.57-3696.157"
80001   wire $or$ls180.v:3696$193_Y
80002   attribute \src "ls180.v:3795.107-3795.193"
80003   wire $or$ls180.v:3795$213_Y
80004   attribute \src "ls180.v:3798.39-3798.204"
80005   wire $or$ls180.v:3798$219_Y
80006   attribute \src "ls180.v:3798.38-3798.289"
80007   wire $or$ls180.v:3798$221_Y
80008   attribute \src "ls180.v:3798.37-3798.374"
80009   wire $or$ls180.v:3798$223_Y
80010   attribute \src "ls180.v:3799.40-3799.207"
80011   wire $or$ls180.v:3799$226_Y
80012   attribute \src "ls180.v:3799.39-3799.293"
80013   wire $or$ls180.v:3799$228_Y
80014   attribute \src "ls180.v:3799.38-3799.379"
80015   wire $or$ls180.v:3799$230_Y
80016   attribute \src "ls180.v:3812.158-3812.332"
80017   wire $or$ls180.v:3812$244_Y
80018   attribute \src "ls180.v:3812.75-3812.506"
80019   wire $or$ls180.v:3812$249_Y
80020   attribute \src "ls180.v:3813.158-3813.332"
80021   wire $or$ls180.v:3813$257_Y
80022   attribute \src "ls180.v:3813.75-3813.506"
80023   wire $or$ls180.v:3813$262_Y
80024   attribute \src "ls180.v:3814.158-3814.332"
80025   wire $or$ls180.v:3814$270_Y
80026   attribute \src "ls180.v:3814.75-3814.506"
80027   wire $or$ls180.v:3814$275_Y
80028   attribute \src "ls180.v:3815.158-3815.332"
80029   wire $or$ls180.v:3815$283_Y
80030   attribute \src "ls180.v:3815.75-3815.506"
80031   wire $or$ls180.v:3815$288_Y
80032   attribute \src "ls180.v:3842.36-3842.104"
80033   wire $or$ls180.v:3842$294_Y
80034   attribute \src "ls180.v:3845.158-3845.332"
80035   wire $or$ls180.v:3845$302_Y
80036   attribute \src "ls180.v:3845.75-3845.506"
80037   wire $or$ls180.v:3845$307_Y
80038   attribute \src "ls180.v:3846.158-3846.332"
80039   wire $or$ls180.v:3846$315_Y
80040   attribute \src "ls180.v:3846.75-3846.506"
80041   wire $or$ls180.v:3846$320_Y
80042   attribute \src "ls180.v:3847.158-3847.332"
80043   wire $or$ls180.v:3847$328_Y
80044   attribute \src "ls180.v:3847.75-3847.506"
80045   wire $or$ls180.v:3847$333_Y
80046   attribute \src "ls180.v:3848.158-3848.332"
80047   wire $or$ls180.v:3848$341_Y
80048   attribute \src "ls180.v:3848.75-3848.506"
80049   wire $or$ls180.v:3848$346_Y
80050   attribute \src "ls180.v:3911.36-3911.104"
80051   wire $or$ls180.v:3911$380_Y
80052   attribute \src "ls180.v:3932.67-3932.221"
80053   wire $or$ls180.v:3932$387_Y
80054   attribute \src "ls180.v:3940.10-3940.62"
80055   wire $or$ls180.v:3940$390_Y
80056   attribute \src "ls180.v:3970.67-3970.221"
80057   wire $or$ls180.v:3970$396_Y
80058   attribute \src "ls180.v:3978.10-3978.61"
80059   wire $or$ls180.v:3978$399_Y
80060   attribute \src "ls180.v:3988.91-3988.180"
80061   wire $or$ls180.v:3988$403_Y
80062   attribute \src "ls180.v:3988.90-3988.255"
80063   wire $or$ls180.v:3988$406_Y
80064   attribute \src "ls180.v:3988.89-3988.330"
80065   wire $or$ls180.v:3988$409_Y
80066   attribute \src "ls180.v:3993.91-3993.180"
80067   wire $or$ls180.v:3993$419_Y
80068   attribute \src "ls180.v:3993.90-3993.255"
80069   wire $or$ls180.v:3993$422_Y
80070   attribute \src "ls180.v:3993.89-3993.330"
80071   wire $or$ls180.v:3993$425_Y
80072   attribute \src "ls180.v:3998.91-3998.180"
80073   wire $or$ls180.v:3998$435_Y
80074   attribute \src "ls180.v:3998.90-3998.255"
80075   wire $or$ls180.v:3998$438_Y
80076   attribute \src "ls180.v:3998.89-3998.330"
80077   wire $or$ls180.v:3998$441_Y
80078   attribute \src "ls180.v:4003.91-4003.180"
80079   wire $or$ls180.v:4003$451_Y
80080   attribute \src "ls180.v:4003.90-4003.255"
80081   wire $or$ls180.v:4003$454_Y
80082   attribute \src "ls180.v:4003.89-4003.330"
80083   wire $or$ls180.v:4003$457_Y
80084   attribute \src "ls180.v:4008.132-4008.221"
80085   wire $or$ls180.v:4008$468_Y
80086   attribute \src "ls180.v:4008.131-4008.296"
80087   wire $or$ls180.v:4008$471_Y
80088   attribute \src "ls180.v:4008.130-4008.371"
80089   wire $or$ls180.v:4008$474_Y
80090   attribute \src "ls180.v:4008.34-4008.411"
80091   wire $or$ls180.v:4008$479_Y
80092   attribute \src "ls180.v:4008.506-4008.595"
80093   wire $or$ls180.v:4008$484_Y
80094   attribute \src "ls180.v:4008.505-4008.670"
80095   wire $or$ls180.v:4008$487_Y
80096   attribute \src "ls180.v:4008.504-4008.745"
80097   wire $or$ls180.v:4008$490_Y
80098   attribute \src "ls180.v:4008.33-4008.785"
80099   wire $or$ls180.v:4008$495_Y
80100   attribute \src "ls180.v:4008.880-4008.969"
80101   wire $or$ls180.v:4008$500_Y
80102   attribute \src "ls180.v:4008.879-4008.1044"
80103   wire $or$ls180.v:4008$503_Y
80104   attribute \src "ls180.v:4008.878-4008.1119"
80105   wire $or$ls180.v:4008$506_Y
80106   attribute \src "ls180.v:4008.32-4008.1159"
80107   wire $or$ls180.v:4008$511_Y
80108   attribute \src "ls180.v:4008.1254-4008.1343"
80109   wire $or$ls180.v:4008$516_Y
80110   attribute \src "ls180.v:4008.1253-4008.1418"
80111   wire $or$ls180.v:4008$519_Y
80112   attribute \src "ls180.v:4008.1252-4008.1493"
80113   wire $or$ls180.v:4008$522_Y
80114   attribute \src "ls180.v:4008.31-4008.1533"
80115   wire $or$ls180.v:4008$527_Y
80116   attribute \src "ls180.v:4071.10-4071.52"
80117   wire $or$ls180.v:4071$536_Y
80118   attribute \src "ls180.v:4098.35-4098.74"
80119   wire $or$ls180.v:4098$546_Y
80120   attribute \src "ls180.v:4099.34-4099.73"
80121   wire $or$ls180.v:4099$550_Y
80122   attribute \src "ls180.v:4100.48-4100.130"
80123   wire $or$ls180.v:4100$556_Y
80124   attribute \src "ls180.v:4101.24-4101.87"
80125   wire $or$ls180.v:4101$559_Y
80126   attribute \src "ls180.v:4102.26-4102.95"
80127   wire $or$ls180.v:4102$561_Y
80128   attribute \src "ls180.v:4132.42-4132.89"
80129   wire $or$ls180.v:4132$569_Y
80130   attribute \src "ls180.v:4156.25-4156.174"
80131   wire $or$ls180.v:4156$579_Y
80132   attribute \src "ls180.v:4171.80-4171.132"
80133   wire $or$ls180.v:4171$581_Y
80134   attribute \src "ls180.v:4182.72-4182.135"
80135   wire $or$ls180.v:4182$586_Y
80136   attribute \src "ls180.v:4201.80-4201.132"
80137   wire $or$ls180.v:4201$592_Y
80138   attribute \src "ls180.v:4212.72-4212.135"
80139   wire $or$ls180.v:4212$597_Y
80140   attribute \src "ls180.v:4346.36-4346.111"
80141   wire $or$ls180.v:4346$618_Y
80142   attribute \src "ls180.v:4346.35-4346.151"
80143   wire $or$ls180.v:4346$619_Y
80144   attribute \src "ls180.v:4346.34-4346.192"
80145   wire $or$ls180.v:4346$620_Y
80146   attribute \src "ls180.v:4346.33-4346.233"
80147   wire $or$ls180.v:4346$621_Y
80148   attribute \src "ls180.v:4347.39-4347.120"
80149   wire $or$ls180.v:4347$622_Y
80150   attribute \src "ls180.v:4347.38-4347.163"
80151   wire $or$ls180.v:4347$623_Y
80152   attribute \src "ls180.v:4347.37-4347.207"
80153   wire $or$ls180.v:4347$624_Y
80154   attribute \src "ls180.v:4347.36-4347.251"
80155   wire $or$ls180.v:4347$625_Y
80156   attribute \src "ls180.v:4348.38-4348.117"
80157   wire $or$ls180.v:4348$626_Y
80158   attribute \src "ls180.v:4348.37-4348.159"
80159   wire $or$ls180.v:4348$627_Y
80160   attribute \src "ls180.v:4348.36-4348.202"
80161   wire $or$ls180.v:4348$628_Y
80162   attribute \src "ls180.v:4348.35-4348.245"
80163   wire $or$ls180.v:4348$629_Y
80164   attribute \src "ls180.v:4349.40-4349.123"
80165   wire $or$ls180.v:4349$630_Y
80166   attribute \src "ls180.v:4349.39-4349.167"
80167   wire $or$ls180.v:4349$631_Y
80168   attribute \src "ls180.v:4349.38-4349.212"
80169   wire $or$ls180.v:4349$632_Y
80170   attribute \src "ls180.v:4349.37-4349.257"
80171   wire $or$ls180.v:4349$633_Y
80172   attribute \src "ls180.v:4350.39-4350.120"
80173   wire width 4 $or$ls180.v:4350$634_Y
80174   attribute \src "ls180.v:4350.38-4350.163"
80175   wire width 4 $or$ls180.v:4350$635_Y
80176   attribute \src "ls180.v:4350.37-4350.207"
80177   wire width 4 $or$ls180.v:4350$636_Y
80178   attribute \src "ls180.v:4350.36-4350.251"
80179   wire width 4 $or$ls180.v:4350$637_Y
80180   attribute \src "ls180.v:4371.35-4371.80"
80181   wire $or$ls180.v:4371$638_Y
80182   attribute \src "ls180.v:4525.91-4525.144"
80183   wire $or$ls180.v:4525$652_Y
80184   attribute \src "ls180.v:4542.53-4542.143"
80185   wire $or$ls180.v:4542$655_Y
80186   attribute \src "ls180.v:4545.47-4545.127"
80187   wire $or$ls180.v:4545$658_Y
80188   attribute \src "ls180.v:4669.54-4669.146"
80189   wire $or$ls180.v:4669$676_Y
80190   attribute \src "ls180.v:4672.48-4672.130"
80191   wire $or$ls180.v:4672$679_Y
80192   attribute \src "ls180.v:4803.55-4803.149"
80193   wire $or$ls180.v:4803$691_Y
80194   attribute \src "ls180.v:4806.49-4806.133"
80195   wire $or$ls180.v:4806$694_Y
80196   attribute \src "ls180.v:5435.80-5435.151"
80197   wire $or$ls180.v:5435$989_Y
80198   attribute \src "ls180.v:5446.49-5446.131"
80199   wire $or$ls180.v:5446$995_Y
80200   attribute \src "ls180.v:5643.80-5643.151"
80201   wire $or$ls180.v:5643$1020_Y
80202   attribute \src "ls180.v:5758.33-5758.102"
80203   wire $or$ls180.v:5758$1060_Y
80204   attribute \src "ls180.v:5758.32-5758.144"
80205   wire $or$ls180.v:5758$1061_Y
80206   attribute \src "ls180.v:5758.31-5758.165"
80207   wire $or$ls180.v:5758$1062_Y
80208   attribute \src "ls180.v:5758.30-5758.201"
80209   wire $or$ls180.v:5758$1063_Y
80210   attribute \src "ls180.v:5764.28-5764.97"
80211   wire $or$ls180.v:5764$1068_Y
80212   attribute \src "ls180.v:5764.27-5764.139"
80213   wire $or$ls180.v:5764$1069_Y
80214   attribute \src "ls180.v:5764.26-5764.160"
80215   wire $or$ls180.v:5764$1070_Y
80216   attribute \src "ls180.v:5764.25-5764.196"
80217   wire $or$ls180.v:5764$1071_Y
80218   attribute \src "ls180.v:5765.30-5765.169"
80219   wire width 32 $or$ls180.v:5765$1074_Y
80220   attribute \src "ls180.v:5765.29-5765.246"
80221   wire width 32 $or$ls180.v:5765$1076_Y
80222   attribute \src "ls180.v:5765.28-5765.302"
80223   wire width 32 $or$ls180.v:5765$1078_Y
80224   attribute \src "ls180.v:5765.27-5765.373"
80225   wire width 32 $or$ls180.v:5765$1080_Y
80226   attribute \src "ls180.v:6519.55-6519.124"
80227   wire width 8 $or$ls180.v:6519$2226_Y
80228   attribute \src "ls180.v:6519.54-6519.161"
80229   wire width 8 $or$ls180.v:6519$2227_Y
80230   attribute \src "ls180.v:6519.53-6519.198"
80231   wire width 8 $or$ls180.v:6519$2228_Y
80232   attribute \src "ls180.v:6519.52-6519.235"
80233   wire width 8 $or$ls180.v:6519$2229_Y
80234   attribute \src "ls180.v:6519.51-6519.272"
80235   wire width 8 $or$ls180.v:6519$2230_Y
80236   attribute \src "ls180.v:6519.50-6519.309"
80237   wire width 8 $or$ls180.v:6519$2231_Y
80238   attribute \src "ls180.v:6519.49-6519.346"
80239   wire width 8 $or$ls180.v:6519$2232_Y
80240   attribute \src "ls180.v:6519.48-6519.383"
80241   wire width 8 $or$ls180.v:6519$2233_Y
80242   attribute \src "ls180.v:6519.47-6519.420"
80243   wire width 8 $or$ls180.v:6519$2234_Y
80244   attribute \src "ls180.v:6519.46-6519.458"
80245   wire width 8 $or$ls180.v:6519$2235_Y
80246   attribute \src "ls180.v:6519.45-6519.496"
80247   wire width 8 $or$ls180.v:6519$2236_Y
80248   attribute \src "ls180.v:6519.44-6519.534"
80249   wire width 8 $or$ls180.v:6519$2237_Y
80250   attribute \src "ls180.v:6519.43-6519.572"
80251   wire width 8 $or$ls180.v:6519$2238_Y
80252   attribute \src "ls180.v:6519.42-6519.610"
80253   wire width 8 $or$ls180.v:6519$2239_Y
80254   attribute \src "ls180.v:6846.90-6846.179"
80255   wire $or$ls180.v:6846$2264_Y
80256   attribute \src "ls180.v:6846.89-6846.254"
80257   wire $or$ls180.v:6846$2267_Y
80258   attribute \src "ls180.v:6846.88-6846.329"
80259   wire $or$ls180.v:6846$2270_Y
80260   attribute \src "ls180.v:6870.90-6870.179"
80261   wire $or$ls180.v:6870$2280_Y
80262   attribute \src "ls180.v:6870.89-6870.254"
80263   wire $or$ls180.v:6870$2283_Y
80264   attribute \src "ls180.v:6870.88-6870.329"
80265   wire $or$ls180.v:6870$2286_Y
80266   attribute \src "ls180.v:6894.90-6894.179"
80267   wire $or$ls180.v:6894$2296_Y
80268   attribute \src "ls180.v:6894.89-6894.254"
80269   wire $or$ls180.v:6894$2299_Y
80270   attribute \src "ls180.v:6894.88-6894.329"
80271   wire $or$ls180.v:6894$2302_Y
80272   attribute \src "ls180.v:6918.90-6918.179"
80273   wire $or$ls180.v:6918$2312_Y
80274   attribute \src "ls180.v:6918.89-6918.254"
80275   wire $or$ls180.v:6918$2315_Y
80276   attribute \src "ls180.v:6918.88-6918.329"
80277   wire $or$ls180.v:6918$2318_Y
80278   attribute \src "ls180.v:7432.20-7432.71"
80279   wire $or$ls180.v:7432$2375_Y
80280   attribute \src "ls180.v:7433.20-7433.71"
80281   wire $or$ls180.v:7433$2376_Y
80282   attribute \src "ls180.v:7434.20-7434.71"
80283   wire $or$ls180.v:7434$2377_Y
80284   attribute \src "ls180.v:7435.20-7435.71"
80285   wire $or$ls180.v:7435$2378_Y
80286   attribute \src "ls180.v:7436.20-7436.71"
80287   wire $or$ls180.v:7436$2379_Y
80288   attribute \src "ls180.v:7437.20-7437.71"
80289   wire $or$ls180.v:7437$2380_Y
80290   attribute \src "ls180.v:7438.20-7438.71"
80291   wire $or$ls180.v:7438$2381_Y
80292   attribute \src "ls180.v:7439.20-7439.71"
80293   wire $or$ls180.v:7439$2382_Y
80294   attribute \src "ls180.v:7440.20-7440.71"
80295   wire $or$ls180.v:7440$2383_Y
80296   attribute \src "ls180.v:7441.20-7441.71"
80297   wire $or$ls180.v:7441$2384_Y
80298   attribute \src "ls180.v:7442.21-7442.73"
80299   wire $or$ls180.v:7442$2385_Y
80300   attribute \src "ls180.v:7443.21-7443.73"
80301   wire $or$ls180.v:7443$2386_Y
80302   attribute \src "ls180.v:7444.21-7444.73"
80303   wire $or$ls180.v:7444$2387_Y
80304   attribute \src "ls180.v:7445.21-7445.73"
80305   wire $or$ls180.v:7445$2388_Y
80306   attribute \src "ls180.v:7446.21-7446.73"
80307   wire $or$ls180.v:7446$2389_Y
80308   attribute \src "ls180.v:7447.21-7447.73"
80309   wire $or$ls180.v:7447$2390_Y
80310   attribute \src "ls180.v:7448.21-7448.73"
80311   wire $or$ls180.v:7448$2391_Y
80312   attribute \src "ls180.v:7449.21-7449.73"
80313   wire $or$ls180.v:7449$2392_Y
80314   attribute \src "ls180.v:7450.21-7450.73"
80315   wire $or$ls180.v:7450$2393_Y
80316   attribute \src "ls180.v:7451.21-7451.73"
80317   wire $or$ls180.v:7451$2394_Y
80318   attribute \src "ls180.v:7452.21-7452.73"
80319   wire $or$ls180.v:7452$2395_Y
80320   attribute \src "ls180.v:7453.21-7453.73"
80321   wire $or$ls180.v:7453$2396_Y
80322   attribute \src "ls180.v:7454.21-7454.73"
80323   wire $or$ls180.v:7454$2397_Y
80324   attribute \src "ls180.v:7455.21-7455.73"
80325   wire $or$ls180.v:7455$2398_Y
80326   attribute \src "ls180.v:7456.21-7456.73"
80327   wire $or$ls180.v:7456$2399_Y
80328   attribute \src "ls180.v:7457.21-7457.73"
80329   wire $or$ls180.v:7457$2400_Y
80330   attribute \src "ls180.v:7458.21-7458.73"
80331   wire $or$ls180.v:7458$2401_Y
80332   attribute \src "ls180.v:7459.21-7459.73"
80333   wire $or$ls180.v:7459$2402_Y
80334   attribute \src "ls180.v:7460.21-7460.73"
80335   wire $or$ls180.v:7460$2403_Y
80336   attribute \src "ls180.v:7461.21-7461.73"
80337   wire $or$ls180.v:7461$2404_Y
80338   attribute \src "ls180.v:7462.21-7462.73"
80339   wire $or$ls180.v:7462$2405_Y
80340   attribute \src "ls180.v:7463.21-7463.73"
80341   wire $or$ls180.v:7463$2406_Y
80342   attribute \src "ls180.v:7464.21-7464.73"
80343   wire $or$ls180.v:7464$2407_Y
80344   attribute \src "ls180.v:7465.21-7465.73"
80345   wire $or$ls180.v:7465$2408_Y
80346   attribute \src "ls180.v:7466.21-7466.73"
80347   wire $or$ls180.v:7466$2409_Y
80348   attribute \src "ls180.v:7467.21-7467.73"
80349   wire $or$ls180.v:7467$2410_Y
80350   attribute \src "ls180.v:7468.7-7468.93"
80351   wire $or$ls180.v:7468$2411_Y
80352   attribute \src "ls180.v:7479.7-7479.93"
80353   wire $or$ls180.v:7479$2412_Y
80354   attribute \src "ls180.v:7490.7-7490.93"
80355   wire $or$ls180.v:7490$2413_Y
80356   attribute \src "ls180.v:7619.7-7619.107"
80357   wire $or$ls180.v:7619$2449_Y
80358   attribute \src "ls180.v:7665.7-7665.107"
80359   wire $or$ls180.v:7665$2465_Y
80360   attribute \src "ls180.v:7711.7-7711.107"
80361   wire $or$ls180.v:7711$2481_Y
80362   attribute \src "ls180.v:7757.7-7757.107"
80363   wire $or$ls180.v:7757$2497_Y
80364   attribute \src "ls180.v:7945.40-7945.125"
80365   wire $or$ls180.v:7945$2518_Y
80366   attribute \src "ls180.v:7945.39-7945.207"
80367   wire $or$ls180.v:7945$2521_Y
80368   attribute \src "ls180.v:7945.38-7945.289"
80369   wire $or$ls180.v:7945$2524_Y
80370   attribute \src "ls180.v:7945.37-7945.371"
80371   wire $or$ls180.v:7945$2527_Y
80372   attribute \src "ls180.v:7946.41-7946.126"
80373   wire $or$ls180.v:7946$2530_Y
80374   attribute \src "ls180.v:7946.40-7946.208"
80375   wire $or$ls180.v:7946$2533_Y
80376   attribute \src "ls180.v:7946.39-7946.290"
80377   wire $or$ls180.v:7946$2536_Y
80378   attribute \src "ls180.v:7946.38-7946.372"
80379   wire $or$ls180.v:7946$2539_Y
80380   attribute \src "ls180.v:7950.7-7950.49"
80381   wire $or$ls180.v:7950$2540_Y
80382   attribute \src "ls180.v:8113.21-8113.74"
80383   wire $or$ls180.v:8113$2588_Y
80384   attribute \src "ls180.v:8148.21-8148.71"
80385   wire $or$ls180.v:8148$2593_Y
80386   attribute \src "ls180.v:8216.32-8216.85"
80387   wire $or$ls180.v:8216$2605_Y
80388   attribute \src "ls180.v:8222.8-8222.97"
80389   wire $or$ls180.v:8222$2607_Y
80390   attribute \src "ls180.v:8239.52-8239.139"
80391   wire $or$ls180.v:8239$2612_Y
80392   attribute \src "ls180.v:8240.51-8240.136"
80393   wire $or$ls180.v:8240$2613_Y
80394   attribute \src "ls180.v:8274.7-8274.87"
80395   wire $or$ls180.v:8274$2616_Y
80396   attribute \src "ls180.v:8297.33-8297.88"
80397   wire $or$ls180.v:8297$2617_Y
80398   attribute \src "ls180.v:8303.8-8303.99"
80399   wire $or$ls180.v:8303$2619_Y
80400   attribute \src "ls180.v:8320.53-8320.142"
80401   wire $or$ls180.v:8320$2624_Y
80402   attribute \src "ls180.v:8321.52-8321.139"
80403   wire $or$ls180.v:8321$2625_Y
80404   attribute \src "ls180.v:8355.7-8355.89"
80405   wire $or$ls180.v:8355$2628_Y
80406   attribute \src "ls180.v:8376.34-8376.91"
80407   wire $or$ls180.v:8376$2629_Y
80408   attribute \src "ls180.v:8382.8-8382.101"
80409   wire $or$ls180.v:8382$2631_Y
80410   attribute \src "ls180.v:8399.54-8399.145"
80411   wire $or$ls180.v:8399$2636_Y
80412   attribute \src "ls180.v:8400.53-8400.142"
80413   wire $or$ls180.v:8400$2637_Y
80414   attribute \src "ls180.v:8416.7-8416.91"
80415   wire $or$ls180.v:8416$2640_Y
80416   attribute \src "ls180.v:8605.8-8605.89"
80417   wire $or$ls180.v:8605$2664_Y
80418   attribute \src "ls180.v:8622.48-8622.127"
80419   wire $or$ls180.v:8622$2669_Y
80420   attribute \src "ls180.v:8623.47-8623.124"
80421   wire $or$ls180.v:8623$2670_Y
80422   attribute \src "ls180.v:3182.46-3182.94"
80423   wire width 13 $sshl$ls180.v:3182$83_Y
80424   attribute \src "ls180.v:3339.46-3339.94"
80425   wire width 13 $sshl$ls180.v:3339$113_Y
80426   attribute \src "ls180.v:3496.46-3496.94"
80427   wire width 13 $sshl$ls180.v:3496$143_Y
80428   attribute \src "ls180.v:3653.46-3653.94"
80429   wire width 13 $sshl$ls180.v:3653$173_Y
80430   attribute \src "ls180.v:3213.63-3213.122"
80431   wire width 3 $sub$ls180.v:3213$96_Y
80432   attribute \src "ls180.v:3370.63-3370.122"
80433   wire width 3 $sub$ls180.v:3370$126_Y
80434   attribute \src "ls180.v:3527.63-3527.122"
80435   wire width 3 $sub$ls180.v:3527$156_Y
80436   attribute \src "ls180.v:3684.63-3684.122"
80437   wire width 3 $sub$ls180.v:3684$186_Y
80438   attribute \src "ls180.v:4090.38-4090.75"
80439   wire width 31 $sub$ls180.v:4090$540_Y
80440   attribute \src "ls180.v:4176.36-4176.68"
80441   wire width 4 $sub$ls180.v:4176$585_Y
80442   attribute \src "ls180.v:4206.36-4206.68"
80443   wire width 4 $sub$ls180.v:4206$596_Y
80444   attribute \src "ls180.v:4231.70-4231.110"
80445   wire width 16 $sub$ls180.v:4231$602_Y
80446   attribute \src "ls180.v:4232.70-4232.104"
80447   wire width 16 $sub$ls180.v:4232$604_Y
80448   attribute \src "ls180.v:4259.37-4259.66"
80449   wire width 8 $sub$ls180.v:4259$608_Y
80450   attribute \src "ls180.v:4289.67-4289.107"
80451   wire width 16 $sub$ls180.v:4289$610_Y
80452   attribute \src "ls180.v:4290.67-4290.101"
80453   wire width 16 $sub$ls180.v:4290$612_Y
80454   attribute \src "ls180.v:4318.35-4318.64"
80455   wire width 8 $sub$ls180.v:4318$616_Y
80456   attribute \src "ls180.v:4572.60-4572.90"
80457   wire width 32 $sub$ls180.v:4572$660_Y
80458   attribute \src "ls180.v:4583.62-4583.104"
80459   wire width 8 $sub$ls180.v:4583$662_Y
80460   attribute \src "ls180.v:4600.60-4600.90"
80461   wire width 32 $sub$ls180.v:4600$666_Y
80462   attribute \src "ls180.v:4829.62-4829.93"
80463   wire width 32 $sub$ls180.v:4829$696_Y
80464   attribute \src "ls180.v:4834.62-4834.93"
80465   wire width 32 $sub$ls180.v:4834$697_Y
80466   attribute \src "ls180.v:4845.64-4845.122"
80467   wire width 10 $sub$ls180.v:4845$700_Y
80468   attribute \src "ls180.v:4866.62-4866.93"
80469   wire width 32 $sub$ls180.v:4866$703_Y
80470   attribute \src "ls180.v:5328.37-5328.75"
80471   wire width 32 $sub$ls180.v:5328$976_Y
80472   attribute \src "ls180.v:5343.62-5343.100"
80473   wire width 32 $sub$ls180.v:5343$979_Y
80474   attribute \src "ls180.v:5354.39-5354.77"
80475   wire width 32 $sub$ls180.v:5354$984_Y
80476   attribute \src "ls180.v:5429.40-5429.76"
80477   wire width 5 $sub$ls180.v:5429$988_Y
80478   attribute \src "ls180.v:5478.56-5478.104"
80479   wire width 32 $sub$ls180.v:5478$1002_Y
80480   attribute \src "ls180.v:5568.71-5568.105"
80481   wire width 32 $sub$ls180.v:5568$1008_Y
80482   attribute \src "ls180.v:5637.40-5637.76"
80483   wire width 5 $sub$ls180.v:5637$1019_Y
80484   attribute \src "ls180.v:7514.31-7514.60"
80485   wire width 32 $sub$ls180.v:7514$2420_Y
80486   attribute \src "ls180.v:7535.31-7535.61"
80487   wire width 10 $sub$ls180.v:7535$2425_Y
80488   attribute \src "ls180.v:7541.34-7541.67"
80489   wire $sub$ls180.v:7541$2426_Y
80490   attribute \src "ls180.v:7552.36-7552.69"
80491   wire $sub$ls180.v:7552$2429_Y
80492   attribute \src "ls180.v:7616.59-7616.116"
80493   wire width 4 $sub$ls180.v:7616$2447_Y
80494   attribute \src "ls180.v:7635.46-7635.90"
80495   wire width 3 $sub$ls180.v:7635$2451_Y
80496   attribute \src "ls180.v:7662.59-7662.116"
80497   wire width 4 $sub$ls180.v:7662$2463_Y
80498   attribute \src "ls180.v:7681.46-7681.90"
80499   wire width 3 $sub$ls180.v:7681$2467_Y
80500   attribute \src "ls180.v:7708.59-7708.116"
80501   wire width 4 $sub$ls180.v:7708$2479_Y
80502   attribute \src "ls180.v:7727.46-7727.90"
80503   wire width 3 $sub$ls180.v:7727$2483_Y
80504   attribute \src "ls180.v:7754.59-7754.116"
80505   wire width 4 $sub$ls180.v:7754$2495_Y
80506   attribute \src "ls180.v:7773.46-7773.90"
80507   wire width 3 $sub$ls180.v:7773$2499_Y
80508   attribute \src "ls180.v:7784.25-7784.48"
80509   wire width 5 $sub$ls180.v:7784$2503_Y
80510   attribute \src "ls180.v:7791.25-7791.48"
80511   wire width 4 $sub$ls180.v:7791$2506_Y
80512   attribute \src "ls180.v:7923.33-7923.64"
80513   wire $sub$ls180.v:7923$2511_Y
80514   attribute \src "ls180.v:7938.33-7938.64"
80515   wire width 3 $sub$ls180.v:7938$2514_Y
80516   attribute \src "ls180.v:8065.33-8065.64"
80517   wire width 5 $sub$ls180.v:8065$2573_Y
80518   attribute \src "ls180.v:8087.33-8087.64"
80519   wire width 5 $sub$ls180.v:8087$2584_Y
80520   attribute \src "ls180.v:8122.34-8122.66"
80521   wire width 3 $sub$ls180.v:8122$2589_Y
80522   attribute \src "ls180.v:8157.32-8157.62"
80523   wire width 3 $sub$ls180.v:8157$2594_Y
80524   attribute \src "ls180.v:8181.30-8181.53"
80525   wire width 32 $sub$ls180.v:8181$2597_Y
80526   attribute \src "ls180.v:8195.30-8195.53"
80527   wire width 32 $sub$ls180.v:8195$2601_Y
80528   attribute \src "ls180.v:8598.36-8598.70"
80529   wire width 6 $sub$ls180.v:8598$2662_Y
80530   attribute \src "ls180.v:8684.36-8684.70"
80531   wire width 6 $sub$ls180.v:8684$2684_Y
80532   attribute \src "ls180.v:8797.22-8797.42"
80533   wire width 20 $sub$ls180.v:8797$2691_Y
80534   attribute \src "ls180.v:4926.353-4926.425"
80535   wire $xor$ls180.v:4926$710_Y
80536   attribute \src "ls180.v:4926.200-4926.272"
80537   wire $xor$ls180.v:4926$711_Y
80538   attribute \src "ls180.v:4926.160-4926.273"
80539   wire $xor$ls180.v:4926$712_Y
80540   attribute \src "ls180.v:4927.353-4927.425"
80541   wire $xor$ls180.v:4927$713_Y
80542   attribute \src "ls180.v:4927.200-4927.272"
80543   wire $xor$ls180.v:4927$714_Y
80544   attribute \src "ls180.v:4927.160-4927.273"
80545   wire $xor$ls180.v:4927$715_Y
80546   attribute \src "ls180.v:4928.353-4928.425"
80547   wire $xor$ls180.v:4928$716_Y
80548   attribute \src "ls180.v:4928.200-4928.272"
80549   wire $xor$ls180.v:4928$717_Y
80550   attribute \src "ls180.v:4928.160-4928.273"
80551   wire $xor$ls180.v:4928$718_Y
80552   attribute \src "ls180.v:4929.353-4929.425"
80553   wire $xor$ls180.v:4929$719_Y
80554   attribute \src "ls180.v:4929.200-4929.272"
80555   wire $xor$ls180.v:4929$720_Y
80556   attribute \src "ls180.v:4929.160-4929.273"
80557   wire $xor$ls180.v:4929$721_Y
80558   attribute \src "ls180.v:4930.353-4930.425"
80559   wire $xor$ls180.v:4930$722_Y
80560   attribute \src "ls180.v:4930.200-4930.272"
80561   wire $xor$ls180.v:4930$723_Y
80562   attribute \src "ls180.v:4930.160-4930.273"
80563   wire $xor$ls180.v:4930$724_Y
80564   attribute \src "ls180.v:4931.353-4931.425"
80565   wire $xor$ls180.v:4931$725_Y
80566   attribute \src "ls180.v:4931.200-4931.272"
80567   wire $xor$ls180.v:4931$726_Y
80568   attribute \src "ls180.v:4931.160-4931.273"
80569   wire $xor$ls180.v:4931$727_Y
80570   attribute \src "ls180.v:4932.353-4932.425"
80571   wire $xor$ls180.v:4932$728_Y
80572   attribute \src "ls180.v:4932.200-4932.272"
80573   wire $xor$ls180.v:4932$729_Y
80574   attribute \src "ls180.v:4932.160-4932.273"
80575   wire $xor$ls180.v:4932$730_Y
80576   attribute \src "ls180.v:4933.353-4933.425"
80577   wire $xor$ls180.v:4933$731_Y
80578   attribute \src "ls180.v:4933.200-4933.272"
80579   wire $xor$ls180.v:4933$732_Y
80580   attribute \src "ls180.v:4933.160-4933.273"
80581   wire $xor$ls180.v:4933$733_Y
80582   attribute \src "ls180.v:4934.353-4934.425"
80583   wire $xor$ls180.v:4934$734_Y
80584   attribute \src "ls180.v:4934.200-4934.272"
80585   wire $xor$ls180.v:4934$735_Y
80586   attribute \src "ls180.v:4934.160-4934.273"
80587   wire $xor$ls180.v:4934$736_Y
80588   attribute \src "ls180.v:4935.354-4935.426"
80589   wire $xor$ls180.v:4935$737_Y
80590   attribute \src "ls180.v:4935.201-4935.273"
80591   wire $xor$ls180.v:4935$738_Y
80592   attribute \src "ls180.v:4935.161-4935.274"
80593   wire $xor$ls180.v:4935$739_Y
80594   attribute \src "ls180.v:4936.361-4936.434"
80595   wire $xor$ls180.v:4936$740_Y
80596   attribute \src "ls180.v:4936.205-4936.278"
80597   wire $xor$ls180.v:4936$741_Y
80598   attribute \src "ls180.v:4936.164-4936.279"
80599   wire $xor$ls180.v:4936$742_Y
80600   attribute \src "ls180.v:4937.361-4937.434"
80601   wire $xor$ls180.v:4937$743_Y
80602   attribute \src "ls180.v:4937.205-4937.278"
80603   wire $xor$ls180.v:4937$744_Y
80604   attribute \src "ls180.v:4937.164-4937.279"
80605   wire $xor$ls180.v:4937$745_Y
80606   attribute \src "ls180.v:4938.361-4938.434"
80607   wire $xor$ls180.v:4938$746_Y
80608   attribute \src "ls180.v:4938.205-4938.278"
80609   wire $xor$ls180.v:4938$747_Y
80610   attribute \src "ls180.v:4938.164-4938.279"
80611   wire $xor$ls180.v:4938$748_Y
80612   attribute \src "ls180.v:4939.361-4939.434"
80613   wire $xor$ls180.v:4939$749_Y
80614   attribute \src "ls180.v:4939.205-4939.278"
80615   wire $xor$ls180.v:4939$750_Y
80616   attribute \src "ls180.v:4939.164-4939.279"
80617   wire $xor$ls180.v:4939$751_Y
80618   attribute \src "ls180.v:4940.361-4940.434"
80619   wire $xor$ls180.v:4940$752_Y
80620   attribute \src "ls180.v:4940.205-4940.278"
80621   wire $xor$ls180.v:4940$753_Y
80622   attribute \src "ls180.v:4940.164-4940.279"
80623   wire $xor$ls180.v:4940$754_Y
80624   attribute \src "ls180.v:4941.361-4941.434"
80625   wire $xor$ls180.v:4941$755_Y
80626   attribute \src "ls180.v:4941.205-4941.278"
80627   wire $xor$ls180.v:4941$756_Y
80628   attribute \src "ls180.v:4941.164-4941.279"
80629   wire $xor$ls180.v:4941$757_Y
80630   attribute \src "ls180.v:4942.361-4942.434"
80631   wire $xor$ls180.v:4942$758_Y
80632   attribute \src "ls180.v:4942.205-4942.278"
80633   wire $xor$ls180.v:4942$759_Y
80634   attribute \src "ls180.v:4942.164-4942.279"
80635   wire $xor$ls180.v:4942$760_Y
80636   attribute \src "ls180.v:4943.361-4943.434"
80637   wire $xor$ls180.v:4943$761_Y
80638   attribute \src "ls180.v:4943.205-4943.278"
80639   wire $xor$ls180.v:4943$762_Y
80640   attribute \src "ls180.v:4943.164-4943.279"
80641   wire $xor$ls180.v:4943$763_Y
80642   attribute \src "ls180.v:4944.361-4944.434"
80643   wire $xor$ls180.v:4944$764_Y
80644   attribute \src "ls180.v:4944.205-4944.278"
80645   wire $xor$ls180.v:4944$765_Y
80646   attribute \src "ls180.v:4944.164-4944.279"
80647   wire $xor$ls180.v:4944$766_Y
80648   attribute \src "ls180.v:4945.361-4945.434"
80649   wire $xor$ls180.v:4945$767_Y
80650   attribute \src "ls180.v:4945.205-4945.278"
80651   wire $xor$ls180.v:4945$768_Y
80652   attribute \src "ls180.v:4945.164-4945.279"
80653   wire $xor$ls180.v:4945$769_Y
80654   attribute \src "ls180.v:4946.361-4946.434"
80655   wire $xor$ls180.v:4946$770_Y
80656   attribute \src "ls180.v:4946.205-4946.278"
80657   wire $xor$ls180.v:4946$771_Y
80658   attribute \src "ls180.v:4946.164-4946.279"
80659   wire $xor$ls180.v:4946$772_Y
80660   attribute \src "ls180.v:4947.361-4947.434"
80661   wire $xor$ls180.v:4947$773_Y
80662   attribute \src "ls180.v:4947.205-4947.278"
80663   wire $xor$ls180.v:4947$774_Y
80664   attribute \src "ls180.v:4947.164-4947.279"
80665   wire $xor$ls180.v:4947$775_Y
80666   attribute \src "ls180.v:4948.361-4948.434"
80667   wire $xor$ls180.v:4948$776_Y
80668   attribute \src "ls180.v:4948.205-4948.278"
80669   wire $xor$ls180.v:4948$777_Y
80670   attribute \src "ls180.v:4948.164-4948.279"
80671   wire $xor$ls180.v:4948$778_Y
80672   attribute \src "ls180.v:4949.361-4949.434"
80673   wire $xor$ls180.v:4949$779_Y
80674   attribute \src "ls180.v:4949.205-4949.278"
80675   wire $xor$ls180.v:4949$780_Y
80676   attribute \src "ls180.v:4949.164-4949.279"
80677   wire $xor$ls180.v:4949$781_Y
80678   attribute \src "ls180.v:4950.361-4950.434"
80679   wire $xor$ls180.v:4950$782_Y
80680   attribute \src "ls180.v:4950.205-4950.278"
80681   wire $xor$ls180.v:4950$783_Y
80682   attribute \src "ls180.v:4950.164-4950.279"
80683   wire $xor$ls180.v:4950$784_Y
80684   attribute \src "ls180.v:4951.361-4951.434"
80685   wire $xor$ls180.v:4951$785_Y
80686   attribute \src "ls180.v:4951.205-4951.278"
80687   wire $xor$ls180.v:4951$786_Y
80688   attribute \src "ls180.v:4951.164-4951.279"
80689   wire $xor$ls180.v:4951$787_Y
80690   attribute \src "ls180.v:4952.361-4952.434"
80691   wire $xor$ls180.v:4952$788_Y
80692   attribute \src "ls180.v:4952.205-4952.278"
80693   wire $xor$ls180.v:4952$789_Y
80694   attribute \src "ls180.v:4952.164-4952.279"
80695   wire $xor$ls180.v:4952$790_Y
80696   attribute \src "ls180.v:4953.361-4953.434"
80697   wire $xor$ls180.v:4953$791_Y
80698   attribute \src "ls180.v:4953.205-4953.278"
80699   wire $xor$ls180.v:4953$792_Y
80700   attribute \src "ls180.v:4953.164-4953.279"
80701   wire $xor$ls180.v:4953$793_Y
80702   attribute \src "ls180.v:4954.361-4954.434"
80703   wire $xor$ls180.v:4954$794_Y
80704   attribute \src "ls180.v:4954.205-4954.278"
80705   wire $xor$ls180.v:4954$795_Y
80706   attribute \src "ls180.v:4954.164-4954.279"
80707   wire $xor$ls180.v:4954$796_Y
80708   attribute \src "ls180.v:4955.361-4955.434"
80709   wire $xor$ls180.v:4955$797_Y
80710   attribute \src "ls180.v:4955.205-4955.278"
80711   wire $xor$ls180.v:4955$798_Y
80712   attribute \src "ls180.v:4955.164-4955.279"
80713   wire $xor$ls180.v:4955$799_Y
80714   attribute \src "ls180.v:4956.360-4956.432"
80715   wire $xor$ls180.v:4956$800_Y
80716   attribute \src "ls180.v:4956.205-4956.277"
80717   wire $xor$ls180.v:4956$801_Y
80718   attribute \src "ls180.v:4956.164-4956.278"
80719   wire $xor$ls180.v:4956$802_Y
80720   attribute \src "ls180.v:4957.360-4957.432"
80721   wire $xor$ls180.v:4957$803_Y
80722   attribute \src "ls180.v:4957.205-4957.277"
80723   wire $xor$ls180.v:4957$804_Y
80724   attribute \src "ls180.v:4957.164-4957.278"
80725   wire $xor$ls180.v:4957$805_Y
80726   attribute \src "ls180.v:4958.360-4958.432"
80727   wire $xor$ls180.v:4958$806_Y
80728   attribute \src "ls180.v:4958.205-4958.277"
80729   wire $xor$ls180.v:4958$807_Y
80730   attribute \src "ls180.v:4958.164-4958.278"
80731   wire $xor$ls180.v:4958$808_Y
80732   attribute \src "ls180.v:4959.360-4959.432"
80733   wire $xor$ls180.v:4959$809_Y
80734   attribute \src "ls180.v:4959.205-4959.277"
80735   wire $xor$ls180.v:4959$810_Y
80736   attribute \src "ls180.v:4959.164-4959.278"
80737   wire $xor$ls180.v:4959$811_Y
80738   attribute \src "ls180.v:4960.360-4960.432"
80739   wire $xor$ls180.v:4960$812_Y
80740   attribute \src "ls180.v:4960.205-4960.277"
80741   wire $xor$ls180.v:4960$813_Y
80742   attribute \src "ls180.v:4960.164-4960.278"
80743   wire $xor$ls180.v:4960$814_Y
80744   attribute \src "ls180.v:4961.360-4961.432"
80745   wire $xor$ls180.v:4961$815_Y
80746   attribute \src "ls180.v:4961.205-4961.277"
80747   wire $xor$ls180.v:4961$816_Y
80748   attribute \src "ls180.v:4961.164-4961.278"
80749   wire $xor$ls180.v:4961$817_Y
80750   attribute \src "ls180.v:4962.360-4962.432"
80751   wire $xor$ls180.v:4962$818_Y
80752   attribute \src "ls180.v:4962.205-4962.277"
80753   wire $xor$ls180.v:4962$819_Y
80754   attribute \src "ls180.v:4962.164-4962.278"
80755   wire $xor$ls180.v:4962$820_Y
80756   attribute \src "ls180.v:4963.360-4963.432"
80757   wire $xor$ls180.v:4963$821_Y
80758   attribute \src "ls180.v:4963.205-4963.277"
80759   wire $xor$ls180.v:4963$822_Y
80760   attribute \src "ls180.v:4963.164-4963.278"
80761   wire $xor$ls180.v:4963$823_Y
80762   attribute \src "ls180.v:4964.360-4964.432"
80763   wire $xor$ls180.v:4964$824_Y
80764   attribute \src "ls180.v:4964.205-4964.277"
80765   wire $xor$ls180.v:4964$825_Y
80766   attribute \src "ls180.v:4964.164-4964.278"
80767   wire $xor$ls180.v:4964$826_Y
80768   attribute \src "ls180.v:4965.360-4965.432"
80769   wire $xor$ls180.v:4965$827_Y
80770   attribute \src "ls180.v:4965.205-4965.277"
80771   wire $xor$ls180.v:4965$828_Y
80772   attribute \src "ls180.v:4965.164-4965.278"
80773   wire $xor$ls180.v:4965$829_Y
80774   attribute \src "ls180.v:4986.899-4986.983"
80775   wire $xor$ls180.v:4986$843_Y
80776   attribute \src "ls180.v:4986.634-4986.718"
80777   wire $xor$ls180.v:4986$844_Y
80778   attribute \src "ls180.v:4986.588-4986.719"
80779   wire $xor$ls180.v:4986$845_Y
80780   attribute \src "ls180.v:4986.234-4986.318"
80781   wire $xor$ls180.v:4986$846_Y
80782   attribute \src "ls180.v:4986.187-4986.319"
80783   wire $xor$ls180.v:4986$847_Y
80784   attribute \src "ls180.v:4987.899-4987.983"
80785   wire $xor$ls180.v:4987$848_Y
80786   attribute \src "ls180.v:4987.634-4987.718"
80787   wire $xor$ls180.v:4987$849_Y
80788   attribute \src "ls180.v:4987.588-4987.719"
80789   wire $xor$ls180.v:4987$850_Y
80790   attribute \src "ls180.v:4987.234-4987.318"
80791   wire $xor$ls180.v:4987$851_Y
80792   attribute \src "ls180.v:4987.187-4987.319"
80793   wire $xor$ls180.v:4987$852_Y
80794   attribute \src "ls180.v:4996.899-4996.983"
80795   wire $xor$ls180.v:4996$854_Y
80796   attribute \src "ls180.v:4996.634-4996.718"
80797   wire $xor$ls180.v:4996$855_Y
80798   attribute \src "ls180.v:4996.588-4996.719"
80799   wire $xor$ls180.v:4996$856_Y
80800   attribute \src "ls180.v:4996.234-4996.318"
80801   wire $xor$ls180.v:4996$857_Y
80802   attribute \src "ls180.v:4996.187-4996.319"
80803   wire $xor$ls180.v:4996$858_Y
80804   attribute \src "ls180.v:4997.899-4997.983"
80805   wire $xor$ls180.v:4997$859_Y
80806   attribute \src "ls180.v:4997.634-4997.718"
80807   wire $xor$ls180.v:4997$860_Y
80808   attribute \src "ls180.v:4997.588-4997.719"
80809   wire $xor$ls180.v:4997$861_Y
80810   attribute \src "ls180.v:4997.234-4997.318"
80811   wire $xor$ls180.v:4997$862_Y
80812   attribute \src "ls180.v:4997.187-4997.319"
80813   wire $xor$ls180.v:4997$863_Y
80814   attribute \src "ls180.v:5006.899-5006.983"
80815   wire $xor$ls180.v:5006$865_Y
80816   attribute \src "ls180.v:5006.634-5006.718"
80817   wire $xor$ls180.v:5006$866_Y
80818   attribute \src "ls180.v:5006.588-5006.719"
80819   wire $xor$ls180.v:5006$867_Y
80820   attribute \src "ls180.v:5006.234-5006.318"
80821   wire $xor$ls180.v:5006$868_Y
80822   attribute \src "ls180.v:5006.187-5006.319"
80823   wire $xor$ls180.v:5006$869_Y
80824   attribute \src "ls180.v:5007.899-5007.983"
80825   wire $xor$ls180.v:5007$870_Y
80826   attribute \src "ls180.v:5007.634-5007.718"
80827   wire $xor$ls180.v:5007$871_Y
80828   attribute \src "ls180.v:5007.588-5007.719"
80829   wire $xor$ls180.v:5007$872_Y
80830   attribute \src "ls180.v:5007.234-5007.318"
80831   wire $xor$ls180.v:5007$873_Y
80832   attribute \src "ls180.v:5007.187-5007.319"
80833   wire $xor$ls180.v:5007$874_Y
80834   attribute \src "ls180.v:5016.899-5016.983"
80835   wire $xor$ls180.v:5016$876_Y
80836   attribute \src "ls180.v:5016.634-5016.718"
80837   wire $xor$ls180.v:5016$877_Y
80838   attribute \src "ls180.v:5016.588-5016.719"
80839   wire $xor$ls180.v:5016$878_Y
80840   attribute \src "ls180.v:5016.234-5016.318"
80841   wire $xor$ls180.v:5016$879_Y
80842   attribute \src "ls180.v:5016.187-5016.319"
80843   wire $xor$ls180.v:5016$880_Y
80844   attribute \src "ls180.v:5017.899-5017.983"
80845   wire $xor$ls180.v:5017$881_Y
80846   attribute \src "ls180.v:5017.634-5017.718"
80847   wire $xor$ls180.v:5017$882_Y
80848   attribute \src "ls180.v:5017.588-5017.719"
80849   wire $xor$ls180.v:5017$883_Y
80850   attribute \src "ls180.v:5017.234-5017.318"
80851   wire $xor$ls180.v:5017$884_Y
80852   attribute \src "ls180.v:5017.187-5017.319"
80853   wire $xor$ls180.v:5017$885_Y
80854   attribute \src "ls180.v:5168.879-5168.961"
80855   wire $xor$ls180.v:5168$918_Y
80856   attribute \src "ls180.v:5168.620-5168.702"
80857   wire $xor$ls180.v:5168$919_Y
80858   attribute \src "ls180.v:5168.575-5168.703"
80859   wire $xor$ls180.v:5168$920_Y
80860   attribute \src "ls180.v:5168.229-5168.311"
80861   wire $xor$ls180.v:5168$921_Y
80862   attribute \src "ls180.v:5168.183-5168.312"
80863   wire $xor$ls180.v:5168$922_Y
80864   attribute \src "ls180.v:5169.879-5169.961"
80865   wire $xor$ls180.v:5169$923_Y
80866   attribute \src "ls180.v:5169.620-5169.702"
80867   wire $xor$ls180.v:5169$924_Y
80868   attribute \src "ls180.v:5169.575-5169.703"
80869   wire $xor$ls180.v:5169$925_Y
80870   attribute \src "ls180.v:5169.229-5169.311"
80871   wire $xor$ls180.v:5169$926_Y
80872   attribute \src "ls180.v:5169.183-5169.312"
80873   wire $xor$ls180.v:5169$927_Y
80874   attribute \src "ls180.v:5178.879-5178.961"
80875   wire $xor$ls180.v:5178$929_Y
80876   attribute \src "ls180.v:5178.620-5178.702"
80877   wire $xor$ls180.v:5178$930_Y
80878   attribute \src "ls180.v:5178.575-5178.703"
80879   wire $xor$ls180.v:5178$931_Y
80880   attribute \src "ls180.v:5178.229-5178.311"
80881   wire $xor$ls180.v:5178$932_Y
80882   attribute \src "ls180.v:5178.183-5178.312"
80883   wire $xor$ls180.v:5178$933_Y
80884   attribute \src "ls180.v:5179.879-5179.961"
80885   wire $xor$ls180.v:5179$934_Y
80886   attribute \src "ls180.v:5179.620-5179.702"
80887   wire $xor$ls180.v:5179$935_Y
80888   attribute \src "ls180.v:5179.575-5179.703"
80889   wire $xor$ls180.v:5179$936_Y
80890   attribute \src "ls180.v:5179.229-5179.311"
80891   wire $xor$ls180.v:5179$937_Y
80892   attribute \src "ls180.v:5179.183-5179.312"
80893   wire $xor$ls180.v:5179$938_Y
80894   attribute \src "ls180.v:5188.879-5188.961"
80895   wire $xor$ls180.v:5188$940_Y
80896   attribute \src "ls180.v:5188.620-5188.702"
80897   wire $xor$ls180.v:5188$941_Y
80898   attribute \src "ls180.v:5188.575-5188.703"
80899   wire $xor$ls180.v:5188$942_Y
80900   attribute \src "ls180.v:5188.229-5188.311"
80901   wire $xor$ls180.v:5188$943_Y
80902   attribute \src "ls180.v:5188.183-5188.312"
80903   wire $xor$ls180.v:5188$944_Y
80904   attribute \src "ls180.v:5189.879-5189.961"
80905   wire $xor$ls180.v:5189$945_Y
80906   attribute \src "ls180.v:5189.620-5189.702"
80907   wire $xor$ls180.v:5189$946_Y
80908   attribute \src "ls180.v:5189.575-5189.703"
80909   wire $xor$ls180.v:5189$947_Y
80910   attribute \src "ls180.v:5189.229-5189.311"
80911   wire $xor$ls180.v:5189$948_Y
80912   attribute \src "ls180.v:5189.183-5189.312"
80913   wire $xor$ls180.v:5189$949_Y
80914   attribute \src "ls180.v:5198.879-5198.961"
80915   wire $xor$ls180.v:5198$951_Y
80916   attribute \src "ls180.v:5198.620-5198.702"
80917   wire $xor$ls180.v:5198$952_Y
80918   attribute \src "ls180.v:5198.575-5198.703"
80919   wire $xor$ls180.v:5198$953_Y
80920   attribute \src "ls180.v:5198.229-5198.311"
80921   wire $xor$ls180.v:5198$954_Y
80922   attribute \src "ls180.v:5198.183-5198.312"
80923   wire $xor$ls180.v:5198$955_Y
80924   attribute \src "ls180.v:5199.879-5199.961"
80925   wire $xor$ls180.v:5199$956_Y
80926   attribute \src "ls180.v:5199.620-5199.702"
80927   wire $xor$ls180.v:5199$957_Y
80928   attribute \src "ls180.v:5199.575-5199.703"
80929   wire $xor$ls180.v:5199$958_Y
80930   attribute \src "ls180.v:5199.229-5199.311"
80931   wire $xor$ls180.v:5199$959_Y
80932   attribute \src "ls180.v:5199.183-5199.312"
80933   wire $xor$ls180.v:5199$960_Y
80934   attribute \src "ls180.v:1749.11-1749.42"
80935   wire width 3 \builder_bankmachine0_next_state
80936   attribute \src "ls180.v:1748.11-1748.37"
80937   wire width 3 \builder_bankmachine0_state
80938   attribute \src "ls180.v:1751.11-1751.42"
80939   wire width 3 \builder_bankmachine1_next_state
80940   attribute \src "ls180.v:1750.11-1750.37"
80941   wire width 3 \builder_bankmachine1_state
80942   attribute \src "ls180.v:1753.11-1753.42"
80943   wire width 3 \builder_bankmachine2_next_state
80944   attribute \src "ls180.v:1752.11-1752.37"
80945   wire width 3 \builder_bankmachine2_state
80946   attribute \src "ls180.v:1755.11-1755.42"
80947   wire width 3 \builder_bankmachine3_next_state
80948   attribute \src "ls180.v:1754.11-1754.37"
80949   wire width 3 \builder_bankmachine3_state
80950   attribute \src "ls180.v:2600.5-2600.34"
80951   wire \builder_comb_rhs_array_muxed0
80952   attribute \src "ls180.v:2601.12-2601.41"
80953   wire width 13 \builder_comb_rhs_array_muxed1
80954   attribute \src "ls180.v:2613.5-2613.35"
80955   wire \builder_comb_rhs_array_muxed10
80956   attribute \src "ls180.v:2614.5-2614.35"
80957   wire \builder_comb_rhs_array_muxed11
80958   attribute \src "ls180.v:2618.12-2618.42"
80959   wire width 22 \builder_comb_rhs_array_muxed12
80960   attribute \src "ls180.v:2619.5-2619.35"
80961   wire \builder_comb_rhs_array_muxed13
80962   attribute \src "ls180.v:2620.5-2620.35"
80963   wire \builder_comb_rhs_array_muxed14
80964   attribute \src "ls180.v:2621.12-2621.42"
80965   wire width 22 \builder_comb_rhs_array_muxed15
80966   attribute \src "ls180.v:2622.5-2622.35"
80967   wire \builder_comb_rhs_array_muxed16
80968   attribute \src "ls180.v:2623.5-2623.35"
80969   wire \builder_comb_rhs_array_muxed17
80970   attribute \src "ls180.v:2624.12-2624.42"
80971   wire width 22 \builder_comb_rhs_array_muxed18
80972   attribute \src "ls180.v:2625.5-2625.35"
80973   wire \builder_comb_rhs_array_muxed19
80974   attribute \src "ls180.v:2602.11-2602.40"
80975   wire width 2 \builder_comb_rhs_array_muxed2
80976   attribute \src "ls180.v:2626.5-2626.35"
80977   wire \builder_comb_rhs_array_muxed20
80978   attribute \src "ls180.v:2627.12-2627.42"
80979   wire width 22 \builder_comb_rhs_array_muxed21
80980   attribute \src "ls180.v:2628.5-2628.35"
80981   wire \builder_comb_rhs_array_muxed22
80982   attribute \src "ls180.v:2629.5-2629.35"
80983   wire \builder_comb_rhs_array_muxed23
80984   attribute \src "ls180.v:2630.12-2630.42"
80985   wire width 32 \builder_comb_rhs_array_muxed24
80986   attribute \src "ls180.v:2631.12-2631.42"
80987   wire width 32 \builder_comb_rhs_array_muxed25
80988   attribute \src "ls180.v:2632.11-2632.41"
80989   wire width 4 \builder_comb_rhs_array_muxed26
80990   attribute \src "ls180.v:2633.5-2633.35"
80991   wire \builder_comb_rhs_array_muxed27
80992   attribute \src "ls180.v:2634.5-2634.35"
80993   wire \builder_comb_rhs_array_muxed28
80994   attribute \src "ls180.v:2635.5-2635.35"
80995   wire \builder_comb_rhs_array_muxed29
80996   attribute \src "ls180.v:2603.5-2603.34"
80997   wire \builder_comb_rhs_array_muxed3
80998   attribute \src "ls180.v:2636.11-2636.41"
80999   wire width 3 \builder_comb_rhs_array_muxed30
81000   attribute \src "ls180.v:2637.11-2637.41"
81001   wire width 2 \builder_comb_rhs_array_muxed31
81002   attribute \src "ls180.v:2604.5-2604.34"
81003   wire \builder_comb_rhs_array_muxed4
81004   attribute \src "ls180.v:2605.5-2605.34"
81005   wire \builder_comb_rhs_array_muxed5
81006   attribute \src "ls180.v:2609.5-2609.34"
81007   wire \builder_comb_rhs_array_muxed6
81008   attribute \src "ls180.v:2610.12-2610.41"
81009   wire width 13 \builder_comb_rhs_array_muxed7
81010   attribute \src "ls180.v:2611.11-2611.40"
81011   wire width 2 \builder_comb_rhs_array_muxed8
81012   attribute \src "ls180.v:2612.5-2612.34"
81013   wire \builder_comb_rhs_array_muxed9
81014   attribute \src "ls180.v:2606.5-2606.32"
81015   wire \builder_comb_t_array_muxed0
81016   attribute \src "ls180.v:2607.5-2607.32"
81017   wire \builder_comb_t_array_muxed1
81018   attribute \src "ls180.v:2608.5-2608.32"
81019   wire \builder_comb_t_array_muxed2
81020   attribute \src "ls180.v:2615.5-2615.32"
81021   wire \builder_comb_t_array_muxed3
81022   attribute \src "ls180.v:2616.5-2616.32"
81023   wire \builder_comb_t_array_muxed4
81024   attribute \src "ls180.v:2617.5-2617.32"
81025   wire \builder_comb_t_array_muxed5
81026   attribute \src "ls180.v:1735.5-1735.34"
81027   wire \builder_converter0_next_state
81028   attribute \src "ls180.v:1734.5-1734.29"
81029   wire \builder_converter0_state
81030   attribute \src "ls180.v:1739.5-1739.34"
81031   wire \builder_converter1_next_state
81032   attribute \src "ls180.v:1738.5-1738.29"
81033   wire \builder_converter1_state
81034   attribute \src "ls180.v:1743.5-1743.34"
81035   wire \builder_converter2_next_state
81036   attribute \src "ls180.v:1742.5-1742.29"
81037   wire \builder_converter2_state
81038   attribute \src "ls180.v:1780.5-1780.33"
81039   wire \builder_converter_next_state
81040   attribute \src "ls180.v:1779.5-1779.28"
81041   wire \builder_converter_state
81042   attribute \src "ls180.v:1900.12-1900.25"
81043   wire width 20 \builder_count
81044   attribute \src "ls180.v:2588.13-2588.41"
81045   wire width 14 \builder_csr_interconnect_adr
81046   attribute \src "ls180.v:2591.12-2591.42"
81047   wire width 8 \builder_csr_interconnect_dat_r
81048   attribute \src "ls180.v:2590.12-2590.42"
81049   wire width 8 \builder_csr_interconnect_dat_w
81050   attribute \src "ls180.v:2589.6-2589.33"
81051   wire \builder_csr_interconnect_we
81052   attribute \src "ls180.v:1938.12-1938.42"
81053   wire width 8 \builder_csrbank0_bus_errors0_r
81054   attribute \src "ls180.v:1937.6-1937.37"
81055   wire \builder_csrbank0_bus_errors0_re
81056   attribute \src "ls180.v:1940.12-1940.42"
81057   wire width 8 \builder_csrbank0_bus_errors0_w
81058   attribute \src "ls180.v:1939.6-1939.37"
81059   wire \builder_csrbank0_bus_errors0_we
81060   attribute \src "ls180.v:1934.12-1934.42"
81061   wire width 8 \builder_csrbank0_bus_errors1_r
81062   attribute \src "ls180.v:1933.6-1933.37"
81063   wire \builder_csrbank0_bus_errors1_re
81064   attribute \src "ls180.v:1936.12-1936.42"
81065   wire width 8 \builder_csrbank0_bus_errors1_w
81066   attribute \src "ls180.v:1935.6-1935.37"
81067   wire \builder_csrbank0_bus_errors1_we
81068   attribute \src "ls180.v:1930.12-1930.42"
81069   wire width 8 \builder_csrbank0_bus_errors2_r
81070   attribute \src "ls180.v:1929.6-1929.37"
81071   wire \builder_csrbank0_bus_errors2_re
81072   attribute \src "ls180.v:1932.12-1932.42"
81073   wire width 8 \builder_csrbank0_bus_errors2_w
81074   attribute \src "ls180.v:1931.6-1931.37"
81075   wire \builder_csrbank0_bus_errors2_we
81076   attribute \src "ls180.v:1926.12-1926.42"
81077   wire width 8 \builder_csrbank0_bus_errors3_r
81078   attribute \src "ls180.v:1925.6-1925.37"
81079   wire \builder_csrbank0_bus_errors3_re
81080   attribute \src "ls180.v:1928.12-1928.42"
81081   wire width 8 \builder_csrbank0_bus_errors3_w
81082   attribute \src "ls180.v:1927.6-1927.37"
81083   wire \builder_csrbank0_bus_errors3_we
81084   attribute \src "ls180.v:1906.6-1906.31"
81085   wire \builder_csrbank0_reset0_r
81086   attribute \src "ls180.v:1905.6-1905.32"
81087   wire \builder_csrbank0_reset0_re
81088   attribute \src "ls180.v:1908.6-1908.31"
81089   wire \builder_csrbank0_reset0_w
81090   attribute \src "ls180.v:1907.6-1907.32"
81091   wire \builder_csrbank0_reset0_we
81092   attribute \src "ls180.v:1922.12-1922.39"
81093   wire width 8 \builder_csrbank0_scratch0_r
81094   attribute \src "ls180.v:1921.6-1921.34"
81095   wire \builder_csrbank0_scratch0_re
81096   attribute \src "ls180.v:1924.12-1924.39"
81097   wire width 8 \builder_csrbank0_scratch0_w
81098   attribute \src "ls180.v:1923.6-1923.34"
81099   wire \builder_csrbank0_scratch0_we
81100   attribute \src "ls180.v:1918.12-1918.39"
81101   wire width 8 \builder_csrbank0_scratch1_r
81102   attribute \src "ls180.v:1917.6-1917.34"
81103   wire \builder_csrbank0_scratch1_re
81104   attribute \src "ls180.v:1920.12-1920.39"
81105   wire width 8 \builder_csrbank0_scratch1_w
81106   attribute \src "ls180.v:1919.6-1919.34"
81107   wire \builder_csrbank0_scratch1_we
81108   attribute \src "ls180.v:1914.12-1914.39"
81109   wire width 8 \builder_csrbank0_scratch2_r
81110   attribute \src "ls180.v:1913.6-1913.34"
81111   wire \builder_csrbank0_scratch2_re
81112   attribute \src "ls180.v:1916.12-1916.39"
81113   wire width 8 \builder_csrbank0_scratch2_w
81114   attribute \src "ls180.v:1915.6-1915.34"
81115   wire \builder_csrbank0_scratch2_we
81116   attribute \src "ls180.v:1910.12-1910.39"
81117   wire width 8 \builder_csrbank0_scratch3_r
81118   attribute \src "ls180.v:1909.6-1909.34"
81119   wire \builder_csrbank0_scratch3_re
81120   attribute \src "ls180.v:1912.12-1912.39"
81121   wire width 8 \builder_csrbank0_scratch3_w
81122   attribute \src "ls180.v:1911.6-1911.34"
81123   wire \builder_csrbank0_scratch3_we
81124   attribute \src "ls180.v:1941.6-1941.26"
81125   wire \builder_csrbank0_sel
81126   attribute \src "ls180.v:2412.12-2412.40"
81127   wire width 8 \builder_csrbank10_control0_r
81128   attribute \src "ls180.v:2411.6-2411.35"
81129   wire \builder_csrbank10_control0_re
81130   attribute \src "ls180.v:2414.12-2414.40"
81131   wire width 8 \builder_csrbank10_control0_w
81132   attribute \src "ls180.v:2413.6-2413.35"
81133   wire \builder_csrbank10_control0_we
81134   attribute \src "ls180.v:2408.12-2408.40"
81135   wire width 8 \builder_csrbank10_control1_r
81136   attribute \src "ls180.v:2407.6-2407.35"
81137   wire \builder_csrbank10_control1_re
81138   attribute \src "ls180.v:2410.12-2410.40"
81139   wire width 8 \builder_csrbank10_control1_w
81140   attribute \src "ls180.v:2409.6-2409.35"
81141   wire \builder_csrbank10_control1_we
81142   attribute \src "ls180.v:2428.6-2428.29"
81143   wire \builder_csrbank10_cs0_r
81144   attribute \src "ls180.v:2427.6-2427.30"
81145   wire \builder_csrbank10_cs0_re
81146   attribute \src "ls180.v:2430.6-2430.29"
81147   wire \builder_csrbank10_cs0_w
81148   attribute \src "ls180.v:2429.6-2429.30"
81149   wire \builder_csrbank10_cs0_we
81150   attribute \src "ls180.v:2432.6-2432.35"
81151   wire \builder_csrbank10_loopback0_r
81152   attribute \src "ls180.v:2431.6-2431.36"
81153   wire \builder_csrbank10_loopback0_re
81154   attribute \src "ls180.v:2434.6-2434.35"
81155   wire \builder_csrbank10_loopback0_w
81156   attribute \src "ls180.v:2433.6-2433.36"
81157   wire \builder_csrbank10_loopback0_we
81158   attribute \src "ls180.v:2424.12-2424.36"
81159   wire width 8 \builder_csrbank10_miso_r
81160   attribute \src "ls180.v:2423.6-2423.31"
81161   wire \builder_csrbank10_miso_re
81162   attribute \src "ls180.v:2426.12-2426.36"
81163   wire width 8 \builder_csrbank10_miso_w
81164   attribute \src "ls180.v:2425.6-2425.31"
81165   wire \builder_csrbank10_miso_we
81166   attribute \src "ls180.v:2420.12-2420.37"
81167   wire width 8 \builder_csrbank10_mosi0_r
81168   attribute \src "ls180.v:2419.6-2419.32"
81169   wire \builder_csrbank10_mosi0_re
81170   attribute \src "ls180.v:2422.12-2422.37"
81171   wire width 8 \builder_csrbank10_mosi0_w
81172   attribute \src "ls180.v:2421.6-2421.32"
81173   wire \builder_csrbank10_mosi0_we
81174   attribute \src "ls180.v:2435.6-2435.27"
81175   wire \builder_csrbank10_sel
81176   attribute \src "ls180.v:2416.6-2416.32"
81177   wire \builder_csrbank10_status_r
81178   attribute \src "ls180.v:2415.6-2415.33"
81179   wire \builder_csrbank10_status_re
81180   attribute \src "ls180.v:2418.6-2418.32"
81181   wire \builder_csrbank10_status_w
81182   attribute \src "ls180.v:2417.6-2417.33"
81183   wire \builder_csrbank10_status_we
81184   attribute \src "ls180.v:2473.12-2473.44"
81185   wire width 8 \builder_csrbank11_clk_divider0_r
81186   attribute \src "ls180.v:2472.6-2472.39"
81187   wire \builder_csrbank11_clk_divider0_re
81188   attribute \src "ls180.v:2475.12-2475.44"
81189   wire width 8 \builder_csrbank11_clk_divider0_w
81190   attribute \src "ls180.v:2474.6-2474.39"
81191   wire \builder_csrbank11_clk_divider0_we
81192   attribute \src "ls180.v:2469.12-2469.44"
81193   wire width 8 \builder_csrbank11_clk_divider1_r
81194   attribute \src "ls180.v:2468.6-2468.39"
81195   wire \builder_csrbank11_clk_divider1_re
81196   attribute \src "ls180.v:2471.12-2471.44"
81197   wire width 8 \builder_csrbank11_clk_divider1_w
81198   attribute \src "ls180.v:2470.6-2470.39"
81199   wire \builder_csrbank11_clk_divider1_we
81200   attribute \src "ls180.v:2445.12-2445.40"
81201   wire width 8 \builder_csrbank11_control0_r
81202   attribute \src "ls180.v:2444.6-2444.35"
81203   wire \builder_csrbank11_control0_re
81204   attribute \src "ls180.v:2447.12-2447.40"
81205   wire width 8 \builder_csrbank11_control0_w
81206   attribute \src "ls180.v:2446.6-2446.35"
81207   wire \builder_csrbank11_control0_we
81208   attribute \src "ls180.v:2441.12-2441.40"
81209   wire width 8 \builder_csrbank11_control1_r
81210   attribute \src "ls180.v:2440.6-2440.35"
81211   wire \builder_csrbank11_control1_re
81212   attribute \src "ls180.v:2443.12-2443.40"
81213   wire width 8 \builder_csrbank11_control1_w
81214   attribute \src "ls180.v:2442.6-2442.35"
81215   wire \builder_csrbank11_control1_we
81216   attribute \src "ls180.v:2461.6-2461.29"
81217   wire \builder_csrbank11_cs0_r
81218   attribute \src "ls180.v:2460.6-2460.30"
81219   wire \builder_csrbank11_cs0_re
81220   attribute \src "ls180.v:2463.6-2463.29"
81221   wire \builder_csrbank11_cs0_w
81222   attribute \src "ls180.v:2462.6-2462.30"
81223   wire \builder_csrbank11_cs0_we
81224   attribute \src "ls180.v:2465.6-2465.35"
81225   wire \builder_csrbank11_loopback0_r
81226   attribute \src "ls180.v:2464.6-2464.36"
81227   wire \builder_csrbank11_loopback0_re
81228   attribute \src "ls180.v:2467.6-2467.35"
81229   wire \builder_csrbank11_loopback0_w
81230   attribute \src "ls180.v:2466.6-2466.36"
81231   wire \builder_csrbank11_loopback0_we
81232   attribute \src "ls180.v:2457.12-2457.36"
81233   wire width 8 \builder_csrbank11_miso_r
81234   attribute \src "ls180.v:2456.6-2456.31"
81235   wire \builder_csrbank11_miso_re
81236   attribute \src "ls180.v:2459.12-2459.36"
81237   wire width 8 \builder_csrbank11_miso_w
81238   attribute \src "ls180.v:2458.6-2458.31"
81239   wire \builder_csrbank11_miso_we
81240   attribute \src "ls180.v:2453.12-2453.37"
81241   wire width 8 \builder_csrbank11_mosi0_r
81242   attribute \src "ls180.v:2452.6-2452.32"
81243   wire \builder_csrbank11_mosi0_re
81244   attribute \src "ls180.v:2455.12-2455.37"
81245   wire width 8 \builder_csrbank11_mosi0_w
81246   attribute \src "ls180.v:2454.6-2454.32"
81247   wire \builder_csrbank11_mosi0_we
81248   attribute \src "ls180.v:2476.6-2476.27"
81249   wire \builder_csrbank11_sel
81250   attribute \src "ls180.v:2449.6-2449.32"
81251   wire \builder_csrbank11_status_r
81252   attribute \src "ls180.v:2448.6-2448.33"
81253   wire \builder_csrbank11_status_re
81254   attribute \src "ls180.v:2451.6-2451.32"
81255   wire \builder_csrbank11_status_w
81256   attribute \src "ls180.v:2450.6-2450.33"
81257   wire \builder_csrbank11_status_we
81258   attribute \src "ls180.v:2514.6-2514.29"
81259   wire \builder_csrbank12_en0_r
81260   attribute \src "ls180.v:2513.6-2513.30"
81261   wire \builder_csrbank12_en0_re
81262   attribute \src "ls180.v:2516.6-2516.29"
81263   wire \builder_csrbank12_en0_w
81264   attribute \src "ls180.v:2515.6-2515.30"
81265   wire \builder_csrbank12_en0_we
81266   attribute \src "ls180.v:2538.6-2538.36"
81267   wire \builder_csrbank12_ev_enable0_r
81268   attribute \src "ls180.v:2537.6-2537.37"
81269   wire \builder_csrbank12_ev_enable0_re
81270   attribute \src "ls180.v:2540.6-2540.36"
81271   wire \builder_csrbank12_ev_enable0_w
81272   attribute \src "ls180.v:2539.6-2539.37"
81273   wire \builder_csrbank12_ev_enable0_we
81274   attribute \src "ls180.v:2494.12-2494.37"
81275   wire width 8 \builder_csrbank12_load0_r
81276   attribute \src "ls180.v:2493.6-2493.32"
81277   wire \builder_csrbank12_load0_re
81278   attribute \src "ls180.v:2496.12-2496.37"
81279   wire width 8 \builder_csrbank12_load0_w
81280   attribute \src "ls180.v:2495.6-2495.32"
81281   wire \builder_csrbank12_load0_we
81282   attribute \src "ls180.v:2490.12-2490.37"
81283   wire width 8 \builder_csrbank12_load1_r
81284   attribute \src "ls180.v:2489.6-2489.32"
81285   wire \builder_csrbank12_load1_re
81286   attribute \src "ls180.v:2492.12-2492.37"
81287   wire width 8 \builder_csrbank12_load1_w
81288   attribute \src "ls180.v:2491.6-2491.32"
81289   wire \builder_csrbank12_load1_we
81290   attribute \src "ls180.v:2486.12-2486.37"
81291   wire width 8 \builder_csrbank12_load2_r
81292   attribute \src "ls180.v:2485.6-2485.32"
81293   wire \builder_csrbank12_load2_re
81294   attribute \src "ls180.v:2488.12-2488.37"
81295   wire width 8 \builder_csrbank12_load2_w
81296   attribute \src "ls180.v:2487.6-2487.32"
81297   wire \builder_csrbank12_load2_we
81298   attribute \src "ls180.v:2482.12-2482.37"
81299   wire width 8 \builder_csrbank12_load3_r
81300   attribute \src "ls180.v:2481.6-2481.32"
81301   wire \builder_csrbank12_load3_re
81302   attribute \src "ls180.v:2484.12-2484.37"
81303   wire width 8 \builder_csrbank12_load3_w
81304   attribute \src "ls180.v:2483.6-2483.32"
81305   wire \builder_csrbank12_load3_we
81306   attribute \src "ls180.v:2510.12-2510.39"
81307   wire width 8 \builder_csrbank12_reload0_r
81308   attribute \src "ls180.v:2509.6-2509.34"
81309   wire \builder_csrbank12_reload0_re
81310   attribute \src "ls180.v:2512.12-2512.39"
81311   wire width 8 \builder_csrbank12_reload0_w
81312   attribute \src "ls180.v:2511.6-2511.34"
81313   wire \builder_csrbank12_reload0_we
81314   attribute \src "ls180.v:2506.12-2506.39"
81315   wire width 8 \builder_csrbank12_reload1_r
81316   attribute \src "ls180.v:2505.6-2505.34"
81317   wire \builder_csrbank12_reload1_re
81318   attribute \src "ls180.v:2508.12-2508.39"
81319   wire width 8 \builder_csrbank12_reload1_w
81320   attribute \src "ls180.v:2507.6-2507.34"
81321   wire \builder_csrbank12_reload1_we
81322   attribute \src "ls180.v:2502.12-2502.39"
81323   wire width 8 \builder_csrbank12_reload2_r
81324   attribute \src "ls180.v:2501.6-2501.34"
81325   wire \builder_csrbank12_reload2_re
81326   attribute \src "ls180.v:2504.12-2504.39"
81327   wire width 8 \builder_csrbank12_reload2_w
81328   attribute \src "ls180.v:2503.6-2503.34"
81329   wire \builder_csrbank12_reload2_we
81330   attribute \src "ls180.v:2498.12-2498.39"
81331   wire width 8 \builder_csrbank12_reload3_r
81332   attribute \src "ls180.v:2497.6-2497.34"
81333   wire \builder_csrbank12_reload3_re
81334   attribute \src "ls180.v:2500.12-2500.39"
81335   wire width 8 \builder_csrbank12_reload3_w
81336   attribute \src "ls180.v:2499.6-2499.34"
81337   wire \builder_csrbank12_reload3_we
81338   attribute \src "ls180.v:2541.6-2541.27"
81339   wire \builder_csrbank12_sel
81340   attribute \src "ls180.v:2518.6-2518.39"
81341   wire \builder_csrbank12_update_value0_r
81342   attribute \src "ls180.v:2517.6-2517.40"
81343   wire \builder_csrbank12_update_value0_re
81344   attribute \src "ls180.v:2520.6-2520.39"
81345   wire \builder_csrbank12_update_value0_w
81346   attribute \src "ls180.v:2519.6-2519.40"
81347   wire \builder_csrbank12_update_value0_we
81348   attribute \src "ls180.v:2534.12-2534.38"
81349   wire width 8 \builder_csrbank12_value0_r
81350   attribute \src "ls180.v:2533.6-2533.33"
81351   wire \builder_csrbank12_value0_re
81352   attribute \src "ls180.v:2536.12-2536.38"
81353   wire width 8 \builder_csrbank12_value0_w
81354   attribute \src "ls180.v:2535.6-2535.33"
81355   wire \builder_csrbank12_value0_we
81356   attribute \src "ls180.v:2530.12-2530.38"
81357   wire width 8 \builder_csrbank12_value1_r
81358   attribute \src "ls180.v:2529.6-2529.33"
81359   wire \builder_csrbank12_value1_re
81360   attribute \src "ls180.v:2532.12-2532.38"
81361   wire width 8 \builder_csrbank12_value1_w
81362   attribute \src "ls180.v:2531.6-2531.33"
81363   wire \builder_csrbank12_value1_we
81364   attribute \src "ls180.v:2526.12-2526.38"
81365   wire width 8 \builder_csrbank12_value2_r
81366   attribute \src "ls180.v:2525.6-2525.33"
81367   wire \builder_csrbank12_value2_re
81368   attribute \src "ls180.v:2528.12-2528.38"
81369   wire width 8 \builder_csrbank12_value2_w
81370   attribute \src "ls180.v:2527.6-2527.33"
81371   wire \builder_csrbank12_value2_we
81372   attribute \src "ls180.v:2522.12-2522.38"
81373   wire width 8 \builder_csrbank12_value3_r
81374   attribute \src "ls180.v:2521.6-2521.33"
81375   wire \builder_csrbank12_value3_re
81376   attribute \src "ls180.v:2524.12-2524.38"
81377   wire width 8 \builder_csrbank12_value3_w
81378   attribute \src "ls180.v:2523.6-2523.33"
81379   wire \builder_csrbank12_value3_we
81380   attribute \src "ls180.v:2555.12-2555.42"
81381   wire width 2 \builder_csrbank13_ev_enable0_r
81382   attribute \src "ls180.v:2554.6-2554.37"
81383   wire \builder_csrbank13_ev_enable0_re
81384   attribute \src "ls180.v:2557.12-2557.42"
81385   wire width 2 \builder_csrbank13_ev_enable0_w
81386   attribute \src "ls180.v:2556.6-2556.37"
81387   wire \builder_csrbank13_ev_enable0_we
81388   attribute \src "ls180.v:2551.6-2551.33"
81389   wire \builder_csrbank13_rxempty_r
81390   attribute \src "ls180.v:2550.6-2550.34"
81391   wire \builder_csrbank13_rxempty_re
81392   attribute \src "ls180.v:2553.6-2553.33"
81393   wire \builder_csrbank13_rxempty_w
81394   attribute \src "ls180.v:2552.6-2552.34"
81395   wire \builder_csrbank13_rxempty_we
81396   attribute \src "ls180.v:2563.6-2563.32"
81397   wire \builder_csrbank13_rxfull_r
81398   attribute \src "ls180.v:2562.6-2562.33"
81399   wire \builder_csrbank13_rxfull_re
81400   attribute \src "ls180.v:2565.6-2565.32"
81401   wire \builder_csrbank13_rxfull_w
81402   attribute \src "ls180.v:2564.6-2564.33"
81403   wire \builder_csrbank13_rxfull_we
81404   attribute \src "ls180.v:2566.6-2566.27"
81405   wire \builder_csrbank13_sel
81406   attribute \src "ls180.v:2559.6-2559.33"
81407   wire \builder_csrbank13_txempty_r
81408   attribute \src "ls180.v:2558.6-2558.34"
81409   wire \builder_csrbank13_txempty_re
81410   attribute \src "ls180.v:2561.6-2561.33"
81411   wire \builder_csrbank13_txempty_w
81412   attribute \src "ls180.v:2560.6-2560.34"
81413   wire \builder_csrbank13_txempty_we
81414   attribute \src "ls180.v:2547.6-2547.32"
81415   wire \builder_csrbank13_txfull_r
81416   attribute \src "ls180.v:2546.6-2546.33"
81417   wire \builder_csrbank13_txfull_re
81418   attribute \src "ls180.v:2549.6-2549.32"
81419   wire \builder_csrbank13_txfull_w
81420   attribute \src "ls180.v:2548.6-2548.33"
81421   wire \builder_csrbank13_txfull_we
81422   attribute \src "ls180.v:2587.6-2587.27"
81423   wire \builder_csrbank14_sel
81424   attribute \src "ls180.v:2584.12-2584.44"
81425   wire width 8 \builder_csrbank14_tuning_word0_r
81426   attribute \src "ls180.v:2583.6-2583.39"
81427   wire \builder_csrbank14_tuning_word0_re
81428   attribute \src "ls180.v:2586.12-2586.44"
81429   wire width 8 \builder_csrbank14_tuning_word0_w
81430   attribute \src "ls180.v:2585.6-2585.39"
81431   wire \builder_csrbank14_tuning_word0_we
81432   attribute \src "ls180.v:2580.12-2580.44"
81433   wire width 8 \builder_csrbank14_tuning_word1_r
81434   attribute \src "ls180.v:2579.6-2579.39"
81435   wire \builder_csrbank14_tuning_word1_re
81436   attribute \src "ls180.v:2582.12-2582.44"
81437   wire width 8 \builder_csrbank14_tuning_word1_w
81438   attribute \src "ls180.v:2581.6-2581.39"
81439   wire \builder_csrbank14_tuning_word1_we
81440   attribute \src "ls180.v:2576.12-2576.44"
81441   wire width 8 \builder_csrbank14_tuning_word2_r
81442   attribute \src "ls180.v:2575.6-2575.39"
81443   wire \builder_csrbank14_tuning_word2_re
81444   attribute \src "ls180.v:2578.12-2578.44"
81445   wire width 8 \builder_csrbank14_tuning_word2_w
81446   attribute \src "ls180.v:2577.6-2577.39"
81447   wire \builder_csrbank14_tuning_word2_we
81448   attribute \src "ls180.v:2572.12-2572.44"
81449   wire width 8 \builder_csrbank14_tuning_word3_r
81450   attribute \src "ls180.v:2571.6-2571.39"
81451   wire \builder_csrbank14_tuning_word3_re
81452   attribute \src "ls180.v:2574.12-2574.44"
81453   wire width 8 \builder_csrbank14_tuning_word3_w
81454   attribute \src "ls180.v:2573.6-2573.39"
81455   wire \builder_csrbank14_tuning_word3_we
81456   attribute \src "ls180.v:1959.12-1959.34"
81457   wire width 8 \builder_csrbank1_in0_r
81458   attribute \src "ls180.v:1958.6-1958.29"
81459   wire \builder_csrbank1_in0_re
81460   attribute \src "ls180.v:1961.12-1961.34"
81461   wire width 8 \builder_csrbank1_in0_w
81462   attribute \src "ls180.v:1960.6-1960.29"
81463   wire \builder_csrbank1_in0_we
81464   attribute \src "ls180.v:1955.12-1955.34"
81465   wire width 8 \builder_csrbank1_in1_r
81466   attribute \src "ls180.v:1954.6-1954.29"
81467   wire \builder_csrbank1_in1_re
81468   attribute \src "ls180.v:1957.12-1957.34"
81469   wire width 8 \builder_csrbank1_in1_w
81470   attribute \src "ls180.v:1956.6-1956.29"
81471   wire \builder_csrbank1_in1_we
81472   attribute \src "ls180.v:1951.12-1951.34"
81473   wire width 8 \builder_csrbank1_oe0_r
81474   attribute \src "ls180.v:1950.6-1950.29"
81475   wire \builder_csrbank1_oe0_re
81476   attribute \src "ls180.v:1953.12-1953.34"
81477   wire width 8 \builder_csrbank1_oe0_w
81478   attribute \src "ls180.v:1952.6-1952.29"
81479   wire \builder_csrbank1_oe0_we
81480   attribute \src "ls180.v:1947.12-1947.34"
81481   wire width 8 \builder_csrbank1_oe1_r
81482   attribute \src "ls180.v:1946.6-1946.29"
81483   wire \builder_csrbank1_oe1_re
81484   attribute \src "ls180.v:1949.12-1949.34"
81485   wire width 8 \builder_csrbank1_oe1_w
81486   attribute \src "ls180.v:1948.6-1948.29"
81487   wire \builder_csrbank1_oe1_we
81488   attribute \src "ls180.v:1967.12-1967.35"
81489   wire width 8 \builder_csrbank1_out0_r
81490   attribute \src "ls180.v:1966.6-1966.30"
81491   wire \builder_csrbank1_out0_re
81492   attribute \src "ls180.v:1969.12-1969.35"
81493   wire width 8 \builder_csrbank1_out0_w
81494   attribute \src "ls180.v:1968.6-1968.30"
81495   wire \builder_csrbank1_out0_we
81496   attribute \src "ls180.v:1963.12-1963.35"
81497   wire width 8 \builder_csrbank1_out1_r
81498   attribute \src "ls180.v:1962.6-1962.30"
81499   wire \builder_csrbank1_out1_re
81500   attribute \src "ls180.v:1965.12-1965.35"
81501   wire width 8 \builder_csrbank1_out1_w
81502   attribute \src "ls180.v:1964.6-1964.30"
81503   wire \builder_csrbank1_out1_we
81504   attribute \src "ls180.v:1970.6-1970.26"
81505   wire \builder_csrbank1_sel
81506   attribute \src "ls180.v:1980.6-1980.26"
81507   wire \builder_csrbank2_r_r
81508   attribute \src "ls180.v:1979.6-1979.27"
81509   wire \builder_csrbank2_r_re
81510   attribute \src "ls180.v:1982.6-1982.26"
81511   wire \builder_csrbank2_r_w
81512   attribute \src "ls180.v:1981.6-1981.27"
81513   wire \builder_csrbank2_r_we
81514   attribute \src "ls180.v:1983.6-1983.26"
81515   wire \builder_csrbank2_sel
81516   attribute \src "ls180.v:1976.12-1976.33"
81517   wire width 3 \builder_csrbank2_w0_r
81518   attribute \src "ls180.v:1975.6-1975.28"
81519   wire \builder_csrbank2_w0_re
81520   attribute \src "ls180.v:1978.12-1978.33"
81521   wire width 3 \builder_csrbank2_w0_w
81522   attribute \src "ls180.v:1977.6-1977.28"
81523   wire \builder_csrbank2_w0_we
81524   attribute \src "ls180.v:1989.6-1989.32"
81525   wire \builder_csrbank3_enable0_r
81526   attribute \src "ls180.v:1988.6-1988.33"
81527   wire \builder_csrbank3_enable0_re
81528   attribute \src "ls180.v:1991.6-1991.32"
81529   wire \builder_csrbank3_enable0_w
81530   attribute \src "ls180.v:1990.6-1990.33"
81531   wire \builder_csrbank3_enable0_we
81532   attribute \src "ls180.v:2021.12-2021.38"
81533   wire width 8 \builder_csrbank3_period0_r
81534   attribute \src "ls180.v:2020.6-2020.33"
81535   wire \builder_csrbank3_period0_re
81536   attribute \src "ls180.v:2023.12-2023.38"
81537   wire width 8 \builder_csrbank3_period0_w
81538   attribute \src "ls180.v:2022.6-2022.33"
81539   wire \builder_csrbank3_period0_we
81540   attribute \src "ls180.v:2017.12-2017.38"
81541   wire width 8 \builder_csrbank3_period1_r
81542   attribute \src "ls180.v:2016.6-2016.33"
81543   wire \builder_csrbank3_period1_re
81544   attribute \src "ls180.v:2019.12-2019.38"
81545   wire width 8 \builder_csrbank3_period1_w
81546   attribute \src "ls180.v:2018.6-2018.33"
81547   wire \builder_csrbank3_period1_we
81548   attribute \src "ls180.v:2013.12-2013.38"
81549   wire width 8 \builder_csrbank3_period2_r
81550   attribute \src "ls180.v:2012.6-2012.33"
81551   wire \builder_csrbank3_period2_re
81552   attribute \src "ls180.v:2015.12-2015.38"
81553   wire width 8 \builder_csrbank3_period2_w
81554   attribute \src "ls180.v:2014.6-2014.33"
81555   wire \builder_csrbank3_period2_we
81556   attribute \src "ls180.v:2009.12-2009.38"
81557   wire width 8 \builder_csrbank3_period3_r
81558   attribute \src "ls180.v:2008.6-2008.33"
81559   wire \builder_csrbank3_period3_re
81560   attribute \src "ls180.v:2011.12-2011.38"
81561   wire width 8 \builder_csrbank3_period3_w
81562   attribute \src "ls180.v:2010.6-2010.33"
81563   wire \builder_csrbank3_period3_we
81564   attribute \src "ls180.v:2024.6-2024.26"
81565   wire \builder_csrbank3_sel
81566   attribute \src "ls180.v:2005.12-2005.37"
81567   wire width 8 \builder_csrbank3_width0_r
81568   attribute \src "ls180.v:2004.6-2004.32"
81569   wire \builder_csrbank3_width0_re
81570   attribute \src "ls180.v:2007.12-2007.37"
81571   wire width 8 \builder_csrbank3_width0_w
81572   attribute \src "ls180.v:2006.6-2006.32"
81573   wire \builder_csrbank3_width0_we
81574   attribute \src "ls180.v:2001.12-2001.37"
81575   wire width 8 \builder_csrbank3_width1_r
81576   attribute \src "ls180.v:2000.6-2000.32"
81577   wire \builder_csrbank3_width1_re
81578   attribute \src "ls180.v:2003.12-2003.37"
81579   wire width 8 \builder_csrbank3_width1_w
81580   attribute \src "ls180.v:2002.6-2002.32"
81581   wire \builder_csrbank3_width1_we
81582   attribute \src "ls180.v:1997.12-1997.37"
81583   wire width 8 \builder_csrbank3_width2_r
81584   attribute \src "ls180.v:1996.6-1996.32"
81585   wire \builder_csrbank3_width2_re
81586   attribute \src "ls180.v:1999.12-1999.37"
81587   wire width 8 \builder_csrbank3_width2_w
81588   attribute \src "ls180.v:1998.6-1998.32"
81589   wire \builder_csrbank3_width2_we
81590   attribute \src "ls180.v:1993.12-1993.37"
81591   wire width 8 \builder_csrbank3_width3_r
81592   attribute \src "ls180.v:1992.6-1992.32"
81593   wire \builder_csrbank3_width3_re
81594   attribute \src "ls180.v:1995.12-1995.37"
81595   wire width 8 \builder_csrbank3_width3_w
81596   attribute \src "ls180.v:1994.6-1994.32"
81597   wire \builder_csrbank3_width3_we
81598   attribute \src "ls180.v:2030.6-2030.32"
81599   wire \builder_csrbank4_enable0_r
81600   attribute \src "ls180.v:2029.6-2029.33"
81601   wire \builder_csrbank4_enable0_re
81602   attribute \src "ls180.v:2032.6-2032.32"
81603   wire \builder_csrbank4_enable0_w
81604   attribute \src "ls180.v:2031.6-2031.33"
81605   wire \builder_csrbank4_enable0_we
81606   attribute \src "ls180.v:2062.12-2062.38"
81607   wire width 8 \builder_csrbank4_period0_r
81608   attribute \src "ls180.v:2061.6-2061.33"
81609   wire \builder_csrbank4_period0_re
81610   attribute \src "ls180.v:2064.12-2064.38"
81611   wire width 8 \builder_csrbank4_period0_w
81612   attribute \src "ls180.v:2063.6-2063.33"
81613   wire \builder_csrbank4_period0_we
81614   attribute \src "ls180.v:2058.12-2058.38"
81615   wire width 8 \builder_csrbank4_period1_r
81616   attribute \src "ls180.v:2057.6-2057.33"
81617   wire \builder_csrbank4_period1_re
81618   attribute \src "ls180.v:2060.12-2060.38"
81619   wire width 8 \builder_csrbank4_period1_w
81620   attribute \src "ls180.v:2059.6-2059.33"
81621   wire \builder_csrbank4_period1_we
81622   attribute \src "ls180.v:2054.12-2054.38"
81623   wire width 8 \builder_csrbank4_period2_r
81624   attribute \src "ls180.v:2053.6-2053.33"
81625   wire \builder_csrbank4_period2_re
81626   attribute \src "ls180.v:2056.12-2056.38"
81627   wire width 8 \builder_csrbank4_period2_w
81628   attribute \src "ls180.v:2055.6-2055.33"
81629   wire \builder_csrbank4_period2_we
81630   attribute \src "ls180.v:2050.12-2050.38"
81631   wire width 8 \builder_csrbank4_period3_r
81632   attribute \src "ls180.v:2049.6-2049.33"
81633   wire \builder_csrbank4_period3_re
81634   attribute \src "ls180.v:2052.12-2052.38"
81635   wire width 8 \builder_csrbank4_period3_w
81636   attribute \src "ls180.v:2051.6-2051.33"
81637   wire \builder_csrbank4_period3_we
81638   attribute \src "ls180.v:2065.6-2065.26"
81639   wire \builder_csrbank4_sel
81640   attribute \src "ls180.v:2046.12-2046.37"
81641   wire width 8 \builder_csrbank4_width0_r
81642   attribute \src "ls180.v:2045.6-2045.32"
81643   wire \builder_csrbank4_width0_re
81644   attribute \src "ls180.v:2048.12-2048.37"
81645   wire width 8 \builder_csrbank4_width0_w
81646   attribute \src "ls180.v:2047.6-2047.32"
81647   wire \builder_csrbank4_width0_we
81648   attribute \src "ls180.v:2042.12-2042.37"
81649   wire width 8 \builder_csrbank4_width1_r
81650   attribute \src "ls180.v:2041.6-2041.32"
81651   wire \builder_csrbank4_width1_re
81652   attribute \src "ls180.v:2044.12-2044.37"
81653   wire width 8 \builder_csrbank4_width1_w
81654   attribute \src "ls180.v:2043.6-2043.32"
81655   wire \builder_csrbank4_width1_we
81656   attribute \src "ls180.v:2038.12-2038.37"
81657   wire width 8 \builder_csrbank4_width2_r
81658   attribute \src "ls180.v:2037.6-2037.32"
81659   wire \builder_csrbank4_width2_re
81660   attribute \src "ls180.v:2040.12-2040.37"
81661   wire width 8 \builder_csrbank4_width2_w
81662   attribute \src "ls180.v:2039.6-2039.32"
81663   wire \builder_csrbank4_width2_we
81664   attribute \src "ls180.v:2034.12-2034.37"
81665   wire width 8 \builder_csrbank4_width3_r
81666   attribute \src "ls180.v:2033.6-2033.32"
81667   wire \builder_csrbank4_width3_re
81668   attribute \src "ls180.v:2036.12-2036.37"
81669   wire width 8 \builder_csrbank4_width3_w
81670   attribute \src "ls180.v:2035.6-2035.32"
81671   wire \builder_csrbank4_width3_we
81672   attribute \src "ls180.v:2099.12-2099.40"
81673   wire width 8 \builder_csrbank5_dma_base0_r
81674   attribute \src "ls180.v:2098.6-2098.35"
81675   wire \builder_csrbank5_dma_base0_re
81676   attribute \src "ls180.v:2101.12-2101.40"
81677   wire width 8 \builder_csrbank5_dma_base0_w
81678   attribute \src "ls180.v:2100.6-2100.35"
81679   wire \builder_csrbank5_dma_base0_we
81680   attribute \src "ls180.v:2095.12-2095.40"
81681   wire width 8 \builder_csrbank5_dma_base1_r
81682   attribute \src "ls180.v:2094.6-2094.35"
81683   wire \builder_csrbank5_dma_base1_re
81684   attribute \src "ls180.v:2097.12-2097.40"
81685   wire width 8 \builder_csrbank5_dma_base1_w
81686   attribute \src "ls180.v:2096.6-2096.35"
81687   wire \builder_csrbank5_dma_base1_we
81688   attribute \src "ls180.v:2091.12-2091.40"
81689   wire width 8 \builder_csrbank5_dma_base2_r
81690   attribute \src "ls180.v:2090.6-2090.35"
81691   wire \builder_csrbank5_dma_base2_re
81692   attribute \src "ls180.v:2093.12-2093.40"
81693   wire width 8 \builder_csrbank5_dma_base2_w
81694   attribute \src "ls180.v:2092.6-2092.35"
81695   wire \builder_csrbank5_dma_base2_we
81696   attribute \src "ls180.v:2087.12-2087.40"
81697   wire width 8 \builder_csrbank5_dma_base3_r
81698   attribute \src "ls180.v:2086.6-2086.35"
81699   wire \builder_csrbank5_dma_base3_re
81700   attribute \src "ls180.v:2089.12-2089.40"
81701   wire width 8 \builder_csrbank5_dma_base3_w
81702   attribute \src "ls180.v:2088.6-2088.35"
81703   wire \builder_csrbank5_dma_base3_we
81704   attribute \src "ls180.v:2083.12-2083.40"
81705   wire width 8 \builder_csrbank5_dma_base4_r
81706   attribute \src "ls180.v:2082.6-2082.35"
81707   wire \builder_csrbank5_dma_base4_re
81708   attribute \src "ls180.v:2085.12-2085.40"
81709   wire width 8 \builder_csrbank5_dma_base4_w
81710   attribute \src "ls180.v:2084.6-2084.35"
81711   wire \builder_csrbank5_dma_base4_we
81712   attribute \src "ls180.v:2079.12-2079.40"
81713   wire width 8 \builder_csrbank5_dma_base5_r
81714   attribute \src "ls180.v:2078.6-2078.35"
81715   wire \builder_csrbank5_dma_base5_re
81716   attribute \src "ls180.v:2081.12-2081.40"
81717   wire width 8 \builder_csrbank5_dma_base5_w
81718   attribute \src "ls180.v:2080.6-2080.35"
81719   wire \builder_csrbank5_dma_base5_we
81720   attribute \src "ls180.v:2075.12-2075.40"
81721   wire width 8 \builder_csrbank5_dma_base6_r
81722   attribute \src "ls180.v:2074.6-2074.35"
81723   wire \builder_csrbank5_dma_base6_re
81724   attribute \src "ls180.v:2077.12-2077.40"
81725   wire width 8 \builder_csrbank5_dma_base6_w
81726   attribute \src "ls180.v:2076.6-2076.35"
81727   wire \builder_csrbank5_dma_base6_we
81728   attribute \src "ls180.v:2071.12-2071.40"
81729   wire width 8 \builder_csrbank5_dma_base7_r
81730   attribute \src "ls180.v:2070.6-2070.35"
81731   wire \builder_csrbank5_dma_base7_re
81732   attribute \src "ls180.v:2073.12-2073.40"
81733   wire width 8 \builder_csrbank5_dma_base7_w
81734   attribute \src "ls180.v:2072.6-2072.35"
81735   wire \builder_csrbank5_dma_base7_we
81736   attribute \src "ls180.v:2123.6-2123.33"
81737   wire \builder_csrbank5_dma_done_r
81738   attribute \src "ls180.v:2122.6-2122.34"
81739   wire \builder_csrbank5_dma_done_re
81740   attribute \src "ls180.v:2125.6-2125.33"
81741   wire \builder_csrbank5_dma_done_w
81742   attribute \src "ls180.v:2124.6-2124.34"
81743   wire \builder_csrbank5_dma_done_we
81744   attribute \src "ls180.v:2119.6-2119.36"
81745   wire \builder_csrbank5_dma_enable0_r
81746   attribute \src "ls180.v:2118.6-2118.37"
81747   wire \builder_csrbank5_dma_enable0_re
81748   attribute \src "ls180.v:2121.6-2121.36"
81749   wire \builder_csrbank5_dma_enable0_w
81750   attribute \src "ls180.v:2120.6-2120.37"
81751   wire \builder_csrbank5_dma_enable0_we
81752   attribute \src "ls180.v:2115.12-2115.42"
81753   wire width 8 \builder_csrbank5_dma_length0_r
81754   attribute \src "ls180.v:2114.6-2114.37"
81755   wire \builder_csrbank5_dma_length0_re
81756   attribute \src "ls180.v:2117.12-2117.42"
81757   wire width 8 \builder_csrbank5_dma_length0_w
81758   attribute \src "ls180.v:2116.6-2116.37"
81759   wire \builder_csrbank5_dma_length0_we
81760   attribute \src "ls180.v:2111.12-2111.42"
81761   wire width 8 \builder_csrbank5_dma_length1_r
81762   attribute \src "ls180.v:2110.6-2110.37"
81763   wire \builder_csrbank5_dma_length1_re
81764   attribute \src "ls180.v:2113.12-2113.42"
81765   wire width 8 \builder_csrbank5_dma_length1_w
81766   attribute \src "ls180.v:2112.6-2112.37"
81767   wire \builder_csrbank5_dma_length1_we
81768   attribute \src "ls180.v:2107.12-2107.42"
81769   wire width 8 \builder_csrbank5_dma_length2_r
81770   attribute \src "ls180.v:2106.6-2106.37"
81771   wire \builder_csrbank5_dma_length2_re
81772   attribute \src "ls180.v:2109.12-2109.42"
81773   wire width 8 \builder_csrbank5_dma_length2_w
81774   attribute \src "ls180.v:2108.6-2108.37"
81775   wire \builder_csrbank5_dma_length2_we
81776   attribute \src "ls180.v:2103.12-2103.42"
81777   wire width 8 \builder_csrbank5_dma_length3_r
81778   attribute \src "ls180.v:2102.6-2102.37"
81779   wire \builder_csrbank5_dma_length3_re
81780   attribute \src "ls180.v:2105.12-2105.42"
81781   wire width 8 \builder_csrbank5_dma_length3_w
81782   attribute \src "ls180.v:2104.6-2104.37"
81783   wire \builder_csrbank5_dma_length3_we
81784   attribute \src "ls180.v:2127.6-2127.34"
81785   wire \builder_csrbank5_dma_loop0_r
81786   attribute \src "ls180.v:2126.6-2126.35"
81787   wire \builder_csrbank5_dma_loop0_re
81788   attribute \src "ls180.v:2129.6-2129.34"
81789   wire \builder_csrbank5_dma_loop0_w
81790   attribute \src "ls180.v:2128.6-2128.35"
81791   wire \builder_csrbank5_dma_loop0_we
81792   attribute \src "ls180.v:2130.6-2130.26"
81793   wire \builder_csrbank5_sel
81794   attribute \src "ls180.v:2260.12-2260.43"
81795   wire width 8 \builder_csrbank6_block_count0_r
81796   attribute \src "ls180.v:2259.6-2259.38"
81797   wire \builder_csrbank6_block_count0_re
81798   attribute \src "ls180.v:2262.12-2262.43"
81799   wire width 8 \builder_csrbank6_block_count0_w
81800   attribute \src "ls180.v:2261.6-2261.38"
81801   wire \builder_csrbank6_block_count0_we
81802   attribute \src "ls180.v:2256.12-2256.43"
81803   wire width 8 \builder_csrbank6_block_count1_r
81804   attribute \src "ls180.v:2255.6-2255.38"
81805   wire \builder_csrbank6_block_count1_re
81806   attribute \src "ls180.v:2258.12-2258.43"
81807   wire width 8 \builder_csrbank6_block_count1_w
81808   attribute \src "ls180.v:2257.6-2257.38"
81809   wire \builder_csrbank6_block_count1_we
81810   attribute \src "ls180.v:2252.12-2252.43"
81811   wire width 8 \builder_csrbank6_block_count2_r
81812   attribute \src "ls180.v:2251.6-2251.38"
81813   wire \builder_csrbank6_block_count2_re
81814   attribute \src "ls180.v:2254.12-2254.43"
81815   wire width 8 \builder_csrbank6_block_count2_w
81816   attribute \src "ls180.v:2253.6-2253.38"
81817   wire \builder_csrbank6_block_count2_we
81818   attribute \src "ls180.v:2248.12-2248.43"
81819   wire width 8 \builder_csrbank6_block_count3_r
81820   attribute \src "ls180.v:2247.6-2247.38"
81821   wire \builder_csrbank6_block_count3_re
81822   attribute \src "ls180.v:2250.12-2250.43"
81823   wire width 8 \builder_csrbank6_block_count3_w
81824   attribute \src "ls180.v:2249.6-2249.38"
81825   wire \builder_csrbank6_block_count3_we
81826   attribute \src "ls180.v:2244.12-2244.44"
81827   wire width 8 \builder_csrbank6_block_length0_r
81828   attribute \src "ls180.v:2243.6-2243.39"
81829   wire \builder_csrbank6_block_length0_re
81830   attribute \src "ls180.v:2246.12-2246.44"
81831   wire width 8 \builder_csrbank6_block_length0_w
81832   attribute \src "ls180.v:2245.6-2245.39"
81833   wire \builder_csrbank6_block_length0_we
81834   attribute \src "ls180.v:2240.12-2240.44"
81835   wire width 2 \builder_csrbank6_block_length1_r
81836   attribute \src "ls180.v:2239.6-2239.39"
81837   wire \builder_csrbank6_block_length1_re
81838   attribute \src "ls180.v:2242.12-2242.44"
81839   wire width 2 \builder_csrbank6_block_length1_w
81840   attribute \src "ls180.v:2241.6-2241.39"
81841   wire \builder_csrbank6_block_length1_we
81842   attribute \src "ls180.v:2148.12-2148.44"
81843   wire width 8 \builder_csrbank6_cmd_argument0_r
81844   attribute \src "ls180.v:2147.6-2147.39"
81845   wire \builder_csrbank6_cmd_argument0_re
81846   attribute \src "ls180.v:2150.12-2150.44"
81847   wire width 8 \builder_csrbank6_cmd_argument0_w
81848   attribute \src "ls180.v:2149.6-2149.39"
81849   wire \builder_csrbank6_cmd_argument0_we
81850   attribute \src "ls180.v:2144.12-2144.44"
81851   wire width 8 \builder_csrbank6_cmd_argument1_r
81852   attribute \src "ls180.v:2143.6-2143.39"
81853   wire \builder_csrbank6_cmd_argument1_re
81854   attribute \src "ls180.v:2146.12-2146.44"
81855   wire width 8 \builder_csrbank6_cmd_argument1_w
81856   attribute \src "ls180.v:2145.6-2145.39"
81857   wire \builder_csrbank6_cmd_argument1_we
81858   attribute \src "ls180.v:2140.12-2140.44"
81859   wire width 8 \builder_csrbank6_cmd_argument2_r
81860   attribute \src "ls180.v:2139.6-2139.39"
81861   wire \builder_csrbank6_cmd_argument2_re
81862   attribute \src "ls180.v:2142.12-2142.44"
81863   wire width 8 \builder_csrbank6_cmd_argument2_w
81864   attribute \src "ls180.v:2141.6-2141.39"
81865   wire \builder_csrbank6_cmd_argument2_we
81866   attribute \src "ls180.v:2136.12-2136.44"
81867   wire width 8 \builder_csrbank6_cmd_argument3_r
81868   attribute \src "ls180.v:2135.6-2135.39"
81869   wire \builder_csrbank6_cmd_argument3_re
81870   attribute \src "ls180.v:2138.12-2138.44"
81871   wire width 8 \builder_csrbank6_cmd_argument3_w
81872   attribute \src "ls180.v:2137.6-2137.39"
81873   wire \builder_csrbank6_cmd_argument3_we
81874   attribute \src "ls180.v:2164.12-2164.43"
81875   wire width 8 \builder_csrbank6_cmd_command0_r
81876   attribute \src "ls180.v:2163.6-2163.38"
81877   wire \builder_csrbank6_cmd_command0_re
81878   attribute \src "ls180.v:2166.12-2166.43"
81879   wire width 8 \builder_csrbank6_cmd_command0_w
81880   attribute \src "ls180.v:2165.6-2165.38"
81881   wire \builder_csrbank6_cmd_command0_we
81882   attribute \src "ls180.v:2160.12-2160.43"
81883   wire width 8 \builder_csrbank6_cmd_command1_r
81884   attribute \src "ls180.v:2159.6-2159.38"
81885   wire \builder_csrbank6_cmd_command1_re
81886   attribute \src "ls180.v:2162.12-2162.43"
81887   wire width 8 \builder_csrbank6_cmd_command1_w
81888   attribute \src "ls180.v:2161.6-2161.38"
81889   wire \builder_csrbank6_cmd_command1_we
81890   attribute \src "ls180.v:2156.12-2156.43"
81891   wire width 8 \builder_csrbank6_cmd_command2_r
81892   attribute \src "ls180.v:2155.6-2155.38"
81893   wire \builder_csrbank6_cmd_command2_re
81894   attribute \src "ls180.v:2158.12-2158.43"
81895   wire width 8 \builder_csrbank6_cmd_command2_w
81896   attribute \src "ls180.v:2157.6-2157.38"
81897   wire \builder_csrbank6_cmd_command2_we
81898   attribute \src "ls180.v:2152.12-2152.43"
81899   wire width 8 \builder_csrbank6_cmd_command3_r
81900   attribute \src "ls180.v:2151.6-2151.38"
81901   wire \builder_csrbank6_cmd_command3_re
81902   attribute \src "ls180.v:2154.12-2154.43"
81903   wire width 8 \builder_csrbank6_cmd_command3_w
81904   attribute \src "ls180.v:2153.6-2153.38"
81905   wire \builder_csrbank6_cmd_command3_we
81906   attribute \src "ls180.v:2232.12-2232.40"
81907   wire width 4 \builder_csrbank6_cmd_event_r
81908   attribute \src "ls180.v:2231.6-2231.35"
81909   wire \builder_csrbank6_cmd_event_re
81910   attribute \src "ls180.v:2234.12-2234.40"
81911   wire width 4 \builder_csrbank6_cmd_event_w
81912   attribute \src "ls180.v:2233.6-2233.35"
81913   wire \builder_csrbank6_cmd_event_we
81914   attribute \src "ls180.v:2228.12-2228.44"
81915   wire width 8 \builder_csrbank6_cmd_response0_r
81916   attribute \src "ls180.v:2227.6-2227.39"
81917   wire \builder_csrbank6_cmd_response0_re
81918   attribute \src "ls180.v:2230.12-2230.44"
81919   wire width 8 \builder_csrbank6_cmd_response0_w
81920   attribute \src "ls180.v:2229.6-2229.39"
81921   wire \builder_csrbank6_cmd_response0_we
81922   attribute \src "ls180.v:2188.12-2188.45"
81923   wire width 8 \builder_csrbank6_cmd_response10_r
81924   attribute \src "ls180.v:2187.6-2187.40"
81925   wire \builder_csrbank6_cmd_response10_re
81926   attribute \src "ls180.v:2190.12-2190.45"
81927   wire width 8 \builder_csrbank6_cmd_response10_w
81928   attribute \src "ls180.v:2189.6-2189.40"
81929   wire \builder_csrbank6_cmd_response10_we
81930   attribute \src "ls180.v:2184.12-2184.45"
81931   wire width 8 \builder_csrbank6_cmd_response11_r
81932   attribute \src "ls180.v:2183.6-2183.40"
81933   wire \builder_csrbank6_cmd_response11_re
81934   attribute \src "ls180.v:2186.12-2186.45"
81935   wire width 8 \builder_csrbank6_cmd_response11_w
81936   attribute \src "ls180.v:2185.6-2185.40"
81937   wire \builder_csrbank6_cmd_response11_we
81938   attribute \src "ls180.v:2180.12-2180.45"
81939   wire width 8 \builder_csrbank6_cmd_response12_r
81940   attribute \src "ls180.v:2179.6-2179.40"
81941   wire \builder_csrbank6_cmd_response12_re
81942   attribute \src "ls180.v:2182.12-2182.45"
81943   wire width 8 \builder_csrbank6_cmd_response12_w
81944   attribute \src "ls180.v:2181.6-2181.40"
81945   wire \builder_csrbank6_cmd_response12_we
81946   attribute \src "ls180.v:2176.12-2176.45"
81947   wire width 8 \builder_csrbank6_cmd_response13_r
81948   attribute \src "ls180.v:2175.6-2175.40"
81949   wire \builder_csrbank6_cmd_response13_re
81950   attribute \src "ls180.v:2178.12-2178.45"
81951   wire width 8 \builder_csrbank6_cmd_response13_w
81952   attribute \src "ls180.v:2177.6-2177.40"
81953   wire \builder_csrbank6_cmd_response13_we
81954   attribute \src "ls180.v:2172.12-2172.45"
81955   wire width 8 \builder_csrbank6_cmd_response14_r
81956   attribute \src "ls180.v:2171.6-2171.40"
81957   wire \builder_csrbank6_cmd_response14_re
81958   attribute \src "ls180.v:2174.12-2174.45"
81959   wire width 8 \builder_csrbank6_cmd_response14_w
81960   attribute \src "ls180.v:2173.6-2173.40"
81961   wire \builder_csrbank6_cmd_response14_we
81962   attribute \src "ls180.v:2168.12-2168.45"
81963   wire width 8 \builder_csrbank6_cmd_response15_r
81964   attribute \src "ls180.v:2167.6-2167.40"
81965   wire \builder_csrbank6_cmd_response15_re
81966   attribute \src "ls180.v:2170.12-2170.45"
81967   wire width 8 \builder_csrbank6_cmd_response15_w
81968   attribute \src "ls180.v:2169.6-2169.40"
81969   wire \builder_csrbank6_cmd_response15_we
81970   attribute \src "ls180.v:2224.12-2224.44"
81971   wire width 8 \builder_csrbank6_cmd_response1_r
81972   attribute \src "ls180.v:2223.6-2223.39"
81973   wire \builder_csrbank6_cmd_response1_re
81974   attribute \src "ls180.v:2226.12-2226.44"
81975   wire width 8 \builder_csrbank6_cmd_response1_w
81976   attribute \src "ls180.v:2225.6-2225.39"
81977   wire \builder_csrbank6_cmd_response1_we
81978   attribute \src "ls180.v:2220.12-2220.44"
81979   wire width 8 \builder_csrbank6_cmd_response2_r
81980   attribute \src "ls180.v:2219.6-2219.39"
81981   wire \builder_csrbank6_cmd_response2_re
81982   attribute \src "ls180.v:2222.12-2222.44"
81983   wire width 8 \builder_csrbank6_cmd_response2_w
81984   attribute \src "ls180.v:2221.6-2221.39"
81985   wire \builder_csrbank6_cmd_response2_we
81986   attribute \src "ls180.v:2216.12-2216.44"
81987   wire width 8 \builder_csrbank6_cmd_response3_r
81988   attribute \src "ls180.v:2215.6-2215.39"
81989   wire \builder_csrbank6_cmd_response3_re
81990   attribute \src "ls180.v:2218.12-2218.44"
81991   wire width 8 \builder_csrbank6_cmd_response3_w
81992   attribute \src "ls180.v:2217.6-2217.39"
81993   wire \builder_csrbank6_cmd_response3_we
81994   attribute \src "ls180.v:2212.12-2212.44"
81995   wire width 8 \builder_csrbank6_cmd_response4_r
81996   attribute \src "ls180.v:2211.6-2211.39"
81997   wire \builder_csrbank6_cmd_response4_re
81998   attribute \src "ls180.v:2214.12-2214.44"
81999   wire width 8 \builder_csrbank6_cmd_response4_w
82000   attribute \src "ls180.v:2213.6-2213.39"
82001   wire \builder_csrbank6_cmd_response4_we
82002   attribute \src "ls180.v:2208.12-2208.44"
82003   wire width 8 \builder_csrbank6_cmd_response5_r
82004   attribute \src "ls180.v:2207.6-2207.39"
82005   wire \builder_csrbank6_cmd_response5_re
82006   attribute \src "ls180.v:2210.12-2210.44"
82007   wire width 8 \builder_csrbank6_cmd_response5_w
82008   attribute \src "ls180.v:2209.6-2209.39"
82009   wire \builder_csrbank6_cmd_response5_we
82010   attribute \src "ls180.v:2204.12-2204.44"
82011   wire width 8 \builder_csrbank6_cmd_response6_r
82012   attribute \src "ls180.v:2203.6-2203.39"
82013   wire \builder_csrbank6_cmd_response6_re
82014   attribute \src "ls180.v:2206.12-2206.44"
82015   wire width 8 \builder_csrbank6_cmd_response6_w
82016   attribute \src "ls180.v:2205.6-2205.39"
82017   wire \builder_csrbank6_cmd_response6_we
82018   attribute \src "ls180.v:2200.12-2200.44"
82019   wire width 8 \builder_csrbank6_cmd_response7_r
82020   attribute \src "ls180.v:2199.6-2199.39"
82021   wire \builder_csrbank6_cmd_response7_re
82022   attribute \src "ls180.v:2202.12-2202.44"
82023   wire width 8 \builder_csrbank6_cmd_response7_w
82024   attribute \src "ls180.v:2201.6-2201.39"
82025   wire \builder_csrbank6_cmd_response7_we
82026   attribute \src "ls180.v:2196.12-2196.44"
82027   wire width 8 \builder_csrbank6_cmd_response8_r
82028   attribute \src "ls180.v:2195.6-2195.39"
82029   wire \builder_csrbank6_cmd_response8_re
82030   attribute \src "ls180.v:2198.12-2198.44"
82031   wire width 8 \builder_csrbank6_cmd_response8_w
82032   attribute \src "ls180.v:2197.6-2197.39"
82033   wire \builder_csrbank6_cmd_response8_we
82034   attribute \src "ls180.v:2192.12-2192.44"
82035   wire width 8 \builder_csrbank6_cmd_response9_r
82036   attribute \src "ls180.v:2191.6-2191.39"
82037   wire \builder_csrbank6_cmd_response9_re
82038   attribute \src "ls180.v:2194.12-2194.44"
82039   wire width 8 \builder_csrbank6_cmd_response9_w
82040   attribute \src "ls180.v:2193.6-2193.39"
82041   wire \builder_csrbank6_cmd_response9_we
82042   attribute \src "ls180.v:2236.12-2236.41"
82043   wire width 4 \builder_csrbank6_data_event_r
82044   attribute \src "ls180.v:2235.6-2235.36"
82045   wire \builder_csrbank6_data_event_re
82046   attribute \src "ls180.v:2238.12-2238.41"
82047   wire width 4 \builder_csrbank6_data_event_w
82048   attribute \src "ls180.v:2237.6-2237.36"
82049   wire \builder_csrbank6_data_event_we
82050   attribute \src "ls180.v:2263.6-2263.26"
82051   wire \builder_csrbank6_sel
82052   attribute \src "ls180.v:2297.12-2297.40"
82053   wire width 8 \builder_csrbank7_dma_base0_r
82054   attribute \src "ls180.v:2296.6-2296.35"
82055   wire \builder_csrbank7_dma_base0_re
82056   attribute \src "ls180.v:2299.12-2299.40"
82057   wire width 8 \builder_csrbank7_dma_base0_w
82058   attribute \src "ls180.v:2298.6-2298.35"
82059   wire \builder_csrbank7_dma_base0_we
82060   attribute \src "ls180.v:2293.12-2293.40"
82061   wire width 8 \builder_csrbank7_dma_base1_r
82062   attribute \src "ls180.v:2292.6-2292.35"
82063   wire \builder_csrbank7_dma_base1_re
82064   attribute \src "ls180.v:2295.12-2295.40"
82065   wire width 8 \builder_csrbank7_dma_base1_w
82066   attribute \src "ls180.v:2294.6-2294.35"
82067   wire \builder_csrbank7_dma_base1_we
82068   attribute \src "ls180.v:2289.12-2289.40"
82069   wire width 8 \builder_csrbank7_dma_base2_r
82070   attribute \src "ls180.v:2288.6-2288.35"
82071   wire \builder_csrbank7_dma_base2_re
82072   attribute \src "ls180.v:2291.12-2291.40"
82073   wire width 8 \builder_csrbank7_dma_base2_w
82074   attribute \src "ls180.v:2290.6-2290.35"
82075   wire \builder_csrbank7_dma_base2_we
82076   attribute \src "ls180.v:2285.12-2285.40"
82077   wire width 8 \builder_csrbank7_dma_base3_r
82078   attribute \src "ls180.v:2284.6-2284.35"
82079   wire \builder_csrbank7_dma_base3_re
82080   attribute \src "ls180.v:2287.12-2287.40"
82081   wire width 8 \builder_csrbank7_dma_base3_w
82082   attribute \src "ls180.v:2286.6-2286.35"
82083   wire \builder_csrbank7_dma_base3_we
82084   attribute \src "ls180.v:2281.12-2281.40"
82085   wire width 8 \builder_csrbank7_dma_base4_r
82086   attribute \src "ls180.v:2280.6-2280.35"
82087   wire \builder_csrbank7_dma_base4_re
82088   attribute \src "ls180.v:2283.12-2283.40"
82089   wire width 8 \builder_csrbank7_dma_base4_w
82090   attribute \src "ls180.v:2282.6-2282.35"
82091   wire \builder_csrbank7_dma_base4_we
82092   attribute \src "ls180.v:2277.12-2277.40"
82093   wire width 8 \builder_csrbank7_dma_base5_r
82094   attribute \src "ls180.v:2276.6-2276.35"
82095   wire \builder_csrbank7_dma_base5_re
82096   attribute \src "ls180.v:2279.12-2279.40"
82097   wire width 8 \builder_csrbank7_dma_base5_w
82098   attribute \src "ls180.v:2278.6-2278.35"
82099   wire \builder_csrbank7_dma_base5_we
82100   attribute \src "ls180.v:2273.12-2273.40"
82101   wire width 8 \builder_csrbank7_dma_base6_r
82102   attribute \src "ls180.v:2272.6-2272.35"
82103   wire \builder_csrbank7_dma_base6_re
82104   attribute \src "ls180.v:2275.12-2275.40"
82105   wire width 8 \builder_csrbank7_dma_base6_w
82106   attribute \src "ls180.v:2274.6-2274.35"
82107   wire \builder_csrbank7_dma_base6_we
82108   attribute \src "ls180.v:2269.12-2269.40"
82109   wire width 8 \builder_csrbank7_dma_base7_r
82110   attribute \src "ls180.v:2268.6-2268.35"
82111   wire \builder_csrbank7_dma_base7_re
82112   attribute \src "ls180.v:2271.12-2271.40"
82113   wire width 8 \builder_csrbank7_dma_base7_w
82114   attribute \src "ls180.v:2270.6-2270.35"
82115   wire \builder_csrbank7_dma_base7_we
82116   attribute \src "ls180.v:2321.6-2321.33"
82117   wire \builder_csrbank7_dma_done_r
82118   attribute \src "ls180.v:2320.6-2320.34"
82119   wire \builder_csrbank7_dma_done_re
82120   attribute \src "ls180.v:2323.6-2323.33"
82121   wire \builder_csrbank7_dma_done_w
82122   attribute \src "ls180.v:2322.6-2322.34"
82123   wire \builder_csrbank7_dma_done_we
82124   attribute \src "ls180.v:2317.6-2317.36"
82125   wire \builder_csrbank7_dma_enable0_r
82126   attribute \src "ls180.v:2316.6-2316.37"
82127   wire \builder_csrbank7_dma_enable0_re
82128   attribute \src "ls180.v:2319.6-2319.36"
82129   wire \builder_csrbank7_dma_enable0_w
82130   attribute \src "ls180.v:2318.6-2318.37"
82131   wire \builder_csrbank7_dma_enable0_we
82132   attribute \src "ls180.v:2313.12-2313.42"
82133   wire width 8 \builder_csrbank7_dma_length0_r
82134   attribute \src "ls180.v:2312.6-2312.37"
82135   wire \builder_csrbank7_dma_length0_re
82136   attribute \src "ls180.v:2315.12-2315.42"
82137   wire width 8 \builder_csrbank7_dma_length0_w
82138   attribute \src "ls180.v:2314.6-2314.37"
82139   wire \builder_csrbank7_dma_length0_we
82140   attribute \src "ls180.v:2309.12-2309.42"
82141   wire width 8 \builder_csrbank7_dma_length1_r
82142   attribute \src "ls180.v:2308.6-2308.37"
82143   wire \builder_csrbank7_dma_length1_re
82144   attribute \src "ls180.v:2311.12-2311.42"
82145   wire width 8 \builder_csrbank7_dma_length1_w
82146   attribute \src "ls180.v:2310.6-2310.37"
82147   wire \builder_csrbank7_dma_length1_we
82148   attribute \src "ls180.v:2305.12-2305.42"
82149   wire width 8 \builder_csrbank7_dma_length2_r
82150   attribute \src "ls180.v:2304.6-2304.37"
82151   wire \builder_csrbank7_dma_length2_re
82152   attribute \src "ls180.v:2307.12-2307.42"
82153   wire width 8 \builder_csrbank7_dma_length2_w
82154   attribute \src "ls180.v:2306.6-2306.37"
82155   wire \builder_csrbank7_dma_length2_we
82156   attribute \src "ls180.v:2301.12-2301.42"
82157   wire width 8 \builder_csrbank7_dma_length3_r
82158   attribute \src "ls180.v:2300.6-2300.37"
82159   wire \builder_csrbank7_dma_length3_re
82160   attribute \src "ls180.v:2303.12-2303.42"
82161   wire width 8 \builder_csrbank7_dma_length3_w
82162   attribute \src "ls180.v:2302.6-2302.37"
82163   wire \builder_csrbank7_dma_length3_we
82164   attribute \src "ls180.v:2325.6-2325.34"
82165   wire \builder_csrbank7_dma_loop0_r
82166   attribute \src "ls180.v:2324.6-2324.35"
82167   wire \builder_csrbank7_dma_loop0_re
82168   attribute \src "ls180.v:2327.6-2327.34"
82169   wire \builder_csrbank7_dma_loop0_w
82170   attribute \src "ls180.v:2326.6-2326.35"
82171   wire \builder_csrbank7_dma_loop0_we
82172   attribute \src "ls180.v:2341.12-2341.42"
82173   wire width 8 \builder_csrbank7_dma_offset0_r
82174   attribute \src "ls180.v:2340.6-2340.37"
82175   wire \builder_csrbank7_dma_offset0_re
82176   attribute \src "ls180.v:2343.12-2343.42"
82177   wire width 8 \builder_csrbank7_dma_offset0_w
82178   attribute \src "ls180.v:2342.6-2342.37"
82179   wire \builder_csrbank7_dma_offset0_we
82180   attribute \src "ls180.v:2337.12-2337.42"
82181   wire width 8 \builder_csrbank7_dma_offset1_r
82182   attribute \src "ls180.v:2336.6-2336.37"
82183   wire \builder_csrbank7_dma_offset1_re
82184   attribute \src "ls180.v:2339.12-2339.42"
82185   wire width 8 \builder_csrbank7_dma_offset1_w
82186   attribute \src "ls180.v:2338.6-2338.37"
82187   wire \builder_csrbank7_dma_offset1_we
82188   attribute \src "ls180.v:2333.12-2333.42"
82189   wire width 8 \builder_csrbank7_dma_offset2_r
82190   attribute \src "ls180.v:2332.6-2332.37"
82191   wire \builder_csrbank7_dma_offset2_re
82192   attribute \src "ls180.v:2335.12-2335.42"
82193   wire width 8 \builder_csrbank7_dma_offset2_w
82194   attribute \src "ls180.v:2334.6-2334.37"
82195   wire \builder_csrbank7_dma_offset2_we
82196   attribute \src "ls180.v:2329.12-2329.42"
82197   wire width 8 \builder_csrbank7_dma_offset3_r
82198   attribute \src "ls180.v:2328.6-2328.37"
82199   wire \builder_csrbank7_dma_offset3_re
82200   attribute \src "ls180.v:2331.12-2331.42"
82201   wire width 8 \builder_csrbank7_dma_offset3_w
82202   attribute \src "ls180.v:2330.6-2330.37"
82203   wire \builder_csrbank7_dma_offset3_we
82204   attribute \src "ls180.v:2344.6-2344.26"
82205   wire \builder_csrbank7_sel
82206   attribute \src "ls180.v:2350.6-2350.36"
82207   wire \builder_csrbank8_card_detect_r
82208   attribute \src "ls180.v:2349.6-2349.37"
82209   wire \builder_csrbank8_card_detect_re
82210   attribute \src "ls180.v:2352.6-2352.36"
82211   wire \builder_csrbank8_card_detect_w
82212   attribute \src "ls180.v:2351.6-2351.37"
82213   wire \builder_csrbank8_card_detect_we
82214   attribute \src "ls180.v:2358.12-2358.47"
82215   wire width 8 \builder_csrbank8_clocker_divider0_r
82216   attribute \src "ls180.v:2357.6-2357.42"
82217   wire \builder_csrbank8_clocker_divider0_re
82218   attribute \src "ls180.v:2360.12-2360.47"
82219   wire width 8 \builder_csrbank8_clocker_divider0_w
82220   attribute \src "ls180.v:2359.6-2359.42"
82221   wire \builder_csrbank8_clocker_divider0_we
82222   attribute \src "ls180.v:2354.6-2354.41"
82223   wire \builder_csrbank8_clocker_divider1_r
82224   attribute \src "ls180.v:2353.6-2353.42"
82225   wire \builder_csrbank8_clocker_divider1_re
82226   attribute \src "ls180.v:2356.6-2356.41"
82227   wire \builder_csrbank8_clocker_divider1_w
82228   attribute \src "ls180.v:2355.6-2355.42"
82229   wire \builder_csrbank8_clocker_divider1_we
82230   attribute \src "ls180.v:2361.6-2361.26"
82231   wire \builder_csrbank8_sel
82232   attribute \src "ls180.v:2367.12-2367.44"
82233   wire width 4 \builder_csrbank9_dfii_control0_r
82234   attribute \src "ls180.v:2366.6-2366.39"
82235   wire \builder_csrbank9_dfii_control0_re
82236   attribute \src "ls180.v:2369.12-2369.44"
82237   wire width 4 \builder_csrbank9_dfii_control0_w
82238   attribute \src "ls180.v:2368.6-2368.39"
82239   wire \builder_csrbank9_dfii_control0_we
82240   attribute \src "ls180.v:2379.12-2379.48"
82241   wire width 8 \builder_csrbank9_dfii_pi0_address0_r
82242   attribute \src "ls180.v:2378.6-2378.43"
82243   wire \builder_csrbank9_dfii_pi0_address0_re
82244   attribute \src "ls180.v:2381.12-2381.48"
82245   wire width 8 \builder_csrbank9_dfii_pi0_address0_w
82246   attribute \src "ls180.v:2380.6-2380.43"
82247   wire \builder_csrbank9_dfii_pi0_address0_we
82248   attribute \src "ls180.v:2375.12-2375.48"
82249   wire width 5 \builder_csrbank9_dfii_pi0_address1_r
82250   attribute \src "ls180.v:2374.6-2374.43"
82251   wire \builder_csrbank9_dfii_pi0_address1_re
82252   attribute \src "ls180.v:2377.12-2377.48"
82253   wire width 5 \builder_csrbank9_dfii_pi0_address1_w
82254   attribute \src "ls180.v:2376.6-2376.43"
82255   wire \builder_csrbank9_dfii_pi0_address1_we
82256   attribute \src "ls180.v:2383.12-2383.49"
82257   wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r
82258   attribute \src "ls180.v:2382.6-2382.44"
82259   wire \builder_csrbank9_dfii_pi0_baddress0_re
82260   attribute \src "ls180.v:2385.12-2385.49"
82261   wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w
82262   attribute \src "ls180.v:2384.6-2384.44"
82263   wire \builder_csrbank9_dfii_pi0_baddress0_we
82264   attribute \src "ls180.v:2371.12-2371.48"
82265   wire width 6 \builder_csrbank9_dfii_pi0_command0_r
82266   attribute \src "ls180.v:2370.6-2370.43"
82267   wire \builder_csrbank9_dfii_pi0_command0_re
82268   attribute \src "ls180.v:2373.12-2373.48"
82269   wire width 6 \builder_csrbank9_dfii_pi0_command0_w
82270   attribute \src "ls180.v:2372.6-2372.43"
82271   wire \builder_csrbank9_dfii_pi0_command0_we
82272   attribute \src "ls180.v:2399.12-2399.47"
82273   wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r
82274   attribute \src "ls180.v:2398.6-2398.42"
82275   wire \builder_csrbank9_dfii_pi0_rddata0_re
82276   attribute \src "ls180.v:2401.12-2401.47"
82277   wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w
82278   attribute \src "ls180.v:2400.6-2400.42"
82279   wire \builder_csrbank9_dfii_pi0_rddata0_we
82280   attribute \src "ls180.v:2395.12-2395.47"
82281   wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r
82282   attribute \src "ls180.v:2394.6-2394.42"
82283   wire \builder_csrbank9_dfii_pi0_rddata1_re
82284   attribute \src "ls180.v:2397.12-2397.47"
82285   wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w
82286   attribute \src "ls180.v:2396.6-2396.42"
82287   wire \builder_csrbank9_dfii_pi0_rddata1_we
82288   attribute \src "ls180.v:2391.12-2391.47"
82289   wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r
82290   attribute \src "ls180.v:2390.6-2390.42"
82291   wire \builder_csrbank9_dfii_pi0_wrdata0_re
82292   attribute \src "ls180.v:2393.12-2393.47"
82293   wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w
82294   attribute \src "ls180.v:2392.6-2392.42"
82295   wire \builder_csrbank9_dfii_pi0_wrdata0_we
82296   attribute \src "ls180.v:2387.12-2387.47"
82297   wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r
82298   attribute \src "ls180.v:2386.6-2386.42"
82299   wire \builder_csrbank9_dfii_pi0_wrdata1_re
82300   attribute \src "ls180.v:2389.12-2389.47"
82301   wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w
82302   attribute \src "ls180.v:2388.6-2388.42"
82303   wire \builder_csrbank9_dfii_pi0_wrdata1_we
82304   attribute \src "ls180.v:2402.6-2402.26"
82305   wire \builder_csrbank9_sel
82306   attribute \src "ls180.v:1899.6-1899.18"
82307   wire \builder_done
82308   attribute \src "ls180.v:1897.5-1897.18"
82309   wire \builder_error
82310   attribute \src "ls180.v:1894.11-1894.24"
82311   wire width 3 \builder_grant
82312   attribute \src "ls180.v:1901.13-1901.44"
82313   wire width 14 \builder_interface0_bank_bus_adr
82314   attribute \src "ls180.v:1904.11-1904.44"
82315   wire width 8 \builder_interface0_bank_bus_dat_r
82316   attribute \src "ls180.v:1903.12-1903.45"
82317   wire width 8 \builder_interface0_bank_bus_dat_w
82318   attribute \src "ls180.v:1902.6-1902.36"
82319   wire \builder_interface0_bank_bus_we
82320   attribute \src "ls180.v:2403.13-2403.45"
82321   wire width 14 \builder_interface10_bank_bus_adr
82322   attribute \src "ls180.v:2406.11-2406.45"
82323   wire width 8 \builder_interface10_bank_bus_dat_r
82324   attribute \src "ls180.v:2405.12-2405.46"
82325   wire width 8 \builder_interface10_bank_bus_dat_w
82326   attribute \src "ls180.v:2404.6-2404.37"
82327   wire \builder_interface10_bank_bus_we
82328   attribute \src "ls180.v:2436.13-2436.45"
82329   wire width 14 \builder_interface11_bank_bus_adr
82330   attribute \src "ls180.v:2439.11-2439.45"
82331   wire width 8 \builder_interface11_bank_bus_dat_r
82332   attribute \src "ls180.v:2438.12-2438.46"
82333   wire width 8 \builder_interface11_bank_bus_dat_w
82334   attribute \src "ls180.v:2437.6-2437.37"
82335   wire \builder_interface11_bank_bus_we
82336   attribute \src "ls180.v:2477.13-2477.45"
82337   wire width 14 \builder_interface12_bank_bus_adr
82338   attribute \src "ls180.v:2480.11-2480.45"
82339   wire width 8 \builder_interface12_bank_bus_dat_r
82340   attribute \src "ls180.v:2479.12-2479.46"
82341   wire width 8 \builder_interface12_bank_bus_dat_w
82342   attribute \src "ls180.v:2478.6-2478.37"
82343   wire \builder_interface12_bank_bus_we
82344   attribute \src "ls180.v:2542.13-2542.45"
82345   wire width 14 \builder_interface13_bank_bus_adr
82346   attribute \src "ls180.v:2545.11-2545.45"
82347   wire width 8 \builder_interface13_bank_bus_dat_r
82348   attribute \src "ls180.v:2544.12-2544.46"
82349   wire width 8 \builder_interface13_bank_bus_dat_w
82350   attribute \src "ls180.v:2543.6-2543.37"
82351   wire \builder_interface13_bank_bus_we
82352   attribute \src "ls180.v:2567.13-2567.45"
82353   wire width 14 \builder_interface14_bank_bus_adr
82354   attribute \src "ls180.v:2570.11-2570.45"
82355   wire width 8 \builder_interface14_bank_bus_dat_r
82356   attribute \src "ls180.v:2569.12-2569.46"
82357   wire width 8 \builder_interface14_bank_bus_dat_w
82358   attribute \src "ls180.v:2568.6-2568.37"
82359   wire \builder_interface14_bank_bus_we
82360   attribute \src "ls180.v:1942.13-1942.44"
82361   wire width 14 \builder_interface1_bank_bus_adr
82362   attribute \src "ls180.v:1945.11-1945.44"
82363   wire width 8 \builder_interface1_bank_bus_dat_r
82364   attribute \src "ls180.v:1944.12-1944.45"
82365   wire width 8 \builder_interface1_bank_bus_dat_w
82366   attribute \src "ls180.v:1943.6-1943.36"
82367   wire \builder_interface1_bank_bus_we
82368   attribute \src "ls180.v:1971.13-1971.44"
82369   wire width 14 \builder_interface2_bank_bus_adr
82370   attribute \src "ls180.v:1974.11-1974.44"
82371   wire width 8 \builder_interface2_bank_bus_dat_r
82372   attribute \src "ls180.v:1973.12-1973.45"
82373   wire width 8 \builder_interface2_bank_bus_dat_w
82374   attribute \src "ls180.v:1972.6-1972.36"
82375   wire \builder_interface2_bank_bus_we
82376   attribute \src "ls180.v:1984.13-1984.44"
82377   wire width 14 \builder_interface3_bank_bus_adr
82378   attribute \src "ls180.v:1987.11-1987.44"
82379   wire width 8 \builder_interface3_bank_bus_dat_r
82380   attribute \src "ls180.v:1986.12-1986.45"
82381   wire width 8 \builder_interface3_bank_bus_dat_w
82382   attribute \src "ls180.v:1985.6-1985.36"
82383   wire \builder_interface3_bank_bus_we
82384   attribute \src "ls180.v:2025.13-2025.44"
82385   wire width 14 \builder_interface4_bank_bus_adr
82386   attribute \src "ls180.v:2028.11-2028.44"
82387   wire width 8 \builder_interface4_bank_bus_dat_r
82388   attribute \src "ls180.v:2027.12-2027.45"
82389   wire width 8 \builder_interface4_bank_bus_dat_w
82390   attribute \src "ls180.v:2026.6-2026.36"
82391   wire \builder_interface4_bank_bus_we
82392   attribute \src "ls180.v:2066.13-2066.44"
82393   wire width 14 \builder_interface5_bank_bus_adr
82394   attribute \src "ls180.v:2069.11-2069.44"
82395   wire width 8 \builder_interface5_bank_bus_dat_r
82396   attribute \src "ls180.v:2068.12-2068.45"
82397   wire width 8 \builder_interface5_bank_bus_dat_w
82398   attribute \src "ls180.v:2067.6-2067.36"
82399   wire \builder_interface5_bank_bus_we
82400   attribute \src "ls180.v:2131.13-2131.44"
82401   wire width 14 \builder_interface6_bank_bus_adr
82402   attribute \src "ls180.v:2134.11-2134.44"
82403   wire width 8 \builder_interface6_bank_bus_dat_r
82404   attribute \src "ls180.v:2133.12-2133.45"
82405   wire width 8 \builder_interface6_bank_bus_dat_w
82406   attribute \src "ls180.v:2132.6-2132.36"
82407   wire \builder_interface6_bank_bus_we
82408   attribute \src "ls180.v:2264.13-2264.44"
82409   wire width 14 \builder_interface7_bank_bus_adr
82410   attribute \src "ls180.v:2267.11-2267.44"
82411   wire width 8 \builder_interface7_bank_bus_dat_r
82412   attribute \src "ls180.v:2266.12-2266.45"
82413   wire width 8 \builder_interface7_bank_bus_dat_w
82414   attribute \src "ls180.v:2265.6-2265.36"
82415   wire \builder_interface7_bank_bus_we
82416   attribute \src "ls180.v:2345.13-2345.44"
82417   wire width 14 \builder_interface8_bank_bus_adr
82418   attribute \src "ls180.v:2348.11-2348.44"
82419   wire width 8 \builder_interface8_bank_bus_dat_r
82420   attribute \src "ls180.v:2347.12-2347.45"
82421   wire width 8 \builder_interface8_bank_bus_dat_w
82422   attribute \src "ls180.v:2346.6-2346.36"
82423   wire \builder_interface8_bank_bus_we
82424   attribute \src "ls180.v:2362.13-2362.44"
82425   wire width 14 \builder_interface9_bank_bus_adr
82426   attribute \src "ls180.v:2365.11-2365.44"
82427   wire width 8 \builder_interface9_bank_bus_dat_r
82428   attribute \src "ls180.v:2364.12-2364.45"
82429   wire width 8 \builder_interface9_bank_bus_dat_w
82430   attribute \src "ls180.v:2363.6-2363.36"
82431   wire \builder_interface9_bank_bus_we
82432   attribute \src "ls180.v:1867.12-1867.35"
82433   wire width 14 \builder_libresocsim_adr
82434   attribute \src "ls180.v:2596.12-2596.47"
82435   wire width 14 \builder_libresocsim_adr_next_value1
82436   attribute \src "ls180.v:2597.5-2597.43"
82437   wire \builder_libresocsim_adr_next_value_ce1
82438   attribute \src "ls180.v:1870.12-1870.37"
82439   wire width 8 \builder_libresocsim_dat_r
82440   attribute \src "ls180.v:1869.11-1869.36"
82441   wire width 8 \builder_libresocsim_dat_w
82442   attribute \src "ls180.v:2594.11-2594.48"
82443   wire width 8 \builder_libresocsim_dat_w_next_value0
82444   attribute \src "ls180.v:2595.5-2595.45"
82445   wire \builder_libresocsim_dat_w_next_value_ce0
82446   attribute \src "ls180.v:1868.5-1868.27"
82447   wire \builder_libresocsim_we
82448   attribute \src "ls180.v:2598.5-2598.39"
82449   wire \builder_libresocsim_we_next_value2
82450   attribute \src "ls180.v:2599.5-2599.42"
82451   wire \builder_libresocsim_we_next_value_ce2
82452   attribute \src "ls180.v:1877.5-1877.37"
82453   wire \builder_libresocsim_wishbone_ack
82454   attribute \src "ls180.v:1871.13-1871.45"
82455   wire width 30 \builder_libresocsim_wishbone_adr
82456   attribute \src "ls180.v:1880.12-1880.44"
82457   wire width 2 \builder_libresocsim_wishbone_bte
82458   attribute \src "ls180.v:1879.12-1879.44"
82459   wire width 3 \builder_libresocsim_wishbone_cti
82460   attribute \src "ls180.v:1875.6-1875.38"
82461   wire \builder_libresocsim_wishbone_cyc
82462   attribute \src "ls180.v:1873.12-1873.46"
82463   wire width 32 \builder_libresocsim_wishbone_dat_r
82464   attribute \src "ls180.v:1872.13-1872.47"
82465   wire width 32 \builder_libresocsim_wishbone_dat_w
82466   attribute \src "ls180.v:1881.5-1881.37"
82467   wire \builder_libresocsim_wishbone_err
82468   attribute \src "ls180.v:1874.12-1874.44"
82469   wire width 4 \builder_libresocsim_wishbone_sel
82470   attribute \src "ls180.v:1876.6-1876.38"
82471   wire \builder_libresocsim_wishbone_stb
82472   attribute \src "ls180.v:1878.6-1878.37"
82473   wire \builder_libresocsim_wishbone_we
82474   attribute \src "ls180.v:1770.5-1770.20"
82475   wire \builder_locked0
82476   attribute \src "ls180.v:1771.5-1771.20"
82477   wire \builder_locked1
82478   attribute \src "ls180.v:1772.5-1772.20"
82479   wire \builder_locked2
82480   attribute \src "ls180.v:1773.5-1773.20"
82481   wire \builder_locked3
82482   attribute \src "ls180.v:1757.11-1757.41"
82483   wire width 3 \builder_multiplexer_next_state
82484   attribute \src "ls180.v:1756.11-1756.36"
82485   wire width 3 \builder_multiplexer_state
82486   attribute \no_retiming "true"
82487   attribute \src "ls180.v:2703.32-2703.59"
82488   wire \builder_multiregimpl0_regs0
82489   attribute \no_retiming "true"
82490   attribute \src "ls180.v:2704.32-2704.59"
82491   wire \builder_multiregimpl0_regs1
82492   attribute \no_retiming "true"
82493   attribute \src "ls180.v:2723.32-2723.60"
82494   wire \builder_multiregimpl10_regs0
82495   attribute \no_retiming "true"
82496   attribute \src "ls180.v:2724.32-2724.60"
82497   wire \builder_multiregimpl10_regs1
82498   attribute \no_retiming "true"
82499   attribute \src "ls180.v:2725.32-2725.60"
82500   wire \builder_multiregimpl11_regs0
82501   attribute \no_retiming "true"
82502   attribute \src "ls180.v:2726.32-2726.60"
82503   wire \builder_multiregimpl11_regs1
82504   attribute \no_retiming "true"
82505   attribute \src "ls180.v:2727.32-2727.60"
82506   wire \builder_multiregimpl12_regs0
82507   attribute \no_retiming "true"
82508   attribute \src "ls180.v:2728.32-2728.60"
82509   wire \builder_multiregimpl12_regs1
82510   attribute \no_retiming "true"
82511   attribute \src "ls180.v:2729.32-2729.60"
82512   wire \builder_multiregimpl13_regs0
82513   attribute \no_retiming "true"
82514   attribute \src "ls180.v:2730.32-2730.60"
82515   wire \builder_multiregimpl13_regs1
82516   attribute \no_retiming "true"
82517   attribute \src "ls180.v:2731.32-2731.60"
82518   wire \builder_multiregimpl14_regs0
82519   attribute \no_retiming "true"
82520   attribute \src "ls180.v:2732.32-2732.60"
82521   wire \builder_multiregimpl14_regs1
82522   attribute \no_retiming "true"
82523   attribute \src "ls180.v:2733.32-2733.60"
82524   wire \builder_multiregimpl15_regs0
82525   attribute \no_retiming "true"
82526   attribute \src "ls180.v:2734.32-2734.60"
82527   wire \builder_multiregimpl15_regs1
82528   attribute \no_retiming "true"
82529   attribute \src "ls180.v:2735.32-2735.60"
82530   wire \builder_multiregimpl16_regs0
82531   attribute \no_retiming "true"
82532   attribute \src "ls180.v:2736.32-2736.60"
82533   wire \builder_multiregimpl16_regs1
82534   attribute \no_retiming "true"
82535   attribute \src "ls180.v:2705.32-2705.59"
82536   wire \builder_multiregimpl1_regs0
82537   attribute \no_retiming "true"
82538   attribute \src "ls180.v:2706.32-2706.59"
82539   wire \builder_multiregimpl1_regs1
82540   attribute \no_retiming "true"
82541   attribute \src "ls180.v:2707.32-2707.59"
82542   wire \builder_multiregimpl2_regs0
82543   attribute \no_retiming "true"
82544   attribute \src "ls180.v:2708.32-2708.59"
82545   wire \builder_multiregimpl2_regs1
82546   attribute \no_retiming "true"
82547   attribute \src "ls180.v:2709.32-2709.59"
82548   wire \builder_multiregimpl3_regs0
82549   attribute \no_retiming "true"
82550   attribute \src "ls180.v:2710.32-2710.59"
82551   wire \builder_multiregimpl3_regs1
82552   attribute \no_retiming "true"
82553   attribute \src "ls180.v:2711.32-2711.59"
82554   wire \builder_multiregimpl4_regs0
82555   attribute \no_retiming "true"
82556   attribute \src "ls180.v:2712.32-2712.59"
82557   wire \builder_multiregimpl4_regs1
82558   attribute \no_retiming "true"
82559   attribute \src "ls180.v:2713.32-2713.59"
82560   wire \builder_multiregimpl5_regs0
82561   attribute \no_retiming "true"
82562   attribute \src "ls180.v:2714.32-2714.59"
82563   wire \builder_multiregimpl5_regs1
82564   attribute \no_retiming "true"
82565   attribute \src "ls180.v:2715.32-2715.59"
82566   wire \builder_multiregimpl6_regs0
82567   attribute \no_retiming "true"
82568   attribute \src "ls180.v:2716.32-2716.59"
82569   wire \builder_multiregimpl6_regs1
82570   attribute \no_retiming "true"
82571   attribute \src "ls180.v:2717.32-2717.59"
82572   wire \builder_multiregimpl7_regs0
82573   attribute \no_retiming "true"
82574   attribute \src "ls180.v:2718.32-2718.59"
82575   wire \builder_multiregimpl7_regs1
82576   attribute \no_retiming "true"
82577   attribute \src "ls180.v:2719.32-2719.59"
82578   wire \builder_multiregimpl8_regs0
82579   attribute \no_retiming "true"
82580   attribute \src "ls180.v:2720.32-2720.59"
82581   wire \builder_multiregimpl8_regs1
82582   attribute \no_retiming "true"
82583   attribute \src "ls180.v:2721.32-2721.59"
82584   wire \builder_multiregimpl9_regs0
82585   attribute \no_retiming "true"
82586   attribute \src "ls180.v:2722.32-2722.59"
82587   wire \builder_multiregimpl9_regs1
82588   attribute \src "ls180.v:1775.5-1775.36"
82589   wire \builder_new_master_rdata_valid0
82590   attribute \src "ls180.v:1776.5-1776.36"
82591   wire \builder_new_master_rdata_valid1
82592   attribute \src "ls180.v:1777.5-1777.36"
82593   wire \builder_new_master_rdata_valid2
82594   attribute \src "ls180.v:1778.5-1778.36"
82595   wire \builder_new_master_rdata_valid3
82596   attribute \src "ls180.v:1774.5-1774.35"
82597   wire \builder_new_master_wdata_ready
82598   attribute \src "ls180.v:2593.11-2593.29"
82599   wire width 2 \builder_next_state
82600   attribute \src "ls180.v:1747.11-1747.39"
82601   wire width 2 \builder_refresher_next_state
82602   attribute \src "ls180.v:1746.11-1746.34"
82603   wire width 2 \builder_refresher_state
82604   attribute \src "ls180.v:1893.12-1893.27"
82605   wire width 5 \builder_request
82606   attribute \src "ls180.v:1760.6-1760.28"
82607   wire \builder_roundrobin0_ce
82608   attribute \src "ls180.v:1759.6-1759.31"
82609   wire \builder_roundrobin0_grant
82610   attribute \src "ls180.v:1758.6-1758.33"
82611   wire \builder_roundrobin0_request
82612   attribute \src "ls180.v:1763.6-1763.28"
82613   wire \builder_roundrobin1_ce
82614   attribute \src "ls180.v:1762.6-1762.31"
82615   wire \builder_roundrobin1_grant
82616   attribute \src "ls180.v:1761.6-1761.33"
82617   wire \builder_roundrobin1_request
82618   attribute \src "ls180.v:1766.6-1766.28"
82619   wire \builder_roundrobin2_ce
82620   attribute \src "ls180.v:1765.6-1765.31"
82621   wire \builder_roundrobin2_grant
82622   attribute \src "ls180.v:1764.6-1764.33"
82623   wire \builder_roundrobin2_request
82624   attribute \src "ls180.v:1769.6-1769.28"
82625   wire \builder_roundrobin3_ce
82626   attribute \src "ls180.v:1768.6-1768.31"
82627   wire \builder_roundrobin3_grant
82628   attribute \src "ls180.v:1767.6-1767.33"
82629   wire \builder_roundrobin3_request
82630   attribute \src "ls180.v:1856.11-1856.44"
82631   wire width 2 \builder_sdblock2memdma_next_state
82632   attribute \src "ls180.v:1855.11-1855.39"
82633   wire width 2 \builder_sdblock2memdma_state
82634   attribute \src "ls180.v:1824.5-1824.50"
82635   wire \builder_sdcore_crcupstreaminserter_next_state
82636   attribute \src "ls180.v:1823.5-1823.45"
82637   wire \builder_sdcore_crcupstreaminserter_state
82638   attribute \src "ls180.v:1836.11-1836.40"
82639   wire width 3 \builder_sdcore_fsm_next_state
82640   attribute \src "ls180.v:1835.11-1835.35"
82641   wire width 3 \builder_sdcore_fsm_state
82642   attribute \src "ls180.v:1860.5-1860.42"
82643   wire \builder_sdmem2blockdma_fsm_next_state
82644   attribute \src "ls180.v:1859.5-1859.37"
82645   wire \builder_sdmem2blockdma_fsm_state
82646   attribute \src "ls180.v:1864.11-1864.58"
82647   wire width 2 \builder_sdmem2blockdma_resetinserter_next_state
82648   attribute \src "ls180.v:1863.11-1863.53"
82649   wire width 2 \builder_sdmem2blockdma_resetinserter_state
82650   attribute \src "ls180.v:1812.11-1812.39"
82651   wire width 3 \builder_sdphy_fsm_next_state
82652   attribute \src "ls180.v:1811.11-1811.34"
82653   wire width 3 \builder_sdphy_fsm_state
82654   attribute \src "ls180.v:1800.11-1800.45"
82655   wire width 3 \builder_sdphy_sdphycmdr_next_state
82656   attribute \src "ls180.v:1799.11-1799.40"
82657   wire width 3 \builder_sdphy_sdphycmdr_state
82658   attribute \src "ls180.v:1796.11-1796.45"
82659   wire width 2 \builder_sdphy_sdphycmdw_next_state
82660   attribute \src "ls180.v:1795.11-1795.40"
82661   wire width 2 \builder_sdphy_sdphycmdw_state
82662   attribute \src "ls180.v:1808.5-1808.39"
82663   wire \builder_sdphy_sdphycrcr_next_state
82664   attribute \src "ls180.v:1807.5-1807.34"
82665   wire \builder_sdphy_sdphycrcr_state
82666   attribute \src "ls180.v:1816.11-1816.46"
82667   wire width 3 \builder_sdphy_sdphydatar_next_state
82668   attribute \src "ls180.v:1815.11-1815.41"
82669   wire width 3 \builder_sdphy_sdphydatar_state
82670   attribute \src "ls180.v:1792.5-1792.39"
82671   wire \builder_sdphy_sdphyinit_next_state
82672   attribute \src "ls180.v:1791.5-1791.34"
82673   wire \builder_sdphy_sdphyinit_state
82674   attribute \src "ls180.v:1888.5-1888.23"
82675   wire \builder_shared_ack
82676   attribute \src "ls180.v:1882.13-1882.31"
82677   wire width 30 \builder_shared_adr
82678   attribute \src "ls180.v:1891.12-1891.30"
82679   wire width 2 \builder_shared_bte
82680   attribute \src "ls180.v:1890.12-1890.30"
82681   wire width 3 \builder_shared_cti
82682   attribute \src "ls180.v:1886.6-1886.24"
82683   wire \builder_shared_cyc
82684   attribute \src "ls180.v:1884.12-1884.32"
82685   wire width 32 \builder_shared_dat_r
82686   attribute \src "ls180.v:1883.13-1883.33"
82687   wire width 32 \builder_shared_dat_w
82688   attribute \src "ls180.v:1892.6-1892.24"
82689   wire \builder_shared_err
82690   attribute \src "ls180.v:1885.12-1885.30"
82691   wire width 4 \builder_shared_sel
82692   attribute \src "ls180.v:1887.6-1887.24"
82693   wire \builder_shared_stb
82694   attribute \src "ls180.v:1889.6-1889.23"
82695   wire \builder_shared_we
82696   attribute \src "ls180.v:1895.11-1895.28"
82697   wire width 5 \builder_slave_sel
82698   attribute \src "ls180.v:1896.11-1896.30"
82699   wire width 5 \builder_slave_sel_r
82700   attribute \src "ls180.v:1784.11-1784.40"
82701   wire width 2 \builder_spimaster0_next_state
82702   attribute \src "ls180.v:1783.11-1783.35"
82703   wire width 2 \builder_spimaster0_state
82704   attribute \src "ls180.v:1788.11-1788.40"
82705   wire width 2 \builder_spimaster1_next_state
82706   attribute \src "ls180.v:1787.11-1787.35"
82707   wire width 2 \builder_spimaster1_state
82708   attribute \src "ls180.v:2592.11-2592.24"
82709   wire width 2 \builder_state
82710   attribute \src "ls180.v:2645.5-2645.32"
82711   wire \builder_sync_f_array_muxed0
82712   attribute \src "ls180.v:2646.5-2646.32"
82713   wire \builder_sync_f_array_muxed1
82714   attribute \src "ls180.v:2638.11-2638.40"
82715   wire width 2 \builder_sync_rhs_array_muxed0
82716   attribute \src "ls180.v:2639.12-2639.41"
82717   wire width 13 \builder_sync_rhs_array_muxed1
82718   attribute \src "ls180.v:2640.5-2640.34"
82719   wire \builder_sync_rhs_array_muxed2
82720   attribute \src "ls180.v:2641.5-2641.34"
82721   wire \builder_sync_rhs_array_muxed3
82722   attribute \src "ls180.v:2642.5-2642.34"
82723   wire \builder_sync_rhs_array_muxed4
82724   attribute \src "ls180.v:2643.5-2643.34"
82725   wire \builder_sync_rhs_array_muxed5
82726   attribute \src "ls180.v:2644.5-2644.34"
82727   wire \builder_sync_rhs_array_muxed6
82728   attribute \src "ls180.v:1898.6-1898.18"
82729   wire \builder_wait
82730   attribute \src "ls180.v:21.20-21.24"
82731   wire width 3 output 17 \eint
82732   attribute \src "ls180.v:140.11-140.17"
82733   wire width 3 \eint_1
82734   attribute \src "ls180.v:5.21-5.27"
82735   wire width 16 output 1 \gpio_i
82736   attribute \src "ls180.v:6.21-6.27"
82737   wire width 16 output 2 \gpio_o
82738   attribute \src "ls180.v:7.21-7.28"
82739   wire width 16 output 3 \gpio_oe
82740   attribute \src "ls180.v:39.14-39.21"
82741   wire output 35 \i2c_scl
82742   attribute \src "ls180.v:40.14-40.23"
82743   wire output 36 \i2c_sda_i
82744   attribute \src "ls180.v:41.14-41.23"
82745   wire output 37 \i2c_sda_o
82746   attribute \src "ls180.v:42.14-42.24"
82747   wire output 38 \i2c_sda_oe
82748   attribute \src "ls180.v:49.13-49.21"
82749   wire input 45 \jtag_tck
82750   attribute \src "ls180.v:50.13-50.21"
82751   wire input 46 \jtag_tdi
82752   attribute \src "ls180.v:51.14-51.22"
82753   wire output 47 \jtag_tdo
82754   attribute \src "ls180.v:48.13-48.21"
82755   wire input 44 \jtag_tms
82756   attribute \src "ls180.v:838.6-838.18"
82757   wire \main_ack_cmd
82758   attribute \src "ls180.v:840.6-840.20"
82759   wire \main_ack_rdata
82760   attribute \src "ls180.v:839.6-839.20"
82761   wire \main_ack_wdata
82762   attribute \src "ls180.v:836.5-836.22"
82763   wire \main_cmd_consumed
82764   attribute \src "ls180.v:833.5-833.27"
82765   wire \main_converter_counter
82766   attribute \src "ls180.v:1781.5-1781.48"
82767   wire \main_converter_counter_converter_next_value
82768   attribute \src "ls180.v:1782.5-1782.51"
82769   wire \main_converter_counter_converter_next_value_ce
82770   attribute \src "ls180.v:835.12-835.32"
82771   wire width 32 \main_converter_dat_r
82772   attribute \src "ls180.v:834.6-834.26"
82773   wire \main_converter_reset
82774   attribute \src "ls180.v:832.5-832.24"
82775   wire \main_converter_skip
82776   attribute \src "ls180.v:262.6-262.23"
82777   wire \main_dfi_p0_act_n
82778   attribute \src "ls180.v:253.13-253.32"
82779   wire width 13 \main_dfi_p0_address
82780   attribute \src "ls180.v:254.12-254.28"
82781   wire width 2 \main_dfi_p0_bank
82782   attribute \src "ls180.v:255.6-255.23"
82783   wire \main_dfi_p0_cas_n
82784   attribute \src "ls180.v:259.6-259.21"
82785   wire \main_dfi_p0_cke
82786   attribute \src "ls180.v:256.6-256.22"
82787   wire \main_dfi_p0_cs_n
82788   attribute \src "ls180.v:260.6-260.21"
82789   wire \main_dfi_p0_odt
82790   attribute \src "ls180.v:257.6-257.23"
82791   wire \main_dfi_p0_ras_n
82792   attribute \src "ls180.v:267.12-267.30"
82793   wire width 16 \main_dfi_p0_rddata
82794   attribute \src "ls180.v:266.6-266.27"
82795   wire \main_dfi_p0_rddata_en
82796   attribute \src "ls180.v:268.5-268.29"
82797   wire \main_dfi_p0_rddata_valid
82798   attribute \src "ls180.v:261.6-261.25"
82799   wire \main_dfi_p0_reset_n
82800   attribute \src "ls180.v:258.6-258.22"
82801   wire \main_dfi_p0_we_n
82802   attribute \src "ls180.v:263.13-263.31"
82803   wire width 16 \main_dfi_p0_wrdata
82804   attribute \src "ls180.v:264.6-264.27"
82805   wire \main_dfi_p0_wrdata_en
82806   attribute \src "ls180.v:265.12-265.35"
82807   wire width 2 \main_dfi_p0_wrdata_mask
82808   attribute \src "ls180.v:1067.12-1067.22"
82809   wire width 36 \main_dummy
82810   attribute \src "ls180.v:984.5-984.20"
82811   wire \main_gpio_oe_re
82812   attribute \src "ls180.v:983.12-983.32"
82813   wire width 16 \main_gpio_oe_storage
82814   attribute \src "ls180.v:988.5-988.21"
82815   wire \main_gpio_out_re
82816   attribute \src "ls180.v:987.12-987.33"
82817   wire width 16 \main_gpio_out_storage
82818   attribute \src "ls180.v:989.13-989.29"
82819   wire width 16 \main_gpio_pads_i
82820   attribute \src "ls180.v:990.13-990.29"
82821   wire width 16 \main_gpio_pads_o
82822   attribute \src "ls180.v:991.13-991.30"
82823   wire width 16 \main_gpio_pads_oe
82824   attribute \src "ls180.v:985.12-985.28"
82825   wire width 16 \main_gpio_status
82826   attribute \src "ls180.v:986.6-986.18"
82827   wire \main_gpio_we
82828   attribute \src "ls180.v:1089.6-1089.17"
82829   wire \main_i2c_oe
82830   attribute \src "ls180.v:1092.5-1092.16"
82831   wire \main_i2c_re
82832   attribute \src "ls180.v:1088.6-1088.18"
82833   wire \main_i2c_scl
82834   attribute \src "ls180.v:1090.6-1090.19"
82835   wire \main_i2c_sda0
82836   attribute \src "ls180.v:1093.6-1093.19"
82837   wire \main_i2c_sda1
82838   attribute \src "ls180.v:1094.6-1094.21"
82839   wire \main_i2c_status
82840   attribute \src "ls180.v:1091.11-1091.27"
82841   wire width 3 \main_i2c_storage
82842   attribute \src "ls180.v:1095.6-1095.17"
82843   wire \main_i2c_we
82844   attribute \src "ls180.v:252.5-252.17"
82845   wire \main_int_rst
82846   attribute \src "ls180.v:1555.6-1555.29"
82847   wire \main_interface0_bus_ack
82848   attribute \src "ls180.v:1549.13-1549.36"
82849   wire width 32 \main_interface0_bus_adr
82850   attribute \src "ls180.v:1558.11-1558.34"
82851   wire width 2 \main_interface0_bus_bte
82852   attribute \src "ls180.v:1557.11-1557.34"
82853   wire width 3 \main_interface0_bus_cti
82854   attribute \src "ls180.v:1553.6-1553.29"
82855   wire \main_interface0_bus_cyc
82856   attribute \src "ls180.v:1551.13-1551.38"
82857   wire width 32 \main_interface0_bus_dat_r
82858   attribute \src "ls180.v:1550.13-1550.38"
82859   wire width 32 \main_interface0_bus_dat_w
82860   attribute \src "ls180.v:1559.6-1559.29"
82861   wire \main_interface0_bus_err
82862   attribute \src "ls180.v:1552.12-1552.35"
82863   wire width 4 \main_interface0_bus_sel
82864   attribute \src "ls180.v:1554.6-1554.29"
82865   wire \main_interface0_bus_stb
82866   attribute \src "ls180.v:1556.6-1556.28"
82867   wire \main_interface0_bus_we
82868   attribute \src "ls180.v:1646.6-1646.29"
82869   wire \main_interface1_bus_ack
82870   attribute \src "ls180.v:1640.12-1640.35"
82871   wire width 32 \main_interface1_bus_adr
82872   attribute \src "ls180.v:1649.11-1649.34"
82873   wire width 2 \main_interface1_bus_bte
82874   attribute \src "ls180.v:1648.11-1648.34"
82875   wire width 3 \main_interface1_bus_cti
82876   attribute \src "ls180.v:1644.5-1644.28"
82877   wire \main_interface1_bus_cyc
82878   attribute \src "ls180.v:1642.13-1642.38"
82879   wire width 32 \main_interface1_bus_dat_r
82880   attribute \src "ls180.v:1641.12-1641.37"
82881   wire width 32 \main_interface1_bus_dat_w
82882   attribute \src "ls180.v:1650.6-1650.29"
82883   wire \main_interface1_bus_err
82884   attribute \src "ls180.v:1643.11-1643.34"
82885   wire width 4 \main_interface1_bus_sel
82886   attribute \src "ls180.v:1645.5-1645.28"
82887   wire \main_interface1_bus_stb
82888   attribute \src "ls180.v:1647.5-1647.27"
82889   wire \main_interface1_bus_we
82890   attribute \src "ls180.v:218.12-218.32"
82891   wire width 7 \main_libresocsim_adr
82892   attribute \src "ls180.v:62.6-62.32"
82893   wire \main_libresocsim_bus_error
82894   attribute \src "ls180.v:63.12-63.39"
82895   wire width 32 \main_libresocsim_bus_errors
82896   attribute \src "ls180.v:59.13-59.47"
82897   wire width 32 \main_libresocsim_bus_errors_status
82898   attribute \src "ls180.v:60.6-60.36"
82899   wire \main_libresocsim_bus_errors_we
82900   attribute \src "ls180.v:174.5-174.40"
82901   wire \main_libresocsim_converter0_counter
82902   attribute \src "ls180.v:1736.5-1736.62"
82903   wire \main_libresocsim_converter0_counter_converter0_next_value
82904   attribute \src "ls180.v:1737.5-1737.65"
82905   wire \main_libresocsim_converter0_counter_converter0_next_value_ce
82906   attribute \src "ls180.v:176.12-176.45"
82907   wire width 64 \main_libresocsim_converter0_dat_r
82908   attribute \src "ls180.v:175.6-175.39"
82909   wire \main_libresocsim_converter0_reset
82910   attribute \src "ls180.v:173.5-173.37"
82911   wire \main_libresocsim_converter0_skip
82912   attribute \src "ls180.v:189.5-189.40"
82913   wire \main_libresocsim_converter1_counter
82914   attribute \src "ls180.v:1740.5-1740.62"
82915   wire \main_libresocsim_converter1_counter_converter1_next_value
82916   attribute \src "ls180.v:1741.5-1741.65"
82917   wire \main_libresocsim_converter1_counter_converter1_next_value_ce
82918   attribute \src "ls180.v:191.12-191.45"
82919   wire width 64 \main_libresocsim_converter1_dat_r
82920   attribute \src "ls180.v:190.6-190.39"
82921   wire \main_libresocsim_converter1_reset
82922   attribute \src "ls180.v:188.5-188.37"
82923   wire \main_libresocsim_converter1_skip
82924   attribute \src "ls180.v:204.5-204.40"
82925   wire \main_libresocsim_converter2_counter
82926   attribute \src "ls180.v:1744.5-1744.62"
82927   wire \main_libresocsim_converter2_counter_converter2_next_value
82928   attribute \src "ls180.v:1745.5-1745.65"
82929   wire \main_libresocsim_converter2_counter_converter2_next_value_ce
82930   attribute \src "ls180.v:206.12-206.45"
82931   wire width 64 \main_libresocsim_converter2_dat_r
82932   attribute \src "ls180.v:205.6-205.39"
82933   wire \main_libresocsim_converter2_reset
82934   attribute \src "ls180.v:203.5-203.37"
82935   wire \main_libresocsim_converter2_skip
82936   attribute \src "ls180.v:219.13-219.35"
82937   wire width 32 \main_libresocsim_dat_r
82938   attribute \src "ls180.v:221.13-221.35"
82939   wire width 32 \main_libresocsim_dat_w
82940   attribute \src "ls180.v:227.5-227.27"
82941   wire \main_libresocsim_en_re
82942   attribute \src "ls180.v:226.5-226.32"
82943   wire \main_libresocsim_en_storage
82944   attribute \src "ls180.v:243.6-243.45"
82945   wire \main_libresocsim_eventmanager_pending_r
82946   attribute \src "ls180.v:242.6-242.46"
82947   wire \main_libresocsim_eventmanager_pending_re
82948   attribute \src "ls180.v:245.6-245.45"
82949   wire \main_libresocsim_eventmanager_pending_w
82950   attribute \src "ls180.v:244.6-244.46"
82951   wire \main_libresocsim_eventmanager_pending_we
82952   attribute \src "ls180.v:247.5-247.37"
82953   wire \main_libresocsim_eventmanager_re
82954   attribute \src "ls180.v:239.6-239.44"
82955   wire \main_libresocsim_eventmanager_status_r
82956   attribute \src "ls180.v:238.6-238.45"
82957   wire \main_libresocsim_eventmanager_status_re
82958   attribute \src "ls180.v:241.6-241.44"
82959   wire \main_libresocsim_eventmanager_status_w
82960   attribute \src "ls180.v:240.6-240.45"
82961   wire \main_libresocsim_eventmanager_status_we
82962   attribute \src "ls180.v:246.5-246.42"
82963   wire \main_libresocsim_eventmanager_storage
82964   attribute \src "ls180.v:168.6-168.57"
82965   wire \main_libresocsim_interface0_converted_interface_ack
82966   attribute \src "ls180.v:162.12-162.63"
82967   wire width 30 \main_libresocsim_interface0_converted_interface_adr
82968   attribute \src "ls180.v:171.11-171.62"
82969   wire width 2 \main_libresocsim_interface0_converted_interface_bte
82970   attribute \src "ls180.v:170.11-170.62"
82971   wire width 3 \main_libresocsim_interface0_converted_interface_cti
82972   attribute \src "ls180.v:166.5-166.56"
82973   wire \main_libresocsim_interface0_converted_interface_cyc
82974   attribute \src "ls180.v:164.13-164.66"
82975   wire width 32 \main_libresocsim_interface0_converted_interface_dat_r
82976   attribute \src "ls180.v:163.12-163.65"
82977   wire width 32 \main_libresocsim_interface0_converted_interface_dat_w
82978   attribute \src "ls180.v:172.6-172.57"
82979   wire \main_libresocsim_interface0_converted_interface_err
82980   attribute \src "ls180.v:165.11-165.62"
82981   wire width 4 \main_libresocsim_interface0_converted_interface_sel
82982   attribute \src "ls180.v:167.5-167.56"
82983   wire \main_libresocsim_interface0_converted_interface_stb
82984   attribute \src "ls180.v:169.5-169.55"
82985   wire \main_libresocsim_interface0_converted_interface_we
82986   attribute \src "ls180.v:183.6-183.57"
82987   wire \main_libresocsim_interface1_converted_interface_ack
82988   attribute \src "ls180.v:177.12-177.63"
82989   wire width 30 \main_libresocsim_interface1_converted_interface_adr
82990   attribute \src "ls180.v:186.11-186.62"
82991   wire width 2 \main_libresocsim_interface1_converted_interface_bte
82992   attribute \src "ls180.v:185.11-185.62"
82993   wire width 3 \main_libresocsim_interface1_converted_interface_cti
82994   attribute \src "ls180.v:181.5-181.56"
82995   wire \main_libresocsim_interface1_converted_interface_cyc
82996   attribute \src "ls180.v:179.13-179.66"
82997   wire width 32 \main_libresocsim_interface1_converted_interface_dat_r
82998   attribute \src "ls180.v:178.12-178.65"
82999   wire width 32 \main_libresocsim_interface1_converted_interface_dat_w
83000   attribute \src "ls180.v:187.6-187.57"
83001   wire \main_libresocsim_interface1_converted_interface_err
83002   attribute \src "ls180.v:180.11-180.62"
83003   wire width 4 \main_libresocsim_interface1_converted_interface_sel
83004   attribute \src "ls180.v:182.5-182.56"
83005   wire \main_libresocsim_interface1_converted_interface_stb
83006   attribute \src "ls180.v:184.5-184.55"
83007   wire \main_libresocsim_interface1_converted_interface_we
83008   attribute \src "ls180.v:198.6-198.57"
83009   wire \main_libresocsim_interface2_converted_interface_ack
83010   attribute \src "ls180.v:192.12-192.63"
83011   wire width 30 \main_libresocsim_interface2_converted_interface_adr
83012   attribute \src "ls180.v:201.11-201.62"
83013   wire width 2 \main_libresocsim_interface2_converted_interface_bte
83014   attribute \src "ls180.v:200.11-200.62"
83015   wire width 3 \main_libresocsim_interface2_converted_interface_cti
83016   attribute \src "ls180.v:196.5-196.56"
83017   wire \main_libresocsim_interface2_converted_interface_cyc
83018   attribute \src "ls180.v:194.13-194.66"
83019   wire width 32 \main_libresocsim_interface2_converted_interface_dat_r
83020   attribute \src "ls180.v:193.12-193.65"
83021   wire width 32 \main_libresocsim_interface2_converted_interface_dat_w
83022   attribute \src "ls180.v:202.6-202.57"
83023   wire \main_libresocsim_interface2_converted_interface_err
83024   attribute \src "ls180.v:195.11-195.62"
83025   wire width 4 \main_libresocsim_interface2_converted_interface_sel
83026   attribute \src "ls180.v:197.5-197.56"
83027   wire \main_libresocsim_interface2_converted_interface_stb
83028   attribute \src "ls180.v:199.5-199.55"
83029   wire \main_libresocsim_interface2_converted_interface_we
83030   attribute \src "ls180.v:232.6-232.26"
83031   wire \main_libresocsim_irq
83032   attribute \src "ls180.v:123.6-123.32"
83033   wire \main_libresocsim_libresoc0
83034   attribute \src "ls180.v:124.6-124.32"
83035   wire \main_libresocsim_libresoc1
83036   attribute \src "ls180.v:125.13-125.39"
83037   wire width 64 \main_libresocsim_libresoc2
83038   attribute \src "ls180.v:127.12-127.45"
83039   wire width 3 \main_libresocsim_libresoc_clk_sel
83040   attribute \src "ls180.v:129.12-129.66"
83041   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
83042   attribute \src "ls180.v:130.13-130.67"
83043   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
83044   attribute \src "ls180.v:131.13-131.68"
83045   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
83046   attribute \src "ls180.v:158.6-158.61"
83047   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
83048   attribute \src "ls180.v:159.5-159.62"
83049   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
83050   attribute \src "ls180.v:160.6-160.63"
83051   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
83052   attribute \src "ls180.v:161.6-161.64"
83053   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
83054   attribute \src "ls180.v:136.6-136.64"
83055   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
83056   attribute \src "ls180.v:137.5-137.65"
83057   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
83058   attribute \src "ls180.v:138.6-138.66"
83059   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
83060   attribute \src "ls180.v:139.6-139.67"
83061   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
83062   attribute \src "ls180.v:146.13-146.68"
83063   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
83064   attribute \src "ls180.v:155.12-155.68"
83065   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
83066   attribute \src "ls180.v:152.6-152.65"
83067   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
83068   attribute \src "ls180.v:154.6-154.63"
83069   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
83070   attribute \src "ls180.v:153.6-153.64"
83071   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
83072   attribute \src "ls180.v:156.12-156.68"
83073   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
83074   attribute \src "ls180.v:147.12-147.70"
83075   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
83076   attribute \src "ls180.v:148.13-148.71"
83077   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
83078   attribute \src "ls180.v:149.6-149.65"
83079   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
83080   attribute \src "ls180.v:151.6-151.65"
83081   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
83082   attribute \src "ls180.v:150.6-150.64"
83083   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
83084   attribute \src "ls180.v:142.6-142.67"
83085   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
83086   attribute \src "ls180.v:144.6-144.68"
83087   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
83088   attribute \src "ls180.v:145.5-145.67"
83089   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
83090   attribute \src "ls180.v:143.6-143.68"
83091   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
83092   attribute \src "ls180.v:132.6-132.67"
83093   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
83094   attribute \src "ls180.v:134.6-134.68"
83095   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
83096   attribute \src "ls180.v:135.5-135.67"
83097   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
83098   attribute \src "ls180.v:133.6-133.68"
83099   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
83100   attribute \src "ls180.v:72.5-72.39"
83101   wire \main_libresocsim_libresoc_dbus_ack
83102   attribute \src "ls180.v:66.13-66.47"
83103   wire width 29 \main_libresocsim_libresoc_dbus_adr
83104   attribute \src "ls180.v:75.12-75.46"
83105   wire width 2 \main_libresocsim_libresoc_dbus_bte
83106   attribute \src "ls180.v:74.12-74.46"
83107   wire width 3 \main_libresocsim_libresoc_dbus_cti
83108   attribute \src "ls180.v:70.6-70.40"
83109   wire \main_libresocsim_libresoc_dbus_cyc
83110   attribute \src "ls180.v:68.13-68.49"
83111   wire width 64 \main_libresocsim_libresoc_dbus_dat_r
83112   attribute \src "ls180.v:67.13-67.49"
83113   wire width 64 \main_libresocsim_libresoc_dbus_dat_w
83114   attribute \src "ls180.v:76.5-76.39"
83115   wire \main_libresocsim_libresoc_dbus_err
83116   attribute \src "ls180.v:69.12-69.46"
83117   wire width 8 \main_libresocsim_libresoc_dbus_sel
83118   attribute \src "ls180.v:71.6-71.40"
83119   wire \main_libresocsim_libresoc_dbus_stb
83120   attribute \src "ls180.v:73.6-73.39"
83121   wire \main_libresocsim_libresoc_dbus_we
83122   attribute \src "ls180.v:83.5-83.39"
83123   wire \main_libresocsim_libresoc_ibus_ack
83124   attribute \src "ls180.v:77.13-77.47"
83125   wire width 29 \main_libresocsim_libresoc_ibus_adr
83126   attribute \src "ls180.v:86.12-86.46"
83127   wire width 2 \main_libresocsim_libresoc_ibus_bte
83128   attribute \src "ls180.v:85.12-85.46"
83129   wire width 3 \main_libresocsim_libresoc_ibus_cti
83130   attribute \src "ls180.v:81.6-81.40"
83131   wire \main_libresocsim_libresoc_ibus_cyc
83132   attribute \src "ls180.v:79.13-79.49"
83133   wire width 64 \main_libresocsim_libresoc_ibus_dat_r
83134   attribute \src "ls180.v:78.13-78.49"
83135   wire width 64 \main_libresocsim_libresoc_ibus_dat_w
83136   attribute \src "ls180.v:87.5-87.39"
83137   wire \main_libresocsim_libresoc_ibus_err
83138   attribute \src "ls180.v:80.12-80.46"
83139   wire width 8 \main_libresocsim_libresoc_ibus_sel
83140   attribute \src "ls180.v:82.6-82.40"
83141   wire \main_libresocsim_libresoc_ibus_stb
83142   attribute \src "ls180.v:84.6-84.39"
83143   wire \main_libresocsim_libresoc_ibus_we
83144   attribute \src "ls180.v:65.12-65.47"
83145   wire width 16 \main_libresocsim_libresoc_interrupt
83146   attribute \src "ls180.v:119.6-119.40"
83147   wire \main_libresocsim_libresoc_jtag_tck
83148   attribute \src "ls180.v:121.6-121.40"
83149   wire \main_libresocsim_libresoc_jtag_tdi
83150   attribute \src "ls180.v:122.6-122.40"
83151   wire \main_libresocsim_libresoc_jtag_tdo
83152   attribute \src "ls180.v:120.6-120.40"
83153   wire \main_libresocsim_libresoc_jtag_tms
83154   attribute \src "ls180.v:116.5-116.42"
83155   wire \main_libresocsim_libresoc_jtag_wb_ack
83156   attribute \src "ls180.v:110.13-110.50"
83157   wire width 29 \main_libresocsim_libresoc_jtag_wb_adr
83158   attribute \src "ls180.v:114.6-114.43"
83159   wire \main_libresocsim_libresoc_jtag_wb_cyc
83160   attribute \src "ls180.v:112.13-112.52"
83161   wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r
83162   attribute \src "ls180.v:111.13-111.52"
83163   wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w
83164   attribute \src "ls180.v:118.5-118.42"
83165   wire \main_libresocsim_libresoc_jtag_wb_err
83166   attribute \src "ls180.v:113.12-113.49"
83167   wire width 8 \main_libresocsim_libresoc_jtag_wb_sel
83168   attribute \src "ls180.v:115.6-115.43"
83169   wire \main_libresocsim_libresoc_jtag_wb_stb
83170   attribute \src "ls180.v:117.6-117.42"
83171   wire \main_libresocsim_libresoc_jtag_wb_we
83172   attribute \src "ls180.v:126.6-126.40"
83173   wire \main_libresocsim_libresoc_pll_18_o
83174   attribute \src "ls180.v:128.6-128.41"
83175   wire \main_libresocsim_libresoc_pll_lck_o
83176   attribute \src "ls180.v:64.6-64.37"
83177   wire \main_libresocsim_libresoc_reset
83178   attribute \src "ls180.v:94.6-94.44"
83179   wire \main_libresocsim_libresoc_xics_icp_ack
83180   attribute \src "ls180.v:88.13-88.51"
83181   wire width 30 \main_libresocsim_libresoc_xics_icp_adr
83182   attribute \src "ls180.v:97.12-97.50"
83183   wire width 2 \main_libresocsim_libresoc_xics_icp_bte
83184   attribute \src "ls180.v:96.12-96.50"
83185   wire width 3 \main_libresocsim_libresoc_xics_icp_cti
83186   attribute \src "ls180.v:92.6-92.44"
83187   wire \main_libresocsim_libresoc_xics_icp_cyc
83188   attribute \src "ls180.v:90.13-90.53"
83189   wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r
83190   attribute \src "ls180.v:89.13-89.53"
83191   wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w
83192   attribute \src "ls180.v:98.6-98.44"
83193   wire \main_libresocsim_libresoc_xics_icp_err
83194   attribute \src "ls180.v:91.12-91.50"
83195   wire width 4 \main_libresocsim_libresoc_xics_icp_sel
83196   attribute \src "ls180.v:93.6-93.44"
83197   wire \main_libresocsim_libresoc_xics_icp_stb
83198   attribute \src "ls180.v:95.6-95.43"
83199   wire \main_libresocsim_libresoc_xics_icp_we
83200   attribute \src "ls180.v:105.6-105.44"
83201   wire \main_libresocsim_libresoc_xics_ics_ack
83202   attribute \src "ls180.v:99.13-99.51"
83203   wire width 30 \main_libresocsim_libresoc_xics_ics_adr
83204   attribute \src "ls180.v:108.12-108.50"
83205   wire width 2 \main_libresocsim_libresoc_xics_ics_bte
83206   attribute \src "ls180.v:107.12-107.50"
83207   wire width 3 \main_libresocsim_libresoc_xics_ics_cti
83208   attribute \src "ls180.v:103.6-103.44"
83209   wire \main_libresocsim_libresoc_xics_ics_cyc
83210   attribute \src "ls180.v:101.13-101.53"
83211   wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r
83212   attribute \src "ls180.v:100.13-100.53"
83213   wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w
83214   attribute \src "ls180.v:109.6-109.44"
83215   wire \main_libresocsim_libresoc_xics_ics_err
83216   attribute \src "ls180.v:102.12-102.50"
83217   wire width 4 \main_libresocsim_libresoc_xics_ics_sel
83218   attribute \src "ls180.v:104.6-104.44"
83219   wire \main_libresocsim_libresoc_xics_ics_stb
83220   attribute \src "ls180.v:106.6-106.43"
83221   wire \main_libresocsim_libresoc_xics_ics_we
83222   attribute \src "ls180.v:223.5-223.29"
83223   wire \main_libresocsim_load_re
83224   attribute \src "ls180.v:222.12-222.41"
83225   wire width 32 \main_libresocsim_load_storage
83226   attribute \src "ls180.v:213.5-213.33"
83227   wire \main_libresocsim_ram_bus_ack
83228   attribute \src "ls180.v:207.13-207.41"
83229   wire width 30 \main_libresocsim_ram_bus_adr
83230   attribute \src "ls180.v:216.12-216.40"
83231   wire width 2 \main_libresocsim_ram_bus_bte
83232   attribute \src "ls180.v:215.12-215.40"
83233   wire width 3 \main_libresocsim_ram_bus_cti
83234   attribute \src "ls180.v:211.6-211.34"
83235   wire \main_libresocsim_ram_bus_cyc
83236   attribute \src "ls180.v:209.13-209.43"
83237   wire width 32 \main_libresocsim_ram_bus_dat_r
83238   attribute \src "ls180.v:208.13-208.43"
83239   wire width 32 \main_libresocsim_ram_bus_dat_w
83240   attribute \src "ls180.v:217.5-217.33"
83241   wire \main_libresocsim_ram_bus_err
83242   attribute \src "ls180.v:210.12-210.40"
83243   wire width 4 \main_libresocsim_ram_bus_sel
83244   attribute \src "ls180.v:212.6-212.34"
83245   wire \main_libresocsim_ram_bus_stb
83246   attribute \src "ls180.v:214.6-214.33"
83247   wire \main_libresocsim_ram_bus_we
83248   attribute \src "ls180.v:225.5-225.31"
83249   wire \main_libresocsim_reload_re
83250   attribute \src "ls180.v:224.12-224.43"
83251   wire width 32 \main_libresocsim_reload_storage
83252   attribute \src "ls180.v:61.6-61.28"
83253   wire \main_libresocsim_reset
83254   attribute \src "ls180.v:56.5-56.30"
83255   wire \main_libresocsim_reset_re
83256   attribute \src "ls180.v:55.5-55.35"
83257   wire \main_libresocsim_reset_storage
83258   attribute \src "ls180.v:58.5-58.32"
83259   wire \main_libresocsim_scratch_re
83260   attribute \src "ls180.v:57.12-57.44"
83261   wire width 32 \main_libresocsim_scratch_storage
83262   attribute \src "ls180.v:229.5-229.37"
83263   wire \main_libresocsim_update_value_re
83264   attribute \src "ls180.v:228.5-228.42"
83265   wire \main_libresocsim_update_value_storage
83266   attribute \src "ls180.v:248.12-248.34"
83267   wire width 32 \main_libresocsim_value
83268   attribute \src "ls180.v:230.12-230.41"
83269   wire width 32 \main_libresocsim_value_status
83270   attribute \src "ls180.v:231.6-231.31"
83271   wire \main_libresocsim_value_we
83272   attribute \src "ls180.v:220.11-220.30"
83273   wire width 4 \main_libresocsim_we
83274   attribute \src "ls180.v:236.5-236.32"
83275   wire \main_libresocsim_zero_clear
83276   attribute \src "ls180.v:237.5-237.38"
83277   wire \main_libresocsim_zero_old_trigger
83278   attribute \src "ls180.v:234.5-234.34"
83279   wire \main_libresocsim_zero_pending
83280   attribute \src "ls180.v:233.6-233.34"
83281   wire \main_libresocsim_zero_status
83282   attribute \src "ls180.v:235.6-235.35"
83283   wire \main_libresocsim_zero_trigger
83284   attribute \src "ls180.v:830.6-830.26"
83285   wire \main_litedram_wb_ack
83286   attribute \src "ls180.v:824.12-824.32"
83287   wire width 30 \main_litedram_wb_adr
83288   attribute \src "ls180.v:828.5-828.25"
83289   wire \main_litedram_wb_cyc
83290   attribute \src "ls180.v:826.13-826.35"
83291   wire width 16 \main_litedram_wb_dat_r
83292   attribute \src "ls180.v:825.12-825.34"
83293   wire width 16 \main_litedram_wb_dat_w
83294   attribute \src "ls180.v:827.11-827.31"
83295   wire width 2 \main_litedram_wb_sel
83296   attribute \src "ls180.v:829.5-829.25"
83297   wire \main_litedram_wb_stb
83298   attribute \src "ls180.v:831.5-831.24"
83299   wire \main_litedram_wb_we
83300   attribute \src "ls180.v:1066.13-1066.20"
83301   wire width 36 \main_nc
83302   attribute \src "ls180.v:803.6-803.24"
83303   wire \main_port_cmd_last
83304   attribute \src "ls180.v:805.13-805.39"
83305   wire width 24 \main_port_cmd_payload_addr
83306   attribute \src "ls180.v:804.6-804.30"
83307   wire \main_port_cmd_payload_we
83308   attribute \src "ls180.v:802.6-802.25"
83309   wire \main_port_cmd_ready
83310   attribute \src "ls180.v:801.6-801.25"
83311   wire \main_port_cmd_valid
83312   attribute \src "ls180.v:800.6-800.21"
83313   wire \main_port_flush
83314   attribute \src "ls180.v:812.13-812.41"
83315   wire width 16 \main_port_rdata_payload_data
83316   attribute \src "ls180.v:811.6-811.27"
83317   wire \main_port_rdata_ready
83318   attribute \src "ls180.v:810.6-810.27"
83319   wire \main_port_rdata_valid
83320   attribute \src "ls180.v:808.13-808.41"
83321   wire width 16 \main_port_wdata_payload_data
83322   attribute \src "ls180.v:809.12-809.38"
83323   wire width 2 \main_port_wdata_payload_we
83324   attribute \src "ls180.v:807.6-807.27"
83325   wire \main_port_wdata_ready
83326   attribute \src "ls180.v:806.6-806.27"
83327   wire \main_port_wdata_valid
83328   attribute \src "ls180.v:1071.12-1071.29"
83329   wire width 32 \main_pwm0_counter
83330   attribute \src "ls180.v:1068.6-1068.22"
83331   wire \main_pwm0_enable
83332   attribute \src "ls180.v:1073.5-1073.24"
83333   wire \main_pwm0_enable_re
83334   attribute \src "ls180.v:1072.5-1072.29"
83335   wire \main_pwm0_enable_storage
83336   attribute \src "ls180.v:1070.13-1070.29"
83337   wire width 32 \main_pwm0_period
83338   attribute \src "ls180.v:1077.5-1077.24"
83339   wire \main_pwm0_period_re
83340   attribute \src "ls180.v:1076.12-1076.36"
83341   wire width 32 \main_pwm0_period_storage
83342   attribute \src "ls180.v:1069.13-1069.28"
83343   wire width 32 \main_pwm0_width
83344   attribute \src "ls180.v:1075.5-1075.23"
83345   wire \main_pwm0_width_re
83346   attribute \src "ls180.v:1074.12-1074.35"
83347   wire width 32 \main_pwm0_width_storage
83348   attribute \src "ls180.v:1081.12-1081.29"
83349   wire width 32 \main_pwm1_counter
83350   attribute \src "ls180.v:1078.6-1078.22"
83351   wire \main_pwm1_enable
83352   attribute \src "ls180.v:1083.5-1083.24"
83353   wire \main_pwm1_enable_re
83354   attribute \src "ls180.v:1082.5-1082.29"
83355   wire \main_pwm1_enable_storage
83356   attribute \src "ls180.v:1080.13-1080.29"
83357   wire width 32 \main_pwm1_period
83358   attribute \src "ls180.v:1087.5-1087.24"
83359   wire \main_pwm1_period_re
83360   attribute \src "ls180.v:1086.12-1086.36"
83361   wire width 32 \main_pwm1_period_storage
83362   attribute \src "ls180.v:1079.13-1079.28"
83363   wire width 32 \main_pwm1_width
83364   attribute \src "ls180.v:1085.5-1085.23"
83365   wire \main_pwm1_width_re
83366   attribute \src "ls180.v:1084.12-1084.35"
83367   wire width 32 \main_pwm1_width_storage
83368   attribute \src "ls180.v:269.11-269.25"
83369   wire width 3 \main_rddata_en
83370   attribute \src "ls180.v:1609.11-1609.43"
83371   wire width 2 \main_sdblock2mem_converter_demux
83372   attribute \src "ls180.v:1610.6-1610.42"
83373   wire \main_sdblock2mem_converter_load_part
83374   attribute \src "ls180.v:1600.6-1600.43"
83375   wire \main_sdblock2mem_converter_sink_first
83376   attribute \src "ls180.v:1601.6-1601.42"
83377   wire \main_sdblock2mem_converter_sink_last
83378   attribute \src "ls180.v:1602.12-1602.56"
83379   wire width 8 \main_sdblock2mem_converter_sink_payload_data
83380   attribute \src "ls180.v:1599.6-1599.43"
83381   wire \main_sdblock2mem_converter_sink_ready
83382   attribute \src "ls180.v:1598.6-1598.43"
83383   wire \main_sdblock2mem_converter_sink_valid
83384   attribute \src "ls180.v:1605.5-1605.44"
83385   wire \main_sdblock2mem_converter_source_first
83386   attribute \src "ls180.v:1606.5-1606.43"
83387   wire \main_sdblock2mem_converter_source_last
83388   attribute \src "ls180.v:1607.12-1607.58"
83389   wire width 32 \main_sdblock2mem_converter_source_payload_data
83390   attribute \src "ls180.v:1608.11-1608.70"
83391   wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count
83392   attribute \src "ls180.v:1604.6-1604.45"
83393   wire \main_sdblock2mem_converter_source_ready
83394   attribute \src "ls180.v:1603.6-1603.45"
83395   wire \main_sdblock2mem_converter_source_valid
83396   attribute \src "ls180.v:1611.5-1611.42"
83397   wire \main_sdblock2mem_converter_strobe_all
83398   attribute \src "ls180.v:1584.11-1584.40"
83399   wire width 5 \main_sdblock2mem_fifo_consume
83400   attribute \src "ls180.v:1589.6-1589.35"
83401   wire \main_sdblock2mem_fifo_do_read
83402   attribute \src "ls180.v:1593.6-1593.41"
83403   wire \main_sdblock2mem_fifo_fifo_in_first
83404   attribute \src "ls180.v:1594.6-1594.40"
83405   wire \main_sdblock2mem_fifo_fifo_in_last
83406   attribute \src "ls180.v:1592.12-1592.54"
83407   wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data
83408   attribute \src "ls180.v:1596.6-1596.42"
83409   wire \main_sdblock2mem_fifo_fifo_out_first
83410   attribute \src "ls180.v:1597.6-1597.41"
83411   wire \main_sdblock2mem_fifo_fifo_out_last
83412   attribute \src "ls180.v:1595.12-1595.55"
83413   wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data
83414   attribute \src "ls180.v:1581.11-1581.38"
83415   wire width 6 \main_sdblock2mem_fifo_level
83416   attribute \src "ls180.v:1583.11-1583.40"
83417   wire width 5 \main_sdblock2mem_fifo_produce
83418   attribute \src "ls180.v:1590.12-1590.44"
83419   wire width 5 \main_sdblock2mem_fifo_rdport_adr
83420   attribute \src "ls180.v:1591.12-1591.46"
83421   wire width 10 \main_sdblock2mem_fifo_rdport_dat_r
83422   attribute \src "ls180.v:1582.5-1582.34"
83423   wire \main_sdblock2mem_fifo_replace
83424   attribute \src "ls180.v:1567.6-1567.38"
83425   wire \main_sdblock2mem_fifo_sink_first
83426   attribute \src "ls180.v:1568.6-1568.37"
83427   wire \main_sdblock2mem_fifo_sink_last
83428   attribute \src "ls180.v:1569.12-1569.51"
83429   wire width 8 \main_sdblock2mem_fifo_sink_payload_data
83430   attribute \src "ls180.v:1566.6-1566.38"
83431   wire \main_sdblock2mem_fifo_sink_ready
83432   attribute \src "ls180.v:1565.6-1565.38"
83433   wire \main_sdblock2mem_fifo_sink_valid
83434   attribute \src "ls180.v:1572.6-1572.40"
83435   wire \main_sdblock2mem_fifo_source_first
83436   attribute \src "ls180.v:1573.6-1573.39"
83437   wire \main_sdblock2mem_fifo_source_last
83438   attribute \src "ls180.v:1574.12-1574.53"
83439   wire width 8 \main_sdblock2mem_fifo_source_payload_data
83440   attribute \src "ls180.v:1571.6-1571.40"
83441   wire \main_sdblock2mem_fifo_source_ready
83442   attribute \src "ls180.v:1570.6-1570.40"
83443   wire \main_sdblock2mem_fifo_source_valid
83444   attribute \src "ls180.v:1579.12-1579.46"
83445   wire width 10 \main_sdblock2mem_fifo_syncfifo_din
83446   attribute \src "ls180.v:1580.12-1580.47"
83447   wire width 10 \main_sdblock2mem_fifo_syncfifo_dout
83448   attribute \src "ls180.v:1577.6-1577.39"
83449   wire \main_sdblock2mem_fifo_syncfifo_re
83450   attribute \src "ls180.v:1578.6-1578.45"
83451   wire \main_sdblock2mem_fifo_syncfifo_readable
83452   attribute \src "ls180.v:1575.6-1575.39"
83453   wire \main_sdblock2mem_fifo_syncfifo_we
83454   attribute \src "ls180.v:1576.6-1576.45"
83455   wire \main_sdblock2mem_fifo_syncfifo_writable
83456   attribute \src "ls180.v:1585.11-1585.43"
83457   wire width 5 \main_sdblock2mem_fifo_wrport_adr
83458   attribute \src "ls180.v:1586.12-1586.46"
83459   wire width 10 \main_sdblock2mem_fifo_wrport_dat_r
83460   attribute \src "ls180.v:1588.12-1588.46"
83461   wire width 10 \main_sdblock2mem_fifo_wrport_dat_w
83462   attribute \src "ls180.v:1587.6-1587.37"
83463   wire \main_sdblock2mem_fifo_wrport_we
83464   attribute \src "ls180.v:1562.6-1562.38"
83465   wire \main_sdblock2mem_sink_sink_first
83466   attribute \src "ls180.v:1563.6-1563.37"
83467   wire \main_sdblock2mem_sink_sink_last
83468   attribute \src "ls180.v:1619.12-1619.54"
83469   wire width 32 \main_sdblock2mem_sink_sink_payload_address
83470   attribute \src "ls180.v:1564.12-1564.52"
83471   wire width 8 \main_sdblock2mem_sink_sink_payload_data0
83472   attribute \src "ls180.v:1620.12-1620.52"
83473   wire width 32 \main_sdblock2mem_sink_sink_payload_data1
83474   attribute \src "ls180.v:1561.6-1561.39"
83475   wire \main_sdblock2mem_sink_sink_ready0
83476   attribute \src "ls180.v:1618.6-1618.39"
83477   wire \main_sdblock2mem_sink_sink_ready1
83478   attribute \src "ls180.v:1560.6-1560.39"
83479   wire \main_sdblock2mem_sink_sink_valid0
83480   attribute \src "ls180.v:1617.5-1617.38"
83481   wire \main_sdblock2mem_sink_sink_valid1
83482   attribute \src "ls180.v:1614.6-1614.42"
83483   wire \main_sdblock2mem_source_source_first
83484   attribute \src "ls180.v:1615.6-1615.41"
83485   wire \main_sdblock2mem_source_source_last
83486   attribute \src "ls180.v:1616.13-1616.56"
83487   wire width 32 \main_sdblock2mem_source_source_payload_data
83488   attribute \src "ls180.v:1613.6-1613.42"
83489   wire \main_sdblock2mem_source_source_ready
83490   attribute \src "ls180.v:1612.6-1612.42"
83491   wire \main_sdblock2mem_source_source_valid
83492   attribute \src "ls180.v:1636.13-1636.52"
83493   wire width 32 \main_sdblock2mem_wishbonedmawriter_base
83494   attribute \src "ls180.v:1627.5-1627.47"
83495   wire \main_sdblock2mem_wishbonedmawriter_base_re
83496   attribute \src "ls180.v:1626.12-1626.59"
83497   wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage
83498   attribute \src "ls180.v:1631.5-1631.49"
83499   wire \main_sdblock2mem_wishbonedmawriter_enable_re
83500   attribute \src "ls180.v:1630.5-1630.54"
83501   wire \main_sdblock2mem_wishbonedmawriter_enable_storage
83502   attribute \src "ls180.v:1638.13-1638.54"
83503   wire width 32 \main_sdblock2mem_wishbonedmawriter_length
83504   attribute \src "ls180.v:1629.5-1629.49"
83505   wire \main_sdblock2mem_wishbonedmawriter_length_re
83506   attribute \src "ls180.v:1628.12-1628.61"
83507   wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage
83508   attribute \src "ls180.v:1635.5-1635.47"
83509   wire \main_sdblock2mem_wishbonedmawriter_loop_re
83510   attribute \src "ls180.v:1634.5-1634.52"
83511   wire \main_sdblock2mem_wishbonedmawriter_loop_storage
83512   attribute \src "ls180.v:1637.12-1637.53"
83513   wire width 32 \main_sdblock2mem_wishbonedmawriter_offset
83514   attribute \src "ls180.v:1857.12-1857.79"
83515   wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
83516   attribute \src "ls180.v:1858.5-1858.75"
83517   wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
83518   attribute \src "ls180.v:1639.6-1639.46"
83519   wire \main_sdblock2mem_wishbonedmawriter_reset
83520   attribute \src "ls180.v:1623.6-1623.51"
83521   wire \main_sdblock2mem_wishbonedmawriter_sink_first
83522   attribute \src "ls180.v:1624.6-1624.50"
83523   wire \main_sdblock2mem_wishbonedmawriter_sink_last
83524   attribute \src "ls180.v:1625.13-1625.65"
83525   wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data
83526   attribute \src "ls180.v:1622.5-1622.50"
83527   wire \main_sdblock2mem_wishbonedmawriter_sink_ready
83528   attribute \src "ls180.v:1621.6-1621.51"
83529   wire \main_sdblock2mem_wishbonedmawriter_sink_valid
83530   attribute \src "ls180.v:1632.5-1632.46"
83531   wire \main_sdblock2mem_wishbonedmawriter_status
83532   attribute \src "ls180.v:1633.6-1633.43"
83533   wire \main_sdblock2mem_wishbonedmawriter_we
83534   attribute \src "ls180.v:1401.5-1401.31"
83535   wire \main_sdcore_block_count_re
83536   attribute \src "ls180.v:1400.12-1400.43"
83537   wire width 32 \main_sdcore_block_count_storage
83538   attribute \src "ls180.v:1399.5-1399.32"
83539   wire \main_sdcore_block_length_re
83540   attribute \src "ls180.v:1398.11-1398.43"
83541   wire width 10 \main_sdcore_block_length_storage
83542   attribute \src "ls180.v:1385.5-1385.32"
83543   wire \main_sdcore_cmd_argument_re
83544   attribute \src "ls180.v:1384.12-1384.44"
83545   wire width 32 \main_sdcore_cmd_argument_storage
83546   attribute \src "ls180.v:1387.5-1387.31"
83547   wire \main_sdcore_cmd_command_re
83548   attribute \src "ls180.v:1386.12-1386.43"
83549   wire width 32 \main_sdcore_cmd_command_storage
83550   attribute \src "ls180.v:1540.11-1540.32"
83551   wire width 3 \main_sdcore_cmd_count
83552   attribute \src "ls180.v:1841.11-1841.55"
83553   wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2
83554   attribute \src "ls180.v:1842.5-1842.52"
83555   wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
83556   attribute \src "ls180.v:1541.5-1541.25"
83557   wire \main_sdcore_cmd_done
83558   attribute \src "ls180.v:1837.5-1837.48"
83559   wire \main_sdcore_cmd_done_sdcore_fsm_next_value0
83560   attribute \src "ls180.v:1838.5-1838.51"
83561   wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
83562   attribute \src "ls180.v:1542.5-1542.26"
83563   wire \main_sdcore_cmd_error
83564   attribute \src "ls180.v:1845.5-1845.49"
83565   wire \main_sdcore_cmd_error_sdcore_fsm_next_value4
83566   attribute \src "ls180.v:1846.5-1846.52"
83567   wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
83568   attribute \src "ls180.v:1394.12-1394.40"
83569   wire width 4 \main_sdcore_cmd_event_status
83570   attribute \src "ls180.v:1395.6-1395.30"
83571   wire \main_sdcore_cmd_event_we
83572   attribute \src "ls180.v:1392.13-1392.44"
83573   wire width 128 \main_sdcore_cmd_response_status
83574   attribute \src "ls180.v:1853.13-1853.67"
83575   wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
83576   attribute \src "ls180.v:1854.5-1854.62"
83577   wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
83578   attribute \src "ls180.v:1393.6-1393.33"
83579   wire \main_sdcore_cmd_response_we
83580   attribute \src "ls180.v:1389.6-1389.28"
83581   wire \main_sdcore_cmd_send_r
83582   attribute \src "ls180.v:1388.6-1388.29"
83583   wire \main_sdcore_cmd_send_re
83584   attribute \src "ls180.v:1391.5-1391.27"
83585   wire \main_sdcore_cmd_send_w
83586   attribute \src "ls180.v:1390.6-1390.29"
83587   wire \main_sdcore_cmd_send_we
83588   attribute \src "ls180.v:1543.5-1543.28"
83589   wire \main_sdcore_cmd_timeout
83590   attribute \src "ls180.v:1847.5-1847.51"
83591   wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
83592   attribute \src "ls180.v:1848.5-1848.54"
83593   wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
83594   attribute \src "ls180.v:1539.12-1539.32"
83595   wire width 2 \main_sdcore_cmd_type
83596   attribute \src "ls180.v:1501.11-1501.40"
83597   wire width 4 \main_sdcore_crc16_checker_cnt
83598   attribute \src "ls180.v:1507.5-1507.39"
83599   wire \main_sdcore_crc16_checker_crc0_clr
83600   attribute \src "ls180.v:1506.12-1506.46"
83601   wire width 16 \main_sdcore_crc16_checker_crc0_crc
83602   attribute \src "ls180.v:1502.12-1502.50"
83603   wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0
83604   attribute \src "ls180.v:1503.13-1503.51"
83605   wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1
83606   attribute \src "ls180.v:1504.13-1504.51"
83607   wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2
83608   attribute \src "ls180.v:1508.6-1508.43"
83609   wire \main_sdcore_crc16_checker_crc0_enable
83610   attribute \src "ls180.v:1505.12-1505.46"
83611   wire width 2 \main_sdcore_crc16_checker_crc0_val
83612   attribute \src "ls180.v:1514.5-1514.39"
83613   wire \main_sdcore_crc16_checker_crc1_clr
83614   attribute \src "ls180.v:1513.12-1513.46"
83615   wire width 16 \main_sdcore_crc16_checker_crc1_crc
83616   attribute \src "ls180.v:1509.12-1509.50"
83617   wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0
83618   attribute \src "ls180.v:1510.13-1510.51"
83619   wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1
83620   attribute \src "ls180.v:1511.13-1511.51"
83621   wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2
83622   attribute \src "ls180.v:1515.6-1515.43"
83623   wire \main_sdcore_crc16_checker_crc1_enable
83624   attribute \src "ls180.v:1512.12-1512.46"
83625   wire width 2 \main_sdcore_crc16_checker_crc1_val
83626   attribute \src "ls180.v:1521.5-1521.39"
83627   wire \main_sdcore_crc16_checker_crc2_clr
83628   attribute \src "ls180.v:1520.12-1520.46"
83629   wire width 16 \main_sdcore_crc16_checker_crc2_crc
83630   attribute \src "ls180.v:1516.12-1516.50"
83631   wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0
83632   attribute \src "ls180.v:1517.13-1517.51"
83633   wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1
83634   attribute \src "ls180.v:1518.13-1518.51"
83635   wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2
83636   attribute \src "ls180.v:1522.6-1522.43"
83637   wire \main_sdcore_crc16_checker_crc2_enable
83638   attribute \src "ls180.v:1519.12-1519.46"
83639   wire width 2 \main_sdcore_crc16_checker_crc2_val
83640   attribute \src "ls180.v:1528.5-1528.39"
83641   wire \main_sdcore_crc16_checker_crc3_clr
83642   attribute \src "ls180.v:1527.12-1527.46"
83643   wire width 16 \main_sdcore_crc16_checker_crc3_crc
83644   attribute \src "ls180.v:1523.12-1523.50"
83645   wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0
83646   attribute \src "ls180.v:1524.13-1524.51"
83647   wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1
83648   attribute \src "ls180.v:1525.13-1525.51"
83649   wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2
83650   attribute \src "ls180.v:1529.6-1529.43"
83651   wire \main_sdcore_crc16_checker_crc3_enable
83652   attribute \src "ls180.v:1526.12-1526.46"
83653   wire width 2 \main_sdcore_crc16_checker_crc3_val
83654   attribute \src "ls180.v:1530.12-1530.45"
83655   wire width 16 \main_sdcore_crc16_checker_crctmp0
83656   attribute \src "ls180.v:1531.12-1531.45"
83657   wire width 16 \main_sdcore_crc16_checker_crctmp1
83658   attribute \src "ls180.v:1532.12-1532.45"
83659   wire width 16 \main_sdcore_crc16_checker_crctmp2
83660   attribute \src "ls180.v:1533.12-1533.45"
83661   wire width 16 \main_sdcore_crc16_checker_crctmp3
83662   attribute \src "ls180.v:1535.12-1535.43"
83663   wire width 16 \main_sdcore_crc16_checker_fifo0
83664   attribute \src "ls180.v:1536.12-1536.43"
83665   wire width 16 \main_sdcore_crc16_checker_fifo1
83666   attribute \src "ls180.v:1537.12-1537.43"
83667   wire width 16 \main_sdcore_crc16_checker_fifo2
83668   attribute \src "ls180.v:1538.12-1538.43"
83669   wire width 16 \main_sdcore_crc16_checker_fifo3
83670   attribute \src "ls180.v:1492.5-1492.41"
83671   wire \main_sdcore_crc16_checker_sink_first
83672   attribute \src "ls180.v:1493.5-1493.40"
83673   wire \main_sdcore_crc16_checker_sink_last
83674   attribute \src "ls180.v:1494.11-1494.54"
83675   wire width 8 \main_sdcore_crc16_checker_sink_payload_data
83676   attribute \src "ls180.v:1491.5-1491.41"
83677   wire \main_sdcore_crc16_checker_sink_ready
83678   attribute \src "ls180.v:1490.5-1490.41"
83679   wire \main_sdcore_crc16_checker_sink_valid
83680   attribute \src "ls180.v:1497.5-1497.43"
83681   wire \main_sdcore_crc16_checker_source_first
83682   attribute \src "ls180.v:1498.6-1498.43"
83683   wire \main_sdcore_crc16_checker_source_last
83684   attribute \src "ls180.v:1499.12-1499.57"
83685   wire width 8 \main_sdcore_crc16_checker_source_payload_data
83686   attribute \src "ls180.v:1496.6-1496.44"
83687   wire \main_sdcore_crc16_checker_source_ready
83688   attribute \src "ls180.v:1495.5-1495.43"
83689   wire \main_sdcore_crc16_checker_source_valid
83690   attribute \src "ls180.v:1500.11-1500.40"
83691   wire width 8 \main_sdcore_crc16_checker_val
83692   attribute \src "ls180.v:1534.5-1534.36"
83693   wire \main_sdcore_crc16_checker_valid
83694   attribute \src "ls180.v:1457.11-1457.41"
83695   wire width 3 \main_sdcore_crc16_inserter_cnt
83696   attribute \src "ls180.v:1833.11-1833.80"
83697   wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
83698   attribute \src "ls180.v:1834.5-1834.77"
83699   wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
83700   attribute \src "ls180.v:1463.6-1463.41"
83701   wire \main_sdcore_crc16_inserter_crc0_clr
83702   attribute \src "ls180.v:1462.12-1462.47"
83703   wire width 16 \main_sdcore_crc16_inserter_crc0_crc
83704   attribute \src "ls180.v:1458.12-1458.51"
83705   wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0
83706   attribute \src "ls180.v:1459.13-1459.52"
83707   wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1
83708   attribute \src "ls180.v:1460.13-1460.52"
83709   wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2
83710   attribute \src "ls180.v:1464.6-1464.44"
83711   wire \main_sdcore_crc16_inserter_crc0_enable
83712   attribute \src "ls180.v:1461.12-1461.47"
83713   wire width 2 \main_sdcore_crc16_inserter_crc0_val
83714   attribute \src "ls180.v:1470.6-1470.41"
83715   wire \main_sdcore_crc16_inserter_crc1_clr
83716   attribute \src "ls180.v:1469.12-1469.47"
83717   wire width 16 \main_sdcore_crc16_inserter_crc1_crc
83718   attribute \src "ls180.v:1465.12-1465.51"
83719   wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0
83720   attribute \src "ls180.v:1466.13-1466.52"
83721   wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1
83722   attribute \src "ls180.v:1467.13-1467.52"
83723   wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2
83724   attribute \src "ls180.v:1471.6-1471.44"
83725   wire \main_sdcore_crc16_inserter_crc1_enable
83726   attribute \src "ls180.v:1468.12-1468.47"
83727   wire width 2 \main_sdcore_crc16_inserter_crc1_val
83728   attribute \src "ls180.v:1477.6-1477.41"
83729   wire \main_sdcore_crc16_inserter_crc2_clr
83730   attribute \src "ls180.v:1476.12-1476.47"
83731   wire width 16 \main_sdcore_crc16_inserter_crc2_crc
83732   attribute \src "ls180.v:1472.12-1472.51"
83733   wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0
83734   attribute \src "ls180.v:1473.13-1473.52"
83735   wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1
83736   attribute \src "ls180.v:1474.13-1474.52"
83737   wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2
83738   attribute \src "ls180.v:1478.6-1478.44"
83739   wire \main_sdcore_crc16_inserter_crc2_enable
83740   attribute \src "ls180.v:1475.12-1475.47"
83741   wire width 2 \main_sdcore_crc16_inserter_crc2_val
83742   attribute \src "ls180.v:1484.6-1484.41"
83743   wire \main_sdcore_crc16_inserter_crc3_clr
83744   attribute \src "ls180.v:1483.12-1483.47"
83745   wire width 16 \main_sdcore_crc16_inserter_crc3_crc
83746   attribute \src "ls180.v:1479.12-1479.51"
83747   wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0
83748   attribute \src "ls180.v:1480.13-1480.52"
83749   wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1
83750   attribute \src "ls180.v:1481.13-1481.52"
83751   wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2
83752   attribute \src "ls180.v:1485.6-1485.44"
83753   wire \main_sdcore_crc16_inserter_crc3_enable
83754   attribute \src "ls180.v:1482.12-1482.47"
83755   wire width 2 \main_sdcore_crc16_inserter_crc3_val
83756   attribute \src "ls180.v:1486.12-1486.46"
83757   wire width 16 \main_sdcore_crc16_inserter_crctmp0
83758   attribute \src "ls180.v:1825.12-1825.85"
83759   wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
83760   attribute \src "ls180.v:1826.5-1826.81"
83761   wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
83762   attribute \src "ls180.v:1487.12-1487.46"
83763   wire width 16 \main_sdcore_crc16_inserter_crctmp1
83764   attribute \src "ls180.v:1827.12-1827.85"
83765   wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
83766   attribute \src "ls180.v:1828.5-1828.81"
83767   wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
83768   attribute \src "ls180.v:1488.12-1488.46"
83769   wire width 16 \main_sdcore_crc16_inserter_crctmp2
83770   attribute \src "ls180.v:1829.12-1829.85"
83771   wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
83772   attribute \src "ls180.v:1830.5-1830.81"
83773   wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
83774   attribute \src "ls180.v:1489.12-1489.46"
83775   wire width 16 \main_sdcore_crc16_inserter_crctmp3
83776   attribute \src "ls180.v:1831.12-1831.85"
83777   wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
83778   attribute \src "ls180.v:1832.5-1832.81"
83779   wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
83780   attribute \src "ls180.v:1449.6-1449.43"
83781   wire \main_sdcore_crc16_inserter_sink_first
83782   attribute \src "ls180.v:1450.6-1450.42"
83783   wire \main_sdcore_crc16_inserter_sink_last
83784   attribute \src "ls180.v:1451.12-1451.56"
83785   wire width 8 \main_sdcore_crc16_inserter_sink_payload_data
83786   attribute \src "ls180.v:1448.5-1448.42"
83787   wire \main_sdcore_crc16_inserter_sink_ready
83788   attribute \src "ls180.v:1447.6-1447.43"
83789   wire \main_sdcore_crc16_inserter_sink_valid
83790   attribute \src "ls180.v:1454.5-1454.44"
83791   wire \main_sdcore_crc16_inserter_source_first
83792   attribute \src "ls180.v:1455.5-1455.43"
83793   wire \main_sdcore_crc16_inserter_source_last
83794   attribute \src "ls180.v:1456.11-1456.57"
83795   wire width 8 \main_sdcore_crc16_inserter_source_payload_data
83796   attribute \src "ls180.v:1453.5-1453.44"
83797   wire \main_sdcore_crc16_inserter_source_ready
83798   attribute \src "ls180.v:1452.5-1452.44"
83799   wire \main_sdcore_crc16_inserter_source_valid
83800   attribute \src "ls180.v:1445.6-1445.35"
83801   wire \main_sdcore_crc7_inserter_clr
83802   attribute \src "ls180.v:1444.11-1444.40"
83803   wire width 7 \main_sdcore_crc7_inserter_crc
83804   attribute \src "ls180.v:1402.11-1402.44"
83805   wire width 7 \main_sdcore_crc7_inserter_crcreg0
83806   attribute \src "ls180.v:1403.12-1403.45"
83807   wire width 7 \main_sdcore_crc7_inserter_crcreg1
83808   attribute \src "ls180.v:1412.12-1412.46"
83809   wire width 7 \main_sdcore_crc7_inserter_crcreg10
83810   attribute \src "ls180.v:1413.12-1413.46"
83811   wire width 7 \main_sdcore_crc7_inserter_crcreg11
83812   attribute \src "ls180.v:1414.12-1414.46"
83813   wire width 7 \main_sdcore_crc7_inserter_crcreg12
83814   attribute \src "ls180.v:1415.12-1415.46"
83815   wire width 7 \main_sdcore_crc7_inserter_crcreg13
83816   attribute \src "ls180.v:1416.12-1416.46"
83817   wire width 7 \main_sdcore_crc7_inserter_crcreg14
83818   attribute \src "ls180.v:1417.12-1417.46"
83819   wire width 7 \main_sdcore_crc7_inserter_crcreg15
83820   attribute \src "ls180.v:1418.12-1418.46"
83821   wire width 7 \main_sdcore_crc7_inserter_crcreg16
83822   attribute \src "ls180.v:1419.12-1419.46"
83823   wire width 7 \main_sdcore_crc7_inserter_crcreg17
83824   attribute \src "ls180.v:1420.12-1420.46"
83825   wire width 7 \main_sdcore_crc7_inserter_crcreg18
83826   attribute \src "ls180.v:1421.12-1421.46"
83827   wire width 7 \main_sdcore_crc7_inserter_crcreg19
83828   attribute \src "ls180.v:1404.12-1404.45"
83829   wire width 7 \main_sdcore_crc7_inserter_crcreg2
83830   attribute \src "ls180.v:1422.12-1422.46"
83831   wire width 7 \main_sdcore_crc7_inserter_crcreg20
83832   attribute \src "ls180.v:1423.12-1423.46"
83833   wire width 7 \main_sdcore_crc7_inserter_crcreg21
83834   attribute \src "ls180.v:1424.12-1424.46"
83835   wire width 7 \main_sdcore_crc7_inserter_crcreg22
83836   attribute \src "ls180.v:1425.12-1425.46"
83837   wire width 7 \main_sdcore_crc7_inserter_crcreg23
83838   attribute \src "ls180.v:1426.12-1426.46"
83839   wire width 7 \main_sdcore_crc7_inserter_crcreg24
83840   attribute \src "ls180.v:1427.12-1427.46"
83841   wire width 7 \main_sdcore_crc7_inserter_crcreg25
83842   attribute \src "ls180.v:1428.12-1428.46"
83843   wire width 7 \main_sdcore_crc7_inserter_crcreg26
83844   attribute \src "ls180.v:1429.12-1429.46"
83845   wire width 7 \main_sdcore_crc7_inserter_crcreg27
83846   attribute \src "ls180.v:1430.12-1430.46"
83847   wire width 7 \main_sdcore_crc7_inserter_crcreg28
83848   attribute \src "ls180.v:1431.12-1431.46"
83849   wire width 7 \main_sdcore_crc7_inserter_crcreg29
83850   attribute \src "ls180.v:1405.12-1405.45"
83851   wire width 7 \main_sdcore_crc7_inserter_crcreg3
83852   attribute \src "ls180.v:1432.12-1432.46"
83853   wire width 7 \main_sdcore_crc7_inserter_crcreg30
83854   attribute \src "ls180.v:1433.12-1433.46"
83855   wire width 7 \main_sdcore_crc7_inserter_crcreg31
83856   attribute \src "ls180.v:1434.12-1434.46"
83857   wire width 7 \main_sdcore_crc7_inserter_crcreg32
83858   attribute \src "ls180.v:1435.12-1435.46"
83859   wire width 7 \main_sdcore_crc7_inserter_crcreg33
83860   attribute \src "ls180.v:1436.12-1436.46"
83861   wire width 7 \main_sdcore_crc7_inserter_crcreg34
83862   attribute \src "ls180.v:1437.12-1437.46"
83863   wire width 7 \main_sdcore_crc7_inserter_crcreg35
83864   attribute \src "ls180.v:1438.12-1438.46"
83865   wire width 7 \main_sdcore_crc7_inserter_crcreg36
83866   attribute \src "ls180.v:1439.12-1439.46"
83867   wire width 7 \main_sdcore_crc7_inserter_crcreg37
83868   attribute \src "ls180.v:1440.12-1440.46"
83869   wire width 7 \main_sdcore_crc7_inserter_crcreg38
83870   attribute \src "ls180.v:1441.12-1441.46"
83871   wire width 7 \main_sdcore_crc7_inserter_crcreg39
83872   attribute \src "ls180.v:1406.12-1406.45"
83873   wire width 7 \main_sdcore_crc7_inserter_crcreg4
83874   attribute \src "ls180.v:1442.12-1442.46"
83875   wire width 7 \main_sdcore_crc7_inserter_crcreg40
83876   attribute \src "ls180.v:1407.12-1407.45"
83877   wire width 7 \main_sdcore_crc7_inserter_crcreg5
83878   attribute \src "ls180.v:1408.12-1408.45"
83879   wire width 7 \main_sdcore_crc7_inserter_crcreg6
83880   attribute \src "ls180.v:1409.12-1409.45"
83881   wire width 7 \main_sdcore_crc7_inserter_crcreg7
83882   attribute \src "ls180.v:1410.12-1410.45"
83883   wire width 7 \main_sdcore_crc7_inserter_crcreg8
83884   attribute \src "ls180.v:1411.12-1411.45"
83885   wire width 7 \main_sdcore_crc7_inserter_crcreg9
83886   attribute \src "ls180.v:1446.6-1446.38"
83887   wire \main_sdcore_crc7_inserter_enable
83888   attribute \src "ls180.v:1443.13-1443.42"
83889   wire width 40 \main_sdcore_crc7_inserter_val
83890   attribute \src "ls180.v:1545.12-1545.34"
83891   wire width 32 \main_sdcore_data_count
83892   attribute \src "ls180.v:1843.12-1843.57"
83893   wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3
83894   attribute \src "ls180.v:1844.5-1844.53"
83895   wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3
83896   attribute \src "ls180.v:1546.5-1546.26"
83897   wire \main_sdcore_data_done
83898   attribute \src "ls180.v:1839.5-1839.49"
83899   wire \main_sdcore_data_done_sdcore_fsm_next_value1
83900   attribute \src "ls180.v:1840.5-1840.52"
83901   wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1
83902   attribute \src "ls180.v:1547.5-1547.27"
83903   wire \main_sdcore_data_error
83904   attribute \src "ls180.v:1849.5-1849.50"
83905   wire \main_sdcore_data_error_sdcore_fsm_next_value6
83906   attribute \src "ls180.v:1850.5-1850.53"
83907   wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6
83908   attribute \src "ls180.v:1396.12-1396.41"
83909   wire width 4 \main_sdcore_data_event_status
83910   attribute \src "ls180.v:1397.6-1397.31"
83911   wire \main_sdcore_data_event_we
83912   attribute \src "ls180.v:1548.5-1548.29"
83913   wire \main_sdcore_data_timeout
83914   attribute \src "ls180.v:1851.5-1851.52"
83915   wire \main_sdcore_data_timeout_sdcore_fsm_next_value7
83916   attribute \src "ls180.v:1852.5-1852.55"
83917   wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
83918   attribute \src "ls180.v:1544.12-1544.33"
83919   wire width 2 \main_sdcore_data_type
83920   attribute \src "ls180.v:1376.6-1376.33"
83921   wire \main_sdcore_sink_sink_first
83922   attribute \src "ls180.v:1377.6-1377.32"
83923   wire \main_sdcore_sink_sink_last
83924   attribute \src "ls180.v:1378.12-1378.46"
83925   wire width 8 \main_sdcore_sink_sink_payload_data
83926   attribute \src "ls180.v:1375.6-1375.33"
83927   wire \main_sdcore_sink_sink_ready
83928   attribute \src "ls180.v:1374.6-1374.33"
83929   wire \main_sdcore_sink_sink_valid
83930   attribute \src "ls180.v:1381.6-1381.37"
83931   wire \main_sdcore_source_source_first
83932   attribute \src "ls180.v:1382.6-1382.36"
83933   wire \main_sdcore_source_source_last
83934   attribute \src "ls180.v:1383.12-1383.50"
83935   wire width 8 \main_sdcore_source_source_payload_data
83936   attribute \src "ls180.v:1380.6-1380.37"
83937   wire \main_sdcore_source_source_ready
83938   attribute \src "ls180.v:1379.6-1379.37"
83939   wire \main_sdcore_source_source_valid
83940   attribute \src "ls180.v:1694.6-1694.38"
83941   wire \main_sdmem2block_converter_first
83942   attribute \src "ls180.v:1695.6-1695.37"
83943   wire \main_sdmem2block_converter_last
83944   attribute \src "ls180.v:1693.11-1693.41"
83945   wire width 2 \main_sdmem2block_converter_mux
83946   attribute \src "ls180.v:1684.6-1684.43"
83947   wire \main_sdmem2block_converter_sink_first
83948   attribute \src "ls180.v:1685.6-1685.42"
83949   wire \main_sdmem2block_converter_sink_last
83950   attribute \src "ls180.v:1686.13-1686.57"
83951   wire width 32 \main_sdmem2block_converter_sink_payload_data
83952   attribute \src "ls180.v:1683.6-1683.43"
83953   wire \main_sdmem2block_converter_sink_ready
83954   attribute \src "ls180.v:1682.6-1682.43"
83955   wire \main_sdmem2block_converter_sink_valid
83956   attribute \src "ls180.v:1689.6-1689.45"
83957   wire \main_sdmem2block_converter_source_first
83958   attribute \src "ls180.v:1690.6-1690.44"
83959   wire \main_sdmem2block_converter_source_last
83960   attribute \src "ls180.v:1691.11-1691.57"
83961   wire width 8 \main_sdmem2block_converter_source_payload_data
83962   attribute \src "ls180.v:1692.6-1692.65"
83963   wire \main_sdmem2block_converter_source_payload_valid_token_count
83964   attribute \src "ls180.v:1688.6-1688.45"
83965   wire \main_sdmem2block_converter_source_ready
83966   attribute \src "ls180.v:1687.6-1687.45"
83967   wire \main_sdmem2block_converter_source_valid
83968   attribute \src "ls180.v:1678.13-1678.38"
83969   wire width 32 \main_sdmem2block_dma_base
83970   attribute \src "ls180.v:1667.5-1667.33"
83971   wire \main_sdmem2block_dma_base_re
83972   attribute \src "ls180.v:1666.12-1666.45"
83973   wire width 64 \main_sdmem2block_dma_base_storage
83974   attribute \src "ls180.v:1665.12-1665.37"
83975   wire width 32 \main_sdmem2block_dma_data
83976   attribute \src "ls180.v:1861.12-1861.67"
83977   wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
83978   attribute \src "ls180.v:1862.5-1862.63"
83979   wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
83980   attribute \src "ls180.v:1672.5-1672.37"
83981   wire \main_sdmem2block_dma_done_status
83982   attribute \src "ls180.v:1673.6-1673.34"
83983   wire \main_sdmem2block_dma_done_we
83984   attribute \src "ls180.v:1671.5-1671.35"
83985   wire \main_sdmem2block_dma_enable_re
83986   attribute \src "ls180.v:1670.5-1670.40"
83987   wire \main_sdmem2block_dma_enable_storage
83988   attribute \src "ls180.v:1680.13-1680.40"
83989   wire width 32 \main_sdmem2block_dma_length
83990   attribute \src "ls180.v:1669.5-1669.35"
83991   wire \main_sdmem2block_dma_length_re
83992   attribute \src "ls180.v:1668.12-1668.47"
83993   wire width 32 \main_sdmem2block_dma_length_storage
83994   attribute \src "ls180.v:1675.5-1675.33"
83995   wire \main_sdmem2block_dma_loop_re
83996   attribute \src "ls180.v:1674.5-1674.38"
83997   wire \main_sdmem2block_dma_loop_storage
83998   attribute \src "ls180.v:1679.12-1679.39"
83999   wire width 32 \main_sdmem2block_dma_offset
84000   attribute \src "ls180.v:1865.12-1865.79"
84001   wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
84002   attribute \src "ls180.v:1866.5-1866.75"
84003   wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
84004   attribute \src "ls180.v:1676.13-1676.47"
84005   wire width 32 \main_sdmem2block_dma_offset_status
84006   attribute \src "ls180.v:1677.6-1677.36"
84007   wire \main_sdmem2block_dma_offset_we
84008   attribute \src "ls180.v:1681.6-1681.32"
84009   wire \main_sdmem2block_dma_reset
84010   attribute \src "ls180.v:1658.5-1658.35"
84011   wire \main_sdmem2block_dma_sink_last
84012   attribute \src "ls180.v:1659.12-1659.53"
84013   wire width 32 \main_sdmem2block_dma_sink_payload_address
84014   attribute \src "ls180.v:1657.5-1657.36"
84015   wire \main_sdmem2block_dma_sink_ready
84016   attribute \src "ls180.v:1656.5-1656.36"
84017   wire \main_sdmem2block_dma_sink_valid
84018   attribute \src "ls180.v:1662.5-1662.38"
84019   wire \main_sdmem2block_dma_source_first
84020   attribute \src "ls180.v:1663.5-1663.37"
84021   wire \main_sdmem2block_dma_source_last
84022   attribute \src "ls180.v:1664.12-1664.52"
84023   wire width 32 \main_sdmem2block_dma_source_payload_data
84024   attribute \src "ls180.v:1661.6-1661.39"
84025   wire \main_sdmem2block_dma_source_ready
84026   attribute \src "ls180.v:1660.5-1660.38"
84027   wire \main_sdmem2block_dma_source_valid
84028   attribute \src "ls180.v:1720.11-1720.40"
84029   wire width 5 \main_sdmem2block_fifo_consume
84030   attribute \src "ls180.v:1725.6-1725.35"
84031   wire \main_sdmem2block_fifo_do_read
84032   attribute \src "ls180.v:1729.6-1729.41"
84033   wire \main_sdmem2block_fifo_fifo_in_first
84034   attribute \src "ls180.v:1730.6-1730.40"
84035   wire \main_sdmem2block_fifo_fifo_in_last
84036   attribute \src "ls180.v:1728.12-1728.54"
84037   wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data
84038   attribute \src "ls180.v:1732.6-1732.42"
84039   wire \main_sdmem2block_fifo_fifo_out_first
84040   attribute \src "ls180.v:1733.6-1733.41"
84041   wire \main_sdmem2block_fifo_fifo_out_last
84042   attribute \src "ls180.v:1731.12-1731.55"
84043   wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data
84044   attribute \src "ls180.v:1717.11-1717.38"
84045   wire width 6 \main_sdmem2block_fifo_level
84046   attribute \src "ls180.v:1719.11-1719.40"
84047   wire width 5 \main_sdmem2block_fifo_produce
84048   attribute \src "ls180.v:1726.12-1726.44"
84049   wire width 5 \main_sdmem2block_fifo_rdport_adr
84050   attribute \src "ls180.v:1727.12-1727.46"
84051   wire width 10 \main_sdmem2block_fifo_rdport_dat_r
84052   attribute \src "ls180.v:1718.5-1718.34"
84053   wire \main_sdmem2block_fifo_replace
84054   attribute \src "ls180.v:1703.6-1703.38"
84055   wire \main_sdmem2block_fifo_sink_first
84056   attribute \src "ls180.v:1704.6-1704.37"
84057   wire \main_sdmem2block_fifo_sink_last
84058   attribute \src "ls180.v:1705.12-1705.51"
84059   wire width 8 \main_sdmem2block_fifo_sink_payload_data
84060   attribute \src "ls180.v:1702.6-1702.38"
84061   wire \main_sdmem2block_fifo_sink_ready
84062   attribute \src "ls180.v:1701.6-1701.38"
84063   wire \main_sdmem2block_fifo_sink_valid
84064   attribute \src "ls180.v:1708.6-1708.40"
84065   wire \main_sdmem2block_fifo_source_first
84066   attribute \src "ls180.v:1709.6-1709.39"
84067   wire \main_sdmem2block_fifo_source_last
84068   attribute \src "ls180.v:1710.12-1710.53"
84069   wire width 8 \main_sdmem2block_fifo_source_payload_data
84070   attribute \src "ls180.v:1707.6-1707.40"
84071   wire \main_sdmem2block_fifo_source_ready
84072   attribute \src "ls180.v:1706.6-1706.40"
84073   wire \main_sdmem2block_fifo_source_valid
84074   attribute \src "ls180.v:1715.12-1715.46"
84075   wire width 10 \main_sdmem2block_fifo_syncfifo_din
84076   attribute \src "ls180.v:1716.12-1716.47"
84077   wire width 10 \main_sdmem2block_fifo_syncfifo_dout
84078   attribute \src "ls180.v:1713.6-1713.39"
84079   wire \main_sdmem2block_fifo_syncfifo_re
84080   attribute \src "ls180.v:1714.6-1714.45"
84081   wire \main_sdmem2block_fifo_syncfifo_readable
84082   attribute \src "ls180.v:1711.6-1711.39"
84083   wire \main_sdmem2block_fifo_syncfifo_we
84084   attribute \src "ls180.v:1712.6-1712.45"
84085   wire \main_sdmem2block_fifo_syncfifo_writable
84086   attribute \src "ls180.v:1721.11-1721.43"
84087   wire width 5 \main_sdmem2block_fifo_wrport_adr
84088   attribute \src "ls180.v:1722.12-1722.46"
84089   wire width 10 \main_sdmem2block_fifo_wrport_dat_r
84090   attribute \src "ls180.v:1724.12-1724.46"
84091   wire width 10 \main_sdmem2block_fifo_wrport_dat_w
84092   attribute \src "ls180.v:1723.6-1723.37"
84093   wire \main_sdmem2block_fifo_wrport_we
84094   attribute \src "ls180.v:1653.6-1653.43"
84095   wire \main_sdmem2block_source_source_first0
84096   attribute \src "ls180.v:1698.6-1698.43"
84097   wire \main_sdmem2block_source_source_first1
84098   attribute \src "ls180.v:1654.6-1654.42"
84099   wire \main_sdmem2block_source_source_last0
84100   attribute \src "ls180.v:1699.6-1699.42"
84101   wire \main_sdmem2block_source_source_last1
84102   attribute \src "ls180.v:1655.12-1655.56"
84103   wire width 8 \main_sdmem2block_source_source_payload_data0
84104   attribute \src "ls180.v:1700.12-1700.56"
84105   wire width 8 \main_sdmem2block_source_source_payload_data1
84106   attribute \src "ls180.v:1652.6-1652.43"
84107   wire \main_sdmem2block_source_source_ready0
84108   attribute \src "ls180.v:1697.6-1697.43"
84109   wire \main_sdmem2block_source_source_ready1
84110   attribute \src "ls180.v:1651.6-1651.43"
84111   wire \main_sdmem2block_source_source_valid0
84112   attribute \src "ls180.v:1696.6-1696.43"
84113   wire \main_sdmem2block_source_source_valid1
84114   attribute \src "ls180.v:1102.6-1102.27"
84115   wire \main_sdphy_clocker_ce
84116   attribute \src "ls180.v:1101.5-1101.28"
84117   wire \main_sdphy_clocker_clk0
84118   attribute \src "ls180.v:1104.5-1104.28"
84119   wire \main_sdphy_clocker_clk1
84120   attribute \src "ls180.v:1105.5-1105.29"
84121   wire \main_sdphy_clocker_clk_d
84122   attribute \src "ls180.v:1103.11-1103.34"
84123   wire width 9 \main_sdphy_clocker_clks
84124   attribute \src "ls180.v:1099.5-1099.26"
84125   wire \main_sdphy_clocker_re
84126   attribute \src "ls180.v:1100.6-1100.29"
84127   wire \main_sdphy_clocker_stop
84128   attribute \src "ls180.v:1098.11-1098.37"
84129   wire width 9 \main_sdphy_clocker_storage
84130   attribute \src "ls180.v:1202.6-1202.41"
84131   wire \main_sdphy_cmdr_cmdr_buf_sink_first
84132   attribute \src "ls180.v:1203.6-1203.40"
84133   wire \main_sdphy_cmdr_cmdr_buf_sink_last
84134   attribute \src "ls180.v:1204.12-1204.54"
84135   wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data
84136   attribute \src "ls180.v:1201.6-1201.41"
84137   wire \main_sdphy_cmdr_cmdr_buf_sink_ready
84138   attribute \src "ls180.v:1200.6-1200.41"
84139   wire \main_sdphy_cmdr_cmdr_buf_sink_valid
84140   attribute \src "ls180.v:1207.5-1207.42"
84141   wire \main_sdphy_cmdr_cmdr_buf_source_first
84142   attribute \src "ls180.v:1208.5-1208.41"
84143   wire \main_sdphy_cmdr_cmdr_buf_source_last
84144   attribute \src "ls180.v:1209.11-1209.55"
84145   wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data
84146   attribute \src "ls180.v:1206.6-1206.43"
84147   wire \main_sdphy_cmdr_cmdr_buf_source_ready
84148   attribute \src "ls180.v:1205.5-1205.42"
84149   wire \main_sdphy_cmdr_cmdr_buf_source_valid
84150   attribute \src "ls180.v:1192.11-1192.47"
84151   wire width 3 \main_sdphy_cmdr_cmdr_converter_demux
84152   attribute \src "ls180.v:1193.6-1193.46"
84153   wire \main_sdphy_cmdr_cmdr_converter_load_part
84154   attribute \src "ls180.v:1183.5-1183.46"
84155   wire \main_sdphy_cmdr_cmdr_converter_sink_first
84156   attribute \src "ls180.v:1184.5-1184.45"
84157   wire \main_sdphy_cmdr_cmdr_converter_sink_last
84158   attribute \src "ls180.v:1185.6-1185.54"
84159   wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data
84160   attribute \src "ls180.v:1182.6-1182.47"
84161   wire \main_sdphy_cmdr_cmdr_converter_sink_ready
84162   attribute \src "ls180.v:1181.6-1181.47"
84163   wire \main_sdphy_cmdr_cmdr_converter_sink_valid
84164   attribute \src "ls180.v:1188.5-1188.48"
84165   wire \main_sdphy_cmdr_cmdr_converter_source_first
84166   attribute \src "ls180.v:1189.5-1189.47"
84167   wire \main_sdphy_cmdr_cmdr_converter_source_last
84168   attribute \src "ls180.v:1190.11-1190.61"
84169   wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data
84170   attribute \src "ls180.v:1191.11-1191.74"
84171   wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count
84172   attribute \src "ls180.v:1187.6-1187.49"
84173   wire \main_sdphy_cmdr_cmdr_converter_source_ready
84174   attribute \src "ls180.v:1186.6-1186.49"
84175   wire \main_sdphy_cmdr_cmdr_converter_source_valid
84176   attribute \src "ls180.v:1194.5-1194.46"
84177   wire \main_sdphy_cmdr_cmdr_converter_strobe_all
84178   attribute \src "ls180.v:1165.6-1165.40"
84179   wire \main_sdphy_cmdr_cmdr_pads_in_first
84180   attribute \src "ls180.v:1166.6-1166.39"
84181   wire \main_sdphy_cmdr_cmdr_pads_in_last
84182   attribute \src "ls180.v:1167.6-1167.46"
84183   wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk
84184   attribute \src "ls180.v:1168.6-1168.48"
84185   wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
84186   attribute \src "ls180.v:1169.6-1169.48"
84187   wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o
84188   attribute \src "ls180.v:1170.6-1170.49"
84189   wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe
84190   attribute \src "ls180.v:1171.12-1171.55"
84191   wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i
84192   attribute \src "ls180.v:1172.12-1172.55"
84193   wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o
84194   attribute \src "ls180.v:1173.6-1173.50"
84195   wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe
84196   attribute \src "ls180.v:1164.5-1164.39"
84197   wire \main_sdphy_cmdr_cmdr_pads_in_ready
84198   attribute \src "ls180.v:1163.6-1163.40"
84199   wire \main_sdphy_cmdr_cmdr_pads_in_valid
84200   attribute \src "ls180.v:1210.5-1210.31"
84201   wire \main_sdphy_cmdr_cmdr_reset
84202   attribute \src "ls180.v:1805.5-1805.59"
84203   wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
84204   attribute \src "ls180.v:1806.5-1806.62"
84205   wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
84206   attribute \src "ls180.v:1180.5-1180.29"
84207   wire \main_sdphy_cmdr_cmdr_run
84208   attribute \src "ls180.v:1176.6-1176.47"
84209   wire \main_sdphy_cmdr_cmdr_source_source_first0
84210   attribute \src "ls180.v:1197.6-1197.47"
84211   wire \main_sdphy_cmdr_cmdr_source_source_first1
84212   attribute \src "ls180.v:1177.6-1177.46"
84213   wire \main_sdphy_cmdr_cmdr_source_source_last0
84214   attribute \src "ls180.v:1198.6-1198.46"
84215   wire \main_sdphy_cmdr_cmdr_source_source_last1
84216   attribute \src "ls180.v:1178.12-1178.60"
84217   wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0
84218   attribute \src "ls180.v:1199.12-1199.60"
84219   wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1
84220   attribute \src "ls180.v:1175.5-1175.46"
84221   wire \main_sdphy_cmdr_cmdr_source_source_ready0
84222   attribute \src "ls180.v:1196.6-1196.47"
84223   wire \main_sdphy_cmdr_cmdr_source_source_ready1
84224   attribute \src "ls180.v:1174.6-1174.47"
84225   wire \main_sdphy_cmdr_cmdr_source_source_valid0
84226   attribute \src "ls180.v:1195.6-1195.47"
84227   wire \main_sdphy_cmdr_cmdr_source_source_valid1
84228   attribute \src "ls180.v:1179.6-1179.32"
84229   wire \main_sdphy_cmdr_cmdr_start
84230   attribute \src "ls180.v:1162.11-1162.32"
84231   wire width 8 \main_sdphy_cmdr_count
84232   attribute \src "ls180.v:1801.11-1801.60"
84233   wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
84234   attribute \src "ls180.v:1802.5-1802.57"
84235   wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
84236   attribute \src "ls180.v:1137.5-1137.42"
84237   wire \main_sdphy_cmdr_pads_in_pads_in_first
84238   attribute \src "ls180.v:1138.5-1138.41"
84239   wire \main_sdphy_cmdr_pads_in_pads_in_last
84240   attribute \src "ls180.v:1139.5-1139.48"
84241   wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk
84242   attribute \src "ls180.v:1140.6-1140.51"
84243   wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i
84244   attribute \src "ls180.v:1141.5-1141.50"
84245   wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o
84246   attribute \src "ls180.v:1142.5-1142.51"
84247   wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe
84248   attribute \src "ls180.v:1143.12-1143.58"
84249   wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
84250   attribute \src "ls180.v:1144.11-1144.57"
84251   wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
84252   attribute \src "ls180.v:1145.5-1145.52"
84253   wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
84254   attribute \src "ls180.v:1136.6-1136.43"
84255   wire \main_sdphy_cmdr_pads_in_pads_in_ready
84256   attribute \src "ls180.v:1135.6-1135.43"
84257   wire \main_sdphy_cmdr_pads_in_pads_in_valid
84258   attribute \src "ls180.v:1147.5-1147.41"
84259   wire \main_sdphy_cmdr_pads_out_payload_clk
84260   attribute \src "ls180.v:1148.5-1148.43"
84261   wire \main_sdphy_cmdr_pads_out_payload_cmd_o
84262   attribute \src "ls180.v:1149.5-1149.44"
84263   wire \main_sdphy_cmdr_pads_out_payload_cmd_oe
84264   attribute \src "ls180.v:1150.11-1150.50"
84265   wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o
84266   attribute \src "ls180.v:1151.5-1151.45"
84267   wire \main_sdphy_cmdr_pads_out_payload_data_oe
84268   attribute \src "ls180.v:1146.6-1146.36"
84269   wire \main_sdphy_cmdr_pads_out_ready
84270   attribute \src "ls180.v:1154.5-1154.30"
84271   wire \main_sdphy_cmdr_sink_last
84272   attribute \src "ls180.v:1155.11-1155.46"
84273   wire width 8 \main_sdphy_cmdr_sink_payload_length
84274   attribute \src "ls180.v:1153.5-1153.31"
84275   wire \main_sdphy_cmdr_sink_ready
84276   attribute \src "ls180.v:1152.5-1152.31"
84277   wire \main_sdphy_cmdr_sink_valid
84278   attribute \src "ls180.v:1158.5-1158.32"
84279   wire \main_sdphy_cmdr_source_last
84280   attribute \src "ls180.v:1159.11-1159.46"
84281   wire width 8 \main_sdphy_cmdr_source_payload_data
84282   attribute \src "ls180.v:1160.11-1160.48"
84283   wire width 3 \main_sdphy_cmdr_source_payload_status
84284   attribute \src "ls180.v:1157.5-1157.33"
84285   wire \main_sdphy_cmdr_source_ready
84286   attribute \src "ls180.v:1156.5-1156.33"
84287   wire \main_sdphy_cmdr_source_valid
84288   attribute \src "ls180.v:1161.12-1161.35"
84289   wire width 32 \main_sdphy_cmdr_timeout
84290   attribute \src "ls180.v:1803.12-1803.63"
84291   wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
84292   attribute \src "ls180.v:1804.5-1804.59"
84293   wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
84294   attribute \src "ls180.v:1134.11-1134.32"
84295   wire width 8 \main_sdphy_cmdw_count
84296   attribute \src "ls180.v:1797.11-1797.59"
84297   wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
84298   attribute \src "ls180.v:1798.5-1798.56"
84299   wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
84300   attribute \src "ls180.v:1133.5-1133.25"
84301   wire \main_sdphy_cmdw_done
84302   attribute \src "ls180.v:1121.6-1121.43"
84303   wire \main_sdphy_cmdw_pads_in_payload_cmd_i
84304   attribute \src "ls180.v:1122.12-1122.50"
84305   wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i
84306   attribute \src "ls180.v:1120.6-1120.35"
84307   wire \main_sdphy_cmdw_pads_in_valid
84308   attribute \src "ls180.v:1124.5-1124.41"
84309   wire \main_sdphy_cmdw_pads_out_payload_clk
84310   attribute \src "ls180.v:1125.5-1125.43"
84311   wire \main_sdphy_cmdw_pads_out_payload_cmd_o
84312   attribute \src "ls180.v:1126.5-1126.44"
84313   wire \main_sdphy_cmdw_pads_out_payload_cmd_oe
84314   attribute \src "ls180.v:1127.11-1127.50"
84315   wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o
84316   attribute \src "ls180.v:1128.5-1128.45"
84317   wire \main_sdphy_cmdw_pads_out_payload_data_oe
84318   attribute \src "ls180.v:1123.6-1123.36"
84319   wire \main_sdphy_cmdw_pads_out_ready
84320   attribute \src "ls180.v:1131.5-1131.30"
84321   wire \main_sdphy_cmdw_sink_last
84322   attribute \src "ls180.v:1132.11-1132.44"
84323   wire width 8 \main_sdphy_cmdw_sink_payload_data
84324   attribute \src "ls180.v:1130.5-1130.31"
84325   wire \main_sdphy_cmdw_sink_ready
84326   attribute \src "ls180.v:1129.5-1129.31"
84327   wire \main_sdphy_cmdw_sink_valid
84328   attribute \src "ls180.v:1318.11-1318.33"
84329   wire width 10 \main_sdphy_datar_count
84330   attribute \src "ls180.v:1817.11-1817.62"
84331   wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
84332   attribute \src "ls180.v:1818.5-1818.59"
84333   wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
84334   attribute \src "ls180.v:1358.6-1358.43"
84335   wire \main_sdphy_datar_datar_buf_sink_first
84336   attribute \src "ls180.v:1359.6-1359.42"
84337   wire \main_sdphy_datar_datar_buf_sink_last
84338   attribute \src "ls180.v:1360.12-1360.56"
84339   wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data
84340   attribute \src "ls180.v:1357.6-1357.43"
84341   wire \main_sdphy_datar_datar_buf_sink_ready
84342   attribute \src "ls180.v:1356.6-1356.43"
84343   wire \main_sdphy_datar_datar_buf_sink_valid
84344   attribute \src "ls180.v:1363.5-1363.44"
84345   wire \main_sdphy_datar_datar_buf_source_first
84346   attribute \src "ls180.v:1364.5-1364.43"
84347   wire \main_sdphy_datar_datar_buf_source_last
84348   attribute \src "ls180.v:1365.11-1365.57"
84349   wire width 8 \main_sdphy_datar_datar_buf_source_payload_data
84350   attribute \src "ls180.v:1362.6-1362.45"
84351   wire \main_sdphy_datar_datar_buf_source_ready
84352   attribute \src "ls180.v:1361.5-1361.44"
84353   wire \main_sdphy_datar_datar_buf_source_valid
84354   attribute \src "ls180.v:1348.5-1348.43"
84355   wire \main_sdphy_datar_datar_converter_demux
84356   attribute \src "ls180.v:1349.6-1349.48"
84357   wire \main_sdphy_datar_datar_converter_load_part
84358   attribute \src "ls180.v:1339.5-1339.48"
84359   wire \main_sdphy_datar_datar_converter_sink_first
84360   attribute \src "ls180.v:1340.5-1340.47"
84361   wire \main_sdphy_datar_datar_converter_sink_last
84362   attribute \src "ls180.v:1341.12-1341.62"
84363   wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data
84364   attribute \src "ls180.v:1338.6-1338.49"
84365   wire \main_sdphy_datar_datar_converter_sink_ready
84366   attribute \src "ls180.v:1337.6-1337.49"
84367   wire \main_sdphy_datar_datar_converter_sink_valid
84368   attribute \src "ls180.v:1344.5-1344.50"
84369   wire \main_sdphy_datar_datar_converter_source_first
84370   attribute \src "ls180.v:1345.5-1345.49"
84371   wire \main_sdphy_datar_datar_converter_source_last
84372   attribute \src "ls180.v:1346.11-1346.63"
84373   wire width 8 \main_sdphy_datar_datar_converter_source_payload_data
84374   attribute \src "ls180.v:1347.11-1347.76"
84375   wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count
84376   attribute \src "ls180.v:1343.6-1343.51"
84377   wire \main_sdphy_datar_datar_converter_source_ready
84378   attribute \src "ls180.v:1342.6-1342.51"
84379   wire \main_sdphy_datar_datar_converter_source_valid
84380   attribute \src "ls180.v:1350.5-1350.48"
84381   wire \main_sdphy_datar_datar_converter_strobe_all
84382   attribute \src "ls180.v:1321.6-1321.42"
84383   wire \main_sdphy_datar_datar_pads_in_first
84384   attribute \src "ls180.v:1322.6-1322.41"
84385   wire \main_sdphy_datar_datar_pads_in_last
84386   attribute \src "ls180.v:1323.6-1323.48"
84387   wire \main_sdphy_datar_datar_pads_in_payload_clk
84388   attribute \src "ls180.v:1324.6-1324.50"
84389   wire \main_sdphy_datar_datar_pads_in_payload_cmd_i
84390   attribute \src "ls180.v:1325.6-1325.50"
84391   wire \main_sdphy_datar_datar_pads_in_payload_cmd_o
84392   attribute \src "ls180.v:1326.6-1326.51"
84393   wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe
84394   attribute \src "ls180.v:1327.12-1327.57"
84395   wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i
84396   attribute \src "ls180.v:1328.12-1328.57"
84397   wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o
84398   attribute \src "ls180.v:1329.6-1329.52"
84399   wire \main_sdphy_datar_datar_pads_in_payload_data_oe
84400   attribute \src "ls180.v:1320.5-1320.41"
84401   wire \main_sdphy_datar_datar_pads_in_ready
84402   attribute \src "ls180.v:1319.6-1319.42"
84403   wire \main_sdphy_datar_datar_pads_in_valid
84404   attribute \src "ls180.v:1366.5-1366.33"
84405   wire \main_sdphy_datar_datar_reset
84406   attribute \src "ls180.v:1821.5-1821.62"
84407   wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
84408   attribute \src "ls180.v:1822.5-1822.65"
84409   wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
84410   attribute \src "ls180.v:1336.5-1336.31"
84411   wire \main_sdphy_datar_datar_run
84412   attribute \src "ls180.v:1332.6-1332.49"
84413   wire \main_sdphy_datar_datar_source_source_first0
84414   attribute \src "ls180.v:1353.6-1353.49"
84415   wire \main_sdphy_datar_datar_source_source_first1
84416   attribute \src "ls180.v:1333.6-1333.48"
84417   wire \main_sdphy_datar_datar_source_source_last0
84418   attribute \src "ls180.v:1354.6-1354.48"
84419   wire \main_sdphy_datar_datar_source_source_last1
84420   attribute \src "ls180.v:1334.12-1334.62"
84421   wire width 8 \main_sdphy_datar_datar_source_source_payload_data0
84422   attribute \src "ls180.v:1355.12-1355.62"
84423   wire width 8 \main_sdphy_datar_datar_source_source_payload_data1
84424   attribute \src "ls180.v:1331.5-1331.48"
84425   wire \main_sdphy_datar_datar_source_source_ready0
84426   attribute \src "ls180.v:1352.6-1352.49"
84427   wire \main_sdphy_datar_datar_source_source_ready1
84428   attribute \src "ls180.v:1330.6-1330.49"
84429   wire \main_sdphy_datar_datar_source_source_valid0
84430   attribute \src "ls180.v:1351.6-1351.49"
84431   wire \main_sdphy_datar_datar_source_source_valid1
84432   attribute \src "ls180.v:1335.6-1335.34"
84433   wire \main_sdphy_datar_datar_start
84434   attribute \src "ls180.v:1291.5-1291.43"
84435   wire \main_sdphy_datar_pads_in_pads_in_first
84436   attribute \src "ls180.v:1292.5-1292.42"
84437   wire \main_sdphy_datar_pads_in_pads_in_last
84438   attribute \src "ls180.v:1293.5-1293.49"
84439   wire \main_sdphy_datar_pads_in_pads_in_payload_clk
84440   attribute \src "ls180.v:1294.6-1294.52"
84441   wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i
84442   attribute \src "ls180.v:1295.5-1295.51"
84443   wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o
84444   attribute \src "ls180.v:1296.5-1296.52"
84445   wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe
84446   attribute \src "ls180.v:1297.12-1297.59"
84447   wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i
84448   attribute \src "ls180.v:1298.11-1298.58"
84449   wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o
84450   attribute \src "ls180.v:1299.5-1299.53"
84451   wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe
84452   attribute \src "ls180.v:1290.6-1290.44"
84453   wire \main_sdphy_datar_pads_in_pads_in_ready
84454   attribute \src "ls180.v:1289.6-1289.44"
84455   wire \main_sdphy_datar_pads_in_pads_in_valid
84456   attribute \src "ls180.v:1301.5-1301.42"
84457   wire \main_sdphy_datar_pads_out_payload_clk
84458   attribute \src "ls180.v:1302.5-1302.44"
84459   wire \main_sdphy_datar_pads_out_payload_cmd_o
84460   attribute \src "ls180.v:1303.5-1303.45"
84461   wire \main_sdphy_datar_pads_out_payload_cmd_oe
84462   attribute \src "ls180.v:1304.11-1304.51"
84463   wire width 4 \main_sdphy_datar_pads_out_payload_data_o
84464   attribute \src "ls180.v:1305.5-1305.46"
84465   wire \main_sdphy_datar_pads_out_payload_data_oe
84466   attribute \src "ls180.v:1300.6-1300.37"
84467   wire \main_sdphy_datar_pads_out_ready
84468   attribute \src "ls180.v:1308.5-1308.31"
84469   wire \main_sdphy_datar_sink_last
84470   attribute \src "ls180.v:1309.11-1309.53"
84471   wire width 10 \main_sdphy_datar_sink_payload_block_length
84472   attribute \src "ls180.v:1307.5-1307.32"
84473   wire \main_sdphy_datar_sink_ready
84474   attribute \src "ls180.v:1306.5-1306.32"
84475   wire \main_sdphy_datar_sink_valid
84476   attribute \src "ls180.v:1312.5-1312.34"
84477   wire \main_sdphy_datar_source_first
84478   attribute \src "ls180.v:1313.5-1313.33"
84479   wire \main_sdphy_datar_source_last
84480   attribute \src "ls180.v:1314.11-1314.47"
84481   wire width 8 \main_sdphy_datar_source_payload_data
84482   attribute \src "ls180.v:1315.11-1315.49"
84483   wire width 3 \main_sdphy_datar_source_payload_status
84484   attribute \src "ls180.v:1311.5-1311.34"
84485   wire \main_sdphy_datar_source_ready
84486   attribute \src "ls180.v:1310.5-1310.34"
84487   wire \main_sdphy_datar_source_valid
84488   attribute \src "ls180.v:1316.5-1316.26"
84489   wire \main_sdphy_datar_stop
84490   attribute \src "ls180.v:1317.12-1317.36"
84491   wire width 32 \main_sdphy_datar_timeout
84492   attribute \src "ls180.v:1819.12-1819.65"
84493   wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
84494   attribute \src "ls180.v:1820.5-1820.61"
84495   wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
84496   attribute \src "ls180.v:1226.11-1226.33"
84497   wire width 8 \main_sdphy_dataw_count
84498   attribute \src "ls180.v:1813.11-1813.54"
84499   wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value
84500   attribute \src "ls180.v:1814.5-1814.51"
84501   wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
84502   attribute \src "ls180.v:1280.6-1280.42"
84503   wire \main_sdphy_dataw_crcr_buf_sink_first
84504   attribute \src "ls180.v:1281.6-1281.41"
84505   wire \main_sdphy_dataw_crcr_buf_sink_last
84506   attribute \src "ls180.v:1282.12-1282.55"
84507   wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data
84508   attribute \src "ls180.v:1279.6-1279.42"
84509   wire \main_sdphy_dataw_crcr_buf_sink_ready
84510   attribute \src "ls180.v:1278.6-1278.42"
84511   wire \main_sdphy_dataw_crcr_buf_sink_valid
84512   attribute \src "ls180.v:1285.5-1285.43"
84513   wire \main_sdphy_dataw_crcr_buf_source_first
84514   attribute \src "ls180.v:1286.5-1286.42"
84515   wire \main_sdphy_dataw_crcr_buf_source_last
84516   attribute \src "ls180.v:1287.11-1287.56"
84517   wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data
84518   attribute \src "ls180.v:1284.6-1284.44"
84519   wire \main_sdphy_dataw_crcr_buf_source_ready
84520   attribute \src "ls180.v:1283.5-1283.43"
84521   wire \main_sdphy_dataw_crcr_buf_source_valid
84522   attribute \src "ls180.v:1270.11-1270.48"
84523   wire width 3 \main_sdphy_dataw_crcr_converter_demux
84524   attribute \src "ls180.v:1271.6-1271.47"
84525   wire \main_sdphy_dataw_crcr_converter_load_part
84526   attribute \src "ls180.v:1261.5-1261.47"
84527   wire \main_sdphy_dataw_crcr_converter_sink_first
84528   attribute \src "ls180.v:1262.5-1262.46"
84529   wire \main_sdphy_dataw_crcr_converter_sink_last
84530   attribute \src "ls180.v:1263.6-1263.55"
84531   wire \main_sdphy_dataw_crcr_converter_sink_payload_data
84532   attribute \src "ls180.v:1260.6-1260.48"
84533   wire \main_sdphy_dataw_crcr_converter_sink_ready
84534   attribute \src "ls180.v:1259.6-1259.48"
84535   wire \main_sdphy_dataw_crcr_converter_sink_valid
84536   attribute \src "ls180.v:1266.5-1266.49"
84537   wire \main_sdphy_dataw_crcr_converter_source_first
84538   attribute \src "ls180.v:1267.5-1267.48"
84539   wire \main_sdphy_dataw_crcr_converter_source_last
84540   attribute \src "ls180.v:1268.11-1268.62"
84541   wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data
84542   attribute \src "ls180.v:1269.11-1269.75"
84543   wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count
84544   attribute \src "ls180.v:1265.6-1265.50"
84545   wire \main_sdphy_dataw_crcr_converter_source_ready
84546   attribute \src "ls180.v:1264.6-1264.50"
84547   wire \main_sdphy_dataw_crcr_converter_source_valid
84548   attribute \src "ls180.v:1272.5-1272.47"
84549   wire \main_sdphy_dataw_crcr_converter_strobe_all
84550   attribute \src "ls180.v:1243.6-1243.41"
84551   wire \main_sdphy_dataw_crcr_pads_in_first
84552   attribute \src "ls180.v:1244.6-1244.40"
84553   wire \main_sdphy_dataw_crcr_pads_in_last
84554   attribute \src "ls180.v:1245.6-1245.47"
84555   wire \main_sdphy_dataw_crcr_pads_in_payload_clk
84556   attribute \src "ls180.v:1246.6-1246.49"
84557   wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i
84558   attribute \src "ls180.v:1247.6-1247.49"
84559   wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o
84560   attribute \src "ls180.v:1248.6-1248.50"
84561   wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe
84562   attribute \src "ls180.v:1249.12-1249.56"
84563   wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i
84564   attribute \src "ls180.v:1250.12-1250.56"
84565   wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o
84566   attribute \src "ls180.v:1251.6-1251.51"
84567   wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe
84568   attribute \src "ls180.v:1242.5-1242.40"
84569   wire \main_sdphy_dataw_crcr_pads_in_ready
84570   attribute \src "ls180.v:1241.6-1241.41"
84571   wire \main_sdphy_dataw_crcr_pads_in_valid
84572   attribute \src "ls180.v:1288.5-1288.32"
84573   wire \main_sdphy_dataw_crcr_reset
84574   attribute \src "ls180.v:1809.5-1809.59"
84575   wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
84576   attribute \src "ls180.v:1810.5-1810.62"
84577   wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
84578   attribute \src "ls180.v:1258.5-1258.30"
84579   wire \main_sdphy_dataw_crcr_run
84580   attribute \src "ls180.v:1254.6-1254.48"
84581   wire \main_sdphy_dataw_crcr_source_source_first0
84582   attribute \src "ls180.v:1275.6-1275.48"
84583   wire \main_sdphy_dataw_crcr_source_source_first1
84584   attribute \src "ls180.v:1255.6-1255.47"
84585   wire \main_sdphy_dataw_crcr_source_source_last0
84586   attribute \src "ls180.v:1276.6-1276.47"
84587   wire \main_sdphy_dataw_crcr_source_source_last1
84588   attribute \src "ls180.v:1256.12-1256.61"
84589   wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0
84590   attribute \src "ls180.v:1277.12-1277.61"
84591   wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1
84592   attribute \src "ls180.v:1253.5-1253.47"
84593   wire \main_sdphy_dataw_crcr_source_source_ready0
84594   attribute \src "ls180.v:1274.6-1274.48"
84595   wire \main_sdphy_dataw_crcr_source_source_ready1
84596   attribute \src "ls180.v:1252.6-1252.48"
84597   wire \main_sdphy_dataw_crcr_source_source_valid0
84598   attribute \src "ls180.v:1273.6-1273.48"
84599   wire \main_sdphy_dataw_crcr_source_source_valid1
84600   attribute \src "ls180.v:1257.6-1257.33"
84601   wire \main_sdphy_dataw_crcr_start
84602   attribute \src "ls180.v:1240.5-1240.27"
84603   wire \main_sdphy_dataw_error
84604   attribute \src "ls180.v:1229.5-1229.43"
84605   wire \main_sdphy_dataw_pads_in_pads_in_first
84606   attribute \src "ls180.v:1230.5-1230.42"
84607   wire \main_sdphy_dataw_pads_in_pads_in_last
84608   attribute \src "ls180.v:1231.5-1231.49"
84609   wire \main_sdphy_dataw_pads_in_pads_in_payload_clk
84610   attribute \src "ls180.v:1232.5-1232.51"
84611   wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i
84612   attribute \src "ls180.v:1233.5-1233.51"
84613   wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o
84614   attribute \src "ls180.v:1234.5-1234.52"
84615   wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe
84616   attribute \src "ls180.v:1235.11-1235.58"
84617   wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i
84618   attribute \src "ls180.v:1236.11-1236.58"
84619   wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o
84620   attribute \src "ls180.v:1237.5-1237.53"
84621   wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
84622   attribute \src "ls180.v:1228.6-1228.44"
84623   wire \main_sdphy_dataw_pads_in_pads_in_ready
84624   attribute \src "ls180.v:1227.5-1227.43"
84625   wire \main_sdphy_dataw_pads_in_pads_in_valid
84626   attribute \src "ls180.v:1212.6-1212.44"
84627   wire \main_sdphy_dataw_pads_in_payload_cmd_i
84628   attribute \src "ls180.v:1213.12-1213.51"
84629   wire width 4 \main_sdphy_dataw_pads_in_payload_data_i
84630   attribute \src "ls180.v:1211.6-1211.36"
84631   wire \main_sdphy_dataw_pads_in_valid
84632   attribute \src "ls180.v:1215.5-1215.42"
84633   wire \main_sdphy_dataw_pads_out_payload_clk
84634   attribute \src "ls180.v:1216.5-1216.44"
84635   wire \main_sdphy_dataw_pads_out_payload_cmd_o
84636   attribute \src "ls180.v:1217.5-1217.45"
84637   wire \main_sdphy_dataw_pads_out_payload_cmd_oe
84638   attribute \src "ls180.v:1218.11-1218.51"
84639   wire width 4 \main_sdphy_dataw_pads_out_payload_data_o
84640   attribute \src "ls180.v:1219.5-1219.46"
84641   wire \main_sdphy_dataw_pads_out_payload_data_oe
84642   attribute \src "ls180.v:1214.6-1214.37"
84643   wire \main_sdphy_dataw_pads_out_ready
84644   attribute \src "ls180.v:1222.5-1222.32"
84645   wire \main_sdphy_dataw_sink_first
84646   attribute \src "ls180.v:1223.5-1223.31"
84647   wire \main_sdphy_dataw_sink_last
84648   attribute \src "ls180.v:1224.11-1224.45"
84649   wire width 8 \main_sdphy_dataw_sink_payload_data
84650   attribute \src "ls180.v:1221.5-1221.32"
84651   wire \main_sdphy_dataw_sink_ready
84652   attribute \src "ls180.v:1220.5-1220.32"
84653   wire \main_sdphy_dataw_sink_valid
84654   attribute \src "ls180.v:1238.5-1238.27"
84655   wire \main_sdphy_dataw_start
84656   attribute \src "ls180.v:1225.5-1225.26"
84657   wire \main_sdphy_dataw_stop
84658   attribute \src "ls180.v:1239.5-1239.27"
84659   wire \main_sdphy_dataw_valid
84660   attribute \src "ls180.v:1119.11-1119.32"
84661   wire width 8 \main_sdphy_init_count
84662   attribute \src "ls180.v:1793.11-1793.59"
84663   wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value
84664   attribute \src "ls180.v:1794.5-1794.56"
84665   wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
84666   attribute \src "ls180.v:1107.6-1107.34"
84667   wire \main_sdphy_init_initialize_r
84668   attribute \src "ls180.v:1106.6-1106.35"
84669   wire \main_sdphy_init_initialize_re
84670   attribute \src "ls180.v:1109.5-1109.33"
84671   wire \main_sdphy_init_initialize_w
84672   attribute \src "ls180.v:1108.6-1108.35"
84673   wire \main_sdphy_init_initialize_we
84674   attribute \src "ls180.v:1111.6-1111.43"
84675   wire \main_sdphy_init_pads_in_payload_cmd_i
84676   attribute \src "ls180.v:1112.12-1112.50"
84677   wire width 4 \main_sdphy_init_pads_in_payload_data_i
84678   attribute \src "ls180.v:1110.6-1110.35"
84679   wire \main_sdphy_init_pads_in_valid
84680   attribute \src "ls180.v:1114.5-1114.41"
84681   wire \main_sdphy_init_pads_out_payload_clk
84682   attribute \src "ls180.v:1115.5-1115.43"
84683   wire \main_sdphy_init_pads_out_payload_cmd_o
84684   attribute \src "ls180.v:1116.5-1116.44"
84685   wire \main_sdphy_init_pads_out_payload_cmd_oe
84686   attribute \src "ls180.v:1117.11-1117.50"
84687   wire width 4 \main_sdphy_init_pads_out_payload_data_o
84688   attribute \src "ls180.v:1118.5-1118.45"
84689   wire \main_sdphy_init_pads_out_payload_data_oe
84690   attribute \src "ls180.v:1113.6-1113.36"
84691   wire \main_sdphy_init_pads_out_ready
84692   attribute \src "ls180.v:1367.6-1367.27"
84693   wire \main_sdphy_sdpads_clk
84694   attribute \src "ls180.v:1368.5-1368.28"
84695   wire \main_sdphy_sdpads_cmd_i
84696   attribute \src "ls180.v:1369.6-1369.29"
84697   wire \main_sdphy_sdpads_cmd_o
84698   attribute \src "ls180.v:1370.6-1370.30"
84699   wire \main_sdphy_sdpads_cmd_oe
84700   attribute \src "ls180.v:1371.11-1371.35"
84701   wire width 4 \main_sdphy_sdpads_data_i
84702   attribute \src "ls180.v:1372.12-1372.36"
84703   wire width 4 \main_sdphy_sdpads_data_o
84704   attribute \src "ls180.v:1373.6-1373.31"
84705   wire \main_sdphy_sdpads_data_oe
84706   attribute \src "ls180.v:1096.6-1096.23"
84707   wire \main_sdphy_status
84708   attribute \src "ls180.v:1097.6-1097.19"
84709   wire \main_sdphy_we
84710   attribute \src "ls180.v:331.5-331.26"
84711   wire \main_sdram_address_re
84712   attribute \src "ls180.v:330.12-330.38"
84713   wire width 13 \main_sdram_address_storage
84714   attribute \src "ls180.v:333.5-333.27"
84715   wire \main_sdram_baddress_re
84716   attribute \src "ls180.v:332.11-332.38"
84717   wire width 2 \main_sdram_baddress_storage
84718   attribute \src "ls180.v:429.5-429.43"
84719   wire \main_sdram_bankmachine0_auto_precharge
84720   attribute \src "ls180.v:451.11-451.63"
84721   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
84722   attribute \src "ls180.v:456.6-456.58"
84723   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
84724   attribute \src "ls180.v:461.6-461.64"
84725   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first
84726   attribute \src "ls180.v:462.6-462.63"
84727   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last
84728   attribute \src "ls180.v:460.13-460.78"
84729   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr
84730   attribute \src "ls180.v:459.6-459.69"
84731   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we
84732   attribute \src "ls180.v:465.6-465.65"
84733   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first
84734   attribute \src "ls180.v:466.6-466.64"
84735   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last
84736   attribute \src "ls180.v:464.13-464.79"
84737   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
84738   attribute \src "ls180.v:463.6-463.70"
84739   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we
84740   attribute \src "ls180.v:448.11-448.61"
84741   wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level
84742   attribute \src "ls180.v:450.11-450.63"
84743   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
84744   attribute \src "ls180.v:457.12-457.67"
84745   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
84746   attribute \src "ls180.v:458.13-458.70"
84747   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
84748   attribute \src "ls180.v:449.5-449.57"
84749   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
84750   attribute \src "ls180.v:432.5-432.60"
84751   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first
84752   attribute \src "ls180.v:433.5-433.59"
84753   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last
84754   attribute \src "ls180.v:435.13-435.75"
84755   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr
84756   attribute \src "ls180.v:434.6-434.66"
84757   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we
84758   attribute \src "ls180.v:431.6-431.61"
84759   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
84760   attribute \src "ls180.v:430.6-430.61"
84761   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid
84762   attribute \src "ls180.v:438.6-438.63"
84763   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first
84764   attribute \src "ls180.v:439.6-439.62"
84765   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
84766   attribute \src "ls180.v:441.13-441.77"
84767   wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
84768   attribute \src "ls180.v:440.6-440.68"
84769   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
84770   attribute \src "ls180.v:437.6-437.63"
84771   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
84772   attribute \src "ls180.v:436.6-436.63"
84773   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
84774   attribute \src "ls180.v:446.13-446.71"
84775   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
84776   attribute \src "ls180.v:447.13-447.72"
84777   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
84778   attribute \src "ls180.v:444.6-444.63"
84779   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
84780   attribute \src "ls180.v:445.6-445.69"
84781   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
84782   attribute \src "ls180.v:442.6-442.63"
84783   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
84784   attribute \src "ls180.v:443.6-443.69"
84785   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
84786   attribute \src "ls180.v:452.11-452.66"
84787   wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
84788   attribute \src "ls180.v:453.13-453.70"
84789   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r
84790   attribute \src "ls180.v:455.13-455.70"
84791   wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
84792   attribute \src "ls180.v:454.6-454.60"
84793   wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
84794   attribute \src "ls180.v:469.6-469.51"
84795   wire \main_sdram_bankmachine0_cmd_buffer_sink_first
84796   attribute \src "ls180.v:470.6-470.50"
84797   wire \main_sdram_bankmachine0_cmd_buffer_sink_last
84798   attribute \src "ls180.v:472.13-472.65"
84799   wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
84800   attribute \src "ls180.v:471.6-471.56"
84801   wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we
84802   attribute \src "ls180.v:468.6-468.51"
84803   wire \main_sdram_bankmachine0_cmd_buffer_sink_ready
84804   attribute \src "ls180.v:467.6-467.51"
84805   wire \main_sdram_bankmachine0_cmd_buffer_sink_valid
84806   attribute \src "ls180.v:475.5-475.52"
84807   wire \main_sdram_bankmachine0_cmd_buffer_source_first
84808   attribute \src "ls180.v:476.5-476.51"
84809   wire \main_sdram_bankmachine0_cmd_buffer_source_last
84810   attribute \src "ls180.v:478.12-478.66"
84811   wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr
84812   attribute \src "ls180.v:477.5-477.57"
84813   wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we
84814   attribute \src "ls180.v:474.6-474.53"
84815   wire \main_sdram_bankmachine0_cmd_buffer_source_ready
84816   attribute \src "ls180.v:473.5-473.52"
84817   wire \main_sdram_bankmachine0_cmd_buffer_source_valid
84818   attribute \src "ls180.v:421.12-421.49"
84819   wire width 13 \main_sdram_bankmachine0_cmd_payload_a
84820   attribute \src "ls180.v:422.12-422.50"
84821   wire width 2 \main_sdram_bankmachine0_cmd_payload_ba
84822   attribute \src "ls180.v:423.5-423.44"
84823   wire \main_sdram_bankmachine0_cmd_payload_cas
84824   attribute \src "ls180.v:426.5-426.47"
84825   wire \main_sdram_bankmachine0_cmd_payload_is_cmd
84826   attribute \src "ls180.v:427.5-427.48"
84827   wire \main_sdram_bankmachine0_cmd_payload_is_read
84828   attribute \src "ls180.v:428.5-428.49"
84829   wire \main_sdram_bankmachine0_cmd_payload_is_write
84830   attribute \src "ls180.v:424.5-424.44"
84831   wire \main_sdram_bankmachine0_cmd_payload_ras
84832   attribute \src "ls180.v:425.5-425.43"
84833   wire \main_sdram_bankmachine0_cmd_payload_we
84834   attribute \src "ls180.v:420.5-420.38"
84835   wire \main_sdram_bankmachine0_cmd_ready
84836   attribute \src "ls180.v:419.5-419.38"
84837   wire \main_sdram_bankmachine0_cmd_valid
84838   attribute \src "ls180.v:418.5-418.40"
84839   wire \main_sdram_bankmachine0_refresh_gnt
84840   attribute \src "ls180.v:417.6-417.41"
84841   wire \main_sdram_bankmachine0_refresh_req
84842   attribute \src "ls180.v:413.13-413.45"
84843   wire width 22 \main_sdram_bankmachine0_req_addr
84844   attribute \src "ls180.v:414.6-414.38"
84845   wire \main_sdram_bankmachine0_req_lock
84846   attribute \src "ls180.v:416.5-416.44"
84847   wire \main_sdram_bankmachine0_req_rdata_valid
84848   attribute \src "ls180.v:411.6-411.39"
84849   wire \main_sdram_bankmachine0_req_ready
84850   attribute \src "ls180.v:410.6-410.39"
84851   wire \main_sdram_bankmachine0_req_valid
84852   attribute \src "ls180.v:415.5-415.44"
84853   wire \main_sdram_bankmachine0_req_wdata_ready
84854   attribute \src "ls180.v:412.6-412.36"
84855   wire \main_sdram_bankmachine0_req_we
84856   attribute \src "ls180.v:479.12-479.39"
84857   wire width 13 \main_sdram_bankmachine0_row
84858   attribute \src "ls180.v:483.5-483.38"
84859   wire \main_sdram_bankmachine0_row_close
84860   attribute \src "ls180.v:484.5-484.47"
84861   wire \main_sdram_bankmachine0_row_col_n_addr_sel
84862   attribute \src "ls180.v:481.6-481.37"
84863   wire \main_sdram_bankmachine0_row_hit
84864   attribute \src "ls180.v:482.5-482.37"
84865   wire \main_sdram_bankmachine0_row_open
84866   attribute \src "ls180.v:480.5-480.39"
84867   wire \main_sdram_bankmachine0_row_opened
84868   attribute \no_retiming "true"
84869   attribute \src "ls180.v:491.32-491.69"
84870   wire \main_sdram_bankmachine0_trascon_ready
84871   attribute \src "ls180.v:490.6-490.43"
84872   wire \main_sdram_bankmachine0_trascon_valid
84873   attribute \no_retiming "true"
84874   attribute \src "ls180.v:489.32-489.68"
84875   wire \main_sdram_bankmachine0_trccon_ready
84876   attribute \src "ls180.v:488.6-488.42"
84877   wire \main_sdram_bankmachine0_trccon_valid
84878   attribute \src "ls180.v:487.11-487.48"
84879   wire width 3 \main_sdram_bankmachine0_twtpcon_count
84880   attribute \no_retiming "true"
84881   attribute \src "ls180.v:486.32-486.69"
84882   wire \main_sdram_bankmachine0_twtpcon_ready
84883   attribute \src "ls180.v:485.6-485.43"
84884   wire \main_sdram_bankmachine0_twtpcon_valid
84885   attribute \src "ls180.v:511.5-511.43"
84886   wire \main_sdram_bankmachine1_auto_precharge
84887   attribute \src "ls180.v:533.11-533.63"
84888   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
84889   attribute \src "ls180.v:538.6-538.58"
84890   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
84891   attribute \src "ls180.v:543.6-543.64"
84892   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first
84893   attribute \src "ls180.v:544.6-544.63"
84894   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last
84895   attribute \src "ls180.v:542.13-542.78"
84896   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr
84897   attribute \src "ls180.v:541.6-541.69"
84898   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we
84899   attribute \src "ls180.v:547.6-547.65"
84900   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first
84901   attribute \src "ls180.v:548.6-548.64"
84902   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last
84903   attribute \src "ls180.v:546.13-546.79"
84904   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
84905   attribute \src "ls180.v:545.6-545.70"
84906   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we
84907   attribute \src "ls180.v:530.11-530.61"
84908   wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level
84909   attribute \src "ls180.v:532.11-532.63"
84910   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
84911   attribute \src "ls180.v:539.12-539.67"
84912   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
84913   attribute \src "ls180.v:540.13-540.70"
84914   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
84915   attribute \src "ls180.v:531.5-531.57"
84916   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
84917   attribute \src "ls180.v:514.5-514.60"
84918   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first
84919   attribute \src "ls180.v:515.5-515.59"
84920   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last
84921   attribute \src "ls180.v:517.13-517.75"
84922   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr
84923   attribute \src "ls180.v:516.6-516.66"
84924   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we
84925   attribute \src "ls180.v:513.6-513.61"
84926   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
84927   attribute \src "ls180.v:512.6-512.61"
84928   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid
84929   attribute \src "ls180.v:520.6-520.63"
84930   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first
84931   attribute \src "ls180.v:521.6-521.62"
84932   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
84933   attribute \src "ls180.v:523.13-523.77"
84934   wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
84935   attribute \src "ls180.v:522.6-522.68"
84936   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
84937   attribute \src "ls180.v:519.6-519.63"
84938   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
84939   attribute \src "ls180.v:518.6-518.63"
84940   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
84941   attribute \src "ls180.v:528.13-528.71"
84942   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
84943   attribute \src "ls180.v:529.13-529.72"
84944   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
84945   attribute \src "ls180.v:526.6-526.63"
84946   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
84947   attribute \src "ls180.v:527.6-527.69"
84948   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
84949   attribute \src "ls180.v:524.6-524.63"
84950   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
84951   attribute \src "ls180.v:525.6-525.69"
84952   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
84953   attribute \src "ls180.v:534.11-534.66"
84954   wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
84955   attribute \src "ls180.v:535.13-535.70"
84956   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r
84957   attribute \src "ls180.v:537.13-537.70"
84958   wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
84959   attribute \src "ls180.v:536.6-536.60"
84960   wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
84961   attribute \src "ls180.v:551.6-551.51"
84962   wire \main_sdram_bankmachine1_cmd_buffer_sink_first
84963   attribute \src "ls180.v:552.6-552.50"
84964   wire \main_sdram_bankmachine1_cmd_buffer_sink_last
84965   attribute \src "ls180.v:554.13-554.65"
84966   wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
84967   attribute \src "ls180.v:553.6-553.56"
84968   wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we
84969   attribute \src "ls180.v:550.6-550.51"
84970   wire \main_sdram_bankmachine1_cmd_buffer_sink_ready
84971   attribute \src "ls180.v:549.6-549.51"
84972   wire \main_sdram_bankmachine1_cmd_buffer_sink_valid
84973   attribute \src "ls180.v:557.5-557.52"
84974   wire \main_sdram_bankmachine1_cmd_buffer_source_first
84975   attribute \src "ls180.v:558.5-558.51"
84976   wire \main_sdram_bankmachine1_cmd_buffer_source_last
84977   attribute \src "ls180.v:560.12-560.66"
84978   wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr
84979   attribute \src "ls180.v:559.5-559.57"
84980   wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we
84981   attribute \src "ls180.v:556.6-556.53"
84982   wire \main_sdram_bankmachine1_cmd_buffer_source_ready
84983   attribute \src "ls180.v:555.5-555.52"
84984   wire \main_sdram_bankmachine1_cmd_buffer_source_valid
84985   attribute \src "ls180.v:503.12-503.49"
84986   wire width 13 \main_sdram_bankmachine1_cmd_payload_a
84987   attribute \src "ls180.v:504.12-504.50"
84988   wire width 2 \main_sdram_bankmachine1_cmd_payload_ba
84989   attribute \src "ls180.v:505.5-505.44"
84990   wire \main_sdram_bankmachine1_cmd_payload_cas
84991   attribute \src "ls180.v:508.5-508.47"
84992   wire \main_sdram_bankmachine1_cmd_payload_is_cmd
84993   attribute \src "ls180.v:509.5-509.48"
84994   wire \main_sdram_bankmachine1_cmd_payload_is_read
84995   attribute \src "ls180.v:510.5-510.49"
84996   wire \main_sdram_bankmachine1_cmd_payload_is_write
84997   attribute \src "ls180.v:506.5-506.44"
84998   wire \main_sdram_bankmachine1_cmd_payload_ras
84999   attribute \src "ls180.v:507.5-507.43"
85000   wire \main_sdram_bankmachine1_cmd_payload_we
85001   attribute \src "ls180.v:502.5-502.38"
85002   wire \main_sdram_bankmachine1_cmd_ready
85003   attribute \src "ls180.v:501.5-501.38"
85004   wire \main_sdram_bankmachine1_cmd_valid
85005   attribute \src "ls180.v:500.5-500.40"
85006   wire \main_sdram_bankmachine1_refresh_gnt
85007   attribute \src "ls180.v:499.6-499.41"
85008   wire \main_sdram_bankmachine1_refresh_req
85009   attribute \src "ls180.v:495.13-495.45"
85010   wire width 22 \main_sdram_bankmachine1_req_addr
85011   attribute \src "ls180.v:496.6-496.38"
85012   wire \main_sdram_bankmachine1_req_lock
85013   attribute \src "ls180.v:498.5-498.44"
85014   wire \main_sdram_bankmachine1_req_rdata_valid
85015   attribute \src "ls180.v:493.6-493.39"
85016   wire \main_sdram_bankmachine1_req_ready
85017   attribute \src "ls180.v:492.6-492.39"
85018   wire \main_sdram_bankmachine1_req_valid
85019   attribute \src "ls180.v:497.5-497.44"
85020   wire \main_sdram_bankmachine1_req_wdata_ready
85021   attribute \src "ls180.v:494.6-494.36"
85022   wire \main_sdram_bankmachine1_req_we
85023   attribute \src "ls180.v:561.12-561.39"
85024   wire width 13 \main_sdram_bankmachine1_row
85025   attribute \src "ls180.v:565.5-565.38"
85026   wire \main_sdram_bankmachine1_row_close
85027   attribute \src "ls180.v:566.5-566.47"
85028   wire \main_sdram_bankmachine1_row_col_n_addr_sel
85029   attribute \src "ls180.v:563.6-563.37"
85030   wire \main_sdram_bankmachine1_row_hit
85031   attribute \src "ls180.v:564.5-564.37"
85032   wire \main_sdram_bankmachine1_row_open
85033   attribute \src "ls180.v:562.5-562.39"
85034   wire \main_sdram_bankmachine1_row_opened
85035   attribute \no_retiming "true"
85036   attribute \src "ls180.v:573.32-573.69"
85037   wire \main_sdram_bankmachine1_trascon_ready
85038   attribute \src "ls180.v:572.6-572.43"
85039   wire \main_sdram_bankmachine1_trascon_valid
85040   attribute \no_retiming "true"
85041   attribute \src "ls180.v:571.32-571.68"
85042   wire \main_sdram_bankmachine1_trccon_ready
85043   attribute \src "ls180.v:570.6-570.42"
85044   wire \main_sdram_bankmachine1_trccon_valid
85045   attribute \src "ls180.v:569.11-569.48"
85046   wire width 3 \main_sdram_bankmachine1_twtpcon_count
85047   attribute \no_retiming "true"
85048   attribute \src "ls180.v:568.32-568.69"
85049   wire \main_sdram_bankmachine1_twtpcon_ready
85050   attribute \src "ls180.v:567.6-567.43"
85051   wire \main_sdram_bankmachine1_twtpcon_valid
85052   attribute \src "ls180.v:593.5-593.43"
85053   wire \main_sdram_bankmachine2_auto_precharge
85054   attribute \src "ls180.v:615.11-615.63"
85055   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
85056   attribute \src "ls180.v:620.6-620.58"
85057   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
85058   attribute \src "ls180.v:625.6-625.64"
85059   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first
85060   attribute \src "ls180.v:626.6-626.63"
85061   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last
85062   attribute \src "ls180.v:624.13-624.78"
85063   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr
85064   attribute \src "ls180.v:623.6-623.69"
85065   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we
85066   attribute \src "ls180.v:629.6-629.65"
85067   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first
85068   attribute \src "ls180.v:630.6-630.64"
85069   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last
85070   attribute \src "ls180.v:628.13-628.79"
85071   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
85072   attribute \src "ls180.v:627.6-627.70"
85073   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we
85074   attribute \src "ls180.v:612.11-612.61"
85075   wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level
85076   attribute \src "ls180.v:614.11-614.63"
85077   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
85078   attribute \src "ls180.v:621.12-621.67"
85079   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
85080   attribute \src "ls180.v:622.13-622.70"
85081   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
85082   attribute \src "ls180.v:613.5-613.57"
85083   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
85084   attribute \src "ls180.v:596.5-596.60"
85085   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first
85086   attribute \src "ls180.v:597.5-597.59"
85087   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last
85088   attribute \src "ls180.v:599.13-599.75"
85089   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr
85090   attribute \src "ls180.v:598.6-598.66"
85091   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we
85092   attribute \src "ls180.v:595.6-595.61"
85093   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
85094   attribute \src "ls180.v:594.6-594.61"
85095   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid
85096   attribute \src "ls180.v:602.6-602.63"
85097   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first
85098   attribute \src "ls180.v:603.6-603.62"
85099   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
85100   attribute \src "ls180.v:605.13-605.77"
85101   wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
85102   attribute \src "ls180.v:604.6-604.68"
85103   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
85104   attribute \src "ls180.v:601.6-601.63"
85105   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
85106   attribute \src "ls180.v:600.6-600.63"
85107   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
85108   attribute \src "ls180.v:610.13-610.71"
85109   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
85110   attribute \src "ls180.v:611.13-611.72"
85111   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
85112   attribute \src "ls180.v:608.6-608.63"
85113   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
85114   attribute \src "ls180.v:609.6-609.69"
85115   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
85116   attribute \src "ls180.v:606.6-606.63"
85117   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
85118   attribute \src "ls180.v:607.6-607.69"
85119   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
85120   attribute \src "ls180.v:616.11-616.66"
85121   wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
85122   attribute \src "ls180.v:617.13-617.70"
85123   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r
85124   attribute \src "ls180.v:619.13-619.70"
85125   wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
85126   attribute \src "ls180.v:618.6-618.60"
85127   wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
85128   attribute \src "ls180.v:633.6-633.51"
85129   wire \main_sdram_bankmachine2_cmd_buffer_sink_first
85130   attribute \src "ls180.v:634.6-634.50"
85131   wire \main_sdram_bankmachine2_cmd_buffer_sink_last
85132   attribute \src "ls180.v:636.13-636.65"
85133   wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
85134   attribute \src "ls180.v:635.6-635.56"
85135   wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we
85136   attribute \src "ls180.v:632.6-632.51"
85137   wire \main_sdram_bankmachine2_cmd_buffer_sink_ready
85138   attribute \src "ls180.v:631.6-631.51"
85139   wire \main_sdram_bankmachine2_cmd_buffer_sink_valid
85140   attribute \src "ls180.v:639.5-639.52"
85141   wire \main_sdram_bankmachine2_cmd_buffer_source_first
85142   attribute \src "ls180.v:640.5-640.51"
85143   wire \main_sdram_bankmachine2_cmd_buffer_source_last
85144   attribute \src "ls180.v:642.12-642.66"
85145   wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr
85146   attribute \src "ls180.v:641.5-641.57"
85147   wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we
85148   attribute \src "ls180.v:638.6-638.53"
85149   wire \main_sdram_bankmachine2_cmd_buffer_source_ready
85150   attribute \src "ls180.v:637.5-637.52"
85151   wire \main_sdram_bankmachine2_cmd_buffer_source_valid
85152   attribute \src "ls180.v:585.12-585.49"
85153   wire width 13 \main_sdram_bankmachine2_cmd_payload_a
85154   attribute \src "ls180.v:586.12-586.50"
85155   wire width 2 \main_sdram_bankmachine2_cmd_payload_ba
85156   attribute \src "ls180.v:587.5-587.44"
85157   wire \main_sdram_bankmachine2_cmd_payload_cas
85158   attribute \src "ls180.v:590.5-590.47"
85159   wire \main_sdram_bankmachine2_cmd_payload_is_cmd
85160   attribute \src "ls180.v:591.5-591.48"
85161   wire \main_sdram_bankmachine2_cmd_payload_is_read
85162   attribute \src "ls180.v:592.5-592.49"
85163   wire \main_sdram_bankmachine2_cmd_payload_is_write
85164   attribute \src "ls180.v:588.5-588.44"
85165   wire \main_sdram_bankmachine2_cmd_payload_ras
85166   attribute \src "ls180.v:589.5-589.43"
85167   wire \main_sdram_bankmachine2_cmd_payload_we
85168   attribute \src "ls180.v:584.5-584.38"
85169   wire \main_sdram_bankmachine2_cmd_ready
85170   attribute \src "ls180.v:583.5-583.38"
85171   wire \main_sdram_bankmachine2_cmd_valid
85172   attribute \src "ls180.v:582.5-582.40"
85173   wire \main_sdram_bankmachine2_refresh_gnt
85174   attribute \src "ls180.v:581.6-581.41"
85175   wire \main_sdram_bankmachine2_refresh_req
85176   attribute \src "ls180.v:577.13-577.45"
85177   wire width 22 \main_sdram_bankmachine2_req_addr
85178   attribute \src "ls180.v:578.6-578.38"
85179   wire \main_sdram_bankmachine2_req_lock
85180   attribute \src "ls180.v:580.5-580.44"
85181   wire \main_sdram_bankmachine2_req_rdata_valid
85182   attribute \src "ls180.v:575.6-575.39"
85183   wire \main_sdram_bankmachine2_req_ready
85184   attribute \src "ls180.v:574.6-574.39"
85185   wire \main_sdram_bankmachine2_req_valid
85186   attribute \src "ls180.v:579.5-579.44"
85187   wire \main_sdram_bankmachine2_req_wdata_ready
85188   attribute \src "ls180.v:576.6-576.36"
85189   wire \main_sdram_bankmachine2_req_we
85190   attribute \src "ls180.v:643.12-643.39"
85191   wire width 13 \main_sdram_bankmachine2_row
85192   attribute \src "ls180.v:647.5-647.38"
85193   wire \main_sdram_bankmachine2_row_close
85194   attribute \src "ls180.v:648.5-648.47"
85195   wire \main_sdram_bankmachine2_row_col_n_addr_sel
85196   attribute \src "ls180.v:645.6-645.37"
85197   wire \main_sdram_bankmachine2_row_hit
85198   attribute \src "ls180.v:646.5-646.37"
85199   wire \main_sdram_bankmachine2_row_open
85200   attribute \src "ls180.v:644.5-644.39"
85201   wire \main_sdram_bankmachine2_row_opened
85202   attribute \no_retiming "true"
85203   attribute \src "ls180.v:655.32-655.69"
85204   wire \main_sdram_bankmachine2_trascon_ready
85205   attribute \src "ls180.v:654.6-654.43"
85206   wire \main_sdram_bankmachine2_trascon_valid
85207   attribute \no_retiming "true"
85208   attribute \src "ls180.v:653.32-653.68"
85209   wire \main_sdram_bankmachine2_trccon_ready
85210   attribute \src "ls180.v:652.6-652.42"
85211   wire \main_sdram_bankmachine2_trccon_valid
85212   attribute \src "ls180.v:651.11-651.48"
85213   wire width 3 \main_sdram_bankmachine2_twtpcon_count
85214   attribute \no_retiming "true"
85215   attribute \src "ls180.v:650.32-650.69"
85216   wire \main_sdram_bankmachine2_twtpcon_ready
85217   attribute \src "ls180.v:649.6-649.43"
85218   wire \main_sdram_bankmachine2_twtpcon_valid
85219   attribute \src "ls180.v:675.5-675.43"
85220   wire \main_sdram_bankmachine3_auto_precharge
85221   attribute \src "ls180.v:697.11-697.63"
85222   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
85223   attribute \src "ls180.v:702.6-702.58"
85224   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
85225   attribute \src "ls180.v:707.6-707.64"
85226   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first
85227   attribute \src "ls180.v:708.6-708.63"
85228   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last
85229   attribute \src "ls180.v:706.13-706.78"
85230   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr
85231   attribute \src "ls180.v:705.6-705.69"
85232   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we
85233   attribute \src "ls180.v:711.6-711.65"
85234   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first
85235   attribute \src "ls180.v:712.6-712.64"
85236   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last
85237   attribute \src "ls180.v:710.13-710.79"
85238   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
85239   attribute \src "ls180.v:709.6-709.70"
85240   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we
85241   attribute \src "ls180.v:694.11-694.61"
85242   wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level
85243   attribute \src "ls180.v:696.11-696.63"
85244   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
85245   attribute \src "ls180.v:703.12-703.67"
85246   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
85247   attribute \src "ls180.v:704.13-704.70"
85248   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
85249   attribute \src "ls180.v:695.5-695.57"
85250   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
85251   attribute \src "ls180.v:678.5-678.60"
85252   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first
85253   attribute \src "ls180.v:679.5-679.59"
85254   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last
85255   attribute \src "ls180.v:681.13-681.75"
85256   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr
85257   attribute \src "ls180.v:680.6-680.66"
85258   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we
85259   attribute \src "ls180.v:677.6-677.61"
85260   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
85261   attribute \src "ls180.v:676.6-676.61"
85262   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid
85263   attribute \src "ls180.v:684.6-684.63"
85264   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first
85265   attribute \src "ls180.v:685.6-685.62"
85266   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
85267   attribute \src "ls180.v:687.13-687.77"
85268   wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
85269   attribute \src "ls180.v:686.6-686.68"
85270   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
85271   attribute \src "ls180.v:683.6-683.63"
85272   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
85273   attribute \src "ls180.v:682.6-682.63"
85274   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
85275   attribute \src "ls180.v:692.13-692.71"
85276   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
85277   attribute \src "ls180.v:693.13-693.72"
85278   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
85279   attribute \src "ls180.v:690.6-690.63"
85280   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
85281   attribute \src "ls180.v:691.6-691.69"
85282   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
85283   attribute \src "ls180.v:688.6-688.63"
85284   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
85285   attribute \src "ls180.v:689.6-689.69"
85286   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
85287   attribute \src "ls180.v:698.11-698.66"
85288   wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
85289   attribute \src "ls180.v:699.13-699.70"
85290   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r
85291   attribute \src "ls180.v:701.13-701.70"
85292   wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
85293   attribute \src "ls180.v:700.6-700.60"
85294   wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
85295   attribute \src "ls180.v:715.6-715.51"
85296   wire \main_sdram_bankmachine3_cmd_buffer_sink_first
85297   attribute \src "ls180.v:716.6-716.50"
85298   wire \main_sdram_bankmachine3_cmd_buffer_sink_last
85299   attribute \src "ls180.v:718.13-718.65"
85300   wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
85301   attribute \src "ls180.v:717.6-717.56"
85302   wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we
85303   attribute \src "ls180.v:714.6-714.51"
85304   wire \main_sdram_bankmachine3_cmd_buffer_sink_ready
85305   attribute \src "ls180.v:713.6-713.51"
85306   wire \main_sdram_bankmachine3_cmd_buffer_sink_valid
85307   attribute \src "ls180.v:721.5-721.52"
85308   wire \main_sdram_bankmachine3_cmd_buffer_source_first
85309   attribute \src "ls180.v:722.5-722.51"
85310   wire \main_sdram_bankmachine3_cmd_buffer_source_last
85311   attribute \src "ls180.v:724.12-724.66"
85312   wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr
85313   attribute \src "ls180.v:723.5-723.57"
85314   wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we
85315   attribute \src "ls180.v:720.6-720.53"
85316   wire \main_sdram_bankmachine3_cmd_buffer_source_ready
85317   attribute \src "ls180.v:719.5-719.52"
85318   wire \main_sdram_bankmachine3_cmd_buffer_source_valid
85319   attribute \src "ls180.v:667.12-667.49"
85320   wire width 13 \main_sdram_bankmachine3_cmd_payload_a
85321   attribute \src "ls180.v:668.12-668.50"
85322   wire width 2 \main_sdram_bankmachine3_cmd_payload_ba
85323   attribute \src "ls180.v:669.5-669.44"
85324   wire \main_sdram_bankmachine3_cmd_payload_cas
85325   attribute \src "ls180.v:672.5-672.47"
85326   wire \main_sdram_bankmachine3_cmd_payload_is_cmd
85327   attribute \src "ls180.v:673.5-673.48"
85328   wire \main_sdram_bankmachine3_cmd_payload_is_read
85329   attribute \src "ls180.v:674.5-674.49"
85330   wire \main_sdram_bankmachine3_cmd_payload_is_write
85331   attribute \src "ls180.v:670.5-670.44"
85332   wire \main_sdram_bankmachine3_cmd_payload_ras
85333   attribute \src "ls180.v:671.5-671.43"
85334   wire \main_sdram_bankmachine3_cmd_payload_we
85335   attribute \src "ls180.v:666.5-666.38"
85336   wire \main_sdram_bankmachine3_cmd_ready
85337   attribute \src "ls180.v:665.5-665.38"
85338   wire \main_sdram_bankmachine3_cmd_valid
85339   attribute \src "ls180.v:664.5-664.40"
85340   wire \main_sdram_bankmachine3_refresh_gnt
85341   attribute \src "ls180.v:663.6-663.41"
85342   wire \main_sdram_bankmachine3_refresh_req
85343   attribute \src "ls180.v:659.13-659.45"
85344   wire width 22 \main_sdram_bankmachine3_req_addr
85345   attribute \src "ls180.v:660.6-660.38"
85346   wire \main_sdram_bankmachine3_req_lock
85347   attribute \src "ls180.v:662.5-662.44"
85348   wire \main_sdram_bankmachine3_req_rdata_valid
85349   attribute \src "ls180.v:657.6-657.39"
85350   wire \main_sdram_bankmachine3_req_ready
85351   attribute \src "ls180.v:656.6-656.39"
85352   wire \main_sdram_bankmachine3_req_valid
85353   attribute \src "ls180.v:661.5-661.44"
85354   wire \main_sdram_bankmachine3_req_wdata_ready
85355   attribute \src "ls180.v:658.6-658.36"
85356   wire \main_sdram_bankmachine3_req_we
85357   attribute \src "ls180.v:725.12-725.39"
85358   wire width 13 \main_sdram_bankmachine3_row
85359   attribute \src "ls180.v:729.5-729.38"
85360   wire \main_sdram_bankmachine3_row_close
85361   attribute \src "ls180.v:730.5-730.47"
85362   wire \main_sdram_bankmachine3_row_col_n_addr_sel
85363   attribute \src "ls180.v:727.6-727.37"
85364   wire \main_sdram_bankmachine3_row_hit
85365   attribute \src "ls180.v:728.5-728.37"
85366   wire \main_sdram_bankmachine3_row_open
85367   attribute \src "ls180.v:726.5-726.39"
85368   wire \main_sdram_bankmachine3_row_opened
85369   attribute \no_retiming "true"
85370   attribute \src "ls180.v:737.32-737.69"
85371   wire \main_sdram_bankmachine3_trascon_ready
85372   attribute \src "ls180.v:736.6-736.43"
85373   wire \main_sdram_bankmachine3_trascon_valid
85374   attribute \no_retiming "true"
85375   attribute \src "ls180.v:735.32-735.68"
85376   wire \main_sdram_bankmachine3_trccon_ready
85377   attribute \src "ls180.v:734.6-734.42"
85378   wire \main_sdram_bankmachine3_trccon_valid
85379   attribute \src "ls180.v:733.11-733.48"
85380   wire width 3 \main_sdram_bankmachine3_twtpcon_count
85381   attribute \no_retiming "true"
85382   attribute \src "ls180.v:732.32-732.69"
85383   wire \main_sdram_bankmachine3_twtpcon_ready
85384   attribute \src "ls180.v:731.6-731.43"
85385   wire \main_sdram_bankmachine3_twtpcon_valid
85386   attribute \src "ls180.v:739.6-739.28"
85387   wire \main_sdram_cas_allowed
85388   attribute \src "ls180.v:757.6-757.30"
85389   wire \main_sdram_choose_cmd_ce
85390   attribute \src "ls180.v:746.13-746.48"
85391   wire width 13 \main_sdram_choose_cmd_cmd_payload_a
85392   attribute \src "ls180.v:747.12-747.48"
85393   wire width 2 \main_sdram_choose_cmd_cmd_payload_ba
85394   attribute \src "ls180.v:748.5-748.42"
85395   wire \main_sdram_choose_cmd_cmd_payload_cas
85396   attribute \src "ls180.v:751.6-751.46"
85397   wire \main_sdram_choose_cmd_cmd_payload_is_cmd
85398   attribute \src "ls180.v:752.6-752.47"
85399   wire \main_sdram_choose_cmd_cmd_payload_is_read
85400   attribute \src "ls180.v:753.6-753.48"
85401   wire \main_sdram_choose_cmd_cmd_payload_is_write
85402   attribute \src "ls180.v:749.5-749.42"
85403   wire \main_sdram_choose_cmd_cmd_payload_ras
85404   attribute \src "ls180.v:750.5-750.41"
85405   wire \main_sdram_choose_cmd_cmd_payload_we
85406   attribute \src "ls180.v:745.5-745.36"
85407   wire \main_sdram_choose_cmd_cmd_ready
85408   attribute \src "ls180.v:744.6-744.37"
85409   wire \main_sdram_choose_cmd_cmd_valid
85410   attribute \src "ls180.v:756.11-756.38"
85411   wire width 2 \main_sdram_choose_cmd_grant
85412   attribute \src "ls180.v:755.12-755.41"
85413   wire width 4 \main_sdram_choose_cmd_request
85414   attribute \src "ls180.v:754.11-754.39"
85415   wire width 4 \main_sdram_choose_cmd_valids
85416   attribute \src "ls180.v:743.5-743.41"
85417   wire \main_sdram_choose_cmd_want_activates
85418   attribute \src "ls180.v:742.5-742.36"
85419   wire \main_sdram_choose_cmd_want_cmds
85420   attribute \src "ls180.v:740.5-740.37"
85421   wire \main_sdram_choose_cmd_want_reads
85422   attribute \src "ls180.v:741.5-741.38"
85423   wire \main_sdram_choose_cmd_want_writes
85424   attribute \src "ls180.v:775.6-775.30"
85425   wire \main_sdram_choose_req_ce
85426   attribute \src "ls180.v:764.13-764.48"
85427   wire width 13 \main_sdram_choose_req_cmd_payload_a
85428   attribute \src "ls180.v:765.12-765.48"
85429   wire width 2 \main_sdram_choose_req_cmd_payload_ba
85430   attribute \src "ls180.v:766.5-766.42"
85431   wire \main_sdram_choose_req_cmd_payload_cas
85432   attribute \src "ls180.v:769.6-769.46"
85433   wire \main_sdram_choose_req_cmd_payload_is_cmd
85434   attribute \src "ls180.v:770.6-770.47"
85435   wire \main_sdram_choose_req_cmd_payload_is_read
85436   attribute \src "ls180.v:771.6-771.48"
85437   wire \main_sdram_choose_req_cmd_payload_is_write
85438   attribute \src "ls180.v:767.5-767.42"
85439   wire \main_sdram_choose_req_cmd_payload_ras
85440   attribute \src "ls180.v:768.5-768.41"
85441   wire \main_sdram_choose_req_cmd_payload_we
85442   attribute \src "ls180.v:763.5-763.36"
85443   wire \main_sdram_choose_req_cmd_ready
85444   attribute \src "ls180.v:762.6-762.37"
85445   wire \main_sdram_choose_req_cmd_valid
85446   attribute \src "ls180.v:774.11-774.38"
85447   wire width 2 \main_sdram_choose_req_grant
85448   attribute \src "ls180.v:773.12-773.41"
85449   wire width 4 \main_sdram_choose_req_request
85450   attribute \src "ls180.v:772.11-772.39"
85451   wire width 4 \main_sdram_choose_req_valids
85452   attribute \src "ls180.v:761.5-761.41"
85453   wire \main_sdram_choose_req_want_activates
85454   attribute \src "ls180.v:760.6-760.37"
85455   wire \main_sdram_choose_req_want_cmds
85456   attribute \src "ls180.v:758.5-758.37"
85457   wire \main_sdram_choose_req_want_reads
85458   attribute \src "ls180.v:759.5-759.38"
85459   wire \main_sdram_choose_req_want_writes
85460   attribute \src "ls180.v:319.6-319.20"
85461   wire \main_sdram_cke
85462   attribute \src "ls180.v:387.5-387.24"
85463   wire \main_sdram_cmd_last
85464   attribute \src "ls180.v:388.12-388.36"
85465   wire width 13 \main_sdram_cmd_payload_a
85466   attribute \src "ls180.v:389.11-389.36"
85467   wire width 2 \main_sdram_cmd_payload_ba
85468   attribute \src "ls180.v:390.5-390.31"
85469   wire \main_sdram_cmd_payload_cas
85470   attribute \src "ls180.v:393.5-393.35"
85471   wire \main_sdram_cmd_payload_is_read
85472   attribute \src "ls180.v:394.5-394.36"
85473   wire \main_sdram_cmd_payload_is_write
85474   attribute \src "ls180.v:391.5-391.31"
85475   wire \main_sdram_cmd_payload_ras
85476   attribute \src "ls180.v:392.5-392.30"
85477   wire \main_sdram_cmd_payload_we
85478   attribute \src "ls180.v:386.5-386.25"
85479   wire \main_sdram_cmd_ready
85480   attribute \src "ls180.v:385.5-385.25"
85481   wire \main_sdram_cmd_valid
85482   attribute \src "ls180.v:327.6-327.32"
85483   wire \main_sdram_command_issue_r
85484   attribute \src "ls180.v:326.6-326.33"
85485   wire \main_sdram_command_issue_re
85486   attribute \src "ls180.v:329.5-329.31"
85487   wire \main_sdram_command_issue_w
85488   attribute \src "ls180.v:328.6-328.33"
85489   wire \main_sdram_command_issue_we
85490   attribute \src "ls180.v:325.5-325.26"
85491   wire \main_sdram_command_re
85492   attribute \src "ls180.v:324.11-324.37"
85493   wire width 6 \main_sdram_command_storage
85494   attribute \src "ls180.v:378.5-378.28"
85495   wire \main_sdram_dfi_p0_act_n
85496   attribute \src "ls180.v:369.12-369.37"
85497   wire width 13 \main_sdram_dfi_p0_address
85498   attribute \src "ls180.v:370.11-370.33"
85499   wire width 2 \main_sdram_dfi_p0_bank
85500   attribute \src "ls180.v:371.5-371.28"
85501   wire \main_sdram_dfi_p0_cas_n
85502   attribute \src "ls180.v:375.6-375.27"
85503   wire \main_sdram_dfi_p0_cke
85504   attribute \src "ls180.v:372.5-372.27"
85505   wire \main_sdram_dfi_p0_cs_n
85506   attribute \src "ls180.v:376.6-376.27"
85507   wire \main_sdram_dfi_p0_odt
85508   attribute \src "ls180.v:373.5-373.28"
85509   wire \main_sdram_dfi_p0_ras_n
85510   attribute \src "ls180.v:383.13-383.37"
85511   wire width 16 \main_sdram_dfi_p0_rddata
85512   attribute \src "ls180.v:382.5-382.32"
85513   wire \main_sdram_dfi_p0_rddata_en
85514   attribute \src "ls180.v:384.6-384.36"
85515   wire \main_sdram_dfi_p0_rddata_valid
85516   attribute \src "ls180.v:377.6-377.31"
85517   wire \main_sdram_dfi_p0_reset_n
85518   attribute \src "ls180.v:374.5-374.27"
85519   wire \main_sdram_dfi_p0_we_n
85520   attribute \src "ls180.v:379.13-379.37"
85521   wire width 16 \main_sdram_dfi_p0_wrdata
85522   attribute \src "ls180.v:380.5-380.32"
85523   wire \main_sdram_dfi_p0_wrdata_en
85524   attribute \src "ls180.v:381.12-381.41"
85525   wire width 2 \main_sdram_dfi_p0_wrdata_mask
85526   attribute \src "ls180.v:793.5-793.19"
85527   wire \main_sdram_en0
85528   attribute \src "ls180.v:796.5-796.19"
85529   wire \main_sdram_en1
85530   attribute \src "ls180.v:799.6-799.30"
85531   wire \main_sdram_go_to_refresh
85532   attribute \src "ls180.v:341.13-341.44"
85533   wire width 22 \main_sdram_interface_bank0_addr
85534   attribute \src "ls180.v:342.6-342.37"
85535   wire \main_sdram_interface_bank0_lock
85536   attribute \src "ls180.v:344.6-344.44"
85537   wire \main_sdram_interface_bank0_rdata_valid
85538   attribute \src "ls180.v:339.6-339.38"
85539   wire \main_sdram_interface_bank0_ready
85540   attribute \src "ls180.v:338.6-338.38"
85541   wire \main_sdram_interface_bank0_valid
85542   attribute \src "ls180.v:343.6-343.44"
85543   wire \main_sdram_interface_bank0_wdata_ready
85544   attribute \src "ls180.v:340.6-340.35"
85545   wire \main_sdram_interface_bank0_we
85546   attribute \src "ls180.v:348.13-348.44"
85547   wire width 22 \main_sdram_interface_bank1_addr
85548   attribute \src "ls180.v:349.6-349.37"
85549   wire \main_sdram_interface_bank1_lock
85550   attribute \src "ls180.v:351.6-351.44"
85551   wire \main_sdram_interface_bank1_rdata_valid
85552   attribute \src "ls180.v:346.6-346.38"
85553   wire \main_sdram_interface_bank1_ready
85554   attribute \src "ls180.v:345.6-345.38"
85555   wire \main_sdram_interface_bank1_valid
85556   attribute \src "ls180.v:350.6-350.44"
85557   wire \main_sdram_interface_bank1_wdata_ready
85558   attribute \src "ls180.v:347.6-347.35"
85559   wire \main_sdram_interface_bank1_we
85560   attribute \src "ls180.v:355.13-355.44"
85561   wire width 22 \main_sdram_interface_bank2_addr
85562   attribute \src "ls180.v:356.6-356.37"
85563   wire \main_sdram_interface_bank2_lock
85564   attribute \src "ls180.v:358.6-358.44"
85565   wire \main_sdram_interface_bank2_rdata_valid
85566   attribute \src "ls180.v:353.6-353.38"
85567   wire \main_sdram_interface_bank2_ready
85568   attribute \src "ls180.v:352.6-352.38"
85569   wire \main_sdram_interface_bank2_valid
85570   attribute \src "ls180.v:357.6-357.44"
85571   wire \main_sdram_interface_bank2_wdata_ready
85572   attribute \src "ls180.v:354.6-354.35"
85573   wire \main_sdram_interface_bank2_we
85574   attribute \src "ls180.v:362.13-362.44"
85575   wire width 22 \main_sdram_interface_bank3_addr
85576   attribute \src "ls180.v:363.6-363.37"
85577   wire \main_sdram_interface_bank3_lock
85578   attribute \src "ls180.v:365.6-365.44"
85579   wire \main_sdram_interface_bank3_rdata_valid
85580   attribute \src "ls180.v:360.6-360.38"
85581   wire \main_sdram_interface_bank3_ready
85582   attribute \src "ls180.v:359.6-359.38"
85583   wire \main_sdram_interface_bank3_valid
85584   attribute \src "ls180.v:364.6-364.44"
85585   wire \main_sdram_interface_bank3_wdata_ready
85586   attribute \src "ls180.v:361.6-361.35"
85587   wire \main_sdram_interface_bank3_we
85588   attribute \src "ls180.v:368.13-368.39"
85589   wire width 16 \main_sdram_interface_rdata
85590   attribute \src "ls180.v:366.12-366.38"
85591   wire width 16 \main_sdram_interface_wdata
85592   attribute \src "ls180.v:367.11-367.40"
85593   wire width 2 \main_sdram_interface_wdata_we
85594   attribute \src "ls180.v:279.5-279.29"
85595   wire \main_sdram_inti_p0_act_n
85596   attribute \src "ls180.v:270.13-270.39"
85597   wire width 13 \main_sdram_inti_p0_address
85598   attribute \src "ls180.v:271.12-271.35"
85599   wire width 2 \main_sdram_inti_p0_bank
85600   attribute \src "ls180.v:272.5-272.29"
85601   wire \main_sdram_inti_p0_cas_n
85602   attribute \src "ls180.v:276.6-276.28"
85603   wire \main_sdram_inti_p0_cke
85604   attribute \src "ls180.v:273.5-273.28"
85605   wire \main_sdram_inti_p0_cs_n
85606   attribute \src "ls180.v:277.6-277.28"
85607   wire \main_sdram_inti_p0_odt
85608   attribute \src "ls180.v:274.5-274.29"
85609   wire \main_sdram_inti_p0_ras_n
85610   attribute \src "ls180.v:284.12-284.37"
85611   wire width 16 \main_sdram_inti_p0_rddata
85612   attribute \src "ls180.v:283.6-283.34"
85613   wire \main_sdram_inti_p0_rddata_en
85614   attribute \src "ls180.v:285.5-285.36"
85615   wire \main_sdram_inti_p0_rddata_valid
85616   attribute \src "ls180.v:278.6-278.32"
85617   wire \main_sdram_inti_p0_reset_n
85618   attribute \src "ls180.v:275.5-275.28"
85619   wire \main_sdram_inti_p0_we_n
85620   attribute \src "ls180.v:280.13-280.38"
85621   wire width 16 \main_sdram_inti_p0_wrdata
85622   attribute \src "ls180.v:281.6-281.34"
85623   wire \main_sdram_inti_p0_wrdata_en
85624   attribute \src "ls180.v:282.12-282.42"
85625   wire width 2 \main_sdram_inti_p0_wrdata_mask
85626   attribute \src "ls180.v:311.5-311.31"
85627   wire \main_sdram_master_p0_act_n
85628   attribute \src "ls180.v:302.12-302.40"
85629   wire width 13 \main_sdram_master_p0_address
85630   attribute \src "ls180.v:303.11-303.36"
85631   wire width 2 \main_sdram_master_p0_bank
85632   attribute \src "ls180.v:304.5-304.31"
85633   wire \main_sdram_master_p0_cas_n
85634   attribute \src "ls180.v:308.5-308.29"
85635   wire \main_sdram_master_p0_cke
85636   attribute \src "ls180.v:305.5-305.30"
85637   wire \main_sdram_master_p0_cs_n
85638   attribute \src "ls180.v:309.5-309.29"
85639   wire \main_sdram_master_p0_odt
85640   attribute \src "ls180.v:306.5-306.31"
85641   wire \main_sdram_master_p0_ras_n
85642   attribute \src "ls180.v:316.13-316.40"
85643   wire width 16 \main_sdram_master_p0_rddata
85644   attribute \src "ls180.v:315.5-315.35"
85645   wire \main_sdram_master_p0_rddata_en
85646   attribute \src "ls180.v:317.6-317.39"
85647   wire \main_sdram_master_p0_rddata_valid
85648   attribute \src "ls180.v:310.5-310.33"
85649   wire \main_sdram_master_p0_reset_n
85650   attribute \src "ls180.v:307.5-307.30"
85651   wire \main_sdram_master_p0_we_n
85652   attribute \src "ls180.v:312.12-312.39"
85653   wire width 16 \main_sdram_master_p0_wrdata
85654   attribute \src "ls180.v:313.5-313.35"
85655   wire \main_sdram_master_p0_wrdata_en
85656   attribute \src "ls180.v:314.11-314.43"
85657   wire width 2 \main_sdram_master_p0_wrdata_mask
85658   attribute \src "ls180.v:794.6-794.26"
85659   wire \main_sdram_max_time0
85660   attribute \src "ls180.v:797.6-797.26"
85661   wire \main_sdram_max_time1
85662   attribute \src "ls180.v:776.12-776.28"
85663   wire width 13 \main_sdram_nop_a
85664   attribute \src "ls180.v:777.11-777.28"
85665   wire width 2 \main_sdram_nop_ba
85666   attribute \src "ls180.v:320.6-320.20"
85667   wire \main_sdram_odt
85668   attribute \src "ls180.v:403.5-403.31"
85669   wire \main_sdram_postponer_count
85670   attribute \src "ls180.v:401.6-401.32"
85671   wire \main_sdram_postponer_req_i
85672   attribute \src "ls180.v:402.5-402.31"
85673   wire \main_sdram_postponer_req_o
85674   attribute \src "ls180.v:738.6-738.28"
85675   wire \main_sdram_ras_allowed
85676   attribute \src "ls180.v:323.5-323.18"
85677   wire \main_sdram_re
85678   attribute \src "ls180.v:791.6-791.31"
85679   wire \main_sdram_read_available
85680   attribute \src "ls180.v:321.6-321.24"
85681   wire \main_sdram_reset_n
85682   attribute \src "ls180.v:318.6-318.20"
85683   wire \main_sdram_sel
85684   attribute \src "ls180.v:409.5-409.31"
85685   wire \main_sdram_sequencer_count
85686   attribute \src "ls180.v:408.11-408.39"
85687   wire width 4 \main_sdram_sequencer_counter
85688   attribute \src "ls180.v:405.6-405.32"
85689   wire \main_sdram_sequencer_done0
85690   attribute \src "ls180.v:407.5-407.31"
85691   wire \main_sdram_sequencer_done1
85692   attribute \src "ls180.v:404.5-404.32"
85693   wire \main_sdram_sequencer_start0
85694   attribute \src "ls180.v:406.6-406.33"
85695   wire \main_sdram_sequencer_start1
85696   attribute \src "ls180.v:295.6-295.31"
85697   wire \main_sdram_slave_p0_act_n
85698   attribute \src "ls180.v:286.13-286.40"
85699   wire width 13 \main_sdram_slave_p0_address
85700   attribute \src "ls180.v:287.12-287.36"
85701   wire width 2 \main_sdram_slave_p0_bank
85702   attribute \src "ls180.v:288.6-288.31"
85703   wire \main_sdram_slave_p0_cas_n
85704   attribute \src "ls180.v:292.6-292.29"
85705   wire \main_sdram_slave_p0_cke
85706   attribute \src "ls180.v:289.6-289.30"
85707   wire \main_sdram_slave_p0_cs_n
85708   attribute \src "ls180.v:293.6-293.29"
85709   wire \main_sdram_slave_p0_odt
85710   attribute \src "ls180.v:290.6-290.31"
85711   wire \main_sdram_slave_p0_ras_n
85712   attribute \src "ls180.v:300.12-300.38"
85713   wire width 16 \main_sdram_slave_p0_rddata
85714   attribute \src "ls180.v:299.6-299.35"
85715   wire \main_sdram_slave_p0_rddata_en
85716   attribute \src "ls180.v:301.5-301.37"
85717   wire \main_sdram_slave_p0_rddata_valid
85718   attribute \src "ls180.v:294.6-294.33"
85719   wire \main_sdram_slave_p0_reset_n
85720   attribute \src "ls180.v:291.6-291.30"
85721   wire \main_sdram_slave_p0_we_n
85722   attribute \src "ls180.v:296.13-296.39"
85723   wire width 16 \main_sdram_slave_p0_wrdata
85724   attribute \src "ls180.v:297.6-297.35"
85725   wire \main_sdram_slave_p0_wrdata_en
85726   attribute \src "ls180.v:298.12-298.43"
85727   wire width 2 \main_sdram_slave_p0_wrdata_mask
85728   attribute \src "ls180.v:336.12-336.29"
85729   wire width 16 \main_sdram_status
85730   attribute \src "ls180.v:779.5-779.24"
85731   wire \main_sdram_steerer0
85732   attribute \src "ls180.v:780.5-780.24"
85733   wire \main_sdram_steerer1
85734   attribute \src "ls180.v:778.11-778.33"
85735   wire width 2 \main_sdram_steerer_sel
85736   attribute \src "ls180.v:322.11-322.29"
85737   wire width 4 \main_sdram_storage
85738   attribute \src "ls180.v:787.5-787.29"
85739   wire \main_sdram_tccdcon_count
85740   attribute \no_retiming "true"
85741   attribute \src "ls180.v:786.32-786.56"
85742   wire \main_sdram_tccdcon_ready
85743   attribute \src "ls180.v:785.6-785.30"
85744   wire \main_sdram_tccdcon_valid
85745   attribute \no_retiming "true"
85746   attribute \src "ls180.v:784.32-784.56"
85747   wire \main_sdram_tfawcon_ready
85748   attribute \src "ls180.v:783.6-783.30"
85749   wire \main_sdram_tfawcon_valid
85750   attribute \src "ls180.v:795.11-795.27"
85751   wire width 5 \main_sdram_time0
85752   attribute \src "ls180.v:798.11-798.27"
85753   wire width 4 \main_sdram_time1
85754   attribute \src "ls180.v:398.12-398.35"
85755   wire width 10 \main_sdram_timer_count0
85756   attribute \src "ls180.v:400.11-400.34"
85757   wire width 10 \main_sdram_timer_count1
85758   attribute \src "ls180.v:397.6-397.28"
85759   wire \main_sdram_timer_done0
85760   attribute \src "ls180.v:399.6-399.28"
85761   wire \main_sdram_timer_done1
85762   attribute \src "ls180.v:396.6-396.27"
85763   wire \main_sdram_timer_wait
85764   attribute \no_retiming "true"
85765   attribute \src "ls180.v:782.32-782.56"
85766   wire \main_sdram_trrdcon_ready
85767   attribute \src "ls180.v:781.6-781.30"
85768   wire \main_sdram_trrdcon_valid
85769   attribute \src "ls180.v:790.11-790.35"
85770   wire width 3 \main_sdram_twtrcon_count
85771   attribute \no_retiming "true"
85772   attribute \src "ls180.v:789.32-789.56"
85773   wire \main_sdram_twtrcon_ready
85774   attribute \src "ls180.v:788.6-788.30"
85775   wire \main_sdram_twtrcon_valid
85776   attribute \src "ls180.v:395.6-395.30"
85777   wire \main_sdram_wants_refresh
85778   attribute \src "ls180.v:337.6-337.19"
85779   wire \main_sdram_we
85780   attribute \src "ls180.v:335.5-335.25"
85781   wire \main_sdram_wrdata_re
85782   attribute \src "ls180.v:334.12-334.37"
85783   wire width 16 \main_sdram_wrdata_storage
85784   attribute \src "ls180.v:792.6-792.32"
85785   wire \main_sdram_write_available
85786   attribute \src "ls180.v:992.6-992.27"
85787   wire \main_spimaster0_start
85788   attribute \src "ls180.v:1002.12-1002.35"
85789   wire width 8 \main_spimaster10_length
85790   attribute \src "ls180.v:1003.12-1003.36"
85791   wire width 16 \main_spimaster11_storage
85792   attribute \src "ls180.v:1004.5-1004.24"
85793   wire \main_spimaster12_re
85794   attribute \src "ls180.v:1005.6-1005.27"
85795   wire \main_spimaster13_done
85796   attribute \src "ls180.v:1006.6-1006.29"
85797   wire \main_spimaster14_status
85798   attribute \src "ls180.v:1007.6-1007.25"
85799   wire \main_spimaster15_we
85800   attribute \src "ls180.v:1008.11-1008.35"
85801   wire width 8 \main_spimaster16_storage
85802   attribute \src "ls180.v:1009.5-1009.24"
85803   wire \main_spimaster17_re
85804   attribute \src "ls180.v:1010.12-1010.35"
85805   wire width 8 \main_spimaster18_status
85806   attribute \src "ls180.v:1011.6-1011.25"
85807   wire \main_spimaster19_we
85808   attribute \src "ls180.v:993.12-993.34"
85809   wire width 8 \main_spimaster1_length
85810   attribute \src "ls180.v:1065.5-1065.23"
85811   wire \main_spimaster1_re
85812   attribute \src "ls180.v:1064.12-1064.35"
85813   wire width 16 \main_spimaster1_storage
85814   attribute \src "ls180.v:1012.6-1012.26"
85815   wire \main_spimaster20_sel
85816   attribute \src "ls180.v:1013.5-1013.29"
85817   wire \main_spimaster21_storage
85818   attribute \src "ls180.v:1014.5-1014.24"
85819   wire \main_spimaster22_re
85820   attribute \src "ls180.v:1015.5-1015.29"
85821   wire \main_spimaster23_storage
85822   attribute \src "ls180.v:1016.5-1016.24"
85823   wire \main_spimaster24_re
85824   attribute \src "ls180.v:1017.5-1017.32"
85825   wire \main_spimaster25_clk_enable
85826   attribute \src "ls180.v:1018.5-1018.31"
85827   wire \main_spimaster26_cs_enable
85828   attribute \src "ls180.v:1019.11-1019.33"
85829   wire width 3 \main_spimaster27_count
85830   attribute \src "ls180.v:1785.11-1785.55"
85831   wire width 3 \main_spimaster27_count_spimaster0_next_value
85832   attribute \src "ls180.v:1786.5-1786.52"
85833   wire \main_spimaster27_count_spimaster0_next_value_ce
85834   attribute \src "ls180.v:1020.5-1020.32"
85835   wire \main_spimaster28_mosi_latch
85836   attribute \src "ls180.v:1021.5-1021.32"
85837   wire \main_spimaster29_miso_latch
85838   attribute \src "ls180.v:994.5-994.25"
85839   wire \main_spimaster2_done
85840   attribute \src "ls180.v:1022.12-1022.40"
85841   wire width 16 \main_spimaster30_clk_divider
85842   attribute \src "ls180.v:1023.6-1023.31"
85843   wire \main_spimaster31_clk_rise
85844   attribute \src "ls180.v:1024.6-1024.31"
85845   wire \main_spimaster32_clk_fall
85846   attribute \src "ls180.v:1025.11-1025.37"
85847   wire width 8 \main_spimaster33_mosi_data
85848   attribute \src "ls180.v:1026.11-1026.36"
85849   wire width 3 \main_spimaster34_mosi_sel
85850   attribute \src "ls180.v:1027.11-1027.37"
85851   wire width 8 \main_spimaster35_miso_data
85852   attribute \src "ls180.v:995.5-995.24"
85853   wire \main_spimaster3_irq
85854   attribute \src "ls180.v:996.12-996.32"
85855   wire width 8 \main_spimaster4_mosi
85856   attribute \src "ls180.v:997.11-997.31"
85857   wire width 8 \main_spimaster5_miso
85858   attribute \src "ls180.v:998.6-998.24"
85859   wire \main_spimaster6_cs
85860   attribute \src "ls180.v:999.6-999.30"
85861   wire \main_spimaster7_loopback
85862   attribute \src "ls180.v:1000.12-1000.39"
85863   wire width 16 \main_spimaster8_clk_divider
85864   attribute \src "ls180.v:1001.5-1001.26"
85865   wire \main_spimaster9_start
85866   attribute \src "ls180.v:1036.13-1036.40"
85867   wire width 16 \main_spisdcard_clk_divider0
85868   attribute \src "ls180.v:1058.12-1058.39"
85869   wire width 16 \main_spisdcard_clk_divider1
85870   attribute \src "ls180.v:1053.5-1053.30"
85871   wire \main_spisdcard_clk_enable
85872   attribute \src "ls180.v:1060.6-1060.29"
85873   wire \main_spisdcard_clk_fall
85874   attribute \src "ls180.v:1059.6-1059.29"
85875   wire \main_spisdcard_clk_rise
85876   attribute \src "ls180.v:1040.5-1040.30"
85877   wire \main_spisdcard_control_re
85878   attribute \src "ls180.v:1039.12-1039.42"
85879   wire width 16 \main_spisdcard_control_storage
85880   attribute \src "ls180.v:1055.11-1055.31"
85881   wire width 3 \main_spisdcard_count
85882   attribute \src "ls180.v:1789.11-1789.53"
85883   wire width 3 \main_spisdcard_count_spimaster1_next_value
85884   attribute \src "ls180.v:1790.5-1790.50"
85885   wire \main_spisdcard_count_spimaster1_next_value_ce
85886   attribute \src "ls180.v:1034.6-1034.23"
85887   wire \main_spisdcard_cs
85888   attribute \src "ls180.v:1054.5-1054.29"
85889   wire \main_spisdcard_cs_enable
85890   attribute \src "ls180.v:1050.5-1050.25"
85891   wire \main_spisdcard_cs_re
85892   attribute \src "ls180.v:1049.5-1049.30"
85893   wire \main_spisdcard_cs_storage
85894   attribute \src "ls180.v:1030.5-1030.25"
85895   wire \main_spisdcard_done0
85896   attribute \src "ls180.v:1041.6-1041.26"
85897   wire \main_spisdcard_done1
85898   attribute \src "ls180.v:1031.5-1031.23"
85899   wire \main_spisdcard_irq
85900   attribute \src "ls180.v:1029.12-1029.34"
85901   wire width 8 \main_spisdcard_length0
85902   attribute \src "ls180.v:1038.12-1038.34"
85903   wire width 8 \main_spisdcard_length1
85904   attribute \src "ls180.v:1035.6-1035.29"
85905   wire \main_spisdcard_loopback
85906   attribute \src "ls180.v:1052.5-1052.31"
85907   wire \main_spisdcard_loopback_re
85908   attribute \src "ls180.v:1051.5-1051.36"
85909   wire \main_spisdcard_loopback_storage
85910   attribute \src "ls180.v:1033.11-1033.30"
85911   wire width 8 \main_spisdcard_miso
85912   attribute \src "ls180.v:1063.11-1063.35"
85913   wire width 8 \main_spisdcard_miso_data
85914   attribute \src "ls180.v:1057.5-1057.30"
85915   wire \main_spisdcard_miso_latch
85916   attribute \src "ls180.v:1046.12-1046.38"
85917   wire width 8 \main_spisdcard_miso_status
85918   attribute \src "ls180.v:1047.6-1047.28"
85919   wire \main_spisdcard_miso_we
85920   attribute \src "ls180.v:1032.12-1032.31"
85921   wire width 8 \main_spisdcard_mosi
85922   attribute \src "ls180.v:1061.11-1061.35"
85923   wire width 8 \main_spisdcard_mosi_data
85924   attribute \src "ls180.v:1056.5-1056.30"
85925   wire \main_spisdcard_mosi_latch
85926   attribute \src "ls180.v:1045.5-1045.27"
85927   wire \main_spisdcard_mosi_re
85928   attribute \src "ls180.v:1062.11-1062.34"
85929   wire width 3 \main_spisdcard_mosi_sel
85930   attribute \src "ls180.v:1044.11-1044.38"
85931   wire width 8 \main_spisdcard_mosi_storage
85932   attribute \src "ls180.v:1048.6-1048.24"
85933   wire \main_spisdcard_sel
85934   attribute \src "ls180.v:1028.6-1028.27"
85935   wire \main_spisdcard_start0
85936   attribute \src "ls180.v:1037.5-1037.26"
85937   wire \main_spisdcard_start1
85938   attribute \src "ls180.v:1042.6-1042.34"
85939   wire \main_spisdcard_status_status
85940   attribute \src "ls180.v:1043.6-1043.30"
85941   wire \main_spisdcard_status_we
85942   attribute \src "ls180.v:889.12-889.44"
85943   wire width 2 \main_uart_eventmanager_pending_r
85944   attribute \src "ls180.v:888.6-888.39"
85945   wire \main_uart_eventmanager_pending_re
85946   attribute \src "ls180.v:891.11-891.43"
85947   wire width 2 \main_uart_eventmanager_pending_w
85948   attribute \src "ls180.v:890.6-890.39"
85949   wire \main_uart_eventmanager_pending_we
85950   attribute \src "ls180.v:893.5-893.30"
85951   wire \main_uart_eventmanager_re
85952   attribute \src "ls180.v:885.12-885.43"
85953   wire width 2 \main_uart_eventmanager_status_r
85954   attribute \src "ls180.v:884.6-884.38"
85955   wire \main_uart_eventmanager_status_re
85956   attribute \src "ls180.v:887.11-887.42"
85957   wire width 2 \main_uart_eventmanager_status_w
85958   attribute \src "ls180.v:886.6-886.38"
85959   wire \main_uart_eventmanager_status_we
85960   attribute \src "ls180.v:892.11-892.41"
85961   wire width 2 \main_uart_eventmanager_storage
85962   attribute \src "ls180.v:873.6-873.19"
85963   wire \main_uart_irq
85964   attribute \src "ls180.v:859.12-859.46"
85965   wire width 32 \main_uart_phy_phase_accumulator_rx
85966   attribute \src "ls180.v:849.12-849.46"
85967   wire width 32 \main_uart_phy_phase_accumulator_tx
85968   attribute \src "ls180.v:842.5-842.21"
85969   wire \main_uart_phy_re
85970   attribute \src "ls180.v:860.6-860.22"
85971   wire \main_uart_phy_rx
85972   attribute \src "ls180.v:863.11-863.36"
85973   wire width 4 \main_uart_phy_rx_bitcount
85974   attribute \src "ls180.v:864.5-864.26"
85975   wire \main_uart_phy_rx_busy
85976   attribute \src "ls180.v:861.5-861.23"
85977   wire \main_uart_phy_rx_r
85978   attribute \src "ls180.v:862.11-862.31"
85979   wire width 8 \main_uart_phy_rx_reg
85980   attribute \src "ls180.v:845.6-845.30"
85981   wire \main_uart_phy_sink_first
85982   attribute \src "ls180.v:846.6-846.29"
85983   wire \main_uart_phy_sink_last
85984   attribute \src "ls180.v:847.12-847.43"
85985   wire width 8 \main_uart_phy_sink_payload_data
85986   attribute \src "ls180.v:844.5-844.29"
85987   wire \main_uart_phy_sink_ready
85988   attribute \src "ls180.v:843.6-843.30"
85989   wire \main_uart_phy_sink_valid
85990   attribute \src "ls180.v:855.5-855.31"
85991   wire \main_uart_phy_source_first
85992   attribute \src "ls180.v:856.5-856.30"
85993   wire \main_uart_phy_source_last
85994   attribute \src "ls180.v:857.11-857.44"
85995   wire width 8 \main_uart_phy_source_payload_data
85996   attribute \src "ls180.v:854.6-854.32"
85997   wire \main_uart_phy_source_ready
85998   attribute \src "ls180.v:853.5-853.31"
85999   wire \main_uart_phy_source_valid
86000   attribute \src "ls180.v:841.12-841.33"
86001   wire width 32 \main_uart_phy_storage
86002   attribute \src "ls180.v:851.11-851.36"
86003   wire width 4 \main_uart_phy_tx_bitcount
86004   attribute \src "ls180.v:852.5-852.26"
86005   wire \main_uart_phy_tx_busy
86006   attribute \src "ls180.v:850.11-850.31"
86007   wire width 8 \main_uart_phy_tx_reg
86008   attribute \src "ls180.v:858.5-858.32"
86009   wire \main_uart_phy_uart_clk_rxen
86010   attribute \src "ls180.v:848.5-848.32"
86011   wire \main_uart_phy_uart_clk_txen
86012   attribute \src "ls180.v:982.5-982.20"
86013   wire \main_uart_reset
86014   attribute \src "ls180.v:882.5-882.23"
86015   wire \main_uart_rx_clear
86016   attribute \src "ls180.v:966.11-966.36"
86017   wire width 4 \main_uart_rx_fifo_consume
86018   attribute \src "ls180.v:971.6-971.31"
86019   wire \main_uart_rx_fifo_do_read
86020   attribute \src "ls180.v:977.6-977.37"
86021   wire \main_uart_rx_fifo_fifo_in_first
86022   attribute \src "ls180.v:978.6-978.36"
86023   wire \main_uart_rx_fifo_fifo_in_last
86024   attribute \src "ls180.v:976.12-976.50"
86025   wire width 8 \main_uart_rx_fifo_fifo_in_payload_data
86026   attribute \src "ls180.v:980.6-980.38"
86027   wire \main_uart_rx_fifo_fifo_out_first
86028   attribute \src "ls180.v:981.6-981.37"
86029   wire \main_uart_rx_fifo_fifo_out_last
86030   attribute \src "ls180.v:979.12-979.51"
86031   wire width 8 \main_uart_rx_fifo_fifo_out_payload_data
86032   attribute \src "ls180.v:963.11-963.35"
86033   wire width 5 \main_uart_rx_fifo_level0
86034   attribute \src "ls180.v:975.12-975.36"
86035   wire width 5 \main_uart_rx_fifo_level1
86036   attribute \src "ls180.v:965.11-965.36"
86037   wire width 4 \main_uart_rx_fifo_produce
86038   attribute \src "ls180.v:972.12-972.40"
86039   wire width 4 \main_uart_rx_fifo_rdport_adr
86040   attribute \src "ls180.v:973.12-973.42"
86041   wire width 10 \main_uart_rx_fifo_rdport_dat_r
86042   attribute \src "ls180.v:974.6-974.33"
86043   wire \main_uart_rx_fifo_rdport_re
86044   attribute \src "ls180.v:955.6-955.26"
86045   wire \main_uart_rx_fifo_re
86046   attribute \src "ls180.v:956.5-956.31"
86047   wire \main_uart_rx_fifo_readable
86048   attribute \src "ls180.v:964.5-964.30"
86049   wire \main_uart_rx_fifo_replace
86050   attribute \src "ls180.v:947.6-947.34"
86051   wire \main_uart_rx_fifo_sink_first
86052   attribute \src "ls180.v:948.6-948.33"
86053   wire \main_uart_rx_fifo_sink_last
86054   attribute \src "ls180.v:949.12-949.47"
86055   wire width 8 \main_uart_rx_fifo_sink_payload_data
86056   attribute \src "ls180.v:946.6-946.34"
86057   wire \main_uart_rx_fifo_sink_ready
86058   attribute \src "ls180.v:945.6-945.34"
86059   wire \main_uart_rx_fifo_sink_valid
86060   attribute \src "ls180.v:952.6-952.36"
86061   wire \main_uart_rx_fifo_source_first
86062   attribute \src "ls180.v:953.6-953.35"
86063   wire \main_uart_rx_fifo_source_last
86064   attribute \src "ls180.v:954.12-954.49"
86065   wire width 8 \main_uart_rx_fifo_source_payload_data
86066   attribute \src "ls180.v:951.6-951.36"
86067   wire \main_uart_rx_fifo_source_ready
86068   attribute \src "ls180.v:950.6-950.36"
86069   wire \main_uart_rx_fifo_source_valid
86070   attribute \src "ls180.v:961.12-961.42"
86071   wire width 10 \main_uart_rx_fifo_syncfifo_din
86072   attribute \src "ls180.v:962.12-962.43"
86073   wire width 10 \main_uart_rx_fifo_syncfifo_dout
86074   attribute \src "ls180.v:959.6-959.35"
86075   wire \main_uart_rx_fifo_syncfifo_re
86076   attribute \src "ls180.v:960.6-960.41"
86077   wire \main_uart_rx_fifo_syncfifo_readable
86078   attribute \src "ls180.v:957.6-957.35"
86079   wire \main_uart_rx_fifo_syncfifo_we
86080   attribute \src "ls180.v:958.6-958.41"
86081   wire \main_uart_rx_fifo_syncfifo_writable
86082   attribute \src "ls180.v:967.11-967.39"
86083   wire width 4 \main_uart_rx_fifo_wrport_adr
86084   attribute \src "ls180.v:968.12-968.42"
86085   wire width 10 \main_uart_rx_fifo_wrport_dat_r
86086   attribute \src "ls180.v:970.12-970.42"
86087   wire width 10 \main_uart_rx_fifo_wrport_dat_w
86088   attribute \src "ls180.v:969.6-969.33"
86089   wire \main_uart_rx_fifo_wrport_we
86090   attribute \src "ls180.v:883.5-883.29"
86091   wire \main_uart_rx_old_trigger
86092   attribute \src "ls180.v:880.5-880.25"
86093   wire \main_uart_rx_pending
86094   attribute \src "ls180.v:879.6-879.25"
86095   wire \main_uart_rx_status
86096   attribute \src "ls180.v:881.6-881.26"
86097   wire \main_uart_rx_trigger
86098   attribute \src "ls180.v:871.6-871.30"
86099   wire \main_uart_rxempty_status
86100   attribute \src "ls180.v:872.6-872.26"
86101   wire \main_uart_rxempty_we
86102   attribute \src "ls180.v:896.6-896.29"
86103   wire \main_uart_rxfull_status
86104   attribute \src "ls180.v:897.6-897.25"
86105   wire \main_uart_rxfull_we
86106   attribute \src "ls180.v:866.12-866.28"
86107   wire width 8 \main_uart_rxtx_r
86108   attribute \src "ls180.v:865.6-865.23"
86109   wire \main_uart_rxtx_re
86110   attribute \src "ls180.v:868.12-868.28"
86111   wire width 8 \main_uart_rxtx_w
86112   attribute \src "ls180.v:867.6-867.23"
86113   wire \main_uart_rxtx_we
86114   attribute \src "ls180.v:877.5-877.23"
86115   wire \main_uart_tx_clear
86116   attribute \src "ls180.v:929.11-929.36"
86117   wire width 4 \main_uart_tx_fifo_consume
86118   attribute \src "ls180.v:934.6-934.31"
86119   wire \main_uart_tx_fifo_do_read
86120   attribute \src "ls180.v:940.6-940.37"
86121   wire \main_uart_tx_fifo_fifo_in_first
86122   attribute \src "ls180.v:941.6-941.36"
86123   wire \main_uart_tx_fifo_fifo_in_last
86124   attribute \src "ls180.v:939.12-939.50"
86125   wire width 8 \main_uart_tx_fifo_fifo_in_payload_data
86126   attribute \src "ls180.v:943.6-943.38"
86127   wire \main_uart_tx_fifo_fifo_out_first
86128   attribute \src "ls180.v:944.6-944.37"
86129   wire \main_uart_tx_fifo_fifo_out_last
86130   attribute \src "ls180.v:942.12-942.51"
86131   wire width 8 \main_uart_tx_fifo_fifo_out_payload_data
86132   attribute \src "ls180.v:926.11-926.35"
86133   wire width 5 \main_uart_tx_fifo_level0
86134   attribute \src "ls180.v:938.12-938.36"
86135   wire width 5 \main_uart_tx_fifo_level1
86136   attribute \src "ls180.v:928.11-928.36"
86137   wire width 4 \main_uart_tx_fifo_produce
86138   attribute \src "ls180.v:935.12-935.40"
86139   wire width 4 \main_uart_tx_fifo_rdport_adr
86140   attribute \src "ls180.v:936.12-936.42"
86141   wire width 10 \main_uart_tx_fifo_rdport_dat_r
86142   attribute \src "ls180.v:937.6-937.33"
86143   wire \main_uart_tx_fifo_rdport_re
86144   attribute \src "ls180.v:918.6-918.26"
86145   wire \main_uart_tx_fifo_re
86146   attribute \src "ls180.v:919.5-919.31"
86147   wire \main_uart_tx_fifo_readable
86148   attribute \src "ls180.v:927.5-927.30"
86149   wire \main_uart_tx_fifo_replace
86150   attribute \src "ls180.v:910.5-910.33"
86151   wire \main_uart_tx_fifo_sink_first
86152   attribute \src "ls180.v:911.5-911.32"
86153   wire \main_uart_tx_fifo_sink_last
86154   attribute \src "ls180.v:912.12-912.47"
86155   wire width 8 \main_uart_tx_fifo_sink_payload_data
86156   attribute \src "ls180.v:909.6-909.34"
86157   wire \main_uart_tx_fifo_sink_ready
86158   attribute \src "ls180.v:908.6-908.34"
86159   wire \main_uart_tx_fifo_sink_valid
86160   attribute \src "ls180.v:915.6-915.36"
86161   wire \main_uart_tx_fifo_source_first
86162   attribute \src "ls180.v:916.6-916.35"
86163   wire \main_uart_tx_fifo_source_last
86164   attribute \src "ls180.v:917.12-917.49"
86165   wire width 8 \main_uart_tx_fifo_source_payload_data
86166   attribute \src "ls180.v:914.6-914.36"
86167   wire \main_uart_tx_fifo_source_ready
86168   attribute \src "ls180.v:913.6-913.36"
86169   wire \main_uart_tx_fifo_source_valid
86170   attribute \src "ls180.v:924.12-924.42"
86171   wire width 10 \main_uart_tx_fifo_syncfifo_din
86172   attribute \src "ls180.v:925.12-925.43"
86173   wire width 10 \main_uart_tx_fifo_syncfifo_dout
86174   attribute \src "ls180.v:922.6-922.35"
86175   wire \main_uart_tx_fifo_syncfifo_re
86176   attribute \src "ls180.v:923.6-923.41"
86177   wire \main_uart_tx_fifo_syncfifo_readable
86178   attribute \src "ls180.v:920.6-920.35"
86179   wire \main_uart_tx_fifo_syncfifo_we
86180   attribute \src "ls180.v:921.6-921.41"
86181   wire \main_uart_tx_fifo_syncfifo_writable
86182   attribute \src "ls180.v:930.11-930.39"
86183   wire width 4 \main_uart_tx_fifo_wrport_adr
86184   attribute \src "ls180.v:931.12-931.42"
86185   wire width 10 \main_uart_tx_fifo_wrport_dat_r
86186   attribute \src "ls180.v:933.12-933.42"
86187   wire width 10 \main_uart_tx_fifo_wrport_dat_w
86188   attribute \src "ls180.v:932.6-932.33"
86189   wire \main_uart_tx_fifo_wrport_we
86190   attribute \src "ls180.v:878.5-878.29"
86191   wire \main_uart_tx_old_trigger
86192   attribute \src "ls180.v:875.5-875.25"
86193   wire \main_uart_tx_pending
86194   attribute \src "ls180.v:874.6-874.25"
86195   wire \main_uart_tx_status
86196   attribute \src "ls180.v:876.6-876.26"
86197   wire \main_uart_tx_trigger
86198   attribute \src "ls180.v:894.6-894.30"
86199   wire \main_uart_txempty_status
86200   attribute \src "ls180.v:895.6-895.26"
86201   wire \main_uart_txempty_we
86202   attribute \src "ls180.v:869.6-869.29"
86203   wire \main_uart_txfull_status
86204   attribute \src "ls180.v:870.6-870.25"
86205   wire \main_uart_txfull_we
86206   attribute \src "ls180.v:900.6-900.31"
86207   wire \main_uart_uart_sink_first
86208   attribute \src "ls180.v:901.6-901.30"
86209   wire \main_uart_uart_sink_last
86210   attribute \src "ls180.v:902.12-902.44"
86211   wire width 8 \main_uart_uart_sink_payload_data
86212   attribute \src "ls180.v:899.6-899.31"
86213   wire \main_uart_uart_sink_ready
86214   attribute \src "ls180.v:898.6-898.31"
86215   wire \main_uart_uart_sink_valid
86216   attribute \src "ls180.v:905.6-905.33"
86217   wire \main_uart_uart_source_first
86218   attribute \src "ls180.v:906.6-906.32"
86219   wire \main_uart_uart_source_last
86220   attribute \src "ls180.v:907.12-907.46"
86221   wire width 8 \main_uart_uart_source_payload_data
86222   attribute \src "ls180.v:904.6-904.33"
86223   wire \main_uart_uart_source_ready
86224   attribute \src "ls180.v:903.6-903.33"
86225   wire \main_uart_uart_source_valid
86226   attribute \src "ls180.v:819.5-819.22"
86227   wire \main_wb_sdram_ack
86228   attribute \src "ls180.v:813.13-813.30"
86229   wire width 30 \main_wb_sdram_adr
86230   attribute \src "ls180.v:822.12-822.29"
86231   wire width 2 \main_wb_sdram_bte
86232   attribute \src "ls180.v:821.12-821.29"
86233   wire width 3 \main_wb_sdram_cti
86234   attribute \src "ls180.v:817.6-817.23"
86235   wire \main_wb_sdram_cyc
86236   attribute \src "ls180.v:815.13-815.32"
86237   wire width 32 \main_wb_sdram_dat_r
86238   attribute \src "ls180.v:814.13-814.32"
86239   wire width 32 \main_wb_sdram_dat_w
86240   attribute \src "ls180.v:823.5-823.22"
86241   wire \main_wb_sdram_err
86242   attribute \src "ls180.v:816.12-816.29"
86243   wire width 4 \main_wb_sdram_sel
86244   attribute \src "ls180.v:818.6-818.23"
86245   wire \main_wb_sdram_stb
86246   attribute \src "ls180.v:820.6-820.22"
86247   wire \main_wb_sdram_we
86248   attribute \src "ls180.v:837.5-837.24"
86249   wire \main_wdata_consumed
86250   attribute \src "ls180.v:10058.11-10058.17"
86251   wire width 7 \memadr
86252   attribute \src "ls180.v:10078.12-10078.18"
86253   wire width 25 \memdat
86254   attribute \src "ls180.v:10092.12-10092.20"
86255   wire width 25 \memdat_1
86256   attribute \src "ls180.v:10106.12-10106.20"
86257   wire width 25 \memdat_2
86258   attribute \src "ls180.v:10120.12-10120.20"
86259   wire width 25 \memdat_3
86260   attribute \src "ls180.v:10134.11-10134.19"
86261   wire width 10 \memdat_4
86262   attribute \src "ls180.v:10135.11-10135.19"
86263   wire width 10 \memdat_5
86264   attribute \src "ls180.v:10151.11-10151.19"
86265   wire width 10 \memdat_6
86266   attribute \src "ls180.v:10152.11-10152.19"
86267   wire width 10 \memdat_7
86268   attribute \src "ls180.v:10168.11-10168.19"
86269   wire width 10 \memdat_8
86270   attribute \src "ls180.v:10182.11-10182.19"
86271   wire width 10 \memdat_9
86272   attribute \src "ls180.v:52.20-52.22"
86273   wire width 36 input 48 \nc
86274   attribute \src "ls180.v:251.6-251.13"
86275   wire \por_clk
86276   attribute \src "ls180.v:22.19-22.22"
86277   wire width 2 output 18 \pwm
86278   attribute \src "ls180.v:141.12-141.17"
86279   wire width 2 \pwm_1
86280   attribute \src "ls180.v:14.13-14.23"
86281   wire output 10 \sdcard_clk
86282   attribute \src "ls180.v:15.14-15.26"
86283   wire output 11 \sdcard_cmd_i
86284   attribute \src "ls180.v:16.13-16.25"
86285   wire output 12 \sdcard_cmd_o
86286   attribute \src "ls180.v:17.13-17.26"
86287   wire output 13 \sdcard_cmd_oe
86288   attribute \src "ls180.v:18.19-18.32"
86289   wire width 4 input 14 \sdcard_data_i
86290   attribute \src "ls180.v:19.19-19.32"
86291   wire width 4 output 15 \sdcard_data_o
86292   attribute \src "ls180.v:20.13-20.27"
86293   wire output 16 \sdcard_data_oe
86294   attribute \src "ls180.v:27.20-27.27"
86295   wire width 13 output 23 \sdram_a
86296   attribute \src "ls180.v:36.19-36.27"
86297   wire width 2 output 32 \sdram_ba
86298   attribute \src "ls180.v:33.13-33.24"
86299   wire output 29 \sdram_cas_n
86300   attribute \src "ls180.v:35.13-35.22"
86301   wire output 31 \sdram_cke
86302   attribute \src "ls180.v:38.13-38.24"
86303   wire output 34 \sdram_clock
86304   attribute \src "ls180.v:157.6-157.19"
86305   wire \sdram_clock_1
86306   attribute \src "ls180.v:34.13-34.23"
86307   wire output 30 \sdram_cs_n
86308   attribute \src "ls180.v:37.19-37.27"
86309   wire width 2 output 33 \sdram_dm
86310   attribute \src "ls180.v:28.21-28.31"
86311   wire width 16 output 24 \sdram_dq_i
86312   attribute \src "ls180.v:29.20-29.30"
86313   wire width 16 output 25 \sdram_dq_o
86314   attribute \src "ls180.v:30.13-30.24"
86315   wire output 26 \sdram_dq_oe
86316   attribute \src "ls180.v:32.13-32.24"
86317   wire output 28 \sdram_ras_n
86318   attribute \src "ls180.v:31.13-31.23"
86319   wire output 27 \sdram_we_n
86320   attribute \src "ls180.v:2647.6-2647.15"
86321   wire \sdrio_clk
86322   attribute \src "ls180.v:2648.6-2648.17"
86323   wire \sdrio_clk_1
86324   attribute \src "ls180.v:2657.6-2657.18"
86325   wire \sdrio_clk_10
86326   attribute \src "ls180.v:2658.6-2658.18"
86327   wire \sdrio_clk_11
86328   attribute \src "ls180.v:2659.6-2659.18"
86329   wire \sdrio_clk_12
86330   attribute \src "ls180.v:2660.6-2660.18"
86331   wire \sdrio_clk_13
86332   attribute \src "ls180.v:2661.6-2661.18"
86333   wire \sdrio_clk_14
86334   attribute \src "ls180.v:2662.6-2662.18"
86335   wire \sdrio_clk_15
86336   attribute \src "ls180.v:2663.6-2663.18"
86337   wire \sdrio_clk_16
86338   attribute \src "ls180.v:2664.6-2664.18"
86339   wire \sdrio_clk_17
86340   attribute \src "ls180.v:2665.6-2665.18"
86341   wire \sdrio_clk_18
86342   attribute \src "ls180.v:2666.6-2666.18"
86343   wire \sdrio_clk_19
86344   attribute \src "ls180.v:2649.6-2649.17"
86345   wire \sdrio_clk_2
86346   attribute \src "ls180.v:2667.6-2667.18"
86347   wire \sdrio_clk_20
86348   attribute \src "ls180.v:2668.6-2668.18"
86349   wire \sdrio_clk_21
86350   attribute \src "ls180.v:2669.6-2669.18"
86351   wire \sdrio_clk_22
86352   attribute \src "ls180.v:2670.6-2670.18"
86353   wire \sdrio_clk_23
86354   attribute \src "ls180.v:2671.6-2671.18"
86355   wire \sdrio_clk_24
86356   attribute \src "ls180.v:2672.6-2672.18"
86357   wire \sdrio_clk_25
86358   attribute \src "ls180.v:2673.6-2673.18"
86359   wire \sdrio_clk_26
86360   attribute \src "ls180.v:2674.6-2674.18"
86361   wire \sdrio_clk_27
86362   attribute \src "ls180.v:2675.6-2675.18"
86363   wire \sdrio_clk_28
86364   attribute \src "ls180.v:2676.6-2676.18"
86365   wire \sdrio_clk_29
86366   attribute \src "ls180.v:2650.6-2650.17"
86367   wire \sdrio_clk_3
86368   attribute \src "ls180.v:2677.6-2677.18"
86369   wire \sdrio_clk_30
86370   attribute \src "ls180.v:2678.6-2678.18"
86371   wire \sdrio_clk_31
86372   attribute \src "ls180.v:2679.6-2679.18"
86373   wire \sdrio_clk_32
86374   attribute \src "ls180.v:2680.6-2680.18"
86375   wire \sdrio_clk_33
86376   attribute \src "ls180.v:2681.6-2681.18"
86377   wire \sdrio_clk_34
86378   attribute \src "ls180.v:2682.6-2682.18"
86379   wire \sdrio_clk_35
86380   attribute \src "ls180.v:2683.6-2683.18"
86381   wire \sdrio_clk_36
86382   attribute \src "ls180.v:2684.6-2684.18"
86383   wire \sdrio_clk_37
86384   attribute \src "ls180.v:2685.6-2685.18"
86385   wire \sdrio_clk_38
86386   attribute \src "ls180.v:2686.6-2686.18"
86387   wire \sdrio_clk_39
86388   attribute \src "ls180.v:2651.6-2651.17"
86389   wire \sdrio_clk_4
86390   attribute \src "ls180.v:2687.6-2687.18"
86391   wire \sdrio_clk_40
86392   attribute \src "ls180.v:2688.6-2688.18"
86393   wire \sdrio_clk_41
86394   attribute \src "ls180.v:2689.6-2689.18"
86395   wire \sdrio_clk_42
86396   attribute \src "ls180.v:2690.6-2690.18"
86397   wire \sdrio_clk_43
86398   attribute \src "ls180.v:2691.6-2691.18"
86399   wire \sdrio_clk_44
86400   attribute \src "ls180.v:2692.6-2692.18"
86401   wire \sdrio_clk_45
86402   attribute \src "ls180.v:2693.6-2693.18"
86403   wire \sdrio_clk_46
86404   attribute \src "ls180.v:2694.6-2694.18"
86405   wire \sdrio_clk_47
86406   attribute \src "ls180.v:2695.6-2695.18"
86407   wire \sdrio_clk_48
86408   attribute \src "ls180.v:2696.6-2696.18"
86409   wire \sdrio_clk_49
86410   attribute \src "ls180.v:2652.6-2652.17"
86411   wire \sdrio_clk_5
86412   attribute \src "ls180.v:2697.6-2697.18"
86413   wire \sdrio_clk_50
86414   attribute \src "ls180.v:2698.6-2698.18"
86415   wire \sdrio_clk_51
86416   attribute \src "ls180.v:2699.6-2699.18"
86417   wire \sdrio_clk_52
86418   attribute \src "ls180.v:2700.6-2700.18"
86419   wire \sdrio_clk_53
86420   attribute \src "ls180.v:2701.6-2701.18"
86421   wire \sdrio_clk_54
86422   attribute \src "ls180.v:2702.6-2702.18"
86423   wire \sdrio_clk_55
86424   attribute \src "ls180.v:2737.6-2737.18"
86425   wire \sdrio_clk_56
86426   attribute \src "ls180.v:2738.6-2738.18"
86427   wire \sdrio_clk_57
86428   attribute \src "ls180.v:2739.6-2739.18"
86429   wire \sdrio_clk_58
86430   attribute \src "ls180.v:2740.6-2740.18"
86431   wire \sdrio_clk_59
86432   attribute \src "ls180.v:2653.6-2653.17"
86433   wire \sdrio_clk_6
86434   attribute \src "ls180.v:2741.6-2741.18"
86435   wire \sdrio_clk_60
86436   attribute \src "ls180.v:2742.6-2742.18"
86437   wire \sdrio_clk_61
86438   attribute \src "ls180.v:2743.6-2743.18"
86439   wire \sdrio_clk_62
86440   attribute \src "ls180.v:2744.6-2744.18"
86441   wire \sdrio_clk_63
86442   attribute \src "ls180.v:2745.6-2745.18"
86443   wire \sdrio_clk_64
86444   attribute \src "ls180.v:2746.6-2746.18"
86445   wire \sdrio_clk_65
86446   attribute \src "ls180.v:2747.6-2747.18"
86447   wire \sdrio_clk_66
86448   attribute \src "ls180.v:2748.6-2748.18"
86449   wire \sdrio_clk_67
86450   attribute \src "ls180.v:2749.6-2749.18"
86451   wire \sdrio_clk_68
86452   attribute \src "ls180.v:2654.6-2654.17"
86453   wire \sdrio_clk_7
86454   attribute \src "ls180.v:2655.6-2655.17"
86455   wire \sdrio_clk_8
86456   attribute \src "ls180.v:2656.6-2656.17"
86457   wire \sdrio_clk_9
86458   attribute \src "ls180.v:23.13-23.26"
86459   wire output 19 \spimaster_clk
86460   attribute \src "ls180.v:25.13-25.27"
86461   wire output 21 \spimaster_cs_n
86462   attribute \src "ls180.v:26.14-26.28"
86463   wire output 22 \spimaster_miso
86464   attribute \src "ls180.v:24.13-24.27"
86465   wire output 20 \spimaster_mosi
86466   attribute \src "ls180.v:8.13-8.26"
86467   wire output 4 \spisdcard_clk
86468   attribute \src "ls180.v:10.13-10.27"
86469   wire output 6 \spisdcard_cs_n
86470   attribute \src "ls180.v:11.14-11.28"
86471   wire output 7 \spisdcard_miso
86472   attribute \src "ls180.v:9.13-9.27"
86473   wire output 5 \spisdcard_mosi
86474   attribute \src "ls180.v:43.13-43.20"
86475   wire input 39 \sys_clk
86476   attribute \src "ls180.v:249.6-249.15"
86477   wire \sys_clk_1
86478   attribute \src "ls180.v:45.19-45.31"
86479   wire width 3 input 41 \sys_clksel_i
86480   attribute \src "ls180.v:46.14-46.26"
86481   wire output 42 \sys_pll_18_o
86482   attribute \src "ls180.v:47.14-47.27"
86483   wire output 43 \sys_pll_lck_o
86484   attribute \src "ls180.v:44.13-44.20"
86485   wire input 40 \sys_rst
86486   attribute \src "ls180.v:250.6-250.15"
86487   wire \sys_rst_1
86488   attribute \src "ls180.v:13.13-13.20"
86489   wire input 9 \uart_rx
86490   attribute \src "ls180.v:12.13-12.20"
86491   wire output 8 \uart_tx
86492   attribute \src "ls180.v:10057.12-10057.15"
86493   memory width 32 size 128 \mem
86494   attribute \src "ls180.v:10077.12-10077.19"
86495   memory width 25 size 8 \storage
86496   attribute \src "ls180.v:10091.12-10091.21"
86497   memory width 25 size 8 \storage_1
86498   attribute \src "ls180.v:10105.12-10105.21"
86499   memory width 25 size 8 \storage_2
86500   attribute \src "ls180.v:10119.12-10119.21"
86501   memory width 25 size 8 \storage_3
86502   attribute \src "ls180.v:10133.11-10133.20"
86503   memory width 10 size 16 \storage_4
86504   attribute \src "ls180.v:10150.11-10150.20"
86505   memory width 10 size 16 \storage_5
86506   attribute \src "ls180.v:10167.11-10167.20"
86507   memory width 10 size 32 \storage_6
86508   attribute \src "ls180.v:10181.11-10181.20"
86509   memory width 10 size 32 \storage_7
86510   attribute \src "ls180.v:2819.68-2819.110"
86511   cell $add $add$ls180.v:2819$22
86512     parameter \A_SIGNED 0
86513     parameter \A_WIDTH 1
86514     parameter \B_SIGNED 0
86515     parameter \B_WIDTH 1
86516     parameter \Y_WIDTH 1
86517     connect \A \main_libresocsim_converter0_counter
86518     connect \B 1'1
86519     connect \Y $add$ls180.v:2819$22_Y
86520   end
86521   attribute \src "ls180.v:2879.68-2879.110"
86522   cell $add $add$ls180.v:2879$33
86523     parameter \A_SIGNED 0
86524     parameter \A_WIDTH 1
86525     parameter \B_SIGNED 0
86526     parameter \B_WIDTH 1
86527     parameter \Y_WIDTH 1
86528     connect \A \main_libresocsim_converter1_counter
86529     connect \B 1'1
86530     connect \Y $add$ls180.v:2879$33_Y
86531   end
86532   attribute \src "ls180.v:2939.68-2939.110"
86533   cell $add $add$ls180.v:2939$44
86534     parameter \A_SIGNED 0
86535     parameter \A_WIDTH 1
86536     parameter \B_SIGNED 0
86537     parameter \B_WIDTH 1
86538     parameter \Y_WIDTH 1
86539     connect \A \main_libresocsim_converter2_counter
86540     connect \B 1'1
86541     connect \Y $add$ls180.v:2939$44_Y
86542   end
86543   attribute \src "ls180.v:4072.54-4072.83"
86544   cell $add $add$ls180.v:4072$537
86545     parameter \A_SIGNED 0
86546     parameter \A_WIDTH 1
86547     parameter \B_SIGNED 0
86548     parameter \B_WIDTH 1
86549     parameter \Y_WIDTH 1
86550     connect \A \main_converter_counter
86551     connect \B 1'1
86552     connect \Y $add$ls180.v:4072$537_Y
86553   end
86554   attribute \src "ls180.v:4172.36-4172.89"
86555   cell $add $add$ls180.v:4172$583
86556     parameter \A_SIGNED 0
86557     parameter \A_WIDTH 5
86558     parameter \B_SIGNED 0
86559     parameter \B_WIDTH 1
86560     parameter \Y_WIDTH 5
86561     connect \A \main_uart_tx_fifo_level0
86562     connect \B \main_uart_tx_fifo_readable
86563     connect \Y $add$ls180.v:4172$583_Y
86564   end
86565   attribute \src "ls180.v:4202.36-4202.89"
86566   cell $add $add$ls180.v:4202$594
86567     parameter \A_SIGNED 0
86568     parameter \A_WIDTH 5
86569     parameter \B_SIGNED 0
86570     parameter \B_WIDTH 1
86571     parameter \Y_WIDTH 5
86572     connect \A \main_uart_rx_fifo_level0
86573     connect \B \main_uart_rx_fifo_readable
86574     connect \Y $add$ls180.v:4202$594_Y
86575   end
86576   attribute \src "ls180.v:4257.54-4257.83"
86577   cell $add $add$ls180.v:4257$607
86578     parameter \A_SIGNED 0
86579     parameter \A_WIDTH 3
86580     parameter \B_SIGNED 0
86581     parameter \B_WIDTH 1
86582     parameter \Y_WIDTH 3
86583     connect \A \main_spimaster27_count
86584     connect \B 1'1
86585     connect \Y $add$ls180.v:4257$607_Y
86586   end
86587   attribute \src "ls180.v:4316.52-4316.79"
86588   cell $add $add$ls180.v:4316$615
86589     parameter \A_SIGNED 0
86590     parameter \A_WIDTH 3
86591     parameter \B_SIGNED 0
86592     parameter \B_WIDTH 1
86593     parameter \Y_WIDTH 3
86594     connect \A \main_spisdcard_count
86595     connect \B 1'1
86596     connect \Y $add$ls180.v:4316$615_Y
86597   end
86598   attribute \src "ls180.v:4420.58-4420.86"
86599   cell $add $add$ls180.v:4420$643
86600     parameter \A_SIGNED 0
86601     parameter \A_WIDTH 8
86602     parameter \B_SIGNED 0
86603     parameter \B_WIDTH 1
86604     parameter \Y_WIDTH 8
86605     connect \A \main_sdphy_init_count
86606     connect \B 1'1
86607     connect \Y $add$ls180.v:4420$643_Y
86608   end
86609   attribute \src "ls180.v:4477.58-4477.86"
86610   cell $add $add$ls180.v:4477$646
86611     parameter \A_SIGNED 0
86612     parameter \A_WIDTH 8
86613     parameter \B_SIGNED 0
86614     parameter \B_WIDTH 1
86615     parameter \Y_WIDTH 8
86616     connect \A \main_sdphy_cmdw_count
86617     connect \B 1'1
86618     connect \Y $add$ls180.v:4477$646_Y
86619   end
86620   attribute \src "ls180.v:4494.58-4494.86"
86621   cell $add $add$ls180.v:4494$648
86622     parameter \A_SIGNED 0
86623     parameter \A_WIDTH 8
86624     parameter \B_SIGNED 0
86625     parameter \B_WIDTH 1
86626     parameter \Y_WIDTH 8
86627     connect \A \main_sdphy_cmdw_count
86628     connect \B 1'1
86629     connect \Y $add$ls180.v:4494$648_Y
86630   end
86631   attribute \src "ls180.v:4587.59-4587.87"
86632   cell $add $add$ls180.v:4587$665
86633     parameter \A_SIGNED 0
86634     parameter \A_WIDTH 8
86635     parameter \B_SIGNED 0
86636     parameter \B_WIDTH 1
86637     parameter \Y_WIDTH 8
86638     connect \A \main_sdphy_cmdr_count
86639     connect \B 1'1
86640     connect \Y $add$ls180.v:4587$665_Y
86641   end
86642   attribute \src "ls180.v:4612.59-4612.87"
86643   cell $add $add$ls180.v:4612$668
86644     parameter \A_SIGNED 0
86645     parameter \A_WIDTH 8
86646     parameter \B_SIGNED 0
86647     parameter \B_WIDTH 1
86648     parameter \Y_WIDTH 8
86649     connect \A \main_sdphy_cmdr_count
86650     connect \B 1'1
86651     connect \Y $add$ls180.v:4612$668_Y
86652   end
86653   attribute \src "ls180.v:4734.53-4734.82"
86654   cell $add $add$ls180.v:4734$685
86655     parameter \A_SIGNED 0
86656     parameter \A_WIDTH 8
86657     parameter \B_SIGNED 0
86658     parameter \B_WIDTH 1
86659     parameter \Y_WIDTH 8
86660     connect \A \main_sdphy_dataw_count
86661     connect \B 1'1
86662     connect \Y $add$ls180.v:4734$685_Y
86663   end
86664   attribute \src "ls180.v:4845.65-4845.114"
86665   cell $add $add$ls180.v:4845$699
86666     parameter \A_SIGNED 0
86667     parameter \A_WIDTH 10
86668     parameter \B_SIGNED 0
86669     parameter \B_WIDTH 4
86670     parameter \Y_WIDTH 10
86671     connect \A \main_sdphy_datar_sink_payload_block_length
86672     connect \B 4'1000
86673     connect \Y $add$ls180.v:4845$699_Y
86674   end
86675   attribute \src "ls180.v:4850.62-4850.91"
86676   cell $add $add$ls180.v:4850$702
86677     parameter \A_SIGNED 0
86678     parameter \A_WIDTH 10
86679     parameter \B_SIGNED 0
86680     parameter \B_WIDTH 1
86681     parameter \Y_WIDTH 10
86682     connect \A \main_sdphy_datar_count
86683     connect \B 1'1
86684     connect \Y $add$ls180.v:4850$702_Y
86685   end
86686   attribute \src "ls180.v:4876.61-4876.90"
86687   cell $add $add$ls180.v:4876$705
86688     parameter \A_SIGNED 0
86689     parameter \A_WIDTH 10
86690     parameter \B_SIGNED 0
86691     parameter \B_WIDTH 1
86692     parameter \Y_WIDTH 10
86693     connect \A \main_sdphy_datar_count
86694     connect \B 1'1
86695     connect \Y $add$ls180.v:4876$705_Y
86696   end
86697   attribute \src "ls180.v:5080.80-5080.117"
86698   cell $add $add$ls180.v:5080$890
86699     parameter \A_SIGNED 0
86700     parameter \A_WIDTH 3
86701     parameter \B_SIGNED 0
86702     parameter \B_WIDTH 1
86703     parameter \Y_WIDTH 3
86704     connect \A \main_sdcore_crc16_inserter_cnt
86705     connect \B 1'1
86706     connect \Y $add$ls180.v:5080$890_Y
86707   end
86708   attribute \src "ls180.v:5274.54-5274.82"
86709   cell $add $add$ls180.v:5274$965
86710     parameter \A_SIGNED 0
86711     parameter \A_WIDTH 3
86712     parameter \B_SIGNED 0
86713     parameter \B_WIDTH 1
86714     parameter \Y_WIDTH 3
86715     connect \A \main_sdcore_cmd_count
86716     connect \B 1'1
86717     connect \Y $add$ls180.v:5274$965_Y
86718   end
86719   attribute \src "ls180.v:5326.55-5326.84"
86720   cell $add $add$ls180.v:5326$975
86721     parameter \A_SIGNED 0
86722     parameter \A_WIDTH 32
86723     parameter \B_SIGNED 0
86724     parameter \B_WIDTH 1
86725     parameter \Y_WIDTH 32
86726     connect \A \main_sdcore_data_count
86727     connect \B 1'1
86728     connect \Y $add$ls180.v:5326$975_Y
86729   end
86730   attribute \src "ls180.v:5352.57-5352.86"
86731   cell $add $add$ls180.v:5352$983
86732     parameter \A_SIGNED 0
86733     parameter \A_WIDTH 32
86734     parameter \B_SIGNED 0
86735     parameter \B_WIDTH 1
86736     parameter \Y_WIDTH 32
86737     connect \A \main_sdcore_data_count
86738     connect \B 1'1
86739     connect \Y $add$ls180.v:5352$983_Y
86740   end
86741   attribute \src "ls180.v:5473.51-5473.134"
86742   cell $add $add$ls180.v:5473$999
86743     parameter \A_SIGNED 0
86744     parameter \A_WIDTH 32
86745     parameter \B_SIGNED 0
86746     parameter \B_WIDTH 32
86747     parameter \Y_WIDTH 32
86748     connect \A \main_sdblock2mem_wishbonedmawriter_base
86749     connect \B \main_sdblock2mem_wishbonedmawriter_offset
86750     connect \Y $add$ls180.v:5473$999_Y
86751   end
86752   attribute \src "ls180.v:5476.77-5476.125"
86753   cell $add $add$ls180.v:5476$1001
86754     parameter \A_SIGNED 0
86755     parameter \A_WIDTH 32
86756     parameter \B_SIGNED 0
86757     parameter \B_WIDTH 1
86758     parameter \Y_WIDTH 32
86759     connect \A \main_sdblock2mem_wishbonedmawriter_offset
86760     connect \B 1'1
86761     connect \Y $add$ls180.v:5476$1001_Y
86762   end
86763   attribute \src "ls180.v:5569.50-5569.105"
86764   cell $add $add$ls180.v:5569$1010
86765     parameter \A_SIGNED 0
86766     parameter \A_WIDTH 32
86767     parameter \B_SIGNED 0
86768     parameter \B_WIDTH 32
86769     parameter \Y_WIDTH 32
86770     connect \A \main_sdmem2block_dma_base
86771     connect \B \main_sdmem2block_dma_offset
86772     connect \Y $add$ls180.v:5569$1010_Y
86773   end
86774   attribute \src "ls180.v:5571.77-5571.111"
86775   cell $add $add$ls180.v:5571$1011
86776     parameter \A_SIGNED 0
86777     parameter \A_WIDTH 32
86778     parameter \B_SIGNED 0
86779     parameter \B_WIDTH 1
86780     parameter \Y_WIDTH 32
86781     connect \A \main_sdmem2block_dma_offset
86782     connect \B 1'1
86783     connect \Y $add$ls180.v:5571$1011_Y
86784   end
86785   attribute \src "ls180.v:7503.36-7503.70"
86786   cell $add $add$ls180.v:7503$2415
86787     parameter \A_SIGNED 0
86788     parameter \A_WIDTH 32
86789     parameter \B_SIGNED 0
86790     parameter \B_WIDTH 1
86791     parameter \Y_WIDTH 32
86792     connect \A \main_libresocsim_bus_errors
86793     connect \B 1'1
86794     connect \Y $add$ls180.v:7503$2415_Y
86795   end
86796   attribute \src "ls180.v:7588.37-7588.72"
86797   cell $add $add$ls180.v:7588$2436
86798     parameter \A_SIGNED 0
86799     parameter \A_WIDTH 4
86800     parameter \B_SIGNED 0
86801     parameter \B_WIDTH 1
86802     parameter \Y_WIDTH 4
86803     connect \A \main_sdram_sequencer_counter
86804     connect \B 1'1
86805     connect \Y $add$ls180.v:7588$2436_Y
86806   end
86807   attribute \src "ls180.v:7605.60-7605.119"
86808   cell $add $add$ls180.v:7605$2440
86809     parameter \A_SIGNED 0
86810     parameter \A_WIDTH 3
86811     parameter \B_SIGNED 0
86812     parameter \B_WIDTH 1
86813     parameter \Y_WIDTH 3
86814     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
86815     connect \B 1'1
86816     connect \Y $add$ls180.v:7605$2440_Y
86817   end
86818   attribute \src "ls180.v:7608.60-7608.119"
86819   cell $add $add$ls180.v:7608$2441
86820     parameter \A_SIGNED 0
86821     parameter \A_WIDTH 3
86822     parameter \B_SIGNED 0
86823     parameter \B_WIDTH 1
86824     parameter \Y_WIDTH 3
86825     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
86826     connect \B 1'1
86827     connect \Y $add$ls180.v:7608$2441_Y
86828   end
86829   attribute \src "ls180.v:7612.59-7612.116"
86830   cell $add $add$ls180.v:7612$2446
86831     parameter \A_SIGNED 0
86832     parameter \A_WIDTH 4
86833     parameter \B_SIGNED 0
86834     parameter \B_WIDTH 1
86835     parameter \Y_WIDTH 4
86836     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
86837     connect \B 1'1
86838     connect \Y $add$ls180.v:7612$2446_Y
86839   end
86840   attribute \src "ls180.v:7651.60-7651.119"
86841   cell $add $add$ls180.v:7651$2456
86842     parameter \A_SIGNED 0
86843     parameter \A_WIDTH 3
86844     parameter \B_SIGNED 0
86845     parameter \B_WIDTH 1
86846     parameter \Y_WIDTH 3
86847     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
86848     connect \B 1'1
86849     connect \Y $add$ls180.v:7651$2456_Y
86850   end
86851   attribute \src "ls180.v:7654.60-7654.119"
86852   cell $add $add$ls180.v:7654$2457
86853     parameter \A_SIGNED 0
86854     parameter \A_WIDTH 3
86855     parameter \B_SIGNED 0
86856     parameter \B_WIDTH 1
86857     parameter \Y_WIDTH 3
86858     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
86859     connect \B 1'1
86860     connect \Y $add$ls180.v:7654$2457_Y
86861   end
86862   attribute \src "ls180.v:7658.59-7658.116"
86863   cell $add $add$ls180.v:7658$2462
86864     parameter \A_SIGNED 0
86865     parameter \A_WIDTH 4
86866     parameter \B_SIGNED 0
86867     parameter \B_WIDTH 1
86868     parameter \Y_WIDTH 4
86869     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
86870     connect \B 1'1
86871     connect \Y $add$ls180.v:7658$2462_Y
86872   end
86873   attribute \src "ls180.v:7697.60-7697.119"
86874   cell $add $add$ls180.v:7697$2472
86875     parameter \A_SIGNED 0
86876     parameter \A_WIDTH 3
86877     parameter \B_SIGNED 0
86878     parameter \B_WIDTH 1
86879     parameter \Y_WIDTH 3
86880     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
86881     connect \B 1'1
86882     connect \Y $add$ls180.v:7697$2472_Y
86883   end
86884   attribute \src "ls180.v:7700.60-7700.119"
86885   cell $add $add$ls180.v:7700$2473
86886     parameter \A_SIGNED 0
86887     parameter \A_WIDTH 3
86888     parameter \B_SIGNED 0
86889     parameter \B_WIDTH 1
86890     parameter \Y_WIDTH 3
86891     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
86892     connect \B 1'1
86893     connect \Y $add$ls180.v:7700$2473_Y
86894   end
86895   attribute \src "ls180.v:7704.59-7704.116"
86896   cell $add $add$ls180.v:7704$2478
86897     parameter \A_SIGNED 0
86898     parameter \A_WIDTH 4
86899     parameter \B_SIGNED 0
86900     parameter \B_WIDTH 1
86901     parameter \Y_WIDTH 4
86902     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
86903     connect \B 1'1
86904     connect \Y $add$ls180.v:7704$2478_Y
86905   end
86906   attribute \src "ls180.v:7743.60-7743.119"
86907   cell $add $add$ls180.v:7743$2488
86908     parameter \A_SIGNED 0
86909     parameter \A_WIDTH 3
86910     parameter \B_SIGNED 0
86911     parameter \B_WIDTH 1
86912     parameter \Y_WIDTH 3
86913     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
86914     connect \B 1'1
86915     connect \Y $add$ls180.v:7743$2488_Y
86916   end
86917   attribute \src "ls180.v:7746.60-7746.119"
86918   cell $add $add$ls180.v:7746$2489
86919     parameter \A_SIGNED 0
86920     parameter \A_WIDTH 3
86921     parameter \B_SIGNED 0
86922     parameter \B_WIDTH 1
86923     parameter \Y_WIDTH 3
86924     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
86925     connect \B 1'1
86926     connect \Y $add$ls180.v:7746$2489_Y
86927   end
86928   attribute \src "ls180.v:7750.59-7750.116"
86929   cell $add $add$ls180.v:7750$2494
86930     parameter \A_SIGNED 0
86931     parameter \A_WIDTH 4
86932     parameter \B_SIGNED 0
86933     parameter \B_WIDTH 1
86934     parameter \Y_WIDTH 4
86935     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
86936     connect \B 1'1
86937     connect \Y $add$ls180.v:7750$2494_Y
86938   end
86939   attribute \src "ls180.v:7980.34-7980.66"
86940   cell $add $add$ls180.v:7980$2548
86941     parameter \A_SIGNED 0
86942     parameter \A_WIDTH 4
86943     parameter \B_SIGNED 0
86944     parameter \B_WIDTH 1
86945     parameter \Y_WIDTH 4
86946     connect \A \main_uart_phy_tx_bitcount
86947     connect \B 1'1
86948     connect \Y $add$ls180.v:7980$2548_Y
86949   end
86950   attribute \src "ls180.v:7996.73-7996.131"
86951   cell $add $add$ls180.v:7996$2551
86952     parameter \A_SIGNED 0
86953     parameter \A_WIDTH 32
86954     parameter \B_SIGNED 0
86955     parameter \B_WIDTH 32
86956     parameter \Y_WIDTH 33
86957     connect \A \main_uart_phy_phase_accumulator_tx
86958     connect \B \main_uart_phy_storage
86959     connect \Y $add$ls180.v:7996$2551_Y
86960   end
86961   attribute \src "ls180.v:8009.34-8009.66"
86962   cell $add $add$ls180.v:8009$2555
86963     parameter \A_SIGNED 0
86964     parameter \A_WIDTH 4
86965     parameter \B_SIGNED 0
86966     parameter \B_WIDTH 1
86967     parameter \Y_WIDTH 4
86968     connect \A \main_uart_phy_rx_bitcount
86969     connect \B 1'1
86970     connect \Y $add$ls180.v:8009$2555_Y
86971   end
86972   attribute \src "ls180.v:8028.73-8028.131"
86973   cell $add $add$ls180.v:8028$2558
86974     parameter \A_SIGNED 0
86975     parameter \A_WIDTH 32
86976     parameter \B_SIGNED 0
86977     parameter \B_WIDTH 32
86978     parameter \Y_WIDTH 33
86979     connect \A \main_uart_phy_phase_accumulator_rx
86980     connect \B \main_uart_phy_storage
86981     connect \Y $add$ls180.v:8028$2558_Y
86982   end
86983   attribute \src "ls180.v:8054.33-8054.65"
86984   cell $add $add$ls180.v:8054$2566
86985     parameter \A_SIGNED 0
86986     parameter \A_WIDTH 4
86987     parameter \B_SIGNED 0
86988     parameter \B_WIDTH 1
86989     parameter \Y_WIDTH 4
86990     connect \A \main_uart_tx_fifo_produce
86991     connect \B 1'1
86992     connect \Y $add$ls180.v:8054$2566_Y
86993   end
86994   attribute \src "ls180.v:8057.33-8057.65"
86995   cell $add $add$ls180.v:8057$2567
86996     parameter \A_SIGNED 0
86997     parameter \A_WIDTH 4
86998     parameter \B_SIGNED 0
86999     parameter \B_WIDTH 1
87000     parameter \Y_WIDTH 4
87001     connect \A \main_uart_tx_fifo_consume
87002     connect \B 1'1
87003     connect \Y $add$ls180.v:8057$2567_Y
87004   end
87005   attribute \src "ls180.v:8061.33-8061.64"
87006   cell $add $add$ls180.v:8061$2572
87007     parameter \A_SIGNED 0
87008     parameter \A_WIDTH 5
87009     parameter \B_SIGNED 0
87010     parameter \B_WIDTH 1
87011     parameter \Y_WIDTH 5
87012     connect \A \main_uart_tx_fifo_level0
87013     connect \B 1'1
87014     connect \Y $add$ls180.v:8061$2572_Y
87015   end
87016   attribute \src "ls180.v:8076.33-8076.65"
87017   cell $add $add$ls180.v:8076$2577
87018     parameter \A_SIGNED 0
87019     parameter \A_WIDTH 4
87020     parameter \B_SIGNED 0
87021     parameter \B_WIDTH 1
87022     parameter \Y_WIDTH 4
87023     connect \A \main_uart_rx_fifo_produce
87024     connect \B 1'1
87025     connect \Y $add$ls180.v:8076$2577_Y
87026   end
87027   attribute \src "ls180.v:8079.33-8079.65"
87028   cell $add $add$ls180.v:8079$2578
87029     parameter \A_SIGNED 0
87030     parameter \A_WIDTH 4
87031     parameter \B_SIGNED 0
87032     parameter \B_WIDTH 1
87033     parameter \Y_WIDTH 4
87034     connect \A \main_uart_rx_fifo_consume
87035     connect \B 1'1
87036     connect \Y $add$ls180.v:8079$2578_Y
87037   end
87038   attribute \src "ls180.v:8083.33-8083.64"
87039   cell $add $add$ls180.v:8083$2583
87040     parameter \A_SIGNED 0
87041     parameter \A_WIDTH 5
87042     parameter \B_SIGNED 0
87043     parameter \B_WIDTH 1
87044     parameter \Y_WIDTH 5
87045     connect \A \main_uart_rx_fifo_level0
87046     connect \B 1'1
87047     connect \Y $add$ls180.v:8083$2583_Y
87048   end
87049   attribute \src "ls180.v:8104.35-8104.70"
87050   cell $add $add$ls180.v:8104$2585
87051     parameter \A_SIGNED 0
87052     parameter \A_WIDTH 16
87053     parameter \B_SIGNED 0
87054     parameter \B_WIDTH 1
87055     parameter \Y_WIDTH 16
87056     connect \A \main_spimaster30_clk_divider
87057     connect \B 1'1
87058     connect \Y $add$ls180.v:8104$2585_Y
87059   end
87060   attribute \src "ls180.v:8139.34-8139.68"
87061   cell $add $add$ls180.v:8139$2590
87062     parameter \A_SIGNED 0
87063     parameter \A_WIDTH 16
87064     parameter \B_SIGNED 0
87065     parameter \B_WIDTH 1
87066     parameter \Y_WIDTH 16
87067     connect \A \main_spisdcard_clk_divider1
87068     connect \B 1'1
87069     connect \Y $add$ls180.v:8139$2590_Y
87070   end
87071   attribute \src "ls180.v:8175.25-8175.49"
87072   cell $add $add$ls180.v:8175$2595
87073     parameter \A_SIGNED 0
87074     parameter \A_WIDTH 32
87075     parameter \B_SIGNED 0
87076     parameter \B_WIDTH 1
87077     parameter \Y_WIDTH 32
87078     connect \A \main_pwm0_counter
87079     connect \B 1'1
87080     connect \Y $add$ls180.v:8175$2595_Y
87081   end
87082   attribute \src "ls180.v:8189.25-8189.49"
87083   cell $add $add$ls180.v:8189$2599
87084     parameter \A_SIGNED 0
87085     parameter \A_WIDTH 32
87086     parameter \B_SIGNED 0
87087     parameter \B_WIDTH 1
87088     parameter \Y_WIDTH 32
87089     connect \A \main_pwm1_counter
87090     connect \B 1'1
87091     connect \Y $add$ls180.v:8189$2599_Y
87092   end
87093   attribute \src "ls180.v:8203.31-8203.61"
87094   cell $add $add$ls180.v:8203$2604
87095     parameter \A_SIGNED 0
87096     parameter \A_WIDTH 9
87097     parameter \B_SIGNED 0
87098     parameter \B_WIDTH 1
87099     parameter \Y_WIDTH 9
87100     connect \A \main_sdphy_clocker_clks
87101     connect \B 1'1
87102     connect \Y $add$ls180.v:8203$2604_Y
87103   end
87104   attribute \src "ls180.v:8226.45-8226.88"
87105   cell $add $add$ls180.v:8226$2608
87106     parameter \A_SIGNED 0
87107     parameter \A_WIDTH 3
87108     parameter \B_SIGNED 0
87109     parameter \B_WIDTH 1
87110     parameter \Y_WIDTH 3
87111     connect \A \main_sdphy_cmdr_cmdr_converter_demux
87112     connect \B 1'1
87113     connect \Y $add$ls180.v:8226$2608_Y
87114   end
87115   attribute \src "ls180.v:8272.71-8272.114"
87116   cell $add $add$ls180.v:8272$2614
87117     parameter \A_SIGNED 0
87118     parameter \A_WIDTH 3
87119     parameter \B_SIGNED 0
87120     parameter \B_WIDTH 1
87121     parameter \Y_WIDTH 4
87122     connect \A \main_sdphy_cmdr_cmdr_converter_demux
87123     connect \B 1'1
87124     connect \Y $add$ls180.v:8272$2614_Y
87125   end
87126   attribute \src "ls180.v:8307.46-8307.90"
87127   cell $add $add$ls180.v:8307$2620
87128     parameter \A_SIGNED 0
87129     parameter \A_WIDTH 3
87130     parameter \B_SIGNED 0
87131     parameter \B_WIDTH 1
87132     parameter \Y_WIDTH 3
87133     connect \A \main_sdphy_dataw_crcr_converter_demux
87134     connect \B 1'1
87135     connect \Y $add$ls180.v:8307$2620_Y
87136   end
87137   attribute \src "ls180.v:8353.72-8353.116"
87138   cell $add $add$ls180.v:8353$2626
87139     parameter \A_SIGNED 0
87140     parameter \A_WIDTH 3
87141     parameter \B_SIGNED 0
87142     parameter \B_WIDTH 1
87143     parameter \Y_WIDTH 4
87144     connect \A \main_sdphy_dataw_crcr_converter_demux
87145     connect \B 1'1
87146     connect \Y $add$ls180.v:8353$2626_Y
87147   end
87148   attribute \src "ls180.v:8386.47-8386.92"
87149   cell $add $add$ls180.v:8386$2632
87150     parameter \A_SIGNED 0
87151     parameter \A_WIDTH 1
87152     parameter \B_SIGNED 0
87153     parameter \B_WIDTH 1
87154     parameter \Y_WIDTH 1
87155     connect \A \main_sdphy_datar_datar_converter_demux
87156     connect \B 1'1
87157     connect \Y $add$ls180.v:8386$2632_Y
87158   end
87159   attribute \src "ls180.v:8414.73-8414.118"
87160   cell $add $add$ls180.v:8414$2638
87161     parameter \A_SIGNED 0
87162     parameter \A_WIDTH 1
87163     parameter \B_SIGNED 0
87164     parameter \B_WIDTH 1
87165     parameter \Y_WIDTH 2
87166     connect \A \main_sdphy_datar_datar_converter_demux
87167     connect \B 1'1
87168     connect \Y $add$ls180.v:8414$2638_Y
87169   end
87170   attribute \src "ls180.v:8526.39-8526.75"
87171   cell $add $add$ls180.v:8526$2651
87172     parameter \A_SIGNED 0
87173     parameter \A_WIDTH 4
87174     parameter \B_SIGNED 0
87175     parameter \B_WIDTH 1
87176     parameter \Y_WIDTH 4
87177     connect \A \main_sdcore_crc16_checker_cnt
87178     connect \B 1'1
87179     connect \Y $add$ls180.v:8526$2651_Y
87180   end
87181   attribute \src "ls180.v:8587.37-8587.73"
87182   cell $add $add$ls180.v:8587$2655
87183     parameter \A_SIGNED 0
87184     parameter \A_WIDTH 5
87185     parameter \B_SIGNED 0
87186     parameter \B_WIDTH 1
87187     parameter \Y_WIDTH 5
87188     connect \A \main_sdblock2mem_fifo_produce
87189     connect \B 1'1
87190     connect \Y $add$ls180.v:8587$2655_Y
87191   end
87192   attribute \src "ls180.v:8590.37-8590.73"
87193   cell $add $add$ls180.v:8590$2656
87194     parameter \A_SIGNED 0
87195     parameter \A_WIDTH 5
87196     parameter \B_SIGNED 0
87197     parameter \B_WIDTH 1
87198     parameter \Y_WIDTH 5
87199     connect \A \main_sdblock2mem_fifo_consume
87200     connect \B 1'1
87201     connect \Y $add$ls180.v:8590$2656_Y
87202   end
87203   attribute \src "ls180.v:8594.36-8594.70"
87204   cell $add $add$ls180.v:8594$2661
87205     parameter \A_SIGNED 0
87206     parameter \A_WIDTH 6
87207     parameter \B_SIGNED 0
87208     parameter \B_WIDTH 1
87209     parameter \Y_WIDTH 6
87210     connect \A \main_sdblock2mem_fifo_level
87211     connect \B 1'1
87212     connect \Y $add$ls180.v:8594$2661_Y
87213   end
87214   attribute \src "ls180.v:8609.41-8609.80"
87215   cell $add $add$ls180.v:8609$2665
87216     parameter \A_SIGNED 0
87217     parameter \A_WIDTH 2
87218     parameter \B_SIGNED 0
87219     parameter \B_WIDTH 1
87220     parameter \Y_WIDTH 2
87221     connect \A \main_sdblock2mem_converter_demux
87222     connect \B 1'1
87223     connect \Y $add$ls180.v:8609$2665_Y
87224   end
87225   attribute \src "ls180.v:8643.67-8643.106"
87226   cell $add $add$ls180.v:8643$2671
87227     parameter \A_SIGNED 0
87228     parameter \A_WIDTH 2
87229     parameter \B_SIGNED 0
87230     parameter \B_WIDTH 1
87231     parameter \Y_WIDTH 3
87232     connect \A \main_sdblock2mem_converter_demux
87233     connect \B 1'1
87234     connect \Y $add$ls180.v:8643$2671_Y
87235   end
87236   attribute \src "ls180.v:8669.39-8669.76"
87237   cell $add $add$ls180.v:8669$2673
87238     parameter \A_SIGNED 0
87239     parameter \A_WIDTH 2
87240     parameter \B_SIGNED 0
87241     parameter \B_WIDTH 1
87242     parameter \Y_WIDTH 2
87243     connect \A \main_sdmem2block_converter_mux
87244     connect \B 1'1
87245     connect \Y $add$ls180.v:8669$2673_Y
87246   end
87247   attribute \src "ls180.v:8673.37-8673.73"
87248   cell $add $add$ls180.v:8673$2677
87249     parameter \A_SIGNED 0
87250     parameter \A_WIDTH 5
87251     parameter \B_SIGNED 0
87252     parameter \B_WIDTH 1
87253     parameter \Y_WIDTH 5
87254     connect \A \main_sdmem2block_fifo_produce
87255     connect \B 1'1
87256     connect \Y $add$ls180.v:8673$2677_Y
87257   end
87258   attribute \src "ls180.v:8676.37-8676.73"
87259   cell $add $add$ls180.v:8676$2678
87260     parameter \A_SIGNED 0
87261     parameter \A_WIDTH 5
87262     parameter \B_SIGNED 0
87263     parameter \B_WIDTH 1
87264     parameter \Y_WIDTH 5
87265     connect \A \main_sdmem2block_fifo_consume
87266     connect \B 1'1
87267     connect \Y $add$ls180.v:8676$2678_Y
87268   end
87269   attribute \src "ls180.v:8680.36-8680.70"
87270   cell $add $add$ls180.v:8680$2683
87271     parameter \A_SIGNED 0
87272     parameter \A_WIDTH 6
87273     parameter \B_SIGNED 0
87274     parameter \B_WIDTH 1
87275     parameter \Y_WIDTH 6
87276     connect \A \main_sdmem2block_fifo_level
87277     connect \B 1'1
87278     connect \Y $add$ls180.v:8680$2683_Y
87279   end
87280   attribute \src "ls180.v:2813.9-2813.80"
87281   cell $and $and$ls180.v:2813$17
87282     parameter \A_SIGNED 0
87283     parameter \A_WIDTH 1
87284     parameter \B_SIGNED 0
87285     parameter \B_WIDTH 1
87286     parameter \Y_WIDTH 1
87287     connect \A \main_libresocsim_libresoc_ibus_stb
87288     connect \B \main_libresocsim_libresoc_ibus_cyc
87289     connect \Y $and$ls180.v:2813$17_Y
87290   end
87291   attribute \src "ls180.v:2831.9-2831.80"
87292   cell $and $and$ls180.v:2831$24
87293     parameter \A_SIGNED 0
87294     parameter \A_WIDTH 1
87295     parameter \B_SIGNED 0
87296     parameter \B_WIDTH 1
87297     parameter \Y_WIDTH 1
87298     connect \A \main_libresocsim_libresoc_ibus_stb
87299     connect \B \main_libresocsim_libresoc_ibus_cyc
87300     connect \Y $and$ls180.v:2831$24_Y
87301   end
87302   attribute \src "ls180.v:2873.9-2873.80"
87303   cell $and $and$ls180.v:2873$28
87304     parameter \A_SIGNED 0
87305     parameter \A_WIDTH 1
87306     parameter \B_SIGNED 0
87307     parameter \B_WIDTH 1
87308     parameter \Y_WIDTH 1
87309     connect \A \main_libresocsim_libresoc_dbus_stb
87310     connect \B \main_libresocsim_libresoc_dbus_cyc
87311     connect \Y $and$ls180.v:2873$28_Y
87312   end
87313   attribute \src "ls180.v:2891.9-2891.80"
87314   cell $and $and$ls180.v:2891$35
87315     parameter \A_SIGNED 0
87316     parameter \A_WIDTH 1
87317     parameter \B_SIGNED 0
87318     parameter \B_WIDTH 1
87319     parameter \Y_WIDTH 1
87320     connect \A \main_libresocsim_libresoc_dbus_stb
87321     connect \B \main_libresocsim_libresoc_dbus_cyc
87322     connect \Y $and$ls180.v:2891$35_Y
87323   end
87324   attribute \src "ls180.v:2933.9-2933.86"
87325   cell $and $and$ls180.v:2933$39
87326     parameter \A_SIGNED 0
87327     parameter \A_WIDTH 1
87328     parameter \B_SIGNED 0
87329     parameter \B_WIDTH 1
87330     parameter \Y_WIDTH 1
87331     connect \A \main_libresocsim_libresoc_jtag_wb_stb
87332     connect \B \main_libresocsim_libresoc_jtag_wb_cyc
87333     connect \Y $and$ls180.v:2933$39_Y
87334   end
87335   attribute \src "ls180.v:2951.9-2951.86"
87336   cell $and $and$ls180.v:2951$46
87337     parameter \A_SIGNED 0
87338     parameter \A_WIDTH 1
87339     parameter \B_SIGNED 0
87340     parameter \B_WIDTH 1
87341     parameter \Y_WIDTH 1
87342     connect \A \main_libresocsim_libresoc_jtag_wb_stb
87343     connect \B \main_libresocsim_libresoc_jtag_wb_cyc
87344     connect \Y $and$ls180.v:2951$46_Y
87345   end
87346   attribute \src "ls180.v:2961.31-2961.90"
87347   cell $and $and$ls180.v:2961$48
87348     parameter \A_SIGNED 0
87349     parameter \A_WIDTH 1
87350     parameter \B_SIGNED 0
87351     parameter \B_WIDTH 1
87352     parameter \Y_WIDTH 1
87353     connect \A \main_libresocsim_ram_bus_cyc
87354     connect \B \main_libresocsim_ram_bus_stb
87355     connect \Y $and$ls180.v:2961$48_Y
87356   end
87357   attribute \src "ls180.v:2961.30-2961.121"
87358   cell $and $and$ls180.v:2961$49
87359     parameter \A_SIGNED 0
87360     parameter \A_WIDTH 1
87361     parameter \B_SIGNED 0
87362     parameter \B_WIDTH 1
87363     parameter \Y_WIDTH 1
87364     connect \A $and$ls180.v:2961$48_Y
87365     connect \B \main_libresocsim_ram_bus_we
87366     connect \Y $and$ls180.v:2961$49_Y
87367   end
87368   attribute \src "ls180.v:2961.29-2961.156"
87369   cell $and $and$ls180.v:2961$50
87370     parameter \A_SIGNED 0
87371     parameter \A_WIDTH 1
87372     parameter \B_SIGNED 0
87373     parameter \B_WIDTH 1
87374     parameter \Y_WIDTH 1
87375     connect \A $and$ls180.v:2961$49_Y
87376     connect \B \main_libresocsim_ram_bus_sel [0]
87377     connect \Y $and$ls180.v:2961$50_Y
87378   end
87379   attribute \src "ls180.v:2962.31-2962.90"
87380   cell $and $and$ls180.v:2962$51
87381     parameter \A_SIGNED 0
87382     parameter \A_WIDTH 1
87383     parameter \B_SIGNED 0
87384     parameter \B_WIDTH 1
87385     parameter \Y_WIDTH 1
87386     connect \A \main_libresocsim_ram_bus_cyc
87387     connect \B \main_libresocsim_ram_bus_stb
87388     connect \Y $and$ls180.v:2962$51_Y
87389   end
87390   attribute \src "ls180.v:2962.30-2962.121"
87391   cell $and $and$ls180.v:2962$52
87392     parameter \A_SIGNED 0
87393     parameter \A_WIDTH 1
87394     parameter \B_SIGNED 0
87395     parameter \B_WIDTH 1
87396     parameter \Y_WIDTH 1
87397     connect \A $and$ls180.v:2962$51_Y
87398     connect \B \main_libresocsim_ram_bus_we
87399     connect \Y $and$ls180.v:2962$52_Y
87400   end
87401   attribute \src "ls180.v:2962.29-2962.156"
87402   cell $and $and$ls180.v:2962$53
87403     parameter \A_SIGNED 0
87404     parameter \A_WIDTH 1
87405     parameter \B_SIGNED 0
87406     parameter \B_WIDTH 1
87407     parameter \Y_WIDTH 1
87408     connect \A $and$ls180.v:2962$52_Y
87409     connect \B \main_libresocsim_ram_bus_sel [1]
87410     connect \Y $and$ls180.v:2962$53_Y
87411   end
87412   attribute \src "ls180.v:2963.31-2963.90"
87413   cell $and $and$ls180.v:2963$54
87414     parameter \A_SIGNED 0
87415     parameter \A_WIDTH 1
87416     parameter \B_SIGNED 0
87417     parameter \B_WIDTH 1
87418     parameter \Y_WIDTH 1
87419     connect \A \main_libresocsim_ram_bus_cyc
87420     connect \B \main_libresocsim_ram_bus_stb
87421     connect \Y $and$ls180.v:2963$54_Y
87422   end
87423   attribute \src "ls180.v:2963.30-2963.121"
87424   cell $and $and$ls180.v:2963$55
87425     parameter \A_SIGNED 0
87426     parameter \A_WIDTH 1
87427     parameter \B_SIGNED 0
87428     parameter \B_WIDTH 1
87429     parameter \Y_WIDTH 1
87430     connect \A $and$ls180.v:2963$54_Y
87431     connect \B \main_libresocsim_ram_bus_we
87432     connect \Y $and$ls180.v:2963$55_Y
87433   end
87434   attribute \src "ls180.v:2963.29-2963.156"
87435   cell $and $and$ls180.v:2963$56
87436     parameter \A_SIGNED 0
87437     parameter \A_WIDTH 1
87438     parameter \B_SIGNED 0
87439     parameter \B_WIDTH 1
87440     parameter \Y_WIDTH 1
87441     connect \A $and$ls180.v:2963$55_Y
87442     connect \B \main_libresocsim_ram_bus_sel [2]
87443     connect \Y $and$ls180.v:2963$56_Y
87444   end
87445   attribute \src "ls180.v:2964.31-2964.90"
87446   cell $and $and$ls180.v:2964$57
87447     parameter \A_SIGNED 0
87448     parameter \A_WIDTH 1
87449     parameter \B_SIGNED 0
87450     parameter \B_WIDTH 1
87451     parameter \Y_WIDTH 1
87452     connect \A \main_libresocsim_ram_bus_cyc
87453     connect \B \main_libresocsim_ram_bus_stb
87454     connect \Y $and$ls180.v:2964$57_Y
87455   end
87456   attribute \src "ls180.v:2964.30-2964.121"
87457   cell $and $and$ls180.v:2964$58
87458     parameter \A_SIGNED 0
87459     parameter \A_WIDTH 1
87460     parameter \B_SIGNED 0
87461     parameter \B_WIDTH 1
87462     parameter \Y_WIDTH 1
87463     connect \A $and$ls180.v:2964$57_Y
87464     connect \B \main_libresocsim_ram_bus_we
87465     connect \Y $and$ls180.v:2964$58_Y
87466   end
87467   attribute \src "ls180.v:2964.29-2964.156"
87468   cell $and $and$ls180.v:2964$59
87469     parameter \A_SIGNED 0
87470     parameter \A_WIDTH 1
87471     parameter \B_SIGNED 0
87472     parameter \B_WIDTH 1
87473     parameter \Y_WIDTH 1
87474     connect \A $and$ls180.v:2964$58_Y
87475     connect \B \main_libresocsim_ram_bus_sel [3]
87476     connect \Y $and$ls180.v:2964$59_Y
87477   end
87478   attribute \src "ls180.v:2973.7-2973.89"
87479   cell $and $and$ls180.v:2973$62
87480     parameter \A_SIGNED 0
87481     parameter \A_WIDTH 1
87482     parameter \B_SIGNED 0
87483     parameter \B_WIDTH 1
87484     parameter \Y_WIDTH 1
87485     connect \A \main_libresocsim_eventmanager_pending_re
87486     connect \B \main_libresocsim_eventmanager_pending_r
87487     connect \Y $and$ls180.v:2973$62_Y
87488   end
87489   attribute \src "ls180.v:2978.32-2978.111"
87490   cell $and $and$ls180.v:2978$63
87491     parameter \A_SIGNED 0
87492     parameter \A_WIDTH 1
87493     parameter \B_SIGNED 0
87494     parameter \B_WIDTH 1
87495     parameter \Y_WIDTH 1
87496     connect \A \main_libresocsim_eventmanager_pending_w
87497     connect \B \main_libresocsim_eventmanager_storage
87498     connect \Y $and$ls180.v:2978$63_Y
87499   end
87500   attribute \src "ls180.v:3092.40-3092.99"
87501   cell $and $and$ls180.v:3092$70
87502     parameter \A_SIGNED 0
87503     parameter \A_WIDTH 1
87504     parameter \B_SIGNED 0
87505     parameter \B_WIDTH 1
87506     parameter \Y_WIDTH 1
87507     connect \A \main_sdram_command_issue_re
87508     connect \B \main_sdram_command_storage [4]
87509     connect \Y $and$ls180.v:3092$70_Y
87510   end
87511   attribute \src "ls180.v:3093.40-3093.99"
87512   cell $and $and$ls180.v:3093$71
87513     parameter \A_SIGNED 0
87514     parameter \A_WIDTH 1
87515     parameter \B_SIGNED 0
87516     parameter \B_WIDTH 1
87517     parameter \Y_WIDTH 1
87518     connect \A \main_sdram_command_issue_re
87519     connect \B \main_sdram_command_storage [5]
87520     connect \Y $and$ls180.v:3093$71_Y
87521   end
87522   attribute \src "ls180.v:3131.38-3131.103"
87523   cell $and $and$ls180.v:3131$77
87524     parameter \A_SIGNED 0
87525     parameter \A_WIDTH 1
87526     parameter \B_SIGNED 0
87527     parameter \B_WIDTH 1
87528     parameter \Y_WIDTH 1
87529     connect \A \main_sdram_sequencer_done1
87530     connect \B $eq$ls180.v:3131$76_Y
87531     connect \Y $and$ls180.v:3131$77_Y
87532   end
87533   attribute \src "ls180.v:3185.50-3185.119"
87534   cell $and $and$ls180.v:3185$85
87535     parameter \A_SIGNED 0
87536     parameter \A_WIDTH 1
87537     parameter \B_SIGNED 0
87538     parameter \B_WIDTH 1
87539     parameter \Y_WIDTH 1
87540     connect \A \main_sdram_bankmachine0_cmd_valid
87541     connect \B \main_sdram_bankmachine0_cmd_ready
87542     connect \Y $and$ls180.v:3185$85_Y
87543   end
87544   attribute \src "ls180.v:3185.49-3185.167"
87545   cell $and $and$ls180.v:3185$86
87546     parameter \A_SIGNED 0
87547     parameter \A_WIDTH 1
87548     parameter \B_SIGNED 0
87549     parameter \B_WIDTH 1
87550     parameter \Y_WIDTH 1
87551     connect \A $and$ls180.v:3185$85_Y
87552     connect \B \main_sdram_bankmachine0_cmd_payload_is_write
87553     connect \Y $and$ls180.v:3185$86_Y
87554   end
87555   attribute \src "ls180.v:3186.49-3186.118"
87556   cell $and $and$ls180.v:3186$87
87557     parameter \A_SIGNED 0
87558     parameter \A_WIDTH 1
87559     parameter \B_SIGNED 0
87560     parameter \B_WIDTH 1
87561     parameter \Y_WIDTH 1
87562     connect \A \main_sdram_bankmachine0_cmd_valid
87563     connect \B \main_sdram_bankmachine0_cmd_ready
87564     connect \Y $and$ls180.v:3186$87_Y
87565   end
87566   attribute \src "ls180.v:3186.48-3186.154"
87567   cell $and $and$ls180.v:3186$88
87568     parameter \A_SIGNED 0
87569     parameter \A_WIDTH 1
87570     parameter \B_SIGNED 0
87571     parameter \B_WIDTH 1
87572     parameter \Y_WIDTH 1
87573     connect \A $and$ls180.v:3186$87_Y
87574     connect \B \main_sdram_bankmachine0_row_open
87575     connect \Y $and$ls180.v:3186$88_Y
87576   end
87577   attribute \src "ls180.v:3187.50-3187.119"
87578   cell $and $and$ls180.v:3187$89
87579     parameter \A_SIGNED 0
87580     parameter \A_WIDTH 1
87581     parameter \B_SIGNED 0
87582     parameter \B_WIDTH 1
87583     parameter \Y_WIDTH 1
87584     connect \A \main_sdram_bankmachine0_cmd_valid
87585     connect \B \main_sdram_bankmachine0_cmd_ready
87586     connect \Y $and$ls180.v:3187$89_Y
87587   end
87588   attribute \src "ls180.v:3187.49-3187.155"
87589   cell $and $and$ls180.v:3187$90
87590     parameter \A_SIGNED 0
87591     parameter \A_WIDTH 1
87592     parameter \B_SIGNED 0
87593     parameter \B_WIDTH 1
87594     parameter \Y_WIDTH 1
87595     connect \A $and$ls180.v:3187$89_Y
87596     connect \B \main_sdram_bankmachine0_row_open
87597     connect \Y $and$ls180.v:3187$90_Y
87598   end
87599   attribute \src "ls180.v:3190.7-3190.114"
87600   cell $and $and$ls180.v:3190$92
87601     parameter \A_SIGNED 0
87602     parameter \A_WIDTH 1
87603     parameter \B_SIGNED 0
87604     parameter \B_WIDTH 1
87605     parameter \Y_WIDTH 1
87606     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
87607     connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
87608     connect \Y $and$ls180.v:3190$92_Y
87609   end
87610   attribute \src "ls180.v:3219.66-3219.246"
87611   cell $and $and$ls180.v:3219$98
87612     parameter \A_SIGNED 0
87613     parameter \A_WIDTH 1
87614     parameter \B_SIGNED 0
87615     parameter \B_WIDTH 1
87616     parameter \Y_WIDTH 1
87617     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
87618     connect \B $or$ls180.v:3219$97_Y
87619     connect \Y $and$ls180.v:3219$98_Y
87620   end
87621   attribute \src "ls180.v:3220.64-3220.187"
87622   cell $and $and$ls180.v:3220$99
87623     parameter \A_SIGNED 0
87624     parameter \A_WIDTH 1
87625     parameter \B_SIGNED 0
87626     parameter \B_WIDTH 1
87627     parameter \Y_WIDTH 1
87628     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
87629     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
87630     connect \Y $and$ls180.v:3220$99_Y
87631   end
87632   attribute \src "ls180.v:3244.9-3244.86"
87633   cell $and $and$ls180.v:3244$105
87634     parameter \A_SIGNED 0
87635     parameter \A_WIDTH 1
87636     parameter \B_SIGNED 0
87637     parameter \B_WIDTH 1
87638     parameter \Y_WIDTH 1
87639     connect \A \main_sdram_bankmachine0_twtpcon_ready
87640     connect \B \main_sdram_bankmachine0_trascon_ready
87641     connect \Y $and$ls180.v:3244$105_Y
87642   end
87643   attribute \src "ls180.v:3256.9-3256.86"
87644   cell $and $and$ls180.v:3256$106
87645     parameter \A_SIGNED 0
87646     parameter \A_WIDTH 1
87647     parameter \B_SIGNED 0
87648     parameter \B_WIDTH 1
87649     parameter \Y_WIDTH 1
87650     connect \A \main_sdram_bankmachine0_twtpcon_ready
87651     connect \B \main_sdram_bankmachine0_trascon_ready
87652     connect \Y $and$ls180.v:3256$106_Y
87653   end
87654   attribute \src "ls180.v:3306.13-3306.87"
87655   cell $and $and$ls180.v:3306$108
87656     parameter \A_SIGNED 0
87657     parameter \A_WIDTH 1
87658     parameter \B_SIGNED 0
87659     parameter \B_WIDTH 1
87660     parameter \Y_WIDTH 1
87661     connect \A \main_sdram_bankmachine0_cmd_ready
87662     connect \B \main_sdram_bankmachine0_auto_precharge
87663     connect \Y $and$ls180.v:3306$108_Y
87664   end
87665   attribute \src "ls180.v:3342.50-3342.119"
87666   cell $and $and$ls180.v:3342$115
87667     parameter \A_SIGNED 0
87668     parameter \A_WIDTH 1
87669     parameter \B_SIGNED 0
87670     parameter \B_WIDTH 1
87671     parameter \Y_WIDTH 1
87672     connect \A \main_sdram_bankmachine1_cmd_valid
87673     connect \B \main_sdram_bankmachine1_cmd_ready
87674     connect \Y $and$ls180.v:3342$115_Y
87675   end
87676   attribute \src "ls180.v:3342.49-3342.167"
87677   cell $and $and$ls180.v:3342$116
87678     parameter \A_SIGNED 0
87679     parameter \A_WIDTH 1
87680     parameter \B_SIGNED 0
87681     parameter \B_WIDTH 1
87682     parameter \Y_WIDTH 1
87683     connect \A $and$ls180.v:3342$115_Y
87684     connect \B \main_sdram_bankmachine1_cmd_payload_is_write
87685     connect \Y $and$ls180.v:3342$116_Y
87686   end
87687   attribute \src "ls180.v:3343.49-3343.118"
87688   cell $and $and$ls180.v:3343$117
87689     parameter \A_SIGNED 0
87690     parameter \A_WIDTH 1
87691     parameter \B_SIGNED 0
87692     parameter \B_WIDTH 1
87693     parameter \Y_WIDTH 1
87694     connect \A \main_sdram_bankmachine1_cmd_valid
87695     connect \B \main_sdram_bankmachine1_cmd_ready
87696     connect \Y $and$ls180.v:3343$117_Y
87697   end
87698   attribute \src "ls180.v:3343.48-3343.154"
87699   cell $and $and$ls180.v:3343$118
87700     parameter \A_SIGNED 0
87701     parameter \A_WIDTH 1
87702     parameter \B_SIGNED 0
87703     parameter \B_WIDTH 1
87704     parameter \Y_WIDTH 1
87705     connect \A $and$ls180.v:3343$117_Y
87706     connect \B \main_sdram_bankmachine1_row_open
87707     connect \Y $and$ls180.v:3343$118_Y
87708   end
87709   attribute \src "ls180.v:3344.50-3344.119"
87710   cell $and $and$ls180.v:3344$119
87711     parameter \A_SIGNED 0
87712     parameter \A_WIDTH 1
87713     parameter \B_SIGNED 0
87714     parameter \B_WIDTH 1
87715     parameter \Y_WIDTH 1
87716     connect \A \main_sdram_bankmachine1_cmd_valid
87717     connect \B \main_sdram_bankmachine1_cmd_ready
87718     connect \Y $and$ls180.v:3344$119_Y
87719   end
87720   attribute \src "ls180.v:3344.49-3344.155"
87721   cell $and $and$ls180.v:3344$120
87722     parameter \A_SIGNED 0
87723     parameter \A_WIDTH 1
87724     parameter \B_SIGNED 0
87725     parameter \B_WIDTH 1
87726     parameter \Y_WIDTH 1
87727     connect \A $and$ls180.v:3344$119_Y
87728     connect \B \main_sdram_bankmachine1_row_open
87729     connect \Y $and$ls180.v:3344$120_Y
87730   end
87731   attribute \src "ls180.v:3347.7-3347.114"
87732   cell $and $and$ls180.v:3347$122
87733     parameter \A_SIGNED 0
87734     parameter \A_WIDTH 1
87735     parameter \B_SIGNED 0
87736     parameter \B_WIDTH 1
87737     parameter \Y_WIDTH 1
87738     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
87739     connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
87740     connect \Y $and$ls180.v:3347$122_Y
87741   end
87742   attribute \src "ls180.v:3376.66-3376.246"
87743   cell $and $and$ls180.v:3376$128
87744     parameter \A_SIGNED 0
87745     parameter \A_WIDTH 1
87746     parameter \B_SIGNED 0
87747     parameter \B_WIDTH 1
87748     parameter \Y_WIDTH 1
87749     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
87750     connect \B $or$ls180.v:3376$127_Y
87751     connect \Y $and$ls180.v:3376$128_Y
87752   end
87753   attribute \src "ls180.v:3377.64-3377.187"
87754   cell $and $and$ls180.v:3377$129
87755     parameter \A_SIGNED 0
87756     parameter \A_WIDTH 1
87757     parameter \B_SIGNED 0
87758     parameter \B_WIDTH 1
87759     parameter \Y_WIDTH 1
87760     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
87761     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
87762     connect \Y $and$ls180.v:3377$129_Y
87763   end
87764   attribute \src "ls180.v:3401.9-3401.86"
87765   cell $and $and$ls180.v:3401$135
87766     parameter \A_SIGNED 0
87767     parameter \A_WIDTH 1
87768     parameter \B_SIGNED 0
87769     parameter \B_WIDTH 1
87770     parameter \Y_WIDTH 1
87771     connect \A \main_sdram_bankmachine1_twtpcon_ready
87772     connect \B \main_sdram_bankmachine1_trascon_ready
87773     connect \Y $and$ls180.v:3401$135_Y
87774   end
87775   attribute \src "ls180.v:3413.9-3413.86"
87776   cell $and $and$ls180.v:3413$136
87777     parameter \A_SIGNED 0
87778     parameter \A_WIDTH 1
87779     parameter \B_SIGNED 0
87780     parameter \B_WIDTH 1
87781     parameter \Y_WIDTH 1
87782     connect \A \main_sdram_bankmachine1_twtpcon_ready
87783     connect \B \main_sdram_bankmachine1_trascon_ready
87784     connect \Y $and$ls180.v:3413$136_Y
87785   end
87786   attribute \src "ls180.v:3463.13-3463.87"
87787   cell $and $and$ls180.v:3463$138
87788     parameter \A_SIGNED 0
87789     parameter \A_WIDTH 1
87790     parameter \B_SIGNED 0
87791     parameter \B_WIDTH 1
87792     parameter \Y_WIDTH 1
87793     connect \A \main_sdram_bankmachine1_cmd_ready
87794     connect \B \main_sdram_bankmachine1_auto_precharge
87795     connect \Y $and$ls180.v:3463$138_Y
87796   end
87797   attribute \src "ls180.v:3499.50-3499.119"
87798   cell $and $and$ls180.v:3499$145
87799     parameter \A_SIGNED 0
87800     parameter \A_WIDTH 1
87801     parameter \B_SIGNED 0
87802     parameter \B_WIDTH 1
87803     parameter \Y_WIDTH 1
87804     connect \A \main_sdram_bankmachine2_cmd_valid
87805     connect \B \main_sdram_bankmachine2_cmd_ready
87806     connect \Y $and$ls180.v:3499$145_Y
87807   end
87808   attribute \src "ls180.v:3499.49-3499.167"
87809   cell $and $and$ls180.v:3499$146
87810     parameter \A_SIGNED 0
87811     parameter \A_WIDTH 1
87812     parameter \B_SIGNED 0
87813     parameter \B_WIDTH 1
87814     parameter \Y_WIDTH 1
87815     connect \A $and$ls180.v:3499$145_Y
87816     connect \B \main_sdram_bankmachine2_cmd_payload_is_write
87817     connect \Y $and$ls180.v:3499$146_Y
87818   end
87819   attribute \src "ls180.v:3500.49-3500.118"
87820   cell $and $and$ls180.v:3500$147
87821     parameter \A_SIGNED 0
87822     parameter \A_WIDTH 1
87823     parameter \B_SIGNED 0
87824     parameter \B_WIDTH 1
87825     parameter \Y_WIDTH 1
87826     connect \A \main_sdram_bankmachine2_cmd_valid
87827     connect \B \main_sdram_bankmachine2_cmd_ready
87828     connect \Y $and$ls180.v:3500$147_Y
87829   end
87830   attribute \src "ls180.v:3500.48-3500.154"
87831   cell $and $and$ls180.v:3500$148
87832     parameter \A_SIGNED 0
87833     parameter \A_WIDTH 1
87834     parameter \B_SIGNED 0
87835     parameter \B_WIDTH 1
87836     parameter \Y_WIDTH 1
87837     connect \A $and$ls180.v:3500$147_Y
87838     connect \B \main_sdram_bankmachine2_row_open
87839     connect \Y $and$ls180.v:3500$148_Y
87840   end
87841   attribute \src "ls180.v:3501.50-3501.119"
87842   cell $and $and$ls180.v:3501$149
87843     parameter \A_SIGNED 0
87844     parameter \A_WIDTH 1
87845     parameter \B_SIGNED 0
87846     parameter \B_WIDTH 1
87847     parameter \Y_WIDTH 1
87848     connect \A \main_sdram_bankmachine2_cmd_valid
87849     connect \B \main_sdram_bankmachine2_cmd_ready
87850     connect \Y $and$ls180.v:3501$149_Y
87851   end
87852   attribute \src "ls180.v:3501.49-3501.155"
87853   cell $and $and$ls180.v:3501$150
87854     parameter \A_SIGNED 0
87855     parameter \A_WIDTH 1
87856     parameter \B_SIGNED 0
87857     parameter \B_WIDTH 1
87858     parameter \Y_WIDTH 1
87859     connect \A $and$ls180.v:3501$149_Y
87860     connect \B \main_sdram_bankmachine2_row_open
87861     connect \Y $and$ls180.v:3501$150_Y
87862   end
87863   attribute \src "ls180.v:3504.7-3504.114"
87864   cell $and $and$ls180.v:3504$152
87865     parameter \A_SIGNED 0
87866     parameter \A_WIDTH 1
87867     parameter \B_SIGNED 0
87868     parameter \B_WIDTH 1
87869     parameter \Y_WIDTH 1
87870     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
87871     connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
87872     connect \Y $and$ls180.v:3504$152_Y
87873   end
87874   attribute \src "ls180.v:3533.66-3533.246"
87875   cell $and $and$ls180.v:3533$158
87876     parameter \A_SIGNED 0
87877     parameter \A_WIDTH 1
87878     parameter \B_SIGNED 0
87879     parameter \B_WIDTH 1
87880     parameter \Y_WIDTH 1
87881     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
87882     connect \B $or$ls180.v:3533$157_Y
87883     connect \Y $and$ls180.v:3533$158_Y
87884   end
87885   attribute \src "ls180.v:3534.64-3534.187"
87886   cell $and $and$ls180.v:3534$159
87887     parameter \A_SIGNED 0
87888     parameter \A_WIDTH 1
87889     parameter \B_SIGNED 0
87890     parameter \B_WIDTH 1
87891     parameter \Y_WIDTH 1
87892     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
87893     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
87894     connect \Y $and$ls180.v:3534$159_Y
87895   end
87896   attribute \src "ls180.v:3558.9-3558.86"
87897   cell $and $and$ls180.v:3558$165
87898     parameter \A_SIGNED 0
87899     parameter \A_WIDTH 1
87900     parameter \B_SIGNED 0
87901     parameter \B_WIDTH 1
87902     parameter \Y_WIDTH 1
87903     connect \A \main_sdram_bankmachine2_twtpcon_ready
87904     connect \B \main_sdram_bankmachine2_trascon_ready
87905     connect \Y $and$ls180.v:3558$165_Y
87906   end
87907   attribute \src "ls180.v:3570.9-3570.86"
87908   cell $and $and$ls180.v:3570$166
87909     parameter \A_SIGNED 0
87910     parameter \A_WIDTH 1
87911     parameter \B_SIGNED 0
87912     parameter \B_WIDTH 1
87913     parameter \Y_WIDTH 1
87914     connect \A \main_sdram_bankmachine2_twtpcon_ready
87915     connect \B \main_sdram_bankmachine2_trascon_ready
87916     connect \Y $and$ls180.v:3570$166_Y
87917   end
87918   attribute \src "ls180.v:3620.13-3620.87"
87919   cell $and $and$ls180.v:3620$168
87920     parameter \A_SIGNED 0
87921     parameter \A_WIDTH 1
87922     parameter \B_SIGNED 0
87923     parameter \B_WIDTH 1
87924     parameter \Y_WIDTH 1
87925     connect \A \main_sdram_bankmachine2_cmd_ready
87926     connect \B \main_sdram_bankmachine2_auto_precharge
87927     connect \Y $and$ls180.v:3620$168_Y
87928   end
87929   attribute \src "ls180.v:3656.50-3656.119"
87930   cell $and $and$ls180.v:3656$175
87931     parameter \A_SIGNED 0
87932     parameter \A_WIDTH 1
87933     parameter \B_SIGNED 0
87934     parameter \B_WIDTH 1
87935     parameter \Y_WIDTH 1
87936     connect \A \main_sdram_bankmachine3_cmd_valid
87937     connect \B \main_sdram_bankmachine3_cmd_ready
87938     connect \Y $and$ls180.v:3656$175_Y
87939   end
87940   attribute \src "ls180.v:3656.49-3656.167"
87941   cell $and $and$ls180.v:3656$176
87942     parameter \A_SIGNED 0
87943     parameter \A_WIDTH 1
87944     parameter \B_SIGNED 0
87945     parameter \B_WIDTH 1
87946     parameter \Y_WIDTH 1
87947     connect \A $and$ls180.v:3656$175_Y
87948     connect \B \main_sdram_bankmachine3_cmd_payload_is_write
87949     connect \Y $and$ls180.v:3656$176_Y
87950   end
87951   attribute \src "ls180.v:3657.49-3657.118"
87952   cell $and $and$ls180.v:3657$177
87953     parameter \A_SIGNED 0
87954     parameter \A_WIDTH 1
87955     parameter \B_SIGNED 0
87956     parameter \B_WIDTH 1
87957     parameter \Y_WIDTH 1
87958     connect \A \main_sdram_bankmachine3_cmd_valid
87959     connect \B \main_sdram_bankmachine3_cmd_ready
87960     connect \Y $and$ls180.v:3657$177_Y
87961   end
87962   attribute \src "ls180.v:3657.48-3657.154"
87963   cell $and $and$ls180.v:3657$178
87964     parameter \A_SIGNED 0
87965     parameter \A_WIDTH 1
87966     parameter \B_SIGNED 0
87967     parameter \B_WIDTH 1
87968     parameter \Y_WIDTH 1
87969     connect \A $and$ls180.v:3657$177_Y
87970     connect \B \main_sdram_bankmachine3_row_open
87971     connect \Y $and$ls180.v:3657$178_Y
87972   end
87973   attribute \src "ls180.v:3658.50-3658.119"
87974   cell $and $and$ls180.v:3658$179
87975     parameter \A_SIGNED 0
87976     parameter \A_WIDTH 1
87977     parameter \B_SIGNED 0
87978     parameter \B_WIDTH 1
87979     parameter \Y_WIDTH 1
87980     connect \A \main_sdram_bankmachine3_cmd_valid
87981     connect \B \main_sdram_bankmachine3_cmd_ready
87982     connect \Y $and$ls180.v:3658$179_Y
87983   end
87984   attribute \src "ls180.v:3658.49-3658.155"
87985   cell $and $and$ls180.v:3658$180
87986     parameter \A_SIGNED 0
87987     parameter \A_WIDTH 1
87988     parameter \B_SIGNED 0
87989     parameter \B_WIDTH 1
87990     parameter \Y_WIDTH 1
87991     connect \A $and$ls180.v:3658$179_Y
87992     connect \B \main_sdram_bankmachine3_row_open
87993     connect \Y $and$ls180.v:3658$180_Y
87994   end
87995   attribute \src "ls180.v:3661.7-3661.114"
87996   cell $and $and$ls180.v:3661$182
87997     parameter \A_SIGNED 0
87998     parameter \A_WIDTH 1
87999     parameter \B_SIGNED 0
88000     parameter \B_WIDTH 1
88001     parameter \Y_WIDTH 1
88002     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
88003     connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
88004     connect \Y $and$ls180.v:3661$182_Y
88005   end
88006   attribute \src "ls180.v:3690.66-3690.246"
88007   cell $and $and$ls180.v:3690$188
88008     parameter \A_SIGNED 0
88009     parameter \A_WIDTH 1
88010     parameter \B_SIGNED 0
88011     parameter \B_WIDTH 1
88012     parameter \Y_WIDTH 1
88013     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
88014     connect \B $or$ls180.v:3690$187_Y
88015     connect \Y $and$ls180.v:3690$188_Y
88016   end
88017   attribute \src "ls180.v:3691.64-3691.187"
88018   cell $and $and$ls180.v:3691$189
88019     parameter \A_SIGNED 0
88020     parameter \A_WIDTH 1
88021     parameter \B_SIGNED 0
88022     parameter \B_WIDTH 1
88023     parameter \Y_WIDTH 1
88024     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
88025     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
88026     connect \Y $and$ls180.v:3691$189_Y
88027   end
88028   attribute \src "ls180.v:3715.9-3715.86"
88029   cell $and $and$ls180.v:3715$195
88030     parameter \A_SIGNED 0
88031     parameter \A_WIDTH 1
88032     parameter \B_SIGNED 0
88033     parameter \B_WIDTH 1
88034     parameter \Y_WIDTH 1
88035     connect \A \main_sdram_bankmachine3_twtpcon_ready
88036     connect \B \main_sdram_bankmachine3_trascon_ready
88037     connect \Y $and$ls180.v:3715$195_Y
88038   end
88039   attribute \src "ls180.v:3727.9-3727.86"
88040   cell $and $and$ls180.v:3727$196
88041     parameter \A_SIGNED 0
88042     parameter \A_WIDTH 1
88043     parameter \B_SIGNED 0
88044     parameter \B_WIDTH 1
88045     parameter \Y_WIDTH 1
88046     connect \A \main_sdram_bankmachine3_twtpcon_ready
88047     connect \B \main_sdram_bankmachine3_trascon_ready
88048     connect \Y $and$ls180.v:3727$196_Y
88049   end
88050   attribute \src "ls180.v:3777.13-3777.87"
88051   cell $and $and$ls180.v:3777$198
88052     parameter \A_SIGNED 0
88053     parameter \A_WIDTH 1
88054     parameter \B_SIGNED 0
88055     parameter \B_WIDTH 1
88056     parameter \Y_WIDTH 1
88057     connect \A \main_sdram_bankmachine3_cmd_ready
88058     connect \B \main_sdram_bankmachine3_auto_precharge
88059     connect \Y $and$ls180.v:3777$198_Y
88060   end
88061   attribute \src "ls180.v:3792.37-3792.102"
88062   cell $and $and$ls180.v:3792$199
88063     parameter \A_SIGNED 0
88064     parameter \A_WIDTH 1
88065     parameter \B_SIGNED 0
88066     parameter \B_WIDTH 1
88067     parameter \Y_WIDTH 1
88068     connect \A \main_sdram_choose_req_cmd_valid
88069     connect \B \main_sdram_choose_req_cmd_ready
88070     connect \Y $and$ls180.v:3792$199_Y
88071   end
88072   attribute \src "ls180.v:3792.108-3792.188"
88073   cell $and $and$ls180.v:3792$201
88074     parameter \A_SIGNED 0
88075     parameter \A_WIDTH 1
88076     parameter \B_SIGNED 0
88077     parameter \B_WIDTH 1
88078     parameter \Y_WIDTH 1
88079     connect \A \main_sdram_choose_req_cmd_payload_ras
88080     connect \B $not$ls180.v:3792$200_Y
88081     connect \Y $and$ls180.v:3792$201_Y
88082   end
88083   attribute \src "ls180.v:3792.107-3792.231"
88084   cell $and $and$ls180.v:3792$203
88085     parameter \A_SIGNED 0
88086     parameter \A_WIDTH 1
88087     parameter \B_SIGNED 0
88088     parameter \B_WIDTH 1
88089     parameter \Y_WIDTH 1
88090     connect \A $and$ls180.v:3792$201_Y
88091     connect \B $not$ls180.v:3792$202_Y
88092     connect \Y $and$ls180.v:3792$203_Y
88093   end
88094   attribute \src "ls180.v:3792.36-3792.232"
88095   cell $and $and$ls180.v:3792$204
88096     parameter \A_SIGNED 0
88097     parameter \A_WIDTH 1
88098     parameter \B_SIGNED 0
88099     parameter \B_WIDTH 1
88100     parameter \Y_WIDTH 1
88101     connect \A $and$ls180.v:3792$199_Y
88102     connect \B $and$ls180.v:3792$203_Y
88103     connect \Y $and$ls180.v:3792$204_Y
88104   end
88105   attribute \src "ls180.v:3793.37-3793.102"
88106   cell $and $and$ls180.v:3793$205
88107     parameter \A_SIGNED 0
88108     parameter \A_WIDTH 1
88109     parameter \B_SIGNED 0
88110     parameter \B_WIDTH 1
88111     parameter \Y_WIDTH 1
88112     connect \A \main_sdram_choose_req_cmd_valid
88113     connect \B \main_sdram_choose_req_cmd_ready
88114     connect \Y $and$ls180.v:3793$205_Y
88115   end
88116   attribute \src "ls180.v:3793.108-3793.188"
88117   cell $and $and$ls180.v:3793$207
88118     parameter \A_SIGNED 0
88119     parameter \A_WIDTH 1
88120     parameter \B_SIGNED 0
88121     parameter \B_WIDTH 1
88122     parameter \Y_WIDTH 1
88123     connect \A \main_sdram_choose_req_cmd_payload_ras
88124     connect \B $not$ls180.v:3793$206_Y
88125     connect \Y $and$ls180.v:3793$207_Y
88126   end
88127   attribute \src "ls180.v:3793.107-3793.231"
88128   cell $and $and$ls180.v:3793$209
88129     parameter \A_SIGNED 0
88130     parameter \A_WIDTH 1
88131     parameter \B_SIGNED 0
88132     parameter \B_WIDTH 1
88133     parameter \Y_WIDTH 1
88134     connect \A $and$ls180.v:3793$207_Y
88135     connect \B $not$ls180.v:3793$208_Y
88136     connect \Y $and$ls180.v:3793$209_Y
88137   end
88138   attribute \src "ls180.v:3793.36-3793.232"
88139   cell $and $and$ls180.v:3793$210
88140     parameter \A_SIGNED 0
88141     parameter \A_WIDTH 1
88142     parameter \B_SIGNED 0
88143     parameter \B_WIDTH 1
88144     parameter \Y_WIDTH 1
88145     connect \A $and$ls180.v:3793$205_Y
88146     connect \B $and$ls180.v:3793$209_Y
88147     connect \Y $and$ls180.v:3793$210_Y
88148   end
88149   attribute \src "ls180.v:3794.34-3794.85"
88150   cell $and $and$ls180.v:3794$211
88151     parameter \A_SIGNED 0
88152     parameter \A_WIDTH 1
88153     parameter \B_SIGNED 0
88154     parameter \B_WIDTH 1
88155     parameter \Y_WIDTH 1
88156     connect \A \main_sdram_trrdcon_ready
88157     connect \B \main_sdram_tfawcon_ready
88158     connect \Y $and$ls180.v:3794$211_Y
88159   end
88160   attribute \src "ls180.v:3795.37-3795.102"
88161   cell $and $and$ls180.v:3795$212
88162     parameter \A_SIGNED 0
88163     parameter \A_WIDTH 1
88164     parameter \B_SIGNED 0
88165     parameter \B_WIDTH 1
88166     parameter \Y_WIDTH 1
88167     connect \A \main_sdram_choose_req_cmd_valid
88168     connect \B \main_sdram_choose_req_cmd_ready
88169     connect \Y $and$ls180.v:3795$212_Y
88170   end
88171   attribute \src "ls180.v:3795.36-3795.194"
88172   cell $and $and$ls180.v:3795$214
88173     parameter \A_SIGNED 0
88174     parameter \A_WIDTH 1
88175     parameter \B_SIGNED 0
88176     parameter \B_WIDTH 1
88177     parameter \Y_WIDTH 1
88178     connect \A $and$ls180.v:3795$212_Y
88179     connect \B $or$ls180.v:3795$213_Y
88180     connect \Y $and$ls180.v:3795$214_Y
88181   end
88182   attribute \src "ls180.v:3797.37-3797.102"
88183   cell $and $and$ls180.v:3797$215
88184     parameter \A_SIGNED 0
88185     parameter \A_WIDTH 1
88186     parameter \B_SIGNED 0
88187     parameter \B_WIDTH 1
88188     parameter \Y_WIDTH 1
88189     connect \A \main_sdram_choose_req_cmd_valid
88190     connect \B \main_sdram_choose_req_cmd_ready
88191     connect \Y $and$ls180.v:3797$215_Y
88192   end
88193   attribute \src "ls180.v:3797.36-3797.148"
88194   cell $and $and$ls180.v:3797$216
88195     parameter \A_SIGNED 0
88196     parameter \A_WIDTH 1
88197     parameter \B_SIGNED 0
88198     parameter \B_WIDTH 1
88199     parameter \Y_WIDTH 1
88200     connect \A $and$ls180.v:3797$215_Y
88201     connect \B \main_sdram_choose_req_cmd_payload_is_write
88202     connect \Y $and$ls180.v:3797$216_Y
88203   end
88204   attribute \src "ls180.v:3798.40-3798.119"
88205   cell $and $and$ls180.v:3798$217
88206     parameter \A_SIGNED 0
88207     parameter \A_WIDTH 1
88208     parameter \B_SIGNED 0
88209     parameter \B_WIDTH 1
88210     parameter \Y_WIDTH 1
88211     connect \A \main_sdram_bankmachine0_cmd_valid
88212     connect \B \main_sdram_bankmachine0_cmd_payload_is_read
88213     connect \Y $and$ls180.v:3798$217_Y
88214   end
88215   attribute \src "ls180.v:3798.124-3798.203"
88216   cell $and $and$ls180.v:3798$218
88217     parameter \A_SIGNED 0
88218     parameter \A_WIDTH 1
88219     parameter \B_SIGNED 0
88220     parameter \B_WIDTH 1
88221     parameter \Y_WIDTH 1
88222     connect \A \main_sdram_bankmachine1_cmd_valid
88223     connect \B \main_sdram_bankmachine1_cmd_payload_is_read
88224     connect \Y $and$ls180.v:3798$218_Y
88225   end
88226   attribute \src "ls180.v:3798.209-3798.288"
88227   cell $and $and$ls180.v:3798$220
88228     parameter \A_SIGNED 0
88229     parameter \A_WIDTH 1
88230     parameter \B_SIGNED 0
88231     parameter \B_WIDTH 1
88232     parameter \Y_WIDTH 1
88233     connect \A \main_sdram_bankmachine2_cmd_valid
88234     connect \B \main_sdram_bankmachine2_cmd_payload_is_read
88235     connect \Y $and$ls180.v:3798$220_Y
88236   end
88237   attribute \src "ls180.v:3798.294-3798.373"
88238   cell $and $and$ls180.v:3798$222
88239     parameter \A_SIGNED 0
88240     parameter \A_WIDTH 1
88241     parameter \B_SIGNED 0
88242     parameter \B_WIDTH 1
88243     parameter \Y_WIDTH 1
88244     connect \A \main_sdram_bankmachine3_cmd_valid
88245     connect \B \main_sdram_bankmachine3_cmd_payload_is_read
88246     connect \Y $and$ls180.v:3798$222_Y
88247   end
88248   attribute \src "ls180.v:3799.41-3799.121"
88249   cell $and $and$ls180.v:3799$224
88250     parameter \A_SIGNED 0
88251     parameter \A_WIDTH 1
88252     parameter \B_SIGNED 0
88253     parameter \B_WIDTH 1
88254     parameter \Y_WIDTH 1
88255     connect \A \main_sdram_bankmachine0_cmd_valid
88256     connect \B \main_sdram_bankmachine0_cmd_payload_is_write
88257     connect \Y $and$ls180.v:3799$224_Y
88258   end
88259   attribute \src "ls180.v:3799.126-3799.206"
88260   cell $and $and$ls180.v:3799$225
88261     parameter \A_SIGNED 0
88262     parameter \A_WIDTH 1
88263     parameter \B_SIGNED 0
88264     parameter \B_WIDTH 1
88265     parameter \Y_WIDTH 1
88266     connect \A \main_sdram_bankmachine1_cmd_valid
88267     connect \B \main_sdram_bankmachine1_cmd_payload_is_write
88268     connect \Y $and$ls180.v:3799$225_Y
88269   end
88270   attribute \src "ls180.v:3799.212-3799.292"
88271   cell $and $and$ls180.v:3799$227
88272     parameter \A_SIGNED 0
88273     parameter \A_WIDTH 1
88274     parameter \B_SIGNED 0
88275     parameter \B_WIDTH 1
88276     parameter \Y_WIDTH 1
88277     connect \A \main_sdram_bankmachine2_cmd_valid
88278     connect \B \main_sdram_bankmachine2_cmd_payload_is_write
88279     connect \Y $and$ls180.v:3799$227_Y
88280   end
88281   attribute \src "ls180.v:3799.298-3799.378"
88282   cell $and $and$ls180.v:3799$229
88283     parameter \A_SIGNED 0
88284     parameter \A_WIDTH 1
88285     parameter \B_SIGNED 0
88286     parameter \B_WIDTH 1
88287     parameter \Y_WIDTH 1
88288     connect \A \main_sdram_bankmachine3_cmd_valid
88289     connect \B \main_sdram_bankmachine3_cmd_payload_is_write
88290     connect \Y $and$ls180.v:3799$229_Y
88291   end
88292   attribute \src "ls180.v:3806.38-3806.111"
88293   cell $and $and$ls180.v:3806$233
88294     parameter \A_SIGNED 0
88295     parameter \A_WIDTH 1
88296     parameter \B_SIGNED 0
88297     parameter \B_WIDTH 1
88298     parameter \Y_WIDTH 1
88299     connect \A \main_sdram_bankmachine0_refresh_gnt
88300     connect \B \main_sdram_bankmachine1_refresh_gnt
88301     connect \Y $and$ls180.v:3806$233_Y
88302   end
88303   attribute \src "ls180.v:3806.37-3806.150"
88304   cell $and $and$ls180.v:3806$234
88305     parameter \A_SIGNED 0
88306     parameter \A_WIDTH 1
88307     parameter \B_SIGNED 0
88308     parameter \B_WIDTH 1
88309     parameter \Y_WIDTH 1
88310     connect \A $and$ls180.v:3806$233_Y
88311     connect \B \main_sdram_bankmachine2_refresh_gnt
88312     connect \Y $and$ls180.v:3806$234_Y
88313   end
88314   attribute \src "ls180.v:3806.36-3806.189"
88315   cell $and $and$ls180.v:3806$235
88316     parameter \A_SIGNED 0
88317     parameter \A_WIDTH 1
88318     parameter \B_SIGNED 0
88319     parameter \B_WIDTH 1
88320     parameter \Y_WIDTH 1
88321     connect \A $and$ls180.v:3806$234_Y
88322     connect \B \main_sdram_bankmachine3_refresh_gnt
88323     connect \Y $and$ls180.v:3806$235_Y
88324   end
88325   attribute \src "ls180.v:3812.77-3812.153"
88326   cell $and $and$ls180.v:3812$238
88327     parameter \A_SIGNED 0
88328     parameter \A_WIDTH 1
88329     parameter \B_SIGNED 0
88330     parameter \B_WIDTH 1
88331     parameter \Y_WIDTH 1
88332     connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
88333     connect \B \main_sdram_choose_cmd_want_cmds
88334     connect \Y $and$ls180.v:3812$238_Y
88335   end
88336   attribute \src "ls180.v:3812.162-3812.246"
88337   cell $and $and$ls180.v:3812$240
88338     parameter \A_SIGNED 0
88339     parameter \A_WIDTH 1
88340     parameter \B_SIGNED 0
88341     parameter \B_WIDTH 1
88342     parameter \Y_WIDTH 1
88343     connect \A \main_sdram_bankmachine0_cmd_payload_ras
88344     connect \B $not$ls180.v:3812$239_Y
88345     connect \Y $and$ls180.v:3812$240_Y
88346   end
88347   attribute \src "ls180.v:3812.161-3812.291"
88348   cell $and $and$ls180.v:3812$242
88349     parameter \A_SIGNED 0
88350     parameter \A_WIDTH 1
88351     parameter \B_SIGNED 0
88352     parameter \B_WIDTH 1
88353     parameter \Y_WIDTH 1
88354     connect \A $and$ls180.v:3812$240_Y
88355     connect \B $not$ls180.v:3812$241_Y
88356     connect \Y $and$ls180.v:3812$242_Y
88357   end
88358   attribute \src "ls180.v:3812.76-3812.333"
88359   cell $and $and$ls180.v:3812$245
88360     parameter \A_SIGNED 0
88361     parameter \A_WIDTH 1
88362     parameter \B_SIGNED 0
88363     parameter \B_WIDTH 1
88364     parameter \Y_WIDTH 1
88365     connect \A $and$ls180.v:3812$238_Y
88366     connect \B $or$ls180.v:3812$244_Y
88367     connect \Y $and$ls180.v:3812$245_Y
88368   end
88369   attribute \src "ls180.v:3812.338-3812.505"
88370   cell $and $and$ls180.v:3812$248
88371     parameter \A_SIGNED 0
88372     parameter \A_WIDTH 1
88373     parameter \B_SIGNED 0
88374     parameter \B_WIDTH 1
88375     parameter \Y_WIDTH 1
88376     connect \A $eq$ls180.v:3812$246_Y
88377     connect \B $eq$ls180.v:3812$247_Y
88378     connect \Y $and$ls180.v:3812$248_Y
88379   end
88380   attribute \src "ls180.v:3812.38-3812.507"
88381   cell $and $and$ls180.v:3812$250
88382     parameter \A_SIGNED 0
88383     parameter \A_WIDTH 1
88384     parameter \B_SIGNED 0
88385     parameter \B_WIDTH 1
88386     parameter \Y_WIDTH 1
88387     connect \A \main_sdram_bankmachine0_cmd_valid
88388     connect \B $or$ls180.v:3812$249_Y
88389     connect \Y $and$ls180.v:3812$250_Y
88390   end
88391   attribute \src "ls180.v:3813.77-3813.153"
88392   cell $and $and$ls180.v:3813$251
88393     parameter \A_SIGNED 0
88394     parameter \A_WIDTH 1
88395     parameter \B_SIGNED 0
88396     parameter \B_WIDTH 1
88397     parameter \Y_WIDTH 1
88398     connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
88399     connect \B \main_sdram_choose_cmd_want_cmds
88400     connect \Y $and$ls180.v:3813$251_Y
88401   end
88402   attribute \src "ls180.v:3813.162-3813.246"
88403   cell $and $and$ls180.v:3813$253
88404     parameter \A_SIGNED 0
88405     parameter \A_WIDTH 1
88406     parameter \B_SIGNED 0
88407     parameter \B_WIDTH 1
88408     parameter \Y_WIDTH 1
88409     connect \A \main_sdram_bankmachine1_cmd_payload_ras
88410     connect \B $not$ls180.v:3813$252_Y
88411     connect \Y $and$ls180.v:3813$253_Y
88412   end
88413   attribute \src "ls180.v:3813.161-3813.291"
88414   cell $and $and$ls180.v:3813$255
88415     parameter \A_SIGNED 0
88416     parameter \A_WIDTH 1
88417     parameter \B_SIGNED 0
88418     parameter \B_WIDTH 1
88419     parameter \Y_WIDTH 1
88420     connect \A $and$ls180.v:3813$253_Y
88421     connect \B $not$ls180.v:3813$254_Y
88422     connect \Y $and$ls180.v:3813$255_Y
88423   end
88424   attribute \src "ls180.v:3813.76-3813.333"
88425   cell $and $and$ls180.v:3813$258
88426     parameter \A_SIGNED 0
88427     parameter \A_WIDTH 1
88428     parameter \B_SIGNED 0
88429     parameter \B_WIDTH 1
88430     parameter \Y_WIDTH 1
88431     connect \A $and$ls180.v:3813$251_Y
88432     connect \B $or$ls180.v:3813$257_Y
88433     connect \Y $and$ls180.v:3813$258_Y
88434   end
88435   attribute \src "ls180.v:3813.338-3813.505"
88436   cell $and $and$ls180.v:3813$261
88437     parameter \A_SIGNED 0
88438     parameter \A_WIDTH 1
88439     parameter \B_SIGNED 0
88440     parameter \B_WIDTH 1
88441     parameter \Y_WIDTH 1
88442     connect \A $eq$ls180.v:3813$259_Y
88443     connect \B $eq$ls180.v:3813$260_Y
88444     connect \Y $and$ls180.v:3813$261_Y
88445   end
88446   attribute \src "ls180.v:3813.38-3813.507"
88447   cell $and $and$ls180.v:3813$263
88448     parameter \A_SIGNED 0
88449     parameter \A_WIDTH 1
88450     parameter \B_SIGNED 0
88451     parameter \B_WIDTH 1
88452     parameter \Y_WIDTH 1
88453     connect \A \main_sdram_bankmachine1_cmd_valid
88454     connect \B $or$ls180.v:3813$262_Y
88455     connect \Y $and$ls180.v:3813$263_Y
88456   end
88457   attribute \src "ls180.v:3814.77-3814.153"
88458   cell $and $and$ls180.v:3814$264
88459     parameter \A_SIGNED 0
88460     parameter \A_WIDTH 1
88461     parameter \B_SIGNED 0
88462     parameter \B_WIDTH 1
88463     parameter \Y_WIDTH 1
88464     connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
88465     connect \B \main_sdram_choose_cmd_want_cmds
88466     connect \Y $and$ls180.v:3814$264_Y
88467   end
88468   attribute \src "ls180.v:3814.162-3814.246"
88469   cell $and $and$ls180.v:3814$266
88470     parameter \A_SIGNED 0
88471     parameter \A_WIDTH 1
88472     parameter \B_SIGNED 0
88473     parameter \B_WIDTH 1
88474     parameter \Y_WIDTH 1
88475     connect \A \main_sdram_bankmachine2_cmd_payload_ras
88476     connect \B $not$ls180.v:3814$265_Y
88477     connect \Y $and$ls180.v:3814$266_Y
88478   end
88479   attribute \src "ls180.v:3814.161-3814.291"
88480   cell $and $and$ls180.v:3814$268
88481     parameter \A_SIGNED 0
88482     parameter \A_WIDTH 1
88483     parameter \B_SIGNED 0
88484     parameter \B_WIDTH 1
88485     parameter \Y_WIDTH 1
88486     connect \A $and$ls180.v:3814$266_Y
88487     connect \B $not$ls180.v:3814$267_Y
88488     connect \Y $and$ls180.v:3814$268_Y
88489   end
88490   attribute \src "ls180.v:3814.76-3814.333"
88491   cell $and $and$ls180.v:3814$271
88492     parameter \A_SIGNED 0
88493     parameter \A_WIDTH 1
88494     parameter \B_SIGNED 0
88495     parameter \B_WIDTH 1
88496     parameter \Y_WIDTH 1
88497     connect \A $and$ls180.v:3814$264_Y
88498     connect \B $or$ls180.v:3814$270_Y
88499     connect \Y $and$ls180.v:3814$271_Y
88500   end
88501   attribute \src "ls180.v:3814.338-3814.505"
88502   cell $and $and$ls180.v:3814$274
88503     parameter \A_SIGNED 0
88504     parameter \A_WIDTH 1
88505     parameter \B_SIGNED 0
88506     parameter \B_WIDTH 1
88507     parameter \Y_WIDTH 1
88508     connect \A $eq$ls180.v:3814$272_Y
88509     connect \B $eq$ls180.v:3814$273_Y
88510     connect \Y $and$ls180.v:3814$274_Y
88511   end
88512   attribute \src "ls180.v:3814.38-3814.507"
88513   cell $and $and$ls180.v:3814$276
88514     parameter \A_SIGNED 0
88515     parameter \A_WIDTH 1
88516     parameter \B_SIGNED 0
88517     parameter \B_WIDTH 1
88518     parameter \Y_WIDTH 1
88519     connect \A \main_sdram_bankmachine2_cmd_valid
88520     connect \B $or$ls180.v:3814$275_Y
88521     connect \Y $and$ls180.v:3814$276_Y
88522   end
88523   attribute \src "ls180.v:3815.77-3815.153"
88524   cell $and $and$ls180.v:3815$277
88525     parameter \A_SIGNED 0
88526     parameter \A_WIDTH 1
88527     parameter \B_SIGNED 0
88528     parameter \B_WIDTH 1
88529     parameter \Y_WIDTH 1
88530     connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
88531     connect \B \main_sdram_choose_cmd_want_cmds
88532     connect \Y $and$ls180.v:3815$277_Y
88533   end
88534   attribute \src "ls180.v:3815.162-3815.246"
88535   cell $and $and$ls180.v:3815$279
88536     parameter \A_SIGNED 0
88537     parameter \A_WIDTH 1
88538     parameter \B_SIGNED 0
88539     parameter \B_WIDTH 1
88540     parameter \Y_WIDTH 1
88541     connect \A \main_sdram_bankmachine3_cmd_payload_ras
88542     connect \B $not$ls180.v:3815$278_Y
88543     connect \Y $and$ls180.v:3815$279_Y
88544   end
88545   attribute \src "ls180.v:3815.161-3815.291"
88546   cell $and $and$ls180.v:3815$281
88547     parameter \A_SIGNED 0
88548     parameter \A_WIDTH 1
88549     parameter \B_SIGNED 0
88550     parameter \B_WIDTH 1
88551     parameter \Y_WIDTH 1
88552     connect \A $and$ls180.v:3815$279_Y
88553     connect \B $not$ls180.v:3815$280_Y
88554     connect \Y $and$ls180.v:3815$281_Y
88555   end
88556   attribute \src "ls180.v:3815.76-3815.333"
88557   cell $and $and$ls180.v:3815$284
88558     parameter \A_SIGNED 0
88559     parameter \A_WIDTH 1
88560     parameter \B_SIGNED 0
88561     parameter \B_WIDTH 1
88562     parameter \Y_WIDTH 1
88563     connect \A $and$ls180.v:3815$277_Y
88564     connect \B $or$ls180.v:3815$283_Y
88565     connect \Y $and$ls180.v:3815$284_Y
88566   end
88567   attribute \src "ls180.v:3815.338-3815.505"
88568   cell $and $and$ls180.v:3815$287
88569     parameter \A_SIGNED 0
88570     parameter \A_WIDTH 1
88571     parameter \B_SIGNED 0
88572     parameter \B_WIDTH 1
88573     parameter \Y_WIDTH 1
88574     connect \A $eq$ls180.v:3815$285_Y
88575     connect \B $eq$ls180.v:3815$286_Y
88576     connect \Y $and$ls180.v:3815$287_Y
88577   end
88578   attribute \src "ls180.v:3815.38-3815.507"
88579   cell $and $and$ls180.v:3815$289
88580     parameter \A_SIGNED 0
88581     parameter \A_WIDTH 1
88582     parameter \B_SIGNED 0
88583     parameter \B_WIDTH 1
88584     parameter \Y_WIDTH 1
88585     connect \A \main_sdram_bankmachine3_cmd_valid
88586     connect \B $or$ls180.v:3815$288_Y
88587     connect \Y $and$ls180.v:3815$289_Y
88588   end
88589   attribute \src "ls180.v:3845.77-3845.153"
88590   cell $and $and$ls180.v:3845$296
88591     parameter \A_SIGNED 0
88592     parameter \A_WIDTH 1
88593     parameter \B_SIGNED 0
88594     parameter \B_WIDTH 1
88595     parameter \Y_WIDTH 1
88596     connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd
88597     connect \B \main_sdram_choose_req_want_cmds
88598     connect \Y $and$ls180.v:3845$296_Y
88599   end
88600   attribute \src "ls180.v:3845.162-3845.246"
88601   cell $and $and$ls180.v:3845$298
88602     parameter \A_SIGNED 0
88603     parameter \A_WIDTH 1
88604     parameter \B_SIGNED 0
88605     parameter \B_WIDTH 1
88606     parameter \Y_WIDTH 1
88607     connect \A \main_sdram_bankmachine0_cmd_payload_ras
88608     connect \B $not$ls180.v:3845$297_Y
88609     connect \Y $and$ls180.v:3845$298_Y
88610   end
88611   attribute \src "ls180.v:3845.161-3845.291"
88612   cell $and $and$ls180.v:3845$300
88613     parameter \A_SIGNED 0
88614     parameter \A_WIDTH 1
88615     parameter \B_SIGNED 0
88616     parameter \B_WIDTH 1
88617     parameter \Y_WIDTH 1
88618     connect \A $and$ls180.v:3845$298_Y
88619     connect \B $not$ls180.v:3845$299_Y
88620     connect \Y $and$ls180.v:3845$300_Y
88621   end
88622   attribute \src "ls180.v:3845.76-3845.333"
88623   cell $and $and$ls180.v:3845$303
88624     parameter \A_SIGNED 0
88625     parameter \A_WIDTH 1
88626     parameter \B_SIGNED 0
88627     parameter \B_WIDTH 1
88628     parameter \Y_WIDTH 1
88629     connect \A $and$ls180.v:3845$296_Y
88630     connect \B $or$ls180.v:3845$302_Y
88631     connect \Y $and$ls180.v:3845$303_Y
88632   end
88633   attribute \src "ls180.v:3845.338-3845.505"
88634   cell $and $and$ls180.v:3845$306
88635     parameter \A_SIGNED 0
88636     parameter \A_WIDTH 1
88637     parameter \B_SIGNED 0
88638     parameter \B_WIDTH 1
88639     parameter \Y_WIDTH 1
88640     connect \A $eq$ls180.v:3845$304_Y
88641     connect \B $eq$ls180.v:3845$305_Y
88642     connect \Y $and$ls180.v:3845$306_Y
88643   end
88644   attribute \src "ls180.v:3845.38-3845.507"
88645   cell $and $and$ls180.v:3845$308
88646     parameter \A_SIGNED 0
88647     parameter \A_WIDTH 1
88648     parameter \B_SIGNED 0
88649     parameter \B_WIDTH 1
88650     parameter \Y_WIDTH 1
88651     connect \A \main_sdram_bankmachine0_cmd_valid
88652     connect \B $or$ls180.v:3845$307_Y
88653     connect \Y $and$ls180.v:3845$308_Y
88654   end
88655   attribute \src "ls180.v:3846.77-3846.153"
88656   cell $and $and$ls180.v:3846$309
88657     parameter \A_SIGNED 0
88658     parameter \A_WIDTH 1
88659     parameter \B_SIGNED 0
88660     parameter \B_WIDTH 1
88661     parameter \Y_WIDTH 1
88662     connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd
88663     connect \B \main_sdram_choose_req_want_cmds
88664     connect \Y $and$ls180.v:3846$309_Y
88665   end
88666   attribute \src "ls180.v:3846.162-3846.246"
88667   cell $and $and$ls180.v:3846$311
88668     parameter \A_SIGNED 0
88669     parameter \A_WIDTH 1
88670     parameter \B_SIGNED 0
88671     parameter \B_WIDTH 1
88672     parameter \Y_WIDTH 1
88673     connect \A \main_sdram_bankmachine1_cmd_payload_ras
88674     connect \B $not$ls180.v:3846$310_Y
88675     connect \Y $and$ls180.v:3846$311_Y
88676   end
88677   attribute \src "ls180.v:3846.161-3846.291"
88678   cell $and $and$ls180.v:3846$313
88679     parameter \A_SIGNED 0
88680     parameter \A_WIDTH 1
88681     parameter \B_SIGNED 0
88682     parameter \B_WIDTH 1
88683     parameter \Y_WIDTH 1
88684     connect \A $and$ls180.v:3846$311_Y
88685     connect \B $not$ls180.v:3846$312_Y
88686     connect \Y $and$ls180.v:3846$313_Y
88687   end
88688   attribute \src "ls180.v:3846.76-3846.333"
88689   cell $and $and$ls180.v:3846$316
88690     parameter \A_SIGNED 0
88691     parameter \A_WIDTH 1
88692     parameter \B_SIGNED 0
88693     parameter \B_WIDTH 1
88694     parameter \Y_WIDTH 1
88695     connect \A $and$ls180.v:3846$309_Y
88696     connect \B $or$ls180.v:3846$315_Y
88697     connect \Y $and$ls180.v:3846$316_Y
88698   end
88699   attribute \src "ls180.v:3846.338-3846.505"
88700   cell $and $and$ls180.v:3846$319
88701     parameter \A_SIGNED 0
88702     parameter \A_WIDTH 1
88703     parameter \B_SIGNED 0
88704     parameter \B_WIDTH 1
88705     parameter \Y_WIDTH 1
88706     connect \A $eq$ls180.v:3846$317_Y
88707     connect \B $eq$ls180.v:3846$318_Y
88708     connect \Y $and$ls180.v:3846$319_Y
88709   end
88710   attribute \src "ls180.v:3846.38-3846.507"
88711   cell $and $and$ls180.v:3846$321
88712     parameter \A_SIGNED 0
88713     parameter \A_WIDTH 1
88714     parameter \B_SIGNED 0
88715     parameter \B_WIDTH 1
88716     parameter \Y_WIDTH 1
88717     connect \A \main_sdram_bankmachine1_cmd_valid
88718     connect \B $or$ls180.v:3846$320_Y
88719     connect \Y $and$ls180.v:3846$321_Y
88720   end
88721   attribute \src "ls180.v:3847.77-3847.153"
88722   cell $and $and$ls180.v:3847$322
88723     parameter \A_SIGNED 0
88724     parameter \A_WIDTH 1
88725     parameter \B_SIGNED 0
88726     parameter \B_WIDTH 1
88727     parameter \Y_WIDTH 1
88728     connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd
88729     connect \B \main_sdram_choose_req_want_cmds
88730     connect \Y $and$ls180.v:3847$322_Y
88731   end
88732   attribute \src "ls180.v:3847.162-3847.246"
88733   cell $and $and$ls180.v:3847$324
88734     parameter \A_SIGNED 0
88735     parameter \A_WIDTH 1
88736     parameter \B_SIGNED 0
88737     parameter \B_WIDTH 1
88738     parameter \Y_WIDTH 1
88739     connect \A \main_sdram_bankmachine2_cmd_payload_ras
88740     connect \B $not$ls180.v:3847$323_Y
88741     connect \Y $and$ls180.v:3847$324_Y
88742   end
88743   attribute \src "ls180.v:3847.161-3847.291"
88744   cell $and $and$ls180.v:3847$326
88745     parameter \A_SIGNED 0
88746     parameter \A_WIDTH 1
88747     parameter \B_SIGNED 0
88748     parameter \B_WIDTH 1
88749     parameter \Y_WIDTH 1
88750     connect \A $and$ls180.v:3847$324_Y
88751     connect \B $not$ls180.v:3847$325_Y
88752     connect \Y $and$ls180.v:3847$326_Y
88753   end
88754   attribute \src "ls180.v:3847.76-3847.333"
88755   cell $and $and$ls180.v:3847$329
88756     parameter \A_SIGNED 0
88757     parameter \A_WIDTH 1
88758     parameter \B_SIGNED 0
88759     parameter \B_WIDTH 1
88760     parameter \Y_WIDTH 1
88761     connect \A $and$ls180.v:3847$322_Y
88762     connect \B $or$ls180.v:3847$328_Y
88763     connect \Y $and$ls180.v:3847$329_Y
88764   end
88765   attribute \src "ls180.v:3847.338-3847.505"
88766   cell $and $and$ls180.v:3847$332
88767     parameter \A_SIGNED 0
88768     parameter \A_WIDTH 1
88769     parameter \B_SIGNED 0
88770     parameter \B_WIDTH 1
88771     parameter \Y_WIDTH 1
88772     connect \A $eq$ls180.v:3847$330_Y
88773     connect \B $eq$ls180.v:3847$331_Y
88774     connect \Y $and$ls180.v:3847$332_Y
88775   end
88776   attribute \src "ls180.v:3847.38-3847.507"
88777   cell $and $and$ls180.v:3847$334
88778     parameter \A_SIGNED 0
88779     parameter \A_WIDTH 1
88780     parameter \B_SIGNED 0
88781     parameter \B_WIDTH 1
88782     parameter \Y_WIDTH 1
88783     connect \A \main_sdram_bankmachine2_cmd_valid
88784     connect \B $or$ls180.v:3847$333_Y
88785     connect \Y $and$ls180.v:3847$334_Y
88786   end
88787   attribute \src "ls180.v:3848.77-3848.153"
88788   cell $and $and$ls180.v:3848$335
88789     parameter \A_SIGNED 0
88790     parameter \A_WIDTH 1
88791     parameter \B_SIGNED 0
88792     parameter \B_WIDTH 1
88793     parameter \Y_WIDTH 1
88794     connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd
88795     connect \B \main_sdram_choose_req_want_cmds
88796     connect \Y $and$ls180.v:3848$335_Y
88797   end
88798   attribute \src "ls180.v:3848.162-3848.246"
88799   cell $and $and$ls180.v:3848$337
88800     parameter \A_SIGNED 0
88801     parameter \A_WIDTH 1
88802     parameter \B_SIGNED 0
88803     parameter \B_WIDTH 1
88804     parameter \Y_WIDTH 1
88805     connect \A \main_sdram_bankmachine3_cmd_payload_ras
88806     connect \B $not$ls180.v:3848$336_Y
88807     connect \Y $and$ls180.v:3848$337_Y
88808   end
88809   attribute \src "ls180.v:3848.161-3848.291"
88810   cell $and $and$ls180.v:3848$339
88811     parameter \A_SIGNED 0
88812     parameter \A_WIDTH 1
88813     parameter \B_SIGNED 0
88814     parameter \B_WIDTH 1
88815     parameter \Y_WIDTH 1
88816     connect \A $and$ls180.v:3848$337_Y
88817     connect \B $not$ls180.v:3848$338_Y
88818     connect \Y $and$ls180.v:3848$339_Y
88819   end
88820   attribute \src "ls180.v:3848.76-3848.333"
88821   cell $and $and$ls180.v:3848$342
88822     parameter \A_SIGNED 0
88823     parameter \A_WIDTH 1
88824     parameter \B_SIGNED 0
88825     parameter \B_WIDTH 1
88826     parameter \Y_WIDTH 1
88827     connect \A $and$ls180.v:3848$335_Y
88828     connect \B $or$ls180.v:3848$341_Y
88829     connect \Y $and$ls180.v:3848$342_Y
88830   end
88831   attribute \src "ls180.v:3848.338-3848.505"
88832   cell $and $and$ls180.v:3848$345
88833     parameter \A_SIGNED 0
88834     parameter \A_WIDTH 1
88835     parameter \B_SIGNED 0
88836     parameter \B_WIDTH 1
88837     parameter \Y_WIDTH 1
88838     connect \A $eq$ls180.v:3848$343_Y
88839     connect \B $eq$ls180.v:3848$344_Y
88840     connect \Y $and$ls180.v:3848$345_Y
88841   end
88842   attribute \src "ls180.v:3848.38-3848.507"
88843   cell $and $and$ls180.v:3848$347
88844     parameter \A_SIGNED 0
88845     parameter \A_WIDTH 1
88846     parameter \B_SIGNED 0
88847     parameter \B_WIDTH 1
88848     parameter \Y_WIDTH 1
88849     connect \A \main_sdram_bankmachine3_cmd_valid
88850     connect \B $or$ls180.v:3848$346_Y
88851     connect \Y $and$ls180.v:3848$347_Y
88852   end
88853   attribute \src "ls180.v:3877.8-3877.73"
88854   cell $and $and$ls180.v:3877$352
88855     parameter \A_SIGNED 0
88856     parameter \A_WIDTH 1
88857     parameter \B_SIGNED 0
88858     parameter \B_WIDTH 1
88859     parameter \Y_WIDTH 1
88860     connect \A \main_sdram_choose_cmd_cmd_valid
88861     connect \B \main_sdram_choose_cmd_cmd_ready
88862     connect \Y $and$ls180.v:3877$352_Y
88863   end
88864   attribute \src "ls180.v:3877.7-3877.114"
88865   cell $and $and$ls180.v:3877$354
88866     parameter \A_SIGNED 0
88867     parameter \A_WIDTH 1
88868     parameter \B_SIGNED 0
88869     parameter \B_WIDTH 1
88870     parameter \Y_WIDTH 1
88871     connect \A $and$ls180.v:3877$352_Y
88872     connect \B $eq$ls180.v:3877$353_Y
88873     connect \Y $and$ls180.v:3877$354_Y
88874   end
88875   attribute \src "ls180.v:3880.8-3880.73"
88876   cell $and $and$ls180.v:3880$355
88877     parameter \A_SIGNED 0
88878     parameter \A_WIDTH 1
88879     parameter \B_SIGNED 0
88880     parameter \B_WIDTH 1
88881     parameter \Y_WIDTH 1
88882     connect \A \main_sdram_choose_req_cmd_valid
88883     connect \B \main_sdram_choose_req_cmd_ready
88884     connect \Y $and$ls180.v:3880$355_Y
88885   end
88886   attribute \src "ls180.v:3880.7-3880.114"
88887   cell $and $and$ls180.v:3880$357
88888     parameter \A_SIGNED 0
88889     parameter \A_WIDTH 1
88890     parameter \B_SIGNED 0
88891     parameter \B_WIDTH 1
88892     parameter \Y_WIDTH 1
88893     connect \A $and$ls180.v:3880$355_Y
88894     connect \B $eq$ls180.v:3880$356_Y
88895     connect \Y $and$ls180.v:3880$357_Y
88896   end
88897   attribute \src "ls180.v:3886.8-3886.73"
88898   cell $and $and$ls180.v:3886$359
88899     parameter \A_SIGNED 0
88900     parameter \A_WIDTH 1
88901     parameter \B_SIGNED 0
88902     parameter \B_WIDTH 1
88903     parameter \Y_WIDTH 1
88904     connect \A \main_sdram_choose_cmd_cmd_valid
88905     connect \B \main_sdram_choose_cmd_cmd_ready
88906     connect \Y $and$ls180.v:3886$359_Y
88907   end
88908   attribute \src "ls180.v:3886.7-3886.114"
88909   cell $and $and$ls180.v:3886$361
88910     parameter \A_SIGNED 0
88911     parameter \A_WIDTH 1
88912     parameter \B_SIGNED 0
88913     parameter \B_WIDTH 1
88914     parameter \Y_WIDTH 1
88915     connect \A $and$ls180.v:3886$359_Y
88916     connect \B $eq$ls180.v:3886$360_Y
88917     connect \Y $and$ls180.v:3886$361_Y
88918   end
88919   attribute \src "ls180.v:3889.8-3889.73"
88920   cell $and $and$ls180.v:3889$362
88921     parameter \A_SIGNED 0
88922     parameter \A_WIDTH 1
88923     parameter \B_SIGNED 0
88924     parameter \B_WIDTH 1
88925     parameter \Y_WIDTH 1
88926     connect \A \main_sdram_choose_req_cmd_valid
88927     connect \B \main_sdram_choose_req_cmd_ready
88928     connect \Y $and$ls180.v:3889$362_Y
88929   end
88930   attribute \src "ls180.v:3889.7-3889.114"
88931   cell $and $and$ls180.v:3889$364
88932     parameter \A_SIGNED 0
88933     parameter \A_WIDTH 1
88934     parameter \B_SIGNED 0
88935     parameter \B_WIDTH 1
88936     parameter \Y_WIDTH 1
88937     connect \A $and$ls180.v:3889$362_Y
88938     connect \B $eq$ls180.v:3889$363_Y
88939     connect \Y $and$ls180.v:3889$364_Y
88940   end
88941   attribute \src "ls180.v:3895.8-3895.73"
88942   cell $and $and$ls180.v:3895$366
88943     parameter \A_SIGNED 0
88944     parameter \A_WIDTH 1
88945     parameter \B_SIGNED 0
88946     parameter \B_WIDTH 1
88947     parameter \Y_WIDTH 1
88948     connect \A \main_sdram_choose_cmd_cmd_valid
88949     connect \B \main_sdram_choose_cmd_cmd_ready
88950     connect \Y $and$ls180.v:3895$366_Y
88951   end
88952   attribute \src "ls180.v:3895.7-3895.114"
88953   cell $and $and$ls180.v:3895$368
88954     parameter \A_SIGNED 0
88955     parameter \A_WIDTH 1
88956     parameter \B_SIGNED 0
88957     parameter \B_WIDTH 1
88958     parameter \Y_WIDTH 1
88959     connect \A $and$ls180.v:3895$366_Y
88960     connect \B $eq$ls180.v:3895$367_Y
88961     connect \Y $and$ls180.v:3895$368_Y
88962   end
88963   attribute \src "ls180.v:3898.8-3898.73"
88964   cell $and $and$ls180.v:3898$369
88965     parameter \A_SIGNED 0
88966     parameter \A_WIDTH 1
88967     parameter \B_SIGNED 0
88968     parameter \B_WIDTH 1
88969     parameter \Y_WIDTH 1
88970     connect \A \main_sdram_choose_req_cmd_valid
88971     connect \B \main_sdram_choose_req_cmd_ready
88972     connect \Y $and$ls180.v:3898$369_Y
88973   end
88974   attribute \src "ls180.v:3898.7-3898.114"
88975   cell $and $and$ls180.v:3898$371
88976     parameter \A_SIGNED 0
88977     parameter \A_WIDTH 1
88978     parameter \B_SIGNED 0
88979     parameter \B_WIDTH 1
88980     parameter \Y_WIDTH 1
88981     connect \A $and$ls180.v:3898$369_Y
88982     connect \B $eq$ls180.v:3898$370_Y
88983     connect \Y $and$ls180.v:3898$371_Y
88984   end
88985   attribute \src "ls180.v:3904.8-3904.73"
88986   cell $and $and$ls180.v:3904$373
88987     parameter \A_SIGNED 0
88988     parameter \A_WIDTH 1
88989     parameter \B_SIGNED 0
88990     parameter \B_WIDTH 1
88991     parameter \Y_WIDTH 1
88992     connect \A \main_sdram_choose_cmd_cmd_valid
88993     connect \B \main_sdram_choose_cmd_cmd_ready
88994     connect \Y $and$ls180.v:3904$373_Y
88995   end
88996   attribute \src "ls180.v:3904.7-3904.114"
88997   cell $and $and$ls180.v:3904$375
88998     parameter \A_SIGNED 0
88999     parameter \A_WIDTH 1
89000     parameter \B_SIGNED 0
89001     parameter \B_WIDTH 1
89002     parameter \Y_WIDTH 1
89003     connect \A $and$ls180.v:3904$373_Y
89004     connect \B $eq$ls180.v:3904$374_Y
89005     connect \Y $and$ls180.v:3904$375_Y
89006   end
89007   attribute \src "ls180.v:3907.8-3907.73"
89008   cell $and $and$ls180.v:3907$376
89009     parameter \A_SIGNED 0
89010     parameter \A_WIDTH 1
89011     parameter \B_SIGNED 0
89012     parameter \B_WIDTH 1
89013     parameter \Y_WIDTH 1
89014     connect \A \main_sdram_choose_req_cmd_valid
89015     connect \B \main_sdram_choose_req_cmd_ready
89016     connect \Y $and$ls180.v:3907$376_Y
89017   end
89018   attribute \src "ls180.v:3907.7-3907.114"
89019   cell $and $and$ls180.v:3907$378
89020     parameter \A_SIGNED 0
89021     parameter \A_WIDTH 1
89022     parameter \B_SIGNED 0
89023     parameter \B_WIDTH 1
89024     parameter \Y_WIDTH 1
89025     connect \A $and$ls180.v:3907$376_Y
89026     connect \B $eq$ls180.v:3907$377_Y
89027     connect \Y $and$ls180.v:3907$378_Y
89028   end
89029   attribute \src "ls180.v:3932.71-3932.151"
89030   cell $and $and$ls180.v:3932$383
89031     parameter \A_SIGNED 0
89032     parameter \A_WIDTH 1
89033     parameter \B_SIGNED 0
89034     parameter \B_WIDTH 1
89035     parameter \Y_WIDTH 1
89036     connect \A \main_sdram_choose_req_cmd_payload_ras
89037     connect \B $not$ls180.v:3932$382_Y
89038     connect \Y $and$ls180.v:3932$383_Y
89039   end
89040   attribute \src "ls180.v:3932.70-3932.194"
89041   cell $and $and$ls180.v:3932$385
89042     parameter \A_SIGNED 0
89043     parameter \A_WIDTH 1
89044     parameter \B_SIGNED 0
89045     parameter \B_WIDTH 1
89046     parameter \Y_WIDTH 1
89047     connect \A $and$ls180.v:3932$383_Y
89048     connect \B $not$ls180.v:3932$384_Y
89049     connect \Y $and$ls180.v:3932$385_Y
89050   end
89051   attribute \src "ls180.v:3932.41-3932.222"
89052   cell $and $and$ls180.v:3932$388
89053     parameter \A_SIGNED 0
89054     parameter \A_WIDTH 1
89055     parameter \B_SIGNED 0
89056     parameter \B_WIDTH 1
89057     parameter \Y_WIDTH 1
89058     connect \A \main_sdram_cas_allowed
89059     connect \B $or$ls180.v:3932$387_Y
89060     connect \Y $and$ls180.v:3932$388_Y
89061   end
89062   attribute \src "ls180.v:3970.71-3970.151"
89063   cell $and $and$ls180.v:3970$392
89064     parameter \A_SIGNED 0
89065     parameter \A_WIDTH 1
89066     parameter \B_SIGNED 0
89067     parameter \B_WIDTH 1
89068     parameter \Y_WIDTH 1
89069     connect \A \main_sdram_choose_req_cmd_payload_ras
89070     connect \B $not$ls180.v:3970$391_Y
89071     connect \Y $and$ls180.v:3970$392_Y
89072   end
89073   attribute \src "ls180.v:3970.70-3970.194"
89074   cell $and $and$ls180.v:3970$394
89075     parameter \A_SIGNED 0
89076     parameter \A_WIDTH 1
89077     parameter \B_SIGNED 0
89078     parameter \B_WIDTH 1
89079     parameter \Y_WIDTH 1
89080     connect \A $and$ls180.v:3970$392_Y
89081     connect \B $not$ls180.v:3970$393_Y
89082     connect \Y $and$ls180.v:3970$394_Y
89083   end
89084   attribute \src "ls180.v:3970.41-3970.222"
89085   cell $and $and$ls180.v:3970$397
89086     parameter \A_SIGNED 0
89087     parameter \A_WIDTH 1
89088     parameter \B_SIGNED 0
89089     parameter \B_WIDTH 1
89090     parameter \Y_WIDTH 1
89091     connect \A \main_sdram_cas_allowed
89092     connect \B $or$ls180.v:3970$396_Y
89093     connect \Y $and$ls180.v:3970$397_Y
89094   end
89095   attribute \src "ls180.v:3988.110-3988.179"
89096   cell $and $and$ls180.v:3988$402
89097     parameter \A_SIGNED 0
89098     parameter \A_WIDTH 1
89099     parameter \B_SIGNED 0
89100     parameter \B_WIDTH 1
89101     parameter \Y_WIDTH 1
89102     connect \A \main_sdram_interface_bank1_lock
89103     connect \B $eq$ls180.v:3988$401_Y
89104     connect \Y $and$ls180.v:3988$402_Y
89105   end
89106   attribute \src "ls180.v:3988.185-3988.254"
89107   cell $and $and$ls180.v:3988$405
89108     parameter \A_SIGNED 0
89109     parameter \A_WIDTH 1
89110     parameter \B_SIGNED 0
89111     parameter \B_WIDTH 1
89112     parameter \Y_WIDTH 1
89113     connect \A \main_sdram_interface_bank2_lock
89114     connect \B $eq$ls180.v:3988$404_Y
89115     connect \Y $and$ls180.v:3988$405_Y
89116   end
89117   attribute \src "ls180.v:3988.260-3988.329"
89118   cell $and $and$ls180.v:3988$408
89119     parameter \A_SIGNED 0
89120     parameter \A_WIDTH 1
89121     parameter \B_SIGNED 0
89122     parameter \B_WIDTH 1
89123     parameter \Y_WIDTH 1
89124     connect \A \main_sdram_interface_bank3_lock
89125     connect \B $eq$ls180.v:3988$407_Y
89126     connect \Y $and$ls180.v:3988$408_Y
89127   end
89128   attribute \src "ls180.v:3988.41-3988.332"
89129   cell $and $and$ls180.v:3988$411
89130     parameter \A_SIGNED 0
89131     parameter \A_WIDTH 1
89132     parameter \B_SIGNED 0
89133     parameter \B_WIDTH 1
89134     parameter \Y_WIDTH 1
89135     connect \A $eq$ls180.v:3988$400_Y
89136     connect \B $not$ls180.v:3988$410_Y
89137     connect \Y $and$ls180.v:3988$411_Y
89138   end
89139   attribute \src "ls180.v:3988.40-3988.355"
89140   cell $and $and$ls180.v:3988$412
89141     parameter \A_SIGNED 0
89142     parameter \A_WIDTH 1
89143     parameter \B_SIGNED 0
89144     parameter \B_WIDTH 1
89145     parameter \Y_WIDTH 1
89146     connect \A $and$ls180.v:3988$411_Y
89147     connect \B \main_port_cmd_valid
89148     connect \Y $and$ls180.v:3988$412_Y
89149   end
89150   attribute \src "ls180.v:3989.34-3989.106"
89151   cell $and $and$ls180.v:3989$415
89152     parameter \A_SIGNED 0
89153     parameter \A_WIDTH 1
89154     parameter \B_SIGNED 0
89155     parameter \B_WIDTH 1
89156     parameter \Y_WIDTH 1
89157     connect \A $not$ls180.v:3989$413_Y
89158     connect \B $not$ls180.v:3989$414_Y
89159     connect \Y $and$ls180.v:3989$415_Y
89160   end
89161   attribute \src "ls180.v:3993.110-3993.179"
89162   cell $and $and$ls180.v:3993$418
89163     parameter \A_SIGNED 0
89164     parameter \A_WIDTH 1
89165     parameter \B_SIGNED 0
89166     parameter \B_WIDTH 1
89167     parameter \Y_WIDTH 1
89168     connect \A \main_sdram_interface_bank0_lock
89169     connect \B $eq$ls180.v:3993$417_Y
89170     connect \Y $and$ls180.v:3993$418_Y
89171   end
89172   attribute \src "ls180.v:3993.185-3993.254"
89173   cell $and $and$ls180.v:3993$421
89174     parameter \A_SIGNED 0
89175     parameter \A_WIDTH 1
89176     parameter \B_SIGNED 0
89177     parameter \B_WIDTH 1
89178     parameter \Y_WIDTH 1
89179     connect \A \main_sdram_interface_bank2_lock
89180     connect \B $eq$ls180.v:3993$420_Y
89181     connect \Y $and$ls180.v:3993$421_Y
89182   end
89183   attribute \src "ls180.v:3993.260-3993.329"
89184   cell $and $and$ls180.v:3993$424
89185     parameter \A_SIGNED 0
89186     parameter \A_WIDTH 1
89187     parameter \B_SIGNED 0
89188     parameter \B_WIDTH 1
89189     parameter \Y_WIDTH 1
89190     connect \A \main_sdram_interface_bank3_lock
89191     connect \B $eq$ls180.v:3993$423_Y
89192     connect \Y $and$ls180.v:3993$424_Y
89193   end
89194   attribute \src "ls180.v:3993.41-3993.332"
89195   cell $and $and$ls180.v:3993$427
89196     parameter \A_SIGNED 0
89197     parameter \A_WIDTH 1
89198     parameter \B_SIGNED 0
89199     parameter \B_WIDTH 1
89200     parameter \Y_WIDTH 1
89201     connect \A $eq$ls180.v:3993$416_Y
89202     connect \B $not$ls180.v:3993$426_Y
89203     connect \Y $and$ls180.v:3993$427_Y
89204   end
89205   attribute \src "ls180.v:3993.40-3993.355"
89206   cell $and $and$ls180.v:3993$428
89207     parameter \A_SIGNED 0
89208     parameter \A_WIDTH 1
89209     parameter \B_SIGNED 0
89210     parameter \B_WIDTH 1
89211     parameter \Y_WIDTH 1
89212     connect \A $and$ls180.v:3993$427_Y
89213     connect \B \main_port_cmd_valid
89214     connect \Y $and$ls180.v:3993$428_Y
89215   end
89216   attribute \src "ls180.v:3994.34-3994.106"
89217   cell $and $and$ls180.v:3994$431
89218     parameter \A_SIGNED 0
89219     parameter \A_WIDTH 1
89220     parameter \B_SIGNED 0
89221     parameter \B_WIDTH 1
89222     parameter \Y_WIDTH 1
89223     connect \A $not$ls180.v:3994$429_Y
89224     connect \B $not$ls180.v:3994$430_Y
89225     connect \Y $and$ls180.v:3994$431_Y
89226   end
89227   attribute \src "ls180.v:3998.110-3998.179"
89228   cell $and $and$ls180.v:3998$434
89229     parameter \A_SIGNED 0
89230     parameter \A_WIDTH 1
89231     parameter \B_SIGNED 0
89232     parameter \B_WIDTH 1
89233     parameter \Y_WIDTH 1
89234     connect \A \main_sdram_interface_bank0_lock
89235     connect \B $eq$ls180.v:3998$433_Y
89236     connect \Y $and$ls180.v:3998$434_Y
89237   end
89238   attribute \src "ls180.v:3998.185-3998.254"
89239   cell $and $and$ls180.v:3998$437
89240     parameter \A_SIGNED 0
89241     parameter \A_WIDTH 1
89242     parameter \B_SIGNED 0
89243     parameter \B_WIDTH 1
89244     parameter \Y_WIDTH 1
89245     connect \A \main_sdram_interface_bank1_lock
89246     connect \B $eq$ls180.v:3998$436_Y
89247     connect \Y $and$ls180.v:3998$437_Y
89248   end
89249   attribute \src "ls180.v:3998.260-3998.329"
89250   cell $and $and$ls180.v:3998$440
89251     parameter \A_SIGNED 0
89252     parameter \A_WIDTH 1
89253     parameter \B_SIGNED 0
89254     parameter \B_WIDTH 1
89255     parameter \Y_WIDTH 1
89256     connect \A \main_sdram_interface_bank3_lock
89257     connect \B $eq$ls180.v:3998$439_Y
89258     connect \Y $and$ls180.v:3998$440_Y
89259   end
89260   attribute \src "ls180.v:3998.41-3998.332"
89261   cell $and $and$ls180.v:3998$443
89262     parameter \A_SIGNED 0
89263     parameter \A_WIDTH 1
89264     parameter \B_SIGNED 0
89265     parameter \B_WIDTH 1
89266     parameter \Y_WIDTH 1
89267     connect \A $eq$ls180.v:3998$432_Y
89268     connect \B $not$ls180.v:3998$442_Y
89269     connect \Y $and$ls180.v:3998$443_Y
89270   end
89271   attribute \src "ls180.v:3998.40-3998.355"
89272   cell $and $and$ls180.v:3998$444
89273     parameter \A_SIGNED 0
89274     parameter \A_WIDTH 1
89275     parameter \B_SIGNED 0
89276     parameter \B_WIDTH 1
89277     parameter \Y_WIDTH 1
89278     connect \A $and$ls180.v:3998$443_Y
89279     connect \B \main_port_cmd_valid
89280     connect \Y $and$ls180.v:3998$444_Y
89281   end
89282   attribute \src "ls180.v:3999.34-3999.106"
89283   cell $and $and$ls180.v:3999$447
89284     parameter \A_SIGNED 0
89285     parameter \A_WIDTH 1
89286     parameter \B_SIGNED 0
89287     parameter \B_WIDTH 1
89288     parameter \Y_WIDTH 1
89289     connect \A $not$ls180.v:3999$445_Y
89290     connect \B $not$ls180.v:3999$446_Y
89291     connect \Y $and$ls180.v:3999$447_Y
89292   end
89293   attribute \src "ls180.v:4003.110-4003.179"
89294   cell $and $and$ls180.v:4003$450
89295     parameter \A_SIGNED 0
89296     parameter \A_WIDTH 1
89297     parameter \B_SIGNED 0
89298     parameter \B_WIDTH 1
89299     parameter \Y_WIDTH 1
89300     connect \A \main_sdram_interface_bank0_lock
89301     connect \B $eq$ls180.v:4003$449_Y
89302     connect \Y $and$ls180.v:4003$450_Y
89303   end
89304   attribute \src "ls180.v:4003.185-4003.254"
89305   cell $and $and$ls180.v:4003$453
89306     parameter \A_SIGNED 0
89307     parameter \A_WIDTH 1
89308     parameter \B_SIGNED 0
89309     parameter \B_WIDTH 1
89310     parameter \Y_WIDTH 1
89311     connect \A \main_sdram_interface_bank1_lock
89312     connect \B $eq$ls180.v:4003$452_Y
89313     connect \Y $and$ls180.v:4003$453_Y
89314   end
89315   attribute \src "ls180.v:4003.260-4003.329"
89316   cell $and $and$ls180.v:4003$456
89317     parameter \A_SIGNED 0
89318     parameter \A_WIDTH 1
89319     parameter \B_SIGNED 0
89320     parameter \B_WIDTH 1
89321     parameter \Y_WIDTH 1
89322     connect \A \main_sdram_interface_bank2_lock
89323     connect \B $eq$ls180.v:4003$455_Y
89324     connect \Y $and$ls180.v:4003$456_Y
89325   end
89326   attribute \src "ls180.v:4003.41-4003.332"
89327   cell $and $and$ls180.v:4003$459
89328     parameter \A_SIGNED 0
89329     parameter \A_WIDTH 1
89330     parameter \B_SIGNED 0
89331     parameter \B_WIDTH 1
89332     parameter \Y_WIDTH 1
89333     connect \A $eq$ls180.v:4003$448_Y
89334     connect \B $not$ls180.v:4003$458_Y
89335     connect \Y $and$ls180.v:4003$459_Y
89336   end
89337   attribute \src "ls180.v:4003.40-4003.355"
89338   cell $and $and$ls180.v:4003$460
89339     parameter \A_SIGNED 0
89340     parameter \A_WIDTH 1
89341     parameter \B_SIGNED 0
89342     parameter \B_WIDTH 1
89343     parameter \Y_WIDTH 1
89344     connect \A $and$ls180.v:4003$459_Y
89345     connect \B \main_port_cmd_valid
89346     connect \Y $and$ls180.v:4003$460_Y
89347   end
89348   attribute \src "ls180.v:4004.34-4004.106"
89349   cell $and $and$ls180.v:4004$463
89350     parameter \A_SIGNED 0
89351     parameter \A_WIDTH 1
89352     parameter \B_SIGNED 0
89353     parameter \B_WIDTH 1
89354     parameter \Y_WIDTH 1
89355     connect \A $not$ls180.v:4004$461_Y
89356     connect \B $not$ls180.v:4004$462_Y
89357     connect \Y $and$ls180.v:4004$463_Y
89358   end
89359   attribute \src "ls180.v:4008.151-4008.220"
89360   cell $and $and$ls180.v:4008$467
89361     parameter \A_SIGNED 0
89362     parameter \A_WIDTH 1
89363     parameter \B_SIGNED 0
89364     parameter \B_WIDTH 1
89365     parameter \Y_WIDTH 1
89366     connect \A \main_sdram_interface_bank1_lock
89367     connect \B $eq$ls180.v:4008$466_Y
89368     connect \Y $and$ls180.v:4008$467_Y
89369   end
89370   attribute \src "ls180.v:4008.226-4008.295"
89371   cell $and $and$ls180.v:4008$470
89372     parameter \A_SIGNED 0
89373     parameter \A_WIDTH 1
89374     parameter \B_SIGNED 0
89375     parameter \B_WIDTH 1
89376     parameter \Y_WIDTH 1
89377     connect \A \main_sdram_interface_bank2_lock
89378     connect \B $eq$ls180.v:4008$469_Y
89379     connect \Y $and$ls180.v:4008$470_Y
89380   end
89381   attribute \src "ls180.v:4008.301-4008.370"
89382   cell $and $and$ls180.v:4008$473
89383     parameter \A_SIGNED 0
89384     parameter \A_WIDTH 1
89385     parameter \B_SIGNED 0
89386     parameter \B_WIDTH 1
89387     parameter \Y_WIDTH 1
89388     connect \A \main_sdram_interface_bank3_lock
89389     connect \B $eq$ls180.v:4008$472_Y
89390     connect \Y $and$ls180.v:4008$473_Y
89391   end
89392   attribute \src "ls180.v:4008.82-4008.373"
89393   cell $and $and$ls180.v:4008$476
89394     parameter \A_SIGNED 0
89395     parameter \A_WIDTH 1
89396     parameter \B_SIGNED 0
89397     parameter \B_WIDTH 1
89398     parameter \Y_WIDTH 1
89399     connect \A $eq$ls180.v:4008$465_Y
89400     connect \B $not$ls180.v:4008$475_Y
89401     connect \Y $and$ls180.v:4008$476_Y
89402   end
89403   attribute \src "ls180.v:4008.43-4008.374"
89404   cell $and $and$ls180.v:4008$477
89405     parameter \A_SIGNED 0
89406     parameter \A_WIDTH 1
89407     parameter \B_SIGNED 0
89408     parameter \B_WIDTH 1
89409     parameter \Y_WIDTH 1
89410     connect \A $eq$ls180.v:4008$464_Y
89411     connect \B $and$ls180.v:4008$476_Y
89412     connect \Y $and$ls180.v:4008$477_Y
89413   end
89414   attribute \src "ls180.v:4008.42-4008.410"
89415   cell $and $and$ls180.v:4008$478
89416     parameter \A_SIGNED 0
89417     parameter \A_WIDTH 1
89418     parameter \B_SIGNED 0
89419     parameter \B_WIDTH 1
89420     parameter \Y_WIDTH 1
89421     connect \A $and$ls180.v:4008$477_Y
89422     connect \B \main_sdram_interface_bank0_ready
89423     connect \Y $and$ls180.v:4008$478_Y
89424   end
89425   attribute \src "ls180.v:4008.525-4008.594"
89426   cell $and $and$ls180.v:4008$483
89427     parameter \A_SIGNED 0
89428     parameter \A_WIDTH 1
89429     parameter \B_SIGNED 0
89430     parameter \B_WIDTH 1
89431     parameter \Y_WIDTH 1
89432     connect \A \main_sdram_interface_bank0_lock
89433     connect \B $eq$ls180.v:4008$482_Y
89434     connect \Y $and$ls180.v:4008$483_Y
89435   end
89436   attribute \src "ls180.v:4008.600-4008.669"
89437   cell $and $and$ls180.v:4008$486
89438     parameter \A_SIGNED 0
89439     parameter \A_WIDTH 1
89440     parameter \B_SIGNED 0
89441     parameter \B_WIDTH 1
89442     parameter \Y_WIDTH 1
89443     connect \A \main_sdram_interface_bank2_lock
89444     connect \B $eq$ls180.v:4008$485_Y
89445     connect \Y $and$ls180.v:4008$486_Y
89446   end
89447   attribute \src "ls180.v:4008.675-4008.744"
89448   cell $and $and$ls180.v:4008$489
89449     parameter \A_SIGNED 0
89450     parameter \A_WIDTH 1
89451     parameter \B_SIGNED 0
89452     parameter \B_WIDTH 1
89453     parameter \Y_WIDTH 1
89454     connect \A \main_sdram_interface_bank3_lock
89455     connect \B $eq$ls180.v:4008$488_Y
89456     connect \Y $and$ls180.v:4008$489_Y
89457   end
89458   attribute \src "ls180.v:4008.456-4008.747"
89459   cell $and $and$ls180.v:4008$492
89460     parameter \A_SIGNED 0
89461     parameter \A_WIDTH 1
89462     parameter \B_SIGNED 0
89463     parameter \B_WIDTH 1
89464     parameter \Y_WIDTH 1
89465     connect \A $eq$ls180.v:4008$481_Y
89466     connect \B $not$ls180.v:4008$491_Y
89467     connect \Y $and$ls180.v:4008$492_Y
89468   end
89469   attribute \src "ls180.v:4008.417-4008.748"
89470   cell $and $and$ls180.v:4008$493
89471     parameter \A_SIGNED 0
89472     parameter \A_WIDTH 1
89473     parameter \B_SIGNED 0
89474     parameter \B_WIDTH 1
89475     parameter \Y_WIDTH 1
89476     connect \A $eq$ls180.v:4008$480_Y
89477     connect \B $and$ls180.v:4008$492_Y
89478     connect \Y $and$ls180.v:4008$493_Y
89479   end
89480   attribute \src "ls180.v:4008.416-4008.784"
89481   cell $and $and$ls180.v:4008$494
89482     parameter \A_SIGNED 0
89483     parameter \A_WIDTH 1
89484     parameter \B_SIGNED 0
89485     parameter \B_WIDTH 1
89486     parameter \Y_WIDTH 1
89487     connect \A $and$ls180.v:4008$493_Y
89488     connect \B \main_sdram_interface_bank1_ready
89489     connect \Y $and$ls180.v:4008$494_Y
89490   end
89491   attribute \src "ls180.v:4008.899-4008.968"
89492   cell $and $and$ls180.v:4008$499
89493     parameter \A_SIGNED 0
89494     parameter \A_WIDTH 1
89495     parameter \B_SIGNED 0
89496     parameter \B_WIDTH 1
89497     parameter \Y_WIDTH 1
89498     connect \A \main_sdram_interface_bank0_lock
89499     connect \B $eq$ls180.v:4008$498_Y
89500     connect \Y $and$ls180.v:4008$499_Y
89501   end
89502   attribute \src "ls180.v:4008.974-4008.1043"
89503   cell $and $and$ls180.v:4008$502
89504     parameter \A_SIGNED 0
89505     parameter \A_WIDTH 1
89506     parameter \B_SIGNED 0
89507     parameter \B_WIDTH 1
89508     parameter \Y_WIDTH 1
89509     connect \A \main_sdram_interface_bank1_lock
89510     connect \B $eq$ls180.v:4008$501_Y
89511     connect \Y $and$ls180.v:4008$502_Y
89512   end
89513   attribute \src "ls180.v:4008.1049-4008.1118"
89514   cell $and $and$ls180.v:4008$505
89515     parameter \A_SIGNED 0
89516     parameter \A_WIDTH 1
89517     parameter \B_SIGNED 0
89518     parameter \B_WIDTH 1
89519     parameter \Y_WIDTH 1
89520     connect \A \main_sdram_interface_bank3_lock
89521     connect \B $eq$ls180.v:4008$504_Y
89522     connect \Y $and$ls180.v:4008$505_Y
89523   end
89524   attribute \src "ls180.v:4008.830-4008.1121"
89525   cell $and $and$ls180.v:4008$508
89526     parameter \A_SIGNED 0
89527     parameter \A_WIDTH 1
89528     parameter \B_SIGNED 0
89529     parameter \B_WIDTH 1
89530     parameter \Y_WIDTH 1
89531     connect \A $eq$ls180.v:4008$497_Y
89532     connect \B $not$ls180.v:4008$507_Y
89533     connect \Y $and$ls180.v:4008$508_Y
89534   end
89535   attribute \src "ls180.v:4008.791-4008.1122"
89536   cell $and $and$ls180.v:4008$509
89537     parameter \A_SIGNED 0
89538     parameter \A_WIDTH 1
89539     parameter \B_SIGNED 0
89540     parameter \B_WIDTH 1
89541     parameter \Y_WIDTH 1
89542     connect \A $eq$ls180.v:4008$496_Y
89543     connect \B $and$ls180.v:4008$508_Y
89544     connect \Y $and$ls180.v:4008$509_Y
89545   end
89546   attribute \src "ls180.v:4008.790-4008.1158"
89547   cell $and $and$ls180.v:4008$510
89548     parameter \A_SIGNED 0
89549     parameter \A_WIDTH 1
89550     parameter \B_SIGNED 0
89551     parameter \B_WIDTH 1
89552     parameter \Y_WIDTH 1
89553     connect \A $and$ls180.v:4008$509_Y
89554     connect \B \main_sdram_interface_bank2_ready
89555     connect \Y $and$ls180.v:4008$510_Y
89556   end
89557   attribute \src "ls180.v:4008.1273-4008.1342"
89558   cell $and $and$ls180.v:4008$515
89559     parameter \A_SIGNED 0
89560     parameter \A_WIDTH 1
89561     parameter \B_SIGNED 0
89562     parameter \B_WIDTH 1
89563     parameter \Y_WIDTH 1
89564     connect \A \main_sdram_interface_bank0_lock
89565     connect \B $eq$ls180.v:4008$514_Y
89566     connect \Y $and$ls180.v:4008$515_Y
89567   end
89568   attribute \src "ls180.v:4008.1348-4008.1417"
89569   cell $and $and$ls180.v:4008$518
89570     parameter \A_SIGNED 0
89571     parameter \A_WIDTH 1
89572     parameter \B_SIGNED 0
89573     parameter \B_WIDTH 1
89574     parameter \Y_WIDTH 1
89575     connect \A \main_sdram_interface_bank1_lock
89576     connect \B $eq$ls180.v:4008$517_Y
89577     connect \Y $and$ls180.v:4008$518_Y
89578   end
89579   attribute \src "ls180.v:4008.1423-4008.1492"
89580   cell $and $and$ls180.v:4008$521
89581     parameter \A_SIGNED 0
89582     parameter \A_WIDTH 1
89583     parameter \B_SIGNED 0
89584     parameter \B_WIDTH 1
89585     parameter \Y_WIDTH 1
89586     connect \A \main_sdram_interface_bank2_lock
89587     connect \B $eq$ls180.v:4008$520_Y
89588     connect \Y $and$ls180.v:4008$521_Y
89589   end
89590   attribute \src "ls180.v:4008.1204-4008.1495"
89591   cell $and $and$ls180.v:4008$524
89592     parameter \A_SIGNED 0
89593     parameter \A_WIDTH 1
89594     parameter \B_SIGNED 0
89595     parameter \B_WIDTH 1
89596     parameter \Y_WIDTH 1
89597     connect \A $eq$ls180.v:4008$513_Y
89598     connect \B $not$ls180.v:4008$523_Y
89599     connect \Y $and$ls180.v:4008$524_Y
89600   end
89601   attribute \src "ls180.v:4008.1165-4008.1496"
89602   cell $and $and$ls180.v:4008$525
89603     parameter \A_SIGNED 0
89604     parameter \A_WIDTH 1
89605     parameter \B_SIGNED 0
89606     parameter \B_WIDTH 1
89607     parameter \Y_WIDTH 1
89608     connect \A $eq$ls180.v:4008$512_Y
89609     connect \B $and$ls180.v:4008$524_Y
89610     connect \Y $and$ls180.v:4008$525_Y
89611   end
89612   attribute \src "ls180.v:4008.1164-4008.1532"
89613   cell $and $and$ls180.v:4008$526
89614     parameter \A_SIGNED 0
89615     parameter \A_WIDTH 1
89616     parameter \B_SIGNED 0
89617     parameter \B_WIDTH 1
89618     parameter \Y_WIDTH 1
89619     connect \A $and$ls180.v:4008$525_Y
89620     connect \B \main_sdram_interface_bank3_ready
89621     connect \Y $and$ls180.v:4008$526_Y
89622   end
89623   attribute \src "ls180.v:4066.9-4066.46"
89624   cell $and $and$ls180.v:4066$532
89625     parameter \A_SIGNED 0
89626     parameter \A_WIDTH 1
89627     parameter \B_SIGNED 0
89628     parameter \B_WIDTH 1
89629     parameter \Y_WIDTH 1
89630     connect \A \main_wb_sdram_stb
89631     connect \B \main_wb_sdram_cyc
89632     connect \Y $and$ls180.v:4066$532_Y
89633   end
89634   attribute \src "ls180.v:4084.9-4084.46"
89635   cell $and $and$ls180.v:4084$539
89636     parameter \A_SIGNED 0
89637     parameter \A_WIDTH 1
89638     parameter \B_SIGNED 0
89639     parameter \B_WIDTH 1
89640     parameter \Y_WIDTH 1
89641     connect \A \main_wb_sdram_stb
89642     connect \B \main_wb_sdram_cyc
89643     connect \Y $and$ls180.v:4084$539_Y
89644   end
89645   attribute \src "ls180.v:4097.32-4097.75"
89646   cell $and $and$ls180.v:4097$543
89647     parameter \A_SIGNED 0
89648     parameter \A_WIDTH 1
89649     parameter \B_SIGNED 0
89650     parameter \B_WIDTH 1
89651     parameter \Y_WIDTH 1
89652     connect \A \main_litedram_wb_cyc
89653     connect \B \main_litedram_wb_stb
89654     connect \Y $and$ls180.v:4097$543_Y
89655   end
89656   attribute \src "ls180.v:4097.31-4097.99"
89657   cell $and $and$ls180.v:4097$545
89658     parameter \A_SIGNED 0
89659     parameter \A_WIDTH 1
89660     parameter \B_SIGNED 0
89661     parameter \B_WIDTH 1
89662     parameter \Y_WIDTH 1
89663     connect \A $and$ls180.v:4097$543_Y
89664     connect \B $not$ls180.v:4097$544_Y
89665     connect \Y $and$ls180.v:4097$545_Y
89666   end
89667   attribute \src "ls180.v:4098.34-4098.102"
89668   cell $and $and$ls180.v:4098$547
89669     parameter \A_SIGNED 0
89670     parameter \A_WIDTH 1
89671     parameter \B_SIGNED 0
89672     parameter \B_WIDTH 1
89673     parameter \Y_WIDTH 1
89674     connect \A $or$ls180.v:4098$546_Y
89675     connect \B \main_port_cmd_payload_we
89676     connect \Y $and$ls180.v:4098$547_Y
89677   end
89678   attribute \src "ls180.v:4098.33-4098.128"
89679   cell $and $and$ls180.v:4098$549
89680     parameter \A_SIGNED 0
89681     parameter \A_WIDTH 1
89682     parameter \B_SIGNED 0
89683     parameter \B_WIDTH 1
89684     parameter \Y_WIDTH 1
89685     connect \A $and$ls180.v:4098$547_Y
89686     connect \B $not$ls180.v:4098$548_Y
89687     connect \Y $and$ls180.v:4098$549_Y
89688   end
89689   attribute \src "ls180.v:4099.33-4099.104"
89690   cell $and $and$ls180.v:4099$552
89691     parameter \A_SIGNED 0
89692     parameter \A_WIDTH 1
89693     parameter \B_SIGNED 0
89694     parameter \B_WIDTH 1
89695     parameter \Y_WIDTH 1
89696     connect \A $or$ls180.v:4099$550_Y
89697     connect \B $not$ls180.v:4099$551_Y
89698     connect \Y $and$ls180.v:4099$552_Y
89699   end
89700   attribute \src "ls180.v:4100.49-4100.85"
89701   cell $and $and$ls180.v:4100$553
89702     parameter \A_SIGNED 0
89703     parameter \A_WIDTH 1
89704     parameter \B_SIGNED 0
89705     parameter \B_WIDTH 1
89706     parameter \Y_WIDTH 1
89707     connect \A \main_litedram_wb_we
89708     connect \B \main_ack_wdata
89709     connect \Y $and$ls180.v:4100$553_Y
89710   end
89711   attribute \src "ls180.v:4100.90-4100.129"
89712   cell $and $and$ls180.v:4100$555
89713     parameter \A_SIGNED 0
89714     parameter \A_WIDTH 1
89715     parameter \B_SIGNED 0
89716     parameter \B_WIDTH 1
89717     parameter \Y_WIDTH 1
89718     connect \A $not$ls180.v:4100$554_Y
89719     connect \B \main_ack_rdata
89720     connect \Y $and$ls180.v:4100$555_Y
89721   end
89722   attribute \src "ls180.v:4100.32-4100.131"
89723   cell $and $and$ls180.v:4100$557
89724     parameter \A_SIGNED 0
89725     parameter \A_WIDTH 1
89726     parameter \B_SIGNED 0
89727     parameter \B_WIDTH 1
89728     parameter \Y_WIDTH 1
89729     connect \A \main_ack_cmd
89730     connect \B $or$ls180.v:4100$556_Y
89731     connect \Y $and$ls180.v:4100$557_Y
89732   end
89733   attribute \src "ls180.v:4101.25-4101.66"
89734   cell $and $and$ls180.v:4101$558
89735     parameter \A_SIGNED 0
89736     parameter \A_WIDTH 1
89737     parameter \B_SIGNED 0
89738     parameter \B_WIDTH 1
89739     parameter \Y_WIDTH 1
89740     connect \A \main_port_cmd_valid
89741     connect \B \main_port_cmd_ready
89742     connect \Y $and$ls180.v:4101$558_Y
89743   end
89744   attribute \src "ls180.v:4102.27-4102.72"
89745   cell $and $and$ls180.v:4102$560
89746     parameter \A_SIGNED 0
89747     parameter \A_WIDTH 1
89748     parameter \B_SIGNED 0
89749     parameter \B_WIDTH 1
89750     parameter \Y_WIDTH 1
89751     connect \A \main_port_wdata_valid
89752     connect \B \main_port_wdata_ready
89753     connect \Y $and$ls180.v:4102$560_Y
89754   end
89755   attribute \src "ls180.v:4103.26-4103.71"
89756   cell $and $and$ls180.v:4103$562
89757     parameter \A_SIGNED 0
89758     parameter \A_WIDTH 1
89759     parameter \B_SIGNED 0
89760     parameter \B_WIDTH 1
89761     parameter \Y_WIDTH 1
89762     connect \A \main_port_rdata_valid
89763     connect \B \main_port_rdata_ready
89764     connect \Y $and$ls180.v:4103$562_Y
89765   end
89766   attribute \src "ls180.v:4132.64-4132.88"
89767   cell $and $and$ls180.v:4132$568
89768     parameter \A_SIGNED 0
89769     parameter \A_WIDTH 1
89770     parameter \B_SIGNED 0
89771     parameter \B_WIDTH 1
89772     parameter \Y_WIDTH 1
89773     connect \A 1'0
89774     connect \B \main_uart_rxtx_we
89775     connect \Y $and$ls180.v:4132$568_Y
89776   end
89777   attribute \src "ls180.v:4136.7-4136.78"
89778   cell $and $and$ls180.v:4136$572
89779     parameter \A_SIGNED 0
89780     parameter \A_WIDTH 1
89781     parameter \B_SIGNED 0
89782     parameter \B_WIDTH 1
89783     parameter \Y_WIDTH 1
89784     connect \A \main_uart_eventmanager_pending_re
89785     connect \B \main_uart_eventmanager_pending_r [0]
89786     connect \Y $and$ls180.v:4136$572_Y
89787   end
89788   attribute \src "ls180.v:4147.7-4147.78"
89789   cell $and $and$ls180.v:4147$575
89790     parameter \A_SIGNED 0
89791     parameter \A_WIDTH 1
89792     parameter \B_SIGNED 0
89793     parameter \B_WIDTH 1
89794     parameter \Y_WIDTH 1
89795     connect \A \main_uart_eventmanager_pending_re
89796     connect \B \main_uart_eventmanager_pending_r [1]
89797     connect \Y $and$ls180.v:4147$575_Y
89798   end
89799   attribute \src "ls180.v:4156.26-4156.97"
89800   cell $and $and$ls180.v:4156$577
89801     parameter \A_SIGNED 0
89802     parameter \A_WIDTH 1
89803     parameter \B_SIGNED 0
89804     parameter \B_WIDTH 1
89805     parameter \Y_WIDTH 1
89806     connect \A \main_uart_eventmanager_pending_w [0]
89807     connect \B \main_uart_eventmanager_storage [0]
89808     connect \Y $and$ls180.v:4156$577_Y
89809   end
89810   attribute \src "ls180.v:4156.102-4156.173"
89811   cell $and $and$ls180.v:4156$578
89812     parameter \A_SIGNED 0
89813     parameter \A_WIDTH 1
89814     parameter \B_SIGNED 0
89815     parameter \B_WIDTH 1
89816     parameter \Y_WIDTH 1
89817     connect \A \main_uart_eventmanager_pending_w [1]
89818     connect \B \main_uart_eventmanager_storage [1]
89819     connect \Y $and$ls180.v:4156$578_Y
89820   end
89821   attribute \src "ls180.v:4171.41-4171.133"
89822   cell $and $and$ls180.v:4171$582
89823     parameter \A_SIGNED 0
89824     parameter \A_WIDTH 1
89825     parameter \B_SIGNED 0
89826     parameter \B_WIDTH 1
89827     parameter \Y_WIDTH 1
89828     connect \A \main_uart_tx_fifo_syncfifo_readable
89829     connect \B $or$ls180.v:4171$581_Y
89830     connect \Y $and$ls180.v:4171$582_Y
89831   end
89832   attribute \src "ls180.v:4182.39-4182.136"
89833   cell $and $and$ls180.v:4182$587
89834     parameter \A_SIGNED 0
89835     parameter \A_WIDTH 1
89836     parameter \B_SIGNED 0
89837     parameter \B_WIDTH 1
89838     parameter \Y_WIDTH 1
89839     connect \A \main_uart_tx_fifo_syncfifo_we
89840     connect \B $or$ls180.v:4182$586_Y
89841     connect \Y $and$ls180.v:4182$587_Y
89842   end
89843   attribute \src "ls180.v:4183.37-4183.104"
89844   cell $and $and$ls180.v:4183$588
89845     parameter \A_SIGNED 0
89846     parameter \A_WIDTH 1
89847     parameter \B_SIGNED 0
89848     parameter \B_WIDTH 1
89849     parameter \Y_WIDTH 1
89850     connect \A \main_uart_tx_fifo_syncfifo_readable
89851     connect \B \main_uart_tx_fifo_syncfifo_re
89852     connect \Y $and$ls180.v:4183$588_Y
89853   end
89854   attribute \src "ls180.v:4201.41-4201.133"
89855   cell $and $and$ls180.v:4201$593
89856     parameter \A_SIGNED 0
89857     parameter \A_WIDTH 1
89858     parameter \B_SIGNED 0
89859     parameter \B_WIDTH 1
89860     parameter \Y_WIDTH 1
89861     connect \A \main_uart_rx_fifo_syncfifo_readable
89862     connect \B $or$ls180.v:4201$592_Y
89863     connect \Y $and$ls180.v:4201$593_Y
89864   end
89865   attribute \src "ls180.v:4212.39-4212.136"
89866   cell $and $and$ls180.v:4212$598
89867     parameter \A_SIGNED 0
89868     parameter \A_WIDTH 1
89869     parameter \B_SIGNED 0
89870     parameter \B_WIDTH 1
89871     parameter \Y_WIDTH 1
89872     connect \A \main_uart_rx_fifo_syncfifo_we
89873     connect \B $or$ls180.v:4212$597_Y
89874     connect \Y $and$ls180.v:4212$598_Y
89875   end
89876   attribute \src "ls180.v:4213.37-4213.104"
89877   cell $and $and$ls180.v:4213$599
89878     parameter \A_SIGNED 0
89879     parameter \A_WIDTH 1
89880     parameter \B_SIGNED 0
89881     parameter \B_WIDTH 1
89882     parameter \Y_WIDTH 1
89883     connect \A \main_uart_rx_fifo_syncfifo_readable
89884     connect \B \main_uart_rx_fifo_syncfifo_re
89885     connect \Y $and$ls180.v:4213$599_Y
89886   end
89887   attribute \src "ls180.v:4401.33-4401.86"
89888   cell $and $and$ls180.v:4401$641
89889     parameter \A_SIGNED 0
89890     parameter \A_WIDTH 1
89891     parameter \B_SIGNED 0
89892     parameter \B_WIDTH 1
89893     parameter \Y_WIDTH 1
89894     connect \A \main_sdphy_clocker_clk1
89895     connect \B $not$ls180.v:4401$640_Y
89896     connect \Y $and$ls180.v:4401$641_Y
89897   end
89898   attribute \src "ls180.v:4505.9-4505.68"
89899   cell $and $and$ls180.v:4505$650
89900     parameter \A_SIGNED 0
89901     parameter \A_WIDTH 1
89902     parameter \B_SIGNED 0
89903     parameter \B_WIDTH 1
89904     parameter \Y_WIDTH 1
89905     connect \A \main_sdphy_cmdw_sink_valid
89906     connect \B \main_sdphy_cmdw_pads_out_ready
89907     connect \Y $and$ls180.v:4505$650_Y
89908   end
89909   attribute \src "ls180.v:4525.53-4525.145"
89910   cell $and $and$ls180.v:4525$653
89911     parameter \A_SIGNED 0
89912     parameter \A_WIDTH 1
89913     parameter \B_SIGNED 0
89914     parameter \B_WIDTH 1
89915     parameter \Y_WIDTH 1
89916     connect \A \main_sdphy_cmdr_cmdr_pads_in_valid
89917     connect \B $or$ls180.v:4525$652_Y
89918     connect \Y $and$ls180.v:4525$653_Y
89919   end
89920   attribute \src "ls180.v:4544.52-4544.137"
89921   cell $and $and$ls180.v:4544$656
89922     parameter \A_SIGNED 0
89923     parameter \A_WIDTH 1
89924     parameter \B_SIGNED 0
89925     parameter \B_WIDTH 1
89926     parameter \Y_WIDTH 1
89927     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
89928     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
89929     connect \Y $and$ls180.v:4544$656_Y
89930   end
89931   attribute \src "ls180.v:4585.9-4585.68"
89932   cell $and $and$ls180.v:4585$664
89933     parameter \A_SIGNED 0
89934     parameter \A_WIDTH 1
89935     parameter \B_SIGNED 0
89936     parameter \B_WIDTH 1
89937     parameter \Y_WIDTH 1
89938     connect \A \main_sdphy_cmdr_source_valid
89939     connect \B \main_sdphy_cmdr_source_ready
89940     connect \Y $and$ls180.v:4585$664_Y
89941   end
89942   attribute \src "ls180.v:4623.9-4623.68"
89943   cell $and $and$ls180.v:4623$670
89944     parameter \A_SIGNED 0
89945     parameter \A_WIDTH 1
89946     parameter \B_SIGNED 0
89947     parameter \B_WIDTH 1
89948     parameter \Y_WIDTH 1
89949     connect \A \main_sdphy_cmdr_source_valid
89950     connect \B \main_sdphy_cmdr_source_ready
89951     connect \Y $and$ls180.v:4623$670_Y
89952   end
89953   attribute \src "ls180.v:4632.10-4632.69"
89954   cell $and $and$ls180.v:4632$671
89955     parameter \A_SIGNED 0
89956     parameter \A_WIDTH 1
89957     parameter \B_SIGNED 0
89958     parameter \B_WIDTH 1
89959     parameter \Y_WIDTH 1
89960     connect \A \main_sdphy_cmdr_sink_valid
89961     connect \B \main_sdphy_cmdr_pads_out_ready
89962     connect \Y $and$ls180.v:4632$671_Y
89963   end
89964   attribute \src "ls180.v:4632.9-4632.93"
89965   cell $and $and$ls180.v:4632$672
89966     parameter \A_SIGNED 0
89967     parameter \A_WIDTH 1
89968     parameter \B_SIGNED 0
89969     parameter \B_WIDTH 1
89970     parameter \Y_WIDTH 1
89971     connect \A $and$ls180.v:4632$671_Y
89972     connect \B \main_sdphy_cmdw_done
89973     connect \Y $and$ls180.v:4632$672_Y
89974   end
89975   attribute \src "ls180.v:4652.54-4652.117"
89976   cell $and $and$ls180.v:4652$674
89977     parameter \A_SIGNED 0
89978     parameter \A_WIDTH 1
89979     parameter \B_SIGNED 0
89980     parameter \B_WIDTH 1
89981     parameter \Y_WIDTH 1
89982     connect \A \main_sdphy_dataw_crcr_pads_in_valid
89983     connect \B \main_sdphy_dataw_crcr_run
89984     connect \Y $and$ls180.v:4652$674_Y
89985   end
89986   attribute \src "ls180.v:4671.53-4671.140"
89987   cell $and $and$ls180.v:4671$677
89988     parameter \A_SIGNED 0
89989     parameter \A_WIDTH 1
89990     parameter \B_SIGNED 0
89991     parameter \B_WIDTH 1
89992     parameter \Y_WIDTH 1
89993     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
89994     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
89995     connect \Y $and$ls180.v:4671$677_Y
89996   end
89997   attribute \src "ls180.v:4768.9-4768.70"
89998   cell $and $and$ls180.v:4768$687
89999     parameter \A_SIGNED 0
90000     parameter \A_WIDTH 1
90001     parameter \B_SIGNED 0
90002     parameter \B_WIDTH 1
90003     parameter \Y_WIDTH 1
90004     connect \A \main_sdphy_dataw_sink_valid
90005     connect \B \main_sdphy_dataw_pads_out_ready
90006     connect \Y $and$ls180.v:4768$687_Y
90007   end
90008   attribute \src "ls180.v:4786.55-4786.120"
90009   cell $and $and$ls180.v:4786$689
90010     parameter \A_SIGNED 0
90011     parameter \A_WIDTH 1
90012     parameter \B_SIGNED 0
90013     parameter \B_WIDTH 1
90014     parameter \Y_WIDTH 1
90015     connect \A \main_sdphy_datar_datar_pads_in_valid
90016     connect \B \main_sdphy_datar_datar_run
90017     connect \Y $and$ls180.v:4786$689_Y
90018   end
90019   attribute \src "ls180.v:4805.54-4805.143"
90020   cell $and $and$ls180.v:4805$692
90021     parameter \A_SIGNED 0
90022     parameter \A_WIDTH 1
90023     parameter \B_SIGNED 0
90024     parameter \B_WIDTH 1
90025     parameter \Y_WIDTH 1
90026     connect \A \main_sdphy_datar_datar_converter_sink_valid
90027     connect \B \main_sdphy_datar_datar_converter_sink_ready
90028     connect \Y $and$ls180.v:4805$692_Y
90029   end
90030   attribute \src "ls180.v:4887.9-4887.70"
90031   cell $and $and$ls180.v:4887$707
90032     parameter \A_SIGNED 0
90033     parameter \A_WIDTH 1
90034     parameter \B_SIGNED 0
90035     parameter \B_WIDTH 1
90036     parameter \Y_WIDTH 1
90037     connect \A \main_sdphy_datar_source_valid
90038     connect \B \main_sdphy_datar_source_ready
90039     connect \Y $and$ls180.v:4887$707_Y
90040   end
90041   attribute \src "ls180.v:4894.9-4894.70"
90042   cell $and $and$ls180.v:4894$708
90043     parameter \A_SIGNED 0
90044     parameter \A_WIDTH 1
90045     parameter \B_SIGNED 0
90046     parameter \B_WIDTH 1
90047     parameter \Y_WIDTH 1
90048     connect \A \main_sdphy_datar_sink_valid
90049     connect \B \main_sdphy_datar_pads_out_ready
90050     connect \Y $and$ls180.v:4894$708_Y
90051   end
90052   attribute \src "ls180.v:4975.48-4975.124"
90053   cell $and $and$ls180.v:4975$831
90054     parameter \A_SIGNED 0
90055     parameter \A_WIDTH 1
90056     parameter \B_SIGNED 0
90057     parameter \B_WIDTH 1
90058     parameter \Y_WIDTH 1
90059     connect \A \main_sdcore_crc16_inserter_sink_last
90060     connect \B \main_sdcore_crc16_inserter_sink_valid
90061     connect \Y $and$ls180.v:4975$831_Y
90062   end
90063   attribute \src "ls180.v:4975.47-4975.165"
90064   cell $and $and$ls180.v:4975$832
90065     parameter \A_SIGNED 0
90066     parameter \A_WIDTH 1
90067     parameter \B_SIGNED 0
90068     parameter \B_WIDTH 1
90069     parameter \Y_WIDTH 1
90070     connect \A $and$ls180.v:4975$831_Y
90071     connect \B \main_sdcore_crc16_inserter_sink_ready
90072     connect \Y $and$ls180.v:4975$832_Y
90073   end
90074   attribute \src "ls180.v:4976.50-4976.127"
90075   cell $and $and$ls180.v:4976$833
90076     parameter \A_SIGNED 0
90077     parameter \A_WIDTH 1
90078     parameter \B_SIGNED 0
90079     parameter \B_WIDTH 1
90080     parameter \Y_WIDTH 1
90081     connect \A \main_sdcore_crc16_inserter_sink_valid
90082     connect \B \main_sdcore_crc16_inserter_sink_ready
90083     connect \Y $and$ls180.v:4976$833_Y
90084   end
90085   attribute \src "ls180.v:4978.48-4978.124"
90086   cell $and $and$ls180.v:4978$834
90087     parameter \A_SIGNED 0
90088     parameter \A_WIDTH 1
90089     parameter \B_SIGNED 0
90090     parameter \B_WIDTH 1
90091     parameter \Y_WIDTH 1
90092     connect \A \main_sdcore_crc16_inserter_sink_last
90093     connect \B \main_sdcore_crc16_inserter_sink_valid
90094     connect \Y $and$ls180.v:4978$834_Y
90095   end
90096   attribute \src "ls180.v:4978.47-4978.165"
90097   cell $and $and$ls180.v:4978$835
90098     parameter \A_SIGNED 0
90099     parameter \A_WIDTH 1
90100     parameter \B_SIGNED 0
90101     parameter \B_WIDTH 1
90102     parameter \Y_WIDTH 1
90103     connect \A $and$ls180.v:4978$834_Y
90104     connect \B \main_sdcore_crc16_inserter_sink_ready
90105     connect \Y $and$ls180.v:4978$835_Y
90106   end
90107   attribute \src "ls180.v:4979.50-4979.127"
90108   cell $and $and$ls180.v:4979$836
90109     parameter \A_SIGNED 0
90110     parameter \A_WIDTH 1
90111     parameter \B_SIGNED 0
90112     parameter \B_WIDTH 1
90113     parameter \Y_WIDTH 1
90114     connect \A \main_sdcore_crc16_inserter_sink_valid
90115     connect \B \main_sdcore_crc16_inserter_sink_ready
90116     connect \Y $and$ls180.v:4979$836_Y
90117   end
90118   attribute \src "ls180.v:4981.48-4981.124"
90119   cell $and $and$ls180.v:4981$837
90120     parameter \A_SIGNED 0
90121     parameter \A_WIDTH 1
90122     parameter \B_SIGNED 0
90123     parameter \B_WIDTH 1
90124     parameter \Y_WIDTH 1
90125     connect \A \main_sdcore_crc16_inserter_sink_last
90126     connect \B \main_sdcore_crc16_inserter_sink_valid
90127     connect \Y $and$ls180.v:4981$837_Y
90128   end
90129   attribute \src "ls180.v:4981.47-4981.165"
90130   cell $and $and$ls180.v:4981$838
90131     parameter \A_SIGNED 0
90132     parameter \A_WIDTH 1
90133     parameter \B_SIGNED 0
90134     parameter \B_WIDTH 1
90135     parameter \Y_WIDTH 1
90136     connect \A $and$ls180.v:4981$837_Y
90137     connect \B \main_sdcore_crc16_inserter_sink_ready
90138     connect \Y $and$ls180.v:4981$838_Y
90139   end
90140   attribute \src "ls180.v:4982.50-4982.127"
90141   cell $and $and$ls180.v:4982$839
90142     parameter \A_SIGNED 0
90143     parameter \A_WIDTH 1
90144     parameter \B_SIGNED 0
90145     parameter \B_WIDTH 1
90146     parameter \Y_WIDTH 1
90147     connect \A \main_sdcore_crc16_inserter_sink_valid
90148     connect \B \main_sdcore_crc16_inserter_sink_ready
90149     connect \Y $and$ls180.v:4982$839_Y
90150   end
90151   attribute \src "ls180.v:4984.48-4984.124"
90152   cell $and $and$ls180.v:4984$840
90153     parameter \A_SIGNED 0
90154     parameter \A_WIDTH 1
90155     parameter \B_SIGNED 0
90156     parameter \B_WIDTH 1
90157     parameter \Y_WIDTH 1
90158     connect \A \main_sdcore_crc16_inserter_sink_last
90159     connect \B \main_sdcore_crc16_inserter_sink_valid
90160     connect \Y $and$ls180.v:4984$840_Y
90161   end
90162   attribute \src "ls180.v:4984.47-4984.165"
90163   cell $and $and$ls180.v:4984$841
90164     parameter \A_SIGNED 0
90165     parameter \A_WIDTH 1
90166     parameter \B_SIGNED 0
90167     parameter \B_WIDTH 1
90168     parameter \Y_WIDTH 1
90169     connect \A $and$ls180.v:4984$840_Y
90170     connect \B \main_sdcore_crc16_inserter_sink_ready
90171     connect \Y $and$ls180.v:4984$841_Y
90172   end
90173   attribute \src "ls180.v:4985.50-4985.127"
90174   cell $and $and$ls180.v:4985$842
90175     parameter \A_SIGNED 0
90176     parameter \A_WIDTH 1
90177     parameter \B_SIGNED 0
90178     parameter \B_WIDTH 1
90179     parameter \Y_WIDTH 1
90180     connect \A \main_sdcore_crc16_inserter_sink_valid
90181     connect \B \main_sdcore_crc16_inserter_sink_ready
90182     connect \Y $and$ls180.v:4985$842_Y
90183   end
90184   attribute \src "ls180.v:5098.10-5098.86"
90185   cell $and $and$ls180.v:5098$891
90186     parameter \A_SIGNED 0
90187     parameter \A_WIDTH 1
90188     parameter \B_SIGNED 0
90189     parameter \B_WIDTH 1
90190     parameter \Y_WIDTH 1
90191     connect \A \main_sdcore_crc16_inserter_sink_valid
90192     connect \B \main_sdcore_crc16_inserter_sink_last
90193     connect \Y $and$ls180.v:5098$891_Y
90194   end
90195   attribute \src "ls180.v:5098.9-5098.127"
90196   cell $and $and$ls180.v:5098$892
90197     parameter \A_SIGNED 0
90198     parameter \A_WIDTH 1
90199     parameter \B_SIGNED 0
90200     parameter \B_WIDTH 1
90201     parameter \Y_WIDTH 1
90202     connect \A $and$ls180.v:5098$891_Y
90203     connect \B \main_sdcore_crc16_inserter_sink_ready
90204     connect \Y $and$ls180.v:5098$892_Y
90205   end
90206   attribute \src "ls180.v:5108.9-5108.152"
90207   cell $and $and$ls180.v:5108$896
90208     parameter \A_SIGNED 0
90209     parameter \A_WIDTH 1
90210     parameter \B_SIGNED 0
90211     parameter \B_WIDTH 1
90212     parameter \Y_WIDTH 1
90213     connect \A $eq$ls180.v:5108$894_Y
90214     connect \B $eq$ls180.v:5108$895_Y
90215     connect \Y $and$ls180.v:5108$896_Y
90216   end
90217   attribute \src "ls180.v:5108.8-5108.226"
90218   cell $and $and$ls180.v:5108$898
90219     parameter \A_SIGNED 0
90220     parameter \A_WIDTH 1
90221     parameter \B_SIGNED 0
90222     parameter \B_WIDTH 1
90223     parameter \Y_WIDTH 1
90224     connect \A $and$ls180.v:5108$896_Y
90225     connect \B $eq$ls180.v:5108$897_Y
90226     connect \Y $and$ls180.v:5108$898_Y
90227   end
90228   attribute \src "ls180.v:5108.7-5108.300"
90229   cell $and $and$ls180.v:5108$900
90230     parameter \A_SIGNED 0
90231     parameter \A_WIDTH 1
90232     parameter \B_SIGNED 0
90233     parameter \B_WIDTH 1
90234     parameter \Y_WIDTH 1
90235     connect \A $and$ls180.v:5108$898_Y
90236     connect \B $eq$ls180.v:5108$899_Y
90237     connect \Y $and$ls180.v:5108$900_Y
90238   end
90239   attribute \src "ls180.v:5113.49-5113.124"
90240   cell $and $and$ls180.v:5113$901
90241     parameter \A_SIGNED 0
90242     parameter \A_WIDTH 1
90243     parameter \B_SIGNED 0
90244     parameter \B_WIDTH 1
90245     parameter \Y_WIDTH 1
90246     connect \A \main_sdcore_crc16_checker_sink_valid
90247     connect \B \main_sdcore_crc16_checker_sink_ready
90248     connect \Y $and$ls180.v:5113$901_Y
90249   end
90250   attribute \src "ls180.v:5123.49-5123.124"
90251   cell $and $and$ls180.v:5123$904
90252     parameter \A_SIGNED 0
90253     parameter \A_WIDTH 1
90254     parameter \B_SIGNED 0
90255     parameter \B_WIDTH 1
90256     parameter \Y_WIDTH 1
90257     connect \A \main_sdcore_crc16_checker_sink_valid
90258     connect \B \main_sdcore_crc16_checker_sink_ready
90259     connect \Y $and$ls180.v:5123$904_Y
90260   end
90261   attribute \src "ls180.v:5133.49-5133.124"
90262   cell $and $and$ls180.v:5133$907
90263     parameter \A_SIGNED 0
90264     parameter \A_WIDTH 1
90265     parameter \B_SIGNED 0
90266     parameter \B_WIDTH 1
90267     parameter \Y_WIDTH 1
90268     connect \A \main_sdcore_crc16_checker_sink_valid
90269     connect \B \main_sdcore_crc16_checker_sink_ready
90270     connect \Y $and$ls180.v:5133$907_Y
90271   end
90272   attribute \src "ls180.v:5143.49-5143.124"
90273   cell $and $and$ls180.v:5143$910
90274     parameter \A_SIGNED 0
90275     parameter \A_WIDTH 1
90276     parameter \B_SIGNED 0
90277     parameter \B_WIDTH 1
90278     parameter \Y_WIDTH 1
90279     connect \A \main_sdcore_crc16_checker_sink_valid
90280     connect \B \main_sdcore_crc16_checker_sink_ready
90281     connect \Y $and$ls180.v:5143$910_Y
90282   end
90283   attribute \src "ls180.v:5155.7-5155.84"
90284   cell $and $and$ls180.v:5155$915
90285     parameter \A_SIGNED 0
90286     parameter \A_WIDTH 1
90287     parameter \B_SIGNED 0
90288     parameter \B_WIDTH 1
90289     parameter \Y_WIDTH 1
90290     connect \A \main_sdcore_crc16_checker_sink_valid
90291     connect \B $gt$ls180.v:5155$914_Y
90292     connect \Y $and$ls180.v:5155$915_Y
90293   end
90294   attribute \src "ls180.v:5273.9-5273.64"
90295   cell $and $and$ls180.v:5273$964
90296     parameter \A_SIGNED 0
90297     parameter \A_WIDTH 1
90298     parameter \B_SIGNED 0
90299     parameter \B_WIDTH 1
90300     parameter \Y_WIDTH 1
90301     connect \A \main_sdphy_cmdw_sink_valid
90302     connect \B \main_sdphy_cmdw_sink_ready
90303     connect \Y $and$ls180.v:5273$964_Y
90304   end
90305   attribute \src "ls180.v:5325.10-5325.66"
90306   cell $and $and$ls180.v:5325$973
90307     parameter \A_SIGNED 0
90308     parameter \A_WIDTH 1
90309     parameter \B_SIGNED 0
90310     parameter \B_WIDTH 1
90311     parameter \Y_WIDTH 1
90312     connect \A \main_sdphy_dataw_sink_valid
90313     connect \B \main_sdphy_dataw_sink_last
90314     connect \Y $and$ls180.v:5325$973_Y
90315   end
90316   attribute \src "ls180.v:5325.9-5325.97"
90317   cell $and $and$ls180.v:5325$974
90318     parameter \A_SIGNED 0
90319     parameter \A_WIDTH 1
90320     parameter \B_SIGNED 0
90321     parameter \B_WIDTH 1
90322     parameter \Y_WIDTH 1
90323     connect \A $and$ls180.v:5325$973_Y
90324     connect \B \main_sdphy_dataw_sink_ready
90325     connect \Y $and$ls180.v:5325$974_Y
90326   end
90327   attribute \src "ls180.v:5351.11-5351.71"
90328   cell $and $and$ls180.v:5351$982
90329     parameter \A_SIGNED 0
90330     parameter \A_WIDTH 1
90331     parameter \B_SIGNED 0
90332     parameter \B_WIDTH 1
90333     parameter \Y_WIDTH 1
90334     connect \A \main_sdphy_datar_source_last
90335     connect \B \main_sdphy_datar_source_ready
90336     connect \Y $and$ls180.v:5351$982_Y
90337   end
90338   attribute \src "ls180.v:5435.43-5435.152"
90339   cell $and $and$ls180.v:5435$990
90340     parameter \A_SIGNED 0
90341     parameter \A_WIDTH 1
90342     parameter \B_SIGNED 0
90343     parameter \B_WIDTH 1
90344     parameter \Y_WIDTH 1
90345     connect \A \main_sdblock2mem_fifo_syncfifo_we
90346     connect \B $or$ls180.v:5435$989_Y
90347     connect \Y $and$ls180.v:5435$990_Y
90348   end
90349   attribute \src "ls180.v:5436.41-5436.116"
90350   cell $and $and$ls180.v:5436$991
90351     parameter \A_SIGNED 0
90352     parameter \A_WIDTH 1
90353     parameter \B_SIGNED 0
90354     parameter \B_WIDTH 1
90355     parameter \Y_WIDTH 1
90356     connect \A \main_sdblock2mem_fifo_syncfifo_readable
90357     connect \B \main_sdblock2mem_fifo_syncfifo_re
90358     connect \Y $and$ls180.v:5436$991_Y
90359   end
90360   attribute \src "ls180.v:5448.48-5448.125"
90361   cell $and $and$ls180.v:5448$996
90362     parameter \A_SIGNED 0
90363     parameter \A_WIDTH 1
90364     parameter \B_SIGNED 0
90365     parameter \B_WIDTH 1
90366     parameter \Y_WIDTH 1
90367     connect \A \main_sdblock2mem_converter_sink_valid
90368     connect \B \main_sdblock2mem_converter_sink_ready
90369     connect \Y $and$ls180.v:5448$996_Y
90370   end
90371   attribute \src "ls180.v:5475.9-5475.102"
90372   cell $and $and$ls180.v:5475$1000
90373     parameter \A_SIGNED 0
90374     parameter \A_WIDTH 1
90375     parameter \B_SIGNED 0
90376     parameter \B_WIDTH 1
90377     parameter \Y_WIDTH 1
90378     connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid
90379     connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready
90380     connect \Y $and$ls180.v:5475$1000_Y
90381   end
90382   attribute \src "ls180.v:5548.9-5548.58"
90383   cell $and $and$ls180.v:5548$1006
90384     parameter \A_SIGNED 0
90385     parameter \A_WIDTH 1
90386     parameter \B_SIGNED 0
90387     parameter \B_WIDTH 1
90388     parameter \Y_WIDTH 1
90389     connect \A \main_interface1_bus_stb
90390     connect \B \main_interface1_bus_ack
90391     connect \Y $and$ls180.v:5548$1006_Y
90392   end
90393   attribute \src "ls180.v:5601.51-5601.123"
90394   cell $and $and$ls180.v:5601$1014
90395     parameter \A_SIGNED 0
90396     parameter \A_WIDTH 1
90397     parameter \B_SIGNED 0
90398     parameter \B_WIDTH 1
90399     parameter \Y_WIDTH 1
90400     connect \A \main_sdmem2block_converter_sink_first
90401     connect \B \main_sdmem2block_converter_first
90402     connect \Y $and$ls180.v:5601$1014_Y
90403   end
90404   attribute \src "ls180.v:5602.50-5602.120"
90405   cell $and $and$ls180.v:5602$1015
90406     parameter \A_SIGNED 0
90407     parameter \A_WIDTH 1
90408     parameter \B_SIGNED 0
90409     parameter \B_WIDTH 1
90410     parameter \Y_WIDTH 1
90411     connect \A \main_sdmem2block_converter_sink_last
90412     connect \B \main_sdmem2block_converter_last
90413     connect \Y $and$ls180.v:5602$1015_Y
90414   end
90415   attribute \src "ls180.v:5603.49-5603.122"
90416   cell $and $and$ls180.v:5603$1016
90417     parameter \A_SIGNED 0
90418     parameter \A_WIDTH 1
90419     parameter \B_SIGNED 0
90420     parameter \B_WIDTH 1
90421     parameter \Y_WIDTH 1
90422     connect \A \main_sdmem2block_converter_last
90423     connect \B \main_sdmem2block_converter_source_ready
90424     connect \Y $and$ls180.v:5603$1016_Y
90425   end
90426   attribute \src "ls180.v:5643.43-5643.152"
90427   cell $and $and$ls180.v:5643$1021
90428     parameter \A_SIGNED 0
90429     parameter \A_WIDTH 1
90430     parameter \B_SIGNED 0
90431     parameter \B_WIDTH 1
90432     parameter \Y_WIDTH 1
90433     connect \A \main_sdmem2block_fifo_syncfifo_we
90434     connect \B $or$ls180.v:5643$1020_Y
90435     connect \Y $and$ls180.v:5643$1021_Y
90436   end
90437   attribute \src "ls180.v:5644.41-5644.116"
90438   cell $and $and$ls180.v:5644$1022
90439     parameter \A_SIGNED 0
90440     parameter \A_WIDTH 1
90441     parameter \B_SIGNED 0
90442     parameter \B_WIDTH 1
90443     parameter \Y_WIDTH 1
90444     connect \A \main_sdmem2block_fifo_syncfifo_readable
90445     connect \B \main_sdmem2block_fifo_syncfifo_re
90446     connect \Y $and$ls180.v:5644$1022_Y
90447   end
90448   attribute \src "ls180.v:5676.9-5676.76"
90449   cell $and $and$ls180.v:5676$1026
90450     parameter \A_SIGNED 0
90451     parameter \A_WIDTH 1
90452     parameter \B_SIGNED 0
90453     parameter \B_WIDTH 1
90454     parameter \Y_WIDTH 1
90455     connect \A \builder_libresocsim_wishbone_cyc
90456     connect \B \builder_libresocsim_wishbone_stb
90457     connect \Y $and$ls180.v:5676$1026_Y
90458   end
90459   attribute \src "ls180.v:5679.44-5679.120"
90460   cell $and $and$ls180.v:5679$1028
90461     parameter \A_SIGNED 0
90462     parameter \A_WIDTH 1
90463     parameter \B_SIGNED 0
90464     parameter \B_WIDTH 1
90465     parameter \Y_WIDTH 1
90466     connect \A \builder_libresocsim_wishbone_we
90467     connect \B $ne$ls180.v:5679$1027_Y
90468     connect \Y $and$ls180.v:5679$1028_Y
90469   end
90470   attribute \src "ls180.v:5699.63-5699.107"
90471   cell $and $and$ls180.v:5699$1030
90472     parameter \A_SIGNED 0
90473     parameter \A_WIDTH 1
90474     parameter \B_SIGNED 0
90475     parameter \B_WIDTH 1
90476     parameter \Y_WIDTH 1
90477     connect \A \builder_shared_ack
90478     connect \B $eq$ls180.v:5699$1029_Y
90479     connect \Y $and$ls180.v:5699$1030_Y
90480   end
90481   attribute \src "ls180.v:5700.63-5700.107"
90482   cell $and $and$ls180.v:5700$1032
90483     parameter \A_SIGNED 0
90484     parameter \A_WIDTH 1
90485     parameter \B_SIGNED 0
90486     parameter \B_WIDTH 1
90487     parameter \Y_WIDTH 1
90488     connect \A \builder_shared_ack
90489     connect \B $eq$ls180.v:5700$1031_Y
90490     connect \Y $and$ls180.v:5700$1032_Y
90491   end
90492   attribute \src "ls180.v:5701.63-5701.107"
90493   cell $and $and$ls180.v:5701$1034
90494     parameter \A_SIGNED 0
90495     parameter \A_WIDTH 1
90496     parameter \B_SIGNED 0
90497     parameter \B_WIDTH 1
90498     parameter \Y_WIDTH 1
90499     connect \A \builder_shared_ack
90500     connect \B $eq$ls180.v:5701$1033_Y
90501     connect \Y $and$ls180.v:5701$1034_Y
90502   end
90503   attribute \src "ls180.v:5702.35-5702.79"
90504   cell $and $and$ls180.v:5702$1036
90505     parameter \A_SIGNED 0
90506     parameter \A_WIDTH 1
90507     parameter \B_SIGNED 0
90508     parameter \B_WIDTH 1
90509     parameter \Y_WIDTH 1
90510     connect \A \builder_shared_ack
90511     connect \B $eq$ls180.v:5702$1035_Y
90512     connect \Y $and$ls180.v:5702$1036_Y
90513   end
90514   attribute \src "ls180.v:5703.35-5703.79"
90515   cell $and $and$ls180.v:5703$1038
90516     parameter \A_SIGNED 0
90517     parameter \A_WIDTH 1
90518     parameter \B_SIGNED 0
90519     parameter \B_WIDTH 1
90520     parameter \Y_WIDTH 1
90521     connect \A \builder_shared_ack
90522     connect \B $eq$ls180.v:5703$1037_Y
90523     connect \Y $and$ls180.v:5703$1038_Y
90524   end
90525   attribute \src "ls180.v:5704.63-5704.107"
90526   cell $and $and$ls180.v:5704$1040
90527     parameter \A_SIGNED 0
90528     parameter \A_WIDTH 1
90529     parameter \B_SIGNED 0
90530     parameter \B_WIDTH 1
90531     parameter \Y_WIDTH 1
90532     connect \A \builder_shared_err
90533     connect \B $eq$ls180.v:5704$1039_Y
90534     connect \Y $and$ls180.v:5704$1040_Y
90535   end
90536   attribute \src "ls180.v:5705.63-5705.107"
90537   cell $and $and$ls180.v:5705$1042
90538     parameter \A_SIGNED 0
90539     parameter \A_WIDTH 1
90540     parameter \B_SIGNED 0
90541     parameter \B_WIDTH 1
90542     parameter \Y_WIDTH 1
90543     connect \A \builder_shared_err
90544     connect \B $eq$ls180.v:5705$1041_Y
90545     connect \Y $and$ls180.v:5705$1042_Y
90546   end
90547   attribute \src "ls180.v:5706.63-5706.107"
90548   cell $and $and$ls180.v:5706$1044
90549     parameter \A_SIGNED 0
90550     parameter \A_WIDTH 1
90551     parameter \B_SIGNED 0
90552     parameter \B_WIDTH 1
90553     parameter \Y_WIDTH 1
90554     connect \A \builder_shared_err
90555     connect \B $eq$ls180.v:5706$1043_Y
90556     connect \Y $and$ls180.v:5706$1044_Y
90557   end
90558   attribute \src "ls180.v:5707.35-5707.79"
90559   cell $and $and$ls180.v:5707$1046
90560     parameter \A_SIGNED 0
90561     parameter \A_WIDTH 1
90562     parameter \B_SIGNED 0
90563     parameter \B_WIDTH 1
90564     parameter \Y_WIDTH 1
90565     connect \A \builder_shared_err
90566     connect \B $eq$ls180.v:5707$1045_Y
90567     connect \Y $and$ls180.v:5707$1046_Y
90568   end
90569   attribute \src "ls180.v:5708.35-5708.79"
90570   cell $and $and$ls180.v:5708$1048
90571     parameter \A_SIGNED 0
90572     parameter \A_WIDTH 1
90573     parameter \B_SIGNED 0
90574     parameter \B_WIDTH 1
90575     parameter \Y_WIDTH 1
90576     connect \A \builder_shared_err
90577     connect \B $eq$ls180.v:5708$1047_Y
90578     connect \Y $and$ls180.v:5708$1048_Y
90579   end
90580   attribute \src "ls180.v:5753.40-5753.81"
90581   cell $and $and$ls180.v:5753$1055
90582     parameter \A_SIGNED 0
90583     parameter \A_WIDTH 1
90584     parameter \B_SIGNED 0
90585     parameter \B_WIDTH 1
90586     parameter \Y_WIDTH 1
90587     connect \A \builder_shared_cyc
90588     connect \B \builder_slave_sel [0]
90589     connect \Y $and$ls180.v:5753$1055_Y
90590   end
90591   attribute \src "ls180.v:5754.50-5754.91"
90592   cell $and $and$ls180.v:5754$1056
90593     parameter \A_SIGNED 0
90594     parameter \A_WIDTH 1
90595     parameter \B_SIGNED 0
90596     parameter \B_WIDTH 1
90597     parameter \Y_WIDTH 1
90598     connect \A \builder_shared_cyc
90599     connect \B \builder_slave_sel [1]
90600     connect \Y $and$ls180.v:5754$1056_Y
90601   end
90602   attribute \src "ls180.v:5755.50-5755.91"
90603   cell $and $and$ls180.v:5755$1057
90604     parameter \A_SIGNED 0
90605     parameter \A_WIDTH 1
90606     parameter \B_SIGNED 0
90607     parameter \B_WIDTH 1
90608     parameter \Y_WIDTH 1
90609     connect \A \builder_shared_cyc
90610     connect \B \builder_slave_sel [2]
90611     connect \Y $and$ls180.v:5755$1057_Y
90612   end
90613   attribute \src "ls180.v:5756.29-5756.70"
90614   cell $and $and$ls180.v:5756$1058
90615     parameter \A_SIGNED 0
90616     parameter \A_WIDTH 1
90617     parameter \B_SIGNED 0
90618     parameter \B_WIDTH 1
90619     parameter \Y_WIDTH 1
90620     connect \A \builder_shared_cyc
90621     connect \B \builder_slave_sel [3]
90622     connect \Y $and$ls180.v:5756$1058_Y
90623   end
90624   attribute \src "ls180.v:5757.44-5757.85"
90625   cell $and $and$ls180.v:5757$1059
90626     parameter \A_SIGNED 0
90627     parameter \A_WIDTH 1
90628     parameter \B_SIGNED 0
90629     parameter \B_WIDTH 1
90630     parameter \Y_WIDTH 1
90631     connect \A \builder_shared_cyc
90632     connect \B \builder_slave_sel [4]
90633     connect \Y $and$ls180.v:5757$1059_Y
90634   end
90635   attribute \src "ls180.v:5759.25-5759.64"
90636   cell $and $and$ls180.v:5759$1064
90637     parameter \A_SIGNED 0
90638     parameter \A_WIDTH 1
90639     parameter \B_SIGNED 0
90640     parameter \B_WIDTH 1
90641     parameter \Y_WIDTH 1
90642     connect \A \builder_shared_stb
90643     connect \B \builder_shared_cyc
90644     connect \Y $and$ls180.v:5759$1064_Y
90645   end
90646   attribute \src "ls180.v:5759.24-5759.89"
90647   cell $and $and$ls180.v:5759$1066
90648     parameter \A_SIGNED 0
90649     parameter \A_WIDTH 1
90650     parameter \B_SIGNED 0
90651     parameter \B_WIDTH 1
90652     parameter \Y_WIDTH 1
90653     connect \A $and$ls180.v:5759$1064_Y
90654     connect \B $not$ls180.v:5759$1065_Y
90655     connect \Y $and$ls180.v:5759$1066_Y
90656   end
90657   attribute \src "ls180.v:5765.31-5765.92"
90658   cell $and $and$ls180.v:5765$1072
90659     parameter \A_SIGNED 0
90660     parameter \A_WIDTH 32
90661     parameter \B_SIGNED 0
90662     parameter \B_WIDTH 32
90663     parameter \Y_WIDTH 32
90664     connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] }
90665     connect \B \main_libresocsim_ram_bus_dat_r
90666     connect \Y $and$ls180.v:5765$1072_Y
90667   end
90668   attribute \src "ls180.v:5765.97-5765.168"
90669   cell $and $and$ls180.v:5765$1073
90670     parameter \A_SIGNED 0
90671     parameter \A_WIDTH 32
90672     parameter \B_SIGNED 0
90673     parameter \B_WIDTH 32
90674     parameter \Y_WIDTH 32
90675     connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] }
90676     connect \B \main_libresocsim_libresoc_xics_icp_dat_r
90677     connect \Y $and$ls180.v:5765$1073_Y
90678   end
90679   attribute \src "ls180.v:5765.174-5765.245"
90680   cell $and $and$ls180.v:5765$1075
90681     parameter \A_SIGNED 0
90682     parameter \A_WIDTH 32
90683     parameter \B_SIGNED 0
90684     parameter \B_WIDTH 32
90685     parameter \Y_WIDTH 32
90686     connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] }
90687     connect \B \main_libresocsim_libresoc_xics_ics_dat_r
90688     connect \Y $and$ls180.v:5765$1075_Y
90689   end
90690   attribute \src "ls180.v:5765.251-5765.301"
90691   cell $and $and$ls180.v:5765$1077
90692     parameter \A_SIGNED 0
90693     parameter \A_WIDTH 32
90694     parameter \B_SIGNED 0
90695     parameter \B_WIDTH 32
90696     parameter \Y_WIDTH 32
90697     connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] }
90698     connect \B \main_wb_sdram_dat_r
90699     connect \Y $and$ls180.v:5765$1077_Y
90700   end
90701   attribute \src "ls180.v:5765.307-5765.372"
90702   cell $and $and$ls180.v:5765$1079
90703     parameter \A_SIGNED 0
90704     parameter \A_WIDTH 32
90705     parameter \B_SIGNED 0
90706     parameter \B_WIDTH 32
90707     parameter \Y_WIDTH 32
90708     connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] }
90709     connect \B \builder_libresocsim_wishbone_dat_r
90710     connect \Y $and$ls180.v:5765$1079_Y
90711   end
90712   attribute \src "ls180.v:5775.39-5775.92"
90713   cell $and $and$ls180.v:5775$1083
90714     parameter \A_SIGNED 0
90715     parameter \A_WIDTH 1
90716     parameter \B_SIGNED 0
90717     parameter \B_WIDTH 1
90718     parameter \Y_WIDTH 1
90719     connect \A \builder_csrbank0_sel
90720     connect \B \builder_interface0_bank_bus_we
90721     connect \Y $and$ls180.v:5775$1083_Y
90722   end
90723   attribute \src "ls180.v:5775.38-5775.142"
90724   cell $and $and$ls180.v:5775$1085
90725     parameter \A_SIGNED 0
90726     parameter \A_WIDTH 1
90727     parameter \B_SIGNED 0
90728     parameter \B_WIDTH 1
90729     parameter \Y_WIDTH 1
90730     connect \A $and$ls180.v:5775$1083_Y
90731     connect \B $eq$ls180.v:5775$1084_Y
90732     connect \Y $and$ls180.v:5775$1085_Y
90733   end
90734   attribute \src "ls180.v:5776.39-5776.95"
90735   cell $and $and$ls180.v:5776$1087
90736     parameter \A_SIGNED 0
90737     parameter \A_WIDTH 1
90738     parameter \B_SIGNED 0
90739     parameter \B_WIDTH 1
90740     parameter \Y_WIDTH 1
90741     connect \A \builder_csrbank0_sel
90742     connect \B $not$ls180.v:5776$1086_Y
90743     connect \Y $and$ls180.v:5776$1087_Y
90744   end
90745   attribute \src "ls180.v:5776.38-5776.145"
90746   cell $and $and$ls180.v:5776$1089
90747     parameter \A_SIGNED 0
90748     parameter \A_WIDTH 1
90749     parameter \B_SIGNED 0
90750     parameter \B_WIDTH 1
90751     parameter \Y_WIDTH 1
90752     connect \A $and$ls180.v:5776$1087_Y
90753     connect \B $eq$ls180.v:5776$1088_Y
90754     connect \Y $and$ls180.v:5776$1089_Y
90755   end
90756   attribute \src "ls180.v:5778.41-5778.94"
90757   cell $and $and$ls180.v:5778$1090
90758     parameter \A_SIGNED 0
90759     parameter \A_WIDTH 1
90760     parameter \B_SIGNED 0
90761     parameter \B_WIDTH 1
90762     parameter \Y_WIDTH 1
90763     connect \A \builder_csrbank0_sel
90764     connect \B \builder_interface0_bank_bus_we
90765     connect \Y $and$ls180.v:5778$1090_Y
90766   end
90767   attribute \src "ls180.v:5778.40-5778.144"
90768   cell $and $and$ls180.v:5778$1092
90769     parameter \A_SIGNED 0
90770     parameter \A_WIDTH 1
90771     parameter \B_SIGNED 0
90772     parameter \B_WIDTH 1
90773     parameter \Y_WIDTH 1
90774     connect \A $and$ls180.v:5778$1090_Y
90775     connect \B $eq$ls180.v:5778$1091_Y
90776     connect \Y $and$ls180.v:5778$1092_Y
90777   end
90778   attribute \src "ls180.v:5779.41-5779.97"
90779   cell $and $and$ls180.v:5779$1094
90780     parameter \A_SIGNED 0
90781     parameter \A_WIDTH 1
90782     parameter \B_SIGNED 0
90783     parameter \B_WIDTH 1
90784     parameter \Y_WIDTH 1
90785     connect \A \builder_csrbank0_sel
90786     connect \B $not$ls180.v:5779$1093_Y
90787     connect \Y $and$ls180.v:5779$1094_Y
90788   end
90789   attribute \src "ls180.v:5779.40-5779.147"
90790   cell $and $and$ls180.v:5779$1096
90791     parameter \A_SIGNED 0
90792     parameter \A_WIDTH 1
90793     parameter \B_SIGNED 0
90794     parameter \B_WIDTH 1
90795     parameter \Y_WIDTH 1
90796     connect \A $and$ls180.v:5779$1094_Y
90797     connect \B $eq$ls180.v:5779$1095_Y
90798     connect \Y $and$ls180.v:5779$1096_Y
90799   end
90800   attribute \src "ls180.v:5781.41-5781.94"
90801   cell $and $and$ls180.v:5781$1097
90802     parameter \A_SIGNED 0
90803     parameter \A_WIDTH 1
90804     parameter \B_SIGNED 0
90805     parameter \B_WIDTH 1
90806     parameter \Y_WIDTH 1
90807     connect \A \builder_csrbank0_sel
90808     connect \B \builder_interface0_bank_bus_we
90809     connect \Y $and$ls180.v:5781$1097_Y
90810   end
90811   attribute \src "ls180.v:5781.40-5781.144"
90812   cell $and $and$ls180.v:5781$1099
90813     parameter \A_SIGNED 0
90814     parameter \A_WIDTH 1
90815     parameter \B_SIGNED 0
90816     parameter \B_WIDTH 1
90817     parameter \Y_WIDTH 1
90818     connect \A $and$ls180.v:5781$1097_Y
90819     connect \B $eq$ls180.v:5781$1098_Y
90820     connect \Y $and$ls180.v:5781$1099_Y
90821   end
90822   attribute \src "ls180.v:5782.41-5782.97"
90823   cell $and $and$ls180.v:5782$1101
90824     parameter \A_SIGNED 0
90825     parameter \A_WIDTH 1
90826     parameter \B_SIGNED 0
90827     parameter \B_WIDTH 1
90828     parameter \Y_WIDTH 1
90829     connect \A \builder_csrbank0_sel
90830     connect \B $not$ls180.v:5782$1100_Y
90831     connect \Y $and$ls180.v:5782$1101_Y
90832   end
90833   attribute \src "ls180.v:5782.40-5782.147"
90834   cell $and $and$ls180.v:5782$1103
90835     parameter \A_SIGNED 0
90836     parameter \A_WIDTH 1
90837     parameter \B_SIGNED 0
90838     parameter \B_WIDTH 1
90839     parameter \Y_WIDTH 1
90840     connect \A $and$ls180.v:5782$1101_Y
90841     connect \B $eq$ls180.v:5782$1102_Y
90842     connect \Y $and$ls180.v:5782$1103_Y
90843   end
90844   attribute \src "ls180.v:5784.41-5784.94"
90845   cell $and $and$ls180.v:5784$1104
90846     parameter \A_SIGNED 0
90847     parameter \A_WIDTH 1
90848     parameter \B_SIGNED 0
90849     parameter \B_WIDTH 1
90850     parameter \Y_WIDTH 1
90851     connect \A \builder_csrbank0_sel
90852     connect \B \builder_interface0_bank_bus_we
90853     connect \Y $and$ls180.v:5784$1104_Y
90854   end
90855   attribute \src "ls180.v:5784.40-5784.144"
90856   cell $and $and$ls180.v:5784$1106
90857     parameter \A_SIGNED 0
90858     parameter \A_WIDTH 1
90859     parameter \B_SIGNED 0
90860     parameter \B_WIDTH 1
90861     parameter \Y_WIDTH 1
90862     connect \A $and$ls180.v:5784$1104_Y
90863     connect \B $eq$ls180.v:5784$1105_Y
90864     connect \Y $and$ls180.v:5784$1106_Y
90865   end
90866   attribute \src "ls180.v:5785.41-5785.97"
90867   cell $and $and$ls180.v:5785$1108
90868     parameter \A_SIGNED 0
90869     parameter \A_WIDTH 1
90870     parameter \B_SIGNED 0
90871     parameter \B_WIDTH 1
90872     parameter \Y_WIDTH 1
90873     connect \A \builder_csrbank0_sel
90874     connect \B $not$ls180.v:5785$1107_Y
90875     connect \Y $and$ls180.v:5785$1108_Y
90876   end
90877   attribute \src "ls180.v:5785.40-5785.147"
90878   cell $and $and$ls180.v:5785$1110
90879     parameter \A_SIGNED 0
90880     parameter \A_WIDTH 1
90881     parameter \B_SIGNED 0
90882     parameter \B_WIDTH 1
90883     parameter \Y_WIDTH 1
90884     connect \A $and$ls180.v:5785$1108_Y
90885     connect \B $eq$ls180.v:5785$1109_Y
90886     connect \Y $and$ls180.v:5785$1110_Y
90887   end
90888   attribute \src "ls180.v:5787.41-5787.94"
90889   cell $and $and$ls180.v:5787$1111
90890     parameter \A_SIGNED 0
90891     parameter \A_WIDTH 1
90892     parameter \B_SIGNED 0
90893     parameter \B_WIDTH 1
90894     parameter \Y_WIDTH 1
90895     connect \A \builder_csrbank0_sel
90896     connect \B \builder_interface0_bank_bus_we
90897     connect \Y $and$ls180.v:5787$1111_Y
90898   end
90899   attribute \src "ls180.v:5787.40-5787.144"
90900   cell $and $and$ls180.v:5787$1113
90901     parameter \A_SIGNED 0
90902     parameter \A_WIDTH 1
90903     parameter \B_SIGNED 0
90904     parameter \B_WIDTH 1
90905     parameter \Y_WIDTH 1
90906     connect \A $and$ls180.v:5787$1111_Y
90907     connect \B $eq$ls180.v:5787$1112_Y
90908     connect \Y $and$ls180.v:5787$1113_Y
90909   end
90910   attribute \src "ls180.v:5788.41-5788.97"
90911   cell $and $and$ls180.v:5788$1115
90912     parameter \A_SIGNED 0
90913     parameter \A_WIDTH 1
90914     parameter \B_SIGNED 0
90915     parameter \B_WIDTH 1
90916     parameter \Y_WIDTH 1
90917     connect \A \builder_csrbank0_sel
90918     connect \B $not$ls180.v:5788$1114_Y
90919     connect \Y $and$ls180.v:5788$1115_Y
90920   end
90921   attribute \src "ls180.v:5788.40-5788.147"
90922   cell $and $and$ls180.v:5788$1117
90923     parameter \A_SIGNED 0
90924     parameter \A_WIDTH 1
90925     parameter \B_SIGNED 0
90926     parameter \B_WIDTH 1
90927     parameter \Y_WIDTH 1
90928     connect \A $and$ls180.v:5788$1115_Y
90929     connect \B $eq$ls180.v:5788$1116_Y
90930     connect \Y $and$ls180.v:5788$1117_Y
90931   end
90932   attribute \src "ls180.v:5790.44-5790.97"
90933   cell $and $and$ls180.v:5790$1118
90934     parameter \A_SIGNED 0
90935     parameter \A_WIDTH 1
90936     parameter \B_SIGNED 0
90937     parameter \B_WIDTH 1
90938     parameter \Y_WIDTH 1
90939     connect \A \builder_csrbank0_sel
90940     connect \B \builder_interface0_bank_bus_we
90941     connect \Y $and$ls180.v:5790$1118_Y
90942   end
90943   attribute \src "ls180.v:5790.43-5790.147"
90944   cell $and $and$ls180.v:5790$1120
90945     parameter \A_SIGNED 0
90946     parameter \A_WIDTH 1
90947     parameter \B_SIGNED 0
90948     parameter \B_WIDTH 1
90949     parameter \Y_WIDTH 1
90950     connect \A $and$ls180.v:5790$1118_Y
90951     connect \B $eq$ls180.v:5790$1119_Y
90952     connect \Y $and$ls180.v:5790$1120_Y
90953   end
90954   attribute \src "ls180.v:5791.44-5791.100"
90955   cell $and $and$ls180.v:5791$1122
90956     parameter \A_SIGNED 0
90957     parameter \A_WIDTH 1
90958     parameter \B_SIGNED 0
90959     parameter \B_WIDTH 1
90960     parameter \Y_WIDTH 1
90961     connect \A \builder_csrbank0_sel
90962     connect \B $not$ls180.v:5791$1121_Y
90963     connect \Y $and$ls180.v:5791$1122_Y
90964   end
90965   attribute \src "ls180.v:5791.43-5791.150"
90966   cell $and $and$ls180.v:5791$1124
90967     parameter \A_SIGNED 0
90968     parameter \A_WIDTH 1
90969     parameter \B_SIGNED 0
90970     parameter \B_WIDTH 1
90971     parameter \Y_WIDTH 1
90972     connect \A $and$ls180.v:5791$1122_Y
90973     connect \B $eq$ls180.v:5791$1123_Y
90974     connect \Y $and$ls180.v:5791$1124_Y
90975   end
90976   attribute \src "ls180.v:5793.44-5793.97"
90977   cell $and $and$ls180.v:5793$1125
90978     parameter \A_SIGNED 0
90979     parameter \A_WIDTH 1
90980     parameter \B_SIGNED 0
90981     parameter \B_WIDTH 1
90982     parameter \Y_WIDTH 1
90983     connect \A \builder_csrbank0_sel
90984     connect \B \builder_interface0_bank_bus_we
90985     connect \Y $and$ls180.v:5793$1125_Y
90986   end
90987   attribute \src "ls180.v:5793.43-5793.147"
90988   cell $and $and$ls180.v:5793$1127
90989     parameter \A_SIGNED 0
90990     parameter \A_WIDTH 1
90991     parameter \B_SIGNED 0
90992     parameter \B_WIDTH 1
90993     parameter \Y_WIDTH 1
90994     connect \A $and$ls180.v:5793$1125_Y
90995     connect \B $eq$ls180.v:5793$1126_Y
90996     connect \Y $and$ls180.v:5793$1127_Y
90997   end
90998   attribute \src "ls180.v:5794.44-5794.100"
90999   cell $and $and$ls180.v:5794$1129
91000     parameter \A_SIGNED 0
91001     parameter \A_WIDTH 1
91002     parameter \B_SIGNED 0
91003     parameter \B_WIDTH 1
91004     parameter \Y_WIDTH 1
91005     connect \A \builder_csrbank0_sel
91006     connect \B $not$ls180.v:5794$1128_Y
91007     connect \Y $and$ls180.v:5794$1129_Y
91008   end
91009   attribute \src "ls180.v:5794.43-5794.150"
91010   cell $and $and$ls180.v:5794$1131
91011     parameter \A_SIGNED 0
91012     parameter \A_WIDTH 1
91013     parameter \B_SIGNED 0
91014     parameter \B_WIDTH 1
91015     parameter \Y_WIDTH 1
91016     connect \A $and$ls180.v:5794$1129_Y
91017     connect \B $eq$ls180.v:5794$1130_Y
91018     connect \Y $and$ls180.v:5794$1131_Y
91019   end
91020   attribute \src "ls180.v:5796.44-5796.97"
91021   cell $and $and$ls180.v:5796$1132
91022     parameter \A_SIGNED 0
91023     parameter \A_WIDTH 1
91024     parameter \B_SIGNED 0
91025     parameter \B_WIDTH 1
91026     parameter \Y_WIDTH 1
91027     connect \A \builder_csrbank0_sel
91028     connect \B \builder_interface0_bank_bus_we
91029     connect \Y $and$ls180.v:5796$1132_Y
91030   end
91031   attribute \src "ls180.v:5796.43-5796.147"
91032   cell $and $and$ls180.v:5796$1134
91033     parameter \A_SIGNED 0
91034     parameter \A_WIDTH 1
91035     parameter \B_SIGNED 0
91036     parameter \B_WIDTH 1
91037     parameter \Y_WIDTH 1
91038     connect \A $and$ls180.v:5796$1132_Y
91039     connect \B $eq$ls180.v:5796$1133_Y
91040     connect \Y $and$ls180.v:5796$1134_Y
91041   end
91042   attribute \src "ls180.v:5797.44-5797.100"
91043   cell $and $and$ls180.v:5797$1136
91044     parameter \A_SIGNED 0
91045     parameter \A_WIDTH 1
91046     parameter \B_SIGNED 0
91047     parameter \B_WIDTH 1
91048     parameter \Y_WIDTH 1
91049     connect \A \builder_csrbank0_sel
91050     connect \B $not$ls180.v:5797$1135_Y
91051     connect \Y $and$ls180.v:5797$1136_Y
91052   end
91053   attribute \src "ls180.v:5797.43-5797.150"
91054   cell $and $and$ls180.v:5797$1138
91055     parameter \A_SIGNED 0
91056     parameter \A_WIDTH 1
91057     parameter \B_SIGNED 0
91058     parameter \B_WIDTH 1
91059     parameter \Y_WIDTH 1
91060     connect \A $and$ls180.v:5797$1136_Y
91061     connect \B $eq$ls180.v:5797$1137_Y
91062     connect \Y $and$ls180.v:5797$1138_Y
91063   end
91064   attribute \src "ls180.v:5799.44-5799.97"
91065   cell $and $and$ls180.v:5799$1139
91066     parameter \A_SIGNED 0
91067     parameter \A_WIDTH 1
91068     parameter \B_SIGNED 0
91069     parameter \B_WIDTH 1
91070     parameter \Y_WIDTH 1
91071     connect \A \builder_csrbank0_sel
91072     connect \B \builder_interface0_bank_bus_we
91073     connect \Y $and$ls180.v:5799$1139_Y
91074   end
91075   attribute \src "ls180.v:5799.43-5799.147"
91076   cell $and $and$ls180.v:5799$1141
91077     parameter \A_SIGNED 0
91078     parameter \A_WIDTH 1
91079     parameter \B_SIGNED 0
91080     parameter \B_WIDTH 1
91081     parameter \Y_WIDTH 1
91082     connect \A $and$ls180.v:5799$1139_Y
91083     connect \B $eq$ls180.v:5799$1140_Y
91084     connect \Y $and$ls180.v:5799$1141_Y
91085   end
91086   attribute \src "ls180.v:5800.44-5800.100"
91087   cell $and $and$ls180.v:5800$1143
91088     parameter \A_SIGNED 0
91089     parameter \A_WIDTH 1
91090     parameter \B_SIGNED 0
91091     parameter \B_WIDTH 1
91092     parameter \Y_WIDTH 1
91093     connect \A \builder_csrbank0_sel
91094     connect \B $not$ls180.v:5800$1142_Y
91095     connect \Y $and$ls180.v:5800$1143_Y
91096   end
91097   attribute \src "ls180.v:5800.43-5800.150"
91098   cell $and $and$ls180.v:5800$1145
91099     parameter \A_SIGNED 0
91100     parameter \A_WIDTH 1
91101     parameter \B_SIGNED 0
91102     parameter \B_WIDTH 1
91103     parameter \Y_WIDTH 1
91104     connect \A $and$ls180.v:5800$1143_Y
91105     connect \B $eq$ls180.v:5800$1144_Y
91106     connect \Y $and$ls180.v:5800$1145_Y
91107   end
91108   attribute \src "ls180.v:5813.36-5813.89"
91109   cell $and $and$ls180.v:5813$1147
91110     parameter \A_SIGNED 0
91111     parameter \A_WIDTH 1
91112     parameter \B_SIGNED 0
91113     parameter \B_WIDTH 1
91114     parameter \Y_WIDTH 1
91115     connect \A \builder_csrbank1_sel
91116     connect \B \builder_interface1_bank_bus_we
91117     connect \Y $and$ls180.v:5813$1147_Y
91118   end
91119   attribute \src "ls180.v:5813.35-5813.139"
91120   cell $and $and$ls180.v:5813$1149
91121     parameter \A_SIGNED 0
91122     parameter \A_WIDTH 1
91123     parameter \B_SIGNED 0
91124     parameter \B_WIDTH 1
91125     parameter \Y_WIDTH 1
91126     connect \A $and$ls180.v:5813$1147_Y
91127     connect \B $eq$ls180.v:5813$1148_Y
91128     connect \Y $and$ls180.v:5813$1149_Y
91129   end
91130   attribute \src "ls180.v:5814.36-5814.92"
91131   cell $and $and$ls180.v:5814$1151
91132     parameter \A_SIGNED 0
91133     parameter \A_WIDTH 1
91134     parameter \B_SIGNED 0
91135     parameter \B_WIDTH 1
91136     parameter \Y_WIDTH 1
91137     connect \A \builder_csrbank1_sel
91138     connect \B $not$ls180.v:5814$1150_Y
91139     connect \Y $and$ls180.v:5814$1151_Y
91140   end
91141   attribute \src "ls180.v:5814.35-5814.142"
91142   cell $and $and$ls180.v:5814$1153
91143     parameter \A_SIGNED 0
91144     parameter \A_WIDTH 1
91145     parameter \B_SIGNED 0
91146     parameter \B_WIDTH 1
91147     parameter \Y_WIDTH 1
91148     connect \A $and$ls180.v:5814$1151_Y
91149     connect \B $eq$ls180.v:5814$1152_Y
91150     connect \Y $and$ls180.v:5814$1153_Y
91151   end
91152   attribute \src "ls180.v:5816.36-5816.89"
91153   cell $and $and$ls180.v:5816$1154
91154     parameter \A_SIGNED 0
91155     parameter \A_WIDTH 1
91156     parameter \B_SIGNED 0
91157     parameter \B_WIDTH 1
91158     parameter \Y_WIDTH 1
91159     connect \A \builder_csrbank1_sel
91160     connect \B \builder_interface1_bank_bus_we
91161     connect \Y $and$ls180.v:5816$1154_Y
91162   end
91163   attribute \src "ls180.v:5816.35-5816.139"
91164   cell $and $and$ls180.v:5816$1156
91165     parameter \A_SIGNED 0
91166     parameter \A_WIDTH 1
91167     parameter \B_SIGNED 0
91168     parameter \B_WIDTH 1
91169     parameter \Y_WIDTH 1
91170     connect \A $and$ls180.v:5816$1154_Y
91171     connect \B $eq$ls180.v:5816$1155_Y
91172     connect \Y $and$ls180.v:5816$1156_Y
91173   end
91174   attribute \src "ls180.v:5817.36-5817.92"
91175   cell $and $and$ls180.v:5817$1158
91176     parameter \A_SIGNED 0
91177     parameter \A_WIDTH 1
91178     parameter \B_SIGNED 0
91179     parameter \B_WIDTH 1
91180     parameter \Y_WIDTH 1
91181     connect \A \builder_csrbank1_sel
91182     connect \B $not$ls180.v:5817$1157_Y
91183     connect \Y $and$ls180.v:5817$1158_Y
91184   end
91185   attribute \src "ls180.v:5817.35-5817.142"
91186   cell $and $and$ls180.v:5817$1160
91187     parameter \A_SIGNED 0
91188     parameter \A_WIDTH 1
91189     parameter \B_SIGNED 0
91190     parameter \B_WIDTH 1
91191     parameter \Y_WIDTH 1
91192     connect \A $and$ls180.v:5817$1158_Y
91193     connect \B $eq$ls180.v:5817$1159_Y
91194     connect \Y $and$ls180.v:5817$1160_Y
91195   end
91196   attribute \src "ls180.v:5819.36-5819.89"
91197   cell $and $and$ls180.v:5819$1161
91198     parameter \A_SIGNED 0
91199     parameter \A_WIDTH 1
91200     parameter \B_SIGNED 0
91201     parameter \B_WIDTH 1
91202     parameter \Y_WIDTH 1
91203     connect \A \builder_csrbank1_sel
91204     connect \B \builder_interface1_bank_bus_we
91205     connect \Y $and$ls180.v:5819$1161_Y
91206   end
91207   attribute \src "ls180.v:5819.35-5819.139"
91208   cell $and $and$ls180.v:5819$1163
91209     parameter \A_SIGNED 0
91210     parameter \A_WIDTH 1
91211     parameter \B_SIGNED 0
91212     parameter \B_WIDTH 1
91213     parameter \Y_WIDTH 1
91214     connect \A $and$ls180.v:5819$1161_Y
91215     connect \B $eq$ls180.v:5819$1162_Y
91216     connect \Y $and$ls180.v:5819$1163_Y
91217   end
91218   attribute \src "ls180.v:5820.36-5820.92"
91219   cell $and $and$ls180.v:5820$1165
91220     parameter \A_SIGNED 0
91221     parameter \A_WIDTH 1
91222     parameter \B_SIGNED 0
91223     parameter \B_WIDTH 1
91224     parameter \Y_WIDTH 1
91225     connect \A \builder_csrbank1_sel
91226     connect \B $not$ls180.v:5820$1164_Y
91227     connect \Y $and$ls180.v:5820$1165_Y
91228   end
91229   attribute \src "ls180.v:5820.35-5820.142"
91230   cell $and $and$ls180.v:5820$1167
91231     parameter \A_SIGNED 0
91232     parameter \A_WIDTH 1
91233     parameter \B_SIGNED 0
91234     parameter \B_WIDTH 1
91235     parameter \Y_WIDTH 1
91236     connect \A $and$ls180.v:5820$1165_Y
91237     connect \B $eq$ls180.v:5820$1166_Y
91238     connect \Y $and$ls180.v:5820$1167_Y
91239   end
91240   attribute \src "ls180.v:5822.36-5822.89"
91241   cell $and $and$ls180.v:5822$1168
91242     parameter \A_SIGNED 0
91243     parameter \A_WIDTH 1
91244     parameter \B_SIGNED 0
91245     parameter \B_WIDTH 1
91246     parameter \Y_WIDTH 1
91247     connect \A \builder_csrbank1_sel
91248     connect \B \builder_interface1_bank_bus_we
91249     connect \Y $and$ls180.v:5822$1168_Y
91250   end
91251   attribute \src "ls180.v:5822.35-5822.139"
91252   cell $and $and$ls180.v:5822$1170
91253     parameter \A_SIGNED 0
91254     parameter \A_WIDTH 1
91255     parameter \B_SIGNED 0
91256     parameter \B_WIDTH 1
91257     parameter \Y_WIDTH 1
91258     connect \A $and$ls180.v:5822$1168_Y
91259     connect \B $eq$ls180.v:5822$1169_Y
91260     connect \Y $and$ls180.v:5822$1170_Y
91261   end
91262   attribute \src "ls180.v:5823.36-5823.92"
91263   cell $and $and$ls180.v:5823$1172
91264     parameter \A_SIGNED 0
91265     parameter \A_WIDTH 1
91266     parameter \B_SIGNED 0
91267     parameter \B_WIDTH 1
91268     parameter \Y_WIDTH 1
91269     connect \A \builder_csrbank1_sel
91270     connect \B $not$ls180.v:5823$1171_Y
91271     connect \Y $and$ls180.v:5823$1172_Y
91272   end
91273   attribute \src "ls180.v:5823.35-5823.142"
91274   cell $and $and$ls180.v:5823$1174
91275     parameter \A_SIGNED 0
91276     parameter \A_WIDTH 1
91277     parameter \B_SIGNED 0
91278     parameter \B_WIDTH 1
91279     parameter \Y_WIDTH 1
91280     connect \A $and$ls180.v:5823$1172_Y
91281     connect \B $eq$ls180.v:5823$1173_Y
91282     connect \Y $and$ls180.v:5823$1174_Y
91283   end
91284   attribute \src "ls180.v:5825.37-5825.90"
91285   cell $and $and$ls180.v:5825$1175
91286     parameter \A_SIGNED 0
91287     parameter \A_WIDTH 1
91288     parameter \B_SIGNED 0
91289     parameter \B_WIDTH 1
91290     parameter \Y_WIDTH 1
91291     connect \A \builder_csrbank1_sel
91292     connect \B \builder_interface1_bank_bus_we
91293     connect \Y $and$ls180.v:5825$1175_Y
91294   end
91295   attribute \src "ls180.v:5825.36-5825.140"
91296   cell $and $and$ls180.v:5825$1177
91297     parameter \A_SIGNED 0
91298     parameter \A_WIDTH 1
91299     parameter \B_SIGNED 0
91300     parameter \B_WIDTH 1
91301     parameter \Y_WIDTH 1
91302     connect \A $and$ls180.v:5825$1175_Y
91303     connect \B $eq$ls180.v:5825$1176_Y
91304     connect \Y $and$ls180.v:5825$1177_Y
91305   end
91306   attribute \src "ls180.v:5826.37-5826.93"
91307   cell $and $and$ls180.v:5826$1179
91308     parameter \A_SIGNED 0
91309     parameter \A_WIDTH 1
91310     parameter \B_SIGNED 0
91311     parameter \B_WIDTH 1
91312     parameter \Y_WIDTH 1
91313     connect \A \builder_csrbank1_sel
91314     connect \B $not$ls180.v:5826$1178_Y
91315     connect \Y $and$ls180.v:5826$1179_Y
91316   end
91317   attribute \src "ls180.v:5826.36-5826.143"
91318   cell $and $and$ls180.v:5826$1181
91319     parameter \A_SIGNED 0
91320     parameter \A_WIDTH 1
91321     parameter \B_SIGNED 0
91322     parameter \B_WIDTH 1
91323     parameter \Y_WIDTH 1
91324     connect \A $and$ls180.v:5826$1179_Y
91325     connect \B $eq$ls180.v:5826$1180_Y
91326     connect \Y $and$ls180.v:5826$1181_Y
91327   end
91328   attribute \src "ls180.v:5828.37-5828.90"
91329   cell $and $and$ls180.v:5828$1182
91330     parameter \A_SIGNED 0
91331     parameter \A_WIDTH 1
91332     parameter \B_SIGNED 0
91333     parameter \B_WIDTH 1
91334     parameter \Y_WIDTH 1
91335     connect \A \builder_csrbank1_sel
91336     connect \B \builder_interface1_bank_bus_we
91337     connect \Y $and$ls180.v:5828$1182_Y
91338   end
91339   attribute \src "ls180.v:5828.36-5828.140"
91340   cell $and $and$ls180.v:5828$1184
91341     parameter \A_SIGNED 0
91342     parameter \A_WIDTH 1
91343     parameter \B_SIGNED 0
91344     parameter \B_WIDTH 1
91345     parameter \Y_WIDTH 1
91346     connect \A $and$ls180.v:5828$1182_Y
91347     connect \B $eq$ls180.v:5828$1183_Y
91348     connect \Y $and$ls180.v:5828$1184_Y
91349   end
91350   attribute \src "ls180.v:5829.37-5829.93"
91351   cell $and $and$ls180.v:5829$1186
91352     parameter \A_SIGNED 0
91353     parameter \A_WIDTH 1
91354     parameter \B_SIGNED 0
91355     parameter \B_WIDTH 1
91356     parameter \Y_WIDTH 1
91357     connect \A \builder_csrbank1_sel
91358     connect \B $not$ls180.v:5829$1185_Y
91359     connect \Y $and$ls180.v:5829$1186_Y
91360   end
91361   attribute \src "ls180.v:5829.36-5829.143"
91362   cell $and $and$ls180.v:5829$1188
91363     parameter \A_SIGNED 0
91364     parameter \A_WIDTH 1
91365     parameter \B_SIGNED 0
91366     parameter \B_WIDTH 1
91367     parameter \Y_WIDTH 1
91368     connect \A $and$ls180.v:5829$1186_Y
91369     connect \B $eq$ls180.v:5829$1187_Y
91370     connect \Y $and$ls180.v:5829$1188_Y
91371   end
91372   attribute \src "ls180.v:5839.35-5839.88"
91373   cell $and $and$ls180.v:5839$1190
91374     parameter \A_SIGNED 0
91375     parameter \A_WIDTH 1
91376     parameter \B_SIGNED 0
91377     parameter \B_WIDTH 1
91378     parameter \Y_WIDTH 1
91379     connect \A \builder_csrbank2_sel
91380     connect \B \builder_interface2_bank_bus_we
91381     connect \Y $and$ls180.v:5839$1190_Y
91382   end
91383   attribute \src "ls180.v:5839.34-5839.136"
91384   cell $and $and$ls180.v:5839$1192
91385     parameter \A_SIGNED 0
91386     parameter \A_WIDTH 1
91387     parameter \B_SIGNED 0
91388     parameter \B_WIDTH 1
91389     parameter \Y_WIDTH 1
91390     connect \A $and$ls180.v:5839$1190_Y
91391     connect \B $eq$ls180.v:5839$1191_Y
91392     connect \Y $and$ls180.v:5839$1192_Y
91393   end
91394   attribute \src "ls180.v:5840.35-5840.91"
91395   cell $and $and$ls180.v:5840$1194
91396     parameter \A_SIGNED 0
91397     parameter \A_WIDTH 1
91398     parameter \B_SIGNED 0
91399     parameter \B_WIDTH 1
91400     parameter \Y_WIDTH 1
91401     connect \A \builder_csrbank2_sel
91402     connect \B $not$ls180.v:5840$1193_Y
91403     connect \Y $and$ls180.v:5840$1194_Y
91404   end
91405   attribute \src "ls180.v:5840.34-5840.139"
91406   cell $and $and$ls180.v:5840$1196
91407     parameter \A_SIGNED 0
91408     parameter \A_WIDTH 1
91409     parameter \B_SIGNED 0
91410     parameter \B_WIDTH 1
91411     parameter \Y_WIDTH 1
91412     connect \A $and$ls180.v:5840$1194_Y
91413     connect \B $eq$ls180.v:5840$1195_Y
91414     connect \Y $and$ls180.v:5840$1196_Y
91415   end
91416   attribute \src "ls180.v:5842.34-5842.87"
91417   cell $and $and$ls180.v:5842$1197
91418     parameter \A_SIGNED 0
91419     parameter \A_WIDTH 1
91420     parameter \B_SIGNED 0
91421     parameter \B_WIDTH 1
91422     parameter \Y_WIDTH 1
91423     connect \A \builder_csrbank2_sel
91424     connect \B \builder_interface2_bank_bus_we
91425     connect \Y $and$ls180.v:5842$1197_Y
91426   end
91427   attribute \src "ls180.v:5842.33-5842.135"
91428   cell $and $and$ls180.v:5842$1199
91429     parameter \A_SIGNED 0
91430     parameter \A_WIDTH 1
91431     parameter \B_SIGNED 0
91432     parameter \B_WIDTH 1
91433     parameter \Y_WIDTH 1
91434     connect \A $and$ls180.v:5842$1197_Y
91435     connect \B $eq$ls180.v:5842$1198_Y
91436     connect \Y $and$ls180.v:5842$1199_Y
91437   end
91438   attribute \src "ls180.v:5843.34-5843.90"
91439   cell $and $and$ls180.v:5843$1201
91440     parameter \A_SIGNED 0
91441     parameter \A_WIDTH 1
91442     parameter \B_SIGNED 0
91443     parameter \B_WIDTH 1
91444     parameter \Y_WIDTH 1
91445     connect \A \builder_csrbank2_sel
91446     connect \B $not$ls180.v:5843$1200_Y
91447     connect \Y $and$ls180.v:5843$1201_Y
91448   end
91449   attribute \src "ls180.v:5843.33-5843.138"
91450   cell $and $and$ls180.v:5843$1203
91451     parameter \A_SIGNED 0
91452     parameter \A_WIDTH 1
91453     parameter \B_SIGNED 0
91454     parameter \B_WIDTH 1
91455     parameter \Y_WIDTH 1
91456     connect \A $and$ls180.v:5843$1201_Y
91457     connect \B $eq$ls180.v:5843$1202_Y
91458     connect \Y $and$ls180.v:5843$1203_Y
91459   end
91460   attribute \src "ls180.v:5853.40-5853.93"
91461   cell $and $and$ls180.v:5853$1205
91462     parameter \A_SIGNED 0
91463     parameter \A_WIDTH 1
91464     parameter \B_SIGNED 0
91465     parameter \B_WIDTH 1
91466     parameter \Y_WIDTH 1
91467     connect \A \builder_csrbank3_sel
91468     connect \B \builder_interface3_bank_bus_we
91469     connect \Y $and$ls180.v:5853$1205_Y
91470   end
91471   attribute \src "ls180.v:5853.39-5853.143"
91472   cell $and $and$ls180.v:5853$1207
91473     parameter \A_SIGNED 0
91474     parameter \A_WIDTH 1
91475     parameter \B_SIGNED 0
91476     parameter \B_WIDTH 1
91477     parameter \Y_WIDTH 1
91478     connect \A $and$ls180.v:5853$1205_Y
91479     connect \B $eq$ls180.v:5853$1206_Y
91480     connect \Y $and$ls180.v:5853$1207_Y
91481   end
91482   attribute \src "ls180.v:5854.40-5854.96"
91483   cell $and $and$ls180.v:5854$1209
91484     parameter \A_SIGNED 0
91485     parameter \A_WIDTH 1
91486     parameter \B_SIGNED 0
91487     parameter \B_WIDTH 1
91488     parameter \Y_WIDTH 1
91489     connect \A \builder_csrbank3_sel
91490     connect \B $not$ls180.v:5854$1208_Y
91491     connect \Y $and$ls180.v:5854$1209_Y
91492   end
91493   attribute \src "ls180.v:5854.39-5854.146"
91494   cell $and $and$ls180.v:5854$1211
91495     parameter \A_SIGNED 0
91496     parameter \A_WIDTH 1
91497     parameter \B_SIGNED 0
91498     parameter \B_WIDTH 1
91499     parameter \Y_WIDTH 1
91500     connect \A $and$ls180.v:5854$1209_Y
91501     connect \B $eq$ls180.v:5854$1210_Y
91502     connect \Y $and$ls180.v:5854$1211_Y
91503   end
91504   attribute \src "ls180.v:5856.39-5856.92"
91505   cell $and $and$ls180.v:5856$1212
91506     parameter \A_SIGNED 0
91507     parameter \A_WIDTH 1
91508     parameter \B_SIGNED 0
91509     parameter \B_WIDTH 1
91510     parameter \Y_WIDTH 1
91511     connect \A \builder_csrbank3_sel
91512     connect \B \builder_interface3_bank_bus_we
91513     connect \Y $and$ls180.v:5856$1212_Y
91514   end
91515   attribute \src "ls180.v:5856.38-5856.142"
91516   cell $and $and$ls180.v:5856$1214
91517     parameter \A_SIGNED 0
91518     parameter \A_WIDTH 1
91519     parameter \B_SIGNED 0
91520     parameter \B_WIDTH 1
91521     parameter \Y_WIDTH 1
91522     connect \A $and$ls180.v:5856$1212_Y
91523     connect \B $eq$ls180.v:5856$1213_Y
91524     connect \Y $and$ls180.v:5856$1214_Y
91525   end
91526   attribute \src "ls180.v:5857.39-5857.95"
91527   cell $and $and$ls180.v:5857$1216
91528     parameter \A_SIGNED 0
91529     parameter \A_WIDTH 1
91530     parameter \B_SIGNED 0
91531     parameter \B_WIDTH 1
91532     parameter \Y_WIDTH 1
91533     connect \A \builder_csrbank3_sel
91534     connect \B $not$ls180.v:5857$1215_Y
91535     connect \Y $and$ls180.v:5857$1216_Y
91536   end
91537   attribute \src "ls180.v:5857.38-5857.145"
91538   cell $and $and$ls180.v:5857$1218
91539     parameter \A_SIGNED 0
91540     parameter \A_WIDTH 1
91541     parameter \B_SIGNED 0
91542     parameter \B_WIDTH 1
91543     parameter \Y_WIDTH 1
91544     connect \A $and$ls180.v:5857$1216_Y
91545     connect \B $eq$ls180.v:5857$1217_Y
91546     connect \Y $and$ls180.v:5857$1218_Y
91547   end
91548   attribute \src "ls180.v:5859.39-5859.92"
91549   cell $and $and$ls180.v:5859$1219
91550     parameter \A_SIGNED 0
91551     parameter \A_WIDTH 1
91552     parameter \B_SIGNED 0
91553     parameter \B_WIDTH 1
91554     parameter \Y_WIDTH 1
91555     connect \A \builder_csrbank3_sel
91556     connect \B \builder_interface3_bank_bus_we
91557     connect \Y $and$ls180.v:5859$1219_Y
91558   end
91559   attribute \src "ls180.v:5859.38-5859.142"
91560   cell $and $and$ls180.v:5859$1221
91561     parameter \A_SIGNED 0
91562     parameter \A_WIDTH 1
91563     parameter \B_SIGNED 0
91564     parameter \B_WIDTH 1
91565     parameter \Y_WIDTH 1
91566     connect \A $and$ls180.v:5859$1219_Y
91567     connect \B $eq$ls180.v:5859$1220_Y
91568     connect \Y $and$ls180.v:5859$1221_Y
91569   end
91570   attribute \src "ls180.v:5860.39-5860.95"
91571   cell $and $and$ls180.v:5860$1223
91572     parameter \A_SIGNED 0
91573     parameter \A_WIDTH 1
91574     parameter \B_SIGNED 0
91575     parameter \B_WIDTH 1
91576     parameter \Y_WIDTH 1
91577     connect \A \builder_csrbank3_sel
91578     connect \B $not$ls180.v:5860$1222_Y
91579     connect \Y $and$ls180.v:5860$1223_Y
91580   end
91581   attribute \src "ls180.v:5860.38-5860.145"
91582   cell $and $and$ls180.v:5860$1225
91583     parameter \A_SIGNED 0
91584     parameter \A_WIDTH 1
91585     parameter \B_SIGNED 0
91586     parameter \B_WIDTH 1
91587     parameter \Y_WIDTH 1
91588     connect \A $and$ls180.v:5860$1223_Y
91589     connect \B $eq$ls180.v:5860$1224_Y
91590     connect \Y $and$ls180.v:5860$1225_Y
91591   end
91592   attribute \src "ls180.v:5862.39-5862.92"
91593   cell $and $and$ls180.v:5862$1226
91594     parameter \A_SIGNED 0
91595     parameter \A_WIDTH 1
91596     parameter \B_SIGNED 0
91597     parameter \B_WIDTH 1
91598     parameter \Y_WIDTH 1
91599     connect \A \builder_csrbank3_sel
91600     connect \B \builder_interface3_bank_bus_we
91601     connect \Y $and$ls180.v:5862$1226_Y
91602   end
91603   attribute \src "ls180.v:5862.38-5862.142"
91604   cell $and $and$ls180.v:5862$1228
91605     parameter \A_SIGNED 0
91606     parameter \A_WIDTH 1
91607     parameter \B_SIGNED 0
91608     parameter \B_WIDTH 1
91609     parameter \Y_WIDTH 1
91610     connect \A $and$ls180.v:5862$1226_Y
91611     connect \B $eq$ls180.v:5862$1227_Y
91612     connect \Y $and$ls180.v:5862$1228_Y
91613   end
91614   attribute \src "ls180.v:5863.39-5863.95"
91615   cell $and $and$ls180.v:5863$1230
91616     parameter \A_SIGNED 0
91617     parameter \A_WIDTH 1
91618     parameter \B_SIGNED 0
91619     parameter \B_WIDTH 1
91620     parameter \Y_WIDTH 1
91621     connect \A \builder_csrbank3_sel
91622     connect \B $not$ls180.v:5863$1229_Y
91623     connect \Y $and$ls180.v:5863$1230_Y
91624   end
91625   attribute \src "ls180.v:5863.38-5863.145"
91626   cell $and $and$ls180.v:5863$1232
91627     parameter \A_SIGNED 0
91628     parameter \A_WIDTH 1
91629     parameter \B_SIGNED 0
91630     parameter \B_WIDTH 1
91631     parameter \Y_WIDTH 1
91632     connect \A $and$ls180.v:5863$1230_Y
91633     connect \B $eq$ls180.v:5863$1231_Y
91634     connect \Y $and$ls180.v:5863$1232_Y
91635   end
91636   attribute \src "ls180.v:5865.39-5865.92"
91637   cell $and $and$ls180.v:5865$1233
91638     parameter \A_SIGNED 0
91639     parameter \A_WIDTH 1
91640     parameter \B_SIGNED 0
91641     parameter \B_WIDTH 1
91642     parameter \Y_WIDTH 1
91643     connect \A \builder_csrbank3_sel
91644     connect \B \builder_interface3_bank_bus_we
91645     connect \Y $and$ls180.v:5865$1233_Y
91646   end
91647   attribute \src "ls180.v:5865.38-5865.142"
91648   cell $and $and$ls180.v:5865$1235
91649     parameter \A_SIGNED 0
91650     parameter \A_WIDTH 1
91651     parameter \B_SIGNED 0
91652     parameter \B_WIDTH 1
91653     parameter \Y_WIDTH 1
91654     connect \A $and$ls180.v:5865$1233_Y
91655     connect \B $eq$ls180.v:5865$1234_Y
91656     connect \Y $and$ls180.v:5865$1235_Y
91657   end
91658   attribute \src "ls180.v:5866.39-5866.95"
91659   cell $and $and$ls180.v:5866$1237
91660     parameter \A_SIGNED 0
91661     parameter \A_WIDTH 1
91662     parameter \B_SIGNED 0
91663     parameter \B_WIDTH 1
91664     parameter \Y_WIDTH 1
91665     connect \A \builder_csrbank3_sel
91666     connect \B $not$ls180.v:5866$1236_Y
91667     connect \Y $and$ls180.v:5866$1237_Y
91668   end
91669   attribute \src "ls180.v:5866.38-5866.145"
91670   cell $and $and$ls180.v:5866$1239
91671     parameter \A_SIGNED 0
91672     parameter \A_WIDTH 1
91673     parameter \B_SIGNED 0
91674     parameter \B_WIDTH 1
91675     parameter \Y_WIDTH 1
91676     connect \A $and$ls180.v:5866$1237_Y
91677     connect \B $eq$ls180.v:5866$1238_Y
91678     connect \Y $and$ls180.v:5866$1239_Y
91679   end
91680   attribute \src "ls180.v:5868.40-5868.93"
91681   cell $and $and$ls180.v:5868$1240
91682     parameter \A_SIGNED 0
91683     parameter \A_WIDTH 1
91684     parameter \B_SIGNED 0
91685     parameter \B_WIDTH 1
91686     parameter \Y_WIDTH 1
91687     connect \A \builder_csrbank3_sel
91688     connect \B \builder_interface3_bank_bus_we
91689     connect \Y $and$ls180.v:5868$1240_Y
91690   end
91691   attribute \src "ls180.v:5868.39-5868.143"
91692   cell $and $and$ls180.v:5868$1242
91693     parameter \A_SIGNED 0
91694     parameter \A_WIDTH 1
91695     parameter \B_SIGNED 0
91696     parameter \B_WIDTH 1
91697     parameter \Y_WIDTH 1
91698     connect \A $and$ls180.v:5868$1240_Y
91699     connect \B $eq$ls180.v:5868$1241_Y
91700     connect \Y $and$ls180.v:5868$1242_Y
91701   end
91702   attribute \src "ls180.v:5869.40-5869.96"
91703   cell $and $and$ls180.v:5869$1244
91704     parameter \A_SIGNED 0
91705     parameter \A_WIDTH 1
91706     parameter \B_SIGNED 0
91707     parameter \B_WIDTH 1
91708     parameter \Y_WIDTH 1
91709     connect \A \builder_csrbank3_sel
91710     connect \B $not$ls180.v:5869$1243_Y
91711     connect \Y $and$ls180.v:5869$1244_Y
91712   end
91713   attribute \src "ls180.v:5869.39-5869.146"
91714   cell $and $and$ls180.v:5869$1246
91715     parameter \A_SIGNED 0
91716     parameter \A_WIDTH 1
91717     parameter \B_SIGNED 0
91718     parameter \B_WIDTH 1
91719     parameter \Y_WIDTH 1
91720     connect \A $and$ls180.v:5869$1244_Y
91721     connect \B $eq$ls180.v:5869$1245_Y
91722     connect \Y $and$ls180.v:5869$1246_Y
91723   end
91724   attribute \src "ls180.v:5871.40-5871.93"
91725   cell $and $and$ls180.v:5871$1247
91726     parameter \A_SIGNED 0
91727     parameter \A_WIDTH 1
91728     parameter \B_SIGNED 0
91729     parameter \B_WIDTH 1
91730     parameter \Y_WIDTH 1
91731     connect \A \builder_csrbank3_sel
91732     connect \B \builder_interface3_bank_bus_we
91733     connect \Y $and$ls180.v:5871$1247_Y
91734   end
91735   attribute \src "ls180.v:5871.39-5871.143"
91736   cell $and $and$ls180.v:5871$1249
91737     parameter \A_SIGNED 0
91738     parameter \A_WIDTH 1
91739     parameter \B_SIGNED 0
91740     parameter \B_WIDTH 1
91741     parameter \Y_WIDTH 1
91742     connect \A $and$ls180.v:5871$1247_Y
91743     connect \B $eq$ls180.v:5871$1248_Y
91744     connect \Y $and$ls180.v:5871$1249_Y
91745   end
91746   attribute \src "ls180.v:5872.40-5872.96"
91747   cell $and $and$ls180.v:5872$1251
91748     parameter \A_SIGNED 0
91749     parameter \A_WIDTH 1
91750     parameter \B_SIGNED 0
91751     parameter \B_WIDTH 1
91752     parameter \Y_WIDTH 1
91753     connect \A \builder_csrbank3_sel
91754     connect \B $not$ls180.v:5872$1250_Y
91755     connect \Y $and$ls180.v:5872$1251_Y
91756   end
91757   attribute \src "ls180.v:5872.39-5872.146"
91758   cell $and $and$ls180.v:5872$1253
91759     parameter \A_SIGNED 0
91760     parameter \A_WIDTH 1
91761     parameter \B_SIGNED 0
91762     parameter \B_WIDTH 1
91763     parameter \Y_WIDTH 1
91764     connect \A $and$ls180.v:5872$1251_Y
91765     connect \B $eq$ls180.v:5872$1252_Y
91766     connect \Y $and$ls180.v:5872$1253_Y
91767   end
91768   attribute \src "ls180.v:5874.40-5874.93"
91769   cell $and $and$ls180.v:5874$1254
91770     parameter \A_SIGNED 0
91771     parameter \A_WIDTH 1
91772     parameter \B_SIGNED 0
91773     parameter \B_WIDTH 1
91774     parameter \Y_WIDTH 1
91775     connect \A \builder_csrbank3_sel
91776     connect \B \builder_interface3_bank_bus_we
91777     connect \Y $and$ls180.v:5874$1254_Y
91778   end
91779   attribute \src "ls180.v:5874.39-5874.143"
91780   cell $and $and$ls180.v:5874$1256
91781     parameter \A_SIGNED 0
91782     parameter \A_WIDTH 1
91783     parameter \B_SIGNED 0
91784     parameter \B_WIDTH 1
91785     parameter \Y_WIDTH 1
91786     connect \A $and$ls180.v:5874$1254_Y
91787     connect \B $eq$ls180.v:5874$1255_Y
91788     connect \Y $and$ls180.v:5874$1256_Y
91789   end
91790   attribute \src "ls180.v:5875.40-5875.96"
91791   cell $and $and$ls180.v:5875$1258
91792     parameter \A_SIGNED 0
91793     parameter \A_WIDTH 1
91794     parameter \B_SIGNED 0
91795     parameter \B_WIDTH 1
91796     parameter \Y_WIDTH 1
91797     connect \A \builder_csrbank3_sel
91798     connect \B $not$ls180.v:5875$1257_Y
91799     connect \Y $and$ls180.v:5875$1258_Y
91800   end
91801   attribute \src "ls180.v:5875.39-5875.146"
91802   cell $and $and$ls180.v:5875$1260
91803     parameter \A_SIGNED 0
91804     parameter \A_WIDTH 1
91805     parameter \B_SIGNED 0
91806     parameter \B_WIDTH 1
91807     parameter \Y_WIDTH 1
91808     connect \A $and$ls180.v:5875$1258_Y
91809     connect \B $eq$ls180.v:5875$1259_Y
91810     connect \Y $and$ls180.v:5875$1260_Y
91811   end
91812   attribute \src "ls180.v:5877.40-5877.93"
91813   cell $and $and$ls180.v:5877$1261
91814     parameter \A_SIGNED 0
91815     parameter \A_WIDTH 1
91816     parameter \B_SIGNED 0
91817     parameter \B_WIDTH 1
91818     parameter \Y_WIDTH 1
91819     connect \A \builder_csrbank3_sel
91820     connect \B \builder_interface3_bank_bus_we
91821     connect \Y $and$ls180.v:5877$1261_Y
91822   end
91823   attribute \src "ls180.v:5877.39-5877.143"
91824   cell $and $and$ls180.v:5877$1263
91825     parameter \A_SIGNED 0
91826     parameter \A_WIDTH 1
91827     parameter \B_SIGNED 0
91828     parameter \B_WIDTH 1
91829     parameter \Y_WIDTH 1
91830     connect \A $and$ls180.v:5877$1261_Y
91831     connect \B $eq$ls180.v:5877$1262_Y
91832     connect \Y $and$ls180.v:5877$1263_Y
91833   end
91834   attribute \src "ls180.v:5878.40-5878.96"
91835   cell $and $and$ls180.v:5878$1265
91836     parameter \A_SIGNED 0
91837     parameter \A_WIDTH 1
91838     parameter \B_SIGNED 0
91839     parameter \B_WIDTH 1
91840     parameter \Y_WIDTH 1
91841     connect \A \builder_csrbank3_sel
91842     connect \B $not$ls180.v:5878$1264_Y
91843     connect \Y $and$ls180.v:5878$1265_Y
91844   end
91845   attribute \src "ls180.v:5878.39-5878.146"
91846   cell $and $and$ls180.v:5878$1267
91847     parameter \A_SIGNED 0
91848     parameter \A_WIDTH 1
91849     parameter \B_SIGNED 0
91850     parameter \B_WIDTH 1
91851     parameter \Y_WIDTH 1
91852     connect \A $and$ls180.v:5878$1265_Y
91853     connect \B $eq$ls180.v:5878$1266_Y
91854     connect \Y $and$ls180.v:5878$1267_Y
91855   end
91856   attribute \src "ls180.v:5890.40-5890.93"
91857   cell $and $and$ls180.v:5890$1269
91858     parameter \A_SIGNED 0
91859     parameter \A_WIDTH 1
91860     parameter \B_SIGNED 0
91861     parameter \B_WIDTH 1
91862     parameter \Y_WIDTH 1
91863     connect \A \builder_csrbank4_sel
91864     connect \B \builder_interface4_bank_bus_we
91865     connect \Y $and$ls180.v:5890$1269_Y
91866   end
91867   attribute \src "ls180.v:5890.39-5890.143"
91868   cell $and $and$ls180.v:5890$1271
91869     parameter \A_SIGNED 0
91870     parameter \A_WIDTH 1
91871     parameter \B_SIGNED 0
91872     parameter \B_WIDTH 1
91873     parameter \Y_WIDTH 1
91874     connect \A $and$ls180.v:5890$1269_Y
91875     connect \B $eq$ls180.v:5890$1270_Y
91876     connect \Y $and$ls180.v:5890$1271_Y
91877   end
91878   attribute \src "ls180.v:5891.40-5891.96"
91879   cell $and $and$ls180.v:5891$1273
91880     parameter \A_SIGNED 0
91881     parameter \A_WIDTH 1
91882     parameter \B_SIGNED 0
91883     parameter \B_WIDTH 1
91884     parameter \Y_WIDTH 1
91885     connect \A \builder_csrbank4_sel
91886     connect \B $not$ls180.v:5891$1272_Y
91887     connect \Y $and$ls180.v:5891$1273_Y
91888   end
91889   attribute \src "ls180.v:5891.39-5891.146"
91890   cell $and $and$ls180.v:5891$1275
91891     parameter \A_SIGNED 0
91892     parameter \A_WIDTH 1
91893     parameter \B_SIGNED 0
91894     parameter \B_WIDTH 1
91895     parameter \Y_WIDTH 1
91896     connect \A $and$ls180.v:5891$1273_Y
91897     connect \B $eq$ls180.v:5891$1274_Y
91898     connect \Y $and$ls180.v:5891$1275_Y
91899   end
91900   attribute \src "ls180.v:5893.39-5893.92"
91901   cell $and $and$ls180.v:5893$1276
91902     parameter \A_SIGNED 0
91903     parameter \A_WIDTH 1
91904     parameter \B_SIGNED 0
91905     parameter \B_WIDTH 1
91906     parameter \Y_WIDTH 1
91907     connect \A \builder_csrbank4_sel
91908     connect \B \builder_interface4_bank_bus_we
91909     connect \Y $and$ls180.v:5893$1276_Y
91910   end
91911   attribute \src "ls180.v:5893.38-5893.142"
91912   cell $and $and$ls180.v:5893$1278
91913     parameter \A_SIGNED 0
91914     parameter \A_WIDTH 1
91915     parameter \B_SIGNED 0
91916     parameter \B_WIDTH 1
91917     parameter \Y_WIDTH 1
91918     connect \A $and$ls180.v:5893$1276_Y
91919     connect \B $eq$ls180.v:5893$1277_Y
91920     connect \Y $and$ls180.v:5893$1278_Y
91921   end
91922   attribute \src "ls180.v:5894.39-5894.95"
91923   cell $and $and$ls180.v:5894$1280
91924     parameter \A_SIGNED 0
91925     parameter \A_WIDTH 1
91926     parameter \B_SIGNED 0
91927     parameter \B_WIDTH 1
91928     parameter \Y_WIDTH 1
91929     connect \A \builder_csrbank4_sel
91930     connect \B $not$ls180.v:5894$1279_Y
91931     connect \Y $and$ls180.v:5894$1280_Y
91932   end
91933   attribute \src "ls180.v:5894.38-5894.145"
91934   cell $and $and$ls180.v:5894$1282
91935     parameter \A_SIGNED 0
91936     parameter \A_WIDTH 1
91937     parameter \B_SIGNED 0
91938     parameter \B_WIDTH 1
91939     parameter \Y_WIDTH 1
91940     connect \A $and$ls180.v:5894$1280_Y
91941     connect \B $eq$ls180.v:5894$1281_Y
91942     connect \Y $and$ls180.v:5894$1282_Y
91943   end
91944   attribute \src "ls180.v:5896.39-5896.92"
91945   cell $and $and$ls180.v:5896$1283
91946     parameter \A_SIGNED 0
91947     parameter \A_WIDTH 1
91948     parameter \B_SIGNED 0
91949     parameter \B_WIDTH 1
91950     parameter \Y_WIDTH 1
91951     connect \A \builder_csrbank4_sel
91952     connect \B \builder_interface4_bank_bus_we
91953     connect \Y $and$ls180.v:5896$1283_Y
91954   end
91955   attribute \src "ls180.v:5896.38-5896.142"
91956   cell $and $and$ls180.v:5896$1285
91957     parameter \A_SIGNED 0
91958     parameter \A_WIDTH 1
91959     parameter \B_SIGNED 0
91960     parameter \B_WIDTH 1
91961     parameter \Y_WIDTH 1
91962     connect \A $and$ls180.v:5896$1283_Y
91963     connect \B $eq$ls180.v:5896$1284_Y
91964     connect \Y $and$ls180.v:5896$1285_Y
91965   end
91966   attribute \src "ls180.v:5897.39-5897.95"
91967   cell $and $and$ls180.v:5897$1287
91968     parameter \A_SIGNED 0
91969     parameter \A_WIDTH 1
91970     parameter \B_SIGNED 0
91971     parameter \B_WIDTH 1
91972     parameter \Y_WIDTH 1
91973     connect \A \builder_csrbank4_sel
91974     connect \B $not$ls180.v:5897$1286_Y
91975     connect \Y $and$ls180.v:5897$1287_Y
91976   end
91977   attribute \src "ls180.v:5897.38-5897.145"
91978   cell $and $and$ls180.v:5897$1289
91979     parameter \A_SIGNED 0
91980     parameter \A_WIDTH 1
91981     parameter \B_SIGNED 0
91982     parameter \B_WIDTH 1
91983     parameter \Y_WIDTH 1
91984     connect \A $and$ls180.v:5897$1287_Y
91985     connect \B $eq$ls180.v:5897$1288_Y
91986     connect \Y $and$ls180.v:5897$1289_Y
91987   end
91988   attribute \src "ls180.v:5899.39-5899.92"
91989   cell $and $and$ls180.v:5899$1290
91990     parameter \A_SIGNED 0
91991     parameter \A_WIDTH 1
91992     parameter \B_SIGNED 0
91993     parameter \B_WIDTH 1
91994     parameter \Y_WIDTH 1
91995     connect \A \builder_csrbank4_sel
91996     connect \B \builder_interface4_bank_bus_we
91997     connect \Y $and$ls180.v:5899$1290_Y
91998   end
91999   attribute \src "ls180.v:5899.38-5899.142"
92000   cell $and $and$ls180.v:5899$1292
92001     parameter \A_SIGNED 0
92002     parameter \A_WIDTH 1
92003     parameter \B_SIGNED 0
92004     parameter \B_WIDTH 1
92005     parameter \Y_WIDTH 1
92006     connect \A $and$ls180.v:5899$1290_Y
92007     connect \B $eq$ls180.v:5899$1291_Y
92008     connect \Y $and$ls180.v:5899$1292_Y
92009   end
92010   attribute \src "ls180.v:5900.39-5900.95"
92011   cell $and $and$ls180.v:5900$1294
92012     parameter \A_SIGNED 0
92013     parameter \A_WIDTH 1
92014     parameter \B_SIGNED 0
92015     parameter \B_WIDTH 1
92016     parameter \Y_WIDTH 1
92017     connect \A \builder_csrbank4_sel
92018     connect \B $not$ls180.v:5900$1293_Y
92019     connect \Y $and$ls180.v:5900$1294_Y
92020   end
92021   attribute \src "ls180.v:5900.38-5900.145"
92022   cell $and $and$ls180.v:5900$1296
92023     parameter \A_SIGNED 0
92024     parameter \A_WIDTH 1
92025     parameter \B_SIGNED 0
92026     parameter \B_WIDTH 1
92027     parameter \Y_WIDTH 1
92028     connect \A $and$ls180.v:5900$1294_Y
92029     connect \B $eq$ls180.v:5900$1295_Y
92030     connect \Y $and$ls180.v:5900$1296_Y
92031   end
92032   attribute \src "ls180.v:5902.39-5902.92"
92033   cell $and $and$ls180.v:5902$1297
92034     parameter \A_SIGNED 0
92035     parameter \A_WIDTH 1
92036     parameter \B_SIGNED 0
92037     parameter \B_WIDTH 1
92038     parameter \Y_WIDTH 1
92039     connect \A \builder_csrbank4_sel
92040     connect \B \builder_interface4_bank_bus_we
92041     connect \Y $and$ls180.v:5902$1297_Y
92042   end
92043   attribute \src "ls180.v:5902.38-5902.142"
92044   cell $and $and$ls180.v:5902$1299
92045     parameter \A_SIGNED 0
92046     parameter \A_WIDTH 1
92047     parameter \B_SIGNED 0
92048     parameter \B_WIDTH 1
92049     parameter \Y_WIDTH 1
92050     connect \A $and$ls180.v:5902$1297_Y
92051     connect \B $eq$ls180.v:5902$1298_Y
92052     connect \Y $and$ls180.v:5902$1299_Y
92053   end
92054   attribute \src "ls180.v:5903.39-5903.95"
92055   cell $and $and$ls180.v:5903$1301
92056     parameter \A_SIGNED 0
92057     parameter \A_WIDTH 1
92058     parameter \B_SIGNED 0
92059     parameter \B_WIDTH 1
92060     parameter \Y_WIDTH 1
92061     connect \A \builder_csrbank4_sel
92062     connect \B $not$ls180.v:5903$1300_Y
92063     connect \Y $and$ls180.v:5903$1301_Y
92064   end
92065   attribute \src "ls180.v:5903.38-5903.145"
92066   cell $and $and$ls180.v:5903$1303
92067     parameter \A_SIGNED 0
92068     parameter \A_WIDTH 1
92069     parameter \B_SIGNED 0
92070     parameter \B_WIDTH 1
92071     parameter \Y_WIDTH 1
92072     connect \A $and$ls180.v:5903$1301_Y
92073     connect \B $eq$ls180.v:5903$1302_Y
92074     connect \Y $and$ls180.v:5903$1303_Y
92075   end
92076   attribute \src "ls180.v:5905.40-5905.93"
92077   cell $and $and$ls180.v:5905$1304
92078     parameter \A_SIGNED 0
92079     parameter \A_WIDTH 1
92080     parameter \B_SIGNED 0
92081     parameter \B_WIDTH 1
92082     parameter \Y_WIDTH 1
92083     connect \A \builder_csrbank4_sel
92084     connect \B \builder_interface4_bank_bus_we
92085     connect \Y $and$ls180.v:5905$1304_Y
92086   end
92087   attribute \src "ls180.v:5905.39-5905.143"
92088   cell $and $and$ls180.v:5905$1306
92089     parameter \A_SIGNED 0
92090     parameter \A_WIDTH 1
92091     parameter \B_SIGNED 0
92092     parameter \B_WIDTH 1
92093     parameter \Y_WIDTH 1
92094     connect \A $and$ls180.v:5905$1304_Y
92095     connect \B $eq$ls180.v:5905$1305_Y
92096     connect \Y $and$ls180.v:5905$1306_Y
92097   end
92098   attribute \src "ls180.v:5906.40-5906.96"
92099   cell $and $and$ls180.v:5906$1308
92100     parameter \A_SIGNED 0
92101     parameter \A_WIDTH 1
92102     parameter \B_SIGNED 0
92103     parameter \B_WIDTH 1
92104     parameter \Y_WIDTH 1
92105     connect \A \builder_csrbank4_sel
92106     connect \B $not$ls180.v:5906$1307_Y
92107     connect \Y $and$ls180.v:5906$1308_Y
92108   end
92109   attribute \src "ls180.v:5906.39-5906.146"
92110   cell $and $and$ls180.v:5906$1310
92111     parameter \A_SIGNED 0
92112     parameter \A_WIDTH 1
92113     parameter \B_SIGNED 0
92114     parameter \B_WIDTH 1
92115     parameter \Y_WIDTH 1
92116     connect \A $and$ls180.v:5906$1308_Y
92117     connect \B $eq$ls180.v:5906$1309_Y
92118     connect \Y $and$ls180.v:5906$1310_Y
92119   end
92120   attribute \src "ls180.v:5908.40-5908.93"
92121   cell $and $and$ls180.v:5908$1311
92122     parameter \A_SIGNED 0
92123     parameter \A_WIDTH 1
92124     parameter \B_SIGNED 0
92125     parameter \B_WIDTH 1
92126     parameter \Y_WIDTH 1
92127     connect \A \builder_csrbank4_sel
92128     connect \B \builder_interface4_bank_bus_we
92129     connect \Y $and$ls180.v:5908$1311_Y
92130   end
92131   attribute \src "ls180.v:5908.39-5908.143"
92132   cell $and $and$ls180.v:5908$1313
92133     parameter \A_SIGNED 0
92134     parameter \A_WIDTH 1
92135     parameter \B_SIGNED 0
92136     parameter \B_WIDTH 1
92137     parameter \Y_WIDTH 1
92138     connect \A $and$ls180.v:5908$1311_Y
92139     connect \B $eq$ls180.v:5908$1312_Y
92140     connect \Y $and$ls180.v:5908$1313_Y
92141   end
92142   attribute \src "ls180.v:5909.40-5909.96"
92143   cell $and $and$ls180.v:5909$1315
92144     parameter \A_SIGNED 0
92145     parameter \A_WIDTH 1
92146     parameter \B_SIGNED 0
92147     parameter \B_WIDTH 1
92148     parameter \Y_WIDTH 1
92149     connect \A \builder_csrbank4_sel
92150     connect \B $not$ls180.v:5909$1314_Y
92151     connect \Y $and$ls180.v:5909$1315_Y
92152   end
92153   attribute \src "ls180.v:5909.39-5909.146"
92154   cell $and $and$ls180.v:5909$1317
92155     parameter \A_SIGNED 0
92156     parameter \A_WIDTH 1
92157     parameter \B_SIGNED 0
92158     parameter \B_WIDTH 1
92159     parameter \Y_WIDTH 1
92160     connect \A $and$ls180.v:5909$1315_Y
92161     connect \B $eq$ls180.v:5909$1316_Y
92162     connect \Y $and$ls180.v:5909$1317_Y
92163   end
92164   attribute \src "ls180.v:5911.40-5911.93"
92165   cell $and $and$ls180.v:5911$1318
92166     parameter \A_SIGNED 0
92167     parameter \A_WIDTH 1
92168     parameter \B_SIGNED 0
92169     parameter \B_WIDTH 1
92170     parameter \Y_WIDTH 1
92171     connect \A \builder_csrbank4_sel
92172     connect \B \builder_interface4_bank_bus_we
92173     connect \Y $and$ls180.v:5911$1318_Y
92174   end
92175   attribute \src "ls180.v:5911.39-5911.143"
92176   cell $and $and$ls180.v:5911$1320
92177     parameter \A_SIGNED 0
92178     parameter \A_WIDTH 1
92179     parameter \B_SIGNED 0
92180     parameter \B_WIDTH 1
92181     parameter \Y_WIDTH 1
92182     connect \A $and$ls180.v:5911$1318_Y
92183     connect \B $eq$ls180.v:5911$1319_Y
92184     connect \Y $and$ls180.v:5911$1320_Y
92185   end
92186   attribute \src "ls180.v:5912.40-5912.96"
92187   cell $and $and$ls180.v:5912$1322
92188     parameter \A_SIGNED 0
92189     parameter \A_WIDTH 1
92190     parameter \B_SIGNED 0
92191     parameter \B_WIDTH 1
92192     parameter \Y_WIDTH 1
92193     connect \A \builder_csrbank4_sel
92194     connect \B $not$ls180.v:5912$1321_Y
92195     connect \Y $and$ls180.v:5912$1322_Y
92196   end
92197   attribute \src "ls180.v:5912.39-5912.146"
92198   cell $and $and$ls180.v:5912$1324
92199     parameter \A_SIGNED 0
92200     parameter \A_WIDTH 1
92201     parameter \B_SIGNED 0
92202     parameter \B_WIDTH 1
92203     parameter \Y_WIDTH 1
92204     connect \A $and$ls180.v:5912$1322_Y
92205     connect \B $eq$ls180.v:5912$1323_Y
92206     connect \Y $and$ls180.v:5912$1324_Y
92207   end
92208   attribute \src "ls180.v:5914.40-5914.93"
92209   cell $and $and$ls180.v:5914$1325
92210     parameter \A_SIGNED 0
92211     parameter \A_WIDTH 1
92212     parameter \B_SIGNED 0
92213     parameter \B_WIDTH 1
92214     parameter \Y_WIDTH 1
92215     connect \A \builder_csrbank4_sel
92216     connect \B \builder_interface4_bank_bus_we
92217     connect \Y $and$ls180.v:5914$1325_Y
92218   end
92219   attribute \src "ls180.v:5914.39-5914.143"
92220   cell $and $and$ls180.v:5914$1327
92221     parameter \A_SIGNED 0
92222     parameter \A_WIDTH 1
92223     parameter \B_SIGNED 0
92224     parameter \B_WIDTH 1
92225     parameter \Y_WIDTH 1
92226     connect \A $and$ls180.v:5914$1325_Y
92227     connect \B $eq$ls180.v:5914$1326_Y
92228     connect \Y $and$ls180.v:5914$1327_Y
92229   end
92230   attribute \src "ls180.v:5915.40-5915.96"
92231   cell $and $and$ls180.v:5915$1329
92232     parameter \A_SIGNED 0
92233     parameter \A_WIDTH 1
92234     parameter \B_SIGNED 0
92235     parameter \B_WIDTH 1
92236     parameter \Y_WIDTH 1
92237     connect \A \builder_csrbank4_sel
92238     connect \B $not$ls180.v:5915$1328_Y
92239     connect \Y $and$ls180.v:5915$1329_Y
92240   end
92241   attribute \src "ls180.v:5915.39-5915.146"
92242   cell $and $and$ls180.v:5915$1331
92243     parameter \A_SIGNED 0
92244     parameter \A_WIDTH 1
92245     parameter \B_SIGNED 0
92246     parameter \B_WIDTH 1
92247     parameter \Y_WIDTH 1
92248     connect \A $and$ls180.v:5915$1329_Y
92249     connect \B $eq$ls180.v:5915$1330_Y
92250     connect \Y $and$ls180.v:5915$1331_Y
92251   end
92252   attribute \src "ls180.v:5927.42-5927.95"
92253   cell $and $and$ls180.v:5927$1333
92254     parameter \A_SIGNED 0
92255     parameter \A_WIDTH 1
92256     parameter \B_SIGNED 0
92257     parameter \B_WIDTH 1
92258     parameter \Y_WIDTH 1
92259     connect \A \builder_csrbank5_sel
92260     connect \B \builder_interface5_bank_bus_we
92261     connect \Y $and$ls180.v:5927$1333_Y
92262   end
92263   attribute \src "ls180.v:5927.41-5927.145"
92264   cell $and $and$ls180.v:5927$1335
92265     parameter \A_SIGNED 0
92266     parameter \A_WIDTH 1
92267     parameter \B_SIGNED 0
92268     parameter \B_WIDTH 1
92269     parameter \Y_WIDTH 1
92270     connect \A $and$ls180.v:5927$1333_Y
92271     connect \B $eq$ls180.v:5927$1334_Y
92272     connect \Y $and$ls180.v:5927$1335_Y
92273   end
92274   attribute \src "ls180.v:5928.42-5928.98"
92275   cell $and $and$ls180.v:5928$1337
92276     parameter \A_SIGNED 0
92277     parameter \A_WIDTH 1
92278     parameter \B_SIGNED 0
92279     parameter \B_WIDTH 1
92280     parameter \Y_WIDTH 1
92281     connect \A \builder_csrbank5_sel
92282     connect \B $not$ls180.v:5928$1336_Y
92283     connect \Y $and$ls180.v:5928$1337_Y
92284   end
92285   attribute \src "ls180.v:5928.41-5928.148"
92286   cell $and $and$ls180.v:5928$1339
92287     parameter \A_SIGNED 0
92288     parameter \A_WIDTH 1
92289     parameter \B_SIGNED 0
92290     parameter \B_WIDTH 1
92291     parameter \Y_WIDTH 1
92292     connect \A $and$ls180.v:5928$1337_Y
92293     connect \B $eq$ls180.v:5928$1338_Y
92294     connect \Y $and$ls180.v:5928$1339_Y
92295   end
92296   attribute \src "ls180.v:5930.42-5930.95"
92297   cell $and $and$ls180.v:5930$1340
92298     parameter \A_SIGNED 0
92299     parameter \A_WIDTH 1
92300     parameter \B_SIGNED 0
92301     parameter \B_WIDTH 1
92302     parameter \Y_WIDTH 1
92303     connect \A \builder_csrbank5_sel
92304     connect \B \builder_interface5_bank_bus_we
92305     connect \Y $and$ls180.v:5930$1340_Y
92306   end
92307   attribute \src "ls180.v:5930.41-5930.145"
92308   cell $and $and$ls180.v:5930$1342
92309     parameter \A_SIGNED 0
92310     parameter \A_WIDTH 1
92311     parameter \B_SIGNED 0
92312     parameter \B_WIDTH 1
92313     parameter \Y_WIDTH 1
92314     connect \A $and$ls180.v:5930$1340_Y
92315     connect \B $eq$ls180.v:5930$1341_Y
92316     connect \Y $and$ls180.v:5930$1342_Y
92317   end
92318   attribute \src "ls180.v:5931.42-5931.98"
92319   cell $and $and$ls180.v:5931$1344
92320     parameter \A_SIGNED 0
92321     parameter \A_WIDTH 1
92322     parameter \B_SIGNED 0
92323     parameter \B_WIDTH 1
92324     parameter \Y_WIDTH 1
92325     connect \A \builder_csrbank5_sel
92326     connect \B $not$ls180.v:5931$1343_Y
92327     connect \Y $and$ls180.v:5931$1344_Y
92328   end
92329   attribute \src "ls180.v:5931.41-5931.148"
92330   cell $and $and$ls180.v:5931$1346
92331     parameter \A_SIGNED 0
92332     parameter \A_WIDTH 1
92333     parameter \B_SIGNED 0
92334     parameter \B_WIDTH 1
92335     parameter \Y_WIDTH 1
92336     connect \A $and$ls180.v:5931$1344_Y
92337     connect \B $eq$ls180.v:5931$1345_Y
92338     connect \Y $and$ls180.v:5931$1346_Y
92339   end
92340   attribute \src "ls180.v:5933.42-5933.95"
92341   cell $and $and$ls180.v:5933$1347
92342     parameter \A_SIGNED 0
92343     parameter \A_WIDTH 1
92344     parameter \B_SIGNED 0
92345     parameter \B_WIDTH 1
92346     parameter \Y_WIDTH 1
92347     connect \A \builder_csrbank5_sel
92348     connect \B \builder_interface5_bank_bus_we
92349     connect \Y $and$ls180.v:5933$1347_Y
92350   end
92351   attribute \src "ls180.v:5933.41-5933.145"
92352   cell $and $and$ls180.v:5933$1349
92353     parameter \A_SIGNED 0
92354     parameter \A_WIDTH 1
92355     parameter \B_SIGNED 0
92356     parameter \B_WIDTH 1
92357     parameter \Y_WIDTH 1
92358     connect \A $and$ls180.v:5933$1347_Y
92359     connect \B $eq$ls180.v:5933$1348_Y
92360     connect \Y $and$ls180.v:5933$1349_Y
92361   end
92362   attribute \src "ls180.v:5934.42-5934.98"
92363   cell $and $and$ls180.v:5934$1351
92364     parameter \A_SIGNED 0
92365     parameter \A_WIDTH 1
92366     parameter \B_SIGNED 0
92367     parameter \B_WIDTH 1
92368     parameter \Y_WIDTH 1
92369     connect \A \builder_csrbank5_sel
92370     connect \B $not$ls180.v:5934$1350_Y
92371     connect \Y $and$ls180.v:5934$1351_Y
92372   end
92373   attribute \src "ls180.v:5934.41-5934.148"
92374   cell $and $and$ls180.v:5934$1353
92375     parameter \A_SIGNED 0
92376     parameter \A_WIDTH 1
92377     parameter \B_SIGNED 0
92378     parameter \B_WIDTH 1
92379     parameter \Y_WIDTH 1
92380     connect \A $and$ls180.v:5934$1351_Y
92381     connect \B $eq$ls180.v:5934$1352_Y
92382     connect \Y $and$ls180.v:5934$1353_Y
92383   end
92384   attribute \src "ls180.v:5936.42-5936.95"
92385   cell $and $and$ls180.v:5936$1354
92386     parameter \A_SIGNED 0
92387     parameter \A_WIDTH 1
92388     parameter \B_SIGNED 0
92389     parameter \B_WIDTH 1
92390     parameter \Y_WIDTH 1
92391     connect \A \builder_csrbank5_sel
92392     connect \B \builder_interface5_bank_bus_we
92393     connect \Y $and$ls180.v:5936$1354_Y
92394   end
92395   attribute \src "ls180.v:5936.41-5936.145"
92396   cell $and $and$ls180.v:5936$1356
92397     parameter \A_SIGNED 0
92398     parameter \A_WIDTH 1
92399     parameter \B_SIGNED 0
92400     parameter \B_WIDTH 1
92401     parameter \Y_WIDTH 1
92402     connect \A $and$ls180.v:5936$1354_Y
92403     connect \B $eq$ls180.v:5936$1355_Y
92404     connect \Y $and$ls180.v:5936$1356_Y
92405   end
92406   attribute \src "ls180.v:5937.42-5937.98"
92407   cell $and $and$ls180.v:5937$1358
92408     parameter \A_SIGNED 0
92409     parameter \A_WIDTH 1
92410     parameter \B_SIGNED 0
92411     parameter \B_WIDTH 1
92412     parameter \Y_WIDTH 1
92413     connect \A \builder_csrbank5_sel
92414     connect \B $not$ls180.v:5937$1357_Y
92415     connect \Y $and$ls180.v:5937$1358_Y
92416   end
92417   attribute \src "ls180.v:5937.41-5937.148"
92418   cell $and $and$ls180.v:5937$1360
92419     parameter \A_SIGNED 0
92420     parameter \A_WIDTH 1
92421     parameter \B_SIGNED 0
92422     parameter \B_WIDTH 1
92423     parameter \Y_WIDTH 1
92424     connect \A $and$ls180.v:5937$1358_Y
92425     connect \B $eq$ls180.v:5937$1359_Y
92426     connect \Y $and$ls180.v:5937$1360_Y
92427   end
92428   attribute \src "ls180.v:5939.42-5939.95"
92429   cell $and $and$ls180.v:5939$1361
92430     parameter \A_SIGNED 0
92431     parameter \A_WIDTH 1
92432     parameter \B_SIGNED 0
92433     parameter \B_WIDTH 1
92434     parameter \Y_WIDTH 1
92435     connect \A \builder_csrbank5_sel
92436     connect \B \builder_interface5_bank_bus_we
92437     connect \Y $and$ls180.v:5939$1361_Y
92438   end
92439   attribute \src "ls180.v:5939.41-5939.145"
92440   cell $and $and$ls180.v:5939$1363
92441     parameter \A_SIGNED 0
92442     parameter \A_WIDTH 1
92443     parameter \B_SIGNED 0
92444     parameter \B_WIDTH 1
92445     parameter \Y_WIDTH 1
92446     connect \A $and$ls180.v:5939$1361_Y
92447     connect \B $eq$ls180.v:5939$1362_Y
92448     connect \Y $and$ls180.v:5939$1363_Y
92449   end
92450   attribute \src "ls180.v:5940.42-5940.98"
92451   cell $and $and$ls180.v:5940$1365
92452     parameter \A_SIGNED 0
92453     parameter \A_WIDTH 1
92454     parameter \B_SIGNED 0
92455     parameter \B_WIDTH 1
92456     parameter \Y_WIDTH 1
92457     connect \A \builder_csrbank5_sel
92458     connect \B $not$ls180.v:5940$1364_Y
92459     connect \Y $and$ls180.v:5940$1365_Y
92460   end
92461   attribute \src "ls180.v:5940.41-5940.148"
92462   cell $and $and$ls180.v:5940$1367
92463     parameter \A_SIGNED 0
92464     parameter \A_WIDTH 1
92465     parameter \B_SIGNED 0
92466     parameter \B_WIDTH 1
92467     parameter \Y_WIDTH 1
92468     connect \A $and$ls180.v:5940$1365_Y
92469     connect \B $eq$ls180.v:5940$1366_Y
92470     connect \Y $and$ls180.v:5940$1367_Y
92471   end
92472   attribute \src "ls180.v:5942.42-5942.95"
92473   cell $and $and$ls180.v:5942$1368
92474     parameter \A_SIGNED 0
92475     parameter \A_WIDTH 1
92476     parameter \B_SIGNED 0
92477     parameter \B_WIDTH 1
92478     parameter \Y_WIDTH 1
92479     connect \A \builder_csrbank5_sel
92480     connect \B \builder_interface5_bank_bus_we
92481     connect \Y $and$ls180.v:5942$1368_Y
92482   end
92483   attribute \src "ls180.v:5942.41-5942.145"
92484   cell $and $and$ls180.v:5942$1370
92485     parameter \A_SIGNED 0
92486     parameter \A_WIDTH 1
92487     parameter \B_SIGNED 0
92488     parameter \B_WIDTH 1
92489     parameter \Y_WIDTH 1
92490     connect \A $and$ls180.v:5942$1368_Y
92491     connect \B $eq$ls180.v:5942$1369_Y
92492     connect \Y $and$ls180.v:5942$1370_Y
92493   end
92494   attribute \src "ls180.v:5943.42-5943.98"
92495   cell $and $and$ls180.v:5943$1372
92496     parameter \A_SIGNED 0
92497     parameter \A_WIDTH 1
92498     parameter \B_SIGNED 0
92499     parameter \B_WIDTH 1
92500     parameter \Y_WIDTH 1
92501     connect \A \builder_csrbank5_sel
92502     connect \B $not$ls180.v:5943$1371_Y
92503     connect \Y $and$ls180.v:5943$1372_Y
92504   end
92505   attribute \src "ls180.v:5943.41-5943.148"
92506   cell $and $and$ls180.v:5943$1374
92507     parameter \A_SIGNED 0
92508     parameter \A_WIDTH 1
92509     parameter \B_SIGNED 0
92510     parameter \B_WIDTH 1
92511     parameter \Y_WIDTH 1
92512     connect \A $and$ls180.v:5943$1372_Y
92513     connect \B $eq$ls180.v:5943$1373_Y
92514     connect \Y $and$ls180.v:5943$1374_Y
92515   end
92516   attribute \src "ls180.v:5945.42-5945.95"
92517   cell $and $and$ls180.v:5945$1375
92518     parameter \A_SIGNED 0
92519     parameter \A_WIDTH 1
92520     parameter \B_SIGNED 0
92521     parameter \B_WIDTH 1
92522     parameter \Y_WIDTH 1
92523     connect \A \builder_csrbank5_sel
92524     connect \B \builder_interface5_bank_bus_we
92525     connect \Y $and$ls180.v:5945$1375_Y
92526   end
92527   attribute \src "ls180.v:5945.41-5945.145"
92528   cell $and $and$ls180.v:5945$1377
92529     parameter \A_SIGNED 0
92530     parameter \A_WIDTH 1
92531     parameter \B_SIGNED 0
92532     parameter \B_WIDTH 1
92533     parameter \Y_WIDTH 1
92534     connect \A $and$ls180.v:5945$1375_Y
92535     connect \B $eq$ls180.v:5945$1376_Y
92536     connect \Y $and$ls180.v:5945$1377_Y
92537   end
92538   attribute \src "ls180.v:5946.42-5946.98"
92539   cell $and $and$ls180.v:5946$1379
92540     parameter \A_SIGNED 0
92541     parameter \A_WIDTH 1
92542     parameter \B_SIGNED 0
92543     parameter \B_WIDTH 1
92544     parameter \Y_WIDTH 1
92545     connect \A \builder_csrbank5_sel
92546     connect \B $not$ls180.v:5946$1378_Y
92547     connect \Y $and$ls180.v:5946$1379_Y
92548   end
92549   attribute \src "ls180.v:5946.41-5946.148"
92550   cell $and $and$ls180.v:5946$1381
92551     parameter \A_SIGNED 0
92552     parameter \A_WIDTH 1
92553     parameter \B_SIGNED 0
92554     parameter \B_WIDTH 1
92555     parameter \Y_WIDTH 1
92556     connect \A $and$ls180.v:5946$1379_Y
92557     connect \B $eq$ls180.v:5946$1380_Y
92558     connect \Y $and$ls180.v:5946$1381_Y
92559   end
92560   attribute \src "ls180.v:5948.42-5948.95"
92561   cell $and $and$ls180.v:5948$1382
92562     parameter \A_SIGNED 0
92563     parameter \A_WIDTH 1
92564     parameter \B_SIGNED 0
92565     parameter \B_WIDTH 1
92566     parameter \Y_WIDTH 1
92567     connect \A \builder_csrbank5_sel
92568     connect \B \builder_interface5_bank_bus_we
92569     connect \Y $and$ls180.v:5948$1382_Y
92570   end
92571   attribute \src "ls180.v:5948.41-5948.145"
92572   cell $and $and$ls180.v:5948$1384
92573     parameter \A_SIGNED 0
92574     parameter \A_WIDTH 1
92575     parameter \B_SIGNED 0
92576     parameter \B_WIDTH 1
92577     parameter \Y_WIDTH 1
92578     connect \A $and$ls180.v:5948$1382_Y
92579     connect \B $eq$ls180.v:5948$1383_Y
92580     connect \Y $and$ls180.v:5948$1384_Y
92581   end
92582   attribute \src "ls180.v:5949.42-5949.98"
92583   cell $and $and$ls180.v:5949$1386
92584     parameter \A_SIGNED 0
92585     parameter \A_WIDTH 1
92586     parameter \B_SIGNED 0
92587     parameter \B_WIDTH 1
92588     parameter \Y_WIDTH 1
92589     connect \A \builder_csrbank5_sel
92590     connect \B $not$ls180.v:5949$1385_Y
92591     connect \Y $and$ls180.v:5949$1386_Y
92592   end
92593   attribute \src "ls180.v:5949.41-5949.148"
92594   cell $and $and$ls180.v:5949$1388
92595     parameter \A_SIGNED 0
92596     parameter \A_WIDTH 1
92597     parameter \B_SIGNED 0
92598     parameter \B_WIDTH 1
92599     parameter \Y_WIDTH 1
92600     connect \A $and$ls180.v:5949$1386_Y
92601     connect \B $eq$ls180.v:5949$1387_Y
92602     connect \Y $and$ls180.v:5949$1388_Y
92603   end
92604   attribute \src "ls180.v:5951.44-5951.97"
92605   cell $and $and$ls180.v:5951$1389
92606     parameter \A_SIGNED 0
92607     parameter \A_WIDTH 1
92608     parameter \B_SIGNED 0
92609     parameter \B_WIDTH 1
92610     parameter \Y_WIDTH 1
92611     connect \A \builder_csrbank5_sel
92612     connect \B \builder_interface5_bank_bus_we
92613     connect \Y $and$ls180.v:5951$1389_Y
92614   end
92615   attribute \src "ls180.v:5951.43-5951.147"
92616   cell $and $and$ls180.v:5951$1391
92617     parameter \A_SIGNED 0
92618     parameter \A_WIDTH 1
92619     parameter \B_SIGNED 0
92620     parameter \B_WIDTH 1
92621     parameter \Y_WIDTH 1
92622     connect \A $and$ls180.v:5951$1389_Y
92623     connect \B $eq$ls180.v:5951$1390_Y
92624     connect \Y $and$ls180.v:5951$1391_Y
92625   end
92626   attribute \src "ls180.v:5952.44-5952.100"
92627   cell $and $and$ls180.v:5952$1393
92628     parameter \A_SIGNED 0
92629     parameter \A_WIDTH 1
92630     parameter \B_SIGNED 0
92631     parameter \B_WIDTH 1
92632     parameter \Y_WIDTH 1
92633     connect \A \builder_csrbank5_sel
92634     connect \B $not$ls180.v:5952$1392_Y
92635     connect \Y $and$ls180.v:5952$1393_Y
92636   end
92637   attribute \src "ls180.v:5952.43-5952.150"
92638   cell $and $and$ls180.v:5952$1395
92639     parameter \A_SIGNED 0
92640     parameter \A_WIDTH 1
92641     parameter \B_SIGNED 0
92642     parameter \B_WIDTH 1
92643     parameter \Y_WIDTH 1
92644     connect \A $and$ls180.v:5952$1393_Y
92645     connect \B $eq$ls180.v:5952$1394_Y
92646     connect \Y $and$ls180.v:5952$1395_Y
92647   end
92648   attribute \src "ls180.v:5954.44-5954.97"
92649   cell $and $and$ls180.v:5954$1396
92650     parameter \A_SIGNED 0
92651     parameter \A_WIDTH 1
92652     parameter \B_SIGNED 0
92653     parameter \B_WIDTH 1
92654     parameter \Y_WIDTH 1
92655     connect \A \builder_csrbank5_sel
92656     connect \B \builder_interface5_bank_bus_we
92657     connect \Y $and$ls180.v:5954$1396_Y
92658   end
92659   attribute \src "ls180.v:5954.43-5954.147"
92660   cell $and $and$ls180.v:5954$1398
92661     parameter \A_SIGNED 0
92662     parameter \A_WIDTH 1
92663     parameter \B_SIGNED 0
92664     parameter \B_WIDTH 1
92665     parameter \Y_WIDTH 1
92666     connect \A $and$ls180.v:5954$1396_Y
92667     connect \B $eq$ls180.v:5954$1397_Y
92668     connect \Y $and$ls180.v:5954$1398_Y
92669   end
92670   attribute \src "ls180.v:5955.44-5955.100"
92671   cell $and $and$ls180.v:5955$1400
92672     parameter \A_SIGNED 0
92673     parameter \A_WIDTH 1
92674     parameter \B_SIGNED 0
92675     parameter \B_WIDTH 1
92676     parameter \Y_WIDTH 1
92677     connect \A \builder_csrbank5_sel
92678     connect \B $not$ls180.v:5955$1399_Y
92679     connect \Y $and$ls180.v:5955$1400_Y
92680   end
92681   attribute \src "ls180.v:5955.43-5955.150"
92682   cell $and $and$ls180.v:5955$1402
92683     parameter \A_SIGNED 0
92684     parameter \A_WIDTH 1
92685     parameter \B_SIGNED 0
92686     parameter \B_WIDTH 1
92687     parameter \Y_WIDTH 1
92688     connect \A $and$ls180.v:5955$1400_Y
92689     connect \B $eq$ls180.v:5955$1401_Y
92690     connect \Y $and$ls180.v:5955$1402_Y
92691   end
92692   attribute \src "ls180.v:5957.44-5957.97"
92693   cell $and $and$ls180.v:5957$1403
92694     parameter \A_SIGNED 0
92695     parameter \A_WIDTH 1
92696     parameter \B_SIGNED 0
92697     parameter \B_WIDTH 1
92698     parameter \Y_WIDTH 1
92699     connect \A \builder_csrbank5_sel
92700     connect \B \builder_interface5_bank_bus_we
92701     connect \Y $and$ls180.v:5957$1403_Y
92702   end
92703   attribute \src "ls180.v:5957.43-5957.148"
92704   cell $and $and$ls180.v:5957$1405
92705     parameter \A_SIGNED 0
92706     parameter \A_WIDTH 1
92707     parameter \B_SIGNED 0
92708     parameter \B_WIDTH 1
92709     parameter \Y_WIDTH 1
92710     connect \A $and$ls180.v:5957$1403_Y
92711     connect \B $eq$ls180.v:5957$1404_Y
92712     connect \Y $and$ls180.v:5957$1405_Y
92713   end
92714   attribute \src "ls180.v:5958.44-5958.100"
92715   cell $and $and$ls180.v:5958$1407
92716     parameter \A_SIGNED 0
92717     parameter \A_WIDTH 1
92718     parameter \B_SIGNED 0
92719     parameter \B_WIDTH 1
92720     parameter \Y_WIDTH 1
92721     connect \A \builder_csrbank5_sel
92722     connect \B $not$ls180.v:5958$1406_Y
92723     connect \Y $and$ls180.v:5958$1407_Y
92724   end
92725   attribute \src "ls180.v:5958.43-5958.151"
92726   cell $and $and$ls180.v:5958$1409
92727     parameter \A_SIGNED 0
92728     parameter \A_WIDTH 1
92729     parameter \B_SIGNED 0
92730     parameter \B_WIDTH 1
92731     parameter \Y_WIDTH 1
92732     connect \A $and$ls180.v:5958$1407_Y
92733     connect \B $eq$ls180.v:5958$1408_Y
92734     connect \Y $and$ls180.v:5958$1409_Y
92735   end
92736   attribute \src "ls180.v:5960.44-5960.97"
92737   cell $and $and$ls180.v:5960$1410
92738     parameter \A_SIGNED 0
92739     parameter \A_WIDTH 1
92740     parameter \B_SIGNED 0
92741     parameter \B_WIDTH 1
92742     parameter \Y_WIDTH 1
92743     connect \A \builder_csrbank5_sel
92744     connect \B \builder_interface5_bank_bus_we
92745     connect \Y $and$ls180.v:5960$1410_Y
92746   end
92747   attribute \src "ls180.v:5960.43-5960.148"
92748   cell $and $and$ls180.v:5960$1412
92749     parameter \A_SIGNED 0
92750     parameter \A_WIDTH 1
92751     parameter \B_SIGNED 0
92752     parameter \B_WIDTH 1
92753     parameter \Y_WIDTH 1
92754     connect \A $and$ls180.v:5960$1410_Y
92755     connect \B $eq$ls180.v:5960$1411_Y
92756     connect \Y $and$ls180.v:5960$1412_Y
92757   end
92758   attribute \src "ls180.v:5961.44-5961.100"
92759   cell $and $and$ls180.v:5961$1414
92760     parameter \A_SIGNED 0
92761     parameter \A_WIDTH 1
92762     parameter \B_SIGNED 0
92763     parameter \B_WIDTH 1
92764     parameter \Y_WIDTH 1
92765     connect \A \builder_csrbank5_sel
92766     connect \B $not$ls180.v:5961$1413_Y
92767     connect \Y $and$ls180.v:5961$1414_Y
92768   end
92769   attribute \src "ls180.v:5961.43-5961.151"
92770   cell $and $and$ls180.v:5961$1416
92771     parameter \A_SIGNED 0
92772     parameter \A_WIDTH 1
92773     parameter \B_SIGNED 0
92774     parameter \B_WIDTH 1
92775     parameter \Y_WIDTH 1
92776     connect \A $and$ls180.v:5961$1414_Y
92777     connect \B $eq$ls180.v:5961$1415_Y
92778     connect \Y $and$ls180.v:5961$1416_Y
92779   end
92780   attribute \src "ls180.v:5963.44-5963.97"
92781   cell $and $and$ls180.v:5963$1417
92782     parameter \A_SIGNED 0
92783     parameter \A_WIDTH 1
92784     parameter \B_SIGNED 0
92785     parameter \B_WIDTH 1
92786     parameter \Y_WIDTH 1
92787     connect \A \builder_csrbank5_sel
92788     connect \B \builder_interface5_bank_bus_we
92789     connect \Y $and$ls180.v:5963$1417_Y
92790   end
92791   attribute \src "ls180.v:5963.43-5963.148"
92792   cell $and $and$ls180.v:5963$1419
92793     parameter \A_SIGNED 0
92794     parameter \A_WIDTH 1
92795     parameter \B_SIGNED 0
92796     parameter \B_WIDTH 1
92797     parameter \Y_WIDTH 1
92798     connect \A $and$ls180.v:5963$1417_Y
92799     connect \B $eq$ls180.v:5963$1418_Y
92800     connect \Y $and$ls180.v:5963$1419_Y
92801   end
92802   attribute \src "ls180.v:5964.44-5964.100"
92803   cell $and $and$ls180.v:5964$1421
92804     parameter \A_SIGNED 0
92805     parameter \A_WIDTH 1
92806     parameter \B_SIGNED 0
92807     parameter \B_WIDTH 1
92808     parameter \Y_WIDTH 1
92809     connect \A \builder_csrbank5_sel
92810     connect \B $not$ls180.v:5964$1420_Y
92811     connect \Y $and$ls180.v:5964$1421_Y
92812   end
92813   attribute \src "ls180.v:5964.43-5964.151"
92814   cell $and $and$ls180.v:5964$1423
92815     parameter \A_SIGNED 0
92816     parameter \A_WIDTH 1
92817     parameter \B_SIGNED 0
92818     parameter \B_WIDTH 1
92819     parameter \Y_WIDTH 1
92820     connect \A $and$ls180.v:5964$1421_Y
92821     connect \B $eq$ls180.v:5964$1422_Y
92822     connect \Y $and$ls180.v:5964$1423_Y
92823   end
92824   attribute \src "ls180.v:5966.41-5966.94"
92825   cell $and $and$ls180.v:5966$1424
92826     parameter \A_SIGNED 0
92827     parameter \A_WIDTH 1
92828     parameter \B_SIGNED 0
92829     parameter \B_WIDTH 1
92830     parameter \Y_WIDTH 1
92831     connect \A \builder_csrbank5_sel
92832     connect \B \builder_interface5_bank_bus_we
92833     connect \Y $and$ls180.v:5966$1424_Y
92834   end
92835   attribute \src "ls180.v:5966.40-5966.145"
92836   cell $and $and$ls180.v:5966$1426
92837     parameter \A_SIGNED 0
92838     parameter \A_WIDTH 1
92839     parameter \B_SIGNED 0
92840     parameter \B_WIDTH 1
92841     parameter \Y_WIDTH 1
92842     connect \A $and$ls180.v:5966$1424_Y
92843     connect \B $eq$ls180.v:5966$1425_Y
92844     connect \Y $and$ls180.v:5966$1426_Y
92845   end
92846   attribute \src "ls180.v:5967.41-5967.97"
92847   cell $and $and$ls180.v:5967$1428
92848     parameter \A_SIGNED 0
92849     parameter \A_WIDTH 1
92850     parameter \B_SIGNED 0
92851     parameter \B_WIDTH 1
92852     parameter \Y_WIDTH 1
92853     connect \A \builder_csrbank5_sel
92854     connect \B $not$ls180.v:5967$1427_Y
92855     connect \Y $and$ls180.v:5967$1428_Y
92856   end
92857   attribute \src "ls180.v:5967.40-5967.148"
92858   cell $and $and$ls180.v:5967$1430
92859     parameter \A_SIGNED 0
92860     parameter \A_WIDTH 1
92861     parameter \B_SIGNED 0
92862     parameter \B_WIDTH 1
92863     parameter \Y_WIDTH 1
92864     connect \A $and$ls180.v:5967$1428_Y
92865     connect \B $eq$ls180.v:5967$1429_Y
92866     connect \Y $and$ls180.v:5967$1430_Y
92867   end
92868   attribute \src "ls180.v:5969.42-5969.95"
92869   cell $and $and$ls180.v:5969$1431
92870     parameter \A_SIGNED 0
92871     parameter \A_WIDTH 1
92872     parameter \B_SIGNED 0
92873     parameter \B_WIDTH 1
92874     parameter \Y_WIDTH 1
92875     connect \A \builder_csrbank5_sel
92876     connect \B \builder_interface5_bank_bus_we
92877     connect \Y $and$ls180.v:5969$1431_Y
92878   end
92879   attribute \src "ls180.v:5969.41-5969.146"
92880   cell $and $and$ls180.v:5969$1433
92881     parameter \A_SIGNED 0
92882     parameter \A_WIDTH 1
92883     parameter \B_SIGNED 0
92884     parameter \B_WIDTH 1
92885     parameter \Y_WIDTH 1
92886     connect \A $and$ls180.v:5969$1431_Y
92887     connect \B $eq$ls180.v:5969$1432_Y
92888     connect \Y $and$ls180.v:5969$1433_Y
92889   end
92890   attribute \src "ls180.v:5970.42-5970.98"
92891   cell $and $and$ls180.v:5970$1435
92892     parameter \A_SIGNED 0
92893     parameter \A_WIDTH 1
92894     parameter \B_SIGNED 0
92895     parameter \B_WIDTH 1
92896     parameter \Y_WIDTH 1
92897     connect \A \builder_csrbank5_sel
92898     connect \B $not$ls180.v:5970$1434_Y
92899     connect \Y $and$ls180.v:5970$1435_Y
92900   end
92901   attribute \src "ls180.v:5970.41-5970.149"
92902   cell $and $and$ls180.v:5970$1437
92903     parameter \A_SIGNED 0
92904     parameter \A_WIDTH 1
92905     parameter \B_SIGNED 0
92906     parameter \B_WIDTH 1
92907     parameter \Y_WIDTH 1
92908     connect \A $and$ls180.v:5970$1435_Y
92909     connect \B $eq$ls180.v:5970$1436_Y
92910     connect \Y $and$ls180.v:5970$1437_Y
92911   end
92912   attribute \src "ls180.v:5989.46-5989.99"
92913   cell $and $and$ls180.v:5989$1439
92914     parameter \A_SIGNED 0
92915     parameter \A_WIDTH 1
92916     parameter \B_SIGNED 0
92917     parameter \B_WIDTH 1
92918     parameter \Y_WIDTH 1
92919     connect \A \builder_csrbank6_sel
92920     connect \B \builder_interface6_bank_bus_we
92921     connect \Y $and$ls180.v:5989$1439_Y
92922   end
92923   attribute \src "ls180.v:5989.45-5989.149"
92924   cell $and $and$ls180.v:5989$1441
92925     parameter \A_SIGNED 0
92926     parameter \A_WIDTH 1
92927     parameter \B_SIGNED 0
92928     parameter \B_WIDTH 1
92929     parameter \Y_WIDTH 1
92930     connect \A $and$ls180.v:5989$1439_Y
92931     connect \B $eq$ls180.v:5989$1440_Y
92932     connect \Y $and$ls180.v:5989$1441_Y
92933   end
92934   attribute \src "ls180.v:5990.46-5990.102"
92935   cell $and $and$ls180.v:5990$1443
92936     parameter \A_SIGNED 0
92937     parameter \A_WIDTH 1
92938     parameter \B_SIGNED 0
92939     parameter \B_WIDTH 1
92940     parameter \Y_WIDTH 1
92941     connect \A \builder_csrbank6_sel
92942     connect \B $not$ls180.v:5990$1442_Y
92943     connect \Y $and$ls180.v:5990$1443_Y
92944   end
92945   attribute \src "ls180.v:5990.45-5990.152"
92946   cell $and $and$ls180.v:5990$1445
92947     parameter \A_SIGNED 0
92948     parameter \A_WIDTH 1
92949     parameter \B_SIGNED 0
92950     parameter \B_WIDTH 1
92951     parameter \Y_WIDTH 1
92952     connect \A $and$ls180.v:5990$1443_Y
92953     connect \B $eq$ls180.v:5990$1444_Y
92954     connect \Y $and$ls180.v:5990$1445_Y
92955   end
92956   attribute \src "ls180.v:5992.46-5992.99"
92957   cell $and $and$ls180.v:5992$1446
92958     parameter \A_SIGNED 0
92959     parameter \A_WIDTH 1
92960     parameter \B_SIGNED 0
92961     parameter \B_WIDTH 1
92962     parameter \Y_WIDTH 1
92963     connect \A \builder_csrbank6_sel
92964     connect \B \builder_interface6_bank_bus_we
92965     connect \Y $and$ls180.v:5992$1446_Y
92966   end
92967   attribute \src "ls180.v:5992.45-5992.149"
92968   cell $and $and$ls180.v:5992$1448
92969     parameter \A_SIGNED 0
92970     parameter \A_WIDTH 1
92971     parameter \B_SIGNED 0
92972     parameter \B_WIDTH 1
92973     parameter \Y_WIDTH 1
92974     connect \A $and$ls180.v:5992$1446_Y
92975     connect \B $eq$ls180.v:5992$1447_Y
92976     connect \Y $and$ls180.v:5992$1448_Y
92977   end
92978   attribute \src "ls180.v:5993.46-5993.102"
92979   cell $and $and$ls180.v:5993$1450
92980     parameter \A_SIGNED 0
92981     parameter \A_WIDTH 1
92982     parameter \B_SIGNED 0
92983     parameter \B_WIDTH 1
92984     parameter \Y_WIDTH 1
92985     connect \A \builder_csrbank6_sel
92986     connect \B $not$ls180.v:5993$1449_Y
92987     connect \Y $and$ls180.v:5993$1450_Y
92988   end
92989   attribute \src "ls180.v:5993.45-5993.152"
92990   cell $and $and$ls180.v:5993$1452
92991     parameter \A_SIGNED 0
92992     parameter \A_WIDTH 1
92993     parameter \B_SIGNED 0
92994     parameter \B_WIDTH 1
92995     parameter \Y_WIDTH 1
92996     connect \A $and$ls180.v:5993$1450_Y
92997     connect \B $eq$ls180.v:5993$1451_Y
92998     connect \Y $and$ls180.v:5993$1452_Y
92999   end
93000   attribute \src "ls180.v:5995.46-5995.99"
93001   cell $and $and$ls180.v:5995$1453
93002     parameter \A_SIGNED 0
93003     parameter \A_WIDTH 1
93004     parameter \B_SIGNED 0
93005     parameter \B_WIDTH 1
93006     parameter \Y_WIDTH 1
93007     connect \A \builder_csrbank6_sel
93008     connect \B \builder_interface6_bank_bus_we
93009     connect \Y $and$ls180.v:5995$1453_Y
93010   end
93011   attribute \src "ls180.v:5995.45-5995.149"
93012   cell $and $and$ls180.v:5995$1455
93013     parameter \A_SIGNED 0
93014     parameter \A_WIDTH 1
93015     parameter \B_SIGNED 0
93016     parameter \B_WIDTH 1
93017     parameter \Y_WIDTH 1
93018     connect \A $and$ls180.v:5995$1453_Y
93019     connect \B $eq$ls180.v:5995$1454_Y
93020     connect \Y $and$ls180.v:5995$1455_Y
93021   end
93022   attribute \src "ls180.v:5996.46-5996.102"
93023   cell $and $and$ls180.v:5996$1457
93024     parameter \A_SIGNED 0
93025     parameter \A_WIDTH 1
93026     parameter \B_SIGNED 0
93027     parameter \B_WIDTH 1
93028     parameter \Y_WIDTH 1
93029     connect \A \builder_csrbank6_sel
93030     connect \B $not$ls180.v:5996$1456_Y
93031     connect \Y $and$ls180.v:5996$1457_Y
93032   end
93033   attribute \src "ls180.v:5996.45-5996.152"
93034   cell $and $and$ls180.v:5996$1459
93035     parameter \A_SIGNED 0
93036     parameter \A_WIDTH 1
93037     parameter \B_SIGNED 0
93038     parameter \B_WIDTH 1
93039     parameter \Y_WIDTH 1
93040     connect \A $and$ls180.v:5996$1457_Y
93041     connect \B $eq$ls180.v:5996$1458_Y
93042     connect \Y $and$ls180.v:5996$1459_Y
93043   end
93044   attribute \src "ls180.v:5998.46-5998.99"
93045   cell $and $and$ls180.v:5998$1460
93046     parameter \A_SIGNED 0
93047     parameter \A_WIDTH 1
93048     parameter \B_SIGNED 0
93049     parameter \B_WIDTH 1
93050     parameter \Y_WIDTH 1
93051     connect \A \builder_csrbank6_sel
93052     connect \B \builder_interface6_bank_bus_we
93053     connect \Y $and$ls180.v:5998$1460_Y
93054   end
93055   attribute \src "ls180.v:5998.45-5998.149"
93056   cell $and $and$ls180.v:5998$1462
93057     parameter \A_SIGNED 0
93058     parameter \A_WIDTH 1
93059     parameter \B_SIGNED 0
93060     parameter \B_WIDTH 1
93061     parameter \Y_WIDTH 1
93062     connect \A $and$ls180.v:5998$1460_Y
93063     connect \B $eq$ls180.v:5998$1461_Y
93064     connect \Y $and$ls180.v:5998$1462_Y
93065   end
93066   attribute \src "ls180.v:5999.46-5999.102"
93067   cell $and $and$ls180.v:5999$1464
93068     parameter \A_SIGNED 0
93069     parameter \A_WIDTH 1
93070     parameter \B_SIGNED 0
93071     parameter \B_WIDTH 1
93072     parameter \Y_WIDTH 1
93073     connect \A \builder_csrbank6_sel
93074     connect \B $not$ls180.v:5999$1463_Y
93075     connect \Y $and$ls180.v:5999$1464_Y
93076   end
93077   attribute \src "ls180.v:5999.45-5999.152"
93078   cell $and $and$ls180.v:5999$1466
93079     parameter \A_SIGNED 0
93080     parameter \A_WIDTH 1
93081     parameter \B_SIGNED 0
93082     parameter \B_WIDTH 1
93083     parameter \Y_WIDTH 1
93084     connect \A $and$ls180.v:5999$1464_Y
93085     connect \B $eq$ls180.v:5999$1465_Y
93086     connect \Y $and$ls180.v:5999$1466_Y
93087   end
93088   attribute \src "ls180.v:6001.45-6001.98"
93089   cell $and $and$ls180.v:6001$1467
93090     parameter \A_SIGNED 0
93091     parameter \A_WIDTH 1
93092     parameter \B_SIGNED 0
93093     parameter \B_WIDTH 1
93094     parameter \Y_WIDTH 1
93095     connect \A \builder_csrbank6_sel
93096     connect \B \builder_interface6_bank_bus_we
93097     connect \Y $and$ls180.v:6001$1467_Y
93098   end
93099   attribute \src "ls180.v:6001.44-6001.148"
93100   cell $and $and$ls180.v:6001$1469
93101     parameter \A_SIGNED 0
93102     parameter \A_WIDTH 1
93103     parameter \B_SIGNED 0
93104     parameter \B_WIDTH 1
93105     parameter \Y_WIDTH 1
93106     connect \A $and$ls180.v:6001$1467_Y
93107     connect \B $eq$ls180.v:6001$1468_Y
93108     connect \Y $and$ls180.v:6001$1469_Y
93109   end
93110   attribute \src "ls180.v:6002.45-6002.101"
93111   cell $and $and$ls180.v:6002$1471
93112     parameter \A_SIGNED 0
93113     parameter \A_WIDTH 1
93114     parameter \B_SIGNED 0
93115     parameter \B_WIDTH 1
93116     parameter \Y_WIDTH 1
93117     connect \A \builder_csrbank6_sel
93118     connect \B $not$ls180.v:6002$1470_Y
93119     connect \Y $and$ls180.v:6002$1471_Y
93120   end
93121   attribute \src "ls180.v:6002.44-6002.151"
93122   cell $and $and$ls180.v:6002$1473
93123     parameter \A_SIGNED 0
93124     parameter \A_WIDTH 1
93125     parameter \B_SIGNED 0
93126     parameter \B_WIDTH 1
93127     parameter \Y_WIDTH 1
93128     connect \A $and$ls180.v:6002$1471_Y
93129     connect \B $eq$ls180.v:6002$1472_Y
93130     connect \Y $and$ls180.v:6002$1473_Y
93131   end
93132   attribute \src "ls180.v:6004.45-6004.98"
93133   cell $and $and$ls180.v:6004$1474
93134     parameter \A_SIGNED 0
93135     parameter \A_WIDTH 1
93136     parameter \B_SIGNED 0
93137     parameter \B_WIDTH 1
93138     parameter \Y_WIDTH 1
93139     connect \A \builder_csrbank6_sel
93140     connect \B \builder_interface6_bank_bus_we
93141     connect \Y $and$ls180.v:6004$1474_Y
93142   end
93143   attribute \src "ls180.v:6004.44-6004.148"
93144   cell $and $and$ls180.v:6004$1476
93145     parameter \A_SIGNED 0
93146     parameter \A_WIDTH 1
93147     parameter \B_SIGNED 0
93148     parameter \B_WIDTH 1
93149     parameter \Y_WIDTH 1
93150     connect \A $and$ls180.v:6004$1474_Y
93151     connect \B $eq$ls180.v:6004$1475_Y
93152     connect \Y $and$ls180.v:6004$1476_Y
93153   end
93154   attribute \src "ls180.v:6005.45-6005.101"
93155   cell $and $and$ls180.v:6005$1478
93156     parameter \A_SIGNED 0
93157     parameter \A_WIDTH 1
93158     parameter \B_SIGNED 0
93159     parameter \B_WIDTH 1
93160     parameter \Y_WIDTH 1
93161     connect \A \builder_csrbank6_sel
93162     connect \B $not$ls180.v:6005$1477_Y
93163     connect \Y $and$ls180.v:6005$1478_Y
93164   end
93165   attribute \src "ls180.v:6005.44-6005.151"
93166   cell $and $and$ls180.v:6005$1480
93167     parameter \A_SIGNED 0
93168     parameter \A_WIDTH 1
93169     parameter \B_SIGNED 0
93170     parameter \B_WIDTH 1
93171     parameter \Y_WIDTH 1
93172     connect \A $and$ls180.v:6005$1478_Y
93173     connect \B $eq$ls180.v:6005$1479_Y
93174     connect \Y $and$ls180.v:6005$1480_Y
93175   end
93176   attribute \src "ls180.v:6007.45-6007.98"
93177   cell $and $and$ls180.v:6007$1481
93178     parameter \A_SIGNED 0
93179     parameter \A_WIDTH 1
93180     parameter \B_SIGNED 0
93181     parameter \B_WIDTH 1
93182     parameter \Y_WIDTH 1
93183     connect \A \builder_csrbank6_sel
93184     connect \B \builder_interface6_bank_bus_we
93185     connect \Y $and$ls180.v:6007$1481_Y
93186   end
93187   attribute \src "ls180.v:6007.44-6007.148"
93188   cell $and $and$ls180.v:6007$1483
93189     parameter \A_SIGNED 0
93190     parameter \A_WIDTH 1
93191     parameter \B_SIGNED 0
93192     parameter \B_WIDTH 1
93193     parameter \Y_WIDTH 1
93194     connect \A $and$ls180.v:6007$1481_Y
93195     connect \B $eq$ls180.v:6007$1482_Y
93196     connect \Y $and$ls180.v:6007$1483_Y
93197   end
93198   attribute \src "ls180.v:6008.45-6008.101"
93199   cell $and $and$ls180.v:6008$1485
93200     parameter \A_SIGNED 0
93201     parameter \A_WIDTH 1
93202     parameter \B_SIGNED 0
93203     parameter \B_WIDTH 1
93204     parameter \Y_WIDTH 1
93205     connect \A \builder_csrbank6_sel
93206     connect \B $not$ls180.v:6008$1484_Y
93207     connect \Y $and$ls180.v:6008$1485_Y
93208   end
93209   attribute \src "ls180.v:6008.44-6008.151"
93210   cell $and $and$ls180.v:6008$1487
93211     parameter \A_SIGNED 0
93212     parameter \A_WIDTH 1
93213     parameter \B_SIGNED 0
93214     parameter \B_WIDTH 1
93215     parameter \Y_WIDTH 1
93216     connect \A $and$ls180.v:6008$1485_Y
93217     connect \B $eq$ls180.v:6008$1486_Y
93218     connect \Y $and$ls180.v:6008$1487_Y
93219   end
93220   attribute \src "ls180.v:6010.45-6010.98"
93221   cell $and $and$ls180.v:6010$1488
93222     parameter \A_SIGNED 0
93223     parameter \A_WIDTH 1
93224     parameter \B_SIGNED 0
93225     parameter \B_WIDTH 1
93226     parameter \Y_WIDTH 1
93227     connect \A \builder_csrbank6_sel
93228     connect \B \builder_interface6_bank_bus_we
93229     connect \Y $and$ls180.v:6010$1488_Y
93230   end
93231   attribute \src "ls180.v:6010.44-6010.148"
93232   cell $and $and$ls180.v:6010$1490
93233     parameter \A_SIGNED 0
93234     parameter \A_WIDTH 1
93235     parameter \B_SIGNED 0
93236     parameter \B_WIDTH 1
93237     parameter \Y_WIDTH 1
93238     connect \A $and$ls180.v:6010$1488_Y
93239     connect \B $eq$ls180.v:6010$1489_Y
93240     connect \Y $and$ls180.v:6010$1490_Y
93241   end
93242   attribute \src "ls180.v:6011.45-6011.101"
93243   cell $and $and$ls180.v:6011$1492
93244     parameter \A_SIGNED 0
93245     parameter \A_WIDTH 1
93246     parameter \B_SIGNED 0
93247     parameter \B_WIDTH 1
93248     parameter \Y_WIDTH 1
93249     connect \A \builder_csrbank6_sel
93250     connect \B $not$ls180.v:6011$1491_Y
93251     connect \Y $and$ls180.v:6011$1492_Y
93252   end
93253   attribute \src "ls180.v:6011.44-6011.151"
93254   cell $and $and$ls180.v:6011$1494
93255     parameter \A_SIGNED 0
93256     parameter \A_WIDTH 1
93257     parameter \B_SIGNED 0
93258     parameter \B_WIDTH 1
93259     parameter \Y_WIDTH 1
93260     connect \A $and$ls180.v:6011$1492_Y
93261     connect \B $eq$ls180.v:6011$1493_Y
93262     connect \Y $and$ls180.v:6011$1494_Y
93263   end
93264   attribute \src "ls180.v:6013.36-6013.89"
93265   cell $and $and$ls180.v:6013$1495
93266     parameter \A_SIGNED 0
93267     parameter \A_WIDTH 1
93268     parameter \B_SIGNED 0
93269     parameter \B_WIDTH 1
93270     parameter \Y_WIDTH 1
93271     connect \A \builder_csrbank6_sel
93272     connect \B \builder_interface6_bank_bus_we
93273     connect \Y $and$ls180.v:6013$1495_Y
93274   end
93275   attribute \src "ls180.v:6013.35-6013.139"
93276   cell $and $and$ls180.v:6013$1497
93277     parameter \A_SIGNED 0
93278     parameter \A_WIDTH 1
93279     parameter \B_SIGNED 0
93280     parameter \B_WIDTH 1
93281     parameter \Y_WIDTH 1
93282     connect \A $and$ls180.v:6013$1495_Y
93283     connect \B $eq$ls180.v:6013$1496_Y
93284     connect \Y $and$ls180.v:6013$1497_Y
93285   end
93286   attribute \src "ls180.v:6014.36-6014.92"
93287   cell $and $and$ls180.v:6014$1499
93288     parameter \A_SIGNED 0
93289     parameter \A_WIDTH 1
93290     parameter \B_SIGNED 0
93291     parameter \B_WIDTH 1
93292     parameter \Y_WIDTH 1
93293     connect \A \builder_csrbank6_sel
93294     connect \B $not$ls180.v:6014$1498_Y
93295     connect \Y $and$ls180.v:6014$1499_Y
93296   end
93297   attribute \src "ls180.v:6014.35-6014.142"
93298   cell $and $and$ls180.v:6014$1501
93299     parameter \A_SIGNED 0
93300     parameter \A_WIDTH 1
93301     parameter \B_SIGNED 0
93302     parameter \B_WIDTH 1
93303     parameter \Y_WIDTH 1
93304     connect \A $and$ls180.v:6014$1499_Y
93305     connect \B $eq$ls180.v:6014$1500_Y
93306     connect \Y $and$ls180.v:6014$1501_Y
93307   end
93308   attribute \src "ls180.v:6016.47-6016.100"
93309   cell $and $and$ls180.v:6016$1502
93310     parameter \A_SIGNED 0
93311     parameter \A_WIDTH 1
93312     parameter \B_SIGNED 0
93313     parameter \B_WIDTH 1
93314     parameter \Y_WIDTH 1
93315     connect \A \builder_csrbank6_sel
93316     connect \B \builder_interface6_bank_bus_we
93317     connect \Y $and$ls180.v:6016$1502_Y
93318   end
93319   attribute \src "ls180.v:6016.46-6016.150"
93320   cell $and $and$ls180.v:6016$1504
93321     parameter \A_SIGNED 0
93322     parameter \A_WIDTH 1
93323     parameter \B_SIGNED 0
93324     parameter \B_WIDTH 1
93325     parameter \Y_WIDTH 1
93326     connect \A $and$ls180.v:6016$1502_Y
93327     connect \B $eq$ls180.v:6016$1503_Y
93328     connect \Y $and$ls180.v:6016$1504_Y
93329   end
93330   attribute \src "ls180.v:6017.47-6017.103"
93331   cell $and $and$ls180.v:6017$1506
93332     parameter \A_SIGNED 0
93333     parameter \A_WIDTH 1
93334     parameter \B_SIGNED 0
93335     parameter \B_WIDTH 1
93336     parameter \Y_WIDTH 1
93337     connect \A \builder_csrbank6_sel
93338     connect \B $not$ls180.v:6017$1505_Y
93339     connect \Y $and$ls180.v:6017$1506_Y
93340   end
93341   attribute \src "ls180.v:6017.46-6017.153"
93342   cell $and $and$ls180.v:6017$1508
93343     parameter \A_SIGNED 0
93344     parameter \A_WIDTH 1
93345     parameter \B_SIGNED 0
93346     parameter \B_WIDTH 1
93347     parameter \Y_WIDTH 1
93348     connect \A $and$ls180.v:6017$1506_Y
93349     connect \B $eq$ls180.v:6017$1507_Y
93350     connect \Y $and$ls180.v:6017$1508_Y
93351   end
93352   attribute \src "ls180.v:6019.47-6019.100"
93353   cell $and $and$ls180.v:6019$1509
93354     parameter \A_SIGNED 0
93355     parameter \A_WIDTH 1
93356     parameter \B_SIGNED 0
93357     parameter \B_WIDTH 1
93358     parameter \Y_WIDTH 1
93359     connect \A \builder_csrbank6_sel
93360     connect \B \builder_interface6_bank_bus_we
93361     connect \Y $and$ls180.v:6019$1509_Y
93362   end
93363   attribute \src "ls180.v:6019.46-6019.151"
93364   cell $and $and$ls180.v:6019$1511
93365     parameter \A_SIGNED 0
93366     parameter \A_WIDTH 1
93367     parameter \B_SIGNED 0
93368     parameter \B_WIDTH 1
93369     parameter \Y_WIDTH 1
93370     connect \A $and$ls180.v:6019$1509_Y
93371     connect \B $eq$ls180.v:6019$1510_Y
93372     connect \Y $and$ls180.v:6019$1511_Y
93373   end
93374   attribute \src "ls180.v:6020.47-6020.103"
93375   cell $and $and$ls180.v:6020$1513
93376     parameter \A_SIGNED 0
93377     parameter \A_WIDTH 1
93378     parameter \B_SIGNED 0
93379     parameter \B_WIDTH 1
93380     parameter \Y_WIDTH 1
93381     connect \A \builder_csrbank6_sel
93382     connect \B $not$ls180.v:6020$1512_Y
93383     connect \Y $and$ls180.v:6020$1513_Y
93384   end
93385   attribute \src "ls180.v:6020.46-6020.154"
93386   cell $and $and$ls180.v:6020$1515
93387     parameter \A_SIGNED 0
93388     parameter \A_WIDTH 1
93389     parameter \B_SIGNED 0
93390     parameter \B_WIDTH 1
93391     parameter \Y_WIDTH 1
93392     connect \A $and$ls180.v:6020$1513_Y
93393     connect \B $eq$ls180.v:6020$1514_Y
93394     connect \Y $and$ls180.v:6020$1515_Y
93395   end
93396   attribute \src "ls180.v:6022.47-6022.100"
93397   cell $and $and$ls180.v:6022$1516
93398     parameter \A_SIGNED 0
93399     parameter \A_WIDTH 1
93400     parameter \B_SIGNED 0
93401     parameter \B_WIDTH 1
93402     parameter \Y_WIDTH 1
93403     connect \A \builder_csrbank6_sel
93404     connect \B \builder_interface6_bank_bus_we
93405     connect \Y $and$ls180.v:6022$1516_Y
93406   end
93407   attribute \src "ls180.v:6022.46-6022.151"
93408   cell $and $and$ls180.v:6022$1518
93409     parameter \A_SIGNED 0
93410     parameter \A_WIDTH 1
93411     parameter \B_SIGNED 0
93412     parameter \B_WIDTH 1
93413     parameter \Y_WIDTH 1
93414     connect \A $and$ls180.v:6022$1516_Y
93415     connect \B $eq$ls180.v:6022$1517_Y
93416     connect \Y $and$ls180.v:6022$1518_Y
93417   end
93418   attribute \src "ls180.v:6023.47-6023.103"
93419   cell $and $and$ls180.v:6023$1520
93420     parameter \A_SIGNED 0
93421     parameter \A_WIDTH 1
93422     parameter \B_SIGNED 0
93423     parameter \B_WIDTH 1
93424     parameter \Y_WIDTH 1
93425     connect \A \builder_csrbank6_sel
93426     connect \B $not$ls180.v:6023$1519_Y
93427     connect \Y $and$ls180.v:6023$1520_Y
93428   end
93429   attribute \src "ls180.v:6023.46-6023.154"
93430   cell $and $and$ls180.v:6023$1522
93431     parameter \A_SIGNED 0
93432     parameter \A_WIDTH 1
93433     parameter \B_SIGNED 0
93434     parameter \B_WIDTH 1
93435     parameter \Y_WIDTH 1
93436     connect \A $and$ls180.v:6023$1520_Y
93437     connect \B $eq$ls180.v:6023$1521_Y
93438     connect \Y $and$ls180.v:6023$1522_Y
93439   end
93440   attribute \src "ls180.v:6025.47-6025.100"
93441   cell $and $and$ls180.v:6025$1523
93442     parameter \A_SIGNED 0
93443     parameter \A_WIDTH 1
93444     parameter \B_SIGNED 0
93445     parameter \B_WIDTH 1
93446     parameter \Y_WIDTH 1
93447     connect \A \builder_csrbank6_sel
93448     connect \B \builder_interface6_bank_bus_we
93449     connect \Y $and$ls180.v:6025$1523_Y
93450   end
93451   attribute \src "ls180.v:6025.46-6025.151"
93452   cell $and $and$ls180.v:6025$1525
93453     parameter \A_SIGNED 0
93454     parameter \A_WIDTH 1
93455     parameter \B_SIGNED 0
93456     parameter \B_WIDTH 1
93457     parameter \Y_WIDTH 1
93458     connect \A $and$ls180.v:6025$1523_Y
93459     connect \B $eq$ls180.v:6025$1524_Y
93460     connect \Y $and$ls180.v:6025$1525_Y
93461   end
93462   attribute \src "ls180.v:6026.47-6026.103"
93463   cell $and $and$ls180.v:6026$1527
93464     parameter \A_SIGNED 0
93465     parameter \A_WIDTH 1
93466     parameter \B_SIGNED 0
93467     parameter \B_WIDTH 1
93468     parameter \Y_WIDTH 1
93469     connect \A \builder_csrbank6_sel
93470     connect \B $not$ls180.v:6026$1526_Y
93471     connect \Y $and$ls180.v:6026$1527_Y
93472   end
93473   attribute \src "ls180.v:6026.46-6026.154"
93474   cell $and $and$ls180.v:6026$1529
93475     parameter \A_SIGNED 0
93476     parameter \A_WIDTH 1
93477     parameter \B_SIGNED 0
93478     parameter \B_WIDTH 1
93479     parameter \Y_WIDTH 1
93480     connect \A $and$ls180.v:6026$1527_Y
93481     connect \B $eq$ls180.v:6026$1528_Y
93482     connect \Y $and$ls180.v:6026$1529_Y
93483   end
93484   attribute \src "ls180.v:6028.47-6028.100"
93485   cell $and $and$ls180.v:6028$1530
93486     parameter \A_SIGNED 0
93487     parameter \A_WIDTH 1
93488     parameter \B_SIGNED 0
93489     parameter \B_WIDTH 1
93490     parameter \Y_WIDTH 1
93491     connect \A \builder_csrbank6_sel
93492     connect \B \builder_interface6_bank_bus_we
93493     connect \Y $and$ls180.v:6028$1530_Y
93494   end
93495   attribute \src "ls180.v:6028.46-6028.151"
93496   cell $and $and$ls180.v:6028$1532
93497     parameter \A_SIGNED 0
93498     parameter \A_WIDTH 1
93499     parameter \B_SIGNED 0
93500     parameter \B_WIDTH 1
93501     parameter \Y_WIDTH 1
93502     connect \A $and$ls180.v:6028$1530_Y
93503     connect \B $eq$ls180.v:6028$1531_Y
93504     connect \Y $and$ls180.v:6028$1532_Y
93505   end
93506   attribute \src "ls180.v:6029.47-6029.103"
93507   cell $and $and$ls180.v:6029$1534
93508     parameter \A_SIGNED 0
93509     parameter \A_WIDTH 1
93510     parameter \B_SIGNED 0
93511     parameter \B_WIDTH 1
93512     parameter \Y_WIDTH 1
93513     connect \A \builder_csrbank6_sel
93514     connect \B $not$ls180.v:6029$1533_Y
93515     connect \Y $and$ls180.v:6029$1534_Y
93516   end
93517   attribute \src "ls180.v:6029.46-6029.154"
93518   cell $and $and$ls180.v:6029$1536
93519     parameter \A_SIGNED 0
93520     parameter \A_WIDTH 1
93521     parameter \B_SIGNED 0
93522     parameter \B_WIDTH 1
93523     parameter \Y_WIDTH 1
93524     connect \A $and$ls180.v:6029$1534_Y
93525     connect \B $eq$ls180.v:6029$1535_Y
93526     connect \Y $and$ls180.v:6029$1536_Y
93527   end
93528   attribute \src "ls180.v:6031.47-6031.100"
93529   cell $and $and$ls180.v:6031$1537
93530     parameter \A_SIGNED 0
93531     parameter \A_WIDTH 1
93532     parameter \B_SIGNED 0
93533     parameter \B_WIDTH 1
93534     parameter \Y_WIDTH 1
93535     connect \A \builder_csrbank6_sel
93536     connect \B \builder_interface6_bank_bus_we
93537     connect \Y $and$ls180.v:6031$1537_Y
93538   end
93539   attribute \src "ls180.v:6031.46-6031.151"
93540   cell $and $and$ls180.v:6031$1539
93541     parameter \A_SIGNED 0
93542     parameter \A_WIDTH 1
93543     parameter \B_SIGNED 0
93544     parameter \B_WIDTH 1
93545     parameter \Y_WIDTH 1
93546     connect \A $and$ls180.v:6031$1537_Y
93547     connect \B $eq$ls180.v:6031$1538_Y
93548     connect \Y $and$ls180.v:6031$1539_Y
93549   end
93550   attribute \src "ls180.v:6032.47-6032.103"
93551   cell $and $and$ls180.v:6032$1541
93552     parameter \A_SIGNED 0
93553     parameter \A_WIDTH 1
93554     parameter \B_SIGNED 0
93555     parameter \B_WIDTH 1
93556     parameter \Y_WIDTH 1
93557     connect \A \builder_csrbank6_sel
93558     connect \B $not$ls180.v:6032$1540_Y
93559     connect \Y $and$ls180.v:6032$1541_Y
93560   end
93561   attribute \src "ls180.v:6032.46-6032.154"
93562   cell $and $and$ls180.v:6032$1543
93563     parameter \A_SIGNED 0
93564     parameter \A_WIDTH 1
93565     parameter \B_SIGNED 0
93566     parameter \B_WIDTH 1
93567     parameter \Y_WIDTH 1
93568     connect \A $and$ls180.v:6032$1541_Y
93569     connect \B $eq$ls180.v:6032$1542_Y
93570     connect \Y $and$ls180.v:6032$1543_Y
93571   end
93572   attribute \src "ls180.v:6034.46-6034.99"
93573   cell $and $and$ls180.v:6034$1544
93574     parameter \A_SIGNED 0
93575     parameter \A_WIDTH 1
93576     parameter \B_SIGNED 0
93577     parameter \B_WIDTH 1
93578     parameter \Y_WIDTH 1
93579     connect \A \builder_csrbank6_sel
93580     connect \B \builder_interface6_bank_bus_we
93581     connect \Y $and$ls180.v:6034$1544_Y
93582   end
93583   attribute \src "ls180.v:6034.45-6034.150"
93584   cell $and $and$ls180.v:6034$1546
93585     parameter \A_SIGNED 0
93586     parameter \A_WIDTH 1
93587     parameter \B_SIGNED 0
93588     parameter \B_WIDTH 1
93589     parameter \Y_WIDTH 1
93590     connect \A $and$ls180.v:6034$1544_Y
93591     connect \B $eq$ls180.v:6034$1545_Y
93592     connect \Y $and$ls180.v:6034$1546_Y
93593   end
93594   attribute \src "ls180.v:6035.46-6035.102"
93595   cell $and $and$ls180.v:6035$1548
93596     parameter \A_SIGNED 0
93597     parameter \A_WIDTH 1
93598     parameter \B_SIGNED 0
93599     parameter \B_WIDTH 1
93600     parameter \Y_WIDTH 1
93601     connect \A \builder_csrbank6_sel
93602     connect \B $not$ls180.v:6035$1547_Y
93603     connect \Y $and$ls180.v:6035$1548_Y
93604   end
93605   attribute \src "ls180.v:6035.45-6035.153"
93606   cell $and $and$ls180.v:6035$1550
93607     parameter \A_SIGNED 0
93608     parameter \A_WIDTH 1
93609     parameter \B_SIGNED 0
93610     parameter \B_WIDTH 1
93611     parameter \Y_WIDTH 1
93612     connect \A $and$ls180.v:6035$1548_Y
93613     connect \B $eq$ls180.v:6035$1549_Y
93614     connect \Y $and$ls180.v:6035$1550_Y
93615   end
93616   attribute \src "ls180.v:6037.46-6037.99"
93617   cell $and $and$ls180.v:6037$1551
93618     parameter \A_SIGNED 0
93619     parameter \A_WIDTH 1
93620     parameter \B_SIGNED 0
93621     parameter \B_WIDTH 1
93622     parameter \Y_WIDTH 1
93623     connect \A \builder_csrbank6_sel
93624     connect \B \builder_interface6_bank_bus_we
93625     connect \Y $and$ls180.v:6037$1551_Y
93626   end
93627   attribute \src "ls180.v:6037.45-6037.150"
93628   cell $and $and$ls180.v:6037$1553
93629     parameter \A_SIGNED 0
93630     parameter \A_WIDTH 1
93631     parameter \B_SIGNED 0
93632     parameter \B_WIDTH 1
93633     parameter \Y_WIDTH 1
93634     connect \A $and$ls180.v:6037$1551_Y
93635     connect \B $eq$ls180.v:6037$1552_Y
93636     connect \Y $and$ls180.v:6037$1553_Y
93637   end
93638   attribute \src "ls180.v:6038.46-6038.102"
93639   cell $and $and$ls180.v:6038$1555
93640     parameter \A_SIGNED 0
93641     parameter \A_WIDTH 1
93642     parameter \B_SIGNED 0
93643     parameter \B_WIDTH 1
93644     parameter \Y_WIDTH 1
93645     connect \A \builder_csrbank6_sel
93646     connect \B $not$ls180.v:6038$1554_Y
93647     connect \Y $and$ls180.v:6038$1555_Y
93648   end
93649   attribute \src "ls180.v:6038.45-6038.153"
93650   cell $and $and$ls180.v:6038$1557
93651     parameter \A_SIGNED 0
93652     parameter \A_WIDTH 1
93653     parameter \B_SIGNED 0
93654     parameter \B_WIDTH 1
93655     parameter \Y_WIDTH 1
93656     connect \A $and$ls180.v:6038$1555_Y
93657     connect \B $eq$ls180.v:6038$1556_Y
93658     connect \Y $and$ls180.v:6038$1557_Y
93659   end
93660   attribute \src "ls180.v:6040.46-6040.99"
93661   cell $and $and$ls180.v:6040$1558
93662     parameter \A_SIGNED 0
93663     parameter \A_WIDTH 1
93664     parameter \B_SIGNED 0
93665     parameter \B_WIDTH 1
93666     parameter \Y_WIDTH 1
93667     connect \A \builder_csrbank6_sel
93668     connect \B \builder_interface6_bank_bus_we
93669     connect \Y $and$ls180.v:6040$1558_Y
93670   end
93671   attribute \src "ls180.v:6040.45-6040.150"
93672   cell $and $and$ls180.v:6040$1560
93673     parameter \A_SIGNED 0
93674     parameter \A_WIDTH 1
93675     parameter \B_SIGNED 0
93676     parameter \B_WIDTH 1
93677     parameter \Y_WIDTH 1
93678     connect \A $and$ls180.v:6040$1558_Y
93679     connect \B $eq$ls180.v:6040$1559_Y
93680     connect \Y $and$ls180.v:6040$1560_Y
93681   end
93682   attribute \src "ls180.v:6041.46-6041.102"
93683   cell $and $and$ls180.v:6041$1562
93684     parameter \A_SIGNED 0
93685     parameter \A_WIDTH 1
93686     parameter \B_SIGNED 0
93687     parameter \B_WIDTH 1
93688     parameter \Y_WIDTH 1
93689     connect \A \builder_csrbank6_sel
93690     connect \B $not$ls180.v:6041$1561_Y
93691     connect \Y $and$ls180.v:6041$1562_Y
93692   end
93693   attribute \src "ls180.v:6041.45-6041.153"
93694   cell $and $and$ls180.v:6041$1564
93695     parameter \A_SIGNED 0
93696     parameter \A_WIDTH 1
93697     parameter \B_SIGNED 0
93698     parameter \B_WIDTH 1
93699     parameter \Y_WIDTH 1
93700     connect \A $and$ls180.v:6041$1562_Y
93701     connect \B $eq$ls180.v:6041$1563_Y
93702     connect \Y $and$ls180.v:6041$1564_Y
93703   end
93704   attribute \src "ls180.v:6043.46-6043.99"
93705   cell $and $and$ls180.v:6043$1565
93706     parameter \A_SIGNED 0
93707     parameter \A_WIDTH 1
93708     parameter \B_SIGNED 0
93709     parameter \B_WIDTH 1
93710     parameter \Y_WIDTH 1
93711     connect \A \builder_csrbank6_sel
93712     connect \B \builder_interface6_bank_bus_we
93713     connect \Y $and$ls180.v:6043$1565_Y
93714   end
93715   attribute \src "ls180.v:6043.45-6043.150"
93716   cell $and $and$ls180.v:6043$1567
93717     parameter \A_SIGNED 0
93718     parameter \A_WIDTH 1
93719     parameter \B_SIGNED 0
93720     parameter \B_WIDTH 1
93721     parameter \Y_WIDTH 1
93722     connect \A $and$ls180.v:6043$1565_Y
93723     connect \B $eq$ls180.v:6043$1566_Y
93724     connect \Y $and$ls180.v:6043$1567_Y
93725   end
93726   attribute \src "ls180.v:6044.46-6044.102"
93727   cell $and $and$ls180.v:6044$1569
93728     parameter \A_SIGNED 0
93729     parameter \A_WIDTH 1
93730     parameter \B_SIGNED 0
93731     parameter \B_WIDTH 1
93732     parameter \Y_WIDTH 1
93733     connect \A \builder_csrbank6_sel
93734     connect \B $not$ls180.v:6044$1568_Y
93735     connect \Y $and$ls180.v:6044$1569_Y
93736   end
93737   attribute \src "ls180.v:6044.45-6044.153"
93738   cell $and $and$ls180.v:6044$1571
93739     parameter \A_SIGNED 0
93740     parameter \A_WIDTH 1
93741     parameter \B_SIGNED 0
93742     parameter \B_WIDTH 1
93743     parameter \Y_WIDTH 1
93744     connect \A $and$ls180.v:6044$1569_Y
93745     connect \B $eq$ls180.v:6044$1570_Y
93746     connect \Y $and$ls180.v:6044$1571_Y
93747   end
93748   attribute \src "ls180.v:6046.46-6046.99"
93749   cell $and $and$ls180.v:6046$1572
93750     parameter \A_SIGNED 0
93751     parameter \A_WIDTH 1
93752     parameter \B_SIGNED 0
93753     parameter \B_WIDTH 1
93754     parameter \Y_WIDTH 1
93755     connect \A \builder_csrbank6_sel
93756     connect \B \builder_interface6_bank_bus_we
93757     connect \Y $and$ls180.v:6046$1572_Y
93758   end
93759   attribute \src "ls180.v:6046.45-6046.150"
93760   cell $and $and$ls180.v:6046$1574
93761     parameter \A_SIGNED 0
93762     parameter \A_WIDTH 1
93763     parameter \B_SIGNED 0
93764     parameter \B_WIDTH 1
93765     parameter \Y_WIDTH 1
93766     connect \A $and$ls180.v:6046$1572_Y
93767     connect \B $eq$ls180.v:6046$1573_Y
93768     connect \Y $and$ls180.v:6046$1574_Y
93769   end
93770   attribute \src "ls180.v:6047.46-6047.102"
93771   cell $and $and$ls180.v:6047$1576
93772     parameter \A_SIGNED 0
93773     parameter \A_WIDTH 1
93774     parameter \B_SIGNED 0
93775     parameter \B_WIDTH 1
93776     parameter \Y_WIDTH 1
93777     connect \A \builder_csrbank6_sel
93778     connect \B $not$ls180.v:6047$1575_Y
93779     connect \Y $and$ls180.v:6047$1576_Y
93780   end
93781   attribute \src "ls180.v:6047.45-6047.153"
93782   cell $and $and$ls180.v:6047$1578
93783     parameter \A_SIGNED 0
93784     parameter \A_WIDTH 1
93785     parameter \B_SIGNED 0
93786     parameter \B_WIDTH 1
93787     parameter \Y_WIDTH 1
93788     connect \A $and$ls180.v:6047$1576_Y
93789     connect \B $eq$ls180.v:6047$1577_Y
93790     connect \Y $and$ls180.v:6047$1578_Y
93791   end
93792   attribute \src "ls180.v:6049.46-6049.99"
93793   cell $and $and$ls180.v:6049$1579
93794     parameter \A_SIGNED 0
93795     parameter \A_WIDTH 1
93796     parameter \B_SIGNED 0
93797     parameter \B_WIDTH 1
93798     parameter \Y_WIDTH 1
93799     connect \A \builder_csrbank6_sel
93800     connect \B \builder_interface6_bank_bus_we
93801     connect \Y $and$ls180.v:6049$1579_Y
93802   end
93803   attribute \src "ls180.v:6049.45-6049.150"
93804   cell $and $and$ls180.v:6049$1581
93805     parameter \A_SIGNED 0
93806     parameter \A_WIDTH 1
93807     parameter \B_SIGNED 0
93808     parameter \B_WIDTH 1
93809     parameter \Y_WIDTH 1
93810     connect \A $and$ls180.v:6049$1579_Y
93811     connect \B $eq$ls180.v:6049$1580_Y
93812     connect \Y $and$ls180.v:6049$1581_Y
93813   end
93814   attribute \src "ls180.v:6050.46-6050.102"
93815   cell $and $and$ls180.v:6050$1583
93816     parameter \A_SIGNED 0
93817     parameter \A_WIDTH 1
93818     parameter \B_SIGNED 0
93819     parameter \B_WIDTH 1
93820     parameter \Y_WIDTH 1
93821     connect \A \builder_csrbank6_sel
93822     connect \B $not$ls180.v:6050$1582_Y
93823     connect \Y $and$ls180.v:6050$1583_Y
93824   end
93825   attribute \src "ls180.v:6050.45-6050.153"
93826   cell $and $and$ls180.v:6050$1585
93827     parameter \A_SIGNED 0
93828     parameter \A_WIDTH 1
93829     parameter \B_SIGNED 0
93830     parameter \B_WIDTH 1
93831     parameter \Y_WIDTH 1
93832     connect \A $and$ls180.v:6050$1583_Y
93833     connect \B $eq$ls180.v:6050$1584_Y
93834     connect \Y $and$ls180.v:6050$1585_Y
93835   end
93836   attribute \src "ls180.v:6052.46-6052.99"
93837   cell $and $and$ls180.v:6052$1586
93838     parameter \A_SIGNED 0
93839     parameter \A_WIDTH 1
93840     parameter \B_SIGNED 0
93841     parameter \B_WIDTH 1
93842     parameter \Y_WIDTH 1
93843     connect \A \builder_csrbank6_sel
93844     connect \B \builder_interface6_bank_bus_we
93845     connect \Y $and$ls180.v:6052$1586_Y
93846   end
93847   attribute \src "ls180.v:6052.45-6052.150"
93848   cell $and $and$ls180.v:6052$1588
93849     parameter \A_SIGNED 0
93850     parameter \A_WIDTH 1
93851     parameter \B_SIGNED 0
93852     parameter \B_WIDTH 1
93853     parameter \Y_WIDTH 1
93854     connect \A $and$ls180.v:6052$1586_Y
93855     connect \B $eq$ls180.v:6052$1587_Y
93856     connect \Y $and$ls180.v:6052$1588_Y
93857   end
93858   attribute \src "ls180.v:6053.46-6053.102"
93859   cell $and $and$ls180.v:6053$1590
93860     parameter \A_SIGNED 0
93861     parameter \A_WIDTH 1
93862     parameter \B_SIGNED 0
93863     parameter \B_WIDTH 1
93864     parameter \Y_WIDTH 1
93865     connect \A \builder_csrbank6_sel
93866     connect \B $not$ls180.v:6053$1589_Y
93867     connect \Y $and$ls180.v:6053$1590_Y
93868   end
93869   attribute \src "ls180.v:6053.45-6053.153"
93870   cell $and $and$ls180.v:6053$1592
93871     parameter \A_SIGNED 0
93872     parameter \A_WIDTH 1
93873     parameter \B_SIGNED 0
93874     parameter \B_WIDTH 1
93875     parameter \Y_WIDTH 1
93876     connect \A $and$ls180.v:6053$1590_Y
93877     connect \B $eq$ls180.v:6053$1591_Y
93878     connect \Y $and$ls180.v:6053$1592_Y
93879   end
93880   attribute \src "ls180.v:6055.46-6055.99"
93881   cell $and $and$ls180.v:6055$1593
93882     parameter \A_SIGNED 0
93883     parameter \A_WIDTH 1
93884     parameter \B_SIGNED 0
93885     parameter \B_WIDTH 1
93886     parameter \Y_WIDTH 1
93887     connect \A \builder_csrbank6_sel
93888     connect \B \builder_interface6_bank_bus_we
93889     connect \Y $and$ls180.v:6055$1593_Y
93890   end
93891   attribute \src "ls180.v:6055.45-6055.150"
93892   cell $and $and$ls180.v:6055$1595
93893     parameter \A_SIGNED 0
93894     parameter \A_WIDTH 1
93895     parameter \B_SIGNED 0
93896     parameter \B_WIDTH 1
93897     parameter \Y_WIDTH 1
93898     connect \A $and$ls180.v:6055$1593_Y
93899     connect \B $eq$ls180.v:6055$1594_Y
93900     connect \Y $and$ls180.v:6055$1595_Y
93901   end
93902   attribute \src "ls180.v:6056.46-6056.102"
93903   cell $and $and$ls180.v:6056$1597
93904     parameter \A_SIGNED 0
93905     parameter \A_WIDTH 1
93906     parameter \B_SIGNED 0
93907     parameter \B_WIDTH 1
93908     parameter \Y_WIDTH 1
93909     connect \A \builder_csrbank6_sel
93910     connect \B $not$ls180.v:6056$1596_Y
93911     connect \Y $and$ls180.v:6056$1597_Y
93912   end
93913   attribute \src "ls180.v:6056.45-6056.153"
93914   cell $and $and$ls180.v:6056$1599
93915     parameter \A_SIGNED 0
93916     parameter \A_WIDTH 1
93917     parameter \B_SIGNED 0
93918     parameter \B_WIDTH 1
93919     parameter \Y_WIDTH 1
93920     connect \A $and$ls180.v:6056$1597_Y
93921     connect \B $eq$ls180.v:6056$1598_Y
93922     connect \Y $and$ls180.v:6056$1599_Y
93923   end
93924   attribute \src "ls180.v:6058.46-6058.99"
93925   cell $and $and$ls180.v:6058$1600
93926     parameter \A_SIGNED 0
93927     parameter \A_WIDTH 1
93928     parameter \B_SIGNED 0
93929     parameter \B_WIDTH 1
93930     parameter \Y_WIDTH 1
93931     connect \A \builder_csrbank6_sel
93932     connect \B \builder_interface6_bank_bus_we
93933     connect \Y $and$ls180.v:6058$1600_Y
93934   end
93935   attribute \src "ls180.v:6058.45-6058.150"
93936   cell $and $and$ls180.v:6058$1602
93937     parameter \A_SIGNED 0
93938     parameter \A_WIDTH 1
93939     parameter \B_SIGNED 0
93940     parameter \B_WIDTH 1
93941     parameter \Y_WIDTH 1
93942     connect \A $and$ls180.v:6058$1600_Y
93943     connect \B $eq$ls180.v:6058$1601_Y
93944     connect \Y $and$ls180.v:6058$1602_Y
93945   end
93946   attribute \src "ls180.v:6059.46-6059.102"
93947   cell $and $and$ls180.v:6059$1604
93948     parameter \A_SIGNED 0
93949     parameter \A_WIDTH 1
93950     parameter \B_SIGNED 0
93951     parameter \B_WIDTH 1
93952     parameter \Y_WIDTH 1
93953     connect \A \builder_csrbank6_sel
93954     connect \B $not$ls180.v:6059$1603_Y
93955     connect \Y $and$ls180.v:6059$1604_Y
93956   end
93957   attribute \src "ls180.v:6059.45-6059.153"
93958   cell $and $and$ls180.v:6059$1606
93959     parameter \A_SIGNED 0
93960     parameter \A_WIDTH 1
93961     parameter \B_SIGNED 0
93962     parameter \B_WIDTH 1
93963     parameter \Y_WIDTH 1
93964     connect \A $and$ls180.v:6059$1604_Y
93965     connect \B $eq$ls180.v:6059$1605_Y
93966     connect \Y $and$ls180.v:6059$1606_Y
93967   end
93968   attribute \src "ls180.v:6061.46-6061.99"
93969   cell $and $and$ls180.v:6061$1607
93970     parameter \A_SIGNED 0
93971     parameter \A_WIDTH 1
93972     parameter \B_SIGNED 0
93973     parameter \B_WIDTH 1
93974     parameter \Y_WIDTH 1
93975     connect \A \builder_csrbank6_sel
93976     connect \B \builder_interface6_bank_bus_we
93977     connect \Y $and$ls180.v:6061$1607_Y
93978   end
93979   attribute \src "ls180.v:6061.45-6061.150"
93980   cell $and $and$ls180.v:6061$1609
93981     parameter \A_SIGNED 0
93982     parameter \A_WIDTH 1
93983     parameter \B_SIGNED 0
93984     parameter \B_WIDTH 1
93985     parameter \Y_WIDTH 1
93986     connect \A $and$ls180.v:6061$1607_Y
93987     connect \B $eq$ls180.v:6061$1608_Y
93988     connect \Y $and$ls180.v:6061$1609_Y
93989   end
93990   attribute \src "ls180.v:6062.46-6062.102"
93991   cell $and $and$ls180.v:6062$1611
93992     parameter \A_SIGNED 0
93993     parameter \A_WIDTH 1
93994     parameter \B_SIGNED 0
93995     parameter \B_WIDTH 1
93996     parameter \Y_WIDTH 1
93997     connect \A \builder_csrbank6_sel
93998     connect \B $not$ls180.v:6062$1610_Y
93999     connect \Y $and$ls180.v:6062$1611_Y
94000   end
94001   attribute \src "ls180.v:6062.45-6062.153"
94002   cell $and $and$ls180.v:6062$1613
94003     parameter \A_SIGNED 0
94004     parameter \A_WIDTH 1
94005     parameter \B_SIGNED 0
94006     parameter \B_WIDTH 1
94007     parameter \Y_WIDTH 1
94008     connect \A $and$ls180.v:6062$1611_Y
94009     connect \B $eq$ls180.v:6062$1612_Y
94010     connect \Y $and$ls180.v:6062$1613_Y
94011   end
94012   attribute \src "ls180.v:6064.42-6064.95"
94013   cell $and $and$ls180.v:6064$1614
94014     parameter \A_SIGNED 0
94015     parameter \A_WIDTH 1
94016     parameter \B_SIGNED 0
94017     parameter \B_WIDTH 1
94018     parameter \Y_WIDTH 1
94019     connect \A \builder_csrbank6_sel
94020     connect \B \builder_interface6_bank_bus_we
94021     connect \Y $and$ls180.v:6064$1614_Y
94022   end
94023   attribute \src "ls180.v:6064.41-6064.146"
94024   cell $and $and$ls180.v:6064$1616
94025     parameter \A_SIGNED 0
94026     parameter \A_WIDTH 1
94027     parameter \B_SIGNED 0
94028     parameter \B_WIDTH 1
94029     parameter \Y_WIDTH 1
94030     connect \A $and$ls180.v:6064$1614_Y
94031     connect \B $eq$ls180.v:6064$1615_Y
94032     connect \Y $and$ls180.v:6064$1616_Y
94033   end
94034   attribute \src "ls180.v:6065.42-6065.98"
94035   cell $and $and$ls180.v:6065$1618
94036     parameter \A_SIGNED 0
94037     parameter \A_WIDTH 1
94038     parameter \B_SIGNED 0
94039     parameter \B_WIDTH 1
94040     parameter \Y_WIDTH 1
94041     connect \A \builder_csrbank6_sel
94042     connect \B $not$ls180.v:6065$1617_Y
94043     connect \Y $and$ls180.v:6065$1618_Y
94044   end
94045   attribute \src "ls180.v:6065.41-6065.149"
94046   cell $and $and$ls180.v:6065$1620
94047     parameter \A_SIGNED 0
94048     parameter \A_WIDTH 1
94049     parameter \B_SIGNED 0
94050     parameter \B_WIDTH 1
94051     parameter \Y_WIDTH 1
94052     connect \A $and$ls180.v:6065$1618_Y
94053     connect \B $eq$ls180.v:6065$1619_Y
94054     connect \Y $and$ls180.v:6065$1620_Y
94055   end
94056   attribute \src "ls180.v:6067.43-6067.96"
94057   cell $and $and$ls180.v:6067$1621
94058     parameter \A_SIGNED 0
94059     parameter \A_WIDTH 1
94060     parameter \B_SIGNED 0
94061     parameter \B_WIDTH 1
94062     parameter \Y_WIDTH 1
94063     connect \A \builder_csrbank6_sel
94064     connect \B \builder_interface6_bank_bus_we
94065     connect \Y $and$ls180.v:6067$1621_Y
94066   end
94067   attribute \src "ls180.v:6067.42-6067.147"
94068   cell $and $and$ls180.v:6067$1623
94069     parameter \A_SIGNED 0
94070     parameter \A_WIDTH 1
94071     parameter \B_SIGNED 0
94072     parameter \B_WIDTH 1
94073     parameter \Y_WIDTH 1
94074     connect \A $and$ls180.v:6067$1621_Y
94075     connect \B $eq$ls180.v:6067$1622_Y
94076     connect \Y $and$ls180.v:6067$1623_Y
94077   end
94078   attribute \src "ls180.v:6068.43-6068.99"
94079   cell $and $and$ls180.v:6068$1625
94080     parameter \A_SIGNED 0
94081     parameter \A_WIDTH 1
94082     parameter \B_SIGNED 0
94083     parameter \B_WIDTH 1
94084     parameter \Y_WIDTH 1
94085     connect \A \builder_csrbank6_sel
94086     connect \B $not$ls180.v:6068$1624_Y
94087     connect \Y $and$ls180.v:6068$1625_Y
94088   end
94089   attribute \src "ls180.v:6068.42-6068.150"
94090   cell $and $and$ls180.v:6068$1627
94091     parameter \A_SIGNED 0
94092     parameter \A_WIDTH 1
94093     parameter \B_SIGNED 0
94094     parameter \B_WIDTH 1
94095     parameter \Y_WIDTH 1
94096     connect \A $and$ls180.v:6068$1625_Y
94097     connect \B $eq$ls180.v:6068$1626_Y
94098     connect \Y $and$ls180.v:6068$1627_Y
94099   end
94100   attribute \src "ls180.v:6070.46-6070.99"
94101   cell $and $and$ls180.v:6070$1628
94102     parameter \A_SIGNED 0
94103     parameter \A_WIDTH 1
94104     parameter \B_SIGNED 0
94105     parameter \B_WIDTH 1
94106     parameter \Y_WIDTH 1
94107     connect \A \builder_csrbank6_sel
94108     connect \B \builder_interface6_bank_bus_we
94109     connect \Y $and$ls180.v:6070$1628_Y
94110   end
94111   attribute \src "ls180.v:6070.45-6070.150"
94112   cell $and $and$ls180.v:6070$1630
94113     parameter \A_SIGNED 0
94114     parameter \A_WIDTH 1
94115     parameter \B_SIGNED 0
94116     parameter \B_WIDTH 1
94117     parameter \Y_WIDTH 1
94118     connect \A $and$ls180.v:6070$1628_Y
94119     connect \B $eq$ls180.v:6070$1629_Y
94120     connect \Y $and$ls180.v:6070$1630_Y
94121   end
94122   attribute \src "ls180.v:6071.46-6071.102"
94123   cell $and $and$ls180.v:6071$1632
94124     parameter \A_SIGNED 0
94125     parameter \A_WIDTH 1
94126     parameter \B_SIGNED 0
94127     parameter \B_WIDTH 1
94128     parameter \Y_WIDTH 1
94129     connect \A \builder_csrbank6_sel
94130     connect \B $not$ls180.v:6071$1631_Y
94131     connect \Y $and$ls180.v:6071$1632_Y
94132   end
94133   attribute \src "ls180.v:6071.45-6071.153"
94134   cell $and $and$ls180.v:6071$1634
94135     parameter \A_SIGNED 0
94136     parameter \A_WIDTH 1
94137     parameter \B_SIGNED 0
94138     parameter \B_WIDTH 1
94139     parameter \Y_WIDTH 1
94140     connect \A $and$ls180.v:6071$1632_Y
94141     connect \B $eq$ls180.v:6071$1633_Y
94142     connect \Y $and$ls180.v:6071$1634_Y
94143   end
94144   attribute \src "ls180.v:6073.46-6073.99"
94145   cell $and $and$ls180.v:6073$1635
94146     parameter \A_SIGNED 0
94147     parameter \A_WIDTH 1
94148     parameter \B_SIGNED 0
94149     parameter \B_WIDTH 1
94150     parameter \Y_WIDTH 1
94151     connect \A \builder_csrbank6_sel
94152     connect \B \builder_interface6_bank_bus_we
94153     connect \Y $and$ls180.v:6073$1635_Y
94154   end
94155   attribute \src "ls180.v:6073.45-6073.150"
94156   cell $and $and$ls180.v:6073$1637
94157     parameter \A_SIGNED 0
94158     parameter \A_WIDTH 1
94159     parameter \B_SIGNED 0
94160     parameter \B_WIDTH 1
94161     parameter \Y_WIDTH 1
94162     connect \A $and$ls180.v:6073$1635_Y
94163     connect \B $eq$ls180.v:6073$1636_Y
94164     connect \Y $and$ls180.v:6073$1637_Y
94165   end
94166   attribute \src "ls180.v:6074.46-6074.102"
94167   cell $and $and$ls180.v:6074$1639
94168     parameter \A_SIGNED 0
94169     parameter \A_WIDTH 1
94170     parameter \B_SIGNED 0
94171     parameter \B_WIDTH 1
94172     parameter \Y_WIDTH 1
94173     connect \A \builder_csrbank6_sel
94174     connect \B $not$ls180.v:6074$1638_Y
94175     connect \Y $and$ls180.v:6074$1639_Y
94176   end
94177   attribute \src "ls180.v:6074.45-6074.153"
94178   cell $and $and$ls180.v:6074$1641
94179     parameter \A_SIGNED 0
94180     parameter \A_WIDTH 1
94181     parameter \B_SIGNED 0
94182     parameter \B_WIDTH 1
94183     parameter \Y_WIDTH 1
94184     connect \A $and$ls180.v:6074$1639_Y
94185     connect \B $eq$ls180.v:6074$1640_Y
94186     connect \Y $and$ls180.v:6074$1641_Y
94187   end
94188   attribute \src "ls180.v:6076.45-6076.98"
94189   cell $and $and$ls180.v:6076$1642
94190     parameter \A_SIGNED 0
94191     parameter \A_WIDTH 1
94192     parameter \B_SIGNED 0
94193     parameter \B_WIDTH 1
94194     parameter \Y_WIDTH 1
94195     connect \A \builder_csrbank6_sel
94196     connect \B \builder_interface6_bank_bus_we
94197     connect \Y $and$ls180.v:6076$1642_Y
94198   end
94199   attribute \src "ls180.v:6076.44-6076.149"
94200   cell $and $and$ls180.v:6076$1644
94201     parameter \A_SIGNED 0
94202     parameter \A_WIDTH 1
94203     parameter \B_SIGNED 0
94204     parameter \B_WIDTH 1
94205     parameter \Y_WIDTH 1
94206     connect \A $and$ls180.v:6076$1642_Y
94207     connect \B $eq$ls180.v:6076$1643_Y
94208     connect \Y $and$ls180.v:6076$1644_Y
94209   end
94210   attribute \src "ls180.v:6077.45-6077.101"
94211   cell $and $and$ls180.v:6077$1646
94212     parameter \A_SIGNED 0
94213     parameter \A_WIDTH 1
94214     parameter \B_SIGNED 0
94215     parameter \B_WIDTH 1
94216     parameter \Y_WIDTH 1
94217     connect \A \builder_csrbank6_sel
94218     connect \B $not$ls180.v:6077$1645_Y
94219     connect \Y $and$ls180.v:6077$1646_Y
94220   end
94221   attribute \src "ls180.v:6077.44-6077.152"
94222   cell $and $and$ls180.v:6077$1648
94223     parameter \A_SIGNED 0
94224     parameter \A_WIDTH 1
94225     parameter \B_SIGNED 0
94226     parameter \B_WIDTH 1
94227     parameter \Y_WIDTH 1
94228     connect \A $and$ls180.v:6077$1646_Y
94229     connect \B $eq$ls180.v:6077$1647_Y
94230     connect \Y $and$ls180.v:6077$1648_Y
94231   end
94232   attribute \src "ls180.v:6079.45-6079.98"
94233   cell $and $and$ls180.v:6079$1649
94234     parameter \A_SIGNED 0
94235     parameter \A_WIDTH 1
94236     parameter \B_SIGNED 0
94237     parameter \B_WIDTH 1
94238     parameter \Y_WIDTH 1
94239     connect \A \builder_csrbank6_sel
94240     connect \B \builder_interface6_bank_bus_we
94241     connect \Y $and$ls180.v:6079$1649_Y
94242   end
94243   attribute \src "ls180.v:6079.44-6079.149"
94244   cell $and $and$ls180.v:6079$1651
94245     parameter \A_SIGNED 0
94246     parameter \A_WIDTH 1
94247     parameter \B_SIGNED 0
94248     parameter \B_WIDTH 1
94249     parameter \Y_WIDTH 1
94250     connect \A $and$ls180.v:6079$1649_Y
94251     connect \B $eq$ls180.v:6079$1650_Y
94252     connect \Y $and$ls180.v:6079$1651_Y
94253   end
94254   attribute \src "ls180.v:6080.45-6080.101"
94255   cell $and $and$ls180.v:6080$1653
94256     parameter \A_SIGNED 0
94257     parameter \A_WIDTH 1
94258     parameter \B_SIGNED 0
94259     parameter \B_WIDTH 1
94260     parameter \Y_WIDTH 1
94261     connect \A \builder_csrbank6_sel
94262     connect \B $not$ls180.v:6080$1652_Y
94263     connect \Y $and$ls180.v:6080$1653_Y
94264   end
94265   attribute \src "ls180.v:6080.44-6080.152"
94266   cell $and $and$ls180.v:6080$1655
94267     parameter \A_SIGNED 0
94268     parameter \A_WIDTH 1
94269     parameter \B_SIGNED 0
94270     parameter \B_WIDTH 1
94271     parameter \Y_WIDTH 1
94272     connect \A $and$ls180.v:6080$1653_Y
94273     connect \B $eq$ls180.v:6080$1654_Y
94274     connect \Y $and$ls180.v:6080$1655_Y
94275   end
94276   attribute \src "ls180.v:6082.45-6082.98"
94277   cell $and $and$ls180.v:6082$1656
94278     parameter \A_SIGNED 0
94279     parameter \A_WIDTH 1
94280     parameter \B_SIGNED 0
94281     parameter \B_WIDTH 1
94282     parameter \Y_WIDTH 1
94283     connect \A \builder_csrbank6_sel
94284     connect \B \builder_interface6_bank_bus_we
94285     connect \Y $and$ls180.v:6082$1656_Y
94286   end
94287   attribute \src "ls180.v:6082.44-6082.149"
94288   cell $and $and$ls180.v:6082$1658
94289     parameter \A_SIGNED 0
94290     parameter \A_WIDTH 1
94291     parameter \B_SIGNED 0
94292     parameter \B_WIDTH 1
94293     parameter \Y_WIDTH 1
94294     connect \A $and$ls180.v:6082$1656_Y
94295     connect \B $eq$ls180.v:6082$1657_Y
94296     connect \Y $and$ls180.v:6082$1658_Y
94297   end
94298   attribute \src "ls180.v:6083.45-6083.101"
94299   cell $and $and$ls180.v:6083$1660
94300     parameter \A_SIGNED 0
94301     parameter \A_WIDTH 1
94302     parameter \B_SIGNED 0
94303     parameter \B_WIDTH 1
94304     parameter \Y_WIDTH 1
94305     connect \A \builder_csrbank6_sel
94306     connect \B $not$ls180.v:6083$1659_Y
94307     connect \Y $and$ls180.v:6083$1660_Y
94308   end
94309   attribute \src "ls180.v:6083.44-6083.152"
94310   cell $and $and$ls180.v:6083$1662
94311     parameter \A_SIGNED 0
94312     parameter \A_WIDTH 1
94313     parameter \B_SIGNED 0
94314     parameter \B_WIDTH 1
94315     parameter \Y_WIDTH 1
94316     connect \A $and$ls180.v:6083$1660_Y
94317     connect \B $eq$ls180.v:6083$1661_Y
94318     connect \Y $and$ls180.v:6083$1662_Y
94319   end
94320   attribute \src "ls180.v:6085.45-6085.98"
94321   cell $and $and$ls180.v:6085$1663
94322     parameter \A_SIGNED 0
94323     parameter \A_WIDTH 1
94324     parameter \B_SIGNED 0
94325     parameter \B_WIDTH 1
94326     parameter \Y_WIDTH 1
94327     connect \A \builder_csrbank6_sel
94328     connect \B \builder_interface6_bank_bus_we
94329     connect \Y $and$ls180.v:6085$1663_Y
94330   end
94331   attribute \src "ls180.v:6085.44-6085.149"
94332   cell $and $and$ls180.v:6085$1665
94333     parameter \A_SIGNED 0
94334     parameter \A_WIDTH 1
94335     parameter \B_SIGNED 0
94336     parameter \B_WIDTH 1
94337     parameter \Y_WIDTH 1
94338     connect \A $and$ls180.v:6085$1663_Y
94339     connect \B $eq$ls180.v:6085$1664_Y
94340     connect \Y $and$ls180.v:6085$1665_Y
94341   end
94342   attribute \src "ls180.v:6086.45-6086.101"
94343   cell $and $and$ls180.v:6086$1667
94344     parameter \A_SIGNED 0
94345     parameter \A_WIDTH 1
94346     parameter \B_SIGNED 0
94347     parameter \B_WIDTH 1
94348     parameter \Y_WIDTH 1
94349     connect \A \builder_csrbank6_sel
94350     connect \B $not$ls180.v:6086$1666_Y
94351     connect \Y $and$ls180.v:6086$1667_Y
94352   end
94353   attribute \src "ls180.v:6086.44-6086.152"
94354   cell $and $and$ls180.v:6086$1669
94355     parameter \A_SIGNED 0
94356     parameter \A_WIDTH 1
94357     parameter \B_SIGNED 0
94358     parameter \B_WIDTH 1
94359     parameter \Y_WIDTH 1
94360     connect \A $and$ls180.v:6086$1667_Y
94361     connect \B $eq$ls180.v:6086$1668_Y
94362     connect \Y $and$ls180.v:6086$1669_Y
94363   end
94364   attribute \src "ls180.v:6124.42-6124.95"
94365   cell $and $and$ls180.v:6124$1671
94366     parameter \A_SIGNED 0
94367     parameter \A_WIDTH 1
94368     parameter \B_SIGNED 0
94369     parameter \B_WIDTH 1
94370     parameter \Y_WIDTH 1
94371     connect \A \builder_csrbank7_sel
94372     connect \B \builder_interface7_bank_bus_we
94373     connect \Y $and$ls180.v:6124$1671_Y
94374   end
94375   attribute \src "ls180.v:6124.41-6124.145"
94376   cell $and $and$ls180.v:6124$1673
94377     parameter \A_SIGNED 0
94378     parameter \A_WIDTH 1
94379     parameter \B_SIGNED 0
94380     parameter \B_WIDTH 1
94381     parameter \Y_WIDTH 1
94382     connect \A $and$ls180.v:6124$1671_Y
94383     connect \B $eq$ls180.v:6124$1672_Y
94384     connect \Y $and$ls180.v:6124$1673_Y
94385   end
94386   attribute \src "ls180.v:6125.42-6125.98"
94387   cell $and $and$ls180.v:6125$1675
94388     parameter \A_SIGNED 0
94389     parameter \A_WIDTH 1
94390     parameter \B_SIGNED 0
94391     parameter \B_WIDTH 1
94392     parameter \Y_WIDTH 1
94393     connect \A \builder_csrbank7_sel
94394     connect \B $not$ls180.v:6125$1674_Y
94395     connect \Y $and$ls180.v:6125$1675_Y
94396   end
94397   attribute \src "ls180.v:6125.41-6125.148"
94398   cell $and $and$ls180.v:6125$1677
94399     parameter \A_SIGNED 0
94400     parameter \A_WIDTH 1
94401     parameter \B_SIGNED 0
94402     parameter \B_WIDTH 1
94403     parameter \Y_WIDTH 1
94404     connect \A $and$ls180.v:6125$1675_Y
94405     connect \B $eq$ls180.v:6125$1676_Y
94406     connect \Y $and$ls180.v:6125$1677_Y
94407   end
94408   attribute \src "ls180.v:6127.42-6127.95"
94409   cell $and $and$ls180.v:6127$1678
94410     parameter \A_SIGNED 0
94411     parameter \A_WIDTH 1
94412     parameter \B_SIGNED 0
94413     parameter \B_WIDTH 1
94414     parameter \Y_WIDTH 1
94415     connect \A \builder_csrbank7_sel
94416     connect \B \builder_interface7_bank_bus_we
94417     connect \Y $and$ls180.v:6127$1678_Y
94418   end
94419   attribute \src "ls180.v:6127.41-6127.145"
94420   cell $and $and$ls180.v:6127$1680
94421     parameter \A_SIGNED 0
94422     parameter \A_WIDTH 1
94423     parameter \B_SIGNED 0
94424     parameter \B_WIDTH 1
94425     parameter \Y_WIDTH 1
94426     connect \A $and$ls180.v:6127$1678_Y
94427     connect \B $eq$ls180.v:6127$1679_Y
94428     connect \Y $and$ls180.v:6127$1680_Y
94429   end
94430   attribute \src "ls180.v:6128.42-6128.98"
94431   cell $and $and$ls180.v:6128$1682
94432     parameter \A_SIGNED 0
94433     parameter \A_WIDTH 1
94434     parameter \B_SIGNED 0
94435     parameter \B_WIDTH 1
94436     parameter \Y_WIDTH 1
94437     connect \A \builder_csrbank7_sel
94438     connect \B $not$ls180.v:6128$1681_Y
94439     connect \Y $and$ls180.v:6128$1682_Y
94440   end
94441   attribute \src "ls180.v:6128.41-6128.148"
94442   cell $and $and$ls180.v:6128$1684
94443     parameter \A_SIGNED 0
94444     parameter \A_WIDTH 1
94445     parameter \B_SIGNED 0
94446     parameter \B_WIDTH 1
94447     parameter \Y_WIDTH 1
94448     connect \A $and$ls180.v:6128$1682_Y
94449     connect \B $eq$ls180.v:6128$1683_Y
94450     connect \Y $and$ls180.v:6128$1684_Y
94451   end
94452   attribute \src "ls180.v:6130.42-6130.95"
94453   cell $and $and$ls180.v:6130$1685
94454     parameter \A_SIGNED 0
94455     parameter \A_WIDTH 1
94456     parameter \B_SIGNED 0
94457     parameter \B_WIDTH 1
94458     parameter \Y_WIDTH 1
94459     connect \A \builder_csrbank7_sel
94460     connect \B \builder_interface7_bank_bus_we
94461     connect \Y $and$ls180.v:6130$1685_Y
94462   end
94463   attribute \src "ls180.v:6130.41-6130.145"
94464   cell $and $and$ls180.v:6130$1687
94465     parameter \A_SIGNED 0
94466     parameter \A_WIDTH 1
94467     parameter \B_SIGNED 0
94468     parameter \B_WIDTH 1
94469     parameter \Y_WIDTH 1
94470     connect \A $and$ls180.v:6130$1685_Y
94471     connect \B $eq$ls180.v:6130$1686_Y
94472     connect \Y $and$ls180.v:6130$1687_Y
94473   end
94474   attribute \src "ls180.v:6131.42-6131.98"
94475   cell $and $and$ls180.v:6131$1689
94476     parameter \A_SIGNED 0
94477     parameter \A_WIDTH 1
94478     parameter \B_SIGNED 0
94479     parameter \B_WIDTH 1
94480     parameter \Y_WIDTH 1
94481     connect \A \builder_csrbank7_sel
94482     connect \B $not$ls180.v:6131$1688_Y
94483     connect \Y $and$ls180.v:6131$1689_Y
94484   end
94485   attribute \src "ls180.v:6131.41-6131.148"
94486   cell $and $and$ls180.v:6131$1691
94487     parameter \A_SIGNED 0
94488     parameter \A_WIDTH 1
94489     parameter \B_SIGNED 0
94490     parameter \B_WIDTH 1
94491     parameter \Y_WIDTH 1
94492     connect \A $and$ls180.v:6131$1689_Y
94493     connect \B $eq$ls180.v:6131$1690_Y
94494     connect \Y $and$ls180.v:6131$1691_Y
94495   end
94496   attribute \src "ls180.v:6133.42-6133.95"
94497   cell $and $and$ls180.v:6133$1692
94498     parameter \A_SIGNED 0
94499     parameter \A_WIDTH 1
94500     parameter \B_SIGNED 0
94501     parameter \B_WIDTH 1
94502     parameter \Y_WIDTH 1
94503     connect \A \builder_csrbank7_sel
94504     connect \B \builder_interface7_bank_bus_we
94505     connect \Y $and$ls180.v:6133$1692_Y
94506   end
94507   attribute \src "ls180.v:6133.41-6133.145"
94508   cell $and $and$ls180.v:6133$1694
94509     parameter \A_SIGNED 0
94510     parameter \A_WIDTH 1
94511     parameter \B_SIGNED 0
94512     parameter \B_WIDTH 1
94513     parameter \Y_WIDTH 1
94514     connect \A $and$ls180.v:6133$1692_Y
94515     connect \B $eq$ls180.v:6133$1693_Y
94516     connect \Y $and$ls180.v:6133$1694_Y
94517   end
94518   attribute \src "ls180.v:6134.42-6134.98"
94519   cell $and $and$ls180.v:6134$1696
94520     parameter \A_SIGNED 0
94521     parameter \A_WIDTH 1
94522     parameter \B_SIGNED 0
94523     parameter \B_WIDTH 1
94524     parameter \Y_WIDTH 1
94525     connect \A \builder_csrbank7_sel
94526     connect \B $not$ls180.v:6134$1695_Y
94527     connect \Y $and$ls180.v:6134$1696_Y
94528   end
94529   attribute \src "ls180.v:6134.41-6134.148"
94530   cell $and $and$ls180.v:6134$1698
94531     parameter \A_SIGNED 0
94532     parameter \A_WIDTH 1
94533     parameter \B_SIGNED 0
94534     parameter \B_WIDTH 1
94535     parameter \Y_WIDTH 1
94536     connect \A $and$ls180.v:6134$1696_Y
94537     connect \B $eq$ls180.v:6134$1697_Y
94538     connect \Y $and$ls180.v:6134$1698_Y
94539   end
94540   attribute \src "ls180.v:6136.42-6136.95"
94541   cell $and $and$ls180.v:6136$1699
94542     parameter \A_SIGNED 0
94543     parameter \A_WIDTH 1
94544     parameter \B_SIGNED 0
94545     parameter \B_WIDTH 1
94546     parameter \Y_WIDTH 1
94547     connect \A \builder_csrbank7_sel
94548     connect \B \builder_interface7_bank_bus_we
94549     connect \Y $and$ls180.v:6136$1699_Y
94550   end
94551   attribute \src "ls180.v:6136.41-6136.145"
94552   cell $and $and$ls180.v:6136$1701
94553     parameter \A_SIGNED 0
94554     parameter \A_WIDTH 1
94555     parameter \B_SIGNED 0
94556     parameter \B_WIDTH 1
94557     parameter \Y_WIDTH 1
94558     connect \A $and$ls180.v:6136$1699_Y
94559     connect \B $eq$ls180.v:6136$1700_Y
94560     connect \Y $and$ls180.v:6136$1701_Y
94561   end
94562   attribute \src "ls180.v:6137.42-6137.98"
94563   cell $and $and$ls180.v:6137$1703
94564     parameter \A_SIGNED 0
94565     parameter \A_WIDTH 1
94566     parameter \B_SIGNED 0
94567     parameter \B_WIDTH 1
94568     parameter \Y_WIDTH 1
94569     connect \A \builder_csrbank7_sel
94570     connect \B $not$ls180.v:6137$1702_Y
94571     connect \Y $and$ls180.v:6137$1703_Y
94572   end
94573   attribute \src "ls180.v:6137.41-6137.148"
94574   cell $and $and$ls180.v:6137$1705
94575     parameter \A_SIGNED 0
94576     parameter \A_WIDTH 1
94577     parameter \B_SIGNED 0
94578     parameter \B_WIDTH 1
94579     parameter \Y_WIDTH 1
94580     connect \A $and$ls180.v:6137$1703_Y
94581     connect \B $eq$ls180.v:6137$1704_Y
94582     connect \Y $and$ls180.v:6137$1705_Y
94583   end
94584   attribute \src "ls180.v:6139.42-6139.95"
94585   cell $and $and$ls180.v:6139$1706
94586     parameter \A_SIGNED 0
94587     parameter \A_WIDTH 1
94588     parameter \B_SIGNED 0
94589     parameter \B_WIDTH 1
94590     parameter \Y_WIDTH 1
94591     connect \A \builder_csrbank7_sel
94592     connect \B \builder_interface7_bank_bus_we
94593     connect \Y $and$ls180.v:6139$1706_Y
94594   end
94595   attribute \src "ls180.v:6139.41-6139.145"
94596   cell $and $and$ls180.v:6139$1708
94597     parameter \A_SIGNED 0
94598     parameter \A_WIDTH 1
94599     parameter \B_SIGNED 0
94600     parameter \B_WIDTH 1
94601     parameter \Y_WIDTH 1
94602     connect \A $and$ls180.v:6139$1706_Y
94603     connect \B $eq$ls180.v:6139$1707_Y
94604     connect \Y $and$ls180.v:6139$1708_Y
94605   end
94606   attribute \src "ls180.v:6140.42-6140.98"
94607   cell $and $and$ls180.v:6140$1710
94608     parameter \A_SIGNED 0
94609     parameter \A_WIDTH 1
94610     parameter \B_SIGNED 0
94611     parameter \B_WIDTH 1
94612     parameter \Y_WIDTH 1
94613     connect \A \builder_csrbank7_sel
94614     connect \B $not$ls180.v:6140$1709_Y
94615     connect \Y $and$ls180.v:6140$1710_Y
94616   end
94617   attribute \src "ls180.v:6140.41-6140.148"
94618   cell $and $and$ls180.v:6140$1712
94619     parameter \A_SIGNED 0
94620     parameter \A_WIDTH 1
94621     parameter \B_SIGNED 0
94622     parameter \B_WIDTH 1
94623     parameter \Y_WIDTH 1
94624     connect \A $and$ls180.v:6140$1710_Y
94625     connect \B $eq$ls180.v:6140$1711_Y
94626     connect \Y $and$ls180.v:6140$1712_Y
94627   end
94628   attribute \src "ls180.v:6142.42-6142.95"
94629   cell $and $and$ls180.v:6142$1713
94630     parameter \A_SIGNED 0
94631     parameter \A_WIDTH 1
94632     parameter \B_SIGNED 0
94633     parameter \B_WIDTH 1
94634     parameter \Y_WIDTH 1
94635     connect \A \builder_csrbank7_sel
94636     connect \B \builder_interface7_bank_bus_we
94637     connect \Y $and$ls180.v:6142$1713_Y
94638   end
94639   attribute \src "ls180.v:6142.41-6142.145"
94640   cell $and $and$ls180.v:6142$1715
94641     parameter \A_SIGNED 0
94642     parameter \A_WIDTH 1
94643     parameter \B_SIGNED 0
94644     parameter \B_WIDTH 1
94645     parameter \Y_WIDTH 1
94646     connect \A $and$ls180.v:6142$1713_Y
94647     connect \B $eq$ls180.v:6142$1714_Y
94648     connect \Y $and$ls180.v:6142$1715_Y
94649   end
94650   attribute \src "ls180.v:6143.42-6143.98"
94651   cell $and $and$ls180.v:6143$1717
94652     parameter \A_SIGNED 0
94653     parameter \A_WIDTH 1
94654     parameter \B_SIGNED 0
94655     parameter \B_WIDTH 1
94656     parameter \Y_WIDTH 1
94657     connect \A \builder_csrbank7_sel
94658     connect \B $not$ls180.v:6143$1716_Y
94659     connect \Y $and$ls180.v:6143$1717_Y
94660   end
94661   attribute \src "ls180.v:6143.41-6143.148"
94662   cell $and $and$ls180.v:6143$1719
94663     parameter \A_SIGNED 0
94664     parameter \A_WIDTH 1
94665     parameter \B_SIGNED 0
94666     parameter \B_WIDTH 1
94667     parameter \Y_WIDTH 1
94668     connect \A $and$ls180.v:6143$1717_Y
94669     connect \B $eq$ls180.v:6143$1718_Y
94670     connect \Y $and$ls180.v:6143$1719_Y
94671   end
94672   attribute \src "ls180.v:6145.42-6145.95"
94673   cell $and $and$ls180.v:6145$1720
94674     parameter \A_SIGNED 0
94675     parameter \A_WIDTH 1
94676     parameter \B_SIGNED 0
94677     parameter \B_WIDTH 1
94678     parameter \Y_WIDTH 1
94679     connect \A \builder_csrbank7_sel
94680     connect \B \builder_interface7_bank_bus_we
94681     connect \Y $and$ls180.v:6145$1720_Y
94682   end
94683   attribute \src "ls180.v:6145.41-6145.145"
94684   cell $and $and$ls180.v:6145$1722
94685     parameter \A_SIGNED 0
94686     parameter \A_WIDTH 1
94687     parameter \B_SIGNED 0
94688     parameter \B_WIDTH 1
94689     parameter \Y_WIDTH 1
94690     connect \A $and$ls180.v:6145$1720_Y
94691     connect \B $eq$ls180.v:6145$1721_Y
94692     connect \Y $and$ls180.v:6145$1722_Y
94693   end
94694   attribute \src "ls180.v:6146.42-6146.98"
94695   cell $and $and$ls180.v:6146$1724
94696     parameter \A_SIGNED 0
94697     parameter \A_WIDTH 1
94698     parameter \B_SIGNED 0
94699     parameter \B_WIDTH 1
94700     parameter \Y_WIDTH 1
94701     connect \A \builder_csrbank7_sel
94702     connect \B $not$ls180.v:6146$1723_Y
94703     connect \Y $and$ls180.v:6146$1724_Y
94704   end
94705   attribute \src "ls180.v:6146.41-6146.148"
94706   cell $and $and$ls180.v:6146$1726
94707     parameter \A_SIGNED 0
94708     parameter \A_WIDTH 1
94709     parameter \B_SIGNED 0
94710     parameter \B_WIDTH 1
94711     parameter \Y_WIDTH 1
94712     connect \A $and$ls180.v:6146$1724_Y
94713     connect \B $eq$ls180.v:6146$1725_Y
94714     connect \Y $and$ls180.v:6146$1726_Y
94715   end
94716   attribute \src "ls180.v:6148.44-6148.97"
94717   cell $and $and$ls180.v:6148$1727
94718     parameter \A_SIGNED 0
94719     parameter \A_WIDTH 1
94720     parameter \B_SIGNED 0
94721     parameter \B_WIDTH 1
94722     parameter \Y_WIDTH 1
94723     connect \A \builder_csrbank7_sel
94724     connect \B \builder_interface7_bank_bus_we
94725     connect \Y $and$ls180.v:6148$1727_Y
94726   end
94727   attribute \src "ls180.v:6148.43-6148.147"
94728   cell $and $and$ls180.v:6148$1729
94729     parameter \A_SIGNED 0
94730     parameter \A_WIDTH 1
94731     parameter \B_SIGNED 0
94732     parameter \B_WIDTH 1
94733     parameter \Y_WIDTH 1
94734     connect \A $and$ls180.v:6148$1727_Y
94735     connect \B $eq$ls180.v:6148$1728_Y
94736     connect \Y $and$ls180.v:6148$1729_Y
94737   end
94738   attribute \src "ls180.v:6149.44-6149.100"
94739   cell $and $and$ls180.v:6149$1731
94740     parameter \A_SIGNED 0
94741     parameter \A_WIDTH 1
94742     parameter \B_SIGNED 0
94743     parameter \B_WIDTH 1
94744     parameter \Y_WIDTH 1
94745     connect \A \builder_csrbank7_sel
94746     connect \B $not$ls180.v:6149$1730_Y
94747     connect \Y $and$ls180.v:6149$1731_Y
94748   end
94749   attribute \src "ls180.v:6149.43-6149.150"
94750   cell $and $and$ls180.v:6149$1733
94751     parameter \A_SIGNED 0
94752     parameter \A_WIDTH 1
94753     parameter \B_SIGNED 0
94754     parameter \B_WIDTH 1
94755     parameter \Y_WIDTH 1
94756     connect \A $and$ls180.v:6149$1731_Y
94757     connect \B $eq$ls180.v:6149$1732_Y
94758     connect \Y $and$ls180.v:6149$1733_Y
94759   end
94760   attribute \src "ls180.v:6151.44-6151.97"
94761   cell $and $and$ls180.v:6151$1734
94762     parameter \A_SIGNED 0
94763     parameter \A_WIDTH 1
94764     parameter \B_SIGNED 0
94765     parameter \B_WIDTH 1
94766     parameter \Y_WIDTH 1
94767     connect \A \builder_csrbank7_sel
94768     connect \B \builder_interface7_bank_bus_we
94769     connect \Y $and$ls180.v:6151$1734_Y
94770   end
94771   attribute \src "ls180.v:6151.43-6151.147"
94772   cell $and $and$ls180.v:6151$1736
94773     parameter \A_SIGNED 0
94774     parameter \A_WIDTH 1
94775     parameter \B_SIGNED 0
94776     parameter \B_WIDTH 1
94777     parameter \Y_WIDTH 1
94778     connect \A $and$ls180.v:6151$1734_Y
94779     connect \B $eq$ls180.v:6151$1735_Y
94780     connect \Y $and$ls180.v:6151$1736_Y
94781   end
94782   attribute \src "ls180.v:6152.44-6152.100"
94783   cell $and $and$ls180.v:6152$1738
94784     parameter \A_SIGNED 0
94785     parameter \A_WIDTH 1
94786     parameter \B_SIGNED 0
94787     parameter \B_WIDTH 1
94788     parameter \Y_WIDTH 1
94789     connect \A \builder_csrbank7_sel
94790     connect \B $not$ls180.v:6152$1737_Y
94791     connect \Y $and$ls180.v:6152$1738_Y
94792   end
94793   attribute \src "ls180.v:6152.43-6152.150"
94794   cell $and $and$ls180.v:6152$1740
94795     parameter \A_SIGNED 0
94796     parameter \A_WIDTH 1
94797     parameter \B_SIGNED 0
94798     parameter \B_WIDTH 1
94799     parameter \Y_WIDTH 1
94800     connect \A $and$ls180.v:6152$1738_Y
94801     connect \B $eq$ls180.v:6152$1739_Y
94802     connect \Y $and$ls180.v:6152$1740_Y
94803   end
94804   attribute \src "ls180.v:6154.44-6154.97"
94805   cell $and $and$ls180.v:6154$1741
94806     parameter \A_SIGNED 0
94807     parameter \A_WIDTH 1
94808     parameter \B_SIGNED 0
94809     parameter \B_WIDTH 1
94810     parameter \Y_WIDTH 1
94811     connect \A \builder_csrbank7_sel
94812     connect \B \builder_interface7_bank_bus_we
94813     connect \Y $and$ls180.v:6154$1741_Y
94814   end
94815   attribute \src "ls180.v:6154.43-6154.148"
94816   cell $and $and$ls180.v:6154$1743
94817     parameter \A_SIGNED 0
94818     parameter \A_WIDTH 1
94819     parameter \B_SIGNED 0
94820     parameter \B_WIDTH 1
94821     parameter \Y_WIDTH 1
94822     connect \A $and$ls180.v:6154$1741_Y
94823     connect \B $eq$ls180.v:6154$1742_Y
94824     connect \Y $and$ls180.v:6154$1743_Y
94825   end
94826   attribute \src "ls180.v:6155.44-6155.100"
94827   cell $and $and$ls180.v:6155$1745
94828     parameter \A_SIGNED 0
94829     parameter \A_WIDTH 1
94830     parameter \B_SIGNED 0
94831     parameter \B_WIDTH 1
94832     parameter \Y_WIDTH 1
94833     connect \A \builder_csrbank7_sel
94834     connect \B $not$ls180.v:6155$1744_Y
94835     connect \Y $and$ls180.v:6155$1745_Y
94836   end
94837   attribute \src "ls180.v:6155.43-6155.151"
94838   cell $and $and$ls180.v:6155$1747
94839     parameter \A_SIGNED 0
94840     parameter \A_WIDTH 1
94841     parameter \B_SIGNED 0
94842     parameter \B_WIDTH 1
94843     parameter \Y_WIDTH 1
94844     connect \A $and$ls180.v:6155$1745_Y
94845     connect \B $eq$ls180.v:6155$1746_Y
94846     connect \Y $and$ls180.v:6155$1747_Y
94847   end
94848   attribute \src "ls180.v:6157.44-6157.97"
94849   cell $and $and$ls180.v:6157$1748
94850     parameter \A_SIGNED 0
94851     parameter \A_WIDTH 1
94852     parameter \B_SIGNED 0
94853     parameter \B_WIDTH 1
94854     parameter \Y_WIDTH 1
94855     connect \A \builder_csrbank7_sel
94856     connect \B \builder_interface7_bank_bus_we
94857     connect \Y $and$ls180.v:6157$1748_Y
94858   end
94859   attribute \src "ls180.v:6157.43-6157.148"
94860   cell $and $and$ls180.v:6157$1750
94861     parameter \A_SIGNED 0
94862     parameter \A_WIDTH 1
94863     parameter \B_SIGNED 0
94864     parameter \B_WIDTH 1
94865     parameter \Y_WIDTH 1
94866     connect \A $and$ls180.v:6157$1748_Y
94867     connect \B $eq$ls180.v:6157$1749_Y
94868     connect \Y $and$ls180.v:6157$1750_Y
94869   end
94870   attribute \src "ls180.v:6158.44-6158.100"
94871   cell $and $and$ls180.v:6158$1752
94872     parameter \A_SIGNED 0
94873     parameter \A_WIDTH 1
94874     parameter \B_SIGNED 0
94875     parameter \B_WIDTH 1
94876     parameter \Y_WIDTH 1
94877     connect \A \builder_csrbank7_sel
94878     connect \B $not$ls180.v:6158$1751_Y
94879     connect \Y $and$ls180.v:6158$1752_Y
94880   end
94881   attribute \src "ls180.v:6158.43-6158.151"
94882   cell $and $and$ls180.v:6158$1754
94883     parameter \A_SIGNED 0
94884     parameter \A_WIDTH 1
94885     parameter \B_SIGNED 0
94886     parameter \B_WIDTH 1
94887     parameter \Y_WIDTH 1
94888     connect \A $and$ls180.v:6158$1752_Y
94889     connect \B $eq$ls180.v:6158$1753_Y
94890     connect \Y $and$ls180.v:6158$1754_Y
94891   end
94892   attribute \src "ls180.v:6160.44-6160.97"
94893   cell $and $and$ls180.v:6160$1755
94894     parameter \A_SIGNED 0
94895     parameter \A_WIDTH 1
94896     parameter \B_SIGNED 0
94897     parameter \B_WIDTH 1
94898     parameter \Y_WIDTH 1
94899     connect \A \builder_csrbank7_sel
94900     connect \B \builder_interface7_bank_bus_we
94901     connect \Y $and$ls180.v:6160$1755_Y
94902   end
94903   attribute \src "ls180.v:6160.43-6160.148"
94904   cell $and $and$ls180.v:6160$1757
94905     parameter \A_SIGNED 0
94906     parameter \A_WIDTH 1
94907     parameter \B_SIGNED 0
94908     parameter \B_WIDTH 1
94909     parameter \Y_WIDTH 1
94910     connect \A $and$ls180.v:6160$1755_Y
94911     connect \B $eq$ls180.v:6160$1756_Y
94912     connect \Y $and$ls180.v:6160$1757_Y
94913   end
94914   attribute \src "ls180.v:6161.44-6161.100"
94915   cell $and $and$ls180.v:6161$1759
94916     parameter \A_SIGNED 0
94917     parameter \A_WIDTH 1
94918     parameter \B_SIGNED 0
94919     parameter \B_WIDTH 1
94920     parameter \Y_WIDTH 1
94921     connect \A \builder_csrbank7_sel
94922     connect \B $not$ls180.v:6161$1758_Y
94923     connect \Y $and$ls180.v:6161$1759_Y
94924   end
94925   attribute \src "ls180.v:6161.43-6161.151"
94926   cell $and $and$ls180.v:6161$1761
94927     parameter \A_SIGNED 0
94928     parameter \A_WIDTH 1
94929     parameter \B_SIGNED 0
94930     parameter \B_WIDTH 1
94931     parameter \Y_WIDTH 1
94932     connect \A $and$ls180.v:6161$1759_Y
94933     connect \B $eq$ls180.v:6161$1760_Y
94934     connect \Y $and$ls180.v:6161$1761_Y
94935   end
94936   attribute \src "ls180.v:6163.41-6163.94"
94937   cell $and $and$ls180.v:6163$1762
94938     parameter \A_SIGNED 0
94939     parameter \A_WIDTH 1
94940     parameter \B_SIGNED 0
94941     parameter \B_WIDTH 1
94942     parameter \Y_WIDTH 1
94943     connect \A \builder_csrbank7_sel
94944     connect \B \builder_interface7_bank_bus_we
94945     connect \Y $and$ls180.v:6163$1762_Y
94946   end
94947   attribute \src "ls180.v:6163.40-6163.145"
94948   cell $and $and$ls180.v:6163$1764
94949     parameter \A_SIGNED 0
94950     parameter \A_WIDTH 1
94951     parameter \B_SIGNED 0
94952     parameter \B_WIDTH 1
94953     parameter \Y_WIDTH 1
94954     connect \A $and$ls180.v:6163$1762_Y
94955     connect \B $eq$ls180.v:6163$1763_Y
94956     connect \Y $and$ls180.v:6163$1764_Y
94957   end
94958   attribute \src "ls180.v:6164.41-6164.97"
94959   cell $and $and$ls180.v:6164$1766
94960     parameter \A_SIGNED 0
94961     parameter \A_WIDTH 1
94962     parameter \B_SIGNED 0
94963     parameter \B_WIDTH 1
94964     parameter \Y_WIDTH 1
94965     connect \A \builder_csrbank7_sel
94966     connect \B $not$ls180.v:6164$1765_Y
94967     connect \Y $and$ls180.v:6164$1766_Y
94968   end
94969   attribute \src "ls180.v:6164.40-6164.148"
94970   cell $and $and$ls180.v:6164$1768
94971     parameter \A_SIGNED 0
94972     parameter \A_WIDTH 1
94973     parameter \B_SIGNED 0
94974     parameter \B_WIDTH 1
94975     parameter \Y_WIDTH 1
94976     connect \A $and$ls180.v:6164$1766_Y
94977     connect \B $eq$ls180.v:6164$1767_Y
94978     connect \Y $and$ls180.v:6164$1768_Y
94979   end
94980   attribute \src "ls180.v:6166.42-6166.95"
94981   cell $and $and$ls180.v:6166$1769
94982     parameter \A_SIGNED 0
94983     parameter \A_WIDTH 1
94984     parameter \B_SIGNED 0
94985     parameter \B_WIDTH 1
94986     parameter \Y_WIDTH 1
94987     connect \A \builder_csrbank7_sel
94988     connect \B \builder_interface7_bank_bus_we
94989     connect \Y $and$ls180.v:6166$1769_Y
94990   end
94991   attribute \src "ls180.v:6166.41-6166.146"
94992   cell $and $and$ls180.v:6166$1771
94993     parameter \A_SIGNED 0
94994     parameter \A_WIDTH 1
94995     parameter \B_SIGNED 0
94996     parameter \B_WIDTH 1
94997     parameter \Y_WIDTH 1
94998     connect \A $and$ls180.v:6166$1769_Y
94999     connect \B $eq$ls180.v:6166$1770_Y
95000     connect \Y $and$ls180.v:6166$1771_Y
95001   end
95002   attribute \src "ls180.v:6167.42-6167.98"
95003   cell $and $and$ls180.v:6167$1773
95004     parameter \A_SIGNED 0
95005     parameter \A_WIDTH 1
95006     parameter \B_SIGNED 0
95007     parameter \B_WIDTH 1
95008     parameter \Y_WIDTH 1
95009     connect \A \builder_csrbank7_sel
95010     connect \B $not$ls180.v:6167$1772_Y
95011     connect \Y $and$ls180.v:6167$1773_Y
95012   end
95013   attribute \src "ls180.v:6167.41-6167.149"
95014   cell $and $and$ls180.v:6167$1775
95015     parameter \A_SIGNED 0
95016     parameter \A_WIDTH 1
95017     parameter \B_SIGNED 0
95018     parameter \B_WIDTH 1
95019     parameter \Y_WIDTH 1
95020     connect \A $and$ls180.v:6167$1773_Y
95021     connect \B $eq$ls180.v:6167$1774_Y
95022     connect \Y $and$ls180.v:6167$1775_Y
95023   end
95024   attribute \src "ls180.v:6169.44-6169.97"
95025   cell $and $and$ls180.v:6169$1776
95026     parameter \A_SIGNED 0
95027     parameter \A_WIDTH 1
95028     parameter \B_SIGNED 0
95029     parameter \B_WIDTH 1
95030     parameter \Y_WIDTH 1
95031     connect \A \builder_csrbank7_sel
95032     connect \B \builder_interface7_bank_bus_we
95033     connect \Y $and$ls180.v:6169$1776_Y
95034   end
95035   attribute \src "ls180.v:6169.43-6169.148"
95036   cell $and $and$ls180.v:6169$1778
95037     parameter \A_SIGNED 0
95038     parameter \A_WIDTH 1
95039     parameter \B_SIGNED 0
95040     parameter \B_WIDTH 1
95041     parameter \Y_WIDTH 1
95042     connect \A $and$ls180.v:6169$1776_Y
95043     connect \B $eq$ls180.v:6169$1777_Y
95044     connect \Y $and$ls180.v:6169$1778_Y
95045   end
95046   attribute \src "ls180.v:6170.44-6170.100"
95047   cell $and $and$ls180.v:6170$1780
95048     parameter \A_SIGNED 0
95049     parameter \A_WIDTH 1
95050     parameter \B_SIGNED 0
95051     parameter \B_WIDTH 1
95052     parameter \Y_WIDTH 1
95053     connect \A \builder_csrbank7_sel
95054     connect \B $not$ls180.v:6170$1779_Y
95055     connect \Y $and$ls180.v:6170$1780_Y
95056   end
95057   attribute \src "ls180.v:6170.43-6170.151"
95058   cell $and $and$ls180.v:6170$1782
95059     parameter \A_SIGNED 0
95060     parameter \A_WIDTH 1
95061     parameter \B_SIGNED 0
95062     parameter \B_WIDTH 1
95063     parameter \Y_WIDTH 1
95064     connect \A $and$ls180.v:6170$1780_Y
95065     connect \B $eq$ls180.v:6170$1781_Y
95066     connect \Y $and$ls180.v:6170$1782_Y
95067   end
95068   attribute \src "ls180.v:6172.44-6172.97"
95069   cell $and $and$ls180.v:6172$1783
95070     parameter \A_SIGNED 0
95071     parameter \A_WIDTH 1
95072     parameter \B_SIGNED 0
95073     parameter \B_WIDTH 1
95074     parameter \Y_WIDTH 1
95075     connect \A \builder_csrbank7_sel
95076     connect \B \builder_interface7_bank_bus_we
95077     connect \Y $and$ls180.v:6172$1783_Y
95078   end
95079   attribute \src "ls180.v:6172.43-6172.148"
95080   cell $and $and$ls180.v:6172$1785
95081     parameter \A_SIGNED 0
95082     parameter \A_WIDTH 1
95083     parameter \B_SIGNED 0
95084     parameter \B_WIDTH 1
95085     parameter \Y_WIDTH 1
95086     connect \A $and$ls180.v:6172$1783_Y
95087     connect \B $eq$ls180.v:6172$1784_Y
95088     connect \Y $and$ls180.v:6172$1785_Y
95089   end
95090   attribute \src "ls180.v:6173.44-6173.100"
95091   cell $and $and$ls180.v:6173$1787
95092     parameter \A_SIGNED 0
95093     parameter \A_WIDTH 1
95094     parameter \B_SIGNED 0
95095     parameter \B_WIDTH 1
95096     parameter \Y_WIDTH 1
95097     connect \A \builder_csrbank7_sel
95098     connect \B $not$ls180.v:6173$1786_Y
95099     connect \Y $and$ls180.v:6173$1787_Y
95100   end
95101   attribute \src "ls180.v:6173.43-6173.151"
95102   cell $and $and$ls180.v:6173$1789
95103     parameter \A_SIGNED 0
95104     parameter \A_WIDTH 1
95105     parameter \B_SIGNED 0
95106     parameter \B_WIDTH 1
95107     parameter \Y_WIDTH 1
95108     connect \A $and$ls180.v:6173$1787_Y
95109     connect \B $eq$ls180.v:6173$1788_Y
95110     connect \Y $and$ls180.v:6173$1789_Y
95111   end
95112   attribute \src "ls180.v:6175.44-6175.97"
95113   cell $and $and$ls180.v:6175$1790
95114     parameter \A_SIGNED 0
95115     parameter \A_WIDTH 1
95116     parameter \B_SIGNED 0
95117     parameter \B_WIDTH 1
95118     parameter \Y_WIDTH 1
95119     connect \A \builder_csrbank7_sel
95120     connect \B \builder_interface7_bank_bus_we
95121     connect \Y $and$ls180.v:6175$1790_Y
95122   end
95123   attribute \src "ls180.v:6175.43-6175.148"
95124   cell $and $and$ls180.v:6175$1792
95125     parameter \A_SIGNED 0
95126     parameter \A_WIDTH 1
95127     parameter \B_SIGNED 0
95128     parameter \B_WIDTH 1
95129     parameter \Y_WIDTH 1
95130     connect \A $and$ls180.v:6175$1790_Y
95131     connect \B $eq$ls180.v:6175$1791_Y
95132     connect \Y $and$ls180.v:6175$1792_Y
95133   end
95134   attribute \src "ls180.v:6176.44-6176.100"
95135   cell $and $and$ls180.v:6176$1794
95136     parameter \A_SIGNED 0
95137     parameter \A_WIDTH 1
95138     parameter \B_SIGNED 0
95139     parameter \B_WIDTH 1
95140     parameter \Y_WIDTH 1
95141     connect \A \builder_csrbank7_sel
95142     connect \B $not$ls180.v:6176$1793_Y
95143     connect \Y $and$ls180.v:6176$1794_Y
95144   end
95145   attribute \src "ls180.v:6176.43-6176.151"
95146   cell $and $and$ls180.v:6176$1796
95147     parameter \A_SIGNED 0
95148     parameter \A_WIDTH 1
95149     parameter \B_SIGNED 0
95150     parameter \B_WIDTH 1
95151     parameter \Y_WIDTH 1
95152     connect \A $and$ls180.v:6176$1794_Y
95153     connect \B $eq$ls180.v:6176$1795_Y
95154     connect \Y $and$ls180.v:6176$1796_Y
95155   end
95156   attribute \src "ls180.v:6178.44-6178.97"
95157   cell $and $and$ls180.v:6178$1797
95158     parameter \A_SIGNED 0
95159     parameter \A_WIDTH 1
95160     parameter \B_SIGNED 0
95161     parameter \B_WIDTH 1
95162     parameter \Y_WIDTH 1
95163     connect \A \builder_csrbank7_sel
95164     connect \B \builder_interface7_bank_bus_we
95165     connect \Y $and$ls180.v:6178$1797_Y
95166   end
95167   attribute \src "ls180.v:6178.43-6178.148"
95168   cell $and $and$ls180.v:6178$1799
95169     parameter \A_SIGNED 0
95170     parameter \A_WIDTH 1
95171     parameter \B_SIGNED 0
95172     parameter \B_WIDTH 1
95173     parameter \Y_WIDTH 1
95174     connect \A $and$ls180.v:6178$1797_Y
95175     connect \B $eq$ls180.v:6178$1798_Y
95176     connect \Y $and$ls180.v:6178$1799_Y
95177   end
95178   attribute \src "ls180.v:6179.44-6179.100"
95179   cell $and $and$ls180.v:6179$1801
95180     parameter \A_SIGNED 0
95181     parameter \A_WIDTH 1
95182     parameter \B_SIGNED 0
95183     parameter \B_WIDTH 1
95184     parameter \Y_WIDTH 1
95185     connect \A \builder_csrbank7_sel
95186     connect \B $not$ls180.v:6179$1800_Y
95187     connect \Y $and$ls180.v:6179$1801_Y
95188   end
95189   attribute \src "ls180.v:6179.43-6179.151"
95190   cell $and $and$ls180.v:6179$1803
95191     parameter \A_SIGNED 0
95192     parameter \A_WIDTH 1
95193     parameter \B_SIGNED 0
95194     parameter \B_WIDTH 1
95195     parameter \Y_WIDTH 1
95196     connect \A $and$ls180.v:6179$1801_Y
95197     connect \B $eq$ls180.v:6179$1802_Y
95198     connect \Y $and$ls180.v:6179$1803_Y
95199   end
95200   attribute \src "ls180.v:6203.44-6203.97"
95201   cell $and $and$ls180.v:6203$1805
95202     parameter \A_SIGNED 0
95203     parameter \A_WIDTH 1
95204     parameter \B_SIGNED 0
95205     parameter \B_WIDTH 1
95206     parameter \Y_WIDTH 1
95207     connect \A \builder_csrbank8_sel
95208     connect \B \builder_interface8_bank_bus_we
95209     connect \Y $and$ls180.v:6203$1805_Y
95210   end
95211   attribute \src "ls180.v:6203.43-6203.147"
95212   cell $and $and$ls180.v:6203$1807
95213     parameter \A_SIGNED 0
95214     parameter \A_WIDTH 1
95215     parameter \B_SIGNED 0
95216     parameter \B_WIDTH 1
95217     parameter \Y_WIDTH 1
95218     connect \A $and$ls180.v:6203$1805_Y
95219     connect \B $eq$ls180.v:6203$1806_Y
95220     connect \Y $and$ls180.v:6203$1807_Y
95221   end
95222   attribute \src "ls180.v:6204.44-6204.100"
95223   cell $and $and$ls180.v:6204$1809
95224     parameter \A_SIGNED 0
95225     parameter \A_WIDTH 1
95226     parameter \B_SIGNED 0
95227     parameter \B_WIDTH 1
95228     parameter \Y_WIDTH 1
95229     connect \A \builder_csrbank8_sel
95230     connect \B $not$ls180.v:6204$1808_Y
95231     connect \Y $and$ls180.v:6204$1809_Y
95232   end
95233   attribute \src "ls180.v:6204.43-6204.150"
95234   cell $and $and$ls180.v:6204$1811
95235     parameter \A_SIGNED 0
95236     parameter \A_WIDTH 1
95237     parameter \B_SIGNED 0
95238     parameter \B_WIDTH 1
95239     parameter \Y_WIDTH 1
95240     connect \A $and$ls180.v:6204$1809_Y
95241     connect \B $eq$ls180.v:6204$1810_Y
95242     connect \Y $and$ls180.v:6204$1811_Y
95243   end
95244   attribute \src "ls180.v:6206.49-6206.102"
95245   cell $and $and$ls180.v:6206$1812
95246     parameter \A_SIGNED 0
95247     parameter \A_WIDTH 1
95248     parameter \B_SIGNED 0
95249     parameter \B_WIDTH 1
95250     parameter \Y_WIDTH 1
95251     connect \A \builder_csrbank8_sel
95252     connect \B \builder_interface8_bank_bus_we
95253     connect \Y $and$ls180.v:6206$1812_Y
95254   end
95255   attribute \src "ls180.v:6206.48-6206.152"
95256   cell $and $and$ls180.v:6206$1814
95257     parameter \A_SIGNED 0
95258     parameter \A_WIDTH 1
95259     parameter \B_SIGNED 0
95260     parameter \B_WIDTH 1
95261     parameter \Y_WIDTH 1
95262     connect \A $and$ls180.v:6206$1812_Y
95263     connect \B $eq$ls180.v:6206$1813_Y
95264     connect \Y $and$ls180.v:6206$1814_Y
95265   end
95266   attribute \src "ls180.v:6207.49-6207.105"
95267   cell $and $and$ls180.v:6207$1816
95268     parameter \A_SIGNED 0
95269     parameter \A_WIDTH 1
95270     parameter \B_SIGNED 0
95271     parameter \B_WIDTH 1
95272     parameter \Y_WIDTH 1
95273     connect \A \builder_csrbank8_sel
95274     connect \B $not$ls180.v:6207$1815_Y
95275     connect \Y $and$ls180.v:6207$1816_Y
95276   end
95277   attribute \src "ls180.v:6207.48-6207.155"
95278   cell $and $and$ls180.v:6207$1818
95279     parameter \A_SIGNED 0
95280     parameter \A_WIDTH 1
95281     parameter \B_SIGNED 0
95282     parameter \B_WIDTH 1
95283     parameter \Y_WIDTH 1
95284     connect \A $and$ls180.v:6207$1816_Y
95285     connect \B $eq$ls180.v:6207$1817_Y
95286     connect \Y $and$ls180.v:6207$1818_Y
95287   end
95288   attribute \src "ls180.v:6209.49-6209.102"
95289   cell $and $and$ls180.v:6209$1819
95290     parameter \A_SIGNED 0
95291     parameter \A_WIDTH 1
95292     parameter \B_SIGNED 0
95293     parameter \B_WIDTH 1
95294     parameter \Y_WIDTH 1
95295     connect \A \builder_csrbank8_sel
95296     connect \B \builder_interface8_bank_bus_we
95297     connect \Y $and$ls180.v:6209$1819_Y
95298   end
95299   attribute \src "ls180.v:6209.48-6209.152"
95300   cell $and $and$ls180.v:6209$1821
95301     parameter \A_SIGNED 0
95302     parameter \A_WIDTH 1
95303     parameter \B_SIGNED 0
95304     parameter \B_WIDTH 1
95305     parameter \Y_WIDTH 1
95306     connect \A $and$ls180.v:6209$1819_Y
95307     connect \B $eq$ls180.v:6209$1820_Y
95308     connect \Y $and$ls180.v:6209$1821_Y
95309   end
95310   attribute \src "ls180.v:6210.49-6210.105"
95311   cell $and $and$ls180.v:6210$1823
95312     parameter \A_SIGNED 0
95313     parameter \A_WIDTH 1
95314     parameter \B_SIGNED 0
95315     parameter \B_WIDTH 1
95316     parameter \Y_WIDTH 1
95317     connect \A \builder_csrbank8_sel
95318     connect \B $not$ls180.v:6210$1822_Y
95319     connect \Y $and$ls180.v:6210$1823_Y
95320   end
95321   attribute \src "ls180.v:6210.48-6210.155"
95322   cell $and $and$ls180.v:6210$1825
95323     parameter \A_SIGNED 0
95324     parameter \A_WIDTH 1
95325     parameter \B_SIGNED 0
95326     parameter \B_WIDTH 1
95327     parameter \Y_WIDTH 1
95328     connect \A $and$ls180.v:6210$1823_Y
95329     connect \B $eq$ls180.v:6210$1824_Y
95330     connect \Y $and$ls180.v:6210$1825_Y
95331   end
95332   attribute \src "ls180.v:6212.42-6212.95"
95333   cell $and $and$ls180.v:6212$1826
95334     parameter \A_SIGNED 0
95335     parameter \A_WIDTH 1
95336     parameter \B_SIGNED 0
95337     parameter \B_WIDTH 1
95338     parameter \Y_WIDTH 1
95339     connect \A \builder_csrbank8_sel
95340     connect \B \builder_interface8_bank_bus_we
95341     connect \Y $and$ls180.v:6212$1826_Y
95342   end
95343   attribute \src "ls180.v:6212.41-6212.145"
95344   cell $and $and$ls180.v:6212$1828
95345     parameter \A_SIGNED 0
95346     parameter \A_WIDTH 1
95347     parameter \B_SIGNED 0
95348     parameter \B_WIDTH 1
95349     parameter \Y_WIDTH 1
95350     connect \A $and$ls180.v:6212$1826_Y
95351     connect \B $eq$ls180.v:6212$1827_Y
95352     connect \Y $and$ls180.v:6212$1828_Y
95353   end
95354   attribute \src "ls180.v:6213.42-6213.98"
95355   cell $and $and$ls180.v:6213$1830
95356     parameter \A_SIGNED 0
95357     parameter \A_WIDTH 1
95358     parameter \B_SIGNED 0
95359     parameter \B_WIDTH 1
95360     parameter \Y_WIDTH 1
95361     connect \A \builder_csrbank8_sel
95362     connect \B $not$ls180.v:6213$1829_Y
95363     connect \Y $and$ls180.v:6213$1830_Y
95364   end
95365   attribute \src "ls180.v:6213.41-6213.148"
95366   cell $and $and$ls180.v:6213$1832
95367     parameter \A_SIGNED 0
95368     parameter \A_WIDTH 1
95369     parameter \B_SIGNED 0
95370     parameter \B_WIDTH 1
95371     parameter \Y_WIDTH 1
95372     connect \A $and$ls180.v:6213$1830_Y
95373     connect \B $eq$ls180.v:6213$1831_Y
95374     connect \Y $and$ls180.v:6213$1832_Y
95375   end
95376   attribute \src "ls180.v:6220.46-6220.99"
95377   cell $and $and$ls180.v:6220$1834
95378     parameter \A_SIGNED 0
95379     parameter \A_WIDTH 1
95380     parameter \B_SIGNED 0
95381     parameter \B_WIDTH 1
95382     parameter \Y_WIDTH 1
95383     connect \A \builder_csrbank9_sel
95384     connect \B \builder_interface9_bank_bus_we
95385     connect \Y $and$ls180.v:6220$1834_Y
95386   end
95387   attribute \src "ls180.v:6220.45-6220.149"
95388   cell $and $and$ls180.v:6220$1836
95389     parameter \A_SIGNED 0
95390     parameter \A_WIDTH 1
95391     parameter \B_SIGNED 0
95392     parameter \B_WIDTH 1
95393     parameter \Y_WIDTH 1
95394     connect \A $and$ls180.v:6220$1834_Y
95395     connect \B $eq$ls180.v:6220$1835_Y
95396     connect \Y $and$ls180.v:6220$1836_Y
95397   end
95398   attribute \src "ls180.v:6221.46-6221.102"
95399   cell $and $and$ls180.v:6221$1838
95400     parameter \A_SIGNED 0
95401     parameter \A_WIDTH 1
95402     parameter \B_SIGNED 0
95403     parameter \B_WIDTH 1
95404     parameter \Y_WIDTH 1
95405     connect \A \builder_csrbank9_sel
95406     connect \B $not$ls180.v:6221$1837_Y
95407     connect \Y $and$ls180.v:6221$1838_Y
95408   end
95409   attribute \src "ls180.v:6221.45-6221.152"
95410   cell $and $and$ls180.v:6221$1840
95411     parameter \A_SIGNED 0
95412     parameter \A_WIDTH 1
95413     parameter \B_SIGNED 0
95414     parameter \B_WIDTH 1
95415     parameter \Y_WIDTH 1
95416     connect \A $and$ls180.v:6221$1838_Y
95417     connect \B $eq$ls180.v:6221$1839_Y
95418     connect \Y $and$ls180.v:6221$1840_Y
95419   end
95420   attribute \src "ls180.v:6223.50-6223.103"
95421   cell $and $and$ls180.v:6223$1841
95422     parameter \A_SIGNED 0
95423     parameter \A_WIDTH 1
95424     parameter \B_SIGNED 0
95425     parameter \B_WIDTH 1
95426     parameter \Y_WIDTH 1
95427     connect \A \builder_csrbank9_sel
95428     connect \B \builder_interface9_bank_bus_we
95429     connect \Y $and$ls180.v:6223$1841_Y
95430   end
95431   attribute \src "ls180.v:6223.49-6223.153"
95432   cell $and $and$ls180.v:6223$1843
95433     parameter \A_SIGNED 0
95434     parameter \A_WIDTH 1
95435     parameter \B_SIGNED 0
95436     parameter \B_WIDTH 1
95437     parameter \Y_WIDTH 1
95438     connect \A $and$ls180.v:6223$1841_Y
95439     connect \B $eq$ls180.v:6223$1842_Y
95440     connect \Y $and$ls180.v:6223$1843_Y
95441   end
95442   attribute \src "ls180.v:6224.50-6224.106"
95443   cell $and $and$ls180.v:6224$1845
95444     parameter \A_SIGNED 0
95445     parameter \A_WIDTH 1
95446     parameter \B_SIGNED 0
95447     parameter \B_WIDTH 1
95448     parameter \Y_WIDTH 1
95449     connect \A \builder_csrbank9_sel
95450     connect \B $not$ls180.v:6224$1844_Y
95451     connect \Y $and$ls180.v:6224$1845_Y
95452   end
95453   attribute \src "ls180.v:6224.49-6224.156"
95454   cell $and $and$ls180.v:6224$1847
95455     parameter \A_SIGNED 0
95456     parameter \A_WIDTH 1
95457     parameter \B_SIGNED 0
95458     parameter \B_WIDTH 1
95459     parameter \Y_WIDTH 1
95460     connect \A $and$ls180.v:6224$1845_Y
95461     connect \B $eq$ls180.v:6224$1846_Y
95462     connect \Y $and$ls180.v:6224$1847_Y
95463   end
95464   attribute \src "ls180.v:6226.40-6226.93"
95465   cell $and $and$ls180.v:6226$1848
95466     parameter \A_SIGNED 0
95467     parameter \A_WIDTH 1
95468     parameter \B_SIGNED 0
95469     parameter \B_WIDTH 1
95470     parameter \Y_WIDTH 1
95471     connect \A \builder_csrbank9_sel
95472     connect \B \builder_interface9_bank_bus_we
95473     connect \Y $and$ls180.v:6226$1848_Y
95474   end
95475   attribute \src "ls180.v:6226.39-6226.143"
95476   cell $and $and$ls180.v:6226$1850
95477     parameter \A_SIGNED 0
95478     parameter \A_WIDTH 1
95479     parameter \B_SIGNED 0
95480     parameter \B_WIDTH 1
95481     parameter \Y_WIDTH 1
95482     connect \A $and$ls180.v:6226$1848_Y
95483     connect \B $eq$ls180.v:6226$1849_Y
95484     connect \Y $and$ls180.v:6226$1850_Y
95485   end
95486   attribute \src "ls180.v:6227.40-6227.96"
95487   cell $and $and$ls180.v:6227$1852
95488     parameter \A_SIGNED 0
95489     parameter \A_WIDTH 1
95490     parameter \B_SIGNED 0
95491     parameter \B_WIDTH 1
95492     parameter \Y_WIDTH 1
95493     connect \A \builder_csrbank9_sel
95494     connect \B $not$ls180.v:6227$1851_Y
95495     connect \Y $and$ls180.v:6227$1852_Y
95496   end
95497   attribute \src "ls180.v:6227.39-6227.146"
95498   cell $and $and$ls180.v:6227$1854
95499     parameter \A_SIGNED 0
95500     parameter \A_WIDTH 1
95501     parameter \B_SIGNED 0
95502     parameter \B_WIDTH 1
95503     parameter \Y_WIDTH 1
95504     connect \A $and$ls180.v:6227$1852_Y
95505     connect \B $eq$ls180.v:6227$1853_Y
95506     connect \Y $and$ls180.v:6227$1854_Y
95507   end
95508   attribute \src "ls180.v:6229.50-6229.103"
95509   cell $and $and$ls180.v:6229$1855
95510     parameter \A_SIGNED 0
95511     parameter \A_WIDTH 1
95512     parameter \B_SIGNED 0
95513     parameter \B_WIDTH 1
95514     parameter \Y_WIDTH 1
95515     connect \A \builder_csrbank9_sel
95516     connect \B \builder_interface9_bank_bus_we
95517     connect \Y $and$ls180.v:6229$1855_Y
95518   end
95519   attribute \src "ls180.v:6229.49-6229.153"
95520   cell $and $and$ls180.v:6229$1857
95521     parameter \A_SIGNED 0
95522     parameter \A_WIDTH 1
95523     parameter \B_SIGNED 0
95524     parameter \B_WIDTH 1
95525     parameter \Y_WIDTH 1
95526     connect \A $and$ls180.v:6229$1855_Y
95527     connect \B $eq$ls180.v:6229$1856_Y
95528     connect \Y $and$ls180.v:6229$1857_Y
95529   end
95530   attribute \src "ls180.v:6230.50-6230.106"
95531   cell $and $and$ls180.v:6230$1859
95532     parameter \A_SIGNED 0
95533     parameter \A_WIDTH 1
95534     parameter \B_SIGNED 0
95535     parameter \B_WIDTH 1
95536     parameter \Y_WIDTH 1
95537     connect \A \builder_csrbank9_sel
95538     connect \B $not$ls180.v:6230$1858_Y
95539     connect \Y $and$ls180.v:6230$1859_Y
95540   end
95541   attribute \src "ls180.v:6230.49-6230.156"
95542   cell $and $and$ls180.v:6230$1861
95543     parameter \A_SIGNED 0
95544     parameter \A_WIDTH 1
95545     parameter \B_SIGNED 0
95546     parameter \B_WIDTH 1
95547     parameter \Y_WIDTH 1
95548     connect \A $and$ls180.v:6230$1859_Y
95549     connect \B $eq$ls180.v:6230$1860_Y
95550     connect \Y $and$ls180.v:6230$1861_Y
95551   end
95552   attribute \src "ls180.v:6232.50-6232.103"
95553   cell $and $and$ls180.v:6232$1862
95554     parameter \A_SIGNED 0
95555     parameter \A_WIDTH 1
95556     parameter \B_SIGNED 0
95557     parameter \B_WIDTH 1
95558     parameter \Y_WIDTH 1
95559     connect \A \builder_csrbank9_sel
95560     connect \B \builder_interface9_bank_bus_we
95561     connect \Y $and$ls180.v:6232$1862_Y
95562   end
95563   attribute \src "ls180.v:6232.49-6232.153"
95564   cell $and $and$ls180.v:6232$1864
95565     parameter \A_SIGNED 0
95566     parameter \A_WIDTH 1
95567     parameter \B_SIGNED 0
95568     parameter \B_WIDTH 1
95569     parameter \Y_WIDTH 1
95570     connect \A $and$ls180.v:6232$1862_Y
95571     connect \B $eq$ls180.v:6232$1863_Y
95572     connect \Y $and$ls180.v:6232$1864_Y
95573   end
95574   attribute \src "ls180.v:6233.50-6233.106"
95575   cell $and $and$ls180.v:6233$1866
95576     parameter \A_SIGNED 0
95577     parameter \A_WIDTH 1
95578     parameter \B_SIGNED 0
95579     parameter \B_WIDTH 1
95580     parameter \Y_WIDTH 1
95581     connect \A \builder_csrbank9_sel
95582     connect \B $not$ls180.v:6233$1865_Y
95583     connect \Y $and$ls180.v:6233$1866_Y
95584   end
95585   attribute \src "ls180.v:6233.49-6233.156"
95586   cell $and $and$ls180.v:6233$1868
95587     parameter \A_SIGNED 0
95588     parameter \A_WIDTH 1
95589     parameter \B_SIGNED 0
95590     parameter \B_WIDTH 1
95591     parameter \Y_WIDTH 1
95592     connect \A $and$ls180.v:6233$1866_Y
95593     connect \B $eq$ls180.v:6233$1867_Y
95594     connect \Y $and$ls180.v:6233$1868_Y
95595   end
95596   attribute \src "ls180.v:6235.51-6235.104"
95597   cell $and $and$ls180.v:6235$1869
95598     parameter \A_SIGNED 0
95599     parameter \A_WIDTH 1
95600     parameter \B_SIGNED 0
95601     parameter \B_WIDTH 1
95602     parameter \Y_WIDTH 1
95603     connect \A \builder_csrbank9_sel
95604     connect \B \builder_interface9_bank_bus_we
95605     connect \Y $and$ls180.v:6235$1869_Y
95606   end
95607   attribute \src "ls180.v:6235.50-6235.154"
95608   cell $and $and$ls180.v:6235$1871
95609     parameter \A_SIGNED 0
95610     parameter \A_WIDTH 1
95611     parameter \B_SIGNED 0
95612     parameter \B_WIDTH 1
95613     parameter \Y_WIDTH 1
95614     connect \A $and$ls180.v:6235$1869_Y
95615     connect \B $eq$ls180.v:6235$1870_Y
95616     connect \Y $and$ls180.v:6235$1871_Y
95617   end
95618   attribute \src "ls180.v:6236.51-6236.107"
95619   cell $and $and$ls180.v:6236$1873
95620     parameter \A_SIGNED 0
95621     parameter \A_WIDTH 1
95622     parameter \B_SIGNED 0
95623     parameter \B_WIDTH 1
95624     parameter \Y_WIDTH 1
95625     connect \A \builder_csrbank9_sel
95626     connect \B $not$ls180.v:6236$1872_Y
95627     connect \Y $and$ls180.v:6236$1873_Y
95628   end
95629   attribute \src "ls180.v:6236.50-6236.157"
95630   cell $and $and$ls180.v:6236$1875
95631     parameter \A_SIGNED 0
95632     parameter \A_WIDTH 1
95633     parameter \B_SIGNED 0
95634     parameter \B_WIDTH 1
95635     parameter \Y_WIDTH 1
95636     connect \A $and$ls180.v:6236$1873_Y
95637     connect \B $eq$ls180.v:6236$1874_Y
95638     connect \Y $and$ls180.v:6236$1875_Y
95639   end
95640   attribute \src "ls180.v:6238.49-6238.102"
95641   cell $and $and$ls180.v:6238$1876
95642     parameter \A_SIGNED 0
95643     parameter \A_WIDTH 1
95644     parameter \B_SIGNED 0
95645     parameter \B_WIDTH 1
95646     parameter \Y_WIDTH 1
95647     connect \A \builder_csrbank9_sel
95648     connect \B \builder_interface9_bank_bus_we
95649     connect \Y $and$ls180.v:6238$1876_Y
95650   end
95651   attribute \src "ls180.v:6238.48-6238.152"
95652   cell $and $and$ls180.v:6238$1878
95653     parameter \A_SIGNED 0
95654     parameter \A_WIDTH 1
95655     parameter \B_SIGNED 0
95656     parameter \B_WIDTH 1
95657     parameter \Y_WIDTH 1
95658     connect \A $and$ls180.v:6238$1876_Y
95659     connect \B $eq$ls180.v:6238$1877_Y
95660     connect \Y $and$ls180.v:6238$1878_Y
95661   end
95662   attribute \src "ls180.v:6239.49-6239.105"
95663   cell $and $and$ls180.v:6239$1880
95664     parameter \A_SIGNED 0
95665     parameter \A_WIDTH 1
95666     parameter \B_SIGNED 0
95667     parameter \B_WIDTH 1
95668     parameter \Y_WIDTH 1
95669     connect \A \builder_csrbank9_sel
95670     connect \B $not$ls180.v:6239$1879_Y
95671     connect \Y $and$ls180.v:6239$1880_Y
95672   end
95673   attribute \src "ls180.v:6239.48-6239.155"
95674   cell $and $and$ls180.v:6239$1882
95675     parameter \A_SIGNED 0
95676     parameter \A_WIDTH 1
95677     parameter \B_SIGNED 0
95678     parameter \B_WIDTH 1
95679     parameter \Y_WIDTH 1
95680     connect \A $and$ls180.v:6239$1880_Y
95681     connect \B $eq$ls180.v:6239$1881_Y
95682     connect \Y $and$ls180.v:6239$1882_Y
95683   end
95684   attribute \src "ls180.v:6241.49-6241.102"
95685   cell $and $and$ls180.v:6241$1883
95686     parameter \A_SIGNED 0
95687     parameter \A_WIDTH 1
95688     parameter \B_SIGNED 0
95689     parameter \B_WIDTH 1
95690     parameter \Y_WIDTH 1
95691     connect \A \builder_csrbank9_sel
95692     connect \B \builder_interface9_bank_bus_we
95693     connect \Y $and$ls180.v:6241$1883_Y
95694   end
95695   attribute \src "ls180.v:6241.48-6241.152"
95696   cell $and $and$ls180.v:6241$1885
95697     parameter \A_SIGNED 0
95698     parameter \A_WIDTH 1
95699     parameter \B_SIGNED 0
95700     parameter \B_WIDTH 1
95701     parameter \Y_WIDTH 1
95702     connect \A $and$ls180.v:6241$1883_Y
95703     connect \B $eq$ls180.v:6241$1884_Y
95704     connect \Y $and$ls180.v:6241$1885_Y
95705   end
95706   attribute \src "ls180.v:6242.49-6242.105"
95707   cell $and $and$ls180.v:6242$1887
95708     parameter \A_SIGNED 0
95709     parameter \A_WIDTH 1
95710     parameter \B_SIGNED 0
95711     parameter \B_WIDTH 1
95712     parameter \Y_WIDTH 1
95713     connect \A \builder_csrbank9_sel
95714     connect \B $not$ls180.v:6242$1886_Y
95715     connect \Y $and$ls180.v:6242$1887_Y
95716   end
95717   attribute \src "ls180.v:6242.48-6242.155"
95718   cell $and $and$ls180.v:6242$1889
95719     parameter \A_SIGNED 0
95720     parameter \A_WIDTH 1
95721     parameter \B_SIGNED 0
95722     parameter \B_WIDTH 1
95723     parameter \Y_WIDTH 1
95724     connect \A $and$ls180.v:6242$1887_Y
95725     connect \B $eq$ls180.v:6242$1888_Y
95726     connect \Y $and$ls180.v:6242$1889_Y
95727   end
95728   attribute \src "ls180.v:6244.49-6244.102"
95729   cell $and $and$ls180.v:6244$1890
95730     parameter \A_SIGNED 0
95731     parameter \A_WIDTH 1
95732     parameter \B_SIGNED 0
95733     parameter \B_WIDTH 1
95734     parameter \Y_WIDTH 1
95735     connect \A \builder_csrbank9_sel
95736     connect \B \builder_interface9_bank_bus_we
95737     connect \Y $and$ls180.v:6244$1890_Y
95738   end
95739   attribute \src "ls180.v:6244.48-6244.152"
95740   cell $and $and$ls180.v:6244$1892
95741     parameter \A_SIGNED 0
95742     parameter \A_WIDTH 1
95743     parameter \B_SIGNED 0
95744     parameter \B_WIDTH 1
95745     parameter \Y_WIDTH 1
95746     connect \A $and$ls180.v:6244$1890_Y
95747     connect \B $eq$ls180.v:6244$1891_Y
95748     connect \Y $and$ls180.v:6244$1892_Y
95749   end
95750   attribute \src "ls180.v:6245.49-6245.105"
95751   cell $and $and$ls180.v:6245$1894
95752     parameter \A_SIGNED 0
95753     parameter \A_WIDTH 1
95754     parameter \B_SIGNED 0
95755     parameter \B_WIDTH 1
95756     parameter \Y_WIDTH 1
95757     connect \A \builder_csrbank9_sel
95758     connect \B $not$ls180.v:6245$1893_Y
95759     connect \Y $and$ls180.v:6245$1894_Y
95760   end
95761   attribute \src "ls180.v:6245.48-6245.155"
95762   cell $and $and$ls180.v:6245$1896
95763     parameter \A_SIGNED 0
95764     parameter \A_WIDTH 1
95765     parameter \B_SIGNED 0
95766     parameter \B_WIDTH 1
95767     parameter \Y_WIDTH 1
95768     connect \A $and$ls180.v:6245$1894_Y
95769     connect \B $eq$ls180.v:6245$1895_Y
95770     connect \Y $and$ls180.v:6245$1896_Y
95771   end
95772   attribute \src "ls180.v:6247.49-6247.102"
95773   cell $and $and$ls180.v:6247$1897
95774     parameter \A_SIGNED 0
95775     parameter \A_WIDTH 1
95776     parameter \B_SIGNED 0
95777     parameter \B_WIDTH 1
95778     parameter \Y_WIDTH 1
95779     connect \A \builder_csrbank9_sel
95780     connect \B \builder_interface9_bank_bus_we
95781     connect \Y $and$ls180.v:6247$1897_Y
95782   end
95783   attribute \src "ls180.v:6247.48-6247.152"
95784   cell $and $and$ls180.v:6247$1899
95785     parameter \A_SIGNED 0
95786     parameter \A_WIDTH 1
95787     parameter \B_SIGNED 0
95788     parameter \B_WIDTH 1
95789     parameter \Y_WIDTH 1
95790     connect \A $and$ls180.v:6247$1897_Y
95791     connect \B $eq$ls180.v:6247$1898_Y
95792     connect \Y $and$ls180.v:6247$1899_Y
95793   end
95794   attribute \src "ls180.v:6248.49-6248.105"
95795   cell $and $and$ls180.v:6248$1901
95796     parameter \A_SIGNED 0
95797     parameter \A_WIDTH 1
95798     parameter \B_SIGNED 0
95799     parameter \B_WIDTH 1
95800     parameter \Y_WIDTH 1
95801     connect \A \builder_csrbank9_sel
95802     connect \B $not$ls180.v:6248$1900_Y
95803     connect \Y $and$ls180.v:6248$1901_Y
95804   end
95805   attribute \src "ls180.v:6248.48-6248.155"
95806   cell $and $and$ls180.v:6248$1903
95807     parameter \A_SIGNED 0
95808     parameter \A_WIDTH 1
95809     parameter \B_SIGNED 0
95810     parameter \B_WIDTH 1
95811     parameter \Y_WIDTH 1
95812     connect \A $and$ls180.v:6248$1901_Y
95813     connect \B $eq$ls180.v:6248$1902_Y
95814     connect \Y $and$ls180.v:6248$1903_Y
95815   end
95816   attribute \src "ls180.v:6265.42-6265.97"
95817   cell $and $and$ls180.v:6265$1905
95818     parameter \A_SIGNED 0
95819     parameter \A_WIDTH 1
95820     parameter \B_SIGNED 0
95821     parameter \B_WIDTH 1
95822     parameter \Y_WIDTH 1
95823     connect \A \builder_csrbank10_sel
95824     connect \B \builder_interface10_bank_bus_we
95825     connect \Y $and$ls180.v:6265$1905_Y
95826   end
95827   attribute \src "ls180.v:6265.41-6265.148"
95828   cell $and $and$ls180.v:6265$1907
95829     parameter \A_SIGNED 0
95830     parameter \A_WIDTH 1
95831     parameter \B_SIGNED 0
95832     parameter \B_WIDTH 1
95833     parameter \Y_WIDTH 1
95834     connect \A $and$ls180.v:6265$1905_Y
95835     connect \B $eq$ls180.v:6265$1906_Y
95836     connect \Y $and$ls180.v:6265$1907_Y
95837   end
95838   attribute \src "ls180.v:6266.42-6266.100"
95839   cell $and $and$ls180.v:6266$1909
95840     parameter \A_SIGNED 0
95841     parameter \A_WIDTH 1
95842     parameter \B_SIGNED 0
95843     parameter \B_WIDTH 1
95844     parameter \Y_WIDTH 1
95845     connect \A \builder_csrbank10_sel
95846     connect \B $not$ls180.v:6266$1908_Y
95847     connect \Y $and$ls180.v:6266$1909_Y
95848   end
95849   attribute \src "ls180.v:6266.41-6266.151"
95850   cell $and $and$ls180.v:6266$1911
95851     parameter \A_SIGNED 0
95852     parameter \A_WIDTH 1
95853     parameter \B_SIGNED 0
95854     parameter \B_WIDTH 1
95855     parameter \Y_WIDTH 1
95856     connect \A $and$ls180.v:6266$1909_Y
95857     connect \B $eq$ls180.v:6266$1910_Y
95858     connect \Y $and$ls180.v:6266$1911_Y
95859   end
95860   attribute \src "ls180.v:6268.42-6268.97"
95861   cell $and $and$ls180.v:6268$1912
95862     parameter \A_SIGNED 0
95863     parameter \A_WIDTH 1
95864     parameter \B_SIGNED 0
95865     parameter \B_WIDTH 1
95866     parameter \Y_WIDTH 1
95867     connect \A \builder_csrbank10_sel
95868     connect \B \builder_interface10_bank_bus_we
95869     connect \Y $and$ls180.v:6268$1912_Y
95870   end
95871   attribute \src "ls180.v:6268.41-6268.148"
95872   cell $and $and$ls180.v:6268$1914
95873     parameter \A_SIGNED 0
95874     parameter \A_WIDTH 1
95875     parameter \B_SIGNED 0
95876     parameter \B_WIDTH 1
95877     parameter \Y_WIDTH 1
95878     connect \A $and$ls180.v:6268$1912_Y
95879     connect \B $eq$ls180.v:6268$1913_Y
95880     connect \Y $and$ls180.v:6268$1914_Y
95881   end
95882   attribute \src "ls180.v:6269.42-6269.100"
95883   cell $and $and$ls180.v:6269$1916
95884     parameter \A_SIGNED 0
95885     parameter \A_WIDTH 1
95886     parameter \B_SIGNED 0
95887     parameter \B_WIDTH 1
95888     parameter \Y_WIDTH 1
95889     connect \A \builder_csrbank10_sel
95890     connect \B $not$ls180.v:6269$1915_Y
95891     connect \Y $and$ls180.v:6269$1916_Y
95892   end
95893   attribute \src "ls180.v:6269.41-6269.151"
95894   cell $and $and$ls180.v:6269$1918
95895     parameter \A_SIGNED 0
95896     parameter \A_WIDTH 1
95897     parameter \B_SIGNED 0
95898     parameter \B_WIDTH 1
95899     parameter \Y_WIDTH 1
95900     connect \A $and$ls180.v:6269$1916_Y
95901     connect \B $eq$ls180.v:6269$1917_Y
95902     connect \Y $and$ls180.v:6269$1918_Y
95903   end
95904   attribute \src "ls180.v:6271.40-6271.95"
95905   cell $and $and$ls180.v:6271$1919
95906     parameter \A_SIGNED 0
95907     parameter \A_WIDTH 1
95908     parameter \B_SIGNED 0
95909     parameter \B_WIDTH 1
95910     parameter \Y_WIDTH 1
95911     connect \A \builder_csrbank10_sel
95912     connect \B \builder_interface10_bank_bus_we
95913     connect \Y $and$ls180.v:6271$1919_Y
95914   end
95915   attribute \src "ls180.v:6271.39-6271.146"
95916   cell $and $and$ls180.v:6271$1921
95917     parameter \A_SIGNED 0
95918     parameter \A_WIDTH 1
95919     parameter \B_SIGNED 0
95920     parameter \B_WIDTH 1
95921     parameter \Y_WIDTH 1
95922     connect \A $and$ls180.v:6271$1919_Y
95923     connect \B $eq$ls180.v:6271$1920_Y
95924     connect \Y $and$ls180.v:6271$1921_Y
95925   end
95926   attribute \src "ls180.v:6272.40-6272.98"
95927   cell $and $and$ls180.v:6272$1923
95928     parameter \A_SIGNED 0
95929     parameter \A_WIDTH 1
95930     parameter \B_SIGNED 0
95931     parameter \B_WIDTH 1
95932     parameter \Y_WIDTH 1
95933     connect \A \builder_csrbank10_sel
95934     connect \B $not$ls180.v:6272$1922_Y
95935     connect \Y $and$ls180.v:6272$1923_Y
95936   end
95937   attribute \src "ls180.v:6272.39-6272.149"
95938   cell $and $and$ls180.v:6272$1925
95939     parameter \A_SIGNED 0
95940     parameter \A_WIDTH 1
95941     parameter \B_SIGNED 0
95942     parameter \B_WIDTH 1
95943     parameter \Y_WIDTH 1
95944     connect \A $and$ls180.v:6272$1923_Y
95945     connect \B $eq$ls180.v:6272$1924_Y
95946     connect \Y $and$ls180.v:6272$1925_Y
95947   end
95948   attribute \src "ls180.v:6274.39-6274.94"
95949   cell $and $and$ls180.v:6274$1926
95950     parameter \A_SIGNED 0
95951     parameter \A_WIDTH 1
95952     parameter \B_SIGNED 0
95953     parameter \B_WIDTH 1
95954     parameter \Y_WIDTH 1
95955     connect \A \builder_csrbank10_sel
95956     connect \B \builder_interface10_bank_bus_we
95957     connect \Y $and$ls180.v:6274$1926_Y
95958   end
95959   attribute \src "ls180.v:6274.38-6274.145"
95960   cell $and $and$ls180.v:6274$1928
95961     parameter \A_SIGNED 0
95962     parameter \A_WIDTH 1
95963     parameter \B_SIGNED 0
95964     parameter \B_WIDTH 1
95965     parameter \Y_WIDTH 1
95966     connect \A $and$ls180.v:6274$1926_Y
95967     connect \B $eq$ls180.v:6274$1927_Y
95968     connect \Y $and$ls180.v:6274$1928_Y
95969   end
95970   attribute \src "ls180.v:6275.39-6275.97"
95971   cell $and $and$ls180.v:6275$1930
95972     parameter \A_SIGNED 0
95973     parameter \A_WIDTH 1
95974     parameter \B_SIGNED 0
95975     parameter \B_WIDTH 1
95976     parameter \Y_WIDTH 1
95977     connect \A \builder_csrbank10_sel
95978     connect \B $not$ls180.v:6275$1929_Y
95979     connect \Y $and$ls180.v:6275$1930_Y
95980   end
95981   attribute \src "ls180.v:6275.38-6275.148"
95982   cell $and $and$ls180.v:6275$1932
95983     parameter \A_SIGNED 0
95984     parameter \A_WIDTH 1
95985     parameter \B_SIGNED 0
95986     parameter \B_WIDTH 1
95987     parameter \Y_WIDTH 1
95988     connect \A $and$ls180.v:6275$1930_Y
95989     connect \B $eq$ls180.v:6275$1931_Y
95990     connect \Y $and$ls180.v:6275$1932_Y
95991   end
95992   attribute \src "ls180.v:6277.38-6277.93"
95993   cell $and $and$ls180.v:6277$1933
95994     parameter \A_SIGNED 0
95995     parameter \A_WIDTH 1
95996     parameter \B_SIGNED 0
95997     parameter \B_WIDTH 1
95998     parameter \Y_WIDTH 1
95999     connect \A \builder_csrbank10_sel
96000     connect \B \builder_interface10_bank_bus_we
96001     connect \Y $and$ls180.v:6277$1933_Y
96002   end
96003   attribute \src "ls180.v:6277.37-6277.144"
96004   cell $and $and$ls180.v:6277$1935
96005     parameter \A_SIGNED 0
96006     parameter \A_WIDTH 1
96007     parameter \B_SIGNED 0
96008     parameter \B_WIDTH 1
96009     parameter \Y_WIDTH 1
96010     connect \A $and$ls180.v:6277$1933_Y
96011     connect \B $eq$ls180.v:6277$1934_Y
96012     connect \Y $and$ls180.v:6277$1935_Y
96013   end
96014   attribute \src "ls180.v:6278.38-6278.96"
96015   cell $and $and$ls180.v:6278$1937
96016     parameter \A_SIGNED 0
96017     parameter \A_WIDTH 1
96018     parameter \B_SIGNED 0
96019     parameter \B_WIDTH 1
96020     parameter \Y_WIDTH 1
96021     connect \A \builder_csrbank10_sel
96022     connect \B $not$ls180.v:6278$1936_Y
96023     connect \Y $and$ls180.v:6278$1937_Y
96024   end
96025   attribute \src "ls180.v:6278.37-6278.147"
96026   cell $and $and$ls180.v:6278$1939
96027     parameter \A_SIGNED 0
96028     parameter \A_WIDTH 1
96029     parameter \B_SIGNED 0
96030     parameter \B_WIDTH 1
96031     parameter \Y_WIDTH 1
96032     connect \A $and$ls180.v:6278$1937_Y
96033     connect \B $eq$ls180.v:6278$1938_Y
96034     connect \Y $and$ls180.v:6278$1939_Y
96035   end
96036   attribute \src "ls180.v:6280.37-6280.92"
96037   cell $and $and$ls180.v:6280$1940
96038     parameter \A_SIGNED 0
96039     parameter \A_WIDTH 1
96040     parameter \B_SIGNED 0
96041     parameter \B_WIDTH 1
96042     parameter \Y_WIDTH 1
96043     connect \A \builder_csrbank10_sel
96044     connect \B \builder_interface10_bank_bus_we
96045     connect \Y $and$ls180.v:6280$1940_Y
96046   end
96047   attribute \src "ls180.v:6280.36-6280.143"
96048   cell $and $and$ls180.v:6280$1942
96049     parameter \A_SIGNED 0
96050     parameter \A_WIDTH 1
96051     parameter \B_SIGNED 0
96052     parameter \B_WIDTH 1
96053     parameter \Y_WIDTH 1
96054     connect \A $and$ls180.v:6280$1940_Y
96055     connect \B $eq$ls180.v:6280$1941_Y
96056     connect \Y $and$ls180.v:6280$1942_Y
96057   end
96058   attribute \src "ls180.v:6281.37-6281.95"
96059   cell $and $and$ls180.v:6281$1944
96060     parameter \A_SIGNED 0
96061     parameter \A_WIDTH 1
96062     parameter \B_SIGNED 0
96063     parameter \B_WIDTH 1
96064     parameter \Y_WIDTH 1
96065     connect \A \builder_csrbank10_sel
96066     connect \B $not$ls180.v:6281$1943_Y
96067     connect \Y $and$ls180.v:6281$1944_Y
96068   end
96069   attribute \src "ls180.v:6281.36-6281.146"
96070   cell $and $and$ls180.v:6281$1946
96071     parameter \A_SIGNED 0
96072     parameter \A_WIDTH 1
96073     parameter \B_SIGNED 0
96074     parameter \B_WIDTH 1
96075     parameter \Y_WIDTH 1
96076     connect \A $and$ls180.v:6281$1944_Y
96077     connect \B $eq$ls180.v:6281$1945_Y
96078     connect \Y $and$ls180.v:6281$1946_Y
96079   end
96080   attribute \src "ls180.v:6283.43-6283.98"
96081   cell $and $and$ls180.v:6283$1947
96082     parameter \A_SIGNED 0
96083     parameter \A_WIDTH 1
96084     parameter \B_SIGNED 0
96085     parameter \B_WIDTH 1
96086     parameter \Y_WIDTH 1
96087     connect \A \builder_csrbank10_sel
96088     connect \B \builder_interface10_bank_bus_we
96089     connect \Y $and$ls180.v:6283$1947_Y
96090   end
96091   attribute \src "ls180.v:6283.42-6283.149"
96092   cell $and $and$ls180.v:6283$1949
96093     parameter \A_SIGNED 0
96094     parameter \A_WIDTH 1
96095     parameter \B_SIGNED 0
96096     parameter \B_WIDTH 1
96097     parameter \Y_WIDTH 1
96098     connect \A $and$ls180.v:6283$1947_Y
96099     connect \B $eq$ls180.v:6283$1948_Y
96100     connect \Y $and$ls180.v:6283$1949_Y
96101   end
96102   attribute \src "ls180.v:6284.43-6284.101"
96103   cell $and $and$ls180.v:6284$1951
96104     parameter \A_SIGNED 0
96105     parameter \A_WIDTH 1
96106     parameter \B_SIGNED 0
96107     parameter \B_WIDTH 1
96108     parameter \Y_WIDTH 1
96109     connect \A \builder_csrbank10_sel
96110     connect \B $not$ls180.v:6284$1950_Y
96111     connect \Y $and$ls180.v:6284$1951_Y
96112   end
96113   attribute \src "ls180.v:6284.42-6284.152"
96114   cell $and $and$ls180.v:6284$1953
96115     parameter \A_SIGNED 0
96116     parameter \A_WIDTH 1
96117     parameter \B_SIGNED 0
96118     parameter \B_WIDTH 1
96119     parameter \Y_WIDTH 1
96120     connect \A $and$ls180.v:6284$1951_Y
96121     connect \B $eq$ls180.v:6284$1952_Y
96122     connect \Y $and$ls180.v:6284$1953_Y
96123   end
96124   attribute \src "ls180.v:6305.42-6305.97"
96125   cell $and $and$ls180.v:6305$1956
96126     parameter \A_SIGNED 0
96127     parameter \A_WIDTH 1
96128     parameter \B_SIGNED 0
96129     parameter \B_WIDTH 1
96130     parameter \Y_WIDTH 1
96131     connect \A \builder_csrbank11_sel
96132     connect \B \builder_interface11_bank_bus_we
96133     connect \Y $and$ls180.v:6305$1956_Y
96134   end
96135   attribute \src "ls180.v:6305.41-6305.148"
96136   cell $and $and$ls180.v:6305$1958
96137     parameter \A_SIGNED 0
96138     parameter \A_WIDTH 1
96139     parameter \B_SIGNED 0
96140     parameter \B_WIDTH 1
96141     parameter \Y_WIDTH 1
96142     connect \A $and$ls180.v:6305$1956_Y
96143     connect \B $eq$ls180.v:6305$1957_Y
96144     connect \Y $and$ls180.v:6305$1958_Y
96145   end
96146   attribute \src "ls180.v:6306.42-6306.100"
96147   cell $and $and$ls180.v:6306$1960
96148     parameter \A_SIGNED 0
96149     parameter \A_WIDTH 1
96150     parameter \B_SIGNED 0
96151     parameter \B_WIDTH 1
96152     parameter \Y_WIDTH 1
96153     connect \A \builder_csrbank11_sel
96154     connect \B $not$ls180.v:6306$1959_Y
96155     connect \Y $and$ls180.v:6306$1960_Y
96156   end
96157   attribute \src "ls180.v:6306.41-6306.151"
96158   cell $and $and$ls180.v:6306$1962
96159     parameter \A_SIGNED 0
96160     parameter \A_WIDTH 1
96161     parameter \B_SIGNED 0
96162     parameter \B_WIDTH 1
96163     parameter \Y_WIDTH 1
96164     connect \A $and$ls180.v:6306$1960_Y
96165     connect \B $eq$ls180.v:6306$1961_Y
96166     connect \Y $and$ls180.v:6306$1962_Y
96167   end
96168   attribute \src "ls180.v:6308.42-6308.97"
96169   cell $and $and$ls180.v:6308$1963
96170     parameter \A_SIGNED 0
96171     parameter \A_WIDTH 1
96172     parameter \B_SIGNED 0
96173     parameter \B_WIDTH 1
96174     parameter \Y_WIDTH 1
96175     connect \A \builder_csrbank11_sel
96176     connect \B \builder_interface11_bank_bus_we
96177     connect \Y $and$ls180.v:6308$1963_Y
96178   end
96179   attribute \src "ls180.v:6308.41-6308.148"
96180   cell $and $and$ls180.v:6308$1965
96181     parameter \A_SIGNED 0
96182     parameter \A_WIDTH 1
96183     parameter \B_SIGNED 0
96184     parameter \B_WIDTH 1
96185     parameter \Y_WIDTH 1
96186     connect \A $and$ls180.v:6308$1963_Y
96187     connect \B $eq$ls180.v:6308$1964_Y
96188     connect \Y $and$ls180.v:6308$1965_Y
96189   end
96190   attribute \src "ls180.v:6309.42-6309.100"
96191   cell $and $and$ls180.v:6309$1967
96192     parameter \A_SIGNED 0
96193     parameter \A_WIDTH 1
96194     parameter \B_SIGNED 0
96195     parameter \B_WIDTH 1
96196     parameter \Y_WIDTH 1
96197     connect \A \builder_csrbank11_sel
96198     connect \B $not$ls180.v:6309$1966_Y
96199     connect \Y $and$ls180.v:6309$1967_Y
96200   end
96201   attribute \src "ls180.v:6309.41-6309.151"
96202   cell $and $and$ls180.v:6309$1969
96203     parameter \A_SIGNED 0
96204     parameter \A_WIDTH 1
96205     parameter \B_SIGNED 0
96206     parameter \B_WIDTH 1
96207     parameter \Y_WIDTH 1
96208     connect \A $and$ls180.v:6309$1967_Y
96209     connect \B $eq$ls180.v:6309$1968_Y
96210     connect \Y $and$ls180.v:6309$1969_Y
96211   end
96212   attribute \src "ls180.v:6311.40-6311.95"
96213   cell $and $and$ls180.v:6311$1970
96214     parameter \A_SIGNED 0
96215     parameter \A_WIDTH 1
96216     parameter \B_SIGNED 0
96217     parameter \B_WIDTH 1
96218     parameter \Y_WIDTH 1
96219     connect \A \builder_csrbank11_sel
96220     connect \B \builder_interface11_bank_bus_we
96221     connect \Y $and$ls180.v:6311$1970_Y
96222   end
96223   attribute \src "ls180.v:6311.39-6311.146"
96224   cell $and $and$ls180.v:6311$1972
96225     parameter \A_SIGNED 0
96226     parameter \A_WIDTH 1
96227     parameter \B_SIGNED 0
96228     parameter \B_WIDTH 1
96229     parameter \Y_WIDTH 1
96230     connect \A $and$ls180.v:6311$1970_Y
96231     connect \B $eq$ls180.v:6311$1971_Y
96232     connect \Y $and$ls180.v:6311$1972_Y
96233   end
96234   attribute \src "ls180.v:6312.40-6312.98"
96235   cell $and $and$ls180.v:6312$1974
96236     parameter \A_SIGNED 0
96237     parameter \A_WIDTH 1
96238     parameter \B_SIGNED 0
96239     parameter \B_WIDTH 1
96240     parameter \Y_WIDTH 1
96241     connect \A \builder_csrbank11_sel
96242     connect \B $not$ls180.v:6312$1973_Y
96243     connect \Y $and$ls180.v:6312$1974_Y
96244   end
96245   attribute \src "ls180.v:6312.39-6312.149"
96246   cell $and $and$ls180.v:6312$1976
96247     parameter \A_SIGNED 0
96248     parameter \A_WIDTH 1
96249     parameter \B_SIGNED 0
96250     parameter \B_WIDTH 1
96251     parameter \Y_WIDTH 1
96252     connect \A $and$ls180.v:6312$1974_Y
96253     connect \B $eq$ls180.v:6312$1975_Y
96254     connect \Y $and$ls180.v:6312$1976_Y
96255   end
96256   attribute \src "ls180.v:6314.39-6314.94"
96257   cell $and $and$ls180.v:6314$1977
96258     parameter \A_SIGNED 0
96259     parameter \A_WIDTH 1
96260     parameter \B_SIGNED 0
96261     parameter \B_WIDTH 1
96262     parameter \Y_WIDTH 1
96263     connect \A \builder_csrbank11_sel
96264     connect \B \builder_interface11_bank_bus_we
96265     connect \Y $and$ls180.v:6314$1977_Y
96266   end
96267   attribute \src "ls180.v:6314.38-6314.145"
96268   cell $and $and$ls180.v:6314$1979
96269     parameter \A_SIGNED 0
96270     parameter \A_WIDTH 1
96271     parameter \B_SIGNED 0
96272     parameter \B_WIDTH 1
96273     parameter \Y_WIDTH 1
96274     connect \A $and$ls180.v:6314$1977_Y
96275     connect \B $eq$ls180.v:6314$1978_Y
96276     connect \Y $and$ls180.v:6314$1979_Y
96277   end
96278   attribute \src "ls180.v:6315.39-6315.97"
96279   cell $and $and$ls180.v:6315$1981
96280     parameter \A_SIGNED 0
96281     parameter \A_WIDTH 1
96282     parameter \B_SIGNED 0
96283     parameter \B_WIDTH 1
96284     parameter \Y_WIDTH 1
96285     connect \A \builder_csrbank11_sel
96286     connect \B $not$ls180.v:6315$1980_Y
96287     connect \Y $and$ls180.v:6315$1981_Y
96288   end
96289   attribute \src "ls180.v:6315.38-6315.148"
96290   cell $and $and$ls180.v:6315$1983
96291     parameter \A_SIGNED 0
96292     parameter \A_WIDTH 1
96293     parameter \B_SIGNED 0
96294     parameter \B_WIDTH 1
96295     parameter \Y_WIDTH 1
96296     connect \A $and$ls180.v:6315$1981_Y
96297     connect \B $eq$ls180.v:6315$1982_Y
96298     connect \Y $and$ls180.v:6315$1983_Y
96299   end
96300   attribute \src "ls180.v:6317.38-6317.93"
96301   cell $and $and$ls180.v:6317$1984
96302     parameter \A_SIGNED 0
96303     parameter \A_WIDTH 1
96304     parameter \B_SIGNED 0
96305     parameter \B_WIDTH 1
96306     parameter \Y_WIDTH 1
96307     connect \A \builder_csrbank11_sel
96308     connect \B \builder_interface11_bank_bus_we
96309     connect \Y $and$ls180.v:6317$1984_Y
96310   end
96311   attribute \src "ls180.v:6317.37-6317.144"
96312   cell $and $and$ls180.v:6317$1986
96313     parameter \A_SIGNED 0
96314     parameter \A_WIDTH 1
96315     parameter \B_SIGNED 0
96316     parameter \B_WIDTH 1
96317     parameter \Y_WIDTH 1
96318     connect \A $and$ls180.v:6317$1984_Y
96319     connect \B $eq$ls180.v:6317$1985_Y
96320     connect \Y $and$ls180.v:6317$1986_Y
96321   end
96322   attribute \src "ls180.v:6318.38-6318.96"
96323   cell $and $and$ls180.v:6318$1988
96324     parameter \A_SIGNED 0
96325     parameter \A_WIDTH 1
96326     parameter \B_SIGNED 0
96327     parameter \B_WIDTH 1
96328     parameter \Y_WIDTH 1
96329     connect \A \builder_csrbank11_sel
96330     connect \B $not$ls180.v:6318$1987_Y
96331     connect \Y $and$ls180.v:6318$1988_Y
96332   end
96333   attribute \src "ls180.v:6318.37-6318.147"
96334   cell $and $and$ls180.v:6318$1990
96335     parameter \A_SIGNED 0
96336     parameter \A_WIDTH 1
96337     parameter \B_SIGNED 0
96338     parameter \B_WIDTH 1
96339     parameter \Y_WIDTH 1
96340     connect \A $and$ls180.v:6318$1988_Y
96341     connect \B $eq$ls180.v:6318$1989_Y
96342     connect \Y $and$ls180.v:6318$1990_Y
96343   end
96344   attribute \src "ls180.v:6320.37-6320.92"
96345   cell $and $and$ls180.v:6320$1991
96346     parameter \A_SIGNED 0
96347     parameter \A_WIDTH 1
96348     parameter \B_SIGNED 0
96349     parameter \B_WIDTH 1
96350     parameter \Y_WIDTH 1
96351     connect \A \builder_csrbank11_sel
96352     connect \B \builder_interface11_bank_bus_we
96353     connect \Y $and$ls180.v:6320$1991_Y
96354   end
96355   attribute \src "ls180.v:6320.36-6320.143"
96356   cell $and $and$ls180.v:6320$1993
96357     parameter \A_SIGNED 0
96358     parameter \A_WIDTH 1
96359     parameter \B_SIGNED 0
96360     parameter \B_WIDTH 1
96361     parameter \Y_WIDTH 1
96362     connect \A $and$ls180.v:6320$1991_Y
96363     connect \B $eq$ls180.v:6320$1992_Y
96364     connect \Y $and$ls180.v:6320$1993_Y
96365   end
96366   attribute \src "ls180.v:6321.37-6321.95"
96367   cell $and $and$ls180.v:6321$1995
96368     parameter \A_SIGNED 0
96369     parameter \A_WIDTH 1
96370     parameter \B_SIGNED 0
96371     parameter \B_WIDTH 1
96372     parameter \Y_WIDTH 1
96373     connect \A \builder_csrbank11_sel
96374     connect \B $not$ls180.v:6321$1994_Y
96375     connect \Y $and$ls180.v:6321$1995_Y
96376   end
96377   attribute \src "ls180.v:6321.36-6321.146"
96378   cell $and $and$ls180.v:6321$1997
96379     parameter \A_SIGNED 0
96380     parameter \A_WIDTH 1
96381     parameter \B_SIGNED 0
96382     parameter \B_WIDTH 1
96383     parameter \Y_WIDTH 1
96384     connect \A $and$ls180.v:6321$1995_Y
96385     connect \B $eq$ls180.v:6321$1996_Y
96386     connect \Y $and$ls180.v:6321$1997_Y
96387   end
96388   attribute \src "ls180.v:6323.43-6323.98"
96389   cell $and $and$ls180.v:6323$1998
96390     parameter \A_SIGNED 0
96391     parameter \A_WIDTH 1
96392     parameter \B_SIGNED 0
96393     parameter \B_WIDTH 1
96394     parameter \Y_WIDTH 1
96395     connect \A \builder_csrbank11_sel
96396     connect \B \builder_interface11_bank_bus_we
96397     connect \Y $and$ls180.v:6323$1998_Y
96398   end
96399   attribute \src "ls180.v:6323.42-6323.149"
96400   cell $and $and$ls180.v:6323$2000
96401     parameter \A_SIGNED 0
96402     parameter \A_WIDTH 1
96403     parameter \B_SIGNED 0
96404     parameter \B_WIDTH 1
96405     parameter \Y_WIDTH 1
96406     connect \A $and$ls180.v:6323$1998_Y
96407     connect \B $eq$ls180.v:6323$1999_Y
96408     connect \Y $and$ls180.v:6323$2000_Y
96409   end
96410   attribute \src "ls180.v:6324.43-6324.101"
96411   cell $and $and$ls180.v:6324$2002
96412     parameter \A_SIGNED 0
96413     parameter \A_WIDTH 1
96414     parameter \B_SIGNED 0
96415     parameter \B_WIDTH 1
96416     parameter \Y_WIDTH 1
96417     connect \A \builder_csrbank11_sel
96418     connect \B $not$ls180.v:6324$2001_Y
96419     connect \Y $and$ls180.v:6324$2002_Y
96420   end
96421   attribute \src "ls180.v:6324.42-6324.152"
96422   cell $and $and$ls180.v:6324$2004
96423     parameter \A_SIGNED 0
96424     parameter \A_WIDTH 1
96425     parameter \B_SIGNED 0
96426     parameter \B_WIDTH 1
96427     parameter \Y_WIDTH 1
96428     connect \A $and$ls180.v:6324$2002_Y
96429     connect \B $eq$ls180.v:6324$2003_Y
96430     connect \Y $and$ls180.v:6324$2004_Y
96431   end
96432   attribute \src "ls180.v:6326.46-6326.101"
96433   cell $and $and$ls180.v:6326$2005
96434     parameter \A_SIGNED 0
96435     parameter \A_WIDTH 1
96436     parameter \B_SIGNED 0
96437     parameter \B_WIDTH 1
96438     parameter \Y_WIDTH 1
96439     connect \A \builder_csrbank11_sel
96440     connect \B \builder_interface11_bank_bus_we
96441     connect \Y $and$ls180.v:6326$2005_Y
96442   end
96443   attribute \src "ls180.v:6326.45-6326.152"
96444   cell $and $and$ls180.v:6326$2007
96445     parameter \A_SIGNED 0
96446     parameter \A_WIDTH 1
96447     parameter \B_SIGNED 0
96448     parameter \B_WIDTH 1
96449     parameter \Y_WIDTH 1
96450     connect \A $and$ls180.v:6326$2005_Y
96451     connect \B $eq$ls180.v:6326$2006_Y
96452     connect \Y $and$ls180.v:6326$2007_Y
96453   end
96454   attribute \src "ls180.v:6327.46-6327.104"
96455   cell $and $and$ls180.v:6327$2009
96456     parameter \A_SIGNED 0
96457     parameter \A_WIDTH 1
96458     parameter \B_SIGNED 0
96459     parameter \B_WIDTH 1
96460     parameter \Y_WIDTH 1
96461     connect \A \builder_csrbank11_sel
96462     connect \B $not$ls180.v:6327$2008_Y
96463     connect \Y $and$ls180.v:6327$2009_Y
96464   end
96465   attribute \src "ls180.v:6327.45-6327.155"
96466   cell $and $and$ls180.v:6327$2011
96467     parameter \A_SIGNED 0
96468     parameter \A_WIDTH 1
96469     parameter \B_SIGNED 0
96470     parameter \B_WIDTH 1
96471     parameter \Y_WIDTH 1
96472     connect \A $and$ls180.v:6327$2009_Y
96473     connect \B $eq$ls180.v:6327$2010_Y
96474     connect \Y $and$ls180.v:6327$2011_Y
96475   end
96476   attribute \src "ls180.v:6329.46-6329.101"
96477   cell $and $and$ls180.v:6329$2012
96478     parameter \A_SIGNED 0
96479     parameter \A_WIDTH 1
96480     parameter \B_SIGNED 0
96481     parameter \B_WIDTH 1
96482     parameter \Y_WIDTH 1
96483     connect \A \builder_csrbank11_sel
96484     connect \B \builder_interface11_bank_bus_we
96485     connect \Y $and$ls180.v:6329$2012_Y
96486   end
96487   attribute \src "ls180.v:6329.45-6329.152"
96488   cell $and $and$ls180.v:6329$2014
96489     parameter \A_SIGNED 0
96490     parameter \A_WIDTH 1
96491     parameter \B_SIGNED 0
96492     parameter \B_WIDTH 1
96493     parameter \Y_WIDTH 1
96494     connect \A $and$ls180.v:6329$2012_Y
96495     connect \B $eq$ls180.v:6329$2013_Y
96496     connect \Y $and$ls180.v:6329$2014_Y
96497   end
96498   attribute \src "ls180.v:6330.46-6330.104"
96499   cell $and $and$ls180.v:6330$2016
96500     parameter \A_SIGNED 0
96501     parameter \A_WIDTH 1
96502     parameter \B_SIGNED 0
96503     parameter \B_WIDTH 1
96504     parameter \Y_WIDTH 1
96505     connect \A \builder_csrbank11_sel
96506     connect \B $not$ls180.v:6330$2015_Y
96507     connect \Y $and$ls180.v:6330$2016_Y
96508   end
96509   attribute \src "ls180.v:6330.45-6330.155"
96510   cell $and $and$ls180.v:6330$2018
96511     parameter \A_SIGNED 0
96512     parameter \A_WIDTH 1
96513     parameter \B_SIGNED 0
96514     parameter \B_WIDTH 1
96515     parameter \Y_WIDTH 1
96516     connect \A $and$ls180.v:6330$2016_Y
96517     connect \B $eq$ls180.v:6330$2017_Y
96518     connect \Y $and$ls180.v:6330$2018_Y
96519   end
96520   attribute \src "ls180.v:6353.39-6353.94"
96521   cell $and $and$ls180.v:6353$2021
96522     parameter \A_SIGNED 0
96523     parameter \A_WIDTH 1
96524     parameter \B_SIGNED 0
96525     parameter \B_WIDTH 1
96526     parameter \Y_WIDTH 1
96527     connect \A \builder_csrbank12_sel
96528     connect \B \builder_interface12_bank_bus_we
96529     connect \Y $and$ls180.v:6353$2021_Y
96530   end
96531   attribute \src "ls180.v:6353.38-6353.145"
96532   cell $and $and$ls180.v:6353$2023
96533     parameter \A_SIGNED 0
96534     parameter \A_WIDTH 1
96535     parameter \B_SIGNED 0
96536     parameter \B_WIDTH 1
96537     parameter \Y_WIDTH 1
96538     connect \A $and$ls180.v:6353$2021_Y
96539     connect \B $eq$ls180.v:6353$2022_Y
96540     connect \Y $and$ls180.v:6353$2023_Y
96541   end
96542   attribute \src "ls180.v:6354.39-6354.97"
96543   cell $and $and$ls180.v:6354$2025
96544     parameter \A_SIGNED 0
96545     parameter \A_WIDTH 1
96546     parameter \B_SIGNED 0
96547     parameter \B_WIDTH 1
96548     parameter \Y_WIDTH 1
96549     connect \A \builder_csrbank12_sel
96550     connect \B $not$ls180.v:6354$2024_Y
96551     connect \Y $and$ls180.v:6354$2025_Y
96552   end
96553   attribute \src "ls180.v:6354.38-6354.148"
96554   cell $and $and$ls180.v:6354$2027
96555     parameter \A_SIGNED 0
96556     parameter \A_WIDTH 1
96557     parameter \B_SIGNED 0
96558     parameter \B_WIDTH 1
96559     parameter \Y_WIDTH 1
96560     connect \A $and$ls180.v:6354$2025_Y
96561     connect \B $eq$ls180.v:6354$2026_Y
96562     connect \Y $and$ls180.v:6354$2027_Y
96563   end
96564   attribute \src "ls180.v:6356.39-6356.94"
96565   cell $and $and$ls180.v:6356$2028
96566     parameter \A_SIGNED 0
96567     parameter \A_WIDTH 1
96568     parameter \B_SIGNED 0
96569     parameter \B_WIDTH 1
96570     parameter \Y_WIDTH 1
96571     connect \A \builder_csrbank12_sel
96572     connect \B \builder_interface12_bank_bus_we
96573     connect \Y $and$ls180.v:6356$2028_Y
96574   end
96575   attribute \src "ls180.v:6356.38-6356.145"
96576   cell $and $and$ls180.v:6356$2030
96577     parameter \A_SIGNED 0
96578     parameter \A_WIDTH 1
96579     parameter \B_SIGNED 0
96580     parameter \B_WIDTH 1
96581     parameter \Y_WIDTH 1
96582     connect \A $and$ls180.v:6356$2028_Y
96583     connect \B $eq$ls180.v:6356$2029_Y
96584     connect \Y $and$ls180.v:6356$2030_Y
96585   end
96586   attribute \src "ls180.v:6357.39-6357.97"
96587   cell $and $and$ls180.v:6357$2032
96588     parameter \A_SIGNED 0
96589     parameter \A_WIDTH 1
96590     parameter \B_SIGNED 0
96591     parameter \B_WIDTH 1
96592     parameter \Y_WIDTH 1
96593     connect \A \builder_csrbank12_sel
96594     connect \B $not$ls180.v:6357$2031_Y
96595     connect \Y $and$ls180.v:6357$2032_Y
96596   end
96597   attribute \src "ls180.v:6357.38-6357.148"
96598   cell $and $and$ls180.v:6357$2034
96599     parameter \A_SIGNED 0
96600     parameter \A_WIDTH 1
96601     parameter \B_SIGNED 0
96602     parameter \B_WIDTH 1
96603     parameter \Y_WIDTH 1
96604     connect \A $and$ls180.v:6357$2032_Y
96605     connect \B $eq$ls180.v:6357$2033_Y
96606     connect \Y $and$ls180.v:6357$2034_Y
96607   end
96608   attribute \src "ls180.v:6359.39-6359.94"
96609   cell $and $and$ls180.v:6359$2035
96610     parameter \A_SIGNED 0
96611     parameter \A_WIDTH 1
96612     parameter \B_SIGNED 0
96613     parameter \B_WIDTH 1
96614     parameter \Y_WIDTH 1
96615     connect \A \builder_csrbank12_sel
96616     connect \B \builder_interface12_bank_bus_we
96617     connect \Y $and$ls180.v:6359$2035_Y
96618   end
96619   attribute \src "ls180.v:6359.38-6359.145"
96620   cell $and $and$ls180.v:6359$2037
96621     parameter \A_SIGNED 0
96622     parameter \A_WIDTH 1
96623     parameter \B_SIGNED 0
96624     parameter \B_WIDTH 1
96625     parameter \Y_WIDTH 1
96626     connect \A $and$ls180.v:6359$2035_Y
96627     connect \B $eq$ls180.v:6359$2036_Y
96628     connect \Y $and$ls180.v:6359$2037_Y
96629   end
96630   attribute \src "ls180.v:6360.39-6360.97"
96631   cell $and $and$ls180.v:6360$2039
96632     parameter \A_SIGNED 0
96633     parameter \A_WIDTH 1
96634     parameter \B_SIGNED 0
96635     parameter \B_WIDTH 1
96636     parameter \Y_WIDTH 1
96637     connect \A \builder_csrbank12_sel
96638     connect \B $not$ls180.v:6360$2038_Y
96639     connect \Y $and$ls180.v:6360$2039_Y
96640   end
96641   attribute \src "ls180.v:6360.38-6360.148"
96642   cell $and $and$ls180.v:6360$2041
96643     parameter \A_SIGNED 0
96644     parameter \A_WIDTH 1
96645     parameter \B_SIGNED 0
96646     parameter \B_WIDTH 1
96647     parameter \Y_WIDTH 1
96648     connect \A $and$ls180.v:6360$2039_Y
96649     connect \B $eq$ls180.v:6360$2040_Y
96650     connect \Y $and$ls180.v:6360$2041_Y
96651   end
96652   attribute \src "ls180.v:6362.39-6362.94"
96653   cell $and $and$ls180.v:6362$2042
96654     parameter \A_SIGNED 0
96655     parameter \A_WIDTH 1
96656     parameter \B_SIGNED 0
96657     parameter \B_WIDTH 1
96658     parameter \Y_WIDTH 1
96659     connect \A \builder_csrbank12_sel
96660     connect \B \builder_interface12_bank_bus_we
96661     connect \Y $and$ls180.v:6362$2042_Y
96662   end
96663   attribute \src "ls180.v:6362.38-6362.145"
96664   cell $and $and$ls180.v:6362$2044
96665     parameter \A_SIGNED 0
96666     parameter \A_WIDTH 1
96667     parameter \B_SIGNED 0
96668     parameter \B_WIDTH 1
96669     parameter \Y_WIDTH 1
96670     connect \A $and$ls180.v:6362$2042_Y
96671     connect \B $eq$ls180.v:6362$2043_Y
96672     connect \Y $and$ls180.v:6362$2044_Y
96673   end
96674   attribute \src "ls180.v:6363.39-6363.97"
96675   cell $and $and$ls180.v:6363$2046
96676     parameter \A_SIGNED 0
96677     parameter \A_WIDTH 1
96678     parameter \B_SIGNED 0
96679     parameter \B_WIDTH 1
96680     parameter \Y_WIDTH 1
96681     connect \A \builder_csrbank12_sel
96682     connect \B $not$ls180.v:6363$2045_Y
96683     connect \Y $and$ls180.v:6363$2046_Y
96684   end
96685   attribute \src "ls180.v:6363.38-6363.148"
96686   cell $and $and$ls180.v:6363$2048
96687     parameter \A_SIGNED 0
96688     parameter \A_WIDTH 1
96689     parameter \B_SIGNED 0
96690     parameter \B_WIDTH 1
96691     parameter \Y_WIDTH 1
96692     connect \A $and$ls180.v:6363$2046_Y
96693     connect \B $eq$ls180.v:6363$2047_Y
96694     connect \Y $and$ls180.v:6363$2048_Y
96695   end
96696   attribute \src "ls180.v:6365.41-6365.96"
96697   cell $and $and$ls180.v:6365$2049
96698     parameter \A_SIGNED 0
96699     parameter \A_WIDTH 1
96700     parameter \B_SIGNED 0
96701     parameter \B_WIDTH 1
96702     parameter \Y_WIDTH 1
96703     connect \A \builder_csrbank12_sel
96704     connect \B \builder_interface12_bank_bus_we
96705     connect \Y $and$ls180.v:6365$2049_Y
96706   end
96707   attribute \src "ls180.v:6365.40-6365.147"
96708   cell $and $and$ls180.v:6365$2051
96709     parameter \A_SIGNED 0
96710     parameter \A_WIDTH 1
96711     parameter \B_SIGNED 0
96712     parameter \B_WIDTH 1
96713     parameter \Y_WIDTH 1
96714     connect \A $and$ls180.v:6365$2049_Y
96715     connect \B $eq$ls180.v:6365$2050_Y
96716     connect \Y $and$ls180.v:6365$2051_Y
96717   end
96718   attribute \src "ls180.v:6366.41-6366.99"
96719   cell $and $and$ls180.v:6366$2053
96720     parameter \A_SIGNED 0
96721     parameter \A_WIDTH 1
96722     parameter \B_SIGNED 0
96723     parameter \B_WIDTH 1
96724     parameter \Y_WIDTH 1
96725     connect \A \builder_csrbank12_sel
96726     connect \B $not$ls180.v:6366$2052_Y
96727     connect \Y $and$ls180.v:6366$2053_Y
96728   end
96729   attribute \src "ls180.v:6366.40-6366.150"
96730   cell $and $and$ls180.v:6366$2055
96731     parameter \A_SIGNED 0
96732     parameter \A_WIDTH 1
96733     parameter \B_SIGNED 0
96734     parameter \B_WIDTH 1
96735     parameter \Y_WIDTH 1
96736     connect \A $and$ls180.v:6366$2053_Y
96737     connect \B $eq$ls180.v:6366$2054_Y
96738     connect \Y $and$ls180.v:6366$2055_Y
96739   end
96740   attribute \src "ls180.v:6368.41-6368.96"
96741   cell $and $and$ls180.v:6368$2056
96742     parameter \A_SIGNED 0
96743     parameter \A_WIDTH 1
96744     parameter \B_SIGNED 0
96745     parameter \B_WIDTH 1
96746     parameter \Y_WIDTH 1
96747     connect \A \builder_csrbank12_sel
96748     connect \B \builder_interface12_bank_bus_we
96749     connect \Y $and$ls180.v:6368$2056_Y
96750   end
96751   attribute \src "ls180.v:6368.40-6368.147"
96752   cell $and $and$ls180.v:6368$2058
96753     parameter \A_SIGNED 0
96754     parameter \A_WIDTH 1
96755     parameter \B_SIGNED 0
96756     parameter \B_WIDTH 1
96757     parameter \Y_WIDTH 1
96758     connect \A $and$ls180.v:6368$2056_Y
96759     connect \B $eq$ls180.v:6368$2057_Y
96760     connect \Y $and$ls180.v:6368$2058_Y
96761   end
96762   attribute \src "ls180.v:6369.41-6369.99"
96763   cell $and $and$ls180.v:6369$2060
96764     parameter \A_SIGNED 0
96765     parameter \A_WIDTH 1
96766     parameter \B_SIGNED 0
96767     parameter \B_WIDTH 1
96768     parameter \Y_WIDTH 1
96769     connect \A \builder_csrbank12_sel
96770     connect \B $not$ls180.v:6369$2059_Y
96771     connect \Y $and$ls180.v:6369$2060_Y
96772   end
96773   attribute \src "ls180.v:6369.40-6369.150"
96774   cell $and $and$ls180.v:6369$2062
96775     parameter \A_SIGNED 0
96776     parameter \A_WIDTH 1
96777     parameter \B_SIGNED 0
96778     parameter \B_WIDTH 1
96779     parameter \Y_WIDTH 1
96780     connect \A $and$ls180.v:6369$2060_Y
96781     connect \B $eq$ls180.v:6369$2061_Y
96782     connect \Y $and$ls180.v:6369$2062_Y
96783   end
96784   attribute \src "ls180.v:6371.41-6371.96"
96785   cell $and $and$ls180.v:6371$2063
96786     parameter \A_SIGNED 0
96787     parameter \A_WIDTH 1
96788     parameter \B_SIGNED 0
96789     parameter \B_WIDTH 1
96790     parameter \Y_WIDTH 1
96791     connect \A \builder_csrbank12_sel
96792     connect \B \builder_interface12_bank_bus_we
96793     connect \Y $and$ls180.v:6371$2063_Y
96794   end
96795   attribute \src "ls180.v:6371.40-6371.147"
96796   cell $and $and$ls180.v:6371$2065
96797     parameter \A_SIGNED 0
96798     parameter \A_WIDTH 1
96799     parameter \B_SIGNED 0
96800     parameter \B_WIDTH 1
96801     parameter \Y_WIDTH 1
96802     connect \A $and$ls180.v:6371$2063_Y
96803     connect \B $eq$ls180.v:6371$2064_Y
96804     connect \Y $and$ls180.v:6371$2065_Y
96805   end
96806   attribute \src "ls180.v:6372.41-6372.99"
96807   cell $and $and$ls180.v:6372$2067
96808     parameter \A_SIGNED 0
96809     parameter \A_WIDTH 1
96810     parameter \B_SIGNED 0
96811     parameter \B_WIDTH 1
96812     parameter \Y_WIDTH 1
96813     connect \A \builder_csrbank12_sel
96814     connect \B $not$ls180.v:6372$2066_Y
96815     connect \Y $and$ls180.v:6372$2067_Y
96816   end
96817   attribute \src "ls180.v:6372.40-6372.150"
96818   cell $and $and$ls180.v:6372$2069
96819     parameter \A_SIGNED 0
96820     parameter \A_WIDTH 1
96821     parameter \B_SIGNED 0
96822     parameter \B_WIDTH 1
96823     parameter \Y_WIDTH 1
96824     connect \A $and$ls180.v:6372$2067_Y
96825     connect \B $eq$ls180.v:6372$2068_Y
96826     connect \Y $and$ls180.v:6372$2069_Y
96827   end
96828   attribute \src "ls180.v:6374.41-6374.96"
96829   cell $and $and$ls180.v:6374$2070
96830     parameter \A_SIGNED 0
96831     parameter \A_WIDTH 1
96832     parameter \B_SIGNED 0
96833     parameter \B_WIDTH 1
96834     parameter \Y_WIDTH 1
96835     connect \A \builder_csrbank12_sel
96836     connect \B \builder_interface12_bank_bus_we
96837     connect \Y $and$ls180.v:6374$2070_Y
96838   end
96839   attribute \src "ls180.v:6374.40-6374.147"
96840   cell $and $and$ls180.v:6374$2072
96841     parameter \A_SIGNED 0
96842     parameter \A_WIDTH 1
96843     parameter \B_SIGNED 0
96844     parameter \B_WIDTH 1
96845     parameter \Y_WIDTH 1
96846     connect \A $and$ls180.v:6374$2070_Y
96847     connect \B $eq$ls180.v:6374$2071_Y
96848     connect \Y $and$ls180.v:6374$2072_Y
96849   end
96850   attribute \src "ls180.v:6375.41-6375.99"
96851   cell $and $and$ls180.v:6375$2074
96852     parameter \A_SIGNED 0
96853     parameter \A_WIDTH 1
96854     parameter \B_SIGNED 0
96855     parameter \B_WIDTH 1
96856     parameter \Y_WIDTH 1
96857     connect \A \builder_csrbank12_sel
96858     connect \B $not$ls180.v:6375$2073_Y
96859     connect \Y $and$ls180.v:6375$2074_Y
96860   end
96861   attribute \src "ls180.v:6375.40-6375.150"
96862   cell $and $and$ls180.v:6375$2076
96863     parameter \A_SIGNED 0
96864     parameter \A_WIDTH 1
96865     parameter \B_SIGNED 0
96866     parameter \B_WIDTH 1
96867     parameter \Y_WIDTH 1
96868     connect \A $and$ls180.v:6375$2074_Y
96869     connect \B $eq$ls180.v:6375$2075_Y
96870     connect \Y $and$ls180.v:6375$2076_Y
96871   end
96872   attribute \src "ls180.v:6377.37-6377.92"
96873   cell $and $and$ls180.v:6377$2077
96874     parameter \A_SIGNED 0
96875     parameter \A_WIDTH 1
96876     parameter \B_SIGNED 0
96877     parameter \B_WIDTH 1
96878     parameter \Y_WIDTH 1
96879     connect \A \builder_csrbank12_sel
96880     connect \B \builder_interface12_bank_bus_we
96881     connect \Y $and$ls180.v:6377$2077_Y
96882   end
96883   attribute \src "ls180.v:6377.36-6377.143"
96884   cell $and $and$ls180.v:6377$2079
96885     parameter \A_SIGNED 0
96886     parameter \A_WIDTH 1
96887     parameter \B_SIGNED 0
96888     parameter \B_WIDTH 1
96889     parameter \Y_WIDTH 1
96890     connect \A $and$ls180.v:6377$2077_Y
96891     connect \B $eq$ls180.v:6377$2078_Y
96892     connect \Y $and$ls180.v:6377$2079_Y
96893   end
96894   attribute \src "ls180.v:6378.37-6378.95"
96895   cell $and $and$ls180.v:6378$2081
96896     parameter \A_SIGNED 0
96897     parameter \A_WIDTH 1
96898     parameter \B_SIGNED 0
96899     parameter \B_WIDTH 1
96900     parameter \Y_WIDTH 1
96901     connect \A \builder_csrbank12_sel
96902     connect \B $not$ls180.v:6378$2080_Y
96903     connect \Y $and$ls180.v:6378$2081_Y
96904   end
96905   attribute \src "ls180.v:6378.36-6378.146"
96906   cell $and $and$ls180.v:6378$2083
96907     parameter \A_SIGNED 0
96908     parameter \A_WIDTH 1
96909     parameter \B_SIGNED 0
96910     parameter \B_WIDTH 1
96911     parameter \Y_WIDTH 1
96912     connect \A $and$ls180.v:6378$2081_Y
96913     connect \B $eq$ls180.v:6378$2082_Y
96914     connect \Y $and$ls180.v:6378$2083_Y
96915   end
96916   attribute \src "ls180.v:6380.47-6380.102"
96917   cell $and $and$ls180.v:6380$2084
96918     parameter \A_SIGNED 0
96919     parameter \A_WIDTH 1
96920     parameter \B_SIGNED 0
96921     parameter \B_WIDTH 1
96922     parameter \Y_WIDTH 1
96923     connect \A \builder_csrbank12_sel
96924     connect \B \builder_interface12_bank_bus_we
96925     connect \Y $and$ls180.v:6380$2084_Y
96926   end
96927   attribute \src "ls180.v:6380.46-6380.153"
96928   cell $and $and$ls180.v:6380$2086
96929     parameter \A_SIGNED 0
96930     parameter \A_WIDTH 1
96931     parameter \B_SIGNED 0
96932     parameter \B_WIDTH 1
96933     parameter \Y_WIDTH 1
96934     connect \A $and$ls180.v:6380$2084_Y
96935     connect \B $eq$ls180.v:6380$2085_Y
96936     connect \Y $and$ls180.v:6380$2086_Y
96937   end
96938   attribute \src "ls180.v:6381.47-6381.105"
96939   cell $and $and$ls180.v:6381$2088
96940     parameter \A_SIGNED 0
96941     parameter \A_WIDTH 1
96942     parameter \B_SIGNED 0
96943     parameter \B_WIDTH 1
96944     parameter \Y_WIDTH 1
96945     connect \A \builder_csrbank12_sel
96946     connect \B $not$ls180.v:6381$2087_Y
96947     connect \Y $and$ls180.v:6381$2088_Y
96948   end
96949   attribute \src "ls180.v:6381.46-6381.156"
96950   cell $and $and$ls180.v:6381$2090
96951     parameter \A_SIGNED 0
96952     parameter \A_WIDTH 1
96953     parameter \B_SIGNED 0
96954     parameter \B_WIDTH 1
96955     parameter \Y_WIDTH 1
96956     connect \A $and$ls180.v:6381$2088_Y
96957     connect \B $eq$ls180.v:6381$2089_Y
96958     connect \Y $and$ls180.v:6381$2090_Y
96959   end
96960   attribute \src "ls180.v:6383.40-6383.95"
96961   cell $and $and$ls180.v:6383$2091
96962     parameter \A_SIGNED 0
96963     parameter \A_WIDTH 1
96964     parameter \B_SIGNED 0
96965     parameter \B_WIDTH 1
96966     parameter \Y_WIDTH 1
96967     connect \A \builder_csrbank12_sel
96968     connect \B \builder_interface12_bank_bus_we
96969     connect \Y $and$ls180.v:6383$2091_Y
96970   end
96971   attribute \src "ls180.v:6383.39-6383.147"
96972   cell $and $and$ls180.v:6383$2093
96973     parameter \A_SIGNED 0
96974     parameter \A_WIDTH 1
96975     parameter \B_SIGNED 0
96976     parameter \B_WIDTH 1
96977     parameter \Y_WIDTH 1
96978     connect \A $and$ls180.v:6383$2091_Y
96979     connect \B $eq$ls180.v:6383$2092_Y
96980     connect \Y $and$ls180.v:6383$2093_Y
96981   end
96982   attribute \src "ls180.v:6384.40-6384.98"
96983   cell $and $and$ls180.v:6384$2095
96984     parameter \A_SIGNED 0
96985     parameter \A_WIDTH 1
96986     parameter \B_SIGNED 0
96987     parameter \B_WIDTH 1
96988     parameter \Y_WIDTH 1
96989     connect \A \builder_csrbank12_sel
96990     connect \B $not$ls180.v:6384$2094_Y
96991     connect \Y $and$ls180.v:6384$2095_Y
96992   end
96993   attribute \src "ls180.v:6384.39-6384.150"
96994   cell $and $and$ls180.v:6384$2097
96995     parameter \A_SIGNED 0
96996     parameter \A_WIDTH 1
96997     parameter \B_SIGNED 0
96998     parameter \B_WIDTH 1
96999     parameter \Y_WIDTH 1
97000     connect \A $and$ls180.v:6384$2095_Y
97001     connect \B $eq$ls180.v:6384$2096_Y
97002     connect \Y $and$ls180.v:6384$2097_Y
97003   end
97004   attribute \src "ls180.v:6386.40-6386.95"
97005   cell $and $and$ls180.v:6386$2098
97006     parameter \A_SIGNED 0
97007     parameter \A_WIDTH 1
97008     parameter \B_SIGNED 0
97009     parameter \B_WIDTH 1
97010     parameter \Y_WIDTH 1
97011     connect \A \builder_csrbank12_sel
97012     connect \B \builder_interface12_bank_bus_we
97013     connect \Y $and$ls180.v:6386$2098_Y
97014   end
97015   attribute \src "ls180.v:6386.39-6386.147"
97016   cell $and $and$ls180.v:6386$2100
97017     parameter \A_SIGNED 0
97018     parameter \A_WIDTH 1
97019     parameter \B_SIGNED 0
97020     parameter \B_WIDTH 1
97021     parameter \Y_WIDTH 1
97022     connect \A $and$ls180.v:6386$2098_Y
97023     connect \B $eq$ls180.v:6386$2099_Y
97024     connect \Y $and$ls180.v:6386$2100_Y
97025   end
97026   attribute \src "ls180.v:6387.40-6387.98"
97027   cell $and $and$ls180.v:6387$2102
97028     parameter \A_SIGNED 0
97029     parameter \A_WIDTH 1
97030     parameter \B_SIGNED 0
97031     parameter \B_WIDTH 1
97032     parameter \Y_WIDTH 1
97033     connect \A \builder_csrbank12_sel
97034     connect \B $not$ls180.v:6387$2101_Y
97035     connect \Y $and$ls180.v:6387$2102_Y
97036   end
97037   attribute \src "ls180.v:6387.39-6387.150"
97038   cell $and $and$ls180.v:6387$2104
97039     parameter \A_SIGNED 0
97040     parameter \A_WIDTH 1
97041     parameter \B_SIGNED 0
97042     parameter \B_WIDTH 1
97043     parameter \Y_WIDTH 1
97044     connect \A $and$ls180.v:6387$2102_Y
97045     connect \B $eq$ls180.v:6387$2103_Y
97046     connect \Y $and$ls180.v:6387$2104_Y
97047   end
97048   attribute \src "ls180.v:6389.40-6389.95"
97049   cell $and $and$ls180.v:6389$2105
97050     parameter \A_SIGNED 0
97051     parameter \A_WIDTH 1
97052     parameter \B_SIGNED 0
97053     parameter \B_WIDTH 1
97054     parameter \Y_WIDTH 1
97055     connect \A \builder_csrbank12_sel
97056     connect \B \builder_interface12_bank_bus_we
97057     connect \Y $and$ls180.v:6389$2105_Y
97058   end
97059   attribute \src "ls180.v:6389.39-6389.147"
97060   cell $and $and$ls180.v:6389$2107
97061     parameter \A_SIGNED 0
97062     parameter \A_WIDTH 1
97063     parameter \B_SIGNED 0
97064     parameter \B_WIDTH 1
97065     parameter \Y_WIDTH 1
97066     connect \A $and$ls180.v:6389$2105_Y
97067     connect \B $eq$ls180.v:6389$2106_Y
97068     connect \Y $and$ls180.v:6389$2107_Y
97069   end
97070   attribute \src "ls180.v:6390.40-6390.98"
97071   cell $and $and$ls180.v:6390$2109
97072     parameter \A_SIGNED 0
97073     parameter \A_WIDTH 1
97074     parameter \B_SIGNED 0
97075     parameter \B_WIDTH 1
97076     parameter \Y_WIDTH 1
97077     connect \A \builder_csrbank12_sel
97078     connect \B $not$ls180.v:6390$2108_Y
97079     connect \Y $and$ls180.v:6390$2109_Y
97080   end
97081   attribute \src "ls180.v:6390.39-6390.150"
97082   cell $and $and$ls180.v:6390$2111
97083     parameter \A_SIGNED 0
97084     parameter \A_WIDTH 1
97085     parameter \B_SIGNED 0
97086     parameter \B_WIDTH 1
97087     parameter \Y_WIDTH 1
97088     connect \A $and$ls180.v:6390$2109_Y
97089     connect \B $eq$ls180.v:6390$2110_Y
97090     connect \Y $and$ls180.v:6390$2111_Y
97091   end
97092   attribute \src "ls180.v:6392.40-6392.95"
97093   cell $and $and$ls180.v:6392$2112
97094     parameter \A_SIGNED 0
97095     parameter \A_WIDTH 1
97096     parameter \B_SIGNED 0
97097     parameter \B_WIDTH 1
97098     parameter \Y_WIDTH 1
97099     connect \A \builder_csrbank12_sel
97100     connect \B \builder_interface12_bank_bus_we
97101     connect \Y $and$ls180.v:6392$2112_Y
97102   end
97103   attribute \src "ls180.v:6392.39-6392.147"
97104   cell $and $and$ls180.v:6392$2114
97105     parameter \A_SIGNED 0
97106     parameter \A_WIDTH 1
97107     parameter \B_SIGNED 0
97108     parameter \B_WIDTH 1
97109     parameter \Y_WIDTH 1
97110     connect \A $and$ls180.v:6392$2112_Y
97111     connect \B $eq$ls180.v:6392$2113_Y
97112     connect \Y $and$ls180.v:6392$2114_Y
97113   end
97114   attribute \src "ls180.v:6393.40-6393.98"
97115   cell $and $and$ls180.v:6393$2116
97116     parameter \A_SIGNED 0
97117     parameter \A_WIDTH 1
97118     parameter \B_SIGNED 0
97119     parameter \B_WIDTH 1
97120     parameter \Y_WIDTH 1
97121     connect \A \builder_csrbank12_sel
97122     connect \B $not$ls180.v:6393$2115_Y
97123     connect \Y $and$ls180.v:6393$2116_Y
97124   end
97125   attribute \src "ls180.v:6393.39-6393.150"
97126   cell $and $and$ls180.v:6393$2118
97127     parameter \A_SIGNED 0
97128     parameter \A_WIDTH 1
97129     parameter \B_SIGNED 0
97130     parameter \B_WIDTH 1
97131     parameter \Y_WIDTH 1
97132     connect \A $and$ls180.v:6393$2116_Y
97133     connect \B $eq$ls180.v:6393$2117_Y
97134     connect \Y $and$ls180.v:6393$2118_Y
97135   end
97136   attribute \src "ls180.v:6395.52-6395.107"
97137   cell $and $and$ls180.v:6395$2119
97138     parameter \A_SIGNED 0
97139     parameter \A_WIDTH 1
97140     parameter \B_SIGNED 0
97141     parameter \B_WIDTH 1
97142     parameter \Y_WIDTH 1
97143     connect \A \builder_csrbank12_sel
97144     connect \B \builder_interface12_bank_bus_we
97145     connect \Y $and$ls180.v:6395$2119_Y
97146   end
97147   attribute \src "ls180.v:6395.51-6395.159"
97148   cell $and $and$ls180.v:6395$2121
97149     parameter \A_SIGNED 0
97150     parameter \A_WIDTH 1
97151     parameter \B_SIGNED 0
97152     parameter \B_WIDTH 1
97153     parameter \Y_WIDTH 1
97154     connect \A $and$ls180.v:6395$2119_Y
97155     connect \B $eq$ls180.v:6395$2120_Y
97156     connect \Y $and$ls180.v:6395$2121_Y
97157   end
97158   attribute \src "ls180.v:6396.52-6396.110"
97159   cell $and $and$ls180.v:6396$2123
97160     parameter \A_SIGNED 0
97161     parameter \A_WIDTH 1
97162     parameter \B_SIGNED 0
97163     parameter \B_WIDTH 1
97164     parameter \Y_WIDTH 1
97165     connect \A \builder_csrbank12_sel
97166     connect \B $not$ls180.v:6396$2122_Y
97167     connect \Y $and$ls180.v:6396$2123_Y
97168   end
97169   attribute \src "ls180.v:6396.51-6396.162"
97170   cell $and $and$ls180.v:6396$2125
97171     parameter \A_SIGNED 0
97172     parameter \A_WIDTH 1
97173     parameter \B_SIGNED 0
97174     parameter \B_WIDTH 1
97175     parameter \Y_WIDTH 1
97176     connect \A $and$ls180.v:6396$2123_Y
97177     connect \B $eq$ls180.v:6396$2124_Y
97178     connect \Y $and$ls180.v:6396$2125_Y
97179   end
97180   attribute \src "ls180.v:6398.53-6398.108"
97181   cell $and $and$ls180.v:6398$2126
97182     parameter \A_SIGNED 0
97183     parameter \A_WIDTH 1
97184     parameter \B_SIGNED 0
97185     parameter \B_WIDTH 1
97186     parameter \Y_WIDTH 1
97187     connect \A \builder_csrbank12_sel
97188     connect \B \builder_interface12_bank_bus_we
97189     connect \Y $and$ls180.v:6398$2126_Y
97190   end
97191   attribute \src "ls180.v:6398.52-6398.160"
97192   cell $and $and$ls180.v:6398$2128
97193     parameter \A_SIGNED 0
97194     parameter \A_WIDTH 1
97195     parameter \B_SIGNED 0
97196     parameter \B_WIDTH 1
97197     parameter \Y_WIDTH 1
97198     connect \A $and$ls180.v:6398$2126_Y
97199     connect \B $eq$ls180.v:6398$2127_Y
97200     connect \Y $and$ls180.v:6398$2128_Y
97201   end
97202   attribute \src "ls180.v:6399.53-6399.111"
97203   cell $and $and$ls180.v:6399$2130
97204     parameter \A_SIGNED 0
97205     parameter \A_WIDTH 1
97206     parameter \B_SIGNED 0
97207     parameter \B_WIDTH 1
97208     parameter \Y_WIDTH 1
97209     connect \A \builder_csrbank12_sel
97210     connect \B $not$ls180.v:6399$2129_Y
97211     connect \Y $and$ls180.v:6399$2130_Y
97212   end
97213   attribute \src "ls180.v:6399.52-6399.163"
97214   cell $and $and$ls180.v:6399$2132
97215     parameter \A_SIGNED 0
97216     parameter \A_WIDTH 1
97217     parameter \B_SIGNED 0
97218     parameter \B_WIDTH 1
97219     parameter \Y_WIDTH 1
97220     connect \A $and$ls180.v:6399$2130_Y
97221     connect \B $eq$ls180.v:6399$2131_Y
97222     connect \Y $and$ls180.v:6399$2132_Y
97223   end
97224   attribute \src "ls180.v:6401.44-6401.99"
97225   cell $and $and$ls180.v:6401$2133
97226     parameter \A_SIGNED 0
97227     parameter \A_WIDTH 1
97228     parameter \B_SIGNED 0
97229     parameter \B_WIDTH 1
97230     parameter \Y_WIDTH 1
97231     connect \A \builder_csrbank12_sel
97232     connect \B \builder_interface12_bank_bus_we
97233     connect \Y $and$ls180.v:6401$2133_Y
97234   end
97235   attribute \src "ls180.v:6401.43-6401.151"
97236   cell $and $and$ls180.v:6401$2135
97237     parameter \A_SIGNED 0
97238     parameter \A_WIDTH 1
97239     parameter \B_SIGNED 0
97240     parameter \B_WIDTH 1
97241     parameter \Y_WIDTH 1
97242     connect \A $and$ls180.v:6401$2133_Y
97243     connect \B $eq$ls180.v:6401$2134_Y
97244     connect \Y $and$ls180.v:6401$2135_Y
97245   end
97246   attribute \src "ls180.v:6402.44-6402.102"
97247   cell $and $and$ls180.v:6402$2137
97248     parameter \A_SIGNED 0
97249     parameter \A_WIDTH 1
97250     parameter \B_SIGNED 0
97251     parameter \B_WIDTH 1
97252     parameter \Y_WIDTH 1
97253     connect \A \builder_csrbank12_sel
97254     connect \B $not$ls180.v:6402$2136_Y
97255     connect \Y $and$ls180.v:6402$2137_Y
97256   end
97257   attribute \src "ls180.v:6402.43-6402.154"
97258   cell $and $and$ls180.v:6402$2139
97259     parameter \A_SIGNED 0
97260     parameter \A_WIDTH 1
97261     parameter \B_SIGNED 0
97262     parameter \B_WIDTH 1
97263     parameter \Y_WIDTH 1
97264     connect \A $and$ls180.v:6402$2137_Y
97265     connect \B $eq$ls180.v:6402$2138_Y
97266     connect \Y $and$ls180.v:6402$2139_Y
97267   end
97268   attribute \src "ls180.v:6421.30-6421.85"
97269   cell $and $and$ls180.v:6421$2141
97270     parameter \A_SIGNED 0
97271     parameter \A_WIDTH 1
97272     parameter \B_SIGNED 0
97273     parameter \B_WIDTH 1
97274     parameter \Y_WIDTH 1
97275     connect \A \builder_csrbank13_sel
97276     connect \B \builder_interface13_bank_bus_we
97277     connect \Y $and$ls180.v:6421$2141_Y
97278   end
97279   attribute \src "ls180.v:6421.29-6421.136"
97280   cell $and $and$ls180.v:6421$2143
97281     parameter \A_SIGNED 0
97282     parameter \A_WIDTH 1
97283     parameter \B_SIGNED 0
97284     parameter \B_WIDTH 1
97285     parameter \Y_WIDTH 1
97286     connect \A $and$ls180.v:6421$2141_Y
97287     connect \B $eq$ls180.v:6421$2142_Y
97288     connect \Y $and$ls180.v:6421$2143_Y
97289   end
97290   attribute \src "ls180.v:6422.30-6422.88"
97291   cell $and $and$ls180.v:6422$2145
97292     parameter \A_SIGNED 0
97293     parameter \A_WIDTH 1
97294     parameter \B_SIGNED 0
97295     parameter \B_WIDTH 1
97296     parameter \Y_WIDTH 1
97297     connect \A \builder_csrbank13_sel
97298     connect \B $not$ls180.v:6422$2144_Y
97299     connect \Y $and$ls180.v:6422$2145_Y
97300   end
97301   attribute \src "ls180.v:6422.29-6422.139"
97302   cell $and $and$ls180.v:6422$2147
97303     parameter \A_SIGNED 0
97304     parameter \A_WIDTH 1
97305     parameter \B_SIGNED 0
97306     parameter \B_WIDTH 1
97307     parameter \Y_WIDTH 1
97308     connect \A $and$ls180.v:6422$2145_Y
97309     connect \B $eq$ls180.v:6422$2146_Y
97310     connect \Y $and$ls180.v:6422$2147_Y
97311   end
97312   attribute \src "ls180.v:6424.40-6424.95"
97313   cell $and $and$ls180.v:6424$2148
97314     parameter \A_SIGNED 0
97315     parameter \A_WIDTH 1
97316     parameter \B_SIGNED 0
97317     parameter \B_WIDTH 1
97318     parameter \Y_WIDTH 1
97319     connect \A \builder_csrbank13_sel
97320     connect \B \builder_interface13_bank_bus_we
97321     connect \Y $and$ls180.v:6424$2148_Y
97322   end
97323   attribute \src "ls180.v:6424.39-6424.146"
97324   cell $and $and$ls180.v:6424$2150
97325     parameter \A_SIGNED 0
97326     parameter \A_WIDTH 1
97327     parameter \B_SIGNED 0
97328     parameter \B_WIDTH 1
97329     parameter \Y_WIDTH 1
97330     connect \A $and$ls180.v:6424$2148_Y
97331     connect \B $eq$ls180.v:6424$2149_Y
97332     connect \Y $and$ls180.v:6424$2150_Y
97333   end
97334   attribute \src "ls180.v:6425.40-6425.98"
97335   cell $and $and$ls180.v:6425$2152
97336     parameter \A_SIGNED 0
97337     parameter \A_WIDTH 1
97338     parameter \B_SIGNED 0
97339     parameter \B_WIDTH 1
97340     parameter \Y_WIDTH 1
97341     connect \A \builder_csrbank13_sel
97342     connect \B $not$ls180.v:6425$2151_Y
97343     connect \Y $and$ls180.v:6425$2152_Y
97344   end
97345   attribute \src "ls180.v:6425.39-6425.149"
97346   cell $and $and$ls180.v:6425$2154
97347     parameter \A_SIGNED 0
97348     parameter \A_WIDTH 1
97349     parameter \B_SIGNED 0
97350     parameter \B_WIDTH 1
97351     parameter \Y_WIDTH 1
97352     connect \A $and$ls180.v:6425$2152_Y
97353     connect \B $eq$ls180.v:6425$2153_Y
97354     connect \Y $and$ls180.v:6425$2154_Y
97355   end
97356   attribute \src "ls180.v:6427.41-6427.96"
97357   cell $and $and$ls180.v:6427$2155
97358     parameter \A_SIGNED 0
97359     parameter \A_WIDTH 1
97360     parameter \B_SIGNED 0
97361     parameter \B_WIDTH 1
97362     parameter \Y_WIDTH 1
97363     connect \A \builder_csrbank13_sel
97364     connect \B \builder_interface13_bank_bus_we
97365     connect \Y $and$ls180.v:6427$2155_Y
97366   end
97367   attribute \src "ls180.v:6427.40-6427.147"
97368   cell $and $and$ls180.v:6427$2157
97369     parameter \A_SIGNED 0
97370     parameter \A_WIDTH 1
97371     parameter \B_SIGNED 0
97372     parameter \B_WIDTH 1
97373     parameter \Y_WIDTH 1
97374     connect \A $and$ls180.v:6427$2155_Y
97375     connect \B $eq$ls180.v:6427$2156_Y
97376     connect \Y $and$ls180.v:6427$2157_Y
97377   end
97378   attribute \src "ls180.v:6428.41-6428.99"
97379   cell $and $and$ls180.v:6428$2159
97380     parameter \A_SIGNED 0
97381     parameter \A_WIDTH 1
97382     parameter \B_SIGNED 0
97383     parameter \B_WIDTH 1
97384     parameter \Y_WIDTH 1
97385     connect \A \builder_csrbank13_sel
97386     connect \B $not$ls180.v:6428$2158_Y
97387     connect \Y $and$ls180.v:6428$2159_Y
97388   end
97389   attribute \src "ls180.v:6428.40-6428.150"
97390   cell $and $and$ls180.v:6428$2161
97391     parameter \A_SIGNED 0
97392     parameter \A_WIDTH 1
97393     parameter \B_SIGNED 0
97394     parameter \B_WIDTH 1
97395     parameter \Y_WIDTH 1
97396     connect \A $and$ls180.v:6428$2159_Y
97397     connect \B $eq$ls180.v:6428$2160_Y
97398     connect \Y $and$ls180.v:6428$2161_Y
97399   end
97400   attribute \src "ls180.v:6430.45-6430.100"
97401   cell $and $and$ls180.v:6430$2162
97402     parameter \A_SIGNED 0
97403     parameter \A_WIDTH 1
97404     parameter \B_SIGNED 0
97405     parameter \B_WIDTH 1
97406     parameter \Y_WIDTH 1
97407     connect \A \builder_csrbank13_sel
97408     connect \B \builder_interface13_bank_bus_we
97409     connect \Y $and$ls180.v:6430$2162_Y
97410   end
97411   attribute \src "ls180.v:6430.44-6430.151"
97412   cell $and $and$ls180.v:6430$2164
97413     parameter \A_SIGNED 0
97414     parameter \A_WIDTH 1
97415     parameter \B_SIGNED 0
97416     parameter \B_WIDTH 1
97417     parameter \Y_WIDTH 1
97418     connect \A $and$ls180.v:6430$2162_Y
97419     connect \B $eq$ls180.v:6430$2163_Y
97420     connect \Y $and$ls180.v:6430$2164_Y
97421   end
97422   attribute \src "ls180.v:6431.45-6431.103"
97423   cell $and $and$ls180.v:6431$2166
97424     parameter \A_SIGNED 0
97425     parameter \A_WIDTH 1
97426     parameter \B_SIGNED 0
97427     parameter \B_WIDTH 1
97428     parameter \Y_WIDTH 1
97429     connect \A \builder_csrbank13_sel
97430     connect \B $not$ls180.v:6431$2165_Y
97431     connect \Y $and$ls180.v:6431$2166_Y
97432   end
97433   attribute \src "ls180.v:6431.44-6431.154"
97434   cell $and $and$ls180.v:6431$2168
97435     parameter \A_SIGNED 0
97436     parameter \A_WIDTH 1
97437     parameter \B_SIGNED 0
97438     parameter \B_WIDTH 1
97439     parameter \Y_WIDTH 1
97440     connect \A $and$ls180.v:6431$2166_Y
97441     connect \B $eq$ls180.v:6431$2167_Y
97442     connect \Y $and$ls180.v:6431$2168_Y
97443   end
97444   attribute \src "ls180.v:6433.46-6433.101"
97445   cell $and $and$ls180.v:6433$2169
97446     parameter \A_SIGNED 0
97447     parameter \A_WIDTH 1
97448     parameter \B_SIGNED 0
97449     parameter \B_WIDTH 1
97450     parameter \Y_WIDTH 1
97451     connect \A \builder_csrbank13_sel
97452     connect \B \builder_interface13_bank_bus_we
97453     connect \Y $and$ls180.v:6433$2169_Y
97454   end
97455   attribute \src "ls180.v:6433.45-6433.152"
97456   cell $and $and$ls180.v:6433$2171
97457     parameter \A_SIGNED 0
97458     parameter \A_WIDTH 1
97459     parameter \B_SIGNED 0
97460     parameter \B_WIDTH 1
97461     parameter \Y_WIDTH 1
97462     connect \A $and$ls180.v:6433$2169_Y
97463     connect \B $eq$ls180.v:6433$2170_Y
97464     connect \Y $and$ls180.v:6433$2171_Y
97465   end
97466   attribute \src "ls180.v:6434.46-6434.104"
97467   cell $and $and$ls180.v:6434$2173
97468     parameter \A_SIGNED 0
97469     parameter \A_WIDTH 1
97470     parameter \B_SIGNED 0
97471     parameter \B_WIDTH 1
97472     parameter \Y_WIDTH 1
97473     connect \A \builder_csrbank13_sel
97474     connect \B $not$ls180.v:6434$2172_Y
97475     connect \Y $and$ls180.v:6434$2173_Y
97476   end
97477   attribute \src "ls180.v:6434.45-6434.155"
97478   cell $and $and$ls180.v:6434$2175
97479     parameter \A_SIGNED 0
97480     parameter \A_WIDTH 1
97481     parameter \B_SIGNED 0
97482     parameter \B_WIDTH 1
97483     parameter \Y_WIDTH 1
97484     connect \A $and$ls180.v:6434$2173_Y
97485     connect \B $eq$ls180.v:6434$2174_Y
97486     connect \Y $and$ls180.v:6434$2175_Y
97487   end
97488   attribute \src "ls180.v:6436.44-6436.99"
97489   cell $and $and$ls180.v:6436$2176
97490     parameter \A_SIGNED 0
97491     parameter \A_WIDTH 1
97492     parameter \B_SIGNED 0
97493     parameter \B_WIDTH 1
97494     parameter \Y_WIDTH 1
97495     connect \A \builder_csrbank13_sel
97496     connect \B \builder_interface13_bank_bus_we
97497     connect \Y $and$ls180.v:6436$2176_Y
97498   end
97499   attribute \src "ls180.v:6436.43-6436.150"
97500   cell $and $and$ls180.v:6436$2178
97501     parameter \A_SIGNED 0
97502     parameter \A_WIDTH 1
97503     parameter \B_SIGNED 0
97504     parameter \B_WIDTH 1
97505     parameter \Y_WIDTH 1
97506     connect \A $and$ls180.v:6436$2176_Y
97507     connect \B $eq$ls180.v:6436$2177_Y
97508     connect \Y $and$ls180.v:6436$2178_Y
97509   end
97510   attribute \src "ls180.v:6437.44-6437.102"
97511   cell $and $and$ls180.v:6437$2180
97512     parameter \A_SIGNED 0
97513     parameter \A_WIDTH 1
97514     parameter \B_SIGNED 0
97515     parameter \B_WIDTH 1
97516     parameter \Y_WIDTH 1
97517     connect \A \builder_csrbank13_sel
97518     connect \B $not$ls180.v:6437$2179_Y
97519     connect \Y $and$ls180.v:6437$2180_Y
97520   end
97521   attribute \src "ls180.v:6437.43-6437.153"
97522   cell $and $and$ls180.v:6437$2182
97523     parameter \A_SIGNED 0
97524     parameter \A_WIDTH 1
97525     parameter \B_SIGNED 0
97526     parameter \B_WIDTH 1
97527     parameter \Y_WIDTH 1
97528     connect \A $and$ls180.v:6437$2180_Y
97529     connect \B $eq$ls180.v:6437$2181_Y
97530     connect \Y $and$ls180.v:6437$2182_Y
97531   end
97532   attribute \src "ls180.v:6439.41-6439.96"
97533   cell $and $and$ls180.v:6439$2183
97534     parameter \A_SIGNED 0
97535     parameter \A_WIDTH 1
97536     parameter \B_SIGNED 0
97537     parameter \B_WIDTH 1
97538     parameter \Y_WIDTH 1
97539     connect \A \builder_csrbank13_sel
97540     connect \B \builder_interface13_bank_bus_we
97541     connect \Y $and$ls180.v:6439$2183_Y
97542   end
97543   attribute \src "ls180.v:6439.40-6439.147"
97544   cell $and $and$ls180.v:6439$2185
97545     parameter \A_SIGNED 0
97546     parameter \A_WIDTH 1
97547     parameter \B_SIGNED 0
97548     parameter \B_WIDTH 1
97549     parameter \Y_WIDTH 1
97550     connect \A $and$ls180.v:6439$2183_Y
97551     connect \B $eq$ls180.v:6439$2184_Y
97552     connect \Y $and$ls180.v:6439$2185_Y
97553   end
97554   attribute \src "ls180.v:6440.41-6440.99"
97555   cell $and $and$ls180.v:6440$2187
97556     parameter \A_SIGNED 0
97557     parameter \A_WIDTH 1
97558     parameter \B_SIGNED 0
97559     parameter \B_WIDTH 1
97560     parameter \Y_WIDTH 1
97561     connect \A \builder_csrbank13_sel
97562     connect \B $not$ls180.v:6440$2186_Y
97563     connect \Y $and$ls180.v:6440$2187_Y
97564   end
97565   attribute \src "ls180.v:6440.40-6440.150"
97566   cell $and $and$ls180.v:6440$2189
97567     parameter \A_SIGNED 0
97568     parameter \A_WIDTH 1
97569     parameter \B_SIGNED 0
97570     parameter \B_WIDTH 1
97571     parameter \Y_WIDTH 1
97572     connect \A $and$ls180.v:6440$2187_Y
97573     connect \B $eq$ls180.v:6440$2188_Y
97574     connect \Y $and$ls180.v:6440$2189_Y
97575   end
97576   attribute \src "ls180.v:6442.40-6442.95"
97577   cell $and $and$ls180.v:6442$2190
97578     parameter \A_SIGNED 0
97579     parameter \A_WIDTH 1
97580     parameter \B_SIGNED 0
97581     parameter \B_WIDTH 1
97582     parameter \Y_WIDTH 1
97583     connect \A \builder_csrbank13_sel
97584     connect \B \builder_interface13_bank_bus_we
97585     connect \Y $and$ls180.v:6442$2190_Y
97586   end
97587   attribute \src "ls180.v:6442.39-6442.146"
97588   cell $and $and$ls180.v:6442$2192
97589     parameter \A_SIGNED 0
97590     parameter \A_WIDTH 1
97591     parameter \B_SIGNED 0
97592     parameter \B_WIDTH 1
97593     parameter \Y_WIDTH 1
97594     connect \A $and$ls180.v:6442$2190_Y
97595     connect \B $eq$ls180.v:6442$2191_Y
97596     connect \Y $and$ls180.v:6442$2192_Y
97597   end
97598   attribute \src "ls180.v:6443.40-6443.98"
97599   cell $and $and$ls180.v:6443$2194
97600     parameter \A_SIGNED 0
97601     parameter \A_WIDTH 1
97602     parameter \B_SIGNED 0
97603     parameter \B_WIDTH 1
97604     parameter \Y_WIDTH 1
97605     connect \A \builder_csrbank13_sel
97606     connect \B $not$ls180.v:6443$2193_Y
97607     connect \Y $and$ls180.v:6443$2194_Y
97608   end
97609   attribute \src "ls180.v:6443.39-6443.149"
97610   cell $and $and$ls180.v:6443$2196
97611     parameter \A_SIGNED 0
97612     parameter \A_WIDTH 1
97613     parameter \B_SIGNED 0
97614     parameter \B_WIDTH 1
97615     parameter \Y_WIDTH 1
97616     connect \A $and$ls180.v:6443$2194_Y
97617     connect \B $eq$ls180.v:6443$2195_Y
97618     connect \Y $and$ls180.v:6443$2196_Y
97619   end
97620   attribute \src "ls180.v:6455.46-6455.101"
97621   cell $and $and$ls180.v:6455$2198
97622     parameter \A_SIGNED 0
97623     parameter \A_WIDTH 1
97624     parameter \B_SIGNED 0
97625     parameter \B_WIDTH 1
97626     parameter \Y_WIDTH 1
97627     connect \A \builder_csrbank14_sel
97628     connect \B \builder_interface14_bank_bus_we
97629     connect \Y $and$ls180.v:6455$2198_Y
97630   end
97631   attribute \src "ls180.v:6455.45-6455.152"
97632   cell $and $and$ls180.v:6455$2200
97633     parameter \A_SIGNED 0
97634     parameter \A_WIDTH 1
97635     parameter \B_SIGNED 0
97636     parameter \B_WIDTH 1
97637     parameter \Y_WIDTH 1
97638     connect \A $and$ls180.v:6455$2198_Y
97639     connect \B $eq$ls180.v:6455$2199_Y
97640     connect \Y $and$ls180.v:6455$2200_Y
97641   end
97642   attribute \src "ls180.v:6456.46-6456.104"
97643   cell $and $and$ls180.v:6456$2202
97644     parameter \A_SIGNED 0
97645     parameter \A_WIDTH 1
97646     parameter \B_SIGNED 0
97647     parameter \B_WIDTH 1
97648     parameter \Y_WIDTH 1
97649     connect \A \builder_csrbank14_sel
97650     connect \B $not$ls180.v:6456$2201_Y
97651     connect \Y $and$ls180.v:6456$2202_Y
97652   end
97653   attribute \src "ls180.v:6456.45-6456.155"
97654   cell $and $and$ls180.v:6456$2204
97655     parameter \A_SIGNED 0
97656     parameter \A_WIDTH 1
97657     parameter \B_SIGNED 0
97658     parameter \B_WIDTH 1
97659     parameter \Y_WIDTH 1
97660     connect \A $and$ls180.v:6456$2202_Y
97661     connect \B $eq$ls180.v:6456$2203_Y
97662     connect \Y $and$ls180.v:6456$2204_Y
97663   end
97664   attribute \src "ls180.v:6458.46-6458.101"
97665   cell $and $and$ls180.v:6458$2205
97666     parameter \A_SIGNED 0
97667     parameter \A_WIDTH 1
97668     parameter \B_SIGNED 0
97669     parameter \B_WIDTH 1
97670     parameter \Y_WIDTH 1
97671     connect \A \builder_csrbank14_sel
97672     connect \B \builder_interface14_bank_bus_we
97673     connect \Y $and$ls180.v:6458$2205_Y
97674   end
97675   attribute \src "ls180.v:6458.45-6458.152"
97676   cell $and $and$ls180.v:6458$2207
97677     parameter \A_SIGNED 0
97678     parameter \A_WIDTH 1
97679     parameter \B_SIGNED 0
97680     parameter \B_WIDTH 1
97681     parameter \Y_WIDTH 1
97682     connect \A $and$ls180.v:6458$2205_Y
97683     connect \B $eq$ls180.v:6458$2206_Y
97684     connect \Y $and$ls180.v:6458$2207_Y
97685   end
97686   attribute \src "ls180.v:6459.46-6459.104"
97687   cell $and $and$ls180.v:6459$2209
97688     parameter \A_SIGNED 0
97689     parameter \A_WIDTH 1
97690     parameter \B_SIGNED 0
97691     parameter \B_WIDTH 1
97692     parameter \Y_WIDTH 1
97693     connect \A \builder_csrbank14_sel
97694     connect \B $not$ls180.v:6459$2208_Y
97695     connect \Y $and$ls180.v:6459$2209_Y
97696   end
97697   attribute \src "ls180.v:6459.45-6459.155"
97698   cell $and $and$ls180.v:6459$2211
97699     parameter \A_SIGNED 0
97700     parameter \A_WIDTH 1
97701     parameter \B_SIGNED 0
97702     parameter \B_WIDTH 1
97703     parameter \Y_WIDTH 1
97704     connect \A $and$ls180.v:6459$2209_Y
97705     connect \B $eq$ls180.v:6459$2210_Y
97706     connect \Y $and$ls180.v:6459$2211_Y
97707   end
97708   attribute \src "ls180.v:6461.46-6461.101"
97709   cell $and $and$ls180.v:6461$2212
97710     parameter \A_SIGNED 0
97711     parameter \A_WIDTH 1
97712     parameter \B_SIGNED 0
97713     parameter \B_WIDTH 1
97714     parameter \Y_WIDTH 1
97715     connect \A \builder_csrbank14_sel
97716     connect \B \builder_interface14_bank_bus_we
97717     connect \Y $and$ls180.v:6461$2212_Y
97718   end
97719   attribute \src "ls180.v:6461.45-6461.152"
97720   cell $and $and$ls180.v:6461$2214
97721     parameter \A_SIGNED 0
97722     parameter \A_WIDTH 1
97723     parameter \B_SIGNED 0
97724     parameter \B_WIDTH 1
97725     parameter \Y_WIDTH 1
97726     connect \A $and$ls180.v:6461$2212_Y
97727     connect \B $eq$ls180.v:6461$2213_Y
97728     connect \Y $and$ls180.v:6461$2214_Y
97729   end
97730   attribute \src "ls180.v:6462.46-6462.104"
97731   cell $and $and$ls180.v:6462$2216
97732     parameter \A_SIGNED 0
97733     parameter \A_WIDTH 1
97734     parameter \B_SIGNED 0
97735     parameter \B_WIDTH 1
97736     parameter \Y_WIDTH 1
97737     connect \A \builder_csrbank14_sel
97738     connect \B $not$ls180.v:6462$2215_Y
97739     connect \Y $and$ls180.v:6462$2216_Y
97740   end
97741   attribute \src "ls180.v:6462.45-6462.155"
97742   cell $and $and$ls180.v:6462$2218
97743     parameter \A_SIGNED 0
97744     parameter \A_WIDTH 1
97745     parameter \B_SIGNED 0
97746     parameter \B_WIDTH 1
97747     parameter \Y_WIDTH 1
97748     connect \A $and$ls180.v:6462$2216_Y
97749     connect \B $eq$ls180.v:6462$2217_Y
97750     connect \Y $and$ls180.v:6462$2218_Y
97751   end
97752   attribute \src "ls180.v:6464.46-6464.101"
97753   cell $and $and$ls180.v:6464$2219
97754     parameter \A_SIGNED 0
97755     parameter \A_WIDTH 1
97756     parameter \B_SIGNED 0
97757     parameter \B_WIDTH 1
97758     parameter \Y_WIDTH 1
97759     connect \A \builder_csrbank14_sel
97760     connect \B \builder_interface14_bank_bus_we
97761     connect \Y $and$ls180.v:6464$2219_Y
97762   end
97763   attribute \src "ls180.v:6464.45-6464.152"
97764   cell $and $and$ls180.v:6464$2221
97765     parameter \A_SIGNED 0
97766     parameter \A_WIDTH 1
97767     parameter \B_SIGNED 0
97768     parameter \B_WIDTH 1
97769     parameter \Y_WIDTH 1
97770     connect \A $and$ls180.v:6464$2219_Y
97771     connect \B $eq$ls180.v:6464$2220_Y
97772     connect \Y $and$ls180.v:6464$2221_Y
97773   end
97774   attribute \src "ls180.v:6465.46-6465.104"
97775   cell $and $and$ls180.v:6465$2223
97776     parameter \A_SIGNED 0
97777     parameter \A_WIDTH 1
97778     parameter \B_SIGNED 0
97779     parameter \B_WIDTH 1
97780     parameter \Y_WIDTH 1
97781     connect \A \builder_csrbank14_sel
97782     connect \B $not$ls180.v:6465$2222_Y
97783     connect \Y $and$ls180.v:6465$2223_Y
97784   end
97785   attribute \src "ls180.v:6465.45-6465.155"
97786   cell $and $and$ls180.v:6465$2225
97787     parameter \A_SIGNED 0
97788     parameter \A_WIDTH 1
97789     parameter \B_SIGNED 0
97790     parameter \B_WIDTH 1
97791     parameter \Y_WIDTH 1
97792     connect \A $and$ls180.v:6465$2223_Y
97793     connect \B $eq$ls180.v:6465$2224_Y
97794     connect \Y $and$ls180.v:6465$2225_Y
97795   end
97796   attribute \src "ls180.v:6846.109-6846.178"
97797   cell $and $and$ls180.v:6846$2263
97798     parameter \A_SIGNED 0
97799     parameter \A_WIDTH 1
97800     parameter \B_SIGNED 0
97801     parameter \B_WIDTH 1
97802     parameter \Y_WIDTH 1
97803     connect \A \main_sdram_interface_bank1_lock
97804     connect \B $eq$ls180.v:6846$2262_Y
97805     connect \Y $and$ls180.v:6846$2263_Y
97806   end
97807   attribute \src "ls180.v:6846.184-6846.253"
97808   cell $and $and$ls180.v:6846$2266
97809     parameter \A_SIGNED 0
97810     parameter \A_WIDTH 1
97811     parameter \B_SIGNED 0
97812     parameter \B_WIDTH 1
97813     parameter \Y_WIDTH 1
97814     connect \A \main_sdram_interface_bank2_lock
97815     connect \B $eq$ls180.v:6846$2265_Y
97816     connect \Y $and$ls180.v:6846$2266_Y
97817   end
97818   attribute \src "ls180.v:6846.259-6846.328"
97819   cell $and $and$ls180.v:6846$2269
97820     parameter \A_SIGNED 0
97821     parameter \A_WIDTH 1
97822     parameter \B_SIGNED 0
97823     parameter \B_WIDTH 1
97824     parameter \Y_WIDTH 1
97825     connect \A \main_sdram_interface_bank3_lock
97826     connect \B $eq$ls180.v:6846$2268_Y
97827     connect \Y $and$ls180.v:6846$2269_Y
97828   end
97829   attribute \src "ls180.v:6846.40-6846.331"
97830   cell $and $and$ls180.v:6846$2272
97831     parameter \A_SIGNED 0
97832     parameter \A_WIDTH 1
97833     parameter \B_SIGNED 0
97834     parameter \B_WIDTH 1
97835     parameter \Y_WIDTH 1
97836     connect \A $eq$ls180.v:6846$2261_Y
97837     connect \B $not$ls180.v:6846$2271_Y
97838     connect \Y $and$ls180.v:6846$2272_Y
97839   end
97840   attribute \src "ls180.v:6846.39-6846.354"
97841   cell $and $and$ls180.v:6846$2273
97842     parameter \A_SIGNED 0
97843     parameter \A_WIDTH 1
97844     parameter \B_SIGNED 0
97845     parameter \B_WIDTH 1
97846     parameter \Y_WIDTH 1
97847     connect \A $and$ls180.v:6846$2272_Y
97848     connect \B \main_port_cmd_valid
97849     connect \Y $and$ls180.v:6846$2273_Y
97850   end
97851   attribute \src "ls180.v:6870.109-6870.178"
97852   cell $and $and$ls180.v:6870$2279
97853     parameter \A_SIGNED 0
97854     parameter \A_WIDTH 1
97855     parameter \B_SIGNED 0
97856     parameter \B_WIDTH 1
97857     parameter \Y_WIDTH 1
97858     connect \A \main_sdram_interface_bank0_lock
97859     connect \B $eq$ls180.v:6870$2278_Y
97860     connect \Y $and$ls180.v:6870$2279_Y
97861   end
97862   attribute \src "ls180.v:6870.184-6870.253"
97863   cell $and $and$ls180.v:6870$2282
97864     parameter \A_SIGNED 0
97865     parameter \A_WIDTH 1
97866     parameter \B_SIGNED 0
97867     parameter \B_WIDTH 1
97868     parameter \Y_WIDTH 1
97869     connect \A \main_sdram_interface_bank2_lock
97870     connect \B $eq$ls180.v:6870$2281_Y
97871     connect \Y $and$ls180.v:6870$2282_Y
97872   end
97873   attribute \src "ls180.v:6870.259-6870.328"
97874   cell $and $and$ls180.v:6870$2285
97875     parameter \A_SIGNED 0
97876     parameter \A_WIDTH 1
97877     parameter \B_SIGNED 0
97878     parameter \B_WIDTH 1
97879     parameter \Y_WIDTH 1
97880     connect \A \main_sdram_interface_bank3_lock
97881     connect \B $eq$ls180.v:6870$2284_Y
97882     connect \Y $and$ls180.v:6870$2285_Y
97883   end
97884   attribute \src "ls180.v:6870.40-6870.331"
97885   cell $and $and$ls180.v:6870$2288
97886     parameter \A_SIGNED 0
97887     parameter \A_WIDTH 1
97888     parameter \B_SIGNED 0
97889     parameter \B_WIDTH 1
97890     parameter \Y_WIDTH 1
97891     connect \A $eq$ls180.v:6870$2277_Y
97892     connect \B $not$ls180.v:6870$2287_Y
97893     connect \Y $and$ls180.v:6870$2288_Y
97894   end
97895   attribute \src "ls180.v:6870.39-6870.354"
97896   cell $and $and$ls180.v:6870$2289
97897     parameter \A_SIGNED 0
97898     parameter \A_WIDTH 1
97899     parameter \B_SIGNED 0
97900     parameter \B_WIDTH 1
97901     parameter \Y_WIDTH 1
97902     connect \A $and$ls180.v:6870$2288_Y
97903     connect \B \main_port_cmd_valid
97904     connect \Y $and$ls180.v:6870$2289_Y
97905   end
97906   attribute \src "ls180.v:6894.109-6894.178"
97907   cell $and $and$ls180.v:6894$2295
97908     parameter \A_SIGNED 0
97909     parameter \A_WIDTH 1
97910     parameter \B_SIGNED 0
97911     parameter \B_WIDTH 1
97912     parameter \Y_WIDTH 1
97913     connect \A \main_sdram_interface_bank0_lock
97914     connect \B $eq$ls180.v:6894$2294_Y
97915     connect \Y $and$ls180.v:6894$2295_Y
97916   end
97917   attribute \src "ls180.v:6894.184-6894.253"
97918   cell $and $and$ls180.v:6894$2298
97919     parameter \A_SIGNED 0
97920     parameter \A_WIDTH 1
97921     parameter \B_SIGNED 0
97922     parameter \B_WIDTH 1
97923     parameter \Y_WIDTH 1
97924     connect \A \main_sdram_interface_bank1_lock
97925     connect \B $eq$ls180.v:6894$2297_Y
97926     connect \Y $and$ls180.v:6894$2298_Y
97927   end
97928   attribute \src "ls180.v:6894.259-6894.328"
97929   cell $and $and$ls180.v:6894$2301
97930     parameter \A_SIGNED 0
97931     parameter \A_WIDTH 1
97932     parameter \B_SIGNED 0
97933     parameter \B_WIDTH 1
97934     parameter \Y_WIDTH 1
97935     connect \A \main_sdram_interface_bank3_lock
97936     connect \B $eq$ls180.v:6894$2300_Y
97937     connect \Y $and$ls180.v:6894$2301_Y
97938   end
97939   attribute \src "ls180.v:6894.40-6894.331"
97940   cell $and $and$ls180.v:6894$2304
97941     parameter \A_SIGNED 0
97942     parameter \A_WIDTH 1
97943     parameter \B_SIGNED 0
97944     parameter \B_WIDTH 1
97945     parameter \Y_WIDTH 1
97946     connect \A $eq$ls180.v:6894$2293_Y
97947     connect \B $not$ls180.v:6894$2303_Y
97948     connect \Y $and$ls180.v:6894$2304_Y
97949   end
97950   attribute \src "ls180.v:6894.39-6894.354"
97951   cell $and $and$ls180.v:6894$2305
97952     parameter \A_SIGNED 0
97953     parameter \A_WIDTH 1
97954     parameter \B_SIGNED 0
97955     parameter \B_WIDTH 1
97956     parameter \Y_WIDTH 1
97957     connect \A $and$ls180.v:6894$2304_Y
97958     connect \B \main_port_cmd_valid
97959     connect \Y $and$ls180.v:6894$2305_Y
97960   end
97961   attribute \src "ls180.v:6918.109-6918.178"
97962   cell $and $and$ls180.v:6918$2311
97963     parameter \A_SIGNED 0
97964     parameter \A_WIDTH 1
97965     parameter \B_SIGNED 0
97966     parameter \B_WIDTH 1
97967     parameter \Y_WIDTH 1
97968     connect \A \main_sdram_interface_bank0_lock
97969     connect \B $eq$ls180.v:6918$2310_Y
97970     connect \Y $and$ls180.v:6918$2311_Y
97971   end
97972   attribute \src "ls180.v:6918.184-6918.253"
97973   cell $and $and$ls180.v:6918$2314
97974     parameter \A_SIGNED 0
97975     parameter \A_WIDTH 1
97976     parameter \B_SIGNED 0
97977     parameter \B_WIDTH 1
97978     parameter \Y_WIDTH 1
97979     connect \A \main_sdram_interface_bank1_lock
97980     connect \B $eq$ls180.v:6918$2313_Y
97981     connect \Y $and$ls180.v:6918$2314_Y
97982   end
97983   attribute \src "ls180.v:6918.259-6918.328"
97984   cell $and $and$ls180.v:6918$2317
97985     parameter \A_SIGNED 0
97986     parameter \A_WIDTH 1
97987     parameter \B_SIGNED 0
97988     parameter \B_WIDTH 1
97989     parameter \Y_WIDTH 1
97990     connect \A \main_sdram_interface_bank2_lock
97991     connect \B $eq$ls180.v:6918$2316_Y
97992     connect \Y $and$ls180.v:6918$2317_Y
97993   end
97994   attribute \src "ls180.v:6918.40-6918.331"
97995   cell $and $and$ls180.v:6918$2320
97996     parameter \A_SIGNED 0
97997     parameter \A_WIDTH 1
97998     parameter \B_SIGNED 0
97999     parameter \B_WIDTH 1
98000     parameter \Y_WIDTH 1
98001     connect \A $eq$ls180.v:6918$2309_Y
98002     connect \B $not$ls180.v:6918$2319_Y
98003     connect \Y $and$ls180.v:6918$2320_Y
98004   end
98005   attribute \src "ls180.v:6918.39-6918.354"
98006   cell $and $and$ls180.v:6918$2321
98007     parameter \A_SIGNED 0
98008     parameter \A_WIDTH 1
98009     parameter \B_SIGNED 0
98010     parameter \B_WIDTH 1
98011     parameter \Y_WIDTH 1
98012     connect \A $and$ls180.v:6918$2320_Y
98013     connect \B \main_port_cmd_valid
98014     connect \Y $and$ls180.v:6918$2321_Y
98015   end
98016   attribute \src "ls180.v:7123.39-7123.104"
98017   cell $and $and$ls180.v:7123$2333
98018     parameter \A_SIGNED 0
98019     parameter \A_WIDTH 1
98020     parameter \B_SIGNED 0
98021     parameter \B_WIDTH 1
98022     parameter \Y_WIDTH 1
98023     connect \A \main_sdram_choose_req_cmd_valid
98024     connect \B \main_sdram_choose_req_cmd_ready
98025     connect \Y $and$ls180.v:7123$2333_Y
98026   end
98027   attribute \src "ls180.v:7123.38-7123.145"
98028   cell $and $and$ls180.v:7123$2334
98029     parameter \A_SIGNED 0
98030     parameter \A_WIDTH 1
98031     parameter \B_SIGNED 0
98032     parameter \B_WIDTH 1
98033     parameter \Y_WIDTH 1
98034     connect \A $and$ls180.v:7123$2333_Y
98035     connect \B \main_sdram_choose_req_cmd_payload_cas
98036     connect \Y $and$ls180.v:7123$2334_Y
98037   end
98038   attribute \src "ls180.v:7126.39-7126.104"
98039   cell $and $and$ls180.v:7126$2335
98040     parameter \A_SIGNED 0
98041     parameter \A_WIDTH 1
98042     parameter \B_SIGNED 0
98043     parameter \B_WIDTH 1
98044     parameter \Y_WIDTH 1
98045     connect \A \main_sdram_choose_req_cmd_valid
98046     connect \B \main_sdram_choose_req_cmd_ready
98047     connect \Y $and$ls180.v:7126$2335_Y
98048   end
98049   attribute \src "ls180.v:7126.38-7126.145"
98050   cell $and $and$ls180.v:7126$2336
98051     parameter \A_SIGNED 0
98052     parameter \A_WIDTH 1
98053     parameter \B_SIGNED 0
98054     parameter \B_WIDTH 1
98055     parameter \Y_WIDTH 1
98056     connect \A $and$ls180.v:7126$2335_Y
98057     connect \B \main_sdram_choose_req_cmd_payload_cas
98058     connect \Y $and$ls180.v:7126$2336_Y
98059   end
98060   attribute \src "ls180.v:7129.39-7129.82"
98061   cell $and $and$ls180.v:7129$2337
98062     parameter \A_SIGNED 0
98063     parameter \A_WIDTH 1
98064     parameter \B_SIGNED 0
98065     parameter \B_WIDTH 1
98066     parameter \Y_WIDTH 1
98067     connect \A \main_sdram_cmd_valid
98068     connect \B \main_sdram_cmd_ready
98069     connect \Y $and$ls180.v:7129$2337_Y
98070   end
98071   attribute \src "ls180.v:7129.38-7129.112"
98072   cell $and $and$ls180.v:7129$2338
98073     parameter \A_SIGNED 0
98074     parameter \A_WIDTH 1
98075     parameter \B_SIGNED 0
98076     parameter \B_WIDTH 1
98077     parameter \Y_WIDTH 1
98078     connect \A $and$ls180.v:7129$2337_Y
98079     connect \B \main_sdram_cmd_payload_cas
98080     connect \Y $and$ls180.v:7129$2338_Y
98081   end
98082   attribute \src "ls180.v:7140.39-7140.104"
98083   cell $and $and$ls180.v:7140$2340
98084     parameter \A_SIGNED 0
98085     parameter \A_WIDTH 1
98086     parameter \B_SIGNED 0
98087     parameter \B_WIDTH 1
98088     parameter \Y_WIDTH 1
98089     connect \A \main_sdram_choose_req_cmd_valid
98090     connect \B \main_sdram_choose_req_cmd_ready
98091     connect \Y $and$ls180.v:7140$2340_Y
98092   end
98093   attribute \src "ls180.v:7140.38-7140.145"
98094   cell $and $and$ls180.v:7140$2341
98095     parameter \A_SIGNED 0
98096     parameter \A_WIDTH 1
98097     parameter \B_SIGNED 0
98098     parameter \B_WIDTH 1
98099     parameter \Y_WIDTH 1
98100     connect \A $and$ls180.v:7140$2340_Y
98101     connect \B \main_sdram_choose_req_cmd_payload_ras
98102     connect \Y $and$ls180.v:7140$2341_Y
98103   end
98104   attribute \src "ls180.v:7143.39-7143.104"
98105   cell $and $and$ls180.v:7143$2342
98106     parameter \A_SIGNED 0
98107     parameter \A_WIDTH 1
98108     parameter \B_SIGNED 0
98109     parameter \B_WIDTH 1
98110     parameter \Y_WIDTH 1
98111     connect \A \main_sdram_choose_req_cmd_valid
98112     connect \B \main_sdram_choose_req_cmd_ready
98113     connect \Y $and$ls180.v:7143$2342_Y
98114   end
98115   attribute \src "ls180.v:7143.38-7143.145"
98116   cell $and $and$ls180.v:7143$2343
98117     parameter \A_SIGNED 0
98118     parameter \A_WIDTH 1
98119     parameter \B_SIGNED 0
98120     parameter \B_WIDTH 1
98121     parameter \Y_WIDTH 1
98122     connect \A $and$ls180.v:7143$2342_Y
98123     connect \B \main_sdram_choose_req_cmd_payload_ras
98124     connect \Y $and$ls180.v:7143$2343_Y
98125   end
98126   attribute \src "ls180.v:7146.39-7146.82"
98127   cell $and $and$ls180.v:7146$2344
98128     parameter \A_SIGNED 0
98129     parameter \A_WIDTH 1
98130     parameter \B_SIGNED 0
98131     parameter \B_WIDTH 1
98132     parameter \Y_WIDTH 1
98133     connect \A \main_sdram_cmd_valid
98134     connect \B \main_sdram_cmd_ready
98135     connect \Y $and$ls180.v:7146$2344_Y
98136   end
98137   attribute \src "ls180.v:7146.38-7146.112"
98138   cell $and $and$ls180.v:7146$2345
98139     parameter \A_SIGNED 0
98140     parameter \A_WIDTH 1
98141     parameter \B_SIGNED 0
98142     parameter \B_WIDTH 1
98143     parameter \Y_WIDTH 1
98144     connect \A $and$ls180.v:7146$2344_Y
98145     connect \B \main_sdram_cmd_payload_ras
98146     connect \Y $and$ls180.v:7146$2345_Y
98147   end
98148   attribute \src "ls180.v:7157.39-7157.104"
98149   cell $and $and$ls180.v:7157$2347
98150     parameter \A_SIGNED 0
98151     parameter \A_WIDTH 1
98152     parameter \B_SIGNED 0
98153     parameter \B_WIDTH 1
98154     parameter \Y_WIDTH 1
98155     connect \A \main_sdram_choose_req_cmd_valid
98156     connect \B \main_sdram_choose_req_cmd_ready
98157     connect \Y $and$ls180.v:7157$2347_Y
98158   end
98159   attribute \src "ls180.v:7157.38-7157.144"
98160   cell $and $and$ls180.v:7157$2348
98161     parameter \A_SIGNED 0
98162     parameter \A_WIDTH 1
98163     parameter \B_SIGNED 0
98164     parameter \B_WIDTH 1
98165     parameter \Y_WIDTH 1
98166     connect \A $and$ls180.v:7157$2347_Y
98167     connect \B \main_sdram_choose_req_cmd_payload_we
98168     connect \Y $and$ls180.v:7157$2348_Y
98169   end
98170   attribute \src "ls180.v:7160.39-7160.104"
98171   cell $and $and$ls180.v:7160$2349
98172     parameter \A_SIGNED 0
98173     parameter \A_WIDTH 1
98174     parameter \B_SIGNED 0
98175     parameter \B_WIDTH 1
98176     parameter \Y_WIDTH 1
98177     connect \A \main_sdram_choose_req_cmd_valid
98178     connect \B \main_sdram_choose_req_cmd_ready
98179     connect \Y $and$ls180.v:7160$2349_Y
98180   end
98181   attribute \src "ls180.v:7160.38-7160.144"
98182   cell $and $and$ls180.v:7160$2350
98183     parameter \A_SIGNED 0
98184     parameter \A_WIDTH 1
98185     parameter \B_SIGNED 0
98186     parameter \B_WIDTH 1
98187     parameter \Y_WIDTH 1
98188     connect \A $and$ls180.v:7160$2349_Y
98189     connect \B \main_sdram_choose_req_cmd_payload_we
98190     connect \Y $and$ls180.v:7160$2350_Y
98191   end
98192   attribute \src "ls180.v:7163.39-7163.82"
98193   cell $and $and$ls180.v:7163$2351
98194     parameter \A_SIGNED 0
98195     parameter \A_WIDTH 1
98196     parameter \B_SIGNED 0
98197     parameter \B_WIDTH 1
98198     parameter \Y_WIDTH 1
98199     connect \A \main_sdram_cmd_valid
98200     connect \B \main_sdram_cmd_ready
98201     connect \Y $and$ls180.v:7163$2351_Y
98202   end
98203   attribute \src "ls180.v:7163.38-7163.111"
98204   cell $and $and$ls180.v:7163$2352
98205     parameter \A_SIGNED 0
98206     parameter \A_WIDTH 1
98207     parameter \B_SIGNED 0
98208     parameter \B_WIDTH 1
98209     parameter \Y_WIDTH 1
98210     connect \A $and$ls180.v:7163$2351_Y
98211     connect \B \main_sdram_cmd_payload_we
98212     connect \Y $and$ls180.v:7163$2352_Y
98213   end
98214   attribute \src "ls180.v:7174.39-7174.104"
98215   cell $and $and$ls180.v:7174$2354
98216     parameter \A_SIGNED 0
98217     parameter \A_WIDTH 1
98218     parameter \B_SIGNED 0
98219     parameter \B_WIDTH 1
98220     parameter \Y_WIDTH 1
98221     connect \A \main_sdram_choose_req_cmd_valid
98222     connect \B \main_sdram_choose_req_cmd_ready
98223     connect \Y $and$ls180.v:7174$2354_Y
98224   end
98225   attribute \src "ls180.v:7174.38-7174.149"
98226   cell $and $and$ls180.v:7174$2355
98227     parameter \A_SIGNED 0
98228     parameter \A_WIDTH 1
98229     parameter \B_SIGNED 0
98230     parameter \B_WIDTH 1
98231     parameter \Y_WIDTH 1
98232     connect \A $and$ls180.v:7174$2354_Y
98233     connect \B \main_sdram_choose_req_cmd_payload_is_read
98234     connect \Y $and$ls180.v:7174$2355_Y
98235   end
98236   attribute \src "ls180.v:7177.39-7177.104"
98237   cell $and $and$ls180.v:7177$2356
98238     parameter \A_SIGNED 0
98239     parameter \A_WIDTH 1
98240     parameter \B_SIGNED 0
98241     parameter \B_WIDTH 1
98242     parameter \Y_WIDTH 1
98243     connect \A \main_sdram_choose_req_cmd_valid
98244     connect \B \main_sdram_choose_req_cmd_ready
98245     connect \Y $and$ls180.v:7177$2356_Y
98246   end
98247   attribute \src "ls180.v:7177.38-7177.149"
98248   cell $and $and$ls180.v:7177$2357
98249     parameter \A_SIGNED 0
98250     parameter \A_WIDTH 1
98251     parameter \B_SIGNED 0
98252     parameter \B_WIDTH 1
98253     parameter \Y_WIDTH 1
98254     connect \A $and$ls180.v:7177$2356_Y
98255     connect \B \main_sdram_choose_req_cmd_payload_is_read
98256     connect \Y $and$ls180.v:7177$2357_Y
98257   end
98258   attribute \src "ls180.v:7180.39-7180.82"
98259   cell $and $and$ls180.v:7180$2358
98260     parameter \A_SIGNED 0
98261     parameter \A_WIDTH 1
98262     parameter \B_SIGNED 0
98263     parameter \B_WIDTH 1
98264     parameter \Y_WIDTH 1
98265     connect \A \main_sdram_cmd_valid
98266     connect \B \main_sdram_cmd_ready
98267     connect \Y $and$ls180.v:7180$2358_Y
98268   end
98269   attribute \src "ls180.v:7180.38-7180.116"
98270   cell $and $and$ls180.v:7180$2359
98271     parameter \A_SIGNED 0
98272     parameter \A_WIDTH 1
98273     parameter \B_SIGNED 0
98274     parameter \B_WIDTH 1
98275     parameter \Y_WIDTH 1
98276     connect \A $and$ls180.v:7180$2358_Y
98277     connect \B \main_sdram_cmd_payload_is_read
98278     connect \Y $and$ls180.v:7180$2359_Y
98279   end
98280   attribute \src "ls180.v:7191.39-7191.104"
98281   cell $and $and$ls180.v:7191$2361
98282     parameter \A_SIGNED 0
98283     parameter \A_WIDTH 1
98284     parameter \B_SIGNED 0
98285     parameter \B_WIDTH 1
98286     parameter \Y_WIDTH 1
98287     connect \A \main_sdram_choose_req_cmd_valid
98288     connect \B \main_sdram_choose_req_cmd_ready
98289     connect \Y $and$ls180.v:7191$2361_Y
98290   end
98291   attribute \src "ls180.v:7191.38-7191.150"
98292   cell $and $and$ls180.v:7191$2362
98293     parameter \A_SIGNED 0
98294     parameter \A_WIDTH 1
98295     parameter \B_SIGNED 0
98296     parameter \B_WIDTH 1
98297     parameter \Y_WIDTH 1
98298     connect \A $and$ls180.v:7191$2361_Y
98299     connect \B \main_sdram_choose_req_cmd_payload_is_write
98300     connect \Y $and$ls180.v:7191$2362_Y
98301   end
98302   attribute \src "ls180.v:7194.39-7194.104"
98303   cell $and $and$ls180.v:7194$2363
98304     parameter \A_SIGNED 0
98305     parameter \A_WIDTH 1
98306     parameter \B_SIGNED 0
98307     parameter \B_WIDTH 1
98308     parameter \Y_WIDTH 1
98309     connect \A \main_sdram_choose_req_cmd_valid
98310     connect \B \main_sdram_choose_req_cmd_ready
98311     connect \Y $and$ls180.v:7194$2363_Y
98312   end
98313   attribute \src "ls180.v:7194.38-7194.150"
98314   cell $and $and$ls180.v:7194$2364
98315     parameter \A_SIGNED 0
98316     parameter \A_WIDTH 1
98317     parameter \B_SIGNED 0
98318     parameter \B_WIDTH 1
98319     parameter \Y_WIDTH 1
98320     connect \A $and$ls180.v:7194$2363_Y
98321     connect \B \main_sdram_choose_req_cmd_payload_is_write
98322     connect \Y $and$ls180.v:7194$2364_Y
98323   end
98324   attribute \src "ls180.v:7197.39-7197.82"
98325   cell $and $and$ls180.v:7197$2365
98326     parameter \A_SIGNED 0
98327     parameter \A_WIDTH 1
98328     parameter \B_SIGNED 0
98329     parameter \B_WIDTH 1
98330     parameter \Y_WIDTH 1
98331     connect \A \main_sdram_cmd_valid
98332     connect \B \main_sdram_cmd_ready
98333     connect \Y $and$ls180.v:7197$2365_Y
98334   end
98335   attribute \src "ls180.v:7197.38-7197.117"
98336   cell $and $and$ls180.v:7197$2366
98337     parameter \A_SIGNED 0
98338     parameter \A_WIDTH 1
98339     parameter \B_SIGNED 0
98340     parameter \B_WIDTH 1
98341     parameter \Y_WIDTH 1
98342     connect \A $and$ls180.v:7197$2365_Y
98343     connect \B \main_sdram_cmd_payload_is_write
98344     connect \Y $and$ls180.v:7197$2366_Y
98345   end
98346   attribute \src "ls180.v:7416.17-7416.67"
98347   cell $and $and$ls180.v:7416$2373
98348     parameter \A_SIGNED 0
98349     parameter \A_WIDTH 1
98350     parameter \B_SIGNED 0
98351     parameter \B_WIDTH 1
98352     parameter \Y_WIDTH 1
98353     connect \A $not$ls180.v:7416$2372_Y
98354     connect \B \main_sdphy_sdpads_clk
98355     connect \Y $and$ls180.v:7416$2373_Y
98356   end
98357   attribute \src "ls180.v:7507.8-7507.67"
98358   cell $and $and$ls180.v:7507$2416
98359     parameter \A_SIGNED 0
98360     parameter \A_WIDTH 1
98361     parameter \B_SIGNED 0
98362     parameter \B_WIDTH 1
98363     parameter \Y_WIDTH 1
98364     connect \A \main_libresocsim_ram_bus_cyc
98365     connect \B \main_libresocsim_ram_bus_stb
98366     connect \Y $and$ls180.v:7507$2416_Y
98367   end
98368   attribute \src "ls180.v:7507.7-7507.102"
98369   cell $and $and$ls180.v:7507$2418
98370     parameter \A_SIGNED 0
98371     parameter \A_WIDTH 1
98372     parameter \B_SIGNED 0
98373     parameter \B_WIDTH 1
98374     parameter \Y_WIDTH 1
98375     connect \A $and$ls180.v:7507$2416_Y
98376     connect \B $not$ls180.v:7507$2417_Y
98377     connect \Y $and$ls180.v:7507$2418_Y
98378   end
98379   attribute \src "ls180.v:7526.7-7526.75"
98380   cell $and $and$ls180.v:7526$2422
98381     parameter \A_SIGNED 0
98382     parameter \A_WIDTH 1
98383     parameter \B_SIGNED 0
98384     parameter \B_WIDTH 1
98385     parameter \Y_WIDTH 1
98386     connect \A $not$ls180.v:7526$2421_Y
98387     connect \B \main_libresocsim_zero_old_trigger
98388     connect \Y $and$ls180.v:7526$2422_Y
98389   end
98390   attribute \src "ls180.v:7534.7-7534.56"
98391   cell $and $and$ls180.v:7534$2424
98392     parameter \A_SIGNED 0
98393     parameter \A_WIDTH 1
98394     parameter \B_SIGNED 0
98395     parameter \B_WIDTH 1
98396     parameter \Y_WIDTH 1
98397     connect \A \main_sdram_timer_wait
98398     connect \B $not$ls180.v:7534$2423_Y
98399     connect \Y $and$ls180.v:7534$2424_Y
98400   end
98401   attribute \src "ls180.v:7562.7-7562.75"
98402   cell $and $and$ls180.v:7562$2431
98403     parameter \A_SIGNED 0
98404     parameter \A_WIDTH 1
98405     parameter \B_SIGNED 0
98406     parameter \B_WIDTH 1
98407     parameter \Y_WIDTH 1
98408     connect \A \main_sdram_sequencer_start1
98409     connect \B $eq$ls180.v:7562$2430_Y
98410     connect \Y $and$ls180.v:7562$2431_Y
98411   end
98412   attribute \src "ls180.v:7604.8-7604.131"
98413   cell $and $and$ls180.v:7604$2437
98414     parameter \A_SIGNED 0
98415     parameter \A_WIDTH 1
98416     parameter \B_SIGNED 0
98417     parameter \B_WIDTH 1
98418     parameter \Y_WIDTH 1
98419     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
98420     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
98421     connect \Y $and$ls180.v:7604$2437_Y
98422   end
98423   attribute \src "ls180.v:7604.7-7604.190"
98424   cell $and $and$ls180.v:7604$2439
98425     parameter \A_SIGNED 0
98426     parameter \A_WIDTH 1
98427     parameter \B_SIGNED 0
98428     parameter \B_WIDTH 1
98429     parameter \Y_WIDTH 1
98430     connect \A $and$ls180.v:7604$2437_Y
98431     connect \B $not$ls180.v:7604$2438_Y
98432     connect \Y $and$ls180.v:7604$2439_Y
98433   end
98434   attribute \src "ls180.v:7610.8-7610.131"
98435   cell $and $and$ls180.v:7610$2442
98436     parameter \A_SIGNED 0
98437     parameter \A_WIDTH 1
98438     parameter \B_SIGNED 0
98439     parameter \B_WIDTH 1
98440     parameter \Y_WIDTH 1
98441     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
98442     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
98443     connect \Y $and$ls180.v:7610$2442_Y
98444   end
98445   attribute \src "ls180.v:7610.7-7610.190"
98446   cell $and $and$ls180.v:7610$2444
98447     parameter \A_SIGNED 0
98448     parameter \A_WIDTH 1
98449     parameter \B_SIGNED 0
98450     parameter \B_WIDTH 1
98451     parameter \Y_WIDTH 1
98452     connect \A $and$ls180.v:7610$2442_Y
98453     connect \B $not$ls180.v:7610$2443_Y
98454     connect \Y $and$ls180.v:7610$2444_Y
98455   end
98456   attribute \src "ls180.v:7650.8-7650.131"
98457   cell $and $and$ls180.v:7650$2453
98458     parameter \A_SIGNED 0
98459     parameter \A_WIDTH 1
98460     parameter \B_SIGNED 0
98461     parameter \B_WIDTH 1
98462     parameter \Y_WIDTH 1
98463     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
98464     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
98465     connect \Y $and$ls180.v:7650$2453_Y
98466   end
98467   attribute \src "ls180.v:7650.7-7650.190"
98468   cell $and $and$ls180.v:7650$2455
98469     parameter \A_SIGNED 0
98470     parameter \A_WIDTH 1
98471     parameter \B_SIGNED 0
98472     parameter \B_WIDTH 1
98473     parameter \Y_WIDTH 1
98474     connect \A $and$ls180.v:7650$2453_Y
98475     connect \B $not$ls180.v:7650$2454_Y
98476     connect \Y $and$ls180.v:7650$2455_Y
98477   end
98478   attribute \src "ls180.v:7656.8-7656.131"
98479   cell $and $and$ls180.v:7656$2458
98480     parameter \A_SIGNED 0
98481     parameter \A_WIDTH 1
98482     parameter \B_SIGNED 0
98483     parameter \B_WIDTH 1
98484     parameter \Y_WIDTH 1
98485     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
98486     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
98487     connect \Y $and$ls180.v:7656$2458_Y
98488   end
98489   attribute \src "ls180.v:7656.7-7656.190"
98490   cell $and $and$ls180.v:7656$2460
98491     parameter \A_SIGNED 0
98492     parameter \A_WIDTH 1
98493     parameter \B_SIGNED 0
98494     parameter \B_WIDTH 1
98495     parameter \Y_WIDTH 1
98496     connect \A $and$ls180.v:7656$2458_Y
98497     connect \B $not$ls180.v:7656$2459_Y
98498     connect \Y $and$ls180.v:7656$2460_Y
98499   end
98500   attribute \src "ls180.v:7696.8-7696.131"
98501   cell $and $and$ls180.v:7696$2469
98502     parameter \A_SIGNED 0
98503     parameter \A_WIDTH 1
98504     parameter \B_SIGNED 0
98505     parameter \B_WIDTH 1
98506     parameter \Y_WIDTH 1
98507     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
98508     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
98509     connect \Y $and$ls180.v:7696$2469_Y
98510   end
98511   attribute \src "ls180.v:7696.7-7696.190"
98512   cell $and $and$ls180.v:7696$2471
98513     parameter \A_SIGNED 0
98514     parameter \A_WIDTH 1
98515     parameter \B_SIGNED 0
98516     parameter \B_WIDTH 1
98517     parameter \Y_WIDTH 1
98518     connect \A $and$ls180.v:7696$2469_Y
98519     connect \B $not$ls180.v:7696$2470_Y
98520     connect \Y $and$ls180.v:7696$2471_Y
98521   end
98522   attribute \src "ls180.v:7702.8-7702.131"
98523   cell $and $and$ls180.v:7702$2474
98524     parameter \A_SIGNED 0
98525     parameter \A_WIDTH 1
98526     parameter \B_SIGNED 0
98527     parameter \B_WIDTH 1
98528     parameter \Y_WIDTH 1
98529     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
98530     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
98531     connect \Y $and$ls180.v:7702$2474_Y
98532   end
98533   attribute \src "ls180.v:7702.7-7702.190"
98534   cell $and $and$ls180.v:7702$2476
98535     parameter \A_SIGNED 0
98536     parameter \A_WIDTH 1
98537     parameter \B_SIGNED 0
98538     parameter \B_WIDTH 1
98539     parameter \Y_WIDTH 1
98540     connect \A $and$ls180.v:7702$2474_Y
98541     connect \B $not$ls180.v:7702$2475_Y
98542     connect \Y $and$ls180.v:7702$2476_Y
98543   end
98544   attribute \src "ls180.v:7742.8-7742.131"
98545   cell $and $and$ls180.v:7742$2485
98546     parameter \A_SIGNED 0
98547     parameter \A_WIDTH 1
98548     parameter \B_SIGNED 0
98549     parameter \B_WIDTH 1
98550     parameter \Y_WIDTH 1
98551     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
98552     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
98553     connect \Y $and$ls180.v:7742$2485_Y
98554   end
98555   attribute \src "ls180.v:7742.7-7742.190"
98556   cell $and $and$ls180.v:7742$2487
98557     parameter \A_SIGNED 0
98558     parameter \A_WIDTH 1
98559     parameter \B_SIGNED 0
98560     parameter \B_WIDTH 1
98561     parameter \Y_WIDTH 1
98562     connect \A $and$ls180.v:7742$2485_Y
98563     connect \B $not$ls180.v:7742$2486_Y
98564     connect \Y $and$ls180.v:7742$2487_Y
98565   end
98566   attribute \src "ls180.v:7748.8-7748.131"
98567   cell $and $and$ls180.v:7748$2490
98568     parameter \A_SIGNED 0
98569     parameter \A_WIDTH 1
98570     parameter \B_SIGNED 0
98571     parameter \B_WIDTH 1
98572     parameter \Y_WIDTH 1
98573     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
98574     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
98575     connect \Y $and$ls180.v:7748$2490_Y
98576   end
98577   attribute \src "ls180.v:7748.7-7748.190"
98578   cell $and $and$ls180.v:7748$2492
98579     parameter \A_SIGNED 0
98580     parameter \A_WIDTH 1
98581     parameter \B_SIGNED 0
98582     parameter \B_WIDTH 1
98583     parameter \Y_WIDTH 1
98584     connect \A $and$ls180.v:7748$2490_Y
98585     connect \B $not$ls180.v:7748$2491_Y
98586     connect \Y $and$ls180.v:7748$2492_Y
98587   end
98588   attribute \src "ls180.v:7945.48-7945.124"
98589   cell $and $and$ls180.v:7945$2517
98590     parameter \A_SIGNED 0
98591     parameter \A_WIDTH 1
98592     parameter \B_SIGNED 0
98593     parameter \B_WIDTH 1
98594     parameter \Y_WIDTH 1
98595     connect \A $eq$ls180.v:7945$2516_Y
98596     connect \B \main_sdram_interface_bank0_wdata_ready
98597     connect \Y $and$ls180.v:7945$2517_Y
98598   end
98599   attribute \src "ls180.v:7945.130-7945.206"
98600   cell $and $and$ls180.v:7945$2520
98601     parameter \A_SIGNED 0
98602     parameter \A_WIDTH 1
98603     parameter \B_SIGNED 0
98604     parameter \B_WIDTH 1
98605     parameter \Y_WIDTH 1
98606     connect \A $eq$ls180.v:7945$2519_Y
98607     connect \B \main_sdram_interface_bank1_wdata_ready
98608     connect \Y $and$ls180.v:7945$2520_Y
98609   end
98610   attribute \src "ls180.v:7945.212-7945.288"
98611   cell $and $and$ls180.v:7945$2523
98612     parameter \A_SIGNED 0
98613     parameter \A_WIDTH 1
98614     parameter \B_SIGNED 0
98615     parameter \B_WIDTH 1
98616     parameter \Y_WIDTH 1
98617     connect \A $eq$ls180.v:7945$2522_Y
98618     connect \B \main_sdram_interface_bank2_wdata_ready
98619     connect \Y $and$ls180.v:7945$2523_Y
98620   end
98621   attribute \src "ls180.v:7945.294-7945.370"
98622   cell $and $and$ls180.v:7945$2526
98623     parameter \A_SIGNED 0
98624     parameter \A_WIDTH 1
98625     parameter \B_SIGNED 0
98626     parameter \B_WIDTH 1
98627     parameter \Y_WIDTH 1
98628     connect \A $eq$ls180.v:7945$2525_Y
98629     connect \B \main_sdram_interface_bank3_wdata_ready
98630     connect \Y $and$ls180.v:7945$2526_Y
98631   end
98632   attribute \src "ls180.v:7946.49-7946.125"
98633   cell $and $and$ls180.v:7946$2529
98634     parameter \A_SIGNED 0
98635     parameter \A_WIDTH 1
98636     parameter \B_SIGNED 0
98637     parameter \B_WIDTH 1
98638     parameter \Y_WIDTH 1
98639     connect \A $eq$ls180.v:7946$2528_Y
98640     connect \B \main_sdram_interface_bank0_rdata_valid
98641     connect \Y $and$ls180.v:7946$2529_Y
98642   end
98643   attribute \src "ls180.v:7946.131-7946.207"
98644   cell $and $and$ls180.v:7946$2532
98645     parameter \A_SIGNED 0
98646     parameter \A_WIDTH 1
98647     parameter \B_SIGNED 0
98648     parameter \B_WIDTH 1
98649     parameter \Y_WIDTH 1
98650     connect \A $eq$ls180.v:7946$2531_Y
98651     connect \B \main_sdram_interface_bank1_rdata_valid
98652     connect \Y $and$ls180.v:7946$2532_Y
98653   end
98654   attribute \src "ls180.v:7946.213-7946.289"
98655   cell $and $and$ls180.v:7946$2535
98656     parameter \A_SIGNED 0
98657     parameter \A_WIDTH 1
98658     parameter \B_SIGNED 0
98659     parameter \B_WIDTH 1
98660     parameter \Y_WIDTH 1
98661     connect \A $eq$ls180.v:7946$2534_Y
98662     connect \B \main_sdram_interface_bank2_rdata_valid
98663     connect \Y $and$ls180.v:7946$2535_Y
98664   end
98665   attribute \src "ls180.v:7946.295-7946.371"
98666   cell $and $and$ls180.v:7946$2538
98667     parameter \A_SIGNED 0
98668     parameter \A_WIDTH 1
98669     parameter \B_SIGNED 0
98670     parameter \B_WIDTH 1
98671     parameter \Y_WIDTH 1
98672     connect \A $eq$ls180.v:7946$2537_Y
98673     connect \B \main_sdram_interface_bank3_rdata_valid
98674     connect \Y $and$ls180.v:7946$2538_Y
98675   end
98676   attribute \src "ls180.v:7965.8-7965.49"
98677   cell $and $and$ls180.v:7965$2541
98678     parameter \A_SIGNED 0
98679     parameter \A_WIDTH 1
98680     parameter \B_SIGNED 0
98681     parameter \B_WIDTH 1
98682     parameter \Y_WIDTH 1
98683     connect \A \main_port_cmd_valid
98684     connect \B \main_port_cmd_ready
98685     connect \Y $and$ls180.v:7965$2541_Y
98686   end
98687   attribute \src "ls180.v:7968.8-7968.53"
98688   cell $and $and$ls180.v:7968$2542
98689     parameter \A_SIGNED 0
98690     parameter \A_WIDTH 1
98691     parameter \B_SIGNED 0
98692     parameter \B_WIDTH 1
98693     parameter \Y_WIDTH 1
98694     connect \A \main_port_wdata_valid
98695     connect \B \main_port_wdata_ready
98696     connect \Y $and$ls180.v:7968$2542_Y
98697   end
98698   attribute \src "ls180.v:7973.8-7973.59"
98699   cell $and $and$ls180.v:7973$2544
98700     parameter \A_SIGNED 0
98701     parameter \A_WIDTH 1
98702     parameter \B_SIGNED 0
98703     parameter \B_WIDTH 1
98704     parameter \Y_WIDTH 1
98705     connect \A \main_uart_phy_sink_valid
98706     connect \B $not$ls180.v:7973$2543_Y
98707     connect \Y $and$ls180.v:7973$2544_Y
98708   end
98709   attribute \src "ls180.v:7973.7-7973.90"
98710   cell $and $and$ls180.v:7973$2546
98711     parameter \A_SIGNED 0
98712     parameter \A_WIDTH 1
98713     parameter \B_SIGNED 0
98714     parameter \B_WIDTH 1
98715     parameter \Y_WIDTH 1
98716     connect \A $and$ls180.v:7973$2544_Y
98717     connect \B $not$ls180.v:7973$2545_Y
98718     connect \Y $and$ls180.v:7973$2546_Y
98719   end
98720   attribute \src "ls180.v:7979.8-7979.59"
98721   cell $and $and$ls180.v:7979$2547
98722     parameter \A_SIGNED 0
98723     parameter \A_WIDTH 1
98724     parameter \B_SIGNED 0
98725     parameter \B_WIDTH 1
98726     parameter \Y_WIDTH 1
98727     connect \A \main_uart_phy_uart_clk_txen
98728     connect \B \main_uart_phy_tx_busy
98729     connect \Y $and$ls180.v:7979$2547_Y
98730   end
98731   attribute \src "ls180.v:8003.8-8003.48"
98732   cell $and $and$ls180.v:8003$2554
98733     parameter \A_SIGNED 0
98734     parameter \A_WIDTH 1
98735     parameter \B_SIGNED 0
98736     parameter \B_WIDTH 1
98737     parameter \Y_WIDTH 1
98738     connect \A $not$ls180.v:8003$2553_Y
98739     connect \B \main_uart_phy_rx_r
98740     connect \Y $and$ls180.v:8003$2554_Y
98741   end
98742   attribute \src "ls180.v:8036.7-8036.57"
98743   cell $and $and$ls180.v:8036$2560
98744     parameter \A_SIGNED 0
98745     parameter \A_WIDTH 1
98746     parameter \B_SIGNED 0
98747     parameter \B_WIDTH 1
98748     parameter \Y_WIDTH 1
98749     connect \A $not$ls180.v:8036$2559_Y
98750     connect \B \main_uart_tx_old_trigger
98751     connect \Y $and$ls180.v:8036$2560_Y
98752   end
98753   attribute \src "ls180.v:8043.7-8043.57"
98754   cell $and $and$ls180.v:8043$2562
98755     parameter \A_SIGNED 0
98756     parameter \A_WIDTH 1
98757     parameter \B_SIGNED 0
98758     parameter \B_WIDTH 1
98759     parameter \Y_WIDTH 1
98760     connect \A $not$ls180.v:8043$2561_Y
98761     connect \B \main_uart_rx_old_trigger
98762     connect \Y $and$ls180.v:8043$2562_Y
98763   end
98764   attribute \src "ls180.v:8053.8-8053.75"
98765   cell $and $and$ls180.v:8053$2563
98766     parameter \A_SIGNED 0
98767     parameter \A_WIDTH 1
98768     parameter \B_SIGNED 0
98769     parameter \B_WIDTH 1
98770     parameter \Y_WIDTH 1
98771     connect \A \main_uart_tx_fifo_syncfifo_we
98772     connect \B \main_uart_tx_fifo_syncfifo_writable
98773     connect \Y $and$ls180.v:8053$2563_Y
98774   end
98775   attribute \src "ls180.v:8053.7-8053.107"
98776   cell $and $and$ls180.v:8053$2565
98777     parameter \A_SIGNED 0
98778     parameter \A_WIDTH 1
98779     parameter \B_SIGNED 0
98780     parameter \B_WIDTH 1
98781     parameter \Y_WIDTH 1
98782     connect \A $and$ls180.v:8053$2563_Y
98783     connect \B $not$ls180.v:8053$2564_Y
98784     connect \Y $and$ls180.v:8053$2565_Y
98785   end
98786   attribute \src "ls180.v:8059.8-8059.75"
98787   cell $and $and$ls180.v:8059$2568
98788     parameter \A_SIGNED 0
98789     parameter \A_WIDTH 1
98790     parameter \B_SIGNED 0
98791     parameter \B_WIDTH 1
98792     parameter \Y_WIDTH 1
98793     connect \A \main_uart_tx_fifo_syncfifo_we
98794     connect \B \main_uart_tx_fifo_syncfifo_writable
98795     connect \Y $and$ls180.v:8059$2568_Y
98796   end
98797   attribute \src "ls180.v:8059.7-8059.107"
98798   cell $and $and$ls180.v:8059$2570
98799     parameter \A_SIGNED 0
98800     parameter \A_WIDTH 1
98801     parameter \B_SIGNED 0
98802     parameter \B_WIDTH 1
98803     parameter \Y_WIDTH 1
98804     connect \A $and$ls180.v:8059$2568_Y
98805     connect \B $not$ls180.v:8059$2569_Y
98806     connect \Y $and$ls180.v:8059$2570_Y
98807   end
98808   attribute \src "ls180.v:8075.8-8075.75"
98809   cell $and $and$ls180.v:8075$2574
98810     parameter \A_SIGNED 0
98811     parameter \A_WIDTH 1
98812     parameter \B_SIGNED 0
98813     parameter \B_WIDTH 1
98814     parameter \Y_WIDTH 1
98815     connect \A \main_uart_rx_fifo_syncfifo_we
98816     connect \B \main_uart_rx_fifo_syncfifo_writable
98817     connect \Y $and$ls180.v:8075$2574_Y
98818   end
98819   attribute \src "ls180.v:8075.7-8075.107"
98820   cell $and $and$ls180.v:8075$2576
98821     parameter \A_SIGNED 0
98822     parameter \A_WIDTH 1
98823     parameter \B_SIGNED 0
98824     parameter \B_WIDTH 1
98825     parameter \Y_WIDTH 1
98826     connect \A $and$ls180.v:8075$2574_Y
98827     connect \B $not$ls180.v:8075$2575_Y
98828     connect \Y $and$ls180.v:8075$2576_Y
98829   end
98830   attribute \src "ls180.v:8081.8-8081.75"
98831   cell $and $and$ls180.v:8081$2579
98832     parameter \A_SIGNED 0
98833     parameter \A_WIDTH 1
98834     parameter \B_SIGNED 0
98835     parameter \B_WIDTH 1
98836     parameter \Y_WIDTH 1
98837     connect \A \main_uart_rx_fifo_syncfifo_we
98838     connect \B \main_uart_rx_fifo_syncfifo_writable
98839     connect \Y $and$ls180.v:8081$2579_Y
98840   end
98841   attribute \src "ls180.v:8081.7-8081.107"
98842   cell $and $and$ls180.v:8081$2581
98843     parameter \A_SIGNED 0
98844     parameter \A_WIDTH 1
98845     parameter \B_SIGNED 0
98846     parameter \B_WIDTH 1
98847     parameter \Y_WIDTH 1
98848     connect \A $and$ls180.v:8081$2579_Y
98849     connect \B $not$ls180.v:8081$2580_Y
98850     connect \Y $and$ls180.v:8081$2581_Y
98851   end
98852   attribute \src "ls180.v:8229.7-8229.96"
98853   cell $and $and$ls180.v:8229$2609
98854     parameter \A_SIGNED 0
98855     parameter \A_WIDTH 1
98856     parameter \B_SIGNED 0
98857     parameter \B_WIDTH 1
98858     parameter \Y_WIDTH 1
98859     connect \A \main_sdphy_cmdr_cmdr_converter_source_valid
98860     connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
98861     connect \Y $and$ls180.v:8229$2609_Y
98862   end
98863   attribute \src "ls180.v:8230.8-8230.93"
98864   cell $and $and$ls180.v:8230$2610
98865     parameter \A_SIGNED 0
98866     parameter \A_WIDTH 1
98867     parameter \B_SIGNED 0
98868     parameter \B_WIDTH 1
98869     parameter \Y_WIDTH 1
98870     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
98871     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
98872     connect \Y $and$ls180.v:8230$2610_Y
98873   end
98874   attribute \src "ls180.v:8238.8-8238.93"
98875   cell $and $and$ls180.v:8238$2611
98876     parameter \A_SIGNED 0
98877     parameter \A_WIDTH 1
98878     parameter \B_SIGNED 0
98879     parameter \B_WIDTH 1
98880     parameter \Y_WIDTH 1
98881     connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid
98882     connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready
98883     connect \Y $and$ls180.v:8238$2611_Y
98884   end
98885   attribute \src "ls180.v:8310.7-8310.98"
98886   cell $and $and$ls180.v:8310$2621
98887     parameter \A_SIGNED 0
98888     parameter \A_WIDTH 1
98889     parameter \B_SIGNED 0
98890     parameter \B_WIDTH 1
98891     parameter \Y_WIDTH 1
98892     connect \A \main_sdphy_dataw_crcr_converter_source_valid
98893     connect \B \main_sdphy_dataw_crcr_converter_source_ready
98894     connect \Y $and$ls180.v:8310$2621_Y
98895   end
98896   attribute \src "ls180.v:8311.8-8311.95"
98897   cell $and $and$ls180.v:8311$2622
98898     parameter \A_SIGNED 0
98899     parameter \A_WIDTH 1
98900     parameter \B_SIGNED 0
98901     parameter \B_WIDTH 1
98902     parameter \Y_WIDTH 1
98903     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
98904     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
98905     connect \Y $and$ls180.v:8311$2622_Y
98906   end
98907   attribute \src "ls180.v:8319.8-8319.95"
98908   cell $and $and$ls180.v:8319$2623
98909     parameter \A_SIGNED 0
98910     parameter \A_WIDTH 1
98911     parameter \B_SIGNED 0
98912     parameter \B_WIDTH 1
98913     parameter \Y_WIDTH 1
98914     connect \A \main_sdphy_dataw_crcr_converter_sink_valid
98915     connect \B \main_sdphy_dataw_crcr_converter_sink_ready
98916     connect \Y $and$ls180.v:8319$2623_Y
98917   end
98918   attribute \src "ls180.v:8389.7-8389.100"
98919   cell $and $and$ls180.v:8389$2633
98920     parameter \A_SIGNED 0
98921     parameter \A_WIDTH 1
98922     parameter \B_SIGNED 0
98923     parameter \B_WIDTH 1
98924     parameter \Y_WIDTH 1
98925     connect \A \main_sdphy_datar_datar_converter_source_valid
98926     connect \B \main_sdphy_datar_datar_converter_source_ready
98927     connect \Y $and$ls180.v:8389$2633_Y
98928   end
98929   attribute \src "ls180.v:8390.8-8390.97"
98930   cell $and $and$ls180.v:8390$2634
98931     parameter \A_SIGNED 0
98932     parameter \A_WIDTH 1
98933     parameter \B_SIGNED 0
98934     parameter \B_WIDTH 1
98935     parameter \Y_WIDTH 1
98936     connect \A \main_sdphy_datar_datar_converter_sink_valid
98937     connect \B \main_sdphy_datar_datar_converter_sink_ready
98938     connect \Y $and$ls180.v:8390$2634_Y
98939   end
98940   attribute \src "ls180.v:8398.8-8398.97"
98941   cell $and $and$ls180.v:8398$2635
98942     parameter \A_SIGNED 0
98943     parameter \A_WIDTH 1
98944     parameter \B_SIGNED 0
98945     parameter \B_WIDTH 1
98946     parameter \Y_WIDTH 1
98947     connect \A \main_sdphy_datar_datar_converter_sink_valid
98948     connect \B \main_sdphy_datar_datar_converter_sink_ready
98949     connect \Y $and$ls180.v:8398$2635_Y
98950   end
98951   attribute \src "ls180.v:8489.7-8489.82"
98952   cell $and $and$ls180.v:8489$2641
98953     parameter \A_SIGNED 0
98954     parameter \A_WIDTH 1
98955     parameter \B_SIGNED 0
98956     parameter \B_WIDTH 1
98957     parameter \Y_WIDTH 1
98958     connect \A \main_sdcore_crc16_checker_sink_ready
98959     connect \B \main_sdcore_crc16_checker_sink_valid
98960     connect \Y $and$ls180.v:8489$2641_Y
98961   end
98962   attribute \src "ls180.v:8492.7-8492.82"
98963   cell $and $and$ls180.v:8492$2642
98964     parameter \A_SIGNED 0
98965     parameter \A_WIDTH 1
98966     parameter \B_SIGNED 0
98967     parameter \B_WIDTH 1
98968     parameter \Y_WIDTH 1
98969     connect \A \main_sdcore_crc16_checker_sink_ready
98970     connect \B \main_sdcore_crc16_checker_sink_valid
98971     connect \Y $and$ls180.v:8492$2642_Y
98972   end
98973   attribute \src "ls180.v:8495.7-8495.82"
98974   cell $and $and$ls180.v:8495$2643
98975     parameter \A_SIGNED 0
98976     parameter \A_WIDTH 1
98977     parameter \B_SIGNED 0
98978     parameter \B_WIDTH 1
98979     parameter \Y_WIDTH 1
98980     connect \A \main_sdcore_crc16_checker_sink_ready
98981     connect \B \main_sdcore_crc16_checker_sink_valid
98982     connect \Y $and$ls180.v:8495$2643_Y
98983   end
98984   attribute \src "ls180.v:8498.7-8498.82"
98985   cell $and $and$ls180.v:8498$2644
98986     parameter \A_SIGNED 0
98987     parameter \A_WIDTH 1
98988     parameter \B_SIGNED 0
98989     parameter \B_WIDTH 1
98990     parameter \Y_WIDTH 1
98991     connect \A \main_sdcore_crc16_checker_sink_ready
98992     connect \B \main_sdcore_crc16_checker_sink_valid
98993     connect \Y $and$ls180.v:8498$2644_Y
98994   end
98995   attribute \src "ls180.v:8501.7-8501.82"
98996   cell $and $and$ls180.v:8501$2645
98997     parameter \A_SIGNED 0
98998     parameter \A_WIDTH 1
98999     parameter \B_SIGNED 0
99000     parameter \B_WIDTH 1
99001     parameter \Y_WIDTH 1
99002     connect \A \main_sdcore_crc16_checker_sink_valid
99003     connect \B \main_sdcore_crc16_checker_sink_ready
99004     connect \Y $and$ls180.v:8501$2645_Y
99005   end
99006   attribute \src "ls180.v:8506.7-8506.82"
99007   cell $and $and$ls180.v:8506$2646
99008     parameter \A_SIGNED 0
99009     parameter \A_WIDTH 1
99010     parameter \B_SIGNED 0
99011     parameter \B_WIDTH 1
99012     parameter \Y_WIDTH 1
99013     connect \A \main_sdcore_crc16_checker_sink_valid
99014     connect \B \main_sdcore_crc16_checker_sink_ready
99015     connect \Y $and$ls180.v:8506$2646_Y
99016   end
99017   attribute \src "ls180.v:8511.7-8511.82"
99018   cell $and $and$ls180.v:8511$2647
99019     parameter \A_SIGNED 0
99020     parameter \A_WIDTH 1
99021     parameter \B_SIGNED 0
99022     parameter \B_WIDTH 1
99023     parameter \Y_WIDTH 1
99024     connect \A \main_sdcore_crc16_checker_sink_valid
99025     connect \B \main_sdcore_crc16_checker_sink_ready
99026     connect \Y $and$ls180.v:8511$2647_Y
99027   end
99028   attribute \src "ls180.v:8516.7-8516.82"
99029   cell $and $and$ls180.v:8516$2648
99030     parameter \A_SIGNED 0
99031     parameter \A_WIDTH 1
99032     parameter \B_SIGNED 0
99033     parameter \B_WIDTH 1
99034     parameter \Y_WIDTH 1
99035     connect \A \main_sdcore_crc16_checker_sink_valid
99036     connect \B \main_sdcore_crc16_checker_sink_ready
99037     connect \Y $and$ls180.v:8516$2648_Y
99038   end
99039   attribute \src "ls180.v:8521.7-8521.82"
99040   cell $and $and$ls180.v:8521$2649
99041     parameter \A_SIGNED 0
99042     parameter \A_WIDTH 1
99043     parameter \B_SIGNED 0
99044     parameter \B_WIDTH 1
99045     parameter \Y_WIDTH 1
99046     connect \A \main_sdcore_crc16_checker_sink_valid
99047     connect \B \main_sdcore_crc16_checker_sink_ready
99048     connect \Y $and$ls180.v:8521$2649_Y
99049   end
99050   attribute \src "ls180.v:8586.8-8586.83"
99051   cell $and $and$ls180.v:8586$2652
99052     parameter \A_SIGNED 0
99053     parameter \A_WIDTH 1
99054     parameter \B_SIGNED 0
99055     parameter \B_WIDTH 1
99056     parameter \Y_WIDTH 1
99057     connect \A \main_sdblock2mem_fifo_syncfifo_we
99058     connect \B \main_sdblock2mem_fifo_syncfifo_writable
99059     connect \Y $and$ls180.v:8586$2652_Y
99060   end
99061   attribute \src "ls180.v:8586.7-8586.119"
99062   cell $and $and$ls180.v:8586$2654
99063     parameter \A_SIGNED 0
99064     parameter \A_WIDTH 1
99065     parameter \B_SIGNED 0
99066     parameter \B_WIDTH 1
99067     parameter \Y_WIDTH 1
99068     connect \A $and$ls180.v:8586$2652_Y
99069     connect \B $not$ls180.v:8586$2653_Y
99070     connect \Y $and$ls180.v:8586$2654_Y
99071   end
99072   attribute \src "ls180.v:8592.8-8592.83"
99073   cell $and $and$ls180.v:8592$2657
99074     parameter \A_SIGNED 0
99075     parameter \A_WIDTH 1
99076     parameter \B_SIGNED 0
99077     parameter \B_WIDTH 1
99078     parameter \Y_WIDTH 1
99079     connect \A \main_sdblock2mem_fifo_syncfifo_we
99080     connect \B \main_sdblock2mem_fifo_syncfifo_writable
99081     connect \Y $and$ls180.v:8592$2657_Y
99082   end
99083   attribute \src "ls180.v:8592.7-8592.119"
99084   cell $and $and$ls180.v:8592$2659
99085     parameter \A_SIGNED 0
99086     parameter \A_WIDTH 1
99087     parameter \B_SIGNED 0
99088     parameter \B_WIDTH 1
99089     parameter \Y_WIDTH 1
99090     connect \A $and$ls180.v:8592$2657_Y
99091     connect \B $not$ls180.v:8592$2658_Y
99092     connect \Y $and$ls180.v:8592$2659_Y
99093   end
99094   attribute \src "ls180.v:8612.7-8612.88"
99095   cell $and $and$ls180.v:8612$2666
99096     parameter \A_SIGNED 0
99097     parameter \A_WIDTH 1
99098     parameter \B_SIGNED 0
99099     parameter \B_WIDTH 1
99100     parameter \Y_WIDTH 1
99101     connect \A \main_sdblock2mem_converter_source_valid
99102     connect \B \main_sdblock2mem_converter_source_ready
99103     connect \Y $and$ls180.v:8612$2666_Y
99104   end
99105   attribute \src "ls180.v:8613.8-8613.85"
99106   cell $and $and$ls180.v:8613$2667
99107     parameter \A_SIGNED 0
99108     parameter \A_WIDTH 1
99109     parameter \B_SIGNED 0
99110     parameter \B_WIDTH 1
99111     parameter \Y_WIDTH 1
99112     connect \A \main_sdblock2mem_converter_sink_valid
99113     connect \B \main_sdblock2mem_converter_sink_ready
99114     connect \Y $and$ls180.v:8613$2667_Y
99115   end
99116   attribute \src "ls180.v:8621.8-8621.85"
99117   cell $and $and$ls180.v:8621$2668
99118     parameter \A_SIGNED 0
99119     parameter \A_WIDTH 1
99120     parameter \B_SIGNED 0
99121     parameter \B_WIDTH 1
99122     parameter \Y_WIDTH 1
99123     connect \A \main_sdblock2mem_converter_sink_valid
99124     connect \B \main_sdblock2mem_converter_sink_ready
99125     connect \Y $and$ls180.v:8621$2668_Y
99126   end
99127   attribute \src "ls180.v:8665.7-8665.88"
99128   cell $and $and$ls180.v:8665$2672
99129     parameter \A_SIGNED 0
99130     parameter \A_WIDTH 1
99131     parameter \B_SIGNED 0
99132     parameter \B_WIDTH 1
99133     parameter \Y_WIDTH 1
99134     connect \A \main_sdmem2block_converter_source_valid
99135     connect \B \main_sdmem2block_converter_source_ready
99136     connect \Y $and$ls180.v:8665$2672_Y
99137   end
99138   attribute \src "ls180.v:8672.8-8672.83"
99139   cell $and $and$ls180.v:8672$2674
99140     parameter \A_SIGNED 0
99141     parameter \A_WIDTH 1
99142     parameter \B_SIGNED 0
99143     parameter \B_WIDTH 1
99144     parameter \Y_WIDTH 1
99145     connect \A \main_sdmem2block_fifo_syncfifo_we
99146     connect \B \main_sdmem2block_fifo_syncfifo_writable
99147     connect \Y $and$ls180.v:8672$2674_Y
99148   end
99149   attribute \src "ls180.v:8672.7-8672.119"
99150   cell $and $and$ls180.v:8672$2676
99151     parameter \A_SIGNED 0
99152     parameter \A_WIDTH 1
99153     parameter \B_SIGNED 0
99154     parameter \B_WIDTH 1
99155     parameter \Y_WIDTH 1
99156     connect \A $and$ls180.v:8672$2674_Y
99157     connect \B $not$ls180.v:8672$2675_Y
99158     connect \Y $and$ls180.v:8672$2676_Y
99159   end
99160   attribute \src "ls180.v:8678.8-8678.83"
99161   cell $and $and$ls180.v:8678$2679
99162     parameter \A_SIGNED 0
99163     parameter \A_WIDTH 1
99164     parameter \B_SIGNED 0
99165     parameter \B_WIDTH 1
99166     parameter \Y_WIDTH 1
99167     connect \A \main_sdmem2block_fifo_syncfifo_we
99168     connect \B \main_sdmem2block_fifo_syncfifo_writable
99169     connect \Y $and$ls180.v:8678$2679_Y
99170   end
99171   attribute \src "ls180.v:8678.7-8678.119"
99172   cell $and $and$ls180.v:8678$2681
99173     parameter \A_SIGNED 0
99174     parameter \A_WIDTH 1
99175     parameter \B_SIGNED 0
99176     parameter \B_WIDTH 1
99177     parameter \Y_WIDTH 1
99178     connect \A $and$ls180.v:8678$2679_Y
99179     connect \B $not$ls180.v:8678$2680_Y
99180     connect \Y $and$ls180.v:8678$2681_Y
99181   end
99182   attribute \src "ls180.v:2814.42-2814.101"
99183   cell $eq $eq$ls180.v:2814$18
99184     parameter \A_SIGNED 0
99185     parameter \A_WIDTH 4
99186     parameter \B_SIGNED 0
99187     parameter \B_WIDTH 1
99188     parameter \Y_WIDTH 1
99189     connect \A \main_libresocsim_interface0_converted_interface_sel
99190     connect \B 1'0
99191     connect \Y $eq$ls180.v:2814$18_Y
99192   end
99193   attribute \src "ls180.v:2821.11-2821.54"
99194   cell $eq $eq$ls180.v:2821$23
99195     parameter \A_SIGNED 0
99196     parameter \A_WIDTH 1
99197     parameter \B_SIGNED 0
99198     parameter \B_WIDTH 1
99199     parameter \Y_WIDTH 1
99200     connect \A \main_libresocsim_converter0_counter
99201     connect \B 1'1
99202     connect \Y $eq$ls180.v:2821$23_Y
99203   end
99204   attribute \src "ls180.v:2874.42-2874.101"
99205   cell $eq $eq$ls180.v:2874$29
99206     parameter \A_SIGNED 0
99207     parameter \A_WIDTH 4
99208     parameter \B_SIGNED 0
99209     parameter \B_WIDTH 1
99210     parameter \Y_WIDTH 1
99211     connect \A \main_libresocsim_interface1_converted_interface_sel
99212     connect \B 1'0
99213     connect \Y $eq$ls180.v:2874$29_Y
99214   end
99215   attribute \src "ls180.v:2881.11-2881.54"
99216   cell $eq $eq$ls180.v:2881$34
99217     parameter \A_SIGNED 0
99218     parameter \A_WIDTH 1
99219     parameter \B_SIGNED 0
99220     parameter \B_WIDTH 1
99221     parameter \Y_WIDTH 1
99222     connect \A \main_libresocsim_converter1_counter
99223     connect \B 1'1
99224     connect \Y $eq$ls180.v:2881$34_Y
99225   end
99226   attribute \src "ls180.v:2934.42-2934.101"
99227   cell $eq $eq$ls180.v:2934$40
99228     parameter \A_SIGNED 0
99229     parameter \A_WIDTH 4
99230     parameter \B_SIGNED 0
99231     parameter \B_WIDTH 1
99232     parameter \Y_WIDTH 1
99233     connect \A \main_libresocsim_interface2_converted_interface_sel
99234     connect \B 1'0
99235     connect \Y $eq$ls180.v:2934$40_Y
99236   end
99237   attribute \src "ls180.v:2941.11-2941.54"
99238   cell $eq $eq$ls180.v:2941$45
99239     parameter \A_SIGNED 0
99240     parameter \A_WIDTH 1
99241     parameter \B_SIGNED 0
99242     parameter \B_WIDTH 1
99243     parameter \Y_WIDTH 1
99244     connect \A \main_libresocsim_converter2_counter
99245     connect \B 1'1
99246     connect \Y $eq$ls180.v:2941$45_Y
99247   end
99248   attribute \src "ls180.v:3127.34-3127.65"
99249   cell $eq $eq$ls180.v:3127$73
99250     parameter \A_SIGNED 0
99251     parameter \A_WIDTH 10
99252     parameter \B_SIGNED 0
99253     parameter \B_WIDTH 1
99254     parameter \Y_WIDTH 1
99255     connect \A \main_sdram_timer_count1
99256     connect \B 1'0
99257     connect \Y $eq$ls180.v:3127$73_Y
99258   end
99259   attribute \src "ls180.v:3131.68-3131.102"
99260   cell $eq $eq$ls180.v:3131$76
99261     parameter \A_SIGNED 0
99262     parameter \A_WIDTH 1
99263     parameter \B_SIGNED 0
99264     parameter \B_WIDTH 1
99265     parameter \Y_WIDTH 1
99266     connect \A \main_sdram_sequencer_count
99267     connect \B 1'0
99268     connect \Y $eq$ls180.v:3131$76_Y
99269   end
99270   attribute \src "ls180.v:3175.43-3175.134"
99271   cell $eq $eq$ls180.v:3175$81
99272     parameter \A_SIGNED 0
99273     parameter \A_WIDTH 13
99274     parameter \B_SIGNED 0
99275     parameter \B_WIDTH 13
99276     parameter \Y_WIDTH 1
99277     connect \A \main_sdram_bankmachine0_row
99278     connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
99279     connect \Y $eq$ls180.v:3175$81_Y
99280   end
99281   attribute \src "ls180.v:3192.47-3192.88"
99282   cell $eq $eq$ls180.v:3192$94
99283     parameter \A_SIGNED 0
99284     parameter \A_WIDTH 1
99285     parameter \B_SIGNED 0
99286     parameter \B_WIDTH 1
99287     parameter \Y_WIDTH 1
99288     connect \A \main_sdram_bankmachine0_row_close
99289     connect \B 1'0
99290     connect \Y $eq$ls180.v:3192$94_Y
99291   end
99292   attribute \src "ls180.v:3332.43-3332.134"
99293   cell $eq $eq$ls180.v:3332$111
99294     parameter \A_SIGNED 0
99295     parameter \A_WIDTH 13
99296     parameter \B_SIGNED 0
99297     parameter \B_WIDTH 13
99298     parameter \Y_WIDTH 1
99299     connect \A \main_sdram_bankmachine1_row
99300     connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
99301     connect \Y $eq$ls180.v:3332$111_Y
99302   end
99303   attribute \src "ls180.v:3349.47-3349.88"
99304   cell $eq $eq$ls180.v:3349$124
99305     parameter \A_SIGNED 0
99306     parameter \A_WIDTH 1
99307     parameter \B_SIGNED 0
99308     parameter \B_WIDTH 1
99309     parameter \Y_WIDTH 1
99310     connect \A \main_sdram_bankmachine1_row_close
99311     connect \B 1'0
99312     connect \Y $eq$ls180.v:3349$124_Y
99313   end
99314   attribute \src "ls180.v:3489.43-3489.134"
99315   cell $eq $eq$ls180.v:3489$141
99316     parameter \A_SIGNED 0
99317     parameter \A_WIDTH 13
99318     parameter \B_SIGNED 0
99319     parameter \B_WIDTH 13
99320     parameter \Y_WIDTH 1
99321     connect \A \main_sdram_bankmachine2_row
99322     connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
99323     connect \Y $eq$ls180.v:3489$141_Y
99324   end
99325   attribute \src "ls180.v:3506.47-3506.88"
99326   cell $eq $eq$ls180.v:3506$154
99327     parameter \A_SIGNED 0
99328     parameter \A_WIDTH 1
99329     parameter \B_SIGNED 0
99330     parameter \B_WIDTH 1
99331     parameter \Y_WIDTH 1
99332     connect \A \main_sdram_bankmachine2_row_close
99333     connect \B 1'0
99334     connect \Y $eq$ls180.v:3506$154_Y
99335   end
99336   attribute \src "ls180.v:3646.43-3646.134"
99337   cell $eq $eq$ls180.v:3646$171
99338     parameter \A_SIGNED 0
99339     parameter \A_WIDTH 13
99340     parameter \B_SIGNED 0
99341     parameter \B_WIDTH 13
99342     parameter \Y_WIDTH 1
99343     connect \A \main_sdram_bankmachine3_row
99344     connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
99345     connect \Y $eq$ls180.v:3646$171_Y
99346   end
99347   attribute \src "ls180.v:3663.47-3663.88"
99348   cell $eq $eq$ls180.v:3663$184
99349     parameter \A_SIGNED 0
99350     parameter \A_WIDTH 1
99351     parameter \B_SIGNED 0
99352     parameter \B_WIDTH 1
99353     parameter \Y_WIDTH 1
99354     connect \A \main_sdram_bankmachine3_row_close
99355     connect \B 1'0
99356     connect \Y $eq$ls180.v:3663$184_Y
99357   end
99358   attribute \src "ls180.v:3800.32-3800.56"
99359   cell $eq $eq$ls180.v:3800$231
99360     parameter \A_SIGNED 0
99361     parameter \A_WIDTH 5
99362     parameter \B_SIGNED 0
99363     parameter \B_WIDTH 1
99364     parameter \Y_WIDTH 1
99365     connect \A \main_sdram_time0
99366     connect \B 1'0
99367     connect \Y $eq$ls180.v:3800$231_Y
99368   end
99369   attribute \src "ls180.v:3801.32-3801.56"
99370   cell $eq $eq$ls180.v:3801$232
99371     parameter \A_SIGNED 0
99372     parameter \A_WIDTH 4
99373     parameter \B_SIGNED 0
99374     parameter \B_WIDTH 1
99375     parameter \Y_WIDTH 1
99376     connect \A \main_sdram_time1
99377     connect \B 1'0
99378     connect \Y $eq$ls180.v:3801$232_Y
99379   end
99380   attribute \src "ls180.v:3812.339-3812.418"
99381   cell $eq $eq$ls180.v:3812$246
99382     parameter \A_SIGNED 0
99383     parameter \A_WIDTH 1
99384     parameter \B_SIGNED 0
99385     parameter \B_WIDTH 1
99386     parameter \Y_WIDTH 1
99387     connect \A \main_sdram_bankmachine0_cmd_payload_is_read
99388     connect \B \main_sdram_choose_cmd_want_reads
99389     connect \Y $eq$ls180.v:3812$246_Y
99390   end
99391   attribute \src "ls180.v:3812.423-3812.504"
99392   cell $eq $eq$ls180.v:3812$247
99393     parameter \A_SIGNED 0
99394     parameter \A_WIDTH 1
99395     parameter \B_SIGNED 0
99396     parameter \B_WIDTH 1
99397     parameter \Y_WIDTH 1
99398     connect \A \main_sdram_bankmachine0_cmd_payload_is_write
99399     connect \B \main_sdram_choose_cmd_want_writes
99400     connect \Y $eq$ls180.v:3812$247_Y
99401   end
99402   attribute \src "ls180.v:3813.339-3813.418"
99403   cell $eq $eq$ls180.v:3813$259
99404     parameter \A_SIGNED 0
99405     parameter \A_WIDTH 1
99406     parameter \B_SIGNED 0
99407     parameter \B_WIDTH 1
99408     parameter \Y_WIDTH 1
99409     connect \A \main_sdram_bankmachine1_cmd_payload_is_read
99410     connect \B \main_sdram_choose_cmd_want_reads
99411     connect \Y $eq$ls180.v:3813$259_Y
99412   end
99413   attribute \src "ls180.v:3813.423-3813.504"
99414   cell $eq $eq$ls180.v:3813$260
99415     parameter \A_SIGNED 0
99416     parameter \A_WIDTH 1
99417     parameter \B_SIGNED 0
99418     parameter \B_WIDTH 1
99419     parameter \Y_WIDTH 1
99420     connect \A \main_sdram_bankmachine1_cmd_payload_is_write
99421     connect \B \main_sdram_choose_cmd_want_writes
99422     connect \Y $eq$ls180.v:3813$260_Y
99423   end
99424   attribute \src "ls180.v:3814.339-3814.418"
99425   cell $eq $eq$ls180.v:3814$272
99426     parameter \A_SIGNED 0
99427     parameter \A_WIDTH 1
99428     parameter \B_SIGNED 0
99429     parameter \B_WIDTH 1
99430     parameter \Y_WIDTH 1
99431     connect \A \main_sdram_bankmachine2_cmd_payload_is_read
99432     connect \B \main_sdram_choose_cmd_want_reads
99433     connect \Y $eq$ls180.v:3814$272_Y
99434   end
99435   attribute \src "ls180.v:3814.423-3814.504"
99436   cell $eq $eq$ls180.v:3814$273
99437     parameter \A_SIGNED 0
99438     parameter \A_WIDTH 1
99439     parameter \B_SIGNED 0
99440     parameter \B_WIDTH 1
99441     parameter \Y_WIDTH 1
99442     connect \A \main_sdram_bankmachine2_cmd_payload_is_write
99443     connect \B \main_sdram_choose_cmd_want_writes
99444     connect \Y $eq$ls180.v:3814$273_Y
99445   end
99446   attribute \src "ls180.v:3815.339-3815.418"
99447   cell $eq $eq$ls180.v:3815$285
99448     parameter \A_SIGNED 0
99449     parameter \A_WIDTH 1
99450     parameter \B_SIGNED 0
99451     parameter \B_WIDTH 1
99452     parameter \Y_WIDTH 1
99453     connect \A \main_sdram_bankmachine3_cmd_payload_is_read
99454     connect \B \main_sdram_choose_cmd_want_reads
99455     connect \Y $eq$ls180.v:3815$285_Y
99456   end
99457   attribute \src "ls180.v:3815.423-3815.504"
99458   cell $eq $eq$ls180.v:3815$286
99459     parameter \A_SIGNED 0
99460     parameter \A_WIDTH 1
99461     parameter \B_SIGNED 0
99462     parameter \B_WIDTH 1
99463     parameter \Y_WIDTH 1
99464     connect \A \main_sdram_bankmachine3_cmd_payload_is_write
99465     connect \B \main_sdram_choose_cmd_want_writes
99466     connect \Y $eq$ls180.v:3815$286_Y
99467   end
99468   attribute \src "ls180.v:3845.339-3845.418"
99469   cell $eq $eq$ls180.v:3845$304
99470     parameter \A_SIGNED 0
99471     parameter \A_WIDTH 1
99472     parameter \B_SIGNED 0
99473     parameter \B_WIDTH 1
99474     parameter \Y_WIDTH 1
99475     connect \A \main_sdram_bankmachine0_cmd_payload_is_read
99476     connect \B \main_sdram_choose_req_want_reads
99477     connect \Y $eq$ls180.v:3845$304_Y
99478   end
99479   attribute \src "ls180.v:3845.423-3845.504"
99480   cell $eq $eq$ls180.v:3845$305
99481     parameter \A_SIGNED 0
99482     parameter \A_WIDTH 1
99483     parameter \B_SIGNED 0
99484     parameter \B_WIDTH 1
99485     parameter \Y_WIDTH 1
99486     connect \A \main_sdram_bankmachine0_cmd_payload_is_write
99487     connect \B \main_sdram_choose_req_want_writes
99488     connect \Y $eq$ls180.v:3845$305_Y
99489   end
99490   attribute \src "ls180.v:3846.339-3846.418"
99491   cell $eq $eq$ls180.v:3846$317
99492     parameter \A_SIGNED 0
99493     parameter \A_WIDTH 1
99494     parameter \B_SIGNED 0
99495     parameter \B_WIDTH 1
99496     parameter \Y_WIDTH 1
99497     connect \A \main_sdram_bankmachine1_cmd_payload_is_read
99498     connect \B \main_sdram_choose_req_want_reads
99499     connect \Y $eq$ls180.v:3846$317_Y
99500   end
99501   attribute \src "ls180.v:3846.423-3846.504"
99502   cell $eq $eq$ls180.v:3846$318
99503     parameter \A_SIGNED 0
99504     parameter \A_WIDTH 1
99505     parameter \B_SIGNED 0
99506     parameter \B_WIDTH 1
99507     parameter \Y_WIDTH 1
99508     connect \A \main_sdram_bankmachine1_cmd_payload_is_write
99509     connect \B \main_sdram_choose_req_want_writes
99510     connect \Y $eq$ls180.v:3846$318_Y
99511   end
99512   attribute \src "ls180.v:3847.339-3847.418"
99513   cell $eq $eq$ls180.v:3847$330
99514     parameter \A_SIGNED 0
99515     parameter \A_WIDTH 1
99516     parameter \B_SIGNED 0
99517     parameter \B_WIDTH 1
99518     parameter \Y_WIDTH 1
99519     connect \A \main_sdram_bankmachine2_cmd_payload_is_read
99520     connect \B \main_sdram_choose_req_want_reads
99521     connect \Y $eq$ls180.v:3847$330_Y
99522   end
99523   attribute \src "ls180.v:3847.423-3847.504"
99524   cell $eq $eq$ls180.v:3847$331
99525     parameter \A_SIGNED 0
99526     parameter \A_WIDTH 1
99527     parameter \B_SIGNED 0
99528     parameter \B_WIDTH 1
99529     parameter \Y_WIDTH 1
99530     connect \A \main_sdram_bankmachine2_cmd_payload_is_write
99531     connect \B \main_sdram_choose_req_want_writes
99532     connect \Y $eq$ls180.v:3847$331_Y
99533   end
99534   attribute \src "ls180.v:3848.339-3848.418"
99535   cell $eq $eq$ls180.v:3848$343
99536     parameter \A_SIGNED 0
99537     parameter \A_WIDTH 1
99538     parameter \B_SIGNED 0
99539     parameter \B_WIDTH 1
99540     parameter \Y_WIDTH 1
99541     connect \A \main_sdram_bankmachine3_cmd_payload_is_read
99542     connect \B \main_sdram_choose_req_want_reads
99543     connect \Y $eq$ls180.v:3848$343_Y
99544   end
99545   attribute \src "ls180.v:3848.423-3848.504"
99546   cell $eq $eq$ls180.v:3848$344
99547     parameter \A_SIGNED 0
99548     parameter \A_WIDTH 1
99549     parameter \B_SIGNED 0
99550     parameter \B_WIDTH 1
99551     parameter \Y_WIDTH 1
99552     connect \A \main_sdram_bankmachine3_cmd_payload_is_write
99553     connect \B \main_sdram_choose_req_want_writes
99554     connect \Y $eq$ls180.v:3848$344_Y
99555   end
99556   attribute \src "ls180.v:3877.78-3877.113"
99557   cell $eq $eq$ls180.v:3877$353
99558     parameter \A_SIGNED 0
99559     parameter \A_WIDTH 2
99560     parameter \B_SIGNED 0
99561     parameter \B_WIDTH 1
99562     parameter \Y_WIDTH 1
99563     connect \A \main_sdram_choose_cmd_grant
99564     connect \B 1'0
99565     connect \Y $eq$ls180.v:3877$353_Y
99566   end
99567   attribute \src "ls180.v:3880.78-3880.113"
99568   cell $eq $eq$ls180.v:3880$356
99569     parameter \A_SIGNED 0
99570     parameter \A_WIDTH 2
99571     parameter \B_SIGNED 0
99572     parameter \B_WIDTH 1
99573     parameter \Y_WIDTH 1
99574     connect \A \main_sdram_choose_req_grant
99575     connect \B 1'0
99576     connect \Y $eq$ls180.v:3880$356_Y
99577   end
99578   attribute \src "ls180.v:3886.78-3886.113"
99579   cell $eq $eq$ls180.v:3886$360
99580     parameter \A_SIGNED 0
99581     parameter \A_WIDTH 2
99582     parameter \B_SIGNED 0
99583     parameter \B_WIDTH 1
99584     parameter \Y_WIDTH 1
99585     connect \A \main_sdram_choose_cmd_grant
99586     connect \B 1'1
99587     connect \Y $eq$ls180.v:3886$360_Y
99588   end
99589   attribute \src "ls180.v:3889.78-3889.113"
99590   cell $eq $eq$ls180.v:3889$363
99591     parameter \A_SIGNED 0
99592     parameter \A_WIDTH 2
99593     parameter \B_SIGNED 0
99594     parameter \B_WIDTH 1
99595     parameter \Y_WIDTH 1
99596     connect \A \main_sdram_choose_req_grant
99597     connect \B 1'1
99598     connect \Y $eq$ls180.v:3889$363_Y
99599   end
99600   attribute \src "ls180.v:3895.78-3895.113"
99601   cell $eq $eq$ls180.v:3895$367
99602     parameter \A_SIGNED 0
99603     parameter \A_WIDTH 2
99604     parameter \B_SIGNED 0
99605     parameter \B_WIDTH 2
99606     parameter \Y_WIDTH 1
99607     connect \A \main_sdram_choose_cmd_grant
99608     connect \B 2'10
99609     connect \Y $eq$ls180.v:3895$367_Y
99610   end
99611   attribute \src "ls180.v:3898.78-3898.113"
99612   cell $eq $eq$ls180.v:3898$370
99613     parameter \A_SIGNED 0
99614     parameter \A_WIDTH 2
99615     parameter \B_SIGNED 0
99616     parameter \B_WIDTH 2
99617     parameter \Y_WIDTH 1
99618     connect \A \main_sdram_choose_req_grant
99619     connect \B 2'10
99620     connect \Y $eq$ls180.v:3898$370_Y
99621   end
99622   attribute \src "ls180.v:3904.78-3904.113"
99623   cell $eq $eq$ls180.v:3904$374
99624     parameter \A_SIGNED 0
99625     parameter \A_WIDTH 2
99626     parameter \B_SIGNED 0
99627     parameter \B_WIDTH 2
99628     parameter \Y_WIDTH 1
99629     connect \A \main_sdram_choose_cmd_grant
99630     connect \B 2'11
99631     connect \Y $eq$ls180.v:3904$374_Y
99632   end
99633   attribute \src "ls180.v:3907.78-3907.113"
99634   cell $eq $eq$ls180.v:3907$377
99635     parameter \A_SIGNED 0
99636     parameter \A_WIDTH 2
99637     parameter \B_SIGNED 0
99638     parameter \B_WIDTH 2
99639     parameter \Y_WIDTH 1
99640     connect \A \main_sdram_choose_req_grant
99641     connect \B 2'11
99642     connect \Y $eq$ls180.v:3907$377_Y
99643   end
99644   attribute \src "ls180.v:3988.42-3988.82"
99645   cell $eq $eq$ls180.v:3988$400
99646     parameter \A_SIGNED 0
99647     parameter \A_WIDTH 2
99648     parameter \B_SIGNED 0
99649     parameter \B_WIDTH 1
99650     parameter \Y_WIDTH 1
99651     connect \A \main_port_cmd_payload_addr [10:9]
99652     connect \B 1'0
99653     connect \Y $eq$ls180.v:3988$400_Y
99654   end
99655   attribute \src "ls180.v:3988.145-3988.178"
99656   cell $eq $eq$ls180.v:3988$401
99657     parameter \A_SIGNED 0
99658     parameter \A_WIDTH 1
99659     parameter \B_SIGNED 0
99660     parameter \B_WIDTH 1
99661     parameter \Y_WIDTH 1
99662     connect \A \builder_roundrobin1_grant
99663     connect \B 1'0
99664     connect \Y $eq$ls180.v:3988$401_Y
99665   end
99666   attribute \src "ls180.v:3988.220-3988.253"
99667   cell $eq $eq$ls180.v:3988$404
99668     parameter \A_SIGNED 0
99669     parameter \A_WIDTH 1
99670     parameter \B_SIGNED 0
99671     parameter \B_WIDTH 1
99672     parameter \Y_WIDTH 1
99673     connect \A \builder_roundrobin2_grant
99674     connect \B 1'0
99675     connect \Y $eq$ls180.v:3988$404_Y
99676   end
99677   attribute \src "ls180.v:3988.295-3988.328"
99678   cell $eq $eq$ls180.v:3988$407
99679     parameter \A_SIGNED 0
99680     parameter \A_WIDTH 1
99681     parameter \B_SIGNED 0
99682     parameter \B_WIDTH 1
99683     parameter \Y_WIDTH 1
99684     connect \A \builder_roundrobin3_grant
99685     connect \B 1'0
99686     connect \Y $eq$ls180.v:3988$407_Y
99687   end
99688   attribute \src "ls180.v:3993.42-3993.82"
99689   cell $eq $eq$ls180.v:3993$416
99690     parameter \A_SIGNED 0
99691     parameter \A_WIDTH 2
99692     parameter \B_SIGNED 0
99693     parameter \B_WIDTH 1
99694     parameter \Y_WIDTH 1
99695     connect \A \main_port_cmd_payload_addr [10:9]
99696     connect \B 1'1
99697     connect \Y $eq$ls180.v:3993$416_Y
99698   end
99699   attribute \src "ls180.v:3993.145-3993.178"
99700   cell $eq $eq$ls180.v:3993$417
99701     parameter \A_SIGNED 0
99702     parameter \A_WIDTH 1
99703     parameter \B_SIGNED 0
99704     parameter \B_WIDTH 1
99705     parameter \Y_WIDTH 1
99706     connect \A \builder_roundrobin0_grant
99707     connect \B 1'0
99708     connect \Y $eq$ls180.v:3993$417_Y
99709   end
99710   attribute \src "ls180.v:3993.220-3993.253"
99711   cell $eq $eq$ls180.v:3993$420
99712     parameter \A_SIGNED 0
99713     parameter \A_WIDTH 1
99714     parameter \B_SIGNED 0
99715     parameter \B_WIDTH 1
99716     parameter \Y_WIDTH 1
99717     connect \A \builder_roundrobin2_grant
99718     connect \B 1'0
99719     connect \Y $eq$ls180.v:3993$420_Y
99720   end
99721   attribute \src "ls180.v:3993.295-3993.328"
99722   cell $eq $eq$ls180.v:3993$423
99723     parameter \A_SIGNED 0
99724     parameter \A_WIDTH 1
99725     parameter \B_SIGNED 0
99726     parameter \B_WIDTH 1
99727     parameter \Y_WIDTH 1
99728     connect \A \builder_roundrobin3_grant
99729     connect \B 1'0
99730     connect \Y $eq$ls180.v:3993$423_Y
99731   end
99732   attribute \src "ls180.v:3998.42-3998.82"
99733   cell $eq $eq$ls180.v:3998$432
99734     parameter \A_SIGNED 0
99735     parameter \A_WIDTH 2
99736     parameter \B_SIGNED 0
99737     parameter \B_WIDTH 2
99738     parameter \Y_WIDTH 1
99739     connect \A \main_port_cmd_payload_addr [10:9]
99740     connect \B 2'10
99741     connect \Y $eq$ls180.v:3998$432_Y
99742   end
99743   attribute \src "ls180.v:3998.145-3998.178"
99744   cell $eq $eq$ls180.v:3998$433
99745     parameter \A_SIGNED 0
99746     parameter \A_WIDTH 1
99747     parameter \B_SIGNED 0
99748     parameter \B_WIDTH 1
99749     parameter \Y_WIDTH 1
99750     connect \A \builder_roundrobin0_grant
99751     connect \B 1'0
99752     connect \Y $eq$ls180.v:3998$433_Y
99753   end
99754   attribute \src "ls180.v:3998.220-3998.253"
99755   cell $eq $eq$ls180.v:3998$436
99756     parameter \A_SIGNED 0
99757     parameter \A_WIDTH 1
99758     parameter \B_SIGNED 0
99759     parameter \B_WIDTH 1
99760     parameter \Y_WIDTH 1
99761     connect \A \builder_roundrobin1_grant
99762     connect \B 1'0
99763     connect \Y $eq$ls180.v:3998$436_Y
99764   end
99765   attribute \src "ls180.v:3998.295-3998.328"
99766   cell $eq $eq$ls180.v:3998$439
99767     parameter \A_SIGNED 0
99768     parameter \A_WIDTH 1
99769     parameter \B_SIGNED 0
99770     parameter \B_WIDTH 1
99771     parameter \Y_WIDTH 1
99772     connect \A \builder_roundrobin3_grant
99773     connect \B 1'0
99774     connect \Y $eq$ls180.v:3998$439_Y
99775   end
99776   attribute \src "ls180.v:4003.42-4003.82"
99777   cell $eq $eq$ls180.v:4003$448
99778     parameter \A_SIGNED 0
99779     parameter \A_WIDTH 2
99780     parameter \B_SIGNED 0
99781     parameter \B_WIDTH 2
99782     parameter \Y_WIDTH 1
99783     connect \A \main_port_cmd_payload_addr [10:9]
99784     connect \B 2'11
99785     connect \Y $eq$ls180.v:4003$448_Y
99786   end
99787   attribute \src "ls180.v:4003.145-4003.178"
99788   cell $eq $eq$ls180.v:4003$449
99789     parameter \A_SIGNED 0
99790     parameter \A_WIDTH 1
99791     parameter \B_SIGNED 0
99792     parameter \B_WIDTH 1
99793     parameter \Y_WIDTH 1
99794     connect \A \builder_roundrobin0_grant
99795     connect \B 1'0
99796     connect \Y $eq$ls180.v:4003$449_Y
99797   end
99798   attribute \src "ls180.v:4003.220-4003.253"
99799   cell $eq $eq$ls180.v:4003$452
99800     parameter \A_SIGNED 0
99801     parameter \A_WIDTH 1
99802     parameter \B_SIGNED 0
99803     parameter \B_WIDTH 1
99804     parameter \Y_WIDTH 1
99805     connect \A \builder_roundrobin1_grant
99806     connect \B 1'0
99807     connect \Y $eq$ls180.v:4003$452_Y
99808   end
99809   attribute \src "ls180.v:4003.295-4003.328"
99810   cell $eq $eq$ls180.v:4003$455
99811     parameter \A_SIGNED 0
99812     parameter \A_WIDTH 1
99813     parameter \B_SIGNED 0
99814     parameter \B_WIDTH 1
99815     parameter \Y_WIDTH 1
99816     connect \A \builder_roundrobin2_grant
99817     connect \B 1'0
99818     connect \Y $eq$ls180.v:4003$455_Y
99819   end
99820   attribute \src "ls180.v:4008.44-4008.77"
99821   cell $eq $eq$ls180.v:4008$464
99822     parameter \A_SIGNED 0
99823     parameter \A_WIDTH 1
99824     parameter \B_SIGNED 0
99825     parameter \B_WIDTH 1
99826     parameter \Y_WIDTH 1
99827     connect \A \builder_roundrobin0_grant
99828     connect \B 1'0
99829     connect \Y $eq$ls180.v:4008$464_Y
99830   end
99831   attribute \src "ls180.v:4008.83-4008.123"
99832   cell $eq $eq$ls180.v:4008$465
99833     parameter \A_SIGNED 0
99834     parameter \A_WIDTH 2
99835     parameter \B_SIGNED 0
99836     parameter \B_WIDTH 1
99837     parameter \Y_WIDTH 1
99838     connect \A \main_port_cmd_payload_addr [10:9]
99839     connect \B 1'0
99840     connect \Y $eq$ls180.v:4008$465_Y
99841   end
99842   attribute \src "ls180.v:4008.186-4008.219"
99843   cell $eq $eq$ls180.v:4008$466
99844     parameter \A_SIGNED 0
99845     parameter \A_WIDTH 1
99846     parameter \B_SIGNED 0
99847     parameter \B_WIDTH 1
99848     parameter \Y_WIDTH 1
99849     connect \A \builder_roundrobin1_grant
99850     connect \B 1'0
99851     connect \Y $eq$ls180.v:4008$466_Y
99852   end
99853   attribute \src "ls180.v:4008.261-4008.294"
99854   cell $eq $eq$ls180.v:4008$469
99855     parameter \A_SIGNED 0
99856     parameter \A_WIDTH 1
99857     parameter \B_SIGNED 0
99858     parameter \B_WIDTH 1
99859     parameter \Y_WIDTH 1
99860     connect \A \builder_roundrobin2_grant
99861     connect \B 1'0
99862     connect \Y $eq$ls180.v:4008$469_Y
99863   end
99864   attribute \src "ls180.v:4008.336-4008.369"
99865   cell $eq $eq$ls180.v:4008$472
99866     parameter \A_SIGNED 0
99867     parameter \A_WIDTH 1
99868     parameter \B_SIGNED 0
99869     parameter \B_WIDTH 1
99870     parameter \Y_WIDTH 1
99871     connect \A \builder_roundrobin3_grant
99872     connect \B 1'0
99873     connect \Y $eq$ls180.v:4008$472_Y
99874   end
99875   attribute \src "ls180.v:4008.418-4008.451"
99876   cell $eq $eq$ls180.v:4008$480
99877     parameter \A_SIGNED 0
99878     parameter \A_WIDTH 1
99879     parameter \B_SIGNED 0
99880     parameter \B_WIDTH 1
99881     parameter \Y_WIDTH 1
99882     connect \A \builder_roundrobin1_grant
99883     connect \B 1'0
99884     connect \Y $eq$ls180.v:4008$480_Y
99885   end
99886   attribute \src "ls180.v:4008.457-4008.497"
99887   cell $eq $eq$ls180.v:4008$481
99888     parameter \A_SIGNED 0
99889     parameter \A_WIDTH 2
99890     parameter \B_SIGNED 0
99891     parameter \B_WIDTH 1
99892     parameter \Y_WIDTH 1
99893     connect \A \main_port_cmd_payload_addr [10:9]
99894     connect \B 1'1
99895     connect \Y $eq$ls180.v:4008$481_Y
99896   end
99897   attribute \src "ls180.v:4008.560-4008.593"
99898   cell $eq $eq$ls180.v:4008$482
99899     parameter \A_SIGNED 0
99900     parameter \A_WIDTH 1
99901     parameter \B_SIGNED 0
99902     parameter \B_WIDTH 1
99903     parameter \Y_WIDTH 1
99904     connect \A \builder_roundrobin0_grant
99905     connect \B 1'0
99906     connect \Y $eq$ls180.v:4008$482_Y
99907   end
99908   attribute \src "ls180.v:4008.635-4008.668"
99909   cell $eq $eq$ls180.v:4008$485
99910     parameter \A_SIGNED 0
99911     parameter \A_WIDTH 1
99912     parameter \B_SIGNED 0
99913     parameter \B_WIDTH 1
99914     parameter \Y_WIDTH 1
99915     connect \A \builder_roundrobin2_grant
99916     connect \B 1'0
99917     connect \Y $eq$ls180.v:4008$485_Y
99918   end
99919   attribute \src "ls180.v:4008.710-4008.743"
99920   cell $eq $eq$ls180.v:4008$488
99921     parameter \A_SIGNED 0
99922     parameter \A_WIDTH 1
99923     parameter \B_SIGNED 0
99924     parameter \B_WIDTH 1
99925     parameter \Y_WIDTH 1
99926     connect \A \builder_roundrobin3_grant
99927     connect \B 1'0
99928     connect \Y $eq$ls180.v:4008$488_Y
99929   end
99930   attribute \src "ls180.v:4008.792-4008.825"
99931   cell $eq $eq$ls180.v:4008$496
99932     parameter \A_SIGNED 0
99933     parameter \A_WIDTH 1
99934     parameter \B_SIGNED 0
99935     parameter \B_WIDTH 1
99936     parameter \Y_WIDTH 1
99937     connect \A \builder_roundrobin2_grant
99938     connect \B 1'0
99939     connect \Y $eq$ls180.v:4008$496_Y
99940   end
99941   attribute \src "ls180.v:4008.831-4008.871"
99942   cell $eq $eq$ls180.v:4008$497
99943     parameter \A_SIGNED 0
99944     parameter \A_WIDTH 2
99945     parameter \B_SIGNED 0
99946     parameter \B_WIDTH 2
99947     parameter \Y_WIDTH 1
99948     connect \A \main_port_cmd_payload_addr [10:9]
99949     connect \B 2'10
99950     connect \Y $eq$ls180.v:4008$497_Y
99951   end
99952   attribute \src "ls180.v:4008.934-4008.967"
99953   cell $eq $eq$ls180.v:4008$498
99954     parameter \A_SIGNED 0
99955     parameter \A_WIDTH 1
99956     parameter \B_SIGNED 0
99957     parameter \B_WIDTH 1
99958     parameter \Y_WIDTH 1
99959     connect \A \builder_roundrobin0_grant
99960     connect \B 1'0
99961     connect \Y $eq$ls180.v:4008$498_Y
99962   end
99963   attribute \src "ls180.v:4008.1009-4008.1042"
99964   cell $eq $eq$ls180.v:4008$501
99965     parameter \A_SIGNED 0
99966     parameter \A_WIDTH 1
99967     parameter \B_SIGNED 0
99968     parameter \B_WIDTH 1
99969     parameter \Y_WIDTH 1
99970     connect \A \builder_roundrobin1_grant
99971     connect \B 1'0
99972     connect \Y $eq$ls180.v:4008$501_Y
99973   end
99974   attribute \src "ls180.v:4008.1084-4008.1117"
99975   cell $eq $eq$ls180.v:4008$504
99976     parameter \A_SIGNED 0
99977     parameter \A_WIDTH 1
99978     parameter \B_SIGNED 0
99979     parameter \B_WIDTH 1
99980     parameter \Y_WIDTH 1
99981     connect \A \builder_roundrobin3_grant
99982     connect \B 1'0
99983     connect \Y $eq$ls180.v:4008$504_Y
99984   end
99985   attribute \src "ls180.v:4008.1166-4008.1199"
99986   cell $eq $eq$ls180.v:4008$512
99987     parameter \A_SIGNED 0
99988     parameter \A_WIDTH 1
99989     parameter \B_SIGNED 0
99990     parameter \B_WIDTH 1
99991     parameter \Y_WIDTH 1
99992     connect \A \builder_roundrobin3_grant
99993     connect \B 1'0
99994     connect \Y $eq$ls180.v:4008$512_Y
99995   end
99996   attribute \src "ls180.v:4008.1205-4008.1245"
99997   cell $eq $eq$ls180.v:4008$513
99998     parameter \A_SIGNED 0
99999     parameter \A_WIDTH 2
100000     parameter \B_SIGNED 0
100001     parameter \B_WIDTH 2
100002     parameter \Y_WIDTH 1
100003     connect \A \main_port_cmd_payload_addr [10:9]
100004     connect \B 2'11
100005     connect \Y $eq$ls180.v:4008$513_Y
100006   end
100007   attribute \src "ls180.v:4008.1308-4008.1341"
100008   cell $eq $eq$ls180.v:4008$514
100009     parameter \A_SIGNED 0
100010     parameter \A_WIDTH 1
100011     parameter \B_SIGNED 0
100012     parameter \B_WIDTH 1
100013     parameter \Y_WIDTH 1
100014     connect \A \builder_roundrobin0_grant
100015     connect \B 1'0
100016     connect \Y $eq$ls180.v:4008$514_Y
100017   end
100018   attribute \src "ls180.v:4008.1383-4008.1416"
100019   cell $eq $eq$ls180.v:4008$517
100020     parameter \A_SIGNED 0
100021     parameter \A_WIDTH 1
100022     parameter \B_SIGNED 0
100023     parameter \B_WIDTH 1
100024     parameter \Y_WIDTH 1
100025     connect \A \builder_roundrobin1_grant
100026     connect \B 1'0
100027     connect \Y $eq$ls180.v:4008$517_Y
100028   end
100029   attribute \src "ls180.v:4008.1458-4008.1491"
100030   cell $eq $eq$ls180.v:4008$520
100031     parameter \A_SIGNED 0
100032     parameter \A_WIDTH 1
100033     parameter \B_SIGNED 0
100034     parameter \B_WIDTH 1
100035     parameter \Y_WIDTH 1
100036     connect \A \builder_roundrobin2_grant
100037     connect \B 1'0
100038     connect \Y $eq$ls180.v:4008$520_Y
100039   end
100040   attribute \src "ls180.v:4067.29-4067.57"
100041   cell $eq $eq$ls180.v:4067$533
100042     parameter \A_SIGNED 0
100043     parameter \A_WIDTH 2
100044     parameter \B_SIGNED 0
100045     parameter \B_WIDTH 1
100046     parameter \Y_WIDTH 1
100047     connect \A \main_litedram_wb_sel
100048     connect \B 1'0
100049     connect \Y $eq$ls180.v:4067$533_Y
100050   end
100051   attribute \src "ls180.v:4074.11-4074.41"
100052   cell $eq $eq$ls180.v:4074$538
100053     parameter \A_SIGNED 0
100054     parameter \A_WIDTH 1
100055     parameter \B_SIGNED 0
100056     parameter \B_WIDTH 1
100057     parameter \Y_WIDTH 1
100058     connect \A \main_converter_counter
100059     connect \B 1'1
100060     connect \Y $eq$ls180.v:4074$538_Y
100061   end
100062   attribute \src "ls180.v:4231.37-4231.111"
100063   cell $eq $eq$ls180.v:4231$603
100064     parameter \A_SIGNED 0
100065     parameter \A_WIDTH 16
100066     parameter \B_SIGNED 0
100067     parameter \B_WIDTH 16
100068     parameter \Y_WIDTH 1
100069     connect \A \main_spimaster30_clk_divider
100070     connect \B $sub$ls180.v:4231$602_Y
100071     connect \Y $eq$ls180.v:4231$603_Y
100072   end
100073   attribute \src "ls180.v:4232.37-4232.105"
100074   cell $eq $eq$ls180.v:4232$605
100075     parameter \A_SIGNED 0
100076     parameter \A_WIDTH 16
100077     parameter \B_SIGNED 0
100078     parameter \B_WIDTH 16
100079     parameter \Y_WIDTH 1
100080     connect \A \main_spimaster30_clk_divider
100081     connect \B $sub$ls180.v:4232$604_Y
100082     connect \Y $eq$ls180.v:4232$605_Y
100083   end
100084   attribute \src "ls180.v:4259.10-4259.67"
100085   cell $eq $eq$ls180.v:4259$609
100086     parameter \A_SIGNED 0
100087     parameter \A_WIDTH 3
100088     parameter \B_SIGNED 0
100089     parameter \B_WIDTH 8
100090     parameter \Y_WIDTH 1
100091     connect \A \main_spimaster27_count
100092     connect \B $sub$ls180.v:4259$608_Y
100093     connect \Y $eq$ls180.v:4259$609_Y
100094   end
100095   attribute \src "ls180.v:4289.35-4289.108"
100096   cell $eq $eq$ls180.v:4289$611
100097     parameter \A_SIGNED 0
100098     parameter \A_WIDTH 16
100099     parameter \B_SIGNED 0
100100     parameter \B_WIDTH 16
100101     parameter \Y_WIDTH 1
100102     connect \A \main_spisdcard_clk_divider1
100103     connect \B $sub$ls180.v:4289$610_Y
100104     connect \Y $eq$ls180.v:4289$611_Y
100105   end
100106   attribute \src "ls180.v:4290.35-4290.102"
100107   cell $eq $eq$ls180.v:4290$613
100108     parameter \A_SIGNED 0
100109     parameter \A_WIDTH 16
100110     parameter \B_SIGNED 0
100111     parameter \B_WIDTH 16
100112     parameter \Y_WIDTH 1
100113     connect \A \main_spisdcard_clk_divider1
100114     connect \B $sub$ls180.v:4290$612_Y
100115     connect \Y $eq$ls180.v:4290$613_Y
100116   end
100117   attribute \src "ls180.v:4318.10-4318.65"
100118   cell $eq $eq$ls180.v:4318$617
100119     parameter \A_SIGNED 0
100120     parameter \A_WIDTH 3
100121     parameter \B_SIGNED 0
100122     parameter \B_WIDTH 8
100123     parameter \Y_WIDTH 1
100124     connect \A \main_spisdcard_count
100125     connect \B $sub$ls180.v:4318$616_Y
100126     connect \Y $eq$ls180.v:4318$617_Y
100127   end
100128   attribute \src "ls180.v:4422.10-4422.40"
100129   cell $eq $eq$ls180.v:4422$644
100130     parameter \A_SIGNED 0
100131     parameter \A_WIDTH 8
100132     parameter \B_SIGNED 0
100133     parameter \B_WIDTH 7
100134     parameter \Y_WIDTH 1
100135     connect \A \main_sdphy_init_count
100136     connect \B 7'1001111
100137     connect \Y $eq$ls180.v:4422$644_Y
100138   end
100139   attribute \src "ls180.v:4479.10-4479.39"
100140   cell $eq $eq$ls180.v:4479$647
100141     parameter \A_SIGNED 0
100142     parameter \A_WIDTH 8
100143     parameter \B_SIGNED 0
100144     parameter \B_WIDTH 3
100145     parameter \Y_WIDTH 1
100146     connect \A \main_sdphy_cmdw_count
100147     connect \B 3'111
100148     connect \Y $eq$ls180.v:4479$647_Y
100149   end
100150   attribute \src "ls180.v:4496.10-4496.39"
100151   cell $eq $eq$ls180.v:4496$649
100152     parameter \A_SIGNED 0
100153     parameter \A_WIDTH 8
100154     parameter \B_SIGNED 0
100155     parameter \B_WIDTH 3
100156     parameter \Y_WIDTH 1
100157     connect \A \main_sdphy_cmdw_count
100158     connect \B 3'111
100159     connect \Y $eq$ls180.v:4496$649_Y
100160   end
100161   attribute \src "ls180.v:4524.38-4524.88"
100162   cell $eq $eq$ls180.v:4524$651
100163     parameter \A_SIGNED 0
100164     parameter \A_WIDTH 1
100165     parameter \B_SIGNED 0
100166     parameter \B_WIDTH 1
100167     parameter \Y_WIDTH 1
100168     connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
100169     connect \B 1'0
100170     connect \Y $eq$ls180.v:4524$651_Y
100171   end
100172   attribute \src "ls180.v:4574.9-4574.40"
100173   cell $eq $eq$ls180.v:4574$661
100174     parameter \A_SIGNED 0
100175     parameter \A_WIDTH 32
100176     parameter \B_SIGNED 0
100177     parameter \B_WIDTH 1
100178     parameter \Y_WIDTH 1
100179     connect \A \main_sdphy_cmdr_timeout
100180     connect \B 1'0
100181     connect \Y $eq$ls180.v:4574$661_Y
100182   end
100183   attribute \src "ls180.v:4583.36-4583.105"
100184   cell $eq $eq$ls180.v:4583$663
100185     parameter \A_SIGNED 0
100186     parameter \A_WIDTH 8
100187     parameter \B_SIGNED 0
100188     parameter \B_WIDTH 8
100189     parameter \Y_WIDTH 1
100190     connect \A \main_sdphy_cmdr_count
100191     connect \B $sub$ls180.v:4583$662_Y
100192     connect \Y $eq$ls180.v:4583$663_Y
100193   end
100194   attribute \src "ls180.v:4602.9-4602.40"
100195   cell $eq $eq$ls180.v:4602$667
100196     parameter \A_SIGNED 0
100197     parameter \A_WIDTH 32
100198     parameter \B_SIGNED 0
100199     parameter \B_WIDTH 1
100200     parameter \Y_WIDTH 1
100201     connect \A \main_sdphy_cmdr_timeout
100202     connect \B 1'0
100203     connect \Y $eq$ls180.v:4602$667_Y
100204   end
100205   attribute \src "ls180.v:4614.10-4614.39"
100206   cell $eq $eq$ls180.v:4614$669
100207     parameter \A_SIGNED 0
100208     parameter \A_WIDTH 8
100209     parameter \B_SIGNED 0
100210     parameter \B_WIDTH 3
100211     parameter \Y_WIDTH 1
100212     connect \A \main_sdphy_cmdr_count
100213     connect \B 3'111
100214     connect \Y $eq$ls180.v:4614$669_Y
100215   end
100216   attribute \src "ls180.v:4651.39-4651.94"
100217   cell $eq $eq$ls180.v:4651$673
100218     parameter \A_SIGNED 0
100219     parameter \A_WIDTH 1
100220     parameter \B_SIGNED 0
100221     parameter \B_WIDTH 1
100222     parameter \Y_WIDTH 1
100223     connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
100224     connect \B 1'0
100225     connect \Y $eq$ls180.v:4651$673_Y
100226   end
100227   attribute \src "ls180.v:4688.32-4688.89"
100228   cell $eq $eq$ls180.v:4688$682
100229     parameter \A_SIGNED 0
100230     parameter \A_WIDTH 8
100231     parameter \B_SIGNED 0
100232     parameter \B_WIDTH 3
100233     parameter \Y_WIDTH 1
100234     connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
100235     connect \B 3'101
100236     connect \Y $eq$ls180.v:4688$682_Y
100237   end
100238   attribute \src "ls180.v:4736.10-4736.40"
100239   cell $eq $eq$ls180.v:4736$686
100240     parameter \A_SIGNED 0
100241     parameter \A_WIDTH 8
100242     parameter \B_SIGNED 0
100243     parameter \B_WIDTH 1
100244     parameter \Y_WIDTH 1
100245     connect \A \main_sdphy_dataw_count
100246     connect \B 1'1
100247     connect \Y $eq$ls180.v:4736$686_Y
100248   end
100249   attribute \src "ls180.v:4785.40-4785.98"
100250   cell $eq $eq$ls180.v:4785$688
100251     parameter \A_SIGNED 0
100252     parameter \A_WIDTH 4
100253     parameter \B_SIGNED 0
100254     parameter \B_WIDTH 1
100255     parameter \Y_WIDTH 1
100256     connect \A \main_sdphy_datar_datar_pads_in_payload_data_i
100257     connect \B 1'0
100258     connect \Y $eq$ls180.v:4785$688_Y
100259   end
100260   attribute \src "ls180.v:4836.9-4836.41"
100261   cell $eq $eq$ls180.v:4836$698
100262     parameter \A_SIGNED 0
100263     parameter \A_WIDTH 32
100264     parameter \B_SIGNED 0
100265     parameter \B_WIDTH 1
100266     parameter \Y_WIDTH 1
100267     connect \A \main_sdphy_datar_timeout
100268     connect \B 1'0
100269     connect \Y $eq$ls180.v:4836$698_Y
100270   end
100271   attribute \src "ls180.v:4845.37-4845.123"
100272   cell $eq $eq$ls180.v:4845$701
100273     parameter \A_SIGNED 0
100274     parameter \A_WIDTH 10
100275     parameter \B_SIGNED 0
100276     parameter \B_WIDTH 10
100277     parameter \Y_WIDTH 1
100278     connect \A \main_sdphy_datar_count
100279     connect \B $sub$ls180.v:4845$700_Y
100280     connect \Y $eq$ls180.v:4845$701_Y
100281   end
100282   attribute \src "ls180.v:4868.9-4868.41"
100283   cell $eq $eq$ls180.v:4868$704
100284     parameter \A_SIGNED 0
100285     parameter \A_WIDTH 32
100286     parameter \B_SIGNED 0
100287     parameter \B_WIDTH 1
100288     parameter \Y_WIDTH 1
100289     connect \A \main_sdphy_datar_timeout
100290     connect \B 1'0
100291     connect \Y $eq$ls180.v:4868$704_Y
100292   end
100293   attribute \src "ls180.v:4878.10-4878.41"
100294   cell $eq $eq$ls180.v:4878$706
100295     parameter \A_SIGNED 0
100296     parameter \A_WIDTH 10
100297     parameter \B_SIGNED 0
100298     parameter \B_WIDTH 6
100299     parameter \Y_WIDTH 1
100300     connect \A \main_sdphy_datar_count
100301     connect \B 6'100111
100302     connect \Y $eq$ls180.v:4878$706_Y
100303   end
100304   attribute \src "ls180.v:5047.9-5047.47"
100305   cell $eq $eq$ls180.v:5047$888
100306     parameter \A_SIGNED 0
100307     parameter \A_WIDTH 3
100308     parameter \B_SIGNED 0
100309     parameter \B_WIDTH 3
100310     parameter \Y_WIDTH 1
100311     connect \A \main_sdcore_crc16_inserter_cnt
100312     connect \B 3'111
100313     connect \Y $eq$ls180.v:5047$888_Y
100314   end
100315   attribute \src "ls180.v:5077.10-5077.48"
100316   cell $eq $eq$ls180.v:5077$889
100317     parameter \A_SIGNED 0
100318     parameter \A_WIDTH 3
100319     parameter \B_SIGNED 0
100320     parameter \B_WIDTH 3
100321     parameter \Y_WIDTH 1
100322     connect \A \main_sdcore_crc16_inserter_cnt
100323     connect \B 3'111
100324     connect \Y $eq$ls180.v:5077$889_Y
100325   end
100326   attribute \src "ls180.v:5108.10-5108.78"
100327   cell $eq $eq$ls180.v:5108$894
100328     parameter \A_SIGNED 0
100329     parameter \A_WIDTH 16
100330     parameter \B_SIGNED 0
100331     parameter \B_WIDTH 16
100332     parameter \Y_WIDTH 1
100333     connect \A \main_sdcore_crc16_checker_fifo0
100334     connect \B \main_sdcore_crc16_checker_crctmp0
100335     connect \Y $eq$ls180.v:5108$894_Y
100336   end
100337   attribute \src "ls180.v:5108.83-5108.151"
100338   cell $eq $eq$ls180.v:5108$895
100339     parameter \A_SIGNED 0
100340     parameter \A_WIDTH 16
100341     parameter \B_SIGNED 0
100342     parameter \B_WIDTH 16
100343     parameter \Y_WIDTH 1
100344     connect \A \main_sdcore_crc16_checker_fifo1
100345     connect \B \main_sdcore_crc16_checker_crctmp1
100346     connect \Y $eq$ls180.v:5108$895_Y
100347   end
100348   attribute \src "ls180.v:5108.157-5108.225"
100349   cell $eq $eq$ls180.v:5108$897
100350     parameter \A_SIGNED 0
100351     parameter \A_WIDTH 16
100352     parameter \B_SIGNED 0
100353     parameter \B_WIDTH 16
100354     parameter \Y_WIDTH 1
100355     connect \A \main_sdcore_crc16_checker_fifo2
100356     connect \B \main_sdcore_crc16_checker_crctmp2
100357     connect \Y $eq$ls180.v:5108$897_Y
100358   end
100359   attribute \src "ls180.v:5108.231-5108.299"
100360   cell $eq $eq$ls180.v:5108$899
100361     parameter \A_SIGNED 0
100362     parameter \A_WIDTH 16
100363     parameter \B_SIGNED 0
100364     parameter \B_WIDTH 16
100365     parameter \Y_WIDTH 1
100366     connect \A \main_sdcore_crc16_checker_fifo3
100367     connect \B \main_sdcore_crc16_checker_crctmp3
100368     connect \Y $eq$ls180.v:5108$899_Y
100369   end
100370   attribute \src "ls180.v:5116.7-5116.44"
100371   cell $eq $eq$ls180.v:5116$903
100372     parameter \A_SIGNED 0
100373     parameter \A_WIDTH 4
100374     parameter \B_SIGNED 0
100375     parameter \B_WIDTH 3
100376     parameter \Y_WIDTH 1
100377     connect \A \main_sdcore_crc16_checker_cnt
100378     connect \B 3'111
100379     connect \Y $eq$ls180.v:5116$903_Y
100380   end
100381   attribute \src "ls180.v:5126.7-5126.44"
100382   cell $eq $eq$ls180.v:5126$906
100383     parameter \A_SIGNED 0
100384     parameter \A_WIDTH 4
100385     parameter \B_SIGNED 0
100386     parameter \B_WIDTH 3
100387     parameter \Y_WIDTH 1
100388     connect \A \main_sdcore_crc16_checker_cnt
100389     connect \B 3'111
100390     connect \Y $eq$ls180.v:5126$906_Y
100391   end
100392   attribute \src "ls180.v:5136.7-5136.44"
100393   cell $eq $eq$ls180.v:5136$909
100394     parameter \A_SIGNED 0
100395     parameter \A_WIDTH 4
100396     parameter \B_SIGNED 0
100397     parameter \B_WIDTH 3
100398     parameter \Y_WIDTH 1
100399     connect \A \main_sdcore_crc16_checker_cnt
100400     connect \B 3'111
100401     connect \Y $eq$ls180.v:5136$909_Y
100402   end
100403   attribute \src "ls180.v:5146.7-5146.44"
100404   cell $eq $eq$ls180.v:5146$912
100405     parameter \A_SIGNED 0
100406     parameter \A_WIDTH 4
100407     parameter \B_SIGNED 0
100408     parameter \B_WIDTH 3
100409     parameter \Y_WIDTH 1
100410     connect \A \main_sdcore_crc16_checker_cnt
100411     connect \B 3'111
100412     connect \Y $eq$ls180.v:5146$912_Y
100413   end
100414   attribute \src "ls180.v:5270.36-5270.64"
100415   cell $eq $eq$ls180.v:5270$963
100416     parameter \A_SIGNED 0
100417     parameter \A_WIDTH 2
100418     parameter \B_SIGNED 0
100419     parameter \B_WIDTH 1
100420     parameter \Y_WIDTH 1
100421     connect \A \main_sdcore_cmd_type
100422     connect \B 1'0
100423     connect \Y $eq$ls180.v:5270$963_Y
100424   end
100425   attribute \src "ls180.v:5276.10-5276.39"
100426   cell $eq $eq$ls180.v:5276$966
100427     parameter \A_SIGNED 0
100428     parameter \A_WIDTH 3
100429     parameter \B_SIGNED 0
100430     parameter \B_WIDTH 3
100431     parameter \Y_WIDTH 1
100432     connect \A \main_sdcore_cmd_count
100433     connect \B 3'101
100434     connect \Y $eq$ls180.v:5276$966_Y
100435   end
100436   attribute \src "ls180.v:5277.11-5277.39"
100437   cell $eq $eq$ls180.v:5277$967
100438     parameter \A_SIGNED 0
100439     parameter \A_WIDTH 2
100440     parameter \B_SIGNED 0
100441     parameter \B_WIDTH 1
100442     parameter \Y_WIDTH 1
100443     connect \A \main_sdcore_cmd_type
100444     connect \B 1'0
100445     connect \Y $eq$ls180.v:5277$967_Y
100446   end
100447   attribute \src "ls180.v:5289.34-5289.63"
100448   cell $eq $eq$ls180.v:5289$968
100449     parameter \A_SIGNED 0
100450     parameter \A_WIDTH 2
100451     parameter \B_SIGNED 0
100452     parameter \B_WIDTH 1
100453     parameter \Y_WIDTH 1
100454     connect \A \main_sdcore_data_type
100455     connect \B 1'0
100456     connect \Y $eq$ls180.v:5289$968_Y
100457   end
100458   attribute \src "ls180.v:5290.9-5290.37"
100459   cell $eq $eq$ls180.v:5290$969
100460     parameter \A_SIGNED 0
100461     parameter \A_WIDTH 2
100462     parameter \B_SIGNED 0
100463     parameter \B_WIDTH 2
100464     parameter \Y_WIDTH 1
100465     connect \A \main_sdcore_cmd_type
100466     connect \B 2'10
100467     connect \Y $eq$ls180.v:5290$969_Y
100468   end
100469   attribute \src "ls180.v:5297.10-5297.55"
100470   cell $eq $eq$ls180.v:5297$970
100471     parameter \A_SIGNED 0
100472     parameter \A_WIDTH 3
100473     parameter \B_SIGNED 0
100474     parameter \B_WIDTH 1
100475     parameter \Y_WIDTH 1
100476     connect \A \main_sdphy_cmdr_source_payload_status
100477     connect \B 1'1
100478     connect \Y $eq$ls180.v:5297$970_Y
100479   end
100480   attribute \src "ls180.v:5303.12-5303.41"
100481   cell $eq $eq$ls180.v:5303$971
100482     parameter \A_SIGNED 0
100483     parameter \A_WIDTH 2
100484     parameter \B_SIGNED 0
100485     parameter \B_WIDTH 2
100486     parameter \Y_WIDTH 1
100487     connect \A \main_sdcore_data_type
100488     connect \B 2'10
100489     connect \Y $eq$ls180.v:5303$971_Y
100490   end
100491   attribute \src "ls180.v:5306.13-5306.42"
100492   cell $eq $eq$ls180.v:5306$972
100493     parameter \A_SIGNED 0
100494     parameter \A_WIDTH 2
100495     parameter \B_SIGNED 0
100496     parameter \B_WIDTH 1
100497     parameter \Y_WIDTH 1
100498     connect \A \main_sdcore_data_type
100499     connect \B 1'1
100500     connect \Y $eq$ls180.v:5306$972_Y
100501   end
100502   attribute \src "ls180.v:5328.10-5328.76"
100503   cell $eq $eq$ls180.v:5328$977
100504     parameter \A_SIGNED 0
100505     parameter \A_WIDTH 32
100506     parameter \B_SIGNED 0
100507     parameter \B_WIDTH 32
100508     parameter \Y_WIDTH 1
100509     connect \A \main_sdcore_data_count
100510     connect \B $sub$ls180.v:5328$976_Y
100511     connect \Y $eq$ls180.v:5328$977_Y
100512   end
100513   attribute \src "ls180.v:5343.35-5343.101"
100514   cell $eq $eq$ls180.v:5343$980
100515     parameter \A_SIGNED 0
100516     parameter \A_WIDTH 32
100517     parameter \B_SIGNED 0
100518     parameter \B_WIDTH 32
100519     parameter \Y_WIDTH 1
100520     connect \A \main_sdcore_data_count
100521     connect \B $sub$ls180.v:5343$979_Y
100522     connect \Y $eq$ls180.v:5343$980_Y
100523   end
100524   attribute \src "ls180.v:5345.10-5345.56"
100525   cell $eq $eq$ls180.v:5345$981
100526     parameter \A_SIGNED 0
100527     parameter \A_WIDTH 3
100528     parameter \B_SIGNED 0
100529     parameter \B_WIDTH 1
100530     parameter \Y_WIDTH 1
100531     connect \A \main_sdphy_datar_source_payload_status
100532     connect \B 1'0
100533     connect \Y $eq$ls180.v:5345$981_Y
100534   end
100535   attribute \src "ls180.v:5354.12-5354.78"
100536   cell $eq $eq$ls180.v:5354$985
100537     parameter \A_SIGNED 0
100538     parameter \A_WIDTH 32
100539     parameter \B_SIGNED 0
100540     parameter \B_WIDTH 32
100541     parameter \Y_WIDTH 1
100542     connect \A \main_sdcore_data_count
100543     connect \B $sub$ls180.v:5354$984_Y
100544     connect \Y $eq$ls180.v:5354$985_Y
100545   end
100546   attribute \src "ls180.v:5361.11-5361.57"
100547   cell $eq $eq$ls180.v:5361$986
100548     parameter \A_SIGNED 0
100549     parameter \A_WIDTH 3
100550     parameter \B_SIGNED 0
100551     parameter \B_WIDTH 1
100552     parameter \Y_WIDTH 1
100553     connect \A \main_sdphy_datar_source_payload_status
100554     connect \B 1'1
100555     connect \Y $eq$ls180.v:5361$986_Y
100556   end
100557   attribute \src "ls180.v:5478.10-5478.105"
100558   cell $eq $eq$ls180.v:5478$1003
100559     parameter \A_SIGNED 0
100560     parameter \A_WIDTH 32
100561     parameter \B_SIGNED 0
100562     parameter \B_WIDTH 32
100563     parameter \Y_WIDTH 1
100564     connect \A \main_sdblock2mem_wishbonedmawriter_offset
100565     connect \B $sub$ls180.v:5478$1002_Y
100566     connect \Y $eq$ls180.v:5478$1003_Y
100567   end
100568   attribute \src "ls180.v:5568.39-5568.106"
100569   cell $eq $eq$ls180.v:5568$1009
100570     parameter \A_SIGNED 0
100571     parameter \A_WIDTH 32
100572     parameter \B_SIGNED 0
100573     parameter \B_WIDTH 32
100574     parameter \Y_WIDTH 1
100575     connect \A \main_sdmem2block_dma_offset
100576     connect \B $sub$ls180.v:5568$1008_Y
100577     connect \Y $eq$ls180.v:5568$1009_Y
100578   end
100579   attribute \src "ls180.v:5598.44-5598.82"
100580   cell $eq $eq$ls180.v:5598$1012
100581     parameter \A_SIGNED 0
100582     parameter \A_WIDTH 2
100583     parameter \B_SIGNED 0
100584     parameter \B_WIDTH 1
100585     parameter \Y_WIDTH 1
100586     connect \A \main_sdmem2block_converter_mux
100587     connect \B 1'0
100588     connect \Y $eq$ls180.v:5598$1012_Y
100589   end
100590   attribute \src "ls180.v:5599.43-5599.81"
100591   cell $eq $eq$ls180.v:5599$1013
100592     parameter \A_SIGNED 0
100593     parameter \A_WIDTH 2
100594     parameter \B_SIGNED 0
100595     parameter \B_WIDTH 2
100596     parameter \Y_WIDTH 1
100597     connect \A \main_sdmem2block_converter_mux
100598     connect \B 2'11
100599     connect \Y $eq$ls180.v:5599$1013_Y
100600   end
100601   attribute \src "ls180.v:5699.85-5699.106"
100602   cell $eq $eq$ls180.v:5699$1029
100603     parameter \A_SIGNED 0
100604     parameter \A_WIDTH 3
100605     parameter \B_SIGNED 0
100606     parameter \B_WIDTH 1
100607     parameter \Y_WIDTH 1
100608     connect \A \builder_grant
100609     connect \B 1'0
100610     connect \Y $eq$ls180.v:5699$1029_Y
100611   end
100612   attribute \src "ls180.v:5700.85-5700.106"
100613   cell $eq $eq$ls180.v:5700$1031
100614     parameter \A_SIGNED 0
100615     parameter \A_WIDTH 3
100616     parameter \B_SIGNED 0
100617     parameter \B_WIDTH 1
100618     parameter \Y_WIDTH 1
100619     connect \A \builder_grant
100620     connect \B 1'1
100621     connect \Y $eq$ls180.v:5700$1031_Y
100622   end
100623   attribute \src "ls180.v:5701.85-5701.106"
100624   cell $eq $eq$ls180.v:5701$1033
100625     parameter \A_SIGNED 0
100626     parameter \A_WIDTH 3
100627     parameter \B_SIGNED 0
100628     parameter \B_WIDTH 2
100629     parameter \Y_WIDTH 1
100630     connect \A \builder_grant
100631     connect \B 2'10
100632     connect \Y $eq$ls180.v:5701$1033_Y
100633   end
100634   attribute \src "ls180.v:5702.57-5702.78"
100635   cell $eq $eq$ls180.v:5702$1035
100636     parameter \A_SIGNED 0
100637     parameter \A_WIDTH 3
100638     parameter \B_SIGNED 0
100639     parameter \B_WIDTH 2
100640     parameter \Y_WIDTH 1
100641     connect \A \builder_grant
100642     connect \B 2'11
100643     connect \Y $eq$ls180.v:5702$1035_Y
100644   end
100645   attribute \src "ls180.v:5703.57-5703.78"
100646   cell $eq $eq$ls180.v:5703$1037
100647     parameter \A_SIGNED 0
100648     parameter \A_WIDTH 3
100649     parameter \B_SIGNED 0
100650     parameter \B_WIDTH 3
100651     parameter \Y_WIDTH 1
100652     connect \A \builder_grant
100653     connect \B 3'100
100654     connect \Y $eq$ls180.v:5703$1037_Y
100655   end
100656   attribute \src "ls180.v:5704.85-5704.106"
100657   cell $eq $eq$ls180.v:5704$1039
100658     parameter \A_SIGNED 0
100659     parameter \A_WIDTH 3
100660     parameter \B_SIGNED 0
100661     parameter \B_WIDTH 1
100662     parameter \Y_WIDTH 1
100663     connect \A \builder_grant
100664     connect \B 1'0
100665     connect \Y $eq$ls180.v:5704$1039_Y
100666   end
100667   attribute \src "ls180.v:5705.85-5705.106"
100668   cell $eq $eq$ls180.v:5705$1041
100669     parameter \A_SIGNED 0
100670     parameter \A_WIDTH 3
100671     parameter \B_SIGNED 0
100672     parameter \B_WIDTH 1
100673     parameter \Y_WIDTH 1
100674     connect \A \builder_grant
100675     connect \B 1'1
100676     connect \Y $eq$ls180.v:5705$1041_Y
100677   end
100678   attribute \src "ls180.v:5706.85-5706.106"
100679   cell $eq $eq$ls180.v:5706$1043
100680     parameter \A_SIGNED 0
100681     parameter \A_WIDTH 3
100682     parameter \B_SIGNED 0
100683     parameter \B_WIDTH 2
100684     parameter \Y_WIDTH 1
100685     connect \A \builder_grant
100686     connect \B 2'10
100687     connect \Y $eq$ls180.v:5706$1043_Y
100688   end
100689   attribute \src "ls180.v:5707.57-5707.78"
100690   cell $eq $eq$ls180.v:5707$1045
100691     parameter \A_SIGNED 0
100692     parameter \A_WIDTH 3
100693     parameter \B_SIGNED 0
100694     parameter \B_WIDTH 2
100695     parameter \Y_WIDTH 1
100696     connect \A \builder_grant
100697     connect \B 2'11
100698     connect \Y $eq$ls180.v:5707$1045_Y
100699   end
100700   attribute \src "ls180.v:5708.57-5708.78"
100701   cell $eq $eq$ls180.v:5708$1047
100702     parameter \A_SIGNED 0
100703     parameter \A_WIDTH 3
100704     parameter \B_SIGNED 0
100705     parameter \B_WIDTH 3
100706     parameter \Y_WIDTH 1
100707     connect \A \builder_grant
100708     connect \B 3'100
100709     connect \Y $eq$ls180.v:5708$1047_Y
100710   end
100711   attribute \src "ls180.v:5712.27-5712.59"
100712   cell $eq $eq$ls180.v:5712$1050
100713     parameter \A_SIGNED 0
100714     parameter \A_WIDTH 23
100715     parameter \B_SIGNED 0
100716     parameter \B_WIDTH 1
100717     parameter \Y_WIDTH 1
100718     connect \A \builder_shared_adr [29:7]
100719     connect \B 1'0
100720     connect \Y $eq$ls180.v:5712$1050_Y
100721   end
100722   attribute \src "ls180.v:5713.27-5713.68"
100723   cell $eq $eq$ls180.v:5713$1051
100724     parameter \A_SIGNED 0
100725     parameter \A_WIDTH 27
100726     parameter \B_SIGNED 0
100727     parameter \B_WIDTH 27
100728     parameter \Y_WIDTH 1
100729     connect \A \builder_shared_adr [29:3]
100730     connect \B 27'110000000000000100000000000
100731     connect \Y $eq$ls180.v:5713$1051_Y
100732   end
100733   attribute \src "ls180.v:5714.27-5714.66"
100734   cell $eq $eq$ls180.v:5714$1052
100735     parameter \A_SIGNED 0
100736     parameter \A_WIDTH 20
100737     parameter \B_SIGNED 0
100738     parameter \B_WIDTH 20
100739     parameter \Y_WIDTH 1
100740     connect \A \builder_shared_adr [29:10]
100741     connect \B 20'11000000000000010001
100742     connect \Y $eq$ls180.v:5714$1052_Y
100743   end
100744   attribute \src "ls180.v:5715.27-5715.61"
100745   cell $eq $eq$ls180.v:5715$1053
100746     parameter \A_SIGNED 0
100747     parameter \A_WIDTH 7
100748     parameter \B_SIGNED 0
100749     parameter \B_WIDTH 7
100750     parameter \Y_WIDTH 1
100751     connect \A \builder_shared_adr [29:23]
100752     connect \B 7'1001000
100753     connect \Y $eq$ls180.v:5715$1053_Y
100754   end
100755   attribute \src "ls180.v:5716.27-5716.65"
100756   cell $eq $eq$ls180.v:5716$1054
100757     parameter \A_SIGNED 0
100758     parameter \A_WIDTH 16
100759     parameter \B_SIGNED 0
100760     parameter \B_WIDTH 16
100761     parameter \Y_WIDTH 1
100762     connect \A \builder_shared_adr [29:14]
100763     connect \B 16'1100000000000000
100764     connect \Y $eq$ls180.v:5716$1054_Y
100765   end
100766   attribute \src "ls180.v:5772.24-5772.45"
100767   cell $eq $eq$ls180.v:5772$1081
100768     parameter \A_SIGNED 0
100769     parameter \A_WIDTH 20
100770     parameter \B_SIGNED 0
100771     parameter \B_WIDTH 1
100772     parameter \Y_WIDTH 1
100773     connect \A \builder_count
100774     connect \B 1'0
100775     connect \Y $eq$ls180.v:5772$1081_Y
100776   end
100777   attribute \src "ls180.v:5773.32-5773.77"
100778   cell $eq $eq$ls180.v:5773$1082
100779     parameter \A_SIGNED 0
100780     parameter \A_WIDTH 5
100781     parameter \B_SIGNED 0
100782     parameter \B_WIDTH 1
100783     parameter \Y_WIDTH 1
100784     connect \A \builder_interface0_bank_bus_adr [13:9]
100785     connect \B 1'0
100786     connect \Y $eq$ls180.v:5773$1082_Y
100787   end
100788   attribute \src "ls180.v:5775.97-5775.141"
100789   cell $eq $eq$ls180.v:5775$1084
100790     parameter \A_SIGNED 0
100791     parameter \A_WIDTH 4
100792     parameter \B_SIGNED 0
100793     parameter \B_WIDTH 1
100794     parameter \Y_WIDTH 1
100795     connect \A \builder_interface0_bank_bus_adr [3:0]
100796     connect \B 1'0
100797     connect \Y $eq$ls180.v:5775$1084_Y
100798   end
100799   attribute \src "ls180.v:5776.100-5776.144"
100800   cell $eq $eq$ls180.v:5776$1088
100801     parameter \A_SIGNED 0
100802     parameter \A_WIDTH 4
100803     parameter \B_SIGNED 0
100804     parameter \B_WIDTH 1
100805     parameter \Y_WIDTH 1
100806     connect \A \builder_interface0_bank_bus_adr [3:0]
100807     connect \B 1'0
100808     connect \Y $eq$ls180.v:5776$1088_Y
100809   end
100810   attribute \src "ls180.v:5778.99-5778.143"
100811   cell $eq $eq$ls180.v:5778$1091
100812     parameter \A_SIGNED 0
100813     parameter \A_WIDTH 4
100814     parameter \B_SIGNED 0
100815     parameter \B_WIDTH 1
100816     parameter \Y_WIDTH 1
100817     connect \A \builder_interface0_bank_bus_adr [3:0]
100818     connect \B 1'1
100819     connect \Y $eq$ls180.v:5778$1091_Y
100820   end
100821   attribute \src "ls180.v:5779.102-5779.146"
100822   cell $eq $eq$ls180.v:5779$1095
100823     parameter \A_SIGNED 0
100824     parameter \A_WIDTH 4
100825     parameter \B_SIGNED 0
100826     parameter \B_WIDTH 1
100827     parameter \Y_WIDTH 1
100828     connect \A \builder_interface0_bank_bus_adr [3:0]
100829     connect \B 1'1
100830     connect \Y $eq$ls180.v:5779$1095_Y
100831   end
100832   attribute \src "ls180.v:5781.99-5781.143"
100833   cell $eq $eq$ls180.v:5781$1098
100834     parameter \A_SIGNED 0
100835     parameter \A_WIDTH 4
100836     parameter \B_SIGNED 0
100837     parameter \B_WIDTH 2
100838     parameter \Y_WIDTH 1
100839     connect \A \builder_interface0_bank_bus_adr [3:0]
100840     connect \B 2'10
100841     connect \Y $eq$ls180.v:5781$1098_Y
100842   end
100843   attribute \src "ls180.v:5782.102-5782.146"
100844   cell $eq $eq$ls180.v:5782$1102
100845     parameter \A_SIGNED 0
100846     parameter \A_WIDTH 4
100847     parameter \B_SIGNED 0
100848     parameter \B_WIDTH 2
100849     parameter \Y_WIDTH 1
100850     connect \A \builder_interface0_bank_bus_adr [3:0]
100851     connect \B 2'10
100852     connect \Y $eq$ls180.v:5782$1102_Y
100853   end
100854   attribute \src "ls180.v:5784.99-5784.143"
100855   cell $eq $eq$ls180.v:5784$1105
100856     parameter \A_SIGNED 0
100857     parameter \A_WIDTH 4
100858     parameter \B_SIGNED 0
100859     parameter \B_WIDTH 2
100860     parameter \Y_WIDTH 1
100861     connect \A \builder_interface0_bank_bus_adr [3:0]
100862     connect \B 2'11
100863     connect \Y $eq$ls180.v:5784$1105_Y
100864   end
100865   attribute \src "ls180.v:5785.102-5785.146"
100866   cell $eq $eq$ls180.v:5785$1109
100867     parameter \A_SIGNED 0
100868     parameter \A_WIDTH 4
100869     parameter \B_SIGNED 0
100870     parameter \B_WIDTH 2
100871     parameter \Y_WIDTH 1
100872     connect \A \builder_interface0_bank_bus_adr [3:0]
100873     connect \B 2'11
100874     connect \Y $eq$ls180.v:5785$1109_Y
100875   end
100876   attribute \src "ls180.v:5787.99-5787.143"
100877   cell $eq $eq$ls180.v:5787$1112
100878     parameter \A_SIGNED 0
100879     parameter \A_WIDTH 4
100880     parameter \B_SIGNED 0
100881     parameter \B_WIDTH 3
100882     parameter \Y_WIDTH 1
100883     connect \A \builder_interface0_bank_bus_adr [3:0]
100884     connect \B 3'100
100885     connect \Y $eq$ls180.v:5787$1112_Y
100886   end
100887   attribute \src "ls180.v:5788.102-5788.146"
100888   cell $eq $eq$ls180.v:5788$1116
100889     parameter \A_SIGNED 0
100890     parameter \A_WIDTH 4
100891     parameter \B_SIGNED 0
100892     parameter \B_WIDTH 3
100893     parameter \Y_WIDTH 1
100894     connect \A \builder_interface0_bank_bus_adr [3:0]
100895     connect \B 3'100
100896     connect \Y $eq$ls180.v:5788$1116_Y
100897   end
100898   attribute \src "ls180.v:5790.102-5790.146"
100899   cell $eq $eq$ls180.v:5790$1119
100900     parameter \A_SIGNED 0
100901     parameter \A_WIDTH 4
100902     parameter \B_SIGNED 0
100903     parameter \B_WIDTH 3
100904     parameter \Y_WIDTH 1
100905     connect \A \builder_interface0_bank_bus_adr [3:0]
100906     connect \B 3'101
100907     connect \Y $eq$ls180.v:5790$1119_Y
100908   end
100909   attribute \src "ls180.v:5791.105-5791.149"
100910   cell $eq $eq$ls180.v:5791$1123
100911     parameter \A_SIGNED 0
100912     parameter \A_WIDTH 4
100913     parameter \B_SIGNED 0
100914     parameter \B_WIDTH 3
100915     parameter \Y_WIDTH 1
100916     connect \A \builder_interface0_bank_bus_adr [3:0]
100917     connect \B 3'101
100918     connect \Y $eq$ls180.v:5791$1123_Y
100919   end
100920   attribute \src "ls180.v:5793.102-5793.146"
100921   cell $eq $eq$ls180.v:5793$1126
100922     parameter \A_SIGNED 0
100923     parameter \A_WIDTH 4
100924     parameter \B_SIGNED 0
100925     parameter \B_WIDTH 3
100926     parameter \Y_WIDTH 1
100927     connect \A \builder_interface0_bank_bus_adr [3:0]
100928     connect \B 3'110
100929     connect \Y $eq$ls180.v:5793$1126_Y
100930   end
100931   attribute \src "ls180.v:5794.105-5794.149"
100932   cell $eq $eq$ls180.v:5794$1130
100933     parameter \A_SIGNED 0
100934     parameter \A_WIDTH 4
100935     parameter \B_SIGNED 0
100936     parameter \B_WIDTH 3
100937     parameter \Y_WIDTH 1
100938     connect \A \builder_interface0_bank_bus_adr [3:0]
100939     connect \B 3'110
100940     connect \Y $eq$ls180.v:5794$1130_Y
100941   end
100942   attribute \src "ls180.v:5796.102-5796.146"
100943   cell $eq $eq$ls180.v:5796$1133
100944     parameter \A_SIGNED 0
100945     parameter \A_WIDTH 4
100946     parameter \B_SIGNED 0
100947     parameter \B_WIDTH 3
100948     parameter \Y_WIDTH 1
100949     connect \A \builder_interface0_bank_bus_adr [3:0]
100950     connect \B 3'111
100951     connect \Y $eq$ls180.v:5796$1133_Y
100952   end
100953   attribute \src "ls180.v:5797.105-5797.149"
100954   cell $eq $eq$ls180.v:5797$1137
100955     parameter \A_SIGNED 0
100956     parameter \A_WIDTH 4
100957     parameter \B_SIGNED 0
100958     parameter \B_WIDTH 3
100959     parameter \Y_WIDTH 1
100960     connect \A \builder_interface0_bank_bus_adr [3:0]
100961     connect \B 3'111
100962     connect \Y $eq$ls180.v:5797$1137_Y
100963   end
100964   attribute \src "ls180.v:5799.102-5799.146"
100965   cell $eq $eq$ls180.v:5799$1140
100966     parameter \A_SIGNED 0
100967     parameter \A_WIDTH 4
100968     parameter \B_SIGNED 0
100969     parameter \B_WIDTH 4
100970     parameter \Y_WIDTH 1
100971     connect \A \builder_interface0_bank_bus_adr [3:0]
100972     connect \B 4'1000
100973     connect \Y $eq$ls180.v:5799$1140_Y
100974   end
100975   attribute \src "ls180.v:5800.105-5800.149"
100976   cell $eq $eq$ls180.v:5800$1144
100977     parameter \A_SIGNED 0
100978     parameter \A_WIDTH 4
100979     parameter \B_SIGNED 0
100980     parameter \B_WIDTH 4
100981     parameter \Y_WIDTH 1
100982     connect \A \builder_interface0_bank_bus_adr [3:0]
100983     connect \B 4'1000
100984     connect \Y $eq$ls180.v:5800$1144_Y
100985   end
100986   attribute \src "ls180.v:5811.32-5811.77"
100987   cell $eq $eq$ls180.v:5811$1146
100988     parameter \A_SIGNED 0
100989     parameter \A_WIDTH 5
100990     parameter \B_SIGNED 0
100991     parameter \B_WIDTH 3
100992     parameter \Y_WIDTH 1
100993     connect \A \builder_interface1_bank_bus_adr [13:9]
100994     connect \B 3'110
100995     connect \Y $eq$ls180.v:5811$1146_Y
100996   end
100997   attribute \src "ls180.v:5813.94-5813.138"
100998   cell $eq $eq$ls180.v:5813$1148
100999     parameter \A_SIGNED 0
101000     parameter \A_WIDTH 3
101001     parameter \B_SIGNED 0
101002     parameter \B_WIDTH 1
101003     parameter \Y_WIDTH 1
101004     connect \A \builder_interface1_bank_bus_adr [2:0]
101005     connect \B 1'0
101006     connect \Y $eq$ls180.v:5813$1148_Y
101007   end
101008   attribute \src "ls180.v:5814.97-5814.141"
101009   cell $eq $eq$ls180.v:5814$1152
101010     parameter \A_SIGNED 0
101011     parameter \A_WIDTH 3
101012     parameter \B_SIGNED 0
101013     parameter \B_WIDTH 1
101014     parameter \Y_WIDTH 1
101015     connect \A \builder_interface1_bank_bus_adr [2:0]
101016     connect \B 1'0
101017     connect \Y $eq$ls180.v:5814$1152_Y
101018   end
101019   attribute \src "ls180.v:5816.94-5816.138"
101020   cell $eq $eq$ls180.v:5816$1155
101021     parameter \A_SIGNED 0
101022     parameter \A_WIDTH 3
101023     parameter \B_SIGNED 0
101024     parameter \B_WIDTH 1
101025     parameter \Y_WIDTH 1
101026     connect \A \builder_interface1_bank_bus_adr [2:0]
101027     connect \B 1'1
101028     connect \Y $eq$ls180.v:5816$1155_Y
101029   end
101030   attribute \src "ls180.v:5817.97-5817.141"
101031   cell $eq $eq$ls180.v:5817$1159
101032     parameter \A_SIGNED 0
101033     parameter \A_WIDTH 3
101034     parameter \B_SIGNED 0
101035     parameter \B_WIDTH 1
101036     parameter \Y_WIDTH 1
101037     connect \A \builder_interface1_bank_bus_adr [2:0]
101038     connect \B 1'1
101039     connect \Y $eq$ls180.v:5817$1159_Y
101040   end
101041   attribute \src "ls180.v:5819.94-5819.138"
101042   cell $eq $eq$ls180.v:5819$1162
101043     parameter \A_SIGNED 0
101044     parameter \A_WIDTH 3
101045     parameter \B_SIGNED 0
101046     parameter \B_WIDTH 2
101047     parameter \Y_WIDTH 1
101048     connect \A \builder_interface1_bank_bus_adr [2:0]
101049     connect \B 2'10
101050     connect \Y $eq$ls180.v:5819$1162_Y
101051   end
101052   attribute \src "ls180.v:5820.97-5820.141"
101053   cell $eq $eq$ls180.v:5820$1166
101054     parameter \A_SIGNED 0
101055     parameter \A_WIDTH 3
101056     parameter \B_SIGNED 0
101057     parameter \B_WIDTH 2
101058     parameter \Y_WIDTH 1
101059     connect \A \builder_interface1_bank_bus_adr [2:0]
101060     connect \B 2'10
101061     connect \Y $eq$ls180.v:5820$1166_Y
101062   end
101063   attribute \src "ls180.v:5822.94-5822.138"
101064   cell $eq $eq$ls180.v:5822$1169
101065     parameter \A_SIGNED 0
101066     parameter \A_WIDTH 3
101067     parameter \B_SIGNED 0
101068     parameter \B_WIDTH 2
101069     parameter \Y_WIDTH 1
101070     connect \A \builder_interface1_bank_bus_adr [2:0]
101071     connect \B 2'11
101072     connect \Y $eq$ls180.v:5822$1169_Y
101073   end
101074   attribute \src "ls180.v:5823.97-5823.141"
101075   cell $eq $eq$ls180.v:5823$1173
101076     parameter \A_SIGNED 0
101077     parameter \A_WIDTH 3
101078     parameter \B_SIGNED 0
101079     parameter \B_WIDTH 2
101080     parameter \Y_WIDTH 1
101081     connect \A \builder_interface1_bank_bus_adr [2:0]
101082     connect \B 2'11
101083     connect \Y $eq$ls180.v:5823$1173_Y
101084   end
101085   attribute \src "ls180.v:5825.95-5825.139"
101086   cell $eq $eq$ls180.v:5825$1176
101087     parameter \A_SIGNED 0
101088     parameter \A_WIDTH 3
101089     parameter \B_SIGNED 0
101090     parameter \B_WIDTH 3
101091     parameter \Y_WIDTH 1
101092     connect \A \builder_interface1_bank_bus_adr [2:0]
101093     connect \B 3'100
101094     connect \Y $eq$ls180.v:5825$1176_Y
101095   end
101096   attribute \src "ls180.v:5826.98-5826.142"
101097   cell $eq $eq$ls180.v:5826$1180
101098     parameter \A_SIGNED 0
101099     parameter \A_WIDTH 3
101100     parameter \B_SIGNED 0
101101     parameter \B_WIDTH 3
101102     parameter \Y_WIDTH 1
101103     connect \A \builder_interface1_bank_bus_adr [2:0]
101104     connect \B 3'100
101105     connect \Y $eq$ls180.v:5826$1180_Y
101106   end
101107   attribute \src "ls180.v:5828.95-5828.139"
101108   cell $eq $eq$ls180.v:5828$1183
101109     parameter \A_SIGNED 0
101110     parameter \A_WIDTH 3
101111     parameter \B_SIGNED 0
101112     parameter \B_WIDTH 3
101113     parameter \Y_WIDTH 1
101114     connect \A \builder_interface1_bank_bus_adr [2:0]
101115     connect \B 3'101
101116     connect \Y $eq$ls180.v:5828$1183_Y
101117   end
101118   attribute \src "ls180.v:5829.98-5829.142"
101119   cell $eq $eq$ls180.v:5829$1187
101120     parameter \A_SIGNED 0
101121     parameter \A_WIDTH 3
101122     parameter \B_SIGNED 0
101123     parameter \B_WIDTH 3
101124     parameter \Y_WIDTH 1
101125     connect \A \builder_interface1_bank_bus_adr [2:0]
101126     connect \B 3'101
101127     connect \Y $eq$ls180.v:5829$1187_Y
101128   end
101129   attribute \src "ls180.v:5837.32-5837.78"
101130   cell $eq $eq$ls180.v:5837$1189
101131     parameter \A_SIGNED 0
101132     parameter \A_WIDTH 5
101133     parameter \B_SIGNED 0
101134     parameter \B_WIDTH 4
101135     parameter \Y_WIDTH 1
101136     connect \A \builder_interface2_bank_bus_adr [13:9]
101137     connect \B 4'1011
101138     connect \Y $eq$ls180.v:5837$1189_Y
101139   end
101140   attribute \src "ls180.v:5839.93-5839.135"
101141   cell $eq $eq$ls180.v:5839$1191
101142     parameter \A_SIGNED 0
101143     parameter \A_WIDTH 1
101144     parameter \B_SIGNED 0
101145     parameter \B_WIDTH 1
101146     parameter \Y_WIDTH 1
101147     connect \A \builder_interface2_bank_bus_adr [0]
101148     connect \B 1'0
101149     connect \Y $eq$ls180.v:5839$1191_Y
101150   end
101151   attribute \src "ls180.v:5840.96-5840.138"
101152   cell $eq $eq$ls180.v:5840$1195
101153     parameter \A_SIGNED 0
101154     parameter \A_WIDTH 1
101155     parameter \B_SIGNED 0
101156     parameter \B_WIDTH 1
101157     parameter \Y_WIDTH 1
101158     connect \A \builder_interface2_bank_bus_adr [0]
101159     connect \B 1'0
101160     connect \Y $eq$ls180.v:5840$1195_Y
101161   end
101162   attribute \src "ls180.v:5842.92-5842.134"
101163   cell $eq $eq$ls180.v:5842$1198
101164     parameter \A_SIGNED 0
101165     parameter \A_WIDTH 1
101166     parameter \B_SIGNED 0
101167     parameter \B_WIDTH 1
101168     parameter \Y_WIDTH 1
101169     connect \A \builder_interface2_bank_bus_adr [0]
101170     connect \B 1'1
101171     connect \Y $eq$ls180.v:5842$1198_Y
101172   end
101173   attribute \src "ls180.v:5843.95-5843.137"
101174   cell $eq $eq$ls180.v:5843$1202
101175     parameter \A_SIGNED 0
101176     parameter \A_WIDTH 1
101177     parameter \B_SIGNED 0
101178     parameter \B_WIDTH 1
101179     parameter \Y_WIDTH 1
101180     connect \A \builder_interface2_bank_bus_adr [0]
101181     connect \B 1'1
101182     connect \Y $eq$ls180.v:5843$1202_Y
101183   end
101184   attribute \src "ls180.v:5851.32-5851.77"
101185   cell $eq $eq$ls180.v:5851$1204
101186     parameter \A_SIGNED 0
101187     parameter \A_WIDTH 5
101188     parameter \B_SIGNED 0
101189     parameter \B_WIDTH 4
101190     parameter \Y_WIDTH 1
101191     connect \A \builder_interface3_bank_bus_adr [13:9]
101192     connect \B 4'1001
101193     connect \Y $eq$ls180.v:5851$1204_Y
101194   end
101195   attribute \src "ls180.v:5853.98-5853.142"
101196   cell $eq $eq$ls180.v:5853$1206
101197     parameter \A_SIGNED 0
101198     parameter \A_WIDTH 4
101199     parameter \B_SIGNED 0
101200     parameter \B_WIDTH 1
101201     parameter \Y_WIDTH 1
101202     connect \A \builder_interface3_bank_bus_adr [3:0]
101203     connect \B 1'0
101204     connect \Y $eq$ls180.v:5853$1206_Y
101205   end
101206   attribute \src "ls180.v:5854.101-5854.145"
101207   cell $eq $eq$ls180.v:5854$1210
101208     parameter \A_SIGNED 0
101209     parameter \A_WIDTH 4
101210     parameter \B_SIGNED 0
101211     parameter \B_WIDTH 1
101212     parameter \Y_WIDTH 1
101213     connect \A \builder_interface3_bank_bus_adr [3:0]
101214     connect \B 1'0
101215     connect \Y $eq$ls180.v:5854$1210_Y
101216   end
101217   attribute \src "ls180.v:5856.97-5856.141"
101218   cell $eq $eq$ls180.v:5856$1213
101219     parameter \A_SIGNED 0
101220     parameter \A_WIDTH 4
101221     parameter \B_SIGNED 0
101222     parameter \B_WIDTH 1
101223     parameter \Y_WIDTH 1
101224     connect \A \builder_interface3_bank_bus_adr [3:0]
101225     connect \B 1'1
101226     connect \Y $eq$ls180.v:5856$1213_Y
101227   end
101228   attribute \src "ls180.v:5857.100-5857.144"
101229   cell $eq $eq$ls180.v:5857$1217
101230     parameter \A_SIGNED 0
101231     parameter \A_WIDTH 4
101232     parameter \B_SIGNED 0
101233     parameter \B_WIDTH 1
101234     parameter \Y_WIDTH 1
101235     connect \A \builder_interface3_bank_bus_adr [3:0]
101236     connect \B 1'1
101237     connect \Y $eq$ls180.v:5857$1217_Y
101238   end
101239   attribute \src "ls180.v:5859.97-5859.141"
101240   cell $eq $eq$ls180.v:5859$1220
101241     parameter \A_SIGNED 0
101242     parameter \A_WIDTH 4
101243     parameter \B_SIGNED 0
101244     parameter \B_WIDTH 2
101245     parameter \Y_WIDTH 1
101246     connect \A \builder_interface3_bank_bus_adr [3:0]
101247     connect \B 2'10
101248     connect \Y $eq$ls180.v:5859$1220_Y
101249   end
101250   attribute \src "ls180.v:5860.100-5860.144"
101251   cell $eq $eq$ls180.v:5860$1224
101252     parameter \A_SIGNED 0
101253     parameter \A_WIDTH 4
101254     parameter \B_SIGNED 0
101255     parameter \B_WIDTH 2
101256     parameter \Y_WIDTH 1
101257     connect \A \builder_interface3_bank_bus_adr [3:0]
101258     connect \B 2'10
101259     connect \Y $eq$ls180.v:5860$1224_Y
101260   end
101261   attribute \src "ls180.v:5862.97-5862.141"
101262   cell $eq $eq$ls180.v:5862$1227
101263     parameter \A_SIGNED 0
101264     parameter \A_WIDTH 4
101265     parameter \B_SIGNED 0
101266     parameter \B_WIDTH 2
101267     parameter \Y_WIDTH 1
101268     connect \A \builder_interface3_bank_bus_adr [3:0]
101269     connect \B 2'11
101270     connect \Y $eq$ls180.v:5862$1227_Y
101271   end
101272   attribute \src "ls180.v:5863.100-5863.144"
101273   cell $eq $eq$ls180.v:5863$1231
101274     parameter \A_SIGNED 0
101275     parameter \A_WIDTH 4
101276     parameter \B_SIGNED 0
101277     parameter \B_WIDTH 2
101278     parameter \Y_WIDTH 1
101279     connect \A \builder_interface3_bank_bus_adr [3:0]
101280     connect \B 2'11
101281     connect \Y $eq$ls180.v:5863$1231_Y
101282   end
101283   attribute \src "ls180.v:5865.97-5865.141"
101284   cell $eq $eq$ls180.v:5865$1234
101285     parameter \A_SIGNED 0
101286     parameter \A_WIDTH 4
101287     parameter \B_SIGNED 0
101288     parameter \B_WIDTH 3
101289     parameter \Y_WIDTH 1
101290     connect \A \builder_interface3_bank_bus_adr [3:0]
101291     connect \B 3'100
101292     connect \Y $eq$ls180.v:5865$1234_Y
101293   end
101294   attribute \src "ls180.v:5866.100-5866.144"
101295   cell $eq $eq$ls180.v:5866$1238
101296     parameter \A_SIGNED 0
101297     parameter \A_WIDTH 4
101298     parameter \B_SIGNED 0
101299     parameter \B_WIDTH 3
101300     parameter \Y_WIDTH 1
101301     connect \A \builder_interface3_bank_bus_adr [3:0]
101302     connect \B 3'100
101303     connect \Y $eq$ls180.v:5866$1238_Y
101304   end
101305   attribute \src "ls180.v:5868.98-5868.142"
101306   cell $eq $eq$ls180.v:5868$1241
101307     parameter \A_SIGNED 0
101308     parameter \A_WIDTH 4
101309     parameter \B_SIGNED 0
101310     parameter \B_WIDTH 3
101311     parameter \Y_WIDTH 1
101312     connect \A \builder_interface3_bank_bus_adr [3:0]
101313     connect \B 3'101
101314     connect \Y $eq$ls180.v:5868$1241_Y
101315   end
101316   attribute \src "ls180.v:5869.101-5869.145"
101317   cell $eq $eq$ls180.v:5869$1245
101318     parameter \A_SIGNED 0
101319     parameter \A_WIDTH 4
101320     parameter \B_SIGNED 0
101321     parameter \B_WIDTH 3
101322     parameter \Y_WIDTH 1
101323     connect \A \builder_interface3_bank_bus_adr [3:0]
101324     connect \B 3'101
101325     connect \Y $eq$ls180.v:5869$1245_Y
101326   end
101327   attribute \src "ls180.v:5871.98-5871.142"
101328   cell $eq $eq$ls180.v:5871$1248
101329     parameter \A_SIGNED 0
101330     parameter \A_WIDTH 4
101331     parameter \B_SIGNED 0
101332     parameter \B_WIDTH 3
101333     parameter \Y_WIDTH 1
101334     connect \A \builder_interface3_bank_bus_adr [3:0]
101335     connect \B 3'110
101336     connect \Y $eq$ls180.v:5871$1248_Y
101337   end
101338   attribute \src "ls180.v:5872.101-5872.145"
101339   cell $eq $eq$ls180.v:5872$1252
101340     parameter \A_SIGNED 0
101341     parameter \A_WIDTH 4
101342     parameter \B_SIGNED 0
101343     parameter \B_WIDTH 3
101344     parameter \Y_WIDTH 1
101345     connect \A \builder_interface3_bank_bus_adr [3:0]
101346     connect \B 3'110
101347     connect \Y $eq$ls180.v:5872$1252_Y
101348   end
101349   attribute \src "ls180.v:5874.98-5874.142"
101350   cell $eq $eq$ls180.v:5874$1255
101351     parameter \A_SIGNED 0
101352     parameter \A_WIDTH 4
101353     parameter \B_SIGNED 0
101354     parameter \B_WIDTH 3
101355     parameter \Y_WIDTH 1
101356     connect \A \builder_interface3_bank_bus_adr [3:0]
101357     connect \B 3'111
101358     connect \Y $eq$ls180.v:5874$1255_Y
101359   end
101360   attribute \src "ls180.v:5875.101-5875.145"
101361   cell $eq $eq$ls180.v:5875$1259
101362     parameter \A_SIGNED 0
101363     parameter \A_WIDTH 4
101364     parameter \B_SIGNED 0
101365     parameter \B_WIDTH 3
101366     parameter \Y_WIDTH 1
101367     connect \A \builder_interface3_bank_bus_adr [3:0]
101368     connect \B 3'111
101369     connect \Y $eq$ls180.v:5875$1259_Y
101370   end
101371   attribute \src "ls180.v:5877.98-5877.142"
101372   cell $eq $eq$ls180.v:5877$1262
101373     parameter \A_SIGNED 0
101374     parameter \A_WIDTH 4
101375     parameter \B_SIGNED 0
101376     parameter \B_WIDTH 4
101377     parameter \Y_WIDTH 1
101378     connect \A \builder_interface3_bank_bus_adr [3:0]
101379     connect \B 4'1000
101380     connect \Y $eq$ls180.v:5877$1262_Y
101381   end
101382   attribute \src "ls180.v:5878.101-5878.145"
101383   cell $eq $eq$ls180.v:5878$1266
101384     parameter \A_SIGNED 0
101385     parameter \A_WIDTH 4
101386     parameter \B_SIGNED 0
101387     parameter \B_WIDTH 4
101388     parameter \Y_WIDTH 1
101389     connect \A \builder_interface3_bank_bus_adr [3:0]
101390     connect \B 4'1000
101391     connect \Y $eq$ls180.v:5878$1266_Y
101392   end
101393   attribute \src "ls180.v:5888.32-5888.78"
101394   cell $eq $eq$ls180.v:5888$1268
101395     parameter \A_SIGNED 0
101396     parameter \A_WIDTH 5
101397     parameter \B_SIGNED 0
101398     parameter \B_WIDTH 4
101399     parameter \Y_WIDTH 1
101400     connect \A \builder_interface4_bank_bus_adr [13:9]
101401     connect \B 4'1010
101402     connect \Y $eq$ls180.v:5888$1268_Y
101403   end
101404   attribute \src "ls180.v:5890.98-5890.142"
101405   cell $eq $eq$ls180.v:5890$1270
101406     parameter \A_SIGNED 0
101407     parameter \A_WIDTH 4
101408     parameter \B_SIGNED 0
101409     parameter \B_WIDTH 1
101410     parameter \Y_WIDTH 1
101411     connect \A \builder_interface4_bank_bus_adr [3:0]
101412     connect \B 1'0
101413     connect \Y $eq$ls180.v:5890$1270_Y
101414   end
101415   attribute \src "ls180.v:5891.101-5891.145"
101416   cell $eq $eq$ls180.v:5891$1274
101417     parameter \A_SIGNED 0
101418     parameter \A_WIDTH 4
101419     parameter \B_SIGNED 0
101420     parameter \B_WIDTH 1
101421     parameter \Y_WIDTH 1
101422     connect \A \builder_interface4_bank_bus_adr [3:0]
101423     connect \B 1'0
101424     connect \Y $eq$ls180.v:5891$1274_Y
101425   end
101426   attribute \src "ls180.v:5893.97-5893.141"
101427   cell $eq $eq$ls180.v:5893$1277
101428     parameter \A_SIGNED 0
101429     parameter \A_WIDTH 4
101430     parameter \B_SIGNED 0
101431     parameter \B_WIDTH 1
101432     parameter \Y_WIDTH 1
101433     connect \A \builder_interface4_bank_bus_adr [3:0]
101434     connect \B 1'1
101435     connect \Y $eq$ls180.v:5893$1277_Y
101436   end
101437   attribute \src "ls180.v:5894.100-5894.144"
101438   cell $eq $eq$ls180.v:5894$1281
101439     parameter \A_SIGNED 0
101440     parameter \A_WIDTH 4
101441     parameter \B_SIGNED 0
101442     parameter \B_WIDTH 1
101443     parameter \Y_WIDTH 1
101444     connect \A \builder_interface4_bank_bus_adr [3:0]
101445     connect \B 1'1
101446     connect \Y $eq$ls180.v:5894$1281_Y
101447   end
101448   attribute \src "ls180.v:5896.97-5896.141"
101449   cell $eq $eq$ls180.v:5896$1284
101450     parameter \A_SIGNED 0
101451     parameter \A_WIDTH 4
101452     parameter \B_SIGNED 0
101453     parameter \B_WIDTH 2
101454     parameter \Y_WIDTH 1
101455     connect \A \builder_interface4_bank_bus_adr [3:0]
101456     connect \B 2'10
101457     connect \Y $eq$ls180.v:5896$1284_Y
101458   end
101459   attribute \src "ls180.v:5897.100-5897.144"
101460   cell $eq $eq$ls180.v:5897$1288
101461     parameter \A_SIGNED 0
101462     parameter \A_WIDTH 4
101463     parameter \B_SIGNED 0
101464     parameter \B_WIDTH 2
101465     parameter \Y_WIDTH 1
101466     connect \A \builder_interface4_bank_bus_adr [3:0]
101467     connect \B 2'10
101468     connect \Y $eq$ls180.v:5897$1288_Y
101469   end
101470   attribute \src "ls180.v:5899.97-5899.141"
101471   cell $eq $eq$ls180.v:5899$1291
101472     parameter \A_SIGNED 0
101473     parameter \A_WIDTH 4
101474     parameter \B_SIGNED 0
101475     parameter \B_WIDTH 2
101476     parameter \Y_WIDTH 1
101477     connect \A \builder_interface4_bank_bus_adr [3:0]
101478     connect \B 2'11
101479     connect \Y $eq$ls180.v:5899$1291_Y
101480   end
101481   attribute \src "ls180.v:5900.100-5900.144"
101482   cell $eq $eq$ls180.v:5900$1295
101483     parameter \A_SIGNED 0
101484     parameter \A_WIDTH 4
101485     parameter \B_SIGNED 0
101486     parameter \B_WIDTH 2
101487     parameter \Y_WIDTH 1
101488     connect \A \builder_interface4_bank_bus_adr [3:0]
101489     connect \B 2'11
101490     connect \Y $eq$ls180.v:5900$1295_Y
101491   end
101492   attribute \src "ls180.v:5902.97-5902.141"
101493   cell $eq $eq$ls180.v:5902$1298
101494     parameter \A_SIGNED 0
101495     parameter \A_WIDTH 4
101496     parameter \B_SIGNED 0
101497     parameter \B_WIDTH 3
101498     parameter \Y_WIDTH 1
101499     connect \A \builder_interface4_bank_bus_adr [3:0]
101500     connect \B 3'100
101501     connect \Y $eq$ls180.v:5902$1298_Y
101502   end
101503   attribute \src "ls180.v:5903.100-5903.144"
101504   cell $eq $eq$ls180.v:5903$1302
101505     parameter \A_SIGNED 0
101506     parameter \A_WIDTH 4
101507     parameter \B_SIGNED 0
101508     parameter \B_WIDTH 3
101509     parameter \Y_WIDTH 1
101510     connect \A \builder_interface4_bank_bus_adr [3:0]
101511     connect \B 3'100
101512     connect \Y $eq$ls180.v:5903$1302_Y
101513   end
101514   attribute \src "ls180.v:5905.98-5905.142"
101515   cell $eq $eq$ls180.v:5905$1305
101516     parameter \A_SIGNED 0
101517     parameter \A_WIDTH 4
101518     parameter \B_SIGNED 0
101519     parameter \B_WIDTH 3
101520     parameter \Y_WIDTH 1
101521     connect \A \builder_interface4_bank_bus_adr [3:0]
101522     connect \B 3'101
101523     connect \Y $eq$ls180.v:5905$1305_Y
101524   end
101525   attribute \src "ls180.v:5906.101-5906.145"
101526   cell $eq $eq$ls180.v:5906$1309
101527     parameter \A_SIGNED 0
101528     parameter \A_WIDTH 4
101529     parameter \B_SIGNED 0
101530     parameter \B_WIDTH 3
101531     parameter \Y_WIDTH 1
101532     connect \A \builder_interface4_bank_bus_adr [3:0]
101533     connect \B 3'101
101534     connect \Y $eq$ls180.v:5906$1309_Y
101535   end
101536   attribute \src "ls180.v:5908.98-5908.142"
101537   cell $eq $eq$ls180.v:5908$1312
101538     parameter \A_SIGNED 0
101539     parameter \A_WIDTH 4
101540     parameter \B_SIGNED 0
101541     parameter \B_WIDTH 3
101542     parameter \Y_WIDTH 1
101543     connect \A \builder_interface4_bank_bus_adr [3:0]
101544     connect \B 3'110
101545     connect \Y $eq$ls180.v:5908$1312_Y
101546   end
101547   attribute \src "ls180.v:5909.101-5909.145"
101548   cell $eq $eq$ls180.v:5909$1316
101549     parameter \A_SIGNED 0
101550     parameter \A_WIDTH 4
101551     parameter \B_SIGNED 0
101552     parameter \B_WIDTH 3
101553     parameter \Y_WIDTH 1
101554     connect \A \builder_interface4_bank_bus_adr [3:0]
101555     connect \B 3'110
101556     connect \Y $eq$ls180.v:5909$1316_Y
101557   end
101558   attribute \src "ls180.v:5911.98-5911.142"
101559   cell $eq $eq$ls180.v:5911$1319
101560     parameter \A_SIGNED 0
101561     parameter \A_WIDTH 4
101562     parameter \B_SIGNED 0
101563     parameter \B_WIDTH 3
101564     parameter \Y_WIDTH 1
101565     connect \A \builder_interface4_bank_bus_adr [3:0]
101566     connect \B 3'111
101567     connect \Y $eq$ls180.v:5911$1319_Y
101568   end
101569   attribute \src "ls180.v:5912.101-5912.145"
101570   cell $eq $eq$ls180.v:5912$1323
101571     parameter \A_SIGNED 0
101572     parameter \A_WIDTH 4
101573     parameter \B_SIGNED 0
101574     parameter \B_WIDTH 3
101575     parameter \Y_WIDTH 1
101576     connect \A \builder_interface4_bank_bus_adr [3:0]
101577     connect \B 3'111
101578     connect \Y $eq$ls180.v:5912$1323_Y
101579   end
101580   attribute \src "ls180.v:5914.98-5914.142"
101581   cell $eq $eq$ls180.v:5914$1326
101582     parameter \A_SIGNED 0
101583     parameter \A_WIDTH 4
101584     parameter \B_SIGNED 0
101585     parameter \B_WIDTH 4
101586     parameter \Y_WIDTH 1
101587     connect \A \builder_interface4_bank_bus_adr [3:0]
101588     connect \B 4'1000
101589     connect \Y $eq$ls180.v:5914$1326_Y
101590   end
101591   attribute \src "ls180.v:5915.101-5915.145"
101592   cell $eq $eq$ls180.v:5915$1330
101593     parameter \A_SIGNED 0
101594     parameter \A_WIDTH 4
101595     parameter \B_SIGNED 0
101596     parameter \B_WIDTH 4
101597     parameter \Y_WIDTH 1
101598     connect \A \builder_interface4_bank_bus_adr [3:0]
101599     connect \B 4'1000
101600     connect \Y $eq$ls180.v:5915$1330_Y
101601   end
101602   attribute \src "ls180.v:5925.32-5925.78"
101603   cell $eq $eq$ls180.v:5925$1332
101604     parameter \A_SIGNED 0
101605     parameter \A_WIDTH 5
101606     parameter \B_SIGNED 0
101607     parameter \B_WIDTH 4
101608     parameter \Y_WIDTH 1
101609     connect \A \builder_interface5_bank_bus_adr [13:9]
101610     connect \B 4'1110
101611     connect \Y $eq$ls180.v:5925$1332_Y
101612   end
101613   attribute \src "ls180.v:5927.100-5927.144"
101614   cell $eq $eq$ls180.v:5927$1334
101615     parameter \A_SIGNED 0
101616     parameter \A_WIDTH 4
101617     parameter \B_SIGNED 0
101618     parameter \B_WIDTH 1
101619     parameter \Y_WIDTH 1
101620     connect \A \builder_interface5_bank_bus_adr [3:0]
101621     connect \B 1'0
101622     connect \Y $eq$ls180.v:5927$1334_Y
101623   end
101624   attribute \src "ls180.v:5928.103-5928.147"
101625   cell $eq $eq$ls180.v:5928$1338
101626     parameter \A_SIGNED 0
101627     parameter \A_WIDTH 4
101628     parameter \B_SIGNED 0
101629     parameter \B_WIDTH 1
101630     parameter \Y_WIDTH 1
101631     connect \A \builder_interface5_bank_bus_adr [3:0]
101632     connect \B 1'0
101633     connect \Y $eq$ls180.v:5928$1338_Y
101634   end
101635   attribute \src "ls180.v:5930.100-5930.144"
101636   cell $eq $eq$ls180.v:5930$1341
101637     parameter \A_SIGNED 0
101638     parameter \A_WIDTH 4
101639     parameter \B_SIGNED 0
101640     parameter \B_WIDTH 1
101641     parameter \Y_WIDTH 1
101642     connect \A \builder_interface5_bank_bus_adr [3:0]
101643     connect \B 1'1
101644     connect \Y $eq$ls180.v:5930$1341_Y
101645   end
101646   attribute \src "ls180.v:5931.103-5931.147"
101647   cell $eq $eq$ls180.v:5931$1345
101648     parameter \A_SIGNED 0
101649     parameter \A_WIDTH 4
101650     parameter \B_SIGNED 0
101651     parameter \B_WIDTH 1
101652     parameter \Y_WIDTH 1
101653     connect \A \builder_interface5_bank_bus_adr [3:0]
101654     connect \B 1'1
101655     connect \Y $eq$ls180.v:5931$1345_Y
101656   end
101657   attribute \src "ls180.v:5933.100-5933.144"
101658   cell $eq $eq$ls180.v:5933$1348
101659     parameter \A_SIGNED 0
101660     parameter \A_WIDTH 4
101661     parameter \B_SIGNED 0
101662     parameter \B_WIDTH 2
101663     parameter \Y_WIDTH 1
101664     connect \A \builder_interface5_bank_bus_adr [3:0]
101665     connect \B 2'10
101666     connect \Y $eq$ls180.v:5933$1348_Y
101667   end
101668   attribute \src "ls180.v:5934.103-5934.147"
101669   cell $eq $eq$ls180.v:5934$1352
101670     parameter \A_SIGNED 0
101671     parameter \A_WIDTH 4
101672     parameter \B_SIGNED 0
101673     parameter \B_WIDTH 2
101674     parameter \Y_WIDTH 1
101675     connect \A \builder_interface5_bank_bus_adr [3:0]
101676     connect \B 2'10
101677     connect \Y $eq$ls180.v:5934$1352_Y
101678   end
101679   attribute \src "ls180.v:5936.100-5936.144"
101680   cell $eq $eq$ls180.v:5936$1355
101681     parameter \A_SIGNED 0
101682     parameter \A_WIDTH 4
101683     parameter \B_SIGNED 0
101684     parameter \B_WIDTH 2
101685     parameter \Y_WIDTH 1
101686     connect \A \builder_interface5_bank_bus_adr [3:0]
101687     connect \B 2'11
101688     connect \Y $eq$ls180.v:5936$1355_Y
101689   end
101690   attribute \src "ls180.v:5937.103-5937.147"
101691   cell $eq $eq$ls180.v:5937$1359
101692     parameter \A_SIGNED 0
101693     parameter \A_WIDTH 4
101694     parameter \B_SIGNED 0
101695     parameter \B_WIDTH 2
101696     parameter \Y_WIDTH 1
101697     connect \A \builder_interface5_bank_bus_adr [3:0]
101698     connect \B 2'11
101699     connect \Y $eq$ls180.v:5937$1359_Y
101700   end
101701   attribute \src "ls180.v:5939.100-5939.144"
101702   cell $eq $eq$ls180.v:5939$1362
101703     parameter \A_SIGNED 0
101704     parameter \A_WIDTH 4
101705     parameter \B_SIGNED 0
101706     parameter \B_WIDTH 3
101707     parameter \Y_WIDTH 1
101708     connect \A \builder_interface5_bank_bus_adr [3:0]
101709     connect \B 3'100
101710     connect \Y $eq$ls180.v:5939$1362_Y
101711   end
101712   attribute \src "ls180.v:5940.103-5940.147"
101713   cell $eq $eq$ls180.v:5940$1366
101714     parameter \A_SIGNED 0
101715     parameter \A_WIDTH 4
101716     parameter \B_SIGNED 0
101717     parameter \B_WIDTH 3
101718     parameter \Y_WIDTH 1
101719     connect \A \builder_interface5_bank_bus_adr [3:0]
101720     connect \B 3'100
101721     connect \Y $eq$ls180.v:5940$1366_Y
101722   end
101723   attribute \src "ls180.v:5942.100-5942.144"
101724   cell $eq $eq$ls180.v:5942$1369
101725     parameter \A_SIGNED 0
101726     parameter \A_WIDTH 4
101727     parameter \B_SIGNED 0
101728     parameter \B_WIDTH 3
101729     parameter \Y_WIDTH 1
101730     connect \A \builder_interface5_bank_bus_adr [3:0]
101731     connect \B 3'101
101732     connect \Y $eq$ls180.v:5942$1369_Y
101733   end
101734   attribute \src "ls180.v:5943.103-5943.147"
101735   cell $eq $eq$ls180.v:5943$1373
101736     parameter \A_SIGNED 0
101737     parameter \A_WIDTH 4
101738     parameter \B_SIGNED 0
101739     parameter \B_WIDTH 3
101740     parameter \Y_WIDTH 1
101741     connect \A \builder_interface5_bank_bus_adr [3:0]
101742     connect \B 3'101
101743     connect \Y $eq$ls180.v:5943$1373_Y
101744   end
101745   attribute \src "ls180.v:5945.100-5945.144"
101746   cell $eq $eq$ls180.v:5945$1376
101747     parameter \A_SIGNED 0
101748     parameter \A_WIDTH 4
101749     parameter \B_SIGNED 0
101750     parameter \B_WIDTH 3
101751     parameter \Y_WIDTH 1
101752     connect \A \builder_interface5_bank_bus_adr [3:0]
101753     connect \B 3'110
101754     connect \Y $eq$ls180.v:5945$1376_Y
101755   end
101756   attribute \src "ls180.v:5946.103-5946.147"
101757   cell $eq $eq$ls180.v:5946$1380
101758     parameter \A_SIGNED 0
101759     parameter \A_WIDTH 4
101760     parameter \B_SIGNED 0
101761     parameter \B_WIDTH 3
101762     parameter \Y_WIDTH 1
101763     connect \A \builder_interface5_bank_bus_adr [3:0]
101764     connect \B 3'110
101765     connect \Y $eq$ls180.v:5946$1380_Y
101766   end
101767   attribute \src "ls180.v:5948.100-5948.144"
101768   cell $eq $eq$ls180.v:5948$1383
101769     parameter \A_SIGNED 0
101770     parameter \A_WIDTH 4
101771     parameter \B_SIGNED 0
101772     parameter \B_WIDTH 3
101773     parameter \Y_WIDTH 1
101774     connect \A \builder_interface5_bank_bus_adr [3:0]
101775     connect \B 3'111
101776     connect \Y $eq$ls180.v:5948$1383_Y
101777   end
101778   attribute \src "ls180.v:5949.103-5949.147"
101779   cell $eq $eq$ls180.v:5949$1387
101780     parameter \A_SIGNED 0
101781     parameter \A_WIDTH 4
101782     parameter \B_SIGNED 0
101783     parameter \B_WIDTH 3
101784     parameter \Y_WIDTH 1
101785     connect \A \builder_interface5_bank_bus_adr [3:0]
101786     connect \B 3'111
101787     connect \Y $eq$ls180.v:5949$1387_Y
101788   end
101789   attribute \src "ls180.v:5951.102-5951.146"
101790   cell $eq $eq$ls180.v:5951$1390
101791     parameter \A_SIGNED 0
101792     parameter \A_WIDTH 4
101793     parameter \B_SIGNED 0
101794     parameter \B_WIDTH 4
101795     parameter \Y_WIDTH 1
101796     connect \A \builder_interface5_bank_bus_adr [3:0]
101797     connect \B 4'1000
101798     connect \Y $eq$ls180.v:5951$1390_Y
101799   end
101800   attribute \src "ls180.v:5952.105-5952.149"
101801   cell $eq $eq$ls180.v:5952$1394
101802     parameter \A_SIGNED 0
101803     parameter \A_WIDTH 4
101804     parameter \B_SIGNED 0
101805     parameter \B_WIDTH 4
101806     parameter \Y_WIDTH 1
101807     connect \A \builder_interface5_bank_bus_adr [3:0]
101808     connect \B 4'1000
101809     connect \Y $eq$ls180.v:5952$1394_Y
101810   end
101811   attribute \src "ls180.v:5954.102-5954.146"
101812   cell $eq $eq$ls180.v:5954$1397
101813     parameter \A_SIGNED 0
101814     parameter \A_WIDTH 4
101815     parameter \B_SIGNED 0
101816     parameter \B_WIDTH 4
101817     parameter \Y_WIDTH 1
101818     connect \A \builder_interface5_bank_bus_adr [3:0]
101819     connect \B 4'1001
101820     connect \Y $eq$ls180.v:5954$1397_Y
101821   end
101822   attribute \src "ls180.v:5955.105-5955.149"
101823   cell $eq $eq$ls180.v:5955$1401
101824     parameter \A_SIGNED 0
101825     parameter \A_WIDTH 4
101826     parameter \B_SIGNED 0
101827     parameter \B_WIDTH 4
101828     parameter \Y_WIDTH 1
101829     connect \A \builder_interface5_bank_bus_adr [3:0]
101830     connect \B 4'1001
101831     connect \Y $eq$ls180.v:5955$1401_Y
101832   end
101833   attribute \src "ls180.v:5957.102-5957.147"
101834   cell $eq $eq$ls180.v:5957$1404
101835     parameter \A_SIGNED 0
101836     parameter \A_WIDTH 4
101837     parameter \B_SIGNED 0
101838     parameter \B_WIDTH 4
101839     parameter \Y_WIDTH 1
101840     connect \A \builder_interface5_bank_bus_adr [3:0]
101841     connect \B 4'1010
101842     connect \Y $eq$ls180.v:5957$1404_Y
101843   end
101844   attribute \src "ls180.v:5958.105-5958.150"
101845   cell $eq $eq$ls180.v:5958$1408
101846     parameter \A_SIGNED 0
101847     parameter \A_WIDTH 4
101848     parameter \B_SIGNED 0
101849     parameter \B_WIDTH 4
101850     parameter \Y_WIDTH 1
101851     connect \A \builder_interface5_bank_bus_adr [3:0]
101852     connect \B 4'1010
101853     connect \Y $eq$ls180.v:5958$1408_Y
101854   end
101855   attribute \src "ls180.v:5960.102-5960.147"
101856   cell $eq $eq$ls180.v:5960$1411
101857     parameter \A_SIGNED 0
101858     parameter \A_WIDTH 4
101859     parameter \B_SIGNED 0
101860     parameter \B_WIDTH 4
101861     parameter \Y_WIDTH 1
101862     connect \A \builder_interface5_bank_bus_adr [3:0]
101863     connect \B 4'1011
101864     connect \Y $eq$ls180.v:5960$1411_Y
101865   end
101866   attribute \src "ls180.v:5961.105-5961.150"
101867   cell $eq $eq$ls180.v:5961$1415
101868     parameter \A_SIGNED 0
101869     parameter \A_WIDTH 4
101870     parameter \B_SIGNED 0
101871     parameter \B_WIDTH 4
101872     parameter \Y_WIDTH 1
101873     connect \A \builder_interface5_bank_bus_adr [3:0]
101874     connect \B 4'1011
101875     connect \Y $eq$ls180.v:5961$1415_Y
101876   end
101877   attribute \src "ls180.v:5963.102-5963.147"
101878   cell $eq $eq$ls180.v:5963$1418
101879     parameter \A_SIGNED 0
101880     parameter \A_WIDTH 4
101881     parameter \B_SIGNED 0
101882     parameter \B_WIDTH 4
101883     parameter \Y_WIDTH 1
101884     connect \A \builder_interface5_bank_bus_adr [3:0]
101885     connect \B 4'1100
101886     connect \Y $eq$ls180.v:5963$1418_Y
101887   end
101888   attribute \src "ls180.v:5964.105-5964.150"
101889   cell $eq $eq$ls180.v:5964$1422
101890     parameter \A_SIGNED 0
101891     parameter \A_WIDTH 4
101892     parameter \B_SIGNED 0
101893     parameter \B_WIDTH 4
101894     parameter \Y_WIDTH 1
101895     connect \A \builder_interface5_bank_bus_adr [3:0]
101896     connect \B 4'1100
101897     connect \Y $eq$ls180.v:5964$1422_Y
101898   end
101899   attribute \src "ls180.v:5966.99-5966.144"
101900   cell $eq $eq$ls180.v:5966$1425
101901     parameter \A_SIGNED 0
101902     parameter \A_WIDTH 4
101903     parameter \B_SIGNED 0
101904     parameter \B_WIDTH 4
101905     parameter \Y_WIDTH 1
101906     connect \A \builder_interface5_bank_bus_adr [3:0]
101907     connect \B 4'1101
101908     connect \Y $eq$ls180.v:5966$1425_Y
101909   end
101910   attribute \src "ls180.v:5967.102-5967.147"
101911   cell $eq $eq$ls180.v:5967$1429
101912     parameter \A_SIGNED 0
101913     parameter \A_WIDTH 4
101914     parameter \B_SIGNED 0
101915     parameter \B_WIDTH 4
101916     parameter \Y_WIDTH 1
101917     connect \A \builder_interface5_bank_bus_adr [3:0]
101918     connect \B 4'1101
101919     connect \Y $eq$ls180.v:5967$1429_Y
101920   end
101921   attribute \src "ls180.v:5969.100-5969.145"
101922   cell $eq $eq$ls180.v:5969$1432
101923     parameter \A_SIGNED 0
101924     parameter \A_WIDTH 4
101925     parameter \B_SIGNED 0
101926     parameter \B_WIDTH 4
101927     parameter \Y_WIDTH 1
101928     connect \A \builder_interface5_bank_bus_adr [3:0]
101929     connect \B 4'1110
101930     connect \Y $eq$ls180.v:5969$1432_Y
101931   end
101932   attribute \src "ls180.v:5970.103-5970.148"
101933   cell $eq $eq$ls180.v:5970$1436
101934     parameter \A_SIGNED 0
101935     parameter \A_WIDTH 4
101936     parameter \B_SIGNED 0
101937     parameter \B_WIDTH 4
101938     parameter \Y_WIDTH 1
101939     connect \A \builder_interface5_bank_bus_adr [3:0]
101940     connect \B 4'1110
101941     connect \Y $eq$ls180.v:5970$1436_Y
101942   end
101943   attribute \src "ls180.v:5987.32-5987.78"
101944   cell $eq $eq$ls180.v:5987$1438
101945     parameter \A_SIGNED 0
101946     parameter \A_WIDTH 5
101947     parameter \B_SIGNED 0
101948     parameter \B_WIDTH 4
101949     parameter \Y_WIDTH 1
101950     connect \A \builder_interface6_bank_bus_adr [13:9]
101951     connect \B 4'1101
101952     connect \Y $eq$ls180.v:5987$1438_Y
101953   end
101954   attribute \src "ls180.v:5989.104-5989.148"
101955   cell $eq $eq$ls180.v:5989$1440
101956     parameter \A_SIGNED 0
101957     parameter \A_WIDTH 6
101958     parameter \B_SIGNED 0
101959     parameter \B_WIDTH 1
101960     parameter \Y_WIDTH 1
101961     connect \A \builder_interface6_bank_bus_adr [5:0]
101962     connect \B 1'0
101963     connect \Y $eq$ls180.v:5989$1440_Y
101964   end
101965   attribute \src "ls180.v:5990.107-5990.151"
101966   cell $eq $eq$ls180.v:5990$1444
101967     parameter \A_SIGNED 0
101968     parameter \A_WIDTH 6
101969     parameter \B_SIGNED 0
101970     parameter \B_WIDTH 1
101971     parameter \Y_WIDTH 1
101972     connect \A \builder_interface6_bank_bus_adr [5:0]
101973     connect \B 1'0
101974     connect \Y $eq$ls180.v:5990$1444_Y
101975   end
101976   attribute \src "ls180.v:5992.104-5992.148"
101977   cell $eq $eq$ls180.v:5992$1447
101978     parameter \A_SIGNED 0
101979     parameter \A_WIDTH 6
101980     parameter \B_SIGNED 0
101981     parameter \B_WIDTH 1
101982     parameter \Y_WIDTH 1
101983     connect \A \builder_interface6_bank_bus_adr [5:0]
101984     connect \B 1'1
101985     connect \Y $eq$ls180.v:5992$1447_Y
101986   end
101987   attribute \src "ls180.v:5993.107-5993.151"
101988   cell $eq $eq$ls180.v:5993$1451
101989     parameter \A_SIGNED 0
101990     parameter \A_WIDTH 6
101991     parameter \B_SIGNED 0
101992     parameter \B_WIDTH 1
101993     parameter \Y_WIDTH 1
101994     connect \A \builder_interface6_bank_bus_adr [5:0]
101995     connect \B 1'1
101996     connect \Y $eq$ls180.v:5993$1451_Y
101997   end
101998   attribute \src "ls180.v:5995.104-5995.148"
101999   cell $eq $eq$ls180.v:5995$1454
102000     parameter \A_SIGNED 0
102001     parameter \A_WIDTH 6
102002     parameter \B_SIGNED 0
102003     parameter \B_WIDTH 2
102004     parameter \Y_WIDTH 1
102005     connect \A \builder_interface6_bank_bus_adr [5:0]
102006     connect \B 2'10
102007     connect \Y $eq$ls180.v:5995$1454_Y
102008   end
102009   attribute \src "ls180.v:5996.107-5996.151"
102010   cell $eq $eq$ls180.v:5996$1458
102011     parameter \A_SIGNED 0
102012     parameter \A_WIDTH 6
102013     parameter \B_SIGNED 0
102014     parameter \B_WIDTH 2
102015     parameter \Y_WIDTH 1
102016     connect \A \builder_interface6_bank_bus_adr [5:0]
102017     connect \B 2'10
102018     connect \Y $eq$ls180.v:5996$1458_Y
102019   end
102020   attribute \src "ls180.v:5998.104-5998.148"
102021   cell $eq $eq$ls180.v:5998$1461
102022     parameter \A_SIGNED 0
102023     parameter \A_WIDTH 6
102024     parameter \B_SIGNED 0
102025     parameter \B_WIDTH 2
102026     parameter \Y_WIDTH 1
102027     connect \A \builder_interface6_bank_bus_adr [5:0]
102028     connect \B 2'11
102029     connect \Y $eq$ls180.v:5998$1461_Y
102030   end
102031   attribute \src "ls180.v:5999.107-5999.151"
102032   cell $eq $eq$ls180.v:5999$1465
102033     parameter \A_SIGNED 0
102034     parameter \A_WIDTH 6
102035     parameter \B_SIGNED 0
102036     parameter \B_WIDTH 2
102037     parameter \Y_WIDTH 1
102038     connect \A \builder_interface6_bank_bus_adr [5:0]
102039     connect \B 2'11
102040     connect \Y $eq$ls180.v:5999$1465_Y
102041   end
102042   attribute \src "ls180.v:6001.103-6001.147"
102043   cell $eq $eq$ls180.v:6001$1468
102044     parameter \A_SIGNED 0
102045     parameter \A_WIDTH 6
102046     parameter \B_SIGNED 0
102047     parameter \B_WIDTH 3
102048     parameter \Y_WIDTH 1
102049     connect \A \builder_interface6_bank_bus_adr [5:0]
102050     connect \B 3'100
102051     connect \Y $eq$ls180.v:6001$1468_Y
102052   end
102053   attribute \src "ls180.v:6002.106-6002.150"
102054   cell $eq $eq$ls180.v:6002$1472
102055     parameter \A_SIGNED 0
102056     parameter \A_WIDTH 6
102057     parameter \B_SIGNED 0
102058     parameter \B_WIDTH 3
102059     parameter \Y_WIDTH 1
102060     connect \A \builder_interface6_bank_bus_adr [5:0]
102061     connect \B 3'100
102062     connect \Y $eq$ls180.v:6002$1472_Y
102063   end
102064   attribute \src "ls180.v:6004.103-6004.147"
102065   cell $eq $eq$ls180.v:6004$1475
102066     parameter \A_SIGNED 0
102067     parameter \A_WIDTH 6
102068     parameter \B_SIGNED 0
102069     parameter \B_WIDTH 3
102070     parameter \Y_WIDTH 1
102071     connect \A \builder_interface6_bank_bus_adr [5:0]
102072     connect \B 3'101
102073     connect \Y $eq$ls180.v:6004$1475_Y
102074   end
102075   attribute \src "ls180.v:6005.106-6005.150"
102076   cell $eq $eq$ls180.v:6005$1479
102077     parameter \A_SIGNED 0
102078     parameter \A_WIDTH 6
102079     parameter \B_SIGNED 0
102080     parameter \B_WIDTH 3
102081     parameter \Y_WIDTH 1
102082     connect \A \builder_interface6_bank_bus_adr [5:0]
102083     connect \B 3'101
102084     connect \Y $eq$ls180.v:6005$1479_Y
102085   end
102086   attribute \src "ls180.v:6007.103-6007.147"
102087   cell $eq $eq$ls180.v:6007$1482
102088     parameter \A_SIGNED 0
102089     parameter \A_WIDTH 6
102090     parameter \B_SIGNED 0
102091     parameter \B_WIDTH 3
102092     parameter \Y_WIDTH 1
102093     connect \A \builder_interface6_bank_bus_adr [5:0]
102094     connect \B 3'110
102095     connect \Y $eq$ls180.v:6007$1482_Y
102096   end
102097   attribute \src "ls180.v:6008.106-6008.150"
102098   cell $eq $eq$ls180.v:6008$1486
102099     parameter \A_SIGNED 0
102100     parameter \A_WIDTH 6
102101     parameter \B_SIGNED 0
102102     parameter \B_WIDTH 3
102103     parameter \Y_WIDTH 1
102104     connect \A \builder_interface6_bank_bus_adr [5:0]
102105     connect \B 3'110
102106     connect \Y $eq$ls180.v:6008$1486_Y
102107   end
102108   attribute \src "ls180.v:6010.103-6010.147"
102109   cell $eq $eq$ls180.v:6010$1489
102110     parameter \A_SIGNED 0
102111     parameter \A_WIDTH 6
102112     parameter \B_SIGNED 0
102113     parameter \B_WIDTH 3
102114     parameter \Y_WIDTH 1
102115     connect \A \builder_interface6_bank_bus_adr [5:0]
102116     connect \B 3'111
102117     connect \Y $eq$ls180.v:6010$1489_Y
102118   end
102119   attribute \src "ls180.v:6011.106-6011.150"
102120   cell $eq $eq$ls180.v:6011$1493
102121     parameter \A_SIGNED 0
102122     parameter \A_WIDTH 6
102123     parameter \B_SIGNED 0
102124     parameter \B_WIDTH 3
102125     parameter \Y_WIDTH 1
102126     connect \A \builder_interface6_bank_bus_adr [5:0]
102127     connect \B 3'111
102128     connect \Y $eq$ls180.v:6011$1493_Y
102129   end
102130   attribute \src "ls180.v:6013.94-6013.138"
102131   cell $eq $eq$ls180.v:6013$1496
102132     parameter \A_SIGNED 0
102133     parameter \A_WIDTH 6
102134     parameter \B_SIGNED 0
102135     parameter \B_WIDTH 4
102136     parameter \Y_WIDTH 1
102137     connect \A \builder_interface6_bank_bus_adr [5:0]
102138     connect \B 4'1000
102139     connect \Y $eq$ls180.v:6013$1496_Y
102140   end
102141   attribute \src "ls180.v:6014.97-6014.141"
102142   cell $eq $eq$ls180.v:6014$1500
102143     parameter \A_SIGNED 0
102144     parameter \A_WIDTH 6
102145     parameter \B_SIGNED 0
102146     parameter \B_WIDTH 4
102147     parameter \Y_WIDTH 1
102148     connect \A \builder_interface6_bank_bus_adr [5:0]
102149     connect \B 4'1000
102150     connect \Y $eq$ls180.v:6014$1500_Y
102151   end
102152   attribute \src "ls180.v:6016.105-6016.149"
102153   cell $eq $eq$ls180.v:6016$1503
102154     parameter \A_SIGNED 0
102155     parameter \A_WIDTH 6
102156     parameter \B_SIGNED 0
102157     parameter \B_WIDTH 4
102158     parameter \Y_WIDTH 1
102159     connect \A \builder_interface6_bank_bus_adr [5:0]
102160     connect \B 4'1001
102161     connect \Y $eq$ls180.v:6016$1503_Y
102162   end
102163   attribute \src "ls180.v:6017.108-6017.152"
102164   cell $eq $eq$ls180.v:6017$1507
102165     parameter \A_SIGNED 0
102166     parameter \A_WIDTH 6
102167     parameter \B_SIGNED 0
102168     parameter \B_WIDTH 4
102169     parameter \Y_WIDTH 1
102170     connect \A \builder_interface6_bank_bus_adr [5:0]
102171     connect \B 4'1001
102172     connect \Y $eq$ls180.v:6017$1507_Y
102173   end
102174   attribute \src "ls180.v:6019.105-6019.150"
102175   cell $eq $eq$ls180.v:6019$1510
102176     parameter \A_SIGNED 0
102177     parameter \A_WIDTH 6
102178     parameter \B_SIGNED 0
102179     parameter \B_WIDTH 4
102180     parameter \Y_WIDTH 1
102181     connect \A \builder_interface6_bank_bus_adr [5:0]
102182     connect \B 4'1010
102183     connect \Y $eq$ls180.v:6019$1510_Y
102184   end
102185   attribute \src "ls180.v:6020.108-6020.153"
102186   cell $eq $eq$ls180.v:6020$1514
102187     parameter \A_SIGNED 0
102188     parameter \A_WIDTH 6
102189     parameter \B_SIGNED 0
102190     parameter \B_WIDTH 4
102191     parameter \Y_WIDTH 1
102192     connect \A \builder_interface6_bank_bus_adr [5:0]
102193     connect \B 4'1010
102194     connect \Y $eq$ls180.v:6020$1514_Y
102195   end
102196   attribute \src "ls180.v:6022.105-6022.150"
102197   cell $eq $eq$ls180.v:6022$1517
102198     parameter \A_SIGNED 0
102199     parameter \A_WIDTH 6
102200     parameter \B_SIGNED 0
102201     parameter \B_WIDTH 4
102202     parameter \Y_WIDTH 1
102203     connect \A \builder_interface6_bank_bus_adr [5:0]
102204     connect \B 4'1011
102205     connect \Y $eq$ls180.v:6022$1517_Y
102206   end
102207   attribute \src "ls180.v:6023.108-6023.153"
102208   cell $eq $eq$ls180.v:6023$1521
102209     parameter \A_SIGNED 0
102210     parameter \A_WIDTH 6
102211     parameter \B_SIGNED 0
102212     parameter \B_WIDTH 4
102213     parameter \Y_WIDTH 1
102214     connect \A \builder_interface6_bank_bus_adr [5:0]
102215     connect \B 4'1011
102216     connect \Y $eq$ls180.v:6023$1521_Y
102217   end
102218   attribute \src "ls180.v:6025.105-6025.150"
102219   cell $eq $eq$ls180.v:6025$1524
102220     parameter \A_SIGNED 0
102221     parameter \A_WIDTH 6
102222     parameter \B_SIGNED 0
102223     parameter \B_WIDTH 4
102224     parameter \Y_WIDTH 1
102225     connect \A \builder_interface6_bank_bus_adr [5:0]
102226     connect \B 4'1100
102227     connect \Y $eq$ls180.v:6025$1524_Y
102228   end
102229   attribute \src "ls180.v:6026.108-6026.153"
102230   cell $eq $eq$ls180.v:6026$1528
102231     parameter \A_SIGNED 0
102232     parameter \A_WIDTH 6
102233     parameter \B_SIGNED 0
102234     parameter \B_WIDTH 4
102235     parameter \Y_WIDTH 1
102236     connect \A \builder_interface6_bank_bus_adr [5:0]
102237     connect \B 4'1100
102238     connect \Y $eq$ls180.v:6026$1528_Y
102239   end
102240   attribute \src "ls180.v:6028.105-6028.150"
102241   cell $eq $eq$ls180.v:6028$1531
102242     parameter \A_SIGNED 0
102243     parameter \A_WIDTH 6
102244     parameter \B_SIGNED 0
102245     parameter \B_WIDTH 4
102246     parameter \Y_WIDTH 1
102247     connect \A \builder_interface6_bank_bus_adr [5:0]
102248     connect \B 4'1101
102249     connect \Y $eq$ls180.v:6028$1531_Y
102250   end
102251   attribute \src "ls180.v:6029.108-6029.153"
102252   cell $eq $eq$ls180.v:6029$1535
102253     parameter \A_SIGNED 0
102254     parameter \A_WIDTH 6
102255     parameter \B_SIGNED 0
102256     parameter \B_WIDTH 4
102257     parameter \Y_WIDTH 1
102258     connect \A \builder_interface6_bank_bus_adr [5:0]
102259     connect \B 4'1101
102260     connect \Y $eq$ls180.v:6029$1535_Y
102261   end
102262   attribute \src "ls180.v:6031.105-6031.150"
102263   cell $eq $eq$ls180.v:6031$1538
102264     parameter \A_SIGNED 0
102265     parameter \A_WIDTH 6
102266     parameter \B_SIGNED 0
102267     parameter \B_WIDTH 4
102268     parameter \Y_WIDTH 1
102269     connect \A \builder_interface6_bank_bus_adr [5:0]
102270     connect \B 4'1110
102271     connect \Y $eq$ls180.v:6031$1538_Y
102272   end
102273   attribute \src "ls180.v:6032.108-6032.153"
102274   cell $eq $eq$ls180.v:6032$1542
102275     parameter \A_SIGNED 0
102276     parameter \A_WIDTH 6
102277     parameter \B_SIGNED 0
102278     parameter \B_WIDTH 4
102279     parameter \Y_WIDTH 1
102280     connect \A \builder_interface6_bank_bus_adr [5:0]
102281     connect \B 4'1110
102282     connect \Y $eq$ls180.v:6032$1542_Y
102283   end
102284   attribute \src "ls180.v:6034.104-6034.149"
102285   cell $eq $eq$ls180.v:6034$1545
102286     parameter \A_SIGNED 0
102287     parameter \A_WIDTH 6
102288     parameter \B_SIGNED 0
102289     parameter \B_WIDTH 4
102290     parameter \Y_WIDTH 1
102291     connect \A \builder_interface6_bank_bus_adr [5:0]
102292     connect \B 4'1111
102293     connect \Y $eq$ls180.v:6034$1545_Y
102294   end
102295   attribute \src "ls180.v:6035.107-6035.152"
102296   cell $eq $eq$ls180.v:6035$1549
102297     parameter \A_SIGNED 0
102298     parameter \A_WIDTH 6
102299     parameter \B_SIGNED 0
102300     parameter \B_WIDTH 4
102301     parameter \Y_WIDTH 1
102302     connect \A \builder_interface6_bank_bus_adr [5:0]
102303     connect \B 4'1111
102304     connect \Y $eq$ls180.v:6035$1549_Y
102305   end
102306   attribute \src "ls180.v:6037.104-6037.149"
102307   cell $eq $eq$ls180.v:6037$1552
102308     parameter \A_SIGNED 0
102309     parameter \A_WIDTH 6
102310     parameter \B_SIGNED 0
102311     parameter \B_WIDTH 5
102312     parameter \Y_WIDTH 1
102313     connect \A \builder_interface6_bank_bus_adr [5:0]
102314     connect \B 5'10000
102315     connect \Y $eq$ls180.v:6037$1552_Y
102316   end
102317   attribute \src "ls180.v:6038.107-6038.152"
102318   cell $eq $eq$ls180.v:6038$1556
102319     parameter \A_SIGNED 0
102320     parameter \A_WIDTH 6
102321     parameter \B_SIGNED 0
102322     parameter \B_WIDTH 5
102323     parameter \Y_WIDTH 1
102324     connect \A \builder_interface6_bank_bus_adr [5:0]
102325     connect \B 5'10000
102326     connect \Y $eq$ls180.v:6038$1556_Y
102327   end
102328   attribute \src "ls180.v:6040.104-6040.149"
102329   cell $eq $eq$ls180.v:6040$1559
102330     parameter \A_SIGNED 0
102331     parameter \A_WIDTH 6
102332     parameter \B_SIGNED 0
102333     parameter \B_WIDTH 5
102334     parameter \Y_WIDTH 1
102335     connect \A \builder_interface6_bank_bus_adr [5:0]
102336     connect \B 5'10001
102337     connect \Y $eq$ls180.v:6040$1559_Y
102338   end
102339   attribute \src "ls180.v:6041.107-6041.152"
102340   cell $eq $eq$ls180.v:6041$1563
102341     parameter \A_SIGNED 0
102342     parameter \A_WIDTH 6
102343     parameter \B_SIGNED 0
102344     parameter \B_WIDTH 5
102345     parameter \Y_WIDTH 1
102346     connect \A \builder_interface6_bank_bus_adr [5:0]
102347     connect \B 5'10001
102348     connect \Y $eq$ls180.v:6041$1563_Y
102349   end
102350   attribute \src "ls180.v:6043.104-6043.149"
102351   cell $eq $eq$ls180.v:6043$1566
102352     parameter \A_SIGNED 0
102353     parameter \A_WIDTH 6
102354     parameter \B_SIGNED 0
102355     parameter \B_WIDTH 5
102356     parameter \Y_WIDTH 1
102357     connect \A \builder_interface6_bank_bus_adr [5:0]
102358     connect \B 5'10010
102359     connect \Y $eq$ls180.v:6043$1566_Y
102360   end
102361   attribute \src "ls180.v:6044.107-6044.152"
102362   cell $eq $eq$ls180.v:6044$1570
102363     parameter \A_SIGNED 0
102364     parameter \A_WIDTH 6
102365     parameter \B_SIGNED 0
102366     parameter \B_WIDTH 5
102367     parameter \Y_WIDTH 1
102368     connect \A \builder_interface6_bank_bus_adr [5:0]
102369     connect \B 5'10010
102370     connect \Y $eq$ls180.v:6044$1570_Y
102371   end
102372   attribute \src "ls180.v:6046.104-6046.149"
102373   cell $eq $eq$ls180.v:6046$1573
102374     parameter \A_SIGNED 0
102375     parameter \A_WIDTH 6
102376     parameter \B_SIGNED 0
102377     parameter \B_WIDTH 5
102378     parameter \Y_WIDTH 1
102379     connect \A \builder_interface6_bank_bus_adr [5:0]
102380     connect \B 5'10011
102381     connect \Y $eq$ls180.v:6046$1573_Y
102382   end
102383   attribute \src "ls180.v:6047.107-6047.152"
102384   cell $eq $eq$ls180.v:6047$1577
102385     parameter \A_SIGNED 0
102386     parameter \A_WIDTH 6
102387     parameter \B_SIGNED 0
102388     parameter \B_WIDTH 5
102389     parameter \Y_WIDTH 1
102390     connect \A \builder_interface6_bank_bus_adr [5:0]
102391     connect \B 5'10011
102392     connect \Y $eq$ls180.v:6047$1577_Y
102393   end
102394   attribute \src "ls180.v:6049.104-6049.149"
102395   cell $eq $eq$ls180.v:6049$1580
102396     parameter \A_SIGNED 0
102397     parameter \A_WIDTH 6
102398     parameter \B_SIGNED 0
102399     parameter \B_WIDTH 5
102400     parameter \Y_WIDTH 1
102401     connect \A \builder_interface6_bank_bus_adr [5:0]
102402     connect \B 5'10100
102403     connect \Y $eq$ls180.v:6049$1580_Y
102404   end
102405   attribute \src "ls180.v:6050.107-6050.152"
102406   cell $eq $eq$ls180.v:6050$1584
102407     parameter \A_SIGNED 0
102408     parameter \A_WIDTH 6
102409     parameter \B_SIGNED 0
102410     parameter \B_WIDTH 5
102411     parameter \Y_WIDTH 1
102412     connect \A \builder_interface6_bank_bus_adr [5:0]
102413     connect \B 5'10100
102414     connect \Y $eq$ls180.v:6050$1584_Y
102415   end
102416   attribute \src "ls180.v:6052.104-6052.149"
102417   cell $eq $eq$ls180.v:6052$1587
102418     parameter \A_SIGNED 0
102419     parameter \A_WIDTH 6
102420     parameter \B_SIGNED 0
102421     parameter \B_WIDTH 5
102422     parameter \Y_WIDTH 1
102423     connect \A \builder_interface6_bank_bus_adr [5:0]
102424     connect \B 5'10101
102425     connect \Y $eq$ls180.v:6052$1587_Y
102426   end
102427   attribute \src "ls180.v:6053.107-6053.152"
102428   cell $eq $eq$ls180.v:6053$1591
102429     parameter \A_SIGNED 0
102430     parameter \A_WIDTH 6
102431     parameter \B_SIGNED 0
102432     parameter \B_WIDTH 5
102433     parameter \Y_WIDTH 1
102434     connect \A \builder_interface6_bank_bus_adr [5:0]
102435     connect \B 5'10101
102436     connect \Y $eq$ls180.v:6053$1591_Y
102437   end
102438   attribute \src "ls180.v:6055.104-6055.149"
102439   cell $eq $eq$ls180.v:6055$1594
102440     parameter \A_SIGNED 0
102441     parameter \A_WIDTH 6
102442     parameter \B_SIGNED 0
102443     parameter \B_WIDTH 5
102444     parameter \Y_WIDTH 1
102445     connect \A \builder_interface6_bank_bus_adr [5:0]
102446     connect \B 5'10110
102447     connect \Y $eq$ls180.v:6055$1594_Y
102448   end
102449   attribute \src "ls180.v:6056.107-6056.152"
102450   cell $eq $eq$ls180.v:6056$1598
102451     parameter \A_SIGNED 0
102452     parameter \A_WIDTH 6
102453     parameter \B_SIGNED 0
102454     parameter \B_WIDTH 5
102455     parameter \Y_WIDTH 1
102456     connect \A \builder_interface6_bank_bus_adr [5:0]
102457     connect \B 5'10110
102458     connect \Y $eq$ls180.v:6056$1598_Y
102459   end
102460   attribute \src "ls180.v:6058.104-6058.149"
102461   cell $eq $eq$ls180.v:6058$1601
102462     parameter \A_SIGNED 0
102463     parameter \A_WIDTH 6
102464     parameter \B_SIGNED 0
102465     parameter \B_WIDTH 5
102466     parameter \Y_WIDTH 1
102467     connect \A \builder_interface6_bank_bus_adr [5:0]
102468     connect \B 5'10111
102469     connect \Y $eq$ls180.v:6058$1601_Y
102470   end
102471   attribute \src "ls180.v:6059.107-6059.152"
102472   cell $eq $eq$ls180.v:6059$1605
102473     parameter \A_SIGNED 0
102474     parameter \A_WIDTH 6
102475     parameter \B_SIGNED 0
102476     parameter \B_WIDTH 5
102477     parameter \Y_WIDTH 1
102478     connect \A \builder_interface6_bank_bus_adr [5:0]
102479     connect \B 5'10111
102480     connect \Y $eq$ls180.v:6059$1605_Y
102481   end
102482   attribute \src "ls180.v:6061.104-6061.149"
102483   cell $eq $eq$ls180.v:6061$1608
102484     parameter \A_SIGNED 0
102485     parameter \A_WIDTH 6
102486     parameter \B_SIGNED 0
102487     parameter \B_WIDTH 5
102488     parameter \Y_WIDTH 1
102489     connect \A \builder_interface6_bank_bus_adr [5:0]
102490     connect \B 5'11000
102491     connect \Y $eq$ls180.v:6061$1608_Y
102492   end
102493   attribute \src "ls180.v:6062.107-6062.152"
102494   cell $eq $eq$ls180.v:6062$1612
102495     parameter \A_SIGNED 0
102496     parameter \A_WIDTH 6
102497     parameter \B_SIGNED 0
102498     parameter \B_WIDTH 5
102499     parameter \Y_WIDTH 1
102500     connect \A \builder_interface6_bank_bus_adr [5:0]
102501     connect \B 5'11000
102502     connect \Y $eq$ls180.v:6062$1612_Y
102503   end
102504   attribute \src "ls180.v:6064.100-6064.145"
102505   cell $eq $eq$ls180.v:6064$1615
102506     parameter \A_SIGNED 0
102507     parameter \A_WIDTH 6
102508     parameter \B_SIGNED 0
102509     parameter \B_WIDTH 5
102510     parameter \Y_WIDTH 1
102511     connect \A \builder_interface6_bank_bus_adr [5:0]
102512     connect \B 5'11001
102513     connect \Y $eq$ls180.v:6064$1615_Y
102514   end
102515   attribute \src "ls180.v:6065.103-6065.148"
102516   cell $eq $eq$ls180.v:6065$1619
102517     parameter \A_SIGNED 0
102518     parameter \A_WIDTH 6
102519     parameter \B_SIGNED 0
102520     parameter \B_WIDTH 5
102521     parameter \Y_WIDTH 1
102522     connect \A \builder_interface6_bank_bus_adr [5:0]
102523     connect \B 5'11001
102524     connect \Y $eq$ls180.v:6065$1619_Y
102525   end
102526   attribute \src "ls180.v:6067.101-6067.146"
102527   cell $eq $eq$ls180.v:6067$1622
102528     parameter \A_SIGNED 0
102529     parameter \A_WIDTH 6
102530     parameter \B_SIGNED 0
102531     parameter \B_WIDTH 5
102532     parameter \Y_WIDTH 1
102533     connect \A \builder_interface6_bank_bus_adr [5:0]
102534     connect \B 5'11010
102535     connect \Y $eq$ls180.v:6067$1622_Y
102536   end
102537   attribute \src "ls180.v:6068.104-6068.149"
102538   cell $eq $eq$ls180.v:6068$1626
102539     parameter \A_SIGNED 0
102540     parameter \A_WIDTH 6
102541     parameter \B_SIGNED 0
102542     parameter \B_WIDTH 5
102543     parameter \Y_WIDTH 1
102544     connect \A \builder_interface6_bank_bus_adr [5:0]
102545     connect \B 5'11010
102546     connect \Y $eq$ls180.v:6068$1626_Y
102547   end
102548   attribute \src "ls180.v:6070.104-6070.149"
102549   cell $eq $eq$ls180.v:6070$1629
102550     parameter \A_SIGNED 0
102551     parameter \A_WIDTH 6
102552     parameter \B_SIGNED 0
102553     parameter \B_WIDTH 5
102554     parameter \Y_WIDTH 1
102555     connect \A \builder_interface6_bank_bus_adr [5:0]
102556     connect \B 5'11011
102557     connect \Y $eq$ls180.v:6070$1629_Y
102558   end
102559   attribute \src "ls180.v:6071.107-6071.152"
102560   cell $eq $eq$ls180.v:6071$1633
102561     parameter \A_SIGNED 0
102562     parameter \A_WIDTH 6
102563     parameter \B_SIGNED 0
102564     parameter \B_WIDTH 5
102565     parameter \Y_WIDTH 1
102566     connect \A \builder_interface6_bank_bus_adr [5:0]
102567     connect \B 5'11011
102568     connect \Y $eq$ls180.v:6071$1633_Y
102569   end
102570   attribute \src "ls180.v:6073.104-6073.149"
102571   cell $eq $eq$ls180.v:6073$1636
102572     parameter \A_SIGNED 0
102573     parameter \A_WIDTH 6
102574     parameter \B_SIGNED 0
102575     parameter \B_WIDTH 5
102576     parameter \Y_WIDTH 1
102577     connect \A \builder_interface6_bank_bus_adr [5:0]
102578     connect \B 5'11100
102579     connect \Y $eq$ls180.v:6073$1636_Y
102580   end
102581   attribute \src "ls180.v:6074.107-6074.152"
102582   cell $eq $eq$ls180.v:6074$1640
102583     parameter \A_SIGNED 0
102584     parameter \A_WIDTH 6
102585     parameter \B_SIGNED 0
102586     parameter \B_WIDTH 5
102587     parameter \Y_WIDTH 1
102588     connect \A \builder_interface6_bank_bus_adr [5:0]
102589     connect \B 5'11100
102590     connect \Y $eq$ls180.v:6074$1640_Y
102591   end
102592   attribute \src "ls180.v:6076.103-6076.148"
102593   cell $eq $eq$ls180.v:6076$1643
102594     parameter \A_SIGNED 0
102595     parameter \A_WIDTH 6
102596     parameter \B_SIGNED 0
102597     parameter \B_WIDTH 5
102598     parameter \Y_WIDTH 1
102599     connect \A \builder_interface6_bank_bus_adr [5:0]
102600     connect \B 5'11101
102601     connect \Y $eq$ls180.v:6076$1643_Y
102602   end
102603   attribute \src "ls180.v:6077.106-6077.151"
102604   cell $eq $eq$ls180.v:6077$1647
102605     parameter \A_SIGNED 0
102606     parameter \A_WIDTH 6
102607     parameter \B_SIGNED 0
102608     parameter \B_WIDTH 5
102609     parameter \Y_WIDTH 1
102610     connect \A \builder_interface6_bank_bus_adr [5:0]
102611     connect \B 5'11101
102612     connect \Y $eq$ls180.v:6077$1647_Y
102613   end
102614   attribute \src "ls180.v:6079.103-6079.148"
102615   cell $eq $eq$ls180.v:6079$1650
102616     parameter \A_SIGNED 0
102617     parameter \A_WIDTH 6
102618     parameter \B_SIGNED 0
102619     parameter \B_WIDTH 5
102620     parameter \Y_WIDTH 1
102621     connect \A \builder_interface6_bank_bus_adr [5:0]
102622     connect \B 5'11110
102623     connect \Y $eq$ls180.v:6079$1650_Y
102624   end
102625   attribute \src "ls180.v:6080.106-6080.151"
102626   cell $eq $eq$ls180.v:6080$1654
102627     parameter \A_SIGNED 0
102628     parameter \A_WIDTH 6
102629     parameter \B_SIGNED 0
102630     parameter \B_WIDTH 5
102631     parameter \Y_WIDTH 1
102632     connect \A \builder_interface6_bank_bus_adr [5:0]
102633     connect \B 5'11110
102634     connect \Y $eq$ls180.v:6080$1654_Y
102635   end
102636   attribute \src "ls180.v:6082.103-6082.148"
102637   cell $eq $eq$ls180.v:6082$1657
102638     parameter \A_SIGNED 0
102639     parameter \A_WIDTH 6
102640     parameter \B_SIGNED 0
102641     parameter \B_WIDTH 5
102642     parameter \Y_WIDTH 1
102643     connect \A \builder_interface6_bank_bus_adr [5:0]
102644     connect \B 5'11111
102645     connect \Y $eq$ls180.v:6082$1657_Y
102646   end
102647   attribute \src "ls180.v:6083.106-6083.151"
102648   cell $eq $eq$ls180.v:6083$1661
102649     parameter \A_SIGNED 0
102650     parameter \A_WIDTH 6
102651     parameter \B_SIGNED 0
102652     parameter \B_WIDTH 5
102653     parameter \Y_WIDTH 1
102654     connect \A \builder_interface6_bank_bus_adr [5:0]
102655     connect \B 5'11111
102656     connect \Y $eq$ls180.v:6083$1661_Y
102657   end
102658   attribute \src "ls180.v:6085.103-6085.148"
102659   cell $eq $eq$ls180.v:6085$1664
102660     parameter \A_SIGNED 0
102661     parameter \A_WIDTH 6
102662     parameter \B_SIGNED 0
102663     parameter \B_WIDTH 6
102664     parameter \Y_WIDTH 1
102665     connect \A \builder_interface6_bank_bus_adr [5:0]
102666     connect \B 6'100000
102667     connect \Y $eq$ls180.v:6085$1664_Y
102668   end
102669   attribute \src "ls180.v:6086.106-6086.151"
102670   cell $eq $eq$ls180.v:6086$1668
102671     parameter \A_SIGNED 0
102672     parameter \A_WIDTH 6
102673     parameter \B_SIGNED 0
102674     parameter \B_WIDTH 6
102675     parameter \Y_WIDTH 1
102676     connect \A \builder_interface6_bank_bus_adr [5:0]
102677     connect \B 6'100000
102678     connect \Y $eq$ls180.v:6086$1668_Y
102679   end
102680   attribute \src "ls180.v:6122.32-6122.78"
102681   cell $eq $eq$ls180.v:6122$1670
102682     parameter \A_SIGNED 0
102683     parameter \A_WIDTH 5
102684     parameter \B_SIGNED 0
102685     parameter \B_WIDTH 4
102686     parameter \Y_WIDTH 1
102687     connect \A \builder_interface7_bank_bus_adr [13:9]
102688     connect \B 4'1111
102689     connect \Y $eq$ls180.v:6122$1670_Y
102690   end
102691   attribute \src "ls180.v:6124.100-6124.144"
102692   cell $eq $eq$ls180.v:6124$1672
102693     parameter \A_SIGNED 0
102694     parameter \A_WIDTH 5
102695     parameter \B_SIGNED 0
102696     parameter \B_WIDTH 1
102697     parameter \Y_WIDTH 1
102698     connect \A \builder_interface7_bank_bus_adr [4:0]
102699     connect \B 1'0
102700     connect \Y $eq$ls180.v:6124$1672_Y
102701   end
102702   attribute \src "ls180.v:6125.103-6125.147"
102703   cell $eq $eq$ls180.v:6125$1676
102704     parameter \A_SIGNED 0
102705     parameter \A_WIDTH 5
102706     parameter \B_SIGNED 0
102707     parameter \B_WIDTH 1
102708     parameter \Y_WIDTH 1
102709     connect \A \builder_interface7_bank_bus_adr [4:0]
102710     connect \B 1'0
102711     connect \Y $eq$ls180.v:6125$1676_Y
102712   end
102713   attribute \src "ls180.v:6127.100-6127.144"
102714   cell $eq $eq$ls180.v:6127$1679
102715     parameter \A_SIGNED 0
102716     parameter \A_WIDTH 5
102717     parameter \B_SIGNED 0
102718     parameter \B_WIDTH 1
102719     parameter \Y_WIDTH 1
102720     connect \A \builder_interface7_bank_bus_adr [4:0]
102721     connect \B 1'1
102722     connect \Y $eq$ls180.v:6127$1679_Y
102723   end
102724   attribute \src "ls180.v:6128.103-6128.147"
102725   cell $eq $eq$ls180.v:6128$1683
102726     parameter \A_SIGNED 0
102727     parameter \A_WIDTH 5
102728     parameter \B_SIGNED 0
102729     parameter \B_WIDTH 1
102730     parameter \Y_WIDTH 1
102731     connect \A \builder_interface7_bank_bus_adr [4:0]
102732     connect \B 1'1
102733     connect \Y $eq$ls180.v:6128$1683_Y
102734   end
102735   attribute \src "ls180.v:6130.100-6130.144"
102736   cell $eq $eq$ls180.v:6130$1686
102737     parameter \A_SIGNED 0
102738     parameter \A_WIDTH 5
102739     parameter \B_SIGNED 0
102740     parameter \B_WIDTH 2
102741     parameter \Y_WIDTH 1
102742     connect \A \builder_interface7_bank_bus_adr [4:0]
102743     connect \B 2'10
102744     connect \Y $eq$ls180.v:6130$1686_Y
102745   end
102746   attribute \src "ls180.v:6131.103-6131.147"
102747   cell $eq $eq$ls180.v:6131$1690
102748     parameter \A_SIGNED 0
102749     parameter \A_WIDTH 5
102750     parameter \B_SIGNED 0
102751     parameter \B_WIDTH 2
102752     parameter \Y_WIDTH 1
102753     connect \A \builder_interface7_bank_bus_adr [4:0]
102754     connect \B 2'10
102755     connect \Y $eq$ls180.v:6131$1690_Y
102756   end
102757   attribute \src "ls180.v:6133.100-6133.144"
102758   cell $eq $eq$ls180.v:6133$1693
102759     parameter \A_SIGNED 0
102760     parameter \A_WIDTH 5
102761     parameter \B_SIGNED 0
102762     parameter \B_WIDTH 2
102763     parameter \Y_WIDTH 1
102764     connect \A \builder_interface7_bank_bus_adr [4:0]
102765     connect \B 2'11
102766     connect \Y $eq$ls180.v:6133$1693_Y
102767   end
102768   attribute \src "ls180.v:6134.103-6134.147"
102769   cell $eq $eq$ls180.v:6134$1697
102770     parameter \A_SIGNED 0
102771     parameter \A_WIDTH 5
102772     parameter \B_SIGNED 0
102773     parameter \B_WIDTH 2
102774     parameter \Y_WIDTH 1
102775     connect \A \builder_interface7_bank_bus_adr [4:0]
102776     connect \B 2'11
102777     connect \Y $eq$ls180.v:6134$1697_Y
102778   end
102779   attribute \src "ls180.v:6136.100-6136.144"
102780   cell $eq $eq$ls180.v:6136$1700
102781     parameter \A_SIGNED 0
102782     parameter \A_WIDTH 5
102783     parameter \B_SIGNED 0
102784     parameter \B_WIDTH 3
102785     parameter \Y_WIDTH 1
102786     connect \A \builder_interface7_bank_bus_adr [4:0]
102787     connect \B 3'100
102788     connect \Y $eq$ls180.v:6136$1700_Y
102789   end
102790   attribute \src "ls180.v:6137.103-6137.147"
102791   cell $eq $eq$ls180.v:6137$1704
102792     parameter \A_SIGNED 0
102793     parameter \A_WIDTH 5
102794     parameter \B_SIGNED 0
102795     parameter \B_WIDTH 3
102796     parameter \Y_WIDTH 1
102797     connect \A \builder_interface7_bank_bus_adr [4:0]
102798     connect \B 3'100
102799     connect \Y $eq$ls180.v:6137$1704_Y
102800   end
102801   attribute \src "ls180.v:6139.100-6139.144"
102802   cell $eq $eq$ls180.v:6139$1707
102803     parameter \A_SIGNED 0
102804     parameter \A_WIDTH 5
102805     parameter \B_SIGNED 0
102806     parameter \B_WIDTH 3
102807     parameter \Y_WIDTH 1
102808     connect \A \builder_interface7_bank_bus_adr [4:0]
102809     connect \B 3'101
102810     connect \Y $eq$ls180.v:6139$1707_Y
102811   end
102812   attribute \src "ls180.v:6140.103-6140.147"
102813   cell $eq $eq$ls180.v:6140$1711
102814     parameter \A_SIGNED 0
102815     parameter \A_WIDTH 5
102816     parameter \B_SIGNED 0
102817     parameter \B_WIDTH 3
102818     parameter \Y_WIDTH 1
102819     connect \A \builder_interface7_bank_bus_adr [4:0]
102820     connect \B 3'101
102821     connect \Y $eq$ls180.v:6140$1711_Y
102822   end
102823   attribute \src "ls180.v:6142.100-6142.144"
102824   cell $eq $eq$ls180.v:6142$1714
102825     parameter \A_SIGNED 0
102826     parameter \A_WIDTH 5
102827     parameter \B_SIGNED 0
102828     parameter \B_WIDTH 3
102829     parameter \Y_WIDTH 1
102830     connect \A \builder_interface7_bank_bus_adr [4:0]
102831     connect \B 3'110
102832     connect \Y $eq$ls180.v:6142$1714_Y
102833   end
102834   attribute \src "ls180.v:6143.103-6143.147"
102835   cell $eq $eq$ls180.v:6143$1718
102836     parameter \A_SIGNED 0
102837     parameter \A_WIDTH 5
102838     parameter \B_SIGNED 0
102839     parameter \B_WIDTH 3
102840     parameter \Y_WIDTH 1
102841     connect \A \builder_interface7_bank_bus_adr [4:0]
102842     connect \B 3'110
102843     connect \Y $eq$ls180.v:6143$1718_Y
102844   end
102845   attribute \src "ls180.v:6145.100-6145.144"
102846   cell $eq $eq$ls180.v:6145$1721
102847     parameter \A_SIGNED 0
102848     parameter \A_WIDTH 5
102849     parameter \B_SIGNED 0
102850     parameter \B_WIDTH 3
102851     parameter \Y_WIDTH 1
102852     connect \A \builder_interface7_bank_bus_adr [4:0]
102853     connect \B 3'111
102854     connect \Y $eq$ls180.v:6145$1721_Y
102855   end
102856   attribute \src "ls180.v:6146.103-6146.147"
102857   cell $eq $eq$ls180.v:6146$1725
102858     parameter \A_SIGNED 0
102859     parameter \A_WIDTH 5
102860     parameter \B_SIGNED 0
102861     parameter \B_WIDTH 3
102862     parameter \Y_WIDTH 1
102863     connect \A \builder_interface7_bank_bus_adr [4:0]
102864     connect \B 3'111
102865     connect \Y $eq$ls180.v:6146$1725_Y
102866   end
102867   attribute \src "ls180.v:6148.102-6148.146"
102868   cell $eq $eq$ls180.v:6148$1728
102869     parameter \A_SIGNED 0
102870     parameter \A_WIDTH 5
102871     parameter \B_SIGNED 0
102872     parameter \B_WIDTH 4
102873     parameter \Y_WIDTH 1
102874     connect \A \builder_interface7_bank_bus_adr [4:0]
102875     connect \B 4'1000
102876     connect \Y $eq$ls180.v:6148$1728_Y
102877   end
102878   attribute \src "ls180.v:6149.105-6149.149"
102879   cell $eq $eq$ls180.v:6149$1732
102880     parameter \A_SIGNED 0
102881     parameter \A_WIDTH 5
102882     parameter \B_SIGNED 0
102883     parameter \B_WIDTH 4
102884     parameter \Y_WIDTH 1
102885     connect \A \builder_interface7_bank_bus_adr [4:0]
102886     connect \B 4'1000
102887     connect \Y $eq$ls180.v:6149$1732_Y
102888   end
102889   attribute \src "ls180.v:6151.102-6151.146"
102890   cell $eq $eq$ls180.v:6151$1735
102891     parameter \A_SIGNED 0
102892     parameter \A_WIDTH 5
102893     parameter \B_SIGNED 0
102894     parameter \B_WIDTH 4
102895     parameter \Y_WIDTH 1
102896     connect \A \builder_interface7_bank_bus_adr [4:0]
102897     connect \B 4'1001
102898     connect \Y $eq$ls180.v:6151$1735_Y
102899   end
102900   attribute \src "ls180.v:6152.105-6152.149"
102901   cell $eq $eq$ls180.v:6152$1739
102902     parameter \A_SIGNED 0
102903     parameter \A_WIDTH 5
102904     parameter \B_SIGNED 0
102905     parameter \B_WIDTH 4
102906     parameter \Y_WIDTH 1
102907     connect \A \builder_interface7_bank_bus_adr [4:0]
102908     connect \B 4'1001
102909     connect \Y $eq$ls180.v:6152$1739_Y
102910   end
102911   attribute \src "ls180.v:6154.102-6154.147"
102912   cell $eq $eq$ls180.v:6154$1742
102913     parameter \A_SIGNED 0
102914     parameter \A_WIDTH 5
102915     parameter \B_SIGNED 0
102916     parameter \B_WIDTH 4
102917     parameter \Y_WIDTH 1
102918     connect \A \builder_interface7_bank_bus_adr [4:0]
102919     connect \B 4'1010
102920     connect \Y $eq$ls180.v:6154$1742_Y
102921   end
102922   attribute \src "ls180.v:6155.105-6155.150"
102923   cell $eq $eq$ls180.v:6155$1746
102924     parameter \A_SIGNED 0
102925     parameter \A_WIDTH 5
102926     parameter \B_SIGNED 0
102927     parameter \B_WIDTH 4
102928     parameter \Y_WIDTH 1
102929     connect \A \builder_interface7_bank_bus_adr [4:0]
102930     connect \B 4'1010
102931     connect \Y $eq$ls180.v:6155$1746_Y
102932   end
102933   attribute \src "ls180.v:6157.102-6157.147"
102934   cell $eq $eq$ls180.v:6157$1749
102935     parameter \A_SIGNED 0
102936     parameter \A_WIDTH 5
102937     parameter \B_SIGNED 0
102938     parameter \B_WIDTH 4
102939     parameter \Y_WIDTH 1
102940     connect \A \builder_interface7_bank_bus_adr [4:0]
102941     connect \B 4'1011
102942     connect \Y $eq$ls180.v:6157$1749_Y
102943   end
102944   attribute \src "ls180.v:6158.105-6158.150"
102945   cell $eq $eq$ls180.v:6158$1753
102946     parameter \A_SIGNED 0
102947     parameter \A_WIDTH 5
102948     parameter \B_SIGNED 0
102949     parameter \B_WIDTH 4
102950     parameter \Y_WIDTH 1
102951     connect \A \builder_interface7_bank_bus_adr [4:0]
102952     connect \B 4'1011
102953     connect \Y $eq$ls180.v:6158$1753_Y
102954   end
102955   attribute \src "ls180.v:6160.102-6160.147"
102956   cell $eq $eq$ls180.v:6160$1756
102957     parameter \A_SIGNED 0
102958     parameter \A_WIDTH 5
102959     parameter \B_SIGNED 0
102960     parameter \B_WIDTH 4
102961     parameter \Y_WIDTH 1
102962     connect \A \builder_interface7_bank_bus_adr [4:0]
102963     connect \B 4'1100
102964     connect \Y $eq$ls180.v:6160$1756_Y
102965   end
102966   attribute \src "ls180.v:6161.105-6161.150"
102967   cell $eq $eq$ls180.v:6161$1760
102968     parameter \A_SIGNED 0
102969     parameter \A_WIDTH 5
102970     parameter \B_SIGNED 0
102971     parameter \B_WIDTH 4
102972     parameter \Y_WIDTH 1
102973     connect \A \builder_interface7_bank_bus_adr [4:0]
102974     connect \B 4'1100
102975     connect \Y $eq$ls180.v:6161$1760_Y
102976   end
102977   attribute \src "ls180.v:6163.99-6163.144"
102978   cell $eq $eq$ls180.v:6163$1763
102979     parameter \A_SIGNED 0
102980     parameter \A_WIDTH 5
102981     parameter \B_SIGNED 0
102982     parameter \B_WIDTH 4
102983     parameter \Y_WIDTH 1
102984     connect \A \builder_interface7_bank_bus_adr [4:0]
102985     connect \B 4'1101
102986     connect \Y $eq$ls180.v:6163$1763_Y
102987   end
102988   attribute \src "ls180.v:6164.102-6164.147"
102989   cell $eq $eq$ls180.v:6164$1767
102990     parameter \A_SIGNED 0
102991     parameter \A_WIDTH 5
102992     parameter \B_SIGNED 0
102993     parameter \B_WIDTH 4
102994     parameter \Y_WIDTH 1
102995     connect \A \builder_interface7_bank_bus_adr [4:0]
102996     connect \B 4'1101
102997     connect \Y $eq$ls180.v:6164$1767_Y
102998   end
102999   attribute \src "ls180.v:6166.100-6166.145"
103000   cell $eq $eq$ls180.v:6166$1770
103001     parameter \A_SIGNED 0
103002     parameter \A_WIDTH 5
103003     parameter \B_SIGNED 0
103004     parameter \B_WIDTH 4
103005     parameter \Y_WIDTH 1
103006     connect \A \builder_interface7_bank_bus_adr [4:0]
103007     connect \B 4'1110
103008     connect \Y $eq$ls180.v:6166$1770_Y
103009   end
103010   attribute \src "ls180.v:6167.103-6167.148"
103011   cell $eq $eq$ls180.v:6167$1774
103012     parameter \A_SIGNED 0
103013     parameter \A_WIDTH 5
103014     parameter \B_SIGNED 0
103015     parameter \B_WIDTH 4
103016     parameter \Y_WIDTH 1
103017     connect \A \builder_interface7_bank_bus_adr [4:0]
103018     connect \B 4'1110
103019     connect \Y $eq$ls180.v:6167$1774_Y
103020   end
103021   attribute \src "ls180.v:6169.102-6169.147"
103022   cell $eq $eq$ls180.v:6169$1777
103023     parameter \A_SIGNED 0
103024     parameter \A_WIDTH 5
103025     parameter \B_SIGNED 0
103026     parameter \B_WIDTH 4
103027     parameter \Y_WIDTH 1
103028     connect \A \builder_interface7_bank_bus_adr [4:0]
103029     connect \B 4'1111
103030     connect \Y $eq$ls180.v:6169$1777_Y
103031   end
103032   attribute \src "ls180.v:6170.105-6170.150"
103033   cell $eq $eq$ls180.v:6170$1781
103034     parameter \A_SIGNED 0
103035     parameter \A_WIDTH 5
103036     parameter \B_SIGNED 0
103037     parameter \B_WIDTH 4
103038     parameter \Y_WIDTH 1
103039     connect \A \builder_interface7_bank_bus_adr [4:0]
103040     connect \B 4'1111
103041     connect \Y $eq$ls180.v:6170$1781_Y
103042   end
103043   attribute \src "ls180.v:6172.102-6172.147"
103044   cell $eq $eq$ls180.v:6172$1784
103045     parameter \A_SIGNED 0
103046     parameter \A_WIDTH 5
103047     parameter \B_SIGNED 0
103048     parameter \B_WIDTH 5
103049     parameter \Y_WIDTH 1
103050     connect \A \builder_interface7_bank_bus_adr [4:0]
103051     connect \B 5'10000
103052     connect \Y $eq$ls180.v:6172$1784_Y
103053   end
103054   attribute \src "ls180.v:6173.105-6173.150"
103055   cell $eq $eq$ls180.v:6173$1788
103056     parameter \A_SIGNED 0
103057     parameter \A_WIDTH 5
103058     parameter \B_SIGNED 0
103059     parameter \B_WIDTH 5
103060     parameter \Y_WIDTH 1
103061     connect \A \builder_interface7_bank_bus_adr [4:0]
103062     connect \B 5'10000
103063     connect \Y $eq$ls180.v:6173$1788_Y
103064   end
103065   attribute \src "ls180.v:6175.102-6175.147"
103066   cell $eq $eq$ls180.v:6175$1791
103067     parameter \A_SIGNED 0
103068     parameter \A_WIDTH 5
103069     parameter \B_SIGNED 0
103070     parameter \B_WIDTH 5
103071     parameter \Y_WIDTH 1
103072     connect \A \builder_interface7_bank_bus_adr [4:0]
103073     connect \B 5'10001
103074     connect \Y $eq$ls180.v:6175$1791_Y
103075   end
103076   attribute \src "ls180.v:6176.105-6176.150"
103077   cell $eq $eq$ls180.v:6176$1795
103078     parameter \A_SIGNED 0
103079     parameter \A_WIDTH 5
103080     parameter \B_SIGNED 0
103081     parameter \B_WIDTH 5
103082     parameter \Y_WIDTH 1
103083     connect \A \builder_interface7_bank_bus_adr [4:0]
103084     connect \B 5'10001
103085     connect \Y $eq$ls180.v:6176$1795_Y
103086   end
103087   attribute \src "ls180.v:6178.102-6178.147"
103088   cell $eq $eq$ls180.v:6178$1798
103089     parameter \A_SIGNED 0
103090     parameter \A_WIDTH 5
103091     parameter \B_SIGNED 0
103092     parameter \B_WIDTH 5
103093     parameter \Y_WIDTH 1
103094     connect \A \builder_interface7_bank_bus_adr [4:0]
103095     connect \B 5'10010
103096     connect \Y $eq$ls180.v:6178$1798_Y
103097   end
103098   attribute \src "ls180.v:6179.105-6179.150"
103099   cell $eq $eq$ls180.v:6179$1802
103100     parameter \A_SIGNED 0
103101     parameter \A_WIDTH 5
103102     parameter \B_SIGNED 0
103103     parameter \B_WIDTH 5
103104     parameter \Y_WIDTH 1
103105     connect \A \builder_interface7_bank_bus_adr [4:0]
103106     connect \B 5'10010
103107     connect \Y $eq$ls180.v:6179$1802_Y
103108   end
103109   attribute \src "ls180.v:6201.32-6201.78"
103110   cell $eq $eq$ls180.v:6201$1804
103111     parameter \A_SIGNED 0
103112     parameter \A_WIDTH 5
103113     parameter \B_SIGNED 0
103114     parameter \B_WIDTH 4
103115     parameter \Y_WIDTH 1
103116     connect \A \builder_interface8_bank_bus_adr [13:9]
103117     connect \B 4'1100
103118     connect \Y $eq$ls180.v:6201$1804_Y
103119   end
103120   attribute \src "ls180.v:6203.102-6203.146"
103121   cell $eq $eq$ls180.v:6203$1806
103122     parameter \A_SIGNED 0
103123     parameter \A_WIDTH 2
103124     parameter \B_SIGNED 0
103125     parameter \B_WIDTH 1
103126     parameter \Y_WIDTH 1
103127     connect \A \builder_interface8_bank_bus_adr [1:0]
103128     connect \B 1'0
103129     connect \Y $eq$ls180.v:6203$1806_Y
103130   end
103131   attribute \src "ls180.v:6204.105-6204.149"
103132   cell $eq $eq$ls180.v:6204$1810
103133     parameter \A_SIGNED 0
103134     parameter \A_WIDTH 2
103135     parameter \B_SIGNED 0
103136     parameter \B_WIDTH 1
103137     parameter \Y_WIDTH 1
103138     connect \A \builder_interface8_bank_bus_adr [1:0]
103139     connect \B 1'0
103140     connect \Y $eq$ls180.v:6204$1810_Y
103141   end
103142   attribute \src "ls180.v:6206.107-6206.151"
103143   cell $eq $eq$ls180.v:6206$1813
103144     parameter \A_SIGNED 0
103145     parameter \A_WIDTH 2
103146     parameter \B_SIGNED 0
103147     parameter \B_WIDTH 1
103148     parameter \Y_WIDTH 1
103149     connect \A \builder_interface8_bank_bus_adr [1:0]
103150     connect \B 1'1
103151     connect \Y $eq$ls180.v:6206$1813_Y
103152   end
103153   attribute \src "ls180.v:6207.110-6207.154"
103154   cell $eq $eq$ls180.v:6207$1817
103155     parameter \A_SIGNED 0
103156     parameter \A_WIDTH 2
103157     parameter \B_SIGNED 0
103158     parameter \B_WIDTH 1
103159     parameter \Y_WIDTH 1
103160     connect \A \builder_interface8_bank_bus_adr [1:0]
103161     connect \B 1'1
103162     connect \Y $eq$ls180.v:6207$1817_Y
103163   end
103164   attribute \src "ls180.v:6209.107-6209.151"
103165   cell $eq $eq$ls180.v:6209$1820
103166     parameter \A_SIGNED 0
103167     parameter \A_WIDTH 2
103168     parameter \B_SIGNED 0
103169     parameter \B_WIDTH 2
103170     parameter \Y_WIDTH 1
103171     connect \A \builder_interface8_bank_bus_adr [1:0]
103172     connect \B 2'10
103173     connect \Y $eq$ls180.v:6209$1820_Y
103174   end
103175   attribute \src "ls180.v:6210.110-6210.154"
103176   cell $eq $eq$ls180.v:6210$1824
103177     parameter \A_SIGNED 0
103178     parameter \A_WIDTH 2
103179     parameter \B_SIGNED 0
103180     parameter \B_WIDTH 2
103181     parameter \Y_WIDTH 1
103182     connect \A \builder_interface8_bank_bus_adr [1:0]
103183     connect \B 2'10
103184     connect \Y $eq$ls180.v:6210$1824_Y
103185   end
103186   attribute \src "ls180.v:6212.100-6212.144"
103187   cell $eq $eq$ls180.v:6212$1827
103188     parameter \A_SIGNED 0
103189     parameter \A_WIDTH 2
103190     parameter \B_SIGNED 0
103191     parameter \B_WIDTH 2
103192     parameter \Y_WIDTH 1
103193     connect \A \builder_interface8_bank_bus_adr [1:0]
103194     connect \B 2'11
103195     connect \Y $eq$ls180.v:6212$1827_Y
103196   end
103197   attribute \src "ls180.v:6213.103-6213.147"
103198   cell $eq $eq$ls180.v:6213$1831
103199     parameter \A_SIGNED 0
103200     parameter \A_WIDTH 2
103201     parameter \B_SIGNED 0
103202     parameter \B_WIDTH 2
103203     parameter \Y_WIDTH 1
103204     connect \A \builder_interface8_bank_bus_adr [1:0]
103205     connect \B 2'11
103206     connect \Y $eq$ls180.v:6213$1831_Y
103207   end
103208   attribute \src "ls180.v:6218.32-6218.77"
103209   cell $eq $eq$ls180.v:6218$1833
103210     parameter \A_SIGNED 0
103211     parameter \A_WIDTH 5
103212     parameter \B_SIGNED 0
103213     parameter \B_WIDTH 2
103214     parameter \Y_WIDTH 1
103215     connect \A \builder_interface9_bank_bus_adr [13:9]
103216     connect \B 2'11
103217     connect \Y $eq$ls180.v:6218$1833_Y
103218   end
103219   attribute \src "ls180.v:6220.104-6220.148"
103220   cell $eq $eq$ls180.v:6220$1835
103221     parameter \A_SIGNED 0
103222     parameter \A_WIDTH 4
103223     parameter \B_SIGNED 0
103224     parameter \B_WIDTH 1
103225     parameter \Y_WIDTH 1
103226     connect \A \builder_interface9_bank_bus_adr [3:0]
103227     connect \B 1'0
103228     connect \Y $eq$ls180.v:6220$1835_Y
103229   end
103230   attribute \src "ls180.v:6221.107-6221.151"
103231   cell $eq $eq$ls180.v:6221$1839
103232     parameter \A_SIGNED 0
103233     parameter \A_WIDTH 4
103234     parameter \B_SIGNED 0
103235     parameter \B_WIDTH 1
103236     parameter \Y_WIDTH 1
103237     connect \A \builder_interface9_bank_bus_adr [3:0]
103238     connect \B 1'0
103239     connect \Y $eq$ls180.v:6221$1839_Y
103240   end
103241   attribute \src "ls180.v:6223.108-6223.152"
103242   cell $eq $eq$ls180.v:6223$1842
103243     parameter \A_SIGNED 0
103244     parameter \A_WIDTH 4
103245     parameter \B_SIGNED 0
103246     parameter \B_WIDTH 1
103247     parameter \Y_WIDTH 1
103248     connect \A \builder_interface9_bank_bus_adr [3:0]
103249     connect \B 1'1
103250     connect \Y $eq$ls180.v:6223$1842_Y
103251   end
103252   attribute \src "ls180.v:6224.111-6224.155"
103253   cell $eq $eq$ls180.v:6224$1846
103254     parameter \A_SIGNED 0
103255     parameter \A_WIDTH 4
103256     parameter \B_SIGNED 0
103257     parameter \B_WIDTH 1
103258     parameter \Y_WIDTH 1
103259     connect \A \builder_interface9_bank_bus_adr [3:0]
103260     connect \B 1'1
103261     connect \Y $eq$ls180.v:6224$1846_Y
103262   end
103263   attribute \src "ls180.v:6226.98-6226.142"
103264   cell $eq $eq$ls180.v:6226$1849
103265     parameter \A_SIGNED 0
103266     parameter \A_WIDTH 4
103267     parameter \B_SIGNED 0
103268     parameter \B_WIDTH 2
103269     parameter \Y_WIDTH 1
103270     connect \A \builder_interface9_bank_bus_adr [3:0]
103271     connect \B 2'10
103272     connect \Y $eq$ls180.v:6226$1849_Y
103273   end
103274   attribute \src "ls180.v:6227.101-6227.145"
103275   cell $eq $eq$ls180.v:6227$1853
103276     parameter \A_SIGNED 0
103277     parameter \A_WIDTH 4
103278     parameter \B_SIGNED 0
103279     parameter \B_WIDTH 2
103280     parameter \Y_WIDTH 1
103281     connect \A \builder_interface9_bank_bus_adr [3:0]
103282     connect \B 2'10
103283     connect \Y $eq$ls180.v:6227$1853_Y
103284   end
103285   attribute \src "ls180.v:6229.108-6229.152"
103286   cell $eq $eq$ls180.v:6229$1856
103287     parameter \A_SIGNED 0
103288     parameter \A_WIDTH 4
103289     parameter \B_SIGNED 0
103290     parameter \B_WIDTH 2
103291     parameter \Y_WIDTH 1
103292     connect \A \builder_interface9_bank_bus_adr [3:0]
103293     connect \B 2'11
103294     connect \Y $eq$ls180.v:6229$1856_Y
103295   end
103296   attribute \src "ls180.v:6230.111-6230.155"
103297   cell $eq $eq$ls180.v:6230$1860
103298     parameter \A_SIGNED 0
103299     parameter \A_WIDTH 4
103300     parameter \B_SIGNED 0
103301     parameter \B_WIDTH 2
103302     parameter \Y_WIDTH 1
103303     connect \A \builder_interface9_bank_bus_adr [3:0]
103304     connect \B 2'11
103305     connect \Y $eq$ls180.v:6230$1860_Y
103306   end
103307   attribute \src "ls180.v:6232.108-6232.152"
103308   cell $eq $eq$ls180.v:6232$1863
103309     parameter \A_SIGNED 0
103310     parameter \A_WIDTH 4
103311     parameter \B_SIGNED 0
103312     parameter \B_WIDTH 3
103313     parameter \Y_WIDTH 1
103314     connect \A \builder_interface9_bank_bus_adr [3:0]
103315     connect \B 3'100
103316     connect \Y $eq$ls180.v:6232$1863_Y
103317   end
103318   attribute \src "ls180.v:6233.111-6233.155"
103319   cell $eq $eq$ls180.v:6233$1867
103320     parameter \A_SIGNED 0
103321     parameter \A_WIDTH 4
103322     parameter \B_SIGNED 0
103323     parameter \B_WIDTH 3
103324     parameter \Y_WIDTH 1
103325     connect \A \builder_interface9_bank_bus_adr [3:0]
103326     connect \B 3'100
103327     connect \Y $eq$ls180.v:6233$1867_Y
103328   end
103329   attribute \src "ls180.v:6235.109-6235.153"
103330   cell $eq $eq$ls180.v:6235$1870
103331     parameter \A_SIGNED 0
103332     parameter \A_WIDTH 4
103333     parameter \B_SIGNED 0
103334     parameter \B_WIDTH 3
103335     parameter \Y_WIDTH 1
103336     connect \A \builder_interface9_bank_bus_adr [3:0]
103337     connect \B 3'101
103338     connect \Y $eq$ls180.v:6235$1870_Y
103339   end
103340   attribute \src "ls180.v:6236.112-6236.156"
103341   cell $eq $eq$ls180.v:6236$1874
103342     parameter \A_SIGNED 0
103343     parameter \A_WIDTH 4
103344     parameter \B_SIGNED 0
103345     parameter \B_WIDTH 3
103346     parameter \Y_WIDTH 1
103347     connect \A \builder_interface9_bank_bus_adr [3:0]
103348     connect \B 3'101
103349     connect \Y $eq$ls180.v:6236$1874_Y
103350   end
103351   attribute \src "ls180.v:6238.107-6238.151"
103352   cell $eq $eq$ls180.v:6238$1877
103353     parameter \A_SIGNED 0
103354     parameter \A_WIDTH 4
103355     parameter \B_SIGNED 0
103356     parameter \B_WIDTH 3
103357     parameter \Y_WIDTH 1
103358     connect \A \builder_interface9_bank_bus_adr [3:0]
103359     connect \B 3'110
103360     connect \Y $eq$ls180.v:6238$1877_Y
103361   end
103362   attribute \src "ls180.v:6239.110-6239.154"
103363   cell $eq $eq$ls180.v:6239$1881
103364     parameter \A_SIGNED 0
103365     parameter \A_WIDTH 4
103366     parameter \B_SIGNED 0
103367     parameter \B_WIDTH 3
103368     parameter \Y_WIDTH 1
103369     connect \A \builder_interface9_bank_bus_adr [3:0]
103370     connect \B 3'110
103371     connect \Y $eq$ls180.v:6239$1881_Y
103372   end
103373   attribute \src "ls180.v:6241.107-6241.151"
103374   cell $eq $eq$ls180.v:6241$1884
103375     parameter \A_SIGNED 0
103376     parameter \A_WIDTH 4
103377     parameter \B_SIGNED 0
103378     parameter \B_WIDTH 3
103379     parameter \Y_WIDTH 1
103380     connect \A \builder_interface9_bank_bus_adr [3:0]
103381     connect \B 3'111
103382     connect \Y $eq$ls180.v:6241$1884_Y
103383   end
103384   attribute \src "ls180.v:6242.110-6242.154"
103385   cell $eq $eq$ls180.v:6242$1888
103386     parameter \A_SIGNED 0
103387     parameter \A_WIDTH 4
103388     parameter \B_SIGNED 0
103389     parameter \B_WIDTH 3
103390     parameter \Y_WIDTH 1
103391     connect \A \builder_interface9_bank_bus_adr [3:0]
103392     connect \B 3'111
103393     connect \Y $eq$ls180.v:6242$1888_Y
103394   end
103395   attribute \src "ls180.v:6244.107-6244.151"
103396   cell $eq $eq$ls180.v:6244$1891
103397     parameter \A_SIGNED 0
103398     parameter \A_WIDTH 4
103399     parameter \B_SIGNED 0
103400     parameter \B_WIDTH 4
103401     parameter \Y_WIDTH 1
103402     connect \A \builder_interface9_bank_bus_adr [3:0]
103403     connect \B 4'1000
103404     connect \Y $eq$ls180.v:6244$1891_Y
103405   end
103406   attribute \src "ls180.v:6245.110-6245.154"
103407   cell $eq $eq$ls180.v:6245$1895
103408     parameter \A_SIGNED 0
103409     parameter \A_WIDTH 4
103410     parameter \B_SIGNED 0
103411     parameter \B_WIDTH 4
103412     parameter \Y_WIDTH 1
103413     connect \A \builder_interface9_bank_bus_adr [3:0]
103414     connect \B 4'1000
103415     connect \Y $eq$ls180.v:6245$1895_Y
103416   end
103417   attribute \src "ls180.v:6247.107-6247.151"
103418   cell $eq $eq$ls180.v:6247$1898
103419     parameter \A_SIGNED 0
103420     parameter \A_WIDTH 4
103421     parameter \B_SIGNED 0
103422     parameter \B_WIDTH 4
103423     parameter \Y_WIDTH 1
103424     connect \A \builder_interface9_bank_bus_adr [3:0]
103425     connect \B 4'1001
103426     connect \Y $eq$ls180.v:6247$1898_Y
103427   end
103428   attribute \src "ls180.v:6248.110-6248.154"
103429   cell $eq $eq$ls180.v:6248$1902
103430     parameter \A_SIGNED 0
103431     parameter \A_WIDTH 4
103432     parameter \B_SIGNED 0
103433     parameter \B_WIDTH 4
103434     parameter \Y_WIDTH 1
103435     connect \A \builder_interface9_bank_bus_adr [3:0]
103436     connect \B 4'1001
103437     connect \Y $eq$ls180.v:6248$1902_Y
103438   end
103439   attribute \src "ls180.v:6263.33-6263.79"
103440   cell $eq $eq$ls180.v:6263$1904
103441     parameter \A_SIGNED 0
103442     parameter \A_WIDTH 5
103443     parameter \B_SIGNED 0
103444     parameter \B_WIDTH 3
103445     parameter \Y_WIDTH 1
103446     connect \A \builder_interface10_bank_bus_adr [13:9]
103447     connect \B 3'111
103448     connect \Y $eq$ls180.v:6263$1904_Y
103449   end
103450   attribute \src "ls180.v:6265.102-6265.147"
103451   cell $eq $eq$ls180.v:6265$1906
103452     parameter \A_SIGNED 0
103453     parameter \A_WIDTH 3
103454     parameter \B_SIGNED 0
103455     parameter \B_WIDTH 1
103456     parameter \Y_WIDTH 1
103457     connect \A \builder_interface10_bank_bus_adr [2:0]
103458     connect \B 1'0
103459     connect \Y $eq$ls180.v:6265$1906_Y
103460   end
103461   attribute \src "ls180.v:6266.105-6266.150"
103462   cell $eq $eq$ls180.v:6266$1910
103463     parameter \A_SIGNED 0
103464     parameter \A_WIDTH 3
103465     parameter \B_SIGNED 0
103466     parameter \B_WIDTH 1
103467     parameter \Y_WIDTH 1
103468     connect \A \builder_interface10_bank_bus_adr [2:0]
103469     connect \B 1'0
103470     connect \Y $eq$ls180.v:6266$1910_Y
103471   end
103472   attribute \src "ls180.v:6268.102-6268.147"
103473   cell $eq $eq$ls180.v:6268$1913
103474     parameter \A_SIGNED 0
103475     parameter \A_WIDTH 3
103476     parameter \B_SIGNED 0
103477     parameter \B_WIDTH 1
103478     parameter \Y_WIDTH 1
103479     connect \A \builder_interface10_bank_bus_adr [2:0]
103480     connect \B 1'1
103481     connect \Y $eq$ls180.v:6268$1913_Y
103482   end
103483   attribute \src "ls180.v:6269.105-6269.150"
103484   cell $eq $eq$ls180.v:6269$1917
103485     parameter \A_SIGNED 0
103486     parameter \A_WIDTH 3
103487     parameter \B_SIGNED 0
103488     parameter \B_WIDTH 1
103489     parameter \Y_WIDTH 1
103490     connect \A \builder_interface10_bank_bus_adr [2:0]
103491     connect \B 1'1
103492     connect \Y $eq$ls180.v:6269$1917_Y
103493   end
103494   attribute \src "ls180.v:6271.100-6271.145"
103495   cell $eq $eq$ls180.v:6271$1920
103496     parameter \A_SIGNED 0
103497     parameter \A_WIDTH 3
103498     parameter \B_SIGNED 0
103499     parameter \B_WIDTH 2
103500     parameter \Y_WIDTH 1
103501     connect \A \builder_interface10_bank_bus_adr [2:0]
103502     connect \B 2'10
103503     connect \Y $eq$ls180.v:6271$1920_Y
103504   end
103505   attribute \src "ls180.v:6272.103-6272.148"
103506   cell $eq $eq$ls180.v:6272$1924
103507     parameter \A_SIGNED 0
103508     parameter \A_WIDTH 3
103509     parameter \B_SIGNED 0
103510     parameter \B_WIDTH 2
103511     parameter \Y_WIDTH 1
103512     connect \A \builder_interface10_bank_bus_adr [2:0]
103513     connect \B 2'10
103514     connect \Y $eq$ls180.v:6272$1924_Y
103515   end
103516   attribute \src "ls180.v:6274.99-6274.144"
103517   cell $eq $eq$ls180.v:6274$1927
103518     parameter \A_SIGNED 0
103519     parameter \A_WIDTH 3
103520     parameter \B_SIGNED 0
103521     parameter \B_WIDTH 2
103522     parameter \Y_WIDTH 1
103523     connect \A \builder_interface10_bank_bus_adr [2:0]
103524     connect \B 2'11
103525     connect \Y $eq$ls180.v:6274$1927_Y
103526   end
103527   attribute \src "ls180.v:6275.102-6275.147"
103528   cell $eq $eq$ls180.v:6275$1931
103529     parameter \A_SIGNED 0
103530     parameter \A_WIDTH 3
103531     parameter \B_SIGNED 0
103532     parameter \B_WIDTH 2
103533     parameter \Y_WIDTH 1
103534     connect \A \builder_interface10_bank_bus_adr [2:0]
103535     connect \B 2'11
103536     connect \Y $eq$ls180.v:6275$1931_Y
103537   end
103538   attribute \src "ls180.v:6277.98-6277.143"
103539   cell $eq $eq$ls180.v:6277$1934
103540     parameter \A_SIGNED 0
103541     parameter \A_WIDTH 3
103542     parameter \B_SIGNED 0
103543     parameter \B_WIDTH 3
103544     parameter \Y_WIDTH 1
103545     connect \A \builder_interface10_bank_bus_adr [2:0]
103546     connect \B 3'100
103547     connect \Y $eq$ls180.v:6277$1934_Y
103548   end
103549   attribute \src "ls180.v:6278.101-6278.146"
103550   cell $eq $eq$ls180.v:6278$1938
103551     parameter \A_SIGNED 0
103552     parameter \A_WIDTH 3
103553     parameter \B_SIGNED 0
103554     parameter \B_WIDTH 3
103555     parameter \Y_WIDTH 1
103556     connect \A \builder_interface10_bank_bus_adr [2:0]
103557     connect \B 3'100
103558     connect \Y $eq$ls180.v:6278$1938_Y
103559   end
103560   attribute \src "ls180.v:6280.97-6280.142"
103561   cell $eq $eq$ls180.v:6280$1941
103562     parameter \A_SIGNED 0
103563     parameter \A_WIDTH 3
103564     parameter \B_SIGNED 0
103565     parameter \B_WIDTH 3
103566     parameter \Y_WIDTH 1
103567     connect \A \builder_interface10_bank_bus_adr [2:0]
103568     connect \B 3'101
103569     connect \Y $eq$ls180.v:6280$1941_Y
103570   end
103571   attribute \src "ls180.v:6281.100-6281.145"
103572   cell $eq $eq$ls180.v:6281$1945
103573     parameter \A_SIGNED 0
103574     parameter \A_WIDTH 3
103575     parameter \B_SIGNED 0
103576     parameter \B_WIDTH 3
103577     parameter \Y_WIDTH 1
103578     connect \A \builder_interface10_bank_bus_adr [2:0]
103579     connect \B 3'101
103580     connect \Y $eq$ls180.v:6281$1945_Y
103581   end
103582   attribute \src "ls180.v:6283.103-6283.148"
103583   cell $eq $eq$ls180.v:6283$1948
103584     parameter \A_SIGNED 0
103585     parameter \A_WIDTH 3
103586     parameter \B_SIGNED 0
103587     parameter \B_WIDTH 3
103588     parameter \Y_WIDTH 1
103589     connect \A \builder_interface10_bank_bus_adr [2:0]
103590     connect \B 3'110
103591     connect \Y $eq$ls180.v:6283$1948_Y
103592   end
103593   attribute \src "ls180.v:6284.106-6284.151"
103594   cell $eq $eq$ls180.v:6284$1952
103595     parameter \A_SIGNED 0
103596     parameter \A_WIDTH 3
103597     parameter \B_SIGNED 0
103598     parameter \B_WIDTH 3
103599     parameter \Y_WIDTH 1
103600     connect \A \builder_interface10_bank_bus_adr [2:0]
103601     connect \B 3'110
103602     connect \Y $eq$ls180.v:6284$1952_Y
103603   end
103604   attribute \src "ls180.v:6303.33-6303.79"
103605   cell $eq $eq$ls180.v:6303$1955
103606     parameter \A_SIGNED 0
103607     parameter \A_WIDTH 5
103608     parameter \B_SIGNED 0
103609     parameter \B_WIDTH 4
103610     parameter \Y_WIDTH 1
103611     connect \A \builder_interface11_bank_bus_adr [13:9]
103612     connect \B 4'1000
103613     connect \Y $eq$ls180.v:6303$1955_Y
103614   end
103615   attribute \src "ls180.v:6305.102-6305.147"
103616   cell $eq $eq$ls180.v:6305$1957
103617     parameter \A_SIGNED 0
103618     parameter \A_WIDTH 4
103619     parameter \B_SIGNED 0
103620     parameter \B_WIDTH 1
103621     parameter \Y_WIDTH 1
103622     connect \A \builder_interface11_bank_bus_adr [3:0]
103623     connect \B 1'0
103624     connect \Y $eq$ls180.v:6305$1957_Y
103625   end
103626   attribute \src "ls180.v:6306.105-6306.150"
103627   cell $eq $eq$ls180.v:6306$1961
103628     parameter \A_SIGNED 0
103629     parameter \A_WIDTH 4
103630     parameter \B_SIGNED 0
103631     parameter \B_WIDTH 1
103632     parameter \Y_WIDTH 1
103633     connect \A \builder_interface11_bank_bus_adr [3:0]
103634     connect \B 1'0
103635     connect \Y $eq$ls180.v:6306$1961_Y
103636   end
103637   attribute \src "ls180.v:6308.102-6308.147"
103638   cell $eq $eq$ls180.v:6308$1964
103639     parameter \A_SIGNED 0
103640     parameter \A_WIDTH 4
103641     parameter \B_SIGNED 0
103642     parameter \B_WIDTH 1
103643     parameter \Y_WIDTH 1
103644     connect \A \builder_interface11_bank_bus_adr [3:0]
103645     connect \B 1'1
103646     connect \Y $eq$ls180.v:6308$1964_Y
103647   end
103648   attribute \src "ls180.v:6309.105-6309.150"
103649   cell $eq $eq$ls180.v:6309$1968
103650     parameter \A_SIGNED 0
103651     parameter \A_WIDTH 4
103652     parameter \B_SIGNED 0
103653     parameter \B_WIDTH 1
103654     parameter \Y_WIDTH 1
103655     connect \A \builder_interface11_bank_bus_adr [3:0]
103656     connect \B 1'1
103657     connect \Y $eq$ls180.v:6309$1968_Y
103658   end
103659   attribute \src "ls180.v:6311.100-6311.145"
103660   cell $eq $eq$ls180.v:6311$1971
103661     parameter \A_SIGNED 0
103662     parameter \A_WIDTH 4
103663     parameter \B_SIGNED 0
103664     parameter \B_WIDTH 2
103665     parameter \Y_WIDTH 1
103666     connect \A \builder_interface11_bank_bus_adr [3:0]
103667     connect \B 2'10
103668     connect \Y $eq$ls180.v:6311$1971_Y
103669   end
103670   attribute \src "ls180.v:6312.103-6312.148"
103671   cell $eq $eq$ls180.v:6312$1975
103672     parameter \A_SIGNED 0
103673     parameter \A_WIDTH 4
103674     parameter \B_SIGNED 0
103675     parameter \B_WIDTH 2
103676     parameter \Y_WIDTH 1
103677     connect \A \builder_interface11_bank_bus_adr [3:0]
103678     connect \B 2'10
103679     connect \Y $eq$ls180.v:6312$1975_Y
103680   end
103681   attribute \src "ls180.v:6314.99-6314.144"
103682   cell $eq $eq$ls180.v:6314$1978
103683     parameter \A_SIGNED 0
103684     parameter \A_WIDTH 4
103685     parameter \B_SIGNED 0
103686     parameter \B_WIDTH 2
103687     parameter \Y_WIDTH 1
103688     connect \A \builder_interface11_bank_bus_adr [3:0]
103689     connect \B 2'11
103690     connect \Y $eq$ls180.v:6314$1978_Y
103691   end
103692   attribute \src "ls180.v:6315.102-6315.147"
103693   cell $eq $eq$ls180.v:6315$1982
103694     parameter \A_SIGNED 0
103695     parameter \A_WIDTH 4
103696     parameter \B_SIGNED 0
103697     parameter \B_WIDTH 2
103698     parameter \Y_WIDTH 1
103699     connect \A \builder_interface11_bank_bus_adr [3:0]
103700     connect \B 2'11
103701     connect \Y $eq$ls180.v:6315$1982_Y
103702   end
103703   attribute \src "ls180.v:6317.98-6317.143"
103704   cell $eq $eq$ls180.v:6317$1985
103705     parameter \A_SIGNED 0
103706     parameter \A_WIDTH 4
103707     parameter \B_SIGNED 0
103708     parameter \B_WIDTH 3
103709     parameter \Y_WIDTH 1
103710     connect \A \builder_interface11_bank_bus_adr [3:0]
103711     connect \B 3'100
103712     connect \Y $eq$ls180.v:6317$1985_Y
103713   end
103714   attribute \src "ls180.v:6318.101-6318.146"
103715   cell $eq $eq$ls180.v:6318$1989
103716     parameter \A_SIGNED 0
103717     parameter \A_WIDTH 4
103718     parameter \B_SIGNED 0
103719     parameter \B_WIDTH 3
103720     parameter \Y_WIDTH 1
103721     connect \A \builder_interface11_bank_bus_adr [3:0]
103722     connect \B 3'100
103723     connect \Y $eq$ls180.v:6318$1989_Y
103724   end
103725   attribute \src "ls180.v:6320.97-6320.142"
103726   cell $eq $eq$ls180.v:6320$1992
103727     parameter \A_SIGNED 0
103728     parameter \A_WIDTH 4
103729     parameter \B_SIGNED 0
103730     parameter \B_WIDTH 3
103731     parameter \Y_WIDTH 1
103732     connect \A \builder_interface11_bank_bus_adr [3:0]
103733     connect \B 3'101
103734     connect \Y $eq$ls180.v:6320$1992_Y
103735   end
103736   attribute \src "ls180.v:6321.100-6321.145"
103737   cell $eq $eq$ls180.v:6321$1996
103738     parameter \A_SIGNED 0
103739     parameter \A_WIDTH 4
103740     parameter \B_SIGNED 0
103741     parameter \B_WIDTH 3
103742     parameter \Y_WIDTH 1
103743     connect \A \builder_interface11_bank_bus_adr [3:0]
103744     connect \B 3'101
103745     connect \Y $eq$ls180.v:6321$1996_Y
103746   end
103747   attribute \src "ls180.v:6323.103-6323.148"
103748   cell $eq $eq$ls180.v:6323$1999
103749     parameter \A_SIGNED 0
103750     parameter \A_WIDTH 4
103751     parameter \B_SIGNED 0
103752     parameter \B_WIDTH 3
103753     parameter \Y_WIDTH 1
103754     connect \A \builder_interface11_bank_bus_adr [3:0]
103755     connect \B 3'110
103756     connect \Y $eq$ls180.v:6323$1999_Y
103757   end
103758   attribute \src "ls180.v:6324.106-6324.151"
103759   cell $eq $eq$ls180.v:6324$2003
103760     parameter \A_SIGNED 0
103761     parameter \A_WIDTH 4
103762     parameter \B_SIGNED 0
103763     parameter \B_WIDTH 3
103764     parameter \Y_WIDTH 1
103765     connect \A \builder_interface11_bank_bus_adr [3:0]
103766     connect \B 3'110
103767     connect \Y $eq$ls180.v:6324$2003_Y
103768   end
103769   attribute \src "ls180.v:6326.106-6326.151"
103770   cell $eq $eq$ls180.v:6326$2006
103771     parameter \A_SIGNED 0
103772     parameter \A_WIDTH 4
103773     parameter \B_SIGNED 0
103774     parameter \B_WIDTH 3
103775     parameter \Y_WIDTH 1
103776     connect \A \builder_interface11_bank_bus_adr [3:0]
103777     connect \B 3'111
103778     connect \Y $eq$ls180.v:6326$2006_Y
103779   end
103780   attribute \src "ls180.v:6327.109-6327.154"
103781   cell $eq $eq$ls180.v:6327$2010
103782     parameter \A_SIGNED 0
103783     parameter \A_WIDTH 4
103784     parameter \B_SIGNED 0
103785     parameter \B_WIDTH 3
103786     parameter \Y_WIDTH 1
103787     connect \A \builder_interface11_bank_bus_adr [3:0]
103788     connect \B 3'111
103789     connect \Y $eq$ls180.v:6327$2010_Y
103790   end
103791   attribute \src "ls180.v:6329.106-6329.151"
103792   cell $eq $eq$ls180.v:6329$2013
103793     parameter \A_SIGNED 0
103794     parameter \A_WIDTH 4
103795     parameter \B_SIGNED 0
103796     parameter \B_WIDTH 4
103797     parameter \Y_WIDTH 1
103798     connect \A \builder_interface11_bank_bus_adr [3:0]
103799     connect \B 4'1000
103800     connect \Y $eq$ls180.v:6329$2013_Y
103801   end
103802   attribute \src "ls180.v:6330.109-6330.154"
103803   cell $eq $eq$ls180.v:6330$2017
103804     parameter \A_SIGNED 0
103805     parameter \A_WIDTH 4
103806     parameter \B_SIGNED 0
103807     parameter \B_WIDTH 4
103808     parameter \Y_WIDTH 1
103809     connect \A \builder_interface11_bank_bus_adr [3:0]
103810     connect \B 4'1000
103811     connect \Y $eq$ls180.v:6330$2017_Y
103812   end
103813   attribute \src "ls180.v:6351.33-6351.79"
103814   cell $eq $eq$ls180.v:6351$2020
103815     parameter \A_SIGNED 0
103816     parameter \A_WIDTH 5
103817     parameter \B_SIGNED 0
103818     parameter \B_WIDTH 2
103819     parameter \Y_WIDTH 1
103820     connect \A \builder_interface12_bank_bus_adr [13:9]
103821     connect \B 2'10
103822     connect \Y $eq$ls180.v:6351$2020_Y
103823   end
103824   attribute \src "ls180.v:6353.99-6353.144"
103825   cell $eq $eq$ls180.v:6353$2022
103826     parameter \A_SIGNED 0
103827     parameter \A_WIDTH 5
103828     parameter \B_SIGNED 0
103829     parameter \B_WIDTH 1
103830     parameter \Y_WIDTH 1
103831     connect \A \builder_interface12_bank_bus_adr [4:0]
103832     connect \B 1'0
103833     connect \Y $eq$ls180.v:6353$2022_Y
103834   end
103835   attribute \src "ls180.v:6354.102-6354.147"
103836   cell $eq $eq$ls180.v:6354$2026
103837     parameter \A_SIGNED 0
103838     parameter \A_WIDTH 5
103839     parameter \B_SIGNED 0
103840     parameter \B_WIDTH 1
103841     parameter \Y_WIDTH 1
103842     connect \A \builder_interface12_bank_bus_adr [4:0]
103843     connect \B 1'0
103844     connect \Y $eq$ls180.v:6354$2026_Y
103845   end
103846   attribute \src "ls180.v:6356.99-6356.144"
103847   cell $eq $eq$ls180.v:6356$2029
103848     parameter \A_SIGNED 0
103849     parameter \A_WIDTH 5
103850     parameter \B_SIGNED 0
103851     parameter \B_WIDTH 1
103852     parameter \Y_WIDTH 1
103853     connect \A \builder_interface12_bank_bus_adr [4:0]
103854     connect \B 1'1
103855     connect \Y $eq$ls180.v:6356$2029_Y
103856   end
103857   attribute \src "ls180.v:6357.102-6357.147"
103858   cell $eq $eq$ls180.v:6357$2033
103859     parameter \A_SIGNED 0
103860     parameter \A_WIDTH 5
103861     parameter \B_SIGNED 0
103862     parameter \B_WIDTH 1
103863     parameter \Y_WIDTH 1
103864     connect \A \builder_interface12_bank_bus_adr [4:0]
103865     connect \B 1'1
103866     connect \Y $eq$ls180.v:6357$2033_Y
103867   end
103868   attribute \src "ls180.v:6359.99-6359.144"
103869   cell $eq $eq$ls180.v:6359$2036
103870     parameter \A_SIGNED 0
103871     parameter \A_WIDTH 5
103872     parameter \B_SIGNED 0
103873     parameter \B_WIDTH 2
103874     parameter \Y_WIDTH 1
103875     connect \A \builder_interface12_bank_bus_adr [4:0]
103876     connect \B 2'10
103877     connect \Y $eq$ls180.v:6359$2036_Y
103878   end
103879   attribute \src "ls180.v:6360.102-6360.147"
103880   cell $eq $eq$ls180.v:6360$2040
103881     parameter \A_SIGNED 0
103882     parameter \A_WIDTH 5
103883     parameter \B_SIGNED 0
103884     parameter \B_WIDTH 2
103885     parameter \Y_WIDTH 1
103886     connect \A \builder_interface12_bank_bus_adr [4:0]
103887     connect \B 2'10
103888     connect \Y $eq$ls180.v:6360$2040_Y
103889   end
103890   attribute \src "ls180.v:6362.99-6362.144"
103891   cell $eq $eq$ls180.v:6362$2043
103892     parameter \A_SIGNED 0
103893     parameter \A_WIDTH 5
103894     parameter \B_SIGNED 0
103895     parameter \B_WIDTH 2
103896     parameter \Y_WIDTH 1
103897     connect \A \builder_interface12_bank_bus_adr [4:0]
103898     connect \B 2'11
103899     connect \Y $eq$ls180.v:6362$2043_Y
103900   end
103901   attribute \src "ls180.v:6363.102-6363.147"
103902   cell $eq $eq$ls180.v:6363$2047
103903     parameter \A_SIGNED 0
103904     parameter \A_WIDTH 5
103905     parameter \B_SIGNED 0
103906     parameter \B_WIDTH 2
103907     parameter \Y_WIDTH 1
103908     connect \A \builder_interface12_bank_bus_adr [4:0]
103909     connect \B 2'11
103910     connect \Y $eq$ls180.v:6363$2047_Y
103911   end
103912   attribute \src "ls180.v:6365.101-6365.146"
103913   cell $eq $eq$ls180.v:6365$2050
103914     parameter \A_SIGNED 0
103915     parameter \A_WIDTH 5
103916     parameter \B_SIGNED 0
103917     parameter \B_WIDTH 3
103918     parameter \Y_WIDTH 1
103919     connect \A \builder_interface12_bank_bus_adr [4:0]
103920     connect \B 3'100
103921     connect \Y $eq$ls180.v:6365$2050_Y
103922   end
103923   attribute \src "ls180.v:6366.104-6366.149"
103924   cell $eq $eq$ls180.v:6366$2054
103925     parameter \A_SIGNED 0
103926     parameter \A_WIDTH 5
103927     parameter \B_SIGNED 0
103928     parameter \B_WIDTH 3
103929     parameter \Y_WIDTH 1
103930     connect \A \builder_interface12_bank_bus_adr [4:0]
103931     connect \B 3'100
103932     connect \Y $eq$ls180.v:6366$2054_Y
103933   end
103934   attribute \src "ls180.v:6368.101-6368.146"
103935   cell $eq $eq$ls180.v:6368$2057
103936     parameter \A_SIGNED 0
103937     parameter \A_WIDTH 5
103938     parameter \B_SIGNED 0
103939     parameter \B_WIDTH 3
103940     parameter \Y_WIDTH 1
103941     connect \A \builder_interface12_bank_bus_adr [4:0]
103942     connect \B 3'101
103943     connect \Y $eq$ls180.v:6368$2057_Y
103944   end
103945   attribute \src "ls180.v:6369.104-6369.149"
103946   cell $eq $eq$ls180.v:6369$2061
103947     parameter \A_SIGNED 0
103948     parameter \A_WIDTH 5
103949     parameter \B_SIGNED 0
103950     parameter \B_WIDTH 3
103951     parameter \Y_WIDTH 1
103952     connect \A \builder_interface12_bank_bus_adr [4:0]
103953     connect \B 3'101
103954     connect \Y $eq$ls180.v:6369$2061_Y
103955   end
103956   attribute \src "ls180.v:6371.101-6371.146"
103957   cell $eq $eq$ls180.v:6371$2064
103958     parameter \A_SIGNED 0
103959     parameter \A_WIDTH 5
103960     parameter \B_SIGNED 0
103961     parameter \B_WIDTH 3
103962     parameter \Y_WIDTH 1
103963     connect \A \builder_interface12_bank_bus_adr [4:0]
103964     connect \B 3'110
103965     connect \Y $eq$ls180.v:6371$2064_Y
103966   end
103967   attribute \src "ls180.v:6372.104-6372.149"
103968   cell $eq $eq$ls180.v:6372$2068
103969     parameter \A_SIGNED 0
103970     parameter \A_WIDTH 5
103971     parameter \B_SIGNED 0
103972     parameter \B_WIDTH 3
103973     parameter \Y_WIDTH 1
103974     connect \A \builder_interface12_bank_bus_adr [4:0]
103975     connect \B 3'110
103976     connect \Y $eq$ls180.v:6372$2068_Y
103977   end
103978   attribute \src "ls180.v:6374.101-6374.146"
103979   cell $eq $eq$ls180.v:6374$2071
103980     parameter \A_SIGNED 0
103981     parameter \A_WIDTH 5
103982     parameter \B_SIGNED 0
103983     parameter \B_WIDTH 3
103984     parameter \Y_WIDTH 1
103985     connect \A \builder_interface12_bank_bus_adr [4:0]
103986     connect \B 3'111
103987     connect \Y $eq$ls180.v:6374$2071_Y
103988   end
103989   attribute \src "ls180.v:6375.104-6375.149"
103990   cell $eq $eq$ls180.v:6375$2075
103991     parameter \A_SIGNED 0
103992     parameter \A_WIDTH 5
103993     parameter \B_SIGNED 0
103994     parameter \B_WIDTH 3
103995     parameter \Y_WIDTH 1
103996     connect \A \builder_interface12_bank_bus_adr [4:0]
103997     connect \B 3'111
103998     connect \Y $eq$ls180.v:6375$2075_Y
103999   end
104000   attribute \src "ls180.v:6377.97-6377.142"
104001   cell $eq $eq$ls180.v:6377$2078
104002     parameter \A_SIGNED 0
104003     parameter \A_WIDTH 5
104004     parameter \B_SIGNED 0
104005     parameter \B_WIDTH 4
104006     parameter \Y_WIDTH 1
104007     connect \A \builder_interface12_bank_bus_adr [4:0]
104008     connect \B 4'1000
104009     connect \Y $eq$ls180.v:6377$2078_Y
104010   end
104011   attribute \src "ls180.v:6378.100-6378.145"
104012   cell $eq $eq$ls180.v:6378$2082
104013     parameter \A_SIGNED 0
104014     parameter \A_WIDTH 5
104015     parameter \B_SIGNED 0
104016     parameter \B_WIDTH 4
104017     parameter \Y_WIDTH 1
104018     connect \A \builder_interface12_bank_bus_adr [4:0]
104019     connect \B 4'1000
104020     connect \Y $eq$ls180.v:6378$2082_Y
104021   end
104022   attribute \src "ls180.v:6380.107-6380.152"
104023   cell $eq $eq$ls180.v:6380$2085
104024     parameter \A_SIGNED 0
104025     parameter \A_WIDTH 5
104026     parameter \B_SIGNED 0
104027     parameter \B_WIDTH 4
104028     parameter \Y_WIDTH 1
104029     connect \A \builder_interface12_bank_bus_adr [4:0]
104030     connect \B 4'1001
104031     connect \Y $eq$ls180.v:6380$2085_Y
104032   end
104033   attribute \src "ls180.v:6381.110-6381.155"
104034   cell $eq $eq$ls180.v:6381$2089
104035     parameter \A_SIGNED 0
104036     parameter \A_WIDTH 5
104037     parameter \B_SIGNED 0
104038     parameter \B_WIDTH 4
104039     parameter \Y_WIDTH 1
104040     connect \A \builder_interface12_bank_bus_adr [4:0]
104041     connect \B 4'1001
104042     connect \Y $eq$ls180.v:6381$2089_Y
104043   end
104044   attribute \src "ls180.v:6383.100-6383.146"
104045   cell $eq $eq$ls180.v:6383$2092
104046     parameter \A_SIGNED 0
104047     parameter \A_WIDTH 5
104048     parameter \B_SIGNED 0
104049     parameter \B_WIDTH 4
104050     parameter \Y_WIDTH 1
104051     connect \A \builder_interface12_bank_bus_adr [4:0]
104052     connect \B 4'1010
104053     connect \Y $eq$ls180.v:6383$2092_Y
104054   end
104055   attribute \src "ls180.v:6384.103-6384.149"
104056   cell $eq $eq$ls180.v:6384$2096
104057     parameter \A_SIGNED 0
104058     parameter \A_WIDTH 5
104059     parameter \B_SIGNED 0
104060     parameter \B_WIDTH 4
104061     parameter \Y_WIDTH 1
104062     connect \A \builder_interface12_bank_bus_adr [4:0]
104063     connect \B 4'1010
104064     connect \Y $eq$ls180.v:6384$2096_Y
104065   end
104066   attribute \src "ls180.v:6386.100-6386.146"
104067   cell $eq $eq$ls180.v:6386$2099
104068     parameter \A_SIGNED 0
104069     parameter \A_WIDTH 5
104070     parameter \B_SIGNED 0
104071     parameter \B_WIDTH 4
104072     parameter \Y_WIDTH 1
104073     connect \A \builder_interface12_bank_bus_adr [4:0]
104074     connect \B 4'1011
104075     connect \Y $eq$ls180.v:6386$2099_Y
104076   end
104077   attribute \src "ls180.v:6387.103-6387.149"
104078   cell $eq $eq$ls180.v:6387$2103
104079     parameter \A_SIGNED 0
104080     parameter \A_WIDTH 5
104081     parameter \B_SIGNED 0
104082     parameter \B_WIDTH 4
104083     parameter \Y_WIDTH 1
104084     connect \A \builder_interface12_bank_bus_adr [4:0]
104085     connect \B 4'1011
104086     connect \Y $eq$ls180.v:6387$2103_Y
104087   end
104088   attribute \src "ls180.v:6389.100-6389.146"
104089   cell $eq $eq$ls180.v:6389$2106
104090     parameter \A_SIGNED 0
104091     parameter \A_WIDTH 5
104092     parameter \B_SIGNED 0
104093     parameter \B_WIDTH 4
104094     parameter \Y_WIDTH 1
104095     connect \A \builder_interface12_bank_bus_adr [4:0]
104096     connect \B 4'1100
104097     connect \Y $eq$ls180.v:6389$2106_Y
104098   end
104099   attribute \src "ls180.v:6390.103-6390.149"
104100   cell $eq $eq$ls180.v:6390$2110
104101     parameter \A_SIGNED 0
104102     parameter \A_WIDTH 5
104103     parameter \B_SIGNED 0
104104     parameter \B_WIDTH 4
104105     parameter \Y_WIDTH 1
104106     connect \A \builder_interface12_bank_bus_adr [4:0]
104107     connect \B 4'1100
104108     connect \Y $eq$ls180.v:6390$2110_Y
104109   end
104110   attribute \src "ls180.v:6392.100-6392.146"
104111   cell $eq $eq$ls180.v:6392$2113
104112     parameter \A_SIGNED 0
104113     parameter \A_WIDTH 5
104114     parameter \B_SIGNED 0
104115     parameter \B_WIDTH 4
104116     parameter \Y_WIDTH 1
104117     connect \A \builder_interface12_bank_bus_adr [4:0]
104118     connect \B 4'1101
104119     connect \Y $eq$ls180.v:6392$2113_Y
104120   end
104121   attribute \src "ls180.v:6393.103-6393.149"
104122   cell $eq $eq$ls180.v:6393$2117
104123     parameter \A_SIGNED 0
104124     parameter \A_WIDTH 5
104125     parameter \B_SIGNED 0
104126     parameter \B_WIDTH 4
104127     parameter \Y_WIDTH 1
104128     connect \A \builder_interface12_bank_bus_adr [4:0]
104129     connect \B 4'1101
104130     connect \Y $eq$ls180.v:6393$2117_Y
104131   end
104132   attribute \src "ls180.v:6395.112-6395.158"
104133   cell $eq $eq$ls180.v:6395$2120
104134     parameter \A_SIGNED 0
104135     parameter \A_WIDTH 5
104136     parameter \B_SIGNED 0
104137     parameter \B_WIDTH 4
104138     parameter \Y_WIDTH 1
104139     connect \A \builder_interface12_bank_bus_adr [4:0]
104140     connect \B 4'1110
104141     connect \Y $eq$ls180.v:6395$2120_Y
104142   end
104143   attribute \src "ls180.v:6396.115-6396.161"
104144   cell $eq $eq$ls180.v:6396$2124
104145     parameter \A_SIGNED 0
104146     parameter \A_WIDTH 5
104147     parameter \B_SIGNED 0
104148     parameter \B_WIDTH 4
104149     parameter \Y_WIDTH 1
104150     connect \A \builder_interface12_bank_bus_adr [4:0]
104151     connect \B 4'1110
104152     connect \Y $eq$ls180.v:6396$2124_Y
104153   end
104154   attribute \src "ls180.v:6398.113-6398.159"
104155   cell $eq $eq$ls180.v:6398$2127
104156     parameter \A_SIGNED 0
104157     parameter \A_WIDTH 5
104158     parameter \B_SIGNED 0
104159     parameter \B_WIDTH 4
104160     parameter \Y_WIDTH 1
104161     connect \A \builder_interface12_bank_bus_adr [4:0]
104162     connect \B 4'1111
104163     connect \Y $eq$ls180.v:6398$2127_Y
104164   end
104165   attribute \src "ls180.v:6399.116-6399.162"
104166   cell $eq $eq$ls180.v:6399$2131
104167     parameter \A_SIGNED 0
104168     parameter \A_WIDTH 5
104169     parameter \B_SIGNED 0
104170     parameter \B_WIDTH 4
104171     parameter \Y_WIDTH 1
104172     connect \A \builder_interface12_bank_bus_adr [4:0]
104173     connect \B 4'1111
104174     connect \Y $eq$ls180.v:6399$2131_Y
104175   end
104176   attribute \src "ls180.v:6401.104-6401.150"
104177   cell $eq $eq$ls180.v:6401$2134
104178     parameter \A_SIGNED 0
104179     parameter \A_WIDTH 5
104180     parameter \B_SIGNED 0
104181     parameter \B_WIDTH 5
104182     parameter \Y_WIDTH 1
104183     connect \A \builder_interface12_bank_bus_adr [4:0]
104184     connect \B 5'10000
104185     connect \Y $eq$ls180.v:6401$2134_Y
104186   end
104187   attribute \src "ls180.v:6402.107-6402.153"
104188   cell $eq $eq$ls180.v:6402$2138
104189     parameter \A_SIGNED 0
104190     parameter \A_WIDTH 5
104191     parameter \B_SIGNED 0
104192     parameter \B_WIDTH 5
104193     parameter \Y_WIDTH 1
104194     connect \A \builder_interface12_bank_bus_adr [4:0]
104195     connect \B 5'10000
104196     connect \Y $eq$ls180.v:6402$2138_Y
104197   end
104198   attribute \src "ls180.v:6419.33-6419.79"
104199   cell $eq $eq$ls180.v:6419$2140
104200     parameter \A_SIGNED 0
104201     parameter \A_WIDTH 5
104202     parameter \B_SIGNED 0
104203     parameter \B_WIDTH 3
104204     parameter \Y_WIDTH 1
104205     connect \A \builder_interface13_bank_bus_adr [13:9]
104206     connect \B 3'101
104207     connect \Y $eq$ls180.v:6419$2140_Y
104208   end
104209   attribute \src "ls180.v:6421.90-6421.135"
104210   cell $eq $eq$ls180.v:6421$2142
104211     parameter \A_SIGNED 0
104212     parameter \A_WIDTH 3
104213     parameter \B_SIGNED 0
104214     parameter \B_WIDTH 1
104215     parameter \Y_WIDTH 1
104216     connect \A \builder_interface13_bank_bus_adr [2:0]
104217     connect \B 1'0
104218     connect \Y $eq$ls180.v:6421$2142_Y
104219   end
104220   attribute \src "ls180.v:6422.93-6422.138"
104221   cell $eq $eq$ls180.v:6422$2146
104222     parameter \A_SIGNED 0
104223     parameter \A_WIDTH 3
104224     parameter \B_SIGNED 0
104225     parameter \B_WIDTH 1
104226     parameter \Y_WIDTH 1
104227     connect \A \builder_interface13_bank_bus_adr [2:0]
104228     connect \B 1'0
104229     connect \Y $eq$ls180.v:6422$2146_Y
104230   end
104231   attribute \src "ls180.v:6424.100-6424.145"
104232   cell $eq $eq$ls180.v:6424$2149
104233     parameter \A_SIGNED 0
104234     parameter \A_WIDTH 3
104235     parameter \B_SIGNED 0
104236     parameter \B_WIDTH 1
104237     parameter \Y_WIDTH 1
104238     connect \A \builder_interface13_bank_bus_adr [2:0]
104239     connect \B 1'1
104240     connect \Y $eq$ls180.v:6424$2149_Y
104241   end
104242   attribute \src "ls180.v:6425.103-6425.148"
104243   cell $eq $eq$ls180.v:6425$2153
104244     parameter \A_SIGNED 0
104245     parameter \A_WIDTH 3
104246     parameter \B_SIGNED 0
104247     parameter \B_WIDTH 1
104248     parameter \Y_WIDTH 1
104249     connect \A \builder_interface13_bank_bus_adr [2:0]
104250     connect \B 1'1
104251     connect \Y $eq$ls180.v:6425$2153_Y
104252   end
104253   attribute \src "ls180.v:6427.101-6427.146"
104254   cell $eq $eq$ls180.v:6427$2156
104255     parameter \A_SIGNED 0
104256     parameter \A_WIDTH 3
104257     parameter \B_SIGNED 0
104258     parameter \B_WIDTH 2
104259     parameter \Y_WIDTH 1
104260     connect \A \builder_interface13_bank_bus_adr [2:0]
104261     connect \B 2'10
104262     connect \Y $eq$ls180.v:6427$2156_Y
104263   end
104264   attribute \src "ls180.v:6428.104-6428.149"
104265   cell $eq $eq$ls180.v:6428$2160
104266     parameter \A_SIGNED 0
104267     parameter \A_WIDTH 3
104268     parameter \B_SIGNED 0
104269     parameter \B_WIDTH 2
104270     parameter \Y_WIDTH 1
104271     connect \A \builder_interface13_bank_bus_adr [2:0]
104272     connect \B 2'10
104273     connect \Y $eq$ls180.v:6428$2160_Y
104274   end
104275   attribute \src "ls180.v:6430.105-6430.150"
104276   cell $eq $eq$ls180.v:6430$2163
104277     parameter \A_SIGNED 0
104278     parameter \A_WIDTH 3
104279     parameter \B_SIGNED 0
104280     parameter \B_WIDTH 2
104281     parameter \Y_WIDTH 1
104282     connect \A \builder_interface13_bank_bus_adr [2:0]
104283     connect \B 2'11
104284     connect \Y $eq$ls180.v:6430$2163_Y
104285   end
104286   attribute \src "ls180.v:6431.108-6431.153"
104287   cell $eq $eq$ls180.v:6431$2167
104288     parameter \A_SIGNED 0
104289     parameter \A_WIDTH 3
104290     parameter \B_SIGNED 0
104291     parameter \B_WIDTH 2
104292     parameter \Y_WIDTH 1
104293     connect \A \builder_interface13_bank_bus_adr [2:0]
104294     connect \B 2'11
104295     connect \Y $eq$ls180.v:6431$2167_Y
104296   end
104297   attribute \src "ls180.v:6433.106-6433.151"
104298   cell $eq $eq$ls180.v:6433$2170
104299     parameter \A_SIGNED 0
104300     parameter \A_WIDTH 3
104301     parameter \B_SIGNED 0
104302     parameter \B_WIDTH 3
104303     parameter \Y_WIDTH 1
104304     connect \A \builder_interface13_bank_bus_adr [2:0]
104305     connect \B 3'100
104306     connect \Y $eq$ls180.v:6433$2170_Y
104307   end
104308   attribute \src "ls180.v:6434.109-6434.154"
104309   cell $eq $eq$ls180.v:6434$2174
104310     parameter \A_SIGNED 0
104311     parameter \A_WIDTH 3
104312     parameter \B_SIGNED 0
104313     parameter \B_WIDTH 3
104314     parameter \Y_WIDTH 1
104315     connect \A \builder_interface13_bank_bus_adr [2:0]
104316     connect \B 3'100
104317     connect \Y $eq$ls180.v:6434$2174_Y
104318   end
104319   attribute \src "ls180.v:6436.104-6436.149"
104320   cell $eq $eq$ls180.v:6436$2177
104321     parameter \A_SIGNED 0
104322     parameter \A_WIDTH 3
104323     parameter \B_SIGNED 0
104324     parameter \B_WIDTH 3
104325     parameter \Y_WIDTH 1
104326     connect \A \builder_interface13_bank_bus_adr [2:0]
104327     connect \B 3'101
104328     connect \Y $eq$ls180.v:6436$2177_Y
104329   end
104330   attribute \src "ls180.v:6437.107-6437.152"
104331   cell $eq $eq$ls180.v:6437$2181
104332     parameter \A_SIGNED 0
104333     parameter \A_WIDTH 3
104334     parameter \B_SIGNED 0
104335     parameter \B_WIDTH 3
104336     parameter \Y_WIDTH 1
104337     connect \A \builder_interface13_bank_bus_adr [2:0]
104338     connect \B 3'101
104339     connect \Y $eq$ls180.v:6437$2181_Y
104340   end
104341   attribute \src "ls180.v:6439.101-6439.146"
104342   cell $eq $eq$ls180.v:6439$2184
104343     parameter \A_SIGNED 0
104344     parameter \A_WIDTH 3
104345     parameter \B_SIGNED 0
104346     parameter \B_WIDTH 3
104347     parameter \Y_WIDTH 1
104348     connect \A \builder_interface13_bank_bus_adr [2:0]
104349     connect \B 3'110
104350     connect \Y $eq$ls180.v:6439$2184_Y
104351   end
104352   attribute \src "ls180.v:6440.104-6440.149"
104353   cell $eq $eq$ls180.v:6440$2188
104354     parameter \A_SIGNED 0
104355     parameter \A_WIDTH 3
104356     parameter \B_SIGNED 0
104357     parameter \B_WIDTH 3
104358     parameter \Y_WIDTH 1
104359     connect \A \builder_interface13_bank_bus_adr [2:0]
104360     connect \B 3'110
104361     connect \Y $eq$ls180.v:6440$2188_Y
104362   end
104363   attribute \src "ls180.v:6442.100-6442.145"
104364   cell $eq $eq$ls180.v:6442$2191
104365     parameter \A_SIGNED 0
104366     parameter \A_WIDTH 3
104367     parameter \B_SIGNED 0
104368     parameter \B_WIDTH 3
104369     parameter \Y_WIDTH 1
104370     connect \A \builder_interface13_bank_bus_adr [2:0]
104371     connect \B 3'111
104372     connect \Y $eq$ls180.v:6442$2191_Y
104373   end
104374   attribute \src "ls180.v:6443.103-6443.148"
104375   cell $eq $eq$ls180.v:6443$2195
104376     parameter \A_SIGNED 0
104377     parameter \A_WIDTH 3
104378     parameter \B_SIGNED 0
104379     parameter \B_WIDTH 3
104380     parameter \Y_WIDTH 1
104381     connect \A \builder_interface13_bank_bus_adr [2:0]
104382     connect \B 3'111
104383     connect \Y $eq$ls180.v:6443$2195_Y
104384   end
104385   attribute \src "ls180.v:6453.33-6453.79"
104386   cell $eq $eq$ls180.v:6453$2197
104387     parameter \A_SIGNED 0
104388     parameter \A_WIDTH 5
104389     parameter \B_SIGNED 0
104390     parameter \B_WIDTH 3
104391     parameter \Y_WIDTH 1
104392     connect \A \builder_interface14_bank_bus_adr [13:9]
104393     connect \B 3'100
104394     connect \Y $eq$ls180.v:6453$2197_Y
104395   end
104396   attribute \src "ls180.v:6455.106-6455.151"
104397   cell $eq $eq$ls180.v:6455$2199
104398     parameter \A_SIGNED 0
104399     parameter \A_WIDTH 2
104400     parameter \B_SIGNED 0
104401     parameter \B_WIDTH 1
104402     parameter \Y_WIDTH 1
104403     connect \A \builder_interface14_bank_bus_adr [1:0]
104404     connect \B 1'0
104405     connect \Y $eq$ls180.v:6455$2199_Y
104406   end
104407   attribute \src "ls180.v:6456.109-6456.154"
104408   cell $eq $eq$ls180.v:6456$2203
104409     parameter \A_SIGNED 0
104410     parameter \A_WIDTH 2
104411     parameter \B_SIGNED 0
104412     parameter \B_WIDTH 1
104413     parameter \Y_WIDTH 1
104414     connect \A \builder_interface14_bank_bus_adr [1:0]
104415     connect \B 1'0
104416     connect \Y $eq$ls180.v:6456$2203_Y
104417   end
104418   attribute \src "ls180.v:6458.106-6458.151"
104419   cell $eq $eq$ls180.v:6458$2206
104420     parameter \A_SIGNED 0
104421     parameter \A_WIDTH 2
104422     parameter \B_SIGNED 0
104423     parameter \B_WIDTH 1
104424     parameter \Y_WIDTH 1
104425     connect \A \builder_interface14_bank_bus_adr [1:0]
104426     connect \B 1'1
104427     connect \Y $eq$ls180.v:6458$2206_Y
104428   end
104429   attribute \src "ls180.v:6459.109-6459.154"
104430   cell $eq $eq$ls180.v:6459$2210
104431     parameter \A_SIGNED 0
104432     parameter \A_WIDTH 2
104433     parameter \B_SIGNED 0
104434     parameter \B_WIDTH 1
104435     parameter \Y_WIDTH 1
104436     connect \A \builder_interface14_bank_bus_adr [1:0]
104437     connect \B 1'1
104438     connect \Y $eq$ls180.v:6459$2210_Y
104439   end
104440   attribute \src "ls180.v:6461.106-6461.151"
104441   cell $eq $eq$ls180.v:6461$2213
104442     parameter \A_SIGNED 0
104443     parameter \A_WIDTH 2
104444     parameter \B_SIGNED 0
104445     parameter \B_WIDTH 2
104446     parameter \Y_WIDTH 1
104447     connect \A \builder_interface14_bank_bus_adr [1:0]
104448     connect \B 2'10
104449     connect \Y $eq$ls180.v:6461$2213_Y
104450   end
104451   attribute \src "ls180.v:6462.109-6462.154"
104452   cell $eq $eq$ls180.v:6462$2217
104453     parameter \A_SIGNED 0
104454     parameter \A_WIDTH 2
104455     parameter \B_SIGNED 0
104456     parameter \B_WIDTH 2
104457     parameter \Y_WIDTH 1
104458     connect \A \builder_interface14_bank_bus_adr [1:0]
104459     connect \B 2'10
104460     connect \Y $eq$ls180.v:6462$2217_Y
104461   end
104462   attribute \src "ls180.v:6464.106-6464.151"
104463   cell $eq $eq$ls180.v:6464$2220
104464     parameter \A_SIGNED 0
104465     parameter \A_WIDTH 2
104466     parameter \B_SIGNED 0
104467     parameter \B_WIDTH 2
104468     parameter \Y_WIDTH 1
104469     connect \A \builder_interface14_bank_bus_adr [1:0]
104470     connect \B 2'11
104471     connect \Y $eq$ls180.v:6464$2220_Y
104472   end
104473   attribute \src "ls180.v:6465.109-6465.154"
104474   cell $eq $eq$ls180.v:6465$2224
104475     parameter \A_SIGNED 0
104476     parameter \A_WIDTH 2
104477     parameter \B_SIGNED 0
104478     parameter \B_WIDTH 2
104479     parameter \Y_WIDTH 1
104480     connect \A \builder_interface14_bank_bus_adr [1:0]
104481     connect \B 2'11
104482     connect \Y $eq$ls180.v:6465$2224_Y
104483   end
104484   attribute \src "ls180.v:6846.41-6846.81"
104485   cell $eq $eq$ls180.v:6846$2261
104486     parameter \A_SIGNED 0
104487     parameter \A_WIDTH 2
104488     parameter \B_SIGNED 0
104489     parameter \B_WIDTH 1
104490     parameter \Y_WIDTH 1
104491     connect \A \main_port_cmd_payload_addr [10:9]
104492     connect \B 1'0
104493     connect \Y $eq$ls180.v:6846$2261_Y
104494   end
104495   attribute \src "ls180.v:6846.144-6846.177"
104496   cell $eq $eq$ls180.v:6846$2262
104497     parameter \A_SIGNED 0
104498     parameter \A_WIDTH 1
104499     parameter \B_SIGNED 0
104500     parameter \B_WIDTH 1
104501     parameter \Y_WIDTH 1
104502     connect \A \builder_roundrobin1_grant
104503     connect \B 1'0
104504     connect \Y $eq$ls180.v:6846$2262_Y
104505   end
104506   attribute \src "ls180.v:6846.219-6846.252"
104507   cell $eq $eq$ls180.v:6846$2265
104508     parameter \A_SIGNED 0
104509     parameter \A_WIDTH 1
104510     parameter \B_SIGNED 0
104511     parameter \B_WIDTH 1
104512     parameter \Y_WIDTH 1
104513     connect \A \builder_roundrobin2_grant
104514     connect \B 1'0
104515     connect \Y $eq$ls180.v:6846$2265_Y
104516   end
104517   attribute \src "ls180.v:6846.294-6846.327"
104518   cell $eq $eq$ls180.v:6846$2268
104519     parameter \A_SIGNED 0
104520     parameter \A_WIDTH 1
104521     parameter \B_SIGNED 0
104522     parameter \B_WIDTH 1
104523     parameter \Y_WIDTH 1
104524     connect \A \builder_roundrobin3_grant
104525     connect \B 1'0
104526     connect \Y $eq$ls180.v:6846$2268_Y
104527   end
104528   attribute \src "ls180.v:6870.41-6870.81"
104529   cell $eq $eq$ls180.v:6870$2277
104530     parameter \A_SIGNED 0
104531     parameter \A_WIDTH 2
104532     parameter \B_SIGNED 0
104533     parameter \B_WIDTH 1
104534     parameter \Y_WIDTH 1
104535     connect \A \main_port_cmd_payload_addr [10:9]
104536     connect \B 1'1
104537     connect \Y $eq$ls180.v:6870$2277_Y
104538   end
104539   attribute \src "ls180.v:6870.144-6870.177"
104540   cell $eq $eq$ls180.v:6870$2278
104541     parameter \A_SIGNED 0
104542     parameter \A_WIDTH 1
104543     parameter \B_SIGNED 0
104544     parameter \B_WIDTH 1
104545     parameter \Y_WIDTH 1
104546     connect \A \builder_roundrobin0_grant
104547     connect \B 1'0
104548     connect \Y $eq$ls180.v:6870$2278_Y
104549   end
104550   attribute \src "ls180.v:6870.219-6870.252"
104551   cell $eq $eq$ls180.v:6870$2281
104552     parameter \A_SIGNED 0
104553     parameter \A_WIDTH 1
104554     parameter \B_SIGNED 0
104555     parameter \B_WIDTH 1
104556     parameter \Y_WIDTH 1
104557     connect \A \builder_roundrobin2_grant
104558     connect \B 1'0
104559     connect \Y $eq$ls180.v:6870$2281_Y
104560   end
104561   attribute \src "ls180.v:6870.294-6870.327"
104562   cell $eq $eq$ls180.v:6870$2284
104563     parameter \A_SIGNED 0
104564     parameter \A_WIDTH 1
104565     parameter \B_SIGNED 0
104566     parameter \B_WIDTH 1
104567     parameter \Y_WIDTH 1
104568     connect \A \builder_roundrobin3_grant
104569     connect \B 1'0
104570     connect \Y $eq$ls180.v:6870$2284_Y
104571   end
104572   attribute \src "ls180.v:6894.41-6894.81"
104573   cell $eq $eq$ls180.v:6894$2293
104574     parameter \A_SIGNED 0
104575     parameter \A_WIDTH 2
104576     parameter \B_SIGNED 0
104577     parameter \B_WIDTH 2
104578     parameter \Y_WIDTH 1
104579     connect \A \main_port_cmd_payload_addr [10:9]
104580     connect \B 2'10
104581     connect \Y $eq$ls180.v:6894$2293_Y
104582   end
104583   attribute \src "ls180.v:6894.144-6894.177"
104584   cell $eq $eq$ls180.v:6894$2294
104585     parameter \A_SIGNED 0
104586     parameter \A_WIDTH 1
104587     parameter \B_SIGNED 0
104588     parameter \B_WIDTH 1
104589     parameter \Y_WIDTH 1
104590     connect \A \builder_roundrobin0_grant
104591     connect \B 1'0
104592     connect \Y $eq$ls180.v:6894$2294_Y
104593   end
104594   attribute \src "ls180.v:6894.219-6894.252"
104595   cell $eq $eq$ls180.v:6894$2297
104596     parameter \A_SIGNED 0
104597     parameter \A_WIDTH 1
104598     parameter \B_SIGNED 0
104599     parameter \B_WIDTH 1
104600     parameter \Y_WIDTH 1
104601     connect \A \builder_roundrobin1_grant
104602     connect \B 1'0
104603     connect \Y $eq$ls180.v:6894$2297_Y
104604   end
104605   attribute \src "ls180.v:6894.294-6894.327"
104606   cell $eq $eq$ls180.v:6894$2300
104607     parameter \A_SIGNED 0
104608     parameter \A_WIDTH 1
104609     parameter \B_SIGNED 0
104610     parameter \B_WIDTH 1
104611     parameter \Y_WIDTH 1
104612     connect \A \builder_roundrobin3_grant
104613     connect \B 1'0
104614     connect \Y $eq$ls180.v:6894$2300_Y
104615   end
104616   attribute \src "ls180.v:6918.41-6918.81"
104617   cell $eq $eq$ls180.v:6918$2309
104618     parameter \A_SIGNED 0
104619     parameter \A_WIDTH 2
104620     parameter \B_SIGNED 0
104621     parameter \B_WIDTH 2
104622     parameter \Y_WIDTH 1
104623     connect \A \main_port_cmd_payload_addr [10:9]
104624     connect \B 2'11
104625     connect \Y $eq$ls180.v:6918$2309_Y
104626   end
104627   attribute \src "ls180.v:6918.144-6918.177"
104628   cell $eq $eq$ls180.v:6918$2310
104629     parameter \A_SIGNED 0
104630     parameter \A_WIDTH 1
104631     parameter \B_SIGNED 0
104632     parameter \B_WIDTH 1
104633     parameter \Y_WIDTH 1
104634     connect \A \builder_roundrobin0_grant
104635     connect \B 1'0
104636     connect \Y $eq$ls180.v:6918$2310_Y
104637   end
104638   attribute \src "ls180.v:6918.219-6918.252"
104639   cell $eq $eq$ls180.v:6918$2313
104640     parameter \A_SIGNED 0
104641     parameter \A_WIDTH 1
104642     parameter \B_SIGNED 0
104643     parameter \B_WIDTH 1
104644     parameter \Y_WIDTH 1
104645     connect \A \builder_roundrobin1_grant
104646     connect \B 1'0
104647     connect \Y $eq$ls180.v:6918$2313_Y
104648   end
104649   attribute \src "ls180.v:6918.294-6918.327"
104650   cell $eq $eq$ls180.v:6918$2316
104651     parameter \A_SIGNED 0
104652     parameter \A_WIDTH 1
104653     parameter \B_SIGNED 0
104654     parameter \B_WIDTH 1
104655     parameter \Y_WIDTH 1
104656     connect \A \builder_roundrobin2_grant
104657     connect \B 1'0
104658     connect \Y $eq$ls180.v:6918$2316_Y
104659   end
104660   attribute \src "ls180.v:7511.8-7511.38"
104661   cell $eq $eq$ls180.v:7511$2419
104662     parameter \A_SIGNED 0
104663     parameter \A_WIDTH 32
104664     parameter \B_SIGNED 0
104665     parameter \B_WIDTH 1
104666     parameter \Y_WIDTH 1
104667     connect \A \main_libresocsim_value
104668     connect \B 1'0
104669     connect \Y $eq$ls180.v:7511$2419_Y
104670   end
104671   attribute \src "ls180.v:7542.8-7542.42"
104672   cell $eq $eq$ls180.v:7542$2427
104673     parameter \A_SIGNED 0
104674     parameter \A_WIDTH 1
104675     parameter \B_SIGNED 0
104676     parameter \B_WIDTH 1
104677     parameter \Y_WIDTH 1
104678     connect \A \main_sdram_postponer_count
104679     connect \B 1'0
104680     connect \Y $eq$ls180.v:7542$2427_Y
104681   end
104682   attribute \src "ls180.v:7562.38-7562.74"
104683   cell $eq $eq$ls180.v:7562$2430
104684     parameter \A_SIGNED 0
104685     parameter \A_WIDTH 4
104686     parameter \B_SIGNED 0
104687     parameter \B_WIDTH 1
104688     parameter \Y_WIDTH 1
104689     connect \A \main_sdram_sequencer_counter
104690     connect \B 1'0
104691     connect \Y $eq$ls180.v:7562$2430_Y
104692   end
104693   attribute \src "ls180.v:7569.7-7569.43"
104694   cell $eq $eq$ls180.v:7569$2432
104695     parameter \A_SIGNED 0
104696     parameter \A_WIDTH 4
104697     parameter \B_SIGNED 0
104698     parameter \B_WIDTH 2
104699     parameter \Y_WIDTH 1
104700     connect \A \main_sdram_sequencer_counter
104701     connect \B 2'10
104702     connect \Y $eq$ls180.v:7569$2432_Y
104703   end
104704   attribute \src "ls180.v:7576.7-7576.43"
104705   cell $eq $eq$ls180.v:7576$2433
104706     parameter \A_SIGNED 0
104707     parameter \A_WIDTH 4
104708     parameter \B_SIGNED 0
104709     parameter \B_WIDTH 4
104710     parameter \Y_WIDTH 1
104711     connect \A \main_sdram_sequencer_counter
104712     connect \B 4'1000
104713     connect \Y $eq$ls180.v:7576$2433_Y
104714   end
104715   attribute \src "ls180.v:7584.7-7584.43"
104716   cell $eq $eq$ls180.v:7584$2434
104717     parameter \A_SIGNED 0
104718     parameter \A_WIDTH 4
104719     parameter \B_SIGNED 0
104720     parameter \B_WIDTH 4
104721     parameter \Y_WIDTH 1
104722     connect \A \main_sdram_sequencer_counter
104723     connect \B 4'1000
104724     connect \Y $eq$ls180.v:7584$2434_Y
104725   end
104726   attribute \src "ls180.v:7636.9-7636.54"
104727   cell $eq $eq$ls180.v:7636$2452
104728     parameter \A_SIGNED 0
104729     parameter \A_WIDTH 3
104730     parameter \B_SIGNED 0
104731     parameter \B_WIDTH 1
104732     parameter \Y_WIDTH 1
104733     connect \A \main_sdram_bankmachine0_twtpcon_count
104734     connect \B 1'1
104735     connect \Y $eq$ls180.v:7636$2452_Y
104736   end
104737   attribute \src "ls180.v:7682.9-7682.54"
104738   cell $eq $eq$ls180.v:7682$2468
104739     parameter \A_SIGNED 0
104740     parameter \A_WIDTH 3
104741     parameter \B_SIGNED 0
104742     parameter \B_WIDTH 1
104743     parameter \Y_WIDTH 1
104744     connect \A \main_sdram_bankmachine1_twtpcon_count
104745     connect \B 1'1
104746     connect \Y $eq$ls180.v:7682$2468_Y
104747   end
104748   attribute \src "ls180.v:7728.9-7728.54"
104749   cell $eq $eq$ls180.v:7728$2484
104750     parameter \A_SIGNED 0
104751     parameter \A_WIDTH 3
104752     parameter \B_SIGNED 0
104753     parameter \B_WIDTH 1
104754     parameter \Y_WIDTH 1
104755     connect \A \main_sdram_bankmachine2_twtpcon_count
104756     connect \B 1'1
104757     connect \Y $eq$ls180.v:7728$2484_Y
104758   end
104759   attribute \src "ls180.v:7774.9-7774.54"
104760   cell $eq $eq$ls180.v:7774$2500
104761     parameter \A_SIGNED 0
104762     parameter \A_WIDTH 3
104763     parameter \B_SIGNED 0
104764     parameter \B_WIDTH 1
104765     parameter \Y_WIDTH 1
104766     connect \A \main_sdram_bankmachine3_twtpcon_count
104767     connect \B 1'1
104768     connect \Y $eq$ls180.v:7774$2500_Y
104769   end
104770   attribute \src "ls180.v:7924.9-7924.41"
104771   cell $eq $eq$ls180.v:7924$2512
104772     parameter \A_SIGNED 0
104773     parameter \A_WIDTH 1
104774     parameter \B_SIGNED 0
104775     parameter \B_WIDTH 1
104776     parameter \Y_WIDTH 1
104777     connect \A \main_sdram_tccdcon_count
104778     connect \B 1'1
104779     connect \Y $eq$ls180.v:7924$2512_Y
104780   end
104781   attribute \src "ls180.v:7939.9-7939.41"
104782   cell $eq $eq$ls180.v:7939$2515
104783     parameter \A_SIGNED 0
104784     parameter \A_WIDTH 3
104785     parameter \B_SIGNED 0
104786     parameter \B_WIDTH 1
104787     parameter \Y_WIDTH 1
104788     connect \A \main_sdram_twtrcon_count
104789     connect \B 1'1
104790     connect \Y $eq$ls180.v:7939$2515_Y
104791   end
104792   attribute \src "ls180.v:7945.49-7945.82"
104793   cell $eq $eq$ls180.v:7945$2516
104794     parameter \A_SIGNED 0
104795     parameter \A_WIDTH 1
104796     parameter \B_SIGNED 0
104797     parameter \B_WIDTH 1
104798     parameter \Y_WIDTH 1
104799     connect \A \builder_roundrobin0_grant
104800     connect \B 1'0
104801     connect \Y $eq$ls180.v:7945$2516_Y
104802   end
104803   attribute \src "ls180.v:7945.131-7945.164"
104804   cell $eq $eq$ls180.v:7945$2519
104805     parameter \A_SIGNED 0
104806     parameter \A_WIDTH 1
104807     parameter \B_SIGNED 0
104808     parameter \B_WIDTH 1
104809     parameter \Y_WIDTH 1
104810     connect \A \builder_roundrobin1_grant
104811     connect \B 1'0
104812     connect \Y $eq$ls180.v:7945$2519_Y
104813   end
104814   attribute \src "ls180.v:7945.213-7945.246"
104815   cell $eq $eq$ls180.v:7945$2522
104816     parameter \A_SIGNED 0
104817     parameter \A_WIDTH 1
104818     parameter \B_SIGNED 0
104819     parameter \B_WIDTH 1
104820     parameter \Y_WIDTH 1
104821     connect \A \builder_roundrobin2_grant
104822     connect \B 1'0
104823     connect \Y $eq$ls180.v:7945$2522_Y
104824   end
104825   attribute \src "ls180.v:7945.295-7945.328"
104826   cell $eq $eq$ls180.v:7945$2525
104827     parameter \A_SIGNED 0
104828     parameter \A_WIDTH 1
104829     parameter \B_SIGNED 0
104830     parameter \B_WIDTH 1
104831     parameter \Y_WIDTH 1
104832     connect \A \builder_roundrobin3_grant
104833     connect \B 1'0
104834     connect \Y $eq$ls180.v:7945$2525_Y
104835   end
104836   attribute \src "ls180.v:7946.50-7946.83"
104837   cell $eq $eq$ls180.v:7946$2528
104838     parameter \A_SIGNED 0
104839     parameter \A_WIDTH 1
104840     parameter \B_SIGNED 0
104841     parameter \B_WIDTH 1
104842     parameter \Y_WIDTH 1
104843     connect \A \builder_roundrobin0_grant
104844     connect \B 1'0
104845     connect \Y $eq$ls180.v:7946$2528_Y
104846   end
104847   attribute \src "ls180.v:7946.132-7946.165"
104848   cell $eq $eq$ls180.v:7946$2531
104849     parameter \A_SIGNED 0
104850     parameter \A_WIDTH 1
104851     parameter \B_SIGNED 0
104852     parameter \B_WIDTH 1
104853     parameter \Y_WIDTH 1
104854     connect \A \builder_roundrobin1_grant
104855     connect \B 1'0
104856     connect \Y $eq$ls180.v:7946$2531_Y
104857   end
104858   attribute \src "ls180.v:7946.214-7946.247"
104859   cell $eq $eq$ls180.v:7946$2534
104860     parameter \A_SIGNED 0
104861     parameter \A_WIDTH 1
104862     parameter \B_SIGNED 0
104863     parameter \B_WIDTH 1
104864     parameter \Y_WIDTH 1
104865     connect \A \builder_roundrobin2_grant
104866     connect \B 1'0
104867     connect \Y $eq$ls180.v:7946$2534_Y
104868   end
104869   attribute \src "ls180.v:7946.296-7946.329"
104870   cell $eq $eq$ls180.v:7946$2537
104871     parameter \A_SIGNED 0
104872     parameter \A_WIDTH 1
104873     parameter \B_SIGNED 0
104874     parameter \B_WIDTH 1
104875     parameter \Y_WIDTH 1
104876     connect \A \builder_roundrobin3_grant
104877     connect \B 1'0
104878     connect \Y $eq$ls180.v:7946$2537_Y
104879   end
104880   attribute \src "ls180.v:7981.9-7981.42"
104881   cell $eq $eq$ls180.v:7981$2549
104882     parameter \A_SIGNED 0
104883     parameter \A_WIDTH 4
104884     parameter \B_SIGNED 0
104885     parameter \B_WIDTH 4
104886     parameter \Y_WIDTH 1
104887     connect \A \main_uart_phy_tx_bitcount
104888     connect \B 4'1000
104889     connect \Y $eq$ls180.v:7981$2549_Y
104890   end
104891   attribute \src "ls180.v:7984.10-7984.43"
104892   cell $eq $eq$ls180.v:7984$2550
104893     parameter \A_SIGNED 0
104894     parameter \A_WIDTH 4
104895     parameter \B_SIGNED 0
104896     parameter \B_WIDTH 4
104897     parameter \Y_WIDTH 1
104898     connect \A \main_uart_phy_tx_bitcount
104899     connect \B 4'1001
104900     connect \Y $eq$ls180.v:7984$2550_Y
104901   end
104902   attribute \src "ls180.v:8010.9-8010.42"
104903   cell $eq $eq$ls180.v:8010$2556
104904     parameter \A_SIGNED 0
104905     parameter \A_WIDTH 4
104906     parameter \B_SIGNED 0
104907     parameter \B_WIDTH 1
104908     parameter \Y_WIDTH 1
104909     connect \A \main_uart_phy_rx_bitcount
104910     connect \B 1'0
104911     connect \Y $eq$ls180.v:8010$2556_Y
104912   end
104913   attribute \src "ls180.v:8015.10-8015.43"
104914   cell $eq $eq$ls180.v:8015$2557
104915     parameter \A_SIGNED 0
104916     parameter \A_WIDTH 4
104917     parameter \B_SIGNED 0
104918     parameter \B_WIDTH 4
104919     parameter \Y_WIDTH 1
104920     connect \A \main_uart_phy_rx_bitcount
104921     connect \B 4'1001
104922     connect \Y $eq$ls180.v:8015$2557_Y
104923   end
104924   attribute \src "ls180.v:8222.9-8222.53"
104925   cell $eq $eq$ls180.v:8222$2606
104926     parameter \A_SIGNED 0
104927     parameter \A_WIDTH 3
104928     parameter \B_SIGNED 0
104929     parameter \B_WIDTH 3
104930     parameter \Y_WIDTH 1
104931     connect \A \main_sdphy_cmdr_cmdr_converter_demux
104932     connect \B 3'111
104933     connect \Y $eq$ls180.v:8222$2606_Y
104934   end
104935   attribute \src "ls180.v:8303.9-8303.54"
104936   cell $eq $eq$ls180.v:8303$2618
104937     parameter \A_SIGNED 0
104938     parameter \A_WIDTH 3
104939     parameter \B_SIGNED 0
104940     parameter \B_WIDTH 3
104941     parameter \Y_WIDTH 1
104942     connect \A \main_sdphy_dataw_crcr_converter_demux
104943     connect \B 3'111
104944     connect \Y $eq$ls180.v:8303$2618_Y
104945   end
104946   attribute \src "ls180.v:8382.9-8382.55"
104947   cell $eq $eq$ls180.v:8382$2630
104948     parameter \A_SIGNED 0
104949     parameter \A_WIDTH 1
104950     parameter \B_SIGNED 0
104951     parameter \B_WIDTH 1
104952     parameter \Y_WIDTH 1
104953     connect \A \main_sdphy_datar_datar_converter_demux
104954     connect \B 1'1
104955     connect \Y $eq$ls180.v:8382$2630_Y
104956   end
104957   attribute \src "ls180.v:8605.9-8605.49"
104958   cell $eq $eq$ls180.v:8605$2663
104959     parameter \A_SIGNED 0
104960     parameter \A_WIDTH 2
104961     parameter \B_SIGNED 0
104962     parameter \B_WIDTH 2
104963     parameter \Y_WIDTH 1
104964     connect \A \main_sdblock2mem_converter_demux
104965     connect \B 2'11
104966     connect \Y $eq$ls180.v:8605$2663_Y
104967   end
104968   attribute \src "ls180.v:8181.8-8181.54"
104969   cell $ge $ge$ls180.v:8181$2598
104970     parameter \A_SIGNED 0
104971     parameter \A_WIDTH 32
104972     parameter \B_SIGNED 0
104973     parameter \B_WIDTH 32
104974     parameter \Y_WIDTH 1
104975     connect \A \main_pwm0_counter
104976     connect \B $sub$ls180.v:8181$2597_Y
104977     connect \Y $ge$ls180.v:8181$2598_Y
104978   end
104979   attribute \src "ls180.v:8195.8-8195.54"
104980   cell $ge $ge$ls180.v:8195$2602
104981     parameter \A_SIGNED 0
104982     parameter \A_WIDTH 32
104983     parameter \B_SIGNED 0
104984     parameter \B_WIDTH 32
104985     parameter \Y_WIDTH 1
104986     connect \A \main_pwm1_counter
104987     connect \B $sub$ls180.v:8195$2601_Y
104988     connect \Y $ge$ls180.v:8195$2602_Y
104989   end
104990   attribute \src "ls180.v:5155.47-5155.83"
104991   cell $gt $gt$ls180.v:5155$914
104992     parameter \A_SIGNED 0
104993     parameter \A_WIDTH 4
104994     parameter \B_SIGNED 0
104995     parameter \B_WIDTH 3
104996     parameter \Y_WIDTH 1
104997     connect \A \main_sdcore_crc16_checker_cnt
104998     connect \B 3'111
104999     connect \Y $gt$ls180.v:5155$914_Y
105000   end
105001   attribute \src "ls180.v:5161.7-5161.43"
105002   cell $lt $lt$ls180.v:5161$917
105003     parameter \A_SIGNED 0
105004     parameter \A_WIDTH 4
105005     parameter \B_SIGNED 0
105006     parameter \B_WIDTH 4
105007     parameter \Y_WIDTH 1
105008     connect \A \main_sdcore_crc16_checker_cnt
105009     connect \B 4'1000
105010     connect \Y $lt$ls180.v:5161$917_Y
105011   end
105012   attribute \src "ls180.v:8176.8-8176.43"
105013   cell $lt $lt$ls180.v:8176$2596
105014     parameter \A_SIGNED 0
105015     parameter \A_WIDTH 32
105016     parameter \B_SIGNED 0
105017     parameter \B_WIDTH 32
105018     parameter \Y_WIDTH 1
105019     connect \A \main_pwm0_counter
105020     connect \B \main_pwm0_width
105021     connect \Y $lt$ls180.v:8176$2596_Y
105022   end
105023   attribute \src "ls180.v:8190.8-8190.43"
105024   cell $lt $lt$ls180.v:8190$2600
105025     parameter \A_SIGNED 0
105026     parameter \A_WIDTH 32
105027     parameter \B_SIGNED 0
105028     parameter \B_WIDTH 32
105029     parameter \Y_WIDTH 1
105030     connect \A \main_pwm1_counter
105031     connect \B \main_pwm1_width
105032     connect \Y $lt$ls180.v:8190$2600_Y
105033   end
105034   attribute \src "ls180.v:10071.33-10071.36"
105035   cell $memrd $memrd$\mem$ls180.v:10071$2705
105036     parameter \ABITS 7
105037     parameter \CLK_ENABLE 0
105038     parameter \CLK_POLARITY 0
105039     parameter \MEMID "\\mem"
105040     parameter \TRANSPARENT 0
105041     parameter \WIDTH 32
105042     connect \ADDR \memadr
105043     connect \CLK 1'x
105044     connect \DATA $memrd$\mem$ls180.v:10071$2705_DATA
105045     connect \EN 1'x
105046   end
105047   attribute \src "ls180.v:10082.12-10082.19"
105048   cell $memrd $memrd$\storage$ls180.v:10082$2710
105049     parameter \ABITS 3
105050     parameter \CLK_ENABLE 0
105051     parameter \CLK_POLARITY 0
105052     parameter \MEMID "\\storage"
105053     parameter \TRANSPARENT 0
105054     parameter \WIDTH 25
105055     connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
105056     connect \CLK 1'x
105057     connect \DATA $memrd$\storage$ls180.v:10082$2710_DATA
105058     connect \EN 1'x
105059   end
105060   attribute \src "ls180.v:10089.68-10089.75"
105061   cell $memrd $memrd$\storage$ls180.v:10089$2712
105062     parameter \ABITS 3
105063     parameter \CLK_ENABLE 0
105064     parameter \CLK_POLARITY 0
105065     parameter \MEMID "\\storage"
105066     parameter \TRANSPARENT 0
105067     parameter \WIDTH 25
105068     connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
105069     connect \CLK 1'x
105070     connect \DATA $memrd$\storage$ls180.v:10089$2712_DATA
105071     connect \EN 1'x
105072   end
105073   attribute \src "ls180.v:10096.14-10096.23"
105074   cell $memrd $memrd$\storage_1$ls180.v:10096$2717
105075     parameter \ABITS 3
105076     parameter \CLK_ENABLE 0
105077     parameter \CLK_POLARITY 0
105078     parameter \MEMID "\\storage_1"
105079     parameter \TRANSPARENT 0
105080     parameter \WIDTH 25
105081     connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
105082     connect \CLK 1'x
105083     connect \DATA $memrd$\storage_1$ls180.v:10096$2717_DATA
105084     connect \EN 1'x
105085   end
105086   attribute \src "ls180.v:10103.68-10103.77"
105087   cell $memrd $memrd$\storage_1$ls180.v:10103$2719
105088     parameter \ABITS 3
105089     parameter \CLK_ENABLE 0
105090     parameter \CLK_POLARITY 0
105091     parameter \MEMID "\\storage_1"
105092     parameter \TRANSPARENT 0
105093     parameter \WIDTH 25
105094     connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
105095     connect \CLK 1'x
105096     connect \DATA $memrd$\storage_1$ls180.v:10103$2719_DATA
105097     connect \EN 1'x
105098   end
105099   attribute \src "ls180.v:10110.14-10110.23"
105100   cell $memrd $memrd$\storage_2$ls180.v:10110$2724
105101     parameter \ABITS 3
105102     parameter \CLK_ENABLE 0
105103     parameter \CLK_POLARITY 0
105104     parameter \MEMID "\\storage_2"
105105     parameter \TRANSPARENT 0
105106     parameter \WIDTH 25
105107     connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
105108     connect \CLK 1'x
105109     connect \DATA $memrd$\storage_2$ls180.v:10110$2724_DATA
105110     connect \EN 1'x
105111   end
105112   attribute \src "ls180.v:10117.68-10117.77"
105113   cell $memrd $memrd$\storage_2$ls180.v:10117$2726
105114     parameter \ABITS 3
105115     parameter \CLK_ENABLE 0
105116     parameter \CLK_POLARITY 0
105117     parameter \MEMID "\\storage_2"
105118     parameter \TRANSPARENT 0
105119     parameter \WIDTH 25
105120     connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
105121     connect \CLK 1'x
105122     connect \DATA $memrd$\storage_2$ls180.v:10117$2726_DATA
105123     connect \EN 1'x
105124   end
105125   attribute \src "ls180.v:10124.14-10124.23"
105126   cell $memrd $memrd$\storage_3$ls180.v:10124$2731
105127     parameter \ABITS 3
105128     parameter \CLK_ENABLE 0
105129     parameter \CLK_POLARITY 0
105130     parameter \MEMID "\\storage_3"
105131     parameter \TRANSPARENT 0
105132     parameter \WIDTH 25
105133     connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
105134     connect \CLK 1'x
105135     connect \DATA $memrd$\storage_3$ls180.v:10124$2731_DATA
105136     connect \EN 1'x
105137   end
105138   attribute \src "ls180.v:10131.68-10131.77"
105139   cell $memrd $memrd$\storage_3$ls180.v:10131$2733
105140     parameter \ABITS 3
105141     parameter \CLK_ENABLE 0
105142     parameter \CLK_POLARITY 0
105143     parameter \MEMID "\\storage_3"
105144     parameter \TRANSPARENT 0
105145     parameter \WIDTH 25
105146     connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
105147     connect \CLK 1'x
105148     connect \DATA $memrd$\storage_3$ls180.v:10131$2733_DATA
105149     connect \EN 1'x
105150   end
105151   attribute \src "ls180.v:10139.14-10139.23"
105152   cell $memrd $memrd$\storage_4$ls180.v:10139$2738
105153     parameter \ABITS 4
105154     parameter \CLK_ENABLE 0
105155     parameter \CLK_POLARITY 0
105156     parameter \MEMID "\\storage_4"
105157     parameter \TRANSPARENT 0
105158     parameter \WIDTH 10
105159     connect \ADDR \main_uart_tx_fifo_wrport_adr
105160     connect \CLK 1'x
105161     connect \DATA $memrd$\storage_4$ls180.v:10139$2738_DATA
105162     connect \EN 1'x
105163   end
105164   attribute \src "ls180.v:10144.15-10144.24"
105165   cell $memrd $memrd$\storage_4$ls180.v:10144$2740
105166     parameter \ABITS 4
105167     parameter \CLK_ENABLE 0
105168     parameter \CLK_POLARITY 0
105169     parameter \MEMID "\\storage_4"
105170     parameter \TRANSPARENT 0
105171     parameter \WIDTH 10
105172     connect \ADDR \main_uart_tx_fifo_rdport_adr
105173     connect \CLK 1'x
105174     connect \DATA $memrd$\storage_4$ls180.v:10144$2740_DATA
105175     connect \EN 1'x
105176   end
105177   attribute \src "ls180.v:10156.14-10156.23"
105178   cell $memrd $memrd$\storage_5$ls180.v:10156$2745
105179     parameter \ABITS 4
105180     parameter \CLK_ENABLE 0
105181     parameter \CLK_POLARITY 0
105182     parameter \MEMID "\\storage_5"
105183     parameter \TRANSPARENT 0
105184     parameter \WIDTH 10
105185     connect \ADDR \main_uart_rx_fifo_wrport_adr
105186     connect \CLK 1'x
105187     connect \DATA $memrd$\storage_5$ls180.v:10156$2745_DATA
105188     connect \EN 1'x
105189   end
105190   attribute \src "ls180.v:10161.15-10161.24"
105191   cell $memrd $memrd$\storage_5$ls180.v:10161$2747
105192     parameter \ABITS 4
105193     parameter \CLK_ENABLE 0
105194     parameter \CLK_POLARITY 0
105195     parameter \MEMID "\\storage_5"
105196     parameter \TRANSPARENT 0
105197     parameter \WIDTH 10
105198     connect \ADDR \main_uart_rx_fifo_rdport_adr
105199     connect \CLK 1'x
105200     connect \DATA $memrd$\storage_5$ls180.v:10161$2747_DATA
105201     connect \EN 1'x
105202   end
105203   attribute \src "ls180.v:10172.14-10172.23"
105204   cell $memrd $memrd$\storage_6$ls180.v:10172$2752
105205     parameter \ABITS 5
105206     parameter \CLK_ENABLE 0
105207     parameter \CLK_POLARITY 0
105208     parameter \MEMID "\\storage_6"
105209     parameter \TRANSPARENT 0
105210     parameter \WIDTH 10
105211     connect \ADDR \main_sdblock2mem_fifo_wrport_adr
105212     connect \CLK 1'x
105213     connect \DATA $memrd$\storage_6$ls180.v:10172$2752_DATA
105214     connect \EN 1'x
105215   end
105216   attribute \src "ls180.v:10179.45-10179.54"
105217   cell $memrd $memrd$\storage_6$ls180.v:10179$2754
105218     parameter \ABITS 5
105219     parameter \CLK_ENABLE 0
105220     parameter \CLK_POLARITY 0
105221     parameter \MEMID "\\storage_6"
105222     parameter \TRANSPARENT 0
105223     parameter \WIDTH 10
105224     connect \ADDR \main_sdblock2mem_fifo_rdport_adr
105225     connect \CLK 1'x
105226     connect \DATA $memrd$\storage_6$ls180.v:10179$2754_DATA
105227     connect \EN 1'x
105228   end
105229   attribute \src "ls180.v:10186.14-10186.23"
105230   cell $memrd $memrd$\storage_7$ls180.v:10186$2759
105231     parameter \ABITS 5
105232     parameter \CLK_ENABLE 0
105233     parameter \CLK_POLARITY 0
105234     parameter \MEMID "\\storage_7"
105235     parameter \TRANSPARENT 0
105236     parameter \WIDTH 10
105237     connect \ADDR \main_sdmem2block_fifo_wrport_adr
105238     connect \CLK 1'x
105239     connect \DATA $memrd$\storage_7$ls180.v:10186$2759_DATA
105240     connect \EN 1'x
105241   end
105242   attribute \src "ls180.v:10193.45-10193.54"
105243   cell $memrd $memrd$\storage_7$ls180.v:10193$2761
105244     parameter \ABITS 5
105245     parameter \CLK_ENABLE 0
105246     parameter \CLK_POLARITY 0
105247     parameter \MEMID "\\storage_7"
105248     parameter \TRANSPARENT 0
105249     parameter \WIDTH 10
105250     connect \ADDR \main_sdmem2block_fifo_rdport_adr
105251     connect \CLK 1'x
105252     connect \DATA $memrd$\storage_7$ls180.v:10193$2761_DATA
105253     connect \EN 1'x
105254   end
105255   attribute \src "ls180.v:0.0-0.0"
105256   cell $memwr $memwr$\mem$ls180.v:0$2763
105257     parameter \ABITS 7
105258     parameter \CLK_ENABLE 0
105259     parameter \CLK_POLARITY 0
105260     parameter \MEMID "\\mem"
105261     parameter \PRIORITY 2763
105262     parameter \WIDTH 32
105263     connect \ADDR $memwr$\mem$ls180.v:10061$1_ADDR
105264     connect \CLK 1'x
105265     connect \DATA $memwr$\mem$ls180.v:10061$1_DATA
105266     connect \EN $memwr$\mem$ls180.v:10061$1_EN
105267   end
105268   attribute \src "ls180.v:0.0-0.0"
105269   cell $memwr $memwr$\mem$ls180.v:0$2764
105270     parameter \ABITS 7
105271     parameter \CLK_ENABLE 0
105272     parameter \CLK_POLARITY 0
105273     parameter \MEMID "\\mem"
105274     parameter \PRIORITY 2764
105275     parameter \WIDTH 32
105276     connect \ADDR $memwr$\mem$ls180.v:10063$2_ADDR
105277     connect \CLK 1'x
105278     connect \DATA $memwr$\mem$ls180.v:10063$2_DATA
105279     connect \EN $memwr$\mem$ls180.v:10063$2_EN
105280   end
105281   attribute \src "ls180.v:0.0-0.0"
105282   cell $memwr $memwr$\mem$ls180.v:0$2765
105283     parameter \ABITS 7
105284     parameter \CLK_ENABLE 0
105285     parameter \CLK_POLARITY 0
105286     parameter \MEMID "\\mem"
105287     parameter \PRIORITY 2765
105288     parameter \WIDTH 32
105289     connect \ADDR $memwr$\mem$ls180.v:10065$3_ADDR
105290     connect \CLK 1'x
105291     connect \DATA $memwr$\mem$ls180.v:10065$3_DATA
105292     connect \EN $memwr$\mem$ls180.v:10065$3_EN
105293   end
105294   attribute \src "ls180.v:0.0-0.0"
105295   cell $memwr $memwr$\mem$ls180.v:0$2766
105296     parameter \ABITS 7
105297     parameter \CLK_ENABLE 0
105298     parameter \CLK_POLARITY 0
105299     parameter \MEMID "\\mem"
105300     parameter \PRIORITY 2766
105301     parameter \WIDTH 32
105302     connect \ADDR $memwr$\mem$ls180.v:10067$4_ADDR
105303     connect \CLK 1'x
105304     connect \DATA $memwr$\mem$ls180.v:10067$4_DATA
105305     connect \EN $memwr$\mem$ls180.v:10067$4_EN
105306   end
105307   attribute \src "ls180.v:0.0-0.0"
105308   cell $memwr $memwr$\storage$ls180.v:0$2767
105309     parameter \ABITS 3
105310     parameter \CLK_ENABLE 0
105311     parameter \CLK_POLARITY 0
105312     parameter \MEMID "\\storage"
105313     parameter \PRIORITY 2767
105314     parameter \WIDTH 25
105315     connect \ADDR $memwr$\storage$ls180.v:10081$5_ADDR
105316     connect \CLK 1'x
105317     connect \DATA $memwr$\storage$ls180.v:10081$5_DATA
105318     connect \EN $memwr$\storage$ls180.v:10081$5_EN
105319   end
105320   attribute \src "ls180.v:0.0-0.0"
105321   cell $memwr $memwr$\storage_1$ls180.v:0$2768
105322     parameter \ABITS 3
105323     parameter \CLK_ENABLE 0
105324     parameter \CLK_POLARITY 0
105325     parameter \MEMID "\\storage_1"
105326     parameter \PRIORITY 2768
105327     parameter \WIDTH 25
105328     connect \ADDR $memwr$\storage_1$ls180.v:10095$6_ADDR
105329     connect \CLK 1'x
105330     connect \DATA $memwr$\storage_1$ls180.v:10095$6_DATA
105331     connect \EN $memwr$\storage_1$ls180.v:10095$6_EN
105332   end
105333   attribute \src "ls180.v:0.0-0.0"
105334   cell $memwr $memwr$\storage_2$ls180.v:0$2769
105335     parameter \ABITS 3
105336     parameter \CLK_ENABLE 0
105337     parameter \CLK_POLARITY 0
105338     parameter \MEMID "\\storage_2"
105339     parameter \PRIORITY 2769
105340     parameter \WIDTH 25
105341     connect \ADDR $memwr$\storage_2$ls180.v:10109$7_ADDR
105342     connect \CLK 1'x
105343     connect \DATA $memwr$\storage_2$ls180.v:10109$7_DATA
105344     connect \EN $memwr$\storage_2$ls180.v:10109$7_EN
105345   end
105346   attribute \src "ls180.v:0.0-0.0"
105347   cell $memwr $memwr$\storage_3$ls180.v:0$2770
105348     parameter \ABITS 3
105349     parameter \CLK_ENABLE 0
105350     parameter \CLK_POLARITY 0
105351     parameter \MEMID "\\storage_3"
105352     parameter \PRIORITY 2770
105353     parameter \WIDTH 25
105354     connect \ADDR $memwr$\storage_3$ls180.v:10123$8_ADDR
105355     connect \CLK 1'x
105356     connect \DATA $memwr$\storage_3$ls180.v:10123$8_DATA
105357     connect \EN $memwr$\storage_3$ls180.v:10123$8_EN
105358   end
105359   attribute \src "ls180.v:0.0-0.0"
105360   cell $memwr $memwr$\storage_4$ls180.v:0$2771
105361     parameter \ABITS 4
105362     parameter \CLK_ENABLE 0
105363     parameter \CLK_POLARITY 0
105364     parameter \MEMID "\\storage_4"
105365     parameter \PRIORITY 2771
105366     parameter \WIDTH 10
105367     connect \ADDR $memwr$\storage_4$ls180.v:10138$9_ADDR
105368     connect \CLK 1'x
105369     connect \DATA $memwr$\storage_4$ls180.v:10138$9_DATA
105370     connect \EN $memwr$\storage_4$ls180.v:10138$9_EN
105371   end
105372   attribute \src "ls180.v:0.0-0.0"
105373   cell $memwr $memwr$\storage_5$ls180.v:0$2772
105374     parameter \ABITS 4
105375     parameter \CLK_ENABLE 0
105376     parameter \CLK_POLARITY 0
105377     parameter \MEMID "\\storage_5"
105378     parameter \PRIORITY 2772
105379     parameter \WIDTH 10
105380     connect \ADDR $memwr$\storage_5$ls180.v:10155$10_ADDR
105381     connect \CLK 1'x
105382     connect \DATA $memwr$\storage_5$ls180.v:10155$10_DATA
105383     connect \EN $memwr$\storage_5$ls180.v:10155$10_EN
105384   end
105385   attribute \src "ls180.v:0.0-0.0"
105386   cell $memwr $memwr$\storage_6$ls180.v:0$2773
105387     parameter \ABITS 5
105388     parameter \CLK_ENABLE 0
105389     parameter \CLK_POLARITY 0
105390     parameter \MEMID "\\storage_6"
105391     parameter \PRIORITY 2773
105392     parameter \WIDTH 10
105393     connect \ADDR $memwr$\storage_6$ls180.v:10171$11_ADDR
105394     connect \CLK 1'x
105395     connect \DATA $memwr$\storage_6$ls180.v:10171$11_DATA
105396     connect \EN $memwr$\storage_6$ls180.v:10171$11_EN
105397   end
105398   attribute \src "ls180.v:0.0-0.0"
105399   cell $memwr $memwr$\storage_7$ls180.v:0$2774
105400     parameter \ABITS 5
105401     parameter \CLK_ENABLE 0
105402     parameter \CLK_POLARITY 0
105403     parameter \MEMID "\\storage_7"
105404     parameter \PRIORITY 2774
105405     parameter \WIDTH 10
105406     connect \ADDR $memwr$\storage_7$ls180.v:10185$12_ADDR
105407     connect \CLK 1'x
105408     connect \DATA $memwr$\storage_7$ls180.v:10185$12_DATA
105409     connect \EN $memwr$\storage_7$ls180.v:10185$12_EN
105410   end
105411   attribute \src "ls180.v:2969.41-2969.71"
105412   cell $ne $ne$ls180.v:2969$60
105413     parameter \A_SIGNED 0
105414     parameter \A_WIDTH 32
105415     parameter \B_SIGNED 0
105416     parameter \B_WIDTH 1
105417     parameter \Y_WIDTH 1
105418     connect \A \main_libresocsim_value
105419     connect \B 1'0
105420     connect \Y $ne$ls180.v:2969$60_Y
105421   end
105422   attribute \src "ls180.v:3130.70-3130.104"
105423   cell $ne $ne$ls180.v:3130$74
105424     parameter \A_SIGNED 0
105425     parameter \A_WIDTH 1
105426     parameter \B_SIGNED 0
105427     parameter \B_WIDTH 1
105428     parameter \Y_WIDTH 1
105429     connect \A \main_sdram_sequencer_count
105430     connect \B 1'0
105431     connect \Y $ne$ls180.v:3130$74_Y
105432   end
105433   attribute \src "ls180.v:3191.8-3191.142"
105434   cell $ne $ne$ls180.v:3191$93
105435     parameter \A_SIGNED 0
105436     parameter \A_WIDTH 13
105437     parameter \B_SIGNED 0
105438     parameter \B_WIDTH 13
105439     parameter \Y_WIDTH 1
105440     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9]
105441     connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
105442     connect \Y $ne$ls180.v:3191$93_Y
105443   end
105444   attribute \src "ls180.v:3223.75-3223.133"
105445   cell $ne $ne$ls180.v:3223$100
105446     parameter \A_SIGNED 0
105447     parameter \A_WIDTH 4
105448     parameter \B_SIGNED 0
105449     parameter \B_WIDTH 4
105450     parameter \Y_WIDTH 1
105451     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
105452     connect \B 4'1000
105453     connect \Y $ne$ls180.v:3223$100_Y
105454   end
105455   attribute \src "ls180.v:3224.75-3224.133"
105456   cell $ne $ne$ls180.v:3224$101
105457     parameter \A_SIGNED 0
105458     parameter \A_WIDTH 4
105459     parameter \B_SIGNED 0
105460     parameter \B_WIDTH 1
105461     parameter \Y_WIDTH 1
105462     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
105463     connect \B 1'0
105464     connect \Y $ne$ls180.v:3224$101_Y
105465   end
105466   attribute \src "ls180.v:3348.8-3348.142"
105467   cell $ne $ne$ls180.v:3348$123
105468     parameter \A_SIGNED 0
105469     parameter \A_WIDTH 13
105470     parameter \B_SIGNED 0
105471     parameter \B_WIDTH 13
105472     parameter \Y_WIDTH 1
105473     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9]
105474     connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
105475     connect \Y $ne$ls180.v:3348$123_Y
105476   end
105477   attribute \src "ls180.v:3380.75-3380.133"
105478   cell $ne $ne$ls180.v:3380$130
105479     parameter \A_SIGNED 0
105480     parameter \A_WIDTH 4
105481     parameter \B_SIGNED 0
105482     parameter \B_WIDTH 4
105483     parameter \Y_WIDTH 1
105484     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
105485     connect \B 4'1000
105486     connect \Y $ne$ls180.v:3380$130_Y
105487   end
105488   attribute \src "ls180.v:3381.75-3381.133"
105489   cell $ne $ne$ls180.v:3381$131
105490     parameter \A_SIGNED 0
105491     parameter \A_WIDTH 4
105492     parameter \B_SIGNED 0
105493     parameter \B_WIDTH 1
105494     parameter \Y_WIDTH 1
105495     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
105496     connect \B 1'0
105497     connect \Y $ne$ls180.v:3381$131_Y
105498   end
105499   attribute \src "ls180.v:3505.8-3505.142"
105500   cell $ne $ne$ls180.v:3505$153
105501     parameter \A_SIGNED 0
105502     parameter \A_WIDTH 13
105503     parameter \B_SIGNED 0
105504     parameter \B_WIDTH 13
105505     parameter \Y_WIDTH 1
105506     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9]
105507     connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
105508     connect \Y $ne$ls180.v:3505$153_Y
105509   end
105510   attribute \src "ls180.v:3537.75-3537.133"
105511   cell $ne $ne$ls180.v:3537$160
105512     parameter \A_SIGNED 0
105513     parameter \A_WIDTH 4
105514     parameter \B_SIGNED 0
105515     parameter \B_WIDTH 4
105516     parameter \Y_WIDTH 1
105517     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
105518     connect \B 4'1000
105519     connect \Y $ne$ls180.v:3537$160_Y
105520   end
105521   attribute \src "ls180.v:3538.75-3538.133"
105522   cell $ne $ne$ls180.v:3538$161
105523     parameter \A_SIGNED 0
105524     parameter \A_WIDTH 4
105525     parameter \B_SIGNED 0
105526     parameter \B_WIDTH 1
105527     parameter \Y_WIDTH 1
105528     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
105529     connect \B 1'0
105530     connect \Y $ne$ls180.v:3538$161_Y
105531   end
105532   attribute \src "ls180.v:3662.8-3662.142"
105533   cell $ne $ne$ls180.v:3662$183
105534     parameter \A_SIGNED 0
105535     parameter \A_WIDTH 13
105536     parameter \B_SIGNED 0
105537     parameter \B_WIDTH 13
105538     parameter \Y_WIDTH 1
105539     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9]
105540     connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
105541     connect \Y $ne$ls180.v:3662$183_Y
105542   end
105543   attribute \src "ls180.v:3694.75-3694.133"
105544   cell $ne $ne$ls180.v:3694$190
105545     parameter \A_SIGNED 0
105546     parameter \A_WIDTH 4
105547     parameter \B_SIGNED 0
105548     parameter \B_WIDTH 4
105549     parameter \Y_WIDTH 1
105550     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
105551     connect \B 4'1000
105552     connect \Y $ne$ls180.v:3694$190_Y
105553   end
105554   attribute \src "ls180.v:3695.75-3695.133"
105555   cell $ne $ne$ls180.v:3695$191
105556     parameter \A_SIGNED 0
105557     parameter \A_WIDTH 4
105558     parameter \B_SIGNED 0
105559     parameter \B_WIDTH 1
105560     parameter \Y_WIDTH 1
105561     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
105562     connect \B 1'0
105563     connect \Y $ne$ls180.v:3695$191_Y
105564   end
105565   attribute \src "ls180.v:4187.47-4187.80"
105566   cell $ne $ne$ls180.v:4187$589
105567     parameter \A_SIGNED 0
105568     parameter \A_WIDTH 5
105569     parameter \B_SIGNED 0
105570     parameter \B_WIDTH 5
105571     parameter \Y_WIDTH 1
105572     connect \A \main_uart_tx_fifo_level0
105573     connect \B 5'10000
105574     connect \Y $ne$ls180.v:4187$589_Y
105575   end
105576   attribute \src "ls180.v:4188.47-4188.79"
105577   cell $ne $ne$ls180.v:4188$590
105578     parameter \A_SIGNED 0
105579     parameter \A_WIDTH 5
105580     parameter \B_SIGNED 0
105581     parameter \B_WIDTH 1
105582     parameter \Y_WIDTH 1
105583     connect \A \main_uart_tx_fifo_level0
105584     connect \B 1'0
105585     connect \Y $ne$ls180.v:4188$590_Y
105586   end
105587   attribute \src "ls180.v:4217.47-4217.80"
105588   cell $ne $ne$ls180.v:4217$600
105589     parameter \A_SIGNED 0
105590     parameter \A_WIDTH 5
105591     parameter \B_SIGNED 0
105592     parameter \B_WIDTH 5
105593     parameter \Y_WIDTH 1
105594     connect \A \main_uart_rx_fifo_level0
105595     connect \B 5'10000
105596     connect \Y $ne$ls180.v:4217$600_Y
105597   end
105598   attribute \src "ls180.v:4218.47-4218.79"
105599   cell $ne $ne$ls180.v:4218$601
105600     parameter \A_SIGNED 0
105601     parameter \A_WIDTH 5
105602     parameter \B_SIGNED 0
105603     parameter \B_WIDTH 1
105604     parameter \Y_WIDTH 1
105605     connect \A \main_uart_rx_fifo_level0
105606     connect \B 1'0
105607     connect \Y $ne$ls180.v:4218$601_Y
105608   end
105609   attribute \src "ls180.v:4687.32-4687.89"
105610   cell $ne $ne$ls180.v:4687$681
105611     parameter \A_SIGNED 0
105612     parameter \A_WIDTH 8
105613     parameter \B_SIGNED 0
105614     parameter \B_WIDTH 3
105615     parameter \Y_WIDTH 1
105616     connect \A \main_sdphy_dataw_crcr_source_source_payload_data0
105617     connect \B 3'101
105618     connect \Y $ne$ls180.v:4687$681_Y
105619   end
105620   attribute \src "ls180.v:5334.10-5334.56"
105621   cell $ne $ne$ls180.v:5334$978
105622     parameter \A_SIGNED 0
105623     parameter \A_WIDTH 3
105624     parameter \B_SIGNED 0
105625     parameter \B_WIDTH 2
105626     parameter \Y_WIDTH 1
105627     connect \A \main_sdphy_datar_source_payload_status
105628     connect \B 2'10
105629     connect \Y $ne$ls180.v:5334$978_Y
105630   end
105631   attribute \src "ls180.v:5439.51-5439.87"
105632   cell $ne $ne$ls180.v:5439$992
105633     parameter \A_SIGNED 0
105634     parameter \A_WIDTH 6
105635     parameter \B_SIGNED 0
105636     parameter \B_WIDTH 6
105637     parameter \Y_WIDTH 1
105638     connect \A \main_sdblock2mem_fifo_level
105639     connect \B 6'100000
105640     connect \Y $ne$ls180.v:5439$992_Y
105641   end
105642   attribute \src "ls180.v:5440.51-5440.86"
105643   cell $ne $ne$ls180.v:5440$993
105644     parameter \A_SIGNED 0
105645     parameter \A_WIDTH 6
105646     parameter \B_SIGNED 0
105647     parameter \B_WIDTH 1
105648     parameter \Y_WIDTH 1
105649     connect \A \main_sdblock2mem_fifo_level
105650     connect \B 1'0
105651     connect \Y $ne$ls180.v:5440$993_Y
105652   end
105653   attribute \src "ls180.v:5647.51-5647.87"
105654   cell $ne $ne$ls180.v:5647$1023
105655     parameter \A_SIGNED 0
105656     parameter \A_WIDTH 6
105657     parameter \B_SIGNED 0
105658     parameter \B_WIDTH 6
105659     parameter \Y_WIDTH 1
105660     connect \A \main_sdmem2block_fifo_level
105661     connect \B 6'100000
105662     connect \Y $ne$ls180.v:5647$1023_Y
105663   end
105664   attribute \src "ls180.v:5648.51-5648.86"
105665   cell $ne $ne$ls180.v:5648$1024
105666     parameter \A_SIGNED 0
105667     parameter \A_WIDTH 6
105668     parameter \B_SIGNED 0
105669     parameter \B_WIDTH 1
105670     parameter \Y_WIDTH 1
105671     connect \A \main_sdmem2block_fifo_level
105672     connect \B 1'0
105673     connect \Y $ne$ls180.v:5648$1024_Y
105674   end
105675   attribute \src "ls180.v:5679.79-5679.119"
105676   cell $ne $ne$ls180.v:5679$1027
105677     parameter \A_SIGNED 0
105678     parameter \A_WIDTH 4
105679     parameter \B_SIGNED 0
105680     parameter \B_WIDTH 1
105681     parameter \Y_WIDTH 1
105682     connect \A \builder_libresocsim_wishbone_sel
105683     connect \B 1'0
105684     connect \Y $ne$ls180.v:5679$1027_Y
105685   end
105686   attribute \src "ls180.v:7501.7-7501.52"
105687   cell $ne $ne$ls180.v:7501$2414
105688     parameter \A_SIGNED 0
105689     parameter \A_WIDTH 32
105690     parameter \B_SIGNED 0
105691     parameter \B_WIDTH 32
105692     parameter \Y_WIDTH 1
105693     connect \A \main_libresocsim_bus_errors
105694     connect \B 32'11111111111111111111111111111111
105695     connect \Y $ne$ls180.v:7501$2414_Y
105696   end
105697   attribute \src "ls180.v:7551.9-7551.43"
105698   cell $ne $ne$ls180.v:7551$2428
105699     parameter \A_SIGNED 0
105700     parameter \A_WIDTH 1
105701     parameter \B_SIGNED 0
105702     parameter \B_WIDTH 1
105703     parameter \Y_WIDTH 1
105704     connect \A \main_sdram_sequencer_count
105705     connect \B 1'0
105706     connect \Y $ne$ls180.v:7551$2428_Y
105707   end
105708   attribute \src "ls180.v:7587.8-7587.44"
105709   cell $ne $ne$ls180.v:7587$2435
105710     parameter \A_SIGNED 0
105711     parameter \A_WIDTH 4
105712     parameter \B_SIGNED 0
105713     parameter \B_WIDTH 1
105714     parameter \Y_WIDTH 1
105715     connect \A \main_sdram_sequencer_counter
105716     connect \B 1'0
105717     connect \Y $ne$ls180.v:7587$2435_Y
105718   end
105719   attribute \src "ls180.v:8525.9-8525.47"
105720   cell $ne $ne$ls180.v:8525$2650
105721     parameter \A_SIGNED 0
105722     parameter \A_WIDTH 4
105723     parameter \B_SIGNED 0
105724     parameter \B_WIDTH 4
105725     parameter \Y_WIDTH 1
105726     connect \A \main_sdcore_crc16_checker_cnt
105727     connect \B 4'1010
105728     connect \Y $ne$ls180.v:8525$2650_Y
105729   end
105730   attribute \src "ls180.v:2777.45-2777.80"
105731   cell $not $not$ls180.v:2777$14
105732     parameter \A_SIGNED 0
105733     parameter \A_WIDTH 1
105734     parameter \Y_WIDTH 1
105735     connect \A \main_libresocsim_libresoc_ibus_cyc
105736     connect \Y $not$ls180.v:2777$14_Y
105737   end
105738   attribute \src "ls180.v:2816.61-2816.94"
105739   cell $not $not$ls180.v:2816$19
105740     parameter \A_SIGNED 0
105741     parameter \A_WIDTH 1
105742     parameter \Y_WIDTH 1
105743     connect \A \main_libresocsim_converter0_skip
105744     connect \Y $not$ls180.v:2816$19_Y
105745   end
105746   attribute \src "ls180.v:2817.61-2817.94"
105747   cell $not $not$ls180.v:2817$20
105748     parameter \A_SIGNED 0
105749     parameter \A_WIDTH 1
105750     parameter \Y_WIDTH 1
105751     connect \A \main_libresocsim_converter0_skip
105752     connect \Y $not$ls180.v:2817$20_Y
105753   end
105754   attribute \src "ls180.v:2837.45-2837.80"
105755   cell $not $not$ls180.v:2837$25
105756     parameter \A_SIGNED 0
105757     parameter \A_WIDTH 1
105758     parameter \Y_WIDTH 1
105759     connect \A \main_libresocsim_libresoc_dbus_cyc
105760     connect \Y $not$ls180.v:2837$25_Y
105761   end
105762   attribute \src "ls180.v:2876.61-2876.94"
105763   cell $not $not$ls180.v:2876$30
105764     parameter \A_SIGNED 0
105765     parameter \A_WIDTH 1
105766     parameter \Y_WIDTH 1
105767     connect \A \main_libresocsim_converter1_skip
105768     connect \Y $not$ls180.v:2876$30_Y
105769   end
105770   attribute \src "ls180.v:2877.61-2877.94"
105771   cell $not $not$ls180.v:2877$31
105772     parameter \A_SIGNED 0
105773     parameter \A_WIDTH 1
105774     parameter \Y_WIDTH 1
105775     connect \A \main_libresocsim_converter1_skip
105776     connect \Y $not$ls180.v:2877$31_Y
105777   end
105778   attribute \src "ls180.v:2897.45-2897.83"
105779   cell $not $not$ls180.v:2897$36
105780     parameter \A_SIGNED 0
105781     parameter \A_WIDTH 1
105782     parameter \Y_WIDTH 1
105783     connect \A \main_libresocsim_libresoc_jtag_wb_cyc
105784     connect \Y $not$ls180.v:2897$36_Y
105785   end
105786   attribute \src "ls180.v:2936.61-2936.94"
105787   cell $not $not$ls180.v:2936$41
105788     parameter \A_SIGNED 0
105789     parameter \A_WIDTH 1
105790     parameter \Y_WIDTH 1
105791     connect \A \main_libresocsim_converter2_skip
105792     connect \Y $not$ls180.v:2936$41_Y
105793   end
105794   attribute \src "ls180.v:2937.61-2937.94"
105795   cell $not $not$ls180.v:2937$42
105796     parameter \A_SIGNED 0
105797     parameter \A_WIDTH 1
105798     parameter \Y_WIDTH 1
105799     connect \A \main_libresocsim_converter2_skip
105800     connect \Y $not$ls180.v:2937$42_Y
105801   end
105802   attribute \src "ls180.v:3079.34-3079.64"
105803   cell $not $not$ls180.v:3079$66
105804     parameter \A_SIGNED 0
105805     parameter \A_WIDTH 1
105806     parameter \Y_WIDTH 1
105807     connect \A \main_sdram_command_storage [0]
105808     connect \Y $not$ls180.v:3079$66_Y
105809   end
105810   attribute \src "ls180.v:3080.31-3080.61"
105811   cell $not $not$ls180.v:3080$67
105812     parameter \A_SIGNED 0
105813     parameter \A_WIDTH 1
105814     parameter \Y_WIDTH 1
105815     connect \A \main_sdram_command_storage [1]
105816     connect \Y $not$ls180.v:3080$67_Y
105817   end
105818   attribute \src "ls180.v:3081.32-3081.62"
105819   cell $not $not$ls180.v:3081$68
105820     parameter \A_SIGNED 0
105821     parameter \A_WIDTH 1
105822     parameter \Y_WIDTH 1
105823     connect \A \main_sdram_command_storage [2]
105824     connect \Y $not$ls180.v:3081$68_Y
105825   end
105826   attribute \src "ls180.v:3082.32-3082.62"
105827   cell $not $not$ls180.v:3082$69
105828     parameter \A_SIGNED 0
105829     parameter \A_WIDTH 1
105830     parameter \Y_WIDTH 1
105831     connect \A \main_sdram_command_storage [3]
105832     connect \Y $not$ls180.v:3082$69_Y
105833   end
105834   attribute \src "ls180.v:3124.33-3124.56"
105835   cell $not $not$ls180.v:3124$72
105836     parameter \A_SIGNED 0
105837     parameter \A_WIDTH 1
105838     parameter \Y_WIDTH 1
105839     connect \A \main_sdram_timer_done0
105840     connect \Y $not$ls180.v:3124$72_Y
105841   end
105842   attribute \src "ls180.v:3225.58-3225.106"
105843   cell $not $not$ls180.v:3225$102
105844     parameter \A_SIGNED 0
105845     parameter \A_WIDTH 1
105846     parameter \Y_WIDTH 1
105847     connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
105848     connect \Y $not$ls180.v:3225$102_Y
105849   end
105850   attribute \src "ls180.v:3279.9-3279.45"
105851   cell $not $not$ls180.v:3279$107
105852     parameter \A_SIGNED 0
105853     parameter \A_WIDTH 1
105854     parameter \Y_WIDTH 1
105855     connect \A \main_sdram_bankmachine0_refresh_req
105856     connect \Y $not$ls180.v:3279$107_Y
105857   end
105858   attribute \src "ls180.v:3382.58-3382.106"
105859   cell $not $not$ls180.v:3382$132
105860     parameter \A_SIGNED 0
105861     parameter \A_WIDTH 1
105862     parameter \Y_WIDTH 1
105863     connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
105864     connect \Y $not$ls180.v:3382$132_Y
105865   end
105866   attribute \src "ls180.v:3436.9-3436.45"
105867   cell $not $not$ls180.v:3436$137
105868     parameter \A_SIGNED 0
105869     parameter \A_WIDTH 1
105870     parameter \Y_WIDTH 1
105871     connect \A \main_sdram_bankmachine1_refresh_req
105872     connect \Y $not$ls180.v:3436$137_Y
105873   end
105874   attribute \src "ls180.v:3539.58-3539.106"
105875   cell $not $not$ls180.v:3539$162
105876     parameter \A_SIGNED 0
105877     parameter \A_WIDTH 1
105878     parameter \Y_WIDTH 1
105879     connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
105880     connect \Y $not$ls180.v:3539$162_Y
105881   end
105882   attribute \src "ls180.v:3593.9-3593.45"
105883   cell $not $not$ls180.v:3593$167
105884     parameter \A_SIGNED 0
105885     parameter \A_WIDTH 1
105886     parameter \Y_WIDTH 1
105887     connect \A \main_sdram_bankmachine2_refresh_req
105888     connect \Y $not$ls180.v:3593$167_Y
105889   end
105890   attribute \src "ls180.v:3696.58-3696.106"
105891   cell $not $not$ls180.v:3696$192
105892     parameter \A_SIGNED 0
105893     parameter \A_WIDTH 1
105894     parameter \Y_WIDTH 1
105895     connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
105896     connect \Y $not$ls180.v:3696$192_Y
105897   end
105898   attribute \src "ls180.v:3750.9-3750.45"
105899   cell $not $not$ls180.v:3750$197
105900     parameter \A_SIGNED 0
105901     parameter \A_WIDTH 1
105902     parameter \Y_WIDTH 1
105903     connect \A \main_sdram_bankmachine3_refresh_req
105904     connect \Y $not$ls180.v:3750$197_Y
105905   end
105906   attribute \src "ls180.v:3792.149-3792.187"
105907   cell $not $not$ls180.v:3792$200
105908     parameter \A_SIGNED 0
105909     parameter \A_WIDTH 1
105910     parameter \Y_WIDTH 1
105911     connect \A \main_sdram_choose_req_cmd_payload_cas
105912     connect \Y $not$ls180.v:3792$200_Y
105913   end
105914   attribute \src "ls180.v:3792.193-3792.230"
105915   cell $not $not$ls180.v:3792$202
105916     parameter \A_SIGNED 0
105917     parameter \A_WIDTH 1
105918     parameter \Y_WIDTH 1
105919     connect \A \main_sdram_choose_req_cmd_payload_we
105920     connect \Y $not$ls180.v:3792$202_Y
105921   end
105922   attribute \src "ls180.v:3793.149-3793.187"
105923   cell $not $not$ls180.v:3793$206
105924     parameter \A_SIGNED 0
105925     parameter \A_WIDTH 1
105926     parameter \Y_WIDTH 1
105927     connect \A \main_sdram_choose_req_cmd_payload_cas
105928     connect \Y $not$ls180.v:3793$206_Y
105929   end
105930   attribute \src "ls180.v:3793.193-3793.230"
105931   cell $not $not$ls180.v:3793$208
105932     parameter \A_SIGNED 0
105933     parameter \A_WIDTH 1
105934     parameter \Y_WIDTH 1
105935     connect \A \main_sdram_choose_req_cmd_payload_we
105936     connect \Y $not$ls180.v:3793$208_Y
105937   end
105938   attribute \src "ls180.v:3809.43-3809.73"
105939   cell $not $not$ls180.v:3809$236
105940     parameter \A_SIGNED 0
105941     parameter \A_WIDTH 2
105942     parameter \Y_WIDTH 2
105943     connect \A \main_sdram_interface_wdata_we
105944     connect \Y $not$ls180.v:3809$236_Y
105945   end
105946   attribute \src "ls180.v:3812.205-3812.245"
105947   cell $not $not$ls180.v:3812$239
105948     parameter \A_SIGNED 0
105949     parameter \A_WIDTH 1
105950     parameter \Y_WIDTH 1
105951     connect \A \main_sdram_bankmachine0_cmd_payload_cas
105952     connect \Y $not$ls180.v:3812$239_Y
105953   end
105954   attribute \src "ls180.v:3812.251-3812.290"
105955   cell $not $not$ls180.v:3812$241
105956     parameter \A_SIGNED 0
105957     parameter \A_WIDTH 1
105958     parameter \Y_WIDTH 1
105959     connect \A \main_sdram_bankmachine0_cmd_payload_we
105960     connect \Y $not$ls180.v:3812$241_Y
105961   end
105962   attribute \src "ls180.v:3812.159-3812.292"
105963   cell $not $not$ls180.v:3812$243
105964     parameter \A_SIGNED 0
105965     parameter \A_WIDTH 1
105966     parameter \Y_WIDTH 1
105967     connect \A $and$ls180.v:3812$242_Y
105968     connect \Y $not$ls180.v:3812$243_Y
105969   end
105970   attribute \src "ls180.v:3813.205-3813.245"
105971   cell $not $not$ls180.v:3813$252
105972     parameter \A_SIGNED 0
105973     parameter \A_WIDTH 1
105974     parameter \Y_WIDTH 1
105975     connect \A \main_sdram_bankmachine1_cmd_payload_cas
105976     connect \Y $not$ls180.v:3813$252_Y
105977   end
105978   attribute \src "ls180.v:3813.251-3813.290"
105979   cell $not $not$ls180.v:3813$254
105980     parameter \A_SIGNED 0
105981     parameter \A_WIDTH 1
105982     parameter \Y_WIDTH 1
105983     connect \A \main_sdram_bankmachine1_cmd_payload_we
105984     connect \Y $not$ls180.v:3813$254_Y
105985   end
105986   attribute \src "ls180.v:3813.159-3813.292"
105987   cell $not $not$ls180.v:3813$256
105988     parameter \A_SIGNED 0
105989     parameter \A_WIDTH 1
105990     parameter \Y_WIDTH 1
105991     connect \A $and$ls180.v:3813$255_Y
105992     connect \Y $not$ls180.v:3813$256_Y
105993   end
105994   attribute \src "ls180.v:3814.205-3814.245"
105995   cell $not $not$ls180.v:3814$265
105996     parameter \A_SIGNED 0
105997     parameter \A_WIDTH 1
105998     parameter \Y_WIDTH 1
105999     connect \A \main_sdram_bankmachine2_cmd_payload_cas
106000     connect \Y $not$ls180.v:3814$265_Y
106001   end
106002   attribute \src "ls180.v:3814.251-3814.290"
106003   cell $not $not$ls180.v:3814$267
106004     parameter \A_SIGNED 0
106005     parameter \A_WIDTH 1
106006     parameter \Y_WIDTH 1
106007     connect \A \main_sdram_bankmachine2_cmd_payload_we
106008     connect \Y $not$ls180.v:3814$267_Y
106009   end
106010   attribute \src "ls180.v:3814.159-3814.292"
106011   cell $not $not$ls180.v:3814$269
106012     parameter \A_SIGNED 0
106013     parameter \A_WIDTH 1
106014     parameter \Y_WIDTH 1
106015     connect \A $and$ls180.v:3814$268_Y
106016     connect \Y $not$ls180.v:3814$269_Y
106017   end
106018   attribute \src "ls180.v:3815.205-3815.245"
106019   cell $not $not$ls180.v:3815$278
106020     parameter \A_SIGNED 0
106021     parameter \A_WIDTH 1
106022     parameter \Y_WIDTH 1
106023     connect \A \main_sdram_bankmachine3_cmd_payload_cas
106024     connect \Y $not$ls180.v:3815$278_Y
106025   end
106026   attribute \src "ls180.v:3815.251-3815.290"
106027   cell $not $not$ls180.v:3815$280
106028     parameter \A_SIGNED 0
106029     parameter \A_WIDTH 1
106030     parameter \Y_WIDTH 1
106031     connect \A \main_sdram_bankmachine3_cmd_payload_we
106032     connect \Y $not$ls180.v:3815$280_Y
106033   end
106034   attribute \src "ls180.v:3815.159-3815.292"
106035   cell $not $not$ls180.v:3815$282
106036     parameter \A_SIGNED 0
106037     parameter \A_WIDTH 1
106038     parameter \Y_WIDTH 1
106039     connect \A $and$ls180.v:3815$281_Y
106040     connect \Y $not$ls180.v:3815$282_Y
106041   end
106042   attribute \src "ls180.v:3842.71-3842.103"
106043   cell $not $not$ls180.v:3842$293
106044     parameter \A_SIGNED 0
106045     parameter \A_WIDTH 1
106046     parameter \Y_WIDTH 1
106047     connect \A \main_sdram_choose_cmd_cmd_valid
106048     connect \Y $not$ls180.v:3842$293_Y
106049   end
106050   attribute \src "ls180.v:3845.205-3845.245"
106051   cell $not $not$ls180.v:3845$297
106052     parameter \A_SIGNED 0
106053     parameter \A_WIDTH 1
106054     parameter \Y_WIDTH 1
106055     connect \A \main_sdram_bankmachine0_cmd_payload_cas
106056     connect \Y $not$ls180.v:3845$297_Y
106057   end
106058   attribute \src "ls180.v:3845.251-3845.290"
106059   cell $not $not$ls180.v:3845$299
106060     parameter \A_SIGNED 0
106061     parameter \A_WIDTH 1
106062     parameter \Y_WIDTH 1
106063     connect \A \main_sdram_bankmachine0_cmd_payload_we
106064     connect \Y $not$ls180.v:3845$299_Y
106065   end
106066   attribute \src "ls180.v:3845.159-3845.292"
106067   cell $not $not$ls180.v:3845$301
106068     parameter \A_SIGNED 0
106069     parameter \A_WIDTH 1
106070     parameter \Y_WIDTH 1
106071     connect \A $and$ls180.v:3845$300_Y
106072     connect \Y $not$ls180.v:3845$301_Y
106073   end
106074   attribute \src "ls180.v:3846.205-3846.245"
106075   cell $not $not$ls180.v:3846$310
106076     parameter \A_SIGNED 0
106077     parameter \A_WIDTH 1
106078     parameter \Y_WIDTH 1
106079     connect \A \main_sdram_bankmachine1_cmd_payload_cas
106080     connect \Y $not$ls180.v:3846$310_Y
106081   end
106082   attribute \src "ls180.v:3846.251-3846.290"
106083   cell $not $not$ls180.v:3846$312
106084     parameter \A_SIGNED 0
106085     parameter \A_WIDTH 1
106086     parameter \Y_WIDTH 1
106087     connect \A \main_sdram_bankmachine1_cmd_payload_we
106088     connect \Y $not$ls180.v:3846$312_Y
106089   end
106090   attribute \src "ls180.v:3846.159-3846.292"
106091   cell $not $not$ls180.v:3846$314
106092     parameter \A_SIGNED 0
106093     parameter \A_WIDTH 1
106094     parameter \Y_WIDTH 1
106095     connect \A $and$ls180.v:3846$313_Y
106096     connect \Y $not$ls180.v:3846$314_Y
106097   end
106098   attribute \src "ls180.v:3847.205-3847.245"
106099   cell $not $not$ls180.v:3847$323
106100     parameter \A_SIGNED 0
106101     parameter \A_WIDTH 1
106102     parameter \Y_WIDTH 1
106103     connect \A \main_sdram_bankmachine2_cmd_payload_cas
106104     connect \Y $not$ls180.v:3847$323_Y
106105   end
106106   attribute \src "ls180.v:3847.251-3847.290"
106107   cell $not $not$ls180.v:3847$325
106108     parameter \A_SIGNED 0
106109     parameter \A_WIDTH 1
106110     parameter \Y_WIDTH 1
106111     connect \A \main_sdram_bankmachine2_cmd_payload_we
106112     connect \Y $not$ls180.v:3847$325_Y
106113   end
106114   attribute \src "ls180.v:3847.159-3847.292"
106115   cell $not $not$ls180.v:3847$327
106116     parameter \A_SIGNED 0
106117     parameter \A_WIDTH 1
106118     parameter \Y_WIDTH 1
106119     connect \A $and$ls180.v:3847$326_Y
106120     connect \Y $not$ls180.v:3847$327_Y
106121   end
106122   attribute \src "ls180.v:3848.205-3848.245"
106123   cell $not $not$ls180.v:3848$336
106124     parameter \A_SIGNED 0
106125     parameter \A_WIDTH 1
106126     parameter \Y_WIDTH 1
106127     connect \A \main_sdram_bankmachine3_cmd_payload_cas
106128     connect \Y $not$ls180.v:3848$336_Y
106129   end
106130   attribute \src "ls180.v:3848.251-3848.290"
106131   cell $not $not$ls180.v:3848$338
106132     parameter \A_SIGNED 0
106133     parameter \A_WIDTH 1
106134     parameter \Y_WIDTH 1
106135     connect \A \main_sdram_bankmachine3_cmd_payload_we
106136     connect \Y $not$ls180.v:3848$338_Y
106137   end
106138   attribute \src "ls180.v:3848.159-3848.292"
106139   cell $not $not$ls180.v:3848$340
106140     parameter \A_SIGNED 0
106141     parameter \A_WIDTH 1
106142     parameter \Y_WIDTH 1
106143     connect \A $and$ls180.v:3848$339_Y
106144     connect \Y $not$ls180.v:3848$340_Y
106145   end
106146   attribute \src "ls180.v:3911.71-3911.103"
106147   cell $not $not$ls180.v:3911$379
106148     parameter \A_SIGNED 0
106149     parameter \A_WIDTH 1
106150     parameter \Y_WIDTH 1
106151     connect \A \main_sdram_choose_req_cmd_valid
106152     connect \Y $not$ls180.v:3911$379_Y
106153   end
106154   attribute \src "ls180.v:3932.112-3932.150"
106155   cell $not $not$ls180.v:3932$382
106156     parameter \A_SIGNED 0
106157     parameter \A_WIDTH 1
106158     parameter \Y_WIDTH 1
106159     connect \A \main_sdram_choose_req_cmd_payload_cas
106160     connect \Y $not$ls180.v:3932$382_Y
106161   end
106162   attribute \src "ls180.v:3932.156-3932.193"
106163   cell $not $not$ls180.v:3932$384
106164     parameter \A_SIGNED 0
106165     parameter \A_WIDTH 1
106166     parameter \Y_WIDTH 1
106167     connect \A \main_sdram_choose_req_cmd_payload_we
106168     connect \Y $not$ls180.v:3932$384_Y
106169   end
106170   attribute \src "ls180.v:3932.68-3932.195"
106171   cell $not $not$ls180.v:3932$386
106172     parameter \A_SIGNED 0
106173     parameter \A_WIDTH 1
106174     parameter \Y_WIDTH 1
106175     connect \A $and$ls180.v:3932$385_Y
106176     connect \Y $not$ls180.v:3932$386_Y
106177   end
106178   attribute \src "ls180.v:3940.11-3940.38"
106179   cell $not $not$ls180.v:3940$389
106180     parameter \A_SIGNED 0
106181     parameter \A_WIDTH 1
106182     parameter \Y_WIDTH 1
106183     connect \A \main_sdram_write_available
106184     connect \Y $not$ls180.v:3940$389_Y
106185   end
106186   attribute \src "ls180.v:3970.112-3970.150"
106187   cell $not $not$ls180.v:3970$391
106188     parameter \A_SIGNED 0
106189     parameter \A_WIDTH 1
106190     parameter \Y_WIDTH 1
106191     connect \A \main_sdram_choose_req_cmd_payload_cas
106192     connect \Y $not$ls180.v:3970$391_Y
106193   end
106194   attribute \src "ls180.v:3970.156-3970.193"
106195   cell $not $not$ls180.v:3970$393
106196     parameter \A_SIGNED 0
106197     parameter \A_WIDTH 1
106198     parameter \Y_WIDTH 1
106199     connect \A \main_sdram_choose_req_cmd_payload_we
106200     connect \Y $not$ls180.v:3970$393_Y
106201   end
106202   attribute \src "ls180.v:3970.68-3970.195"
106203   cell $not $not$ls180.v:3970$395
106204     parameter \A_SIGNED 0
106205     parameter \A_WIDTH 1
106206     parameter \Y_WIDTH 1
106207     connect \A $and$ls180.v:3970$394_Y
106208     connect \Y $not$ls180.v:3970$395_Y
106209   end
106210   attribute \src "ls180.v:3978.11-3978.37"
106211   cell $not $not$ls180.v:3978$398
106212     parameter \A_SIGNED 0
106213     parameter \A_WIDTH 1
106214     parameter \Y_WIDTH 1
106215     connect \A \main_sdram_read_available
106216     connect \Y $not$ls180.v:3978$398_Y
106217   end
106218   attribute \src "ls180.v:3988.87-3988.331"
106219   cell $not $not$ls180.v:3988$410
106220     parameter \A_SIGNED 0
106221     parameter \A_WIDTH 1
106222     parameter \Y_WIDTH 1
106223     connect \A $or$ls180.v:3988$409_Y
106224     connect \Y $not$ls180.v:3988$410_Y
106225   end
106226   attribute \src "ls180.v:3989.35-3989.68"
106227   cell $not $not$ls180.v:3989$413
106228     parameter \A_SIGNED 0
106229     parameter \A_WIDTH 1
106230     parameter \Y_WIDTH 1
106231     connect \A \main_sdram_interface_bank0_valid
106232     connect \Y $not$ls180.v:3989$413_Y
106233   end
106234   attribute \src "ls180.v:3989.73-3989.105"
106235   cell $not $not$ls180.v:3989$414
106236     parameter \A_SIGNED 0
106237     parameter \A_WIDTH 1
106238     parameter \Y_WIDTH 1
106239     connect \A \main_sdram_interface_bank0_lock
106240     connect \Y $not$ls180.v:3989$414_Y
106241   end
106242   attribute \src "ls180.v:3993.87-3993.331"
106243   cell $not $not$ls180.v:3993$426
106244     parameter \A_SIGNED 0
106245     parameter \A_WIDTH 1
106246     parameter \Y_WIDTH 1
106247     connect \A $or$ls180.v:3993$425_Y
106248     connect \Y $not$ls180.v:3993$426_Y
106249   end
106250   attribute \src "ls180.v:3994.35-3994.68"
106251   cell $not $not$ls180.v:3994$429
106252     parameter \A_SIGNED 0
106253     parameter \A_WIDTH 1
106254     parameter \Y_WIDTH 1
106255     connect \A \main_sdram_interface_bank1_valid
106256     connect \Y $not$ls180.v:3994$429_Y
106257   end
106258   attribute \src "ls180.v:3994.73-3994.105"
106259   cell $not $not$ls180.v:3994$430
106260     parameter \A_SIGNED 0
106261     parameter \A_WIDTH 1
106262     parameter \Y_WIDTH 1
106263     connect \A \main_sdram_interface_bank1_lock
106264     connect \Y $not$ls180.v:3994$430_Y
106265   end
106266   attribute \src "ls180.v:3998.87-3998.331"
106267   cell $not $not$ls180.v:3998$442
106268     parameter \A_SIGNED 0
106269     parameter \A_WIDTH 1
106270     parameter \Y_WIDTH 1
106271     connect \A $or$ls180.v:3998$441_Y
106272     connect \Y $not$ls180.v:3998$442_Y
106273   end
106274   attribute \src "ls180.v:3999.35-3999.68"
106275   cell $not $not$ls180.v:3999$445
106276     parameter \A_SIGNED 0
106277     parameter \A_WIDTH 1
106278     parameter \Y_WIDTH 1
106279     connect \A \main_sdram_interface_bank2_valid
106280     connect \Y $not$ls180.v:3999$445_Y
106281   end
106282   attribute \src "ls180.v:3999.73-3999.105"
106283   cell $not $not$ls180.v:3999$446
106284     parameter \A_SIGNED 0
106285     parameter \A_WIDTH 1
106286     parameter \Y_WIDTH 1
106287     connect \A \main_sdram_interface_bank2_lock
106288     connect \Y $not$ls180.v:3999$446_Y
106289   end
106290   attribute \src "ls180.v:4003.87-4003.331"
106291   cell $not $not$ls180.v:4003$458
106292     parameter \A_SIGNED 0
106293     parameter \A_WIDTH 1
106294     parameter \Y_WIDTH 1
106295     connect \A $or$ls180.v:4003$457_Y
106296     connect \Y $not$ls180.v:4003$458_Y
106297   end
106298   attribute \src "ls180.v:4004.35-4004.68"
106299   cell $not $not$ls180.v:4004$461
106300     parameter \A_SIGNED 0
106301     parameter \A_WIDTH 1
106302     parameter \Y_WIDTH 1
106303     connect \A \main_sdram_interface_bank3_valid
106304     connect \Y $not$ls180.v:4004$461_Y
106305   end
106306   attribute \src "ls180.v:4004.73-4004.105"
106307   cell $not $not$ls180.v:4004$462
106308     parameter \A_SIGNED 0
106309     parameter \A_WIDTH 1
106310     parameter \Y_WIDTH 1
106311     connect \A \main_sdram_interface_bank3_lock
106312     connect \Y $not$ls180.v:4004$462_Y
106313   end
106314   attribute \src "ls180.v:4008.128-4008.372"
106315   cell $not $not$ls180.v:4008$475
106316     parameter \A_SIGNED 0
106317     parameter \A_WIDTH 1
106318     parameter \Y_WIDTH 1
106319     connect \A $or$ls180.v:4008$474_Y
106320     connect \Y $not$ls180.v:4008$475_Y
106321   end
106322   attribute \src "ls180.v:4008.502-4008.746"
106323   cell $not $not$ls180.v:4008$491
106324     parameter \A_SIGNED 0
106325     parameter \A_WIDTH 1
106326     parameter \Y_WIDTH 1
106327     connect \A $or$ls180.v:4008$490_Y
106328     connect \Y $not$ls180.v:4008$491_Y
106329   end
106330   attribute \src "ls180.v:4008.876-4008.1120"
106331   cell $not $not$ls180.v:4008$507
106332     parameter \A_SIGNED 0
106333     parameter \A_WIDTH 1
106334     parameter \Y_WIDTH 1
106335     connect \A $or$ls180.v:4008$506_Y
106336     connect \Y $not$ls180.v:4008$507_Y
106337   end
106338   attribute \src "ls180.v:4008.1250-4008.1494"
106339   cell $not $not$ls180.v:4008$523
106340     parameter \A_SIGNED 0
106341     parameter \A_WIDTH 1
106342     parameter \Y_WIDTH 1
106343     connect \A $or$ls180.v:4008$522_Y
106344     connect \Y $not$ls180.v:4008$523_Y
106345   end
106346   attribute \src "ls180.v:4030.32-4030.50"
106347   cell $not $not$ls180.v:4030$529
106348     parameter \A_SIGNED 0
106349     parameter \A_WIDTH 1
106350     parameter \Y_WIDTH 1
106351     connect \A \main_wb_sdram_cyc
106352     connect \Y $not$ls180.v:4030$529_Y
106353   end
106354   attribute \src "ls180.v:4069.30-4069.50"
106355   cell $not $not$ls180.v:4069$534
106356     parameter \A_SIGNED 0
106357     parameter \A_WIDTH 1
106358     parameter \Y_WIDTH 1
106359     connect \A \main_converter_skip
106360     connect \Y $not$ls180.v:4069$534_Y
106361   end
106362   attribute \src "ls180.v:4070.30-4070.50"
106363   cell $not $not$ls180.v:4070$535
106364     parameter \A_SIGNED 0
106365     parameter \A_WIDTH 1
106366     parameter \Y_WIDTH 1
106367     connect \A \main_converter_skip
106368     connect \Y $not$ls180.v:4070$535_Y
106369   end
106370   attribute \src "ls180.v:4095.27-4095.48"
106371   cell $not $not$ls180.v:4095$541
106372     parameter \A_SIGNED 0
106373     parameter \A_WIDTH 1
106374     parameter \Y_WIDTH 1
106375     connect \A \main_litedram_wb_cyc
106376     connect \Y $not$ls180.v:4095$541_Y
106377   end
106378   attribute \src "ls180.v:4096.30-4096.50"
106379   cell $not $not$ls180.v:4096$542
106380     parameter \A_SIGNED 0
106381     parameter \A_WIDTH 1
106382     parameter \Y_WIDTH 1
106383     connect \A \main_litedram_wb_we
106384     connect \Y $not$ls180.v:4096$542_Y
106385   end
106386   attribute \src "ls180.v:4097.80-4097.98"
106387   cell $not $not$ls180.v:4097$544
106388     parameter \A_SIGNED 0
106389     parameter \A_WIDTH 1
106390     parameter \Y_WIDTH 1
106391     connect \A \main_cmd_consumed
106392     connect \Y $not$ls180.v:4097$544_Y
106393   end
106394   attribute \src "ls180.v:4098.107-4098.127"
106395   cell $not $not$ls180.v:4098$548
106396     parameter \A_SIGNED 0
106397     parameter \A_WIDTH 1
106398     parameter \Y_WIDTH 1
106399     connect \A \main_wdata_consumed
106400     connect \Y $not$ls180.v:4098$548_Y
106401   end
106402   attribute \src "ls180.v:4099.78-4099.103"
106403   cell $not $not$ls180.v:4099$551
106404     parameter \A_SIGNED 0
106405     parameter \A_WIDTH 1
106406     parameter \Y_WIDTH 1
106407     connect \A \main_port_cmd_payload_we
106408     connect \Y $not$ls180.v:4099$551_Y
106409   end
106410   attribute \src "ls180.v:4100.91-4100.111"
106411   cell $not $not$ls180.v:4100$554
106412     parameter \A_SIGNED 0
106413     parameter \A_WIDTH 1
106414     parameter \Y_WIDTH 1
106415     connect \A \main_litedram_wb_we
106416     connect \Y $not$ls180.v:4100$554_Y
106417   end
106418   attribute \src "ls180.v:4116.35-4116.64"
106419   cell $not $not$ls180.v:4116$563
106420     parameter \A_SIGNED 0
106421     parameter \A_WIDTH 1
106422     parameter \Y_WIDTH 1
106423     connect \A \main_uart_tx_fifo_sink_ready
106424     connect \Y $not$ls180.v:4116$563_Y
106425   end
106426   attribute \src "ls180.v:4117.36-4117.67"
106427   cell $not $not$ls180.v:4117$564
106428     parameter \A_SIGNED 0
106429     parameter \A_WIDTH 1
106430     parameter \Y_WIDTH 1
106431     connect \A \main_uart_tx_fifo_source_valid
106432     connect \Y $not$ls180.v:4117$564_Y
106433   end
106434   attribute \src "ls180.v:4123.32-4123.61"
106435   cell $not $not$ls180.v:4123$565
106436     parameter \A_SIGNED 0
106437     parameter \A_WIDTH 1
106438     parameter \Y_WIDTH 1
106439     connect \A \main_uart_tx_fifo_sink_ready
106440     connect \Y $not$ls180.v:4123$565_Y
106441   end
106442   attribute \src "ls180.v:4129.36-4129.67"
106443   cell $not $not$ls180.v:4129$566
106444     parameter \A_SIGNED 0
106445     parameter \A_WIDTH 1
106446     parameter \Y_WIDTH 1
106447     connect \A \main_uart_rx_fifo_source_valid
106448     connect \Y $not$ls180.v:4129$566_Y
106449   end
106450   attribute \src "ls180.v:4130.35-4130.64"
106451   cell $not $not$ls180.v:4130$567
106452     parameter \A_SIGNED 0
106453     parameter \A_WIDTH 1
106454     parameter \Y_WIDTH 1
106455     connect \A \main_uart_rx_fifo_sink_ready
106456     connect \Y $not$ls180.v:4130$567_Y
106457   end
106458   attribute \src "ls180.v:4133.32-4133.63"
106459   cell $not $not$ls180.v:4133$570
106460     parameter \A_SIGNED 0
106461     parameter \A_WIDTH 1
106462     parameter \Y_WIDTH 1
106463     connect \A \main_uart_rx_fifo_source_valid
106464     connect \Y $not$ls180.v:4133$570_Y
106465   end
106466   attribute \src "ls180.v:4171.81-4171.108"
106467   cell $not $not$ls180.v:4171$580
106468     parameter \A_SIGNED 0
106469     parameter \A_WIDTH 1
106470     parameter \Y_WIDTH 1
106471     connect \A \main_uart_tx_fifo_readable
106472     connect \Y $not$ls180.v:4171$580_Y
106473   end
106474   attribute \src "ls180.v:4201.81-4201.108"
106475   cell $not $not$ls180.v:4201$591
106476     parameter \A_SIGNED 0
106477     parameter \A_WIDTH 1
106478     parameter \Y_WIDTH 1
106479     connect \A \main_uart_rx_fifo_readable
106480     connect \Y $not$ls180.v:4201$591_Y
106481   end
106482   attribute \src "ls180.v:4401.60-4401.85"
106483   cell $not $not$ls180.v:4401$640
106484     parameter \A_SIGNED 0
106485     parameter \A_WIDTH 1
106486     parameter \Y_WIDTH 1
106487     connect \A \main_sdphy_clocker_clk_d
106488     connect \Y $not$ls180.v:4401$640_Y
106489   end
106490   attribute \src "ls180.v:4542.54-4542.96"
106491   cell $not $not$ls180.v:4542$654
106492     parameter \A_SIGNED 0
106493     parameter \A_WIDTH 1
106494     parameter \Y_WIDTH 1
106495     connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all
106496     connect \Y $not$ls180.v:4542$654_Y
106497   end
106498   attribute \src "ls180.v:4545.48-4545.86"
106499   cell $not $not$ls180.v:4545$657
106500     parameter \A_SIGNED 0
106501     parameter \A_WIDTH 1
106502     parameter \Y_WIDTH 1
106503     connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
106504     connect \Y $not$ls180.v:4545$657_Y
106505   end
106506   attribute \src "ls180.v:4669.55-4669.98"
106507   cell $not $not$ls180.v:4669$675
106508     parameter \A_SIGNED 0
106509     parameter \A_WIDTH 1
106510     parameter \Y_WIDTH 1
106511     connect \A \main_sdphy_dataw_crcr_converter_strobe_all
106512     connect \Y $not$ls180.v:4669$675_Y
106513   end
106514   attribute \src "ls180.v:4672.49-4672.88"
106515   cell $not $not$ls180.v:4672$678
106516     parameter \A_SIGNED 0
106517     parameter \A_WIDTH 1
106518     parameter \Y_WIDTH 1
106519     connect \A \main_sdphy_dataw_crcr_buf_source_valid
106520     connect \Y $not$ls180.v:4672$678_Y
106521   end
106522   attribute \src "ls180.v:4722.30-4722.58"
106523   cell $not $not$ls180.v:4722$684
106524     parameter \A_SIGNED 0
106525     parameter \A_WIDTH 1
106526     parameter \Y_WIDTH 1
106527     connect \A \main_sdphy_dataw_sink_valid
106528     connect \Y $not$ls180.v:4722$684_Y
106529   end
106530   attribute \src "ls180.v:4803.56-4803.100"
106531   cell $not $not$ls180.v:4803$690
106532     parameter \A_SIGNED 0
106533     parameter \A_WIDTH 1
106534     parameter \Y_WIDTH 1
106535     connect \A \main_sdphy_datar_datar_converter_strobe_all
106536     connect \Y $not$ls180.v:4803$690_Y
106537   end
106538   attribute \src "ls180.v:4806.50-4806.90"
106539   cell $not $not$ls180.v:4806$693
106540     parameter \A_SIGNED 0
106541     parameter \A_WIDTH 1
106542     parameter \Y_WIDTH 1
106543     connect \A \main_sdphy_datar_datar_buf_source_valid
106544     connect \Y $not$ls180.v:4806$693_Y
106545   end
106546   attribute \src "ls180.v:4922.42-4922.74"
106547   cell $not $not$ls180.v:4922$709
106548     parameter \A_SIGNED 0
106549     parameter \A_WIDTH 1
106550     parameter \Y_WIDTH 1
106551     connect \A \main_sdcore_crc16_checker_valid
106552     connect \Y $not$ls180.v:4922$709_Y
106553   end
106554   attribute \src "ls180.v:5446.50-5446.88"
106555   cell $not $not$ls180.v:5446$994
106556     parameter \A_SIGNED 0
106557     parameter \A_WIDTH 1
106558     parameter \Y_WIDTH 1
106559     connect \A \main_sdblock2mem_converter_strobe_all
106560     connect \Y $not$ls180.v:5446$994_Y
106561   end
106562   attribute \src "ls180.v:5458.52-5458.102"
106563   cell $not $not$ls180.v:5458$997
106564     parameter \A_SIGNED 0
106565     parameter \A_WIDTH 1
106566     parameter \Y_WIDTH 1
106567     connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage
106568     connect \Y $not$ls180.v:5458$997_Y
106569   end
106570   attribute \src "ls180.v:5517.38-5517.74"
106571   cell $not $not$ls180.v:5517$1004
106572     parameter \A_SIGNED 0
106573     parameter \A_WIDTH 1
106574     parameter \Y_WIDTH 1
106575     connect \A \main_sdmem2block_dma_enable_storage
106576     connect \Y $not$ls180.v:5517$1004_Y
106577   end
106578   attribute \src "ls180.v:5759.69-5759.88"
106579   cell $not $not$ls180.v:5759$1065
106580     parameter \A_SIGNED 0
106581     parameter \A_WIDTH 1
106582     parameter \Y_WIDTH 1
106583     connect \A \builder_shared_ack
106584     connect \Y $not$ls180.v:5759$1065_Y
106585   end
106586   attribute \src "ls180.v:5776.63-5776.94"
106587   cell $not $not$ls180.v:5776$1086
106588     parameter \A_SIGNED 0
106589     parameter \A_WIDTH 1
106590     parameter \Y_WIDTH 1
106591     connect \A \builder_interface0_bank_bus_we
106592     connect \Y $not$ls180.v:5776$1086_Y
106593   end
106594   attribute \src "ls180.v:5779.65-5779.96"
106595   cell $not $not$ls180.v:5779$1093
106596     parameter \A_SIGNED 0
106597     parameter \A_WIDTH 1
106598     parameter \Y_WIDTH 1
106599     connect \A \builder_interface0_bank_bus_we
106600     connect \Y $not$ls180.v:5779$1093_Y
106601   end
106602   attribute \src "ls180.v:5782.65-5782.96"
106603   cell $not $not$ls180.v:5782$1100
106604     parameter \A_SIGNED 0
106605     parameter \A_WIDTH 1
106606     parameter \Y_WIDTH 1
106607     connect \A \builder_interface0_bank_bus_we
106608     connect \Y $not$ls180.v:5782$1100_Y
106609   end
106610   attribute \src "ls180.v:5785.65-5785.96"
106611   cell $not $not$ls180.v:5785$1107
106612     parameter \A_SIGNED 0
106613     parameter \A_WIDTH 1
106614     parameter \Y_WIDTH 1
106615     connect \A \builder_interface0_bank_bus_we
106616     connect \Y $not$ls180.v:5785$1107_Y
106617   end
106618   attribute \src "ls180.v:5788.65-5788.96"
106619   cell $not $not$ls180.v:5788$1114
106620     parameter \A_SIGNED 0
106621     parameter \A_WIDTH 1
106622     parameter \Y_WIDTH 1
106623     connect \A \builder_interface0_bank_bus_we
106624     connect \Y $not$ls180.v:5788$1114_Y
106625   end
106626   attribute \src "ls180.v:5791.68-5791.99"
106627   cell $not $not$ls180.v:5791$1121
106628     parameter \A_SIGNED 0
106629     parameter \A_WIDTH 1
106630     parameter \Y_WIDTH 1
106631     connect \A \builder_interface0_bank_bus_we
106632     connect \Y $not$ls180.v:5791$1121_Y
106633   end
106634   attribute \src "ls180.v:5794.68-5794.99"
106635   cell $not $not$ls180.v:5794$1128
106636     parameter \A_SIGNED 0
106637     parameter \A_WIDTH 1
106638     parameter \Y_WIDTH 1
106639     connect \A \builder_interface0_bank_bus_we
106640     connect \Y $not$ls180.v:5794$1128_Y
106641   end
106642   attribute \src "ls180.v:5797.68-5797.99"
106643   cell $not $not$ls180.v:5797$1135
106644     parameter \A_SIGNED 0
106645     parameter \A_WIDTH 1
106646     parameter \Y_WIDTH 1
106647     connect \A \builder_interface0_bank_bus_we
106648     connect \Y $not$ls180.v:5797$1135_Y
106649   end
106650   attribute \src "ls180.v:5800.68-5800.99"
106651   cell $not $not$ls180.v:5800$1142
106652     parameter \A_SIGNED 0
106653     parameter \A_WIDTH 1
106654     parameter \Y_WIDTH 1
106655     connect \A \builder_interface0_bank_bus_we
106656     connect \Y $not$ls180.v:5800$1142_Y
106657   end
106658   attribute \src "ls180.v:5814.60-5814.91"
106659   cell $not $not$ls180.v:5814$1150
106660     parameter \A_SIGNED 0
106661     parameter \A_WIDTH 1
106662     parameter \Y_WIDTH 1
106663     connect \A \builder_interface1_bank_bus_we
106664     connect \Y $not$ls180.v:5814$1150_Y
106665   end
106666   attribute \src "ls180.v:5817.60-5817.91"
106667   cell $not $not$ls180.v:5817$1157
106668     parameter \A_SIGNED 0
106669     parameter \A_WIDTH 1
106670     parameter \Y_WIDTH 1
106671     connect \A \builder_interface1_bank_bus_we
106672     connect \Y $not$ls180.v:5817$1157_Y
106673   end
106674   attribute \src "ls180.v:5820.60-5820.91"
106675   cell $not $not$ls180.v:5820$1164
106676     parameter \A_SIGNED 0
106677     parameter \A_WIDTH 1
106678     parameter \Y_WIDTH 1
106679     connect \A \builder_interface1_bank_bus_we
106680     connect \Y $not$ls180.v:5820$1164_Y
106681   end
106682   attribute \src "ls180.v:5823.60-5823.91"
106683   cell $not $not$ls180.v:5823$1171
106684     parameter \A_SIGNED 0
106685     parameter \A_WIDTH 1
106686     parameter \Y_WIDTH 1
106687     connect \A \builder_interface1_bank_bus_we
106688     connect \Y $not$ls180.v:5823$1171_Y
106689   end
106690   attribute \src "ls180.v:5826.61-5826.92"
106691   cell $not $not$ls180.v:5826$1178
106692     parameter \A_SIGNED 0
106693     parameter \A_WIDTH 1
106694     parameter \Y_WIDTH 1
106695     connect \A \builder_interface1_bank_bus_we
106696     connect \Y $not$ls180.v:5826$1178_Y
106697   end
106698   attribute \src "ls180.v:5829.61-5829.92"
106699   cell $not $not$ls180.v:5829$1185
106700     parameter \A_SIGNED 0
106701     parameter \A_WIDTH 1
106702     parameter \Y_WIDTH 1
106703     connect \A \builder_interface1_bank_bus_we
106704     connect \Y $not$ls180.v:5829$1185_Y
106705   end
106706   attribute \src "ls180.v:5840.59-5840.90"
106707   cell $not $not$ls180.v:5840$1193
106708     parameter \A_SIGNED 0
106709     parameter \A_WIDTH 1
106710     parameter \Y_WIDTH 1
106711     connect \A \builder_interface2_bank_bus_we
106712     connect \Y $not$ls180.v:5840$1193_Y
106713   end
106714   attribute \src "ls180.v:5843.58-5843.89"
106715   cell $not $not$ls180.v:5843$1200
106716     parameter \A_SIGNED 0
106717     parameter \A_WIDTH 1
106718     parameter \Y_WIDTH 1
106719     connect \A \builder_interface2_bank_bus_we
106720     connect \Y $not$ls180.v:5843$1200_Y
106721   end
106722   attribute \src "ls180.v:5854.64-5854.95"
106723   cell $not $not$ls180.v:5854$1208
106724     parameter \A_SIGNED 0
106725     parameter \A_WIDTH 1
106726     parameter \Y_WIDTH 1
106727     connect \A \builder_interface3_bank_bus_we
106728     connect \Y $not$ls180.v:5854$1208_Y
106729   end
106730   attribute \src "ls180.v:5857.63-5857.94"
106731   cell $not $not$ls180.v:5857$1215
106732     parameter \A_SIGNED 0
106733     parameter \A_WIDTH 1
106734     parameter \Y_WIDTH 1
106735     connect \A \builder_interface3_bank_bus_we
106736     connect \Y $not$ls180.v:5857$1215_Y
106737   end
106738   attribute \src "ls180.v:5860.63-5860.94"
106739   cell $not $not$ls180.v:5860$1222
106740     parameter \A_SIGNED 0
106741     parameter \A_WIDTH 1
106742     parameter \Y_WIDTH 1
106743     connect \A \builder_interface3_bank_bus_we
106744     connect \Y $not$ls180.v:5860$1222_Y
106745   end
106746   attribute \src "ls180.v:5863.63-5863.94"
106747   cell $not $not$ls180.v:5863$1229
106748     parameter \A_SIGNED 0
106749     parameter \A_WIDTH 1
106750     parameter \Y_WIDTH 1
106751     connect \A \builder_interface3_bank_bus_we
106752     connect \Y $not$ls180.v:5863$1229_Y
106753   end
106754   attribute \src "ls180.v:5866.63-5866.94"
106755   cell $not $not$ls180.v:5866$1236
106756     parameter \A_SIGNED 0
106757     parameter \A_WIDTH 1
106758     parameter \Y_WIDTH 1
106759     connect \A \builder_interface3_bank_bus_we
106760     connect \Y $not$ls180.v:5866$1236_Y
106761   end
106762   attribute \src "ls180.v:5869.64-5869.95"
106763   cell $not $not$ls180.v:5869$1243
106764     parameter \A_SIGNED 0
106765     parameter \A_WIDTH 1
106766     parameter \Y_WIDTH 1
106767     connect \A \builder_interface3_bank_bus_we
106768     connect \Y $not$ls180.v:5869$1243_Y
106769   end
106770   attribute \src "ls180.v:5872.64-5872.95"
106771   cell $not $not$ls180.v:5872$1250
106772     parameter \A_SIGNED 0
106773     parameter \A_WIDTH 1
106774     parameter \Y_WIDTH 1
106775     connect \A \builder_interface3_bank_bus_we
106776     connect \Y $not$ls180.v:5872$1250_Y
106777   end
106778   attribute \src "ls180.v:5875.64-5875.95"
106779   cell $not $not$ls180.v:5875$1257
106780     parameter \A_SIGNED 0
106781     parameter \A_WIDTH 1
106782     parameter \Y_WIDTH 1
106783     connect \A \builder_interface3_bank_bus_we
106784     connect \Y $not$ls180.v:5875$1257_Y
106785   end
106786   attribute \src "ls180.v:5878.64-5878.95"
106787   cell $not $not$ls180.v:5878$1264
106788     parameter \A_SIGNED 0
106789     parameter \A_WIDTH 1
106790     parameter \Y_WIDTH 1
106791     connect \A \builder_interface3_bank_bus_we
106792     connect \Y $not$ls180.v:5878$1264_Y
106793   end
106794   attribute \src "ls180.v:5891.64-5891.95"
106795   cell $not $not$ls180.v:5891$1272
106796     parameter \A_SIGNED 0
106797     parameter \A_WIDTH 1
106798     parameter \Y_WIDTH 1
106799     connect \A \builder_interface4_bank_bus_we
106800     connect \Y $not$ls180.v:5891$1272_Y
106801   end
106802   attribute \src "ls180.v:5894.63-5894.94"
106803   cell $not $not$ls180.v:5894$1279
106804     parameter \A_SIGNED 0
106805     parameter \A_WIDTH 1
106806     parameter \Y_WIDTH 1
106807     connect \A \builder_interface4_bank_bus_we
106808     connect \Y $not$ls180.v:5894$1279_Y
106809   end
106810   attribute \src "ls180.v:5897.63-5897.94"
106811   cell $not $not$ls180.v:5897$1286
106812     parameter \A_SIGNED 0
106813     parameter \A_WIDTH 1
106814     parameter \Y_WIDTH 1
106815     connect \A \builder_interface4_bank_bus_we
106816     connect \Y $not$ls180.v:5897$1286_Y
106817   end
106818   attribute \src "ls180.v:5900.63-5900.94"
106819   cell $not $not$ls180.v:5900$1293
106820     parameter \A_SIGNED 0
106821     parameter \A_WIDTH 1
106822     parameter \Y_WIDTH 1
106823     connect \A \builder_interface4_bank_bus_we
106824     connect \Y $not$ls180.v:5900$1293_Y
106825   end
106826   attribute \src "ls180.v:5903.63-5903.94"
106827   cell $not $not$ls180.v:5903$1300
106828     parameter \A_SIGNED 0
106829     parameter \A_WIDTH 1
106830     parameter \Y_WIDTH 1
106831     connect \A \builder_interface4_bank_bus_we
106832     connect \Y $not$ls180.v:5903$1300_Y
106833   end
106834   attribute \src "ls180.v:5906.64-5906.95"
106835   cell $not $not$ls180.v:5906$1307
106836     parameter \A_SIGNED 0
106837     parameter \A_WIDTH 1
106838     parameter \Y_WIDTH 1
106839     connect \A \builder_interface4_bank_bus_we
106840     connect \Y $not$ls180.v:5906$1307_Y
106841   end
106842   attribute \src "ls180.v:5909.64-5909.95"
106843   cell $not $not$ls180.v:5909$1314
106844     parameter \A_SIGNED 0
106845     parameter \A_WIDTH 1
106846     parameter \Y_WIDTH 1
106847     connect \A \builder_interface4_bank_bus_we
106848     connect \Y $not$ls180.v:5909$1314_Y
106849   end
106850   attribute \src "ls180.v:5912.64-5912.95"
106851   cell $not $not$ls180.v:5912$1321
106852     parameter \A_SIGNED 0
106853     parameter \A_WIDTH 1
106854     parameter \Y_WIDTH 1
106855     connect \A \builder_interface4_bank_bus_we
106856     connect \Y $not$ls180.v:5912$1321_Y
106857   end
106858   attribute \src "ls180.v:5915.64-5915.95"
106859   cell $not $not$ls180.v:5915$1328
106860     parameter \A_SIGNED 0
106861     parameter \A_WIDTH 1
106862     parameter \Y_WIDTH 1
106863     connect \A \builder_interface4_bank_bus_we
106864     connect \Y $not$ls180.v:5915$1328_Y
106865   end
106866   attribute \src "ls180.v:5928.66-5928.97"
106867   cell $not $not$ls180.v:5928$1336
106868     parameter \A_SIGNED 0
106869     parameter \A_WIDTH 1
106870     parameter \Y_WIDTH 1
106871     connect \A \builder_interface5_bank_bus_we
106872     connect \Y $not$ls180.v:5928$1336_Y
106873   end
106874   attribute \src "ls180.v:5931.66-5931.97"
106875   cell $not $not$ls180.v:5931$1343
106876     parameter \A_SIGNED 0
106877     parameter \A_WIDTH 1
106878     parameter \Y_WIDTH 1
106879     connect \A \builder_interface5_bank_bus_we
106880     connect \Y $not$ls180.v:5931$1343_Y
106881   end
106882   attribute \src "ls180.v:5934.66-5934.97"
106883   cell $not $not$ls180.v:5934$1350
106884     parameter \A_SIGNED 0
106885     parameter \A_WIDTH 1
106886     parameter \Y_WIDTH 1
106887     connect \A \builder_interface5_bank_bus_we
106888     connect \Y $not$ls180.v:5934$1350_Y
106889   end
106890   attribute \src "ls180.v:5937.66-5937.97"
106891   cell $not $not$ls180.v:5937$1357
106892     parameter \A_SIGNED 0
106893     parameter \A_WIDTH 1
106894     parameter \Y_WIDTH 1
106895     connect \A \builder_interface5_bank_bus_we
106896     connect \Y $not$ls180.v:5937$1357_Y
106897   end
106898   attribute \src "ls180.v:5940.66-5940.97"
106899   cell $not $not$ls180.v:5940$1364
106900     parameter \A_SIGNED 0
106901     parameter \A_WIDTH 1
106902     parameter \Y_WIDTH 1
106903     connect \A \builder_interface5_bank_bus_we
106904     connect \Y $not$ls180.v:5940$1364_Y
106905   end
106906   attribute \src "ls180.v:5943.66-5943.97"
106907   cell $not $not$ls180.v:5943$1371
106908     parameter \A_SIGNED 0
106909     parameter \A_WIDTH 1
106910     parameter \Y_WIDTH 1
106911     connect \A \builder_interface5_bank_bus_we
106912     connect \Y $not$ls180.v:5943$1371_Y
106913   end
106914   attribute \src "ls180.v:5946.66-5946.97"
106915   cell $not $not$ls180.v:5946$1378
106916     parameter \A_SIGNED 0
106917     parameter \A_WIDTH 1
106918     parameter \Y_WIDTH 1
106919     connect \A \builder_interface5_bank_bus_we
106920     connect \Y $not$ls180.v:5946$1378_Y
106921   end
106922   attribute \src "ls180.v:5949.66-5949.97"
106923   cell $not $not$ls180.v:5949$1385
106924     parameter \A_SIGNED 0
106925     parameter \A_WIDTH 1
106926     parameter \Y_WIDTH 1
106927     connect \A \builder_interface5_bank_bus_we
106928     connect \Y $not$ls180.v:5949$1385_Y
106929   end
106930   attribute \src "ls180.v:5952.68-5952.99"
106931   cell $not $not$ls180.v:5952$1392
106932     parameter \A_SIGNED 0
106933     parameter \A_WIDTH 1
106934     parameter \Y_WIDTH 1
106935     connect \A \builder_interface5_bank_bus_we
106936     connect \Y $not$ls180.v:5952$1392_Y
106937   end
106938   attribute \src "ls180.v:5955.68-5955.99"
106939   cell $not $not$ls180.v:5955$1399
106940     parameter \A_SIGNED 0
106941     parameter \A_WIDTH 1
106942     parameter \Y_WIDTH 1
106943     connect \A \builder_interface5_bank_bus_we
106944     connect \Y $not$ls180.v:5955$1399_Y
106945   end
106946   attribute \src "ls180.v:5958.68-5958.99"
106947   cell $not $not$ls180.v:5958$1406
106948     parameter \A_SIGNED 0
106949     parameter \A_WIDTH 1
106950     parameter \Y_WIDTH 1
106951     connect \A \builder_interface5_bank_bus_we
106952     connect \Y $not$ls180.v:5958$1406_Y
106953   end
106954   attribute \src "ls180.v:5961.68-5961.99"
106955   cell $not $not$ls180.v:5961$1413
106956     parameter \A_SIGNED 0
106957     parameter \A_WIDTH 1
106958     parameter \Y_WIDTH 1
106959     connect \A \builder_interface5_bank_bus_we
106960     connect \Y $not$ls180.v:5961$1413_Y
106961   end
106962   attribute \src "ls180.v:5964.68-5964.99"
106963   cell $not $not$ls180.v:5964$1420
106964     parameter \A_SIGNED 0
106965     parameter \A_WIDTH 1
106966     parameter \Y_WIDTH 1
106967     connect \A \builder_interface5_bank_bus_we
106968     connect \Y $not$ls180.v:5964$1420_Y
106969   end
106970   attribute \src "ls180.v:5967.65-5967.96"
106971   cell $not $not$ls180.v:5967$1427
106972     parameter \A_SIGNED 0
106973     parameter \A_WIDTH 1
106974     parameter \Y_WIDTH 1
106975     connect \A \builder_interface5_bank_bus_we
106976     connect \Y $not$ls180.v:5967$1427_Y
106977   end
106978   attribute \src "ls180.v:5970.66-5970.97"
106979   cell $not $not$ls180.v:5970$1434
106980     parameter \A_SIGNED 0
106981     parameter \A_WIDTH 1
106982     parameter \Y_WIDTH 1
106983     connect \A \builder_interface5_bank_bus_we
106984     connect \Y $not$ls180.v:5970$1434_Y
106985   end
106986   attribute \src "ls180.v:5990.70-5990.101"
106987   cell $not $not$ls180.v:5990$1442
106988     parameter \A_SIGNED 0
106989     parameter \A_WIDTH 1
106990     parameter \Y_WIDTH 1
106991     connect \A \builder_interface6_bank_bus_we
106992     connect \Y $not$ls180.v:5990$1442_Y
106993   end
106994   attribute \src "ls180.v:5993.70-5993.101"
106995   cell $not $not$ls180.v:5993$1449
106996     parameter \A_SIGNED 0
106997     parameter \A_WIDTH 1
106998     parameter \Y_WIDTH 1
106999     connect \A \builder_interface6_bank_bus_we
107000     connect \Y $not$ls180.v:5993$1449_Y
107001   end
107002   attribute \src "ls180.v:5996.70-5996.101"
107003   cell $not $not$ls180.v:5996$1456
107004     parameter \A_SIGNED 0
107005     parameter \A_WIDTH 1
107006     parameter \Y_WIDTH 1
107007     connect \A \builder_interface6_bank_bus_we
107008     connect \Y $not$ls180.v:5996$1456_Y
107009   end
107010   attribute \src "ls180.v:5999.70-5999.101"
107011   cell $not $not$ls180.v:5999$1463
107012     parameter \A_SIGNED 0
107013     parameter \A_WIDTH 1
107014     parameter \Y_WIDTH 1
107015     connect \A \builder_interface6_bank_bus_we
107016     connect \Y $not$ls180.v:5999$1463_Y
107017   end
107018   attribute \src "ls180.v:6002.69-6002.100"
107019   cell $not $not$ls180.v:6002$1470
107020     parameter \A_SIGNED 0
107021     parameter \A_WIDTH 1
107022     parameter \Y_WIDTH 1
107023     connect \A \builder_interface6_bank_bus_we
107024     connect \Y $not$ls180.v:6002$1470_Y
107025   end
107026   attribute \src "ls180.v:6005.69-6005.100"
107027   cell $not $not$ls180.v:6005$1477
107028     parameter \A_SIGNED 0
107029     parameter \A_WIDTH 1
107030     parameter \Y_WIDTH 1
107031     connect \A \builder_interface6_bank_bus_we
107032     connect \Y $not$ls180.v:6005$1477_Y
107033   end
107034   attribute \src "ls180.v:6008.69-6008.100"
107035   cell $not $not$ls180.v:6008$1484
107036     parameter \A_SIGNED 0
107037     parameter \A_WIDTH 1
107038     parameter \Y_WIDTH 1
107039     connect \A \builder_interface6_bank_bus_we
107040     connect \Y $not$ls180.v:6008$1484_Y
107041   end
107042   attribute \src "ls180.v:6011.69-6011.100"
107043   cell $not $not$ls180.v:6011$1491
107044     parameter \A_SIGNED 0
107045     parameter \A_WIDTH 1
107046     parameter \Y_WIDTH 1
107047     connect \A \builder_interface6_bank_bus_we
107048     connect \Y $not$ls180.v:6011$1491_Y
107049   end
107050   attribute \src "ls180.v:6014.60-6014.91"
107051   cell $not $not$ls180.v:6014$1498
107052     parameter \A_SIGNED 0
107053     parameter \A_WIDTH 1
107054     parameter \Y_WIDTH 1
107055     connect \A \builder_interface6_bank_bus_we
107056     connect \Y $not$ls180.v:6014$1498_Y
107057   end
107058   attribute \src "ls180.v:6017.71-6017.102"
107059   cell $not $not$ls180.v:6017$1505
107060     parameter \A_SIGNED 0
107061     parameter \A_WIDTH 1
107062     parameter \Y_WIDTH 1
107063     connect \A \builder_interface6_bank_bus_we
107064     connect \Y $not$ls180.v:6017$1505_Y
107065   end
107066   attribute \src "ls180.v:6020.71-6020.102"
107067   cell $not $not$ls180.v:6020$1512
107068     parameter \A_SIGNED 0
107069     parameter \A_WIDTH 1
107070     parameter \Y_WIDTH 1
107071     connect \A \builder_interface6_bank_bus_we
107072     connect \Y $not$ls180.v:6020$1512_Y
107073   end
107074   attribute \src "ls180.v:6023.71-6023.102"
107075   cell $not $not$ls180.v:6023$1519
107076     parameter \A_SIGNED 0
107077     parameter \A_WIDTH 1
107078     parameter \Y_WIDTH 1
107079     connect \A \builder_interface6_bank_bus_we
107080     connect \Y $not$ls180.v:6023$1519_Y
107081   end
107082   attribute \src "ls180.v:6026.71-6026.102"
107083   cell $not $not$ls180.v:6026$1526
107084     parameter \A_SIGNED 0
107085     parameter \A_WIDTH 1
107086     parameter \Y_WIDTH 1
107087     connect \A \builder_interface6_bank_bus_we
107088     connect \Y $not$ls180.v:6026$1526_Y
107089   end
107090   attribute \src "ls180.v:6029.71-6029.102"
107091   cell $not $not$ls180.v:6029$1533
107092     parameter \A_SIGNED 0
107093     parameter \A_WIDTH 1
107094     parameter \Y_WIDTH 1
107095     connect \A \builder_interface6_bank_bus_we
107096     connect \Y $not$ls180.v:6029$1533_Y
107097   end
107098   attribute \src "ls180.v:6032.71-6032.102"
107099   cell $not $not$ls180.v:6032$1540
107100     parameter \A_SIGNED 0
107101     parameter \A_WIDTH 1
107102     parameter \Y_WIDTH 1
107103     connect \A \builder_interface6_bank_bus_we
107104     connect \Y $not$ls180.v:6032$1540_Y
107105   end
107106   attribute \src "ls180.v:6035.70-6035.101"
107107   cell $not $not$ls180.v:6035$1547
107108     parameter \A_SIGNED 0
107109     parameter \A_WIDTH 1
107110     parameter \Y_WIDTH 1
107111     connect \A \builder_interface6_bank_bus_we
107112     connect \Y $not$ls180.v:6035$1547_Y
107113   end
107114   attribute \src "ls180.v:6038.70-6038.101"
107115   cell $not $not$ls180.v:6038$1554
107116     parameter \A_SIGNED 0
107117     parameter \A_WIDTH 1
107118     parameter \Y_WIDTH 1
107119     connect \A \builder_interface6_bank_bus_we
107120     connect \Y $not$ls180.v:6038$1554_Y
107121   end
107122   attribute \src "ls180.v:6041.70-6041.101"
107123   cell $not $not$ls180.v:6041$1561
107124     parameter \A_SIGNED 0
107125     parameter \A_WIDTH 1
107126     parameter \Y_WIDTH 1
107127     connect \A \builder_interface6_bank_bus_we
107128     connect \Y $not$ls180.v:6041$1561_Y
107129   end
107130   attribute \src "ls180.v:6044.70-6044.101"
107131   cell $not $not$ls180.v:6044$1568
107132     parameter \A_SIGNED 0
107133     parameter \A_WIDTH 1
107134     parameter \Y_WIDTH 1
107135     connect \A \builder_interface6_bank_bus_we
107136     connect \Y $not$ls180.v:6044$1568_Y
107137   end
107138   attribute \src "ls180.v:6047.70-6047.101"
107139   cell $not $not$ls180.v:6047$1575
107140     parameter \A_SIGNED 0
107141     parameter \A_WIDTH 1
107142     parameter \Y_WIDTH 1
107143     connect \A \builder_interface6_bank_bus_we
107144     connect \Y $not$ls180.v:6047$1575_Y
107145   end
107146   attribute \src "ls180.v:6050.70-6050.101"
107147   cell $not $not$ls180.v:6050$1582
107148     parameter \A_SIGNED 0
107149     parameter \A_WIDTH 1
107150     parameter \Y_WIDTH 1
107151     connect \A \builder_interface6_bank_bus_we
107152     connect \Y $not$ls180.v:6050$1582_Y
107153   end
107154   attribute \src "ls180.v:6053.70-6053.101"
107155   cell $not $not$ls180.v:6053$1589
107156     parameter \A_SIGNED 0
107157     parameter \A_WIDTH 1
107158     parameter \Y_WIDTH 1
107159     connect \A \builder_interface6_bank_bus_we
107160     connect \Y $not$ls180.v:6053$1589_Y
107161   end
107162   attribute \src "ls180.v:6056.70-6056.101"
107163   cell $not $not$ls180.v:6056$1596
107164     parameter \A_SIGNED 0
107165     parameter \A_WIDTH 1
107166     parameter \Y_WIDTH 1
107167     connect \A \builder_interface6_bank_bus_we
107168     connect \Y $not$ls180.v:6056$1596_Y
107169   end
107170   attribute \src "ls180.v:6059.70-6059.101"
107171   cell $not $not$ls180.v:6059$1603
107172     parameter \A_SIGNED 0
107173     parameter \A_WIDTH 1
107174     parameter \Y_WIDTH 1
107175     connect \A \builder_interface6_bank_bus_we
107176     connect \Y $not$ls180.v:6059$1603_Y
107177   end
107178   attribute \src "ls180.v:6062.70-6062.101"
107179   cell $not $not$ls180.v:6062$1610
107180     parameter \A_SIGNED 0
107181     parameter \A_WIDTH 1
107182     parameter \Y_WIDTH 1
107183     connect \A \builder_interface6_bank_bus_we
107184     connect \Y $not$ls180.v:6062$1610_Y
107185   end
107186   attribute \src "ls180.v:6065.66-6065.97"
107187   cell $not $not$ls180.v:6065$1617
107188     parameter \A_SIGNED 0
107189     parameter \A_WIDTH 1
107190     parameter \Y_WIDTH 1
107191     connect \A \builder_interface6_bank_bus_we
107192     connect \Y $not$ls180.v:6065$1617_Y
107193   end
107194   attribute \src "ls180.v:6068.67-6068.98"
107195   cell $not $not$ls180.v:6068$1624
107196     parameter \A_SIGNED 0
107197     parameter \A_WIDTH 1
107198     parameter \Y_WIDTH 1
107199     connect \A \builder_interface6_bank_bus_we
107200     connect \Y $not$ls180.v:6068$1624_Y
107201   end
107202   attribute \src "ls180.v:6071.70-6071.101"
107203   cell $not $not$ls180.v:6071$1631
107204     parameter \A_SIGNED 0
107205     parameter \A_WIDTH 1
107206     parameter \Y_WIDTH 1
107207     connect \A \builder_interface6_bank_bus_we
107208     connect \Y $not$ls180.v:6071$1631_Y
107209   end
107210   attribute \src "ls180.v:6074.70-6074.101"
107211   cell $not $not$ls180.v:6074$1638
107212     parameter \A_SIGNED 0
107213     parameter \A_WIDTH 1
107214     parameter \Y_WIDTH 1
107215     connect \A \builder_interface6_bank_bus_we
107216     connect \Y $not$ls180.v:6074$1638_Y
107217   end
107218   attribute \src "ls180.v:6077.69-6077.100"
107219   cell $not $not$ls180.v:6077$1645
107220     parameter \A_SIGNED 0
107221     parameter \A_WIDTH 1
107222     parameter \Y_WIDTH 1
107223     connect \A \builder_interface6_bank_bus_we
107224     connect \Y $not$ls180.v:6077$1645_Y
107225   end
107226   attribute \src "ls180.v:6080.69-6080.100"
107227   cell $not $not$ls180.v:6080$1652
107228     parameter \A_SIGNED 0
107229     parameter \A_WIDTH 1
107230     parameter \Y_WIDTH 1
107231     connect \A \builder_interface6_bank_bus_we
107232     connect \Y $not$ls180.v:6080$1652_Y
107233   end
107234   attribute \src "ls180.v:6083.69-6083.100"
107235   cell $not $not$ls180.v:6083$1659
107236     parameter \A_SIGNED 0
107237     parameter \A_WIDTH 1
107238     parameter \Y_WIDTH 1
107239     connect \A \builder_interface6_bank_bus_we
107240     connect \Y $not$ls180.v:6083$1659_Y
107241   end
107242   attribute \src "ls180.v:6086.69-6086.100"
107243   cell $not $not$ls180.v:6086$1666
107244     parameter \A_SIGNED 0
107245     parameter \A_WIDTH 1
107246     parameter \Y_WIDTH 1
107247     connect \A \builder_interface6_bank_bus_we
107248     connect \Y $not$ls180.v:6086$1666_Y
107249   end
107250   attribute \src "ls180.v:6125.66-6125.97"
107251   cell $not $not$ls180.v:6125$1674
107252     parameter \A_SIGNED 0
107253     parameter \A_WIDTH 1
107254     parameter \Y_WIDTH 1
107255     connect \A \builder_interface7_bank_bus_we
107256     connect \Y $not$ls180.v:6125$1674_Y
107257   end
107258   attribute \src "ls180.v:6128.66-6128.97"
107259   cell $not $not$ls180.v:6128$1681
107260     parameter \A_SIGNED 0
107261     parameter \A_WIDTH 1
107262     parameter \Y_WIDTH 1
107263     connect \A \builder_interface7_bank_bus_we
107264     connect \Y $not$ls180.v:6128$1681_Y
107265   end
107266   attribute \src "ls180.v:6131.66-6131.97"
107267   cell $not $not$ls180.v:6131$1688
107268     parameter \A_SIGNED 0
107269     parameter \A_WIDTH 1
107270     parameter \Y_WIDTH 1
107271     connect \A \builder_interface7_bank_bus_we
107272     connect \Y $not$ls180.v:6131$1688_Y
107273   end
107274   attribute \src "ls180.v:6134.66-6134.97"
107275   cell $not $not$ls180.v:6134$1695
107276     parameter \A_SIGNED 0
107277     parameter \A_WIDTH 1
107278     parameter \Y_WIDTH 1
107279     connect \A \builder_interface7_bank_bus_we
107280     connect \Y $not$ls180.v:6134$1695_Y
107281   end
107282   attribute \src "ls180.v:6137.66-6137.97"
107283   cell $not $not$ls180.v:6137$1702
107284     parameter \A_SIGNED 0
107285     parameter \A_WIDTH 1
107286     parameter \Y_WIDTH 1
107287     connect \A \builder_interface7_bank_bus_we
107288     connect \Y $not$ls180.v:6137$1702_Y
107289   end
107290   attribute \src "ls180.v:6140.66-6140.97"
107291   cell $not $not$ls180.v:6140$1709
107292     parameter \A_SIGNED 0
107293     parameter \A_WIDTH 1
107294     parameter \Y_WIDTH 1
107295     connect \A \builder_interface7_bank_bus_we
107296     connect \Y $not$ls180.v:6140$1709_Y
107297   end
107298   attribute \src "ls180.v:6143.66-6143.97"
107299   cell $not $not$ls180.v:6143$1716
107300     parameter \A_SIGNED 0
107301     parameter \A_WIDTH 1
107302     parameter \Y_WIDTH 1
107303     connect \A \builder_interface7_bank_bus_we
107304     connect \Y $not$ls180.v:6143$1716_Y
107305   end
107306   attribute \src "ls180.v:6146.66-6146.97"
107307   cell $not $not$ls180.v:6146$1723
107308     parameter \A_SIGNED 0
107309     parameter \A_WIDTH 1
107310     parameter \Y_WIDTH 1
107311     connect \A \builder_interface7_bank_bus_we
107312     connect \Y $not$ls180.v:6146$1723_Y
107313   end
107314   attribute \src "ls180.v:6149.68-6149.99"
107315   cell $not $not$ls180.v:6149$1730
107316     parameter \A_SIGNED 0
107317     parameter \A_WIDTH 1
107318     parameter \Y_WIDTH 1
107319     connect \A \builder_interface7_bank_bus_we
107320     connect \Y $not$ls180.v:6149$1730_Y
107321   end
107322   attribute \src "ls180.v:6152.68-6152.99"
107323   cell $not $not$ls180.v:6152$1737
107324     parameter \A_SIGNED 0
107325     parameter \A_WIDTH 1
107326     parameter \Y_WIDTH 1
107327     connect \A \builder_interface7_bank_bus_we
107328     connect \Y $not$ls180.v:6152$1737_Y
107329   end
107330   attribute \src "ls180.v:6155.68-6155.99"
107331   cell $not $not$ls180.v:6155$1744
107332     parameter \A_SIGNED 0
107333     parameter \A_WIDTH 1
107334     parameter \Y_WIDTH 1
107335     connect \A \builder_interface7_bank_bus_we
107336     connect \Y $not$ls180.v:6155$1744_Y
107337   end
107338   attribute \src "ls180.v:6158.68-6158.99"
107339   cell $not $not$ls180.v:6158$1751
107340     parameter \A_SIGNED 0
107341     parameter \A_WIDTH 1
107342     parameter \Y_WIDTH 1
107343     connect \A \builder_interface7_bank_bus_we
107344     connect \Y $not$ls180.v:6158$1751_Y
107345   end
107346   attribute \src "ls180.v:6161.68-6161.99"
107347   cell $not $not$ls180.v:6161$1758
107348     parameter \A_SIGNED 0
107349     parameter \A_WIDTH 1
107350     parameter \Y_WIDTH 1
107351     connect \A \builder_interface7_bank_bus_we
107352     connect \Y $not$ls180.v:6161$1758_Y
107353   end
107354   attribute \src "ls180.v:6164.65-6164.96"
107355   cell $not $not$ls180.v:6164$1765
107356     parameter \A_SIGNED 0
107357     parameter \A_WIDTH 1
107358     parameter \Y_WIDTH 1
107359     connect \A \builder_interface7_bank_bus_we
107360     connect \Y $not$ls180.v:6164$1765_Y
107361   end
107362   attribute \src "ls180.v:6167.66-6167.97"
107363   cell $not $not$ls180.v:6167$1772
107364     parameter \A_SIGNED 0
107365     parameter \A_WIDTH 1
107366     parameter \Y_WIDTH 1
107367     connect \A \builder_interface7_bank_bus_we
107368     connect \Y $not$ls180.v:6167$1772_Y
107369   end
107370   attribute \src "ls180.v:6170.68-6170.99"
107371   cell $not $not$ls180.v:6170$1779
107372     parameter \A_SIGNED 0
107373     parameter \A_WIDTH 1
107374     parameter \Y_WIDTH 1
107375     connect \A \builder_interface7_bank_bus_we
107376     connect \Y $not$ls180.v:6170$1779_Y
107377   end
107378   attribute \src "ls180.v:6173.68-6173.99"
107379   cell $not $not$ls180.v:6173$1786
107380     parameter \A_SIGNED 0
107381     parameter \A_WIDTH 1
107382     parameter \Y_WIDTH 1
107383     connect \A \builder_interface7_bank_bus_we
107384     connect \Y $not$ls180.v:6173$1786_Y
107385   end
107386   attribute \src "ls180.v:6176.68-6176.99"
107387   cell $not $not$ls180.v:6176$1793
107388     parameter \A_SIGNED 0
107389     parameter \A_WIDTH 1
107390     parameter \Y_WIDTH 1
107391     connect \A \builder_interface7_bank_bus_we
107392     connect \Y $not$ls180.v:6176$1793_Y
107393   end
107394   attribute \src "ls180.v:6179.68-6179.99"
107395   cell $not $not$ls180.v:6179$1800
107396     parameter \A_SIGNED 0
107397     parameter \A_WIDTH 1
107398     parameter \Y_WIDTH 1
107399     connect \A \builder_interface7_bank_bus_we
107400     connect \Y $not$ls180.v:6179$1800_Y
107401   end
107402   attribute \src "ls180.v:6204.68-6204.99"
107403   cell $not $not$ls180.v:6204$1808
107404     parameter \A_SIGNED 0
107405     parameter \A_WIDTH 1
107406     parameter \Y_WIDTH 1
107407     connect \A \builder_interface8_bank_bus_we
107408     connect \Y $not$ls180.v:6204$1808_Y
107409   end
107410   attribute \src "ls180.v:6207.73-6207.104"
107411   cell $not $not$ls180.v:6207$1815
107412     parameter \A_SIGNED 0
107413     parameter \A_WIDTH 1
107414     parameter \Y_WIDTH 1
107415     connect \A \builder_interface8_bank_bus_we
107416     connect \Y $not$ls180.v:6207$1815_Y
107417   end
107418   attribute \src "ls180.v:6210.73-6210.104"
107419   cell $not $not$ls180.v:6210$1822
107420     parameter \A_SIGNED 0
107421     parameter \A_WIDTH 1
107422     parameter \Y_WIDTH 1
107423     connect \A \builder_interface8_bank_bus_we
107424     connect \Y $not$ls180.v:6210$1822_Y
107425   end
107426   attribute \src "ls180.v:6213.66-6213.97"
107427   cell $not $not$ls180.v:6213$1829
107428     parameter \A_SIGNED 0
107429     parameter \A_WIDTH 1
107430     parameter \Y_WIDTH 1
107431     connect \A \builder_interface8_bank_bus_we
107432     connect \Y $not$ls180.v:6213$1829_Y
107433   end
107434   attribute \src "ls180.v:6221.70-6221.101"
107435   cell $not $not$ls180.v:6221$1837
107436     parameter \A_SIGNED 0
107437     parameter \A_WIDTH 1
107438     parameter \Y_WIDTH 1
107439     connect \A \builder_interface9_bank_bus_we
107440     connect \Y $not$ls180.v:6221$1837_Y
107441   end
107442   attribute \src "ls180.v:6224.74-6224.105"
107443   cell $not $not$ls180.v:6224$1844
107444     parameter \A_SIGNED 0
107445     parameter \A_WIDTH 1
107446     parameter \Y_WIDTH 1
107447     connect \A \builder_interface9_bank_bus_we
107448     connect \Y $not$ls180.v:6224$1844_Y
107449   end
107450   attribute \src "ls180.v:6227.64-6227.95"
107451   cell $not $not$ls180.v:6227$1851
107452     parameter \A_SIGNED 0
107453     parameter \A_WIDTH 1
107454     parameter \Y_WIDTH 1
107455     connect \A \builder_interface9_bank_bus_we
107456     connect \Y $not$ls180.v:6227$1851_Y
107457   end
107458   attribute \src "ls180.v:6230.74-6230.105"
107459   cell $not $not$ls180.v:6230$1858
107460     parameter \A_SIGNED 0
107461     parameter \A_WIDTH 1
107462     parameter \Y_WIDTH 1
107463     connect \A \builder_interface9_bank_bus_we
107464     connect \Y $not$ls180.v:6230$1858_Y
107465   end
107466   attribute \src "ls180.v:6233.74-6233.105"
107467   cell $not $not$ls180.v:6233$1865
107468     parameter \A_SIGNED 0
107469     parameter \A_WIDTH 1
107470     parameter \Y_WIDTH 1
107471     connect \A \builder_interface9_bank_bus_we
107472     connect \Y $not$ls180.v:6233$1865_Y
107473   end
107474   attribute \src "ls180.v:6236.75-6236.106"
107475   cell $not $not$ls180.v:6236$1872
107476     parameter \A_SIGNED 0
107477     parameter \A_WIDTH 1
107478     parameter \Y_WIDTH 1
107479     connect \A \builder_interface9_bank_bus_we
107480     connect \Y $not$ls180.v:6236$1872_Y
107481   end
107482   attribute \src "ls180.v:6239.73-6239.104"
107483   cell $not $not$ls180.v:6239$1879
107484     parameter \A_SIGNED 0
107485     parameter \A_WIDTH 1
107486     parameter \Y_WIDTH 1
107487     connect \A \builder_interface9_bank_bus_we
107488     connect \Y $not$ls180.v:6239$1879_Y
107489   end
107490   attribute \src "ls180.v:6242.73-6242.104"
107491   cell $not $not$ls180.v:6242$1886
107492     parameter \A_SIGNED 0
107493     parameter \A_WIDTH 1
107494     parameter \Y_WIDTH 1
107495     connect \A \builder_interface9_bank_bus_we
107496     connect \Y $not$ls180.v:6242$1886_Y
107497   end
107498   attribute \src "ls180.v:6245.73-6245.104"
107499   cell $not $not$ls180.v:6245$1893
107500     parameter \A_SIGNED 0
107501     parameter \A_WIDTH 1
107502     parameter \Y_WIDTH 1
107503     connect \A \builder_interface9_bank_bus_we
107504     connect \Y $not$ls180.v:6245$1893_Y
107505   end
107506   attribute \src "ls180.v:6248.73-6248.104"
107507   cell $not $not$ls180.v:6248$1900
107508     parameter \A_SIGNED 0
107509     parameter \A_WIDTH 1
107510     parameter \Y_WIDTH 1
107511     connect \A \builder_interface9_bank_bus_we
107512     connect \Y $not$ls180.v:6248$1900_Y
107513   end
107514   attribute \src "ls180.v:6266.67-6266.99"
107515   cell $not $not$ls180.v:6266$1908
107516     parameter \A_SIGNED 0
107517     parameter \A_WIDTH 1
107518     parameter \Y_WIDTH 1
107519     connect \A \builder_interface10_bank_bus_we
107520     connect \Y $not$ls180.v:6266$1908_Y
107521   end
107522   attribute \src "ls180.v:6269.67-6269.99"
107523   cell $not $not$ls180.v:6269$1915
107524     parameter \A_SIGNED 0
107525     parameter \A_WIDTH 1
107526     parameter \Y_WIDTH 1
107527     connect \A \builder_interface10_bank_bus_we
107528     connect \Y $not$ls180.v:6269$1915_Y
107529   end
107530   attribute \src "ls180.v:6272.65-6272.97"
107531   cell $not $not$ls180.v:6272$1922
107532     parameter \A_SIGNED 0
107533     parameter \A_WIDTH 1
107534     parameter \Y_WIDTH 1
107535     connect \A \builder_interface10_bank_bus_we
107536     connect \Y $not$ls180.v:6272$1922_Y
107537   end
107538   attribute \src "ls180.v:6275.64-6275.96"
107539   cell $not $not$ls180.v:6275$1929
107540     parameter \A_SIGNED 0
107541     parameter \A_WIDTH 1
107542     parameter \Y_WIDTH 1
107543     connect \A \builder_interface10_bank_bus_we
107544     connect \Y $not$ls180.v:6275$1929_Y
107545   end
107546   attribute \src "ls180.v:6278.63-6278.95"
107547   cell $not $not$ls180.v:6278$1936
107548     parameter \A_SIGNED 0
107549     parameter \A_WIDTH 1
107550     parameter \Y_WIDTH 1
107551     connect \A \builder_interface10_bank_bus_we
107552     connect \Y $not$ls180.v:6278$1936_Y
107553   end
107554   attribute \src "ls180.v:6281.62-6281.94"
107555   cell $not $not$ls180.v:6281$1943
107556     parameter \A_SIGNED 0
107557     parameter \A_WIDTH 1
107558     parameter \Y_WIDTH 1
107559     connect \A \builder_interface10_bank_bus_we
107560     connect \Y $not$ls180.v:6281$1943_Y
107561   end
107562   attribute \src "ls180.v:6284.68-6284.100"
107563   cell $not $not$ls180.v:6284$1950
107564     parameter \A_SIGNED 0
107565     parameter \A_WIDTH 1
107566     parameter \Y_WIDTH 1
107567     connect \A \builder_interface10_bank_bus_we
107568     connect \Y $not$ls180.v:6284$1950_Y
107569   end
107570   attribute \src "ls180.v:6306.67-6306.99"
107571   cell $not $not$ls180.v:6306$1959
107572     parameter \A_SIGNED 0
107573     parameter \A_WIDTH 1
107574     parameter \Y_WIDTH 1
107575     connect \A \builder_interface11_bank_bus_we
107576     connect \Y $not$ls180.v:6306$1959_Y
107577   end
107578   attribute \src "ls180.v:6309.67-6309.99"
107579   cell $not $not$ls180.v:6309$1966
107580     parameter \A_SIGNED 0
107581     parameter \A_WIDTH 1
107582     parameter \Y_WIDTH 1
107583     connect \A \builder_interface11_bank_bus_we
107584     connect \Y $not$ls180.v:6309$1966_Y
107585   end
107586   attribute \src "ls180.v:6312.65-6312.97"
107587   cell $not $not$ls180.v:6312$1973
107588     parameter \A_SIGNED 0
107589     parameter \A_WIDTH 1
107590     parameter \Y_WIDTH 1
107591     connect \A \builder_interface11_bank_bus_we
107592     connect \Y $not$ls180.v:6312$1973_Y
107593   end
107594   attribute \src "ls180.v:6315.64-6315.96"
107595   cell $not $not$ls180.v:6315$1980
107596     parameter \A_SIGNED 0
107597     parameter \A_WIDTH 1
107598     parameter \Y_WIDTH 1
107599     connect \A \builder_interface11_bank_bus_we
107600     connect \Y $not$ls180.v:6315$1980_Y
107601   end
107602   attribute \src "ls180.v:6318.63-6318.95"
107603   cell $not $not$ls180.v:6318$1987
107604     parameter \A_SIGNED 0
107605     parameter \A_WIDTH 1
107606     parameter \Y_WIDTH 1
107607     connect \A \builder_interface11_bank_bus_we
107608     connect \Y $not$ls180.v:6318$1987_Y
107609   end
107610   attribute \src "ls180.v:6321.62-6321.94"
107611   cell $not $not$ls180.v:6321$1994
107612     parameter \A_SIGNED 0
107613     parameter \A_WIDTH 1
107614     parameter \Y_WIDTH 1
107615     connect \A \builder_interface11_bank_bus_we
107616     connect \Y $not$ls180.v:6321$1994_Y
107617   end
107618   attribute \src "ls180.v:6324.68-6324.100"
107619   cell $not $not$ls180.v:6324$2001
107620     parameter \A_SIGNED 0
107621     parameter \A_WIDTH 1
107622     parameter \Y_WIDTH 1
107623     connect \A \builder_interface11_bank_bus_we
107624     connect \Y $not$ls180.v:6324$2001_Y
107625   end
107626   attribute \src "ls180.v:6327.71-6327.103"
107627   cell $not $not$ls180.v:6327$2008
107628     parameter \A_SIGNED 0
107629     parameter \A_WIDTH 1
107630     parameter \Y_WIDTH 1
107631     connect \A \builder_interface11_bank_bus_we
107632     connect \Y $not$ls180.v:6327$2008_Y
107633   end
107634   attribute \src "ls180.v:6330.71-6330.103"
107635   cell $not $not$ls180.v:6330$2015
107636     parameter \A_SIGNED 0
107637     parameter \A_WIDTH 1
107638     parameter \Y_WIDTH 1
107639     connect \A \builder_interface11_bank_bus_we
107640     connect \Y $not$ls180.v:6330$2015_Y
107641   end
107642   attribute \src "ls180.v:6354.64-6354.96"
107643   cell $not $not$ls180.v:6354$2024
107644     parameter \A_SIGNED 0
107645     parameter \A_WIDTH 1
107646     parameter \Y_WIDTH 1
107647     connect \A \builder_interface12_bank_bus_we
107648     connect \Y $not$ls180.v:6354$2024_Y
107649   end
107650   attribute \src "ls180.v:6357.64-6357.96"
107651   cell $not $not$ls180.v:6357$2031
107652     parameter \A_SIGNED 0
107653     parameter \A_WIDTH 1
107654     parameter \Y_WIDTH 1
107655     connect \A \builder_interface12_bank_bus_we
107656     connect \Y $not$ls180.v:6357$2031_Y
107657   end
107658   attribute \src "ls180.v:6360.64-6360.96"
107659   cell $not $not$ls180.v:6360$2038
107660     parameter \A_SIGNED 0
107661     parameter \A_WIDTH 1
107662     parameter \Y_WIDTH 1
107663     connect \A \builder_interface12_bank_bus_we
107664     connect \Y $not$ls180.v:6360$2038_Y
107665   end
107666   attribute \src "ls180.v:6363.64-6363.96"
107667   cell $not $not$ls180.v:6363$2045
107668     parameter \A_SIGNED 0
107669     parameter \A_WIDTH 1
107670     parameter \Y_WIDTH 1
107671     connect \A \builder_interface12_bank_bus_we
107672     connect \Y $not$ls180.v:6363$2045_Y
107673   end
107674   attribute \src "ls180.v:6366.66-6366.98"
107675   cell $not $not$ls180.v:6366$2052
107676     parameter \A_SIGNED 0
107677     parameter \A_WIDTH 1
107678     parameter \Y_WIDTH 1
107679     connect \A \builder_interface12_bank_bus_we
107680     connect \Y $not$ls180.v:6366$2052_Y
107681   end
107682   attribute \src "ls180.v:6369.66-6369.98"
107683   cell $not $not$ls180.v:6369$2059
107684     parameter \A_SIGNED 0
107685     parameter \A_WIDTH 1
107686     parameter \Y_WIDTH 1
107687     connect \A \builder_interface12_bank_bus_we
107688     connect \Y $not$ls180.v:6369$2059_Y
107689   end
107690   attribute \src "ls180.v:6372.66-6372.98"
107691   cell $not $not$ls180.v:6372$2066
107692     parameter \A_SIGNED 0
107693     parameter \A_WIDTH 1
107694     parameter \Y_WIDTH 1
107695     connect \A \builder_interface12_bank_bus_we
107696     connect \Y $not$ls180.v:6372$2066_Y
107697   end
107698   attribute \src "ls180.v:6375.66-6375.98"
107699   cell $not $not$ls180.v:6375$2073
107700     parameter \A_SIGNED 0
107701     parameter \A_WIDTH 1
107702     parameter \Y_WIDTH 1
107703     connect \A \builder_interface12_bank_bus_we
107704     connect \Y $not$ls180.v:6375$2073_Y
107705   end
107706   attribute \src "ls180.v:6378.62-6378.94"
107707   cell $not $not$ls180.v:6378$2080
107708     parameter \A_SIGNED 0
107709     parameter \A_WIDTH 1
107710     parameter \Y_WIDTH 1
107711     connect \A \builder_interface12_bank_bus_we
107712     connect \Y $not$ls180.v:6378$2080_Y
107713   end
107714   attribute \src "ls180.v:6381.72-6381.104"
107715   cell $not $not$ls180.v:6381$2087
107716     parameter \A_SIGNED 0
107717     parameter \A_WIDTH 1
107718     parameter \Y_WIDTH 1
107719     connect \A \builder_interface12_bank_bus_we
107720     connect \Y $not$ls180.v:6381$2087_Y
107721   end
107722   attribute \src "ls180.v:6384.65-6384.97"
107723   cell $not $not$ls180.v:6384$2094
107724     parameter \A_SIGNED 0
107725     parameter \A_WIDTH 1
107726     parameter \Y_WIDTH 1
107727     connect \A \builder_interface12_bank_bus_we
107728     connect \Y $not$ls180.v:6384$2094_Y
107729   end
107730   attribute \src "ls180.v:6387.65-6387.97"
107731   cell $not $not$ls180.v:6387$2101
107732     parameter \A_SIGNED 0
107733     parameter \A_WIDTH 1
107734     parameter \Y_WIDTH 1
107735     connect \A \builder_interface12_bank_bus_we
107736     connect \Y $not$ls180.v:6387$2101_Y
107737   end
107738   attribute \src "ls180.v:6390.65-6390.97"
107739   cell $not $not$ls180.v:6390$2108
107740     parameter \A_SIGNED 0
107741     parameter \A_WIDTH 1
107742     parameter \Y_WIDTH 1
107743     connect \A \builder_interface12_bank_bus_we
107744     connect \Y $not$ls180.v:6390$2108_Y
107745   end
107746   attribute \src "ls180.v:6393.65-6393.97"
107747   cell $not $not$ls180.v:6393$2115
107748     parameter \A_SIGNED 0
107749     parameter \A_WIDTH 1
107750     parameter \Y_WIDTH 1
107751     connect \A \builder_interface12_bank_bus_we
107752     connect \Y $not$ls180.v:6393$2115_Y
107753   end
107754   attribute \src "ls180.v:6396.77-6396.109"
107755   cell $not $not$ls180.v:6396$2122
107756     parameter \A_SIGNED 0
107757     parameter \A_WIDTH 1
107758     parameter \Y_WIDTH 1
107759     connect \A \builder_interface12_bank_bus_we
107760     connect \Y $not$ls180.v:6396$2122_Y
107761   end
107762   attribute \src "ls180.v:6399.78-6399.110"
107763   cell $not $not$ls180.v:6399$2129
107764     parameter \A_SIGNED 0
107765     parameter \A_WIDTH 1
107766     parameter \Y_WIDTH 1
107767     connect \A \builder_interface12_bank_bus_we
107768     connect \Y $not$ls180.v:6399$2129_Y
107769   end
107770   attribute \src "ls180.v:6402.69-6402.101"
107771   cell $not $not$ls180.v:6402$2136
107772     parameter \A_SIGNED 0
107773     parameter \A_WIDTH 1
107774     parameter \Y_WIDTH 1
107775     connect \A \builder_interface12_bank_bus_we
107776     connect \Y $not$ls180.v:6402$2136_Y
107777   end
107778   attribute \src "ls180.v:6422.55-6422.87"
107779   cell $not $not$ls180.v:6422$2144
107780     parameter \A_SIGNED 0
107781     parameter \A_WIDTH 1
107782     parameter \Y_WIDTH 1
107783     connect \A \builder_interface13_bank_bus_we
107784     connect \Y $not$ls180.v:6422$2144_Y
107785   end
107786   attribute \src "ls180.v:6425.65-6425.97"
107787   cell $not $not$ls180.v:6425$2151
107788     parameter \A_SIGNED 0
107789     parameter \A_WIDTH 1
107790     parameter \Y_WIDTH 1
107791     connect \A \builder_interface13_bank_bus_we
107792     connect \Y $not$ls180.v:6425$2151_Y
107793   end
107794   attribute \src "ls180.v:6428.66-6428.98"
107795   cell $not $not$ls180.v:6428$2158
107796     parameter \A_SIGNED 0
107797     parameter \A_WIDTH 1
107798     parameter \Y_WIDTH 1
107799     connect \A \builder_interface13_bank_bus_we
107800     connect \Y $not$ls180.v:6428$2158_Y
107801   end
107802   attribute \src "ls180.v:6431.70-6431.102"
107803   cell $not $not$ls180.v:6431$2165
107804     parameter \A_SIGNED 0
107805     parameter \A_WIDTH 1
107806     parameter \Y_WIDTH 1
107807     connect \A \builder_interface13_bank_bus_we
107808     connect \Y $not$ls180.v:6431$2165_Y
107809   end
107810   attribute \src "ls180.v:6434.71-6434.103"
107811   cell $not $not$ls180.v:6434$2172
107812     parameter \A_SIGNED 0
107813     parameter \A_WIDTH 1
107814     parameter \Y_WIDTH 1
107815     connect \A \builder_interface13_bank_bus_we
107816     connect \Y $not$ls180.v:6434$2172_Y
107817   end
107818   attribute \src "ls180.v:6437.69-6437.101"
107819   cell $not $not$ls180.v:6437$2179
107820     parameter \A_SIGNED 0
107821     parameter \A_WIDTH 1
107822     parameter \Y_WIDTH 1
107823     connect \A \builder_interface13_bank_bus_we
107824     connect \Y $not$ls180.v:6437$2179_Y
107825   end
107826   attribute \src "ls180.v:6440.66-6440.98"
107827   cell $not $not$ls180.v:6440$2186
107828     parameter \A_SIGNED 0
107829     parameter \A_WIDTH 1
107830     parameter \Y_WIDTH 1
107831     connect \A \builder_interface13_bank_bus_we
107832     connect \Y $not$ls180.v:6440$2186_Y
107833   end
107834   attribute \src "ls180.v:6443.65-6443.97"
107835   cell $not $not$ls180.v:6443$2193
107836     parameter \A_SIGNED 0
107837     parameter \A_WIDTH 1
107838     parameter \Y_WIDTH 1
107839     connect \A \builder_interface13_bank_bus_we
107840     connect \Y $not$ls180.v:6443$2193_Y
107841   end
107842   attribute \src "ls180.v:6456.71-6456.103"
107843   cell $not $not$ls180.v:6456$2201
107844     parameter \A_SIGNED 0
107845     parameter \A_WIDTH 1
107846     parameter \Y_WIDTH 1
107847     connect \A \builder_interface14_bank_bus_we
107848     connect \Y $not$ls180.v:6456$2201_Y
107849   end
107850   attribute \src "ls180.v:6459.71-6459.103"
107851   cell $not $not$ls180.v:6459$2208
107852     parameter \A_SIGNED 0
107853     parameter \A_WIDTH 1
107854     parameter \Y_WIDTH 1
107855     connect \A \builder_interface14_bank_bus_we
107856     connect \Y $not$ls180.v:6459$2208_Y
107857   end
107858   attribute \src "ls180.v:6462.71-6462.103"
107859   cell $not $not$ls180.v:6462$2215
107860     parameter \A_SIGNED 0
107861     parameter \A_WIDTH 1
107862     parameter \Y_WIDTH 1
107863     connect \A \builder_interface14_bank_bus_we
107864     connect \Y $not$ls180.v:6462$2215_Y
107865   end
107866   attribute \src "ls180.v:6465.71-6465.103"
107867   cell $not $not$ls180.v:6465$2222
107868     parameter \A_SIGNED 0
107869     parameter \A_WIDTH 1
107870     parameter \Y_WIDTH 1
107871     connect \A \builder_interface14_bank_bus_we
107872     connect \Y $not$ls180.v:6465$2222_Y
107873   end
107874   attribute \src "ls180.v:6846.86-6846.330"
107875   cell $not $not$ls180.v:6846$2271
107876     parameter \A_SIGNED 0
107877     parameter \A_WIDTH 1
107878     parameter \Y_WIDTH 1
107879     connect \A $or$ls180.v:6846$2270_Y
107880     connect \Y $not$ls180.v:6846$2271_Y
107881   end
107882   attribute \src "ls180.v:6870.86-6870.330"
107883   cell $not $not$ls180.v:6870$2287
107884     parameter \A_SIGNED 0
107885     parameter \A_WIDTH 1
107886     parameter \Y_WIDTH 1
107887     connect \A $or$ls180.v:6870$2286_Y
107888     connect \Y $not$ls180.v:6870$2287_Y
107889   end
107890   attribute \src "ls180.v:6894.86-6894.330"
107891   cell $not $not$ls180.v:6894$2303
107892     parameter \A_SIGNED 0
107893     parameter \A_WIDTH 1
107894     parameter \Y_WIDTH 1
107895     connect \A $or$ls180.v:6894$2302_Y
107896     connect \Y $not$ls180.v:6894$2303_Y
107897   end
107898   attribute \src "ls180.v:6918.86-6918.330"
107899   cell $not $not$ls180.v:6918$2319
107900     parameter \A_SIGNED 0
107901     parameter \A_WIDTH 1
107902     parameter \Y_WIDTH 1
107903     connect \A $or$ls180.v:6918$2318_Y
107904     connect \Y $not$ls180.v:6918$2319_Y
107905   end
107906   attribute \src "ls180.v:7416.18-7416.42"
107907   cell $not $not$ls180.v:7416$2372
107908     parameter \A_SIGNED 0
107909     parameter \A_WIDTH 1
107910     parameter \Y_WIDTH 1
107911     connect \A \main_sdphy_clocker_clk0
107912     connect \Y $not$ls180.v:7416$2372_Y
107913   end
107914   attribute \src "ls180.v:7507.72-7507.101"
107915   cell $not $not$ls180.v:7507$2417
107916     parameter \A_SIGNED 0
107917     parameter \A_WIDTH 1
107918     parameter \Y_WIDTH 1
107919     connect \A \main_libresocsim_ram_bus_ack
107920     connect \Y $not$ls180.v:7507$2417_Y
107921   end
107922   attribute \src "ls180.v:7526.8-7526.38"
107923   cell $not $not$ls180.v:7526$2421
107924     parameter \A_SIGNED 0
107925     parameter \A_WIDTH 1
107926     parameter \Y_WIDTH 1
107927     connect \A \main_libresocsim_zero_trigger
107928     connect \Y $not$ls180.v:7526$2421_Y
107929   end
107930   attribute \src "ls180.v:7534.32-7534.55"
107931   cell $not $not$ls180.v:7534$2423
107932     parameter \A_SIGNED 0
107933     parameter \A_WIDTH 1
107934     parameter \Y_WIDTH 1
107935     connect \A \main_sdram_timer_done0
107936     connect \Y $not$ls180.v:7534$2423_Y
107937   end
107938   attribute \src "ls180.v:7604.136-7604.189"
107939   cell $not $not$ls180.v:7604$2438
107940     parameter \A_SIGNED 0
107941     parameter \A_WIDTH 1
107942     parameter \Y_WIDTH 1
107943     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
107944     connect \Y $not$ls180.v:7604$2438_Y
107945   end
107946   attribute \src "ls180.v:7610.136-7610.189"
107947   cell $not $not$ls180.v:7610$2443
107948     parameter \A_SIGNED 0
107949     parameter \A_WIDTH 1
107950     parameter \Y_WIDTH 1
107951     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
107952     connect \Y $not$ls180.v:7610$2443_Y
107953   end
107954   attribute \src "ls180.v:7611.8-7611.61"
107955   cell $not $not$ls180.v:7611$2445
107956     parameter \A_SIGNED 0
107957     parameter \A_WIDTH 1
107958     parameter \Y_WIDTH 1
107959     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
107960     connect \Y $not$ls180.v:7611$2445_Y
107961   end
107962   attribute \src "ls180.v:7619.8-7619.56"
107963   cell $not $not$ls180.v:7619$2448
107964     parameter \A_SIGNED 0
107965     parameter \A_WIDTH 1
107966     parameter \Y_WIDTH 1
107967     connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid
107968     connect \Y $not$ls180.v:7619$2448_Y
107969   end
107970   attribute \src "ls180.v:7634.8-7634.46"
107971   cell $not $not$ls180.v:7634$2450
107972     parameter \A_SIGNED 0
107973     parameter \A_WIDTH 1
107974     parameter \Y_WIDTH 1
107975     connect \A \main_sdram_bankmachine0_twtpcon_ready
107976     connect \Y $not$ls180.v:7634$2450_Y
107977   end
107978   attribute \src "ls180.v:7650.136-7650.189"
107979   cell $not $not$ls180.v:7650$2454
107980     parameter \A_SIGNED 0
107981     parameter \A_WIDTH 1
107982     parameter \Y_WIDTH 1
107983     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
107984     connect \Y $not$ls180.v:7650$2454_Y
107985   end
107986   attribute \src "ls180.v:7656.136-7656.189"
107987   cell $not $not$ls180.v:7656$2459
107988     parameter \A_SIGNED 0
107989     parameter \A_WIDTH 1
107990     parameter \Y_WIDTH 1
107991     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
107992     connect \Y $not$ls180.v:7656$2459_Y
107993   end
107994   attribute \src "ls180.v:7657.8-7657.61"
107995   cell $not $not$ls180.v:7657$2461
107996     parameter \A_SIGNED 0
107997     parameter \A_WIDTH 1
107998     parameter \Y_WIDTH 1
107999     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
108000     connect \Y $not$ls180.v:7657$2461_Y
108001   end
108002   attribute \src "ls180.v:7665.8-7665.56"
108003   cell $not $not$ls180.v:7665$2464
108004     parameter \A_SIGNED 0
108005     parameter \A_WIDTH 1
108006     parameter \Y_WIDTH 1
108007     connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid
108008     connect \Y $not$ls180.v:7665$2464_Y
108009   end
108010   attribute \src "ls180.v:7680.8-7680.46"
108011   cell $not $not$ls180.v:7680$2466
108012     parameter \A_SIGNED 0
108013     parameter \A_WIDTH 1
108014     parameter \Y_WIDTH 1
108015     connect \A \main_sdram_bankmachine1_twtpcon_ready
108016     connect \Y $not$ls180.v:7680$2466_Y
108017   end
108018   attribute \src "ls180.v:7696.136-7696.189"
108019   cell $not $not$ls180.v:7696$2470
108020     parameter \A_SIGNED 0
108021     parameter \A_WIDTH 1
108022     parameter \Y_WIDTH 1
108023     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
108024     connect \Y $not$ls180.v:7696$2470_Y
108025   end
108026   attribute \src "ls180.v:7702.136-7702.189"
108027   cell $not $not$ls180.v:7702$2475
108028     parameter \A_SIGNED 0
108029     parameter \A_WIDTH 1
108030     parameter \Y_WIDTH 1
108031     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
108032     connect \Y $not$ls180.v:7702$2475_Y
108033   end
108034   attribute \src "ls180.v:7703.8-7703.61"
108035   cell $not $not$ls180.v:7703$2477
108036     parameter \A_SIGNED 0
108037     parameter \A_WIDTH 1
108038     parameter \Y_WIDTH 1
108039     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
108040     connect \Y $not$ls180.v:7703$2477_Y
108041   end
108042   attribute \src "ls180.v:7711.8-7711.56"
108043   cell $not $not$ls180.v:7711$2480
108044     parameter \A_SIGNED 0
108045     parameter \A_WIDTH 1
108046     parameter \Y_WIDTH 1
108047     connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid
108048     connect \Y $not$ls180.v:7711$2480_Y
108049   end
108050   attribute \src "ls180.v:7726.8-7726.46"
108051   cell $not $not$ls180.v:7726$2482
108052     parameter \A_SIGNED 0
108053     parameter \A_WIDTH 1
108054     parameter \Y_WIDTH 1
108055     connect \A \main_sdram_bankmachine2_twtpcon_ready
108056     connect \Y $not$ls180.v:7726$2482_Y
108057   end
108058   attribute \src "ls180.v:7742.136-7742.189"
108059   cell $not $not$ls180.v:7742$2486
108060     parameter \A_SIGNED 0
108061     parameter \A_WIDTH 1
108062     parameter \Y_WIDTH 1
108063     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
108064     connect \Y $not$ls180.v:7742$2486_Y
108065   end
108066   attribute \src "ls180.v:7748.136-7748.189"
108067   cell $not $not$ls180.v:7748$2491
108068     parameter \A_SIGNED 0
108069     parameter \A_WIDTH 1
108070     parameter \Y_WIDTH 1
108071     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
108072     connect \Y $not$ls180.v:7748$2491_Y
108073   end
108074   attribute \src "ls180.v:7749.8-7749.61"
108075   cell $not $not$ls180.v:7749$2493
108076     parameter \A_SIGNED 0
108077     parameter \A_WIDTH 1
108078     parameter \Y_WIDTH 1
108079     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
108080     connect \Y $not$ls180.v:7749$2493_Y
108081   end
108082   attribute \src "ls180.v:7757.8-7757.56"
108083   cell $not $not$ls180.v:7757$2496
108084     parameter \A_SIGNED 0
108085     parameter \A_WIDTH 1
108086     parameter \Y_WIDTH 1
108087     connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid
108088     connect \Y $not$ls180.v:7757$2496_Y
108089   end
108090   attribute \src "ls180.v:7772.8-7772.46"
108091   cell $not $not$ls180.v:7772$2498
108092     parameter \A_SIGNED 0
108093     parameter \A_WIDTH 1
108094     parameter \Y_WIDTH 1
108095     connect \A \main_sdram_bankmachine3_twtpcon_ready
108096     connect \Y $not$ls180.v:7772$2498_Y
108097   end
108098   attribute \src "ls180.v:7780.7-7780.22"
108099   cell $not $not$ls180.v:7780$2501
108100     parameter \A_SIGNED 0
108101     parameter \A_WIDTH 1
108102     parameter \Y_WIDTH 1
108103     connect \A \main_sdram_en0
108104     connect \Y $not$ls180.v:7780$2501_Y
108105   end
108106   attribute \src "ls180.v:7783.8-7783.29"
108107   cell $not $not$ls180.v:7783$2502
108108     parameter \A_SIGNED 0
108109     parameter \A_WIDTH 1
108110     parameter \Y_WIDTH 1
108111     connect \A \main_sdram_max_time0
108112     connect \Y $not$ls180.v:7783$2502_Y
108113   end
108114   attribute \src "ls180.v:7787.7-7787.22"
108115   cell $not $not$ls180.v:7787$2504
108116     parameter \A_SIGNED 0
108117     parameter \A_WIDTH 1
108118     parameter \Y_WIDTH 1
108119     connect \A \main_sdram_en1
108120     connect \Y $not$ls180.v:7787$2504_Y
108121   end
108122   attribute \src "ls180.v:7790.8-7790.29"
108123   cell $not $not$ls180.v:7790$2505
108124     parameter \A_SIGNED 0
108125     parameter \A_WIDTH 1
108126     parameter \Y_WIDTH 1
108127     connect \A \main_sdram_max_time1
108128     connect \Y $not$ls180.v:7790$2505_Y
108129   end
108130   attribute \src "ls180.v:7909.30-7909.60"
108131   cell $not $not$ls180.v:7909$2507
108132     parameter \A_SIGNED 0
108133     parameter \A_WIDTH 1
108134     parameter \Y_WIDTH 1
108135     connect \A \builder_sync_rhs_array_muxed2
108136     connect \Y $not$ls180.v:7909$2507_Y
108137   end
108138   attribute \src "ls180.v:7910.30-7910.60"
108139   cell $not $not$ls180.v:7910$2508
108140     parameter \A_SIGNED 0
108141     parameter \A_WIDTH 1
108142     parameter \Y_WIDTH 1
108143     connect \A \builder_sync_rhs_array_muxed3
108144     connect \Y $not$ls180.v:7910$2508_Y
108145   end
108146   attribute \src "ls180.v:7911.29-7911.59"
108147   cell $not $not$ls180.v:7911$2509
108148     parameter \A_SIGNED 0
108149     parameter \A_WIDTH 1
108150     parameter \Y_WIDTH 1
108151     connect \A \builder_sync_rhs_array_muxed4
108152     connect \Y $not$ls180.v:7911$2509_Y
108153   end
108154   attribute \src "ls180.v:7922.8-7922.33"
108155   cell $not $not$ls180.v:7922$2510
108156     parameter \A_SIGNED 0
108157     parameter \A_WIDTH 1
108158     parameter \Y_WIDTH 1
108159     connect \A \main_sdram_tccdcon_ready
108160     connect \Y $not$ls180.v:7922$2510_Y
108161   end
108162   attribute \src "ls180.v:7937.8-7937.33"
108163   cell $not $not$ls180.v:7937$2513
108164     parameter \A_SIGNED 0
108165     parameter \A_WIDTH 1
108166     parameter \Y_WIDTH 1
108167     connect \A \main_sdram_twtrcon_ready
108168     connect \Y $not$ls180.v:7937$2513_Y
108169   end
108170   attribute \src "ls180.v:7973.36-7973.58"
108171   cell $not $not$ls180.v:7973$2543
108172     parameter \A_SIGNED 0
108173     parameter \A_WIDTH 1
108174     parameter \Y_WIDTH 1
108175     connect \A \main_uart_phy_tx_busy
108176     connect \Y $not$ls180.v:7973$2543_Y
108177   end
108178   attribute \src "ls180.v:7973.64-7973.89"
108179   cell $not $not$ls180.v:7973$2545
108180     parameter \A_SIGNED 0
108181     parameter \A_WIDTH 1
108182     parameter \Y_WIDTH 1
108183     connect \A \main_uart_phy_sink_ready
108184     connect \Y $not$ls180.v:7973$2545_Y
108185   end
108186   attribute \src "ls180.v:8002.7-8002.29"
108187   cell $not $not$ls180.v:8002$2552
108188     parameter \A_SIGNED 0
108189     parameter \A_WIDTH 1
108190     parameter \Y_WIDTH 1
108191     connect \A \main_uart_phy_rx_busy
108192     connect \Y $not$ls180.v:8002$2552_Y
108193   end
108194   attribute \src "ls180.v:8003.9-8003.26"
108195   cell $not $not$ls180.v:8003$2553
108196     parameter \A_SIGNED 0
108197     parameter \A_WIDTH 1
108198     parameter \Y_WIDTH 1
108199     connect \A \main_uart_phy_rx
108200     connect \Y $not$ls180.v:8003$2553_Y
108201   end
108202   attribute \src "ls180.v:8036.8-8036.29"
108203   cell $not $not$ls180.v:8036$2559
108204     parameter \A_SIGNED 0
108205     parameter \A_WIDTH 1
108206     parameter \Y_WIDTH 1
108207     connect \A \main_uart_tx_trigger
108208     connect \Y $not$ls180.v:8036$2559_Y
108209   end
108210   attribute \src "ls180.v:8043.8-8043.29"
108211   cell $not $not$ls180.v:8043$2561
108212     parameter \A_SIGNED 0
108213     parameter \A_WIDTH 1
108214     parameter \Y_WIDTH 1
108215     connect \A \main_uart_rx_trigger
108216     connect \Y $not$ls180.v:8043$2561_Y
108217   end
108218   attribute \src "ls180.v:8053.80-8053.106"
108219   cell $not $not$ls180.v:8053$2564
108220     parameter \A_SIGNED 0
108221     parameter \A_WIDTH 1
108222     parameter \Y_WIDTH 1
108223     connect \A \main_uart_tx_fifo_replace
108224     connect \Y $not$ls180.v:8053$2564_Y
108225   end
108226   attribute \src "ls180.v:8059.80-8059.106"
108227   cell $not $not$ls180.v:8059$2569
108228     parameter \A_SIGNED 0
108229     parameter \A_WIDTH 1
108230     parameter \Y_WIDTH 1
108231     connect \A \main_uart_tx_fifo_replace
108232     connect \Y $not$ls180.v:8059$2569_Y
108233   end
108234   attribute \src "ls180.v:8060.8-8060.34"
108235   cell $not $not$ls180.v:8060$2571
108236     parameter \A_SIGNED 0
108237     parameter \A_WIDTH 1
108238     parameter \Y_WIDTH 1
108239     connect \A \main_uart_tx_fifo_do_read
108240     connect \Y $not$ls180.v:8060$2571_Y
108241   end
108242   attribute \src "ls180.v:8075.80-8075.106"
108243   cell $not $not$ls180.v:8075$2575
108244     parameter \A_SIGNED 0
108245     parameter \A_WIDTH 1
108246     parameter \Y_WIDTH 1
108247     connect \A \main_uart_rx_fifo_replace
108248     connect \Y $not$ls180.v:8075$2575_Y
108249   end
108250   attribute \src "ls180.v:8081.80-8081.106"
108251   cell $not $not$ls180.v:8081$2580
108252     parameter \A_SIGNED 0
108253     parameter \A_WIDTH 1
108254     parameter \Y_WIDTH 1
108255     connect \A \main_uart_rx_fifo_replace
108256     connect \Y $not$ls180.v:8081$2580_Y
108257   end
108258   attribute \src "ls180.v:8082.8-8082.34"
108259   cell $not $not$ls180.v:8082$2582
108260     parameter \A_SIGNED 0
108261     parameter \A_WIDTH 1
108262     parameter \Y_WIDTH 1
108263     connect \A \main_uart_rx_fifo_do_read
108264     connect \Y $not$ls180.v:8082$2582_Y
108265   end
108266   attribute \src "ls180.v:8113.22-8113.41"
108267   cell $not $not$ls180.v:8113$2586
108268     parameter \A_SIGNED 0
108269     parameter \A_WIDTH 1
108270     parameter \Y_WIDTH 1
108271     connect \A \main_spimaster6_cs
108272     connect \Y $not$ls180.v:8113$2586_Y
108273   end
108274   attribute \src "ls180.v:8113.46-8113.73"
108275   cell $not $not$ls180.v:8113$2587
108276     parameter \A_SIGNED 0
108277     parameter \A_WIDTH 1
108278     parameter \Y_WIDTH 1
108279     connect \A \main_spimaster26_cs_enable
108280     connect \Y $not$ls180.v:8113$2587_Y
108281   end
108282   attribute \src "ls180.v:8148.22-8148.40"
108283   cell $not $not$ls180.v:8148$2591
108284     parameter \A_SIGNED 0
108285     parameter \A_WIDTH 1
108286     parameter \Y_WIDTH 1
108287     connect \A \main_spisdcard_cs
108288     connect \Y $not$ls180.v:8148$2591_Y
108289   end
108290   attribute \src "ls180.v:8148.45-8148.70"
108291   cell $not $not$ls180.v:8148$2592
108292     parameter \A_SIGNED 0
108293     parameter \A_WIDTH 1
108294     parameter \Y_WIDTH 1
108295     connect \A \main_spisdcard_cs_enable
108296     connect \Y $not$ls180.v:8148$2592_Y
108297   end
108298   attribute \src "ls180.v:8202.7-8202.31"
108299   cell $not $not$ls180.v:8202$2603
108300     parameter \A_SIGNED 0
108301     parameter \A_WIDTH 1
108302     parameter \Y_WIDTH 1
108303     connect \A \main_sdphy_clocker_stop
108304     connect \Y $not$ls180.v:8202$2603_Y
108305   end
108306   attribute \src "ls180.v:8274.8-8274.46"
108307   cell $not $not$ls180.v:8274$2615
108308     parameter \A_SIGNED 0
108309     parameter \A_WIDTH 1
108310     parameter \Y_WIDTH 1
108311     connect \A \main_sdphy_cmdr_cmdr_buf_source_valid
108312     connect \Y $not$ls180.v:8274$2615_Y
108313   end
108314   attribute \src "ls180.v:8355.8-8355.47"
108315   cell $not $not$ls180.v:8355$2627
108316     parameter \A_SIGNED 0
108317     parameter \A_WIDTH 1
108318     parameter \Y_WIDTH 1
108319     connect \A \main_sdphy_dataw_crcr_buf_source_valid
108320     connect \Y $not$ls180.v:8355$2627_Y
108321   end
108322   attribute \src "ls180.v:8416.8-8416.48"
108323   cell $not $not$ls180.v:8416$2639
108324     parameter \A_SIGNED 0
108325     parameter \A_WIDTH 1
108326     parameter \Y_WIDTH 1
108327     connect \A \main_sdphy_datar_datar_buf_source_valid
108328     connect \Y $not$ls180.v:8416$2639_Y
108329   end
108330   attribute \src "ls180.v:8586.88-8586.118"
108331   cell $not $not$ls180.v:8586$2653
108332     parameter \A_SIGNED 0
108333     parameter \A_WIDTH 1
108334     parameter \Y_WIDTH 1
108335     connect \A \main_sdblock2mem_fifo_replace
108336     connect \Y $not$ls180.v:8586$2653_Y
108337   end
108338   attribute \src "ls180.v:8592.88-8592.118"
108339   cell $not $not$ls180.v:8592$2658
108340     parameter \A_SIGNED 0
108341     parameter \A_WIDTH 1
108342     parameter \Y_WIDTH 1
108343     connect \A \main_sdblock2mem_fifo_replace
108344     connect \Y $not$ls180.v:8592$2658_Y
108345   end
108346   attribute \src "ls180.v:8593.8-8593.38"
108347   cell $not $not$ls180.v:8593$2660
108348     parameter \A_SIGNED 0
108349     parameter \A_WIDTH 1
108350     parameter \Y_WIDTH 1
108351     connect \A \main_sdblock2mem_fifo_do_read
108352     connect \Y $not$ls180.v:8593$2660_Y
108353   end
108354   attribute \src "ls180.v:8672.88-8672.118"
108355   cell $not $not$ls180.v:8672$2675
108356     parameter \A_SIGNED 0
108357     parameter \A_WIDTH 1
108358     parameter \Y_WIDTH 1
108359     connect \A \main_sdmem2block_fifo_replace
108360     connect \Y $not$ls180.v:8672$2675_Y
108361   end
108362   attribute \src "ls180.v:8678.88-8678.118"
108363   cell $not $not$ls180.v:8678$2680
108364     parameter \A_SIGNED 0
108365     parameter \A_WIDTH 1
108366     parameter \Y_WIDTH 1
108367     connect \A \main_sdmem2block_fifo_replace
108368     connect \Y $not$ls180.v:8678$2680_Y
108369   end
108370   attribute \src "ls180.v:8679.8-8679.38"
108371   cell $not $not$ls180.v:8679$2682
108372     parameter \A_SIGNED 0
108373     parameter \A_WIDTH 1
108374     parameter \Y_WIDTH 1
108375     connect \A \main_sdmem2block_fifo_do_read
108376     connect \Y $not$ls180.v:8679$2682_Y
108377   end
108378   attribute \src "ls180.v:8699.9-8699.28"
108379   cell $not $not$ls180.v:8699$2685
108380     parameter \A_SIGNED 0
108381     parameter \A_WIDTH 1
108382     parameter \Y_WIDTH 1
108383     connect \A \builder_request [0]
108384     connect \Y $not$ls180.v:8699$2685_Y
108385   end
108386   attribute \src "ls180.v:8718.9-8718.28"
108387   cell $not $not$ls180.v:8718$2686
108388     parameter \A_SIGNED 0
108389     parameter \A_WIDTH 1
108390     parameter \Y_WIDTH 1
108391     connect \A \builder_request [1]
108392     connect \Y $not$ls180.v:8718$2686_Y
108393   end
108394   attribute \src "ls180.v:8737.9-8737.28"
108395   cell $not $not$ls180.v:8737$2687
108396     parameter \A_SIGNED 0
108397     parameter \A_WIDTH 1
108398     parameter \Y_WIDTH 1
108399     connect \A \builder_request [2]
108400     connect \Y $not$ls180.v:8737$2687_Y
108401   end
108402   attribute \src "ls180.v:8756.9-8756.28"
108403   cell $not $not$ls180.v:8756$2688
108404     parameter \A_SIGNED 0
108405     parameter \A_WIDTH 1
108406     parameter \Y_WIDTH 1
108407     connect \A \builder_request [3]
108408     connect \Y $not$ls180.v:8756$2688_Y
108409   end
108410   attribute \src "ls180.v:8775.9-8775.28"
108411   cell $not $not$ls180.v:8775$2689
108412     parameter \A_SIGNED 0
108413     parameter \A_WIDTH 1
108414     parameter \Y_WIDTH 1
108415     connect \A \builder_request [4]
108416     connect \Y $not$ls180.v:8775$2689_Y
108417   end
108418   attribute \src "ls180.v:8796.8-8796.21"
108419   cell $not $not$ls180.v:8796$2690
108420     parameter \A_SIGNED 0
108421     parameter \A_WIDTH 1
108422     parameter \Y_WIDTH 1
108423     connect \A \builder_done
108424     connect \Y $not$ls180.v:8796$2690_Y
108425   end
108426   attribute \src "ls180.v:10295.8-10295.51"
108427   cell $or $or$ls180.v:10295$2762
108428     parameter \A_SIGNED 0
108429     parameter \A_WIDTH 1
108430     parameter \B_SIGNED 0
108431     parameter \B_WIDTH 1
108432     parameter \Y_WIDTH 1
108433     connect \A \sys_rst_1
108434     connect \B \main_libresocsim_libresoc_reset
108435     connect \Y $or$ls180.v:10295$2762_Y
108436   end
108437   attribute \src "ls180.v:2818.10-2818.96"
108438   cell $or $or$ls180.v:2818$21
108439     parameter \A_SIGNED 0
108440     parameter \A_WIDTH 1
108441     parameter \B_SIGNED 0
108442     parameter \B_WIDTH 1
108443     parameter \Y_WIDTH 1
108444     connect \A \main_libresocsim_interface0_converted_interface_ack
108445     connect \B \main_libresocsim_converter0_skip
108446     connect \Y $or$ls180.v:2818$21_Y
108447   end
108448   attribute \src "ls180.v:2878.10-2878.96"
108449   cell $or $or$ls180.v:2878$32
108450     parameter \A_SIGNED 0
108451     parameter \A_WIDTH 1
108452     parameter \B_SIGNED 0
108453     parameter \B_WIDTH 1
108454     parameter \Y_WIDTH 1
108455     connect \A \main_libresocsim_interface1_converted_interface_ack
108456     connect \B \main_libresocsim_converter1_skip
108457     connect \Y $or$ls180.v:2878$32_Y
108458   end
108459   attribute \src "ls180.v:2938.10-2938.96"
108460   cell $or $or$ls180.v:2938$43
108461     parameter \A_SIGNED 0
108462     parameter \A_WIDTH 1
108463     parameter \B_SIGNED 0
108464     parameter \B_WIDTH 1
108465     parameter \Y_WIDTH 1
108466     connect \A \main_libresocsim_interface2_converted_interface_ack
108467     connect \B \main_libresocsim_converter2_skip
108468     connect \Y $or$ls180.v:2938$43_Y
108469   end
108470   attribute \src "ls180.v:3130.39-3130.105"
108471   cell $or $or$ls180.v:3130$75
108472     parameter \A_SIGNED 0
108473     parameter \A_WIDTH 1
108474     parameter \B_SIGNED 0
108475     parameter \B_WIDTH 1
108476     parameter \Y_WIDTH 1
108477     connect \A \main_sdram_sequencer_start0
108478     connect \B $ne$ls180.v:3130$74_Y
108479     connect \Y $or$ls180.v:3130$75_Y
108480   end
108481   attribute \src "ls180.v:3173.59-3173.140"
108482   cell $or $or$ls180.v:3173$79
108483     parameter \A_SIGNED 0
108484     parameter \A_WIDTH 1
108485     parameter \B_SIGNED 0
108486     parameter \B_WIDTH 1
108487     parameter \Y_WIDTH 1
108488     connect \A \main_sdram_bankmachine0_req_wdata_ready
108489     connect \B \main_sdram_bankmachine0_req_rdata_valid
108490     connect \Y $or$ls180.v:3173$79_Y
108491   end
108492   attribute \src "ls180.v:3174.44-3174.151"
108493   cell $or $or$ls180.v:3174$80
108494     parameter \A_SIGNED 0
108495     parameter \A_WIDTH 1
108496     parameter \B_SIGNED 0
108497     parameter \B_WIDTH 1
108498     parameter \Y_WIDTH 1
108499     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
108500     connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid
108501     connect \Y $or$ls180.v:3174$80_Y
108502   end
108503   attribute \src "ls180.v:3182.45-3182.170"
108504   cell $or $or$ls180.v:3182$84
108505     parameter \A_SIGNED 0
108506     parameter \A_WIDTH 13
108507     parameter \B_SIGNED 0
108508     parameter \B_WIDTH 13
108509     parameter \Y_WIDTH 13
108510     connect \A $sshl$ls180.v:3182$83_Y
108511     connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] }
108512     connect \Y $or$ls180.v:3182$84_Y
108513   end
108514   attribute \src "ls180.v:3219.127-3219.245"
108515   cell $or $or$ls180.v:3219$97
108516     parameter \A_SIGNED 0
108517     parameter \A_WIDTH 1
108518     parameter \B_SIGNED 0
108519     parameter \B_WIDTH 1
108520     parameter \Y_WIDTH 1
108521     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
108522     connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
108523     connect \Y $or$ls180.v:3219$97_Y
108524   end
108525   attribute \src "ls180.v:3225.57-3225.157"
108526   cell $or $or$ls180.v:3225$103
108527     parameter \A_SIGNED 0
108528     parameter \A_WIDTH 1
108529     parameter \B_SIGNED 0
108530     parameter \B_WIDTH 1
108531     parameter \Y_WIDTH 1
108532     connect \A $not$ls180.v:3225$102_Y
108533     connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
108534     connect \Y $or$ls180.v:3225$103_Y
108535   end
108536   attribute \src "ls180.v:3330.59-3330.140"
108537   cell $or $or$ls180.v:3330$109
108538     parameter \A_SIGNED 0
108539     parameter \A_WIDTH 1
108540     parameter \B_SIGNED 0
108541     parameter \B_WIDTH 1
108542     parameter \Y_WIDTH 1
108543     connect \A \main_sdram_bankmachine1_req_wdata_ready
108544     connect \B \main_sdram_bankmachine1_req_rdata_valid
108545     connect \Y $or$ls180.v:3330$109_Y
108546   end
108547   attribute \src "ls180.v:3331.44-3331.151"
108548   cell $or $or$ls180.v:3331$110
108549     parameter \A_SIGNED 0
108550     parameter \A_WIDTH 1
108551     parameter \B_SIGNED 0
108552     parameter \B_WIDTH 1
108553     parameter \Y_WIDTH 1
108554     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
108555     connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid
108556     connect \Y $or$ls180.v:3331$110_Y
108557   end
108558   attribute \src "ls180.v:3339.45-3339.170"
108559   cell $or $or$ls180.v:3339$114
108560     parameter \A_SIGNED 0
108561     parameter \A_WIDTH 13
108562     parameter \B_SIGNED 0
108563     parameter \B_WIDTH 13
108564     parameter \Y_WIDTH 13
108565     connect \A $sshl$ls180.v:3339$113_Y
108566     connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] }
108567     connect \Y $or$ls180.v:3339$114_Y
108568   end
108569   attribute \src "ls180.v:3376.127-3376.245"
108570   cell $or $or$ls180.v:3376$127
108571     parameter \A_SIGNED 0
108572     parameter \A_WIDTH 1
108573     parameter \B_SIGNED 0
108574     parameter \B_WIDTH 1
108575     parameter \Y_WIDTH 1
108576     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
108577     connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
108578     connect \Y $or$ls180.v:3376$127_Y
108579   end
108580   attribute \src "ls180.v:3382.57-3382.157"
108581   cell $or $or$ls180.v:3382$133
108582     parameter \A_SIGNED 0
108583     parameter \A_WIDTH 1
108584     parameter \B_SIGNED 0
108585     parameter \B_WIDTH 1
108586     parameter \Y_WIDTH 1
108587     connect \A $not$ls180.v:3382$132_Y
108588     connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
108589     connect \Y $or$ls180.v:3382$133_Y
108590   end
108591   attribute \src "ls180.v:3487.59-3487.140"
108592   cell $or $or$ls180.v:3487$139
108593     parameter \A_SIGNED 0
108594     parameter \A_WIDTH 1
108595     parameter \B_SIGNED 0
108596     parameter \B_WIDTH 1
108597     parameter \Y_WIDTH 1
108598     connect \A \main_sdram_bankmachine2_req_wdata_ready
108599     connect \B \main_sdram_bankmachine2_req_rdata_valid
108600     connect \Y $or$ls180.v:3487$139_Y
108601   end
108602   attribute \src "ls180.v:3488.44-3488.151"
108603   cell $or $or$ls180.v:3488$140
108604     parameter \A_SIGNED 0
108605     parameter \A_WIDTH 1
108606     parameter \B_SIGNED 0
108607     parameter \B_WIDTH 1
108608     parameter \Y_WIDTH 1
108609     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
108610     connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid
108611     connect \Y $or$ls180.v:3488$140_Y
108612   end
108613   attribute \src "ls180.v:3496.45-3496.170"
108614   cell $or $or$ls180.v:3496$144
108615     parameter \A_SIGNED 0
108616     parameter \A_WIDTH 13
108617     parameter \B_SIGNED 0
108618     parameter \B_WIDTH 13
108619     parameter \Y_WIDTH 13
108620     connect \A $sshl$ls180.v:3496$143_Y
108621     connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] }
108622     connect \Y $or$ls180.v:3496$144_Y
108623   end
108624   attribute \src "ls180.v:3533.127-3533.245"
108625   cell $or $or$ls180.v:3533$157
108626     parameter \A_SIGNED 0
108627     parameter \A_WIDTH 1
108628     parameter \B_SIGNED 0
108629     parameter \B_WIDTH 1
108630     parameter \Y_WIDTH 1
108631     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
108632     connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
108633     connect \Y $or$ls180.v:3533$157_Y
108634   end
108635   attribute \src "ls180.v:3539.57-3539.157"
108636   cell $or $or$ls180.v:3539$163
108637     parameter \A_SIGNED 0
108638     parameter \A_WIDTH 1
108639     parameter \B_SIGNED 0
108640     parameter \B_WIDTH 1
108641     parameter \Y_WIDTH 1
108642     connect \A $not$ls180.v:3539$162_Y
108643     connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
108644     connect \Y $or$ls180.v:3539$163_Y
108645   end
108646   attribute \src "ls180.v:3644.59-3644.140"
108647   cell $or $or$ls180.v:3644$169
108648     parameter \A_SIGNED 0
108649     parameter \A_WIDTH 1
108650     parameter \B_SIGNED 0
108651     parameter \B_WIDTH 1
108652     parameter \Y_WIDTH 1
108653     connect \A \main_sdram_bankmachine3_req_wdata_ready
108654     connect \B \main_sdram_bankmachine3_req_rdata_valid
108655     connect \Y $or$ls180.v:3644$169_Y
108656   end
108657   attribute \src "ls180.v:3645.44-3645.151"
108658   cell $or $or$ls180.v:3645$170
108659     parameter \A_SIGNED 0
108660     parameter \A_WIDTH 1
108661     parameter \B_SIGNED 0
108662     parameter \B_WIDTH 1
108663     parameter \Y_WIDTH 1
108664     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
108665     connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid
108666     connect \Y $or$ls180.v:3645$170_Y
108667   end
108668   attribute \src "ls180.v:3653.45-3653.170"
108669   cell $or $or$ls180.v:3653$174
108670     parameter \A_SIGNED 0
108671     parameter \A_WIDTH 13
108672     parameter \B_SIGNED 0
108673     parameter \B_WIDTH 13
108674     parameter \Y_WIDTH 13
108675     connect \A $sshl$ls180.v:3653$173_Y
108676     connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] }
108677     connect \Y $or$ls180.v:3653$174_Y
108678   end
108679   attribute \src "ls180.v:3690.127-3690.245"
108680   cell $or $or$ls180.v:3690$187
108681     parameter \A_SIGNED 0
108682     parameter \A_WIDTH 1
108683     parameter \B_SIGNED 0
108684     parameter \B_WIDTH 1
108685     parameter \Y_WIDTH 1
108686     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
108687     connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
108688     connect \Y $or$ls180.v:3690$187_Y
108689   end
108690   attribute \src "ls180.v:3696.57-3696.157"
108691   cell $or $or$ls180.v:3696$193
108692     parameter \A_SIGNED 0
108693     parameter \A_WIDTH 1
108694     parameter \B_SIGNED 0
108695     parameter \B_WIDTH 1
108696     parameter \Y_WIDTH 1
108697     connect \A $not$ls180.v:3696$192_Y
108698     connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
108699     connect \Y $or$ls180.v:3696$193_Y
108700   end
108701   attribute \src "ls180.v:3795.107-3795.193"
108702   cell $or $or$ls180.v:3795$213
108703     parameter \A_SIGNED 0
108704     parameter \A_WIDTH 1
108705     parameter \B_SIGNED 0
108706     parameter \B_WIDTH 1
108707     parameter \Y_WIDTH 1
108708     connect \A \main_sdram_choose_req_cmd_payload_is_write
108709     connect \B \main_sdram_choose_req_cmd_payload_is_read
108710     connect \Y $or$ls180.v:3795$213_Y
108711   end
108712   attribute \src "ls180.v:3798.39-3798.204"
108713   cell $or $or$ls180.v:3798$219
108714     parameter \A_SIGNED 0
108715     parameter \A_WIDTH 1
108716     parameter \B_SIGNED 0
108717     parameter \B_WIDTH 1
108718     parameter \Y_WIDTH 1
108719     connect \A $and$ls180.v:3798$217_Y
108720     connect \B $and$ls180.v:3798$218_Y
108721     connect \Y $or$ls180.v:3798$219_Y
108722   end
108723   attribute \src "ls180.v:3798.38-3798.289"
108724   cell $or $or$ls180.v:3798$221
108725     parameter \A_SIGNED 0
108726     parameter \A_WIDTH 1
108727     parameter \B_SIGNED 0
108728     parameter \B_WIDTH 1
108729     parameter \Y_WIDTH 1
108730     connect \A $or$ls180.v:3798$219_Y
108731     connect \B $and$ls180.v:3798$220_Y
108732     connect \Y $or$ls180.v:3798$221_Y
108733   end
108734   attribute \src "ls180.v:3798.37-3798.374"
108735   cell $or $or$ls180.v:3798$223
108736     parameter \A_SIGNED 0
108737     parameter \A_WIDTH 1
108738     parameter \B_SIGNED 0
108739     parameter \B_WIDTH 1
108740     parameter \Y_WIDTH 1
108741     connect \A $or$ls180.v:3798$221_Y
108742     connect \B $and$ls180.v:3798$222_Y
108743     connect \Y $or$ls180.v:3798$223_Y
108744   end
108745   attribute \src "ls180.v:3799.40-3799.207"
108746   cell $or $or$ls180.v:3799$226
108747     parameter \A_SIGNED 0
108748     parameter \A_WIDTH 1
108749     parameter \B_SIGNED 0
108750     parameter \B_WIDTH 1
108751     parameter \Y_WIDTH 1
108752     connect \A $and$ls180.v:3799$224_Y
108753     connect \B $and$ls180.v:3799$225_Y
108754     connect \Y $or$ls180.v:3799$226_Y
108755   end
108756   attribute \src "ls180.v:3799.39-3799.293"
108757   cell $or $or$ls180.v:3799$228
108758     parameter \A_SIGNED 0
108759     parameter \A_WIDTH 1
108760     parameter \B_SIGNED 0
108761     parameter \B_WIDTH 1
108762     parameter \Y_WIDTH 1
108763     connect \A $or$ls180.v:3799$226_Y
108764     connect \B $and$ls180.v:3799$227_Y
108765     connect \Y $or$ls180.v:3799$228_Y
108766   end
108767   attribute \src "ls180.v:3799.38-3799.379"
108768   cell $or $or$ls180.v:3799$230
108769     parameter \A_SIGNED 0
108770     parameter \A_WIDTH 1
108771     parameter \B_SIGNED 0
108772     parameter \B_WIDTH 1
108773     parameter \Y_WIDTH 1
108774     connect \A $or$ls180.v:3799$228_Y
108775     connect \B $and$ls180.v:3799$229_Y
108776     connect \Y $or$ls180.v:3799$230_Y
108777   end
108778   attribute \src "ls180.v:3812.158-3812.332"
108779   cell $or $or$ls180.v:3812$244
108780     parameter \A_SIGNED 0
108781     parameter \A_WIDTH 1
108782     parameter \B_SIGNED 0
108783     parameter \B_WIDTH 1
108784     parameter \Y_WIDTH 1
108785     connect \A $not$ls180.v:3812$243_Y
108786     connect \B \main_sdram_choose_cmd_want_activates
108787     connect \Y $or$ls180.v:3812$244_Y
108788   end
108789   attribute \src "ls180.v:3812.75-3812.506"
108790   cell $or $or$ls180.v:3812$249
108791     parameter \A_SIGNED 0
108792     parameter \A_WIDTH 1
108793     parameter \B_SIGNED 0
108794     parameter \B_WIDTH 1
108795     parameter \Y_WIDTH 1
108796     connect \A $and$ls180.v:3812$245_Y
108797     connect \B $and$ls180.v:3812$248_Y
108798     connect \Y $or$ls180.v:3812$249_Y
108799   end
108800   attribute \src "ls180.v:3813.158-3813.332"
108801   cell $or $or$ls180.v:3813$257
108802     parameter \A_SIGNED 0
108803     parameter \A_WIDTH 1
108804     parameter \B_SIGNED 0
108805     parameter \B_WIDTH 1
108806     parameter \Y_WIDTH 1
108807     connect \A $not$ls180.v:3813$256_Y
108808     connect \B \main_sdram_choose_cmd_want_activates
108809     connect \Y $or$ls180.v:3813$257_Y
108810   end
108811   attribute \src "ls180.v:3813.75-3813.506"
108812   cell $or $or$ls180.v:3813$262
108813     parameter \A_SIGNED 0
108814     parameter \A_WIDTH 1
108815     parameter \B_SIGNED 0
108816     parameter \B_WIDTH 1
108817     parameter \Y_WIDTH 1
108818     connect \A $and$ls180.v:3813$258_Y
108819     connect \B $and$ls180.v:3813$261_Y
108820     connect \Y $or$ls180.v:3813$262_Y
108821   end
108822   attribute \src "ls180.v:3814.158-3814.332"
108823   cell $or $or$ls180.v:3814$270
108824     parameter \A_SIGNED 0
108825     parameter \A_WIDTH 1
108826     parameter \B_SIGNED 0
108827     parameter \B_WIDTH 1
108828     parameter \Y_WIDTH 1
108829     connect \A $not$ls180.v:3814$269_Y
108830     connect \B \main_sdram_choose_cmd_want_activates
108831     connect \Y $or$ls180.v:3814$270_Y
108832   end
108833   attribute \src "ls180.v:3814.75-3814.506"
108834   cell $or $or$ls180.v:3814$275
108835     parameter \A_SIGNED 0
108836     parameter \A_WIDTH 1
108837     parameter \B_SIGNED 0
108838     parameter \B_WIDTH 1
108839     parameter \Y_WIDTH 1
108840     connect \A $and$ls180.v:3814$271_Y
108841     connect \B $and$ls180.v:3814$274_Y
108842     connect \Y $or$ls180.v:3814$275_Y
108843   end
108844   attribute \src "ls180.v:3815.158-3815.332"
108845   cell $or $or$ls180.v:3815$283
108846     parameter \A_SIGNED 0
108847     parameter \A_WIDTH 1
108848     parameter \B_SIGNED 0
108849     parameter \B_WIDTH 1
108850     parameter \Y_WIDTH 1
108851     connect \A $not$ls180.v:3815$282_Y
108852     connect \B \main_sdram_choose_cmd_want_activates
108853     connect \Y $or$ls180.v:3815$283_Y
108854   end
108855   attribute \src "ls180.v:3815.75-3815.506"
108856   cell $or $or$ls180.v:3815$288
108857     parameter \A_SIGNED 0
108858     parameter \A_WIDTH 1
108859     parameter \B_SIGNED 0
108860     parameter \B_WIDTH 1
108861     parameter \Y_WIDTH 1
108862     connect \A $and$ls180.v:3815$284_Y
108863     connect \B $and$ls180.v:3815$287_Y
108864     connect \Y $or$ls180.v:3815$288_Y
108865   end
108866   attribute \src "ls180.v:3842.36-3842.104"
108867   cell $or $or$ls180.v:3842$294
108868     parameter \A_SIGNED 0
108869     parameter \A_WIDTH 1
108870     parameter \B_SIGNED 0
108871     parameter \B_WIDTH 1
108872     parameter \Y_WIDTH 1
108873     connect \A \main_sdram_choose_cmd_cmd_ready
108874     connect \B $not$ls180.v:3842$293_Y
108875     connect \Y $or$ls180.v:3842$294_Y
108876   end
108877   attribute \src "ls180.v:3845.158-3845.332"
108878   cell $or $or$ls180.v:3845$302
108879     parameter \A_SIGNED 0
108880     parameter \A_WIDTH 1
108881     parameter \B_SIGNED 0
108882     parameter \B_WIDTH 1
108883     parameter \Y_WIDTH 1
108884     connect \A $not$ls180.v:3845$301_Y
108885     connect \B \main_sdram_choose_req_want_activates
108886     connect \Y $or$ls180.v:3845$302_Y
108887   end
108888   attribute \src "ls180.v:3845.75-3845.506"
108889   cell $or $or$ls180.v:3845$307
108890     parameter \A_SIGNED 0
108891     parameter \A_WIDTH 1
108892     parameter \B_SIGNED 0
108893     parameter \B_WIDTH 1
108894     parameter \Y_WIDTH 1
108895     connect \A $and$ls180.v:3845$303_Y
108896     connect \B $and$ls180.v:3845$306_Y
108897     connect \Y $or$ls180.v:3845$307_Y
108898   end
108899   attribute \src "ls180.v:3846.158-3846.332"
108900   cell $or $or$ls180.v:3846$315
108901     parameter \A_SIGNED 0
108902     parameter \A_WIDTH 1
108903     parameter \B_SIGNED 0
108904     parameter \B_WIDTH 1
108905     parameter \Y_WIDTH 1
108906     connect \A $not$ls180.v:3846$314_Y
108907     connect \B \main_sdram_choose_req_want_activates
108908     connect \Y $or$ls180.v:3846$315_Y
108909   end
108910   attribute \src "ls180.v:3846.75-3846.506"
108911   cell $or $or$ls180.v:3846$320
108912     parameter \A_SIGNED 0
108913     parameter \A_WIDTH 1
108914     parameter \B_SIGNED 0
108915     parameter \B_WIDTH 1
108916     parameter \Y_WIDTH 1
108917     connect \A $and$ls180.v:3846$316_Y
108918     connect \B $and$ls180.v:3846$319_Y
108919     connect \Y $or$ls180.v:3846$320_Y
108920   end
108921   attribute \src "ls180.v:3847.158-3847.332"
108922   cell $or $or$ls180.v:3847$328
108923     parameter \A_SIGNED 0
108924     parameter \A_WIDTH 1
108925     parameter \B_SIGNED 0
108926     parameter \B_WIDTH 1
108927     parameter \Y_WIDTH 1
108928     connect \A $not$ls180.v:3847$327_Y
108929     connect \B \main_sdram_choose_req_want_activates
108930     connect \Y $or$ls180.v:3847$328_Y
108931   end
108932   attribute \src "ls180.v:3847.75-3847.506"
108933   cell $or $or$ls180.v:3847$333
108934     parameter \A_SIGNED 0
108935     parameter \A_WIDTH 1
108936     parameter \B_SIGNED 0
108937     parameter \B_WIDTH 1
108938     parameter \Y_WIDTH 1
108939     connect \A $and$ls180.v:3847$329_Y
108940     connect \B $and$ls180.v:3847$332_Y
108941     connect \Y $or$ls180.v:3847$333_Y
108942   end
108943   attribute \src "ls180.v:3848.158-3848.332"
108944   cell $or $or$ls180.v:3848$341
108945     parameter \A_SIGNED 0
108946     parameter \A_WIDTH 1
108947     parameter \B_SIGNED 0
108948     parameter \B_WIDTH 1
108949     parameter \Y_WIDTH 1
108950     connect \A $not$ls180.v:3848$340_Y
108951     connect \B \main_sdram_choose_req_want_activates
108952     connect \Y $or$ls180.v:3848$341_Y
108953   end
108954   attribute \src "ls180.v:3848.75-3848.506"
108955   cell $or $or$ls180.v:3848$346
108956     parameter \A_SIGNED 0
108957     parameter \A_WIDTH 1
108958     parameter \B_SIGNED 0
108959     parameter \B_WIDTH 1
108960     parameter \Y_WIDTH 1
108961     connect \A $and$ls180.v:3848$342_Y
108962     connect \B $and$ls180.v:3848$345_Y
108963     connect \Y $or$ls180.v:3848$346_Y
108964   end
108965   attribute \src "ls180.v:3911.36-3911.104"
108966   cell $or $or$ls180.v:3911$380
108967     parameter \A_SIGNED 0
108968     parameter \A_WIDTH 1
108969     parameter \B_SIGNED 0
108970     parameter \B_WIDTH 1
108971     parameter \Y_WIDTH 1
108972     connect \A \main_sdram_choose_req_cmd_ready
108973     connect \B $not$ls180.v:3911$379_Y
108974     connect \Y $or$ls180.v:3911$380_Y
108975   end
108976   attribute \src "ls180.v:3932.67-3932.221"
108977   cell $or $or$ls180.v:3932$387
108978     parameter \A_SIGNED 0
108979     parameter \A_WIDTH 1
108980     parameter \B_SIGNED 0
108981     parameter \B_WIDTH 1
108982     parameter \Y_WIDTH 1
108983     connect \A $not$ls180.v:3932$386_Y
108984     connect \B \main_sdram_ras_allowed
108985     connect \Y $or$ls180.v:3932$387_Y
108986   end
108987   attribute \src "ls180.v:3940.10-3940.62"
108988   cell $or $or$ls180.v:3940$390
108989     parameter \A_SIGNED 0
108990     parameter \A_WIDTH 1
108991     parameter \B_SIGNED 0
108992     parameter \B_WIDTH 1
108993     parameter \Y_WIDTH 1
108994     connect \A $not$ls180.v:3940$389_Y
108995     connect \B \main_sdram_max_time1
108996     connect \Y $or$ls180.v:3940$390_Y
108997   end
108998   attribute \src "ls180.v:3970.67-3970.221"
108999   cell $or $or$ls180.v:3970$396
109000     parameter \A_SIGNED 0
109001     parameter \A_WIDTH 1
109002     parameter \B_SIGNED 0
109003     parameter \B_WIDTH 1
109004     parameter \Y_WIDTH 1
109005     connect \A $not$ls180.v:3970$395_Y
109006     connect \B \main_sdram_ras_allowed
109007     connect \Y $or$ls180.v:3970$396_Y
109008   end
109009   attribute \src "ls180.v:3978.10-3978.61"
109010   cell $or $or$ls180.v:3978$399
109011     parameter \A_SIGNED 0
109012     parameter \A_WIDTH 1
109013     parameter \B_SIGNED 0
109014     parameter \B_WIDTH 1
109015     parameter \Y_WIDTH 1
109016     connect \A $not$ls180.v:3978$398_Y
109017     connect \B \main_sdram_max_time0
109018     connect \Y $or$ls180.v:3978$399_Y
109019   end
109020   attribute \src "ls180.v:3988.91-3988.180"
109021   cell $or $or$ls180.v:3988$403
109022     parameter \A_SIGNED 0
109023     parameter \A_WIDTH 1
109024     parameter \B_SIGNED 0
109025     parameter \B_WIDTH 1
109026     parameter \Y_WIDTH 1
109027     connect \A \builder_locked0
109028     connect \B $and$ls180.v:3988$402_Y
109029     connect \Y $or$ls180.v:3988$403_Y
109030   end
109031   attribute \src "ls180.v:3988.90-3988.255"
109032   cell $or $or$ls180.v:3988$406
109033     parameter \A_SIGNED 0
109034     parameter \A_WIDTH 1
109035     parameter \B_SIGNED 0
109036     parameter \B_WIDTH 1
109037     parameter \Y_WIDTH 1
109038     connect \A $or$ls180.v:3988$403_Y
109039     connect \B $and$ls180.v:3988$405_Y
109040     connect \Y $or$ls180.v:3988$406_Y
109041   end
109042   attribute \src "ls180.v:3988.89-3988.330"
109043   cell $or $or$ls180.v:3988$409
109044     parameter \A_SIGNED 0
109045     parameter \A_WIDTH 1
109046     parameter \B_SIGNED 0
109047     parameter \B_WIDTH 1
109048     parameter \Y_WIDTH 1
109049     connect \A $or$ls180.v:3988$406_Y
109050     connect \B $and$ls180.v:3988$408_Y
109051     connect \Y $or$ls180.v:3988$409_Y
109052   end
109053   attribute \src "ls180.v:3993.91-3993.180"
109054   cell $or $or$ls180.v:3993$419
109055     parameter \A_SIGNED 0
109056     parameter \A_WIDTH 1
109057     parameter \B_SIGNED 0
109058     parameter \B_WIDTH 1
109059     parameter \Y_WIDTH 1
109060     connect \A \builder_locked1
109061     connect \B $and$ls180.v:3993$418_Y
109062     connect \Y $or$ls180.v:3993$419_Y
109063   end
109064   attribute \src "ls180.v:3993.90-3993.255"
109065   cell $or $or$ls180.v:3993$422
109066     parameter \A_SIGNED 0
109067     parameter \A_WIDTH 1
109068     parameter \B_SIGNED 0
109069     parameter \B_WIDTH 1
109070     parameter \Y_WIDTH 1
109071     connect \A $or$ls180.v:3993$419_Y
109072     connect \B $and$ls180.v:3993$421_Y
109073     connect \Y $or$ls180.v:3993$422_Y
109074   end
109075   attribute \src "ls180.v:3993.89-3993.330"
109076   cell $or $or$ls180.v:3993$425
109077     parameter \A_SIGNED 0
109078     parameter \A_WIDTH 1
109079     parameter \B_SIGNED 0
109080     parameter \B_WIDTH 1
109081     parameter \Y_WIDTH 1
109082     connect \A $or$ls180.v:3993$422_Y
109083     connect \B $and$ls180.v:3993$424_Y
109084     connect \Y $or$ls180.v:3993$425_Y
109085   end
109086   attribute \src "ls180.v:3998.91-3998.180"
109087   cell $or $or$ls180.v:3998$435
109088     parameter \A_SIGNED 0
109089     parameter \A_WIDTH 1
109090     parameter \B_SIGNED 0
109091     parameter \B_WIDTH 1
109092     parameter \Y_WIDTH 1
109093     connect \A \builder_locked2
109094     connect \B $and$ls180.v:3998$434_Y
109095     connect \Y $or$ls180.v:3998$435_Y
109096   end
109097   attribute \src "ls180.v:3998.90-3998.255"
109098   cell $or $or$ls180.v:3998$438
109099     parameter \A_SIGNED 0
109100     parameter \A_WIDTH 1
109101     parameter \B_SIGNED 0
109102     parameter \B_WIDTH 1
109103     parameter \Y_WIDTH 1
109104     connect \A $or$ls180.v:3998$435_Y
109105     connect \B $and$ls180.v:3998$437_Y
109106     connect \Y $or$ls180.v:3998$438_Y
109107   end
109108   attribute \src "ls180.v:3998.89-3998.330"
109109   cell $or $or$ls180.v:3998$441
109110     parameter \A_SIGNED 0
109111     parameter \A_WIDTH 1
109112     parameter \B_SIGNED 0
109113     parameter \B_WIDTH 1
109114     parameter \Y_WIDTH 1
109115     connect \A $or$ls180.v:3998$438_Y
109116     connect \B $and$ls180.v:3998$440_Y
109117     connect \Y $or$ls180.v:3998$441_Y
109118   end
109119   attribute \src "ls180.v:4003.91-4003.180"
109120   cell $or $or$ls180.v:4003$451
109121     parameter \A_SIGNED 0
109122     parameter \A_WIDTH 1
109123     parameter \B_SIGNED 0
109124     parameter \B_WIDTH 1
109125     parameter \Y_WIDTH 1
109126     connect \A \builder_locked3
109127     connect \B $and$ls180.v:4003$450_Y
109128     connect \Y $or$ls180.v:4003$451_Y
109129   end
109130   attribute \src "ls180.v:4003.90-4003.255"
109131   cell $or $or$ls180.v:4003$454
109132     parameter \A_SIGNED 0
109133     parameter \A_WIDTH 1
109134     parameter \B_SIGNED 0
109135     parameter \B_WIDTH 1
109136     parameter \Y_WIDTH 1
109137     connect \A $or$ls180.v:4003$451_Y
109138     connect \B $and$ls180.v:4003$453_Y
109139     connect \Y $or$ls180.v:4003$454_Y
109140   end
109141   attribute \src "ls180.v:4003.89-4003.330"
109142   cell $or $or$ls180.v:4003$457
109143     parameter \A_SIGNED 0
109144     parameter \A_WIDTH 1
109145     parameter \B_SIGNED 0
109146     parameter \B_WIDTH 1
109147     parameter \Y_WIDTH 1
109148     connect \A $or$ls180.v:4003$454_Y
109149     connect \B $and$ls180.v:4003$456_Y
109150     connect \Y $or$ls180.v:4003$457_Y
109151   end
109152   attribute \src "ls180.v:4008.132-4008.221"
109153   cell $or $or$ls180.v:4008$468
109154     parameter \A_SIGNED 0
109155     parameter \A_WIDTH 1
109156     parameter \B_SIGNED 0
109157     parameter \B_WIDTH 1
109158     parameter \Y_WIDTH 1
109159     connect \A \builder_locked0
109160     connect \B $and$ls180.v:4008$467_Y
109161     connect \Y $or$ls180.v:4008$468_Y
109162   end
109163   attribute \src "ls180.v:4008.131-4008.296"
109164   cell $or $or$ls180.v:4008$471
109165     parameter \A_SIGNED 0
109166     parameter \A_WIDTH 1
109167     parameter \B_SIGNED 0
109168     parameter \B_WIDTH 1
109169     parameter \Y_WIDTH 1
109170     connect \A $or$ls180.v:4008$468_Y
109171     connect \B $and$ls180.v:4008$470_Y
109172     connect \Y $or$ls180.v:4008$471_Y
109173   end
109174   attribute \src "ls180.v:4008.130-4008.371"
109175   cell $or $or$ls180.v:4008$474
109176     parameter \A_SIGNED 0
109177     parameter \A_WIDTH 1
109178     parameter \B_SIGNED 0
109179     parameter \B_WIDTH 1
109180     parameter \Y_WIDTH 1
109181     connect \A $or$ls180.v:4008$471_Y
109182     connect \B $and$ls180.v:4008$473_Y
109183     connect \Y $or$ls180.v:4008$474_Y
109184   end
109185   attribute \src "ls180.v:4008.34-4008.411"
109186   cell $or $or$ls180.v:4008$479
109187     parameter \A_SIGNED 0
109188     parameter \A_WIDTH 1
109189     parameter \B_SIGNED 0
109190     parameter \B_WIDTH 1
109191     parameter \Y_WIDTH 1
109192     connect \A 1'0
109193     connect \B $and$ls180.v:4008$478_Y
109194     connect \Y $or$ls180.v:4008$479_Y
109195   end
109196   attribute \src "ls180.v:4008.506-4008.595"
109197   cell $or $or$ls180.v:4008$484
109198     parameter \A_SIGNED 0
109199     parameter \A_WIDTH 1
109200     parameter \B_SIGNED 0
109201     parameter \B_WIDTH 1
109202     parameter \Y_WIDTH 1
109203     connect \A \builder_locked1
109204     connect \B $and$ls180.v:4008$483_Y
109205     connect \Y $or$ls180.v:4008$484_Y
109206   end
109207   attribute \src "ls180.v:4008.505-4008.670"
109208   cell $or $or$ls180.v:4008$487
109209     parameter \A_SIGNED 0
109210     parameter \A_WIDTH 1
109211     parameter \B_SIGNED 0
109212     parameter \B_WIDTH 1
109213     parameter \Y_WIDTH 1
109214     connect \A $or$ls180.v:4008$484_Y
109215     connect \B $and$ls180.v:4008$486_Y
109216     connect \Y $or$ls180.v:4008$487_Y
109217   end
109218   attribute \src "ls180.v:4008.504-4008.745"
109219   cell $or $or$ls180.v:4008$490
109220     parameter \A_SIGNED 0
109221     parameter \A_WIDTH 1
109222     parameter \B_SIGNED 0
109223     parameter \B_WIDTH 1
109224     parameter \Y_WIDTH 1
109225     connect \A $or$ls180.v:4008$487_Y
109226     connect \B $and$ls180.v:4008$489_Y
109227     connect \Y $or$ls180.v:4008$490_Y
109228   end
109229   attribute \src "ls180.v:4008.33-4008.785"
109230   cell $or $or$ls180.v:4008$495
109231     parameter \A_SIGNED 0
109232     parameter \A_WIDTH 1
109233     parameter \B_SIGNED 0
109234     parameter \B_WIDTH 1
109235     parameter \Y_WIDTH 1
109236     connect \A $or$ls180.v:4008$479_Y
109237     connect \B $and$ls180.v:4008$494_Y
109238     connect \Y $or$ls180.v:4008$495_Y
109239   end
109240   attribute \src "ls180.v:4008.880-4008.969"
109241   cell $or $or$ls180.v:4008$500
109242     parameter \A_SIGNED 0
109243     parameter \A_WIDTH 1
109244     parameter \B_SIGNED 0
109245     parameter \B_WIDTH 1
109246     parameter \Y_WIDTH 1
109247     connect \A \builder_locked2
109248     connect \B $and$ls180.v:4008$499_Y
109249     connect \Y $or$ls180.v:4008$500_Y
109250   end
109251   attribute \src "ls180.v:4008.879-4008.1044"
109252   cell $or $or$ls180.v:4008$503
109253     parameter \A_SIGNED 0
109254     parameter \A_WIDTH 1
109255     parameter \B_SIGNED 0
109256     parameter \B_WIDTH 1
109257     parameter \Y_WIDTH 1
109258     connect \A $or$ls180.v:4008$500_Y
109259     connect \B $and$ls180.v:4008$502_Y
109260     connect \Y $or$ls180.v:4008$503_Y
109261   end
109262   attribute \src "ls180.v:4008.878-4008.1119"
109263   cell $or $or$ls180.v:4008$506
109264     parameter \A_SIGNED 0
109265     parameter \A_WIDTH 1
109266     parameter \B_SIGNED 0
109267     parameter \B_WIDTH 1
109268     parameter \Y_WIDTH 1
109269     connect \A $or$ls180.v:4008$503_Y
109270     connect \B $and$ls180.v:4008$505_Y
109271     connect \Y $or$ls180.v:4008$506_Y
109272   end
109273   attribute \src "ls180.v:4008.32-4008.1159"
109274   cell $or $or$ls180.v:4008$511
109275     parameter \A_SIGNED 0
109276     parameter \A_WIDTH 1
109277     parameter \B_SIGNED 0
109278     parameter \B_WIDTH 1
109279     parameter \Y_WIDTH 1
109280     connect \A $or$ls180.v:4008$495_Y
109281     connect \B $and$ls180.v:4008$510_Y
109282     connect \Y $or$ls180.v:4008$511_Y
109283   end
109284   attribute \src "ls180.v:4008.1254-4008.1343"
109285   cell $or $or$ls180.v:4008$516
109286     parameter \A_SIGNED 0
109287     parameter \A_WIDTH 1
109288     parameter \B_SIGNED 0
109289     parameter \B_WIDTH 1
109290     parameter \Y_WIDTH 1
109291     connect \A \builder_locked3
109292     connect \B $and$ls180.v:4008$515_Y
109293     connect \Y $or$ls180.v:4008$516_Y
109294   end
109295   attribute \src "ls180.v:4008.1253-4008.1418"
109296   cell $or $or$ls180.v:4008$519
109297     parameter \A_SIGNED 0
109298     parameter \A_WIDTH 1
109299     parameter \B_SIGNED 0
109300     parameter \B_WIDTH 1
109301     parameter \Y_WIDTH 1
109302     connect \A $or$ls180.v:4008$516_Y
109303     connect \B $and$ls180.v:4008$518_Y
109304     connect \Y $or$ls180.v:4008$519_Y
109305   end
109306   attribute \src "ls180.v:4008.1252-4008.1493"
109307   cell $or $or$ls180.v:4008$522
109308     parameter \A_SIGNED 0
109309     parameter \A_WIDTH 1
109310     parameter \B_SIGNED 0
109311     parameter \B_WIDTH 1
109312     parameter \Y_WIDTH 1
109313     connect \A $or$ls180.v:4008$519_Y
109314     connect \B $and$ls180.v:4008$521_Y
109315     connect \Y $or$ls180.v:4008$522_Y
109316   end
109317   attribute \src "ls180.v:4008.31-4008.1533"
109318   cell $or $or$ls180.v:4008$527
109319     parameter \A_SIGNED 0
109320     parameter \A_WIDTH 1
109321     parameter \B_SIGNED 0
109322     parameter \B_WIDTH 1
109323     parameter \Y_WIDTH 1
109324     connect \A $or$ls180.v:4008$511_Y
109325     connect \B $and$ls180.v:4008$526_Y
109326     connect \Y $or$ls180.v:4008$527_Y
109327   end
109328   attribute \src "ls180.v:4071.10-4071.52"
109329   cell $or $or$ls180.v:4071$536
109330     parameter \A_SIGNED 0
109331     parameter \A_WIDTH 1
109332     parameter \B_SIGNED 0
109333     parameter \B_WIDTH 1
109334     parameter \Y_WIDTH 1
109335     connect \A \main_litedram_wb_ack
109336     connect \B \main_converter_skip
109337     connect \Y $or$ls180.v:4071$536_Y
109338   end
109339   attribute \src "ls180.v:4098.35-4098.74"
109340   cell $or $or$ls180.v:4098$546
109341     parameter \A_SIGNED 0
109342     parameter \A_WIDTH 1
109343     parameter \B_SIGNED 0
109344     parameter \B_WIDTH 1
109345     parameter \Y_WIDTH 1
109346     connect \A \main_port_cmd_valid
109347     connect \B \main_cmd_consumed
109348     connect \Y $or$ls180.v:4098$546_Y
109349   end
109350   attribute \src "ls180.v:4099.34-4099.73"
109351   cell $or $or$ls180.v:4099$550
109352     parameter \A_SIGNED 0
109353     parameter \A_WIDTH 1
109354     parameter \B_SIGNED 0
109355     parameter \B_WIDTH 1
109356     parameter \Y_WIDTH 1
109357     connect \A \main_port_cmd_valid
109358     connect \B \main_cmd_consumed
109359     connect \Y $or$ls180.v:4099$550_Y
109360   end
109361   attribute \src "ls180.v:4100.48-4100.130"
109362   cell $or $or$ls180.v:4100$556
109363     parameter \A_SIGNED 0
109364     parameter \A_WIDTH 1
109365     parameter \B_SIGNED 0
109366     parameter \B_WIDTH 1
109367     parameter \Y_WIDTH 1
109368     connect \A $and$ls180.v:4100$553_Y
109369     connect \B $and$ls180.v:4100$555_Y
109370     connect \Y $or$ls180.v:4100$556_Y
109371   end
109372   attribute \src "ls180.v:4101.24-4101.87"
109373   cell $or $or$ls180.v:4101$559
109374     parameter \A_SIGNED 0
109375     parameter \A_WIDTH 1
109376     parameter \B_SIGNED 0
109377     parameter \B_WIDTH 1
109378     parameter \Y_WIDTH 1
109379     connect \A $and$ls180.v:4101$558_Y
109380     connect \B \main_cmd_consumed
109381     connect \Y $or$ls180.v:4101$559_Y
109382   end
109383   attribute \src "ls180.v:4102.26-4102.95"
109384   cell $or $or$ls180.v:4102$561
109385     parameter \A_SIGNED 0
109386     parameter \A_WIDTH 1
109387     parameter \B_SIGNED 0
109388     parameter \B_WIDTH 1
109389     parameter \Y_WIDTH 1
109390     connect \A $and$ls180.v:4102$560_Y
109391     connect \B \main_wdata_consumed
109392     connect \Y $or$ls180.v:4102$561_Y
109393   end
109394   attribute \src "ls180.v:4132.42-4132.89"
109395   cell $or $or$ls180.v:4132$569
109396     parameter \A_SIGNED 0
109397     parameter \A_WIDTH 1
109398     parameter \B_SIGNED 0
109399     parameter \B_WIDTH 1
109400     parameter \Y_WIDTH 1
109401     connect \A \main_uart_rx_clear
109402     connect \B $and$ls180.v:4132$568_Y
109403     connect \Y $or$ls180.v:4132$569_Y
109404   end
109405   attribute \src "ls180.v:4156.25-4156.174"
109406   cell $or $or$ls180.v:4156$579
109407     parameter \A_SIGNED 0
109408     parameter \A_WIDTH 1
109409     parameter \B_SIGNED 0
109410     parameter \B_WIDTH 1
109411     parameter \Y_WIDTH 1
109412     connect \A $and$ls180.v:4156$577_Y
109413     connect \B $and$ls180.v:4156$578_Y
109414     connect \Y $or$ls180.v:4156$579_Y
109415   end
109416   attribute \src "ls180.v:4171.80-4171.132"
109417   cell $or $or$ls180.v:4171$581
109418     parameter \A_SIGNED 0
109419     parameter \A_WIDTH 1
109420     parameter \B_SIGNED 0
109421     parameter \B_WIDTH 1
109422     parameter \Y_WIDTH 1
109423     connect \A $not$ls180.v:4171$580_Y
109424     connect \B \main_uart_tx_fifo_re
109425     connect \Y $or$ls180.v:4171$581_Y
109426   end
109427   attribute \src "ls180.v:4182.72-4182.135"
109428   cell $or $or$ls180.v:4182$586
109429     parameter \A_SIGNED 0
109430     parameter \A_WIDTH 1
109431     parameter \B_SIGNED 0
109432     parameter \B_WIDTH 1
109433     parameter \Y_WIDTH 1
109434     connect \A \main_uart_tx_fifo_syncfifo_writable
109435     connect \B \main_uart_tx_fifo_replace
109436     connect \Y $or$ls180.v:4182$586_Y
109437   end
109438   attribute \src "ls180.v:4201.80-4201.132"
109439   cell $or $or$ls180.v:4201$592
109440     parameter \A_SIGNED 0
109441     parameter \A_WIDTH 1
109442     parameter \B_SIGNED 0
109443     parameter \B_WIDTH 1
109444     parameter \Y_WIDTH 1
109445     connect \A $not$ls180.v:4201$591_Y
109446     connect \B \main_uart_rx_fifo_re
109447     connect \Y $or$ls180.v:4201$592_Y
109448   end
109449   attribute \src "ls180.v:4212.72-4212.135"
109450   cell $or $or$ls180.v:4212$597
109451     parameter \A_SIGNED 0
109452     parameter \A_WIDTH 1
109453     parameter \B_SIGNED 0
109454     parameter \B_WIDTH 1
109455     parameter \Y_WIDTH 1
109456     connect \A \main_uart_rx_fifo_syncfifo_writable
109457     connect \B \main_uart_rx_fifo_replace
109458     connect \Y $or$ls180.v:4212$597_Y
109459   end
109460   attribute \src "ls180.v:4346.36-4346.111"
109461   cell $or $or$ls180.v:4346$618
109462     parameter \A_SIGNED 0
109463     parameter \A_WIDTH 1
109464     parameter \B_SIGNED 0
109465     parameter \B_WIDTH 1
109466     parameter \Y_WIDTH 1
109467     connect \A \main_sdphy_init_pads_out_payload_clk
109468     connect \B \main_sdphy_cmdw_pads_out_payload_clk
109469     connect \Y $or$ls180.v:4346$618_Y
109470   end
109471   attribute \src "ls180.v:4346.35-4346.151"
109472   cell $or $or$ls180.v:4346$619
109473     parameter \A_SIGNED 0
109474     parameter \A_WIDTH 1
109475     parameter \B_SIGNED 0
109476     parameter \B_WIDTH 1
109477     parameter \Y_WIDTH 1
109478     connect \A $or$ls180.v:4346$618_Y
109479     connect \B \main_sdphy_cmdr_pads_out_payload_clk
109480     connect \Y $or$ls180.v:4346$619_Y
109481   end
109482   attribute \src "ls180.v:4346.34-4346.192"
109483   cell $or $or$ls180.v:4346$620
109484     parameter \A_SIGNED 0
109485     parameter \A_WIDTH 1
109486     parameter \B_SIGNED 0
109487     parameter \B_WIDTH 1
109488     parameter \Y_WIDTH 1
109489     connect \A $or$ls180.v:4346$619_Y
109490     connect \B \main_sdphy_dataw_pads_out_payload_clk
109491     connect \Y $or$ls180.v:4346$620_Y
109492   end
109493   attribute \src "ls180.v:4346.33-4346.233"
109494   cell $or $or$ls180.v:4346$621
109495     parameter \A_SIGNED 0
109496     parameter \A_WIDTH 1
109497     parameter \B_SIGNED 0
109498     parameter \B_WIDTH 1
109499     parameter \Y_WIDTH 1
109500     connect \A $or$ls180.v:4346$620_Y
109501     connect \B \main_sdphy_datar_pads_out_payload_clk
109502     connect \Y $or$ls180.v:4346$621_Y
109503   end
109504   attribute \src "ls180.v:4347.39-4347.120"
109505   cell $or $or$ls180.v:4347$622
109506     parameter \A_SIGNED 0
109507     parameter \A_WIDTH 1
109508     parameter \B_SIGNED 0
109509     parameter \B_WIDTH 1
109510     parameter \Y_WIDTH 1
109511     connect \A \main_sdphy_init_pads_out_payload_cmd_oe
109512     connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe
109513     connect \Y $or$ls180.v:4347$622_Y
109514   end
109515   attribute \src "ls180.v:4347.38-4347.163"
109516   cell $or $or$ls180.v:4347$623
109517     parameter \A_SIGNED 0
109518     parameter \A_WIDTH 1
109519     parameter \B_SIGNED 0
109520     parameter \B_WIDTH 1
109521     parameter \Y_WIDTH 1
109522     connect \A $or$ls180.v:4347$622_Y
109523     connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe
109524     connect \Y $or$ls180.v:4347$623_Y
109525   end
109526   attribute \src "ls180.v:4347.37-4347.207"
109527   cell $or $or$ls180.v:4347$624
109528     parameter \A_SIGNED 0
109529     parameter \A_WIDTH 1
109530     parameter \B_SIGNED 0
109531     parameter \B_WIDTH 1
109532     parameter \Y_WIDTH 1
109533     connect \A $or$ls180.v:4347$623_Y
109534     connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe
109535     connect \Y $or$ls180.v:4347$624_Y
109536   end
109537   attribute \src "ls180.v:4347.36-4347.251"
109538   cell $or $or$ls180.v:4347$625
109539     parameter \A_SIGNED 0
109540     parameter \A_WIDTH 1
109541     parameter \B_SIGNED 0
109542     parameter \B_WIDTH 1
109543     parameter \Y_WIDTH 1
109544     connect \A $or$ls180.v:4347$624_Y
109545     connect \B \main_sdphy_datar_pads_out_payload_cmd_oe
109546     connect \Y $or$ls180.v:4347$625_Y
109547   end
109548   attribute \src "ls180.v:4348.38-4348.117"
109549   cell $or $or$ls180.v:4348$626
109550     parameter \A_SIGNED 0
109551     parameter \A_WIDTH 1
109552     parameter \B_SIGNED 0
109553     parameter \B_WIDTH 1
109554     parameter \Y_WIDTH 1
109555     connect \A \main_sdphy_init_pads_out_payload_cmd_o
109556     connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o
109557     connect \Y $or$ls180.v:4348$626_Y
109558   end
109559   attribute \src "ls180.v:4348.37-4348.159"
109560   cell $or $or$ls180.v:4348$627
109561     parameter \A_SIGNED 0
109562     parameter \A_WIDTH 1
109563     parameter \B_SIGNED 0
109564     parameter \B_WIDTH 1
109565     parameter \Y_WIDTH 1
109566     connect \A $or$ls180.v:4348$626_Y
109567     connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o
109568     connect \Y $or$ls180.v:4348$627_Y
109569   end
109570   attribute \src "ls180.v:4348.36-4348.202"
109571   cell $or $or$ls180.v:4348$628
109572     parameter \A_SIGNED 0
109573     parameter \A_WIDTH 1
109574     parameter \B_SIGNED 0
109575     parameter \B_WIDTH 1
109576     parameter \Y_WIDTH 1
109577     connect \A $or$ls180.v:4348$627_Y
109578     connect \B \main_sdphy_dataw_pads_out_payload_cmd_o
109579     connect \Y $or$ls180.v:4348$628_Y
109580   end
109581   attribute \src "ls180.v:4348.35-4348.245"
109582   cell $or $or$ls180.v:4348$629
109583     parameter \A_SIGNED 0
109584     parameter \A_WIDTH 1
109585     parameter \B_SIGNED 0
109586     parameter \B_WIDTH 1
109587     parameter \Y_WIDTH 1
109588     connect \A $or$ls180.v:4348$628_Y
109589     connect \B \main_sdphy_datar_pads_out_payload_cmd_o
109590     connect \Y $or$ls180.v:4348$629_Y
109591   end
109592   attribute \src "ls180.v:4349.40-4349.123"
109593   cell $or $or$ls180.v:4349$630
109594     parameter \A_SIGNED 0
109595     parameter \A_WIDTH 1
109596     parameter \B_SIGNED 0
109597     parameter \B_WIDTH 1
109598     parameter \Y_WIDTH 1
109599     connect \A \main_sdphy_init_pads_out_payload_data_oe
109600     connect \B \main_sdphy_cmdw_pads_out_payload_data_oe
109601     connect \Y $or$ls180.v:4349$630_Y
109602   end
109603   attribute \src "ls180.v:4349.39-4349.167"
109604   cell $or $or$ls180.v:4349$631
109605     parameter \A_SIGNED 0
109606     parameter \A_WIDTH 1
109607     parameter \B_SIGNED 0
109608     parameter \B_WIDTH 1
109609     parameter \Y_WIDTH 1
109610     connect \A $or$ls180.v:4349$630_Y
109611     connect \B \main_sdphy_cmdr_pads_out_payload_data_oe
109612     connect \Y $or$ls180.v:4349$631_Y
109613   end
109614   attribute \src "ls180.v:4349.38-4349.212"
109615   cell $or $or$ls180.v:4349$632
109616     parameter \A_SIGNED 0
109617     parameter \A_WIDTH 1
109618     parameter \B_SIGNED 0
109619     parameter \B_WIDTH 1
109620     parameter \Y_WIDTH 1
109621     connect \A $or$ls180.v:4349$631_Y
109622     connect \B \main_sdphy_dataw_pads_out_payload_data_oe
109623     connect \Y $or$ls180.v:4349$632_Y
109624   end
109625   attribute \src "ls180.v:4349.37-4349.257"
109626   cell $or $or$ls180.v:4349$633
109627     parameter \A_SIGNED 0
109628     parameter \A_WIDTH 1
109629     parameter \B_SIGNED 0
109630     parameter \B_WIDTH 1
109631     parameter \Y_WIDTH 1
109632     connect \A $or$ls180.v:4349$632_Y
109633     connect \B \main_sdphy_datar_pads_out_payload_data_oe
109634     connect \Y $or$ls180.v:4349$633_Y
109635   end
109636   attribute \src "ls180.v:4350.39-4350.120"
109637   cell $or $or$ls180.v:4350$634
109638     parameter \A_SIGNED 0
109639     parameter \A_WIDTH 4
109640     parameter \B_SIGNED 0
109641     parameter \B_WIDTH 4
109642     parameter \Y_WIDTH 4
109643     connect \A \main_sdphy_init_pads_out_payload_data_o
109644     connect \B \main_sdphy_cmdw_pads_out_payload_data_o
109645     connect \Y $or$ls180.v:4350$634_Y
109646   end
109647   attribute \src "ls180.v:4350.38-4350.163"
109648   cell $or $or$ls180.v:4350$635
109649     parameter \A_SIGNED 0
109650     parameter \A_WIDTH 4
109651     parameter \B_SIGNED 0
109652     parameter \B_WIDTH 4
109653     parameter \Y_WIDTH 4
109654     connect \A $or$ls180.v:4350$634_Y
109655     connect \B \main_sdphy_cmdr_pads_out_payload_data_o
109656     connect \Y $or$ls180.v:4350$635_Y
109657   end
109658   attribute \src "ls180.v:4350.37-4350.207"
109659   cell $or $or$ls180.v:4350$636
109660     parameter \A_SIGNED 0
109661     parameter \A_WIDTH 4
109662     parameter \B_SIGNED 0
109663     parameter \B_WIDTH 4
109664     parameter \Y_WIDTH 4
109665     connect \A $or$ls180.v:4350$635_Y
109666     connect \B \main_sdphy_dataw_pads_out_payload_data_o
109667     connect \Y $or$ls180.v:4350$636_Y
109668   end
109669   attribute \src "ls180.v:4350.36-4350.251"
109670   cell $or $or$ls180.v:4350$637
109671     parameter \A_SIGNED 0
109672     parameter \A_WIDTH 4
109673     parameter \B_SIGNED 0
109674     parameter \B_WIDTH 4
109675     parameter \Y_WIDTH 4
109676     connect \A $or$ls180.v:4350$636_Y
109677     connect \B \main_sdphy_datar_pads_out_payload_data_o
109678     connect \Y $or$ls180.v:4350$637_Y
109679   end
109680   attribute \src "ls180.v:4371.35-4371.80"
109681   cell $or $or$ls180.v:4371$638
109682     parameter \A_SIGNED 0
109683     parameter \A_WIDTH 1
109684     parameter \B_SIGNED 0
109685     parameter \B_WIDTH 1
109686     parameter \Y_WIDTH 1
109687     connect \A \main_sdphy_dataw_stop
109688     connect \B \main_sdphy_datar_stop
109689     connect \Y $or$ls180.v:4371$638_Y
109690   end
109691   attribute \src "ls180.v:4525.91-4525.144"
109692   cell $or $or$ls180.v:4525$652
109693     parameter \A_SIGNED 0
109694     parameter \A_WIDTH 1
109695     parameter \B_SIGNED 0
109696     parameter \B_WIDTH 1
109697     parameter \Y_WIDTH 1
109698     connect \A \main_sdphy_cmdr_cmdr_start
109699     connect \B \main_sdphy_cmdr_cmdr_run
109700     connect \Y $or$ls180.v:4525$652_Y
109701   end
109702   attribute \src "ls180.v:4542.53-4542.143"
109703   cell $or $or$ls180.v:4542$655
109704     parameter \A_SIGNED 0
109705     parameter \A_WIDTH 1
109706     parameter \B_SIGNED 0
109707     parameter \B_WIDTH 1
109708     parameter \Y_WIDTH 1
109709     connect \A $not$ls180.v:4542$654_Y
109710     connect \B \main_sdphy_cmdr_cmdr_converter_source_ready
109711     connect \Y $or$ls180.v:4542$655_Y
109712   end
109713   attribute \src "ls180.v:4545.47-4545.127"
109714   cell $or $or$ls180.v:4545$658
109715     parameter \A_SIGNED 0
109716     parameter \A_WIDTH 1
109717     parameter \B_SIGNED 0
109718     parameter \B_WIDTH 1
109719     parameter \Y_WIDTH 1
109720     connect \A $not$ls180.v:4545$657_Y
109721     connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
109722     connect \Y $or$ls180.v:4545$658_Y
109723   end
109724   attribute \src "ls180.v:4669.54-4669.146"
109725   cell $or $or$ls180.v:4669$676
109726     parameter \A_SIGNED 0
109727     parameter \A_WIDTH 1
109728     parameter \B_SIGNED 0
109729     parameter \B_WIDTH 1
109730     parameter \Y_WIDTH 1
109731     connect \A $not$ls180.v:4669$675_Y
109732     connect \B \main_sdphy_dataw_crcr_converter_source_ready
109733     connect \Y $or$ls180.v:4669$676_Y
109734   end
109735   attribute \src "ls180.v:4672.48-4672.130"
109736   cell $or $or$ls180.v:4672$679
109737     parameter \A_SIGNED 0
109738     parameter \A_WIDTH 1
109739     parameter \B_SIGNED 0
109740     parameter \B_WIDTH 1
109741     parameter \Y_WIDTH 1
109742     connect \A $not$ls180.v:4672$678_Y
109743     connect \B \main_sdphy_dataw_crcr_buf_source_ready
109744     connect \Y $or$ls180.v:4672$679_Y
109745   end
109746   attribute \src "ls180.v:4803.55-4803.149"
109747   cell $or $or$ls180.v:4803$691
109748     parameter \A_SIGNED 0
109749     parameter \A_WIDTH 1
109750     parameter \B_SIGNED 0
109751     parameter \B_WIDTH 1
109752     parameter \Y_WIDTH 1
109753     connect \A $not$ls180.v:4803$690_Y
109754     connect \B \main_sdphy_datar_datar_converter_source_ready
109755     connect \Y $or$ls180.v:4803$691_Y
109756   end
109757   attribute \src "ls180.v:4806.49-4806.133"
109758   cell $or $or$ls180.v:4806$694
109759     parameter \A_SIGNED 0
109760     parameter \A_WIDTH 1
109761     parameter \B_SIGNED 0
109762     parameter \B_WIDTH 1
109763     parameter \Y_WIDTH 1
109764     connect \A $not$ls180.v:4806$693_Y
109765     connect \B \main_sdphy_datar_datar_buf_source_ready
109766     connect \Y $or$ls180.v:4806$694_Y
109767   end
109768   attribute \src "ls180.v:5435.80-5435.151"
109769   cell $or $or$ls180.v:5435$989
109770     parameter \A_SIGNED 0
109771     parameter \A_WIDTH 1
109772     parameter \B_SIGNED 0
109773     parameter \B_WIDTH 1
109774     parameter \Y_WIDTH 1
109775     connect \A \main_sdblock2mem_fifo_syncfifo_writable
109776     connect \B \main_sdblock2mem_fifo_replace
109777     connect \Y $or$ls180.v:5435$989_Y
109778   end
109779   attribute \src "ls180.v:5446.49-5446.131"
109780   cell $or $or$ls180.v:5446$995
109781     parameter \A_SIGNED 0
109782     parameter \A_WIDTH 1
109783     parameter \B_SIGNED 0
109784     parameter \B_WIDTH 1
109785     parameter \Y_WIDTH 1
109786     connect \A $not$ls180.v:5446$994_Y
109787     connect \B \main_sdblock2mem_converter_source_ready
109788     connect \Y $or$ls180.v:5446$995_Y
109789   end
109790   attribute \src "ls180.v:5643.80-5643.151"
109791   cell $or $or$ls180.v:5643$1020
109792     parameter \A_SIGNED 0
109793     parameter \A_WIDTH 1
109794     parameter \B_SIGNED 0
109795     parameter \B_WIDTH 1
109796     parameter \Y_WIDTH 1
109797     connect \A \main_sdmem2block_fifo_syncfifo_writable
109798     connect \B \main_sdmem2block_fifo_replace
109799     connect \Y $or$ls180.v:5643$1020_Y
109800   end
109801   attribute \src "ls180.v:5758.33-5758.102"
109802   cell $or $or$ls180.v:5758$1060
109803     parameter \A_SIGNED 0
109804     parameter \A_WIDTH 1
109805     parameter \B_SIGNED 0
109806     parameter \B_WIDTH 1
109807     parameter \Y_WIDTH 1
109808     connect \A \main_libresocsim_ram_bus_err
109809     connect \B \main_libresocsim_libresoc_xics_icp_err
109810     connect \Y $or$ls180.v:5758$1060_Y
109811   end
109812   attribute \src "ls180.v:5758.32-5758.144"
109813   cell $or $or$ls180.v:5758$1061
109814     parameter \A_SIGNED 0
109815     parameter \A_WIDTH 1
109816     parameter \B_SIGNED 0
109817     parameter \B_WIDTH 1
109818     parameter \Y_WIDTH 1
109819     connect \A $or$ls180.v:5758$1060_Y
109820     connect \B \main_libresocsim_libresoc_xics_ics_err
109821     connect \Y $or$ls180.v:5758$1061_Y
109822   end
109823   attribute \src "ls180.v:5758.31-5758.165"
109824   cell $or $or$ls180.v:5758$1062
109825     parameter \A_SIGNED 0
109826     parameter \A_WIDTH 1
109827     parameter \B_SIGNED 0
109828     parameter \B_WIDTH 1
109829     parameter \Y_WIDTH 1
109830     connect \A $or$ls180.v:5758$1061_Y
109831     connect \B \main_wb_sdram_err
109832     connect \Y $or$ls180.v:5758$1062_Y
109833   end
109834   attribute \src "ls180.v:5758.30-5758.201"
109835   cell $or $or$ls180.v:5758$1063
109836     parameter \A_SIGNED 0
109837     parameter \A_WIDTH 1
109838     parameter \B_SIGNED 0
109839     parameter \B_WIDTH 1
109840     parameter \Y_WIDTH 1
109841     connect \A $or$ls180.v:5758$1062_Y
109842     connect \B \builder_libresocsim_wishbone_err
109843     connect \Y $or$ls180.v:5758$1063_Y
109844   end
109845   attribute \src "ls180.v:5764.28-5764.97"
109846   cell $or $or$ls180.v:5764$1068
109847     parameter \A_SIGNED 0
109848     parameter \A_WIDTH 1
109849     parameter \B_SIGNED 0
109850     parameter \B_WIDTH 1
109851     parameter \Y_WIDTH 1
109852     connect \A \main_libresocsim_ram_bus_ack
109853     connect \B \main_libresocsim_libresoc_xics_icp_ack
109854     connect \Y $or$ls180.v:5764$1068_Y
109855   end
109856   attribute \src "ls180.v:5764.27-5764.139"
109857   cell $or $or$ls180.v:5764$1069
109858     parameter \A_SIGNED 0
109859     parameter \A_WIDTH 1
109860     parameter \B_SIGNED 0
109861     parameter \B_WIDTH 1
109862     parameter \Y_WIDTH 1
109863     connect \A $or$ls180.v:5764$1068_Y
109864     connect \B \main_libresocsim_libresoc_xics_ics_ack
109865     connect \Y $or$ls180.v:5764$1069_Y
109866   end
109867   attribute \src "ls180.v:5764.26-5764.160"
109868   cell $or $or$ls180.v:5764$1070
109869     parameter \A_SIGNED 0
109870     parameter \A_WIDTH 1
109871     parameter \B_SIGNED 0
109872     parameter \B_WIDTH 1
109873     parameter \Y_WIDTH 1
109874     connect \A $or$ls180.v:5764$1069_Y
109875     connect \B \main_wb_sdram_ack
109876     connect \Y $or$ls180.v:5764$1070_Y
109877   end
109878   attribute \src "ls180.v:5764.25-5764.196"
109879   cell $or $or$ls180.v:5764$1071
109880     parameter \A_SIGNED 0
109881     parameter \A_WIDTH 1
109882     parameter \B_SIGNED 0
109883     parameter \B_WIDTH 1
109884     parameter \Y_WIDTH 1
109885     connect \A $or$ls180.v:5764$1070_Y
109886     connect \B \builder_libresocsim_wishbone_ack
109887     connect \Y $or$ls180.v:5764$1071_Y
109888   end
109889   attribute \src "ls180.v:5765.30-5765.169"
109890   cell $or $or$ls180.v:5765$1074
109891     parameter \A_SIGNED 0
109892     parameter \A_WIDTH 32
109893     parameter \B_SIGNED 0
109894     parameter \B_WIDTH 32
109895     parameter \Y_WIDTH 32
109896     connect \A $and$ls180.v:5765$1072_Y
109897     connect \B $and$ls180.v:5765$1073_Y
109898     connect \Y $or$ls180.v:5765$1074_Y
109899   end
109900   attribute \src "ls180.v:5765.29-5765.246"
109901   cell $or $or$ls180.v:5765$1076
109902     parameter \A_SIGNED 0
109903     parameter \A_WIDTH 32
109904     parameter \B_SIGNED 0
109905     parameter \B_WIDTH 32
109906     parameter \Y_WIDTH 32
109907     connect \A $or$ls180.v:5765$1074_Y
109908     connect \B $and$ls180.v:5765$1075_Y
109909     connect \Y $or$ls180.v:5765$1076_Y
109910   end
109911   attribute \src "ls180.v:5765.28-5765.302"
109912   cell $or $or$ls180.v:5765$1078
109913     parameter \A_SIGNED 0
109914     parameter \A_WIDTH 32
109915     parameter \B_SIGNED 0
109916     parameter \B_WIDTH 32
109917     parameter \Y_WIDTH 32
109918     connect \A $or$ls180.v:5765$1076_Y
109919     connect \B $and$ls180.v:5765$1077_Y
109920     connect \Y $or$ls180.v:5765$1078_Y
109921   end
109922   attribute \src "ls180.v:5765.27-5765.373"
109923   cell $or $or$ls180.v:5765$1080
109924     parameter \A_SIGNED 0
109925     parameter \A_WIDTH 32
109926     parameter \B_SIGNED 0
109927     parameter \B_WIDTH 32
109928     parameter \Y_WIDTH 32
109929     connect \A $or$ls180.v:5765$1078_Y
109930     connect \B $and$ls180.v:5765$1079_Y
109931     connect \Y $or$ls180.v:5765$1080_Y
109932   end
109933   attribute \src "ls180.v:6519.55-6519.124"
109934   cell $or $or$ls180.v:6519$2226
109935     parameter \A_SIGNED 0
109936     parameter \A_WIDTH 8
109937     parameter \B_SIGNED 0
109938     parameter \B_WIDTH 8
109939     parameter \Y_WIDTH 8
109940     connect \A \builder_interface0_bank_bus_dat_r
109941     connect \B \builder_interface1_bank_bus_dat_r
109942     connect \Y $or$ls180.v:6519$2226_Y
109943   end
109944   attribute \src "ls180.v:6519.54-6519.161"
109945   cell $or $or$ls180.v:6519$2227
109946     parameter \A_SIGNED 0
109947     parameter \A_WIDTH 8
109948     parameter \B_SIGNED 0
109949     parameter \B_WIDTH 8
109950     parameter \Y_WIDTH 8
109951     connect \A $or$ls180.v:6519$2226_Y
109952     connect \B \builder_interface2_bank_bus_dat_r
109953     connect \Y $or$ls180.v:6519$2227_Y
109954   end
109955   attribute \src "ls180.v:6519.53-6519.198"
109956   cell $or $or$ls180.v:6519$2228
109957     parameter \A_SIGNED 0
109958     parameter \A_WIDTH 8
109959     parameter \B_SIGNED 0
109960     parameter \B_WIDTH 8
109961     parameter \Y_WIDTH 8
109962     connect \A $or$ls180.v:6519$2227_Y
109963     connect \B \builder_interface3_bank_bus_dat_r
109964     connect \Y $or$ls180.v:6519$2228_Y
109965   end
109966   attribute \src "ls180.v:6519.52-6519.235"
109967   cell $or $or$ls180.v:6519$2229
109968     parameter \A_SIGNED 0
109969     parameter \A_WIDTH 8
109970     parameter \B_SIGNED 0
109971     parameter \B_WIDTH 8
109972     parameter \Y_WIDTH 8
109973     connect \A $or$ls180.v:6519$2228_Y
109974     connect \B \builder_interface4_bank_bus_dat_r
109975     connect \Y $or$ls180.v:6519$2229_Y
109976   end
109977   attribute \src "ls180.v:6519.51-6519.272"
109978   cell $or $or$ls180.v:6519$2230
109979     parameter \A_SIGNED 0
109980     parameter \A_WIDTH 8
109981     parameter \B_SIGNED 0
109982     parameter \B_WIDTH 8
109983     parameter \Y_WIDTH 8
109984     connect \A $or$ls180.v:6519$2229_Y
109985     connect \B \builder_interface5_bank_bus_dat_r
109986     connect \Y $or$ls180.v:6519$2230_Y
109987   end
109988   attribute \src "ls180.v:6519.50-6519.309"
109989   cell $or $or$ls180.v:6519$2231
109990     parameter \A_SIGNED 0
109991     parameter \A_WIDTH 8
109992     parameter \B_SIGNED 0
109993     parameter \B_WIDTH 8
109994     parameter \Y_WIDTH 8
109995     connect \A $or$ls180.v:6519$2230_Y
109996     connect \B \builder_interface6_bank_bus_dat_r
109997     connect \Y $or$ls180.v:6519$2231_Y
109998   end
109999   attribute \src "ls180.v:6519.49-6519.346"
110000   cell $or $or$ls180.v:6519$2232
110001     parameter \A_SIGNED 0
110002     parameter \A_WIDTH 8
110003     parameter \B_SIGNED 0
110004     parameter \B_WIDTH 8
110005     parameter \Y_WIDTH 8
110006     connect \A $or$ls180.v:6519$2231_Y
110007     connect \B \builder_interface7_bank_bus_dat_r
110008     connect \Y $or$ls180.v:6519$2232_Y
110009   end
110010   attribute \src "ls180.v:6519.48-6519.383"
110011   cell $or $or$ls180.v:6519$2233
110012     parameter \A_SIGNED 0
110013     parameter \A_WIDTH 8
110014     parameter \B_SIGNED 0
110015     parameter \B_WIDTH 8
110016     parameter \Y_WIDTH 8
110017     connect \A $or$ls180.v:6519$2232_Y
110018     connect \B \builder_interface8_bank_bus_dat_r
110019     connect \Y $or$ls180.v:6519$2233_Y
110020   end
110021   attribute \src "ls180.v:6519.47-6519.420"
110022   cell $or $or$ls180.v:6519$2234
110023     parameter \A_SIGNED 0
110024     parameter \A_WIDTH 8
110025     parameter \B_SIGNED 0
110026     parameter \B_WIDTH 8
110027     parameter \Y_WIDTH 8
110028     connect \A $or$ls180.v:6519$2233_Y
110029     connect \B \builder_interface9_bank_bus_dat_r
110030     connect \Y $or$ls180.v:6519$2234_Y
110031   end
110032   attribute \src "ls180.v:6519.46-6519.458"
110033   cell $or $or$ls180.v:6519$2235
110034     parameter \A_SIGNED 0
110035     parameter \A_WIDTH 8
110036     parameter \B_SIGNED 0
110037     parameter \B_WIDTH 8
110038     parameter \Y_WIDTH 8
110039     connect \A $or$ls180.v:6519$2234_Y
110040     connect \B \builder_interface10_bank_bus_dat_r
110041     connect \Y $or$ls180.v:6519$2235_Y
110042   end
110043   attribute \src "ls180.v:6519.45-6519.496"
110044   cell $or $or$ls180.v:6519$2236
110045     parameter \A_SIGNED 0
110046     parameter \A_WIDTH 8
110047     parameter \B_SIGNED 0
110048     parameter \B_WIDTH 8
110049     parameter \Y_WIDTH 8
110050     connect \A $or$ls180.v:6519$2235_Y
110051     connect \B \builder_interface11_bank_bus_dat_r
110052     connect \Y $or$ls180.v:6519$2236_Y
110053   end
110054   attribute \src "ls180.v:6519.44-6519.534"
110055   cell $or $or$ls180.v:6519$2237
110056     parameter \A_SIGNED 0
110057     parameter \A_WIDTH 8
110058     parameter \B_SIGNED 0
110059     parameter \B_WIDTH 8
110060     parameter \Y_WIDTH 8
110061     connect \A $or$ls180.v:6519$2236_Y
110062     connect \B \builder_interface12_bank_bus_dat_r
110063     connect \Y $or$ls180.v:6519$2237_Y
110064   end
110065   attribute \src "ls180.v:6519.43-6519.572"
110066   cell $or $or$ls180.v:6519$2238
110067     parameter \A_SIGNED 0
110068     parameter \A_WIDTH 8
110069     parameter \B_SIGNED 0
110070     parameter \B_WIDTH 8
110071     parameter \Y_WIDTH 8
110072     connect \A $or$ls180.v:6519$2237_Y
110073     connect \B \builder_interface13_bank_bus_dat_r
110074     connect \Y $or$ls180.v:6519$2238_Y
110075   end
110076   attribute \src "ls180.v:6519.42-6519.610"
110077   cell $or $or$ls180.v:6519$2239
110078     parameter \A_SIGNED 0
110079     parameter \A_WIDTH 8
110080     parameter \B_SIGNED 0
110081     parameter \B_WIDTH 8
110082     parameter \Y_WIDTH 8
110083     connect \A $or$ls180.v:6519$2238_Y
110084     connect \B \builder_interface14_bank_bus_dat_r
110085     connect \Y $or$ls180.v:6519$2239_Y
110086   end
110087   attribute \src "ls180.v:6846.90-6846.179"
110088   cell $or $or$ls180.v:6846$2264
110089     parameter \A_SIGNED 0
110090     parameter \A_WIDTH 1
110091     parameter \B_SIGNED 0
110092     parameter \B_WIDTH 1
110093     parameter \Y_WIDTH 1
110094     connect \A \builder_locked0
110095     connect \B $and$ls180.v:6846$2263_Y
110096     connect \Y $or$ls180.v:6846$2264_Y
110097   end
110098   attribute \src "ls180.v:6846.89-6846.254"
110099   cell $or $or$ls180.v:6846$2267
110100     parameter \A_SIGNED 0
110101     parameter \A_WIDTH 1
110102     parameter \B_SIGNED 0
110103     parameter \B_WIDTH 1
110104     parameter \Y_WIDTH 1
110105     connect \A $or$ls180.v:6846$2264_Y
110106     connect \B $and$ls180.v:6846$2266_Y
110107     connect \Y $or$ls180.v:6846$2267_Y
110108   end
110109   attribute \src "ls180.v:6846.88-6846.329"
110110   cell $or $or$ls180.v:6846$2270
110111     parameter \A_SIGNED 0
110112     parameter \A_WIDTH 1
110113     parameter \B_SIGNED 0
110114     parameter \B_WIDTH 1
110115     parameter \Y_WIDTH 1
110116     connect \A $or$ls180.v:6846$2267_Y
110117     connect \B $and$ls180.v:6846$2269_Y
110118     connect \Y $or$ls180.v:6846$2270_Y
110119   end
110120   attribute \src "ls180.v:6870.90-6870.179"
110121   cell $or $or$ls180.v:6870$2280
110122     parameter \A_SIGNED 0
110123     parameter \A_WIDTH 1
110124     parameter \B_SIGNED 0
110125     parameter \B_WIDTH 1
110126     parameter \Y_WIDTH 1
110127     connect \A \builder_locked1
110128     connect \B $and$ls180.v:6870$2279_Y
110129     connect \Y $or$ls180.v:6870$2280_Y
110130   end
110131   attribute \src "ls180.v:6870.89-6870.254"
110132   cell $or $or$ls180.v:6870$2283
110133     parameter \A_SIGNED 0
110134     parameter \A_WIDTH 1
110135     parameter \B_SIGNED 0
110136     parameter \B_WIDTH 1
110137     parameter \Y_WIDTH 1
110138     connect \A $or$ls180.v:6870$2280_Y
110139     connect \B $and$ls180.v:6870$2282_Y
110140     connect \Y $or$ls180.v:6870$2283_Y
110141   end
110142   attribute \src "ls180.v:6870.88-6870.329"
110143   cell $or $or$ls180.v:6870$2286
110144     parameter \A_SIGNED 0
110145     parameter \A_WIDTH 1
110146     parameter \B_SIGNED 0
110147     parameter \B_WIDTH 1
110148     parameter \Y_WIDTH 1
110149     connect \A $or$ls180.v:6870$2283_Y
110150     connect \B $and$ls180.v:6870$2285_Y
110151     connect \Y $or$ls180.v:6870$2286_Y
110152   end
110153   attribute \src "ls180.v:6894.90-6894.179"
110154   cell $or $or$ls180.v:6894$2296
110155     parameter \A_SIGNED 0
110156     parameter \A_WIDTH 1
110157     parameter \B_SIGNED 0
110158     parameter \B_WIDTH 1
110159     parameter \Y_WIDTH 1
110160     connect \A \builder_locked2
110161     connect \B $and$ls180.v:6894$2295_Y
110162     connect \Y $or$ls180.v:6894$2296_Y
110163   end
110164   attribute \src "ls180.v:6894.89-6894.254"
110165   cell $or $or$ls180.v:6894$2299
110166     parameter \A_SIGNED 0
110167     parameter \A_WIDTH 1
110168     parameter \B_SIGNED 0
110169     parameter \B_WIDTH 1
110170     parameter \Y_WIDTH 1
110171     connect \A $or$ls180.v:6894$2296_Y
110172     connect \B $and$ls180.v:6894$2298_Y
110173     connect \Y $or$ls180.v:6894$2299_Y
110174   end
110175   attribute \src "ls180.v:6894.88-6894.329"
110176   cell $or $or$ls180.v:6894$2302
110177     parameter \A_SIGNED 0
110178     parameter \A_WIDTH 1
110179     parameter \B_SIGNED 0
110180     parameter \B_WIDTH 1
110181     parameter \Y_WIDTH 1
110182     connect \A $or$ls180.v:6894$2299_Y
110183     connect \B $and$ls180.v:6894$2301_Y
110184     connect \Y $or$ls180.v:6894$2302_Y
110185   end
110186   attribute \src "ls180.v:6918.90-6918.179"
110187   cell $or $or$ls180.v:6918$2312
110188     parameter \A_SIGNED 0
110189     parameter \A_WIDTH 1
110190     parameter \B_SIGNED 0
110191     parameter \B_WIDTH 1
110192     parameter \Y_WIDTH 1
110193     connect \A \builder_locked3
110194     connect \B $and$ls180.v:6918$2311_Y
110195     connect \Y $or$ls180.v:6918$2312_Y
110196   end
110197   attribute \src "ls180.v:6918.89-6918.254"
110198   cell $or $or$ls180.v:6918$2315
110199     parameter \A_SIGNED 0
110200     parameter \A_WIDTH 1
110201     parameter \B_SIGNED 0
110202     parameter \B_WIDTH 1
110203     parameter \Y_WIDTH 1
110204     connect \A $or$ls180.v:6918$2312_Y
110205     connect \B $and$ls180.v:6918$2314_Y
110206     connect \Y $or$ls180.v:6918$2315_Y
110207   end
110208   attribute \src "ls180.v:6918.88-6918.329"
110209   cell $or $or$ls180.v:6918$2318
110210     parameter \A_SIGNED 0
110211     parameter \A_WIDTH 1
110212     parameter \B_SIGNED 0
110213     parameter \B_WIDTH 1
110214     parameter \Y_WIDTH 1
110215     connect \A $or$ls180.v:6918$2315_Y
110216     connect \B $and$ls180.v:6918$2317_Y
110217     connect \Y $or$ls180.v:6918$2318_Y
110218   end
110219   attribute \src "ls180.v:7432.20-7432.71"
110220   cell $or $or$ls180.v:7432$2375
110221     parameter \A_SIGNED 0
110222     parameter \A_WIDTH 1
110223     parameter \B_SIGNED 0
110224     parameter \B_WIDTH 1
110225     parameter \Y_WIDTH 1
110226     connect \A \main_nc [0]
110227     connect \B \main_libresocsim_libresoc_interrupt [0]
110228     connect \Y $or$ls180.v:7432$2375_Y
110229   end
110230   attribute \src "ls180.v:7433.20-7433.71"
110231   cell $or $or$ls180.v:7433$2376
110232     parameter \A_SIGNED 0
110233     parameter \A_WIDTH 1
110234     parameter \B_SIGNED 0
110235     parameter \B_WIDTH 1
110236     parameter \Y_WIDTH 1
110237     connect \A \main_nc [1]
110238     connect \B \main_libresocsim_libresoc_interrupt [0]
110239     connect \Y $or$ls180.v:7433$2376_Y
110240   end
110241   attribute \src "ls180.v:7434.20-7434.71"
110242   cell $or $or$ls180.v:7434$2377
110243     parameter \A_SIGNED 0
110244     parameter \A_WIDTH 1
110245     parameter \B_SIGNED 0
110246     parameter \B_WIDTH 1
110247     parameter \Y_WIDTH 1
110248     connect \A \main_nc [2]
110249     connect \B \main_libresocsim_libresoc_interrupt [0]
110250     connect \Y $or$ls180.v:7434$2377_Y
110251   end
110252   attribute \src "ls180.v:7435.20-7435.71"
110253   cell $or $or$ls180.v:7435$2378
110254     parameter \A_SIGNED 0
110255     parameter \A_WIDTH 1
110256     parameter \B_SIGNED 0
110257     parameter \B_WIDTH 1
110258     parameter \Y_WIDTH 1
110259     connect \A \main_nc [3]
110260     connect \B \main_libresocsim_libresoc_interrupt [0]
110261     connect \Y $or$ls180.v:7435$2378_Y
110262   end
110263   attribute \src "ls180.v:7436.20-7436.71"
110264   cell $or $or$ls180.v:7436$2379
110265     parameter \A_SIGNED 0
110266     parameter \A_WIDTH 1
110267     parameter \B_SIGNED 0
110268     parameter \B_WIDTH 1
110269     parameter \Y_WIDTH 1
110270     connect \A \main_nc [4]
110271     connect \B \main_libresocsim_libresoc_interrupt [0]
110272     connect \Y $or$ls180.v:7436$2379_Y
110273   end
110274   attribute \src "ls180.v:7437.20-7437.71"
110275   cell $or $or$ls180.v:7437$2380
110276     parameter \A_SIGNED 0
110277     parameter \A_WIDTH 1
110278     parameter \B_SIGNED 0
110279     parameter \B_WIDTH 1
110280     parameter \Y_WIDTH 1
110281     connect \A \main_nc [5]
110282     connect \B \main_libresocsim_libresoc_interrupt [0]
110283     connect \Y $or$ls180.v:7437$2380_Y
110284   end
110285   attribute \src "ls180.v:7438.20-7438.71"
110286   cell $or $or$ls180.v:7438$2381
110287     parameter \A_SIGNED 0
110288     parameter \A_WIDTH 1
110289     parameter \B_SIGNED 0
110290     parameter \B_WIDTH 1
110291     parameter \Y_WIDTH 1
110292     connect \A \main_nc [6]
110293     connect \B \main_libresocsim_libresoc_interrupt [0]
110294     connect \Y $or$ls180.v:7438$2381_Y
110295   end
110296   attribute \src "ls180.v:7439.20-7439.71"
110297   cell $or $or$ls180.v:7439$2382
110298     parameter \A_SIGNED 0
110299     parameter \A_WIDTH 1
110300     parameter \B_SIGNED 0
110301     parameter \B_WIDTH 1
110302     parameter \Y_WIDTH 1
110303     connect \A \main_nc [7]
110304     connect \B \main_libresocsim_libresoc_interrupt [0]
110305     connect \Y $or$ls180.v:7439$2382_Y
110306   end
110307   attribute \src "ls180.v:7440.20-7440.71"
110308   cell $or $or$ls180.v:7440$2383
110309     parameter \A_SIGNED 0
110310     parameter \A_WIDTH 1
110311     parameter \B_SIGNED 0
110312     parameter \B_WIDTH 1
110313     parameter \Y_WIDTH 1
110314     connect \A \main_nc [8]
110315     connect \B \main_libresocsim_libresoc_interrupt [0]
110316     connect \Y $or$ls180.v:7440$2383_Y
110317   end
110318   attribute \src "ls180.v:7441.20-7441.71"
110319   cell $or $or$ls180.v:7441$2384
110320     parameter \A_SIGNED 0
110321     parameter \A_WIDTH 1
110322     parameter \B_SIGNED 0
110323     parameter \B_WIDTH 1
110324     parameter \Y_WIDTH 1
110325     connect \A \main_nc [9]
110326     connect \B \main_libresocsim_libresoc_interrupt [0]
110327     connect \Y $or$ls180.v:7441$2384_Y
110328   end
110329   attribute \src "ls180.v:7442.21-7442.73"
110330   cell $or $or$ls180.v:7442$2385
110331     parameter \A_SIGNED 0
110332     parameter \A_WIDTH 1
110333     parameter \B_SIGNED 0
110334     parameter \B_WIDTH 1
110335     parameter \Y_WIDTH 1
110336     connect \A \main_nc [10]
110337     connect \B \main_libresocsim_libresoc_interrupt [0]
110338     connect \Y $or$ls180.v:7442$2385_Y
110339   end
110340   attribute \src "ls180.v:7443.21-7443.73"
110341   cell $or $or$ls180.v:7443$2386
110342     parameter \A_SIGNED 0
110343     parameter \A_WIDTH 1
110344     parameter \B_SIGNED 0
110345     parameter \B_WIDTH 1
110346     parameter \Y_WIDTH 1
110347     connect \A \main_nc [11]
110348     connect \B \main_libresocsim_libresoc_interrupt [0]
110349     connect \Y $or$ls180.v:7443$2386_Y
110350   end
110351   attribute \src "ls180.v:7444.21-7444.73"
110352   cell $or $or$ls180.v:7444$2387
110353     parameter \A_SIGNED 0
110354     parameter \A_WIDTH 1
110355     parameter \B_SIGNED 0
110356     parameter \B_WIDTH 1
110357     parameter \Y_WIDTH 1
110358     connect \A \main_nc [12]
110359     connect \B \main_libresocsim_libresoc_interrupt [0]
110360     connect \Y $or$ls180.v:7444$2387_Y
110361   end
110362   attribute \src "ls180.v:7445.21-7445.73"
110363   cell $or $or$ls180.v:7445$2388
110364     parameter \A_SIGNED 0
110365     parameter \A_WIDTH 1
110366     parameter \B_SIGNED 0
110367     parameter \B_WIDTH 1
110368     parameter \Y_WIDTH 1
110369     connect \A \main_nc [13]
110370     connect \B \main_libresocsim_libresoc_interrupt [0]
110371     connect \Y $or$ls180.v:7445$2388_Y
110372   end
110373   attribute \src "ls180.v:7446.21-7446.73"
110374   cell $or $or$ls180.v:7446$2389
110375     parameter \A_SIGNED 0
110376     parameter \A_WIDTH 1
110377     parameter \B_SIGNED 0
110378     parameter \B_WIDTH 1
110379     parameter \Y_WIDTH 1
110380     connect \A \main_nc [14]
110381     connect \B \main_libresocsim_libresoc_interrupt [0]
110382     connect \Y $or$ls180.v:7446$2389_Y
110383   end
110384   attribute \src "ls180.v:7447.21-7447.73"
110385   cell $or $or$ls180.v:7447$2390
110386     parameter \A_SIGNED 0
110387     parameter \A_WIDTH 1
110388     parameter \B_SIGNED 0
110389     parameter \B_WIDTH 1
110390     parameter \Y_WIDTH 1
110391     connect \A \main_nc [15]
110392     connect \B \main_libresocsim_libresoc_interrupt [0]
110393     connect \Y $or$ls180.v:7447$2390_Y
110394   end
110395   attribute \src "ls180.v:7448.21-7448.73"
110396   cell $or $or$ls180.v:7448$2391
110397     parameter \A_SIGNED 0
110398     parameter \A_WIDTH 1
110399     parameter \B_SIGNED 0
110400     parameter \B_WIDTH 1
110401     parameter \Y_WIDTH 1
110402     connect \A \main_nc [16]
110403     connect \B \main_libresocsim_libresoc_interrupt [0]
110404     connect \Y $or$ls180.v:7448$2391_Y
110405   end
110406   attribute \src "ls180.v:7449.21-7449.73"
110407   cell $or $or$ls180.v:7449$2392
110408     parameter \A_SIGNED 0
110409     parameter \A_WIDTH 1
110410     parameter \B_SIGNED 0
110411     parameter \B_WIDTH 1
110412     parameter \Y_WIDTH 1
110413     connect \A \main_nc [17]
110414     connect \B \main_libresocsim_libresoc_interrupt [0]
110415     connect \Y $or$ls180.v:7449$2392_Y
110416   end
110417   attribute \src "ls180.v:7450.21-7450.73"
110418   cell $or $or$ls180.v:7450$2393
110419     parameter \A_SIGNED 0
110420     parameter \A_WIDTH 1
110421     parameter \B_SIGNED 0
110422     parameter \B_WIDTH 1
110423     parameter \Y_WIDTH 1
110424     connect \A \main_nc [18]
110425     connect \B \main_libresocsim_libresoc_interrupt [0]
110426     connect \Y $or$ls180.v:7450$2393_Y
110427   end
110428   attribute \src "ls180.v:7451.21-7451.73"
110429   cell $or $or$ls180.v:7451$2394
110430     parameter \A_SIGNED 0
110431     parameter \A_WIDTH 1
110432     parameter \B_SIGNED 0
110433     parameter \B_WIDTH 1
110434     parameter \Y_WIDTH 1
110435     connect \A \main_nc [19]
110436     connect \B \main_libresocsim_libresoc_interrupt [0]
110437     connect \Y $or$ls180.v:7451$2394_Y
110438   end
110439   attribute \src "ls180.v:7452.21-7452.73"
110440   cell $or $or$ls180.v:7452$2395
110441     parameter \A_SIGNED 0
110442     parameter \A_WIDTH 1
110443     parameter \B_SIGNED 0
110444     parameter \B_WIDTH 1
110445     parameter \Y_WIDTH 1
110446     connect \A \main_nc [20]
110447     connect \B \main_libresocsim_libresoc_interrupt [0]
110448     connect \Y $or$ls180.v:7452$2395_Y
110449   end
110450   attribute \src "ls180.v:7453.21-7453.73"
110451   cell $or $or$ls180.v:7453$2396
110452     parameter \A_SIGNED 0
110453     parameter \A_WIDTH 1
110454     parameter \B_SIGNED 0
110455     parameter \B_WIDTH 1
110456     parameter \Y_WIDTH 1
110457     connect \A \main_nc [21]
110458     connect \B \main_libresocsim_libresoc_interrupt [0]
110459     connect \Y $or$ls180.v:7453$2396_Y
110460   end
110461   attribute \src "ls180.v:7454.21-7454.73"
110462   cell $or $or$ls180.v:7454$2397
110463     parameter \A_SIGNED 0
110464     parameter \A_WIDTH 1
110465     parameter \B_SIGNED 0
110466     parameter \B_WIDTH 1
110467     parameter \Y_WIDTH 1
110468     connect \A \main_nc [22]
110469     connect \B \main_libresocsim_libresoc_interrupt [0]
110470     connect \Y $or$ls180.v:7454$2397_Y
110471   end
110472   attribute \src "ls180.v:7455.21-7455.73"
110473   cell $or $or$ls180.v:7455$2398
110474     parameter \A_SIGNED 0
110475     parameter \A_WIDTH 1
110476     parameter \B_SIGNED 0
110477     parameter \B_WIDTH 1
110478     parameter \Y_WIDTH 1
110479     connect \A \main_nc [23]
110480     connect \B \main_libresocsim_libresoc_interrupt [0]
110481     connect \Y $or$ls180.v:7455$2398_Y
110482   end
110483   attribute \src "ls180.v:7456.21-7456.73"
110484   cell $or $or$ls180.v:7456$2399
110485     parameter \A_SIGNED 0
110486     parameter \A_WIDTH 1
110487     parameter \B_SIGNED 0
110488     parameter \B_WIDTH 1
110489     parameter \Y_WIDTH 1
110490     connect \A \main_nc [24]
110491     connect \B \main_libresocsim_libresoc_interrupt [0]
110492     connect \Y $or$ls180.v:7456$2399_Y
110493   end
110494   attribute \src "ls180.v:7457.21-7457.73"
110495   cell $or $or$ls180.v:7457$2400
110496     parameter \A_SIGNED 0
110497     parameter \A_WIDTH 1
110498     parameter \B_SIGNED 0
110499     parameter \B_WIDTH 1
110500     parameter \Y_WIDTH 1
110501     connect \A \main_nc [25]
110502     connect \B \main_libresocsim_libresoc_interrupt [0]
110503     connect \Y $or$ls180.v:7457$2400_Y
110504   end
110505   attribute \src "ls180.v:7458.21-7458.73"
110506   cell $or $or$ls180.v:7458$2401
110507     parameter \A_SIGNED 0
110508     parameter \A_WIDTH 1
110509     parameter \B_SIGNED 0
110510     parameter \B_WIDTH 1
110511     parameter \Y_WIDTH 1
110512     connect \A \main_nc [26]
110513     connect \B \main_libresocsim_libresoc_interrupt [0]
110514     connect \Y $or$ls180.v:7458$2401_Y
110515   end
110516   attribute \src "ls180.v:7459.21-7459.73"
110517   cell $or $or$ls180.v:7459$2402
110518     parameter \A_SIGNED 0
110519     parameter \A_WIDTH 1
110520     parameter \B_SIGNED 0
110521     parameter \B_WIDTH 1
110522     parameter \Y_WIDTH 1
110523     connect \A \main_nc [27]
110524     connect \B \main_libresocsim_libresoc_interrupt [0]
110525     connect \Y $or$ls180.v:7459$2402_Y
110526   end
110527   attribute \src "ls180.v:7460.21-7460.73"
110528   cell $or $or$ls180.v:7460$2403
110529     parameter \A_SIGNED 0
110530     parameter \A_WIDTH 1
110531     parameter \B_SIGNED 0
110532     parameter \B_WIDTH 1
110533     parameter \Y_WIDTH 1
110534     connect \A \main_nc [28]
110535     connect \B \main_libresocsim_libresoc_interrupt [0]
110536     connect \Y $or$ls180.v:7460$2403_Y
110537   end
110538   attribute \src "ls180.v:7461.21-7461.73"
110539   cell $or $or$ls180.v:7461$2404
110540     parameter \A_SIGNED 0
110541     parameter \A_WIDTH 1
110542     parameter \B_SIGNED 0
110543     parameter \B_WIDTH 1
110544     parameter \Y_WIDTH 1
110545     connect \A \main_nc [29]
110546     connect \B \main_libresocsim_libresoc_interrupt [0]
110547     connect \Y $or$ls180.v:7461$2404_Y
110548   end
110549   attribute \src "ls180.v:7462.21-7462.73"
110550   cell $or $or$ls180.v:7462$2405
110551     parameter \A_SIGNED 0
110552     parameter \A_WIDTH 1
110553     parameter \B_SIGNED 0
110554     parameter \B_WIDTH 1
110555     parameter \Y_WIDTH 1
110556     connect \A \main_nc [30]
110557     connect \B \main_libresocsim_libresoc_interrupt [0]
110558     connect \Y $or$ls180.v:7462$2405_Y
110559   end
110560   attribute \src "ls180.v:7463.21-7463.73"
110561   cell $or $or$ls180.v:7463$2406
110562     parameter \A_SIGNED 0
110563     parameter \A_WIDTH 1
110564     parameter \B_SIGNED 0
110565     parameter \B_WIDTH 1
110566     parameter \Y_WIDTH 1
110567     connect \A \main_nc [31]
110568     connect \B \main_libresocsim_libresoc_interrupt [0]
110569     connect \Y $or$ls180.v:7463$2406_Y
110570   end
110571   attribute \src "ls180.v:7464.21-7464.73"
110572   cell $or $or$ls180.v:7464$2407
110573     parameter \A_SIGNED 0
110574     parameter \A_WIDTH 1
110575     parameter \B_SIGNED 0
110576     parameter \B_WIDTH 1
110577     parameter \Y_WIDTH 1
110578     connect \A \main_nc [32]
110579     connect \B \main_libresocsim_libresoc_interrupt [0]
110580     connect \Y $or$ls180.v:7464$2407_Y
110581   end
110582   attribute \src "ls180.v:7465.21-7465.73"
110583   cell $or $or$ls180.v:7465$2408
110584     parameter \A_SIGNED 0
110585     parameter \A_WIDTH 1
110586     parameter \B_SIGNED 0
110587     parameter \B_WIDTH 1
110588     parameter \Y_WIDTH 1
110589     connect \A \main_nc [33]
110590     connect \B \main_libresocsim_libresoc_interrupt [0]
110591     connect \Y $or$ls180.v:7465$2408_Y
110592   end
110593   attribute \src "ls180.v:7466.21-7466.73"
110594   cell $or $or$ls180.v:7466$2409
110595     parameter \A_SIGNED 0
110596     parameter \A_WIDTH 1
110597     parameter \B_SIGNED 0
110598     parameter \B_WIDTH 1
110599     parameter \Y_WIDTH 1
110600     connect \A \main_nc [34]
110601     connect \B \main_libresocsim_libresoc_interrupt [0]
110602     connect \Y $or$ls180.v:7466$2409_Y
110603   end
110604   attribute \src "ls180.v:7467.21-7467.73"
110605   cell $or $or$ls180.v:7467$2410
110606     parameter \A_SIGNED 0
110607     parameter \A_WIDTH 1
110608     parameter \B_SIGNED 0
110609     parameter \B_WIDTH 1
110610     parameter \Y_WIDTH 1
110611     connect \A \main_nc [35]
110612     connect \B \main_libresocsim_libresoc_interrupt [0]
110613     connect \Y $or$ls180.v:7467$2410_Y
110614   end
110615   attribute \src "ls180.v:7468.7-7468.93"
110616   cell $or $or$ls180.v:7468$2411
110617     parameter \A_SIGNED 0
110618     parameter \A_WIDTH 1
110619     parameter \B_SIGNED 0
110620     parameter \B_WIDTH 1
110621     parameter \Y_WIDTH 1
110622     connect \A \main_libresocsim_interface0_converted_interface_ack
110623     connect \B \main_libresocsim_converter0_skip
110624     connect \Y $or$ls180.v:7468$2411_Y
110625   end
110626   attribute \src "ls180.v:7479.7-7479.93"
110627   cell $or $or$ls180.v:7479$2412
110628     parameter \A_SIGNED 0
110629     parameter \A_WIDTH 1
110630     parameter \B_SIGNED 0
110631     parameter \B_WIDTH 1
110632     parameter \Y_WIDTH 1
110633     connect \A \main_libresocsim_interface1_converted_interface_ack
110634     connect \B \main_libresocsim_converter1_skip
110635     connect \Y $or$ls180.v:7479$2412_Y
110636   end
110637   attribute \src "ls180.v:7490.7-7490.93"
110638   cell $or $or$ls180.v:7490$2413
110639     parameter \A_SIGNED 0
110640     parameter \A_WIDTH 1
110641     parameter \B_SIGNED 0
110642     parameter \B_WIDTH 1
110643     parameter \Y_WIDTH 1
110644     connect \A \main_libresocsim_interface2_converted_interface_ack
110645     connect \B \main_libresocsim_converter2_skip
110646     connect \Y $or$ls180.v:7490$2413_Y
110647   end
110648   attribute \src "ls180.v:7619.7-7619.107"
110649   cell $or $or$ls180.v:7619$2449
110650     parameter \A_SIGNED 0
110651     parameter \A_WIDTH 1
110652     parameter \B_SIGNED 0
110653     parameter \B_WIDTH 1
110654     parameter \Y_WIDTH 1
110655     connect \A $not$ls180.v:7619$2448_Y
110656     connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready
110657     connect \Y $or$ls180.v:7619$2449_Y
110658   end
110659   attribute \src "ls180.v:7665.7-7665.107"
110660   cell $or $or$ls180.v:7665$2465
110661     parameter \A_SIGNED 0
110662     parameter \A_WIDTH 1
110663     parameter \B_SIGNED 0
110664     parameter \B_WIDTH 1
110665     parameter \Y_WIDTH 1
110666     connect \A $not$ls180.v:7665$2464_Y
110667     connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready
110668     connect \Y $or$ls180.v:7665$2465_Y
110669   end
110670   attribute \src "ls180.v:7711.7-7711.107"
110671   cell $or $or$ls180.v:7711$2481
110672     parameter \A_SIGNED 0
110673     parameter \A_WIDTH 1
110674     parameter \B_SIGNED 0
110675     parameter \B_WIDTH 1
110676     parameter \Y_WIDTH 1
110677     connect \A $not$ls180.v:7711$2480_Y
110678     connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready
110679     connect \Y $or$ls180.v:7711$2481_Y
110680   end
110681   attribute \src "ls180.v:7757.7-7757.107"
110682   cell $or $or$ls180.v:7757$2497
110683     parameter \A_SIGNED 0
110684     parameter \A_WIDTH 1
110685     parameter \B_SIGNED 0
110686     parameter \B_WIDTH 1
110687     parameter \Y_WIDTH 1
110688     connect \A $not$ls180.v:7757$2496_Y
110689     connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready
110690     connect \Y $or$ls180.v:7757$2497_Y
110691   end
110692   attribute \src "ls180.v:7945.40-7945.125"
110693   cell $or $or$ls180.v:7945$2518
110694     parameter \A_SIGNED 0
110695     parameter \A_WIDTH 1
110696     parameter \B_SIGNED 0
110697     parameter \B_WIDTH 1
110698     parameter \Y_WIDTH 1
110699     connect \A 1'0
110700     connect \B $and$ls180.v:7945$2517_Y
110701     connect \Y $or$ls180.v:7945$2518_Y
110702   end
110703   attribute \src "ls180.v:7945.39-7945.207"
110704   cell $or $or$ls180.v:7945$2521
110705     parameter \A_SIGNED 0
110706     parameter \A_WIDTH 1
110707     parameter \B_SIGNED 0
110708     parameter \B_WIDTH 1
110709     parameter \Y_WIDTH 1
110710     connect \A $or$ls180.v:7945$2518_Y
110711     connect \B $and$ls180.v:7945$2520_Y
110712     connect \Y $or$ls180.v:7945$2521_Y
110713   end
110714   attribute \src "ls180.v:7945.38-7945.289"
110715   cell $or $or$ls180.v:7945$2524
110716     parameter \A_SIGNED 0
110717     parameter \A_WIDTH 1
110718     parameter \B_SIGNED 0
110719     parameter \B_WIDTH 1
110720     parameter \Y_WIDTH 1
110721     connect \A $or$ls180.v:7945$2521_Y
110722     connect \B $and$ls180.v:7945$2523_Y
110723     connect \Y $or$ls180.v:7945$2524_Y
110724   end
110725   attribute \src "ls180.v:7945.37-7945.371"
110726   cell $or $or$ls180.v:7945$2527
110727     parameter \A_SIGNED 0
110728     parameter \A_WIDTH 1
110729     parameter \B_SIGNED 0
110730     parameter \B_WIDTH 1
110731     parameter \Y_WIDTH 1
110732     connect \A $or$ls180.v:7945$2524_Y
110733     connect \B $and$ls180.v:7945$2526_Y
110734     connect \Y $or$ls180.v:7945$2527_Y
110735   end
110736   attribute \src "ls180.v:7946.41-7946.126"
110737   cell $or $or$ls180.v:7946$2530
110738     parameter \A_SIGNED 0
110739     parameter \A_WIDTH 1
110740     parameter \B_SIGNED 0
110741     parameter \B_WIDTH 1
110742     parameter \Y_WIDTH 1
110743     connect \A 1'0
110744     connect \B $and$ls180.v:7946$2529_Y
110745     connect \Y $or$ls180.v:7946$2530_Y
110746   end
110747   attribute \src "ls180.v:7946.40-7946.208"
110748   cell $or $or$ls180.v:7946$2533
110749     parameter \A_SIGNED 0
110750     parameter \A_WIDTH 1
110751     parameter \B_SIGNED 0
110752     parameter \B_WIDTH 1
110753     parameter \Y_WIDTH 1
110754     connect \A $or$ls180.v:7946$2530_Y
110755     connect \B $and$ls180.v:7946$2532_Y
110756     connect \Y $or$ls180.v:7946$2533_Y
110757   end
110758   attribute \src "ls180.v:7946.39-7946.290"
110759   cell $or $or$ls180.v:7946$2536
110760     parameter \A_SIGNED 0
110761     parameter \A_WIDTH 1
110762     parameter \B_SIGNED 0
110763     parameter \B_WIDTH 1
110764     parameter \Y_WIDTH 1
110765     connect \A $or$ls180.v:7946$2533_Y
110766     connect \B $and$ls180.v:7946$2535_Y
110767     connect \Y $or$ls180.v:7946$2536_Y
110768   end
110769   attribute \src "ls180.v:7946.38-7946.372"
110770   cell $or $or$ls180.v:7946$2539
110771     parameter \A_SIGNED 0
110772     parameter \A_WIDTH 1
110773     parameter \B_SIGNED 0
110774     parameter \B_WIDTH 1
110775     parameter \Y_WIDTH 1
110776     connect \A $or$ls180.v:7946$2536_Y
110777     connect \B $and$ls180.v:7946$2538_Y
110778     connect \Y $or$ls180.v:7946$2539_Y
110779   end
110780   attribute \src "ls180.v:7950.7-7950.49"
110781   cell $or $or$ls180.v:7950$2540
110782     parameter \A_SIGNED 0
110783     parameter \A_WIDTH 1
110784     parameter \B_SIGNED 0
110785     parameter \B_WIDTH 1
110786     parameter \Y_WIDTH 1
110787     connect \A \main_litedram_wb_ack
110788     connect \B \main_converter_skip
110789     connect \Y $or$ls180.v:7950$2540_Y
110790   end
110791   attribute \src "ls180.v:8113.21-8113.74"
110792   cell $or $or$ls180.v:8113$2588
110793     parameter \A_SIGNED 0
110794     parameter \A_WIDTH 1
110795     parameter \B_SIGNED 0
110796     parameter \B_WIDTH 1
110797     parameter \Y_WIDTH 1
110798     connect \A $not$ls180.v:8113$2586_Y
110799     connect \B $not$ls180.v:8113$2587_Y
110800     connect \Y $or$ls180.v:8113$2588_Y
110801   end
110802   attribute \src "ls180.v:8148.21-8148.71"
110803   cell $or $or$ls180.v:8148$2593
110804     parameter \A_SIGNED 0
110805     parameter \A_WIDTH 1
110806     parameter \B_SIGNED 0
110807     parameter \B_WIDTH 1
110808     parameter \Y_WIDTH 1
110809     connect \A $not$ls180.v:8148$2591_Y
110810     connect \B $not$ls180.v:8148$2592_Y
110811     connect \Y $or$ls180.v:8148$2593_Y
110812   end
110813   attribute \src "ls180.v:8216.32-8216.85"
110814   cell $or $or$ls180.v:8216$2605
110815     parameter \A_SIGNED 0
110816     parameter \A_WIDTH 1
110817     parameter \B_SIGNED 0
110818     parameter \B_WIDTH 1
110819     parameter \Y_WIDTH 1
110820     connect \A \main_sdphy_cmdr_cmdr_start
110821     connect \B \main_sdphy_cmdr_cmdr_run
110822     connect \Y $or$ls180.v:8216$2605_Y
110823   end
110824   attribute \src "ls180.v:8222.8-8222.97"
110825   cell $or $or$ls180.v:8222$2607
110826     parameter \A_SIGNED 0
110827     parameter \A_WIDTH 1
110828     parameter \B_SIGNED 0
110829     parameter \B_WIDTH 1
110830     parameter \Y_WIDTH 1
110831     connect \A $eq$ls180.v:8222$2606_Y
110832     connect \B \main_sdphy_cmdr_cmdr_converter_sink_last
110833     connect \Y $or$ls180.v:8222$2607_Y
110834   end
110835   attribute \src "ls180.v:8239.52-8239.139"
110836   cell $or $or$ls180.v:8239$2612
110837     parameter \A_SIGNED 0
110838     parameter \A_WIDTH 1
110839     parameter \B_SIGNED 0
110840     parameter \B_WIDTH 1
110841     parameter \Y_WIDTH 1
110842     connect \A \main_sdphy_cmdr_cmdr_converter_sink_first
110843     connect \B \main_sdphy_cmdr_cmdr_converter_source_first
110844     connect \Y $or$ls180.v:8239$2612_Y
110845   end
110846   attribute \src "ls180.v:8240.51-8240.136"
110847   cell $or $or$ls180.v:8240$2613
110848     parameter \A_SIGNED 0
110849     parameter \A_WIDTH 1
110850     parameter \B_SIGNED 0
110851     parameter \B_WIDTH 1
110852     parameter \Y_WIDTH 1
110853     connect \A \main_sdphy_cmdr_cmdr_converter_sink_last
110854     connect \B \main_sdphy_cmdr_cmdr_converter_source_last
110855     connect \Y $or$ls180.v:8240$2613_Y
110856   end
110857   attribute \src "ls180.v:8274.7-8274.87"
110858   cell $or $or$ls180.v:8274$2616
110859     parameter \A_SIGNED 0
110860     parameter \A_WIDTH 1
110861     parameter \B_SIGNED 0
110862     parameter \B_WIDTH 1
110863     parameter \Y_WIDTH 1
110864     connect \A $not$ls180.v:8274$2615_Y
110865     connect \B \main_sdphy_cmdr_cmdr_buf_source_ready
110866     connect \Y $or$ls180.v:8274$2616_Y
110867   end
110868   attribute \src "ls180.v:8297.33-8297.88"
110869   cell $or $or$ls180.v:8297$2617
110870     parameter \A_SIGNED 0
110871     parameter \A_WIDTH 1
110872     parameter \B_SIGNED 0
110873     parameter \B_WIDTH 1
110874     parameter \Y_WIDTH 1
110875     connect \A \main_sdphy_dataw_crcr_start
110876     connect \B \main_sdphy_dataw_crcr_run
110877     connect \Y $or$ls180.v:8297$2617_Y
110878   end
110879   attribute \src "ls180.v:8303.8-8303.99"
110880   cell $or $or$ls180.v:8303$2619
110881     parameter \A_SIGNED 0
110882     parameter \A_WIDTH 1
110883     parameter \B_SIGNED 0
110884     parameter \B_WIDTH 1
110885     parameter \Y_WIDTH 1
110886     connect \A $eq$ls180.v:8303$2618_Y
110887     connect \B \main_sdphy_dataw_crcr_converter_sink_last
110888     connect \Y $or$ls180.v:8303$2619_Y
110889   end
110890   attribute \src "ls180.v:8320.53-8320.142"
110891   cell $or $or$ls180.v:8320$2624
110892     parameter \A_SIGNED 0
110893     parameter \A_WIDTH 1
110894     parameter \B_SIGNED 0
110895     parameter \B_WIDTH 1
110896     parameter \Y_WIDTH 1
110897     connect \A \main_sdphy_dataw_crcr_converter_sink_first
110898     connect \B \main_sdphy_dataw_crcr_converter_source_first
110899     connect \Y $or$ls180.v:8320$2624_Y
110900   end
110901   attribute \src "ls180.v:8321.52-8321.139"
110902   cell $or $or$ls180.v:8321$2625
110903     parameter \A_SIGNED 0
110904     parameter \A_WIDTH 1
110905     parameter \B_SIGNED 0
110906     parameter \B_WIDTH 1
110907     parameter \Y_WIDTH 1
110908     connect \A \main_sdphy_dataw_crcr_converter_sink_last
110909     connect \B \main_sdphy_dataw_crcr_converter_source_last
110910     connect \Y $or$ls180.v:8321$2625_Y
110911   end
110912   attribute \src "ls180.v:8355.7-8355.89"
110913   cell $or $or$ls180.v:8355$2628
110914     parameter \A_SIGNED 0
110915     parameter \A_WIDTH 1
110916     parameter \B_SIGNED 0
110917     parameter \B_WIDTH 1
110918     parameter \Y_WIDTH 1
110919     connect \A $not$ls180.v:8355$2627_Y
110920     connect \B \main_sdphy_dataw_crcr_buf_source_ready
110921     connect \Y $or$ls180.v:8355$2628_Y
110922   end
110923   attribute \src "ls180.v:8376.34-8376.91"
110924   cell $or $or$ls180.v:8376$2629
110925     parameter \A_SIGNED 0
110926     parameter \A_WIDTH 1
110927     parameter \B_SIGNED 0
110928     parameter \B_WIDTH 1
110929     parameter \Y_WIDTH 1
110930     connect \A \main_sdphy_datar_datar_start
110931     connect \B \main_sdphy_datar_datar_run
110932     connect \Y $or$ls180.v:8376$2629_Y
110933   end
110934   attribute \src "ls180.v:8382.8-8382.101"
110935   cell $or $or$ls180.v:8382$2631
110936     parameter \A_SIGNED 0
110937     parameter \A_WIDTH 1
110938     parameter \B_SIGNED 0
110939     parameter \B_WIDTH 1
110940     parameter \Y_WIDTH 1
110941     connect \A $eq$ls180.v:8382$2630_Y
110942     connect \B \main_sdphy_datar_datar_converter_sink_last
110943     connect \Y $or$ls180.v:8382$2631_Y
110944   end
110945   attribute \src "ls180.v:8399.54-8399.145"
110946   cell $or $or$ls180.v:8399$2636
110947     parameter \A_SIGNED 0
110948     parameter \A_WIDTH 1
110949     parameter \B_SIGNED 0
110950     parameter \B_WIDTH 1
110951     parameter \Y_WIDTH 1
110952     connect \A \main_sdphy_datar_datar_converter_sink_first
110953     connect \B \main_sdphy_datar_datar_converter_source_first
110954     connect \Y $or$ls180.v:8399$2636_Y
110955   end
110956   attribute \src "ls180.v:8400.53-8400.142"
110957   cell $or $or$ls180.v:8400$2637
110958     parameter \A_SIGNED 0
110959     parameter \A_WIDTH 1
110960     parameter \B_SIGNED 0
110961     parameter \B_WIDTH 1
110962     parameter \Y_WIDTH 1
110963     connect \A \main_sdphy_datar_datar_converter_sink_last
110964     connect \B \main_sdphy_datar_datar_converter_source_last
110965     connect \Y $or$ls180.v:8400$2637_Y
110966   end
110967   attribute \src "ls180.v:8416.7-8416.91"
110968   cell $or $or$ls180.v:8416$2640
110969     parameter \A_SIGNED 0
110970     parameter \A_WIDTH 1
110971     parameter \B_SIGNED 0
110972     parameter \B_WIDTH 1
110973     parameter \Y_WIDTH 1
110974     connect \A $not$ls180.v:8416$2639_Y
110975     connect \B \main_sdphy_datar_datar_buf_source_ready
110976     connect \Y $or$ls180.v:8416$2640_Y
110977   end
110978   attribute \src "ls180.v:8605.8-8605.89"
110979   cell $or $or$ls180.v:8605$2664
110980     parameter \A_SIGNED 0
110981     parameter \A_WIDTH 1
110982     parameter \B_SIGNED 0
110983     parameter \B_WIDTH 1
110984     parameter \Y_WIDTH 1
110985     connect \A $eq$ls180.v:8605$2663_Y
110986     connect \B \main_sdblock2mem_converter_sink_last
110987     connect \Y $or$ls180.v:8605$2664_Y
110988   end
110989   attribute \src "ls180.v:8622.48-8622.127"
110990   cell $or $or$ls180.v:8622$2669
110991     parameter \A_SIGNED 0
110992     parameter \A_WIDTH 1
110993     parameter \B_SIGNED 0
110994     parameter \B_WIDTH 1
110995     parameter \Y_WIDTH 1
110996     connect \A \main_sdblock2mem_converter_sink_first
110997     connect \B \main_sdblock2mem_converter_source_first
110998     connect \Y $or$ls180.v:8622$2669_Y
110999   end
111000   attribute \src "ls180.v:8623.47-8623.124"
111001   cell $or $or$ls180.v:8623$2670
111002     parameter \A_SIGNED 0
111003     parameter \A_WIDTH 1
111004     parameter \B_SIGNED 0
111005     parameter \B_WIDTH 1
111006     parameter \Y_WIDTH 1
111007     connect \A \main_sdblock2mem_converter_sink_last
111008     connect \B \main_sdblock2mem_converter_source_last
111009     connect \Y $or$ls180.v:8623$2670_Y
111010   end
111011   attribute \src "ls180.v:3182.46-3182.94"
111012   cell $sshl $sshl$ls180.v:3182$83
111013     parameter \A_SIGNED 0
111014     parameter \A_WIDTH 1
111015     parameter \B_SIGNED 0
111016     parameter \B_WIDTH 4
111017     parameter \Y_WIDTH 13
111018     connect \A \main_sdram_bankmachine0_auto_precharge
111019     connect \B 4'1010
111020     connect \Y $sshl$ls180.v:3182$83_Y
111021   end
111022   attribute \src "ls180.v:3339.46-3339.94"
111023   cell $sshl $sshl$ls180.v:3339$113
111024     parameter \A_SIGNED 0
111025     parameter \A_WIDTH 1
111026     parameter \B_SIGNED 0
111027     parameter \B_WIDTH 4
111028     parameter \Y_WIDTH 13
111029     connect \A \main_sdram_bankmachine1_auto_precharge
111030     connect \B 4'1010
111031     connect \Y $sshl$ls180.v:3339$113_Y
111032   end
111033   attribute \src "ls180.v:3496.46-3496.94"
111034   cell $sshl $sshl$ls180.v:3496$143
111035     parameter \A_SIGNED 0
111036     parameter \A_WIDTH 1
111037     parameter \B_SIGNED 0
111038     parameter \B_WIDTH 4
111039     parameter \Y_WIDTH 13
111040     connect \A \main_sdram_bankmachine2_auto_precharge
111041     connect \B 4'1010
111042     connect \Y $sshl$ls180.v:3496$143_Y
111043   end
111044   attribute \src "ls180.v:3653.46-3653.94"
111045   cell $sshl $sshl$ls180.v:3653$173
111046     parameter \A_SIGNED 0
111047     parameter \A_WIDTH 1
111048     parameter \B_SIGNED 0
111049     parameter \B_WIDTH 4
111050     parameter \Y_WIDTH 13
111051     connect \A \main_sdram_bankmachine3_auto_precharge
111052     connect \B 4'1010
111053     connect \Y $sshl$ls180.v:3653$173_Y
111054   end
111055   attribute \src "ls180.v:3213.63-3213.122"
111056   cell $sub $sub$ls180.v:3213$96
111057     parameter \A_SIGNED 0
111058     parameter \A_WIDTH 3
111059     parameter \B_SIGNED 0
111060     parameter \B_WIDTH 1
111061     parameter \Y_WIDTH 3
111062     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
111063     connect \B 1'1
111064     connect \Y $sub$ls180.v:3213$96_Y
111065   end
111066   attribute \src "ls180.v:3370.63-3370.122"
111067   cell $sub $sub$ls180.v:3370$126
111068     parameter \A_SIGNED 0
111069     parameter \A_WIDTH 3
111070     parameter \B_SIGNED 0
111071     parameter \B_WIDTH 1
111072     parameter \Y_WIDTH 3
111073     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
111074     connect \B 1'1
111075     connect \Y $sub$ls180.v:3370$126_Y
111076   end
111077   attribute \src "ls180.v:3527.63-3527.122"
111078   cell $sub $sub$ls180.v:3527$156
111079     parameter \A_SIGNED 0
111080     parameter \A_WIDTH 3
111081     parameter \B_SIGNED 0
111082     parameter \B_WIDTH 1
111083     parameter \Y_WIDTH 3
111084     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
111085     connect \B 1'1
111086     connect \Y $sub$ls180.v:3527$156_Y
111087   end
111088   attribute \src "ls180.v:3684.63-3684.122"
111089   cell $sub $sub$ls180.v:3684$186
111090     parameter \A_SIGNED 0
111091     parameter \A_WIDTH 3
111092     parameter \B_SIGNED 0
111093     parameter \B_WIDTH 1
111094     parameter \Y_WIDTH 3
111095     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
111096     connect \B 1'1
111097     connect \Y $sub$ls180.v:3684$186_Y
111098   end
111099   attribute \src "ls180.v:4090.38-4090.75"
111100   cell $sub $sub$ls180.v:4090$540
111101     parameter \A_SIGNED 0
111102     parameter \A_WIDTH 30
111103     parameter \B_SIGNED 0
111104     parameter \B_WIDTH 31
111105     parameter \Y_WIDTH 31
111106     connect \A \main_litedram_wb_adr
111107     connect \B 31'1001000000000000000000000000000
111108     connect \Y $sub$ls180.v:4090$540_Y
111109   end
111110   attribute \src "ls180.v:4176.36-4176.68"
111111   cell $sub $sub$ls180.v:4176$585
111112     parameter \A_SIGNED 0
111113     parameter \A_WIDTH 4
111114     parameter \B_SIGNED 0
111115     parameter \B_WIDTH 1
111116     parameter \Y_WIDTH 4
111117     connect \A \main_uart_tx_fifo_produce
111118     connect \B 1'1
111119     connect \Y $sub$ls180.v:4176$585_Y
111120   end
111121   attribute \src "ls180.v:4206.36-4206.68"
111122   cell $sub $sub$ls180.v:4206$596
111123     parameter \A_SIGNED 0
111124     parameter \A_WIDTH 4
111125     parameter \B_SIGNED 0
111126     parameter \B_WIDTH 1
111127     parameter \Y_WIDTH 4
111128     connect \A \main_uart_rx_fifo_produce
111129     connect \B 1'1
111130     connect \Y $sub$ls180.v:4206$596_Y
111131   end
111132   attribute \src "ls180.v:4231.70-4231.110"
111133   cell $sub $sub$ls180.v:4231$602
111134     parameter \A_SIGNED 0
111135     parameter \A_WIDTH 15
111136     parameter \B_SIGNED 0
111137     parameter \B_WIDTH 1
111138     parameter \Y_WIDTH 16
111139     connect \A \main_spimaster8_clk_divider [15:1]
111140     connect \B 1'1
111141     connect \Y $sub$ls180.v:4231$602_Y
111142   end
111143   attribute \src "ls180.v:4232.70-4232.104"
111144   cell $sub $sub$ls180.v:4232$604
111145     parameter \A_SIGNED 0
111146     parameter \A_WIDTH 16
111147     parameter \B_SIGNED 0
111148     parameter \B_WIDTH 1
111149     parameter \Y_WIDTH 16
111150     connect \A \main_spimaster8_clk_divider
111151     connect \B 1'1
111152     connect \Y $sub$ls180.v:4232$604_Y
111153   end
111154   attribute \src "ls180.v:4259.37-4259.66"
111155   cell $sub $sub$ls180.v:4259$608
111156     parameter \A_SIGNED 0
111157     parameter \A_WIDTH 8
111158     parameter \B_SIGNED 0
111159     parameter \B_WIDTH 1
111160     parameter \Y_WIDTH 8
111161     connect \A \main_spimaster1_length
111162     connect \B 1'1
111163     connect \Y $sub$ls180.v:4259$608_Y
111164   end
111165   attribute \src "ls180.v:4289.67-4289.107"
111166   cell $sub $sub$ls180.v:4289$610
111167     parameter \A_SIGNED 0
111168     parameter \A_WIDTH 15
111169     parameter \B_SIGNED 0
111170     parameter \B_WIDTH 1
111171     parameter \Y_WIDTH 16
111172     connect \A \main_spisdcard_clk_divider0 [15:1]
111173     connect \B 1'1
111174     connect \Y $sub$ls180.v:4289$610_Y
111175   end
111176   attribute \src "ls180.v:4290.67-4290.101"
111177   cell $sub $sub$ls180.v:4290$612
111178     parameter \A_SIGNED 0
111179     parameter \A_WIDTH 16
111180     parameter \B_SIGNED 0
111181     parameter \B_WIDTH 1
111182     parameter \Y_WIDTH 16
111183     connect \A \main_spisdcard_clk_divider0
111184     connect \B 1'1
111185     connect \Y $sub$ls180.v:4290$612_Y
111186   end
111187   attribute \src "ls180.v:4318.35-4318.64"
111188   cell $sub $sub$ls180.v:4318$616
111189     parameter \A_SIGNED 0
111190     parameter \A_WIDTH 8
111191     parameter \B_SIGNED 0
111192     parameter \B_WIDTH 1
111193     parameter \Y_WIDTH 8
111194     connect \A \main_spisdcard_length0
111195     connect \B 1'1
111196     connect \Y $sub$ls180.v:4318$616_Y
111197   end
111198   attribute \src "ls180.v:4572.60-4572.90"
111199   cell $sub $sub$ls180.v:4572$660
111200     parameter \A_SIGNED 0
111201     parameter \A_WIDTH 32
111202     parameter \B_SIGNED 0
111203     parameter \B_WIDTH 1
111204     parameter \Y_WIDTH 32
111205     connect \A \main_sdphy_cmdr_timeout
111206     connect \B 1'1
111207     connect \Y $sub$ls180.v:4572$660_Y
111208   end
111209   attribute \src "ls180.v:4583.62-4583.104"
111210   cell $sub $sub$ls180.v:4583$662
111211     parameter \A_SIGNED 0
111212     parameter \A_WIDTH 8
111213     parameter \B_SIGNED 0
111214     parameter \B_WIDTH 1
111215     parameter \Y_WIDTH 8
111216     connect \A \main_sdphy_cmdr_sink_payload_length
111217     connect \B 1'1
111218     connect \Y $sub$ls180.v:4583$662_Y
111219   end
111220   attribute \src "ls180.v:4600.60-4600.90"
111221   cell $sub $sub$ls180.v:4600$666
111222     parameter \A_SIGNED 0
111223     parameter \A_WIDTH 32
111224     parameter \B_SIGNED 0
111225     parameter \B_WIDTH 1
111226     parameter \Y_WIDTH 32
111227     connect \A \main_sdphy_cmdr_timeout
111228     connect \B 1'1
111229     connect \Y $sub$ls180.v:4600$666_Y
111230   end
111231   attribute \src "ls180.v:4829.62-4829.93"
111232   cell $sub $sub$ls180.v:4829$696
111233     parameter \A_SIGNED 0
111234     parameter \A_WIDTH 32
111235     parameter \B_SIGNED 0
111236     parameter \B_WIDTH 1
111237     parameter \Y_WIDTH 32
111238     connect \A \main_sdphy_datar_timeout
111239     connect \B 1'1
111240     connect \Y $sub$ls180.v:4829$696_Y
111241   end
111242   attribute \src "ls180.v:4834.62-4834.93"
111243   cell $sub $sub$ls180.v:4834$697
111244     parameter \A_SIGNED 0
111245     parameter \A_WIDTH 32
111246     parameter \B_SIGNED 0
111247     parameter \B_WIDTH 1
111248     parameter \Y_WIDTH 32
111249     connect \A \main_sdphy_datar_timeout
111250     connect \B 1'1
111251     connect \Y $sub$ls180.v:4834$697_Y
111252   end
111253   attribute \src "ls180.v:4845.64-4845.122"
111254   cell $sub $sub$ls180.v:4845$700
111255     parameter \A_SIGNED 0
111256     parameter \A_WIDTH 10
111257     parameter \B_SIGNED 0
111258     parameter \B_WIDTH 1
111259     parameter \Y_WIDTH 10
111260     connect \A $add$ls180.v:4845$699_Y
111261     connect \B 1'1
111262     connect \Y $sub$ls180.v:4845$700_Y
111263   end
111264   attribute \src "ls180.v:4866.62-4866.93"
111265   cell $sub $sub$ls180.v:4866$703
111266     parameter \A_SIGNED 0
111267     parameter \A_WIDTH 32
111268     parameter \B_SIGNED 0
111269     parameter \B_WIDTH 1
111270     parameter \Y_WIDTH 32
111271     connect \A \main_sdphy_datar_timeout
111272     connect \B 1'1
111273     connect \Y $sub$ls180.v:4866$703_Y
111274   end
111275   attribute \src "ls180.v:5328.37-5328.75"
111276   cell $sub $sub$ls180.v:5328$976
111277     parameter \A_SIGNED 0
111278     parameter \A_WIDTH 32
111279     parameter \B_SIGNED 0
111280     parameter \B_WIDTH 1
111281     parameter \Y_WIDTH 32
111282     connect \A \main_sdcore_block_count_storage
111283     connect \B 1'1
111284     connect \Y $sub$ls180.v:5328$976_Y
111285   end
111286   attribute \src "ls180.v:5343.62-5343.100"
111287   cell $sub $sub$ls180.v:5343$979
111288     parameter \A_SIGNED 0
111289     parameter \A_WIDTH 32
111290     parameter \B_SIGNED 0
111291     parameter \B_WIDTH 1
111292     parameter \Y_WIDTH 32
111293     connect \A \main_sdcore_block_count_storage
111294     connect \B 1'1
111295     connect \Y $sub$ls180.v:5343$979_Y
111296   end
111297   attribute \src "ls180.v:5354.39-5354.77"
111298   cell $sub $sub$ls180.v:5354$984
111299     parameter \A_SIGNED 0
111300     parameter \A_WIDTH 32
111301     parameter \B_SIGNED 0
111302     parameter \B_WIDTH 1
111303     parameter \Y_WIDTH 32
111304     connect \A \main_sdcore_block_count_storage
111305     connect \B 1'1
111306     connect \Y $sub$ls180.v:5354$984_Y
111307   end
111308   attribute \src "ls180.v:5429.40-5429.76"
111309   cell $sub $sub$ls180.v:5429$988
111310     parameter \A_SIGNED 0
111311     parameter \A_WIDTH 5
111312     parameter \B_SIGNED 0
111313     parameter \B_WIDTH 1
111314     parameter \Y_WIDTH 5
111315     connect \A \main_sdblock2mem_fifo_produce
111316     connect \B 1'1
111317     connect \Y $sub$ls180.v:5429$988_Y
111318   end
111319   attribute \src "ls180.v:5478.56-5478.104"
111320   cell $sub $sub$ls180.v:5478$1002
111321     parameter \A_SIGNED 0
111322     parameter \A_WIDTH 32
111323     parameter \B_SIGNED 0
111324     parameter \B_WIDTH 1
111325     parameter \Y_WIDTH 32
111326     connect \A \main_sdblock2mem_wishbonedmawriter_length
111327     connect \B 1'1
111328     connect \Y $sub$ls180.v:5478$1002_Y
111329   end
111330   attribute \src "ls180.v:5568.71-5568.105"
111331   cell $sub $sub$ls180.v:5568$1008
111332     parameter \A_SIGNED 0
111333     parameter \A_WIDTH 32
111334     parameter \B_SIGNED 0
111335     parameter \B_WIDTH 1
111336     parameter \Y_WIDTH 32
111337     connect \A \main_sdmem2block_dma_length
111338     connect \B 1'1
111339     connect \Y $sub$ls180.v:5568$1008_Y
111340   end
111341   attribute \src "ls180.v:5637.40-5637.76"
111342   cell $sub $sub$ls180.v:5637$1019
111343     parameter \A_SIGNED 0
111344     parameter \A_WIDTH 5
111345     parameter \B_SIGNED 0
111346     parameter \B_WIDTH 1
111347     parameter \Y_WIDTH 5
111348     connect \A \main_sdmem2block_fifo_produce
111349     connect \B 1'1
111350     connect \Y $sub$ls180.v:5637$1019_Y
111351   end
111352   attribute \src "ls180.v:7514.31-7514.60"
111353   cell $sub $sub$ls180.v:7514$2420
111354     parameter \A_SIGNED 0
111355     parameter \A_WIDTH 32
111356     parameter \B_SIGNED 0
111357     parameter \B_WIDTH 1
111358     parameter \Y_WIDTH 32
111359     connect \A \main_libresocsim_value
111360     connect \B 1'1
111361     connect \Y $sub$ls180.v:7514$2420_Y
111362   end
111363   attribute \src "ls180.v:7535.31-7535.61"
111364   cell $sub $sub$ls180.v:7535$2425
111365     parameter \A_SIGNED 0
111366     parameter \A_WIDTH 10
111367     parameter \B_SIGNED 0
111368     parameter \B_WIDTH 1
111369     parameter \Y_WIDTH 10
111370     connect \A \main_sdram_timer_count1
111371     connect \B 1'1
111372     connect \Y $sub$ls180.v:7535$2425_Y
111373   end
111374   attribute \src "ls180.v:7541.34-7541.67"
111375   cell $sub $sub$ls180.v:7541$2426
111376     parameter \A_SIGNED 0
111377     parameter \A_WIDTH 1
111378     parameter \B_SIGNED 0
111379     parameter \B_WIDTH 1
111380     parameter \Y_WIDTH 1
111381     connect \A \main_sdram_postponer_count
111382     connect \B 1'1
111383     connect \Y $sub$ls180.v:7541$2426_Y
111384   end
111385   attribute \src "ls180.v:7552.36-7552.69"
111386   cell $sub $sub$ls180.v:7552$2429
111387     parameter \A_SIGNED 0
111388     parameter \A_WIDTH 1
111389     parameter \B_SIGNED 0
111390     parameter \B_WIDTH 1
111391     parameter \Y_WIDTH 1
111392     connect \A \main_sdram_sequencer_count
111393     connect \B 1'1
111394     connect \Y $sub$ls180.v:7552$2429_Y
111395   end
111396   attribute \src "ls180.v:7616.59-7616.116"
111397   cell $sub $sub$ls180.v:7616$2447
111398     parameter \A_SIGNED 0
111399     parameter \A_WIDTH 4
111400     parameter \B_SIGNED 0
111401     parameter \B_WIDTH 1
111402     parameter \Y_WIDTH 4
111403     connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level
111404     connect \B 1'1
111405     connect \Y $sub$ls180.v:7616$2447_Y
111406   end
111407   attribute \src "ls180.v:7635.46-7635.90"
111408   cell $sub $sub$ls180.v:7635$2451
111409     parameter \A_SIGNED 0
111410     parameter \A_WIDTH 3
111411     parameter \B_SIGNED 0
111412     parameter \B_WIDTH 1
111413     parameter \Y_WIDTH 3
111414     connect \A \main_sdram_bankmachine0_twtpcon_count
111415     connect \B 1'1
111416     connect \Y $sub$ls180.v:7635$2451_Y
111417   end
111418   attribute \src "ls180.v:7662.59-7662.116"
111419   cell $sub $sub$ls180.v:7662$2463
111420     parameter \A_SIGNED 0
111421     parameter \A_WIDTH 4
111422     parameter \B_SIGNED 0
111423     parameter \B_WIDTH 1
111424     parameter \Y_WIDTH 4
111425     connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level
111426     connect \B 1'1
111427     connect \Y $sub$ls180.v:7662$2463_Y
111428   end
111429   attribute \src "ls180.v:7681.46-7681.90"
111430   cell $sub $sub$ls180.v:7681$2467
111431     parameter \A_SIGNED 0
111432     parameter \A_WIDTH 3
111433     parameter \B_SIGNED 0
111434     parameter \B_WIDTH 1
111435     parameter \Y_WIDTH 3
111436     connect \A \main_sdram_bankmachine1_twtpcon_count
111437     connect \B 1'1
111438     connect \Y $sub$ls180.v:7681$2467_Y
111439   end
111440   attribute \src "ls180.v:7708.59-7708.116"
111441   cell $sub $sub$ls180.v:7708$2479
111442     parameter \A_SIGNED 0
111443     parameter \A_WIDTH 4
111444     parameter \B_SIGNED 0
111445     parameter \B_WIDTH 1
111446     parameter \Y_WIDTH 4
111447     connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level
111448     connect \B 1'1
111449     connect \Y $sub$ls180.v:7708$2479_Y
111450   end
111451   attribute \src "ls180.v:7727.46-7727.90"
111452   cell $sub $sub$ls180.v:7727$2483
111453     parameter \A_SIGNED 0
111454     parameter \A_WIDTH 3
111455     parameter \B_SIGNED 0
111456     parameter \B_WIDTH 1
111457     parameter \Y_WIDTH 3
111458     connect \A \main_sdram_bankmachine2_twtpcon_count
111459     connect \B 1'1
111460     connect \Y $sub$ls180.v:7727$2483_Y
111461   end
111462   attribute \src "ls180.v:7754.59-7754.116"
111463   cell $sub $sub$ls180.v:7754$2495
111464     parameter \A_SIGNED 0
111465     parameter \A_WIDTH 4
111466     parameter \B_SIGNED 0
111467     parameter \B_WIDTH 1
111468     parameter \Y_WIDTH 4
111469     connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level
111470     connect \B 1'1
111471     connect \Y $sub$ls180.v:7754$2495_Y
111472   end
111473   attribute \src "ls180.v:7773.46-7773.90"
111474   cell $sub $sub$ls180.v:7773$2499
111475     parameter \A_SIGNED 0
111476     parameter \A_WIDTH 3
111477     parameter \B_SIGNED 0
111478     parameter \B_WIDTH 1
111479     parameter \Y_WIDTH 3
111480     connect \A \main_sdram_bankmachine3_twtpcon_count
111481     connect \B 1'1
111482     connect \Y $sub$ls180.v:7773$2499_Y
111483   end
111484   attribute \src "ls180.v:7784.25-7784.48"
111485   cell $sub $sub$ls180.v:7784$2503
111486     parameter \A_SIGNED 0
111487     parameter \A_WIDTH 5
111488     parameter \B_SIGNED 0
111489     parameter \B_WIDTH 1
111490     parameter \Y_WIDTH 5
111491     connect \A \main_sdram_time0
111492     connect \B 1'1
111493     connect \Y $sub$ls180.v:7784$2503_Y
111494   end
111495   attribute \src "ls180.v:7791.25-7791.48"
111496   cell $sub $sub$ls180.v:7791$2506
111497     parameter \A_SIGNED 0
111498     parameter \A_WIDTH 4
111499     parameter \B_SIGNED 0
111500     parameter \B_WIDTH 1
111501     parameter \Y_WIDTH 4
111502     connect \A \main_sdram_time1
111503     connect \B 1'1
111504     connect \Y $sub$ls180.v:7791$2506_Y
111505   end
111506   attribute \src "ls180.v:7923.33-7923.64"
111507   cell $sub $sub$ls180.v:7923$2511
111508     parameter \A_SIGNED 0
111509     parameter \A_WIDTH 1
111510     parameter \B_SIGNED 0
111511     parameter \B_WIDTH 1
111512     parameter \Y_WIDTH 1
111513     connect \A \main_sdram_tccdcon_count
111514     connect \B 1'1
111515     connect \Y $sub$ls180.v:7923$2511_Y
111516   end
111517   attribute \src "ls180.v:7938.33-7938.64"
111518   cell $sub $sub$ls180.v:7938$2514
111519     parameter \A_SIGNED 0
111520     parameter \A_WIDTH 3
111521     parameter \B_SIGNED 0
111522     parameter \B_WIDTH 1
111523     parameter \Y_WIDTH 3
111524     connect \A \main_sdram_twtrcon_count
111525     connect \B 1'1
111526     connect \Y $sub$ls180.v:7938$2514_Y
111527   end
111528   attribute \src "ls180.v:8065.33-8065.64"
111529   cell $sub $sub$ls180.v:8065$2573
111530     parameter \A_SIGNED 0
111531     parameter \A_WIDTH 5
111532     parameter \B_SIGNED 0
111533     parameter \B_WIDTH 1
111534     parameter \Y_WIDTH 5
111535     connect \A \main_uart_tx_fifo_level0
111536     connect \B 1'1
111537     connect \Y $sub$ls180.v:8065$2573_Y
111538   end
111539   attribute \src "ls180.v:8087.33-8087.64"
111540   cell $sub $sub$ls180.v:8087$2584
111541     parameter \A_SIGNED 0
111542     parameter \A_WIDTH 5
111543     parameter \B_SIGNED 0
111544     parameter \B_WIDTH 1
111545     parameter \Y_WIDTH 5
111546     connect \A \main_uart_rx_fifo_level0
111547     connect \B 1'1
111548     connect \Y $sub$ls180.v:8087$2584_Y
111549   end
111550   attribute \src "ls180.v:8122.34-8122.66"
111551   cell $sub $sub$ls180.v:8122$2589
111552     parameter \A_SIGNED 0
111553     parameter \A_WIDTH 3
111554     parameter \B_SIGNED 0
111555     parameter \B_WIDTH 1
111556     parameter \Y_WIDTH 3
111557     connect \A \main_spimaster34_mosi_sel
111558     connect \B 1'1
111559     connect \Y $sub$ls180.v:8122$2589_Y
111560   end
111561   attribute \src "ls180.v:8157.32-8157.62"
111562   cell $sub $sub$ls180.v:8157$2594
111563     parameter \A_SIGNED 0
111564     parameter \A_WIDTH 3
111565     parameter \B_SIGNED 0
111566     parameter \B_WIDTH 1
111567     parameter \Y_WIDTH 3
111568     connect \A \main_spisdcard_mosi_sel
111569     connect \B 1'1
111570     connect \Y $sub$ls180.v:8157$2594_Y
111571   end
111572   attribute \src "ls180.v:8181.30-8181.53"
111573   cell $sub $sub$ls180.v:8181$2597
111574     parameter \A_SIGNED 0
111575     parameter \A_WIDTH 32
111576     parameter \B_SIGNED 0
111577     parameter \B_WIDTH 1
111578     parameter \Y_WIDTH 32
111579     connect \A \main_pwm0_period
111580     connect \B 1'1
111581     connect \Y $sub$ls180.v:8181$2597_Y
111582   end
111583   attribute \src "ls180.v:8195.30-8195.53"
111584   cell $sub $sub$ls180.v:8195$2601
111585     parameter \A_SIGNED 0
111586     parameter \A_WIDTH 32
111587     parameter \B_SIGNED 0
111588     parameter \B_WIDTH 1
111589     parameter \Y_WIDTH 32
111590     connect \A \main_pwm1_period
111591     connect \B 1'1
111592     connect \Y $sub$ls180.v:8195$2601_Y
111593   end
111594   attribute \src "ls180.v:8598.36-8598.70"
111595   cell $sub $sub$ls180.v:8598$2662
111596     parameter \A_SIGNED 0
111597     parameter \A_WIDTH 6
111598     parameter \B_SIGNED 0
111599     parameter \B_WIDTH 1
111600     parameter \Y_WIDTH 6
111601     connect \A \main_sdblock2mem_fifo_level
111602     connect \B 1'1
111603     connect \Y $sub$ls180.v:8598$2662_Y
111604   end
111605   attribute \src "ls180.v:8684.36-8684.70"
111606   cell $sub $sub$ls180.v:8684$2684
111607     parameter \A_SIGNED 0
111608     parameter \A_WIDTH 6
111609     parameter \B_SIGNED 0
111610     parameter \B_WIDTH 1
111611     parameter \Y_WIDTH 6
111612     connect \A \main_sdmem2block_fifo_level
111613     connect \B 1'1
111614     connect \Y $sub$ls180.v:8684$2684_Y
111615   end
111616   attribute \src "ls180.v:8797.22-8797.42"
111617   cell $sub $sub$ls180.v:8797$2691
111618     parameter \A_SIGNED 0
111619     parameter \A_WIDTH 20
111620     parameter \B_SIGNED 0
111621     parameter \B_WIDTH 1
111622     parameter \Y_WIDTH 20
111623     connect \A \builder_count
111624     connect \B 1'1
111625     connect \Y $sub$ls180.v:8797$2691_Y
111626   end
111627   attribute \src "ls180.v:4926.353-4926.425"
111628   cell $xor $xor$ls180.v:4926$710
111629     parameter \A_SIGNED 0
111630     parameter \A_WIDTH 1
111631     parameter \B_SIGNED 0
111632     parameter \B_WIDTH 1
111633     parameter \Y_WIDTH 1
111634     connect \A \main_sdcore_crc7_inserter_val [39]
111635     connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
111636     connect \Y $xor$ls180.v:4926$710_Y
111637   end
111638   attribute \src "ls180.v:4926.200-4926.272"
111639   cell $xor $xor$ls180.v:4926$711
111640     parameter \A_SIGNED 0
111641     parameter \A_WIDTH 1
111642     parameter \B_SIGNED 0
111643     parameter \B_WIDTH 1
111644     parameter \Y_WIDTH 1
111645     connect \A \main_sdcore_crc7_inserter_val [39]
111646     connect \B \main_sdcore_crc7_inserter_crcreg0 [6]
111647     connect \Y $xor$ls180.v:4926$711_Y
111648   end
111649   attribute \src "ls180.v:4926.160-4926.273"
111650   cell $xor $xor$ls180.v:4926$712
111651     parameter \A_SIGNED 0
111652     parameter \A_WIDTH 1
111653     parameter \B_SIGNED 0
111654     parameter \B_WIDTH 1
111655     parameter \Y_WIDTH 1
111656     connect \A \main_sdcore_crc7_inserter_crcreg0 [2]
111657     connect \B $xor$ls180.v:4926$711_Y
111658     connect \Y $xor$ls180.v:4926$712_Y
111659   end
111660   attribute \src "ls180.v:4927.353-4927.425"
111661   cell $xor $xor$ls180.v:4927$713
111662     parameter \A_SIGNED 0
111663     parameter \A_WIDTH 1
111664     parameter \B_SIGNED 0
111665     parameter \B_WIDTH 1
111666     parameter \Y_WIDTH 1
111667     connect \A \main_sdcore_crc7_inserter_val [38]
111668     connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
111669     connect \Y $xor$ls180.v:4927$713_Y
111670   end
111671   attribute \src "ls180.v:4927.200-4927.272"
111672   cell $xor $xor$ls180.v:4927$714
111673     parameter \A_SIGNED 0
111674     parameter \A_WIDTH 1
111675     parameter \B_SIGNED 0
111676     parameter \B_WIDTH 1
111677     parameter \Y_WIDTH 1
111678     connect \A \main_sdcore_crc7_inserter_val [38]
111679     connect \B \main_sdcore_crc7_inserter_crcreg1 [6]
111680     connect \Y $xor$ls180.v:4927$714_Y
111681   end
111682   attribute \src "ls180.v:4927.160-4927.273"
111683   cell $xor $xor$ls180.v:4927$715
111684     parameter \A_SIGNED 0
111685     parameter \A_WIDTH 1
111686     parameter \B_SIGNED 0
111687     parameter \B_WIDTH 1
111688     parameter \Y_WIDTH 1
111689     connect \A \main_sdcore_crc7_inserter_crcreg1 [2]
111690     connect \B $xor$ls180.v:4927$714_Y
111691     connect \Y $xor$ls180.v:4927$715_Y
111692   end
111693   attribute \src "ls180.v:4928.353-4928.425"
111694   cell $xor $xor$ls180.v:4928$716
111695     parameter \A_SIGNED 0
111696     parameter \A_WIDTH 1
111697     parameter \B_SIGNED 0
111698     parameter \B_WIDTH 1
111699     parameter \Y_WIDTH 1
111700     connect \A \main_sdcore_crc7_inserter_val [37]
111701     connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
111702     connect \Y $xor$ls180.v:4928$716_Y
111703   end
111704   attribute \src "ls180.v:4928.200-4928.272"
111705   cell $xor $xor$ls180.v:4928$717
111706     parameter \A_SIGNED 0
111707     parameter \A_WIDTH 1
111708     parameter \B_SIGNED 0
111709     parameter \B_WIDTH 1
111710     parameter \Y_WIDTH 1
111711     connect \A \main_sdcore_crc7_inserter_val [37]
111712     connect \B \main_sdcore_crc7_inserter_crcreg2 [6]
111713     connect \Y $xor$ls180.v:4928$717_Y
111714   end
111715   attribute \src "ls180.v:4928.160-4928.273"
111716   cell $xor $xor$ls180.v:4928$718
111717     parameter \A_SIGNED 0
111718     parameter \A_WIDTH 1
111719     parameter \B_SIGNED 0
111720     parameter \B_WIDTH 1
111721     parameter \Y_WIDTH 1
111722     connect \A \main_sdcore_crc7_inserter_crcreg2 [2]
111723     connect \B $xor$ls180.v:4928$717_Y
111724     connect \Y $xor$ls180.v:4928$718_Y
111725   end
111726   attribute \src "ls180.v:4929.353-4929.425"
111727   cell $xor $xor$ls180.v:4929$719
111728     parameter \A_SIGNED 0
111729     parameter \A_WIDTH 1
111730     parameter \B_SIGNED 0
111731     parameter \B_WIDTH 1
111732     parameter \Y_WIDTH 1
111733     connect \A \main_sdcore_crc7_inserter_val [36]
111734     connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
111735     connect \Y $xor$ls180.v:4929$719_Y
111736   end
111737   attribute \src "ls180.v:4929.200-4929.272"
111738   cell $xor $xor$ls180.v:4929$720
111739     parameter \A_SIGNED 0
111740     parameter \A_WIDTH 1
111741     parameter \B_SIGNED 0
111742     parameter \B_WIDTH 1
111743     parameter \Y_WIDTH 1
111744     connect \A \main_sdcore_crc7_inserter_val [36]
111745     connect \B \main_sdcore_crc7_inserter_crcreg3 [6]
111746     connect \Y $xor$ls180.v:4929$720_Y
111747   end
111748   attribute \src "ls180.v:4929.160-4929.273"
111749   cell $xor $xor$ls180.v:4929$721
111750     parameter \A_SIGNED 0
111751     parameter \A_WIDTH 1
111752     parameter \B_SIGNED 0
111753     parameter \B_WIDTH 1
111754     parameter \Y_WIDTH 1
111755     connect \A \main_sdcore_crc7_inserter_crcreg3 [2]
111756     connect \B $xor$ls180.v:4929$720_Y
111757     connect \Y $xor$ls180.v:4929$721_Y
111758   end
111759   attribute \src "ls180.v:4930.353-4930.425"
111760   cell $xor $xor$ls180.v:4930$722
111761     parameter \A_SIGNED 0
111762     parameter \A_WIDTH 1
111763     parameter \B_SIGNED 0
111764     parameter \B_WIDTH 1
111765     parameter \Y_WIDTH 1
111766     connect \A \main_sdcore_crc7_inserter_val [35]
111767     connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
111768     connect \Y $xor$ls180.v:4930$722_Y
111769   end
111770   attribute \src "ls180.v:4930.200-4930.272"
111771   cell $xor $xor$ls180.v:4930$723
111772     parameter \A_SIGNED 0
111773     parameter \A_WIDTH 1
111774     parameter \B_SIGNED 0
111775     parameter \B_WIDTH 1
111776     parameter \Y_WIDTH 1
111777     connect \A \main_sdcore_crc7_inserter_val [35]
111778     connect \B \main_sdcore_crc7_inserter_crcreg4 [6]
111779     connect \Y $xor$ls180.v:4930$723_Y
111780   end
111781   attribute \src "ls180.v:4930.160-4930.273"
111782   cell $xor $xor$ls180.v:4930$724
111783     parameter \A_SIGNED 0
111784     parameter \A_WIDTH 1
111785     parameter \B_SIGNED 0
111786     parameter \B_WIDTH 1
111787     parameter \Y_WIDTH 1
111788     connect \A \main_sdcore_crc7_inserter_crcreg4 [2]
111789     connect \B $xor$ls180.v:4930$723_Y
111790     connect \Y $xor$ls180.v:4930$724_Y
111791   end
111792   attribute \src "ls180.v:4931.353-4931.425"
111793   cell $xor $xor$ls180.v:4931$725
111794     parameter \A_SIGNED 0
111795     parameter \A_WIDTH 1
111796     parameter \B_SIGNED 0
111797     parameter \B_WIDTH 1
111798     parameter \Y_WIDTH 1
111799     connect \A \main_sdcore_crc7_inserter_val [34]
111800     connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
111801     connect \Y $xor$ls180.v:4931$725_Y
111802   end
111803   attribute \src "ls180.v:4931.200-4931.272"
111804   cell $xor $xor$ls180.v:4931$726
111805     parameter \A_SIGNED 0
111806     parameter \A_WIDTH 1
111807     parameter \B_SIGNED 0
111808     parameter \B_WIDTH 1
111809     parameter \Y_WIDTH 1
111810     connect \A \main_sdcore_crc7_inserter_val [34]
111811     connect \B \main_sdcore_crc7_inserter_crcreg5 [6]
111812     connect \Y $xor$ls180.v:4931$726_Y
111813   end
111814   attribute \src "ls180.v:4931.160-4931.273"
111815   cell $xor $xor$ls180.v:4931$727
111816     parameter \A_SIGNED 0
111817     parameter \A_WIDTH 1
111818     parameter \B_SIGNED 0
111819     parameter \B_WIDTH 1
111820     parameter \Y_WIDTH 1
111821     connect \A \main_sdcore_crc7_inserter_crcreg5 [2]
111822     connect \B $xor$ls180.v:4931$726_Y
111823     connect \Y $xor$ls180.v:4931$727_Y
111824   end
111825   attribute \src "ls180.v:4932.353-4932.425"
111826   cell $xor $xor$ls180.v:4932$728
111827     parameter \A_SIGNED 0
111828     parameter \A_WIDTH 1
111829     parameter \B_SIGNED 0
111830     parameter \B_WIDTH 1
111831     parameter \Y_WIDTH 1
111832     connect \A \main_sdcore_crc7_inserter_val [33]
111833     connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
111834     connect \Y $xor$ls180.v:4932$728_Y
111835   end
111836   attribute \src "ls180.v:4932.200-4932.272"
111837   cell $xor $xor$ls180.v:4932$729
111838     parameter \A_SIGNED 0
111839     parameter \A_WIDTH 1
111840     parameter \B_SIGNED 0
111841     parameter \B_WIDTH 1
111842     parameter \Y_WIDTH 1
111843     connect \A \main_sdcore_crc7_inserter_val [33]
111844     connect \B \main_sdcore_crc7_inserter_crcreg6 [6]
111845     connect \Y $xor$ls180.v:4932$729_Y
111846   end
111847   attribute \src "ls180.v:4932.160-4932.273"
111848   cell $xor $xor$ls180.v:4932$730
111849     parameter \A_SIGNED 0
111850     parameter \A_WIDTH 1
111851     parameter \B_SIGNED 0
111852     parameter \B_WIDTH 1
111853     parameter \Y_WIDTH 1
111854     connect \A \main_sdcore_crc7_inserter_crcreg6 [2]
111855     connect \B $xor$ls180.v:4932$729_Y
111856     connect \Y $xor$ls180.v:4932$730_Y
111857   end
111858   attribute \src "ls180.v:4933.353-4933.425"
111859   cell $xor $xor$ls180.v:4933$731
111860     parameter \A_SIGNED 0
111861     parameter \A_WIDTH 1
111862     parameter \B_SIGNED 0
111863     parameter \B_WIDTH 1
111864     parameter \Y_WIDTH 1
111865     connect \A \main_sdcore_crc7_inserter_val [32]
111866     connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
111867     connect \Y $xor$ls180.v:4933$731_Y
111868   end
111869   attribute \src "ls180.v:4933.200-4933.272"
111870   cell $xor $xor$ls180.v:4933$732
111871     parameter \A_SIGNED 0
111872     parameter \A_WIDTH 1
111873     parameter \B_SIGNED 0
111874     parameter \B_WIDTH 1
111875     parameter \Y_WIDTH 1
111876     connect \A \main_sdcore_crc7_inserter_val [32]
111877     connect \B \main_sdcore_crc7_inserter_crcreg7 [6]
111878     connect \Y $xor$ls180.v:4933$732_Y
111879   end
111880   attribute \src "ls180.v:4933.160-4933.273"
111881   cell $xor $xor$ls180.v:4933$733
111882     parameter \A_SIGNED 0
111883     parameter \A_WIDTH 1
111884     parameter \B_SIGNED 0
111885     parameter \B_WIDTH 1
111886     parameter \Y_WIDTH 1
111887     connect \A \main_sdcore_crc7_inserter_crcreg7 [2]
111888     connect \B $xor$ls180.v:4933$732_Y
111889     connect \Y $xor$ls180.v:4933$733_Y
111890   end
111891   attribute \src "ls180.v:4934.353-4934.425"
111892   cell $xor $xor$ls180.v:4934$734
111893     parameter \A_SIGNED 0
111894     parameter \A_WIDTH 1
111895     parameter \B_SIGNED 0
111896     parameter \B_WIDTH 1
111897     parameter \Y_WIDTH 1
111898     connect \A \main_sdcore_crc7_inserter_val [31]
111899     connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
111900     connect \Y $xor$ls180.v:4934$734_Y
111901   end
111902   attribute \src "ls180.v:4934.200-4934.272"
111903   cell $xor $xor$ls180.v:4934$735
111904     parameter \A_SIGNED 0
111905     parameter \A_WIDTH 1
111906     parameter \B_SIGNED 0
111907     parameter \B_WIDTH 1
111908     parameter \Y_WIDTH 1
111909     connect \A \main_sdcore_crc7_inserter_val [31]
111910     connect \B \main_sdcore_crc7_inserter_crcreg8 [6]
111911     connect \Y $xor$ls180.v:4934$735_Y
111912   end
111913   attribute \src "ls180.v:4934.160-4934.273"
111914   cell $xor $xor$ls180.v:4934$736
111915     parameter \A_SIGNED 0
111916     parameter \A_WIDTH 1
111917     parameter \B_SIGNED 0
111918     parameter \B_WIDTH 1
111919     parameter \Y_WIDTH 1
111920     connect \A \main_sdcore_crc7_inserter_crcreg8 [2]
111921     connect \B $xor$ls180.v:4934$735_Y
111922     connect \Y $xor$ls180.v:4934$736_Y
111923   end
111924   attribute \src "ls180.v:4935.354-4935.426"
111925   cell $xor $xor$ls180.v:4935$737
111926     parameter \A_SIGNED 0
111927     parameter \A_WIDTH 1
111928     parameter \B_SIGNED 0
111929     parameter \B_WIDTH 1
111930     parameter \Y_WIDTH 1
111931     connect \A \main_sdcore_crc7_inserter_val [30]
111932     connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
111933     connect \Y $xor$ls180.v:4935$737_Y
111934   end
111935   attribute \src "ls180.v:4935.201-4935.273"
111936   cell $xor $xor$ls180.v:4935$738
111937     parameter \A_SIGNED 0
111938     parameter \A_WIDTH 1
111939     parameter \B_SIGNED 0
111940     parameter \B_WIDTH 1
111941     parameter \Y_WIDTH 1
111942     connect \A \main_sdcore_crc7_inserter_val [30]
111943     connect \B \main_sdcore_crc7_inserter_crcreg9 [6]
111944     connect \Y $xor$ls180.v:4935$738_Y
111945   end
111946   attribute \src "ls180.v:4935.161-4935.274"
111947   cell $xor $xor$ls180.v:4935$739
111948     parameter \A_SIGNED 0
111949     parameter \A_WIDTH 1
111950     parameter \B_SIGNED 0
111951     parameter \B_WIDTH 1
111952     parameter \Y_WIDTH 1
111953     connect \A \main_sdcore_crc7_inserter_crcreg9 [2]
111954     connect \B $xor$ls180.v:4935$738_Y
111955     connect \Y $xor$ls180.v:4935$739_Y
111956   end
111957   attribute \src "ls180.v:4936.361-4936.434"
111958   cell $xor $xor$ls180.v:4936$740
111959     parameter \A_SIGNED 0
111960     parameter \A_WIDTH 1
111961     parameter \B_SIGNED 0
111962     parameter \B_WIDTH 1
111963     parameter \Y_WIDTH 1
111964     connect \A \main_sdcore_crc7_inserter_val [29]
111965     connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
111966     connect \Y $xor$ls180.v:4936$740_Y
111967   end
111968   attribute \src "ls180.v:4936.205-4936.278"
111969   cell $xor $xor$ls180.v:4936$741
111970     parameter \A_SIGNED 0
111971     parameter \A_WIDTH 1
111972     parameter \B_SIGNED 0
111973     parameter \B_WIDTH 1
111974     parameter \Y_WIDTH 1
111975     connect \A \main_sdcore_crc7_inserter_val [29]
111976     connect \B \main_sdcore_crc7_inserter_crcreg10 [6]
111977     connect \Y $xor$ls180.v:4936$741_Y
111978   end
111979   attribute \src "ls180.v:4936.164-4936.279"
111980   cell $xor $xor$ls180.v:4936$742
111981     parameter \A_SIGNED 0
111982     parameter \A_WIDTH 1
111983     parameter \B_SIGNED 0
111984     parameter \B_WIDTH 1
111985     parameter \Y_WIDTH 1
111986     connect \A \main_sdcore_crc7_inserter_crcreg10 [2]
111987     connect \B $xor$ls180.v:4936$741_Y
111988     connect \Y $xor$ls180.v:4936$742_Y
111989   end
111990   attribute \src "ls180.v:4937.361-4937.434"
111991   cell $xor $xor$ls180.v:4937$743
111992     parameter \A_SIGNED 0
111993     parameter \A_WIDTH 1
111994     parameter \B_SIGNED 0
111995     parameter \B_WIDTH 1
111996     parameter \Y_WIDTH 1
111997     connect \A \main_sdcore_crc7_inserter_val [28]
111998     connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
111999     connect \Y $xor$ls180.v:4937$743_Y
112000   end
112001   attribute \src "ls180.v:4937.205-4937.278"
112002   cell $xor $xor$ls180.v:4937$744
112003     parameter \A_SIGNED 0
112004     parameter \A_WIDTH 1
112005     parameter \B_SIGNED 0
112006     parameter \B_WIDTH 1
112007     parameter \Y_WIDTH 1
112008     connect \A \main_sdcore_crc7_inserter_val [28]
112009     connect \B \main_sdcore_crc7_inserter_crcreg11 [6]
112010     connect \Y $xor$ls180.v:4937$744_Y
112011   end
112012   attribute \src "ls180.v:4937.164-4937.279"
112013   cell $xor $xor$ls180.v:4937$745
112014     parameter \A_SIGNED 0
112015     parameter \A_WIDTH 1
112016     parameter \B_SIGNED 0
112017     parameter \B_WIDTH 1
112018     parameter \Y_WIDTH 1
112019     connect \A \main_sdcore_crc7_inserter_crcreg11 [2]
112020     connect \B $xor$ls180.v:4937$744_Y
112021     connect \Y $xor$ls180.v:4937$745_Y
112022   end
112023   attribute \src "ls180.v:4938.361-4938.434"
112024   cell $xor $xor$ls180.v:4938$746
112025     parameter \A_SIGNED 0
112026     parameter \A_WIDTH 1
112027     parameter \B_SIGNED 0
112028     parameter \B_WIDTH 1
112029     parameter \Y_WIDTH 1
112030     connect \A \main_sdcore_crc7_inserter_val [27]
112031     connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
112032     connect \Y $xor$ls180.v:4938$746_Y
112033   end
112034   attribute \src "ls180.v:4938.205-4938.278"
112035   cell $xor $xor$ls180.v:4938$747
112036     parameter \A_SIGNED 0
112037     parameter \A_WIDTH 1
112038     parameter \B_SIGNED 0
112039     parameter \B_WIDTH 1
112040     parameter \Y_WIDTH 1
112041     connect \A \main_sdcore_crc7_inserter_val [27]
112042     connect \B \main_sdcore_crc7_inserter_crcreg12 [6]
112043     connect \Y $xor$ls180.v:4938$747_Y
112044   end
112045   attribute \src "ls180.v:4938.164-4938.279"
112046   cell $xor $xor$ls180.v:4938$748
112047     parameter \A_SIGNED 0
112048     parameter \A_WIDTH 1
112049     parameter \B_SIGNED 0
112050     parameter \B_WIDTH 1
112051     parameter \Y_WIDTH 1
112052     connect \A \main_sdcore_crc7_inserter_crcreg12 [2]
112053     connect \B $xor$ls180.v:4938$747_Y
112054     connect \Y $xor$ls180.v:4938$748_Y
112055   end
112056   attribute \src "ls180.v:4939.361-4939.434"
112057   cell $xor $xor$ls180.v:4939$749
112058     parameter \A_SIGNED 0
112059     parameter \A_WIDTH 1
112060     parameter \B_SIGNED 0
112061     parameter \B_WIDTH 1
112062     parameter \Y_WIDTH 1
112063     connect \A \main_sdcore_crc7_inserter_val [26]
112064     connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
112065     connect \Y $xor$ls180.v:4939$749_Y
112066   end
112067   attribute \src "ls180.v:4939.205-4939.278"
112068   cell $xor $xor$ls180.v:4939$750
112069     parameter \A_SIGNED 0
112070     parameter \A_WIDTH 1
112071     parameter \B_SIGNED 0
112072     parameter \B_WIDTH 1
112073     parameter \Y_WIDTH 1
112074     connect \A \main_sdcore_crc7_inserter_val [26]
112075     connect \B \main_sdcore_crc7_inserter_crcreg13 [6]
112076     connect \Y $xor$ls180.v:4939$750_Y
112077   end
112078   attribute \src "ls180.v:4939.164-4939.279"
112079   cell $xor $xor$ls180.v:4939$751
112080     parameter \A_SIGNED 0
112081     parameter \A_WIDTH 1
112082     parameter \B_SIGNED 0
112083     parameter \B_WIDTH 1
112084     parameter \Y_WIDTH 1
112085     connect \A \main_sdcore_crc7_inserter_crcreg13 [2]
112086     connect \B $xor$ls180.v:4939$750_Y
112087     connect \Y $xor$ls180.v:4939$751_Y
112088   end
112089   attribute \src "ls180.v:4940.361-4940.434"
112090   cell $xor $xor$ls180.v:4940$752
112091     parameter \A_SIGNED 0
112092     parameter \A_WIDTH 1
112093     parameter \B_SIGNED 0
112094     parameter \B_WIDTH 1
112095     parameter \Y_WIDTH 1
112096     connect \A \main_sdcore_crc7_inserter_val [25]
112097     connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
112098     connect \Y $xor$ls180.v:4940$752_Y
112099   end
112100   attribute \src "ls180.v:4940.205-4940.278"
112101   cell $xor $xor$ls180.v:4940$753
112102     parameter \A_SIGNED 0
112103     parameter \A_WIDTH 1
112104     parameter \B_SIGNED 0
112105     parameter \B_WIDTH 1
112106     parameter \Y_WIDTH 1
112107     connect \A \main_sdcore_crc7_inserter_val [25]
112108     connect \B \main_sdcore_crc7_inserter_crcreg14 [6]
112109     connect \Y $xor$ls180.v:4940$753_Y
112110   end
112111   attribute \src "ls180.v:4940.164-4940.279"
112112   cell $xor $xor$ls180.v:4940$754
112113     parameter \A_SIGNED 0
112114     parameter \A_WIDTH 1
112115     parameter \B_SIGNED 0
112116     parameter \B_WIDTH 1
112117     parameter \Y_WIDTH 1
112118     connect \A \main_sdcore_crc7_inserter_crcreg14 [2]
112119     connect \B $xor$ls180.v:4940$753_Y
112120     connect \Y $xor$ls180.v:4940$754_Y
112121   end
112122   attribute \src "ls180.v:4941.361-4941.434"
112123   cell $xor $xor$ls180.v:4941$755
112124     parameter \A_SIGNED 0
112125     parameter \A_WIDTH 1
112126     parameter \B_SIGNED 0
112127     parameter \B_WIDTH 1
112128     parameter \Y_WIDTH 1
112129     connect \A \main_sdcore_crc7_inserter_val [24]
112130     connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
112131     connect \Y $xor$ls180.v:4941$755_Y
112132   end
112133   attribute \src "ls180.v:4941.205-4941.278"
112134   cell $xor $xor$ls180.v:4941$756
112135     parameter \A_SIGNED 0
112136     parameter \A_WIDTH 1
112137     parameter \B_SIGNED 0
112138     parameter \B_WIDTH 1
112139     parameter \Y_WIDTH 1
112140     connect \A \main_sdcore_crc7_inserter_val [24]
112141     connect \B \main_sdcore_crc7_inserter_crcreg15 [6]
112142     connect \Y $xor$ls180.v:4941$756_Y
112143   end
112144   attribute \src "ls180.v:4941.164-4941.279"
112145   cell $xor $xor$ls180.v:4941$757
112146     parameter \A_SIGNED 0
112147     parameter \A_WIDTH 1
112148     parameter \B_SIGNED 0
112149     parameter \B_WIDTH 1
112150     parameter \Y_WIDTH 1
112151     connect \A \main_sdcore_crc7_inserter_crcreg15 [2]
112152     connect \B $xor$ls180.v:4941$756_Y
112153     connect \Y $xor$ls180.v:4941$757_Y
112154   end
112155   attribute \src "ls180.v:4942.361-4942.434"
112156   cell $xor $xor$ls180.v:4942$758
112157     parameter \A_SIGNED 0
112158     parameter \A_WIDTH 1
112159     parameter \B_SIGNED 0
112160     parameter \B_WIDTH 1
112161     parameter \Y_WIDTH 1
112162     connect \A \main_sdcore_crc7_inserter_val [23]
112163     connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
112164     connect \Y $xor$ls180.v:4942$758_Y
112165   end
112166   attribute \src "ls180.v:4942.205-4942.278"
112167   cell $xor $xor$ls180.v:4942$759
112168     parameter \A_SIGNED 0
112169     parameter \A_WIDTH 1
112170     parameter \B_SIGNED 0
112171     parameter \B_WIDTH 1
112172     parameter \Y_WIDTH 1
112173     connect \A \main_sdcore_crc7_inserter_val [23]
112174     connect \B \main_sdcore_crc7_inserter_crcreg16 [6]
112175     connect \Y $xor$ls180.v:4942$759_Y
112176   end
112177   attribute \src "ls180.v:4942.164-4942.279"
112178   cell $xor $xor$ls180.v:4942$760
112179     parameter \A_SIGNED 0
112180     parameter \A_WIDTH 1
112181     parameter \B_SIGNED 0
112182     parameter \B_WIDTH 1
112183     parameter \Y_WIDTH 1
112184     connect \A \main_sdcore_crc7_inserter_crcreg16 [2]
112185     connect \B $xor$ls180.v:4942$759_Y
112186     connect \Y $xor$ls180.v:4942$760_Y
112187   end
112188   attribute \src "ls180.v:4943.361-4943.434"
112189   cell $xor $xor$ls180.v:4943$761
112190     parameter \A_SIGNED 0
112191     parameter \A_WIDTH 1
112192     parameter \B_SIGNED 0
112193     parameter \B_WIDTH 1
112194     parameter \Y_WIDTH 1
112195     connect \A \main_sdcore_crc7_inserter_val [22]
112196     connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
112197     connect \Y $xor$ls180.v:4943$761_Y
112198   end
112199   attribute \src "ls180.v:4943.205-4943.278"
112200   cell $xor $xor$ls180.v:4943$762
112201     parameter \A_SIGNED 0
112202     parameter \A_WIDTH 1
112203     parameter \B_SIGNED 0
112204     parameter \B_WIDTH 1
112205     parameter \Y_WIDTH 1
112206     connect \A \main_sdcore_crc7_inserter_val [22]
112207     connect \B \main_sdcore_crc7_inserter_crcreg17 [6]
112208     connect \Y $xor$ls180.v:4943$762_Y
112209   end
112210   attribute \src "ls180.v:4943.164-4943.279"
112211   cell $xor $xor$ls180.v:4943$763
112212     parameter \A_SIGNED 0
112213     parameter \A_WIDTH 1
112214     parameter \B_SIGNED 0
112215     parameter \B_WIDTH 1
112216     parameter \Y_WIDTH 1
112217     connect \A \main_sdcore_crc7_inserter_crcreg17 [2]
112218     connect \B $xor$ls180.v:4943$762_Y
112219     connect \Y $xor$ls180.v:4943$763_Y
112220   end
112221   attribute \src "ls180.v:4944.361-4944.434"
112222   cell $xor $xor$ls180.v:4944$764
112223     parameter \A_SIGNED 0
112224     parameter \A_WIDTH 1
112225     parameter \B_SIGNED 0
112226     parameter \B_WIDTH 1
112227     parameter \Y_WIDTH 1
112228     connect \A \main_sdcore_crc7_inserter_val [21]
112229     connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
112230     connect \Y $xor$ls180.v:4944$764_Y
112231   end
112232   attribute \src "ls180.v:4944.205-4944.278"
112233   cell $xor $xor$ls180.v:4944$765
112234     parameter \A_SIGNED 0
112235     parameter \A_WIDTH 1
112236     parameter \B_SIGNED 0
112237     parameter \B_WIDTH 1
112238     parameter \Y_WIDTH 1
112239     connect \A \main_sdcore_crc7_inserter_val [21]
112240     connect \B \main_sdcore_crc7_inserter_crcreg18 [6]
112241     connect \Y $xor$ls180.v:4944$765_Y
112242   end
112243   attribute \src "ls180.v:4944.164-4944.279"
112244   cell $xor $xor$ls180.v:4944$766
112245     parameter \A_SIGNED 0
112246     parameter \A_WIDTH 1
112247     parameter \B_SIGNED 0
112248     parameter \B_WIDTH 1
112249     parameter \Y_WIDTH 1
112250     connect \A \main_sdcore_crc7_inserter_crcreg18 [2]
112251     connect \B $xor$ls180.v:4944$765_Y
112252     connect \Y $xor$ls180.v:4944$766_Y
112253   end
112254   attribute \src "ls180.v:4945.361-4945.434"
112255   cell $xor $xor$ls180.v:4945$767
112256     parameter \A_SIGNED 0
112257     parameter \A_WIDTH 1
112258     parameter \B_SIGNED 0
112259     parameter \B_WIDTH 1
112260     parameter \Y_WIDTH 1
112261     connect \A \main_sdcore_crc7_inserter_val [20]
112262     connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
112263     connect \Y $xor$ls180.v:4945$767_Y
112264   end
112265   attribute \src "ls180.v:4945.205-4945.278"
112266   cell $xor $xor$ls180.v:4945$768
112267     parameter \A_SIGNED 0
112268     parameter \A_WIDTH 1
112269     parameter \B_SIGNED 0
112270     parameter \B_WIDTH 1
112271     parameter \Y_WIDTH 1
112272     connect \A \main_sdcore_crc7_inserter_val [20]
112273     connect \B \main_sdcore_crc7_inserter_crcreg19 [6]
112274     connect \Y $xor$ls180.v:4945$768_Y
112275   end
112276   attribute \src "ls180.v:4945.164-4945.279"
112277   cell $xor $xor$ls180.v:4945$769
112278     parameter \A_SIGNED 0
112279     parameter \A_WIDTH 1
112280     parameter \B_SIGNED 0
112281     parameter \B_WIDTH 1
112282     parameter \Y_WIDTH 1
112283     connect \A \main_sdcore_crc7_inserter_crcreg19 [2]
112284     connect \B $xor$ls180.v:4945$768_Y
112285     connect \Y $xor$ls180.v:4945$769_Y
112286   end
112287   attribute \src "ls180.v:4946.361-4946.434"
112288   cell $xor $xor$ls180.v:4946$770
112289     parameter \A_SIGNED 0
112290     parameter \A_WIDTH 1
112291     parameter \B_SIGNED 0
112292     parameter \B_WIDTH 1
112293     parameter \Y_WIDTH 1
112294     connect \A \main_sdcore_crc7_inserter_val [19]
112295     connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
112296     connect \Y $xor$ls180.v:4946$770_Y
112297   end
112298   attribute \src "ls180.v:4946.205-4946.278"
112299   cell $xor $xor$ls180.v:4946$771
112300     parameter \A_SIGNED 0
112301     parameter \A_WIDTH 1
112302     parameter \B_SIGNED 0
112303     parameter \B_WIDTH 1
112304     parameter \Y_WIDTH 1
112305     connect \A \main_sdcore_crc7_inserter_val [19]
112306     connect \B \main_sdcore_crc7_inserter_crcreg20 [6]
112307     connect \Y $xor$ls180.v:4946$771_Y
112308   end
112309   attribute \src "ls180.v:4946.164-4946.279"
112310   cell $xor $xor$ls180.v:4946$772
112311     parameter \A_SIGNED 0
112312     parameter \A_WIDTH 1
112313     parameter \B_SIGNED 0
112314     parameter \B_WIDTH 1
112315     parameter \Y_WIDTH 1
112316     connect \A \main_sdcore_crc7_inserter_crcreg20 [2]
112317     connect \B $xor$ls180.v:4946$771_Y
112318     connect \Y $xor$ls180.v:4946$772_Y
112319   end
112320   attribute \src "ls180.v:4947.361-4947.434"
112321   cell $xor $xor$ls180.v:4947$773
112322     parameter \A_SIGNED 0
112323     parameter \A_WIDTH 1
112324     parameter \B_SIGNED 0
112325     parameter \B_WIDTH 1
112326     parameter \Y_WIDTH 1
112327     connect \A \main_sdcore_crc7_inserter_val [18]
112328     connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
112329     connect \Y $xor$ls180.v:4947$773_Y
112330   end
112331   attribute \src "ls180.v:4947.205-4947.278"
112332   cell $xor $xor$ls180.v:4947$774
112333     parameter \A_SIGNED 0
112334     parameter \A_WIDTH 1
112335     parameter \B_SIGNED 0
112336     parameter \B_WIDTH 1
112337     parameter \Y_WIDTH 1
112338     connect \A \main_sdcore_crc7_inserter_val [18]
112339     connect \B \main_sdcore_crc7_inserter_crcreg21 [6]
112340     connect \Y $xor$ls180.v:4947$774_Y
112341   end
112342   attribute \src "ls180.v:4947.164-4947.279"
112343   cell $xor $xor$ls180.v:4947$775
112344     parameter \A_SIGNED 0
112345     parameter \A_WIDTH 1
112346     parameter \B_SIGNED 0
112347     parameter \B_WIDTH 1
112348     parameter \Y_WIDTH 1
112349     connect \A \main_sdcore_crc7_inserter_crcreg21 [2]
112350     connect \B $xor$ls180.v:4947$774_Y
112351     connect \Y $xor$ls180.v:4947$775_Y
112352   end
112353   attribute \src "ls180.v:4948.361-4948.434"
112354   cell $xor $xor$ls180.v:4948$776
112355     parameter \A_SIGNED 0
112356     parameter \A_WIDTH 1
112357     parameter \B_SIGNED 0
112358     parameter \B_WIDTH 1
112359     parameter \Y_WIDTH 1
112360     connect \A \main_sdcore_crc7_inserter_val [17]
112361     connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
112362     connect \Y $xor$ls180.v:4948$776_Y
112363   end
112364   attribute \src "ls180.v:4948.205-4948.278"
112365   cell $xor $xor$ls180.v:4948$777
112366     parameter \A_SIGNED 0
112367     parameter \A_WIDTH 1
112368     parameter \B_SIGNED 0
112369     parameter \B_WIDTH 1
112370     parameter \Y_WIDTH 1
112371     connect \A \main_sdcore_crc7_inserter_val [17]
112372     connect \B \main_sdcore_crc7_inserter_crcreg22 [6]
112373     connect \Y $xor$ls180.v:4948$777_Y
112374   end
112375   attribute \src "ls180.v:4948.164-4948.279"
112376   cell $xor $xor$ls180.v:4948$778
112377     parameter \A_SIGNED 0
112378     parameter \A_WIDTH 1
112379     parameter \B_SIGNED 0
112380     parameter \B_WIDTH 1
112381     parameter \Y_WIDTH 1
112382     connect \A \main_sdcore_crc7_inserter_crcreg22 [2]
112383     connect \B $xor$ls180.v:4948$777_Y
112384     connect \Y $xor$ls180.v:4948$778_Y
112385   end
112386   attribute \src "ls180.v:4949.361-4949.434"
112387   cell $xor $xor$ls180.v:4949$779
112388     parameter \A_SIGNED 0
112389     parameter \A_WIDTH 1
112390     parameter \B_SIGNED 0
112391     parameter \B_WIDTH 1
112392     parameter \Y_WIDTH 1
112393     connect \A \main_sdcore_crc7_inserter_val [16]
112394     connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
112395     connect \Y $xor$ls180.v:4949$779_Y
112396   end
112397   attribute \src "ls180.v:4949.205-4949.278"
112398   cell $xor $xor$ls180.v:4949$780
112399     parameter \A_SIGNED 0
112400     parameter \A_WIDTH 1
112401     parameter \B_SIGNED 0
112402     parameter \B_WIDTH 1
112403     parameter \Y_WIDTH 1
112404     connect \A \main_sdcore_crc7_inserter_val [16]
112405     connect \B \main_sdcore_crc7_inserter_crcreg23 [6]
112406     connect \Y $xor$ls180.v:4949$780_Y
112407   end
112408   attribute \src "ls180.v:4949.164-4949.279"
112409   cell $xor $xor$ls180.v:4949$781
112410     parameter \A_SIGNED 0
112411     parameter \A_WIDTH 1
112412     parameter \B_SIGNED 0
112413     parameter \B_WIDTH 1
112414     parameter \Y_WIDTH 1
112415     connect \A \main_sdcore_crc7_inserter_crcreg23 [2]
112416     connect \B $xor$ls180.v:4949$780_Y
112417     connect \Y $xor$ls180.v:4949$781_Y
112418   end
112419   attribute \src "ls180.v:4950.361-4950.434"
112420   cell $xor $xor$ls180.v:4950$782
112421     parameter \A_SIGNED 0
112422     parameter \A_WIDTH 1
112423     parameter \B_SIGNED 0
112424     parameter \B_WIDTH 1
112425     parameter \Y_WIDTH 1
112426     connect \A \main_sdcore_crc7_inserter_val [15]
112427     connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
112428     connect \Y $xor$ls180.v:4950$782_Y
112429   end
112430   attribute \src "ls180.v:4950.205-4950.278"
112431   cell $xor $xor$ls180.v:4950$783
112432     parameter \A_SIGNED 0
112433     parameter \A_WIDTH 1
112434     parameter \B_SIGNED 0
112435     parameter \B_WIDTH 1
112436     parameter \Y_WIDTH 1
112437     connect \A \main_sdcore_crc7_inserter_val [15]
112438     connect \B \main_sdcore_crc7_inserter_crcreg24 [6]
112439     connect \Y $xor$ls180.v:4950$783_Y
112440   end
112441   attribute \src "ls180.v:4950.164-4950.279"
112442   cell $xor $xor$ls180.v:4950$784
112443     parameter \A_SIGNED 0
112444     parameter \A_WIDTH 1
112445     parameter \B_SIGNED 0
112446     parameter \B_WIDTH 1
112447     parameter \Y_WIDTH 1
112448     connect \A \main_sdcore_crc7_inserter_crcreg24 [2]
112449     connect \B $xor$ls180.v:4950$783_Y
112450     connect \Y $xor$ls180.v:4950$784_Y
112451   end
112452   attribute \src "ls180.v:4951.361-4951.434"
112453   cell $xor $xor$ls180.v:4951$785
112454     parameter \A_SIGNED 0
112455     parameter \A_WIDTH 1
112456     parameter \B_SIGNED 0
112457     parameter \B_WIDTH 1
112458     parameter \Y_WIDTH 1
112459     connect \A \main_sdcore_crc7_inserter_val [14]
112460     connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
112461     connect \Y $xor$ls180.v:4951$785_Y
112462   end
112463   attribute \src "ls180.v:4951.205-4951.278"
112464   cell $xor $xor$ls180.v:4951$786
112465     parameter \A_SIGNED 0
112466     parameter \A_WIDTH 1
112467     parameter \B_SIGNED 0
112468     parameter \B_WIDTH 1
112469     parameter \Y_WIDTH 1
112470     connect \A \main_sdcore_crc7_inserter_val [14]
112471     connect \B \main_sdcore_crc7_inserter_crcreg25 [6]
112472     connect \Y $xor$ls180.v:4951$786_Y
112473   end
112474   attribute \src "ls180.v:4951.164-4951.279"
112475   cell $xor $xor$ls180.v:4951$787
112476     parameter \A_SIGNED 0
112477     parameter \A_WIDTH 1
112478     parameter \B_SIGNED 0
112479     parameter \B_WIDTH 1
112480     parameter \Y_WIDTH 1
112481     connect \A \main_sdcore_crc7_inserter_crcreg25 [2]
112482     connect \B $xor$ls180.v:4951$786_Y
112483     connect \Y $xor$ls180.v:4951$787_Y
112484   end
112485   attribute \src "ls180.v:4952.361-4952.434"
112486   cell $xor $xor$ls180.v:4952$788
112487     parameter \A_SIGNED 0
112488     parameter \A_WIDTH 1
112489     parameter \B_SIGNED 0
112490     parameter \B_WIDTH 1
112491     parameter \Y_WIDTH 1
112492     connect \A \main_sdcore_crc7_inserter_val [13]
112493     connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
112494     connect \Y $xor$ls180.v:4952$788_Y
112495   end
112496   attribute \src "ls180.v:4952.205-4952.278"
112497   cell $xor $xor$ls180.v:4952$789
112498     parameter \A_SIGNED 0
112499     parameter \A_WIDTH 1
112500     parameter \B_SIGNED 0
112501     parameter \B_WIDTH 1
112502     parameter \Y_WIDTH 1
112503     connect \A \main_sdcore_crc7_inserter_val [13]
112504     connect \B \main_sdcore_crc7_inserter_crcreg26 [6]
112505     connect \Y $xor$ls180.v:4952$789_Y
112506   end
112507   attribute \src "ls180.v:4952.164-4952.279"
112508   cell $xor $xor$ls180.v:4952$790
112509     parameter \A_SIGNED 0
112510     parameter \A_WIDTH 1
112511     parameter \B_SIGNED 0
112512     parameter \B_WIDTH 1
112513     parameter \Y_WIDTH 1
112514     connect \A \main_sdcore_crc7_inserter_crcreg26 [2]
112515     connect \B $xor$ls180.v:4952$789_Y
112516     connect \Y $xor$ls180.v:4952$790_Y
112517   end
112518   attribute \src "ls180.v:4953.361-4953.434"
112519   cell $xor $xor$ls180.v:4953$791
112520     parameter \A_SIGNED 0
112521     parameter \A_WIDTH 1
112522     parameter \B_SIGNED 0
112523     parameter \B_WIDTH 1
112524     parameter \Y_WIDTH 1
112525     connect \A \main_sdcore_crc7_inserter_val [12]
112526     connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
112527     connect \Y $xor$ls180.v:4953$791_Y
112528   end
112529   attribute \src "ls180.v:4953.205-4953.278"
112530   cell $xor $xor$ls180.v:4953$792
112531     parameter \A_SIGNED 0
112532     parameter \A_WIDTH 1
112533     parameter \B_SIGNED 0
112534     parameter \B_WIDTH 1
112535     parameter \Y_WIDTH 1
112536     connect \A \main_sdcore_crc7_inserter_val [12]
112537     connect \B \main_sdcore_crc7_inserter_crcreg27 [6]
112538     connect \Y $xor$ls180.v:4953$792_Y
112539   end
112540   attribute \src "ls180.v:4953.164-4953.279"
112541   cell $xor $xor$ls180.v:4953$793
112542     parameter \A_SIGNED 0
112543     parameter \A_WIDTH 1
112544     parameter \B_SIGNED 0
112545     parameter \B_WIDTH 1
112546     parameter \Y_WIDTH 1
112547     connect \A \main_sdcore_crc7_inserter_crcreg27 [2]
112548     connect \B $xor$ls180.v:4953$792_Y
112549     connect \Y $xor$ls180.v:4953$793_Y
112550   end
112551   attribute \src "ls180.v:4954.361-4954.434"
112552   cell $xor $xor$ls180.v:4954$794
112553     parameter \A_SIGNED 0
112554     parameter \A_WIDTH 1
112555     parameter \B_SIGNED 0
112556     parameter \B_WIDTH 1
112557     parameter \Y_WIDTH 1
112558     connect \A \main_sdcore_crc7_inserter_val [11]
112559     connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
112560     connect \Y $xor$ls180.v:4954$794_Y
112561   end
112562   attribute \src "ls180.v:4954.205-4954.278"
112563   cell $xor $xor$ls180.v:4954$795
112564     parameter \A_SIGNED 0
112565     parameter \A_WIDTH 1
112566     parameter \B_SIGNED 0
112567     parameter \B_WIDTH 1
112568     parameter \Y_WIDTH 1
112569     connect \A \main_sdcore_crc7_inserter_val [11]
112570     connect \B \main_sdcore_crc7_inserter_crcreg28 [6]
112571     connect \Y $xor$ls180.v:4954$795_Y
112572   end
112573   attribute \src "ls180.v:4954.164-4954.279"
112574   cell $xor $xor$ls180.v:4954$796
112575     parameter \A_SIGNED 0
112576     parameter \A_WIDTH 1
112577     parameter \B_SIGNED 0
112578     parameter \B_WIDTH 1
112579     parameter \Y_WIDTH 1
112580     connect \A \main_sdcore_crc7_inserter_crcreg28 [2]
112581     connect \B $xor$ls180.v:4954$795_Y
112582     connect \Y $xor$ls180.v:4954$796_Y
112583   end
112584   attribute \src "ls180.v:4955.361-4955.434"
112585   cell $xor $xor$ls180.v:4955$797
112586     parameter \A_SIGNED 0
112587     parameter \A_WIDTH 1
112588     parameter \B_SIGNED 0
112589     parameter \B_WIDTH 1
112590     parameter \Y_WIDTH 1
112591     connect \A \main_sdcore_crc7_inserter_val [10]
112592     connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
112593     connect \Y $xor$ls180.v:4955$797_Y
112594   end
112595   attribute \src "ls180.v:4955.205-4955.278"
112596   cell $xor $xor$ls180.v:4955$798
112597     parameter \A_SIGNED 0
112598     parameter \A_WIDTH 1
112599     parameter \B_SIGNED 0
112600     parameter \B_WIDTH 1
112601     parameter \Y_WIDTH 1
112602     connect \A \main_sdcore_crc7_inserter_val [10]
112603     connect \B \main_sdcore_crc7_inserter_crcreg29 [6]
112604     connect \Y $xor$ls180.v:4955$798_Y
112605   end
112606   attribute \src "ls180.v:4955.164-4955.279"
112607   cell $xor $xor$ls180.v:4955$799
112608     parameter \A_SIGNED 0
112609     parameter \A_WIDTH 1
112610     parameter \B_SIGNED 0
112611     parameter \B_WIDTH 1
112612     parameter \Y_WIDTH 1
112613     connect \A \main_sdcore_crc7_inserter_crcreg29 [2]
112614     connect \B $xor$ls180.v:4955$798_Y
112615     connect \Y $xor$ls180.v:4955$799_Y
112616   end
112617   attribute \src "ls180.v:4956.360-4956.432"
112618   cell $xor $xor$ls180.v:4956$800
112619     parameter \A_SIGNED 0
112620     parameter \A_WIDTH 1
112621     parameter \B_SIGNED 0
112622     parameter \B_WIDTH 1
112623     parameter \Y_WIDTH 1
112624     connect \A \main_sdcore_crc7_inserter_val [9]
112625     connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
112626     connect \Y $xor$ls180.v:4956$800_Y
112627   end
112628   attribute \src "ls180.v:4956.205-4956.277"
112629   cell $xor $xor$ls180.v:4956$801
112630     parameter \A_SIGNED 0
112631     parameter \A_WIDTH 1
112632     parameter \B_SIGNED 0
112633     parameter \B_WIDTH 1
112634     parameter \Y_WIDTH 1
112635     connect \A \main_sdcore_crc7_inserter_val [9]
112636     connect \B \main_sdcore_crc7_inserter_crcreg30 [6]
112637     connect \Y $xor$ls180.v:4956$801_Y
112638   end
112639   attribute \src "ls180.v:4956.164-4956.278"
112640   cell $xor $xor$ls180.v:4956$802
112641     parameter \A_SIGNED 0
112642     parameter \A_WIDTH 1
112643     parameter \B_SIGNED 0
112644     parameter \B_WIDTH 1
112645     parameter \Y_WIDTH 1
112646     connect \A \main_sdcore_crc7_inserter_crcreg30 [2]
112647     connect \B $xor$ls180.v:4956$801_Y
112648     connect \Y $xor$ls180.v:4956$802_Y
112649   end
112650   attribute \src "ls180.v:4957.360-4957.432"
112651   cell $xor $xor$ls180.v:4957$803
112652     parameter \A_SIGNED 0
112653     parameter \A_WIDTH 1
112654     parameter \B_SIGNED 0
112655     parameter \B_WIDTH 1
112656     parameter \Y_WIDTH 1
112657     connect \A \main_sdcore_crc7_inserter_val [8]
112658     connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
112659     connect \Y $xor$ls180.v:4957$803_Y
112660   end
112661   attribute \src "ls180.v:4957.205-4957.277"
112662   cell $xor $xor$ls180.v:4957$804
112663     parameter \A_SIGNED 0
112664     parameter \A_WIDTH 1
112665     parameter \B_SIGNED 0
112666     parameter \B_WIDTH 1
112667     parameter \Y_WIDTH 1
112668     connect \A \main_sdcore_crc7_inserter_val [8]
112669     connect \B \main_sdcore_crc7_inserter_crcreg31 [6]
112670     connect \Y $xor$ls180.v:4957$804_Y
112671   end
112672   attribute \src "ls180.v:4957.164-4957.278"
112673   cell $xor $xor$ls180.v:4957$805
112674     parameter \A_SIGNED 0
112675     parameter \A_WIDTH 1
112676     parameter \B_SIGNED 0
112677     parameter \B_WIDTH 1
112678     parameter \Y_WIDTH 1
112679     connect \A \main_sdcore_crc7_inserter_crcreg31 [2]
112680     connect \B $xor$ls180.v:4957$804_Y
112681     connect \Y $xor$ls180.v:4957$805_Y
112682   end
112683   attribute \src "ls180.v:4958.360-4958.432"
112684   cell $xor $xor$ls180.v:4958$806
112685     parameter \A_SIGNED 0
112686     parameter \A_WIDTH 1
112687     parameter \B_SIGNED 0
112688     parameter \B_WIDTH 1
112689     parameter \Y_WIDTH 1
112690     connect \A \main_sdcore_crc7_inserter_val [7]
112691     connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
112692     connect \Y $xor$ls180.v:4958$806_Y
112693   end
112694   attribute \src "ls180.v:4958.205-4958.277"
112695   cell $xor $xor$ls180.v:4958$807
112696     parameter \A_SIGNED 0
112697     parameter \A_WIDTH 1
112698     parameter \B_SIGNED 0
112699     parameter \B_WIDTH 1
112700     parameter \Y_WIDTH 1
112701     connect \A \main_sdcore_crc7_inserter_val [7]
112702     connect \B \main_sdcore_crc7_inserter_crcreg32 [6]
112703     connect \Y $xor$ls180.v:4958$807_Y
112704   end
112705   attribute \src "ls180.v:4958.164-4958.278"
112706   cell $xor $xor$ls180.v:4958$808
112707     parameter \A_SIGNED 0
112708     parameter \A_WIDTH 1
112709     parameter \B_SIGNED 0
112710     parameter \B_WIDTH 1
112711     parameter \Y_WIDTH 1
112712     connect \A \main_sdcore_crc7_inserter_crcreg32 [2]
112713     connect \B $xor$ls180.v:4958$807_Y
112714     connect \Y $xor$ls180.v:4958$808_Y
112715   end
112716   attribute \src "ls180.v:4959.360-4959.432"
112717   cell $xor $xor$ls180.v:4959$809
112718     parameter \A_SIGNED 0
112719     parameter \A_WIDTH 1
112720     parameter \B_SIGNED 0
112721     parameter \B_WIDTH 1
112722     parameter \Y_WIDTH 1
112723     connect \A \main_sdcore_crc7_inserter_val [6]
112724     connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
112725     connect \Y $xor$ls180.v:4959$809_Y
112726   end
112727   attribute \src "ls180.v:4959.205-4959.277"
112728   cell $xor $xor$ls180.v:4959$810
112729     parameter \A_SIGNED 0
112730     parameter \A_WIDTH 1
112731     parameter \B_SIGNED 0
112732     parameter \B_WIDTH 1
112733     parameter \Y_WIDTH 1
112734     connect \A \main_sdcore_crc7_inserter_val [6]
112735     connect \B \main_sdcore_crc7_inserter_crcreg33 [6]
112736     connect \Y $xor$ls180.v:4959$810_Y
112737   end
112738   attribute \src "ls180.v:4959.164-4959.278"
112739   cell $xor $xor$ls180.v:4959$811
112740     parameter \A_SIGNED 0
112741     parameter \A_WIDTH 1
112742     parameter \B_SIGNED 0
112743     parameter \B_WIDTH 1
112744     parameter \Y_WIDTH 1
112745     connect \A \main_sdcore_crc7_inserter_crcreg33 [2]
112746     connect \B $xor$ls180.v:4959$810_Y
112747     connect \Y $xor$ls180.v:4959$811_Y
112748   end
112749   attribute \src "ls180.v:4960.360-4960.432"
112750   cell $xor $xor$ls180.v:4960$812
112751     parameter \A_SIGNED 0
112752     parameter \A_WIDTH 1
112753     parameter \B_SIGNED 0
112754     parameter \B_WIDTH 1
112755     parameter \Y_WIDTH 1
112756     connect \A \main_sdcore_crc7_inserter_val [5]
112757     connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
112758     connect \Y $xor$ls180.v:4960$812_Y
112759   end
112760   attribute \src "ls180.v:4960.205-4960.277"
112761   cell $xor $xor$ls180.v:4960$813
112762     parameter \A_SIGNED 0
112763     parameter \A_WIDTH 1
112764     parameter \B_SIGNED 0
112765     parameter \B_WIDTH 1
112766     parameter \Y_WIDTH 1
112767     connect \A \main_sdcore_crc7_inserter_val [5]
112768     connect \B \main_sdcore_crc7_inserter_crcreg34 [6]
112769     connect \Y $xor$ls180.v:4960$813_Y
112770   end
112771   attribute \src "ls180.v:4960.164-4960.278"
112772   cell $xor $xor$ls180.v:4960$814
112773     parameter \A_SIGNED 0
112774     parameter \A_WIDTH 1
112775     parameter \B_SIGNED 0
112776     parameter \B_WIDTH 1
112777     parameter \Y_WIDTH 1
112778     connect \A \main_sdcore_crc7_inserter_crcreg34 [2]
112779     connect \B $xor$ls180.v:4960$813_Y
112780     connect \Y $xor$ls180.v:4960$814_Y
112781   end
112782   attribute \src "ls180.v:4961.360-4961.432"
112783   cell $xor $xor$ls180.v:4961$815
112784     parameter \A_SIGNED 0
112785     parameter \A_WIDTH 1
112786     parameter \B_SIGNED 0
112787     parameter \B_WIDTH 1
112788     parameter \Y_WIDTH 1
112789     connect \A \main_sdcore_crc7_inserter_val [4]
112790     connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
112791     connect \Y $xor$ls180.v:4961$815_Y
112792   end
112793   attribute \src "ls180.v:4961.205-4961.277"
112794   cell $xor $xor$ls180.v:4961$816
112795     parameter \A_SIGNED 0
112796     parameter \A_WIDTH 1
112797     parameter \B_SIGNED 0
112798     parameter \B_WIDTH 1
112799     parameter \Y_WIDTH 1
112800     connect \A \main_sdcore_crc7_inserter_val [4]
112801     connect \B \main_sdcore_crc7_inserter_crcreg35 [6]
112802     connect \Y $xor$ls180.v:4961$816_Y
112803   end
112804   attribute \src "ls180.v:4961.164-4961.278"
112805   cell $xor $xor$ls180.v:4961$817
112806     parameter \A_SIGNED 0
112807     parameter \A_WIDTH 1
112808     parameter \B_SIGNED 0
112809     parameter \B_WIDTH 1
112810     parameter \Y_WIDTH 1
112811     connect \A \main_sdcore_crc7_inserter_crcreg35 [2]
112812     connect \B $xor$ls180.v:4961$816_Y
112813     connect \Y $xor$ls180.v:4961$817_Y
112814   end
112815   attribute \src "ls180.v:4962.360-4962.432"
112816   cell $xor $xor$ls180.v:4962$818
112817     parameter \A_SIGNED 0
112818     parameter \A_WIDTH 1
112819     parameter \B_SIGNED 0
112820     parameter \B_WIDTH 1
112821     parameter \Y_WIDTH 1
112822     connect \A \main_sdcore_crc7_inserter_val [3]
112823     connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
112824     connect \Y $xor$ls180.v:4962$818_Y
112825   end
112826   attribute \src "ls180.v:4962.205-4962.277"
112827   cell $xor $xor$ls180.v:4962$819
112828     parameter \A_SIGNED 0
112829     parameter \A_WIDTH 1
112830     parameter \B_SIGNED 0
112831     parameter \B_WIDTH 1
112832     parameter \Y_WIDTH 1
112833     connect \A \main_sdcore_crc7_inserter_val [3]
112834     connect \B \main_sdcore_crc7_inserter_crcreg36 [6]
112835     connect \Y $xor$ls180.v:4962$819_Y
112836   end
112837   attribute \src "ls180.v:4962.164-4962.278"
112838   cell $xor $xor$ls180.v:4962$820
112839     parameter \A_SIGNED 0
112840     parameter \A_WIDTH 1
112841     parameter \B_SIGNED 0
112842     parameter \B_WIDTH 1
112843     parameter \Y_WIDTH 1
112844     connect \A \main_sdcore_crc7_inserter_crcreg36 [2]
112845     connect \B $xor$ls180.v:4962$819_Y
112846     connect \Y $xor$ls180.v:4962$820_Y
112847   end
112848   attribute \src "ls180.v:4963.360-4963.432"
112849   cell $xor $xor$ls180.v:4963$821
112850     parameter \A_SIGNED 0
112851     parameter \A_WIDTH 1
112852     parameter \B_SIGNED 0
112853     parameter \B_WIDTH 1
112854     parameter \Y_WIDTH 1
112855     connect \A \main_sdcore_crc7_inserter_val [2]
112856     connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
112857     connect \Y $xor$ls180.v:4963$821_Y
112858   end
112859   attribute \src "ls180.v:4963.205-4963.277"
112860   cell $xor $xor$ls180.v:4963$822
112861     parameter \A_SIGNED 0
112862     parameter \A_WIDTH 1
112863     parameter \B_SIGNED 0
112864     parameter \B_WIDTH 1
112865     parameter \Y_WIDTH 1
112866     connect \A \main_sdcore_crc7_inserter_val [2]
112867     connect \B \main_sdcore_crc7_inserter_crcreg37 [6]
112868     connect \Y $xor$ls180.v:4963$822_Y
112869   end
112870   attribute \src "ls180.v:4963.164-4963.278"
112871   cell $xor $xor$ls180.v:4963$823
112872     parameter \A_SIGNED 0
112873     parameter \A_WIDTH 1
112874     parameter \B_SIGNED 0
112875     parameter \B_WIDTH 1
112876     parameter \Y_WIDTH 1
112877     connect \A \main_sdcore_crc7_inserter_crcreg37 [2]
112878     connect \B $xor$ls180.v:4963$822_Y
112879     connect \Y $xor$ls180.v:4963$823_Y
112880   end
112881   attribute \src "ls180.v:4964.360-4964.432"
112882   cell $xor $xor$ls180.v:4964$824
112883     parameter \A_SIGNED 0
112884     parameter \A_WIDTH 1
112885     parameter \B_SIGNED 0
112886     parameter \B_WIDTH 1
112887     parameter \Y_WIDTH 1
112888     connect \A \main_sdcore_crc7_inserter_val [1]
112889     connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
112890     connect \Y $xor$ls180.v:4964$824_Y
112891   end
112892   attribute \src "ls180.v:4964.205-4964.277"
112893   cell $xor $xor$ls180.v:4964$825
112894     parameter \A_SIGNED 0
112895     parameter \A_WIDTH 1
112896     parameter \B_SIGNED 0
112897     parameter \B_WIDTH 1
112898     parameter \Y_WIDTH 1
112899     connect \A \main_sdcore_crc7_inserter_val [1]
112900     connect \B \main_sdcore_crc7_inserter_crcreg38 [6]
112901     connect \Y $xor$ls180.v:4964$825_Y
112902   end
112903   attribute \src "ls180.v:4964.164-4964.278"
112904   cell $xor $xor$ls180.v:4964$826
112905     parameter \A_SIGNED 0
112906     parameter \A_WIDTH 1
112907     parameter \B_SIGNED 0
112908     parameter \B_WIDTH 1
112909     parameter \Y_WIDTH 1
112910     connect \A \main_sdcore_crc7_inserter_crcreg38 [2]
112911     connect \B $xor$ls180.v:4964$825_Y
112912     connect \Y $xor$ls180.v:4964$826_Y
112913   end
112914   attribute \src "ls180.v:4965.360-4965.432"
112915   cell $xor $xor$ls180.v:4965$827
112916     parameter \A_SIGNED 0
112917     parameter \A_WIDTH 1
112918     parameter \B_SIGNED 0
112919     parameter \B_WIDTH 1
112920     parameter \Y_WIDTH 1
112921     connect \A \main_sdcore_crc7_inserter_val [0]
112922     connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
112923     connect \Y $xor$ls180.v:4965$827_Y
112924   end
112925   attribute \src "ls180.v:4965.205-4965.277"
112926   cell $xor $xor$ls180.v:4965$828
112927     parameter \A_SIGNED 0
112928     parameter \A_WIDTH 1
112929     parameter \B_SIGNED 0
112930     parameter \B_WIDTH 1
112931     parameter \Y_WIDTH 1
112932     connect \A \main_sdcore_crc7_inserter_val [0]
112933     connect \B \main_sdcore_crc7_inserter_crcreg39 [6]
112934     connect \Y $xor$ls180.v:4965$828_Y
112935   end
112936   attribute \src "ls180.v:4965.164-4965.278"
112937   cell $xor $xor$ls180.v:4965$829
112938     parameter \A_SIGNED 0
112939     parameter \A_WIDTH 1
112940     parameter \B_SIGNED 0
112941     parameter \B_WIDTH 1
112942     parameter \Y_WIDTH 1
112943     connect \A \main_sdcore_crc7_inserter_crcreg39 [2]
112944     connect \B $xor$ls180.v:4965$828_Y
112945     connect \Y $xor$ls180.v:4965$829_Y
112946   end
112947   attribute \src "ls180.v:4986.899-4986.983"
112948   cell $xor $xor$ls180.v:4986$843
112949     parameter \A_SIGNED 0
112950     parameter \A_WIDTH 1
112951     parameter \B_SIGNED 0
112952     parameter \B_WIDTH 1
112953     parameter \Y_WIDTH 1
112954     connect \A \main_sdcore_crc16_inserter_crc0_val [1]
112955     connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
112956     connect \Y $xor$ls180.v:4986$843_Y
112957   end
112958   attribute \src "ls180.v:4986.634-4986.718"
112959   cell $xor $xor$ls180.v:4986$844
112960     parameter \A_SIGNED 0
112961     parameter \A_WIDTH 1
112962     parameter \B_SIGNED 0
112963     parameter \B_WIDTH 1
112964     parameter \Y_WIDTH 1
112965     connect \A \main_sdcore_crc16_inserter_crc0_val [1]
112966     connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
112967     connect \Y $xor$ls180.v:4986$844_Y
112968   end
112969   attribute \src "ls180.v:4986.588-4986.719"
112970   cell $xor $xor$ls180.v:4986$845
112971     parameter \A_SIGNED 0
112972     parameter \A_WIDTH 1
112973     parameter \B_SIGNED 0
112974     parameter \B_WIDTH 1
112975     parameter \Y_WIDTH 1
112976     connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4]
112977     connect \B $xor$ls180.v:4986$844_Y
112978     connect \Y $xor$ls180.v:4986$845_Y
112979   end
112980   attribute \src "ls180.v:4986.234-4986.318"
112981   cell $xor $xor$ls180.v:4986$846
112982     parameter \A_SIGNED 0
112983     parameter \A_WIDTH 1
112984     parameter \B_SIGNED 0
112985     parameter \B_WIDTH 1
112986     parameter \Y_WIDTH 1
112987     connect \A \main_sdcore_crc16_inserter_crc0_val [1]
112988     connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15]
112989     connect \Y $xor$ls180.v:4986$846_Y
112990   end
112991   attribute \src "ls180.v:4986.187-4986.319"
112992   cell $xor $xor$ls180.v:4986$847
112993     parameter \A_SIGNED 0
112994     parameter \A_WIDTH 1
112995     parameter \B_SIGNED 0
112996     parameter \B_WIDTH 1
112997     parameter \Y_WIDTH 1
112998     connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11]
112999     connect \B $xor$ls180.v:4986$846_Y
113000     connect \Y $xor$ls180.v:4986$847_Y
113001   end
113002   attribute \src "ls180.v:4987.899-4987.983"
113003   cell $xor $xor$ls180.v:4987$848
113004     parameter \A_SIGNED 0
113005     parameter \A_WIDTH 1
113006     parameter \B_SIGNED 0
113007     parameter \B_WIDTH 1
113008     parameter \Y_WIDTH 1
113009     connect \A \main_sdcore_crc16_inserter_crc0_val [0]
113010     connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
113011     connect \Y $xor$ls180.v:4987$848_Y
113012   end
113013   attribute \src "ls180.v:4987.634-4987.718"
113014   cell $xor $xor$ls180.v:4987$849
113015     parameter \A_SIGNED 0
113016     parameter \A_WIDTH 1
113017     parameter \B_SIGNED 0
113018     parameter \B_WIDTH 1
113019     parameter \Y_WIDTH 1
113020     connect \A \main_sdcore_crc16_inserter_crc0_val [0]
113021     connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
113022     connect \Y $xor$ls180.v:4987$849_Y
113023   end
113024   attribute \src "ls180.v:4987.588-4987.719"
113025   cell $xor $xor$ls180.v:4987$850
113026     parameter \A_SIGNED 0
113027     parameter \A_WIDTH 1
113028     parameter \B_SIGNED 0
113029     parameter \B_WIDTH 1
113030     parameter \Y_WIDTH 1
113031     connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4]
113032     connect \B $xor$ls180.v:4987$849_Y
113033     connect \Y $xor$ls180.v:4987$850_Y
113034   end
113035   attribute \src "ls180.v:4987.234-4987.318"
113036   cell $xor $xor$ls180.v:4987$851
113037     parameter \A_SIGNED 0
113038     parameter \A_WIDTH 1
113039     parameter \B_SIGNED 0
113040     parameter \B_WIDTH 1
113041     parameter \Y_WIDTH 1
113042     connect \A \main_sdcore_crc16_inserter_crc0_val [0]
113043     connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15]
113044     connect \Y $xor$ls180.v:4987$851_Y
113045   end
113046   attribute \src "ls180.v:4987.187-4987.319"
113047   cell $xor $xor$ls180.v:4987$852
113048     parameter \A_SIGNED 0
113049     parameter \A_WIDTH 1
113050     parameter \B_SIGNED 0
113051     parameter \B_WIDTH 1
113052     parameter \Y_WIDTH 1
113053     connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11]
113054     connect \B $xor$ls180.v:4987$851_Y
113055     connect \Y $xor$ls180.v:4987$852_Y
113056   end
113057   attribute \src "ls180.v:4996.899-4996.983"
113058   cell $xor $xor$ls180.v:4996$854
113059     parameter \A_SIGNED 0
113060     parameter \A_WIDTH 1
113061     parameter \B_SIGNED 0
113062     parameter \B_WIDTH 1
113063     parameter \Y_WIDTH 1
113064     connect \A \main_sdcore_crc16_inserter_crc1_val [1]
113065     connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
113066     connect \Y $xor$ls180.v:4996$854_Y
113067   end
113068   attribute \src "ls180.v:4996.634-4996.718"
113069   cell $xor $xor$ls180.v:4996$855
113070     parameter \A_SIGNED 0
113071     parameter \A_WIDTH 1
113072     parameter \B_SIGNED 0
113073     parameter \B_WIDTH 1
113074     parameter \Y_WIDTH 1
113075     connect \A \main_sdcore_crc16_inserter_crc1_val [1]
113076     connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
113077     connect \Y $xor$ls180.v:4996$855_Y
113078   end
113079   attribute \src "ls180.v:4996.588-4996.719"
113080   cell $xor $xor$ls180.v:4996$856
113081     parameter \A_SIGNED 0
113082     parameter \A_WIDTH 1
113083     parameter \B_SIGNED 0
113084     parameter \B_WIDTH 1
113085     parameter \Y_WIDTH 1
113086     connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4]
113087     connect \B $xor$ls180.v:4996$855_Y
113088     connect \Y $xor$ls180.v:4996$856_Y
113089   end
113090   attribute \src "ls180.v:4996.234-4996.318"
113091   cell $xor $xor$ls180.v:4996$857
113092     parameter \A_SIGNED 0
113093     parameter \A_WIDTH 1
113094     parameter \B_SIGNED 0
113095     parameter \B_WIDTH 1
113096     parameter \Y_WIDTH 1
113097     connect \A \main_sdcore_crc16_inserter_crc1_val [1]
113098     connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15]
113099     connect \Y $xor$ls180.v:4996$857_Y
113100   end
113101   attribute \src "ls180.v:4996.187-4996.319"
113102   cell $xor $xor$ls180.v:4996$858
113103     parameter \A_SIGNED 0
113104     parameter \A_WIDTH 1
113105     parameter \B_SIGNED 0
113106     parameter \B_WIDTH 1
113107     parameter \Y_WIDTH 1
113108     connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11]
113109     connect \B $xor$ls180.v:4996$857_Y
113110     connect \Y $xor$ls180.v:4996$858_Y
113111   end
113112   attribute \src "ls180.v:4997.899-4997.983"
113113   cell $xor $xor$ls180.v:4997$859
113114     parameter \A_SIGNED 0
113115     parameter \A_WIDTH 1
113116     parameter \B_SIGNED 0
113117     parameter \B_WIDTH 1
113118     parameter \Y_WIDTH 1
113119     connect \A \main_sdcore_crc16_inserter_crc1_val [0]
113120     connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
113121     connect \Y $xor$ls180.v:4997$859_Y
113122   end
113123   attribute \src "ls180.v:4997.634-4997.718"
113124   cell $xor $xor$ls180.v:4997$860
113125     parameter \A_SIGNED 0
113126     parameter \A_WIDTH 1
113127     parameter \B_SIGNED 0
113128     parameter \B_WIDTH 1
113129     parameter \Y_WIDTH 1
113130     connect \A \main_sdcore_crc16_inserter_crc1_val [0]
113131     connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
113132     connect \Y $xor$ls180.v:4997$860_Y
113133   end
113134   attribute \src "ls180.v:4997.588-4997.719"
113135   cell $xor $xor$ls180.v:4997$861
113136     parameter \A_SIGNED 0
113137     parameter \A_WIDTH 1
113138     parameter \B_SIGNED 0
113139     parameter \B_WIDTH 1
113140     parameter \Y_WIDTH 1
113141     connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4]
113142     connect \B $xor$ls180.v:4997$860_Y
113143     connect \Y $xor$ls180.v:4997$861_Y
113144   end
113145   attribute \src "ls180.v:4997.234-4997.318"
113146   cell $xor $xor$ls180.v:4997$862
113147     parameter \A_SIGNED 0
113148     parameter \A_WIDTH 1
113149     parameter \B_SIGNED 0
113150     parameter \B_WIDTH 1
113151     parameter \Y_WIDTH 1
113152     connect \A \main_sdcore_crc16_inserter_crc1_val [0]
113153     connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15]
113154     connect \Y $xor$ls180.v:4997$862_Y
113155   end
113156   attribute \src "ls180.v:4997.187-4997.319"
113157   cell $xor $xor$ls180.v:4997$863
113158     parameter \A_SIGNED 0
113159     parameter \A_WIDTH 1
113160     parameter \B_SIGNED 0
113161     parameter \B_WIDTH 1
113162     parameter \Y_WIDTH 1
113163     connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11]
113164     connect \B $xor$ls180.v:4997$862_Y
113165     connect \Y $xor$ls180.v:4997$863_Y
113166   end
113167   attribute \src "ls180.v:5006.899-5006.983"
113168   cell $xor $xor$ls180.v:5006$865
113169     parameter \A_SIGNED 0
113170     parameter \A_WIDTH 1
113171     parameter \B_SIGNED 0
113172     parameter \B_WIDTH 1
113173     parameter \Y_WIDTH 1
113174     connect \A \main_sdcore_crc16_inserter_crc2_val [1]
113175     connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
113176     connect \Y $xor$ls180.v:5006$865_Y
113177   end
113178   attribute \src "ls180.v:5006.634-5006.718"
113179   cell $xor $xor$ls180.v:5006$866
113180     parameter \A_SIGNED 0
113181     parameter \A_WIDTH 1
113182     parameter \B_SIGNED 0
113183     parameter \B_WIDTH 1
113184     parameter \Y_WIDTH 1
113185     connect \A \main_sdcore_crc16_inserter_crc2_val [1]
113186     connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
113187     connect \Y $xor$ls180.v:5006$866_Y
113188   end
113189   attribute \src "ls180.v:5006.588-5006.719"
113190   cell $xor $xor$ls180.v:5006$867
113191     parameter \A_SIGNED 0
113192     parameter \A_WIDTH 1
113193     parameter \B_SIGNED 0
113194     parameter \B_WIDTH 1
113195     parameter \Y_WIDTH 1
113196     connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4]
113197     connect \B $xor$ls180.v:5006$866_Y
113198     connect \Y $xor$ls180.v:5006$867_Y
113199   end
113200   attribute \src "ls180.v:5006.234-5006.318"
113201   cell $xor $xor$ls180.v:5006$868
113202     parameter \A_SIGNED 0
113203     parameter \A_WIDTH 1
113204     parameter \B_SIGNED 0
113205     parameter \B_WIDTH 1
113206     parameter \Y_WIDTH 1
113207     connect \A \main_sdcore_crc16_inserter_crc2_val [1]
113208     connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15]
113209     connect \Y $xor$ls180.v:5006$868_Y
113210   end
113211   attribute \src "ls180.v:5006.187-5006.319"
113212   cell $xor $xor$ls180.v:5006$869
113213     parameter \A_SIGNED 0
113214     parameter \A_WIDTH 1
113215     parameter \B_SIGNED 0
113216     parameter \B_WIDTH 1
113217     parameter \Y_WIDTH 1
113218     connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11]
113219     connect \B $xor$ls180.v:5006$868_Y
113220     connect \Y $xor$ls180.v:5006$869_Y
113221   end
113222   attribute \src "ls180.v:5007.899-5007.983"
113223   cell $xor $xor$ls180.v:5007$870
113224     parameter \A_SIGNED 0
113225     parameter \A_WIDTH 1
113226     parameter \B_SIGNED 0
113227     parameter \B_WIDTH 1
113228     parameter \Y_WIDTH 1
113229     connect \A \main_sdcore_crc16_inserter_crc2_val [0]
113230     connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
113231     connect \Y $xor$ls180.v:5007$870_Y
113232   end
113233   attribute \src "ls180.v:5007.634-5007.718"
113234   cell $xor $xor$ls180.v:5007$871
113235     parameter \A_SIGNED 0
113236     parameter \A_WIDTH 1
113237     parameter \B_SIGNED 0
113238     parameter \B_WIDTH 1
113239     parameter \Y_WIDTH 1
113240     connect \A \main_sdcore_crc16_inserter_crc2_val [0]
113241     connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
113242     connect \Y $xor$ls180.v:5007$871_Y
113243   end
113244   attribute \src "ls180.v:5007.588-5007.719"
113245   cell $xor $xor$ls180.v:5007$872
113246     parameter \A_SIGNED 0
113247     parameter \A_WIDTH 1
113248     parameter \B_SIGNED 0
113249     parameter \B_WIDTH 1
113250     parameter \Y_WIDTH 1
113251     connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4]
113252     connect \B $xor$ls180.v:5007$871_Y
113253     connect \Y $xor$ls180.v:5007$872_Y
113254   end
113255   attribute \src "ls180.v:5007.234-5007.318"
113256   cell $xor $xor$ls180.v:5007$873
113257     parameter \A_SIGNED 0
113258     parameter \A_WIDTH 1
113259     parameter \B_SIGNED 0
113260     parameter \B_WIDTH 1
113261     parameter \Y_WIDTH 1
113262     connect \A \main_sdcore_crc16_inserter_crc2_val [0]
113263     connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15]
113264     connect \Y $xor$ls180.v:5007$873_Y
113265   end
113266   attribute \src "ls180.v:5007.187-5007.319"
113267   cell $xor $xor$ls180.v:5007$874
113268     parameter \A_SIGNED 0
113269     parameter \A_WIDTH 1
113270     parameter \B_SIGNED 0
113271     parameter \B_WIDTH 1
113272     parameter \Y_WIDTH 1
113273     connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11]
113274     connect \B $xor$ls180.v:5007$873_Y
113275     connect \Y $xor$ls180.v:5007$874_Y
113276   end
113277   attribute \src "ls180.v:5016.899-5016.983"
113278   cell $xor $xor$ls180.v:5016$876
113279     parameter \A_SIGNED 0
113280     parameter \A_WIDTH 1
113281     parameter \B_SIGNED 0
113282     parameter \B_WIDTH 1
113283     parameter \Y_WIDTH 1
113284     connect \A \main_sdcore_crc16_inserter_crc3_val [1]
113285     connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
113286     connect \Y $xor$ls180.v:5016$876_Y
113287   end
113288   attribute \src "ls180.v:5016.634-5016.718"
113289   cell $xor $xor$ls180.v:5016$877
113290     parameter \A_SIGNED 0
113291     parameter \A_WIDTH 1
113292     parameter \B_SIGNED 0
113293     parameter \B_WIDTH 1
113294     parameter \Y_WIDTH 1
113295     connect \A \main_sdcore_crc16_inserter_crc3_val [1]
113296     connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
113297     connect \Y $xor$ls180.v:5016$877_Y
113298   end
113299   attribute \src "ls180.v:5016.588-5016.719"
113300   cell $xor $xor$ls180.v:5016$878
113301     parameter \A_SIGNED 0
113302     parameter \A_WIDTH 1
113303     parameter \B_SIGNED 0
113304     parameter \B_WIDTH 1
113305     parameter \Y_WIDTH 1
113306     connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4]
113307     connect \B $xor$ls180.v:5016$877_Y
113308     connect \Y $xor$ls180.v:5016$878_Y
113309   end
113310   attribute \src "ls180.v:5016.234-5016.318"
113311   cell $xor $xor$ls180.v:5016$879
113312     parameter \A_SIGNED 0
113313     parameter \A_WIDTH 1
113314     parameter \B_SIGNED 0
113315     parameter \B_WIDTH 1
113316     parameter \Y_WIDTH 1
113317     connect \A \main_sdcore_crc16_inserter_crc3_val [1]
113318     connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15]
113319     connect \Y $xor$ls180.v:5016$879_Y
113320   end
113321   attribute \src "ls180.v:5016.187-5016.319"
113322   cell $xor $xor$ls180.v:5016$880
113323     parameter \A_SIGNED 0
113324     parameter \A_WIDTH 1
113325     parameter \B_SIGNED 0
113326     parameter \B_WIDTH 1
113327     parameter \Y_WIDTH 1
113328     connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11]
113329     connect \B $xor$ls180.v:5016$879_Y
113330     connect \Y $xor$ls180.v:5016$880_Y
113331   end
113332   attribute \src "ls180.v:5017.899-5017.983"
113333   cell $xor $xor$ls180.v:5017$881
113334     parameter \A_SIGNED 0
113335     parameter \A_WIDTH 1
113336     parameter \B_SIGNED 0
113337     parameter \B_WIDTH 1
113338     parameter \Y_WIDTH 1
113339     connect \A \main_sdcore_crc16_inserter_crc3_val [0]
113340     connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
113341     connect \Y $xor$ls180.v:5017$881_Y
113342   end
113343   attribute \src "ls180.v:5017.634-5017.718"
113344   cell $xor $xor$ls180.v:5017$882
113345     parameter \A_SIGNED 0
113346     parameter \A_WIDTH 1
113347     parameter \B_SIGNED 0
113348     parameter \B_WIDTH 1
113349     parameter \Y_WIDTH 1
113350     connect \A \main_sdcore_crc16_inserter_crc3_val [0]
113351     connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
113352     connect \Y $xor$ls180.v:5017$882_Y
113353   end
113354   attribute \src "ls180.v:5017.588-5017.719"
113355   cell $xor $xor$ls180.v:5017$883
113356     parameter \A_SIGNED 0
113357     parameter \A_WIDTH 1
113358     parameter \B_SIGNED 0
113359     parameter \B_WIDTH 1
113360     parameter \Y_WIDTH 1
113361     connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4]
113362     connect \B $xor$ls180.v:5017$882_Y
113363     connect \Y $xor$ls180.v:5017$883_Y
113364   end
113365   attribute \src "ls180.v:5017.234-5017.318"
113366   cell $xor $xor$ls180.v:5017$884
113367     parameter \A_SIGNED 0
113368     parameter \A_WIDTH 1
113369     parameter \B_SIGNED 0
113370     parameter \B_WIDTH 1
113371     parameter \Y_WIDTH 1
113372     connect \A \main_sdcore_crc16_inserter_crc3_val [0]
113373     connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15]
113374     connect \Y $xor$ls180.v:5017$884_Y
113375   end
113376   attribute \src "ls180.v:5017.187-5017.319"
113377   cell $xor $xor$ls180.v:5017$885
113378     parameter \A_SIGNED 0
113379     parameter \A_WIDTH 1
113380     parameter \B_SIGNED 0
113381     parameter \B_WIDTH 1
113382     parameter \Y_WIDTH 1
113383     connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11]
113384     connect \B $xor$ls180.v:5017$884_Y
113385     connect \Y $xor$ls180.v:5017$885_Y
113386   end
113387   attribute \src "ls180.v:5168.879-5168.961"
113388   cell $xor $xor$ls180.v:5168$918
113389     parameter \A_SIGNED 0
113390     parameter \A_WIDTH 1
113391     parameter \B_SIGNED 0
113392     parameter \B_WIDTH 1
113393     parameter \Y_WIDTH 1
113394     connect \A \main_sdcore_crc16_checker_crc0_val [1]
113395     connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
113396     connect \Y $xor$ls180.v:5168$918_Y
113397   end
113398   attribute \src "ls180.v:5168.620-5168.702"
113399   cell $xor $xor$ls180.v:5168$919
113400     parameter \A_SIGNED 0
113401     parameter \A_WIDTH 1
113402     parameter \B_SIGNED 0
113403     parameter \B_WIDTH 1
113404     parameter \Y_WIDTH 1
113405     connect \A \main_sdcore_crc16_checker_crc0_val [1]
113406     connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
113407     connect \Y $xor$ls180.v:5168$919_Y
113408   end
113409   attribute \src "ls180.v:5168.575-5168.703"
113410   cell $xor $xor$ls180.v:5168$920
113411     parameter \A_SIGNED 0
113412     parameter \A_WIDTH 1
113413     parameter \B_SIGNED 0
113414     parameter \B_WIDTH 1
113415     parameter \Y_WIDTH 1
113416     connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4]
113417     connect \B $xor$ls180.v:5168$919_Y
113418     connect \Y $xor$ls180.v:5168$920_Y
113419   end
113420   attribute \src "ls180.v:5168.229-5168.311"
113421   cell $xor $xor$ls180.v:5168$921
113422     parameter \A_SIGNED 0
113423     parameter \A_WIDTH 1
113424     parameter \B_SIGNED 0
113425     parameter \B_WIDTH 1
113426     parameter \Y_WIDTH 1
113427     connect \A \main_sdcore_crc16_checker_crc0_val [1]
113428     connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15]
113429     connect \Y $xor$ls180.v:5168$921_Y
113430   end
113431   attribute \src "ls180.v:5168.183-5168.312"
113432   cell $xor $xor$ls180.v:5168$922
113433     parameter \A_SIGNED 0
113434     parameter \A_WIDTH 1
113435     parameter \B_SIGNED 0
113436     parameter \B_WIDTH 1
113437     parameter \Y_WIDTH 1
113438     connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11]
113439     connect \B $xor$ls180.v:5168$921_Y
113440     connect \Y $xor$ls180.v:5168$922_Y
113441   end
113442   attribute \src "ls180.v:5169.879-5169.961"
113443   cell $xor $xor$ls180.v:5169$923
113444     parameter \A_SIGNED 0
113445     parameter \A_WIDTH 1
113446     parameter \B_SIGNED 0
113447     parameter \B_WIDTH 1
113448     parameter \Y_WIDTH 1
113449     connect \A \main_sdcore_crc16_checker_crc0_val [0]
113450     connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
113451     connect \Y $xor$ls180.v:5169$923_Y
113452   end
113453   attribute \src "ls180.v:5169.620-5169.702"
113454   cell $xor $xor$ls180.v:5169$924
113455     parameter \A_SIGNED 0
113456     parameter \A_WIDTH 1
113457     parameter \B_SIGNED 0
113458     parameter \B_WIDTH 1
113459     parameter \Y_WIDTH 1
113460     connect \A \main_sdcore_crc16_checker_crc0_val [0]
113461     connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
113462     connect \Y $xor$ls180.v:5169$924_Y
113463   end
113464   attribute \src "ls180.v:5169.575-5169.703"
113465   cell $xor $xor$ls180.v:5169$925
113466     parameter \A_SIGNED 0
113467     parameter \A_WIDTH 1
113468     parameter \B_SIGNED 0
113469     parameter \B_WIDTH 1
113470     parameter \Y_WIDTH 1
113471     connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4]
113472     connect \B $xor$ls180.v:5169$924_Y
113473     connect \Y $xor$ls180.v:5169$925_Y
113474   end
113475   attribute \src "ls180.v:5169.229-5169.311"
113476   cell $xor $xor$ls180.v:5169$926
113477     parameter \A_SIGNED 0
113478     parameter \A_WIDTH 1
113479     parameter \B_SIGNED 0
113480     parameter \B_WIDTH 1
113481     parameter \Y_WIDTH 1
113482     connect \A \main_sdcore_crc16_checker_crc0_val [0]
113483     connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15]
113484     connect \Y $xor$ls180.v:5169$926_Y
113485   end
113486   attribute \src "ls180.v:5169.183-5169.312"
113487   cell $xor $xor$ls180.v:5169$927
113488     parameter \A_SIGNED 0
113489     parameter \A_WIDTH 1
113490     parameter \B_SIGNED 0
113491     parameter \B_WIDTH 1
113492     parameter \Y_WIDTH 1
113493     connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11]
113494     connect \B $xor$ls180.v:5169$926_Y
113495     connect \Y $xor$ls180.v:5169$927_Y
113496   end
113497   attribute \src "ls180.v:5178.879-5178.961"
113498   cell $xor $xor$ls180.v:5178$929
113499     parameter \A_SIGNED 0
113500     parameter \A_WIDTH 1
113501     parameter \B_SIGNED 0
113502     parameter \B_WIDTH 1
113503     parameter \Y_WIDTH 1
113504     connect \A \main_sdcore_crc16_checker_crc1_val [1]
113505     connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
113506     connect \Y $xor$ls180.v:5178$929_Y
113507   end
113508   attribute \src "ls180.v:5178.620-5178.702"
113509   cell $xor $xor$ls180.v:5178$930
113510     parameter \A_SIGNED 0
113511     parameter \A_WIDTH 1
113512     parameter \B_SIGNED 0
113513     parameter \B_WIDTH 1
113514     parameter \Y_WIDTH 1
113515     connect \A \main_sdcore_crc16_checker_crc1_val [1]
113516     connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
113517     connect \Y $xor$ls180.v:5178$930_Y
113518   end
113519   attribute \src "ls180.v:5178.575-5178.703"
113520   cell $xor $xor$ls180.v:5178$931
113521     parameter \A_SIGNED 0
113522     parameter \A_WIDTH 1
113523     parameter \B_SIGNED 0
113524     parameter \B_WIDTH 1
113525     parameter \Y_WIDTH 1
113526     connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4]
113527     connect \B $xor$ls180.v:5178$930_Y
113528     connect \Y $xor$ls180.v:5178$931_Y
113529   end
113530   attribute \src "ls180.v:5178.229-5178.311"
113531   cell $xor $xor$ls180.v:5178$932
113532     parameter \A_SIGNED 0
113533     parameter \A_WIDTH 1
113534     parameter \B_SIGNED 0
113535     parameter \B_WIDTH 1
113536     parameter \Y_WIDTH 1
113537     connect \A \main_sdcore_crc16_checker_crc1_val [1]
113538     connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15]
113539     connect \Y $xor$ls180.v:5178$932_Y
113540   end
113541   attribute \src "ls180.v:5178.183-5178.312"
113542   cell $xor $xor$ls180.v:5178$933
113543     parameter \A_SIGNED 0
113544     parameter \A_WIDTH 1
113545     parameter \B_SIGNED 0
113546     parameter \B_WIDTH 1
113547     parameter \Y_WIDTH 1
113548     connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11]
113549     connect \B $xor$ls180.v:5178$932_Y
113550     connect \Y $xor$ls180.v:5178$933_Y
113551   end
113552   attribute \src "ls180.v:5179.879-5179.961"
113553   cell $xor $xor$ls180.v:5179$934
113554     parameter \A_SIGNED 0
113555     parameter \A_WIDTH 1
113556     parameter \B_SIGNED 0
113557     parameter \B_WIDTH 1
113558     parameter \Y_WIDTH 1
113559     connect \A \main_sdcore_crc16_checker_crc1_val [0]
113560     connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
113561     connect \Y $xor$ls180.v:5179$934_Y
113562   end
113563   attribute \src "ls180.v:5179.620-5179.702"
113564   cell $xor $xor$ls180.v:5179$935
113565     parameter \A_SIGNED 0
113566     parameter \A_WIDTH 1
113567     parameter \B_SIGNED 0
113568     parameter \B_WIDTH 1
113569     parameter \Y_WIDTH 1
113570     connect \A \main_sdcore_crc16_checker_crc1_val [0]
113571     connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
113572     connect \Y $xor$ls180.v:5179$935_Y
113573   end
113574   attribute \src "ls180.v:5179.575-5179.703"
113575   cell $xor $xor$ls180.v:5179$936
113576     parameter \A_SIGNED 0
113577     parameter \A_WIDTH 1
113578     parameter \B_SIGNED 0
113579     parameter \B_WIDTH 1
113580     parameter \Y_WIDTH 1
113581     connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4]
113582     connect \B $xor$ls180.v:5179$935_Y
113583     connect \Y $xor$ls180.v:5179$936_Y
113584   end
113585   attribute \src "ls180.v:5179.229-5179.311"
113586   cell $xor $xor$ls180.v:5179$937
113587     parameter \A_SIGNED 0
113588     parameter \A_WIDTH 1
113589     parameter \B_SIGNED 0
113590     parameter \B_WIDTH 1
113591     parameter \Y_WIDTH 1
113592     connect \A \main_sdcore_crc16_checker_crc1_val [0]
113593     connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15]
113594     connect \Y $xor$ls180.v:5179$937_Y
113595   end
113596   attribute \src "ls180.v:5179.183-5179.312"
113597   cell $xor $xor$ls180.v:5179$938
113598     parameter \A_SIGNED 0
113599     parameter \A_WIDTH 1
113600     parameter \B_SIGNED 0
113601     parameter \B_WIDTH 1
113602     parameter \Y_WIDTH 1
113603     connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11]
113604     connect \B $xor$ls180.v:5179$937_Y
113605     connect \Y $xor$ls180.v:5179$938_Y
113606   end
113607   attribute \src "ls180.v:5188.879-5188.961"
113608   cell $xor $xor$ls180.v:5188$940
113609     parameter \A_SIGNED 0
113610     parameter \A_WIDTH 1
113611     parameter \B_SIGNED 0
113612     parameter \B_WIDTH 1
113613     parameter \Y_WIDTH 1
113614     connect \A \main_sdcore_crc16_checker_crc2_val [1]
113615     connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
113616     connect \Y $xor$ls180.v:5188$940_Y
113617   end
113618   attribute \src "ls180.v:5188.620-5188.702"
113619   cell $xor $xor$ls180.v:5188$941
113620     parameter \A_SIGNED 0
113621     parameter \A_WIDTH 1
113622     parameter \B_SIGNED 0
113623     parameter \B_WIDTH 1
113624     parameter \Y_WIDTH 1
113625     connect \A \main_sdcore_crc16_checker_crc2_val [1]
113626     connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
113627     connect \Y $xor$ls180.v:5188$941_Y
113628   end
113629   attribute \src "ls180.v:5188.575-5188.703"
113630   cell $xor $xor$ls180.v:5188$942
113631     parameter \A_SIGNED 0
113632     parameter \A_WIDTH 1
113633     parameter \B_SIGNED 0
113634     parameter \B_WIDTH 1
113635     parameter \Y_WIDTH 1
113636     connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4]
113637     connect \B $xor$ls180.v:5188$941_Y
113638     connect \Y $xor$ls180.v:5188$942_Y
113639   end
113640   attribute \src "ls180.v:5188.229-5188.311"
113641   cell $xor $xor$ls180.v:5188$943
113642     parameter \A_SIGNED 0
113643     parameter \A_WIDTH 1
113644     parameter \B_SIGNED 0
113645     parameter \B_WIDTH 1
113646     parameter \Y_WIDTH 1
113647     connect \A \main_sdcore_crc16_checker_crc2_val [1]
113648     connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15]
113649     connect \Y $xor$ls180.v:5188$943_Y
113650   end
113651   attribute \src "ls180.v:5188.183-5188.312"
113652   cell $xor $xor$ls180.v:5188$944
113653     parameter \A_SIGNED 0
113654     parameter \A_WIDTH 1
113655     parameter \B_SIGNED 0
113656     parameter \B_WIDTH 1
113657     parameter \Y_WIDTH 1
113658     connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11]
113659     connect \B $xor$ls180.v:5188$943_Y
113660     connect \Y $xor$ls180.v:5188$944_Y
113661   end
113662   attribute \src "ls180.v:5189.879-5189.961"
113663   cell $xor $xor$ls180.v:5189$945
113664     parameter \A_SIGNED 0
113665     parameter \A_WIDTH 1
113666     parameter \B_SIGNED 0
113667     parameter \B_WIDTH 1
113668     parameter \Y_WIDTH 1
113669     connect \A \main_sdcore_crc16_checker_crc2_val [0]
113670     connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
113671     connect \Y $xor$ls180.v:5189$945_Y
113672   end
113673   attribute \src "ls180.v:5189.620-5189.702"
113674   cell $xor $xor$ls180.v:5189$946
113675     parameter \A_SIGNED 0
113676     parameter \A_WIDTH 1
113677     parameter \B_SIGNED 0
113678     parameter \B_WIDTH 1
113679     parameter \Y_WIDTH 1
113680     connect \A \main_sdcore_crc16_checker_crc2_val [0]
113681     connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
113682     connect \Y $xor$ls180.v:5189$946_Y
113683   end
113684   attribute \src "ls180.v:5189.575-5189.703"
113685   cell $xor $xor$ls180.v:5189$947
113686     parameter \A_SIGNED 0
113687     parameter \A_WIDTH 1
113688     parameter \B_SIGNED 0
113689     parameter \B_WIDTH 1
113690     parameter \Y_WIDTH 1
113691     connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4]
113692     connect \B $xor$ls180.v:5189$946_Y
113693     connect \Y $xor$ls180.v:5189$947_Y
113694   end
113695   attribute \src "ls180.v:5189.229-5189.311"
113696   cell $xor $xor$ls180.v:5189$948
113697     parameter \A_SIGNED 0
113698     parameter \A_WIDTH 1
113699     parameter \B_SIGNED 0
113700     parameter \B_WIDTH 1
113701     parameter \Y_WIDTH 1
113702     connect \A \main_sdcore_crc16_checker_crc2_val [0]
113703     connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15]
113704     connect \Y $xor$ls180.v:5189$948_Y
113705   end
113706   attribute \src "ls180.v:5189.183-5189.312"
113707   cell $xor $xor$ls180.v:5189$949
113708     parameter \A_SIGNED 0
113709     parameter \A_WIDTH 1
113710     parameter \B_SIGNED 0
113711     parameter \B_WIDTH 1
113712     parameter \Y_WIDTH 1
113713     connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11]
113714     connect \B $xor$ls180.v:5189$948_Y
113715     connect \Y $xor$ls180.v:5189$949_Y
113716   end
113717   attribute \src "ls180.v:5198.879-5198.961"
113718   cell $xor $xor$ls180.v:5198$951
113719     parameter \A_SIGNED 0
113720     parameter \A_WIDTH 1
113721     parameter \B_SIGNED 0
113722     parameter \B_WIDTH 1
113723     parameter \Y_WIDTH 1
113724     connect \A \main_sdcore_crc16_checker_crc3_val [1]
113725     connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
113726     connect \Y $xor$ls180.v:5198$951_Y
113727   end
113728   attribute \src "ls180.v:5198.620-5198.702"
113729   cell $xor $xor$ls180.v:5198$952
113730     parameter \A_SIGNED 0
113731     parameter \A_WIDTH 1
113732     parameter \B_SIGNED 0
113733     parameter \B_WIDTH 1
113734     parameter \Y_WIDTH 1
113735     connect \A \main_sdcore_crc16_checker_crc3_val [1]
113736     connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
113737     connect \Y $xor$ls180.v:5198$952_Y
113738   end
113739   attribute \src "ls180.v:5198.575-5198.703"
113740   cell $xor $xor$ls180.v:5198$953
113741     parameter \A_SIGNED 0
113742     parameter \A_WIDTH 1
113743     parameter \B_SIGNED 0
113744     parameter \B_WIDTH 1
113745     parameter \Y_WIDTH 1
113746     connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4]
113747     connect \B $xor$ls180.v:5198$952_Y
113748     connect \Y $xor$ls180.v:5198$953_Y
113749   end
113750   attribute \src "ls180.v:5198.229-5198.311"
113751   cell $xor $xor$ls180.v:5198$954
113752     parameter \A_SIGNED 0
113753     parameter \A_WIDTH 1
113754     parameter \B_SIGNED 0
113755     parameter \B_WIDTH 1
113756     parameter \Y_WIDTH 1
113757     connect \A \main_sdcore_crc16_checker_crc3_val [1]
113758     connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15]
113759     connect \Y $xor$ls180.v:5198$954_Y
113760   end
113761   attribute \src "ls180.v:5198.183-5198.312"
113762   cell $xor $xor$ls180.v:5198$955
113763     parameter \A_SIGNED 0
113764     parameter \A_WIDTH 1
113765     parameter \B_SIGNED 0
113766     parameter \B_WIDTH 1
113767     parameter \Y_WIDTH 1
113768     connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11]
113769     connect \B $xor$ls180.v:5198$954_Y
113770     connect \Y $xor$ls180.v:5198$955_Y
113771   end
113772   attribute \src "ls180.v:5199.879-5199.961"
113773   cell $xor $xor$ls180.v:5199$956
113774     parameter \A_SIGNED 0
113775     parameter \A_WIDTH 1
113776     parameter \B_SIGNED 0
113777     parameter \B_WIDTH 1
113778     parameter \Y_WIDTH 1
113779     connect \A \main_sdcore_crc16_checker_crc3_val [0]
113780     connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
113781     connect \Y $xor$ls180.v:5199$956_Y
113782   end
113783   attribute \src "ls180.v:5199.620-5199.702"
113784   cell $xor $xor$ls180.v:5199$957
113785     parameter \A_SIGNED 0
113786     parameter \A_WIDTH 1
113787     parameter \B_SIGNED 0
113788     parameter \B_WIDTH 1
113789     parameter \Y_WIDTH 1
113790     connect \A \main_sdcore_crc16_checker_crc3_val [0]
113791     connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
113792     connect \Y $xor$ls180.v:5199$957_Y
113793   end
113794   attribute \src "ls180.v:5199.575-5199.703"
113795   cell $xor $xor$ls180.v:5199$958
113796     parameter \A_SIGNED 0
113797     parameter \A_WIDTH 1
113798     parameter \B_SIGNED 0
113799     parameter \B_WIDTH 1
113800     parameter \Y_WIDTH 1
113801     connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4]
113802     connect \B $xor$ls180.v:5199$957_Y
113803     connect \Y $xor$ls180.v:5199$958_Y
113804   end
113805   attribute \src "ls180.v:5199.229-5199.311"
113806   cell $xor $xor$ls180.v:5199$959
113807     parameter \A_SIGNED 0
113808     parameter \A_WIDTH 1
113809     parameter \B_SIGNED 0
113810     parameter \B_WIDTH 1
113811     parameter \Y_WIDTH 1
113812     connect \A \main_sdcore_crc16_checker_crc3_val [0]
113813     connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15]
113814     connect \Y $xor$ls180.v:5199$959_Y
113815   end
113816   attribute \src "ls180.v:5199.183-5199.312"
113817   cell $xor $xor$ls180.v:5199$960
113818     parameter \A_SIGNED 0
113819     parameter \A_WIDTH 1
113820     parameter \B_SIGNED 0
113821     parameter \B_WIDTH 1
113822     parameter \Y_WIDTH 1
113823     connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11]
113824     connect \B $xor$ls180.v:5199$959_Y
113825     connect \Y $xor$ls180.v:5199$960_Y
113826   end
113827   attribute \module_not_derived 1
113828   attribute \src "ls180.v:10195.13-10573.2"
113829   cell \test_issuer \test_issuer
113830     connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck
113831     connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi
113832     connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo
113833     connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms
113834     connect \busy_o \main_libresocsim_libresoc0
113835     connect \clk \sys_clk_1
113836     connect \clk_sel_i \main_libresocsim_libresoc_clk_sel
113837     connect \core_bigendian_i 1'0
113838     connect \dbus__ack \main_libresocsim_libresoc_dbus_ack
113839     connect \dbus__adr \main_libresocsim_libresoc_dbus_adr
113840     connect \dbus__bte \main_libresocsim_libresoc_dbus_bte
113841     connect \dbus__cti \main_libresocsim_libresoc_dbus_cti
113842     connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc
113843     connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r
113844     connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w
113845     connect \dbus__err \main_libresocsim_libresoc_dbus_err
113846     connect \dbus__sel \main_libresocsim_libresoc_dbus_sel
113847     connect \dbus__stb \main_libresocsim_libresoc_dbus_stb
113848     connect \dbus__we \main_libresocsim_libresoc_dbus_we
113849     connect \eint_0__core__i \eint [0]
113850     connect \eint_0__pad__i \eint_1 [0]
113851     connect \eint_1__core__i \eint [1]
113852     connect \eint_1__pad__i \eint_1 [1]
113853     connect \eint_2__core__i \eint [2]
113854     connect \eint_2__pad__i \eint_1 [2]
113855     connect \gpio_e10__core__i \gpio_i [10]
113856     connect \gpio_e10__core__o \gpio_o [10]
113857     connect \gpio_e10__core__oe \gpio_oe [10]
113858     connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10]
113859     connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10]
113860     connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10]
113861     connect \gpio_e11__core__i \gpio_i [11]
113862     connect \gpio_e11__core__o \gpio_o [11]
113863     connect \gpio_e11__core__oe \gpio_oe [11]
113864     connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11]
113865     connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11]
113866     connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11]
113867     connect \gpio_e12__core__i \gpio_i [12]
113868     connect \gpio_e12__core__o \gpio_o [12]
113869     connect \gpio_e12__core__oe \gpio_oe [12]
113870     connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12]
113871     connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12]
113872     connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12]
113873     connect \gpio_e13__core__i \gpio_i [13]
113874     connect \gpio_e13__core__o \gpio_o [13]
113875     connect \gpio_e13__core__oe \gpio_oe [13]
113876     connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13]
113877     connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13]
113878     connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13]
113879     connect \gpio_e14__core__i \gpio_i [14]
113880     connect \gpio_e14__core__o \gpio_o [14]
113881     connect \gpio_e14__core__oe \gpio_oe [14]
113882     connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14]
113883     connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14]
113884     connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14]
113885     connect \gpio_e15__core__i \gpio_i [15]
113886     connect \gpio_e15__core__o \gpio_o [15]
113887     connect \gpio_e15__core__oe \gpio_oe [15]
113888     connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15]
113889     connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15]
113890     connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15]
113891     connect \gpio_e8__core__i \gpio_i [8]
113892     connect \gpio_e8__core__o \gpio_o [8]
113893     connect \gpio_e8__core__oe \gpio_oe [8]
113894     connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8]
113895     connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8]
113896     connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8]
113897     connect \gpio_e9__core__i \gpio_i [9]
113898     connect \gpio_e9__core__o \gpio_o [9]
113899     connect \gpio_e9__core__oe \gpio_oe [9]
113900     connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9]
113901     connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9]
113902     connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9]
113903     connect \gpio_s0__core__i \gpio_i [0]
113904     connect \gpio_s0__core__o \gpio_o [0]
113905     connect \gpio_s0__core__oe \gpio_oe [0]
113906     connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0]
113907     connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0]
113908     connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0]
113909     connect \gpio_s1__core__i \gpio_i [1]
113910     connect \gpio_s1__core__o \gpio_o [1]
113911     connect \gpio_s1__core__oe \gpio_oe [1]
113912     connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1]
113913     connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1]
113914     connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1]
113915     connect \gpio_s2__core__i \gpio_i [2]
113916     connect \gpio_s2__core__o \gpio_o [2]
113917     connect \gpio_s2__core__oe \gpio_oe [2]
113918     connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2]
113919     connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2]
113920     connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2]
113921     connect \gpio_s3__core__i \gpio_i [3]
113922     connect \gpio_s3__core__o \gpio_o [3]
113923     connect \gpio_s3__core__oe \gpio_oe [3]
113924     connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3]
113925     connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3]
113926     connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3]
113927     connect \gpio_s4__core__i \gpio_i [4]
113928     connect \gpio_s4__core__o \gpio_o [4]
113929     connect \gpio_s4__core__oe \gpio_oe [4]
113930     connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4]
113931     connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4]
113932     connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4]
113933     connect \gpio_s5__core__i \gpio_i [5]
113934     connect \gpio_s5__core__o \gpio_o [5]
113935     connect \gpio_s5__core__oe \gpio_oe [5]
113936     connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5]
113937     connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5]
113938     connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5]
113939     connect \gpio_s6__core__i \gpio_i [6]
113940     connect \gpio_s6__core__o \gpio_o [6]
113941     connect \gpio_s6__core__oe \gpio_oe [6]
113942     connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6]
113943     connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6]
113944     connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6]
113945     connect \gpio_s7__core__i \gpio_i [7]
113946     connect \gpio_s7__core__o \gpio_o [7]
113947     connect \gpio_s7__core__oe \gpio_oe [7]
113948     connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7]
113949     connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7]
113950     connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7]
113951     connect \ibus__ack \main_libresocsim_libresoc_ibus_ack
113952     connect \ibus__adr \main_libresocsim_libresoc_ibus_adr
113953     connect \ibus__bte \main_libresocsim_libresoc_ibus_bte
113954     connect \ibus__cti \main_libresocsim_libresoc_ibus_cti
113955     connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc
113956     connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r
113957     connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w
113958     connect \ibus__err \main_libresocsim_libresoc_ibus_err
113959     connect \ibus__sel \main_libresocsim_libresoc_ibus_sel
113960     connect \ibus__stb \main_libresocsim_libresoc_ibus_stb
113961     connect \ibus__we \main_libresocsim_libresoc_ibus_we
113962     connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack
113963     connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr
113964     connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte
113965     connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti
113966     connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc
113967     connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r
113968     connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w
113969     connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err
113970     connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel
113971     connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb
113972     connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we
113973     connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack
113974     connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr
113975     connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte
113976     connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti
113977     connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc
113978     connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r
113979     connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w
113980     connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err
113981     connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel
113982     connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb
113983     connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we
113984     connect \int_level_i \main_libresocsim_libresoc_interrupt
113985     connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack
113986     connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr
113987     connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc
113988     connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r
113989     connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w
113990     connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err
113991     connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel
113992     connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb
113993     connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we
113994     connect \memerr_o \main_libresocsim_libresoc1
113995     connect \mspi0_clk__core__o \spimaster_clk
113996     connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
113997     connect \mspi0_cs_n__core__o \spimaster_cs_n
113998     connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
113999     connect \mspi0_miso__core__i \spimaster_miso
114000     connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
114001     connect \mspi0_mosi__core__o \spimaster_mosi
114002     connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
114003     connect \mspi1_clk__core__o \spisdcard_clk
114004     connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
114005     connect \mspi1_cs_n__core__o \spisdcard_cs_n
114006     connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
114007     connect \mspi1_miso__core__i \spisdcard_miso
114008     connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
114009     connect \mspi1_mosi__core__o \spisdcard_mosi
114010     connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
114011     connect \mtwi_scl__core__o \i2c_scl
114012     connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
114013     connect \mtwi_sda__core__i \i2c_sda_i
114014     connect \mtwi_sda__core__o \i2c_sda_o
114015     connect \mtwi_sda__core__oe \i2c_sda_oe
114016     connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
114017     connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
114018     connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
114019     connect \pc_i 1'0
114020     connect \pc_i_ok 1'0
114021     connect \pc_o \main_libresocsim_libresoc2
114022     connect \pll_18_o \main_libresocsim_libresoc_pll_18_o
114023     connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o
114024     connect \pwm_0__core__o \pwm [0]
114025     connect \pwm_0__pad__o \pwm_1 [0]
114026     connect \pwm_1__core__o \pwm [1]
114027     connect \pwm_1__pad__o \pwm_1 [1]
114028     connect \rst $or$ls180.v:10295$2762_Y
114029     connect \sd0_clk__core__o \sdcard_clk
114030     connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
114031     connect \sd0_cmd__core__i \sdcard_cmd_i
114032     connect \sd0_cmd__core__o \sdcard_cmd_o
114033     connect \sd0_cmd__core__oe \sdcard_cmd_oe
114034     connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
114035     connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
114036     connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
114037     connect \sd0_data0__core__i \sdcard_cmd_i
114038     connect \sd0_data0__core__o \sdcard_cmd_o
114039     connect \sd0_data0__core__oe \sdcard_cmd_oe
114040     connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
114041     connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
114042     connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
114043     connect \sd0_data1__core__i \sdcard_cmd_i
114044     connect \sd0_data1__core__o \sdcard_cmd_o
114045     connect \sd0_data1__core__oe \sdcard_cmd_oe
114046     connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
114047     connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
114048     connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
114049     connect \sd0_data2__core__i \sdcard_cmd_i
114050     connect \sd0_data2__core__o \sdcard_cmd_o
114051     connect \sd0_data2__core__oe \sdcard_cmd_oe
114052     connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
114053     connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
114054     connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
114055     connect \sd0_data3__core__i \sdcard_cmd_i
114056     connect \sd0_data3__core__o \sdcard_cmd_o
114057     connect \sd0_data3__core__oe \sdcard_cmd_oe
114058     connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
114059     connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
114060     connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
114061     connect \sdr_a_0__core__o \sdram_a [0]
114062     connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0]
114063     connect \sdr_a_10__core__o \sdram_a [10]
114064     connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10]
114065     connect \sdr_a_11__core__o \sdram_a [11]
114066     connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11]
114067     connect \sdr_a_12__core__o \sdram_a [12]
114068     connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12]
114069     connect \sdr_a_1__core__o \sdram_a [1]
114070     connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1]
114071     connect \sdr_a_2__core__o \sdram_a [2]
114072     connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2]
114073     connect \sdr_a_3__core__o \sdram_a [3]
114074     connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3]
114075     connect \sdr_a_4__core__o \sdram_a [4]
114076     connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4]
114077     connect \sdr_a_5__core__o \sdram_a [5]
114078     connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5]
114079     connect \sdr_a_6__core__o \sdram_a [6]
114080     connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6]
114081     connect \sdr_a_7__core__o \sdram_a [7]
114082     connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7]
114083     connect \sdr_a_8__core__o \sdram_a [8]
114084     connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8]
114085     connect \sdr_a_9__core__o \sdram_a [9]
114086     connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9]
114087     connect \sdr_ba_0__core__o \sdram_ba [0]
114088     connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0]
114089     connect \sdr_ba_1__core__o \sdram_ba [1]
114090     connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1]
114091     connect \sdr_cas_n__core__o \sdram_cas_n
114092     connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
114093     connect \sdr_cke__core__o \sdram_cke
114094     connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
114095     connect \sdr_clock__core__o \sdram_clock
114096     connect \sdr_clock__pad__o \sdram_clock_1
114097     connect \sdr_cs_n__core__o \sdram_cs_n
114098     connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
114099     connect \sdr_dm_0__core__o \sdram_dm [0]
114100     connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0]
114101     connect \sdr_dm_1__core__i \sdram_dq_i [1]
114102     connect \sdr_dm_1__core__o \sdram_dq_o [1]
114103     connect \sdr_dm_1__core__oe \sdram_dq_oe
114104     connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1]
114105     connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1]
114106     connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114107     connect \sdr_dq_0__core__i \sdram_dq_i [0]
114108     connect \sdr_dq_0__core__o \sdram_dq_o [0]
114109     connect \sdr_dq_0__core__oe \sdram_dq_oe
114110     connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0]
114111     connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0]
114112     connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114113     connect \sdr_dq_10__core__i \sdram_dq_i [10]
114114     connect \sdr_dq_10__core__o \sdram_dq_o [10]
114115     connect \sdr_dq_10__core__oe \sdram_dq_oe
114116     connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10]
114117     connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10]
114118     connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114119     connect \sdr_dq_11__core__i \sdram_dq_i [11]
114120     connect \sdr_dq_11__core__o \sdram_dq_o [11]
114121     connect \sdr_dq_11__core__oe \sdram_dq_oe
114122     connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11]
114123     connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11]
114124     connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114125     connect \sdr_dq_12__core__i \sdram_dq_i [12]
114126     connect \sdr_dq_12__core__o \sdram_dq_o [12]
114127     connect \sdr_dq_12__core__oe \sdram_dq_oe
114128     connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12]
114129     connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12]
114130     connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114131     connect \sdr_dq_13__core__i \sdram_dq_i [13]
114132     connect \sdr_dq_13__core__o \sdram_dq_o [13]
114133     connect \sdr_dq_13__core__oe \sdram_dq_oe
114134     connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13]
114135     connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13]
114136     connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114137     connect \sdr_dq_14__core__i \sdram_dq_i [14]
114138     connect \sdr_dq_14__core__o \sdram_dq_o [14]
114139     connect \sdr_dq_14__core__oe \sdram_dq_oe
114140     connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14]
114141     connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14]
114142     connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114143     connect \sdr_dq_15__core__i \sdram_dq_i [15]
114144     connect \sdr_dq_15__core__o \sdram_dq_o [15]
114145     connect \sdr_dq_15__core__oe \sdram_dq_oe
114146     connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15]
114147     connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15]
114148     connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114149     connect \sdr_dq_1__core__i \sdram_dq_i [1]
114150     connect \sdr_dq_1__core__o \sdram_dq_o [1]
114151     connect \sdr_dq_1__core__oe \sdram_dq_oe
114152     connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1]
114153     connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1]
114154     connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114155     connect \sdr_dq_2__core__i \sdram_dq_i [2]
114156     connect \sdr_dq_2__core__o \sdram_dq_o [2]
114157     connect \sdr_dq_2__core__oe \sdram_dq_oe
114158     connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2]
114159     connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2]
114160     connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114161     connect \sdr_dq_3__core__i \sdram_dq_i [3]
114162     connect \sdr_dq_3__core__o \sdram_dq_o [3]
114163     connect \sdr_dq_3__core__oe \sdram_dq_oe
114164     connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3]
114165     connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3]
114166     connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114167     connect \sdr_dq_4__core__i \sdram_dq_i [4]
114168     connect \sdr_dq_4__core__o \sdram_dq_o [4]
114169     connect \sdr_dq_4__core__oe \sdram_dq_oe
114170     connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4]
114171     connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4]
114172     connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114173     connect \sdr_dq_5__core__i \sdram_dq_i [5]
114174     connect \sdr_dq_5__core__o \sdram_dq_o [5]
114175     connect \sdr_dq_5__core__oe \sdram_dq_oe
114176     connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5]
114177     connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5]
114178     connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114179     connect \sdr_dq_6__core__i \sdram_dq_i [6]
114180     connect \sdr_dq_6__core__o \sdram_dq_o [6]
114181     connect \sdr_dq_6__core__oe \sdram_dq_oe
114182     connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6]
114183     connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6]
114184     connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114185     connect \sdr_dq_7__core__i \sdram_dq_i [7]
114186     connect \sdr_dq_7__core__o \sdram_dq_o [7]
114187     connect \sdr_dq_7__core__oe \sdram_dq_oe
114188     connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7]
114189     connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7]
114190     connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114191     connect \sdr_dq_8__core__i \sdram_dq_i [8]
114192     connect \sdr_dq_8__core__o \sdram_dq_o [8]
114193     connect \sdr_dq_8__core__oe \sdram_dq_oe
114194     connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8]
114195     connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8]
114196     connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114197     connect \sdr_dq_9__core__i \sdram_dq_i [9]
114198     connect \sdr_dq_9__core__o \sdram_dq_o [9]
114199     connect \sdr_dq_9__core__oe \sdram_dq_oe
114200     connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9]
114201     connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9]
114202     connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
114203     connect \sdr_ras_n__core__o \sdram_ras_n
114204     connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
114205     connect \sdr_we_n__core__o \sdram_we_n
114206     connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
114207   end
114208   attribute \src "ls180.v:0.0-0.0"
114209   process $proc$ls180.v:0$3720
114210     sync always
114211     sync init
114212   end
114213   attribute \src "ls180.v:1000.12-1000.47"
114214   process $proc$ls180.v:1000$3146
114215     assign { } { }
114216     assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
114217     sync always
114218       update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0]
114219     sync init
114220   end
114221   attribute \src "ls180.v:1001.5-1001.33"
114222   process $proc$ls180.v:1001$3147
114223     assign { } { }
114224     assign $1\main_spimaster9_start[0:0] 1'0
114225     sync always
114226     sync init
114227       update \main_spimaster9_start $1\main_spimaster9_start[0:0]
114228   end
114229   attribute \src "ls180.v:1003.12-1003.44"
114230   process $proc$ls180.v:1003$3148
114231     assign { } { }
114232     assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
114233     sync always
114234     sync init
114235       update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
114236   end
114237   attribute \src "ls180.v:1004.5-1004.31"
114238   process $proc$ls180.v:1004$3149
114239     assign { } { }
114240     assign $1\main_spimaster12_re[0:0] 1'0
114241     sync always
114242     sync init
114243       update \main_spimaster12_re $1\main_spimaster12_re[0:0]
114244   end
114245   attribute \src "ls180.v:10059.1-10069.4"
114246   process $proc$ls180.v:10059$2692
114247     assign { } { }
114248     assign { } { }
114249     assign { } { }
114250     assign { } { }
114251     assign { } { }
114252     assign { } { }
114253     assign { } { }
114254     assign { } { }
114255     assign { } { }
114256     assign { } { }
114257     assign { } { }
114258     assign { } { }
114259     assign { } { }
114260     assign $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 7'xxxxxxx
114261     assign $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
114262     assign $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 0
114263     assign $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 7'xxxxxxx
114264     assign $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
114265     assign $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 0
114266     assign $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 7'xxxxxxx
114267     assign $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
114268     assign $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 0
114269     assign $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 7'xxxxxxx
114270     assign $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
114271     assign $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 0
114272     assign $0\memadr[6:0] \main_libresocsim_adr
114273     attribute \src "ls180.v:10060.2-10061.65"
114274     switch \main_libresocsim_we [0]
114275       attribute \src "ls180.v:10060.6-10060.28"
114276       case 1'1
114277         assign $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 \main_libresocsim_adr
114278         assign $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] }
114279         assign $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 255
114280       case
114281     end
114282     attribute \src "ls180.v:10062.2-10063.67"
114283     switch \main_libresocsim_we [1]
114284       attribute \src "ls180.v:10062.6-10062.28"
114285       case 1'1
114286         assign $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 \main_libresocsim_adr
114287         assign $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
114288         assign $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 65280
114289       case
114290     end
114291     attribute \src "ls180.v:10064.2-10065.69"
114292     switch \main_libresocsim_we [2]
114293       attribute \src "ls180.v:10064.6-10064.28"
114294       case 1'1
114295         assign $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 \main_libresocsim_adr
114296         assign $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
114297         assign $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 16711680
114298       case
114299     end
114300     attribute \src "ls180.v:10066.2-10067.69"
114301     switch \main_libresocsim_we [3]
114302       attribute \src "ls180.v:10066.6-10066.28"
114303       case 1'1
114304         assign $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 \main_libresocsim_adr
114305         assign $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
114306         assign $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 32'11111111000000000000000000000000
114307       case
114308     end
114309     sync posedge \sys_clk_1
114310       update \memadr $0\memadr[6:0]
114311       update $memwr$\mem$ls180.v:10061$1_ADDR $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693
114312       update $memwr$\mem$ls180.v:10061$1_DATA $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694
114313       update $memwr$\mem$ls180.v:10061$1_EN $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695
114314       update $memwr$\mem$ls180.v:10063$2_ADDR $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696
114315       update $memwr$\mem$ls180.v:10063$2_DATA $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697
114316       update $memwr$\mem$ls180.v:10063$2_EN $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698
114317       update $memwr$\mem$ls180.v:10065$3_ADDR $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699
114318       update $memwr$\mem$ls180.v:10065$3_DATA $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700
114319       update $memwr$\mem$ls180.v:10065$3_EN $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701
114320       update $memwr$\mem$ls180.v:10067$4_ADDR $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702
114321       update $memwr$\mem$ls180.v:10067$4_DATA $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703
114322       update $memwr$\mem$ls180.v:10067$4_EN $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704
114323   end
114324   attribute \src "ls180.v:10079.1-10083.4"
114325   process $proc$ls180.v:10079$2706
114326     assign { } { }
114327     assign { } { }
114328     assign { } { }
114329     assign { } { }
114330     assign $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 3'xxx
114331     assign $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx
114332     assign $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 25'0000000000000000000000000
114333     assign $0\memdat[24:0] $memrd$\storage$ls180.v:10082$2710_DATA
114334     attribute \src "ls180.v:10080.2-10081.129"
114335     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
114336       attribute \src "ls180.v:10080.6-10080.60"
114337       case 1'1
114338         assign $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
114339         assign $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
114340         assign $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 25'1111111111111111111111111
114341       case
114342     end
114343     sync posedge \sys_clk_1
114344       update \memdat $0\memdat[24:0]
114345       update $memwr$\storage$ls180.v:10081$5_ADDR $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707
114346       update $memwr$\storage$ls180.v:10081$5_DATA $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708
114347       update $memwr$\storage$ls180.v:10081$5_EN $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709
114348   end
114349   attribute \src "ls180.v:1008.11-1008.42"
114350   process $proc$ls180.v:1008$3150
114351     assign { } { }
114352     assign $1\main_spimaster16_storage[7:0] 8'00000000
114353     sync always
114354     sync init
114355       update \main_spimaster16_storage $1\main_spimaster16_storage[7:0]
114356   end
114357   attribute \src "ls180.v:10085.1-10086.4"
114358   process $proc$ls180.v:10085$2711
114359     sync posedge \sys_clk_1
114360   end
114361   attribute \src "ls180.v:1009.5-1009.31"
114362   process $proc$ls180.v:1009$3151
114363     assign { } { }
114364     assign $1\main_spimaster17_re[0:0] 1'0
114365     sync always
114366     sync init
114367       update \main_spimaster17_re $1\main_spimaster17_re[0:0]
114368   end
114369   attribute \src "ls180.v:10093.1-10097.4"
114370   process $proc$ls180.v:10093$2713
114371     assign { } { }
114372     assign { } { }
114373     assign { } { }
114374     assign { } { }
114375     assign $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 3'xxx
114376     assign $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx
114377     assign $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 25'0000000000000000000000000
114378     assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10096$2717_DATA
114379     attribute \src "ls180.v:10094.2-10095.131"
114380     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
114381       attribute \src "ls180.v:10094.6-10094.60"
114382       case 1'1
114383         assign $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
114384         assign $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
114385         assign $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 25'1111111111111111111111111
114386       case
114387     end
114388     sync posedge \sys_clk_1
114389       update \memdat_1 $0\memdat_1[24:0]
114390       update $memwr$\storage_1$ls180.v:10095$6_ADDR $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714
114391       update $memwr$\storage_1$ls180.v:10095$6_DATA $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715
114392       update $memwr$\storage_1$ls180.v:10095$6_EN $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716
114393   end
114394   attribute \src "ls180.v:10099.1-10100.4"
114395   process $proc$ls180.v:10099$2718
114396     sync posedge \sys_clk_1
114397   end
114398   attribute \src "ls180.v:10107.1-10111.4"
114399   process $proc$ls180.v:10107$2720
114400     assign { } { }
114401     assign { } { }
114402     assign { } { }
114403     assign { } { }
114404     assign $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 3'xxx
114405     assign $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx
114406     assign $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 25'0000000000000000000000000
114407     assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10110$2724_DATA
114408     attribute \src "ls180.v:10108.2-10109.131"
114409     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
114410       attribute \src "ls180.v:10108.6-10108.60"
114411       case 1'1
114412         assign $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
114413         assign $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
114414         assign $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 25'1111111111111111111111111
114415       case
114416     end
114417     sync posedge \sys_clk_1
114418       update \memdat_2 $0\memdat_2[24:0]
114419       update $memwr$\storage_2$ls180.v:10109$7_ADDR $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721
114420       update $memwr$\storage_2$ls180.v:10109$7_DATA $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722
114421       update $memwr$\storage_2$ls180.v:10109$7_EN $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723
114422   end
114423   attribute \src "ls180.v:10113.1-10114.4"
114424   process $proc$ls180.v:10113$2725
114425     sync posedge \sys_clk_1
114426   end
114427   attribute \src "ls180.v:10121.1-10125.4"
114428   process $proc$ls180.v:10121$2727
114429     assign { } { }
114430     assign { } { }
114431     assign { } { }
114432     assign { } { }
114433     assign $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 3'xxx
114434     assign $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx
114435     assign $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 25'0000000000000000000000000
114436     assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10124$2731_DATA
114437     attribute \src "ls180.v:10122.2-10123.131"
114438     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
114439       attribute \src "ls180.v:10122.6-10122.60"
114440       case 1'1
114441         assign $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
114442         assign $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
114443         assign $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 25'1111111111111111111111111
114444       case
114445     end
114446     sync posedge \sys_clk_1
114447       update \memdat_3 $0\memdat_3[24:0]
114448       update $memwr$\storage_3$ls180.v:10123$8_ADDR $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728
114449       update $memwr$\storage_3$ls180.v:10123$8_DATA $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729
114450       update $memwr$\storage_3$ls180.v:10123$8_EN $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730
114451   end
114452   attribute \src "ls180.v:10127.1-10128.4"
114453   process $proc$ls180.v:10127$2732
114454     sync posedge \sys_clk_1
114455   end
114456   attribute \src "ls180.v:1013.5-1013.36"
114457   process $proc$ls180.v:1013$3152
114458     assign { } { }
114459     assign $1\main_spimaster21_storage[0:0] 1'1
114460     sync always
114461     sync init
114462       update \main_spimaster21_storage $1\main_spimaster21_storage[0:0]
114463   end
114464   attribute \src "ls180.v:10136.1-10140.4"
114465   process $proc$ls180.v:10136$2734
114466     assign { } { }
114467     assign { } { }
114468     assign { } { }
114469     assign { } { }
114470     assign $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 4'xxxx
114471     assign $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 10'xxxxxxxxxx
114472     assign $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 10'0000000000
114473     assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10139$2738_DATA
114474     attribute \src "ls180.v:10137.2-10138.77"
114475     switch \main_uart_tx_fifo_wrport_we
114476       attribute \src "ls180.v:10137.6-10137.33"
114477       case 1'1
114478         assign $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr
114479         assign $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w
114480         assign $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 10'1111111111
114481       case
114482     end
114483     sync posedge \sys_clk_1
114484       update \memdat_4 $0\memdat_4[9:0]
114485       update $memwr$\storage_4$ls180.v:10138$9_ADDR $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735
114486       update $memwr$\storage_4$ls180.v:10138$9_DATA $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736
114487       update $memwr$\storage_4$ls180.v:10138$9_EN $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737
114488   end
114489   attribute \src "ls180.v:1014.5-1014.31"
114490   process $proc$ls180.v:1014$3153
114491     assign { } { }
114492     assign $1\main_spimaster22_re[0:0] 1'0
114493     sync always
114494     sync init
114495       update \main_spimaster22_re $1\main_spimaster22_re[0:0]
114496   end
114497   attribute \src "ls180.v:10142.1-10145.4"
114498   process $proc$ls180.v:10142$2739
114499     assign $0\memdat_5[9:0] \memdat_5
114500     attribute \src "ls180.v:10143.2-10144.55"
114501     switch \main_uart_tx_fifo_rdport_re
114502       attribute \src "ls180.v:10143.6-10143.33"
114503       case 1'1
114504         assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10144$2740_DATA
114505       case
114506     end
114507     sync posedge \sys_clk_1
114508       update \memdat_5 $0\memdat_5[9:0]
114509   end
114510   attribute \src "ls180.v:1015.5-1015.36"
114511   process $proc$ls180.v:1015$3154
114512     assign { } { }
114513     assign $1\main_spimaster23_storage[0:0] 1'0
114514     sync always
114515     sync init
114516       update \main_spimaster23_storage $1\main_spimaster23_storage[0:0]
114517   end
114518   attribute \src "ls180.v:10153.1-10157.4"
114519   process $proc$ls180.v:10153$2741
114520     assign { } { }
114521     assign { } { }
114522     assign { } { }
114523     assign { } { }
114524     assign $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 4'xxxx
114525     assign $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 10'xxxxxxxxxx
114526     assign $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 10'0000000000
114527     assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10156$2745_DATA
114528     attribute \src "ls180.v:10154.2-10155.77"
114529     switch \main_uart_rx_fifo_wrport_we
114530       attribute \src "ls180.v:10154.6-10154.33"
114531       case 1'1
114532         assign $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr
114533         assign $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w
114534         assign $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 10'1111111111
114535       case
114536     end
114537     sync posedge \sys_clk_1
114538       update \memdat_6 $0\memdat_6[9:0]
114539       update $memwr$\storage_5$ls180.v:10155$10_ADDR $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742
114540       update $memwr$\storage_5$ls180.v:10155$10_DATA $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743
114541       update $memwr$\storage_5$ls180.v:10155$10_EN $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744
114542   end
114543   attribute \src "ls180.v:10159.1-10162.4"
114544   process $proc$ls180.v:10159$2746
114545     assign $0\memdat_7[9:0] \memdat_7
114546     attribute \src "ls180.v:10160.2-10161.55"
114547     switch \main_uart_rx_fifo_rdport_re
114548       attribute \src "ls180.v:10160.6-10160.33"
114549       case 1'1
114550         assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10161$2747_DATA
114551       case
114552     end
114553     sync posedge \sys_clk_1
114554       update \memdat_7 $0\memdat_7[9:0]
114555   end
114556   attribute \src "ls180.v:1016.5-1016.31"
114557   process $proc$ls180.v:1016$3155
114558     assign { } { }
114559     assign $1\main_spimaster24_re[0:0] 1'0
114560     sync always
114561     sync init
114562       update \main_spimaster24_re $1\main_spimaster24_re[0:0]
114563   end
114564   attribute \src "ls180.v:10169.1-10173.4"
114565   process $proc$ls180.v:10169$2748
114566     assign { } { }
114567     assign { } { }
114568     assign { } { }
114569     assign { } { }
114570     assign $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 5'xxxxx
114571     assign $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 10'xxxxxxxxxx
114572     assign $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 10'0000000000
114573     assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10172$2752_DATA
114574     attribute \src "ls180.v:10170.2-10171.85"
114575     switch \main_sdblock2mem_fifo_wrport_we
114576       attribute \src "ls180.v:10170.6-10170.37"
114577       case 1'1
114578         assign $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr
114579         assign $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w
114580         assign $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 10'1111111111
114581       case
114582     end
114583     sync posedge \sys_clk_1
114584       update \memdat_8 $0\memdat_8[9:0]
114585       update $memwr$\storage_6$ls180.v:10171$11_ADDR $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749
114586       update $memwr$\storage_6$ls180.v:10171$11_DATA $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750
114587       update $memwr$\storage_6$ls180.v:10171$11_EN $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751
114588   end
114589   attribute \src "ls180.v:1017.5-1017.39"
114590   process $proc$ls180.v:1017$3156
114591     assign { } { }
114592     assign $1\main_spimaster25_clk_enable[0:0] 1'0
114593     sync always
114594     sync init
114595       update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0]
114596   end
114597   attribute \src "ls180.v:10175.1-10176.4"
114598   process $proc$ls180.v:10175$2753
114599     sync posedge \sys_clk_1
114600   end
114601   attribute \src "ls180.v:1018.5-1018.38"
114602   process $proc$ls180.v:1018$3157
114603     assign { } { }
114604     assign $1\main_spimaster26_cs_enable[0:0] 1'0
114605     sync always
114606     sync init
114607       update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
114608   end
114609   attribute \src "ls180.v:10183.1-10187.4"
114610   process $proc$ls180.v:10183$2755
114611     assign { } { }
114612     assign { } { }
114613     assign { } { }
114614     assign { } { }
114615     assign $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 5'xxxxx
114616     assign $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 10'xxxxxxxxxx
114617     assign $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 10'0000000000
114618     assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10186$2759_DATA
114619     attribute \src "ls180.v:10184.2-10185.85"
114620     switch \main_sdmem2block_fifo_wrport_we
114621       attribute \src "ls180.v:10184.6-10184.37"
114622       case 1'1
114623         assign $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr
114624         assign $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w
114625         assign $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 10'1111111111
114626       case
114627     end
114628     sync posedge \sys_clk_1
114629       update \memdat_9 $0\memdat_9[9:0]
114630       update $memwr$\storage_7$ls180.v:10185$12_ADDR $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756
114631       update $memwr$\storage_7$ls180.v:10185$12_DATA $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757
114632       update $memwr$\storage_7$ls180.v:10185$12_EN $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758
114633   end
114634   attribute \src "ls180.v:10189.1-10190.4"
114635   process $proc$ls180.v:10189$2760
114636     sync posedge \sys_clk_1
114637   end
114638   attribute \src "ls180.v:1019.11-1019.40"
114639   process $proc$ls180.v:1019$3158
114640     assign { } { }
114641     assign $1\main_spimaster27_count[2:0] 3'000
114642     sync always
114643     sync init
114644       update \main_spimaster27_count $1\main_spimaster27_count[2:0]
114645   end
114646   attribute \src "ls180.v:1020.5-1020.39"
114647   process $proc$ls180.v:1020$3159
114648     assign { } { }
114649     assign $1\main_spimaster28_mosi_latch[0:0] 1'0
114650     sync always
114651     sync init
114652       update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
114653   end
114654   attribute \src "ls180.v:1021.5-1021.39"
114655   process $proc$ls180.v:1021$3160
114656     assign { } { }
114657     assign $1\main_spimaster29_miso_latch[0:0] 1'0
114658     sync always
114659     sync init
114660       update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0]
114661   end
114662   attribute \src "ls180.v:1022.12-1022.48"
114663   process $proc$ls180.v:1022$3161
114664     assign { } { }
114665     assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000
114666     sync always
114667     sync init
114668       update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0]
114669   end
114670   attribute \src "ls180.v:1025.11-1025.44"
114671   process $proc$ls180.v:1025$3162
114672     assign { } { }
114673     assign $1\main_spimaster33_mosi_data[7:0] 8'00000000
114674     sync always
114675     sync init
114676       update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0]
114677   end
114678   attribute \src "ls180.v:1026.11-1026.43"
114679   process $proc$ls180.v:1026$3163
114680     assign { } { }
114681     assign $1\main_spimaster34_mosi_sel[2:0] 3'000
114682     sync always
114683     sync init
114684       update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0]
114685   end
114686   attribute \src "ls180.v:1027.11-1027.44"
114687   process $proc$ls180.v:1027$3164
114688     assign { } { }
114689     assign $1\main_spimaster35_miso_data[7:0] 8'00000000
114690     sync always
114691     sync init
114692       update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0]
114693   end
114694   attribute \src "ls180.v:1030.5-1030.32"
114695   process $proc$ls180.v:1030$3165
114696     assign { } { }
114697     assign $1\main_spisdcard_done0[0:0] 1'0
114698     sync always
114699     sync init
114700       update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0]
114701   end
114702   attribute \src "ls180.v:1031.5-1031.30"
114703   process $proc$ls180.v:1031$3166
114704     assign { } { }
114705     assign $1\main_spisdcard_irq[0:0] 1'0
114706     sync always
114707     sync init
114708       update \main_spisdcard_irq $1\main_spisdcard_irq[0:0]
114709   end
114710   attribute \src "ls180.v:1033.11-1033.37"
114711   process $proc$ls180.v:1033$3167
114712     assign { } { }
114713     assign $1\main_spisdcard_miso[7:0] 8'00000000
114714     sync always
114715     sync init
114716       update \main_spisdcard_miso $1\main_spisdcard_miso[7:0]
114717   end
114718   attribute \src "ls180.v:1037.5-1037.33"
114719   process $proc$ls180.v:1037$3168
114720     assign { } { }
114721     assign $1\main_spisdcard_start1[0:0] 1'0
114722     sync always
114723     sync init
114724       update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0]
114725   end
114726   attribute \src "ls180.v:1039.12-1039.50"
114727   process $proc$ls180.v:1039$3169
114728     assign { } { }
114729     assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000
114730     sync always
114731     sync init
114732       update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0]
114733   end
114734   attribute \src "ls180.v:1040.5-1040.37"
114735   process $proc$ls180.v:1040$3170
114736     assign { } { }
114737     assign $1\main_spisdcard_control_re[0:0] 1'0
114738     sync always
114739     sync init
114740       update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0]
114741   end
114742   attribute \src "ls180.v:1044.11-1044.45"
114743   process $proc$ls180.v:1044$3171
114744     assign { } { }
114745     assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000
114746     sync always
114747     sync init
114748       update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0]
114749   end
114750   attribute \src "ls180.v:1045.5-1045.34"
114751   process $proc$ls180.v:1045$3172
114752     assign { } { }
114753     assign $1\main_spisdcard_mosi_re[0:0] 1'0
114754     sync always
114755     sync init
114756       update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0]
114757   end
114758   attribute \src "ls180.v:1049.5-1049.37"
114759   process $proc$ls180.v:1049$3173
114760     assign { } { }
114761     assign $1\main_spisdcard_cs_storage[0:0] 1'1
114762     sync always
114763     sync init
114764       update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0]
114765   end
114766   attribute \src "ls180.v:1050.5-1050.32"
114767   process $proc$ls180.v:1050$3174
114768     assign { } { }
114769     assign $1\main_spisdcard_cs_re[0:0] 1'0
114770     sync always
114771     sync init
114772       update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0]
114773   end
114774   attribute \src "ls180.v:1051.5-1051.43"
114775   process $proc$ls180.v:1051$3175
114776     assign { } { }
114777     assign $1\main_spisdcard_loopback_storage[0:0] 1'0
114778     sync always
114779     sync init
114780       update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0]
114781   end
114782   attribute \src "ls180.v:1052.5-1052.38"
114783   process $proc$ls180.v:1052$3176
114784     assign { } { }
114785     assign $1\main_spisdcard_loopback_re[0:0] 1'0
114786     sync always
114787     sync init
114788       update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0]
114789   end
114790   attribute \src "ls180.v:1053.5-1053.37"
114791   process $proc$ls180.v:1053$3177
114792     assign { } { }
114793     assign $1\main_spisdcard_clk_enable[0:0] 1'0
114794     sync always
114795     sync init
114796       update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0]
114797   end
114798   attribute \src "ls180.v:1054.5-1054.36"
114799   process $proc$ls180.v:1054$3178
114800     assign { } { }
114801     assign $1\main_spisdcard_cs_enable[0:0] 1'0
114802     sync always
114803     sync init
114804       update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0]
114805   end
114806   attribute \src "ls180.v:1055.11-1055.38"
114807   process $proc$ls180.v:1055$3179
114808     assign { } { }
114809     assign $1\main_spisdcard_count[2:0] 3'000
114810     sync always
114811     sync init
114812       update \main_spisdcard_count $1\main_spisdcard_count[2:0]
114813   end
114814   attribute \src "ls180.v:1056.5-1056.37"
114815   process $proc$ls180.v:1056$3180
114816     assign { } { }
114817     assign $1\main_spisdcard_mosi_latch[0:0] 1'0
114818     sync always
114819     sync init
114820       update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0]
114821   end
114822   attribute \src "ls180.v:1057.5-1057.37"
114823   process $proc$ls180.v:1057$3181
114824     assign { } { }
114825     assign $1\main_spisdcard_miso_latch[0:0] 1'0
114826     sync always
114827     sync init
114828       update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0]
114829   end
114830   attribute \src "ls180.v:1058.12-1058.47"
114831   process $proc$ls180.v:1058$3182
114832     assign { } { }
114833     assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
114834     sync always
114835     sync init
114836       update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0]
114837   end
114838   attribute \src "ls180.v:1061.11-1061.42"
114839   process $proc$ls180.v:1061$3183
114840     assign { } { }
114841     assign $1\main_spisdcard_mosi_data[7:0] 8'00000000
114842     sync always
114843     sync init
114844       update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0]
114845   end
114846   attribute \src "ls180.v:1062.11-1062.41"
114847   process $proc$ls180.v:1062$3184
114848     assign { } { }
114849     assign $1\main_spisdcard_mosi_sel[2:0] 3'000
114850     sync always
114851     sync init
114852       update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0]
114853   end
114854   attribute \src "ls180.v:1063.11-1063.42"
114855   process $proc$ls180.v:1063$3185
114856     assign { } { }
114857     assign $1\main_spisdcard_miso_data[7:0] 8'00000000
114858     sync always
114859     sync init
114860       update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0]
114861   end
114862   attribute \src "ls180.v:1064.12-1064.45"
114863   process $proc$ls180.v:1064$3186
114864     assign { } { }
114865     assign $1\main_spimaster1_storage[15:0] 16'0000000001111101
114866     sync always
114867     sync init
114868       update \main_spimaster1_storage $1\main_spimaster1_storage[15:0]
114869   end
114870   attribute \src "ls180.v:1065.5-1065.30"
114871   process $proc$ls180.v:1065$3187
114872     assign { } { }
114873     assign $1\main_spimaster1_re[0:0] 1'0
114874     sync always
114875     sync init
114876       update \main_spimaster1_re $1\main_spimaster1_re[0:0]
114877   end
114878   attribute \src "ls180.v:1067.12-1067.30"
114879   process $proc$ls180.v:1067$3188
114880     assign { } { }
114881     assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000
114882     sync always
114883     sync init
114884       update \main_dummy $1\main_dummy[35:0]
114885   end
114886   attribute \src "ls180.v:1071.12-1071.37"
114887   process $proc$ls180.v:1071$3189
114888     assign { } { }
114889     assign $1\main_pwm0_counter[31:0] 0
114890     sync always
114891     sync init
114892       update \main_pwm0_counter $1\main_pwm0_counter[31:0]
114893   end
114894   attribute \src "ls180.v:1072.5-1072.36"
114895   process $proc$ls180.v:1072$3190
114896     assign { } { }
114897     assign $1\main_pwm0_enable_storage[0:0] 1'0
114898     sync always
114899     sync init
114900       update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
114901   end
114902   attribute \src "ls180.v:1073.5-1073.31"
114903   process $proc$ls180.v:1073$3191
114904     assign { } { }
114905     assign $1\main_pwm0_enable_re[0:0] 1'0
114906     sync always
114907     sync init
114908       update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
114909   end
114910   attribute \src "ls180.v:1074.12-1074.43"
114911   process $proc$ls180.v:1074$3192
114912     assign { } { }
114913     assign $1\main_pwm0_width_storage[31:0] 0
114914     sync always
114915     sync init
114916       update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
114917   end
114918   attribute \src "ls180.v:1075.5-1075.30"
114919   process $proc$ls180.v:1075$3193
114920     assign { } { }
114921     assign $1\main_pwm0_width_re[0:0] 1'0
114922     sync always
114923     sync init
114924       update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
114925   end
114926   attribute \src "ls180.v:1076.12-1076.44"
114927   process $proc$ls180.v:1076$3194
114928     assign { } { }
114929     assign $1\main_pwm0_period_storage[31:0] 0
114930     sync always
114931     sync init
114932       update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
114933   end
114934   attribute \src "ls180.v:1077.5-1077.31"
114935   process $proc$ls180.v:1077$3195
114936     assign { } { }
114937     assign $1\main_pwm0_period_re[0:0] 1'0
114938     sync always
114939     sync init
114940       update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
114941   end
114942   attribute \src "ls180.v:1081.12-1081.37"
114943   process $proc$ls180.v:1081$3196
114944     assign { } { }
114945     assign $1\main_pwm1_counter[31:0] 0
114946     sync always
114947     sync init
114948       update \main_pwm1_counter $1\main_pwm1_counter[31:0]
114949   end
114950   attribute \src "ls180.v:1082.5-1082.36"
114951   process $proc$ls180.v:1082$3197
114952     assign { } { }
114953     assign $1\main_pwm1_enable_storage[0:0] 1'0
114954     sync always
114955     sync init
114956       update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0]
114957   end
114958   attribute \src "ls180.v:1083.5-1083.31"
114959   process $proc$ls180.v:1083$3198
114960     assign { } { }
114961     assign $1\main_pwm1_enable_re[0:0] 1'0
114962     sync always
114963     sync init
114964       update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0]
114965   end
114966   attribute \src "ls180.v:1084.12-1084.43"
114967   process $proc$ls180.v:1084$3199
114968     assign { } { }
114969     assign $1\main_pwm1_width_storage[31:0] 0
114970     sync always
114971     sync init
114972       update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0]
114973   end
114974   attribute \src "ls180.v:1085.5-1085.30"
114975   process $proc$ls180.v:1085$3200
114976     assign { } { }
114977     assign $1\main_pwm1_width_re[0:0] 1'0
114978     sync always
114979     sync init
114980       update \main_pwm1_width_re $1\main_pwm1_width_re[0:0]
114981   end
114982   attribute \src "ls180.v:1086.12-1086.44"
114983   process $proc$ls180.v:1086$3201
114984     assign { } { }
114985     assign $1\main_pwm1_period_storage[31:0] 0
114986     sync always
114987     sync init
114988       update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0]
114989   end
114990   attribute \src "ls180.v:1087.5-1087.31"
114991   process $proc$ls180.v:1087$3202
114992     assign { } { }
114993     assign $1\main_pwm1_period_re[0:0] 1'0
114994     sync always
114995     sync init
114996       update \main_pwm1_period_re $1\main_pwm1_period_re[0:0]
114997   end
114998   attribute \src "ls180.v:1091.11-1091.34"
114999   process $proc$ls180.v:1091$3203
115000     assign { } { }
115001     assign $1\main_i2c_storage[2:0] 3'000
115002     sync always
115003     sync init
115004       update \main_i2c_storage $1\main_i2c_storage[2:0]
115005   end
115006   attribute \src "ls180.v:1092.5-1092.23"
115007   process $proc$ls180.v:1092$3204
115008     assign { } { }
115009     assign $1\main_i2c_re[0:0] 1'0
115010     sync always
115011     sync init
115012       update \main_i2c_re $1\main_i2c_re[0:0]
115013   end
115014   attribute \src "ls180.v:1098.11-1098.46"
115015   process $proc$ls180.v:1098$3205
115016     assign { } { }
115017     assign $1\main_sdphy_clocker_storage[8:0] 9'100000000
115018     sync always
115019     sync init
115020       update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0]
115021   end
115022   attribute \src "ls180.v:1099.5-1099.33"
115023   process $proc$ls180.v:1099$3206
115024     assign { } { }
115025     assign $1\main_sdphy_clocker_re[0:0] 1'0
115026     sync always
115027     sync init
115028       update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0]
115029   end
115030   attribute \src "ls180.v:1101.5-1101.35"
115031   process $proc$ls180.v:1101$3207
115032     assign { } { }
115033     assign $1\main_sdphy_clocker_clk0[0:0] 1'0
115034     sync always
115035     sync init
115036       update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0]
115037   end
115038   attribute \src "ls180.v:1103.11-1103.41"
115039   process $proc$ls180.v:1103$3208
115040     assign { } { }
115041     assign $1\main_sdphy_clocker_clks[8:0] 9'000000000
115042     sync always
115043     sync init
115044       update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0]
115045   end
115046   attribute \src "ls180.v:1104.5-1104.35"
115047   process $proc$ls180.v:1104$3209
115048     assign { } { }
115049     assign $1\main_sdphy_clocker_clk1[0:0] 1'0
115050     sync always
115051     sync init
115052       update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0]
115053   end
115054   attribute \src "ls180.v:1105.5-1105.36"
115055   process $proc$ls180.v:1105$3210
115056     assign { } { }
115057     assign $1\main_sdphy_clocker_clk_d[0:0] 1'0
115058     sync always
115059     sync init
115060       update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0]
115061   end
115062   attribute \src "ls180.v:1109.5-1109.40"
115063   process $proc$ls180.v:1109$3211
115064     assign { } { }
115065     assign $0\main_sdphy_init_initialize_w[0:0] 1'0
115066     sync always
115067       update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0]
115068     sync init
115069   end
115070   attribute \src "ls180.v:1114.5-1114.48"
115071   process $proc$ls180.v:1114$3212
115072     assign { } { }
115073     assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
115074     sync always
115075     sync init
115076       update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0]
115077   end
115078   attribute \src "ls180.v:1115.5-1115.50"
115079   process $proc$ls180.v:1115$3213
115080     assign { } { }
115081     assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
115082     sync always
115083     sync init
115084       update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
115085   end
115086   attribute \src "ls180.v:1116.5-1116.51"
115087   process $proc$ls180.v:1116$3214
115088     assign { } { }
115089     assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
115090     sync always
115091     sync init
115092       update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
115093   end
115094   attribute \src "ls180.v:1117.11-1117.57"
115095   process $proc$ls180.v:1117$3215
115096     assign { } { }
115097     assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
115098     sync always
115099     sync init
115100       update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0]
115101   end
115102   attribute \src "ls180.v:1118.5-1118.52"
115103   process $proc$ls180.v:1118$3216
115104     assign { } { }
115105     assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
115106     sync always
115107     sync init
115108       update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
115109   end
115110   attribute \src "ls180.v:1119.11-1119.39"
115111   process $proc$ls180.v:1119$3217
115112     assign { } { }
115113     assign $1\main_sdphy_init_count[7:0] 8'00000000
115114     sync always
115115     sync init
115116       update \main_sdphy_init_count $1\main_sdphy_init_count[7:0]
115117   end
115118   attribute \src "ls180.v:1124.5-1124.48"
115119   process $proc$ls180.v:1124$3218
115120     assign { } { }
115121     assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
115122     sync always
115123     sync init
115124       update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
115125   end
115126   attribute \src "ls180.v:1125.5-1125.50"
115127   process $proc$ls180.v:1125$3219
115128     assign { } { }
115129     assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
115130     sync always
115131     sync init
115132       update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
115133   end
115134   attribute \src "ls180.v:1126.5-1126.51"
115135   process $proc$ls180.v:1126$3220
115136     assign { } { }
115137     assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
115138     sync always
115139     sync init
115140       update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
115141   end
115142   attribute \src "ls180.v:1127.11-1127.57"
115143   process $proc$ls180.v:1127$3221
115144     assign { } { }
115145     assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000
115146     sync always
115147       update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0]
115148     sync init
115149   end
115150   attribute \src "ls180.v:1128.5-1128.52"
115151   process $proc$ls180.v:1128$3222
115152     assign { } { }
115153     assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0
115154     sync always
115155       update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0]
115156     sync init
115157   end
115158   attribute \src "ls180.v:1129.5-1129.38"
115159   process $proc$ls180.v:1129$3223
115160     assign { } { }
115161     assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0
115162     sync always
115163     sync init
115164       update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0]
115165   end
115166   attribute \src "ls180.v:1130.5-1130.38"
115167   process $proc$ls180.v:1130$3224
115168     assign { } { }
115169     assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0
115170     sync always
115171     sync init
115172       update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0]
115173   end
115174   attribute \src "ls180.v:1131.5-1131.37"
115175   process $proc$ls180.v:1131$3225
115176     assign { } { }
115177     assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0
115178     sync always
115179     sync init
115180       update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0]
115181   end
115182   attribute \src "ls180.v:1132.11-1132.51"
115183   process $proc$ls180.v:1132$3226
115184     assign { } { }
115185     assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
115186     sync always
115187     sync init
115188       update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0]
115189   end
115190   attribute \src "ls180.v:1133.5-1133.32"
115191   process $proc$ls180.v:1133$3227
115192     assign { } { }
115193     assign $1\main_sdphy_cmdw_done[0:0] 1'0
115194     sync always
115195     sync init
115196       update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0]
115197   end
115198   attribute \src "ls180.v:1134.11-1134.39"
115199   process $proc$ls180.v:1134$3228
115200     assign { } { }
115201     assign $1\main_sdphy_cmdw_count[7:0] 8'00000000
115202     sync always
115203     sync init
115204       update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0]
115205   end
115206   attribute \src "ls180.v:1137.5-1137.49"
115207   process $proc$ls180.v:1137$3229
115208     assign { } { }
115209     assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0
115210     sync always
115211       update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0]
115212     sync init
115213   end
115214   attribute \src "ls180.v:1138.5-1138.48"
115215   process $proc$ls180.v:1138$3230
115216     assign { } { }
115217     assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0
115218     sync always
115219       update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0]
115220     sync init
115221   end
115222   attribute \src "ls180.v:1139.5-1139.55"
115223   process $proc$ls180.v:1139$3231
115224     assign { } { }
115225     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0
115226     sync always
115227       update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0]
115228     sync init
115229   end
115230   attribute \src "ls180.v:1141.5-1141.57"
115231   process $proc$ls180.v:1141$3232
115232     assign { } { }
115233     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0
115234     sync always
115235       update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0]
115236     sync init
115237   end
115238   attribute \src "ls180.v:1142.5-1142.58"
115239   process $proc$ls180.v:1142$3233
115240     assign { } { }
115241     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
115242     sync always
115243       update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0]
115244     sync init
115245   end
115246   attribute \src "ls180.v:1144.11-1144.64"
115247   process $proc$ls180.v:1144$3234
115248     assign { } { }
115249     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000
115250     sync always
115251       update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0]
115252     sync init
115253   end
115254   attribute \src "ls180.v:1145.5-1145.59"
115255   process $proc$ls180.v:1145$3235
115256     assign { } { }
115257     assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0
115258     sync always
115259       update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0]
115260     sync init
115261   end
115262   attribute \src "ls180.v:1147.5-1147.48"
115263   process $proc$ls180.v:1147$3236
115264     assign { } { }
115265     assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
115266     sync always
115267     sync init
115268       update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
115269   end
115270   attribute \src "ls180.v:1148.5-1148.50"
115271   process $proc$ls180.v:1148$3237
115272     assign { } { }
115273     assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
115274     sync always
115275     sync init
115276       update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
115277   end
115278   attribute \src "ls180.v:1149.5-1149.51"
115279   process $proc$ls180.v:1149$3238
115280     assign { } { }
115281     assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
115282     sync always
115283     sync init
115284       update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
115285   end
115286   attribute \src "ls180.v:1150.11-1150.57"
115287   process $proc$ls180.v:1150$3239
115288     assign { } { }
115289     assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000
115290     sync always
115291       update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0]
115292     sync init
115293   end
115294   attribute \src "ls180.v:1151.5-1151.52"
115295   process $proc$ls180.v:1151$3240
115296     assign { } { }
115297     assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0
115298     sync always
115299       update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0]
115300     sync init
115301   end
115302   attribute \src "ls180.v:1152.5-1152.38"
115303   process $proc$ls180.v:1152$3241
115304     assign { } { }
115305     assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0
115306     sync always
115307     sync init
115308       update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0]
115309   end
115310   attribute \src "ls180.v:1153.5-1153.38"
115311   process $proc$ls180.v:1153$3242
115312     assign { } { }
115313     assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0
115314     sync always
115315     sync init
115316       update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0]
115317   end
115318   attribute \src "ls180.v:1154.5-1154.37"
115319   process $proc$ls180.v:1154$3243
115320     assign { } { }
115321     assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0
115322     sync always
115323     sync init
115324       update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0]
115325   end
115326   attribute \src "ls180.v:1155.11-1155.53"
115327   process $proc$ls180.v:1155$3244
115328     assign { } { }
115329     assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
115330     sync always
115331     sync init
115332       update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0]
115333   end
115334   attribute \src "ls180.v:1156.5-1156.40"
115335   process $proc$ls180.v:1156$3245
115336     assign { } { }
115337     assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0
115338     sync always
115339     sync init
115340       update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0]
115341   end
115342   attribute \src "ls180.v:1157.5-1157.40"
115343   process $proc$ls180.v:1157$3246
115344     assign { } { }
115345     assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0
115346     sync always
115347     sync init
115348       update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0]
115349   end
115350   attribute \src "ls180.v:1158.5-1158.39"
115351   process $proc$ls180.v:1158$3247
115352     assign { } { }
115353     assign $1\main_sdphy_cmdr_source_last[0:0] 1'0
115354     sync always
115355     sync init
115356       update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0]
115357   end
115358   attribute \src "ls180.v:1159.11-1159.53"
115359   process $proc$ls180.v:1159$3248
115360     assign { } { }
115361     assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
115362     sync always
115363     sync init
115364       update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0]
115365   end
115366   attribute \src "ls180.v:116.5-116.49"
115367   process $proc$ls180.v:116$2785
115368     assign { } { }
115369     assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
115370     sync always
115371     sync init
115372       update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
115373   end
115374   attribute \src "ls180.v:1160.11-1160.55"
115375   process $proc$ls180.v:1160$3249
115376     assign { } { }
115377     assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000
115378     sync always
115379     sync init
115380       update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0]
115381   end
115382   attribute \src "ls180.v:1161.12-1161.48"
115383   process $proc$ls180.v:1161$3250
115384     assign { } { }
115385     assign $1\main_sdphy_cmdr_timeout[31:0] 500000
115386     sync always
115387     sync init
115388       update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0]
115389   end
115390   attribute \src "ls180.v:1162.11-1162.39"
115391   process $proc$ls180.v:1162$3251
115392     assign { } { }
115393     assign $1\main_sdphy_cmdr_count[7:0] 8'00000000
115394     sync always
115395     sync init
115396       update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0]
115397   end
115398   attribute \src "ls180.v:1164.5-1164.46"
115399   process $proc$ls180.v:1164$3252
115400     assign { } { }
115401     assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0
115402     sync always
115403       update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0]
115404     sync init
115405   end
115406   attribute \src "ls180.v:1175.5-1175.53"
115407   process $proc$ls180.v:1175$3253
115408     assign { } { }
115409     assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
115410     sync always
115411     sync init
115412       update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
115413   end
115414   attribute \src "ls180.v:118.5-118.49"
115415   process $proc$ls180.v:118$2786
115416     assign { } { }
115417     assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0
115418     sync always
115419       update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0]
115420     sync init
115421   end
115422   attribute \src "ls180.v:1180.5-1180.36"
115423   process $proc$ls180.v:1180$3254
115424     assign { } { }
115425     assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0
115426     sync always
115427     sync init
115428       update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0]
115429   end
115430   attribute \src "ls180.v:1183.5-1183.53"
115431   process $proc$ls180.v:1183$3255
115432     assign { } { }
115433     assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0
115434     sync always
115435       update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0]
115436     sync init
115437   end
115438   attribute \src "ls180.v:1184.5-1184.52"
115439   process $proc$ls180.v:1184$3256
115440     assign { } { }
115441     assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0
115442     sync always
115443       update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0]
115444     sync init
115445   end
115446   attribute \src "ls180.v:1188.5-1188.55"
115447   process $proc$ls180.v:1188$3257
115448     assign { } { }
115449     assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
115450     sync always
115451     sync init
115452       update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
115453   end
115454   attribute \src "ls180.v:1189.5-1189.54"
115455   process $proc$ls180.v:1189$3258
115456     assign { } { }
115457     assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
115458     sync always
115459     sync init
115460       update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
115461   end
115462   attribute \src "ls180.v:1190.11-1190.68"
115463   process $proc$ls180.v:1190$3259
115464     assign { } { }
115465     assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000
115466     sync always
115467     sync init
115468       update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
115469   end
115470   attribute \src "ls180.v:1191.11-1191.81"
115471   process $proc$ls180.v:1191$3260
115472     assign { } { }
115473     assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000
115474     sync always
115475     sync init
115476       update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
115477   end
115478   attribute \src "ls180.v:1192.11-1192.54"
115479   process $proc$ls180.v:1192$3261
115480     assign { } { }
115481     assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
115482     sync always
115483     sync init
115484       update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
115485   end
115486   attribute \src "ls180.v:1194.5-1194.53"
115487   process $proc$ls180.v:1194$3262
115488     assign { } { }
115489     assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
115490     sync always
115491     sync init
115492       update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
115493   end
115494   attribute \src "ls180.v:1205.5-1205.49"
115495   process $proc$ls180.v:1205$3263
115496     assign { } { }
115497     assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
115498     sync always
115499     sync init
115500       update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
115501   end
115502   attribute \src "ls180.v:1207.5-1207.49"
115503   process $proc$ls180.v:1207$3264
115504     assign { } { }
115505     assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0
115506     sync always
115507     sync init
115508       update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
115509   end
115510   attribute \src "ls180.v:1208.5-1208.48"
115511   process $proc$ls180.v:1208$3265
115512     assign { } { }
115513     assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0
115514     sync always
115515     sync init
115516       update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
115517   end
115518   attribute \src "ls180.v:1209.11-1209.62"
115519   process $proc$ls180.v:1209$3266
115520     assign { } { }
115521     assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000
115522     sync always
115523     sync init
115524       update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
115525   end
115526   attribute \src "ls180.v:1210.5-1210.38"
115527   process $proc$ls180.v:1210$3267
115528     assign { } { }
115529     assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
115530     sync always
115531     sync init
115532       update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0]
115533   end
115534   attribute \src "ls180.v:1215.5-1215.49"
115535   process $proc$ls180.v:1215$3268
115536     assign { } { }
115537     assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
115538     sync always
115539     sync init
115540       update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
115541   end
115542   attribute \src "ls180.v:1216.5-1216.51"
115543   process $proc$ls180.v:1216$3269
115544     assign { } { }
115545     assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0
115546     sync always
115547       update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0]
115548     sync init
115549   end
115550   attribute \src "ls180.v:1217.5-1217.52"
115551   process $proc$ls180.v:1217$3270
115552     assign { } { }
115553     assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0
115554     sync always
115555       update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0]
115556     sync init
115557   end
115558   attribute \src "ls180.v:1218.11-1218.58"
115559   process $proc$ls180.v:1218$3271
115560     assign { } { }
115561     assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
115562     sync always
115563     sync init
115564       update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
115565   end
115566   attribute \src "ls180.v:1219.5-1219.53"
115567   process $proc$ls180.v:1219$3272
115568     assign { } { }
115569     assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
115570     sync always
115571     sync init
115572       update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
115573   end
115574   attribute \src "ls180.v:1220.5-1220.39"
115575   process $proc$ls180.v:1220$3273
115576     assign { } { }
115577     assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0
115578     sync always
115579     sync init
115580       update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0]
115581   end
115582   attribute \src "ls180.v:1221.5-1221.39"
115583   process $proc$ls180.v:1221$3274
115584     assign { } { }
115585     assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0
115586     sync always
115587     sync init
115588       update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0]
115589   end
115590   attribute \src "ls180.v:1222.5-1222.39"
115591   process $proc$ls180.v:1222$3275
115592     assign { } { }
115593     assign $1\main_sdphy_dataw_sink_first[0:0] 1'0
115594     sync always
115595     sync init
115596       update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0]
115597   end
115598   attribute \src "ls180.v:1223.5-1223.38"
115599   process $proc$ls180.v:1223$3276
115600     assign { } { }
115601     assign $1\main_sdphy_dataw_sink_last[0:0] 1'0
115602     sync always
115603     sync init
115604       update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0]
115605   end
115606   attribute \src "ls180.v:1224.11-1224.52"
115607   process $proc$ls180.v:1224$3277
115608     assign { } { }
115609     assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
115610     sync always
115611     sync init
115612       update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0]
115613   end
115614   attribute \src "ls180.v:1225.5-1225.33"
115615   process $proc$ls180.v:1225$3278
115616     assign { } { }
115617     assign $1\main_sdphy_dataw_stop[0:0] 1'0
115618     sync always
115619     sync init
115620       update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0]
115621   end
115622   attribute \src "ls180.v:1226.11-1226.40"
115623   process $proc$ls180.v:1226$3279
115624     assign { } { }
115625     assign $1\main_sdphy_dataw_count[7:0] 8'00000000
115626     sync always
115627     sync init
115628       update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0]
115629   end
115630   attribute \src "ls180.v:1227.5-1227.50"
115631   process $proc$ls180.v:1227$3280
115632     assign { } { }
115633     assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0
115634     sync always
115635       update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0]
115636     sync init
115637   end
115638   attribute \src "ls180.v:1229.5-1229.50"
115639   process $proc$ls180.v:1229$3281
115640     assign { } { }
115641     assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0
115642     sync always
115643       update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0]
115644     sync init
115645   end
115646   attribute \src "ls180.v:1230.5-1230.49"
115647   process $proc$ls180.v:1230$3282
115648     assign { } { }
115649     assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0
115650     sync always
115651       update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0]
115652     sync init
115653   end
115654   attribute \src "ls180.v:1231.5-1231.56"
115655   process $proc$ls180.v:1231$3283
115656     assign { } { }
115657     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0
115658     sync always
115659       update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0]
115660     sync init
115661   end
115662   attribute \src "ls180.v:1232.5-1232.58"
115663   process $proc$ls180.v:1232$3284
115664     assign { } { }
115665     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0
115666     sync always
115667       update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0]
115668     sync init
115669   end
115670   attribute \src "ls180.v:1233.5-1233.58"
115671   process $proc$ls180.v:1233$3285
115672     assign { } { }
115673     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0
115674     sync always
115675       update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0]
115676     sync init
115677   end
115678   attribute \src "ls180.v:1234.5-1234.59"
115679   process $proc$ls180.v:1234$3286
115680     assign { } { }
115681     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
115682     sync always
115683       update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0]
115684     sync init
115685   end
115686   attribute \src "ls180.v:1235.11-1235.65"
115687   process $proc$ls180.v:1235$3287
115688     assign { } { }
115689     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000
115690     sync always
115691       update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0]
115692     sync init
115693   end
115694   attribute \src "ls180.v:1236.11-1236.65"
115695   process $proc$ls180.v:1236$3288
115696     assign { } { }
115697     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000
115698     sync always
115699       update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0]
115700     sync init
115701   end
115702   attribute \src "ls180.v:1237.5-1237.60"
115703   process $proc$ls180.v:1237$3289
115704     assign { } { }
115705     assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0
115706     sync always
115707       update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0]
115708     sync init
115709   end
115710   attribute \src "ls180.v:1238.5-1238.34"
115711   process $proc$ls180.v:1238$3290
115712     assign { } { }
115713     assign $1\main_sdphy_dataw_start[0:0] 1'0
115714     sync always
115715     sync init
115716       update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0]
115717   end
115718   attribute \src "ls180.v:1239.5-1239.34"
115719   process $proc$ls180.v:1239$3291
115720     assign { } { }
115721     assign $1\main_sdphy_dataw_valid[0:0] 1'0
115722     sync always
115723     sync init
115724       update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0]
115725   end
115726   attribute \src "ls180.v:1240.5-1240.34"
115727   process $proc$ls180.v:1240$3292
115728     assign { } { }
115729     assign $1\main_sdphy_dataw_error[0:0] 1'0
115730     sync always
115731     sync init
115732       update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0]
115733   end
115734   attribute \src "ls180.v:1242.5-1242.47"
115735   process $proc$ls180.v:1242$3293
115736     assign { } { }
115737     assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0
115738     sync always
115739       update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0]
115740     sync init
115741   end
115742   attribute \src "ls180.v:1253.5-1253.54"
115743   process $proc$ls180.v:1253$3294
115744     assign { } { }
115745     assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
115746     sync always
115747     sync init
115748       update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
115749   end
115750   attribute \src "ls180.v:1258.5-1258.37"
115751   process $proc$ls180.v:1258$3295
115752     assign { } { }
115753     assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0
115754     sync always
115755     sync init
115756       update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0]
115757   end
115758   attribute \src "ls180.v:1261.5-1261.54"
115759   process $proc$ls180.v:1261$3296
115760     assign { } { }
115761     assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0
115762     sync always
115763       update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0]
115764     sync init
115765   end
115766   attribute \src "ls180.v:1262.5-1262.53"
115767   process $proc$ls180.v:1262$3297
115768     assign { } { }
115769     assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0
115770     sync always
115771       update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0]
115772     sync init
115773   end
115774   attribute \src "ls180.v:1266.5-1266.56"
115775   process $proc$ls180.v:1266$3298
115776     assign { } { }
115777     assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
115778     sync always
115779     sync init
115780       update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
115781   end
115782   attribute \src "ls180.v:1267.5-1267.55"
115783   process $proc$ls180.v:1267$3299
115784     assign { } { }
115785     assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
115786     sync always
115787     sync init
115788       update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
115789   end
115790   attribute \src "ls180.v:1268.11-1268.69"
115791   process $proc$ls180.v:1268$3300
115792     assign { } { }
115793     assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000
115794     sync always
115795     sync init
115796       update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
115797   end
115798   attribute \src "ls180.v:1269.11-1269.82"
115799   process $proc$ls180.v:1269$3301
115800     assign { } { }
115801     assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000
115802     sync always
115803     sync init
115804       update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
115805   end
115806   attribute \src "ls180.v:1270.11-1270.55"
115807   process $proc$ls180.v:1270$3302
115808     assign { } { }
115809     assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
115810     sync always
115811     sync init
115812       update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0]
115813   end
115814   attribute \src "ls180.v:1272.5-1272.54"
115815   process $proc$ls180.v:1272$3303
115816     assign { } { }
115817     assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
115818     sync always
115819     sync init
115820       update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
115821   end
115822   attribute \src "ls180.v:1283.5-1283.50"
115823   process $proc$ls180.v:1283$3304
115824     assign { } { }
115825     assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
115826     sync always
115827     sync init
115828       update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
115829   end
115830   attribute \src "ls180.v:1285.5-1285.50"
115831   process $proc$ls180.v:1285$3305
115832     assign { } { }
115833     assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0
115834     sync always
115835     sync init
115836       update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
115837   end
115838   attribute \src "ls180.v:1286.5-1286.49"
115839   process $proc$ls180.v:1286$3306
115840     assign { } { }
115841     assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0
115842     sync always
115843     sync init
115844       update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
115845   end
115846   attribute \src "ls180.v:1287.11-1287.63"
115847   process $proc$ls180.v:1287$3307
115848     assign { } { }
115849     assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000
115850     sync always
115851     sync init
115852       update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
115853   end
115854   attribute \src "ls180.v:1288.5-1288.39"
115855   process $proc$ls180.v:1288$3308
115856     assign { } { }
115857     assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0
115858     sync always
115859     sync init
115860       update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0]
115861   end
115862   attribute \src "ls180.v:129.12-129.74"
115863   process $proc$ls180.v:129$2787
115864     assign { } { }
115865     assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
115866     sync always
115867       update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
115868     sync init
115869   end
115870   attribute \src "ls180.v:1291.5-1291.50"
115871   process $proc$ls180.v:1291$3309
115872     assign { } { }
115873     assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0
115874     sync always
115875       update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0]
115876     sync init
115877   end
115878   attribute \src "ls180.v:1292.5-1292.49"
115879   process $proc$ls180.v:1292$3310
115880     assign { } { }
115881     assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0
115882     sync always
115883       update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0]
115884     sync init
115885   end
115886   attribute \src "ls180.v:1293.5-1293.56"
115887   process $proc$ls180.v:1293$3311
115888     assign { } { }
115889     assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0
115890     sync always
115891       update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0]
115892     sync init
115893   end
115894   attribute \src "ls180.v:1295.5-1295.58"
115895   process $proc$ls180.v:1295$3312
115896     assign { } { }
115897     assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0
115898     sync always
115899       update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0]
115900     sync init
115901   end
115902   attribute \src "ls180.v:1296.5-1296.59"
115903   process $proc$ls180.v:1296$3313
115904     assign { } { }
115905     assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
115906     sync always
115907       update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0]
115908     sync init
115909   end
115910   attribute \src "ls180.v:1298.11-1298.65"
115911   process $proc$ls180.v:1298$3314
115912     assign { } { }
115913     assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000
115914     sync always
115915       update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0]
115916     sync init
115917   end
115918   attribute \src "ls180.v:1299.5-1299.60"
115919   process $proc$ls180.v:1299$3315
115920     assign { } { }
115921     assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0
115922     sync always
115923       update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
115924     sync init
115925   end
115926   attribute \src "ls180.v:1301.5-1301.49"
115927   process $proc$ls180.v:1301$3316
115928     assign { } { }
115929     assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
115930     sync always
115931     sync init
115932       update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0]
115933   end
115934   attribute \src "ls180.v:1302.5-1302.51"
115935   process $proc$ls180.v:1302$3317
115936     assign { } { }
115937     assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0
115938     sync always
115939       update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0]
115940     sync init
115941   end
115942   attribute \src "ls180.v:1303.5-1303.52"
115943   process $proc$ls180.v:1303$3318
115944     assign { } { }
115945     assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0
115946     sync always
115947       update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0]
115948     sync init
115949   end
115950   attribute \src "ls180.v:1304.11-1304.58"
115951   process $proc$ls180.v:1304$3319
115952     assign { } { }
115953     assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000
115954     sync always
115955       update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0]
115956     sync init
115957   end
115958   attribute \src "ls180.v:1305.5-1305.53"
115959   process $proc$ls180.v:1305$3320
115960     assign { } { }
115961     assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0
115962     sync always
115963       update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0]
115964     sync init
115965   end
115966   attribute \src "ls180.v:1306.5-1306.39"
115967   process $proc$ls180.v:1306$3321
115968     assign { } { }
115969     assign $1\main_sdphy_datar_sink_valid[0:0] 1'0
115970     sync always
115971     sync init
115972       update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0]
115973   end
115974   attribute \src "ls180.v:1307.5-1307.39"
115975   process $proc$ls180.v:1307$3322
115976     assign { } { }
115977     assign $1\main_sdphy_datar_sink_ready[0:0] 1'0
115978     sync always
115979     sync init
115980       update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0]
115981   end
115982   attribute \src "ls180.v:1308.5-1308.38"
115983   process $proc$ls180.v:1308$3323
115984     assign { } { }
115985     assign $1\main_sdphy_datar_sink_last[0:0] 1'0
115986     sync always
115987     sync init
115988       update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0]
115989   end
115990   attribute \src "ls180.v:1309.11-1309.61"
115991   process $proc$ls180.v:1309$3324
115992     assign { } { }
115993     assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
115994     sync always
115995     sync init
115996       update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0]
115997   end
115998   attribute \src "ls180.v:1310.5-1310.41"
115999   process $proc$ls180.v:1310$3325
116000     assign { } { }
116001     assign $1\main_sdphy_datar_source_valid[0:0] 1'0
116002     sync always
116003     sync init
116004       update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0]
116005   end
116006   attribute \src "ls180.v:1311.5-1311.41"
116007   process $proc$ls180.v:1311$3326
116008     assign { } { }
116009     assign $1\main_sdphy_datar_source_ready[0:0] 1'0
116010     sync always
116011     sync init
116012       update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0]
116013   end
116014   attribute \src "ls180.v:1312.5-1312.41"
116015   process $proc$ls180.v:1312$3327
116016     assign { } { }
116017     assign $0\main_sdphy_datar_source_first[0:0] 1'0
116018     sync always
116019       update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0]
116020     sync init
116021   end
116022   attribute \src "ls180.v:1313.5-1313.40"
116023   process $proc$ls180.v:1313$3328
116024     assign { } { }
116025     assign $1\main_sdphy_datar_source_last[0:0] 1'0
116026     sync always
116027     sync init
116028       update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0]
116029   end
116030   attribute \src "ls180.v:1314.11-1314.54"
116031   process $proc$ls180.v:1314$3329
116032     assign { } { }
116033     assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000
116034     sync always
116035     sync init
116036       update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0]
116037   end
116038   attribute \src "ls180.v:1315.11-1315.56"
116039   process $proc$ls180.v:1315$3330
116040     assign { } { }
116041     assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000
116042     sync always
116043     sync init
116044       update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0]
116045   end
116046   attribute \src "ls180.v:1316.5-1316.33"
116047   process $proc$ls180.v:1316$3331
116048     assign { } { }
116049     assign $1\main_sdphy_datar_stop[0:0] 1'0
116050     sync always
116051     sync init
116052       update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0]
116053   end
116054   attribute \src "ls180.v:1317.12-1317.49"
116055   process $proc$ls180.v:1317$3332
116056     assign { } { }
116057     assign $1\main_sdphy_datar_timeout[31:0] 500000
116058     sync always
116059     sync init
116060       update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0]
116061   end
116062   attribute \src "ls180.v:1318.11-1318.41"
116063   process $proc$ls180.v:1318$3333
116064     assign { } { }
116065     assign $1\main_sdphy_datar_count[9:0] 10'0000000000
116066     sync always
116067     sync init
116068       update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
116069   end
116070   attribute \src "ls180.v:1320.5-1320.48"
116071   process $proc$ls180.v:1320$3334
116072     assign { } { }
116073     assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0
116074     sync always
116075       update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
116076     sync init
116077   end
116078   attribute \src "ls180.v:1331.5-1331.55"
116079   process $proc$ls180.v:1331$3335
116080     assign { } { }
116081     assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
116082     sync always
116083     sync init
116084       update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0]
116085   end
116086   attribute \src "ls180.v:1336.5-1336.38"
116087   process $proc$ls180.v:1336$3336
116088     assign { } { }
116089     assign $1\main_sdphy_datar_datar_run[0:0] 1'0
116090     sync always
116091     sync init
116092       update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0]
116093   end
116094   attribute \src "ls180.v:1339.5-1339.55"
116095   process $proc$ls180.v:1339$3337
116096     assign { } { }
116097     assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0
116098     sync always
116099       update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0]
116100     sync init
116101   end
116102   attribute \src "ls180.v:1340.5-1340.54"
116103   process $proc$ls180.v:1340$3338
116104     assign { } { }
116105     assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0
116106     sync always
116107       update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0]
116108     sync init
116109   end
116110   attribute \src "ls180.v:1344.5-1344.57"
116111   process $proc$ls180.v:1344$3339
116112     assign { } { }
116113     assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
116114     sync always
116115     sync init
116116       update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0]
116117   end
116118   attribute \src "ls180.v:1345.5-1345.56"
116119   process $proc$ls180.v:1345$3340
116120     assign { } { }
116121     assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
116122     sync always
116123     sync init
116124       update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0]
116125   end
116126   attribute \src "ls180.v:1346.11-1346.70"
116127   process $proc$ls180.v:1346$3341
116128     assign { } { }
116129     assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000
116130     sync always
116131     sync init
116132       update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
116133   end
116134   attribute \src "ls180.v:1347.11-1347.83"
116135   process $proc$ls180.v:1347$3342
116136     assign { } { }
116137     assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00
116138     sync always
116139     sync init
116140       update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
116141   end
116142   attribute \src "ls180.v:1348.5-1348.50"
116143   process $proc$ls180.v:1348$3343
116144     assign { } { }
116145     assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0
116146     sync always
116147     sync init
116148       update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0]
116149   end
116150   attribute \src "ls180.v:135.5-135.74"
116151   process $proc$ls180.v:135$2788
116152     assign { } { }
116153     assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
116154     sync always
116155       update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
116156     sync init
116157   end
116158   attribute \src "ls180.v:1350.5-1350.55"
116159   process $proc$ls180.v:1350$3344
116160     assign { } { }
116161     assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
116162     sync always
116163     sync init
116164       update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
116165   end
116166   attribute \src "ls180.v:1361.5-1361.51"
116167   process $proc$ls180.v:1361$3345
116168     assign { } { }
116169     assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
116170     sync always
116171     sync init
116172       update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0]
116173   end
116174   attribute \src "ls180.v:1363.5-1363.51"
116175   process $proc$ls180.v:1363$3346
116176     assign { } { }
116177     assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0
116178     sync always
116179     sync init
116180       update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0]
116181   end
116182   attribute \src "ls180.v:1364.5-1364.50"
116183   process $proc$ls180.v:1364$3347
116184     assign { } { }
116185     assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0
116186     sync always
116187     sync init
116188       update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0]
116189   end
116190   attribute \src "ls180.v:1365.11-1365.64"
116191   process $proc$ls180.v:1365$3348
116192     assign { } { }
116193     assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000
116194     sync always
116195     sync init
116196       update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
116197   end
116198   attribute \src "ls180.v:1366.5-1366.40"
116199   process $proc$ls180.v:1366$3349
116200     assign { } { }
116201     assign $1\main_sdphy_datar_datar_reset[0:0] 1'0
116202     sync always
116203     sync init
116204       update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0]
116205   end
116206   attribute \src "ls180.v:1368.5-1368.35"
116207   process $proc$ls180.v:1368$3350
116208     assign { } { }
116209     assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0
116210     sync always
116211     sync init
116212       update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
116213   end
116214   attribute \src "ls180.v:137.5-137.72"
116215   process $proc$ls180.v:137$2789
116216     assign { } { }
116217     assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
116218     sync always
116219       update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
116220     sync init
116221   end
116222   attribute \src "ls180.v:1371.11-1371.42"
116223   process $proc$ls180.v:1371$3351
116224     assign { } { }
116225     assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
116226     sync always
116227     sync init
116228       update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
116229   end
116230   attribute \src "ls180.v:1384.12-1384.52"
116231   process $proc$ls180.v:1384$3352
116232     assign { } { }
116233     assign $1\main_sdcore_cmd_argument_storage[31:0] 0
116234     sync always
116235     sync init
116236       update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0]
116237   end
116238   attribute \src "ls180.v:1385.5-1385.39"
116239   process $proc$ls180.v:1385$3353
116240     assign { } { }
116241     assign $1\main_sdcore_cmd_argument_re[0:0] 1'0
116242     sync always
116243     sync init
116244       update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0]
116245   end
116246   attribute \src "ls180.v:1386.12-1386.51"
116247   process $proc$ls180.v:1386$3354
116248     assign { } { }
116249     assign $1\main_sdcore_cmd_command_storage[31:0] 0
116250     sync always
116251     sync init
116252       update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0]
116253   end
116254   attribute \src "ls180.v:1387.5-1387.38"
116255   process $proc$ls180.v:1387$3355
116256     assign { } { }
116257     assign $1\main_sdcore_cmd_command_re[0:0] 1'0
116258     sync always
116259     sync init
116260       update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0]
116261   end
116262   attribute \src "ls180.v:1391.5-1391.34"
116263   process $proc$ls180.v:1391$3356
116264     assign { } { }
116265     assign $0\main_sdcore_cmd_send_w[0:0] 1'0
116266     sync always
116267       update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0]
116268     sync init
116269   end
116270   attribute \src "ls180.v:1392.13-1392.53"
116271   process $proc$ls180.v:1392$3357
116272     assign { } { }
116273     assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
116274     sync always
116275     sync init
116276       update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0]
116277   end
116278   attribute \src "ls180.v:1398.11-1398.51"
116279   process $proc$ls180.v:1398$3358
116280     assign { } { }
116281     assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000
116282     sync always
116283     sync init
116284       update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0]
116285   end
116286   attribute \src "ls180.v:1399.5-1399.39"
116287   process $proc$ls180.v:1399$3359
116288     assign { } { }
116289     assign $1\main_sdcore_block_length_re[0:0] 1'0
116290     sync always
116291     sync init
116292       update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
116293   end
116294   attribute \src "ls180.v:140.11-140.24"
116295   process $proc$ls180.v:140$2790
116296     assign { } { }
116297     assign $0\eint_1[2:0] 3'000
116298     sync always
116299       update \eint_1 $0\eint_1[2:0]
116300     sync init
116301   end
116302   attribute \src "ls180.v:1400.12-1400.51"
116303   process $proc$ls180.v:1400$3360
116304     assign { } { }
116305     assign $1\main_sdcore_block_count_storage[31:0] 0
116306     sync always
116307     sync init
116308       update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0]
116309   end
116310   attribute \src "ls180.v:1401.5-1401.38"
116311   process $proc$ls180.v:1401$3361
116312     assign { } { }
116313     assign $1\main_sdcore_block_count_re[0:0] 1'0
116314     sync always
116315     sync init
116316       update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0]
116317   end
116318   attribute \src "ls180.v:1402.11-1402.51"
116319   process $proc$ls180.v:1402$3362
116320     assign { } { }
116321     assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
116322     sync always
116323     sync init
116324       update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
116325   end
116326   attribute \src "ls180.v:1444.11-1444.47"
116327   process $proc$ls180.v:1444$3363
116328     assign { } { }
116329     assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
116330     sync always
116331     sync init
116332       update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0]
116333   end
116334   attribute \src "ls180.v:1448.5-1448.49"
116335   process $proc$ls180.v:1448$3364
116336     assign { } { }
116337     assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
116338     sync always
116339     sync init
116340       update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
116341   end
116342   attribute \src "ls180.v:145.5-145.74"
116343   process $proc$ls180.v:145$2791
116344     assign { } { }
116345     assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
116346     sync always
116347       update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
116348     sync init
116349   end
116350   attribute \src "ls180.v:1452.5-1452.51"
116351   process $proc$ls180.v:1452$3365
116352     assign { } { }
116353     assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
116354     sync always
116355     sync init
116356       update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0]
116357   end
116358   attribute \src "ls180.v:1453.5-1453.51"
116359   process $proc$ls180.v:1453$3366
116360     assign { } { }
116361     assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
116362     sync always
116363     sync init
116364       update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0]
116365   end
116366   attribute \src "ls180.v:1454.5-1454.51"
116367   process $proc$ls180.v:1454$3367
116368     assign { } { }
116369     assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0
116370     sync always
116371       update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0]
116372     sync init
116373   end
116374   attribute \src "ls180.v:1455.5-1455.50"
116375   process $proc$ls180.v:1455$3368
116376     assign { } { }
116377     assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0
116378     sync always
116379     sync init
116380       update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0]
116381   end
116382   attribute \src "ls180.v:1456.11-1456.64"
116383   process $proc$ls180.v:1456$3369
116384     assign { } { }
116385     assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
116386     sync always
116387     sync init
116388       update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
116389   end
116390   attribute \src "ls180.v:1457.11-1457.48"
116391   process $proc$ls180.v:1457$3370
116392     assign { } { }
116393     assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000
116394     sync always
116395     sync init
116396       update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0]
116397   end
116398   attribute \src "ls180.v:1458.12-1458.59"
116399   process $proc$ls180.v:1458$3371
116400     assign { } { }
116401     assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
116402     sync always
116403     sync init
116404       update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
116405   end
116406   attribute \src "ls180.v:1462.12-1462.55"
116407   process $proc$ls180.v:1462$3372
116408     assign { } { }
116409     assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
116410     sync always
116411     sync init
116412       update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
116413   end
116414   attribute \src "ls180.v:1465.12-1465.59"
116415   process $proc$ls180.v:1465$3373
116416     assign { } { }
116417     assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
116418     sync always
116419     sync init
116420       update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
116421   end
116422   attribute \src "ls180.v:1469.12-1469.55"
116423   process $proc$ls180.v:1469$3374
116424     assign { } { }
116425     assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
116426     sync always
116427     sync init
116428       update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
116429   end
116430   attribute \src "ls180.v:147.12-147.78"
116431   process $proc$ls180.v:147$2792
116432     assign { } { }
116433     assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
116434     sync always
116435       update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
116436     sync init
116437   end
116438   attribute \src "ls180.v:1472.12-1472.59"
116439   process $proc$ls180.v:1472$3375
116440     assign { } { }
116441     assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
116442     sync always
116443     sync init
116444       update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
116445   end
116446   attribute \src "ls180.v:1476.12-1476.55"
116447   process $proc$ls180.v:1476$3376
116448     assign { } { }
116449     assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
116450     sync always
116451     sync init
116452       update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
116453   end
116454   attribute \src "ls180.v:1479.12-1479.59"
116455   process $proc$ls180.v:1479$3377
116456     assign { } { }
116457     assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
116458     sync always
116459     sync init
116460       update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
116461   end
116462   attribute \src "ls180.v:1483.12-1483.55"
116463   process $proc$ls180.v:1483$3378
116464     assign { } { }
116465     assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
116466     sync always
116467     sync init
116468       update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
116469   end
116470   attribute \src "ls180.v:1486.12-1486.54"
116471   process $proc$ls180.v:1486$3379
116472     assign { } { }
116473     assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
116474     sync always
116475     sync init
116476       update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
116477   end
116478   attribute \src "ls180.v:1487.12-1487.54"
116479   process $proc$ls180.v:1487$3380
116480     assign { } { }
116481     assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
116482     sync always
116483     sync init
116484       update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
116485   end
116486   attribute \src "ls180.v:1488.12-1488.54"
116487   process $proc$ls180.v:1488$3381
116488     assign { } { }
116489     assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
116490     sync always
116491     sync init
116492       update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
116493   end
116494   attribute \src "ls180.v:1489.12-1489.54"
116495   process $proc$ls180.v:1489$3382
116496     assign { } { }
116497     assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
116498     sync always
116499     sync init
116500       update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
116501   end
116502   attribute \src "ls180.v:1490.5-1490.48"
116503   process $proc$ls180.v:1490$3383
116504     assign { } { }
116505     assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
116506     sync always
116507     sync init
116508       update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0]
116509   end
116510   attribute \src "ls180.v:1491.5-1491.48"
116511   process $proc$ls180.v:1491$3384
116512     assign { } { }
116513     assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
116514     sync always
116515     sync init
116516       update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0]
116517   end
116518   attribute \src "ls180.v:1492.5-1492.48"
116519   process $proc$ls180.v:1492$3385
116520     assign { } { }
116521     assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0
116522     sync always
116523     sync init
116524       update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0]
116525   end
116526   attribute \src "ls180.v:1493.5-1493.47"
116527   process $proc$ls180.v:1493$3386
116528     assign { } { }
116529     assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0
116530     sync always
116531     sync init
116532       update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0]
116533   end
116534   attribute \src "ls180.v:1494.11-1494.61"
116535   process $proc$ls180.v:1494$3387
116536     assign { } { }
116537     assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
116538     sync always
116539     sync init
116540       update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
116541   end
116542   attribute \src "ls180.v:1495.5-1495.50"
116543   process $proc$ls180.v:1495$3388
116544     assign { } { }
116545     assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0
116546     sync always
116547     sync init
116548       update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0]
116549   end
116550   attribute \src "ls180.v:1497.5-1497.50"
116551   process $proc$ls180.v:1497$3389
116552     assign { } { }
116553     assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0
116554     sync always
116555       update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0]
116556     sync init
116557   end
116558   attribute \src "ls180.v:1500.11-1500.47"
116559   process $proc$ls180.v:1500$3390
116560     assign { } { }
116561     assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000
116562     sync always
116563     sync init
116564       update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0]
116565   end
116566   attribute \src "ls180.v:1501.11-1501.47"
116567   process $proc$ls180.v:1501$3391
116568     assign { } { }
116569     assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000
116570     sync always
116571     sync init
116572       update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0]
116573   end
116574   attribute \src "ls180.v:1502.12-1502.58"
116575   process $proc$ls180.v:1502$3392
116576     assign { } { }
116577     assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
116578     sync always
116579     sync init
116580       update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
116581   end
116582   attribute \src "ls180.v:1506.12-1506.54"
116583   process $proc$ls180.v:1506$3393
116584     assign { } { }
116585     assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
116586     sync always
116587     sync init
116588       update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0]
116589   end
116590   attribute \src "ls180.v:1507.5-1507.46"
116591   process $proc$ls180.v:1507$3394
116592     assign { } { }
116593     assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
116594     sync always
116595     sync init
116596       update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0]
116597   end
116598   attribute \src "ls180.v:1509.12-1509.58"
116599   process $proc$ls180.v:1509$3395
116600     assign { } { }
116601     assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
116602     sync always
116603     sync init
116604       update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
116605   end
116606   attribute \src "ls180.v:1513.12-1513.54"
116607   process $proc$ls180.v:1513$3396
116608     assign { } { }
116609     assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
116610     sync always
116611     sync init
116612       update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0]
116613   end
116614   attribute \src "ls180.v:1514.5-1514.46"
116615   process $proc$ls180.v:1514$3397
116616     assign { } { }
116617     assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
116618     sync always
116619     sync init
116620       update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0]
116621   end
116622   attribute \src "ls180.v:1516.12-1516.58"
116623   process $proc$ls180.v:1516$3398
116624     assign { } { }
116625     assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
116626     sync always
116627     sync init
116628       update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
116629   end
116630   attribute \src "ls180.v:1520.12-1520.54"
116631   process $proc$ls180.v:1520$3399
116632     assign { } { }
116633     assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
116634     sync always
116635     sync init
116636       update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0]
116637   end
116638   attribute \src "ls180.v:1521.5-1521.46"
116639   process $proc$ls180.v:1521$3400
116640     assign { } { }
116641     assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
116642     sync always
116643     sync init
116644       update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0]
116645   end
116646   attribute \src "ls180.v:1523.12-1523.58"
116647   process $proc$ls180.v:1523$3401
116648     assign { } { }
116649     assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
116650     sync always
116651     sync init
116652       update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
116653   end
116654   attribute \src "ls180.v:1527.12-1527.54"
116655   process $proc$ls180.v:1527$3402
116656     assign { } { }
116657     assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
116658     sync always
116659     sync init
116660       update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
116661   end
116662   attribute \src "ls180.v:1528.5-1528.46"
116663   process $proc$ls180.v:1528$3403
116664     assign { } { }
116665     assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
116666     sync always
116667     sync init
116668       update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0]
116669   end
116670   attribute \src "ls180.v:1530.12-1530.53"
116671   process $proc$ls180.v:1530$3404
116672     assign { } { }
116673     assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
116674     sync always
116675     sync init
116676       update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0]
116677   end
116678   attribute \src "ls180.v:1531.12-1531.53"
116679   process $proc$ls180.v:1531$3405
116680     assign { } { }
116681     assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
116682     sync always
116683     sync init
116684       update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0]
116685   end
116686   attribute \src "ls180.v:1532.12-1532.53"
116687   process $proc$ls180.v:1532$3406
116688     assign { } { }
116689     assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
116690     sync always
116691     sync init
116692       update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0]
116693   end
116694   attribute \src "ls180.v:1533.12-1533.53"
116695   process $proc$ls180.v:1533$3407
116696     assign { } { }
116697     assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
116698     sync always
116699     sync init
116700       update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0]
116701   end
116702   attribute \src "ls180.v:1534.5-1534.43"
116703   process $proc$ls180.v:1534$3408
116704     assign { } { }
116705     assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0
116706     sync always
116707     sync init
116708       update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0]
116709   end
116710   attribute \src "ls180.v:1535.12-1535.51"
116711   process $proc$ls180.v:1535$3409
116712     assign { } { }
116713     assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
116714     sync always
116715     sync init
116716       update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0]
116717   end
116718   attribute \src "ls180.v:1536.12-1536.51"
116719   process $proc$ls180.v:1536$3410
116720     assign { } { }
116721     assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
116722     sync always
116723     sync init
116724       update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0]
116725   end
116726   attribute \src "ls180.v:1537.12-1537.51"
116727   process $proc$ls180.v:1537$3411
116728     assign { } { }
116729     assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
116730     sync always
116731     sync init
116732       update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0]
116733   end
116734   attribute \src "ls180.v:1538.12-1538.51"
116735   process $proc$ls180.v:1538$3412
116736     assign { } { }
116737     assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
116738     sync always
116739     sync init
116740       update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
116741   end
116742   attribute \src "ls180.v:1540.11-1540.39"
116743   process $proc$ls180.v:1540$3413
116744     assign { } { }
116745     assign $1\main_sdcore_cmd_count[2:0] 3'000
116746     sync always
116747     sync init
116748       update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0]
116749   end
116750   attribute \src "ls180.v:1541.5-1541.32"
116751   process $proc$ls180.v:1541$3414
116752     assign { } { }
116753     assign $1\main_sdcore_cmd_done[0:0] 1'0
116754     sync always
116755     sync init
116756       update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0]
116757   end
116758   attribute \src "ls180.v:1542.5-1542.33"
116759   process $proc$ls180.v:1542$3415
116760     assign { } { }
116761     assign $1\main_sdcore_cmd_error[0:0] 1'0
116762     sync always
116763     sync init
116764       update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0]
116765   end
116766   attribute \src "ls180.v:1543.5-1543.35"
116767   process $proc$ls180.v:1543$3416
116768     assign { } { }
116769     assign $1\main_sdcore_cmd_timeout[0:0] 1'0
116770     sync always
116771     sync init
116772       update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0]
116773   end
116774   attribute \src "ls180.v:1545.12-1545.42"
116775   process $proc$ls180.v:1545$3417
116776     assign { } { }
116777     assign $1\main_sdcore_data_count[31:0] 0
116778     sync always
116779     sync init
116780       update \main_sdcore_data_count $1\main_sdcore_data_count[31:0]
116781   end
116782   attribute \src "ls180.v:1546.5-1546.33"
116783   process $proc$ls180.v:1546$3418
116784     assign { } { }
116785     assign $1\main_sdcore_data_done[0:0] 1'0
116786     sync always
116787     sync init
116788       update \main_sdcore_data_done $1\main_sdcore_data_done[0:0]
116789   end
116790   attribute \src "ls180.v:1547.5-1547.34"
116791   process $proc$ls180.v:1547$3419
116792     assign { } { }
116793     assign $1\main_sdcore_data_error[0:0] 1'0
116794     sync always
116795     sync init
116796       update \main_sdcore_data_error $1\main_sdcore_data_error[0:0]
116797   end
116798   attribute \src "ls180.v:1548.5-1548.36"
116799   process $proc$ls180.v:1548$3420
116800     assign { } { }
116801     assign $1\main_sdcore_data_timeout[0:0] 1'0
116802     sync always
116803     sync init
116804       update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
116805   end
116806   attribute \src "ls180.v:1557.11-1557.41"
116807   process $proc$ls180.v:1557$3421
116808     assign { } { }
116809     assign $0\main_interface0_bus_cti[2:0] 3'000
116810     sync always
116811       update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0]
116812     sync init
116813   end
116814   attribute \src "ls180.v:1558.11-1558.41"
116815   process $proc$ls180.v:1558$3422
116816     assign { } { }
116817     assign $0\main_interface0_bus_bte[1:0] 2'00
116818     sync always
116819       update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0]
116820     sync init
116821   end
116822   attribute \src "ls180.v:1581.11-1581.45"
116823   process $proc$ls180.v:1581$3423
116824     assign { } { }
116825     assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
116826     sync always
116827     sync init
116828       update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
116829   end
116830   attribute \src "ls180.v:1582.5-1582.41"
116831   process $proc$ls180.v:1582$3424
116832     assign { } { }
116833     assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0
116834     sync always
116835       update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0]
116836     sync init
116837   end
116838   attribute \src "ls180.v:1583.11-1583.47"
116839   process $proc$ls180.v:1583$3425
116840     assign { } { }
116841     assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000
116842     sync always
116843     sync init
116844       update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0]
116845   end
116846   attribute \src "ls180.v:1584.11-1584.47"
116847   process $proc$ls180.v:1584$3426
116848     assign { } { }
116849     assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000
116850     sync always
116851     sync init
116852       update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0]
116853   end
116854   attribute \src "ls180.v:1585.11-1585.50"
116855   process $proc$ls180.v:1585$3427
116856     assign { } { }
116857     assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
116858     sync always
116859     sync init
116860       update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
116861   end
116862   attribute \src "ls180.v:159.5-159.69"
116863   process $proc$ls180.v:159$2793
116864     assign { } { }
116865     assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
116866     sync always
116867       update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
116868     sync init
116869   end
116870   attribute \src "ls180.v:1605.5-1605.51"
116871   process $proc$ls180.v:1605$3428
116872     assign { } { }
116873     assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0
116874     sync always
116875     sync init
116876       update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0]
116877   end
116878   attribute \src "ls180.v:1606.5-1606.50"
116879   process $proc$ls180.v:1606$3429
116880     assign { } { }
116881     assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0
116882     sync always
116883     sync init
116884       update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0]
116885   end
116886   attribute \src "ls180.v:1607.12-1607.66"
116887   process $proc$ls180.v:1607$3430
116888     assign { } { }
116889     assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0
116890     sync always
116891     sync init
116892       update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0]
116893   end
116894   attribute \src "ls180.v:1608.11-1608.77"
116895   process $proc$ls180.v:1608$3431
116896     assign { } { }
116897     assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000
116898     sync always
116899     sync init
116900       update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
116901   end
116902   attribute \src "ls180.v:1609.11-1609.50"
116903   process $proc$ls180.v:1609$3432
116904     assign { } { }
116905     assign $1\main_sdblock2mem_converter_demux[1:0] 2'00
116906     sync always
116907     sync init
116908       update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
116909   end
116910   attribute \src "ls180.v:1611.5-1611.49"
116911   process $proc$ls180.v:1611$3433
116912     assign { } { }
116913     assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0
116914     sync always
116915     sync init
116916       update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0]
116917   end
116918   attribute \src "ls180.v:1617.5-1617.45"
116919   process $proc$ls180.v:1617$3434
116920     assign { } { }
116921     assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
116922     sync always
116923     sync init
116924       update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
116925   end
116926   attribute \src "ls180.v:1619.12-1619.62"
116927   process $proc$ls180.v:1619$3435
116928     assign { } { }
116929     assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
116930     sync always
116931     sync init
116932       update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
116933   end
116934   attribute \src "ls180.v:162.12-162.71"
116935   process $proc$ls180.v:162$2794
116936     assign { } { }
116937     assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
116938     sync always
116939     sync init
116940       update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
116941   end
116942   attribute \src "ls180.v:1620.12-1620.60"
116943   process $proc$ls180.v:1620$3436
116944     assign { } { }
116945     assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
116946     sync always
116947     sync init
116948       update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
116949   end
116950   attribute \src "ls180.v:1622.5-1622.57"
116951   process $proc$ls180.v:1622$3437
116952     assign { } { }
116953     assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
116954     sync always
116955     sync init
116956       update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
116957   end
116958   attribute \src "ls180.v:1626.12-1626.67"
116959   process $proc$ls180.v:1626$3438
116960     assign { } { }
116961     assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
116962     sync always
116963     sync init
116964       update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
116965   end
116966   attribute \src "ls180.v:1627.5-1627.54"
116967   process $proc$ls180.v:1627$3439
116968     assign { } { }
116969     assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
116970     sync always
116971     sync init
116972       update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
116973   end
116974   attribute \src "ls180.v:1628.12-1628.69"
116975   process $proc$ls180.v:1628$3440
116976     assign { } { }
116977     assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
116978     sync always
116979     sync init
116980       update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
116981   end
116982   attribute \src "ls180.v:1629.5-1629.56"
116983   process $proc$ls180.v:1629$3441
116984     assign { } { }
116985     assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
116986     sync always
116987     sync init
116988       update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
116989   end
116990   attribute \src "ls180.v:163.12-163.73"
116991   process $proc$ls180.v:163$2795
116992     assign { } { }
116993     assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
116994     sync always
116995     sync init
116996       update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
116997   end
116998   attribute \src "ls180.v:1630.5-1630.61"
116999   process $proc$ls180.v:1630$3442
117000     assign { } { }
117001     assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
117002     sync always
117003     sync init
117004       update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
117005   end
117006   attribute \src "ls180.v:1631.5-1631.56"
117007   process $proc$ls180.v:1631$3443
117008     assign { } { }
117009     assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
117010     sync always
117011     sync init
117012       update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
117013   end
117014   attribute \src "ls180.v:1632.5-1632.53"
117015   process $proc$ls180.v:1632$3444
117016     assign { } { }
117017     assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
117018     sync always
117019     sync init
117020       update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
117021   end
117022   attribute \src "ls180.v:1634.5-1634.59"
117023   process $proc$ls180.v:1634$3445
117024     assign { } { }
117025     assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
117026     sync always
117027     sync init
117028       update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
117029   end
117030   attribute \src "ls180.v:1635.5-1635.54"
117031   process $proc$ls180.v:1635$3446
117032     assign { } { }
117033     assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
117034     sync always
117035     sync init
117036       update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
117037   end
117038   attribute \src "ls180.v:1637.12-1637.61"
117039   process $proc$ls180.v:1637$3447
117040     assign { } { }
117041     assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
117042     sync always
117043     sync init
117044       update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
117045   end
117046   attribute \src "ls180.v:1640.12-1640.43"
117047   process $proc$ls180.v:1640$3448
117048     assign { } { }
117049     assign $1\main_interface1_bus_adr[31:0] 0
117050     sync always
117051     sync init
117052       update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0]
117053   end
117054   attribute \src "ls180.v:1641.12-1641.45"
117055   process $proc$ls180.v:1641$3449
117056     assign { } { }
117057     assign $0\main_interface1_bus_dat_w[31:0] 0
117058     sync always
117059       update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0]
117060     sync init
117061   end
117062   attribute \src "ls180.v:1643.11-1643.41"
117063   process $proc$ls180.v:1643$3450
117064     assign { } { }
117065     assign $1\main_interface1_bus_sel[3:0] 4'0000
117066     sync always
117067     sync init
117068       update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0]
117069   end
117070   attribute \src "ls180.v:1644.5-1644.35"
117071   process $proc$ls180.v:1644$3451
117072     assign { } { }
117073     assign $1\main_interface1_bus_cyc[0:0] 1'0
117074     sync always
117075     sync init
117076       update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0]
117077   end
117078   attribute \src "ls180.v:1645.5-1645.35"
117079   process $proc$ls180.v:1645$3452
117080     assign { } { }
117081     assign $1\main_interface1_bus_stb[0:0] 1'0
117082     sync always
117083     sync init
117084       update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0]
117085   end
117086   attribute \src "ls180.v:1647.5-1647.34"
117087   process $proc$ls180.v:1647$3453
117088     assign { } { }
117089     assign $1\main_interface1_bus_we[0:0] 1'0
117090     sync always
117091     sync init
117092       update \main_interface1_bus_we $1\main_interface1_bus_we[0:0]
117093   end
117094   attribute \src "ls180.v:1648.11-1648.41"
117095   process $proc$ls180.v:1648$3454
117096     assign { } { }
117097     assign $0\main_interface1_bus_cti[2:0] 3'000
117098     sync always
117099       update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0]
117100     sync init
117101   end
117102   attribute \src "ls180.v:1649.11-1649.41"
117103   process $proc$ls180.v:1649$3455
117104     assign { } { }
117105     assign $0\main_interface1_bus_bte[1:0] 2'00
117106     sync always
117107       update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0]
117108     sync init
117109   end
117110   attribute \src "ls180.v:165.11-165.69"
117111   process $proc$ls180.v:165$2796
117112     assign { } { }
117113     assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
117114     sync always
117115     sync init
117116       update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
117117   end
117118   attribute \src "ls180.v:1656.5-1656.43"
117119   process $proc$ls180.v:1656$3456
117120     assign { } { }
117121     assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0
117122     sync always
117123     sync init
117124       update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0]
117125   end
117126   attribute \src "ls180.v:1657.5-1657.43"
117127   process $proc$ls180.v:1657$3457
117128     assign { } { }
117129     assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0
117130     sync always
117131     sync init
117132       update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0]
117133   end
117134   attribute \src "ls180.v:1658.5-1658.42"
117135   process $proc$ls180.v:1658$3458
117136     assign { } { }
117137     assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0
117138     sync always
117139     sync init
117140       update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0]
117141   end
117142   attribute \src "ls180.v:1659.12-1659.61"
117143   process $proc$ls180.v:1659$3459
117144     assign { } { }
117145     assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0
117146     sync always
117147     sync init
117148       update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0]
117149   end
117150   attribute \src "ls180.v:166.5-166.63"
117151   process $proc$ls180.v:166$2797
117152     assign { } { }
117153     assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
117154     sync always
117155     sync init
117156       update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
117157   end
117158   attribute \src "ls180.v:1660.5-1660.45"
117159   process $proc$ls180.v:1660$3460
117160     assign { } { }
117161     assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0
117162     sync always
117163     sync init
117164       update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0]
117165   end
117166   attribute \src "ls180.v:1662.5-1662.45"
117167   process $proc$ls180.v:1662$3461
117168     assign { } { }
117169     assign $0\main_sdmem2block_dma_source_first[0:0] 1'0
117170     sync always
117171       update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0]
117172     sync init
117173   end
117174   attribute \src "ls180.v:1663.5-1663.44"
117175   process $proc$ls180.v:1663$3462
117176     assign { } { }
117177     assign $1\main_sdmem2block_dma_source_last[0:0] 1'0
117178     sync always
117179     sync init
117180       update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0]
117181   end
117182   attribute \src "ls180.v:1664.12-1664.60"
117183   process $proc$ls180.v:1664$3463
117184     assign { } { }
117185     assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0
117186     sync always
117187     sync init
117188       update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0]
117189   end
117190   attribute \src "ls180.v:1665.12-1665.45"
117191   process $proc$ls180.v:1665$3464
117192     assign { } { }
117193     assign $1\main_sdmem2block_dma_data[31:0] 0
117194     sync always
117195     sync init
117196       update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0]
117197   end
117198   attribute \src "ls180.v:1666.12-1666.53"
117199   process $proc$ls180.v:1666$3465
117200     assign { } { }
117201     assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
117202     sync always
117203     sync init
117204       update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0]
117205   end
117206   attribute \src "ls180.v:1667.5-1667.40"
117207   process $proc$ls180.v:1667$3466
117208     assign { } { }
117209     assign $1\main_sdmem2block_dma_base_re[0:0] 1'0
117210     sync always
117211     sync init
117212       update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0]
117213   end
117214   attribute \src "ls180.v:1668.12-1668.55"
117215   process $proc$ls180.v:1668$3467
117216     assign { } { }
117217     assign $1\main_sdmem2block_dma_length_storage[31:0] 0
117218     sync always
117219     sync init
117220       update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0]
117221   end
117222   attribute \src "ls180.v:1669.5-1669.42"
117223   process $proc$ls180.v:1669$3468
117224     assign { } { }
117225     assign $1\main_sdmem2block_dma_length_re[0:0] 1'0
117226     sync always
117227     sync init
117228       update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0]
117229   end
117230   attribute \src "ls180.v:167.5-167.63"
117231   process $proc$ls180.v:167$2798
117232     assign { } { }
117233     assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
117234     sync always
117235     sync init
117236       update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
117237   end
117238   attribute \src "ls180.v:1670.5-1670.47"
117239   process $proc$ls180.v:1670$3469
117240     assign { } { }
117241     assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0
117242     sync always
117243     sync init
117244       update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0]
117245   end
117246   attribute \src "ls180.v:1671.5-1671.42"
117247   process $proc$ls180.v:1671$3470
117248     assign { } { }
117249     assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0
117250     sync always
117251     sync init
117252       update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0]
117253   end
117254   attribute \src "ls180.v:1672.5-1672.44"
117255   process $proc$ls180.v:1672$3471
117256     assign { } { }
117257     assign $1\main_sdmem2block_dma_done_status[0:0] 1'0
117258     sync always
117259     sync init
117260       update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0]
117261   end
117262   attribute \src "ls180.v:1674.5-1674.45"
117263   process $proc$ls180.v:1674$3472
117264     assign { } { }
117265     assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0
117266     sync always
117267     sync init
117268       update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0]
117269   end
117270   attribute \src "ls180.v:1675.5-1675.40"
117271   process $proc$ls180.v:1675$3473
117272     assign { } { }
117273     assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0
117274     sync always
117275     sync init
117276       update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0]
117277   end
117278   attribute \src "ls180.v:1679.12-1679.47"
117279   process $proc$ls180.v:1679$3474
117280     assign { } { }
117281     assign $1\main_sdmem2block_dma_offset[31:0] 0
117282     sync always
117283     sync init
117284       update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0]
117285   end
117286   attribute \src "ls180.v:169.5-169.62"
117287   process $proc$ls180.v:169$2799
117288     assign { } { }
117289     assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
117290     sync always
117291     sync init
117292       update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
117293   end
117294   attribute \src "ls180.v:1691.11-1691.64"
117295   process $proc$ls180.v:1691$3475
117296     assign { } { }
117297     assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
117298     sync always
117299     sync init
117300       update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
117301   end
117302   attribute \src "ls180.v:1693.11-1693.48"
117303   process $proc$ls180.v:1693$3476
117304     assign { } { }
117305     assign $1\main_sdmem2block_converter_mux[1:0] 2'00
117306     sync always
117307     sync init
117308       update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0]
117309   end
117310   attribute \src "ls180.v:170.11-170.69"
117311   process $proc$ls180.v:170$2800
117312     assign { } { }
117313     assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
117314     sync always
117315       update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0]
117316     sync init
117317   end
117318   attribute \src "ls180.v:171.11-171.69"
117319   process $proc$ls180.v:171$2801
117320     assign { } { }
117321     assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
117322     sync always
117323       update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0]
117324     sync init
117325   end
117326   attribute \src "ls180.v:1717.11-1717.45"
117327   process $proc$ls180.v:1717$3477
117328     assign { } { }
117329     assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
117330     sync always
117331     sync init
117332       update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
117333   end
117334   attribute \src "ls180.v:1718.5-1718.41"
117335   process $proc$ls180.v:1718$3478
117336     assign { } { }
117337     assign $0\main_sdmem2block_fifo_replace[0:0] 1'0
117338     sync always
117339       update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0]
117340     sync init
117341   end
117342   attribute \src "ls180.v:1719.11-1719.47"
117343   process $proc$ls180.v:1719$3479
117344     assign { } { }
117345     assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000
117346     sync always
117347     sync init
117348       update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0]
117349   end
117350   attribute \src "ls180.v:1720.11-1720.47"
117351   process $proc$ls180.v:1720$3480
117352     assign { } { }
117353     assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000
117354     sync always
117355     sync init
117356       update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0]
117357   end
117358   attribute \src "ls180.v:1721.11-1721.50"
117359   process $proc$ls180.v:1721$3481
117360     assign { } { }
117361     assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
117362     sync always
117363     sync init
117364       update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0]
117365   end
117366   attribute \src "ls180.v:173.5-173.44"
117367   process $proc$ls180.v:173$2802
117368     assign { } { }
117369     assign $1\main_libresocsim_converter0_skip[0:0] 1'0
117370     sync always
117371     sync init
117372       update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
117373   end
117374   attribute \src "ls180.v:1734.5-1734.36"
117375   process $proc$ls180.v:1734$3482
117376     assign { } { }
117377     assign $1\builder_converter0_state[0:0] 1'0
117378     sync always
117379     sync init
117380       update \builder_converter0_state $1\builder_converter0_state[0:0]
117381   end
117382   attribute \src "ls180.v:1735.5-1735.41"
117383   process $proc$ls180.v:1735$3483
117384     assign { } { }
117385     assign $1\builder_converter0_next_state[0:0] 1'0
117386     sync always
117387     sync init
117388       update \builder_converter0_next_state $1\builder_converter0_next_state[0:0]
117389   end
117390   attribute \src "ls180.v:1736.5-1736.69"
117391   process $proc$ls180.v:1736$3484
117392     assign { } { }
117393     assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
117394     sync always
117395     sync init
117396       update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
117397   end
117398   attribute \src "ls180.v:1737.5-1737.72"
117399   process $proc$ls180.v:1737$3485
117400     assign { } { }
117401     assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
117402     sync always
117403     sync init
117404       update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
117405   end
117406   attribute \src "ls180.v:1738.5-1738.36"
117407   process $proc$ls180.v:1738$3486
117408     assign { } { }
117409     assign $1\builder_converter1_state[0:0] 1'0
117410     sync always
117411     sync init
117412       update \builder_converter1_state $1\builder_converter1_state[0:0]
117413   end
117414   attribute \src "ls180.v:1739.5-1739.41"
117415   process $proc$ls180.v:1739$3487
117416     assign { } { }
117417     assign $1\builder_converter1_next_state[0:0] 1'0
117418     sync always
117419     sync init
117420       update \builder_converter1_next_state $1\builder_converter1_next_state[0:0]
117421   end
117422   attribute \src "ls180.v:174.5-174.47"
117423   process $proc$ls180.v:174$2803
117424     assign { } { }
117425     assign $1\main_libresocsim_converter0_counter[0:0] 1'0
117426     sync always
117427     sync init
117428       update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
117429   end
117430   attribute \src "ls180.v:1740.5-1740.69"
117431   process $proc$ls180.v:1740$3488
117432     assign { } { }
117433     assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
117434     sync always
117435     sync init
117436       update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
117437   end
117438   attribute \src "ls180.v:1741.5-1741.72"
117439   process $proc$ls180.v:1741$3489
117440     assign { } { }
117441     assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
117442     sync always
117443     sync init
117444       update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
117445   end
117446   attribute \src "ls180.v:1742.5-1742.36"
117447   process $proc$ls180.v:1742$3490
117448     assign { } { }
117449     assign $1\builder_converter2_state[0:0] 1'0
117450     sync always
117451     sync init
117452       update \builder_converter2_state $1\builder_converter2_state[0:0]
117453   end
117454   attribute \src "ls180.v:1743.5-1743.41"
117455   process $proc$ls180.v:1743$3491
117456     assign { } { }
117457     assign $1\builder_converter2_next_state[0:0] 1'0
117458     sync always
117459     sync init
117460       update \builder_converter2_next_state $1\builder_converter2_next_state[0:0]
117461   end
117462   attribute \src "ls180.v:1744.5-1744.69"
117463   process $proc$ls180.v:1744$3492
117464     assign { } { }
117465     assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
117466     sync always
117467     sync init
117468       update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
117469   end
117470   attribute \src "ls180.v:1745.5-1745.72"
117471   process $proc$ls180.v:1745$3493
117472     assign { } { }
117473     assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
117474     sync always
117475     sync init
117476       update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
117477   end
117478   attribute \src "ls180.v:1746.11-1746.41"
117479   process $proc$ls180.v:1746$3494
117480     assign { } { }
117481     assign $1\builder_refresher_state[1:0] 2'00
117482     sync always
117483     sync init
117484       update \builder_refresher_state $1\builder_refresher_state[1:0]
117485   end
117486   attribute \src "ls180.v:1747.11-1747.46"
117487   process $proc$ls180.v:1747$3495
117488     assign { } { }
117489     assign $1\builder_refresher_next_state[1:0] 2'00
117490     sync always
117491     sync init
117492       update \builder_refresher_next_state $1\builder_refresher_next_state[1:0]
117493   end
117494   attribute \src "ls180.v:1748.11-1748.44"
117495   process $proc$ls180.v:1748$3496
117496     assign { } { }
117497     assign $1\builder_bankmachine0_state[2:0] 3'000
117498     sync always
117499     sync init
117500       update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0]
117501   end
117502   attribute \src "ls180.v:1749.11-1749.49"
117503   process $proc$ls180.v:1749$3497
117504     assign { } { }
117505     assign $1\builder_bankmachine0_next_state[2:0] 3'000
117506     sync always
117507     sync init
117508       update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0]
117509   end
117510   attribute \src "ls180.v:1750.11-1750.44"
117511   process $proc$ls180.v:1750$3498
117512     assign { } { }
117513     assign $1\builder_bankmachine1_state[2:0] 3'000
117514     sync always
117515     sync init
117516       update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0]
117517   end
117518   attribute \src "ls180.v:1751.11-1751.49"
117519   process $proc$ls180.v:1751$3499
117520     assign { } { }
117521     assign $1\builder_bankmachine1_next_state[2:0] 3'000
117522     sync always
117523     sync init
117524       update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0]
117525   end
117526   attribute \src "ls180.v:1752.11-1752.44"
117527   process $proc$ls180.v:1752$3500
117528     assign { } { }
117529     assign $1\builder_bankmachine2_state[2:0] 3'000
117530     sync always
117531     sync init
117532       update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0]
117533   end
117534   attribute \src "ls180.v:1753.11-1753.49"
117535   process $proc$ls180.v:1753$3501
117536     assign { } { }
117537     assign $1\builder_bankmachine2_next_state[2:0] 3'000
117538     sync always
117539     sync init
117540       update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0]
117541   end
117542   attribute \src "ls180.v:1754.11-1754.44"
117543   process $proc$ls180.v:1754$3502
117544     assign { } { }
117545     assign $1\builder_bankmachine3_state[2:0] 3'000
117546     sync always
117547     sync init
117548       update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0]
117549   end
117550   attribute \src "ls180.v:1755.11-1755.49"
117551   process $proc$ls180.v:1755$3503
117552     assign { } { }
117553     assign $1\builder_bankmachine3_next_state[2:0] 3'000
117554     sync always
117555     sync init
117556       update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0]
117557   end
117558   attribute \src "ls180.v:1756.11-1756.43"
117559   process $proc$ls180.v:1756$3504
117560     assign { } { }
117561     assign $1\builder_multiplexer_state[2:0] 3'000
117562     sync always
117563     sync init
117564       update \builder_multiplexer_state $1\builder_multiplexer_state[2:0]
117565   end
117566   attribute \src "ls180.v:1757.11-1757.48"
117567   process $proc$ls180.v:1757$3505
117568     assign { } { }
117569     assign $1\builder_multiplexer_next_state[2:0] 3'000
117570     sync always
117571     sync init
117572       update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0]
117573   end
117574   attribute \src "ls180.v:176.12-176.53"
117575   process $proc$ls180.v:176$2804
117576     assign { } { }
117577     assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
117578     sync always
117579     sync init
117580       update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
117581   end
117582   attribute \src "ls180.v:177.12-177.71"
117583   process $proc$ls180.v:177$2805
117584     assign { } { }
117585     assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
117586     sync always
117587     sync init
117588       update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
117589   end
117590   attribute \src "ls180.v:1770.5-1770.27"
117591   process $proc$ls180.v:1770$3506
117592     assign { } { }
117593     assign $0\builder_locked0[0:0] 1'0
117594     sync always
117595       update \builder_locked0 $0\builder_locked0[0:0]
117596     sync init
117597   end
117598   attribute \src "ls180.v:1771.5-1771.27"
117599   process $proc$ls180.v:1771$3507
117600     assign { } { }
117601     assign $0\builder_locked1[0:0] 1'0
117602     sync always
117603       update \builder_locked1 $0\builder_locked1[0:0]
117604     sync init
117605   end
117606   attribute \src "ls180.v:1772.5-1772.27"
117607   process $proc$ls180.v:1772$3508
117608     assign { } { }
117609     assign $0\builder_locked2[0:0] 1'0
117610     sync always
117611       update \builder_locked2 $0\builder_locked2[0:0]
117612     sync init
117613   end
117614   attribute \src "ls180.v:1773.5-1773.27"
117615   process $proc$ls180.v:1773$3509
117616     assign { } { }
117617     assign $0\builder_locked3[0:0] 1'0
117618     sync always
117619       update \builder_locked3 $0\builder_locked3[0:0]
117620     sync init
117621   end
117622   attribute \src "ls180.v:1774.5-1774.42"
117623   process $proc$ls180.v:1774$3510
117624     assign { } { }
117625     assign $1\builder_new_master_wdata_ready[0:0] 1'0
117626     sync always
117627     sync init
117628       update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0]
117629   end
117630   attribute \src "ls180.v:1775.5-1775.43"
117631   process $proc$ls180.v:1775$3511
117632     assign { } { }
117633     assign $1\builder_new_master_rdata_valid0[0:0] 1'0
117634     sync always
117635     sync init
117636       update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0]
117637   end
117638   attribute \src "ls180.v:1776.5-1776.43"
117639   process $proc$ls180.v:1776$3512
117640     assign { } { }
117641     assign $1\builder_new_master_rdata_valid1[0:0] 1'0
117642     sync always
117643     sync init
117644       update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0]
117645   end
117646   attribute \src "ls180.v:1777.5-1777.43"
117647   process $proc$ls180.v:1777$3513
117648     assign { } { }
117649     assign $1\builder_new_master_rdata_valid2[0:0] 1'0
117650     sync always
117651     sync init
117652       update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0]
117653   end
117654   attribute \src "ls180.v:1778.5-1778.43"
117655   process $proc$ls180.v:1778$3514
117656     assign { } { }
117657     assign $1\builder_new_master_rdata_valid3[0:0] 1'0
117658     sync always
117659     sync init
117660       update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0]
117661   end
117662   attribute \src "ls180.v:1779.5-1779.35"
117663   process $proc$ls180.v:1779$3515
117664     assign { } { }
117665     assign $1\builder_converter_state[0:0] 1'0
117666     sync always
117667     sync init
117668       update \builder_converter_state $1\builder_converter_state[0:0]
117669   end
117670   attribute \src "ls180.v:178.12-178.73"
117671   process $proc$ls180.v:178$2806
117672     assign { } { }
117673     assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
117674     sync always
117675     sync init
117676       update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
117677   end
117678   attribute \src "ls180.v:1780.5-1780.40"
117679   process $proc$ls180.v:1780$3516
117680     assign { } { }
117681     assign $1\builder_converter_next_state[0:0] 1'0
117682     sync always
117683     sync init
117684       update \builder_converter_next_state $1\builder_converter_next_state[0:0]
117685   end
117686   attribute \src "ls180.v:1781.5-1781.55"
117687   process $proc$ls180.v:1781$3517
117688     assign { } { }
117689     assign $1\main_converter_counter_converter_next_value[0:0] 1'0
117690     sync always
117691     sync init
117692       update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0]
117693   end
117694   attribute \src "ls180.v:1782.5-1782.58"
117695   process $proc$ls180.v:1782$3518
117696     assign { } { }
117697     assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0
117698     sync always
117699     sync init
117700       update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0]
117701   end
117702   attribute \src "ls180.v:1783.11-1783.42"
117703   process $proc$ls180.v:1783$3519
117704     assign { } { }
117705     assign $1\builder_spimaster0_state[1:0] 2'00
117706     sync always
117707     sync init
117708       update \builder_spimaster0_state $1\builder_spimaster0_state[1:0]
117709   end
117710   attribute \src "ls180.v:1784.11-1784.47"
117711   process $proc$ls180.v:1784$3520
117712     assign { } { }
117713     assign $1\builder_spimaster0_next_state[1:0] 2'00
117714     sync always
117715     sync init
117716       update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0]
117717   end
117718   attribute \src "ls180.v:1785.11-1785.62"
117719   process $proc$ls180.v:1785$3521
117720     assign { } { }
117721     assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
117722     sync always
117723     sync init
117724       update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0]
117725   end
117726   attribute \src "ls180.v:1786.5-1786.59"
117727   process $proc$ls180.v:1786$3522
117728     assign { } { }
117729     assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
117730     sync always
117731     sync init
117732       update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
117733   end
117734   attribute \src "ls180.v:1787.11-1787.42"
117735   process $proc$ls180.v:1787$3523
117736     assign { } { }
117737     assign $1\builder_spimaster1_state[1:0] 2'00
117738     sync always
117739     sync init
117740       update \builder_spimaster1_state $1\builder_spimaster1_state[1:0]
117741   end
117742   attribute \src "ls180.v:1788.11-1788.47"
117743   process $proc$ls180.v:1788$3524
117744     assign { } { }
117745     assign $1\builder_spimaster1_next_state[1:0] 2'00
117746     sync always
117747     sync init
117748       update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0]
117749   end
117750   attribute \src "ls180.v:1789.11-1789.60"
117751   process $proc$ls180.v:1789$3525
117752     assign { } { }
117753     assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
117754     sync always
117755     sync init
117756       update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0]
117757   end
117758   attribute \src "ls180.v:1790.5-1790.57"
117759   process $proc$ls180.v:1790$3526
117760     assign { } { }
117761     assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
117762     sync always
117763     sync init
117764       update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
117765   end
117766   attribute \src "ls180.v:1791.5-1791.41"
117767   process $proc$ls180.v:1791$3527
117768     assign { } { }
117769     assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0
117770     sync always
117771     sync init
117772       update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0]
117773   end
117774   attribute \src "ls180.v:1792.5-1792.46"
117775   process $proc$ls180.v:1792$3528
117776     assign { } { }
117777     assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0
117778     sync always
117779     sync init
117780       update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0]
117781   end
117782   attribute \src "ls180.v:1793.11-1793.66"
117783   process $proc$ls180.v:1793$3529
117784     assign { } { }
117785     assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
117786     sync always
117787     sync init
117788       update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
117789   end
117790   attribute \src "ls180.v:1794.5-1794.63"
117791   process $proc$ls180.v:1794$3530
117792     assign { } { }
117793     assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
117794     sync always
117795     sync init
117796       update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
117797   end
117798   attribute \src "ls180.v:1795.11-1795.47"
117799   process $proc$ls180.v:1795$3531
117800     assign { } { }
117801     assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00
117802     sync always
117803     sync init
117804       update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0]
117805   end
117806   attribute \src "ls180.v:1796.11-1796.52"
117807   process $proc$ls180.v:1796$3532
117808     assign { } { }
117809     assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
117810     sync always
117811     sync init
117812       update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0]
117813   end
117814   attribute \src "ls180.v:1797.11-1797.66"
117815   process $proc$ls180.v:1797$3533
117816     assign { } { }
117817     assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
117818     sync always
117819     sync init
117820       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
117821   end
117822   attribute \src "ls180.v:1798.5-1798.63"
117823   process $proc$ls180.v:1798$3534
117824     assign { } { }
117825     assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
117826     sync always
117827     sync init
117828       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
117829   end
117830   attribute \src "ls180.v:1799.11-1799.47"
117831   process $proc$ls180.v:1799$3535
117832     assign { } { }
117833     assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000
117834     sync always
117835     sync init
117836       update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0]
117837   end
117838   attribute \src "ls180.v:180.11-180.69"
117839   process $proc$ls180.v:180$2807
117840     assign { } { }
117841     assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
117842     sync always
117843     sync init
117844       update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
117845   end
117846   attribute \src "ls180.v:1800.11-1800.52"
117847   process $proc$ls180.v:1800$3536
117848     assign { } { }
117849     assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
117850     sync always
117851     sync init
117852       update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0]
117853   end
117854   attribute \src "ls180.v:1801.11-1801.67"
117855   process $proc$ls180.v:1801$3537
117856     assign { } { }
117857     assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
117858     sync always
117859     sync init
117860       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
117861   end
117862   attribute \src "ls180.v:1802.5-1802.64"
117863   process $proc$ls180.v:1802$3538
117864     assign { } { }
117865     assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
117866     sync always
117867     sync init
117868       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
117869   end
117870   attribute \src "ls180.v:1803.12-1803.71"
117871   process $proc$ls180.v:1803$3539
117872     assign { } { }
117873     assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
117874     sync always
117875     sync init
117876       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
117877   end
117878   attribute \src "ls180.v:1804.5-1804.66"
117879   process $proc$ls180.v:1804$3540
117880     assign { } { }
117881     assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
117882     sync always
117883     sync init
117884       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
117885   end
117886   attribute \src "ls180.v:1805.5-1805.66"
117887   process $proc$ls180.v:1805$3541
117888     assign { } { }
117889     assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
117890     sync always
117891     sync init
117892       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
117893   end
117894   attribute \src "ls180.v:1806.5-1806.69"
117895   process $proc$ls180.v:1806$3542
117896     assign { } { }
117897     assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
117898     sync always
117899     sync init
117900       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
117901   end
117902   attribute \src "ls180.v:1807.5-1807.41"
117903   process $proc$ls180.v:1807$3543
117904     assign { } { }
117905     assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0
117906     sync always
117907     sync init
117908       update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0]
117909   end
117910   attribute \src "ls180.v:1808.5-1808.46"
117911   process $proc$ls180.v:1808$3544
117912     assign { } { }
117913     assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
117914     sync always
117915     sync init
117916       update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0]
117917   end
117918   attribute \src "ls180.v:1809.5-1809.66"
117919   process $proc$ls180.v:1809$3545
117920     assign { } { }
117921     assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
117922     sync always
117923     sync init
117924       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
117925   end
117926   attribute \src "ls180.v:181.5-181.63"
117927   process $proc$ls180.v:181$2808
117928     assign { } { }
117929     assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
117930     sync always
117931     sync init
117932       update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
117933   end
117934   attribute \src "ls180.v:1810.5-1810.69"
117935   process $proc$ls180.v:1810$3546
117936     assign { } { }
117937     assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
117938     sync always
117939     sync init
117940       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
117941   end
117942   attribute \src "ls180.v:1811.11-1811.41"
117943   process $proc$ls180.v:1811$3547
117944     assign { } { }
117945     assign $1\builder_sdphy_fsm_state[2:0] 3'000
117946     sync always
117947     sync init
117948       update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0]
117949   end
117950   attribute \src "ls180.v:1812.11-1812.46"
117951   process $proc$ls180.v:1812$3548
117952     assign { } { }
117953     assign $1\builder_sdphy_fsm_next_state[2:0] 3'000
117954     sync always
117955     sync init
117956       update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0]
117957   end
117958   attribute \src "ls180.v:1813.11-1813.61"
117959   process $proc$ls180.v:1813$3549
117960     assign { } { }
117961     assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
117962     sync always
117963     sync init
117964       update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
117965   end
117966   attribute \src "ls180.v:1814.5-1814.58"
117967   process $proc$ls180.v:1814$3550
117968     assign { } { }
117969     assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
117970     sync always
117971     sync init
117972       update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
117973   end
117974   attribute \src "ls180.v:1815.11-1815.48"
117975   process $proc$ls180.v:1815$3551
117976     assign { } { }
117977     assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000
117978     sync always
117979     sync init
117980       update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0]
117981   end
117982   attribute \src "ls180.v:1816.11-1816.53"
117983   process $proc$ls180.v:1816$3552
117984     assign { } { }
117985     assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000
117986     sync always
117987     sync init
117988       update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0]
117989   end
117990   attribute \src "ls180.v:1817.11-1817.70"
117991   process $proc$ls180.v:1817$3553
117992     assign { } { }
117993     assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
117994     sync always
117995     sync init
117996       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
117997   end
117998   attribute \src "ls180.v:1818.5-1818.66"
117999   process $proc$ls180.v:1818$3554
118000     assign { } { }
118001     assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
118002     sync always
118003     sync init
118004       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
118005   end
118006   attribute \src "ls180.v:1819.12-1819.73"
118007   process $proc$ls180.v:1819$3555
118008     assign { } { }
118009     assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
118010     sync always
118011     sync init
118012       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
118013   end
118014   attribute \src "ls180.v:182.5-182.63"
118015   process $proc$ls180.v:182$2809
118016     assign { } { }
118017     assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
118018     sync always
118019     sync init
118020       update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
118021   end
118022   attribute \src "ls180.v:1820.5-1820.68"
118023   process $proc$ls180.v:1820$3556
118024     assign { } { }
118025     assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
118026     sync always
118027     sync init
118028       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
118029   end
118030   attribute \src "ls180.v:1821.5-1821.69"
118031   process $proc$ls180.v:1821$3557
118032     assign { } { }
118033     assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
118034     sync always
118035     sync init
118036       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
118037   end
118038   attribute \src "ls180.v:1822.5-1822.72"
118039   process $proc$ls180.v:1822$3558
118040     assign { } { }
118041     assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
118042     sync always
118043     sync init
118044       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
118045   end
118046   attribute \src "ls180.v:1823.5-1823.52"
118047   process $proc$ls180.v:1823$3559
118048     assign { } { }
118049     assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
118050     sync always
118051     sync init
118052       update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0]
118053   end
118054   attribute \src "ls180.v:1824.5-1824.57"
118055   process $proc$ls180.v:1824$3560
118056     assign { } { }
118057     assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
118058     sync always
118059     sync init
118060       update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
118061   end
118062   attribute \src "ls180.v:1825.12-1825.93"
118063   process $proc$ls180.v:1825$3561
118064     assign { } { }
118065     assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
118066     sync always
118067     sync init
118068       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
118069   end
118070   attribute \src "ls180.v:1826.5-1826.88"
118071   process $proc$ls180.v:1826$3562
118072     assign { } { }
118073     assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
118074     sync always
118075     sync init
118076       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
118077   end
118078   attribute \src "ls180.v:1827.12-1827.93"
118079   process $proc$ls180.v:1827$3563
118080     assign { } { }
118081     assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
118082     sync always
118083     sync init
118084       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
118085   end
118086   attribute \src "ls180.v:1828.5-1828.88"
118087   process $proc$ls180.v:1828$3564
118088     assign { } { }
118089     assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
118090     sync always
118091     sync init
118092       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
118093   end
118094   attribute \src "ls180.v:1829.12-1829.93"
118095   process $proc$ls180.v:1829$3565
118096     assign { } { }
118097     assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
118098     sync always
118099     sync init
118100       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
118101   end
118102   attribute \src "ls180.v:1830.5-1830.88"
118103   process $proc$ls180.v:1830$3566
118104     assign { } { }
118105     assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
118106     sync always
118107     sync init
118108       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
118109   end
118110   attribute \src "ls180.v:1831.12-1831.93"
118111   process $proc$ls180.v:1831$3567
118112     assign { } { }
118113     assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
118114     sync always
118115     sync init
118116       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
118117   end
118118   attribute \src "ls180.v:1832.5-1832.88"
118119   process $proc$ls180.v:1832$3568
118120     assign { } { }
118121     assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
118122     sync always
118123     sync init
118124       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
118125   end
118126   attribute \src "ls180.v:1833.11-1833.87"
118127   process $proc$ls180.v:1833$3569
118128     assign { } { }
118129     assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
118130     sync always
118131     sync init
118132       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
118133   end
118134   attribute \src "ls180.v:1834.5-1834.84"
118135   process $proc$ls180.v:1834$3570
118136     assign { } { }
118137     assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
118138     sync always
118139     sync init
118140       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
118141   end
118142   attribute \src "ls180.v:1835.11-1835.42"
118143   process $proc$ls180.v:1835$3571
118144     assign { } { }
118145     assign $1\builder_sdcore_fsm_state[2:0] 3'000
118146     sync always
118147     sync init
118148       update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0]
118149   end
118150   attribute \src "ls180.v:1836.11-1836.47"
118151   process $proc$ls180.v:1836$3572
118152     assign { } { }
118153     assign $1\builder_sdcore_fsm_next_state[2:0] 3'000
118154     sync always
118155     sync init
118156       update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0]
118157   end
118158   attribute \src "ls180.v:1837.5-1837.55"
118159   process $proc$ls180.v:1837$3573
118160     assign { } { }
118161     assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
118162     sync always
118163     sync init
118164       update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
118165   end
118166   attribute \src "ls180.v:1838.5-1838.58"
118167   process $proc$ls180.v:1838$3574
118168     assign { } { }
118169     assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
118170     sync always
118171     sync init
118172       update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
118173   end
118174   attribute \src "ls180.v:1839.5-1839.56"
118175   process $proc$ls180.v:1839$3575
118176     assign { } { }
118177     assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
118178     sync always
118179     sync init
118180       update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
118181   end
118182   attribute \src "ls180.v:184.5-184.62"
118183   process $proc$ls180.v:184$2810
118184     assign { } { }
118185     assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
118186     sync always
118187     sync init
118188       update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
118189   end
118190   attribute \src "ls180.v:1840.5-1840.59"
118191   process $proc$ls180.v:1840$3576
118192     assign { } { }
118193     assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
118194     sync always
118195     sync init
118196       update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
118197   end
118198   attribute \src "ls180.v:1841.11-1841.62"
118199   process $proc$ls180.v:1841$3577
118200     assign { } { }
118201     assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
118202     sync always
118203     sync init
118204       update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
118205   end
118206   attribute \src "ls180.v:1842.5-1842.59"
118207   process $proc$ls180.v:1842$3578
118208     assign { } { }
118209     assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
118210     sync always
118211     sync init
118212       update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
118213   end
118214   attribute \src "ls180.v:1843.12-1843.65"
118215   process $proc$ls180.v:1843$3579
118216     assign { } { }
118217     assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
118218     sync always
118219     sync init
118220       update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
118221   end
118222   attribute \src "ls180.v:1844.5-1844.60"
118223   process $proc$ls180.v:1844$3580
118224     assign { } { }
118225     assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
118226     sync always
118227     sync init
118228       update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
118229   end
118230   attribute \src "ls180.v:1845.5-1845.56"
118231   process $proc$ls180.v:1845$3581
118232     assign { } { }
118233     assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
118234     sync always
118235     sync init
118236       update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
118237   end
118238   attribute \src "ls180.v:1846.5-1846.59"
118239   process $proc$ls180.v:1846$3582
118240     assign { } { }
118241     assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
118242     sync always
118243     sync init
118244       update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
118245   end
118246   attribute \src "ls180.v:1847.5-1847.58"
118247   process $proc$ls180.v:1847$3583
118248     assign { } { }
118249     assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
118250     sync always
118251     sync init
118252       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
118253   end
118254   attribute \src "ls180.v:1848.5-1848.61"
118255   process $proc$ls180.v:1848$3584
118256     assign { } { }
118257     assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
118258     sync always
118259     sync init
118260       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
118261   end
118262   attribute \src "ls180.v:1849.5-1849.57"
118263   process $proc$ls180.v:1849$3585
118264     assign { } { }
118265     assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
118266     sync always
118267     sync init
118268       update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
118269   end
118270   attribute \src "ls180.v:185.11-185.69"
118271   process $proc$ls180.v:185$2811
118272     assign { } { }
118273     assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
118274     sync always
118275       update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0]
118276     sync init
118277   end
118278   attribute \src "ls180.v:1850.5-1850.60"
118279   process $proc$ls180.v:1850$3586
118280     assign { } { }
118281     assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
118282     sync always
118283     sync init
118284       update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
118285   end
118286   attribute \src "ls180.v:1851.5-1851.59"
118287   process $proc$ls180.v:1851$3587
118288     assign { } { }
118289     assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
118290     sync always
118291     sync init
118292       update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
118293   end
118294   attribute \src "ls180.v:1852.5-1852.62"
118295   process $proc$ls180.v:1852$3588
118296     assign { } { }
118297     assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
118298     sync always
118299     sync init
118300       update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
118301   end
118302   attribute \src "ls180.v:1853.13-1853.76"
118303   process $proc$ls180.v:1853$3589
118304     assign { } { }
118305     assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
118306     sync always
118307     sync init
118308       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
118309   end
118310   attribute \src "ls180.v:1854.5-1854.69"
118311   process $proc$ls180.v:1854$3590
118312     assign { } { }
118313     assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
118314     sync always
118315     sync init
118316       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
118317   end
118318   attribute \src "ls180.v:1855.11-1855.46"
118319   process $proc$ls180.v:1855$3591
118320     assign { } { }
118321     assign $1\builder_sdblock2memdma_state[1:0] 2'00
118322     sync always
118323     sync init
118324       update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0]
118325   end
118326   attribute \src "ls180.v:1856.11-1856.51"
118327   process $proc$ls180.v:1856$3592
118328     assign { } { }
118329     assign $1\builder_sdblock2memdma_next_state[1:0] 2'00
118330     sync always
118331     sync init
118332       update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0]
118333   end
118334   attribute \src "ls180.v:1857.12-1857.87"
118335   process $proc$ls180.v:1857$3593
118336     assign { } { }
118337     assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
118338     sync always
118339     sync init
118340       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
118341   end
118342   attribute \src "ls180.v:1858.5-1858.82"
118343   process $proc$ls180.v:1858$3594
118344     assign { } { }
118345     assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
118346     sync always
118347     sync init
118348       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
118349   end
118350   attribute \src "ls180.v:1859.5-1859.44"
118351   process $proc$ls180.v:1859$3595
118352     assign { } { }
118353     assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0
118354     sync always
118355     sync init
118356       update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0]
118357   end
118358   attribute \src "ls180.v:186.11-186.69"
118359   process $proc$ls180.v:186$2812
118360     assign { } { }
118361     assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
118362     sync always
118363       update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0]
118364     sync init
118365   end
118366   attribute \src "ls180.v:1860.5-1860.49"
118367   process $proc$ls180.v:1860$3596
118368     assign { } { }
118369     assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
118370     sync always
118371     sync init
118372       update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0]
118373   end
118374   attribute \src "ls180.v:1861.12-1861.75"
118375   process $proc$ls180.v:1861$3597
118376     assign { } { }
118377     assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
118378     sync always
118379     sync init
118380       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
118381   end
118382   attribute \src "ls180.v:1862.5-1862.70"
118383   process $proc$ls180.v:1862$3598
118384     assign { } { }
118385     assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
118386     sync always
118387     sync init
118388       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
118389   end
118390   attribute \src "ls180.v:1863.11-1863.60"
118391   process $proc$ls180.v:1863$3599
118392     assign { } { }
118393     assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
118394     sync always
118395     sync init
118396       update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0]
118397   end
118398   attribute \src "ls180.v:1864.11-1864.65"
118399   process $proc$ls180.v:1864$3600
118400     assign { } { }
118401     assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00
118402     sync always
118403     sync init
118404       update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
118405   end
118406   attribute \src "ls180.v:1865.12-1865.87"
118407   process $proc$ls180.v:1865$3601
118408     assign { } { }
118409     assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
118410     sync always
118411     sync init
118412       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
118413   end
118414   attribute \src "ls180.v:1866.5-1866.82"
118415   process $proc$ls180.v:1866$3602
118416     assign { } { }
118417     assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
118418     sync always
118419     sync init
118420       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
118421   end
118422   attribute \src "ls180.v:1867.12-1867.43"
118423   process $proc$ls180.v:1867$3603
118424     assign { } { }
118425     assign $1\builder_libresocsim_adr[13:0] 14'00000000000000
118426     sync always
118427     sync init
118428       update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0]
118429   end
118430   attribute \src "ls180.v:1868.5-1868.34"
118431   process $proc$ls180.v:1868$3604
118432     assign { } { }
118433     assign $1\builder_libresocsim_we[0:0] 1'0
118434     sync always
118435     sync init
118436       update \builder_libresocsim_we $1\builder_libresocsim_we[0:0]
118437   end
118438   attribute \src "ls180.v:1869.11-1869.43"
118439   process $proc$ls180.v:1869$3605
118440     assign { } { }
118441     assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
118442     sync always
118443     sync init
118444       update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
118445   end
118446   attribute \src "ls180.v:1873.12-1873.54"
118447   process $proc$ls180.v:1873$3606
118448     assign { } { }
118449     assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
118450     sync always
118451     sync init
118452       update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
118453   end
118454   attribute \src "ls180.v:1877.5-1877.44"
118455   process $proc$ls180.v:1877$3607
118456     assign { } { }
118457     assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
118458     sync always
118459     sync init
118460       update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
118461   end
118462   attribute \src "ls180.v:188.5-188.44"
118463   process $proc$ls180.v:188$2813
118464     assign { } { }
118465     assign $1\main_libresocsim_converter1_skip[0:0] 1'0
118466     sync always
118467     sync init
118468       update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
118469   end
118470   attribute \src "ls180.v:1881.5-1881.44"
118471   process $proc$ls180.v:1881$3608
118472     assign { } { }
118473     assign $0\builder_libresocsim_wishbone_err[0:0] 1'0
118474     sync always
118475       update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0]
118476     sync init
118477   end
118478   attribute \src "ls180.v:1884.12-1884.40"
118479   process $proc$ls180.v:1884$3609
118480     assign { } { }
118481     assign $1\builder_shared_dat_r[31:0] 0
118482     sync always
118483     sync init
118484       update \builder_shared_dat_r $1\builder_shared_dat_r[31:0]
118485   end
118486   attribute \src "ls180.v:1888.5-1888.30"
118487   process $proc$ls180.v:1888$3610
118488     assign { } { }
118489     assign $1\builder_shared_ack[0:0] 1'0
118490     sync always
118491     sync init
118492       update \builder_shared_ack $1\builder_shared_ack[0:0]
118493   end
118494   attribute \src "ls180.v:189.5-189.47"
118495   process $proc$ls180.v:189$2814
118496     assign { } { }
118497     assign $1\main_libresocsim_converter1_counter[0:0] 1'0
118498     sync always
118499     sync init
118500       update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
118501   end
118502   attribute \src "ls180.v:1894.11-1894.31"
118503   process $proc$ls180.v:1894$3611
118504     assign { } { }
118505     assign $1\builder_grant[2:0] 3'000
118506     sync always
118507     sync init
118508       update \builder_grant $1\builder_grant[2:0]
118509   end
118510   attribute \src "ls180.v:1895.11-1895.35"
118511   process $proc$ls180.v:1895$3612
118512     assign { } { }
118513     assign $1\builder_slave_sel[4:0] 5'00000
118514     sync always
118515     sync init
118516       update \builder_slave_sel $1\builder_slave_sel[4:0]
118517   end
118518   attribute \src "ls180.v:1896.11-1896.37"
118519   process $proc$ls180.v:1896$3613
118520     assign { } { }
118521     assign $1\builder_slave_sel_r[4:0] 5'00000
118522     sync always
118523     sync init
118524       update \builder_slave_sel_r $1\builder_slave_sel_r[4:0]
118525   end
118526   attribute \src "ls180.v:1897.5-1897.25"
118527   process $proc$ls180.v:1897$3614
118528     assign { } { }
118529     assign $1\builder_error[0:0] 1'0
118530     sync always
118531     sync init
118532       update \builder_error $1\builder_error[0:0]
118533   end
118534   attribute \src "ls180.v:1900.12-1900.39"
118535   process $proc$ls180.v:1900$3615
118536     assign { } { }
118537     assign $1\builder_count[19:0] 20'11110100001001000000
118538     sync always
118539     sync init
118540       update \builder_count $1\builder_count[19:0]
118541   end
118542   attribute \src "ls180.v:1904.11-1904.51"
118543   process $proc$ls180.v:1904$3616
118544     assign { } { }
118545     assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
118546     sync always
118547     sync init
118548       update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0]
118549   end
118550   attribute \src "ls180.v:191.12-191.53"
118551   process $proc$ls180.v:191$2815
118552     assign { } { }
118553     assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
118554     sync always
118555     sync init
118556       update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
118557   end
118558   attribute \src "ls180.v:192.12-192.71"
118559   process $proc$ls180.v:192$2816
118560     assign { } { }
118561     assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
118562     sync always
118563     sync init
118564       update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
118565   end
118566   attribute \src "ls180.v:193.12-193.73"
118567   process $proc$ls180.v:193$2817
118568     assign { } { }
118569     assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
118570     sync always
118571     sync init
118572       update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
118573   end
118574   attribute \src "ls180.v:1945.11-1945.51"
118575   process $proc$ls180.v:1945$3617
118576     assign { } { }
118577     assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
118578     sync always
118579     sync init
118580       update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
118581   end
118582   attribute \src "ls180.v:195.11-195.69"
118583   process $proc$ls180.v:195$2818
118584     assign { } { }
118585     assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
118586     sync always
118587     sync init
118588       update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
118589   end
118590   attribute \src "ls180.v:196.5-196.63"
118591   process $proc$ls180.v:196$2819
118592     assign { } { }
118593     assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
118594     sync always
118595     sync init
118596       update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
118597   end
118598   attribute \src "ls180.v:197.5-197.63"
118599   process $proc$ls180.v:197$2820
118600     assign { } { }
118601     assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
118602     sync always
118603     sync init
118604       update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
118605   end
118606   attribute \src "ls180.v:1974.11-1974.51"
118607   process $proc$ls180.v:1974$3618
118608     assign { } { }
118609     assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
118610     sync always
118611     sync init
118612       update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
118613   end
118614   attribute \src "ls180.v:1987.11-1987.51"
118615   process $proc$ls180.v:1987$3619
118616     assign { } { }
118617     assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
118618     sync always
118619     sync init
118620       update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
118621   end
118622   attribute \src "ls180.v:199.5-199.62"
118623   process $proc$ls180.v:199$2821
118624     assign { } { }
118625     assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
118626     sync always
118627     sync init
118628       update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0]
118629   end
118630   attribute \src "ls180.v:200.11-200.69"
118631   process $proc$ls180.v:200$2822
118632     assign { } { }
118633     assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000
118634     sync always
118635       update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0]
118636     sync init
118637   end
118638   attribute \src "ls180.v:201.11-201.69"
118639   process $proc$ls180.v:201$2823
118640     assign { } { }
118641     assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00
118642     sync always
118643       update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0]
118644     sync init
118645   end
118646   attribute \src "ls180.v:2028.11-2028.51"
118647   process $proc$ls180.v:2028$3620
118648     assign { } { }
118649     assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
118650     sync always
118651     sync init
118652       update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
118653   end
118654   attribute \src "ls180.v:203.5-203.44"
118655   process $proc$ls180.v:203$2824
118656     assign { } { }
118657     assign $1\main_libresocsim_converter2_skip[0:0] 1'0
118658     sync always
118659     sync init
118660       update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0]
118661   end
118662   attribute \src "ls180.v:204.5-204.47"
118663   process $proc$ls180.v:204$2825
118664     assign { } { }
118665     assign $1\main_libresocsim_converter2_counter[0:0] 1'0
118666     sync always
118667     sync init
118668       update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0]
118669   end
118670   attribute \src "ls180.v:206.12-206.53"
118671   process $proc$ls180.v:206$2826
118672     assign { } { }
118673     assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
118674     sync always
118675     sync init
118676       update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0]
118677   end
118678   attribute \src "ls180.v:2069.11-2069.51"
118679   process $proc$ls180.v:2069$3621
118680     assign { } { }
118681     assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
118682     sync always
118683     sync init
118684       update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
118685   end
118686   attribute \src "ls180.v:213.5-213.40"
118687   process $proc$ls180.v:213$2827
118688     assign { } { }
118689     assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
118690     sync always
118691     sync init
118692       update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
118693   end
118694   attribute \src "ls180.v:2134.11-2134.51"
118695   process $proc$ls180.v:2134$3622
118696     assign { } { }
118697     assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
118698     sync always
118699     sync init
118700       update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
118701   end
118702   attribute \src "ls180.v:217.5-217.40"
118703   process $proc$ls180.v:217$2828
118704     assign { } { }
118705     assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
118706     sync always
118707       update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0]
118708     sync init
118709   end
118710   attribute \src "ls180.v:220.11-220.37"
118711   process $proc$ls180.v:220$2829
118712     assign { } { }
118713     assign $1\main_libresocsim_we[3:0] 4'0000
118714     sync always
118715     sync init
118716       update \main_libresocsim_we $1\main_libresocsim_we[3:0]
118717   end
118718   attribute \src "ls180.v:222.12-222.49"
118719   process $proc$ls180.v:222$2830
118720     assign { } { }
118721     assign $1\main_libresocsim_load_storage[31:0] 0
118722     sync always
118723     sync init
118724       update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
118725   end
118726   attribute \src "ls180.v:223.5-223.36"
118727   process $proc$ls180.v:223$2831
118728     assign { } { }
118729     assign $1\main_libresocsim_load_re[0:0] 1'0
118730     sync always
118731     sync init
118732       update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0]
118733   end
118734   attribute \src "ls180.v:224.12-224.51"
118735   process $proc$ls180.v:224$2832
118736     assign { } { }
118737     assign $1\main_libresocsim_reload_storage[31:0] 0
118738     sync always
118739     sync init
118740       update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0]
118741   end
118742   attribute \src "ls180.v:225.5-225.38"
118743   process $proc$ls180.v:225$2833
118744     assign { } { }
118745     assign $1\main_libresocsim_reload_re[0:0] 1'0
118746     sync always
118747     sync init
118748       update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
118749   end
118750   attribute \src "ls180.v:226.5-226.39"
118751   process $proc$ls180.v:226$2834
118752     assign { } { }
118753     assign $1\main_libresocsim_en_storage[0:0] 1'0
118754     sync always
118755     sync init
118756       update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0]
118757   end
118758   attribute \src "ls180.v:2267.11-2267.51"
118759   process $proc$ls180.v:2267$3623
118760     assign { } { }
118761     assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
118762     sync always
118763     sync init
118764       update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
118765   end
118766   attribute \src "ls180.v:227.5-227.34"
118767   process $proc$ls180.v:227$2835
118768     assign { } { }
118769     assign $1\main_libresocsim_en_re[0:0] 1'0
118770     sync always
118771     sync init
118772       update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0]
118773   end
118774   attribute \src "ls180.v:228.5-228.49"
118775   process $proc$ls180.v:228$2836
118776     assign { } { }
118777     assign $1\main_libresocsim_update_value_storage[0:0] 1'0
118778     sync always
118779     sync init
118780       update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0]
118781   end
118782   attribute \src "ls180.v:229.5-229.44"
118783   process $proc$ls180.v:229$2837
118784     assign { } { }
118785     assign $1\main_libresocsim_update_value_re[0:0] 1'0
118786     sync always
118787     sync init
118788       update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
118789   end
118790   attribute \src "ls180.v:230.12-230.49"
118791   process $proc$ls180.v:230$2838
118792     assign { } { }
118793     assign $1\main_libresocsim_value_status[31:0] 0
118794     sync always
118795     sync init
118796       update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0]
118797   end
118798   attribute \src "ls180.v:234.5-234.41"
118799   process $proc$ls180.v:234$2839
118800     assign { } { }
118801     assign $1\main_libresocsim_zero_pending[0:0] 1'0
118802     sync always
118803     sync init
118804       update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
118805   end
118806   attribute \src "ls180.v:2348.11-2348.51"
118807   process $proc$ls180.v:2348$3624
118808     assign { } { }
118809     assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
118810     sync always
118811     sync init
118812       update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
118813   end
118814   attribute \src "ls180.v:236.5-236.39"
118815   process $proc$ls180.v:236$2840
118816     assign { } { }
118817     assign $1\main_libresocsim_zero_clear[0:0] 1'0
118818     sync always
118819     sync init
118820       update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0]
118821   end
118822   attribute \src "ls180.v:2365.11-2365.51"
118823   process $proc$ls180.v:2365$3625
118824     assign { } { }
118825     assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
118826     sync always
118827     sync init
118828       update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
118829   end
118830   attribute \src "ls180.v:237.5-237.45"
118831   process $proc$ls180.v:237$2841
118832     assign { } { }
118833     assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
118834     sync always
118835     sync init
118836       update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
118837   end
118838   attribute \src "ls180.v:2406.11-2406.52"
118839   process $proc$ls180.v:2406$3626
118840     assign { } { }
118841     assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
118842     sync always
118843     sync init
118844       update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
118845   end
118846   attribute \src "ls180.v:2439.11-2439.52"
118847   process $proc$ls180.v:2439$3627
118848     assign { } { }
118849     assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
118850     sync always
118851     sync init
118852       update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
118853   end
118854   attribute \src "ls180.v:246.5-246.49"
118855   process $proc$ls180.v:246$2842
118856     assign { } { }
118857     assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0
118858     sync always
118859     sync init
118860       update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0]
118861   end
118862   attribute \src "ls180.v:247.5-247.44"
118863   process $proc$ls180.v:247$2843
118864     assign { } { }
118865     assign $1\main_libresocsim_eventmanager_re[0:0] 1'0
118866     sync always
118867     sync init
118868       update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0]
118869   end
118870   attribute \src "ls180.v:248.12-248.42"
118871   process $proc$ls180.v:248$2844
118872     assign { } { }
118873     assign $1\main_libresocsim_value[31:0] 0
118874     sync always
118875     sync init
118876       update \main_libresocsim_value $1\main_libresocsim_value[31:0]
118877   end
118878   attribute \src "ls180.v:2480.11-2480.52"
118879   process $proc$ls180.v:2480$3628
118880     assign { } { }
118881     assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
118882     sync always
118883     sync init
118884       update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
118885   end
118886   attribute \src "ls180.v:252.5-252.24"
118887   process $proc$ls180.v:252$2845
118888     assign { } { }
118889     assign $1\main_int_rst[0:0] 1'1
118890     sync always
118891     sync init
118892       update \main_int_rst $1\main_int_rst[0:0]
118893   end
118894   attribute \src "ls180.v:2545.11-2545.52"
118895   process $proc$ls180.v:2545$3629
118896     assign { } { }
118897     assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
118898     sync always
118899     sync init
118900       update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0]
118901   end
118902   attribute \src "ls180.v:2570.11-2570.52"
118903   process $proc$ls180.v:2570$3630
118904     assign { } { }
118905     assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
118906     sync always
118907     sync init
118908       update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0]
118909   end
118910   attribute \src "ls180.v:2592.11-2592.31"
118911   process $proc$ls180.v:2592$3631
118912     assign { } { }
118913     assign $1\builder_state[1:0] 2'00
118914     sync always
118915     sync init
118916       update \builder_state $1\builder_state[1:0]
118917   end
118918   attribute \src "ls180.v:2593.11-2593.36"
118919   process $proc$ls180.v:2593$3632
118920     assign { } { }
118921     assign $1\builder_next_state[1:0] 2'00
118922     sync always
118923     sync init
118924       update \builder_next_state $1\builder_next_state[1:0]
118925   end
118926   attribute \src "ls180.v:2594.11-2594.55"
118927   process $proc$ls180.v:2594$3633
118928     assign { } { }
118929     assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
118930     sync always
118931     sync init
118932       update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0]
118933   end
118934   attribute \src "ls180.v:2595.5-2595.52"
118935   process $proc$ls180.v:2595$3634
118936     assign { } { }
118937     assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
118938     sync always
118939     sync init
118940       update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
118941   end
118942   attribute \src "ls180.v:2596.12-2596.55"
118943   process $proc$ls180.v:2596$3635
118944     assign { } { }
118945     assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
118946     sync always
118947     sync init
118948       update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0]
118949   end
118950   attribute \src "ls180.v:2597.5-2597.50"
118951   process $proc$ls180.v:2597$3636
118952     assign { } { }
118953     assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
118954     sync always
118955     sync init
118956       update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0]
118957   end
118958   attribute \src "ls180.v:2598.5-2598.46"
118959   process $proc$ls180.v:2598$3637
118960     assign { } { }
118961     assign $1\builder_libresocsim_we_next_value2[0:0] 1'0
118962     sync always
118963     sync init
118964       update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0]
118965   end
118966   attribute \src "ls180.v:2599.5-2599.49"
118967   process $proc$ls180.v:2599$3638
118968     assign { } { }
118969     assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0
118970     sync always
118971     sync init
118972       update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0]
118973   end
118974   attribute \src "ls180.v:2600.5-2600.41"
118975   process $proc$ls180.v:2600$3639
118976     assign { } { }
118977     assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0
118978     sync always
118979     sync init
118980       update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0]
118981   end
118982   attribute \src "ls180.v:2601.12-2601.49"
118983   process $proc$ls180.v:2601$3640
118984     assign { } { }
118985     assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
118986     sync always
118987     sync init
118988       update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0]
118989   end
118990   attribute \src "ls180.v:2602.11-2602.47"
118991   process $proc$ls180.v:2602$3641
118992     assign { } { }
118993     assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00
118994     sync always
118995     sync init
118996       update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0]
118997   end
118998   attribute \src "ls180.v:2603.5-2603.41"
118999   process $proc$ls180.v:2603$3642
119000     assign { } { }
119001     assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0
119002     sync always
119003     sync init
119004       update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0]
119005   end
119006   attribute \src "ls180.v:2604.5-2604.41"
119007   process $proc$ls180.v:2604$3643
119008     assign { } { }
119009     assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0
119010     sync always
119011     sync init
119012       update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0]
119013   end
119014   attribute \src "ls180.v:2605.5-2605.41"
119015   process $proc$ls180.v:2605$3644
119016     assign { } { }
119017     assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0
119018     sync always
119019     sync init
119020       update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0]
119021   end
119022   attribute \src "ls180.v:2606.5-2606.39"
119023   process $proc$ls180.v:2606$3645
119024     assign { } { }
119025     assign $1\builder_comb_t_array_muxed0[0:0] 1'0
119026     sync always
119027     sync init
119028       update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0]
119029   end
119030   attribute \src "ls180.v:2607.5-2607.39"
119031   process $proc$ls180.v:2607$3646
119032     assign { } { }
119033     assign $1\builder_comb_t_array_muxed1[0:0] 1'0
119034     sync always
119035     sync init
119036       update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0]
119037   end
119038   attribute \src "ls180.v:2608.5-2608.39"
119039   process $proc$ls180.v:2608$3647
119040     assign { } { }
119041     assign $1\builder_comb_t_array_muxed2[0:0] 1'0
119042     sync always
119043     sync init
119044       update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0]
119045   end
119046   attribute \src "ls180.v:2609.5-2609.41"
119047   process $proc$ls180.v:2609$3648
119048     assign { } { }
119049     assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0
119050     sync always
119051     sync init
119052       update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0]
119053   end
119054   attribute \src "ls180.v:2610.12-2610.49"
119055   process $proc$ls180.v:2610$3649
119056     assign { } { }
119057     assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
119058     sync always
119059     sync init
119060       update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0]
119061   end
119062   attribute \src "ls180.v:2611.11-2611.47"
119063   process $proc$ls180.v:2611$3650
119064     assign { } { }
119065     assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00
119066     sync always
119067     sync init
119068       update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0]
119069   end
119070   attribute \src "ls180.v:2612.5-2612.41"
119071   process $proc$ls180.v:2612$3651
119072     assign { } { }
119073     assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0
119074     sync always
119075     sync init
119076       update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0]
119077   end
119078   attribute \src "ls180.v:2613.5-2613.42"
119079   process $proc$ls180.v:2613$3652
119080     assign { } { }
119081     assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0
119082     sync always
119083     sync init
119084       update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0]
119085   end
119086   attribute \src "ls180.v:2614.5-2614.42"
119087   process $proc$ls180.v:2614$3653
119088     assign { } { }
119089     assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0
119090     sync always
119091     sync init
119092       update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0]
119093   end
119094   attribute \src "ls180.v:2615.5-2615.39"
119095   process $proc$ls180.v:2615$3654
119096     assign { } { }
119097     assign $1\builder_comb_t_array_muxed3[0:0] 1'0
119098     sync always
119099     sync init
119100       update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0]
119101   end
119102   attribute \src "ls180.v:2616.5-2616.39"
119103   process $proc$ls180.v:2616$3655
119104     assign { } { }
119105     assign $1\builder_comb_t_array_muxed4[0:0] 1'0
119106     sync always
119107     sync init
119108       update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0]
119109   end
119110   attribute \src "ls180.v:2617.5-2617.39"
119111   process $proc$ls180.v:2617$3656
119112     assign { } { }
119113     assign $1\builder_comb_t_array_muxed5[0:0] 1'0
119114     sync always
119115     sync init
119116       update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0]
119117   end
119118   attribute \src "ls180.v:2618.12-2618.50"
119119   process $proc$ls180.v:2618$3657
119120     assign { } { }
119121     assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
119122     sync always
119123     sync init
119124       update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0]
119125   end
119126   attribute \src "ls180.v:2619.5-2619.42"
119127   process $proc$ls180.v:2619$3658
119128     assign { } { }
119129     assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0
119130     sync always
119131     sync init
119132       update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0]
119133   end
119134   attribute \src "ls180.v:2620.5-2620.42"
119135   process $proc$ls180.v:2620$3659
119136     assign { } { }
119137     assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0
119138     sync always
119139     sync init
119140       update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0]
119141   end
119142   attribute \src "ls180.v:2621.12-2621.50"
119143   process $proc$ls180.v:2621$3660
119144     assign { } { }
119145     assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
119146     sync always
119147     sync init
119148       update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0]
119149   end
119150   attribute \src "ls180.v:2622.5-2622.42"
119151   process $proc$ls180.v:2622$3661
119152     assign { } { }
119153     assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0
119154     sync always
119155     sync init
119156       update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0]
119157   end
119158   attribute \src "ls180.v:2623.5-2623.42"
119159   process $proc$ls180.v:2623$3662
119160     assign { } { }
119161     assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0
119162     sync always
119163     sync init
119164       update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0]
119165   end
119166   attribute \src "ls180.v:2624.12-2624.50"
119167   process $proc$ls180.v:2624$3663
119168     assign { } { }
119169     assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
119170     sync always
119171     sync init
119172       update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0]
119173   end
119174   attribute \src "ls180.v:2625.5-2625.42"
119175   process $proc$ls180.v:2625$3664
119176     assign { } { }
119177     assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0
119178     sync always
119179     sync init
119180       update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0]
119181   end
119182   attribute \src "ls180.v:2626.5-2626.42"
119183   process $proc$ls180.v:2626$3665
119184     assign { } { }
119185     assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0
119186     sync always
119187     sync init
119188       update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0]
119189   end
119190   attribute \src "ls180.v:2627.12-2627.50"
119191   process $proc$ls180.v:2627$3666
119192     assign { } { }
119193     assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
119194     sync always
119195     sync init
119196       update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0]
119197   end
119198   attribute \src "ls180.v:2628.5-2628.42"
119199   process $proc$ls180.v:2628$3667
119200     assign { } { }
119201     assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0
119202     sync always
119203     sync init
119204       update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0]
119205   end
119206   attribute \src "ls180.v:2629.5-2629.42"
119207   process $proc$ls180.v:2629$3668
119208     assign { } { }
119209     assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0
119210     sync always
119211     sync init
119212       update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0]
119213   end
119214   attribute \src "ls180.v:2630.12-2630.50"
119215   process $proc$ls180.v:2630$3669
119216     assign { } { }
119217     assign $1\builder_comb_rhs_array_muxed24[31:0] 0
119218     sync always
119219     sync init
119220       update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0]
119221   end
119222   attribute \src "ls180.v:2631.12-2631.50"
119223   process $proc$ls180.v:2631$3670
119224     assign { } { }
119225     assign $1\builder_comb_rhs_array_muxed25[31:0] 0
119226     sync always
119227     sync init
119228       update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0]
119229   end
119230   attribute \src "ls180.v:2632.11-2632.48"
119231   process $proc$ls180.v:2632$3671
119232     assign { } { }
119233     assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000
119234     sync always
119235     sync init
119236       update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0]
119237   end
119238   attribute \src "ls180.v:2633.5-2633.42"
119239   process $proc$ls180.v:2633$3672
119240     assign { } { }
119241     assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0
119242     sync always
119243     sync init
119244       update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0]
119245   end
119246   attribute \src "ls180.v:2634.5-2634.42"
119247   process $proc$ls180.v:2634$3673
119248     assign { } { }
119249     assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0
119250     sync always
119251     sync init
119252       update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0]
119253   end
119254   attribute \src "ls180.v:2635.5-2635.42"
119255   process $proc$ls180.v:2635$3674
119256     assign { } { }
119257     assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0
119258     sync always
119259     sync init
119260       update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0]
119261   end
119262   attribute \src "ls180.v:2636.11-2636.48"
119263   process $proc$ls180.v:2636$3675
119264     assign { } { }
119265     assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000
119266     sync always
119267     sync init
119268       update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0]
119269   end
119270   attribute \src "ls180.v:2637.11-2637.48"
119271   process $proc$ls180.v:2637$3676
119272     assign { } { }
119273     assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00
119274     sync always
119275     sync init
119276       update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0]
119277   end
119278   attribute \src "ls180.v:2638.11-2638.47"
119279   process $proc$ls180.v:2638$3677
119280     assign { } { }
119281     assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00
119282     sync always
119283     sync init
119284       update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0]
119285   end
119286   attribute \src "ls180.v:2639.12-2639.49"
119287   process $proc$ls180.v:2639$3678
119288     assign { } { }
119289     assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
119290     sync always
119291     sync init
119292       update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0]
119293   end
119294   attribute \src "ls180.v:2640.5-2640.41"
119295   process $proc$ls180.v:2640$3679
119296     assign { } { }
119297     assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0
119298     sync always
119299     sync init
119300       update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0]
119301   end
119302   attribute \src "ls180.v:2641.5-2641.41"
119303   process $proc$ls180.v:2641$3680
119304     assign { } { }
119305     assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0
119306     sync always
119307     sync init
119308       update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0]
119309   end
119310   attribute \src "ls180.v:2642.5-2642.41"
119311   process $proc$ls180.v:2642$3681
119312     assign { } { }
119313     assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0
119314     sync always
119315     sync init
119316       update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0]
119317   end
119318   attribute \src "ls180.v:2643.5-2643.41"
119319   process $proc$ls180.v:2643$3682
119320     assign { } { }
119321     assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0
119322     sync always
119323     sync init
119324       update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0]
119325   end
119326   attribute \src "ls180.v:2644.5-2644.41"
119327   process $proc$ls180.v:2644$3683
119328     assign { } { }
119329     assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0
119330     sync always
119331     sync init
119332       update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0]
119333   end
119334   attribute \src "ls180.v:2645.5-2645.39"
119335   process $proc$ls180.v:2645$3684
119336     assign { } { }
119337     assign $1\builder_sync_f_array_muxed0[0:0] 1'0
119338     sync always
119339     sync init
119340       update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0]
119341   end
119342   attribute \src "ls180.v:2646.5-2646.39"
119343   process $proc$ls180.v:2646$3685
119344     assign { } { }
119345     assign $1\builder_sync_f_array_muxed1[0:0] 1'0
119346     sync always
119347     sync init
119348       update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0]
119349   end
119350   attribute \src "ls180.v:267.12-267.38"
119351   process $proc$ls180.v:267$2846
119352     assign { } { }
119353     assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
119354     sync always
119355     sync init
119356       update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
119357   end
119358   attribute \src "ls180.v:268.5-268.36"
119359   process $proc$ls180.v:268$2847
119360     assign { } { }
119361     assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
119362     sync always
119363     sync init
119364       update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
119365   end
119366   attribute \src "ls180.v:269.11-269.32"
119367   process $proc$ls180.v:269$2848
119368     assign { } { }
119369     assign $1\main_rddata_en[2:0] 3'000
119370     sync always
119371     sync init
119372       update \main_rddata_en $1\main_rddata_en[2:0]
119373   end
119374   attribute \src "ls180.v:2703.32-2703.66"
119375   process $proc$ls180.v:2703$3686
119376     assign { } { }
119377     assign $1\builder_multiregimpl0_regs0[0:0] 1'0
119378     sync always
119379     sync init
119380       update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0]
119381   end
119382   attribute \src "ls180.v:2704.32-2704.66"
119383   process $proc$ls180.v:2704$3687
119384     assign { } { }
119385     assign $1\builder_multiregimpl0_regs1[0:0] 1'0
119386     sync always
119387     sync init
119388       update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0]
119389   end
119390   attribute \src "ls180.v:2705.32-2705.66"
119391   process $proc$ls180.v:2705$3688
119392     assign { } { }
119393     assign $1\builder_multiregimpl1_regs0[0:0] 1'0
119394     sync always
119395     sync init
119396       update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0]
119397   end
119398   attribute \src "ls180.v:2706.32-2706.66"
119399   process $proc$ls180.v:2706$3689
119400     assign { } { }
119401     assign $1\builder_multiregimpl1_regs1[0:0] 1'0
119402     sync always
119403     sync init
119404       update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0]
119405   end
119406   attribute \src "ls180.v:2707.32-2707.66"
119407   process $proc$ls180.v:2707$3690
119408     assign { } { }
119409     assign $1\builder_multiregimpl2_regs0[0:0] 1'0
119410     sync always
119411     sync init
119412       update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0]
119413   end
119414   attribute \src "ls180.v:2708.32-2708.66"
119415   process $proc$ls180.v:2708$3691
119416     assign { } { }
119417     assign $1\builder_multiregimpl2_regs1[0:0] 1'0
119418     sync always
119419     sync init
119420       update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0]
119421   end
119422   attribute \src "ls180.v:2709.32-2709.66"
119423   process $proc$ls180.v:2709$3692
119424     assign { } { }
119425     assign $1\builder_multiregimpl3_regs0[0:0] 1'0
119426     sync always
119427     sync init
119428       update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0]
119429   end
119430   attribute \src "ls180.v:2710.32-2710.66"
119431   process $proc$ls180.v:2710$3693
119432     assign { } { }
119433     assign $1\builder_multiregimpl3_regs1[0:0] 1'0
119434     sync always
119435     sync init
119436       update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0]
119437   end
119438   attribute \src "ls180.v:2711.32-2711.66"
119439   process $proc$ls180.v:2711$3694
119440     assign { } { }
119441     assign $1\builder_multiregimpl4_regs0[0:0] 1'0
119442     sync always
119443     sync init
119444       update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0]
119445   end
119446   attribute \src "ls180.v:2712.32-2712.66"
119447   process $proc$ls180.v:2712$3695
119448     assign { } { }
119449     assign $1\builder_multiregimpl4_regs1[0:0] 1'0
119450     sync always
119451     sync init
119452       update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0]
119453   end
119454   attribute \src "ls180.v:2713.32-2713.66"
119455   process $proc$ls180.v:2713$3696
119456     assign { } { }
119457     assign $1\builder_multiregimpl5_regs0[0:0] 1'0
119458     sync always
119459     sync init
119460       update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0]
119461   end
119462   attribute \src "ls180.v:2714.32-2714.66"
119463   process $proc$ls180.v:2714$3697
119464     assign { } { }
119465     assign $1\builder_multiregimpl5_regs1[0:0] 1'0
119466     sync always
119467     sync init
119468       update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0]
119469   end
119470   attribute \src "ls180.v:2715.32-2715.66"
119471   process $proc$ls180.v:2715$3698
119472     assign { } { }
119473     assign $1\builder_multiregimpl6_regs0[0:0] 1'0
119474     sync always
119475     sync init
119476       update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0]
119477   end
119478   attribute \src "ls180.v:2716.32-2716.66"
119479   process $proc$ls180.v:2716$3699
119480     assign { } { }
119481     assign $1\builder_multiregimpl6_regs1[0:0] 1'0
119482     sync always
119483     sync init
119484       update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0]
119485   end
119486   attribute \src "ls180.v:2717.32-2717.66"
119487   process $proc$ls180.v:2717$3700
119488     assign { } { }
119489     assign $1\builder_multiregimpl7_regs0[0:0] 1'0
119490     sync always
119491     sync init
119492       update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0]
119493   end
119494   attribute \src "ls180.v:2718.32-2718.66"
119495   process $proc$ls180.v:2718$3701
119496     assign { } { }
119497     assign $1\builder_multiregimpl7_regs1[0:0] 1'0
119498     sync always
119499     sync init
119500       update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0]
119501   end
119502   attribute \src "ls180.v:2719.32-2719.66"
119503   process $proc$ls180.v:2719$3702
119504     assign { } { }
119505     assign $1\builder_multiregimpl8_regs0[0:0] 1'0
119506     sync always
119507     sync init
119508       update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0]
119509   end
119510   attribute \src "ls180.v:272.5-272.36"
119511   process $proc$ls180.v:272$2849
119512     assign { } { }
119513     assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
119514     sync always
119515     sync init
119516       update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
119517   end
119518   attribute \src "ls180.v:2720.32-2720.66"
119519   process $proc$ls180.v:2720$3703
119520     assign { } { }
119521     assign $1\builder_multiregimpl8_regs1[0:0] 1'0
119522     sync always
119523     sync init
119524       update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0]
119525   end
119526   attribute \src "ls180.v:2721.32-2721.66"
119527   process $proc$ls180.v:2721$3704
119528     assign { } { }
119529     assign $1\builder_multiregimpl9_regs0[0:0] 1'0
119530     sync always
119531     sync init
119532       update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0]
119533   end
119534   attribute \src "ls180.v:2722.32-2722.66"
119535   process $proc$ls180.v:2722$3705
119536     assign { } { }
119537     assign $1\builder_multiregimpl9_regs1[0:0] 1'0
119538     sync always
119539     sync init
119540       update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0]
119541   end
119542   attribute \src "ls180.v:2723.32-2723.67"
119543   process $proc$ls180.v:2723$3706
119544     assign { } { }
119545     assign $1\builder_multiregimpl10_regs0[0:0] 1'0
119546     sync always
119547     sync init
119548       update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0]
119549   end
119550   attribute \src "ls180.v:2724.32-2724.67"
119551   process $proc$ls180.v:2724$3707
119552     assign { } { }
119553     assign $1\builder_multiregimpl10_regs1[0:0] 1'0
119554     sync always
119555     sync init
119556       update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0]
119557   end
119558   attribute \src "ls180.v:2725.32-2725.67"
119559   process $proc$ls180.v:2725$3708
119560     assign { } { }
119561     assign $1\builder_multiregimpl11_regs0[0:0] 1'0
119562     sync always
119563     sync init
119564       update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0]
119565   end
119566   attribute \src "ls180.v:2726.32-2726.67"
119567   process $proc$ls180.v:2726$3709
119568     assign { } { }
119569     assign $1\builder_multiregimpl11_regs1[0:0] 1'0
119570     sync always
119571     sync init
119572       update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0]
119573   end
119574   attribute \src "ls180.v:2727.32-2727.67"
119575   process $proc$ls180.v:2727$3710
119576     assign { } { }
119577     assign $1\builder_multiregimpl12_regs0[0:0] 1'0
119578     sync always
119579     sync init
119580       update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0]
119581   end
119582   attribute \src "ls180.v:2728.32-2728.67"
119583   process $proc$ls180.v:2728$3711
119584     assign { } { }
119585     assign $1\builder_multiregimpl12_regs1[0:0] 1'0
119586     sync always
119587     sync init
119588       update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0]
119589   end
119590   attribute \src "ls180.v:2729.32-2729.67"
119591   process $proc$ls180.v:2729$3712
119592     assign { } { }
119593     assign $1\builder_multiregimpl13_regs0[0:0] 1'0
119594     sync always
119595     sync init
119596       update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0]
119597   end
119598   attribute \src "ls180.v:273.5-273.35"
119599   process $proc$ls180.v:273$2850
119600     assign { } { }
119601     assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
119602     sync always
119603     sync init
119604       update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
119605   end
119606   attribute \src "ls180.v:2730.32-2730.67"
119607   process $proc$ls180.v:2730$3713
119608     assign { } { }
119609     assign $1\builder_multiregimpl13_regs1[0:0] 1'0
119610     sync always
119611     sync init
119612       update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0]
119613   end
119614   attribute \src "ls180.v:2731.32-2731.67"
119615   process $proc$ls180.v:2731$3714
119616     assign { } { }
119617     assign $1\builder_multiregimpl14_regs0[0:0] 1'0
119618     sync always
119619     sync init
119620       update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0]
119621   end
119622   attribute \src "ls180.v:2732.32-2732.67"
119623   process $proc$ls180.v:2732$3715
119624     assign { } { }
119625     assign $1\builder_multiregimpl14_regs1[0:0] 1'0
119626     sync always
119627     sync init
119628       update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0]
119629   end
119630   attribute \src "ls180.v:2733.32-2733.67"
119631   process $proc$ls180.v:2733$3716
119632     assign { } { }
119633     assign $1\builder_multiregimpl15_regs0[0:0] 1'0
119634     sync always
119635     sync init
119636       update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0]
119637   end
119638   attribute \src "ls180.v:2734.32-2734.67"
119639   process $proc$ls180.v:2734$3717
119640     assign { } { }
119641     assign $1\builder_multiregimpl15_regs1[0:0] 1'0
119642     sync always
119643     sync init
119644       update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0]
119645   end
119646   attribute \src "ls180.v:2735.32-2735.67"
119647   process $proc$ls180.v:2735$3718
119648     assign { } { }
119649     assign $1\builder_multiregimpl16_regs0[0:0] 1'0
119650     sync always
119651     sync init
119652       update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0]
119653   end
119654   attribute \src "ls180.v:2736.32-2736.67"
119655   process $proc$ls180.v:2736$3719
119656     assign { } { }
119657     assign $1\builder_multiregimpl16_regs1[0:0] 1'0
119658     sync always
119659     sync init
119660       update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0]
119661   end
119662   attribute \src "ls180.v:274.5-274.36"
119663   process $proc$ls180.v:274$2851
119664     assign { } { }
119665     assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
119666     sync always
119667     sync init
119668       update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
119669   end
119670   attribute \src "ls180.v:275.5-275.35"
119671   process $proc$ls180.v:275$2852
119672     assign { } { }
119673     assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
119674     sync always
119675     sync init
119676       update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0]
119677   end
119678   attribute \src "ls180.v:2771.1-2776.4"
119679   process $proc$ls180.v:2771$13
119680     assign { } { }
119681     assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000
119682     assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint }
119683     assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq
119684     assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq
119685     sync always
119686       update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0]
119687   end
119688   attribute \src "ls180.v:2778.1-2788.4"
119689   process $proc$ls180.v:2778$15
119690     assign { } { }
119691     assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
119692     attribute \src "ls180.v:2780.2-2787.9"
119693     switch \main_libresocsim_converter0_counter
119694       attribute \src "ls180.v:0.0-0.0"
119695       case 1'0
119696         assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0]
119697       attribute \src "ls180.v:0.0-0.0"
119698       case 1'1
119699         assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32]
119700       case
119701     end
119702     sync always
119703       update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
119704   end
119705   attribute \src "ls180.v:279.5-279.36"
119706   process $proc$ls180.v:279$2853
119707     assign { } { }
119708     assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
119709     sync always
119710       update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0]
119711     sync init
119712   end
119713   attribute \src "ls180.v:2790.1-2836.4"
119714   process $proc$ls180.v:2790$16
119715     assign { } { }
119716     assign { } { }
119717     assign { } { }
119718     assign { } { }
119719     assign { } { }
119720     assign { } { }
119721     assign { } { }
119722     assign { } { }
119723     assign { } { }
119724     assign { } { }
119725     assign { } { }
119726     assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
119727     assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
119728     assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
119729     assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
119730     assign $0\main_libresocsim_converter0_skip[0:0] 1'0
119731     assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
119732     assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
119733     assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
119734     assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
119735     assign $0\builder_converter0_next_state[0:0] \builder_converter0_state
119736     attribute \src "ls180.v:2802.2-2835.9"
119737     switch \builder_converter0_state
119738       attribute \src "ls180.v:0.0-0.0"
119739       case 1'1
119740         assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter }
119741         attribute \src "ls180.v:2805.4-2812.11"
119742         switch \main_libresocsim_converter0_counter
119743           attribute \src "ls180.v:0.0-0.0"
119744           case 1'0
119745             assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0]
119746           attribute \src "ls180.v:0.0-0.0"
119747           case 1'1
119748             assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4]
119749           case
119750         end
119751         attribute \src "ls180.v:2813.4-2826.7"
119752         switch $and$ls180.v:2813$17_Y
119753           attribute \src "ls180.v:2813.8-2813.81"
119754           case 1'1
119755             assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2814$18_Y
119756             assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we
119757             assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2816$19_Y
119758             assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2817$20_Y
119759             attribute \src "ls180.v:2818.5-2825.8"
119760             switch $or$ls180.v:2818$21_Y
119761               attribute \src "ls180.v:2818.9-2818.97"
119762               case 1'1
119763                 assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2819$22_Y
119764                 assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
119765                 attribute \src "ls180.v:2821.6-2824.9"
119766                 switch $eq$ls180.v:2821$23_Y
119767                   attribute \src "ls180.v:2821.10-2821.55"
119768                   case 1'1
119769                     assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1
119770                     assign $0\builder_converter0_next_state[0:0] 1'0
119771                   case
119772                 end
119773               case
119774             end
119775           case
119776         end
119777       attribute \src "ls180.v:0.0-0.0"
119778       case
119779         assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
119780         assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1
119781         attribute \src "ls180.v:2831.4-2833.7"
119782         switch $and$ls180.v:2831$24_Y
119783           attribute \src "ls180.v:2831.8-2831.81"
119784           case 1'1
119785             assign $0\builder_converter0_next_state[0:0] 1'1
119786           case
119787         end
119788     end
119789     sync always
119790       update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0]
119791       update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0]
119792       update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0]
119793       update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0]
119794       update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0]
119795       update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0]
119796       update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0]
119797       update \builder_converter0_next_state $0\builder_converter0_next_state[0:0]
119798       update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0]
119799       update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
119800   end
119801   attribute \src "ls180.v:2838.1-2848.4"
119802   process $proc$ls180.v:2838$26
119803     assign { } { }
119804     assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
119805     attribute \src "ls180.v:2840.2-2847.9"
119806     switch \main_libresocsim_converter1_counter
119807       attribute \src "ls180.v:0.0-0.0"
119808       case 1'0
119809         assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0]
119810       attribute \src "ls180.v:0.0-0.0"
119811       case 1'1
119812         assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32]
119813       case
119814     end
119815     sync always
119816       update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
119817   end
119818   attribute \src "ls180.v:284.12-284.45"
119819   process $proc$ls180.v:284$2854
119820     assign { } { }
119821     assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
119822     sync always
119823     sync init
119824       update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
119825   end
119826   attribute \src "ls180.v:285.5-285.43"
119827   process $proc$ls180.v:285$2855
119828     assign { } { }
119829     assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
119830     sync always
119831     sync init
119832       update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0]
119833   end
119834   attribute \src "ls180.v:2850.1-2896.4"
119835   process $proc$ls180.v:2850$27
119836     assign { } { }
119837     assign { } { }
119838     assign { } { }
119839     assign { } { }
119840     assign { } { }
119841     assign { } { }
119842     assign { } { }
119843     assign { } { }
119844     assign { } { }
119845     assign { } { }
119846     assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
119847     assign $0\main_libresocsim_converter1_skip[0:0] 1'0
119848     assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
119849     assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
119850     assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
119851     assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
119852     assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
119853     assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
119854     assign { } { }
119855     assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
119856     assign $0\builder_converter1_next_state[0:0] \builder_converter1_state
119857     attribute \src "ls180.v:2862.2-2895.9"
119858     switch \builder_converter1_state
119859       attribute \src "ls180.v:0.0-0.0"
119860       case 1'1
119861         assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter }
119862         attribute \src "ls180.v:2865.4-2872.11"
119863         switch \main_libresocsim_converter1_counter
119864           attribute \src "ls180.v:0.0-0.0"
119865           case 1'0
119866             assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0]
119867           attribute \src "ls180.v:0.0-0.0"
119868           case 1'1
119869             assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4]
119870           case
119871         end
119872         attribute \src "ls180.v:2873.4-2886.7"
119873         switch $and$ls180.v:2873$28_Y
119874           attribute \src "ls180.v:2873.8-2873.81"
119875           case 1'1
119876             assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2874$29_Y
119877             assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we
119878             assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2876$30_Y
119879             assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2877$31_Y
119880             attribute \src "ls180.v:2878.5-2885.8"
119881             switch $or$ls180.v:2878$32_Y
119882               attribute \src "ls180.v:2878.9-2878.97"
119883               case 1'1
119884                 assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2879$33_Y
119885                 assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
119886                 attribute \src "ls180.v:2881.6-2884.9"
119887                 switch $eq$ls180.v:2881$34_Y
119888                   attribute \src "ls180.v:2881.10-2881.55"
119889                   case 1'1
119890                     assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1
119891                     assign $0\builder_converter1_next_state[0:0] 1'0
119892                   case
119893                 end
119894               case
119895             end
119896           case
119897         end
119898       attribute \src "ls180.v:0.0-0.0"
119899       case
119900         assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
119901         assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1
119902         attribute \src "ls180.v:2891.4-2893.7"
119903         switch $and$ls180.v:2891$35_Y
119904           attribute \src "ls180.v:2891.8-2891.81"
119905           case 1'1
119906             assign $0\builder_converter1_next_state[0:0] 1'1
119907           case
119908         end
119909     end
119910     sync always
119911       update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0]
119912       update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0]
119913       update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0]
119914       update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0]
119915       update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0]
119916       update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0]
119917       update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0]
119918       update \builder_converter1_next_state $0\builder_converter1_next_state[0:0]
119919       update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0]
119920       update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
119921   end
119922   attribute \src "ls180.v:2898.1-2908.4"
119923   process $proc$ls180.v:2898$37
119924     assign { } { }
119925     assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
119926     attribute \src "ls180.v:2900.2-2907.9"
119927     switch \main_libresocsim_converter2_counter
119928       attribute \src "ls180.v:0.0-0.0"
119929       case 1'0
119930         assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0]
119931       attribute \src "ls180.v:0.0-0.0"
119932       case 1'1
119933         assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32]
119934       case
119935     end
119936     sync always
119937       update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0]
119938   end
119939   attribute \src "ls180.v:2910.1-2956.4"
119940   process $proc$ls180.v:2910$38
119941     assign { } { }
119942     assign { } { }
119943     assign { } { }
119944     assign { } { }
119945     assign { } { }
119946     assign { } { }
119947     assign { } { }
119948     assign { } { }
119949     assign { } { }
119950     assign { } { }
119951     assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
119952     assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0
119953     assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
119954     assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
119955     assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
119956     assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
119957     assign $0\main_libresocsim_converter2_skip[0:0] 1'0
119958     assign { } { }
119959     assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
119960     assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
119961     assign $0\builder_converter2_next_state[0:0] \builder_converter2_state
119962     attribute \src "ls180.v:2922.2-2955.9"
119963     switch \builder_converter2_state
119964       attribute \src "ls180.v:0.0-0.0"
119965       case 1'1
119966         assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter }
119967         attribute \src "ls180.v:2925.4-2932.11"
119968         switch \main_libresocsim_converter2_counter
119969           attribute \src "ls180.v:0.0-0.0"
119970           case 1'0
119971             assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0]
119972           attribute \src "ls180.v:0.0-0.0"
119973           case 1'1
119974             assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4]
119975           case
119976         end
119977         attribute \src "ls180.v:2933.4-2946.7"
119978         switch $and$ls180.v:2933$39_Y
119979           attribute \src "ls180.v:2933.8-2933.87"
119980           case 1'1
119981             assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2934$40_Y
119982             assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we
119983             assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2936$41_Y
119984             assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2937$42_Y
119985             attribute \src "ls180.v:2938.5-2945.8"
119986             switch $or$ls180.v:2938$43_Y
119987               attribute \src "ls180.v:2938.9-2938.97"
119988               case 1'1
119989                 assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2939$44_Y
119990                 assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
119991                 attribute \src "ls180.v:2941.6-2944.9"
119992                 switch $eq$ls180.v:2941$45_Y
119993                   attribute \src "ls180.v:2941.10-2941.55"
119994                   case 1'1
119995                     assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1
119996                     assign $0\builder_converter2_next_state[0:0] 1'0
119997                   case
119998                 end
119999               case
120000             end
120001           case
120002         end
120003       attribute \src "ls180.v:0.0-0.0"
120004       case
120005         assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
120006         assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1
120007         attribute \src "ls180.v:2951.4-2953.7"
120008         switch $and$ls180.v:2951$46_Y
120009           attribute \src "ls180.v:2951.8-2951.87"
120010           case 1'1
120011             assign $0\builder_converter2_next_state[0:0] 1'1
120012           case
120013         end
120014     end
120015     sync always
120016       update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0]
120017       update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0]
120018       update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0]
120019       update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0]
120020       update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0]
120021       update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0]
120022       update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0]
120023       update \builder_converter2_next_state $0\builder_converter2_next_state[0:0]
120024       update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0]
120025       update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
120026   end
120027   attribute \src "ls180.v:2959.1-2965.4"
120028   process $proc$ls180.v:2959$47
120029     assign { } { }
120030     assign { } { }
120031     assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2961$50_Y
120032     assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2962$53_Y
120033     assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2963$56_Y
120034     assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2964$59_Y
120035     sync always
120036       update \main_libresocsim_we $0\main_libresocsim_we[3:0]
120037   end
120038   attribute \src "ls180.v:2971.1-2976.4"
120039   process $proc$ls180.v:2971$61
120040     assign { } { }
120041     assign $0\main_libresocsim_zero_clear[0:0] 1'0
120042     attribute \src "ls180.v:2973.2-2975.5"
120043     switch $and$ls180.v:2973$62_Y
120044       attribute \src "ls180.v:2973.6-2973.90"
120045       case 1'1
120046         assign $0\main_libresocsim_zero_clear[0:0] 1'1
120047       case
120048     end
120049     sync always
120050       update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0]
120051   end
120052   attribute \src "ls180.v:300.12-300.46"
120053   process $proc$ls180.v:300$2856
120054     assign { } { }
120055     assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
120056     sync always
120057     sync init
120058       update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
120059   end
120060   attribute \src "ls180.v:301.5-301.44"
120061   process $proc$ls180.v:301$2857
120062     assign { } { }
120063     assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
120064     sync always
120065     sync init
120066       update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0]
120067   end
120068   attribute \src "ls180.v:3015.1-3069.4"
120069   process $proc$ls180.v:3015$64
120070     assign { } { }
120071     assign { } { }
120072     assign { } { }
120073     assign { } { }
120074     assign { } { }
120075     assign { } { }
120076     assign { } { }
120077     assign { } { }
120078     assign { } { }
120079     assign { } { }
120080     assign { } { }
120081     assign { } { }
120082     assign { } { }
120083     assign { } { }
120084     assign { } { }
120085     assign { } { }
120086     assign { } { }
120087     assign { } { }
120088     assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
120089     assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0
120090     assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0
120091     assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00
120092     assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0
120093     assign $0\main_sdram_master_p0_act_n[0:0] 1'1
120094     assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
120095     assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0
120096     assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000
120097     assign $0\main_sdram_master_p0_bank[1:0] 2'00
120098     assign $0\main_sdram_master_p0_cas_n[0:0] 1'1
120099     assign $0\main_sdram_master_p0_cs_n[0:0] 1'1
120100     assign $0\main_sdram_master_p0_ras_n[0:0] 1'1
120101     assign $0\main_sdram_master_p0_we_n[0:0] 1'1
120102     assign $0\main_sdram_master_p0_cke[0:0] 1'0
120103     assign $0\main_sdram_master_p0_odt[0:0] 1'0
120104     assign $0\main_sdram_master_p0_reset_n[0:0] 1'0
120105     assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
120106     attribute \src "ls180.v:3034.2-3068.5"
120107     switch \main_sdram_sel
120108       attribute \src "ls180.v:3034.6-3034.20"
120109       case 1'1
120110         assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address
120111         assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank
120112         assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n
120113         assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n
120114         assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n
120115         assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n
120116         assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke
120117         assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt
120118         assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n
120119         assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n
120120         assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata
120121         assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en
120122         assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask
120123         assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en
120124         assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata
120125         assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid
120126       attribute \src "ls180.v:3051.6-3051.10"
120127       case
120128         assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address
120129         assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank
120130         assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n
120131         assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n
120132         assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n
120133         assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n
120134         assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke
120135         assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt
120136         assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n
120137         assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n
120138         assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata
120139         assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en
120140         assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask
120141         assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en
120142         assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata
120143         assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid
120144     end
120145     sync always
120146       update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0]
120147       update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0]
120148       update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0]
120149       update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0]
120150       update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0]
120151       update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0]
120152       update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0]
120153       update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0]
120154       update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0]
120155       update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0]
120156       update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0]
120157       update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0]
120158       update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0]
120159       update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0]
120160       update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0]
120161       update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0]
120162       update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0]
120163       update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0]
120164   end
120165   attribute \src "ls180.v:302.12-302.48"
120166   process $proc$ls180.v:302$2858
120167     assign { } { }
120168     assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
120169     sync always
120170     sync init
120171       update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
120172   end
120173   attribute \src "ls180.v:303.11-303.43"
120174   process $proc$ls180.v:303$2859
120175     assign { } { }
120176     assign $1\main_sdram_master_p0_bank[1:0] 2'00
120177     sync always
120178     sync init
120179       update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
120180   end
120181   attribute \src "ls180.v:304.5-304.38"
120182   process $proc$ls180.v:304$2860
120183     assign { } { }
120184     assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
120185     sync always
120186     sync init
120187       update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
120188   end
120189   attribute \src "ls180.v:305.5-305.37"
120190   process $proc$ls180.v:305$2861
120191     assign { } { }
120192     assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
120193     sync always
120194     sync init
120195       update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
120196   end
120197   attribute \src "ls180.v:306.5-306.38"
120198   process $proc$ls180.v:306$2862
120199     assign { } { }
120200     assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
120201     sync always
120202     sync init
120203       update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
120204   end
120205   attribute \src "ls180.v:307.5-307.37"
120206   process $proc$ls180.v:307$2863
120207     assign { } { }
120208     assign $1\main_sdram_master_p0_we_n[0:0] 1'1
120209     sync always
120210     sync init
120211       update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0]
120212   end
120213   attribute \src "ls180.v:3073.1-3089.4"
120214   process $proc$ls180.v:3073$65
120215     assign { } { }
120216     assign { } { }
120217     assign { } { }
120218     assign { } { }
120219     assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1
120220     assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1
120221     assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
120222     assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1
120223     attribute \src "ls180.v:3078.2-3088.5"
120224     switch \main_sdram_command_issue_re
120225       attribute \src "ls180.v:3078.6-3078.33"
120226       case 1'1
120227         assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3079$66_Y
120228         assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3080$67_Y
120229         assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3081$68_Y
120230         assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3082$69_Y
120231       attribute \src "ls180.v:3083.6-3083.10"
120232       case
120233         assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1
120234         assign $0\main_sdram_inti_p0_we_n[0:0] 1'1
120235         assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1
120236         assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1
120237     end
120238     sync always
120239       update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0]
120240       update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0]
120241       update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0]
120242       update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0]
120243   end
120244   attribute \src "ls180.v:308.5-308.36"
120245   process $proc$ls180.v:308$2864
120246     assign { } { }
120247     assign $1\main_sdram_master_p0_cke[0:0] 1'0
120248     sync always
120249     sync init
120250       update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
120251   end
120252   attribute \src "ls180.v:309.5-309.36"
120253   process $proc$ls180.v:309$2865
120254     assign { } { }
120255     assign $1\main_sdram_master_p0_odt[0:0] 1'0
120256     sync always
120257     sync init
120258       update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
120259   end
120260   attribute \src "ls180.v:310.5-310.40"
120261   process $proc$ls180.v:310$2866
120262     assign { } { }
120263     assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
120264     sync always
120265     sync init
120266       update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
120267   end
120268   attribute \src "ls180.v:311.5-311.38"
120269   process $proc$ls180.v:311$2867
120270     assign { } { }
120271     assign $1\main_sdram_master_p0_act_n[0:0] 1'1
120272     sync always
120273     sync init
120274       update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
120275   end
120276   attribute \src "ls180.v:312.12-312.47"
120277   process $proc$ls180.v:312$2868
120278     assign { } { }
120279     assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
120280     sync always
120281     sync init
120282       update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
120283   end
120284   attribute \src "ls180.v:313.5-313.42"
120285   process $proc$ls180.v:313$2869
120286     assign { } { }
120287     assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
120288     sync always
120289     sync init
120290       update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0]
120291   end
120292   attribute \src "ls180.v:3132.1-3162.4"
120293   process $proc$ls180.v:3132$78
120294     assign { } { }
120295     assign { } { }
120296     assign { } { }
120297     assign { } { }
120298     assign $0\main_sdram_cmd_last[0:0] 1'0
120299     assign $0\main_sdram_sequencer_start0[0:0] 1'0
120300     assign { } { }
120301     assign $0\main_sdram_cmd_valid[0:0] 1'0
120302     assign $0\builder_refresher_next_state[1:0] \builder_refresher_state
120303     attribute \src "ls180.v:3138.2-3161.9"
120304     switch \builder_refresher_state
120305       attribute \src "ls180.v:0.0-0.0"
120306       case 2'01
120307         assign $0\main_sdram_cmd_valid[0:0] 1'1
120308         attribute \src "ls180.v:3141.4-3144.7"
120309         switch \main_sdram_cmd_ready
120310           attribute \src "ls180.v:3141.8-3141.28"
120311           case 1'1
120312             assign $0\main_sdram_sequencer_start0[0:0] 1'1
120313             assign $0\builder_refresher_next_state[1:0] 2'10
120314           case
120315         end
120316       attribute \src "ls180.v:0.0-0.0"
120317       case 2'10
120318         assign $0\main_sdram_cmd_valid[0:0] 1'1
120319         attribute \src "ls180.v:3148.4-3152.7"
120320         switch \main_sdram_sequencer_done0
120321           attribute \src "ls180.v:3148.8-3148.34"
120322           case 1'1
120323             assign $0\main_sdram_cmd_valid[0:0] 1'0
120324             assign $0\main_sdram_cmd_last[0:0] 1'1
120325             assign $0\builder_refresher_next_state[1:0] 2'00
120326           case
120327         end
120328       attribute \src "ls180.v:0.0-0.0"
120329       case
120330         attribute \src "ls180.v:3155.4-3159.7"
120331         switch 1'1
120332           attribute \src "ls180.v:3155.8-3155.12"
120333           case 1'1
120334             attribute \src "ls180.v:3156.5-3158.8"
120335             switch \main_sdram_wants_refresh
120336               attribute \src "ls180.v:3156.9-3156.33"
120337               case 1'1
120338                 assign $0\builder_refresher_next_state[1:0] 2'01
120339               case
120340             end
120341           case
120342         end
120343     end
120344     sync always
120345       update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0]
120346       update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0]
120347       update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0]
120348       update \builder_refresher_next_state $0\builder_refresher_next_state[1:0]
120349   end
120350   attribute \src "ls180.v:314.11-314.50"
120351   process $proc$ls180.v:314$2870
120352     assign { } { }
120353     assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
120354     sync always
120355     sync init
120356       update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
120357   end
120358   attribute \src "ls180.v:315.5-315.42"
120359   process $proc$ls180.v:315$2871
120360     assign { } { }
120361     assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
120362     sync always
120363     sync init
120364       update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0]
120365   end
120366   attribute \src "ls180.v:3177.1-3184.4"
120367   process $proc$ls180.v:3177$82
120368     assign { } { }
120369     assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
120370     attribute \src "ls180.v:3179.2-3183.5"
120371     switch \main_sdram_bankmachine0_row_col_n_addr_sel
120372       attribute \src "ls180.v:3179.6-3179.48"
120373       case 1'1
120374         assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
120375       attribute \src "ls180.v:3181.6-3181.10"
120376       case
120377         assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3182$84_Y
120378     end
120379     sync always
120380       update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0]
120381   end
120382   attribute \src "ls180.v:3188.1-3195.4"
120383   process $proc$ls180.v:3188$91
120384     assign { } { }
120385     assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
120386     attribute \src "ls180.v:3190.2-3194.5"
120387     switch $and$ls180.v:3190$92_Y
120388       attribute \src "ls180.v:3190.6-3190.115"
120389       case 1'1
120390         attribute \src "ls180.v:3191.3-3193.6"
120391         switch $ne$ls180.v:3191$93_Y
120392           attribute \src "ls180.v:3191.7-3191.143"
120393           case 1'1
120394             assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3192$94_Y
120395           case
120396         end
120397       case
120398     end
120399     sync always
120400       update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0]
120401   end
120402   attribute \src "ls180.v:3210.1-3217.4"
120403   process $proc$ls180.v:3210$95
120404     assign { } { }
120405     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
120406     attribute \src "ls180.v:3212.2-3216.5"
120407     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace
120408       attribute \src "ls180.v:3212.6-3212.58"
120409       case 1'1
120410         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3213$96_Y
120411       attribute \src "ls180.v:3214.6-3214.10"
120412       case
120413         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
120414     end
120415     sync always
120416       update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
120417   end
120418   attribute \src "ls180.v:322.11-322.36"
120419   process $proc$ls180.v:322$2872
120420     assign { } { }
120421     assign $1\main_sdram_storage[3:0] 4'0001
120422     sync always
120423     sync init
120424       update \main_sdram_storage $1\main_sdram_storage[3:0]
120425   end
120426   attribute \src "ls180.v:3226.1-3319.4"
120427   process $proc$ls180.v:3226$104
120428     assign { } { }
120429     assign { } { }
120430     assign { } { }
120431     assign { } { }
120432     assign { } { }
120433     assign { } { }
120434     assign { } { }
120435     assign { } { }
120436     assign { } { }
120437     assign { } { }
120438     assign { } { }
120439     assign { } { }
120440     assign { } { }
120441     assign { } { }
120442     assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
120443     assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
120444     assign { } { }
120445     assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
120446     assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
120447     assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0
120448     assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0
120449     assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
120450     assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
120451     assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
120452     assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
120453     assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
120454     assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
120455     assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
120456     assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state
120457     attribute \src "ls180.v:3242.2-3318.9"
120458     switch \builder_bankmachine0_state
120459       attribute \src "ls180.v:0.0-0.0"
120460       case 3'001
120461         assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
120462         attribute \src "ls180.v:3244.4-3252.7"
120463         switch $and$ls180.v:3244$105_Y
120464           attribute \src "ls180.v:3244.8-3244.87"
120465           case 1'1
120466             assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
120467             assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
120468             assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
120469             assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
120470             attribute \src "ls180.v:3246.5-3248.8"
120471             switch \main_sdram_bankmachine0_cmd_ready
120472               attribute \src "ls180.v:3246.9-3246.42"
120473               case 1'1
120474                 assign $0\builder_bankmachine0_next_state[2:0] 3'101
120475               case
120476             end
120477           case
120478         end
120479       attribute \src "ls180.v:0.0-0.0"
120480       case 3'010
120481         assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
120482         attribute \src "ls180.v:3256.4-3258.7"
120483         switch $and$ls180.v:3256$106_Y
120484           attribute \src "ls180.v:3256.8-3256.87"
120485           case 1'1
120486             assign $0\builder_bankmachine0_next_state[2:0] 3'101
120487           case
120488         end
120489       attribute \src "ls180.v:0.0-0.0"
120490       case 3'011
120491         attribute \src "ls180.v:3262.4-3271.7"
120492         switch \main_sdram_bankmachine0_trccon_ready
120493           attribute \src "ls180.v:3262.8-3262.44"
120494           case 1'1
120495             assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1
120496             assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1
120497             assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
120498             assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
120499             assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
120500             attribute \src "ls180.v:3267.5-3269.8"
120501             switch \main_sdram_bankmachine0_cmd_ready
120502               attribute \src "ls180.v:3267.9-3267.42"
120503               case 1'1
120504                 assign $0\builder_bankmachine0_next_state[2:0] 3'110
120505               case
120506             end
120507           case
120508         end
120509       attribute \src "ls180.v:0.0-0.0"
120510       case 3'100
120511         assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1
120512         assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
120513         attribute \src "ls180.v:3274.4-3276.7"
120514         switch \main_sdram_bankmachine0_twtpcon_ready
120515           attribute \src "ls180.v:3274.8-3274.45"
120516           case 1'1
120517             assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1
120518           case
120519         end
120520         attribute \src "ls180.v:3279.4-3281.7"
120521         switch $not$ls180.v:3279$107_Y
120522           attribute \src "ls180.v:3279.8-3279.46"
120523           case 1'1
120524             assign $0\builder_bankmachine0_next_state[2:0] 3'000
120525           case
120526         end
120527       attribute \src "ls180.v:0.0-0.0"
120528       case 3'101
120529         assign $0\builder_bankmachine0_next_state[2:0] 3'011
120530       attribute \src "ls180.v:0.0-0.0"
120531       case 3'110
120532         assign $0\builder_bankmachine0_next_state[2:0] 3'000
120533       attribute \src "ls180.v:0.0-0.0"
120534       case
120535         attribute \src "ls180.v:3290.4-3316.7"
120536         switch \main_sdram_bankmachine0_refresh_req
120537           attribute \src "ls180.v:3290.8-3290.43"
120538           case 1'1
120539             assign $0\builder_bankmachine0_next_state[2:0] 3'100
120540           attribute \src "ls180.v:3292.8-3292.12"
120541           case
120542             attribute \src "ls180.v:3293.5-3315.8"
120543             switch \main_sdram_bankmachine0_cmd_buffer_source_valid
120544               attribute \src "ls180.v:3293.9-3293.56"
120545               case 1'1
120546                 attribute \src "ls180.v:3294.6-3314.9"
120547                 switch \main_sdram_bankmachine0_row_opened
120548                   attribute \src "ls180.v:3294.10-3294.44"
120549                   case 1'1
120550                     attribute \src "ls180.v:3295.7-3311.10"
120551                     switch \main_sdram_bankmachine0_row_hit
120552                       attribute \src "ls180.v:3295.11-3295.42"
120553                       case 1'1
120554                         assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1
120555                         assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1
120556                         attribute \src "ls180.v:3297.8-3304.11"
120557                         switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we
120558                           attribute \src "ls180.v:3297.12-3297.64"
120559                           case 1'1
120560                             assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready
120561                             assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1
120562                             assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1
120563                           attribute \src "ls180.v:3301.12-3301.16"
120564                           case
120565                             assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready
120566                             assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1
120567                         end
120568                         attribute \src "ls180.v:3306.8-3308.11"
120569                         switch $and$ls180.v:3306$108_Y
120570                           attribute \src "ls180.v:3306.12-3306.88"
120571                           case 1'1
120572                             assign $0\builder_bankmachine0_next_state[2:0] 3'010
120573                           case
120574                         end
120575                       attribute \src "ls180.v:3309.11-3309.15"
120576                       case
120577                         assign $0\builder_bankmachine0_next_state[2:0] 3'001
120578                     end
120579                   attribute \src "ls180.v:3312.10-3312.14"
120580                   case
120581                     assign $0\builder_bankmachine0_next_state[2:0] 3'011
120582                 end
120583               case
120584             end
120585         end
120586     end
120587     sync always
120588       update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0]
120589       update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0]
120590       update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0]
120591       update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0]
120592       update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0]
120593       update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0]
120594       update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0]
120595       update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
120596       update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
120597       update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
120598       update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0]
120599       update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0]
120600       update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
120601       update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0]
120602   end
120603   attribute \src "ls180.v:323.5-323.25"
120604   process $proc$ls180.v:323$2873
120605     assign { } { }
120606     assign $1\main_sdram_re[0:0] 1'0
120607     sync always
120608     sync init
120609       update \main_sdram_re $1\main_sdram_re[0:0]
120610   end
120611   attribute \src "ls180.v:324.11-324.44"
120612   process $proc$ls180.v:324$2874
120613     assign { } { }
120614     assign $1\main_sdram_command_storage[5:0] 6'000000
120615     sync always
120616     sync init
120617       update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
120618   end
120619   attribute \src "ls180.v:325.5-325.33"
120620   process $proc$ls180.v:325$2875
120621     assign { } { }
120622     assign $1\main_sdram_command_re[0:0] 1'0
120623     sync always
120624     sync init
120625       update \main_sdram_command_re $1\main_sdram_command_re[0:0]
120626   end
120627   attribute \src "ls180.v:329.5-329.38"
120628   process $proc$ls180.v:329$2876
120629     assign { } { }
120630     assign $0\main_sdram_command_issue_w[0:0] 1'0
120631     sync always
120632       update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0]
120633     sync init
120634   end
120635   attribute \src "ls180.v:330.12-330.46"
120636   process $proc$ls180.v:330$2877
120637     assign { } { }
120638     assign $1\main_sdram_address_storage[12:0] 13'0000000000000
120639     sync always
120640     sync init
120641       update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
120642   end
120643   attribute \src "ls180.v:331.5-331.33"
120644   process $proc$ls180.v:331$2878
120645     assign { } { }
120646     assign $1\main_sdram_address_re[0:0] 1'0
120647     sync always
120648     sync init
120649       update \main_sdram_address_re $1\main_sdram_address_re[0:0]
120650   end
120651   attribute \src "ls180.v:332.11-332.45"
120652   process $proc$ls180.v:332$2879
120653     assign { } { }
120654     assign $1\main_sdram_baddress_storage[1:0] 2'00
120655     sync always
120656     sync init
120657       update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
120658   end
120659   attribute \src "ls180.v:333.5-333.34"
120660   process $proc$ls180.v:333$2880
120661     assign { } { }
120662     assign $1\main_sdram_baddress_re[0:0] 1'0
120663     sync always
120664     sync init
120665       update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0]
120666   end
120667   attribute \src "ls180.v:3334.1-3341.4"
120668   process $proc$ls180.v:3334$112
120669     assign { } { }
120670     assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
120671     attribute \src "ls180.v:3336.2-3340.5"
120672     switch \main_sdram_bankmachine1_row_col_n_addr_sel
120673       attribute \src "ls180.v:3336.6-3336.48"
120674       case 1'1
120675         assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
120676       attribute \src "ls180.v:3338.6-3338.10"
120677       case
120678         assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3339$114_Y
120679     end
120680     sync always
120681       update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
120682   end
120683   attribute \src "ls180.v:334.12-334.45"
120684   process $proc$ls180.v:334$2881
120685     assign { } { }
120686     assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
120687     sync always
120688     sync init
120689       update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0]
120690   end
120691   attribute \src "ls180.v:3345.1-3352.4"
120692   process $proc$ls180.v:3345$121
120693     assign { } { }
120694     assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
120695     attribute \src "ls180.v:3347.2-3351.5"
120696     switch $and$ls180.v:3347$122_Y
120697       attribute \src "ls180.v:3347.6-3347.115"
120698       case 1'1
120699         attribute \src "ls180.v:3348.3-3350.6"
120700         switch $ne$ls180.v:3348$123_Y
120701           attribute \src "ls180.v:3348.7-3348.143"
120702           case 1'1
120703             assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3349$124_Y
120704           case
120705         end
120706       case
120707     end
120708     sync always
120709       update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0]
120710   end
120711   attribute \src "ls180.v:335.5-335.32"
120712   process $proc$ls180.v:335$2882
120713     assign { } { }
120714     assign $1\main_sdram_wrdata_re[0:0] 1'0
120715     sync always
120716     sync init
120717       update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
120718   end
120719   attribute \src "ls180.v:336.12-336.37"
120720   process $proc$ls180.v:336$2883
120721     assign { } { }
120722     assign $1\main_sdram_status[15:0] 16'0000000000000000
120723     sync always
120724     sync init
120725       update \main_sdram_status $1\main_sdram_status[15:0]
120726   end
120727   attribute \src "ls180.v:3367.1-3374.4"
120728   process $proc$ls180.v:3367$125
120729     assign { } { }
120730     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
120731     attribute \src "ls180.v:3369.2-3373.5"
120732     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace
120733       attribute \src "ls180.v:3369.6-3369.58"
120734       case 1'1
120735         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3370$126_Y
120736       attribute \src "ls180.v:3371.6-3371.10"
120737       case
120738         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
120739     end
120740     sync always
120741       update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
120742   end
120743   attribute \src "ls180.v:3383.1-3476.4"
120744   process $proc$ls180.v:3383$134
120745     assign { } { }
120746     assign { } { }
120747     assign { } { }
120748     assign { } { }
120749     assign { } { }
120750     assign { } { }
120751     assign { } { }
120752     assign { } { }
120753     assign { } { }
120754     assign { } { }
120755     assign { } { }
120756     assign { } { }
120757     assign { } { }
120758     assign { } { }
120759     assign { } { }
120760     assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
120761     assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
120762     assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
120763     assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
120764     assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
120765     assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
120766     assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
120767     assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
120768     assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
120769     assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0
120770     assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0
120771     assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
120772     assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
120773     assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state
120774     attribute \src "ls180.v:3399.2-3475.9"
120775     switch \builder_bankmachine1_state
120776       attribute \src "ls180.v:0.0-0.0"
120777       case 3'001
120778         assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
120779         attribute \src "ls180.v:3401.4-3409.7"
120780         switch $and$ls180.v:3401$135_Y
120781           attribute \src "ls180.v:3401.8-3401.87"
120782           case 1'1
120783             assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
120784             assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
120785             assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
120786             assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
120787             attribute \src "ls180.v:3403.5-3405.8"
120788             switch \main_sdram_bankmachine1_cmd_ready
120789               attribute \src "ls180.v:3403.9-3403.42"
120790               case 1'1
120791                 assign $0\builder_bankmachine1_next_state[2:0] 3'101
120792               case
120793             end
120794           case
120795         end
120796       attribute \src "ls180.v:0.0-0.0"
120797       case 3'010
120798         assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
120799         attribute \src "ls180.v:3413.4-3415.7"
120800         switch $and$ls180.v:3413$136_Y
120801           attribute \src "ls180.v:3413.8-3413.87"
120802           case 1'1
120803             assign $0\builder_bankmachine1_next_state[2:0] 3'101
120804           case
120805         end
120806       attribute \src "ls180.v:0.0-0.0"
120807       case 3'011
120808         attribute \src "ls180.v:3419.4-3428.7"
120809         switch \main_sdram_bankmachine1_trccon_ready
120810           attribute \src "ls180.v:3419.8-3419.44"
120811           case 1'1
120812             assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1
120813             assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1
120814             assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
120815             assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
120816             assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
120817             attribute \src "ls180.v:3424.5-3426.8"
120818             switch \main_sdram_bankmachine1_cmd_ready
120819               attribute \src "ls180.v:3424.9-3424.42"
120820               case 1'1
120821                 assign $0\builder_bankmachine1_next_state[2:0] 3'110
120822               case
120823             end
120824           case
120825         end
120826       attribute \src "ls180.v:0.0-0.0"
120827       case 3'100
120828         assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1
120829         assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
120830         attribute \src "ls180.v:3431.4-3433.7"
120831         switch \main_sdram_bankmachine1_twtpcon_ready
120832           attribute \src "ls180.v:3431.8-3431.45"
120833           case 1'1
120834             assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1
120835           case
120836         end
120837         attribute \src "ls180.v:3436.4-3438.7"
120838         switch $not$ls180.v:3436$137_Y
120839           attribute \src "ls180.v:3436.8-3436.46"
120840           case 1'1
120841             assign $0\builder_bankmachine1_next_state[2:0] 3'000
120842           case
120843         end
120844       attribute \src "ls180.v:0.0-0.0"
120845       case 3'101
120846         assign $0\builder_bankmachine1_next_state[2:0] 3'011
120847       attribute \src "ls180.v:0.0-0.0"
120848       case 3'110
120849         assign $0\builder_bankmachine1_next_state[2:0] 3'000
120850       attribute \src "ls180.v:0.0-0.0"
120851       case
120852         attribute \src "ls180.v:3447.4-3473.7"
120853         switch \main_sdram_bankmachine1_refresh_req
120854           attribute \src "ls180.v:3447.8-3447.43"
120855           case 1'1
120856             assign $0\builder_bankmachine1_next_state[2:0] 3'100
120857           attribute \src "ls180.v:3449.8-3449.12"
120858           case
120859             attribute \src "ls180.v:3450.5-3472.8"
120860             switch \main_sdram_bankmachine1_cmd_buffer_source_valid
120861               attribute \src "ls180.v:3450.9-3450.56"
120862               case 1'1
120863                 attribute \src "ls180.v:3451.6-3471.9"
120864                 switch \main_sdram_bankmachine1_row_opened
120865                   attribute \src "ls180.v:3451.10-3451.44"
120866                   case 1'1
120867                     attribute \src "ls180.v:3452.7-3468.10"
120868                     switch \main_sdram_bankmachine1_row_hit
120869                       attribute \src "ls180.v:3452.11-3452.42"
120870                       case 1'1
120871                         assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1
120872                         assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1
120873                         attribute \src "ls180.v:3454.8-3461.11"
120874                         switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we
120875                           attribute \src "ls180.v:3454.12-3454.64"
120876                           case 1'1
120877                             assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready
120878                             assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1
120879                             assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1
120880                           attribute \src "ls180.v:3458.12-3458.16"
120881                           case
120882                             assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready
120883                             assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1
120884                         end
120885                         attribute \src "ls180.v:3463.8-3465.11"
120886                         switch $and$ls180.v:3463$138_Y
120887                           attribute \src "ls180.v:3463.12-3463.88"
120888                           case 1'1
120889                             assign $0\builder_bankmachine1_next_state[2:0] 3'010
120890                           case
120891                         end
120892                       attribute \src "ls180.v:3466.11-3466.15"
120893                       case
120894                         assign $0\builder_bankmachine1_next_state[2:0] 3'001
120895                     end
120896                   attribute \src "ls180.v:3469.10-3469.14"
120897                   case
120898                     assign $0\builder_bankmachine1_next_state[2:0] 3'011
120899                 end
120900               case
120901             end
120902         end
120903     end
120904     sync always
120905       update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0]
120906       update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0]
120907       update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0]
120908       update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0]
120909       update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0]
120910       update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0]
120911       update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0]
120912       update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
120913       update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
120914       update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
120915       update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0]
120916       update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0]
120917       update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
120918       update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0]
120919   end
120920   attribute \src "ls180.v:3491.1-3498.4"
120921   process $proc$ls180.v:3491$142
120922     assign { } { }
120923     assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
120924     attribute \src "ls180.v:3493.2-3497.5"
120925     switch \main_sdram_bankmachine2_row_col_n_addr_sel
120926       attribute \src "ls180.v:3493.6-3493.48"
120927       case 1'1
120928         assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
120929       attribute \src "ls180.v:3495.6-3495.10"
120930       case
120931         assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3496$144_Y
120932     end
120933     sync always
120934       update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0]
120935   end
120936   attribute \src "ls180.v:3502.1-3509.4"
120937   process $proc$ls180.v:3502$151
120938     assign { } { }
120939     assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
120940     attribute \src "ls180.v:3504.2-3508.5"
120941     switch $and$ls180.v:3504$152_Y
120942       attribute \src "ls180.v:3504.6-3504.115"
120943       case 1'1
120944         attribute \src "ls180.v:3505.3-3507.6"
120945         switch $ne$ls180.v:3505$153_Y
120946           attribute \src "ls180.v:3505.7-3505.143"
120947           case 1'1
120948             assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3506$154_Y
120949           case
120950         end
120951       case
120952     end
120953     sync always
120954       update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0]
120955   end
120956   attribute \src "ls180.v:3524.1-3531.4"
120957   process $proc$ls180.v:3524$155
120958     assign { } { }
120959     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
120960     attribute \src "ls180.v:3526.2-3530.5"
120961     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace
120962       attribute \src "ls180.v:3526.6-3526.58"
120963       case 1'1
120964         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3527$156_Y
120965       attribute \src "ls180.v:3528.6-3528.10"
120966       case
120967         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
120968     end
120969     sync always
120970       update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
120971   end
120972   attribute \src "ls180.v:3540.1-3633.4"
120973   process $proc$ls180.v:3540$164
120974     assign { } { }
120975     assign { } { }
120976     assign { } { }
120977     assign { } { }
120978     assign { } { }
120979     assign { } { }
120980     assign { } { }
120981     assign { } { }
120982     assign { } { }
120983     assign { } { }
120984     assign { } { }
120985     assign { } { }
120986     assign { } { }
120987     assign { } { }
120988     assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0
120989     assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0
120990     assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
120991     assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
120992     assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
120993     assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
120994     assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
120995     assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
120996     assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
120997     assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
120998     assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
120999     assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
121000     assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
121001     assign { } { }
121002     assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state
121003     attribute \src "ls180.v:3556.2-3632.9"
121004     switch \builder_bankmachine2_state
121005       attribute \src "ls180.v:0.0-0.0"
121006       case 3'001
121007         assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
121008         attribute \src "ls180.v:3558.4-3566.7"
121009         switch $and$ls180.v:3558$165_Y
121010           attribute \src "ls180.v:3558.8-3558.87"
121011           case 1'1
121012             assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
121013             assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
121014             assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
121015             assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
121016             attribute \src "ls180.v:3560.5-3562.8"
121017             switch \main_sdram_bankmachine2_cmd_ready
121018               attribute \src "ls180.v:3560.9-3560.42"
121019               case 1'1
121020                 assign $0\builder_bankmachine2_next_state[2:0] 3'101
121021               case
121022             end
121023           case
121024         end
121025       attribute \src "ls180.v:0.0-0.0"
121026       case 3'010
121027         assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
121028         attribute \src "ls180.v:3570.4-3572.7"
121029         switch $and$ls180.v:3570$166_Y
121030           attribute \src "ls180.v:3570.8-3570.87"
121031           case 1'1
121032             assign $0\builder_bankmachine2_next_state[2:0] 3'101
121033           case
121034         end
121035       attribute \src "ls180.v:0.0-0.0"
121036       case 3'011
121037         attribute \src "ls180.v:3576.4-3585.7"
121038         switch \main_sdram_bankmachine2_trccon_ready
121039           attribute \src "ls180.v:3576.8-3576.44"
121040           case 1'1
121041             assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1
121042             assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1
121043             assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
121044             assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
121045             assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
121046             attribute \src "ls180.v:3581.5-3583.8"
121047             switch \main_sdram_bankmachine2_cmd_ready
121048               attribute \src "ls180.v:3581.9-3581.42"
121049               case 1'1
121050                 assign $0\builder_bankmachine2_next_state[2:0] 3'110
121051               case
121052             end
121053           case
121054         end
121055       attribute \src "ls180.v:0.0-0.0"
121056       case 3'100
121057         assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1
121058         assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
121059         attribute \src "ls180.v:3588.4-3590.7"
121060         switch \main_sdram_bankmachine2_twtpcon_ready
121061           attribute \src "ls180.v:3588.8-3588.45"
121062           case 1'1
121063             assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1
121064           case
121065         end
121066         attribute \src "ls180.v:3593.4-3595.7"
121067         switch $not$ls180.v:3593$167_Y
121068           attribute \src "ls180.v:3593.8-3593.46"
121069           case 1'1
121070             assign $0\builder_bankmachine2_next_state[2:0] 3'000
121071           case
121072         end
121073       attribute \src "ls180.v:0.0-0.0"
121074       case 3'101
121075         assign $0\builder_bankmachine2_next_state[2:0] 3'011
121076       attribute \src "ls180.v:0.0-0.0"
121077       case 3'110
121078         assign $0\builder_bankmachine2_next_state[2:0] 3'000
121079       attribute \src "ls180.v:0.0-0.0"
121080       case
121081         attribute \src "ls180.v:3604.4-3630.7"
121082         switch \main_sdram_bankmachine2_refresh_req
121083           attribute \src "ls180.v:3604.8-3604.43"
121084           case 1'1
121085             assign $0\builder_bankmachine2_next_state[2:0] 3'100
121086           attribute \src "ls180.v:3606.8-3606.12"
121087           case
121088             attribute \src "ls180.v:3607.5-3629.8"
121089             switch \main_sdram_bankmachine2_cmd_buffer_source_valid
121090               attribute \src "ls180.v:3607.9-3607.56"
121091               case 1'1
121092                 attribute \src "ls180.v:3608.6-3628.9"
121093                 switch \main_sdram_bankmachine2_row_opened
121094                   attribute \src "ls180.v:3608.10-3608.44"
121095                   case 1'1
121096                     attribute \src "ls180.v:3609.7-3625.10"
121097                     switch \main_sdram_bankmachine2_row_hit
121098                       attribute \src "ls180.v:3609.11-3609.42"
121099                       case 1'1
121100                         assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1
121101                         assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1
121102                         attribute \src "ls180.v:3611.8-3618.11"
121103                         switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we
121104                           attribute \src "ls180.v:3611.12-3611.64"
121105                           case 1'1
121106                             assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready
121107                             assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1
121108                             assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1
121109                           attribute \src "ls180.v:3615.12-3615.16"
121110                           case
121111                             assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready
121112                             assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1
121113                         end
121114                         attribute \src "ls180.v:3620.8-3622.11"
121115                         switch $and$ls180.v:3620$168_Y
121116                           attribute \src "ls180.v:3620.12-3620.88"
121117                           case 1'1
121118                             assign $0\builder_bankmachine2_next_state[2:0] 3'010
121119                           case
121120                         end
121121                       attribute \src "ls180.v:3623.11-3623.15"
121122                       case
121123                         assign $0\builder_bankmachine2_next_state[2:0] 3'001
121124                     end
121125                   attribute \src "ls180.v:3626.10-3626.14"
121126                   case
121127                     assign $0\builder_bankmachine2_next_state[2:0] 3'011
121128                 end
121129               case
121130             end
121131         end
121132     end
121133     sync always
121134       update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0]
121135       update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0]
121136       update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0]
121137       update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0]
121138       update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0]
121139       update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0]
121140       update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0]
121141       update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
121142       update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
121143       update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
121144       update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0]
121145       update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0]
121146       update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
121147       update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0]
121148   end
121149   attribute \src "ls180.v:3648.1-3655.4"
121150   process $proc$ls180.v:3648$172
121151     assign { } { }
121152     assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
121153     attribute \src "ls180.v:3650.2-3654.5"
121154     switch \main_sdram_bankmachine3_row_col_n_addr_sel
121155       attribute \src "ls180.v:3650.6-3650.48"
121156       case 1'1
121157         assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
121158       attribute \src "ls180.v:3652.6-3652.10"
121159       case
121160         assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3653$174_Y
121161     end
121162     sync always
121163       update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0]
121164   end
121165   attribute \src "ls180.v:3659.1-3666.4"
121166   process $proc$ls180.v:3659$181
121167     assign { } { }
121168     assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
121169     attribute \src "ls180.v:3661.2-3665.5"
121170     switch $and$ls180.v:3661$182_Y
121171       attribute \src "ls180.v:3661.6-3661.115"
121172       case 1'1
121173         attribute \src "ls180.v:3662.3-3664.6"
121174         switch $ne$ls180.v:3662$183_Y
121175           attribute \src "ls180.v:3662.7-3662.143"
121176           case 1'1
121177             assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3663$184_Y
121178           case
121179         end
121180       case
121181     end
121182     sync always
121183       update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0]
121184   end
121185   attribute \src "ls180.v:366.12-366.46"
121186   process $proc$ls180.v:366$2884
121187     assign { } { }
121188     assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
121189     sync always
121190     sync init
121191       update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
121192   end
121193   attribute \src "ls180.v:367.11-367.47"
121194   process $proc$ls180.v:367$2885
121195     assign { } { }
121196     assign $1\main_sdram_interface_wdata_we[1:0] 2'00
121197     sync always
121198     sync init
121199       update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0]
121200   end
121201   attribute \src "ls180.v:3681.1-3688.4"
121202   process $proc$ls180.v:3681$185
121203     assign { } { }
121204     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
121205     attribute \src "ls180.v:3683.2-3687.5"
121206     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace
121207       attribute \src "ls180.v:3683.6-3683.58"
121208       case 1'1
121209         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3684$186_Y
121210       attribute \src "ls180.v:3685.6-3685.10"
121211       case
121212         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
121213     end
121214     sync always
121215       update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
121216   end
121217   attribute \src "ls180.v:369.12-369.45"
121218   process $proc$ls180.v:369$2886
121219     assign { } { }
121220     assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
121221     sync always
121222     sync init
121223       update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0]
121224   end
121225   attribute \src "ls180.v:3697.1-3790.4"
121226   process $proc$ls180.v:3697$194
121227     assign { } { }
121228     assign { } { }
121229     assign { } { }
121230     assign { } { }
121231     assign { } { }
121232     assign { } { }
121233     assign { } { }
121234     assign { } { }
121235     assign { } { }
121236     assign { } { }
121237     assign { } { }
121238     assign { } { }
121239     assign { } { }
121240     assign { } { }
121241     assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
121242     assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
121243     assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0
121244     assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0
121245     assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
121246     assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
121247     assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
121248     assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
121249     assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
121250     assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
121251     assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
121252     assign { } { }
121253     assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
121254     assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
121255     assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state
121256     attribute \src "ls180.v:3713.2-3789.9"
121257     switch \builder_bankmachine3_state
121258       attribute \src "ls180.v:0.0-0.0"
121259       case 3'001
121260         assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
121261         attribute \src "ls180.v:3715.4-3723.7"
121262         switch $and$ls180.v:3715$195_Y
121263           attribute \src "ls180.v:3715.8-3715.87"
121264           case 1'1
121265             assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
121266             assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
121267             assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
121268             assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
121269             attribute \src "ls180.v:3717.5-3719.8"
121270             switch \main_sdram_bankmachine3_cmd_ready
121271               attribute \src "ls180.v:3717.9-3717.42"
121272               case 1'1
121273                 assign $0\builder_bankmachine3_next_state[2:0] 3'101
121274               case
121275             end
121276           case
121277         end
121278       attribute \src "ls180.v:0.0-0.0"
121279       case 3'010
121280         assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
121281         attribute \src "ls180.v:3727.4-3729.7"
121282         switch $and$ls180.v:3727$196_Y
121283           attribute \src "ls180.v:3727.8-3727.87"
121284           case 1'1
121285             assign $0\builder_bankmachine3_next_state[2:0] 3'101
121286           case
121287         end
121288       attribute \src "ls180.v:0.0-0.0"
121289       case 3'011
121290         attribute \src "ls180.v:3733.4-3742.7"
121291         switch \main_sdram_bankmachine3_trccon_ready
121292           attribute \src "ls180.v:3733.8-3733.44"
121293           case 1'1
121294             assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1
121295             assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1
121296             assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
121297             assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
121298             assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
121299             attribute \src "ls180.v:3738.5-3740.8"
121300             switch \main_sdram_bankmachine3_cmd_ready
121301               attribute \src "ls180.v:3738.9-3738.42"
121302               case 1'1
121303                 assign $0\builder_bankmachine3_next_state[2:0] 3'110
121304               case
121305             end
121306           case
121307         end
121308       attribute \src "ls180.v:0.0-0.0"
121309       case 3'100
121310         assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1
121311         assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
121312         attribute \src "ls180.v:3745.4-3747.7"
121313         switch \main_sdram_bankmachine3_twtpcon_ready
121314           attribute \src "ls180.v:3745.8-3745.45"
121315           case 1'1
121316             assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1
121317           case
121318         end
121319         attribute \src "ls180.v:3750.4-3752.7"
121320         switch $not$ls180.v:3750$197_Y
121321           attribute \src "ls180.v:3750.8-3750.46"
121322           case 1'1
121323             assign $0\builder_bankmachine3_next_state[2:0] 3'000
121324           case
121325         end
121326       attribute \src "ls180.v:0.0-0.0"
121327       case 3'101
121328         assign $0\builder_bankmachine3_next_state[2:0] 3'011
121329       attribute \src "ls180.v:0.0-0.0"
121330       case 3'110
121331         assign $0\builder_bankmachine3_next_state[2:0] 3'000
121332       attribute \src "ls180.v:0.0-0.0"
121333       case
121334         attribute \src "ls180.v:3761.4-3787.7"
121335         switch \main_sdram_bankmachine3_refresh_req
121336           attribute \src "ls180.v:3761.8-3761.43"
121337           case 1'1
121338             assign $0\builder_bankmachine3_next_state[2:0] 3'100
121339           attribute \src "ls180.v:3763.8-3763.12"
121340           case
121341             attribute \src "ls180.v:3764.5-3786.8"
121342             switch \main_sdram_bankmachine3_cmd_buffer_source_valid
121343               attribute \src "ls180.v:3764.9-3764.56"
121344               case 1'1
121345                 attribute \src "ls180.v:3765.6-3785.9"
121346                 switch \main_sdram_bankmachine3_row_opened
121347                   attribute \src "ls180.v:3765.10-3765.44"
121348                   case 1'1
121349                     attribute \src "ls180.v:3766.7-3782.10"
121350                     switch \main_sdram_bankmachine3_row_hit
121351                       attribute \src "ls180.v:3766.11-3766.42"
121352                       case 1'1
121353                         assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1
121354                         assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1
121355                         attribute \src "ls180.v:3768.8-3775.11"
121356                         switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we
121357                           attribute \src "ls180.v:3768.12-3768.64"
121358                           case 1'1
121359                             assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready
121360                             assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1
121361                             assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1
121362                           attribute \src "ls180.v:3772.12-3772.16"
121363                           case
121364                             assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready
121365                             assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1
121366                         end
121367                         attribute \src "ls180.v:3777.8-3779.11"
121368                         switch $and$ls180.v:3777$198_Y
121369                           attribute \src "ls180.v:3777.12-3777.88"
121370                           case 1'1
121371                             assign $0\builder_bankmachine3_next_state[2:0] 3'010
121372                           case
121373                         end
121374                       attribute \src "ls180.v:3780.11-3780.15"
121375                       case
121376                         assign $0\builder_bankmachine3_next_state[2:0] 3'001
121377                     end
121378                   attribute \src "ls180.v:3783.10-3783.14"
121379                   case
121380                     assign $0\builder_bankmachine3_next_state[2:0] 3'011
121381                 end
121382               case
121383             end
121384         end
121385     end
121386     sync always
121387       update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0]
121388       update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0]
121389       update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0]
121390       update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0]
121391       update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0]
121392       update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0]
121393       update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0]
121394       update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
121395       update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
121396       update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
121397       update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0]
121398       update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0]
121399       update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
121400       update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0]
121401   end
121402   attribute \src "ls180.v:370.11-370.40"
121403   process $proc$ls180.v:370$2887
121404     assign { } { }
121405     assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
121406     sync always
121407     sync init
121408       update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
121409   end
121410   attribute \src "ls180.v:371.5-371.35"
121411   process $proc$ls180.v:371$2888
121412     assign { } { }
121413     assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
121414     sync always
121415     sync init
121416       update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
121417   end
121418   attribute \src "ls180.v:372.5-372.34"
121419   process $proc$ls180.v:372$2889
121420     assign { } { }
121421     assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
121422     sync always
121423     sync init
121424       update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
121425   end
121426   attribute \src "ls180.v:373.5-373.35"
121427   process $proc$ls180.v:373$2890
121428     assign { } { }
121429     assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
121430     sync always
121431     sync init
121432       update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
121433   end
121434   attribute \src "ls180.v:374.5-374.34"
121435   process $proc$ls180.v:374$2891
121436     assign { } { }
121437     assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
121438     sync always
121439     sync init
121440       update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
121441   end
121442   attribute \src "ls180.v:378.5-378.35"
121443   process $proc$ls180.v:378$2892
121444     assign { } { }
121445     assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
121446     sync always
121447       update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0]
121448     sync init
121449   end
121450   attribute \src "ls180.v:380.5-380.39"
121451   process $proc$ls180.v:380$2893
121452     assign { } { }
121453     assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
121454     sync always
121455     sync init
121456       update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0]
121457   end
121458   attribute \src "ls180.v:3810.1-3816.4"
121459   process $proc$ls180.v:3810$237
121460     assign { } { }
121461     assign { } { }
121462     assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3812$250_Y
121463     assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3813$263_Y
121464     assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3814$276_Y
121465     assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3815$289_Y
121466     sync always
121467       update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
121468   end
121469   attribute \src "ls180.v:382.5-382.39"
121470   process $proc$ls180.v:382$2894
121471     assign { } { }
121472     assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
121473     sync always
121474     sync init
121475       update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0]
121476   end
121477   attribute \src "ls180.v:3824.1-3829.4"
121478   process $proc$ls180.v:3824$290
121479     assign { } { }
121480     assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
121481     attribute \src "ls180.v:3826.2-3828.5"
121482     switch \main_sdram_choose_cmd_cmd_valid
121483       attribute \src "ls180.v:3826.6-3826.37"
121484       case 1'1
121485         assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0
121486       case
121487     end
121488     sync always
121489       update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0]
121490   end
121491   attribute \src "ls180.v:3830.1-3835.4"
121492   process $proc$ls180.v:3830$291
121493     assign { } { }
121494     assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
121495     attribute \src "ls180.v:3832.2-3834.5"
121496     switch \main_sdram_choose_cmd_cmd_valid
121497       attribute \src "ls180.v:3832.6-3832.37"
121498       case 1'1
121499         assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1
121500       case
121501     end
121502     sync always
121503       update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0]
121504   end
121505   attribute \src "ls180.v:3836.1-3841.4"
121506   process $proc$ls180.v:3836$292
121507     assign { } { }
121508     assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
121509     attribute \src "ls180.v:3838.2-3840.5"
121510     switch \main_sdram_choose_cmd_cmd_valid
121511       attribute \src "ls180.v:3838.6-3838.37"
121512       case 1'1
121513         assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2
121514       case
121515     end
121516     sync always
121517       update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0]
121518   end
121519   attribute \src "ls180.v:3843.1-3849.4"
121520   process $proc$ls180.v:3843$295
121521     assign { } { }
121522     assign { } { }
121523     assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3845$308_Y
121524     assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3846$321_Y
121525     assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3847$334_Y
121526     assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3848$347_Y
121527     sync always
121528       update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0]
121529   end
121530   attribute \src "ls180.v:385.5-385.32"
121531   process $proc$ls180.v:385$2895
121532     assign { } { }
121533     assign $1\main_sdram_cmd_valid[0:0] 1'0
121534     sync always
121535     sync init
121536       update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0]
121537   end
121538   attribute \src "ls180.v:3857.1-3862.4"
121539   process $proc$ls180.v:3857$348
121540     assign { } { }
121541     assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
121542     attribute \src "ls180.v:3859.2-3861.5"
121543     switch \main_sdram_choose_req_cmd_valid
121544       attribute \src "ls180.v:3859.6-3859.37"
121545       case 1'1
121546         assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3
121547       case
121548     end
121549     sync always
121550       update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0]
121551   end
121552   attribute \src "ls180.v:386.5-386.32"
121553   process $proc$ls180.v:386$2896
121554     assign { } { }
121555     assign $1\main_sdram_cmd_ready[0:0] 1'0
121556     sync always
121557     sync init
121558       update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0]
121559   end
121560   attribute \src "ls180.v:3863.1-3868.4"
121561   process $proc$ls180.v:3863$349
121562     assign { } { }
121563     assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
121564     attribute \src "ls180.v:3865.2-3867.5"
121565     switch \main_sdram_choose_req_cmd_valid
121566       attribute \src "ls180.v:3865.6-3865.37"
121567       case 1'1
121568         assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4
121569       case
121570     end
121571     sync always
121572       update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0]
121573   end
121574   attribute \src "ls180.v:3869.1-3874.4"
121575   process $proc$ls180.v:3869$350
121576     assign { } { }
121577     assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
121578     attribute \src "ls180.v:3871.2-3873.5"
121579     switch \main_sdram_choose_req_cmd_valid
121580       attribute \src "ls180.v:3871.6-3871.37"
121581       case 1'1
121582         assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5
121583       case
121584     end
121585     sync always
121586       update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0]
121587   end
121588   attribute \src "ls180.v:387.5-387.31"
121589   process $proc$ls180.v:387$2897
121590     assign { } { }
121591     assign $1\main_sdram_cmd_last[0:0] 1'0
121592     sync always
121593     sync init
121594       update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0]
121595   end
121596   attribute \src "ls180.v:3875.1-3883.4"
121597   process $proc$ls180.v:3875$351
121598     assign { } { }
121599     assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
121600     attribute \src "ls180.v:3877.2-3879.5"
121601     switch $and$ls180.v:3877$354_Y
121602       attribute \src "ls180.v:3877.6-3877.115"
121603       case 1'1
121604         assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
121605       case
121606     end
121607     attribute \src "ls180.v:3880.2-3882.5"
121608     switch $and$ls180.v:3880$357_Y
121609       attribute \src "ls180.v:3880.6-3880.115"
121610       case 1'1
121611         assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1
121612       case
121613     end
121614     sync always
121615       update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0]
121616   end
121617   attribute \src "ls180.v:388.12-388.44"
121618   process $proc$ls180.v:388$2898
121619     assign { } { }
121620     assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
121621     sync always
121622     sync init
121623       update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0]
121624   end
121625   attribute \src "ls180.v:3884.1-3892.4"
121626   process $proc$ls180.v:3884$358
121627     assign { } { }
121628     assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
121629     attribute \src "ls180.v:3886.2-3888.5"
121630     switch $and$ls180.v:3886$361_Y
121631       attribute \src "ls180.v:3886.6-3886.115"
121632       case 1'1
121633         assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
121634       case
121635     end
121636     attribute \src "ls180.v:3889.2-3891.5"
121637     switch $and$ls180.v:3889$364_Y
121638       attribute \src "ls180.v:3889.6-3889.115"
121639       case 1'1
121640         assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1
121641       case
121642     end
121643     sync always
121644       update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0]
121645   end
121646   attribute \src "ls180.v:389.11-389.43"
121647   process $proc$ls180.v:389$2899
121648     assign { } { }
121649     assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
121650     sync always
121651     sync init
121652       update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0]
121653   end
121654   attribute \src "ls180.v:3893.1-3901.4"
121655   process $proc$ls180.v:3893$365
121656     assign { } { }
121657     assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
121658     attribute \src "ls180.v:3895.2-3897.5"
121659     switch $and$ls180.v:3895$368_Y
121660       attribute \src "ls180.v:3895.6-3895.115"
121661       case 1'1
121662         assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
121663       case
121664     end
121665     attribute \src "ls180.v:3898.2-3900.5"
121666     switch $and$ls180.v:3898$371_Y
121667       attribute \src "ls180.v:3898.6-3898.115"
121668       case 1'1
121669         assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1
121670       case
121671     end
121672     sync always
121673       update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0]
121674   end
121675   attribute \src "ls180.v:390.5-390.38"
121676   process $proc$ls180.v:390$2900
121677     assign { } { }
121678     assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
121679     sync always
121680     sync init
121681       update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0]
121682   end
121683   attribute \src "ls180.v:3902.1-3910.4"
121684   process $proc$ls180.v:3902$372
121685     assign { } { }
121686     assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
121687     attribute \src "ls180.v:3904.2-3906.5"
121688     switch $and$ls180.v:3904$375_Y
121689       attribute \src "ls180.v:3904.6-3904.115"
121690       case 1'1
121691         assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
121692       case
121693     end
121694     attribute \src "ls180.v:3907.2-3909.5"
121695     switch $and$ls180.v:3907$378_Y
121696       attribute \src "ls180.v:3907.6-3907.115"
121697       case 1'1
121698         assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1
121699       case
121700     end
121701     sync always
121702       update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0]
121703   end
121704   attribute \src "ls180.v:391.5-391.38"
121705   process $proc$ls180.v:391$2901
121706     assign { } { }
121707     assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
121708     sync always
121709     sync init
121710       update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0]
121711   end
121712   attribute \src "ls180.v:3915.1-3987.4"
121713   process $proc$ls180.v:3915$381
121714     assign { } { }
121715     assign { } { }
121716     assign { } { }
121717     assign { } { }
121718     assign { } { }
121719     assign { } { }
121720     assign { } { }
121721     assign { } { }
121722     assign { } { }
121723     assign { } { }
121724     assign $0\main_sdram_steerer_sel[1:0] 2'00
121725     assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0
121726     assign $0\main_sdram_en0[0:0] 1'0
121727     assign { } { }
121728     assign $0\main_sdram_en1[0:0] 1'0
121729     assign $0\main_sdram_choose_req_want_reads[0:0] 1'0
121730     assign $0\main_sdram_choose_req_want_writes[0:0] 1'0
121731     assign $0\main_sdram_cmd_ready[0:0] 1'0
121732     assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed
121733     assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state
121734     attribute \src "ls180.v:3927.2-3986.9"
121735     switch \builder_multiplexer_state
121736       attribute \src "ls180.v:0.0-0.0"
121737       case 3'001
121738         assign $0\main_sdram_en1[0:0] 1'1
121739         assign $0\main_sdram_choose_req_want_writes[0:0] 1'1
121740         assign $0\main_sdram_steerer_sel[1:0] 2'10
121741         attribute \src "ls180.v:3931.4-3937.7"
121742         switch 1'1
121743           attribute \src "ls180.v:3931.8-3931.12"
121744           case 1'1
121745             assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3932$388_Y
121746           case
121747         end
121748         attribute \src "ls180.v:3939.4-3943.7"
121749         switch \main_sdram_read_available
121750           attribute \src "ls180.v:3939.8-3939.33"
121751           case 1'1
121752             attribute \src "ls180.v:3940.5-3942.8"
121753             switch $or$ls180.v:3940$390_Y
121754               attribute \src "ls180.v:3940.9-3940.63"
121755               case 1'1
121756                 assign $0\builder_multiplexer_next_state[2:0] 3'011
121757               case
121758             end
121759           case
121760         end
121761         attribute \src "ls180.v:3944.4-3946.7"
121762         switch \main_sdram_go_to_refresh
121763           attribute \src "ls180.v:3944.8-3944.32"
121764           case 1'1
121765             assign $0\builder_multiplexer_next_state[2:0] 3'010
121766           case
121767         end
121768       attribute \src "ls180.v:0.0-0.0"
121769       case 3'010
121770         assign $0\main_sdram_steerer_sel[1:0] 2'11
121771         assign $0\main_sdram_cmd_ready[0:0] 1'1
121772         attribute \src "ls180.v:3951.4-3953.7"
121773         switch \main_sdram_cmd_last
121774           attribute \src "ls180.v:3951.8-3951.27"
121775           case 1'1
121776             assign $0\builder_multiplexer_next_state[2:0] 3'000
121777           case
121778         end
121779       attribute \src "ls180.v:0.0-0.0"
121780       case 3'011
121781         attribute \src "ls180.v:3956.4-3958.7"
121782         switch \main_sdram_twtrcon_ready
121783           attribute \src "ls180.v:3956.8-3956.32"
121784           case 1'1
121785             assign $0\builder_multiplexer_next_state[2:0] 3'000
121786           case
121787         end
121788       attribute \src "ls180.v:0.0-0.0"
121789       case 3'100
121790         assign $0\builder_multiplexer_next_state[2:0] 3'101
121791       attribute \src "ls180.v:0.0-0.0"
121792       case 3'101
121793         assign $0\builder_multiplexer_next_state[2:0] 3'001
121794       attribute \src "ls180.v:0.0-0.0"
121795       case
121796         assign $0\main_sdram_en0[0:0] 1'1
121797         assign $0\main_sdram_choose_req_want_reads[0:0] 1'1
121798         assign $0\main_sdram_steerer_sel[1:0] 2'10
121799         attribute \src "ls180.v:3969.4-3975.7"
121800         switch 1'1
121801           attribute \src "ls180.v:3969.8-3969.12"
121802           case 1'1
121803             assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3970$397_Y
121804           case
121805         end
121806         attribute \src "ls180.v:3977.4-3981.7"
121807         switch \main_sdram_write_available
121808           attribute \src "ls180.v:3977.8-3977.34"
121809           case 1'1
121810             attribute \src "ls180.v:3978.5-3980.8"
121811             switch $or$ls180.v:3978$399_Y
121812               attribute \src "ls180.v:3978.9-3978.62"
121813               case 1'1
121814                 assign $0\builder_multiplexer_next_state[2:0] 3'100
121815               case
121816             end
121817           case
121818         end
121819         attribute \src "ls180.v:3982.4-3984.7"
121820         switch \main_sdram_go_to_refresh
121821           attribute \src "ls180.v:3982.8-3982.32"
121822           case 1'1
121823             assign $0\builder_multiplexer_next_state[2:0] 3'010
121824           case
121825         end
121826     end
121827     sync always
121828       update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0]
121829       update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0]
121830       update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0]
121831       update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0]
121832       update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0]
121833       update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0]
121834       update \main_sdram_en0 $0\main_sdram_en0[0:0]
121835       update \main_sdram_en1 $0\main_sdram_en1[0:0]
121836       update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0]
121837   end
121838   attribute \src "ls180.v:392.5-392.37"
121839   process $proc$ls180.v:392$2902
121840     assign { } { }
121841     assign $1\main_sdram_cmd_payload_we[0:0] 1'0
121842     sync always
121843     sync init
121844       update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
121845   end
121846   attribute \src "ls180.v:393.5-393.42"
121847   process $proc$ls180.v:393$2903
121848     assign { } { }
121849     assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
121850     sync always
121851       update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0]
121852     sync init
121853   end
121854   attribute \src "ls180.v:394.5-394.43"
121855   process $proc$ls180.v:394$2904
121856     assign { } { }
121857     assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
121858     sync always
121859       update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0]
121860     sync init
121861   end
121862   attribute \src "ls180.v:400.11-400.44"
121863   process $proc$ls180.v:400$2905
121864     assign { } { }
121865     assign $1\main_sdram_timer_count1[9:0] 10'1100001101
121866     sync always
121867     sync init
121868       update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0]
121869   end
121870   attribute \src "ls180.v:4011.1-4024.4"
121871   process $proc$ls180.v:4011$528
121872     assign { } { }
121873     assign { } { }
121874     assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000
121875     assign $0\main_sdram_interface_wdata_we[1:0] 2'00
121876     attribute \src "ls180.v:4014.2-4023.9"
121877     switch \builder_new_master_wdata_ready
121878       attribute \src "ls180.v:0.0-0.0"
121879       case 1'1
121880         assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data
121881         assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we
121882       attribute \src "ls180.v:0.0-0.0"
121883       case
121884         assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000
121885         assign $0\main_sdram_interface_wdata_we[1:0] 2'00
121886     end
121887     sync always
121888       update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0]
121889       update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0]
121890   end
121891   attribute \src "ls180.v:402.5-402.38"
121892   process $proc$ls180.v:402$2906
121893     assign { } { }
121894     assign $1\main_sdram_postponer_req_o[0:0] 1'0
121895     sync always
121896     sync init
121897       update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
121898   end
121899   attribute \src "ls180.v:403.5-403.38"
121900   process $proc$ls180.v:403$2907
121901     assign { } { }
121902     assign $1\main_sdram_postponer_count[0:0] 1'0
121903     sync always
121904     sync init
121905       update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0]
121906   end
121907   attribute \src "ls180.v:4031.1-4041.4"
121908   process $proc$ls180.v:4031$530
121909     assign { } { }
121910     assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000
121911     attribute \src "ls180.v:4033.2-4040.9"
121912     switch \main_converter_counter
121913       attribute \src "ls180.v:0.0-0.0"
121914       case 1'0
121915         assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0]
121916       attribute \src "ls180.v:0.0-0.0"
121917       case 1'1
121918         assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16]
121919       case
121920     end
121921     sync always
121922       update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0]
121923   end
121924   attribute \src "ls180.v:404.5-404.39"
121925   process $proc$ls180.v:404$2908
121926     assign { } { }
121927     assign $1\main_sdram_sequencer_start0[0:0] 1'0
121928     sync always
121929     sync init
121930       update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0]
121931   end
121932   attribute \src "ls180.v:4043.1-4089.4"
121933   process $proc$ls180.v:4043$531
121934     assign { } { }
121935     assign { } { }
121936     assign { } { }
121937     assign { } { }
121938     assign { } { }
121939     assign { } { }
121940     assign { } { }
121941     assign { } { }
121942     assign { } { }
121943     assign { } { }
121944     assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0
121945     assign $0\main_litedram_wb_we[0:0] 1'0
121946     assign $0\main_converter_skip[0:0] 1'0
121947     assign $0\main_wb_sdram_ack[0:0] 1'0
121948     assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
121949     assign $0\main_litedram_wb_sel[1:0] 2'00
121950     assign $0\main_litedram_wb_cyc[0:0] 1'0
121951     assign { } { }
121952     assign $0\main_litedram_wb_stb[0:0] 1'0
121953     assign $0\main_converter_counter_converter_next_value[0:0] 1'0
121954     assign $0\builder_converter_next_state[0:0] \builder_converter_state
121955     attribute \src "ls180.v:4055.2-4088.9"
121956     switch \builder_converter_state
121957       attribute \src "ls180.v:0.0-0.0"
121958       case 1'1
121959         assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter }
121960         attribute \src "ls180.v:4058.4-4065.11"
121961         switch \main_converter_counter
121962           attribute \src "ls180.v:0.0-0.0"
121963           case 1'0
121964             assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0]
121965           attribute \src "ls180.v:0.0-0.0"
121966           case 1'1
121967             assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2]
121968           case
121969         end
121970         attribute \src "ls180.v:4066.4-4079.7"
121971         switch $and$ls180.v:4066$532_Y
121972           attribute \src "ls180.v:4066.8-4066.47"
121973           case 1'1
121974             assign $0\main_converter_skip[0:0] $eq$ls180.v:4067$533_Y
121975             assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we
121976             assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4069$534_Y
121977             assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4070$535_Y
121978             attribute \src "ls180.v:4071.5-4078.8"
121979             switch $or$ls180.v:4071$536_Y
121980               attribute \src "ls180.v:4071.9-4071.53"
121981               case 1'1
121982                 assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4072$537_Y
121983                 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
121984                 attribute \src "ls180.v:4074.6-4077.9"
121985                 switch $eq$ls180.v:4074$538_Y
121986                   attribute \src "ls180.v:4074.10-4074.42"
121987                   case 1'1
121988                     assign $0\main_wb_sdram_ack[0:0] 1'1
121989                     assign $0\builder_converter_next_state[0:0] 1'0
121990                   case
121991                 end
121992               case
121993             end
121994           case
121995         end
121996       attribute \src "ls180.v:0.0-0.0"
121997       case
121998         assign $0\main_converter_counter_converter_next_value[0:0] 1'0
121999         assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1
122000         attribute \src "ls180.v:4084.4-4086.7"
122001         switch $and$ls180.v:4084$539_Y
122002           attribute \src "ls180.v:4084.8-4084.47"
122003           case 1'1
122004             assign $0\builder_converter_next_state[0:0] 1'1
122005           case
122006         end
122007     end
122008     sync always
122009       update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0]
122010       update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0]
122011       update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0]
122012       update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0]
122013       update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0]
122014       update \main_litedram_wb_we $0\main_litedram_wb_we[0:0]
122015       update \main_converter_skip $0\main_converter_skip[0:0]
122016       update \builder_converter_next_state $0\builder_converter_next_state[0:0]
122017       update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0]
122018       update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0]
122019   end
122020   attribute \src "ls180.v:407.5-407.38"
122021   process $proc$ls180.v:407$2909
122022     assign { } { }
122023     assign $1\main_sdram_sequencer_done1[0:0] 1'0
122024     sync always
122025     sync init
122026       update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
122027   end
122028   attribute \src "ls180.v:408.11-408.46"
122029   process $proc$ls180.v:408$2910
122030     assign { } { }
122031     assign $1\main_sdram_sequencer_counter[3:0] 4'0000
122032     sync always
122033     sync init
122034       update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
122035   end
122036   attribute \src "ls180.v:409.5-409.38"
122037   process $proc$ls180.v:409$2911
122038     assign { } { }
122039     assign $1\main_sdram_sequencer_count[0:0] 1'0
122040     sync always
122041     sync init
122042       update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0]
122043   end
122044   attribute \src "ls180.v:4134.1-4139.4"
122045   process $proc$ls180.v:4134$571
122046     assign { } { }
122047     assign $0\main_uart_tx_clear[0:0] 1'0
122048     attribute \src "ls180.v:4136.2-4138.5"
122049     switch $and$ls180.v:4136$572_Y
122050       attribute \src "ls180.v:4136.6-4136.79"
122051       case 1'1
122052         assign $0\main_uart_tx_clear[0:0] 1'1
122053       case
122054     end
122055     sync always
122056       update \main_uart_tx_clear $0\main_uart_tx_clear[0:0]
122057   end
122058   attribute \src "ls180.v:4140.1-4144.4"
122059   process $proc$ls180.v:4140$573
122060     assign { } { }
122061     assign { } { }
122062     assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status
122063     assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status
122064     sync always
122065       update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0]
122066   end
122067   attribute \src "ls180.v:4145.1-4150.4"
122068   process $proc$ls180.v:4145$574
122069     assign { } { }
122070     assign $0\main_uart_rx_clear[0:0] 1'0
122071     attribute \src "ls180.v:4147.2-4149.5"
122072     switch $and$ls180.v:4147$575_Y
122073       attribute \src "ls180.v:4147.6-4147.79"
122074       case 1'1
122075         assign $0\main_uart_rx_clear[0:0] 1'1
122076       case
122077     end
122078     sync always
122079       update \main_uart_rx_clear $0\main_uart_rx_clear[0:0]
122080   end
122081   attribute \src "ls180.v:415.5-415.51"
122082   process $proc$ls180.v:415$2912
122083     assign { } { }
122084     assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
122085     sync always
122086     sync init
122087       update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0]
122088   end
122089   attribute \src "ls180.v:4151.1-4155.4"
122090   process $proc$ls180.v:4151$576
122091     assign { } { }
122092     assign { } { }
122093     assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending
122094     assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending
122095     sync always
122096       update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0]
122097   end
122098   attribute \src "ls180.v:416.5-416.51"
122099   process $proc$ls180.v:416$2913
122100     assign { } { }
122101     assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
122102     sync always
122103     sync init
122104       update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0]
122105   end
122106   attribute \src "ls180.v:4173.1-4180.4"
122107   process $proc$ls180.v:4173$584
122108     assign { } { }
122109     assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
122110     attribute \src "ls180.v:4175.2-4179.5"
122111     switch \main_uart_tx_fifo_replace
122112       attribute \src "ls180.v:4175.6-4175.31"
122113       case 1'1
122114         assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4176$585_Y
122115       attribute \src "ls180.v:4177.6-4177.10"
122116       case
122117         assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce
122118     end
122119     sync always
122120       update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0]
122121   end
122122   attribute \src "ls180.v:418.5-418.47"
122123   process $proc$ls180.v:418$2914
122124     assign { } { }
122125     assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
122126     sync always
122127     sync init
122128       update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
122129   end
122130   attribute \src "ls180.v:419.5-419.45"
122131   process $proc$ls180.v:419$2915
122132     assign { } { }
122133     assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
122134     sync always
122135     sync init
122136       update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
122137   end
122138   attribute \src "ls180.v:420.5-420.45"
122139   process $proc$ls180.v:420$2916
122140     assign { } { }
122141     assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
122142     sync always
122143     sync init
122144       update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0]
122145   end
122146   attribute \src "ls180.v:4203.1-4210.4"
122147   process $proc$ls180.v:4203$595
122148     assign { } { }
122149     assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
122150     attribute \src "ls180.v:4205.2-4209.5"
122151     switch \main_uart_rx_fifo_replace
122152       attribute \src "ls180.v:4205.6-4205.31"
122153       case 1'1
122154         assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4206$596_Y
122155       attribute \src "ls180.v:4207.6-4207.10"
122156       case
122157         assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce
122158     end
122159     sync always
122160       update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0]
122161   end
122162   attribute \src "ls180.v:421.12-421.57"
122163   process $proc$ls180.v:421$2917
122164     assign { } { }
122165     assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
122166     sync always
122167     sync init
122168       update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
122169   end
122170   attribute \src "ls180.v:423.5-423.51"
122171   process $proc$ls180.v:423$2918
122172     assign { } { }
122173     assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
122174     sync always
122175     sync init
122176       update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0]
122177   end
122178   attribute \src "ls180.v:4233.1-4281.4"
122179   process $proc$ls180.v:4233$606
122180     assign { } { }
122181     assign { } { }
122182     assign { } { }
122183     assign { } { }
122184     assign { } { }
122185     assign { } { }
122186     assign { } { }
122187     assign { } { }
122188     assign { } { }
122189     assign $0\main_spimaster25_clk_enable[0:0] 1'0
122190     assign $0\main_spimaster26_cs_enable[0:0] 1'0
122191     assign $0\main_spimaster28_mosi_latch[0:0] 1'0
122192     assign $0\main_spimaster2_done[0:0] 1'0
122193     assign $0\main_spimaster29_miso_latch[0:0] 1'0
122194     assign $0\main_spimaster3_irq[0:0] 1'0
122195     assign { } { }
122196     assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
122197     assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
122198     assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state
122199     attribute \src "ls180.v:4244.2-4280.9"
122200     switch \builder_spimaster0_state
122201       attribute \src "ls180.v:0.0-0.0"
122202       case 2'01
122203         assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
122204         assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1
122205         attribute \src "ls180.v:4248.4-4251.7"
122206         switch \main_spimaster32_clk_fall
122207           attribute \src "ls180.v:4248.8-4248.33"
122208           case 1'1
122209             assign $0\main_spimaster26_cs_enable[0:0] 1'1
122210             assign $0\builder_spimaster0_next_state[1:0] 2'10
122211           case
122212         end
122213       attribute \src "ls180.v:0.0-0.0"
122214       case 2'10
122215         assign $0\main_spimaster25_clk_enable[0:0] 1'1
122216         assign $0\main_spimaster26_cs_enable[0:0] 1'1
122217         attribute \src "ls180.v:4256.4-4262.7"
122218         switch \main_spimaster32_clk_fall
122219           attribute \src "ls180.v:4256.8-4256.33"
122220           case 1'1
122221             assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4257$607_Y
122222             assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1
122223             attribute \src "ls180.v:4259.5-4261.8"
122224             switch $eq$ls180.v:4259$609_Y
122225               attribute \src "ls180.v:4259.9-4259.68"
122226               case 1'1
122227                 assign $0\builder_spimaster0_next_state[1:0] 2'11
122228               case
122229             end
122230           case
122231         end
122232       attribute \src "ls180.v:0.0-0.0"
122233       case 2'11
122234         assign $0\main_spimaster26_cs_enable[0:0] 1'1
122235         attribute \src "ls180.v:4266.4-4270.7"
122236         switch \main_spimaster31_clk_rise
122237           attribute \src "ls180.v:4266.8-4266.33"
122238           case 1'1
122239             assign $0\main_spimaster29_miso_latch[0:0] 1'1
122240             assign $0\main_spimaster3_irq[0:0] 1'1
122241             assign $0\builder_spimaster0_next_state[1:0] 2'00
122242           case
122243         end
122244       attribute \src "ls180.v:0.0-0.0"
122245       case
122246         assign $0\main_spimaster2_done[0:0] 1'1
122247         attribute \src "ls180.v:4274.4-4278.7"
122248         switch \main_spimaster0_start
122249           attribute \src "ls180.v:4274.8-4274.29"
122250           case 1'1
122251             assign $0\main_spimaster2_done[0:0] 1'0
122252             assign $0\main_spimaster28_mosi_latch[0:0] 1'1
122253             assign $0\builder_spimaster0_next_state[1:0] 2'01
122254           case
122255         end
122256     end
122257     sync always
122258       update \main_spimaster2_done $0\main_spimaster2_done[0:0]
122259       update \main_spimaster3_irq $0\main_spimaster3_irq[0:0]
122260       update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0]
122261       update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0]
122262       update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0]
122263       update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0]
122264       update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0]
122265       update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0]
122266       update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
122267   end
122268   attribute \src "ls180.v:424.5-424.51"
122269   process $proc$ls180.v:424$2919
122270     assign { } { }
122271     assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
122272     sync always
122273     sync init
122274       update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
122275   end
122276   attribute \src "ls180.v:425.5-425.50"
122277   process $proc$ls180.v:425$2920
122278     assign { } { }
122279     assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
122280     sync always
122281     sync init
122282       update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
122283   end
122284   attribute \src "ls180.v:426.5-426.54"
122285   process $proc$ls180.v:426$2921
122286     assign { } { }
122287     assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
122288     sync always
122289     sync init
122290       update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
122291   end
122292   attribute \src "ls180.v:427.5-427.55"
122293   process $proc$ls180.v:427$2922
122294     assign { } { }
122295     assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
122296     sync always
122297     sync init
122298       update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
122299   end
122300   attribute \src "ls180.v:428.5-428.56"
122301   process $proc$ls180.v:428$2923
122302     assign { } { }
122303     assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
122304     sync always
122305     sync init
122306       update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
122307   end
122308   attribute \src "ls180.v:429.5-429.50"
122309   process $proc$ls180.v:429$2924
122310     assign { } { }
122311     assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
122312     sync always
122313     sync init
122314       update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0]
122315   end
122316   attribute \src "ls180.v:4292.1-4340.4"
122317   process $proc$ls180.v:4292$614
122318     assign { } { }
122319     assign { } { }
122320     assign { } { }
122321     assign { } { }
122322     assign { } { }
122323     assign { } { }
122324     assign { } { }
122325     assign { } { }
122326     assign { } { }
122327     assign $0\main_spisdcard_clk_enable[0:0] 1'0
122328     assign $0\main_spisdcard_cs_enable[0:0] 1'0
122329     assign $0\main_spisdcard_mosi_latch[0:0] 1'0
122330     assign { } { }
122331     assign $0\main_spisdcard_done0[0:0] 1'0
122332     assign $0\main_spisdcard_miso_latch[0:0] 1'0
122333     assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
122334     assign $0\main_spisdcard_irq[0:0] 1'0
122335     assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
122336     assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state
122337     attribute \src "ls180.v:4303.2-4339.9"
122338     switch \builder_spimaster1_state
122339       attribute \src "ls180.v:0.0-0.0"
122340       case 2'01
122341         assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
122342         assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1
122343         attribute \src "ls180.v:4307.4-4310.7"
122344         switch \main_spisdcard_clk_fall
122345           attribute \src "ls180.v:4307.8-4307.31"
122346           case 1'1
122347             assign $0\main_spisdcard_cs_enable[0:0] 1'1
122348             assign $0\builder_spimaster1_next_state[1:0] 2'10
122349           case
122350         end
122351       attribute \src "ls180.v:0.0-0.0"
122352       case 2'10
122353         assign $0\main_spisdcard_clk_enable[0:0] 1'1
122354         assign $0\main_spisdcard_cs_enable[0:0] 1'1
122355         attribute \src "ls180.v:4315.4-4321.7"
122356         switch \main_spisdcard_clk_fall
122357           attribute \src "ls180.v:4315.8-4315.31"
122358           case 1'1
122359             assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4316$615_Y
122360             assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1
122361             attribute \src "ls180.v:4318.5-4320.8"
122362             switch $eq$ls180.v:4318$617_Y
122363               attribute \src "ls180.v:4318.9-4318.66"
122364               case 1'1
122365                 assign $0\builder_spimaster1_next_state[1:0] 2'11
122366               case
122367             end
122368           case
122369         end
122370       attribute \src "ls180.v:0.0-0.0"
122371       case 2'11
122372         assign $0\main_spisdcard_cs_enable[0:0] 1'1
122373         attribute \src "ls180.v:4325.4-4329.7"
122374         switch \main_spisdcard_clk_rise
122375           attribute \src "ls180.v:4325.8-4325.31"
122376           case 1'1
122377             assign $0\main_spisdcard_miso_latch[0:0] 1'1
122378             assign $0\main_spisdcard_irq[0:0] 1'1
122379             assign $0\builder_spimaster1_next_state[1:0] 2'00
122380           case
122381         end
122382       attribute \src "ls180.v:0.0-0.0"
122383       case
122384         assign $0\main_spisdcard_done0[0:0] 1'1
122385         attribute \src "ls180.v:4333.4-4337.7"
122386         switch \main_spisdcard_start0
122387           attribute \src "ls180.v:4333.8-4333.29"
122388           case 1'1
122389             assign $0\main_spisdcard_done0[0:0] 1'0
122390             assign $0\main_spisdcard_mosi_latch[0:0] 1'1
122391             assign $0\builder_spimaster1_next_state[1:0] 2'01
122392           case
122393         end
122394     end
122395     sync always
122396       update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0]
122397       update \main_spisdcard_irq $0\main_spisdcard_irq[0:0]
122398       update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0]
122399       update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0]
122400       update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0]
122401       update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0]
122402       update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0]
122403       update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0]
122404       update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
122405   end
122406   attribute \src "ls180.v:432.5-432.67"
122407   process $proc$ls180.v:432$2925
122408     assign { } { }
122409     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
122410     sync always
122411       update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
122412     sync init
122413   end
122414   attribute \src "ls180.v:433.5-433.66"
122415   process $proc$ls180.v:433$2926
122416     assign { } { }
122417     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
122418     sync always
122419       update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
122420     sync init
122421   end
122422   attribute \src "ls180.v:4372.1-4400.4"
122423   process $proc$ls180.v:4372$639
122424     assign { } { }
122425     assign $0\main_sdphy_clocker_clk1[0:0] 1'0
122426     attribute \src "ls180.v:4374.2-4399.9"
122427     switch \main_sdphy_clocker_storage
122428       attribute \src "ls180.v:0.0-0.0"
122429       case 9'000000100
122430         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1]
122431       attribute \src "ls180.v:0.0-0.0"
122432       case 9'000001000
122433         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2]
122434       attribute \src "ls180.v:0.0-0.0"
122435       case 9'000010000
122436         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3]
122437       attribute \src "ls180.v:0.0-0.0"
122438       case 9'000100000
122439         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4]
122440       attribute \src "ls180.v:0.0-0.0"
122441       case 9'001000000
122442         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5]
122443       attribute \src "ls180.v:0.0-0.0"
122444       case 9'010000000
122445         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6]
122446       attribute \src "ls180.v:0.0-0.0"
122447       case 9'100000000
122448         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7]
122449       attribute \src "ls180.v:0.0-0.0"
122450       case
122451         assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0]
122452     end
122453     sync always
122454       update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0]
122455   end
122456   attribute \src "ls180.v:4402.1-4435.4"
122457   process $proc$ls180.v:4402$642
122458     assign { } { }
122459     assign { } { }
122460     assign { } { }
122461     assign { } { }
122462     assign { } { }
122463     assign { } { }
122464     assign { } { }
122465     assign { } { }
122466     assign { } { }
122467     assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
122468     assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
122469     assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
122470     assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
122471     assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
122472     assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
122473     assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
122474     assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state
122475     attribute \src "ls180.v:4412.2-4434.9"
122476     switch \builder_sdphy_sdphyinit_state
122477       attribute \src "ls180.v:0.0-0.0"
122478       case 1'1
122479         assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1
122480         assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1
122481         assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1
122482         assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1
122483         assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111
122484         attribute \src "ls180.v:4419.4-4425.7"
122485         switch \main_sdphy_init_pads_out_ready
122486           attribute \src "ls180.v:4419.8-4419.38"
122487           case 1'1
122488             assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4420$643_Y
122489             assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
122490             attribute \src "ls180.v:4422.5-4424.8"
122491             switch $eq$ls180.v:4422$644_Y
122492               attribute \src "ls180.v:4422.9-4422.41"
122493               case 1'1
122494                 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0
122495               case
122496             end
122497           case
122498         end
122499       attribute \src "ls180.v:0.0-0.0"
122500       case
122501         assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
122502         assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1
122503         attribute \src "ls180.v:4430.4-4432.7"
122504         switch \main_sdphy_init_initialize_re
122505           attribute \src "ls180.v:4430.8-4430.37"
122506           case 1'1
122507             assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1
122508           case
122509         end
122510     end
122511     sync always
122512       update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0]
122513       update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0]
122514       update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
122515       update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0]
122516       update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0]
122517       update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0]
122518       update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
122519       update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
122520   end
122521   attribute \src "ls180.v:4436.1-4512.4"
122522   process $proc$ls180.v:4436$645
122523     assign { } { }
122524     assign { } { }
122525     assign { } { }
122526     assign { } { }
122527     assign { } { }
122528     assign { } { }
122529     assign { } { }
122530     assign { } { }
122531     assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
122532     assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
122533     assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
122534     assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
122535     assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0
122536     assign $0\main_sdphy_cmdw_done[0:0] 1'0
122537     assign { } { }
122538     assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
122539     assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state
122540     attribute \src "ls180.v:4446.2-4511.9"
122541     switch \builder_sdphy_sdphycmdw_state
122542       attribute \src "ls180.v:0.0-0.0"
122543       case 2'01
122544         assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
122545         assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
122546         attribute \src "ls180.v:4450.4-4475.11"
122547         switch \main_sdphy_cmdw_count
122548           attribute \src "ls180.v:0.0-0.0"
122549           case 8'00000000
122550             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7]
122551           attribute \src "ls180.v:0.0-0.0"
122552           case 8'00000001
122553             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6]
122554           attribute \src "ls180.v:0.0-0.0"
122555           case 8'00000010
122556             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5]
122557           attribute \src "ls180.v:0.0-0.0"
122558           case 8'00000011
122559             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4]
122560           attribute \src "ls180.v:0.0-0.0"
122561           case 8'00000100
122562             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3]
122563           attribute \src "ls180.v:0.0-0.0"
122564           case 8'00000101
122565             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2]
122566           attribute \src "ls180.v:0.0-0.0"
122567           case 8'00000110
122568             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1]
122569           attribute \src "ls180.v:0.0-0.0"
122570           case 8'00000111
122571             assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0]
122572           case
122573         end
122574         attribute \src "ls180.v:4476.4-4487.7"
122575         switch \main_sdphy_cmdw_pads_out_ready
122576           attribute \src "ls180.v:4476.8-4476.38"
122577           case 1'1
122578             assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4477$646_Y
122579             assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
122580             attribute \src "ls180.v:4479.5-4486.8"
122581             switch $eq$ls180.v:4479$647_Y
122582               attribute \src "ls180.v:4479.9-4479.40"
122583               case 1'1
122584                 attribute \src "ls180.v:4480.6-4485.9"
122585                 switch \main_sdphy_cmdw_sink_last
122586                   attribute \src "ls180.v:4480.10-4480.35"
122587                   case 1'1
122588                     assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10
122589                   attribute \src "ls180.v:4482.10-4482.14"
122590                   case
122591                     assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
122592                     assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
122593                 end
122594               case
122595             end
122596           case
122597         end
122598       attribute \src "ls180.v:0.0-0.0"
122599       case 2'10
122600         assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1
122601         assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1
122602         assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1
122603         attribute \src "ls180.v:4493.4-4500.7"
122604         switch \main_sdphy_cmdw_pads_out_ready
122605           attribute \src "ls180.v:4493.8-4493.38"
122606           case 1'1
122607             assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4494$648_Y
122608             assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
122609             attribute \src "ls180.v:4496.5-4499.8"
122610             switch $eq$ls180.v:4496$649_Y
122611               attribute \src "ls180.v:4496.9-4496.40"
122612               case 1'1
122613                 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1
122614                 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
122615               case
122616             end
122617           case
122618         end
122619       attribute \src "ls180.v:0.0-0.0"
122620       case
122621         assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
122622         assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1
122623         attribute \src "ls180.v:4505.4-4509.7"
122624         switch $and$ls180.v:4505$650_Y
122625           attribute \src "ls180.v:4505.8-4505.69"
122626           case 1'1
122627             assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01
122628           attribute \src "ls180.v:4507.8-4507.12"
122629           case
122630             assign $0\main_sdphy_cmdw_done[0:0] 1'1
122631         end
122632     end
122633     sync always
122634       update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0]
122635       update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
122636       update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
122637       update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0]
122638       update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0]
122639       update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0]
122640       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
122641       update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
122642   end
122643   attribute \src "ls180.v:448.11-448.68"
122644   process $proc$ls180.v:448$2927
122645     assign { } { }
122646     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
122647     sync always
122648     sync init
122649       update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
122650   end
122651   attribute \src "ls180.v:449.5-449.64"
122652   process $proc$ls180.v:449$2928
122653     assign { } { }
122654     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
122655     sync always
122656       update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
122657     sync init
122658   end
122659   attribute \src "ls180.v:450.11-450.70"
122660   process $proc$ls180.v:450$2929
122661     assign { } { }
122662     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
122663     sync always
122664     sync init
122665       update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
122666   end
122667   attribute \src "ls180.v:451.11-451.70"
122668   process $proc$ls180.v:451$2930
122669     assign { } { }
122670     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
122671     sync always
122672     sync init
122673       update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
122674   end
122675   attribute \src "ls180.v:452.11-452.73"
122676   process $proc$ls180.v:452$2931
122677     assign { } { }
122678     assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
122679     sync always
122680     sync init
122681       update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
122682   end
122683   attribute \src "ls180.v:4546.1-4639.4"
122684   process $proc$ls180.v:4546$659
122685     assign { } { }
122686     assign { } { }
122687     assign { } { }
122688     assign { } { }
122689     assign { } { }
122690     assign { } { }
122691     assign { } { }
122692     assign { } { }
122693     assign { } { }
122694     assign { } { }
122695     assign { } { }
122696     assign { } { }
122697     assign { } { }
122698     assign { } { }
122699     assign { } { }
122700     assign { } { }
122701     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
122702     assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
122703     assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
122704     assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
122705     assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
122706     assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
122707     assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
122708     assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
122709     assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
122710     assign { } { }
122711     assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0
122712     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
122713     assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0
122714     assign $0\main_sdphy_cmdr_source_last[0:0] 1'0
122715     assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
122716     assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
122717     assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state
122718     attribute \src "ls180.v:4564.2-4638.9"
122719     switch \builder_sdphy_sdphycmdr_state
122720       attribute \src "ls180.v:0.0-0.0"
122721       case 3'001
122722         assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
122723         assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
122724         assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
122725         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4572$660_Y
122726         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
122727         attribute \src "ls180.v:4569.4-4571.7"
122728         switch \main_sdphy_cmdr_cmdr_source_source_valid0
122729           attribute \src "ls180.v:4569.8-4569.49"
122730           case 1'1
122731             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010
122732           case
122733         end
122734         attribute \src "ls180.v:4574.4-4577.7"
122735         switch $eq$ls180.v:4574$661_Y
122736           attribute \src "ls180.v:4574.8-4574.41"
122737           case 1'1
122738             assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
122739             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
122740           case
122741         end
122742       attribute \src "ls180.v:0.0-0.0"
122743       case 3'010
122744         assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
122745         assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0
122746         assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000
122747         assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4583$663_Y
122748         assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0
122749         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4600$666_Y
122750         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
122751         attribute \src "ls180.v:4585.4-4599.7"
122752         switch $and$ls180.v:4585$664_Y
122753           attribute \src "ls180.v:4585.8-4585.69"
122754           case 1'1
122755             assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1
122756             assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4587$665_Y
122757             assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
122758             attribute \src "ls180.v:4589.5-4598.8"
122759             switch \main_sdphy_cmdr_source_last
122760               attribute \src "ls180.v:4589.9-4589.36"
122761               case 1'1
122762                 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
122763                 attribute \src "ls180.v:4591.6-4597.9"
122764                 switch \main_sdphy_cmdr_sink_last
122765                   attribute \src "ls180.v:4591.10-4591.35"
122766                   case 1'1
122767                     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
122768                     assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
122769                     assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011
122770                   attribute \src "ls180.v:4595.10-4595.14"
122771                   case
122772                     assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
122773                 end
122774               case
122775             end
122776           case
122777         end
122778         attribute \src "ls180.v:4602.4-4605.7"
122779         switch $eq$ls180.v:4602$667_Y
122780           attribute \src "ls180.v:4602.8-4602.41"
122781           case 1'1
122782             assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1
122783             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100
122784           case
122785         end
122786       attribute \src "ls180.v:0.0-0.0"
122787       case 3'011
122788         assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1
122789         assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1
122790         assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1
122791         attribute \src "ls180.v:4611.4-4617.7"
122792         switch \main_sdphy_cmdr_pads_out_ready
122793           attribute \src "ls180.v:4611.8-4611.38"
122794           case 1'1
122795             assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4612$668_Y
122796             assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
122797             attribute \src "ls180.v:4614.5-4616.8"
122798             switch $eq$ls180.v:4614$669_Y
122799               attribute \src "ls180.v:4614.9-4614.40"
122800               case 1'1
122801                 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
122802               case
122803             end
122804           case
122805         end
122806       attribute \src "ls180.v:0.0-0.0"
122807       case 3'100
122808         assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1
122809         assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001
122810         assign $0\main_sdphy_cmdr_source_last[0:0] 1'1
122811         attribute \src "ls180.v:4623.4-4625.7"
122812         switch $and$ls180.v:4623$670_Y
122813           attribute \src "ls180.v:4623.8-4623.69"
122814           case 1'1
122815             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
122816           case
122817         end
122818       attribute \src "ls180.v:0.0-0.0"
122819       case
122820         assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
122821         assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1
122822         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000
122823         assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1
122824         attribute \src "ls180.v:4632.4-4636.7"
122825         switch $and$ls180.v:4632$672_Y
122826           attribute \src "ls180.v:4632.8-4632.94"
122827           case 1'1
122828             assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1
122829             assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1
122830             assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001
122831           case
122832         end
122833     end
122834     sync always
122835       update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0]
122836       update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
122837       update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
122838       update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0]
122839       update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0]
122840       update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0]
122841       update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0]
122842       update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0]
122843       update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0]
122844       update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0]
122845       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
122846       update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
122847       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
122848       update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
122849       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
122850       update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
122851   end
122852   attribute \src "ls180.v:4673.1-4700.4"
122853   process $proc$ls180.v:4673$680
122854     assign { } { }
122855     assign { } { }
122856     assign { } { }
122857     assign { } { }
122858     assign { } { }
122859     assign { } { }
122860     assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
122861     assign { } { }
122862     assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
122863     assign $0\main_sdphy_dataw_valid[0:0] 1'0
122864     assign $0\main_sdphy_dataw_error[0:0] 1'0
122865     assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
122866     assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state
122867     attribute \src "ls180.v:4681.2-4699.9"
122868     switch \builder_sdphy_sdphycrcr_state
122869       attribute \src "ls180.v:0.0-0.0"
122870       case 1'1
122871         assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
122872         assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
122873         assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1
122874         attribute \src "ls180.v:4686.4-4690.7"
122875         switch \main_sdphy_dataw_crcr_source_source_valid0
122876           attribute \src "ls180.v:4686.8-4686.50"
122877           case 1'1
122878             assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4687$681_Y
122879             assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4688$682_Y
122880             assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
122881           case
122882         end
122883       attribute \src "ls180.v:0.0-0.0"
122884       case
122885         attribute \src "ls180.v:4693.4-4697.7"
122886         switch \main_sdphy_dataw_start
122887           attribute \src "ls180.v:4693.8-4693.30"
122888           case 1'1
122889             assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1
122890             assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1
122891             assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1
122892           case
122893         end
122894     end
122895     sync always
122896       update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0]
122897       update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0]
122898       update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0]
122899       update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0]
122900       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
122901       update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
122902   end
122903   attribute \src "ls180.v:4701.1-4773.4"
122904   process $proc$ls180.v:4701$683
122905     assign { } { }
122906     assign { } { }
122907     assign { } { }
122908     assign { } { }
122909     assign { } { }
122910     assign { } { }
122911     assign { } { }
122912     assign { } { }
122913     assign { } { }
122914     assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0
122915     assign $0\main_sdphy_dataw_start[0:0] 1'0
122916     assign { } { }
122917     assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
122918     assign $0\main_sdphy_dataw_stop[0:0] 1'0
122919     assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
122920     assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
122921     assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
122922     assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
122923     assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state
122924     attribute \src "ls180.v:4712.2-4772.9"
122925     switch \builder_sdphy_fsm_state
122926       attribute \src "ls180.v:0.0-0.0"
122927       case 3'001
122928         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
122929         assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
122930         assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
122931         attribute \src "ls180.v:4717.4-4719.7"
122932         switch \main_sdphy_dataw_pads_out_ready
122933           attribute \src "ls180.v:4717.8-4717.39"
122934           case 1'1
122935             assign $0\builder_sdphy_fsm_next_state[2:0] 3'010
122936           case
122937         end
122938       attribute \src "ls180.v:0.0-0.0"
122939       case 3'010
122940         assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4722$684_Y
122941         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
122942         assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
122943         attribute \src "ls180.v:4725.4-4732.11"
122944         switch \main_sdphy_dataw_count
122945           attribute \src "ls180.v:0.0-0.0"
122946           case 8'00000000
122947             assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4]
122948           attribute \src "ls180.v:0.0-0.0"
122949           case 8'00000001
122950             assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0]
122951           case
122952         end
122953         attribute \src "ls180.v:4733.4-4745.7"
122954         switch \main_sdphy_dataw_pads_out_ready
122955           attribute \src "ls180.v:4733.8-4733.39"
122956           case 1'1
122957             assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4734$685_Y
122958             assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
122959             attribute \src "ls180.v:4736.5-4744.8"
122960             switch $eq$ls180.v:4736$686_Y
122961               attribute \src "ls180.v:4736.9-4736.41"
122962               case 1'1
122963                 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
122964                 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
122965                 attribute \src "ls180.v:4739.6-4743.9"
122966                 switch \main_sdphy_dataw_sink_last
122967                   attribute \src "ls180.v:4739.10-4739.36"
122968                   case 1'1
122969                     assign $0\builder_sdphy_fsm_next_state[2:0] 3'011
122970                   attribute \src "ls180.v:4741.10-4741.14"
122971                   case
122972                     assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
122973                 end
122974               case
122975             end
122976           case
122977         end
122978       attribute \src "ls180.v:0.0-0.0"
122979       case 3'011
122980         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
122981         assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1
122982         assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111
122983         attribute \src "ls180.v:4751.4-4754.7"
122984         switch \main_sdphy_dataw_pads_out_ready
122985           attribute \src "ls180.v:4751.8-4751.39"
122986           case 1'1
122987             assign $0\main_sdphy_dataw_start[0:0] 1'1
122988             assign $0\builder_sdphy_fsm_next_state[2:0] 3'100
122989           case
122990         end
122991       attribute \src "ls180.v:0.0-0.0"
122992       case 3'100
122993         assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1
122994         attribute \src "ls180.v:4758.4-4763.7"
122995         switch \main_sdphy_dataw_pads_out_ready
122996           attribute \src "ls180.v:4758.8-4758.39"
122997           case 1'1
122998             attribute \src "ls180.v:4759.5-4762.8"
122999             switch \main_sdphy_dataw_pads_in_payload_data_i [0]
123000               attribute \src "ls180.v:4759.9-4759.51"
123001               case 1'1
123002                 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1
123003                 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000
123004               case
123005             end
123006           case
123007         end
123008       attribute \src "ls180.v:0.0-0.0"
123009       case
123010         assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
123011         assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1
123012         attribute \src "ls180.v:4768.4-4770.7"
123013         switch $and$ls180.v:4768$687_Y
123014           attribute \src "ls180.v:4768.8-4768.71"
123015           case 1'1
123016             assign $0\builder_sdphy_fsm_next_state[2:0] 3'001
123017           case
123018         end
123019     end
123020     sync always
123021       update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0]
123022       update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0]
123023       update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
123024       update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0]
123025       update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0]
123026       update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0]
123027       update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0]
123028       update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
123029       update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
123030   end
123031   attribute \src "ls180.v:473.5-473.59"
123032   process $proc$ls180.v:473$2932
123033     assign { } { }
123034     assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
123035     sync always
123036     sync init
123037       update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
123038   end
123039   attribute \src "ls180.v:475.5-475.59"
123040   process $proc$ls180.v:475$2933
123041     assign { } { }
123042     assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
123043     sync always
123044     sync init
123045       update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
123046   end
123047   attribute \src "ls180.v:476.5-476.58"
123048   process $proc$ls180.v:476$2934
123049     assign { } { }
123050     assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
123051     sync always
123052     sync init
123053       update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
123054   end
123055   attribute \src "ls180.v:477.5-477.64"
123056   process $proc$ls180.v:477$2935
123057     assign { } { }
123058     assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
123059     sync always
123060     sync init
123061       update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
123062   end
123063   attribute \src "ls180.v:478.12-478.74"
123064   process $proc$ls180.v:478$2936
123065     assign { } { }
123066     assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
123067     sync always
123068     sync init
123069       update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
123070   end
123071   attribute \src "ls180.v:479.12-479.47"
123072   process $proc$ls180.v:479$2937
123073     assign { } { }
123074     assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
123075     sync always
123076     sync init
123077       update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
123078   end
123079   attribute \src "ls180.v:480.5-480.46"
123080   process $proc$ls180.v:480$2938
123081     assign { } { }
123082     assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
123083     sync always
123084     sync init
123085       update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0]
123086   end
123087   attribute \src "ls180.v:4807.1-4908.4"
123088   process $proc$ls180.v:4807$695
123089     assign { } { }
123090     assign { } { }
123091     assign { } { }
123092     assign { } { }
123093     assign { } { }
123094     assign { } { }
123095     assign { } { }
123096     assign { } { }
123097     assign { } { }
123098     assign { } { }
123099     assign { } { }
123100     assign { } { }
123101     assign { } { }
123102     assign { } { }
123103     assign { } { }
123104     assign $0\main_sdphy_datar_sink_ready[0:0] 1'0
123105     assign { } { }
123106     assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
123107     assign $0\main_sdphy_datar_source_valid[0:0] 1'0
123108     assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
123109     assign $0\main_sdphy_datar_source_last[0:0] 1'0
123110     assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
123111     assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
123112     assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
123113     assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
123114     assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000
123115     assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
123116     assign $0\main_sdphy_datar_stop[0:0] 1'0
123117     assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
123118     assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
123119     assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state
123120     attribute \src "ls180.v:4824.2-4907.9"
123121     switch \builder_sdphy_sdphydatar_state
123122       attribute \src "ls180.v:0.0-0.0"
123123       case 3'001
123124         assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
123125         assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
123126         assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1
123127         assign { } { }
123128         assign { } { }
123129         assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4834$697_Y
123130         assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
123131         attribute \src "ls180.v:4831.4-4833.7"
123132         switch \main_sdphy_datar_datar_source_source_valid0
123133           attribute \src "ls180.v:4831.8-4831.51"
123134           case 1'1
123135             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010
123136           case
123137         end
123138         attribute \src "ls180.v:4836.4-4839.7"
123139         switch $eq$ls180.v:4836$698_Y
123140           attribute \src "ls180.v:4836.8-4836.42"
123141           case 1'1
123142             assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
123143             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
123144           case
123145         end
123146       attribute \src "ls180.v:0.0-0.0"
123147       case 3'010
123148         assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
123149         assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0
123150         assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000
123151         assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4845$701_Y
123152         assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0
123153         assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4866$703_Y
123154         assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
123155         attribute \src "ls180.v:4847.4-4865.7"
123156         switch \main_sdphy_datar_source_valid
123157           attribute \src "ls180.v:4847.8-4847.37"
123158           case 1'1
123159             attribute \src "ls180.v:4848.5-4864.8"
123160             switch \main_sdphy_datar_source_ready
123161               attribute \src "ls180.v:4848.9-4848.38"
123162               case 1'1
123163                 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1
123164                 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4850$702_Y
123165                 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
123166                 attribute \src "ls180.v:4852.6-4861.9"
123167                 switch \main_sdphy_datar_source_last
123168                   attribute \src "ls180.v:4852.10-4852.38"
123169                   case 1'1
123170                     assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
123171                     attribute \src "ls180.v:4854.7-4860.10"
123172                     switch \main_sdphy_datar_sink_last
123173                       attribute \src "ls180.v:4854.11-4854.37"
123174                       case 1'1
123175                         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
123176                         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
123177                         assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011
123178                       attribute \src "ls180.v:4858.11-4858.15"
123179                       case
123180                         assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
123181                     end
123182                   case
123183                 end
123184               attribute \src "ls180.v:4862.9-4862.13"
123185               case
123186                 assign $0\main_sdphy_datar_stop[0:0] 1'1
123187             end
123188           case
123189         end
123190         attribute \src "ls180.v:4868.4-4871.7"
123191         switch $eq$ls180.v:4868$704_Y
123192           attribute \src "ls180.v:4868.8-4868.42"
123193           case 1'1
123194             assign $0\main_sdphy_datar_sink_ready[0:0] 1'1
123195             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100
123196           case
123197         end
123198       attribute \src "ls180.v:0.0-0.0"
123199       case 3'011
123200         assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
123201         attribute \src "ls180.v:4875.4-4881.7"
123202         switch \main_sdphy_datar_pads_out_ready
123203           attribute \src "ls180.v:4875.8-4875.39"
123204           case 1'1
123205             assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4876$705_Y
123206             assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
123207             attribute \src "ls180.v:4878.5-4880.8"
123208             switch $eq$ls180.v:4878$706_Y
123209               attribute \src "ls180.v:4878.9-4878.42"
123210               case 1'1
123211                 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
123212               case
123213             end
123214           case
123215         end
123216       attribute \src "ls180.v:0.0-0.0"
123217       case 3'100
123218         assign $0\main_sdphy_datar_source_valid[0:0] 1'1
123219         assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001
123220         assign $0\main_sdphy_datar_source_last[0:0] 1'1
123221         attribute \src "ls180.v:4887.4-4889.7"
123222         switch $and$ls180.v:4887$707_Y
123223           attribute \src "ls180.v:4887.8-4887.71"
123224           case 1'1
123225             assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000
123226           case
123227         end
123228       attribute \src "ls180.v:0.0-0.0"
123229       case
123230         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
123231         assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
123232         attribute \src "ls180.v:4894.4-4905.7"
123233         switch $and$ls180.v:4894$708_Y
123234           attribute \src "ls180.v:4894.8-4894.71"
123235           case 1'1
123236             assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1
123237             attribute \src "ls180.v:4896.5-4904.8"
123238             switch \main_sdphy_datar_pads_out_ready
123239               attribute \src "ls180.v:4896.9-4896.40"
123240               case 1'1
123241                 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000
123242                 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1
123243                 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
123244                 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1
123245                 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1
123246                 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1
123247                 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001
123248               case
123249             end
123250           case
123251         end
123252     end
123253     sync always
123254       update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0]
123255       update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0]
123256       update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0]
123257       update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0]
123258       update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0]
123259       update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0]
123260       update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0]
123261       update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0]
123262       update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0]
123263       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
123264       update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
123265       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
123266       update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
123267       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
123268       update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
123269   end
123270   attribute \src "ls180.v:482.5-482.44"
123271   process $proc$ls180.v:482$2939
123272     assign { } { }
123273     assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
123274     sync always
123275     sync init
123276       update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
123277   end
123278   attribute \src "ls180.v:483.5-483.45"
123279   process $proc$ls180.v:483$2940
123280     assign { } { }
123281     assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
123282     sync always
123283     sync init
123284       update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
123285   end
123286   attribute \src "ls180.v:484.5-484.54"
123287   process $proc$ls180.v:484$2941
123288     assign { } { }
123289     assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
123290     sync always
123291     sync init
123292       update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
123293   end
123294   attribute \src "ls180.v:486.32-486.76"
123295   process $proc$ls180.v:486$2942
123296     assign { } { }
123297     assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
123298     sync always
123299     sync init
123300       update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
123301   end
123302   attribute \src "ls180.v:487.11-487.55"
123303   process $proc$ls180.v:487$2943
123304     assign { } { }
123305     assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
123306     sync always
123307     sync init
123308       update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
123309   end
123310   attribute \src "ls180.v:489.32-489.75"
123311   process $proc$ls180.v:489$2944
123312     assign { } { }
123313     assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
123314     sync always
123315       update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0]
123316     sync init
123317   end
123318   attribute \src "ls180.v:491.32-491.76"
123319   process $proc$ls180.v:491$2945
123320     assign { } { }
123321     assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
123322     sync always
123323       update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0]
123324     sync init
123325   end
123326   attribute \src "ls180.v:4966.1-4973.4"
123327   process $proc$ls180.v:4966$830
123328     assign { } { }
123329     assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
123330     attribute \src "ls180.v:4968.2-4972.5"
123331     switch \main_sdcore_crc7_inserter_enable
123332       attribute \src "ls180.v:4968.6-4968.38"
123333       case 1'1
123334         assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40
123335       attribute \src "ls180.v:4970.6-4970.10"
123336       case
123337         assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0
123338     end
123339     sync always
123340       update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0]
123341   end
123342   attribute \src "ls180.v:497.5-497.51"
123343   process $proc$ls180.v:497$2946
123344     assign { } { }
123345     assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
123346     sync always
123347     sync init
123348       update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
123349   end
123350   attribute \src "ls180.v:498.5-498.51"
123351   process $proc$ls180.v:498$2947
123352     assign { } { }
123353     assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
123354     sync always
123355     sync init
123356       update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0]
123357   end
123358   attribute \src "ls180.v:4988.1-4995.4"
123359   process $proc$ls180.v:4988$853
123360     assign { } { }
123361     assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
123362     attribute \src "ls180.v:4990.2-4994.5"
123363     switch \main_sdcore_crc16_inserter_crc0_enable
123364       attribute \src "ls180.v:4990.6-4990.44"
123365       case 1'1
123366         assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
123367       attribute \src "ls180.v:4992.6-4992.10"
123368       case
123369         assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0
123370     end
123371     sync always
123372       update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0]
123373   end
123374   attribute \src "ls180.v:4998.1-5005.4"
123375   process $proc$ls180.v:4998$864
123376     assign { } { }
123377     assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
123378     attribute \src "ls180.v:5000.2-5004.5"
123379     switch \main_sdcore_crc16_inserter_crc1_enable
123380       attribute \src "ls180.v:5000.6-5000.44"
123381       case 1'1
123382         assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
123383       attribute \src "ls180.v:5002.6-5002.10"
123384       case
123385         assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0
123386     end
123387     sync always
123388       update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
123389   end
123390   attribute \src "ls180.v:500.5-500.47"
123391   process $proc$ls180.v:500$2948
123392     assign { } { }
123393     assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
123394     sync always
123395     sync init
123396       update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0]
123397   end
123398   attribute \src "ls180.v:5008.1-5015.4"
123399   process $proc$ls180.v:5008$875
123400     assign { } { }
123401     assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
123402     attribute \src "ls180.v:5010.2-5014.5"
123403     switch \main_sdcore_crc16_inserter_crc2_enable
123404       attribute \src "ls180.v:5010.6-5010.44"
123405       case 1'1
123406         assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
123407       attribute \src "ls180.v:5012.6-5012.10"
123408       case
123409         assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0
123410     end
123411     sync always
123412       update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
123413   end
123414   attribute \src "ls180.v:501.5-501.45"
123415   process $proc$ls180.v:501$2949
123416     assign { } { }
123417     assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
123418     sync always
123419     sync init
123420       update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0]
123421   end
123422   attribute \src "ls180.v:5018.1-5025.4"
123423   process $proc$ls180.v:5018$886
123424     assign { } { }
123425     assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
123426     attribute \src "ls180.v:5020.2-5024.5"
123427     switch \main_sdcore_crc16_inserter_crc3_enable
123428       attribute \src "ls180.v:5020.6-5020.44"
123429       case 1'1
123430         assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
123431       attribute \src "ls180.v:5022.6-5022.10"
123432       case
123433         assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0
123434     end
123435     sync always
123436       update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
123437   end
123438   attribute \src "ls180.v:502.5-502.45"
123439   process $proc$ls180.v:502$2950
123440     assign { } { }
123441     assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
123442     sync always
123443     sync init
123444       update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0]
123445   end
123446   attribute \src "ls180.v:5026.1-5105.4"
123447   process $proc$ls180.v:5026$887
123448     assign { } { }
123449     assign { } { }
123450     assign { } { }
123451     assign { } { }
123452     assign { } { }
123453     assign { } { }
123454     assign { } { }
123455     assign { } { }
123456     assign { } { }
123457     assign { } { }
123458     assign { } { }
123459     assign { } { }
123460     assign { } { }
123461     assign { } { }
123462     assign { } { }
123463     assign { } { }
123464     assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
123465     assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
123466     assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
123467     assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
123468     assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
123469     assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
123470     assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0
123471     assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
123472     assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
123473     assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
123474     assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
123475     assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
123476     assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
123477     assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
123478     assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state
123479     attribute \src "ls180.v:5043.2-5104.9"
123480     switch \builder_sdcore_crcupstreaminserter_state
123481       attribute \src "ls180.v:0.0-0.0"
123482       case 1'1
123483         assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
123484         assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1
123485         attribute \src "ls180.v:5047.4-5049.7"
123486         switch $eq$ls180.v:5047$888_Y
123487           attribute \src "ls180.v:5047.8-5047.48"
123488           case 1'1
123489             assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1
123490           case
123491         end
123492         attribute \src "ls180.v:5050.4-5075.11"
123493         switch \main_sdcore_crc16_inserter_cnt
123494           attribute \src "ls180.v:0.0-0.0"
123495           case 3'000
123496             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] }
123497           attribute \src "ls180.v:0.0-0.0"
123498           case 3'001
123499             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] }
123500           attribute \src "ls180.v:0.0-0.0"
123501           case 3'010
123502             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] }
123503           attribute \src "ls180.v:0.0-0.0"
123504           case 3'011
123505             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] }
123506           attribute \src "ls180.v:0.0-0.0"
123507           case 3'100
123508             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] }
123509           attribute \src "ls180.v:0.0-0.0"
123510           case 3'101
123511             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] }
123512           attribute \src "ls180.v:0.0-0.0"
123513           case 3'110
123514             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] }
123515           attribute \src "ls180.v:0.0-0.0"
123516           case 3'111
123517             assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] }
123518           case
123519         end
123520         attribute \src "ls180.v:5076.4-5083.7"
123521         switch \main_sdcore_crc16_inserter_source_ready
123522           attribute \src "ls180.v:5076.8-5076.47"
123523           case 1'1
123524             attribute \src "ls180.v:5077.5-5082.8"
123525             switch $eq$ls180.v:5077$889_Y
123526               attribute \src "ls180.v:5077.9-5077.49"
123527               case 1'1
123528                 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
123529               attribute \src "ls180.v:5079.9-5079.13"
123530               case
123531                 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5080$890_Y
123532                 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1
123533             end
123534           case
123535         end
123536       attribute \src "ls180.v:0.0-0.0"
123537       case
123538         assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data
123539         assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid
123540         assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready
123541         assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0
123542         assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc
123543         assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1
123544         assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc
123545         assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1
123546         assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc
123547         assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1
123548         assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc
123549         assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1
123550         attribute \src "ls180.v:5098.4-5102.7"
123551         switch $and$ls180.v:5098$892_Y
123552           attribute \src "ls180.v:5098.8-5098.128"
123553           case 1'1
123554             assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1
123555             assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
123556             assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1
123557           case
123558         end
123559     end
123560     sync always
123561       update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0]
123562       update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0]
123563       update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0]
123564       update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0]
123565       update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0]
123566       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
123567       update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
123568       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
123569       update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
123570       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
123571       update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
123572       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
123573       update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
123574       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
123575       update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
123576   end
123577   attribute \src "ls180.v:503.12-503.57"
123578   process $proc$ls180.v:503$2951
123579     assign { } { }
123580     assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
123581     sync always
123582     sync init
123583       update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
123584   end
123585   attribute \src "ls180.v:505.5-505.51"
123586   process $proc$ls180.v:505$2952
123587     assign { } { }
123588     assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
123589     sync always
123590     sync init
123591       update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
123592   end
123593   attribute \src "ls180.v:506.5-506.51"
123594   process $proc$ls180.v:506$2953
123595     assign { } { }
123596     assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
123597     sync always
123598     sync init
123599       update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
123600   end
123601   attribute \src "ls180.v:507.5-507.50"
123602   process $proc$ls180.v:507$2954
123603     assign { } { }
123604     assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
123605     sync always
123606     sync init
123607       update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
123608   end
123609   attribute \src "ls180.v:508.5-508.54"
123610   process $proc$ls180.v:508$2955
123611     assign { } { }
123612     assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
123613     sync always
123614     sync init
123615       update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
123616   end
123617   attribute \src "ls180.v:509.5-509.55"
123618   process $proc$ls180.v:509$2956
123619     assign { } { }
123620     assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
123621     sync always
123622     sync init
123623       update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
123624   end
123625   attribute \src "ls180.v:510.5-510.56"
123626   process $proc$ls180.v:510$2957
123627     assign { } { }
123628     assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
123629     sync always
123630     sync init
123631       update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0]
123632   end
123633   attribute \src "ls180.v:5106.1-5111.4"
123634   process $proc$ls180.v:5106$893
123635     assign { } { }
123636     assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0
123637     attribute \src "ls180.v:5108.2-5110.5"
123638     switch $and$ls180.v:5108$900_Y
123639       attribute \src "ls180.v:5108.6-5108.301"
123640       case 1'1
123641         assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1
123642       case
123643     end
123644     sync always
123645       update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0]
123646   end
123647   attribute \src "ls180.v:511.5-511.50"
123648   process $proc$ls180.v:511$2958
123649     assign { } { }
123650     assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
123651     sync always
123652     sync init
123653       update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0]
123654   end
123655   attribute \src "ls180.v:5114.1-5121.4"
123656   process $proc$ls180.v:5114$902
123657     assign { } { }
123658     assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
123659     attribute \src "ls180.v:5116.2-5120.5"
123660     switch $eq$ls180.v:5116$903_Y
123661       attribute \src "ls180.v:5116.6-5116.45"
123662       case 1'1
123663         assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1
123664       attribute \src "ls180.v:5118.6-5118.10"
123665       case
123666         assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
123667     end
123668     sync always
123669       update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0]
123670   end
123671   attribute \src "ls180.v:5124.1-5131.4"
123672   process $proc$ls180.v:5124$905
123673     assign { } { }
123674     assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
123675     attribute \src "ls180.v:5126.2-5130.5"
123676     switch $eq$ls180.v:5126$906_Y
123677       attribute \src "ls180.v:5126.6-5126.45"
123678       case 1'1
123679         assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1
123680       attribute \src "ls180.v:5128.6-5128.10"
123681       case
123682         assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
123683     end
123684     sync always
123685       update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0]
123686   end
123687   attribute \src "ls180.v:5134.1-5141.4"
123688   process $proc$ls180.v:5134$908
123689     assign { } { }
123690     assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
123691     attribute \src "ls180.v:5136.2-5140.5"
123692     switch $eq$ls180.v:5136$909_Y
123693       attribute \src "ls180.v:5136.6-5136.45"
123694       case 1'1
123695         assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1
123696       attribute \src "ls180.v:5138.6-5138.10"
123697       case
123698         assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
123699     end
123700     sync always
123701       update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0]
123702   end
123703   attribute \src "ls180.v:514.5-514.67"
123704   process $proc$ls180.v:514$2959
123705     assign { } { }
123706     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
123707     sync always
123708       update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
123709     sync init
123710   end
123711   attribute \src "ls180.v:5144.1-5151.4"
123712   process $proc$ls180.v:5144$911
123713     assign { } { }
123714     assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
123715     attribute \src "ls180.v:5146.2-5150.5"
123716     switch $eq$ls180.v:5146$912_Y
123717       attribute \src "ls180.v:5146.6-5146.45"
123718       case 1'1
123719         assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1
123720       attribute \src "ls180.v:5148.6-5148.10"
123721       case
123722         assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
123723     end
123724     sync always
123725       update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0]
123726   end
123727   attribute \src "ls180.v:515.5-515.66"
123728   process $proc$ls180.v:515$2960
123729     assign { } { }
123730     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
123731     sync always
123732       update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
123733     sync init
123734   end
123735   attribute \src "ls180.v:5153.1-5158.4"
123736   process $proc$ls180.v:5153$913
123737     assign { } { }
123738     assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0
123739     attribute \src "ls180.v:5155.2-5157.5"
123740     switch $and$ls180.v:5155$915_Y
123741       attribute \src "ls180.v:5155.6-5155.85"
123742       case 1'1
123743         assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1
123744       case
123745     end
123746     sync always
123747       update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0]
123748   end
123749   attribute \src "ls180.v:5159.1-5166.4"
123750   process $proc$ls180.v:5159$916
123751     assign { } { }
123752     assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
123753     attribute \src "ls180.v:5161.2-5165.5"
123754     switch $lt$ls180.v:5161$917_Y
123755       attribute \src "ls180.v:5161.6-5161.44"
123756       case 1'1
123757         assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1
123758       attribute \src "ls180.v:5163.6-5163.10"
123759       case
123760         assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready
123761     end
123762     sync always
123763       update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0]
123764   end
123765   attribute \src "ls180.v:5170.1-5177.4"
123766   process $proc$ls180.v:5170$928
123767     assign { } { }
123768     assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
123769     attribute \src "ls180.v:5172.2-5176.5"
123770     switch \main_sdcore_crc16_checker_crc0_enable
123771       attribute \src "ls180.v:5172.6-5172.43"
123772       case 1'1
123773         assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
123774       attribute \src "ls180.v:5174.6-5174.10"
123775       case
123776         assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0
123777     end
123778     sync always
123779       update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0]
123780   end
123781   attribute \src "ls180.v:5180.1-5187.4"
123782   process $proc$ls180.v:5180$939
123783     assign { } { }
123784     assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
123785     attribute \src "ls180.v:5182.2-5186.5"
123786     switch \main_sdcore_crc16_checker_crc1_enable
123787       attribute \src "ls180.v:5182.6-5182.43"
123788       case 1'1
123789         assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
123790       attribute \src "ls180.v:5184.6-5184.10"
123791       case
123792         assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0
123793     end
123794     sync always
123795       update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0]
123796   end
123797   attribute \src "ls180.v:5190.1-5197.4"
123798   process $proc$ls180.v:5190$950
123799     assign { } { }
123800     assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
123801     attribute \src "ls180.v:5192.2-5196.5"
123802     switch \main_sdcore_crc16_checker_crc2_enable
123803       attribute \src "ls180.v:5192.6-5192.43"
123804       case 1'1
123805         assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
123806       attribute \src "ls180.v:5194.6-5194.10"
123807       case
123808         assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0
123809     end
123810     sync always
123811       update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0]
123812   end
123813   attribute \src "ls180.v:5200.1-5207.4"
123814   process $proc$ls180.v:5200$961
123815     assign { } { }
123816     assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
123817     attribute \src "ls180.v:5202.2-5206.5"
123818     switch \main_sdcore_crc16_checker_crc3_enable
123819       attribute \src "ls180.v:5202.6-5202.43"
123820       case 1'1
123821         assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
123822       attribute \src "ls180.v:5204.6-5204.10"
123823       case
123824         assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0
123825     end
123826     sync always
123827       update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0]
123828   end
123829   attribute \src "ls180.v:5208.1-5398.4"
123830   process $proc$ls180.v:5208$962
123831     assign { } { }
123832     assign { } { }
123833     assign { } { }
123834     assign { } { }
123835     assign { } { }
123836     assign { } { }
123837     assign { } { }
123838     assign { } { }
123839     assign { } { }
123840     assign { } { }
123841     assign { } { }
123842     assign { } { }
123843     assign { } { }
123844     assign { } { }
123845     assign { } { }
123846     assign { } { }
123847     assign { } { }
123848     assign { } { }
123849     assign { } { }
123850     assign { } { }
123851     assign { } { }
123852     assign { } { }
123853     assign { } { }
123854     assign { } { }
123855     assign { } { }
123856     assign { } { }
123857     assign { } { }
123858     assign { } { }
123859     assign { } { }
123860     assign { } { }
123861     assign { } { }
123862     assign { } { }
123863     assign { } { }
123864     assign { } { }
123865     assign { } { }
123866     assign { } { }
123867     assign { } { }
123868     assign { } { }
123869     assign { } { }
123870     assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0
123871     assign { } { }
123872     assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
123873     assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
123874     assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0
123875     assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
123876     assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
123877     assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
123878     assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
123879     assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
123880     assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
123881     assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
123882     assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
123883     assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
123884     assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
123885     assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
123886     assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
123887     assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0
123888     assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0
123889     assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
123890     assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
123891     assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
123892     assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
123893     assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
123894     assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
123895     assign $0\main_sdphy_datar_sink_valid[0:0] 1'0
123896     assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0
123897     assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
123898     assign $0\main_sdphy_dataw_sink_first[0:0] 1'0
123899     assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
123900     assign $0\main_sdphy_dataw_sink_last[0:0] 1'0
123901     assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
123902     assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
123903     assign $0\main_sdphy_datar_sink_last[0:0] 1'0
123904     assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0
123905     assign $0\main_sdphy_datar_source_ready[0:0] 1'0
123906     assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0
123907     assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
123908     assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0
123909     assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state
123910     attribute \src "ls180.v:5249.2-5397.9"
123911     switch \builder_sdcore_fsm_state
123912       attribute \src "ls180.v:0.0-0.0"
123913       case 3'001
123914         assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1
123915         attribute \src "ls180.v:5252.4-5272.11"
123916         switch \main_sdcore_cmd_count
123917           attribute \src "ls180.v:0.0-0.0"
123918           case 3'000
123919             assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] }
123920           attribute \src "ls180.v:0.0-0.0"
123921           case 3'001
123922             assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24]
123923           attribute \src "ls180.v:0.0-0.0"
123924           case 3'010
123925             assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16]
123926           attribute \src "ls180.v:0.0-0.0"
123927           case 3'011
123928             assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8]
123929           attribute \src "ls180.v:0.0-0.0"
123930           case 3'100
123931             assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0]
123932           attribute \src "ls180.v:0.0-0.0"
123933           case 3'101
123934             assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 }
123935             assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5270$963_Y
123936           case
123937         end
123938         attribute \src "ls180.v:5273.4-5285.7"
123939         switch $and$ls180.v:5273$964_Y
123940           attribute \src "ls180.v:5273.8-5273.65"
123941           case 1'1
123942             assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5274$965_Y
123943             assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
123944             attribute \src "ls180.v:5276.5-5284.8"
123945             switch $eq$ls180.v:5276$966_Y
123946               attribute \src "ls180.v:5276.9-5276.40"
123947               case 1'1
123948                 attribute \src "ls180.v:5277.6-5283.9"
123949                 switch $eq$ls180.v:5277$967_Y
123950                   attribute \src "ls180.v:5277.10-5277.40"
123951                   case 1'1
123952                     assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1
123953                     assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
123954                     assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
123955                   attribute \src "ls180.v:5281.10-5281.14"
123956                   case
123957                     assign $0\builder_sdcore_fsm_next_state[2:0] 3'010
123958                 end
123959               case
123960             end
123961           case
123962         end
123963       attribute \src "ls180.v:0.0-0.0"
123964       case 3'010
123965         assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1
123966         assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5289$968_Y
123967         assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1
123968         attribute \src "ls180.v:5290.4-5294.7"
123969         switch $eq$ls180.v:5290$969_Y
123970           attribute \src "ls180.v:5290.8-5290.38"
123971           case 1'1
123972             assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001
123973           attribute \src "ls180.v:5292.8-5292.12"
123974           case
123975             assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110
123976         end
123977         attribute \src "ls180.v:5296.4-5317.7"
123978         switch \main_sdphy_cmdr_source_valid
123979           attribute \src "ls180.v:5296.8-5296.36"
123980           case 1'1
123981             attribute \src "ls180.v:5297.5-5316.8"
123982             switch $eq$ls180.v:5297$970_Y
123983               attribute \src "ls180.v:5297.9-5297.56"
123984               case 1'1
123985                 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1
123986                 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1
123987                 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
123988               attribute \src "ls180.v:5301.9-5301.13"
123989               case
123990                 attribute \src "ls180.v:5302.6-5315.9"
123991                 switch \main_sdphy_cmdr_source_last
123992                   attribute \src "ls180.v:5302.10-5302.37"
123993                   case 1'1
123994                     attribute \src "ls180.v:5303.7-5311.10"
123995                     switch $eq$ls180.v:5303$971_Y
123996                       attribute \src "ls180.v:5303.11-5303.42"
123997                       case 1'1
123998                         assign $0\builder_sdcore_fsm_next_state[2:0] 3'011
123999                       attribute \src "ls180.v:5305.11-5305.15"
124000                       case
124001                         attribute \src "ls180.v:5306.8-5310.11"
124002                         switch $eq$ls180.v:5306$972_Y
124003                           attribute \src "ls180.v:5306.12-5306.43"
124004                           case 1'1
124005                             assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
124006                           attribute \src "ls180.v:5308.12-5308.16"
124007                           case
124008                             assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
124009                         end
124010                     end
124011                   attribute \src "ls180.v:5312.10-5312.14"
124012                   case
124013                     assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data }
124014                     assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1
124015                 end
124016             end
124017           case
124018         end
124019       attribute \src "ls180.v:0.0-0.0"
124020       case 3'011
124021         assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid
124022         assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready
124023         assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first
124024         assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last
124025         assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data
124026         assign $0\main_sdphy_datar_source_ready[0:0] 1'1
124027         attribute \src "ls180.v:5325.4-5331.7"
124028         switch $and$ls180.v:5325$974_Y
124029           attribute \src "ls180.v:5325.8-5325.98"
124030           case 1'1
124031             assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5326$975_Y
124032             assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
124033             attribute \src "ls180.v:5328.5-5330.8"
124034             switch $eq$ls180.v:5328$977_Y
124035               attribute \src "ls180.v:5328.9-5328.77"
124036               case 1'1
124037                 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
124038               case
124039             end
124040           case
124041         end
124042         attribute \src "ls180.v:5333.4-5338.7"
124043         switch \main_sdphy_datar_source_valid
124044           attribute \src "ls180.v:5333.8-5333.37"
124045           case 1'1
124046             attribute \src "ls180.v:5334.5-5337.8"
124047             switch $ne$ls180.v:5334$978_Y
124048               attribute \src "ls180.v:5334.9-5334.57"
124049               case 1'1
124050                 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1
124051                 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1
124052               case
124053             end
124054           case
124055         end
124056       attribute \src "ls180.v:0.0-0.0"
124057       case 3'100
124058         assign $0\main_sdphy_datar_sink_valid[0:0] 1'1
124059         assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage
124060         assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5343$980_Y
124061         attribute \src "ls180.v:5344.4-5370.7"
124062         switch \main_sdphy_datar_source_valid
124063           attribute \src "ls180.v:5344.8-5344.37"
124064           case 1'1
124065             attribute \src "ls180.v:5345.5-5369.8"
124066             switch $eq$ls180.v:5345$981_Y
124067               attribute \src "ls180.v:5345.9-5345.57"
124068               case 1'1
124069                 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid
124070                 assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready
124071                 assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first
124072                 assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last
124073                 assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data
124074                 attribute \src "ls180.v:5351.6-5359.9"
124075                 switch $and$ls180.v:5351$982_Y
124076                   attribute \src "ls180.v:5351.10-5351.72"
124077                   case 1'1
124078                     assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5352$983_Y
124079                     assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
124080                     attribute \src "ls180.v:5354.7-5358.10"
124081                     switch $eq$ls180.v:5354$985_Y
124082                       attribute \src "ls180.v:5354.11-5354.79"
124083                       case 1'1
124084                         assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
124085                       attribute \src "ls180.v:5356.11-5356.15"
124086                       case
124087                         assign $0\builder_sdcore_fsm_next_state[2:0] 3'100
124088                     end
124089                   case
124090                 end
124091               attribute \src "ls180.v:5360.9-5360.13"
124092               case
124093                 attribute \src "ls180.v:5361.6-5368.9"
124094                 switch $eq$ls180.v:5361$986_Y
124095                   attribute \src "ls180.v:5361.10-5361.58"
124096                   case 1'1
124097                     assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1
124098                     assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1
124099                     assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
124100                     assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
124101                     assign $0\main_sdphy_datar_source_ready[0:0] 1'1
124102                     assign $0\builder_sdcore_fsm_next_state[2:0] 3'000
124103                   case
124104                 end
124105             end
124106           case
124107         end
124108       attribute \src "ls180.v:0.0-0.0"
124109       case
124110         assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1
124111         assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
124112         assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1
124113         assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1
124114         assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
124115         assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1
124116         assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
124117         assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1
124118         attribute \src "ls180.v:5381.4-5395.7"
124119         switch \main_sdcore_cmd_send_re
124120           attribute \src "ls180.v:5381.8-5381.31"
124121           case 1'1
124122             assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
124123             assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1
124124             assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
124125             assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1
124126             assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
124127             assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1
124128             assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
124129             assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1
124130             assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
124131             assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1
124132             assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
124133             assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1
124134             assign $0\builder_sdcore_fsm_next_state[2:0] 3'001
124135           case
124136         end
124137     end
124138     sync always
124139       update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0]
124140       update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0]
124141       update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0]
124142       update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0]
124143       update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0]
124144       update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0]
124145       update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0]
124146       update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0]
124147       update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0]
124148       update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0]
124149       update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0]
124150       update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0]
124151       update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0]
124152       update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0]
124153       update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0]
124154       update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0]
124155       update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0]
124156       update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0]
124157       update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0]
124158       update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0]
124159       update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0]
124160       update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
124161       update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
124162       update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
124163       update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
124164       update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
124165       update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
124166       update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
124167       update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
124168       update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
124169       update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
124170       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
124171       update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
124172       update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
124173       update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
124174       update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
124175       update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
124176       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
124177       update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
124178   end
124179   attribute \src "ls180.v:530.11-530.68"
124180   process $proc$ls180.v:530$2961
124181     assign { } { }
124182     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
124183     sync always
124184     sync init
124185       update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
124186   end
124187   attribute \src "ls180.v:531.5-531.64"
124188   process $proc$ls180.v:531$2962
124189     assign { } { }
124190     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
124191     sync always
124192       update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
124193     sync init
124194   end
124195   attribute \src "ls180.v:532.11-532.70"
124196   process $proc$ls180.v:532$2963
124197     assign { } { }
124198     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
124199     sync always
124200     sync init
124201       update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
124202   end
124203   attribute \src "ls180.v:533.11-533.70"
124204   process $proc$ls180.v:533$2964
124205     assign { } { }
124206     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
124207     sync always
124208     sync init
124209       update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
124210   end
124211   attribute \src "ls180.v:534.11-534.73"
124212   process $proc$ls180.v:534$2965
124213     assign { } { }
124214     assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
124215     sync always
124216     sync init
124217       update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
124218   end
124219   attribute \src "ls180.v:5426.1-5433.4"
124220   process $proc$ls180.v:5426$987
124221     assign { } { }
124222     assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
124223     attribute \src "ls180.v:5428.2-5432.5"
124224     switch \main_sdblock2mem_fifo_replace
124225       attribute \src "ls180.v:5428.6-5428.35"
124226       case 1'1
124227         assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5429$988_Y
124228       attribute \src "ls180.v:5430.6-5430.10"
124229       case
124230         assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce
124231     end
124232     sync always
124233       update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0]
124234   end
124235   attribute \src "ls180.v:5459.1-5498.4"
124236   process $proc$ls180.v:5459$998
124237     assign { } { }
124238     assign { } { }
124239     assign { } { }
124240     assign { } { }
124241     assign { } { }
124242     assign { } { }
124243     assign { } { }
124244     assign { } { }
124245     assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
124246     assign { } { }
124247     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
124248     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
124249     assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0
124250     assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
124251     assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
124252     assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
124253     assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state
124254     attribute \src "ls180.v:5469.2-5497.9"
124255     switch \builder_sdblock2memdma_state
124256       attribute \src "ls180.v:0.0-0.0"
124257       case 2'01
124258         assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid
124259         assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data
124260         assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5473$999_Y
124261         assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1
124262         attribute \src "ls180.v:5475.4-5486.7"
124263         switch $and$ls180.v:5475$1000_Y
124264           attribute \src "ls180.v:5475.8-5475.103"
124265           case 1'1
124266             assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5476$1001_Y
124267             assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
124268             attribute \src "ls180.v:5478.5-5485.8"
124269             switch $eq$ls180.v:5478$1003_Y
124270               attribute \src "ls180.v:5478.9-5478.106"
124271               case 1'1
124272                 attribute \src "ls180.v:5479.6-5484.9"
124273                 switch \main_sdblock2mem_wishbonedmawriter_loop_storage
124274                   attribute \src "ls180.v:5479.10-5479.57"
124275                   case 1'1
124276                     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
124277                     assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
124278                   attribute \src "ls180.v:5482.10-5482.14"
124279                   case
124280                     assign $0\builder_sdblock2memdma_next_state[1:0] 2'10
124281                 end
124282               case
124283             end
124284           case
124285         end
124286       attribute \src "ls180.v:0.0-0.0"
124287       case 2'10
124288         assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1
124289       attribute \src "ls180.v:0.0-0.0"
124290       case
124291         assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1
124292         assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
124293         assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1
124294         assign $0\builder_sdblock2memdma_next_state[1:0] 2'01
124295     end
124296     sync always
124297       update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0]
124298       update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0]
124299       update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0]
124300       update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
124301       update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0]
124302       update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0]
124303       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
124304       update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
124305   end
124306   attribute \src "ls180.v:55.5-55.42"
124307   process $proc$ls180.v:55$2775
124308     assign { } { }
124309     assign $1\main_libresocsim_reset_storage[0:0] 1'0
124310     sync always
124311     sync init
124312       update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0]
124313   end
124314   attribute \src "ls180.v:5518.1-5555.4"
124315   process $proc$ls180.v:5518$1005
124316     assign { } { }
124317     assign { } { }
124318     assign { } { }
124319     assign { } { }
124320     assign { } { }
124321     assign { } { }
124322     assign { } { }
124323     assign { } { }
124324     assign { } { }
124325     assign { } { }
124326     assign { } { }
124327     assign { } { }
124328     assign $0\main_interface1_bus_we[0:0] 1'0
124329     assign $0\main_sdmem2block_dma_source_last[0:0] 1'0
124330     assign { } { }
124331     assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0
124332     assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
124333     assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
124334     assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0
124335     assign $0\main_interface1_bus_adr[31:0] 0
124336     assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0
124337     assign $0\main_interface1_bus_sel[3:0] 4'0000
124338     assign $0\main_interface1_bus_cyc[0:0] 1'0
124339     assign $0\main_interface1_bus_stb[0:0] 1'0
124340     assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state
124341     attribute \src "ls180.v:5532.2-5554.9"
124342     switch \builder_sdmem2blockdma_fsm_state
124343       attribute \src "ls180.v:0.0-0.0"
124344       case 1'1
124345         assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1
124346         assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last
124347         assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data
124348         attribute \src "ls180.v:5537.4-5540.7"
124349         switch \main_sdmem2block_dma_source_ready
124350           attribute \src "ls180.v:5537.8-5537.41"
124351           case 1'1
124352             assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1
124353             assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
124354           case
124355         end
124356       attribute \src "ls180.v:0.0-0.0"
124357       case
124358         assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid
124359         assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid
124360         assign $0\main_interface1_bus_we[0:0] 1'0
124361         assign $0\main_interface1_bus_sel[3:0] 4'1111
124362         assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address
124363         attribute \src "ls180.v:5548.4-5552.7"
124364         switch $and$ls180.v:5548$1006_Y
124365           attribute \src "ls180.v:5548.8-5548.59"
124366           case 1'1
124367             assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] }
124368             assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1
124369             assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1
124370           case
124371         end
124372     end
124373     sync always
124374       update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0]
124375       update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0]
124376       update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0]
124377       update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0]
124378       update \main_interface1_bus_we $0\main_interface1_bus_we[0:0]
124379       update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0]
124380       update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0]
124381       update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0]
124382       update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0]
124383       update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0]
124384       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
124385       update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
124386   end
124387   attribute \src "ls180.v:555.5-555.59"
124388   process $proc$ls180.v:555$2966
124389     assign { } { }
124390     assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
124391     sync always
124392     sync init
124393       update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
124394   end
124395   attribute \src "ls180.v:5556.1-5592.4"
124396   process $proc$ls180.v:5556$1007
124397     assign { } { }
124398     assign { } { }
124399     assign { } { }
124400     assign { } { }
124401     assign { } { }
124402     assign { } { }
124403     assign { } { }
124404     assign $0\main_sdmem2block_dma_done_status[0:0] 1'0
124405     assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0
124406     assign { } { }
124407     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
124408     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
124409     assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0
124410     assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0
124411     assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state
124412     attribute \src "ls180.v:5565.2-5591.9"
124413     switch \builder_sdmem2blockdma_resetinserter_state
124414       attribute \src "ls180.v:0.0-0.0"
124415       case 2'01
124416         assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1
124417         assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5568$1009_Y
124418         assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5569$1010_Y
124419         attribute \src "ls180.v:5570.4-5581.7"
124420         switch \main_sdmem2block_dma_sink_ready
124421           attribute \src "ls180.v:5570.8-5570.39"
124422           case 1'1
124423             assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5571$1011_Y
124424             assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
124425             attribute \src "ls180.v:5573.5-5580.8"
124426             switch \main_sdmem2block_dma_sink_last
124427               attribute \src "ls180.v:5573.9-5573.39"
124428               case 1'1
124429                 attribute \src "ls180.v:5574.6-5579.9"
124430                 switch \main_sdmem2block_dma_loop_storage
124431                   attribute \src "ls180.v:5574.10-5574.43"
124432                   case 1'1
124433                     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
124434                     assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
124435                   attribute \src "ls180.v:5577.10-5577.14"
124436                   case
124437                     assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10
124438                 end
124439               case
124440             end
124441           case
124442         end
124443       attribute \src "ls180.v:0.0-0.0"
124444       case 2'10
124445         assign $0\main_sdmem2block_dma_done_status[0:0] 1'1
124446       attribute \src "ls180.v:0.0-0.0"
124447       case
124448         assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
124449         assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1
124450         assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01
124451     end
124452     sync always
124453       update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0]
124454       update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0]
124455       update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0]
124456       update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0]
124457       update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0]
124458       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
124459       update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
124460   end
124461   attribute \src "ls180.v:557.5-557.59"
124462   process $proc$ls180.v:557$2967
124463     assign { } { }
124464     assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
124465     sync always
124466     sync init
124467       update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
124468   end
124469   attribute \src "ls180.v:558.5-558.58"
124470   process $proc$ls180.v:558$2968
124471     assign { } { }
124472     assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
124473     sync always
124474     sync init
124475       update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
124476   end
124477   attribute \src "ls180.v:559.5-559.64"
124478   process $proc$ls180.v:559$2969
124479     assign { } { }
124480     assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
124481     sync always
124482     sync init
124483       update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
124484   end
124485   attribute \src "ls180.v:56.5-56.37"
124486   process $proc$ls180.v:56$2776
124487     assign { } { }
124488     assign $1\main_libresocsim_reset_re[0:0] 1'0
124489     sync always
124490     sync init
124491       update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
124492   end
124493   attribute \src "ls180.v:560.12-560.74"
124494   process $proc$ls180.v:560$2970
124495     assign { } { }
124496     assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
124497     sync always
124498     sync init
124499       update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
124500   end
124501   attribute \src "ls180.v:5604.1-5620.4"
124502   process $proc$ls180.v:5604$1017
124503     assign { } { }
124504     assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
124505     attribute \src "ls180.v:5606.2-5619.9"
124506     switch \main_sdmem2block_converter_mux
124507       attribute \src "ls180.v:0.0-0.0"
124508       case 2'00
124509         assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24]
124510       attribute \src "ls180.v:0.0-0.0"
124511       case 2'01
124512         assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16]
124513       attribute \src "ls180.v:0.0-0.0"
124514       case 2'10
124515         assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8]
124516       attribute \src "ls180.v:0.0-0.0"
124517       case
124518         assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0]
124519     end
124520     sync always
124521       update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0]
124522   end
124523   attribute \src "ls180.v:561.12-561.47"
124524   process $proc$ls180.v:561$2971
124525     assign { } { }
124526     assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
124527     sync always
124528     sync init
124529       update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
124530   end
124531   attribute \src "ls180.v:562.5-562.46"
124532   process $proc$ls180.v:562$2972
124533     assign { } { }
124534     assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
124535     sync always
124536     sync init
124537       update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0]
124538   end
124539   attribute \src "ls180.v:5634.1-5641.4"
124540   process $proc$ls180.v:5634$1018
124541     assign { } { }
124542     assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
124543     attribute \src "ls180.v:5636.2-5640.5"
124544     switch \main_sdmem2block_fifo_replace
124545       attribute \src "ls180.v:5636.6-5636.35"
124546       case 1'1
124547         assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5637$1019_Y
124548       attribute \src "ls180.v:5638.6-5638.10"
124549       case
124550         assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce
124551     end
124552     sync always
124553       update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0]
124554   end
124555   attribute \src "ls180.v:564.5-564.44"
124556   process $proc$ls180.v:564$2973
124557     assign { } { }
124558     assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
124559     sync always
124560     sync init
124561       update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0]
124562   end
124563   attribute \src "ls180.v:5649.1-5685.4"
124564   process $proc$ls180.v:5649$1025
124565     assign { } { }
124566     assign { } { }
124567     assign { } { }
124568     assign { } { }
124569     assign { } { }
124570     assign { } { }
124571     assign { } { }
124572     assign { } { }
124573     assign { } { }
124574     assign { } { }
124575     assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
124576     assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
124577     assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
124578     assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
124579     assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
124580     assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0
124581     assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0
124582     assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0
124583     assign $0\builder_next_state[1:0] \builder_state
124584     attribute \src "ls180.v:5660.2-5684.9"
124585     switch \builder_state
124586       attribute \src "ls180.v:0.0-0.0"
124587       case 2'01
124588         assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
124589         assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1
124590         assign $0\builder_libresocsim_we_next_value2[0:0] 1'0
124591         assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1
124592         assign $0\builder_next_state[1:0] 2'10
124593       attribute \src "ls180.v:0.0-0.0"
124594       case 2'10
124595         assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1
124596         assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r }
124597         assign $0\builder_next_state[1:0] 2'00
124598       attribute \src "ls180.v:0.0-0.0"
124599       case
124600         assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0]
124601         assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1
124602         attribute \src "ls180.v:5676.4-5682.7"
124603         switch $and$ls180.v:5676$1026_Y
124604           attribute \src "ls180.v:5676.8-5676.77"
124605           case 1'1
124606             assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0]
124607             assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1
124608             assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5679$1028_Y
124609             assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1
124610             assign $0\builder_next_state[1:0] 2'01
124611           case
124612         end
124613     end
124614     sync always
124615       update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0]
124616       update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0]
124617       update \builder_next_state $0\builder_next_state[1:0]
124618       update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0]
124619       update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0]
124620       update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0]
124621       update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0]
124622       update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0]
124623       update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0]
124624   end
124625   attribute \src "ls180.v:565.5-565.45"
124626   process $proc$ls180.v:565$2974
124627     assign { } { }
124628     assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
124629     sync always
124630     sync init
124631       update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
124632   end
124633   attribute \src "ls180.v:566.5-566.54"
124634   process $proc$ls180.v:566$2975
124635     assign { } { }
124636     assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
124637     sync always
124638     sync init
124639       update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
124640   end
124641   attribute \src "ls180.v:568.32-568.76"
124642   process $proc$ls180.v:568$2976
124643     assign { } { }
124644     assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
124645     sync always
124646     sync init
124647       update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
124648   end
124649   attribute \src "ls180.v:569.11-569.55"
124650   process $proc$ls180.v:569$2977
124651     assign { } { }
124652     assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
124653     sync always
124654     sync init
124655       update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0]
124656   end
124657   attribute \src "ls180.v:57.12-57.60"
124658   process $proc$ls180.v:57$2777
124659     assign { } { }
124660     assign $1\main_libresocsim_scratch_storage[31:0] 305419896
124661     sync always
124662     sync init
124663       update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
124664   end
124665   attribute \src "ls180.v:571.32-571.75"
124666   process $proc$ls180.v:571$2978
124667     assign { } { }
124668     assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
124669     sync always
124670       update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0]
124671     sync init
124672   end
124673   attribute \src "ls180.v:5710.1-5717.4"
124674   process $proc$ls180.v:5710$1049
124675     assign { } { }
124676     assign { } { }
124677     assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5712$1050_Y
124678     assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5713$1051_Y
124679     assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5714$1052_Y
124680     assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5715$1053_Y
124681     assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5716$1054_Y
124682     sync always
124683       update \builder_slave_sel $0\builder_slave_sel[4:0]
124684   end
124685   attribute \src "ls180.v:573.32-573.76"
124686   process $proc$ls180.v:573$2979
124687     assign { } { }
124688     assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
124689     sync always
124690       update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0]
124691     sync init
124692   end
124693   attribute \src "ls180.v:5760.1-5771.4"
124694   process $proc$ls180.v:5760$1067
124695     assign { } { }
124696     assign { } { }
124697     assign { } { }
124698     assign { } { }
124699     assign { } { }
124700     assign $0\builder_error[0:0] 1'0
124701     assign $0\builder_shared_ack[0:0] $or$ls180.v:5764$1071_Y
124702     assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5765$1080_Y
124703     attribute \src "ls180.v:5766.2-5770.5"
124704     switch \builder_done
124705       attribute \src "ls180.v:5766.6-5766.18"
124706       case 1'1
124707         assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111
124708         assign $0\builder_shared_ack[0:0] 1'1
124709         assign $0\builder_error[0:0] 1'1
124710       case
124711     end
124712     sync always
124713       update \builder_shared_dat_r $0\builder_shared_dat_r[31:0]
124714       update \builder_shared_ack $0\builder_shared_ack[0:0]
124715       update \builder_error $0\builder_error[0:0]
124716   end
124717   attribute \src "ls180.v:579.5-579.51"
124718   process $proc$ls180.v:579$2980
124719     assign { } { }
124720     assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
124721     sync always
124722     sync init
124723       update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0]
124724   end
124725   attribute \src "ls180.v:58.5-58.39"
124726   process $proc$ls180.v:58$2778
124727     assign { } { }
124728     assign $1\main_libresocsim_scratch_re[0:0] 1'0
124729     sync always
124730     sync init
124731       update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
124732   end
124733   attribute \src "ls180.v:580.5-580.51"
124734   process $proc$ls180.v:580$2981
124735     assign { } { }
124736     assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
124737     sync always
124738     sync init
124739       update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
124740   end
124741   attribute \src "ls180.v:582.5-582.47"
124742   process $proc$ls180.v:582$2982
124743     assign { } { }
124744     assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
124745     sync always
124746     sync init
124747       update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
124748   end
124749   attribute \src "ls180.v:583.5-583.45"
124750   process $proc$ls180.v:583$2983
124751     assign { } { }
124752     assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
124753     sync always
124754     sync init
124755       update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
124756   end
124757   attribute \src "ls180.v:584.5-584.45"
124758   process $proc$ls180.v:584$2984
124759     assign { } { }
124760     assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
124761     sync always
124762     sync init
124763       update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
124764   end
124765   attribute \src "ls180.v:585.12-585.57"
124766   process $proc$ls180.v:585$2985
124767     assign { } { }
124768     assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
124769     sync always
124770     sync init
124771       update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
124772   end
124773   attribute \src "ls180.v:587.5-587.51"
124774   process $proc$ls180.v:587$2986
124775     assign { } { }
124776     assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
124777     sync always
124778     sync init
124779       update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
124780   end
124781   attribute \src "ls180.v:588.5-588.51"
124782   process $proc$ls180.v:588$2987
124783     assign { } { }
124784     assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
124785     sync always
124786     sync init
124787       update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
124788   end
124789   attribute \src "ls180.v:589.5-589.50"
124790   process $proc$ls180.v:589$2988
124791     assign { } { }
124792     assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
124793     sync always
124794     sync init
124795       update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
124796   end
124797   attribute \src "ls180.v:590.5-590.54"
124798   process $proc$ls180.v:590$2989
124799     assign { } { }
124800     assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
124801     sync always
124802     sync init
124803       update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
124804   end
124805   attribute \src "ls180.v:591.5-591.55"
124806   process $proc$ls180.v:591$2990
124807     assign { } { }
124808     assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
124809     sync always
124810     sync init
124811       update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
124812   end
124813   attribute \src "ls180.v:592.5-592.56"
124814   process $proc$ls180.v:592$2991
124815     assign { } { }
124816     assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
124817     sync always
124818     sync init
124819       update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
124820   end
124821   attribute \src "ls180.v:593.5-593.50"
124822   process $proc$ls180.v:593$2992
124823     assign { } { }
124824     assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
124825     sync always
124826     sync init
124827       update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0]
124828   end
124829   attribute \src "ls180.v:596.5-596.67"
124830   process $proc$ls180.v:596$2993
124831     assign { } { }
124832     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
124833     sync always
124834       update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
124835     sync init
124836   end
124837   attribute \src "ls180.v:597.5-597.66"
124838   process $proc$ls180.v:597$2994
124839     assign { } { }
124840     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
124841     sync always
124842       update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
124843     sync init
124844   end
124845   attribute \src "ls180.v:612.11-612.68"
124846   process $proc$ls180.v:612$2995
124847     assign { } { }
124848     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
124849     sync always
124850     sync init
124851       update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
124852   end
124853   attribute \src "ls180.v:613.5-613.64"
124854   process $proc$ls180.v:613$2996
124855     assign { } { }
124856     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
124857     sync always
124858       update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
124859     sync init
124860   end
124861   attribute \src "ls180.v:614.11-614.70"
124862   process $proc$ls180.v:614$2997
124863     assign { } { }
124864     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
124865     sync always
124866     sync init
124867       update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
124868   end
124869   attribute \src "ls180.v:615.11-615.70"
124870   process $proc$ls180.v:615$2998
124871     assign { } { }
124872     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
124873     sync always
124874     sync init
124875       update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
124876   end
124877   attribute \src "ls180.v:616.11-616.73"
124878   process $proc$ls180.v:616$2999
124879     assign { } { }
124880     assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
124881     sync always
124882     sync init
124883       update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
124884   end
124885   attribute \src "ls180.v:6285.1-6290.4"
124886   process $proc$ls180.v:6285$1954
124887     assign { } { }
124888     assign $0\main_spimaster9_start[0:0] 1'0
124889     attribute \src "ls180.v:6287.2-6289.5"
124890     switch \main_spimaster12_re
124891       attribute \src "ls180.v:6287.6-6287.25"
124892       case 1'1
124893         assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0]
124894       case
124895     end
124896     sync always
124897       update \main_spimaster9_start $0\main_spimaster9_start[0:0]
124898   end
124899   attribute \src "ls180.v:63.12-63.47"
124900   process $proc$ls180.v:63$2779
124901     assign { } { }
124902     assign $1\main_libresocsim_bus_errors[31:0] 0
124903     sync always
124904     sync init
124905       update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0]
124906   end
124907   attribute \src "ls180.v:6331.1-6336.4"
124908   process $proc$ls180.v:6331$2019
124909     assign { } { }
124910     assign $0\main_spisdcard_start1[0:0] 1'0
124911     attribute \src "ls180.v:6333.2-6335.5"
124912     switch \main_spisdcard_control_re
124913       attribute \src "ls180.v:6333.6-6333.31"
124914       case 1'1
124915         assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0]
124916       case
124917     end
124918     sync always
124919       update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0]
124920   end
124921   attribute \src "ls180.v:637.5-637.59"
124922   process $proc$ls180.v:637$3000
124923     assign { } { }
124924     assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
124925     sync always
124926     sync init
124927       update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
124928   end
124929   attribute \src "ls180.v:639.5-639.59"
124930   process $proc$ls180.v:639$3001
124931     assign { } { }
124932     assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
124933     sync always
124934     sync init
124935       update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
124936   end
124937   attribute \src "ls180.v:640.5-640.58"
124938   process $proc$ls180.v:640$3002
124939     assign { } { }
124940     assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
124941     sync always
124942     sync init
124943       update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
124944   end
124945   attribute \src "ls180.v:641.5-641.64"
124946   process $proc$ls180.v:641$3003
124947     assign { } { }
124948     assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
124949     sync always
124950     sync init
124951       update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
124952   end
124953   attribute \src "ls180.v:642.12-642.74"
124954   process $proc$ls180.v:642$3004
124955     assign { } { }
124956     assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
124957     sync always
124958     sync init
124959       update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
124960   end
124961   attribute \src "ls180.v:643.12-643.47"
124962   process $proc$ls180.v:643$3005
124963     assign { } { }
124964     assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
124965     sync always
124966     sync init
124967       update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
124968   end
124969   attribute \src "ls180.v:644.5-644.46"
124970   process $proc$ls180.v:644$3006
124971     assign { } { }
124972     assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
124973     sync always
124974     sync init
124975       update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0]
124976   end
124977   attribute \src "ls180.v:646.5-646.44"
124978   process $proc$ls180.v:646$3007
124979     assign { } { }
124980     assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
124981     sync always
124982     sync init
124983       update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0]
124984   end
124985   attribute \src "ls180.v:647.5-647.45"
124986   process $proc$ls180.v:647$3008
124987     assign { } { }
124988     assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
124989     sync always
124990     sync init
124991       update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
124992   end
124993   attribute \src "ls180.v:648.5-648.54"
124994   process $proc$ls180.v:648$3009
124995     assign { } { }
124996     assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
124997     sync always
124998     sync init
124999       update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]
125000   end
125001   attribute \src "ls180.v:65.12-65.55"
125002   process $proc$ls180.v:65$2780
125003     assign { } { }
125004     assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
125005     sync always
125006     sync init
125007       update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
125008   end
125009   attribute \src "ls180.v:650.32-650.76"
125010   process $proc$ls180.v:650$3010
125011     assign { } { }
125012     assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
125013     sync always
125014     sync init
125015       update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
125016   end
125017   attribute \src "ls180.v:651.11-651.55"
125018   process $proc$ls180.v:651$3011
125019     assign { } { }
125020     assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
125021     sync always
125022     sync init
125023       update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0]
125024   end
125025   attribute \src "ls180.v:6520.1-6536.4"
125026   process $proc$ls180.v:6520$2240
125027     assign { } { }
125028     assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0
125029     attribute \src "ls180.v:6522.2-6535.9"
125030     switch \main_sdram_choose_cmd_grant
125031       attribute \src "ls180.v:0.0-0.0"
125032       case 2'00
125033         assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0]
125034       attribute \src "ls180.v:0.0-0.0"
125035       case 2'01
125036         assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1]
125037       attribute \src "ls180.v:0.0-0.0"
125038       case 2'10
125039         assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2]
125040       attribute \src "ls180.v:0.0-0.0"
125041       case
125042         assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3]
125043     end
125044     sync always
125045       update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0]
125046   end
125047   attribute \src "ls180.v:653.32-653.75"
125048   process $proc$ls180.v:653$3012
125049     assign { } { }
125050     assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
125051     sync always
125052       update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0]
125053     sync init
125054   end
125055   attribute \src "ls180.v:6537.1-6553.4"
125056   process $proc$ls180.v:6537$2241
125057     assign { } { }
125058     assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
125059     attribute \src "ls180.v:6539.2-6552.9"
125060     switch \main_sdram_choose_cmd_grant
125061       attribute \src "ls180.v:0.0-0.0"
125062       case 2'00
125063         assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a
125064       attribute \src "ls180.v:0.0-0.0"
125065       case 2'01
125066         assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a
125067       attribute \src "ls180.v:0.0-0.0"
125068       case 2'10
125069         assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a
125070       attribute \src "ls180.v:0.0-0.0"
125071       case
125072         assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a
125073     end
125074     sync always
125075       update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0]
125076   end
125077   attribute \src "ls180.v:655.32-655.76"
125078   process $proc$ls180.v:655$3013
125079     assign { } { }
125080     assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
125081     sync always
125082       update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0]
125083     sync init
125084   end
125085   attribute \src "ls180.v:6554.1-6570.4"
125086   process $proc$ls180.v:6554$2242
125087     assign { } { }
125088     assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00
125089     attribute \src "ls180.v:6556.2-6569.9"
125090     switch \main_sdram_choose_cmd_grant
125091       attribute \src "ls180.v:0.0-0.0"
125092       case 2'00
125093         assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba
125094       attribute \src "ls180.v:0.0-0.0"
125095       case 2'01
125096         assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba
125097       attribute \src "ls180.v:0.0-0.0"
125098       case 2'10
125099         assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba
125100       attribute \src "ls180.v:0.0-0.0"
125101       case
125102         assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba
125103     end
125104     sync always
125105       update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0]
125106   end
125107   attribute \src "ls180.v:6571.1-6587.4"
125108   process $proc$ls180.v:6571$2243
125109     assign { } { }
125110     assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0
125111     attribute \src "ls180.v:6573.2-6586.9"
125112     switch \main_sdram_choose_cmd_grant
125113       attribute \src "ls180.v:0.0-0.0"
125114       case 2'00
125115         assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read
125116       attribute \src "ls180.v:0.0-0.0"
125117       case 2'01
125118         assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read
125119       attribute \src "ls180.v:0.0-0.0"
125120       case 2'10
125121         assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read
125122       attribute \src "ls180.v:0.0-0.0"
125123       case
125124         assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read
125125     end
125126     sync always
125127       update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0]
125128   end
125129   attribute \src "ls180.v:6588.1-6604.4"
125130   process $proc$ls180.v:6588$2244
125131     assign { } { }
125132     assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0
125133     attribute \src "ls180.v:6590.2-6603.9"
125134     switch \main_sdram_choose_cmd_grant
125135       attribute \src "ls180.v:0.0-0.0"
125136       case 2'00
125137         assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write
125138       attribute \src "ls180.v:0.0-0.0"
125139       case 2'01
125140         assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write
125141       attribute \src "ls180.v:0.0-0.0"
125142       case 2'10
125143         assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write
125144       attribute \src "ls180.v:0.0-0.0"
125145       case
125146         assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write
125147     end
125148     sync always
125149       update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0]
125150   end
125151   attribute \src "ls180.v:6605.1-6621.4"
125152   process $proc$ls180.v:6605$2245
125153     assign { } { }
125154     assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0
125155     attribute \src "ls180.v:6607.2-6620.9"
125156     switch \main_sdram_choose_cmd_grant
125157       attribute \src "ls180.v:0.0-0.0"
125158       case 2'00
125159         assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd
125160       attribute \src "ls180.v:0.0-0.0"
125161       case 2'01
125162         assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd
125163       attribute \src "ls180.v:0.0-0.0"
125164       case 2'10
125165         assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd
125166       attribute \src "ls180.v:0.0-0.0"
125167       case
125168         assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd
125169     end
125170     sync always
125171       update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0]
125172   end
125173   attribute \src "ls180.v:661.5-661.51"
125174   process $proc$ls180.v:661$3014
125175     assign { } { }
125176     assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
125177     sync always
125178     sync init
125179       update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
125180   end
125181   attribute \src "ls180.v:662.5-662.51"
125182   process $proc$ls180.v:662$3015
125183     assign { } { }
125184     assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
125185     sync always
125186     sync init
125187       update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0]
125188   end
125189   attribute \src "ls180.v:6622.1-6638.4"
125190   process $proc$ls180.v:6622$2246
125191     assign { } { }
125192     assign $0\builder_comb_t_array_muxed0[0:0] 1'0
125193     attribute \src "ls180.v:6624.2-6637.9"
125194     switch \main_sdram_choose_cmd_grant
125195       attribute \src "ls180.v:0.0-0.0"
125196       case 2'00
125197         assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas
125198       attribute \src "ls180.v:0.0-0.0"
125199       case 2'01
125200         assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas
125201       attribute \src "ls180.v:0.0-0.0"
125202       case 2'10
125203         assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas
125204       attribute \src "ls180.v:0.0-0.0"
125205       case
125206         assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas
125207     end
125208     sync always
125209       update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0]
125210   end
125211   attribute \src "ls180.v:6639.1-6655.4"
125212   process $proc$ls180.v:6639$2247
125213     assign { } { }
125214     assign $0\builder_comb_t_array_muxed1[0:0] 1'0
125215     attribute \src "ls180.v:6641.2-6654.9"
125216     switch \main_sdram_choose_cmd_grant
125217       attribute \src "ls180.v:0.0-0.0"
125218       case 2'00
125219         assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras
125220       attribute \src "ls180.v:0.0-0.0"
125221       case 2'01
125222         assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras
125223       attribute \src "ls180.v:0.0-0.0"
125224       case 2'10
125225         assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras
125226       attribute \src "ls180.v:0.0-0.0"
125227       case
125228         assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras
125229     end
125230     sync always
125231       update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0]
125232   end
125233   attribute \src "ls180.v:664.5-664.47"
125234   process $proc$ls180.v:664$3016
125235     assign { } { }
125236     assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
125237     sync always
125238     sync init
125239       update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
125240   end
125241   attribute \src "ls180.v:665.5-665.45"
125242   process $proc$ls180.v:665$3017
125243     assign { } { }
125244     assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
125245     sync always
125246     sync init
125247       update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0]
125248   end
125249   attribute \src "ls180.v:6656.1-6672.4"
125250   process $proc$ls180.v:6656$2248
125251     assign { } { }
125252     assign $0\builder_comb_t_array_muxed2[0:0] 1'0
125253     attribute \src "ls180.v:6658.2-6671.9"
125254     switch \main_sdram_choose_cmd_grant
125255       attribute \src "ls180.v:0.0-0.0"
125256       case 2'00
125257         assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we
125258       attribute \src "ls180.v:0.0-0.0"
125259       case 2'01
125260         assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we
125261       attribute \src "ls180.v:0.0-0.0"
125262       case 2'10
125263         assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we
125264       attribute \src "ls180.v:0.0-0.0"
125265       case
125266         assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we
125267     end
125268     sync always
125269       update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0]
125270   end
125271   attribute \src "ls180.v:666.5-666.45"
125272   process $proc$ls180.v:666$3018
125273     assign { } { }
125274     assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
125275     sync always
125276     sync init
125277       update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
125278   end
125279   attribute \src "ls180.v:667.12-667.57"
125280   process $proc$ls180.v:667$3019
125281     assign { } { }
125282     assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
125283     sync always
125284     sync init
125285       update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0]
125286   end
125287   attribute \src "ls180.v:6673.1-6689.4"
125288   process $proc$ls180.v:6673$2249
125289     assign { } { }
125290     assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0
125291     attribute \src "ls180.v:6675.2-6688.9"
125292     switch \main_sdram_choose_req_grant
125293       attribute \src "ls180.v:0.0-0.0"
125294       case 2'00
125295         assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0]
125296       attribute \src "ls180.v:0.0-0.0"
125297       case 2'01
125298         assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1]
125299       attribute \src "ls180.v:0.0-0.0"
125300       case 2'10
125301         assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2]
125302       attribute \src "ls180.v:0.0-0.0"
125303       case
125304         assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3]
125305     end
125306     sync always
125307       update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0]
125308   end
125309   attribute \src "ls180.v:669.5-669.51"
125310   process $proc$ls180.v:669$3020
125311     assign { } { }
125312     assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
125313     sync always
125314     sync init
125315       update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0]
125316   end
125317   attribute \src "ls180.v:6690.1-6706.4"
125318   process $proc$ls180.v:6690$2250
125319     assign { } { }
125320     assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
125321     attribute \src "ls180.v:6692.2-6705.9"
125322     switch \main_sdram_choose_req_grant
125323       attribute \src "ls180.v:0.0-0.0"
125324       case 2'00
125325         assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a
125326       attribute \src "ls180.v:0.0-0.0"
125327       case 2'01
125328         assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a
125329       attribute \src "ls180.v:0.0-0.0"
125330       case 2'10
125331         assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a
125332       attribute \src "ls180.v:0.0-0.0"
125333       case
125334         assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a
125335     end
125336     sync always
125337       update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0]
125338   end
125339   attribute \src "ls180.v:670.5-670.51"
125340   process $proc$ls180.v:670$3021
125341     assign { } { }
125342     assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
125343     sync always
125344     sync init
125345       update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0]
125346   end
125347   attribute \src "ls180.v:6707.1-6723.4"
125348   process $proc$ls180.v:6707$2251
125349     assign { } { }
125350     assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00
125351     attribute \src "ls180.v:6709.2-6722.9"
125352     switch \main_sdram_choose_req_grant
125353       attribute \src "ls180.v:0.0-0.0"
125354       case 2'00
125355         assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba
125356       attribute \src "ls180.v:0.0-0.0"
125357       case 2'01
125358         assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba
125359       attribute \src "ls180.v:0.0-0.0"
125360       case 2'10
125361         assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba
125362       attribute \src "ls180.v:0.0-0.0"
125363       case
125364         assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba
125365     end
125366     sync always
125367       update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0]
125368   end
125369   attribute \src "ls180.v:671.5-671.50"
125370   process $proc$ls180.v:671$3022
125371     assign { } { }
125372     assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
125373     sync always
125374     sync init
125375       update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
125376   end
125377   attribute \src "ls180.v:672.5-672.54"
125378   process $proc$ls180.v:672$3023
125379     assign { } { }
125380     assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
125381     sync always
125382     sync init
125383       update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]
125384   end
125385   attribute \src "ls180.v:6724.1-6740.4"
125386   process $proc$ls180.v:6724$2252
125387     assign { } { }
125388     assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0
125389     attribute \src "ls180.v:6726.2-6739.9"
125390     switch \main_sdram_choose_req_grant
125391       attribute \src "ls180.v:0.0-0.0"
125392       case 2'00
125393         assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read
125394       attribute \src "ls180.v:0.0-0.0"
125395       case 2'01
125396         assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read
125397       attribute \src "ls180.v:0.0-0.0"
125398       case 2'10
125399         assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read
125400       attribute \src "ls180.v:0.0-0.0"
125401       case
125402         assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read
125403     end
125404     sync always
125405       update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0]
125406   end
125407   attribute \src "ls180.v:673.5-673.55"
125408   process $proc$ls180.v:673$3024
125409     assign { } { }
125410     assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
125411     sync always
125412     sync init
125413       update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
125414   end
125415   attribute \src "ls180.v:674.5-674.56"
125416   process $proc$ls180.v:674$3025
125417     assign { } { }
125418     assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
125419     sync always
125420     sync init
125421       update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0]
125422   end
125423   attribute \src "ls180.v:6741.1-6757.4"
125424   process $proc$ls180.v:6741$2253
125425     assign { } { }
125426     assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0
125427     attribute \src "ls180.v:6743.2-6756.9"
125428     switch \main_sdram_choose_req_grant
125429       attribute \src "ls180.v:0.0-0.0"
125430       case 2'00
125431         assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write
125432       attribute \src "ls180.v:0.0-0.0"
125433       case 2'01
125434         assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write
125435       attribute \src "ls180.v:0.0-0.0"
125436       case 2'10
125437         assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write
125438       attribute \src "ls180.v:0.0-0.0"
125439       case
125440         assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write
125441     end
125442     sync always
125443       update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0]
125444   end
125445   attribute \src "ls180.v:675.5-675.50"
125446   process $proc$ls180.v:675$3026
125447     assign { } { }
125448     assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
125449     sync always
125450     sync init
125451       update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0]
125452   end
125453   attribute \src "ls180.v:6758.1-6774.4"
125454   process $proc$ls180.v:6758$2254
125455     assign { } { }
125456     assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0
125457     attribute \src "ls180.v:6760.2-6773.9"
125458     switch \main_sdram_choose_req_grant
125459       attribute \src "ls180.v:0.0-0.0"
125460       case 2'00
125461         assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd
125462       attribute \src "ls180.v:0.0-0.0"
125463       case 2'01
125464         assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd
125465       attribute \src "ls180.v:0.0-0.0"
125466       case 2'10
125467         assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd
125468       attribute \src "ls180.v:0.0-0.0"
125469       case
125470         assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd
125471     end
125472     sync always
125473       update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0]
125474   end
125475   attribute \src "ls180.v:6775.1-6791.4"
125476   process $proc$ls180.v:6775$2255
125477     assign { } { }
125478     assign $0\builder_comb_t_array_muxed3[0:0] 1'0
125479     attribute \src "ls180.v:6777.2-6790.9"
125480     switch \main_sdram_choose_req_grant
125481       attribute \src "ls180.v:0.0-0.0"
125482       case 2'00
125483         assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas
125484       attribute \src "ls180.v:0.0-0.0"
125485       case 2'01
125486         assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas
125487       attribute \src "ls180.v:0.0-0.0"
125488       case 2'10
125489         assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas
125490       attribute \src "ls180.v:0.0-0.0"
125491       case
125492         assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas
125493     end
125494     sync always
125495       update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0]
125496   end
125497   attribute \src "ls180.v:678.5-678.67"
125498   process $proc$ls180.v:678$3027
125499     assign { } { }
125500     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
125501     sync always
125502       update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
125503     sync init
125504   end
125505   attribute \src "ls180.v:679.5-679.66"
125506   process $proc$ls180.v:679$3028
125507     assign { } { }
125508     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
125509     sync always
125510       update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
125511     sync init
125512   end
125513   attribute \src "ls180.v:6792.1-6808.4"
125514   process $proc$ls180.v:6792$2256
125515     assign { } { }
125516     assign $0\builder_comb_t_array_muxed4[0:0] 1'0
125517     attribute \src "ls180.v:6794.2-6807.9"
125518     switch \main_sdram_choose_req_grant
125519       attribute \src "ls180.v:0.0-0.0"
125520       case 2'00
125521         assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras
125522       attribute \src "ls180.v:0.0-0.0"
125523       case 2'01
125524         assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras
125525       attribute \src "ls180.v:0.0-0.0"
125526       case 2'10
125527         assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras
125528       attribute \src "ls180.v:0.0-0.0"
125529       case
125530         assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras
125531     end
125532     sync always
125533       update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0]
125534   end
125535   attribute \src "ls180.v:6809.1-6825.4"
125536   process $proc$ls180.v:6809$2257
125537     assign { } { }
125538     assign $0\builder_comb_t_array_muxed5[0:0] 1'0
125539     attribute \src "ls180.v:6811.2-6824.9"
125540     switch \main_sdram_choose_req_grant
125541       attribute \src "ls180.v:0.0-0.0"
125542       case 2'00
125543         assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we
125544       attribute \src "ls180.v:0.0-0.0"
125545       case 2'01
125546         assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we
125547       attribute \src "ls180.v:0.0-0.0"
125548       case 2'10
125549         assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we
125550       attribute \src "ls180.v:0.0-0.0"
125551       case
125552         assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we
125553     end
125554     sync always
125555       update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0]
125556   end
125557   attribute \src "ls180.v:6826.1-6833.4"
125558   process $proc$ls180.v:6826$2258
125559     assign { } { }
125560     assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
125561     attribute \src "ls180.v:6828.2-6832.9"
125562     switch \builder_roundrobin0_grant
125563       attribute \src "ls180.v:0.0-0.0"
125564       case
125565         assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] }
125566     end
125567     sync always
125568       update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0]
125569   end
125570   attribute \src "ls180.v:6834.1-6841.4"
125571   process $proc$ls180.v:6834$2259
125572     assign { } { }
125573     assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0
125574     attribute \src "ls180.v:6836.2-6840.9"
125575     switch \builder_roundrobin0_grant
125576       attribute \src "ls180.v:0.0-0.0"
125577       case
125578         assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we
125579     end
125580     sync always
125581       update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0]
125582   end
125583   attribute \src "ls180.v:6842.1-6849.4"
125584   process $proc$ls180.v:6842$2260
125585     assign { } { }
125586     assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0
125587     attribute \src "ls180.v:6844.2-6848.9"
125588     switch \builder_roundrobin0_grant
125589       attribute \src "ls180.v:0.0-0.0"
125590       case
125591         assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6846$2273_Y
125592     end
125593     sync always
125594       update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0]
125595   end
125596   attribute \src "ls180.v:6850.1-6857.4"
125597   process $proc$ls180.v:6850$2274
125598     assign { } { }
125599     assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
125600     attribute \src "ls180.v:6852.2-6856.9"
125601     switch \builder_roundrobin1_grant
125602       attribute \src "ls180.v:0.0-0.0"
125603       case
125604         assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] }
125605     end
125606     sync always
125607       update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0]
125608   end
125609   attribute \src "ls180.v:6858.1-6865.4"
125610   process $proc$ls180.v:6858$2275
125611     assign { } { }
125612     assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0
125613     attribute \src "ls180.v:6860.2-6864.9"
125614     switch \builder_roundrobin1_grant
125615       attribute \src "ls180.v:0.0-0.0"
125616       case
125617         assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we
125618     end
125619     sync always
125620       update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0]
125621   end
125622   attribute \src "ls180.v:6866.1-6873.4"
125623   process $proc$ls180.v:6866$2276
125624     assign { } { }
125625     assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0
125626     attribute \src "ls180.v:6868.2-6872.9"
125627     switch \builder_roundrobin1_grant
125628       attribute \src "ls180.v:0.0-0.0"
125629       case
125630         assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6870$2289_Y
125631     end
125632     sync always
125633       update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0]
125634   end
125635   attribute \src "ls180.v:6874.1-6881.4"
125636   process $proc$ls180.v:6874$2290
125637     assign { } { }
125638     assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
125639     attribute \src "ls180.v:6876.2-6880.9"
125640     switch \builder_roundrobin2_grant
125641       attribute \src "ls180.v:0.0-0.0"
125642       case
125643         assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] }
125644     end
125645     sync always
125646       update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0]
125647   end
125648   attribute \src "ls180.v:6882.1-6889.4"
125649   process $proc$ls180.v:6882$2291
125650     assign { } { }
125651     assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0
125652     attribute \src "ls180.v:6884.2-6888.9"
125653     switch \builder_roundrobin2_grant
125654       attribute \src "ls180.v:0.0-0.0"
125655       case
125656         assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we
125657     end
125658     sync always
125659       update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0]
125660   end
125661   attribute \src "ls180.v:6890.1-6897.4"
125662   process $proc$ls180.v:6890$2292
125663     assign { } { }
125664     assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0
125665     attribute \src "ls180.v:6892.2-6896.9"
125666     switch \builder_roundrobin2_grant
125667       attribute \src "ls180.v:0.0-0.0"
125668       case
125669         assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6894$2305_Y
125670     end
125671     sync always
125672       update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0]
125673   end
125674   attribute \src "ls180.v:6898.1-6905.4"
125675   process $proc$ls180.v:6898$2306
125676     assign { } { }
125677     assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
125678     attribute \src "ls180.v:6900.2-6904.9"
125679     switch \builder_roundrobin3_grant
125680       attribute \src "ls180.v:0.0-0.0"
125681       case
125682         assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] }
125683     end
125684     sync always
125685       update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0]
125686   end
125687   attribute \src "ls180.v:6906.1-6913.4"
125688   process $proc$ls180.v:6906$2307
125689     assign { } { }
125690     assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0
125691     attribute \src "ls180.v:6908.2-6912.9"
125692     switch \builder_roundrobin3_grant
125693       attribute \src "ls180.v:0.0-0.0"
125694       case
125695         assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we
125696     end
125697     sync always
125698       update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0]
125699   end
125700   attribute \src "ls180.v:6914.1-6921.4"
125701   process $proc$ls180.v:6914$2308
125702     assign { } { }
125703     assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0
125704     attribute \src "ls180.v:6916.2-6920.9"
125705     switch \builder_roundrobin3_grant
125706       attribute \src "ls180.v:0.0-0.0"
125707       case
125708         assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6918$2321_Y
125709     end
125710     sync always
125711       update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0]
125712   end
125713   attribute \src "ls180.v:6922.1-6941.4"
125714   process $proc$ls180.v:6922$2322
125715     assign { } { }
125716     assign $0\builder_comb_rhs_array_muxed24[31:0] 0
125717     attribute \src "ls180.v:6924.2-6940.9"
125718     switch \builder_grant
125719       attribute \src "ls180.v:0.0-0.0"
125720       case 3'000
125721         assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr }
125722       attribute \src "ls180.v:0.0-0.0"
125723       case 3'001
125724         assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr }
125725       attribute \src "ls180.v:0.0-0.0"
125726       case 3'010
125727         assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr }
125728       attribute \src "ls180.v:0.0-0.0"
125729       case 3'011
125730         assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr
125731       attribute \src "ls180.v:0.0-0.0"
125732       case
125733         assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr
125734     end
125735     sync always
125736       update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0]
125737   end
125738   attribute \src "ls180.v:694.11-694.68"
125739   process $proc$ls180.v:694$3029
125740     assign { } { }
125741     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
125742     sync always
125743     sync init
125744       update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
125745   end
125746   attribute \src "ls180.v:6942.1-6961.4"
125747   process $proc$ls180.v:6942$2323
125748     assign { } { }
125749     assign $0\builder_comb_rhs_array_muxed25[31:0] 0
125750     attribute \src "ls180.v:6944.2-6960.9"
125751     switch \builder_grant
125752       attribute \src "ls180.v:0.0-0.0"
125753       case 3'000
125754         assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w
125755       attribute \src "ls180.v:0.0-0.0"
125756       case 3'001
125757         assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w
125758       attribute \src "ls180.v:0.0-0.0"
125759       case 3'010
125760         assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w
125761       attribute \src "ls180.v:0.0-0.0"
125762       case 3'011
125763         assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w
125764       attribute \src "ls180.v:0.0-0.0"
125765       case
125766         assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w
125767     end
125768     sync always
125769       update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0]
125770   end
125771   attribute \src "ls180.v:695.5-695.64"
125772   process $proc$ls180.v:695$3030
125773     assign { } { }
125774     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
125775     sync always
125776       update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
125777     sync init
125778   end
125779   attribute \src "ls180.v:696.11-696.70"
125780   process $proc$ls180.v:696$3031
125781     assign { } { }
125782     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
125783     sync always
125784     sync init
125785       update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
125786   end
125787   attribute \src "ls180.v:6962.1-6981.4"
125788   process $proc$ls180.v:6962$2324
125789     assign { } { }
125790     assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000
125791     attribute \src "ls180.v:6964.2-6980.9"
125792     switch \builder_grant
125793       attribute \src "ls180.v:0.0-0.0"
125794       case 3'000
125795         assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel
125796       attribute \src "ls180.v:0.0-0.0"
125797       case 3'001
125798         assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel
125799       attribute \src "ls180.v:0.0-0.0"
125800       case 3'010
125801         assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel
125802       attribute \src "ls180.v:0.0-0.0"
125803       case 3'011
125804         assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel
125805       attribute \src "ls180.v:0.0-0.0"
125806       case
125807         assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel
125808     end
125809     sync always
125810       update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0]
125811   end
125812   attribute \src "ls180.v:697.11-697.70"
125813   process $proc$ls180.v:697$3032
125814     assign { } { }
125815     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
125816     sync always
125817     sync init
125818       update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
125819   end
125820   attribute \src "ls180.v:698.11-698.73"
125821   process $proc$ls180.v:698$3033
125822     assign { } { }
125823     assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
125824     sync always
125825     sync init
125826       update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
125827   end
125828   attribute \src "ls180.v:6982.1-7001.4"
125829   process $proc$ls180.v:6982$2325
125830     assign { } { }
125831     assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0
125832     attribute \src "ls180.v:6984.2-7000.9"
125833     switch \builder_grant
125834       attribute \src "ls180.v:0.0-0.0"
125835       case 3'000
125836         assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc
125837       attribute \src "ls180.v:0.0-0.0"
125838       case 3'001
125839         assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc
125840       attribute \src "ls180.v:0.0-0.0"
125841       case 3'010
125842         assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc
125843       attribute \src "ls180.v:0.0-0.0"
125844       case 3'011
125845         assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc
125846       attribute \src "ls180.v:0.0-0.0"
125847       case
125848         assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc
125849     end
125850     sync always
125851       update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0]
125852   end
125853   attribute \src "ls180.v:7002.1-7021.4"
125854   process $proc$ls180.v:7002$2326
125855     assign { } { }
125856     assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0
125857     attribute \src "ls180.v:7004.2-7020.9"
125858     switch \builder_grant
125859       attribute \src "ls180.v:0.0-0.0"
125860       case 3'000
125861         assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb
125862       attribute \src "ls180.v:0.0-0.0"
125863       case 3'001
125864         assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb
125865       attribute \src "ls180.v:0.0-0.0"
125866       case 3'010
125867         assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb
125868       attribute \src "ls180.v:0.0-0.0"
125869       case 3'011
125870         assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb
125871       attribute \src "ls180.v:0.0-0.0"
125872       case
125873         assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb
125874     end
125875     sync always
125876       update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0]
125877   end
125878   attribute \src "ls180.v:7022.1-7041.4"
125879   process $proc$ls180.v:7022$2327
125880     assign { } { }
125881     assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0
125882     attribute \src "ls180.v:7024.2-7040.9"
125883     switch \builder_grant
125884       attribute \src "ls180.v:0.0-0.0"
125885       case 3'000
125886         assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we
125887       attribute \src "ls180.v:0.0-0.0"
125888       case 3'001
125889         assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we
125890       attribute \src "ls180.v:0.0-0.0"
125891       case 3'010
125892         assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we
125893       attribute \src "ls180.v:0.0-0.0"
125894       case 3'011
125895         assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we
125896       attribute \src "ls180.v:0.0-0.0"
125897       case
125898         assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we
125899     end
125900     sync always
125901       update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0]
125902   end
125903   attribute \src "ls180.v:7042.1-7061.4"
125904   process $proc$ls180.v:7042$2328
125905     assign { } { }
125906     assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000
125907     attribute \src "ls180.v:7044.2-7060.9"
125908     switch \builder_grant
125909       attribute \src "ls180.v:0.0-0.0"
125910       case 3'000
125911         assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti
125912       attribute \src "ls180.v:0.0-0.0"
125913       case 3'001
125914         assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti
125915       attribute \src "ls180.v:0.0-0.0"
125916       case 3'010
125917         assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti
125918       attribute \src "ls180.v:0.0-0.0"
125919       case 3'011
125920         assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti
125921       attribute \src "ls180.v:0.0-0.0"
125922       case
125923         assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti
125924     end
125925     sync always
125926       update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0]
125927   end
125928   attribute \src "ls180.v:7062.1-7081.4"
125929   process $proc$ls180.v:7062$2329
125930     assign { } { }
125931     assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00
125932     attribute \src "ls180.v:7064.2-7080.9"
125933     switch \builder_grant
125934       attribute \src "ls180.v:0.0-0.0"
125935       case 3'000
125936         assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte
125937       attribute \src "ls180.v:0.0-0.0"
125938       case 3'001
125939         assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte
125940       attribute \src "ls180.v:0.0-0.0"
125941       case 3'010
125942         assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte
125943       attribute \src "ls180.v:0.0-0.0"
125944       case 3'011
125945         assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte
125946       attribute \src "ls180.v:0.0-0.0"
125947       case
125948         assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte
125949     end
125950     sync always
125951       update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0]
125952   end
125953   attribute \src "ls180.v:7082.1-7098.4"
125954   process $proc$ls180.v:7082$2330
125955     assign { } { }
125956     assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00
125957     attribute \src "ls180.v:7084.2-7097.9"
125958     switch \main_sdram_steerer_sel
125959       attribute \src "ls180.v:0.0-0.0"
125960       case 2'00
125961         assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba
125962       attribute \src "ls180.v:0.0-0.0"
125963       case 2'01
125964         assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba
125965       attribute \src "ls180.v:0.0-0.0"
125966       case 2'10
125967         assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba
125968       attribute \src "ls180.v:0.0-0.0"
125969       case
125970         assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba
125971     end
125972     sync always
125973       update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0]
125974   end
125975   attribute \src "ls180.v:7099.1-7115.4"
125976   process $proc$ls180.v:7099$2331
125977     assign { } { }
125978     assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
125979     attribute \src "ls180.v:7101.2-7114.9"
125980     switch \main_sdram_steerer_sel
125981       attribute \src "ls180.v:0.0-0.0"
125982       case 2'00
125983         assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a
125984       attribute \src "ls180.v:0.0-0.0"
125985       case 2'01
125986         assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a
125987       attribute \src "ls180.v:0.0-0.0"
125988       case 2'10
125989         assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a
125990       attribute \src "ls180.v:0.0-0.0"
125991       case
125992         assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a
125993     end
125994     sync always
125995       update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0]
125996   end
125997   attribute \src "ls180.v:7116.1-7132.4"
125998   process $proc$ls180.v:7116$2332
125999     assign { } { }
126000     assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
126001     attribute \src "ls180.v:7118.2-7131.9"
126002     switch \main_sdram_steerer_sel
126003       attribute \src "ls180.v:0.0-0.0"
126004       case 2'00
126005         assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0
126006       attribute \src "ls180.v:0.0-0.0"
126007       case 2'01
126008         assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7123$2334_Y
126009       attribute \src "ls180.v:0.0-0.0"
126010       case 2'10
126011         assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7126$2336_Y
126012       attribute \src "ls180.v:0.0-0.0"
126013       case
126014         assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7129$2338_Y
126015     end
126016     sync always
126017       update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0]
126018   end
126019   attribute \src "ls180.v:7133.1-7149.4"
126020   process $proc$ls180.v:7133$2339
126021     assign { } { }
126022     assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
126023     attribute \src "ls180.v:7135.2-7148.9"
126024     switch \main_sdram_steerer_sel
126025       attribute \src "ls180.v:0.0-0.0"
126026       case 2'00
126027         assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0
126028       attribute \src "ls180.v:0.0-0.0"
126029       case 2'01
126030         assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7140$2341_Y
126031       attribute \src "ls180.v:0.0-0.0"
126032       case 2'10
126033         assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7143$2343_Y
126034       attribute \src "ls180.v:0.0-0.0"
126035       case
126036         assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7146$2345_Y
126037     end
126038     sync always
126039       update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0]
126040   end
126041   attribute \src "ls180.v:7150.1-7166.4"
126042   process $proc$ls180.v:7150$2346
126043     assign { } { }
126044     assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
126045     attribute \src "ls180.v:7152.2-7165.9"
126046     switch \main_sdram_steerer_sel
126047       attribute \src "ls180.v:0.0-0.0"
126048       case 2'00
126049         assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0
126050       attribute \src "ls180.v:0.0-0.0"
126051       case 2'01
126052         assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7157$2348_Y
126053       attribute \src "ls180.v:0.0-0.0"
126054       case 2'10
126055         assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7160$2350_Y
126056       attribute \src "ls180.v:0.0-0.0"
126057       case
126058         assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7163$2352_Y
126059     end
126060     sync always
126061       update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0]
126062   end
126063   attribute \src "ls180.v:7167.1-7183.4"
126064   process $proc$ls180.v:7167$2353
126065     assign { } { }
126066     assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
126067     attribute \src "ls180.v:7169.2-7182.9"
126068     switch \main_sdram_steerer_sel
126069       attribute \src "ls180.v:0.0-0.0"
126070       case 2'00
126071         assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0
126072       attribute \src "ls180.v:0.0-0.0"
126073       case 2'01
126074         assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7174$2355_Y
126075       attribute \src "ls180.v:0.0-0.0"
126076       case 2'10
126077         assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7177$2357_Y
126078       attribute \src "ls180.v:0.0-0.0"
126079       case
126080         assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7180$2359_Y
126081     end
126082     sync always
126083       update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0]
126084   end
126085   attribute \src "ls180.v:7184.1-7200.4"
126086   process $proc$ls180.v:7184$2360
126087     assign { } { }
126088     assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
126089     attribute \src "ls180.v:7186.2-7199.9"
126090     switch \main_sdram_steerer_sel
126091       attribute \src "ls180.v:0.0-0.0"
126092       case 2'00
126093         assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0
126094       attribute \src "ls180.v:0.0-0.0"
126095       case 2'01
126096         assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7191$2362_Y
126097       attribute \src "ls180.v:0.0-0.0"
126098       case 2'10
126099         assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7194$2364_Y
126100       attribute \src "ls180.v:0.0-0.0"
126101       case
126102         assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7197$2366_Y
126103     end
126104     sync always
126105       update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0]
126106   end
126107   attribute \src "ls180.v:719.5-719.59"
126108   process $proc$ls180.v:719$3034
126109     assign { } { }
126110     assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
126111     sync always
126112     sync init
126113       update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
126114   end
126115   attribute \src "ls180.v:72.5-72.46"
126116   process $proc$ls180.v:72$2781
126117     assign { } { }
126118     assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0
126119     sync always
126120     sync init
126121       update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0]
126122   end
126123   attribute \src "ls180.v:7201.1-7229.4"
126124   process $proc$ls180.v:7201$2367
126125     assign { } { }
126126     assign $0\builder_sync_f_array_muxed0[0:0] 1'0
126127     attribute \src "ls180.v:7203.2-7228.9"
126128     switch \main_spimaster34_mosi_sel
126129       attribute \src "ls180.v:0.0-0.0"
126130       case 3'000
126131         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0]
126132       attribute \src "ls180.v:0.0-0.0"
126133       case 3'001
126134         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1]
126135       attribute \src "ls180.v:0.0-0.0"
126136       case 3'010
126137         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2]
126138       attribute \src "ls180.v:0.0-0.0"
126139       case 3'011
126140         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3]
126141       attribute \src "ls180.v:0.0-0.0"
126142       case 3'100
126143         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4]
126144       attribute \src "ls180.v:0.0-0.0"
126145       case 3'101
126146         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5]
126147       attribute \src "ls180.v:0.0-0.0"
126148       case 3'110
126149         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6]
126150       attribute \src "ls180.v:0.0-0.0"
126151       case
126152         assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7]
126153     end
126154     sync always
126155       update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0]
126156   end
126157   attribute \src "ls180.v:721.5-721.59"
126158   process $proc$ls180.v:721$3035
126159     assign { } { }
126160     assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
126161     sync always
126162     sync init
126163       update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
126164   end
126165   attribute \src "ls180.v:722.5-722.58"
126166   process $proc$ls180.v:722$3036
126167     assign { } { }
126168     assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
126169     sync always
126170     sync init
126171       update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
126172   end
126173   attribute \src "ls180.v:723.5-723.64"
126174   process $proc$ls180.v:723$3037
126175     assign { } { }
126176     assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
126177     sync always
126178     sync init
126179       update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
126180   end
126181   attribute \src "ls180.v:7230.1-7258.4"
126182   process $proc$ls180.v:7230$2368
126183     assign { } { }
126184     assign $0\builder_sync_f_array_muxed1[0:0] 1'0
126185     attribute \src "ls180.v:7232.2-7257.9"
126186     switch \main_spisdcard_mosi_sel
126187       attribute \src "ls180.v:0.0-0.0"
126188       case 3'000
126189         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0]
126190       attribute \src "ls180.v:0.0-0.0"
126191       case 3'001
126192         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1]
126193       attribute \src "ls180.v:0.0-0.0"
126194       case 3'010
126195         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2]
126196       attribute \src "ls180.v:0.0-0.0"
126197       case 3'011
126198         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3]
126199       attribute \src "ls180.v:0.0-0.0"
126200       case 3'100
126201         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4]
126202       attribute \src "ls180.v:0.0-0.0"
126203       case 3'101
126204         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5]
126205       attribute \src "ls180.v:0.0-0.0"
126206       case 3'110
126207         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6]
126208       attribute \src "ls180.v:0.0-0.0"
126209       case
126210         assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7]
126211     end
126212     sync always
126213       update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0]
126214   end
126215   attribute \src "ls180.v:724.12-724.74"
126216   process $proc$ls180.v:724$3038
126217     assign { } { }
126218     assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
126219     sync always
126220     sync init
126221       update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
126222   end
126223   attribute \src "ls180.v:725.12-725.47"
126224   process $proc$ls180.v:725$3039
126225     assign { } { }
126226     assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
126227     sync always
126228     sync init
126229       update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
126230   end
126231   attribute \src "ls180.v:726.5-726.46"
126232   process $proc$ls180.v:726$3040
126233     assign { } { }
126234     assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
126235     sync always
126236     sync init
126237       update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
126238   end
126239   attribute \src "ls180.v:728.5-728.44"
126240   process $proc$ls180.v:728$3041
126241     assign { } { }
126242     assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
126243     sync always
126244     sync init
126245       update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
126246   end
126247   attribute \src "ls180.v:729.5-729.45"
126248   process $proc$ls180.v:729$3042
126249     assign { } { }
126250     assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
126251     sync always
126252     sync init
126253       update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
126254   end
126255   attribute \src "ls180.v:730.5-730.54"
126256   process $proc$ls180.v:730$3043
126257     assign { } { }
126258     assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
126259     sync always
126260     sync init
126261       update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]
126262   end
126263   attribute \src "ls180.v:7316.1-7334.4"
126264   process $proc$ls180.v:7316$2369
126265     assign { } { }
126266     assign { } { }
126267     assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1
126268     assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1
126269     assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1
126270     assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1
126271     assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1
126272     assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1
126273     assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1
126274     assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1
126275     assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1
126276     assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1
126277     assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1
126278     assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1
126279     assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1
126280     assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1
126281     assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1
126282     assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1
126283     sync always
126284       update \main_gpio_status $0\main_gpio_status[15:0]
126285   end
126286   attribute \src "ls180.v:732.32-732.76"
126287   process $proc$ls180.v:732$3044
126288     assign { } { }
126289     assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
126290     sync always
126291     sync init
126292       update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
126293   end
126294   attribute \src "ls180.v:733.11-733.55"
126295   process $proc$ls180.v:733$3045
126296     assign { } { }
126297     assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
126298     sync always
126299     sync init
126300       update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
126301   end
126302   attribute \src "ls180.v:735.32-735.75"
126303   process $proc$ls180.v:735$3046
126304     assign { } { }
126305     assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
126306     sync always
126307       update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0]
126308     sync init
126309   end
126310   attribute \src "ls180.v:7355.1-7357.4"
126311   process $proc$ls180.v:7355$2370
126312     assign { } { }
126313     assign $0\main_int_rst[0:0] \sys_rst
126314     sync posedge \por_clk
126315       update \main_int_rst $0\main_int_rst[0:0]
126316   end
126317   attribute \src "ls180.v:7359.1-7429.4"
126318   process $proc$ls180.v:7359$2371
126319     assign { } { }
126320     assign { } { }
126321     assign { } { }
126322     assign { } { }
126323     assign { } { }
126324     assign { } { }
126325     assign { } { }
126326     assign { } { }
126327     assign { } { }
126328     assign { } { }
126329     assign { } { }
126330     assign { } { }
126331     assign { } { }
126332     assign { } { }
126333     assign { } { }
126334     assign { } { }
126335     assign { } { }
126336     assign { } { }
126337     assign { } { }
126338     assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0]
126339     assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1]
126340     assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2]
126341     assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3]
126342     assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4]
126343     assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5]
126344     assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6]
126345     assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7]
126346     assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8]
126347     assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9]
126348     assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10]
126349     assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11]
126350     assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12]
126351     assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0]
126352     assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1]
126353     assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n
126354     assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n
126355     assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n
126356     assign $0\sdram_cke[0:0] \main_dfi_p0_cke
126357     assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n
126358     assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en
126359     assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0]
126360     assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0]
126361     assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1]
126362     assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1]
126363     assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2]
126364     assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2]
126365     assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3]
126366     assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3]
126367     assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4]
126368     assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4]
126369     assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5]
126370     assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5]
126371     assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6]
126372     assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6]
126373     assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7]
126374     assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7]
126375     assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8]
126376     assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8]
126377     assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9]
126378     assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9]
126379     assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10]
126380     assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10]
126381     assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11]
126382     assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11]
126383     assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12]
126384     assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12]
126385     assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13]
126386     assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13]
126387     assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14]
126388     assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14]
126389     assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15]
126390     assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15]
126391     assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0]
126392     assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1]
126393     assign $0\sdram_clock[0:0] \sys_clk_1
126394     assign $0\sdcard_clk[0:0] $and$ls180.v:7416$2373_Y
126395     assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe
126396     assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o
126397     assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i
126398     assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe
126399     assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0]
126400     assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0]
126401     assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1]
126402     assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1]
126403     assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2]
126404     assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2]
126405     assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3]
126406     assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3]
126407     sync posedge \sdrio_clk
126408       update \sdcard_clk $0\sdcard_clk[0:0]
126409       update \sdcard_cmd_o $0\sdcard_cmd_o[0:0]
126410       update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0]
126411       update \sdcard_data_o $0\sdcard_data_o[3:0]
126412       update \sdcard_data_oe $0\sdcard_data_oe[0:0]
126413       update \sdram_a $0\sdram_a[12:0]
126414       update \sdram_dq_o $0\sdram_dq_o[15:0]
126415       update \sdram_dq_oe $0\sdram_dq_oe[0:0]
126416       update \sdram_we_n $0\sdram_we_n[0:0]
126417       update \sdram_ras_n $0\sdram_ras_n[0:0]
126418       update \sdram_cas_n $0\sdram_cas_n[0:0]
126419       update \sdram_cs_n $0\sdram_cs_n[0:0]
126420       update \sdram_cke $0\sdram_cke[0:0]
126421       update \sdram_ba $0\sdram_ba[1:0]
126422       update \sdram_dm $0\sdram_dm[1:0]
126423       update \sdram_clock $0\sdram_clock[0:0]
126424       update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0]
126425       update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0]
126426       update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
126427   end
126428   attribute \src "ls180.v:737.32-737.76"
126429   process $proc$ls180.v:737$3047
126430     assign { } { }
126431     assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
126432     sync always
126433       update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0]
126434     sync init
126435   end
126436   attribute \src "ls180.v:740.5-740.44"
126437   process $proc$ls180.v:740$3048
126438     assign { } { }
126439     assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
126440     sync always
126441       update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0]
126442     sync init
126443   end
126444   attribute \src "ls180.v:741.5-741.45"
126445   process $proc$ls180.v:741$3049
126446     assign { } { }
126447     assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
126448     sync always
126449       update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0]
126450     sync init
126451   end
126452   attribute \src "ls180.v:742.5-742.43"
126453   process $proc$ls180.v:742$3050
126454     assign { } { }
126455     assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
126456     sync always
126457       update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0]
126458     sync init
126459   end
126460   attribute \src "ls180.v:743.5-743.48"
126461   process $proc$ls180.v:743$3051
126462     assign { } { }
126463     assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
126464     sync always
126465       update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0]
126466     sync init
126467   end
126468   attribute \src "ls180.v:7431.1-10055.4"
126469   process $proc$ls180.v:7431$2374
126470     assign $0\spisdcard_clk[0:0] \spisdcard_clk
126471     assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
126472     assign { } { }
126473     assign $0\uart_tx[0:0] \uart_tx
126474     assign $0\pwm[1:0] \pwm
126475     assign $0\spimaster_clk[0:0] \spimaster_clk
126476     assign $0\spimaster_mosi[0:0] \spimaster_mosi
126477     assign { } { }
126478     assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
126479     assign { } { }
126480     assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
126481     assign { } { }
126482     assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors
126483     assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter
126484     assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r
126485     assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter
126486     assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r
126487     assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter
126488     assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r
126489     assign { } { }
126490     assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage
126491     assign { } { }
126492     assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage
126493     assign { } { }
126494     assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage
126495     assign { } { }
126496     assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage
126497     assign { } { }
126498     assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status
126499     assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending
126500     assign { } { }
126501     assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage
126502     assign { } { }
126503     assign $0\main_libresocsim_value[31:0] \main_libresocsim_value
126504     assign { } { }
126505     assign { } { }
126506     assign $0\main_sdram_storage[3:0] \main_sdram_storage
126507     assign { } { }
126508     assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage
126509     assign { } { }
126510     assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage
126511     assign { } { }
126512     assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage
126513     assign { } { }
126514     assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage
126515     assign { } { }
126516     assign $0\main_sdram_status[15:0] \main_sdram_status
126517     assign { } { }
126518     assign { } { }
126519     assign { } { }
126520     assign { } { }
126521     assign { } { }
126522     assign { } { }
126523     assign { } { }
126524     assign { } { }
126525     assign { } { }
126526     assign { } { }
126527     assign { } { }
126528     assign { } { }
126529     assign { } { }
126530     assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1
126531     assign { } { }
126532     assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count
126533     assign { } { }
126534     assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter
126535     assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count
126536     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level
126537     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce
126538     assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
126539     assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid
126540     assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first
126541     assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last
126542     assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we
126543     assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr
126544     assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row
126545     assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened
126546     assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready
126547     assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count
126548     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level
126549     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce
126550     assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
126551     assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid
126552     assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first
126553     assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last
126554     assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we
126555     assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr
126556     assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row
126557     assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened
126558     assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready
126559     assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count
126560     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level
126561     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce
126562     assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
126563     assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid
126564     assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first
126565     assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last
126566     assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we
126567     assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr
126568     assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row
126569     assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened
126570     assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready
126571     assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count
126572     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level
126573     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce
126574     assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
126575     assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid
126576     assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first
126577     assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last
126578     assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we
126579     assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr
126580     assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row
126581     assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened
126582     assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready
126583     assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count
126584     assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant
126585     assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant
126586     assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready
126587     assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count
126588     assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready
126589     assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count
126590     assign $0\main_sdram_time0[4:0] \main_sdram_time0
126591     assign $0\main_sdram_time1[3:0] \main_sdram_time1
126592     assign $0\main_converter_counter[0:0] \main_converter_counter
126593     assign $0\main_converter_dat_r[31:0] \main_converter_dat_r
126594     assign $0\main_cmd_consumed[0:0] \main_cmd_consumed
126595     assign $0\main_wdata_consumed[0:0] \main_wdata_consumed
126596     assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage
126597     assign { } { }
126598     assign { } { }
126599     assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen
126600     assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx
126601     assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg
126602     assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount
126603     assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy
126604     assign { } { }
126605     assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data
126606     assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen
126607     assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx
126608     assign { } { }
126609     assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg
126610     assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount
126611     assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy
126612     assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending
126613     assign { } { }
126614     assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending
126615     assign { } { }
126616     assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage
126617     assign { } { }
126618     assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable
126619     assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0
126620     assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce
126621     assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume
126622     assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable
126623     assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0
126624     assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce
126625     assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume
126626     assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage
126627     assign { } { }
126628     assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage
126629     assign { } { }
126630     assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso
126631     assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage
126632     assign { } { }
126633     assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage
126634     assign { } { }
126635     assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage
126636     assign { } { }
126637     assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage
126638     assign { } { }
126639     assign $0\main_spimaster27_count[2:0] \main_spimaster27_count
126640     assign { } { }
126641     assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data
126642     assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel
126643     assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data
126644     assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso
126645     assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage
126646     assign { } { }
126647     assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage
126648     assign { } { }
126649     assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage
126650     assign { } { }
126651     assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage
126652     assign { } { }
126653     assign $0\main_spisdcard_count[2:0] \main_spisdcard_count
126654     assign { } { }
126655     assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data
126656     assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel
126657     assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data
126658     assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage
126659     assign { } { }
126660     assign { } { }
126661     assign $0\main_pwm0_counter[31:0] \main_pwm0_counter
126662     assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage
126663     assign { } { }
126664     assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage
126665     assign { } { }
126666     assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage
126667     assign { } { }
126668     assign $0\main_pwm1_counter[31:0] \main_pwm1_counter
126669     assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage
126670     assign { } { }
126671     assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage
126672     assign { } { }
126673     assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage
126674     assign { } { }
126675     assign $0\main_i2c_storage[2:0] \main_i2c_storage
126676     assign { } { }
126677     assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage
126678     assign { } { }
126679     assign { } { }
126680     assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks
126681     assign { } { }
126682     assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count
126683     assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count
126684     assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout
126685     assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count
126686     assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run
126687     assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first
126688     assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last
126689     assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data
126690     assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count
126691     assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux
126692     assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all
126693     assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid
126694     assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first
126695     assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last
126696     assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data
126697     assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset
126698     assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count
126699     assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run
126700     assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first
126701     assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last
126702     assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data
126703     assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count
126704     assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux
126705     assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all
126706     assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid
126707     assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first
126708     assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last
126709     assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data
126710     assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset
126711     assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout
126712     assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count
126713     assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run
126714     assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first
126715     assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last
126716     assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data
126717     assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count
126718     assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux
126719     assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all
126720     assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid
126721     assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first
126722     assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last
126723     assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data
126724     assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset
126725     assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage
126726     assign { } { }
126727     assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage
126728     assign { } { }
126729     assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status
126730     assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage
126731     assign { } { }
126732     assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage
126733     assign { } { }
126734     assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0
126735     assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt
126736     assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0
126737     assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0
126738     assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0
126739     assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0
126740     assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0
126741     assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1
126742     assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2
126743     assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3
126744     assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val
126745     assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt
126746     assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0
126747     assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0
126748     assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0
126749     assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0
126750     assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0
126751     assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1
126752     assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2
126753     assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3
126754     assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0
126755     assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1
126756     assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2
126757     assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3
126758     assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count
126759     assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done
126760     assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error
126761     assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout
126762     assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count
126763     assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done
126764     assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error
126765     assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout
126766     assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level
126767     assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce
126768     assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume
126769     assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first
126770     assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last
126771     assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data
126772     assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count
126773     assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux
126774     assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all
126775     assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage
126776     assign { } { }
126777     assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage
126778     assign { } { }
126779     assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage
126780     assign { } { }
126781     assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage
126782     assign { } { }
126783     assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset
126784     assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data
126785     assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage
126786     assign { } { }
126787     assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage
126788     assign { } { }
126789     assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage
126790     assign { } { }
126791     assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage
126792     assign { } { }
126793     assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset
126794     assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux
126795     assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level
126796     assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce
126797     assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume
126798     assign { } { }
126799     assign { } { }
126800     assign { } { }
126801     assign { } { }
126802     assign { } { }
126803     assign { } { }
126804     assign { } { }
126805     assign { } { }
126806     assign { } { }
126807     assign { } { }
126808     assign { } { }
126809     assign { } { }
126810     assign { } { }
126811     assign { } { }
126812     assign { } { }
126813     assign { } { }
126814     assign { } { }
126815     assign { } { }
126816     assign { } { }
126817     assign { } { }
126818     assign { } { }
126819     assign { } { }
126820     assign { } { }
126821     assign { } { }
126822     assign { } { }
126823     assign { } { }
126824     assign { } { }
126825     assign { } { }
126826     assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr
126827     assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we
126828     assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w
126829     assign $0\builder_grant[2:0] \builder_grant
126830     assign { } { }
126831     assign $0\builder_count[19:0] \builder_count
126832     assign { } { }
126833     assign { } { }
126834     assign { } { }
126835     assign { } { }
126836     assign { } { }
126837     assign { } { }
126838     assign { } { }
126839     assign { } { }
126840     assign { } { }
126841     assign { } { }
126842     assign { } { }
126843     assign { } { }
126844     assign { } { }
126845     assign { } { }
126846     assign { } { }
126847     assign { } { }
126848     assign { } { }
126849     assign { } { }
126850     assign { } { }
126851     assign { } { }
126852     assign { } { }
126853     assign { } { }
126854     assign { } { }
126855     assign { } { }
126856     assign { } { }
126857     assign { } { }
126858     assign { } { }
126859     assign { } { }
126860     assign { } { }
126861     assign { } { }
126862     assign { } { }
126863     assign { } { }
126864     assign { } { }
126865     assign { } { }
126866     assign { } { }
126867     assign { } { }
126868     assign { } { }
126869     assign { } { }
126870     assign { } { }
126871     assign { } { }
126872     assign { } { }
126873     assign { } { }
126874     assign { } { }
126875     assign { } { }
126876     assign { } { }
126877     assign { } { }
126878     assign { } { }
126879     assign { } { }
126880     assign { } { }
126881     assign { } { }
126882     assign $0\main_dummy[35:0] [0] $or$ls180.v:7432$2375_Y
126883     assign $0\main_dummy[35:0] [1] $or$ls180.v:7433$2376_Y
126884     assign $0\main_dummy[35:0] [2] $or$ls180.v:7434$2377_Y
126885     assign $0\main_dummy[35:0] [3] $or$ls180.v:7435$2378_Y
126886     assign $0\main_dummy[35:0] [4] $or$ls180.v:7436$2379_Y
126887     assign $0\main_dummy[35:0] [5] $or$ls180.v:7437$2380_Y
126888     assign $0\main_dummy[35:0] [6] $or$ls180.v:7438$2381_Y
126889     assign $0\main_dummy[35:0] [7] $or$ls180.v:7439$2382_Y
126890     assign $0\main_dummy[35:0] [8] $or$ls180.v:7440$2383_Y
126891     assign $0\main_dummy[35:0] [9] $or$ls180.v:7441$2384_Y
126892     assign $0\main_dummy[35:0] [10] $or$ls180.v:7442$2385_Y
126893     assign $0\main_dummy[35:0] [11] $or$ls180.v:7443$2386_Y
126894     assign $0\main_dummy[35:0] [12] $or$ls180.v:7444$2387_Y
126895     assign $0\main_dummy[35:0] [13] $or$ls180.v:7445$2388_Y
126896     assign $0\main_dummy[35:0] [14] $or$ls180.v:7446$2389_Y
126897     assign $0\main_dummy[35:0] [15] $or$ls180.v:7447$2390_Y
126898     assign $0\main_dummy[35:0] [16] $or$ls180.v:7448$2391_Y
126899     assign $0\main_dummy[35:0] [17] $or$ls180.v:7449$2392_Y
126900     assign $0\main_dummy[35:0] [18] $or$ls180.v:7450$2393_Y
126901     assign $0\main_dummy[35:0] [19] $or$ls180.v:7451$2394_Y
126902     assign $0\main_dummy[35:0] [20] $or$ls180.v:7452$2395_Y
126903     assign $0\main_dummy[35:0] [21] $or$ls180.v:7453$2396_Y
126904     assign $0\main_dummy[35:0] [22] $or$ls180.v:7454$2397_Y
126905     assign $0\main_dummy[35:0] [23] $or$ls180.v:7455$2398_Y
126906     assign $0\main_dummy[35:0] [24] $or$ls180.v:7456$2399_Y
126907     assign $0\main_dummy[35:0] [25] $or$ls180.v:7457$2400_Y
126908     assign $0\main_dummy[35:0] [26] $or$ls180.v:7458$2401_Y
126909     assign $0\main_dummy[35:0] [27] $or$ls180.v:7459$2402_Y
126910     assign $0\main_dummy[35:0] [28] $or$ls180.v:7460$2403_Y
126911     assign $0\main_dummy[35:0] [29] $or$ls180.v:7461$2404_Y
126912     assign $0\main_dummy[35:0] [30] $or$ls180.v:7462$2405_Y
126913     assign $0\main_dummy[35:0] [31] $or$ls180.v:7463$2406_Y
126914     assign $0\main_dummy[35:0] [32] $or$ls180.v:7464$2407_Y
126915     assign $0\main_dummy[35:0] [33] $or$ls180.v:7465$2408_Y
126916     assign $0\main_dummy[35:0] [34] $or$ls180.v:7466$2409_Y
126917     assign $0\main_dummy[35:0] [35] $or$ls180.v:7467$2410_Y
126918     assign $0\builder_converter0_state[0:0] \builder_converter0_next_state
126919     assign $0\builder_converter1_state[0:0] \builder_converter1_next_state
126920     assign $0\builder_converter2_state[0:0] \builder_converter2_next_state
126921     assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0
126922     assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger
126923     assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en }
126924     assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2]
126925     assign $0\main_sdram_postponer_req_o[0:0] 1'0
126926     assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
126927     assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
126928     assign $0\main_sdram_cmd_payload_cas[0:0] 1'0
126929     assign $0\main_sdram_cmd_payload_ras[0:0] 1'0
126930     assign $0\main_sdram_cmd_payload_we[0:0] 1'0
126931     assign $0\main_sdram_sequencer_done1[0:0] 1'0
126932     assign $0\builder_refresher_state[1:0] \builder_refresher_next_state
126933     assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state
126934     assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state
126935     assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state
126936     assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state
126937     assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0
126938     assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0
126939     assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1
126940     assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7909$2507_Y
126941     assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7910$2508_Y
126942     assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7911$2509_Y
126943     assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5
126944     assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6
126945     assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state
126946     assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7945$2527_Y
126947     assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7946$2539_Y
126948     assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0
126949     assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1
126950     assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2
126951     assign $0\builder_converter_state[0:0] \builder_converter_next_state
126952     assign $0\main_uart_phy_sink_ready[0:0] 1'0
126953     assign $0\main_uart_phy_source_valid[0:0] 1'0
126954     assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx
126955     assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger
126956     assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger
126957     assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8104$2585_Y
126958     assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8113$2588_Y
126959     assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state
126960     assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8139$2590_Y
126961     assign $0\spimaster_cs_n[0:0] $or$ls180.v:8148$2593_Y
126962     assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state
126963     assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1
126964     assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1
126965     assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state
126966     assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state
126967     assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state
126968     assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state
126969     assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state
126970     assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state
126971     assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state
126972     assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state
126973     assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state
126974     assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state
126975     assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state
126976     assign $0\builder_state[1:0] \builder_next_state
126977     assign $0\builder_slave_sel_r[4:0] \builder_slave_sel
126978     assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
126979     assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re
126980     assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re
126981     assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
126982     assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re
126983     assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re
126984     assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
126985     assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re
126986     assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
126987     assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re
126988     assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re
126989     assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re
126990     assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
126991     assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re
126992     assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re
126993     assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re
126994     assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
126995     assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re
126996     assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re
126997     assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re
126998     assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re
126999     assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
127000     assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re
127001     assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re
127002     assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re
127003     assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re
127004     assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
127005     assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re
127006     assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re
127007     assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re
127008     assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re
127009     assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
127010     assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re
127011     assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
127012     assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re
127013     assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re
127014     assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re
127015     assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re
127016     assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re
127017     assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
127018     assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re
127019     assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re
127020     assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re
127021     assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re
127022     assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
127023     assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re
127024     assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re
127025     assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re
127026     assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re
127027     assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re
127028     assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
127029     assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re
127030     assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re
127031     assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re
127032     assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re
127033     assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re
127034     assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
127035     assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re
127036     assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
127037     assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re
127038     assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx
127039     assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0
127040     assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0]
127041     assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0
127042     assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1]
127043     assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0
127044     assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2]
127045     assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0
127046     assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3]
127047     assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0
127048     assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4]
127049     assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0
127050     assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5]
127051     assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0
127052     assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6]
127053     assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0
127054     assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7]
127055     assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0
127056     assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8]
127057     assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0
127058     assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9]
127059     assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0
127060     assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10]
127061     assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0
127062     assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11]
127063     assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0
127064     assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12]
127065     assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0
127066     assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13]
127067     assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0
127068     assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14]
127069     assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0
127070     assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15]
127071     assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0
127072     attribute \src "ls180.v:7468.2-7470.5"
127073     switch $or$ls180.v:7468$2411_Y
127074       attribute \src "ls180.v:7468.6-7468.94"
127075       case 1'1
127076         assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r
127077       case
127078     end
127079     attribute \src "ls180.v:7472.2-7474.5"
127080     switch \main_libresocsim_converter0_counter_converter0_next_value_ce
127081       attribute \src "ls180.v:7472.6-7472.66"
127082       case 1'1
127083         assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value
127084       case
127085     end
127086     attribute \src "ls180.v:7475.2-7478.5"
127087     switch \main_libresocsim_converter0_reset
127088       attribute \src "ls180.v:7475.6-7475.39"
127089       case 1'1
127090         assign $0\main_libresocsim_converter0_counter[0:0] 1'0
127091         assign $0\builder_converter0_state[0:0] 1'0
127092       case
127093     end
127094     attribute \src "ls180.v:7479.2-7481.5"
127095     switch $or$ls180.v:7479$2412_Y
127096       attribute \src "ls180.v:7479.6-7479.94"
127097       case 1'1
127098         assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r
127099       case
127100     end
127101     attribute \src "ls180.v:7483.2-7485.5"
127102     switch \main_libresocsim_converter1_counter_converter1_next_value_ce
127103       attribute \src "ls180.v:7483.6-7483.66"
127104       case 1'1
127105         assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value
127106       case
127107     end
127108     attribute \src "ls180.v:7486.2-7489.5"
127109     switch \main_libresocsim_converter1_reset
127110       attribute \src "ls180.v:7486.6-7486.39"
127111       case 1'1
127112         assign $0\main_libresocsim_converter1_counter[0:0] 1'0
127113         assign $0\builder_converter1_state[0:0] 1'0
127114       case
127115     end
127116     attribute \src "ls180.v:7490.2-7492.5"
127117     switch $or$ls180.v:7490$2413_Y
127118       attribute \src "ls180.v:7490.6-7490.94"
127119       case 1'1
127120         assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r
127121       case
127122     end
127123     attribute \src "ls180.v:7494.2-7496.5"
127124     switch \main_libresocsim_converter2_counter_converter2_next_value_ce
127125       attribute \src "ls180.v:7494.6-7494.66"
127126       case 1'1
127127         assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value
127128       case
127129     end
127130     attribute \src "ls180.v:7497.2-7500.5"
127131     switch \main_libresocsim_converter2_reset
127132       attribute \src "ls180.v:7497.6-7497.39"
127133       case 1'1
127134         assign $0\main_libresocsim_converter2_counter[0:0] 1'0
127135         assign $0\builder_converter2_state[0:0] 1'0
127136       case
127137     end
127138     attribute \src "ls180.v:7501.2-7505.5"
127139     switch $ne$ls180.v:7501$2414_Y
127140       attribute \src "ls180.v:7501.6-7501.53"
127141       case 1'1
127142         attribute \src "ls180.v:7502.3-7504.6"
127143         switch \main_libresocsim_bus_error
127144           attribute \src "ls180.v:7502.7-7502.33"
127145           case 1'1
127146             assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7503$2415_Y
127147           case
127148         end
127149       case
127150     end
127151     attribute \src "ls180.v:7507.2-7509.5"
127152     switch $and$ls180.v:7507$2418_Y
127153       attribute \src "ls180.v:7507.6-7507.103"
127154       case 1'1
127155         assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1
127156       case
127157     end
127158     attribute \src "ls180.v:7510.2-7518.5"
127159     switch \main_libresocsim_en_storage
127160       attribute \src "ls180.v:7510.6-7510.33"
127161       case 1'1
127162         attribute \src "ls180.v:7511.3-7515.6"
127163         switch $eq$ls180.v:7511$2419_Y
127164           attribute \src "ls180.v:7511.7-7511.39"
127165           case 1'1
127166             assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage
127167           attribute \src "ls180.v:7513.7-7513.11"
127168           case
127169             assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7514$2420_Y
127170         end
127171       attribute \src "ls180.v:7516.6-7516.10"
127172       case
127173         assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage
127174     end
127175     attribute \src "ls180.v:7519.2-7521.5"
127176     switch \main_libresocsim_update_value_re
127177       attribute \src "ls180.v:7519.6-7519.38"
127178       case 1'1
127179         assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value
127180       case
127181     end
127182     attribute \src "ls180.v:7522.2-7524.5"
127183     switch \main_libresocsim_zero_clear
127184       attribute \src "ls180.v:7522.6-7522.33"
127185       case 1'1
127186         assign $0\main_libresocsim_zero_pending[0:0] 1'0
127187       case
127188     end
127189     attribute \src "ls180.v:7526.2-7528.5"
127190     switch $and$ls180.v:7526$2422_Y
127191       attribute \src "ls180.v:7526.6-7526.76"
127192       case 1'1
127193         assign $0\main_libresocsim_zero_pending[0:0] 1'1
127194       case
127195     end
127196     attribute \src "ls180.v:7531.2-7533.5"
127197     switch \main_sdram_inti_p0_rddata_valid
127198       attribute \src "ls180.v:7531.6-7531.37"
127199       case 1'1
127200         assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata
127201       case
127202     end
127203     attribute \src "ls180.v:7534.2-7538.5"
127204     switch $and$ls180.v:7534$2424_Y
127205       attribute \src "ls180.v:7534.6-7534.57"
127206       case 1'1
127207         assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7535$2425_Y
127208       attribute \src "ls180.v:7536.6-7536.10"
127209       case
127210         assign $0\main_sdram_timer_count1[9:0] 10'1100001101
127211     end
127212     attribute \src "ls180.v:7540.2-7546.5"
127213     switch \main_sdram_postponer_req_i
127214       attribute \src "ls180.v:7540.6-7540.32"
127215       case 1'1
127216         assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7541$2426_Y
127217         attribute \src "ls180.v:7542.3-7545.6"
127218         switch $eq$ls180.v:7542$2427_Y
127219           attribute \src "ls180.v:7542.7-7542.43"
127220           case 1'1
127221             assign $0\main_sdram_postponer_count[0:0] 1'0
127222             assign $0\main_sdram_postponer_req_o[0:0] 1'1
127223           case
127224         end
127225       case
127226     end
127227     attribute \src "ls180.v:7547.2-7555.5"
127228     switch \main_sdram_sequencer_start0
127229       attribute \src "ls180.v:7547.6-7547.33"
127230       case 1'1
127231         assign $0\main_sdram_sequencer_count[0:0] 1'0
127232       attribute \src "ls180.v:7549.6-7549.10"
127233       case
127234         attribute \src "ls180.v:7550.3-7554.6"
127235         switch \main_sdram_sequencer_done1
127236           attribute \src "ls180.v:7550.7-7550.33"
127237           case 1'1
127238             attribute \src "ls180.v:7551.4-7553.7"
127239             switch $ne$ls180.v:7551$2428_Y
127240               attribute \src "ls180.v:7551.8-7551.44"
127241               case 1'1
127242                 assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7552$2429_Y
127243               case
127244             end
127245           case
127246         end
127247     end
127248     attribute \src "ls180.v:7562.2-7568.5"
127249     switch $and$ls180.v:7562$2431_Y
127250       attribute \src "ls180.v:7562.6-7562.76"
127251       case 1'1
127252         assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000
127253         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
127254         assign $0\main_sdram_cmd_payload_cas[0:0] 1'0
127255         assign $0\main_sdram_cmd_payload_ras[0:0] 1'1
127256         assign $0\main_sdram_cmd_payload_we[0:0] 1'1
127257       case
127258     end
127259     attribute \src "ls180.v:7569.2-7575.5"
127260     switch $eq$ls180.v:7569$2432_Y
127261       attribute \src "ls180.v:7569.6-7569.44"
127262       case 1'1
127263         assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
127264         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
127265         assign $0\main_sdram_cmd_payload_cas[0:0] 1'1
127266         assign $0\main_sdram_cmd_payload_ras[0:0] 1'1
127267         assign $0\main_sdram_cmd_payload_we[0:0] 1'0
127268       case
127269     end
127270     attribute \src "ls180.v:7576.2-7583.5"
127271     switch $eq$ls180.v:7576$2433_Y
127272       attribute \src "ls180.v:7576.6-7576.44"
127273       case 1'1
127274         assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000
127275         assign $0\main_sdram_cmd_payload_ba[1:0] 2'00
127276         assign $0\main_sdram_cmd_payload_cas[0:0] 1'0
127277         assign $0\main_sdram_cmd_payload_ras[0:0] 1'0
127278         assign $0\main_sdram_cmd_payload_we[0:0] 1'0
127279         assign $0\main_sdram_sequencer_done1[0:0] 1'1
127280       case
127281     end
127282     attribute \src "ls180.v:7584.2-7594.5"
127283     switch $eq$ls180.v:7584$2434_Y
127284       attribute \src "ls180.v:7584.6-7584.44"
127285       case 1'1
127286         assign $0\main_sdram_sequencer_counter[3:0] 4'0000
127287       attribute \src "ls180.v:7586.6-7586.10"
127288       case
127289         attribute \src "ls180.v:7587.3-7593.6"
127290         switch $ne$ls180.v:7587$2435_Y
127291           attribute \src "ls180.v:7587.7-7587.45"
127292           case 1'1
127293             assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7588$2436_Y
127294           attribute \src "ls180.v:7589.7-7589.11"
127295           case
127296             attribute \src "ls180.v:7590.4-7592.7"
127297             switch \main_sdram_sequencer_start1
127298               attribute \src "ls180.v:7590.8-7590.35"
127299               case 1'1
127300                 assign $0\main_sdram_sequencer_counter[3:0] 4'0001
127301               case
127302             end
127303         end
127304     end
127305     attribute \src "ls180.v:7596.2-7603.5"
127306     switch \main_sdram_bankmachine0_row_close
127307       attribute \src "ls180.v:7596.6-7596.39"
127308       case 1'1
127309         assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0
127310       attribute \src "ls180.v:7598.6-7598.10"
127311       case
127312         attribute \src "ls180.v:7599.3-7602.6"
127313         switch \main_sdram_bankmachine0_row_open
127314           attribute \src "ls180.v:7599.7-7599.39"
127315           case 1'1
127316             assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1
127317             assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
127318           case
127319         end
127320     end
127321     attribute \src "ls180.v:7604.2-7606.5"
127322     switch $and$ls180.v:7604$2439_Y
127323       attribute \src "ls180.v:7604.6-7604.191"
127324       case 1'1
127325         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7605$2440_Y
127326       case
127327     end
127328     attribute \src "ls180.v:7607.2-7609.5"
127329     switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
127330       attribute \src "ls180.v:7607.6-7607.58"
127331       case 1'1
127332         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7608$2441_Y
127333       case
127334     end
127335     attribute \src "ls180.v:7610.2-7618.5"
127336     switch $and$ls180.v:7610$2444_Y
127337       attribute \src "ls180.v:7610.6-7610.191"
127338       case 1'1
127339         attribute \src "ls180.v:7611.3-7613.6"
127340         switch $not$ls180.v:7611$2445_Y
127341           attribute \src "ls180.v:7611.7-7611.62"
127342           case 1'1
127343             assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7612$2446_Y
127344           case
127345         end
127346       attribute \src "ls180.v:7614.6-7614.10"
127347       case
127348         attribute \src "ls180.v:7615.3-7617.6"
127349         switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read
127350           attribute \src "ls180.v:7615.7-7615.59"
127351           case 1'1
127352             assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7616$2447_Y
127353           case
127354         end
127355     end
127356     attribute \src "ls180.v:7619.2-7625.5"
127357     switch $or$ls180.v:7619$2449_Y
127358       attribute \src "ls180.v:7619.6-7619.108"
127359       case 1'1
127360         assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid
127361         assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first
127362         assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last
127363         assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we
127364         assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr
127365       case
127366     end
127367     attribute \src "ls180.v:7626.2-7640.5"
127368     switch \main_sdram_bankmachine0_twtpcon_valid
127369       attribute \src "ls180.v:7626.6-7626.43"
127370       case 1'1
127371         assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100
127372         attribute \src "ls180.v:7628.3-7632.6"
127373         switch 1'0
127374           attribute \src "ls180.v:7630.7-7630.11"
127375           case
127376             assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
127377         end
127378       attribute \src "ls180.v:7633.6-7633.10"
127379       case
127380         attribute \src "ls180.v:7634.3-7639.6"
127381         switch $not$ls180.v:7634$2450_Y
127382           attribute \src "ls180.v:7634.7-7634.47"
127383           case 1'1
127384             assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7635$2451_Y
127385             attribute \src "ls180.v:7636.4-7638.7"
127386             switch $eq$ls180.v:7636$2452_Y
127387               attribute \src "ls180.v:7636.8-7636.55"
127388               case 1'1
127389                 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1
127390               case
127391             end
127392           case
127393         end
127394     end
127395     attribute \src "ls180.v:7642.2-7649.5"
127396     switch \main_sdram_bankmachine1_row_close
127397       attribute \src "ls180.v:7642.6-7642.39"
127398       case 1'1
127399         assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0
127400       attribute \src "ls180.v:7644.6-7644.10"
127401       case
127402         attribute \src "ls180.v:7645.3-7648.6"
127403         switch \main_sdram_bankmachine1_row_open
127404           attribute \src "ls180.v:7645.7-7645.39"
127405           case 1'1
127406             assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1
127407             assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
127408           case
127409         end
127410     end
127411     attribute \src "ls180.v:7650.2-7652.5"
127412     switch $and$ls180.v:7650$2455_Y
127413       attribute \src "ls180.v:7650.6-7650.191"
127414       case 1'1
127415         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7651$2456_Y
127416       case
127417     end
127418     attribute \src "ls180.v:7653.2-7655.5"
127419     switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
127420       attribute \src "ls180.v:7653.6-7653.58"
127421       case 1'1
127422         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7654$2457_Y
127423       case
127424     end
127425     attribute \src "ls180.v:7656.2-7664.5"
127426     switch $and$ls180.v:7656$2460_Y
127427       attribute \src "ls180.v:7656.6-7656.191"
127428       case 1'1
127429         attribute \src "ls180.v:7657.3-7659.6"
127430         switch $not$ls180.v:7657$2461_Y
127431           attribute \src "ls180.v:7657.7-7657.62"
127432           case 1'1
127433             assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7658$2462_Y
127434           case
127435         end
127436       attribute \src "ls180.v:7660.6-7660.10"
127437       case
127438         attribute \src "ls180.v:7661.3-7663.6"
127439         switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read
127440           attribute \src "ls180.v:7661.7-7661.59"
127441           case 1'1
127442             assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7662$2463_Y
127443           case
127444         end
127445     end
127446     attribute \src "ls180.v:7665.2-7671.5"
127447     switch $or$ls180.v:7665$2465_Y
127448       attribute \src "ls180.v:7665.6-7665.108"
127449       case 1'1
127450         assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid
127451         assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first
127452         assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last
127453         assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we
127454         assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr
127455       case
127456     end
127457     attribute \src "ls180.v:7672.2-7686.5"
127458     switch \main_sdram_bankmachine1_twtpcon_valid
127459       attribute \src "ls180.v:7672.6-7672.43"
127460       case 1'1
127461         assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100
127462         attribute \src "ls180.v:7674.3-7678.6"
127463         switch 1'0
127464           attribute \src "ls180.v:7676.7-7676.11"
127465           case
127466             assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
127467         end
127468       attribute \src "ls180.v:7679.6-7679.10"
127469       case
127470         attribute \src "ls180.v:7680.3-7685.6"
127471         switch $not$ls180.v:7680$2466_Y
127472           attribute \src "ls180.v:7680.7-7680.47"
127473           case 1'1
127474             assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7681$2467_Y
127475             attribute \src "ls180.v:7682.4-7684.7"
127476             switch $eq$ls180.v:7682$2468_Y
127477               attribute \src "ls180.v:7682.8-7682.55"
127478               case 1'1
127479                 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1
127480               case
127481             end
127482           case
127483         end
127484     end
127485     attribute \src "ls180.v:7688.2-7695.5"
127486     switch \main_sdram_bankmachine2_row_close
127487       attribute \src "ls180.v:7688.6-7688.39"
127488       case 1'1
127489         assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0
127490       attribute \src "ls180.v:7690.6-7690.10"
127491       case
127492         attribute \src "ls180.v:7691.3-7694.6"
127493         switch \main_sdram_bankmachine2_row_open
127494           attribute \src "ls180.v:7691.7-7691.39"
127495           case 1'1
127496             assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1
127497             assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
127498           case
127499         end
127500     end
127501     attribute \src "ls180.v:7696.2-7698.5"
127502     switch $and$ls180.v:7696$2471_Y
127503       attribute \src "ls180.v:7696.6-7696.191"
127504       case 1'1
127505         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7697$2472_Y
127506       case
127507     end
127508     attribute \src "ls180.v:7699.2-7701.5"
127509     switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
127510       attribute \src "ls180.v:7699.6-7699.58"
127511       case 1'1
127512         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7700$2473_Y
127513       case
127514     end
127515     attribute \src "ls180.v:7702.2-7710.5"
127516     switch $and$ls180.v:7702$2476_Y
127517       attribute \src "ls180.v:7702.6-7702.191"
127518       case 1'1
127519         attribute \src "ls180.v:7703.3-7705.6"
127520         switch $not$ls180.v:7703$2477_Y
127521           attribute \src "ls180.v:7703.7-7703.62"
127522           case 1'1
127523             assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7704$2478_Y
127524           case
127525         end
127526       attribute \src "ls180.v:7706.6-7706.10"
127527       case
127528         attribute \src "ls180.v:7707.3-7709.6"
127529         switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read
127530           attribute \src "ls180.v:7707.7-7707.59"
127531           case 1'1
127532             assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7708$2479_Y
127533           case
127534         end
127535     end
127536     attribute \src "ls180.v:7711.2-7717.5"
127537     switch $or$ls180.v:7711$2481_Y
127538       attribute \src "ls180.v:7711.6-7711.108"
127539       case 1'1
127540         assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid
127541         assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first
127542         assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last
127543         assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we
127544         assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr
127545       case
127546     end
127547     attribute \src "ls180.v:7718.2-7732.5"
127548     switch \main_sdram_bankmachine2_twtpcon_valid
127549       attribute \src "ls180.v:7718.6-7718.43"
127550       case 1'1
127551         assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100
127552         attribute \src "ls180.v:7720.3-7724.6"
127553         switch 1'0
127554           attribute \src "ls180.v:7722.7-7722.11"
127555           case
127556             assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
127557         end
127558       attribute \src "ls180.v:7725.6-7725.10"
127559       case
127560         attribute \src "ls180.v:7726.3-7731.6"
127561         switch $not$ls180.v:7726$2482_Y
127562           attribute \src "ls180.v:7726.7-7726.47"
127563           case 1'1
127564             assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7727$2483_Y
127565             attribute \src "ls180.v:7728.4-7730.7"
127566             switch $eq$ls180.v:7728$2484_Y
127567               attribute \src "ls180.v:7728.8-7728.55"
127568               case 1'1
127569                 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1
127570               case
127571             end
127572           case
127573         end
127574     end
127575     attribute \src "ls180.v:7734.2-7741.5"
127576     switch \main_sdram_bankmachine3_row_close
127577       attribute \src "ls180.v:7734.6-7734.39"
127578       case 1'1
127579         assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0
127580       attribute \src "ls180.v:7736.6-7736.10"
127581       case
127582         attribute \src "ls180.v:7737.3-7740.6"
127583         switch \main_sdram_bankmachine3_row_open
127584           attribute \src "ls180.v:7737.7-7737.39"
127585           case 1'1
127586             assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1
127587             assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
127588           case
127589         end
127590     end
127591     attribute \src "ls180.v:7742.2-7744.5"
127592     switch $and$ls180.v:7742$2487_Y
127593       attribute \src "ls180.v:7742.6-7742.191"
127594       case 1'1
127595         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7743$2488_Y
127596       case
127597     end
127598     attribute \src "ls180.v:7745.2-7747.5"
127599     switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
127600       attribute \src "ls180.v:7745.6-7745.58"
127601       case 1'1
127602         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7746$2489_Y
127603       case
127604     end
127605     attribute \src "ls180.v:7748.2-7756.5"
127606     switch $and$ls180.v:7748$2492_Y
127607       attribute \src "ls180.v:7748.6-7748.191"
127608       case 1'1
127609         attribute \src "ls180.v:7749.3-7751.6"
127610         switch $not$ls180.v:7749$2493_Y
127611           attribute \src "ls180.v:7749.7-7749.62"
127612           case 1'1
127613             assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7750$2494_Y
127614           case
127615         end
127616       attribute \src "ls180.v:7752.6-7752.10"
127617       case
127618         attribute \src "ls180.v:7753.3-7755.6"
127619         switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read
127620           attribute \src "ls180.v:7753.7-7753.59"
127621           case 1'1
127622             assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7754$2495_Y
127623           case
127624         end
127625     end
127626     attribute \src "ls180.v:7757.2-7763.5"
127627     switch $or$ls180.v:7757$2497_Y
127628       attribute \src "ls180.v:7757.6-7757.108"
127629       case 1'1
127630         assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid
127631         assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first
127632         assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last
127633         assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we
127634         assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr
127635       case
127636     end
127637     attribute \src "ls180.v:7764.2-7778.5"
127638     switch \main_sdram_bankmachine3_twtpcon_valid
127639       attribute \src "ls180.v:7764.6-7764.43"
127640       case 1'1
127641         assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100
127642         attribute \src "ls180.v:7766.3-7770.6"
127643         switch 1'0
127644           attribute \src "ls180.v:7768.7-7768.11"
127645           case
127646             assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
127647         end
127648       attribute \src "ls180.v:7771.6-7771.10"
127649       case
127650         attribute \src "ls180.v:7772.3-7777.6"
127651         switch $not$ls180.v:7772$2498_Y
127652           attribute \src "ls180.v:7772.7-7772.47"
127653           case 1'1
127654             assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7773$2499_Y
127655             attribute \src "ls180.v:7774.4-7776.7"
127656             switch $eq$ls180.v:7774$2500_Y
127657               attribute \src "ls180.v:7774.8-7774.55"
127658               case 1'1
127659                 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1
127660               case
127661             end
127662           case
127663         end
127664     end
127665     attribute \src "ls180.v:7780.2-7786.5"
127666     switch $not$ls180.v:7780$2501_Y
127667       attribute \src "ls180.v:7780.6-7780.23"
127668       case 1'1
127669         assign $0\main_sdram_time0[4:0] 5'11111
127670       attribute \src "ls180.v:7782.6-7782.10"
127671       case
127672         attribute \src "ls180.v:7783.3-7785.6"
127673         switch $not$ls180.v:7783$2502_Y
127674           attribute \src "ls180.v:7783.7-7783.30"
127675           case 1'1
127676             assign $0\main_sdram_time0[4:0] $sub$ls180.v:7784$2503_Y
127677           case
127678         end
127679     end
127680     attribute \src "ls180.v:7787.2-7793.5"
127681     switch $not$ls180.v:7787$2504_Y
127682       attribute \src "ls180.v:7787.6-7787.23"
127683       case 1'1
127684         assign $0\main_sdram_time1[3:0] 4'1111
127685       attribute \src "ls180.v:7789.6-7789.10"
127686       case
127687         attribute \src "ls180.v:7790.3-7792.6"
127688         switch $not$ls180.v:7790$2505_Y
127689           attribute \src "ls180.v:7790.7-7790.30"
127690           case 1'1
127691             assign $0\main_sdram_time1[3:0] $sub$ls180.v:7791$2506_Y
127692           case
127693         end
127694     end
127695     attribute \src "ls180.v:7794.2-7849.5"
127696     switch \main_sdram_choose_cmd_ce
127697       attribute \src "ls180.v:7794.6-7794.30"
127698       case 1'1
127699         attribute \src "ls180.v:7795.3-7848.10"
127700         switch \main_sdram_choose_cmd_grant
127701           attribute \src "ls180.v:0.0-0.0"
127702           case 2'00
127703             attribute \src "ls180.v:7797.5-7807.8"
127704             switch \main_sdram_choose_cmd_request [1]
127705               attribute \src "ls180.v:7797.9-7797.41"
127706               case 1'1
127707                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
127708               attribute \src "ls180.v:7799.9-7799.13"
127709               case
127710                 attribute \src "ls180.v:7800.6-7806.9"
127711                 switch \main_sdram_choose_cmd_request [2]
127712                   attribute \src "ls180.v:7800.10-7800.42"
127713                   case 1'1
127714                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
127715                   attribute \src "ls180.v:7802.10-7802.14"
127716                   case
127717                     attribute \src "ls180.v:7803.7-7805.10"
127718                     switch \main_sdram_choose_cmd_request [3]
127719                       attribute \src "ls180.v:7803.11-7803.43"
127720                       case 1'1
127721                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
127722                       case
127723                     end
127724                 end
127725             end
127726           attribute \src "ls180.v:0.0-0.0"
127727           case 2'01
127728             attribute \src "ls180.v:7810.5-7820.8"
127729             switch \main_sdram_choose_cmd_request [2]
127730               attribute \src "ls180.v:7810.9-7810.41"
127731               case 1'1
127732                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
127733               attribute \src "ls180.v:7812.9-7812.13"
127734               case
127735                 attribute \src "ls180.v:7813.6-7819.9"
127736                 switch \main_sdram_choose_cmd_request [3]
127737                   attribute \src "ls180.v:7813.10-7813.42"
127738                   case 1'1
127739                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
127740                   attribute \src "ls180.v:7815.10-7815.14"
127741                   case
127742                     attribute \src "ls180.v:7816.7-7818.10"
127743                     switch \main_sdram_choose_cmd_request [0]
127744                       attribute \src "ls180.v:7816.11-7816.43"
127745                       case 1'1
127746                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
127747                       case
127748                     end
127749                 end
127750             end
127751           attribute \src "ls180.v:0.0-0.0"
127752           case 2'10
127753             attribute \src "ls180.v:7823.5-7833.8"
127754             switch \main_sdram_choose_cmd_request [3]
127755               attribute \src "ls180.v:7823.9-7823.41"
127756               case 1'1
127757                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11
127758               attribute \src "ls180.v:7825.9-7825.13"
127759               case
127760                 attribute \src "ls180.v:7826.6-7832.9"
127761                 switch \main_sdram_choose_cmd_request [0]
127762                   attribute \src "ls180.v:7826.10-7826.42"
127763                   case 1'1
127764                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
127765                   attribute \src "ls180.v:7828.10-7828.14"
127766                   case
127767                     attribute \src "ls180.v:7829.7-7831.10"
127768                     switch \main_sdram_choose_cmd_request [1]
127769                       attribute \src "ls180.v:7829.11-7829.43"
127770                       case 1'1
127771                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
127772                       case
127773                     end
127774                 end
127775             end
127776           attribute \src "ls180.v:0.0-0.0"
127777           case 2'11
127778             attribute \src "ls180.v:7836.5-7846.8"
127779             switch \main_sdram_choose_cmd_request [0]
127780               attribute \src "ls180.v:7836.9-7836.41"
127781               case 1'1
127782                 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
127783               attribute \src "ls180.v:7838.9-7838.13"
127784               case
127785                 attribute \src "ls180.v:7839.6-7845.9"
127786                 switch \main_sdram_choose_cmd_request [1]
127787                   attribute \src "ls180.v:7839.10-7839.42"
127788                   case 1'1
127789                     assign $0\main_sdram_choose_cmd_grant[1:0] 2'01
127790                   attribute \src "ls180.v:7841.10-7841.14"
127791                   case
127792                     attribute \src "ls180.v:7842.7-7844.10"
127793                     switch \main_sdram_choose_cmd_request [2]
127794                       attribute \src "ls180.v:7842.11-7842.43"
127795                       case 1'1
127796                         assign $0\main_sdram_choose_cmd_grant[1:0] 2'10
127797                       case
127798                     end
127799                 end
127800             end
127801           case
127802         end
127803       case
127804     end
127805     attribute \src "ls180.v:7850.2-7905.5"
127806     switch \main_sdram_choose_req_ce
127807       attribute \src "ls180.v:7850.6-7850.30"
127808       case 1'1
127809         attribute \src "ls180.v:7851.3-7904.10"
127810         switch \main_sdram_choose_req_grant
127811           attribute \src "ls180.v:0.0-0.0"
127812           case 2'00
127813             attribute \src "ls180.v:7853.5-7863.8"
127814             switch \main_sdram_choose_req_request [1]
127815               attribute \src "ls180.v:7853.9-7853.41"
127816               case 1'1
127817                 assign $0\main_sdram_choose_req_grant[1:0] 2'01
127818               attribute \src "ls180.v:7855.9-7855.13"
127819               case
127820                 attribute \src "ls180.v:7856.6-7862.9"
127821                 switch \main_sdram_choose_req_request [2]
127822                   attribute \src "ls180.v:7856.10-7856.42"
127823                   case 1'1
127824                     assign $0\main_sdram_choose_req_grant[1:0] 2'10
127825                   attribute \src "ls180.v:7858.10-7858.14"
127826                   case
127827                     attribute \src "ls180.v:7859.7-7861.10"
127828                     switch \main_sdram_choose_req_request [3]
127829                       attribute \src "ls180.v:7859.11-7859.43"
127830                       case 1'1
127831                         assign $0\main_sdram_choose_req_grant[1:0] 2'11
127832                       case
127833                     end
127834                 end
127835             end
127836           attribute \src "ls180.v:0.0-0.0"
127837           case 2'01
127838             attribute \src "ls180.v:7866.5-7876.8"
127839             switch \main_sdram_choose_req_request [2]
127840               attribute \src "ls180.v:7866.9-7866.41"
127841               case 1'1
127842                 assign $0\main_sdram_choose_req_grant[1:0] 2'10
127843               attribute \src "ls180.v:7868.9-7868.13"
127844               case
127845                 attribute \src "ls180.v:7869.6-7875.9"
127846                 switch \main_sdram_choose_req_request [3]
127847                   attribute \src "ls180.v:7869.10-7869.42"
127848                   case 1'1
127849                     assign $0\main_sdram_choose_req_grant[1:0] 2'11
127850                   attribute \src "ls180.v:7871.10-7871.14"
127851                   case
127852                     attribute \src "ls180.v:7872.7-7874.10"
127853                     switch \main_sdram_choose_req_request [0]
127854                       attribute \src "ls180.v:7872.11-7872.43"
127855                       case 1'1
127856                         assign $0\main_sdram_choose_req_grant[1:0] 2'00
127857                       case
127858                     end
127859                 end
127860             end
127861           attribute \src "ls180.v:0.0-0.0"
127862           case 2'10
127863             attribute \src "ls180.v:7879.5-7889.8"
127864             switch \main_sdram_choose_req_request [3]
127865               attribute \src "ls180.v:7879.9-7879.41"
127866               case 1'1
127867                 assign $0\main_sdram_choose_req_grant[1:0] 2'11
127868               attribute \src "ls180.v:7881.9-7881.13"
127869               case
127870                 attribute \src "ls180.v:7882.6-7888.9"
127871                 switch \main_sdram_choose_req_request [0]
127872                   attribute \src "ls180.v:7882.10-7882.42"
127873                   case 1'1
127874                     assign $0\main_sdram_choose_req_grant[1:0] 2'00
127875                   attribute \src "ls180.v:7884.10-7884.14"
127876                   case
127877                     attribute \src "ls180.v:7885.7-7887.10"
127878                     switch \main_sdram_choose_req_request [1]
127879                       attribute \src "ls180.v:7885.11-7885.43"
127880                       case 1'1
127881                         assign $0\main_sdram_choose_req_grant[1:0] 2'01
127882                       case
127883                     end
127884                 end
127885             end
127886           attribute \src "ls180.v:0.0-0.0"
127887           case 2'11
127888             attribute \src "ls180.v:7892.5-7902.8"
127889             switch \main_sdram_choose_req_request [0]
127890               attribute \src "ls180.v:7892.9-7892.41"
127891               case 1'1
127892                 assign $0\main_sdram_choose_req_grant[1:0] 2'00
127893               attribute \src "ls180.v:7894.9-7894.13"
127894               case
127895                 attribute \src "ls180.v:7895.6-7901.9"
127896                 switch \main_sdram_choose_req_request [1]
127897                   attribute \src "ls180.v:7895.10-7895.42"
127898                   case 1'1
127899                     assign $0\main_sdram_choose_req_grant[1:0] 2'01
127900                   attribute \src "ls180.v:7897.10-7897.14"
127901                   case
127902                     attribute \src "ls180.v:7898.7-7900.10"
127903                     switch \main_sdram_choose_req_request [2]
127904                       attribute \src "ls180.v:7898.11-7898.43"
127905                       case 1'1
127906                         assign $0\main_sdram_choose_req_grant[1:0] 2'10
127907                       case
127908                     end
127909                 end
127910             end
127911           case
127912         end
127913       case
127914     end
127915     attribute \src "ls180.v:7914.2-7928.5"
127916     switch \main_sdram_tccdcon_valid
127917       attribute \src "ls180.v:7914.6-7914.30"
127918       case 1'1
127919         assign $0\main_sdram_tccdcon_count[0:0] 1'0
127920         attribute \src "ls180.v:7916.3-7920.6"
127921         switch 1'1
127922           attribute \src "ls180.v:7916.7-7916.11"
127923           case 1'1
127924             assign $0\main_sdram_tccdcon_ready[0:0] 1'1
127925           case
127926         end
127927       attribute \src "ls180.v:7921.6-7921.10"
127928       case
127929         attribute \src "ls180.v:7922.3-7927.6"
127930         switch $not$ls180.v:7922$2510_Y
127931           attribute \src "ls180.v:7922.7-7922.34"
127932           case 1'1
127933             assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7923$2511_Y
127934             attribute \src "ls180.v:7924.4-7926.7"
127935             switch $eq$ls180.v:7924$2512_Y
127936               attribute \src "ls180.v:7924.8-7924.42"
127937               case 1'1
127938                 assign $0\main_sdram_tccdcon_ready[0:0] 1'1
127939               case
127940             end
127941           case
127942         end
127943     end
127944     attribute \src "ls180.v:7929.2-7943.5"
127945     switch \main_sdram_twtrcon_valid
127946       attribute \src "ls180.v:7929.6-7929.30"
127947       case 1'1
127948         assign $0\main_sdram_twtrcon_count[2:0] 3'100
127949         attribute \src "ls180.v:7931.3-7935.6"
127950         switch 1'0
127951           attribute \src "ls180.v:7933.7-7933.11"
127952           case
127953             assign $0\main_sdram_twtrcon_ready[0:0] 1'0
127954         end
127955       attribute \src "ls180.v:7936.6-7936.10"
127956       case
127957         attribute \src "ls180.v:7937.3-7942.6"
127958         switch $not$ls180.v:7937$2513_Y
127959           attribute \src "ls180.v:7937.7-7937.34"
127960           case 1'1
127961             assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7938$2514_Y
127962             attribute \src "ls180.v:7939.4-7941.7"
127963             switch $eq$ls180.v:7939$2515_Y
127964               attribute \src "ls180.v:7939.8-7939.42"
127965               case 1'1
127966                 assign $0\main_sdram_twtrcon_ready[0:0] 1'1
127967               case
127968             end
127969           case
127970         end
127971     end
127972     attribute \src "ls180.v:7950.2-7952.5"
127973     switch $or$ls180.v:7950$2540_Y
127974       attribute \src "ls180.v:7950.6-7950.50"
127975       case 1'1
127976         assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r
127977       case
127978     end
127979     attribute \src "ls180.v:7954.2-7956.5"
127980     switch \main_converter_counter_converter_next_value_ce
127981       attribute \src "ls180.v:7954.6-7954.52"
127982       case 1'1
127983         assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value
127984       case
127985     end
127986     attribute \src "ls180.v:7957.2-7960.5"
127987     switch \main_converter_reset
127988       attribute \src "ls180.v:7957.6-7957.26"
127989       case 1'1
127990         assign $0\main_converter_counter[0:0] 1'0
127991         assign $0\builder_converter_state[0:0] 1'0
127992       case
127993     end
127994     attribute \src "ls180.v:7961.2-7971.5"
127995     switch \main_litedram_wb_ack
127996       attribute \src "ls180.v:7961.6-7961.26"
127997       case 1'1
127998         assign $0\main_cmd_consumed[0:0] 1'0
127999         assign $0\main_wdata_consumed[0:0] 1'0
128000       attribute \src "ls180.v:7964.6-7964.10"
128001       case
128002         attribute \src "ls180.v:7965.3-7967.6"
128003         switch $and$ls180.v:7965$2541_Y
128004           attribute \src "ls180.v:7965.7-7965.50"
128005           case 1'1
128006             assign $0\main_cmd_consumed[0:0] 1'1
128007           case
128008         end
128009         attribute \src "ls180.v:7968.3-7970.6"
128010         switch $and$ls180.v:7968$2542_Y
128011           attribute \src "ls180.v:7968.7-7968.54"
128012           case 1'1
128013             assign $0\main_wdata_consumed[0:0] 1'1
128014           case
128015         end
128016     end
128017     attribute \src "ls180.v:7973.2-7994.5"
128018     switch $and$ls180.v:7973$2546_Y
128019       attribute \src "ls180.v:7973.6-7973.91"
128020       case 1'1
128021         assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data
128022         assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000
128023         assign $0\main_uart_phy_tx_busy[0:0] 1'1
128024         assign $0\uart_tx[0:0] 1'0
128025       attribute \src "ls180.v:7978.6-7978.10"
128026       case
128027         attribute \src "ls180.v:7979.3-7993.6"
128028         switch $and$ls180.v:7979$2547_Y
128029           attribute \src "ls180.v:7979.7-7979.60"
128030           case 1'1
128031             assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7980$2548_Y
128032             attribute \src "ls180.v:7981.4-7992.7"
128033             switch $eq$ls180.v:7981$2549_Y
128034               attribute \src "ls180.v:7981.8-7981.43"
128035               case 1'1
128036                 assign $0\uart_tx[0:0] 1'1
128037               attribute \src "ls180.v:7983.8-7983.12"
128038               case
128039                 attribute \src "ls180.v:7984.5-7991.8"
128040                 switch $eq$ls180.v:7984$2550_Y
128041                   attribute \src "ls180.v:7984.9-7984.44"
128042                   case 1'1
128043                     assign $0\uart_tx[0:0] 1'1
128044                     assign $0\main_uart_phy_tx_busy[0:0] 1'0
128045                     assign $0\main_uart_phy_sink_ready[0:0] 1'1
128046                   attribute \src "ls180.v:7988.9-7988.13"
128047                   case
128048                     assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0]
128049                     assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] }
128050                 end
128051             end
128052           case
128053         end
128054     end
128055     attribute \src "ls180.v:7995.2-7999.5"
128056     switch \main_uart_phy_tx_busy
128057       attribute \src "ls180.v:7995.6-7995.27"
128058       case 1'1
128059         assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7996$2551_Y
128060       attribute \src "ls180.v:7997.6-7997.10"
128061       case
128062         assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage }
128063     end
128064     attribute \src "ls180.v:8002.2-8026.5"
128065     switch $not$ls180.v:8002$2552_Y
128066       attribute \src "ls180.v:8002.6-8002.30"
128067       case 1'1
128068         attribute \src "ls180.v:8003.3-8006.6"
128069         switch $and$ls180.v:8003$2554_Y
128070           attribute \src "ls180.v:8003.7-8003.49"
128071           case 1'1
128072             assign $0\main_uart_phy_rx_busy[0:0] 1'1
128073             assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000
128074           case
128075         end
128076       attribute \src "ls180.v:8007.6-8007.10"
128077       case
128078         attribute \src "ls180.v:8008.3-8025.6"
128079         switch \main_uart_phy_uart_clk_rxen
128080           attribute \src "ls180.v:8008.7-8008.34"
128081           case 1'1
128082             assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8009$2555_Y
128083             attribute \src "ls180.v:8010.4-8024.7"
128084             switch $eq$ls180.v:8010$2556_Y
128085               attribute \src "ls180.v:8010.8-8010.43"
128086               case 1'1
128087                 attribute \src "ls180.v:8011.5-8013.8"
128088                 switch \main_uart_phy_rx
128089                   attribute \src "ls180.v:8011.9-8011.25"
128090                   case 1'1
128091                     assign $0\main_uart_phy_rx_busy[0:0] 1'0
128092                   case
128093                 end
128094               attribute \src "ls180.v:8014.8-8014.12"
128095               case
128096                 attribute \src "ls180.v:8015.5-8023.8"
128097                 switch $eq$ls180.v:8015$2557_Y
128098                   attribute \src "ls180.v:8015.9-8015.44"
128099                   case 1'1
128100                     assign $0\main_uart_phy_rx_busy[0:0] 1'0
128101                     attribute \src "ls180.v:8017.6-8020.9"
128102                     switch \main_uart_phy_rx
128103                       attribute \src "ls180.v:8017.10-8017.26"
128104                       case 1'1
128105                         assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg
128106                         assign $0\main_uart_phy_source_valid[0:0] 1'1
128107                       case
128108                     end
128109                   attribute \src "ls180.v:8021.9-8021.13"
128110                   case
128111                     assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] }
128112                 end
128113             end
128114           case
128115         end
128116     end
128117     attribute \src "ls180.v:8027.2-8031.5"
128118     switch \main_uart_phy_rx_busy
128119       attribute \src "ls180.v:8027.6-8027.27"
128120       case 1'1
128121         assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8028$2558_Y
128122       attribute \src "ls180.v:8029.6-8029.10"
128123       case
128124         assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
128125     end
128126     attribute \src "ls180.v:8032.2-8034.5"
128127     switch \main_uart_tx_clear
128128       attribute \src "ls180.v:8032.6-8032.24"
128129       case 1'1
128130         assign $0\main_uart_tx_pending[0:0] 1'0
128131       case
128132     end
128133     attribute \src "ls180.v:8036.2-8038.5"
128134     switch $and$ls180.v:8036$2560_Y
128135       attribute \src "ls180.v:8036.6-8036.58"
128136       case 1'1
128137         assign $0\main_uart_tx_pending[0:0] 1'1
128138       case
128139     end
128140     attribute \src "ls180.v:8039.2-8041.5"
128141     switch \main_uart_rx_clear
128142       attribute \src "ls180.v:8039.6-8039.24"
128143       case 1'1
128144         assign $0\main_uart_rx_pending[0:0] 1'0
128145       case
128146     end
128147     attribute \src "ls180.v:8043.2-8045.5"
128148     switch $and$ls180.v:8043$2562_Y
128149       attribute \src "ls180.v:8043.6-8043.58"
128150       case 1'1
128151         assign $0\main_uart_rx_pending[0:0] 1'1
128152       case
128153     end
128154     attribute \src "ls180.v:8046.2-8052.5"
128155     switch \main_uart_tx_fifo_syncfifo_re
128156       attribute \src "ls180.v:8046.6-8046.35"
128157       case 1'1
128158         assign $0\main_uart_tx_fifo_readable[0:0] 1'1
128159       attribute \src "ls180.v:8048.6-8048.10"
128160       case
128161         attribute \src "ls180.v:8049.3-8051.6"
128162         switch \main_uart_tx_fifo_re
128163           attribute \src "ls180.v:8049.7-8049.27"
128164           case 1'1
128165             assign $0\main_uart_tx_fifo_readable[0:0] 1'0
128166           case
128167         end
128168     end
128169     attribute \src "ls180.v:8053.2-8055.5"
128170     switch $and$ls180.v:8053$2565_Y
128171       attribute \src "ls180.v:8053.6-8053.108"
128172       case 1'1
128173         assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8054$2566_Y
128174       case
128175     end
128176     attribute \src "ls180.v:8056.2-8058.5"
128177     switch \main_uart_tx_fifo_do_read
128178       attribute \src "ls180.v:8056.6-8056.31"
128179       case 1'1
128180         assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8057$2567_Y
128181       case
128182     end
128183     attribute \src "ls180.v:8059.2-8067.5"
128184     switch $and$ls180.v:8059$2570_Y
128185       attribute \src "ls180.v:8059.6-8059.108"
128186       case 1'1
128187         attribute \src "ls180.v:8060.3-8062.6"
128188         switch $not$ls180.v:8060$2571_Y
128189           attribute \src "ls180.v:8060.7-8060.35"
128190           case 1'1
128191             assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8061$2572_Y
128192           case
128193         end
128194       attribute \src "ls180.v:8063.6-8063.10"
128195       case
128196         attribute \src "ls180.v:8064.3-8066.6"
128197         switch \main_uart_tx_fifo_do_read
128198           attribute \src "ls180.v:8064.7-8064.32"
128199           case 1'1
128200             assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8065$2573_Y
128201           case
128202         end
128203     end
128204     attribute \src "ls180.v:8068.2-8074.5"
128205     switch \main_uart_rx_fifo_syncfifo_re
128206       attribute \src "ls180.v:8068.6-8068.35"
128207       case 1'1
128208         assign $0\main_uart_rx_fifo_readable[0:0] 1'1
128209       attribute \src "ls180.v:8070.6-8070.10"
128210       case
128211         attribute \src "ls180.v:8071.3-8073.6"
128212         switch \main_uart_rx_fifo_re
128213           attribute \src "ls180.v:8071.7-8071.27"
128214           case 1'1
128215             assign $0\main_uart_rx_fifo_readable[0:0] 1'0
128216           case
128217         end
128218     end
128219     attribute \src "ls180.v:8075.2-8077.5"
128220     switch $and$ls180.v:8075$2576_Y
128221       attribute \src "ls180.v:8075.6-8075.108"
128222       case 1'1
128223         assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8076$2577_Y
128224       case
128225     end
128226     attribute \src "ls180.v:8078.2-8080.5"
128227     switch \main_uart_rx_fifo_do_read
128228       attribute \src "ls180.v:8078.6-8078.31"
128229       case 1'1
128230         assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8079$2578_Y
128231       case
128232     end
128233     attribute \src "ls180.v:8081.2-8089.5"
128234     switch $and$ls180.v:8081$2581_Y
128235       attribute \src "ls180.v:8081.6-8081.108"
128236       case 1'1
128237         attribute \src "ls180.v:8082.3-8084.6"
128238         switch $not$ls180.v:8082$2582_Y
128239           attribute \src "ls180.v:8082.7-8082.35"
128240           case 1'1
128241             assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8083$2583_Y
128242           case
128243         end
128244       attribute \src "ls180.v:8085.6-8085.10"
128245       case
128246         attribute \src "ls180.v:8086.3-8088.6"
128247         switch \main_uart_rx_fifo_do_read
128248           attribute \src "ls180.v:8086.7-8086.32"
128249           case 1'1
128250             assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8087$2584_Y
128251           case
128252         end
128253     end
128254     attribute \src "ls180.v:8090.2-8103.5"
128255     switch \main_uart_reset
128256       attribute \src "ls180.v:8090.6-8090.21"
128257       case 1'1
128258         assign $0\main_uart_tx_pending[0:0] 1'0
128259         assign $0\main_uart_tx_old_trigger[0:0] 1'0
128260         assign $0\main_uart_rx_pending[0:0] 1'0
128261         assign $0\main_uart_rx_old_trigger[0:0] 1'0
128262         assign $0\main_uart_tx_fifo_readable[0:0] 1'0
128263         assign $0\main_uart_tx_fifo_level0[4:0] 5'00000
128264         assign $0\main_uart_tx_fifo_produce[3:0] 4'0000
128265         assign $0\main_uart_tx_fifo_consume[3:0] 4'0000
128266         assign $0\main_uart_rx_fifo_readable[0:0] 1'0
128267         assign $0\main_uart_rx_fifo_level0[4:0] 5'00000
128268         assign $0\main_uart_rx_fifo_produce[3:0] 4'0000
128269         assign $0\main_uart_rx_fifo_consume[3:0] 4'0000
128270       case
128271     end
128272     attribute \src "ls180.v:8105.2-8112.5"
128273     switch \main_spimaster31_clk_rise
128274       attribute \src "ls180.v:8105.6-8105.31"
128275       case 1'1
128276         assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable
128277       attribute \src "ls180.v:8107.6-8107.10"
128278       case
128279         attribute \src "ls180.v:8108.3-8111.6"
128280         switch \main_spimaster32_clk_fall
128281           attribute \src "ls180.v:8108.7-8108.32"
128282           case 1'1
128283             assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000
128284             assign $0\spisdcard_clk[0:0] 1'0
128285           case
128286         end
128287     end
128288     attribute \src "ls180.v:8114.2-8124.5"
128289     switch \main_spimaster28_mosi_latch
128290       attribute \src "ls180.v:8114.6-8114.33"
128291       case 1'1
128292         assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi
128293         assign $0\main_spimaster34_mosi_sel[2:0] 3'111
128294       attribute \src "ls180.v:8117.6-8117.10"
128295       case
128296         attribute \src "ls180.v:8118.3-8123.6"
128297         switch \main_spimaster32_clk_fall
128298           attribute \src "ls180.v:8118.7-8118.32"
128299           case 1'1
128300             assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8122$2589_Y
128301             attribute \src "ls180.v:8119.4-8121.7"
128302             switch \main_spimaster26_cs_enable
128303               attribute \src "ls180.v:8119.8-8119.34"
128304               case 1'1
128305                 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0
128306               case
128307             end
128308           case
128309         end
128310     end
128311     attribute \src "ls180.v:8125.2-8131.5"
128312     switch \main_spimaster31_clk_rise
128313       attribute \src "ls180.v:8125.6-8125.31"
128314       case 1'1
128315         attribute \src "ls180.v:8126.3-8130.6"
128316         switch \main_spimaster7_loopback
128317           attribute \src "ls180.v:8126.7-8126.31"
128318           case 1'1
128319             assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi }
128320           attribute \src "ls180.v:8128.7-8128.11"
128321           case
128322             assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso }
128323         end
128324       case
128325     end
128326     attribute \src "ls180.v:8132.2-8134.5"
128327     switch \main_spimaster29_miso_latch
128328       attribute \src "ls180.v:8132.6-8132.33"
128329       case 1'1
128330         assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data
128331       case
128332     end
128333     attribute \src "ls180.v:8136.2-8138.5"
128334     switch \main_spimaster27_count_spimaster0_next_value_ce
128335       attribute \src "ls180.v:8136.6-8136.53"
128336       case 1'1
128337         assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value
128338       case
128339     end
128340     attribute \src "ls180.v:8140.2-8147.5"
128341     switch \main_spisdcard_clk_rise
128342       attribute \src "ls180.v:8140.6-8140.29"
128343       case 1'1
128344         assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable
128345       attribute \src "ls180.v:8142.6-8142.10"
128346       case
128347         attribute \src "ls180.v:8143.3-8146.6"
128348         switch \main_spisdcard_clk_fall
128349           attribute \src "ls180.v:8143.7-8143.30"
128350           case 1'1
128351             assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
128352             assign $0\spimaster_clk[0:0] 1'0
128353           case
128354         end
128355     end
128356     attribute \src "ls180.v:8149.2-8159.5"
128357     switch \main_spisdcard_mosi_latch
128358       attribute \src "ls180.v:8149.6-8149.31"
128359       case 1'1
128360         assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi
128361         assign $0\main_spisdcard_mosi_sel[2:0] 3'111
128362       attribute \src "ls180.v:8152.6-8152.10"
128363       case
128364         attribute \src "ls180.v:8153.3-8158.6"
128365         switch \main_spisdcard_clk_fall
128366           attribute \src "ls180.v:8153.7-8153.30"
128367           case 1'1
128368             assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8157$2594_Y
128369             attribute \src "ls180.v:8154.4-8156.7"
128370             switch \main_spisdcard_cs_enable
128371               attribute \src "ls180.v:8154.8-8154.32"
128372               case 1'1
128373                 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1
128374               case
128375             end
128376           case
128377         end
128378     end
128379     attribute \src "ls180.v:8160.2-8166.5"
128380     switch \main_spisdcard_clk_rise
128381       attribute \src "ls180.v:8160.6-8160.29"
128382       case 1'1
128383         attribute \src "ls180.v:8161.3-8165.6"
128384         switch \main_spisdcard_loopback
128385           attribute \src "ls180.v:8161.7-8161.30"
128386           case 1'1
128387             assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi }
128388           attribute \src "ls180.v:8163.7-8163.11"
128389           case
128390             assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso }
128391         end
128392       case
128393     end
128394     attribute \src "ls180.v:8167.2-8169.5"
128395     switch \main_spisdcard_miso_latch
128396       attribute \src "ls180.v:8167.6-8167.31"
128397       case 1'1
128398         assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data
128399       case
128400     end
128401     attribute \src "ls180.v:8171.2-8173.5"
128402     switch \main_spisdcard_count_spimaster1_next_value_ce
128403       attribute \src "ls180.v:8171.6-8171.51"
128404       case 1'1
128405         assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value
128406       case
128407     end
128408     attribute \src "ls180.v:8174.2-8187.5"
128409     switch \main_pwm0_enable
128410       attribute \src "ls180.v:8174.6-8174.22"
128411       case 1'1
128412         assign $0\main_pwm0_counter[31:0] $add$ls180.v:8175$2595_Y
128413         attribute \src "ls180.v:8176.3-8180.6"
128414         switch $lt$ls180.v:8176$2596_Y
128415           attribute \src "ls180.v:8176.7-8176.44"
128416           case 1'1
128417             assign $0\pwm[1:0] [0] 1'1
128418           attribute \src "ls180.v:8178.7-8178.11"
128419           case
128420             assign $0\pwm[1:0] [0] 1'0
128421         end
128422         attribute \src "ls180.v:8181.3-8183.6"
128423         switch $ge$ls180.v:8181$2598_Y
128424           attribute \src "ls180.v:8181.7-8181.55"
128425           case 1'1
128426             assign $0\main_pwm0_counter[31:0] 0
128427           case
128428         end
128429       attribute \src "ls180.v:8184.6-8184.10"
128430       case
128431         assign $0\main_pwm0_counter[31:0] 0
128432         assign $0\pwm[1:0] [0] 1'0
128433     end
128434     attribute \src "ls180.v:8188.2-8201.5"
128435     switch \main_pwm1_enable
128436       attribute \src "ls180.v:8188.6-8188.22"
128437       case 1'1
128438         assign $0\main_pwm1_counter[31:0] $add$ls180.v:8189$2599_Y
128439         attribute \src "ls180.v:8190.3-8194.6"
128440         switch $lt$ls180.v:8190$2600_Y
128441           attribute \src "ls180.v:8190.7-8190.44"
128442           case 1'1
128443             assign $0\pwm[1:0] [1] 1'1
128444           attribute \src "ls180.v:8192.7-8192.11"
128445           case
128446             assign $0\pwm[1:0] [1] 1'0
128447         end
128448         attribute \src "ls180.v:8195.3-8197.6"
128449         switch $ge$ls180.v:8195$2602_Y
128450           attribute \src "ls180.v:8195.7-8195.55"
128451           case 1'1
128452             assign $0\main_pwm1_counter[31:0] 0
128453           case
128454         end
128455       attribute \src "ls180.v:8198.6-8198.10"
128456       case
128457         assign $0\main_pwm1_counter[31:0] 0
128458         assign $0\pwm[1:0] [1] 1'0
128459     end
128460     attribute \src "ls180.v:8202.2-8204.5"
128461     switch $not$ls180.v:8202$2603_Y
128462       attribute \src "ls180.v:8202.6-8202.32"
128463       case 1'1
128464         assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8203$2604_Y
128465       case
128466     end
128467     attribute \src "ls180.v:8208.2-8210.5"
128468     switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce
128469       attribute \src "ls180.v:8208.6-8208.57"
128470       case 1'1
128471         assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value
128472       case
128473     end
128474     attribute \src "ls180.v:8212.2-8214.5"
128475     switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce
128476       attribute \src "ls180.v:8212.6-8212.57"
128477       case 1'1
128478         assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value
128479       case
128480     end
128481     attribute \src "ls180.v:8215.2-8217.5"
128482     switch \main_sdphy_cmdr_cmdr_pads_in_valid
128483       attribute \src "ls180.v:8215.6-8215.40"
128484       case 1'1
128485         assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8216$2605_Y
128486       case
128487     end
128488     attribute \src "ls180.v:8218.2-8220.5"
128489     switch \main_sdphy_cmdr_cmdr_converter_source_ready
128490       attribute \src "ls180.v:8218.6-8218.49"
128491       case 1'1
128492         assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
128493       case
128494     end
128495     attribute \src "ls180.v:8221.2-8228.5"
128496     switch \main_sdphy_cmdr_cmdr_converter_load_part
128497       attribute \src "ls180.v:8221.6-8221.46"
128498       case 1'1
128499         attribute \src "ls180.v:8222.3-8227.6"
128500         switch $or$ls180.v:8222$2607_Y
128501           attribute \src "ls180.v:8222.7-8222.98"
128502           case 1'1
128503             assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
128504             assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1
128505           attribute \src "ls180.v:8225.7-8225.11"
128506           case
128507             assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8226$2608_Y
128508         end
128509       case
128510     end
128511     attribute \src "ls180.v:8229.2-8242.5"
128512     switch $and$ls180.v:8229$2609_Y
128513       attribute \src "ls180.v:8229.6-8229.97"
128514       case 1'1
128515         attribute \src "ls180.v:8230.3-8236.6"
128516         switch $and$ls180.v:8230$2610_Y
128517           attribute \src "ls180.v:8230.7-8230.94"
128518           case 1'1
128519             assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first
128520             assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last
128521           attribute \src "ls180.v:8233.7-8233.11"
128522           case
128523             assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
128524             assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
128525         end
128526       attribute \src "ls180.v:8237.6-8237.10"
128527       case
128528         attribute \src "ls180.v:8238.3-8241.6"
128529         switch $and$ls180.v:8238$2611_Y
128530           attribute \src "ls180.v:8238.7-8238.94"
128531           case 1'1
128532             assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8239$2612_Y
128533             assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8240$2613_Y
128534           case
128535         end
128536     end
128537     attribute \src "ls180.v:8243.2-8270.5"
128538     switch \main_sdphy_cmdr_cmdr_converter_load_part
128539       attribute \src "ls180.v:8243.6-8243.46"
128540       case 1'1
128541         attribute \src "ls180.v:8244.3-8269.10"
128542         switch \main_sdphy_cmdr_cmdr_converter_demux
128543           attribute \src "ls180.v:0.0-0.0"
128544           case 3'000
128545             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128546           attribute \src "ls180.v:0.0-0.0"
128547           case 3'001
128548             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128549           attribute \src "ls180.v:0.0-0.0"
128550           case 3'010
128551             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128552           attribute \src "ls180.v:0.0-0.0"
128553           case 3'011
128554             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128555           attribute \src "ls180.v:0.0-0.0"
128556           case 3'100
128557             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128558           attribute \src "ls180.v:0.0-0.0"
128559           case 3'101
128560             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128561           attribute \src "ls180.v:0.0-0.0"
128562           case 3'110
128563             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128564           attribute \src "ls180.v:0.0-0.0"
128565           case 3'111
128566             assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data
128567           case
128568         end
128569       case
128570     end
128571     attribute \src "ls180.v:8271.2-8273.5"
128572     switch \main_sdphy_cmdr_cmdr_converter_load_part
128573       attribute \src "ls180.v:8271.6-8271.46"
128574       case 1'1
128575         assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8272$2614_Y
128576       case
128577     end
128578     attribute \src "ls180.v:8274.2-8279.5"
128579     switch $or$ls180.v:8274$2616_Y
128580       attribute \src "ls180.v:8274.6-8274.88"
128581       case 1'1
128582         assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid
128583         assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first
128584         assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last
128585         assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data
128586       case
128587     end
128588     attribute \src "ls180.v:8280.2-8285.5"
128589     switch \main_sdphy_cmdr_cmdr_reset
128590       attribute \src "ls180.v:8280.6-8280.32"
128591       case 1'1
128592         assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0
128593         assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
128594         assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
128595         assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
128596       case
128597     end
128598     attribute \src "ls180.v:8287.2-8289.5"
128599     switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0
128600       attribute \src "ls180.v:8287.6-8287.58"
128601       case 1'1
128602         assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0
128603       case
128604     end
128605     attribute \src "ls180.v:8290.2-8292.5"
128606     switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1
128607       attribute \src "ls180.v:8290.6-8290.60"
128608       case 1'1
128609         assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1
128610       case
128611     end
128612     attribute \src "ls180.v:8293.2-8295.5"
128613     switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2
128614       attribute \src "ls180.v:8293.6-8293.63"
128615       case 1'1
128616         assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2
128617       case
128618     end
128619     attribute \src "ls180.v:8296.2-8298.5"
128620     switch \main_sdphy_dataw_crcr_pads_in_valid
128621       attribute \src "ls180.v:8296.6-8296.41"
128622       case 1'1
128623         assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8297$2617_Y
128624       case
128625     end
128626     attribute \src "ls180.v:8299.2-8301.5"
128627     switch \main_sdphy_dataw_crcr_converter_source_ready
128628       attribute \src "ls180.v:8299.6-8299.50"
128629       case 1'1
128630         assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
128631       case
128632     end
128633     attribute \src "ls180.v:8302.2-8309.5"
128634     switch \main_sdphy_dataw_crcr_converter_load_part
128635       attribute \src "ls180.v:8302.6-8302.47"
128636       case 1'1
128637         attribute \src "ls180.v:8303.3-8308.6"
128638         switch $or$ls180.v:8303$2619_Y
128639           attribute \src "ls180.v:8303.7-8303.100"
128640           case 1'1
128641             assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
128642             assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1
128643           attribute \src "ls180.v:8306.7-8306.11"
128644           case
128645             assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8307$2620_Y
128646         end
128647       case
128648     end
128649     attribute \src "ls180.v:8310.2-8323.5"
128650     switch $and$ls180.v:8310$2621_Y
128651       attribute \src "ls180.v:8310.6-8310.99"
128652       case 1'1
128653         attribute \src "ls180.v:8311.3-8317.6"
128654         switch $and$ls180.v:8311$2622_Y
128655           attribute \src "ls180.v:8311.7-8311.96"
128656           case 1'1
128657             assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first
128658             assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last
128659           attribute \src "ls180.v:8314.7-8314.11"
128660           case
128661             assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
128662             assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
128663         end
128664       attribute \src "ls180.v:8318.6-8318.10"
128665       case
128666         attribute \src "ls180.v:8319.3-8322.6"
128667         switch $and$ls180.v:8319$2623_Y
128668           attribute \src "ls180.v:8319.7-8319.96"
128669           case 1'1
128670             assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8320$2624_Y
128671             assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8321$2625_Y
128672           case
128673         end
128674     end
128675     attribute \src "ls180.v:8324.2-8351.5"
128676     switch \main_sdphy_dataw_crcr_converter_load_part
128677       attribute \src "ls180.v:8324.6-8324.47"
128678       case 1'1
128679         attribute \src "ls180.v:8325.3-8350.10"
128680         switch \main_sdphy_dataw_crcr_converter_demux
128681           attribute \src "ls180.v:0.0-0.0"
128682           case 3'000
128683             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data
128684           attribute \src "ls180.v:0.0-0.0"
128685           case 3'001
128686             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data
128687           attribute \src "ls180.v:0.0-0.0"
128688           case 3'010
128689             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data
128690           attribute \src "ls180.v:0.0-0.0"
128691           case 3'011
128692             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data
128693           attribute \src "ls180.v:0.0-0.0"
128694           case 3'100
128695             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data
128696           attribute \src "ls180.v:0.0-0.0"
128697           case 3'101
128698             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data
128699           attribute \src "ls180.v:0.0-0.0"
128700           case 3'110
128701             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data
128702           attribute \src "ls180.v:0.0-0.0"
128703           case 3'111
128704             assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data
128705           case
128706         end
128707       case
128708     end
128709     attribute \src "ls180.v:8352.2-8354.5"
128710     switch \main_sdphy_dataw_crcr_converter_load_part
128711       attribute \src "ls180.v:8352.6-8352.47"
128712       case 1'1
128713         assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8353$2626_Y
128714       case
128715     end
128716     attribute \src "ls180.v:8355.2-8360.5"
128717     switch $or$ls180.v:8355$2628_Y
128718       attribute \src "ls180.v:8355.6-8355.90"
128719       case 1'1
128720         assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid
128721         assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first
128722         assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last
128723         assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data
128724       case
128725     end
128726     attribute \src "ls180.v:8361.2-8366.5"
128727     switch \main_sdphy_dataw_crcr_reset
128728       attribute \src "ls180.v:8361.6-8361.33"
128729       case 1'1
128730         assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0
128731         assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
128732         assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
128733         assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
128734       case
128735     end
128736     attribute \src "ls180.v:8368.2-8370.5"
128737     switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce
128738       attribute \src "ls180.v:8368.6-8368.63"
128739       case 1'1
128740         assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value
128741       case
128742     end
128743     attribute \src "ls180.v:8372.2-8374.5"
128744     switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce
128745       attribute \src "ls180.v:8372.6-8372.52"
128746       case 1'1
128747         assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value
128748       case
128749     end
128750     attribute \src "ls180.v:8375.2-8377.5"
128751     switch \main_sdphy_datar_datar_pads_in_valid
128752       attribute \src "ls180.v:8375.6-8375.42"
128753       case 1'1
128754         assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8376$2629_Y
128755       case
128756     end
128757     attribute \src "ls180.v:8378.2-8380.5"
128758     switch \main_sdphy_datar_datar_converter_source_ready
128759       attribute \src "ls180.v:8378.6-8378.51"
128760       case 1'1
128761         assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
128762       case
128763     end
128764     attribute \src "ls180.v:8381.2-8388.5"
128765     switch \main_sdphy_datar_datar_converter_load_part
128766       attribute \src "ls180.v:8381.6-8381.48"
128767       case 1'1
128768         attribute \src "ls180.v:8382.3-8387.6"
128769         switch $or$ls180.v:8382$2631_Y
128770           attribute \src "ls180.v:8382.7-8382.102"
128771           case 1'1
128772             assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
128773             assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1
128774           attribute \src "ls180.v:8385.7-8385.11"
128775           case
128776             assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8386$2632_Y
128777         end
128778       case
128779     end
128780     attribute \src "ls180.v:8389.2-8402.5"
128781     switch $and$ls180.v:8389$2633_Y
128782       attribute \src "ls180.v:8389.6-8389.101"
128783       case 1'1
128784         attribute \src "ls180.v:8390.3-8396.6"
128785         switch $and$ls180.v:8390$2634_Y
128786           attribute \src "ls180.v:8390.7-8390.98"
128787           case 1'1
128788             assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first
128789             assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last
128790           attribute \src "ls180.v:8393.7-8393.11"
128791           case
128792             assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
128793             assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
128794         end
128795       attribute \src "ls180.v:8397.6-8397.10"
128796       case
128797         attribute \src "ls180.v:8398.3-8401.6"
128798         switch $and$ls180.v:8398$2635_Y
128799           attribute \src "ls180.v:8398.7-8398.98"
128800           case 1'1
128801             assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8399$2636_Y
128802             assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8400$2637_Y
128803           case
128804         end
128805     end
128806     attribute \src "ls180.v:8403.2-8412.5"
128807     switch \main_sdphy_datar_datar_converter_load_part
128808       attribute \src "ls180.v:8403.6-8403.48"
128809       case 1'1
128810         attribute \src "ls180.v:8404.3-8411.10"
128811         switch \main_sdphy_datar_datar_converter_demux
128812           attribute \src "ls180.v:0.0-0.0"
128813           case 1'0
128814             assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data
128815           attribute \src "ls180.v:0.0-0.0"
128816           case 1'1
128817             assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data
128818           case
128819         end
128820       case
128821     end
128822     attribute \src "ls180.v:8413.2-8415.5"
128823     switch \main_sdphy_datar_datar_converter_load_part
128824       attribute \src "ls180.v:8413.6-8413.48"
128825       case 1'1
128826         assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8414$2638_Y
128827       case
128828     end
128829     attribute \src "ls180.v:8416.2-8421.5"
128830     switch $or$ls180.v:8416$2640_Y
128831       attribute \src "ls180.v:8416.6-8416.92"
128832       case 1'1
128833         assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid
128834         assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first
128835         assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last
128836         assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data
128837       case
128838     end
128839     attribute \src "ls180.v:8422.2-8427.5"
128840     switch \main_sdphy_datar_datar_reset
128841       attribute \src "ls180.v:8422.6-8422.34"
128842       case 1'1
128843         assign $0\main_sdphy_datar_datar_run[0:0] 1'0
128844         assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
128845         assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
128846         assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
128847       case
128848     end
128849     attribute \src "ls180.v:8429.2-8431.5"
128850     switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0
128851       attribute \src "ls180.v:8429.6-8429.60"
128852       case 1'1
128853         assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0
128854       case
128855     end
128856     attribute \src "ls180.v:8432.2-8434.5"
128857     switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1
128858       attribute \src "ls180.v:8432.6-8432.62"
128859       case 1'1
128860         assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1
128861       case
128862     end
128863     attribute \src "ls180.v:8435.2-8437.5"
128864     switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2
128865       attribute \src "ls180.v:8435.6-8435.66"
128866       case 1'1
128867         assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2
128868       case
128869     end
128870     attribute \src "ls180.v:8438.2-8444.5"
128871     switch \main_sdcore_crc7_inserter_clr
128872       attribute \src "ls180.v:8438.6-8438.35"
128873       case 1'1
128874         assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
128875       attribute \src "ls180.v:8440.6-8440.10"
128876       case
128877         attribute \src "ls180.v:8441.3-8443.6"
128878         switch \main_sdcore_crc7_inserter_enable
128879           attribute \src "ls180.v:8441.7-8441.39"
128880           case 1'1
128881             assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40
128882           case
128883         end
128884     end
128885     attribute \src "ls180.v:8445.2-8451.5"
128886     switch \main_sdcore_crc16_inserter_crc0_clr
128887       attribute \src "ls180.v:8445.6-8445.41"
128888       case 1'1
128889         assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
128890       attribute \src "ls180.v:8447.6-8447.10"
128891       case
128892         attribute \src "ls180.v:8448.3-8450.6"
128893         switch \main_sdcore_crc16_inserter_crc0_enable
128894           attribute \src "ls180.v:8448.7-8448.45"
128895           case 1'1
128896             assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2
128897           case
128898         end
128899     end
128900     attribute \src "ls180.v:8452.2-8458.5"
128901     switch \main_sdcore_crc16_inserter_crc1_clr
128902       attribute \src "ls180.v:8452.6-8452.41"
128903       case 1'1
128904         assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
128905       attribute \src "ls180.v:8454.6-8454.10"
128906       case
128907         attribute \src "ls180.v:8455.3-8457.6"
128908         switch \main_sdcore_crc16_inserter_crc1_enable
128909           attribute \src "ls180.v:8455.7-8455.45"
128910           case 1'1
128911             assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2
128912           case
128913         end
128914     end
128915     attribute \src "ls180.v:8459.2-8465.5"
128916     switch \main_sdcore_crc16_inserter_crc2_clr
128917       attribute \src "ls180.v:8459.6-8459.41"
128918       case 1'1
128919         assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
128920       attribute \src "ls180.v:8461.6-8461.10"
128921       case
128922         attribute \src "ls180.v:8462.3-8464.6"
128923         switch \main_sdcore_crc16_inserter_crc2_enable
128924           attribute \src "ls180.v:8462.7-8462.45"
128925           case 1'1
128926             assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2
128927           case
128928         end
128929     end
128930     attribute \src "ls180.v:8466.2-8472.5"
128931     switch \main_sdcore_crc16_inserter_crc3_clr
128932       attribute \src "ls180.v:8466.6-8466.41"
128933       case 1'1
128934         assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
128935       attribute \src "ls180.v:8468.6-8468.10"
128936       case
128937         attribute \src "ls180.v:8469.3-8471.6"
128938         switch \main_sdcore_crc16_inserter_crc3_enable
128939           attribute \src "ls180.v:8469.7-8469.45"
128940           case 1'1
128941             assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2
128942           case
128943         end
128944     end
128945     attribute \src "ls180.v:8474.2-8476.5"
128946     switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0
128947       attribute \src "ls180.v:8474.6-8474.82"
128948       case 1'1
128949         assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0
128950       case
128951     end
128952     attribute \src "ls180.v:8477.2-8479.5"
128953     switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1
128954       attribute \src "ls180.v:8477.6-8477.82"
128955       case 1'1
128956         assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1
128957       case
128958     end
128959     attribute \src "ls180.v:8480.2-8482.5"
128960     switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2
128961       attribute \src "ls180.v:8480.6-8480.82"
128962       case 1'1
128963         assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2
128964       case
128965     end
128966     attribute \src "ls180.v:8483.2-8485.5"
128967     switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3
128968       attribute \src "ls180.v:8483.6-8483.82"
128969       case 1'1
128970         assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3
128971       case
128972     end
128973     attribute \src "ls180.v:8486.2-8488.5"
128974     switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4
128975       attribute \src "ls180.v:8486.6-8486.78"
128976       case 1'1
128977         assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4
128978       case
128979     end
128980     attribute \src "ls180.v:8489.2-8491.5"
128981     switch $and$ls180.v:8489$2641_Y
128982       attribute \src "ls180.v:8489.6-8489.83"
128983       case 1'1
128984         assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc
128985       case
128986     end
128987     attribute \src "ls180.v:8492.2-8494.5"
128988     switch $and$ls180.v:8492$2642_Y
128989       attribute \src "ls180.v:8492.6-8492.83"
128990       case 1'1
128991         assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc
128992       case
128993     end
128994     attribute \src "ls180.v:8495.2-8497.5"
128995     switch $and$ls180.v:8495$2643_Y
128996       attribute \src "ls180.v:8495.6-8495.83"
128997       case 1'1
128998         assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc
128999       case
129000     end
129001     attribute \src "ls180.v:8498.2-8500.5"
129002     switch $and$ls180.v:8498$2644_Y
129003       attribute \src "ls180.v:8498.6-8498.83"
129004       case 1'1
129005         assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc
129006       case
129007     end
129008     attribute \src "ls180.v:8501.2-8505.5"
129009     switch $and$ls180.v:8501$2645_Y
129010       attribute \src "ls180.v:8501.6-8501.83"
129011       case 1'1
129012         assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] }
129013         assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13]
129014         assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12]
129015       case
129016     end
129017     attribute \src "ls180.v:8506.2-8510.5"
129018     switch $and$ls180.v:8506$2646_Y
129019       attribute \src "ls180.v:8506.6-8506.83"
129020       case 1'1
129021         assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] }
129022         assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13]
129023         assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12]
129024       case
129025     end
129026     attribute \src "ls180.v:8511.2-8515.5"
129027     switch $and$ls180.v:8511$2647_Y
129028       attribute \src "ls180.v:8511.6-8511.83"
129029       case 1'1
129030         assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] }
129031         assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13]
129032         assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12]
129033       case
129034     end
129035     attribute \src "ls180.v:8516.2-8520.5"
129036     switch $and$ls180.v:8516$2648_Y
129037       attribute \src "ls180.v:8516.6-8516.83"
129038       case 1'1
129039         assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] }
129040         assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13]
129041         assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12]
129042       case
129043     end
129044     attribute \src "ls180.v:8521.2-8529.5"
129045     switch $and$ls180.v:8521$2649_Y
129046       attribute \src "ls180.v:8521.6-8521.83"
129047       case 1'1
129048         attribute \src "ls180.v:8522.3-8528.6"
129049         switch \main_sdcore_crc16_checker_sink_last
129050           attribute \src "ls180.v:8522.7-8522.42"
129051           case 1'1
129052             assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000
129053           attribute \src "ls180.v:8524.7-8524.11"
129054           case
129055             attribute \src "ls180.v:8525.4-8527.7"
129056             switch $ne$ls180.v:8525$2650_Y
129057               attribute \src "ls180.v:8525.8-8525.48"
129058               case 1'1
129059                 assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8526$2651_Y
129060               case
129061             end
129062         end
129063       case
129064     end
129065     attribute \src "ls180.v:8530.2-8536.5"
129066     switch \main_sdcore_crc16_checker_crc0_clr
129067       attribute \src "ls180.v:8530.6-8530.40"
129068       case 1'1
129069         assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
129070       attribute \src "ls180.v:8532.6-8532.10"
129071       case
129072         attribute \src "ls180.v:8533.3-8535.6"
129073         switch \main_sdcore_crc16_checker_crc0_enable
129074           attribute \src "ls180.v:8533.7-8533.44"
129075           case 1'1
129076             assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2
129077           case
129078         end
129079     end
129080     attribute \src "ls180.v:8537.2-8543.5"
129081     switch \main_sdcore_crc16_checker_crc1_clr
129082       attribute \src "ls180.v:8537.6-8537.40"
129083       case 1'1
129084         assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
129085       attribute \src "ls180.v:8539.6-8539.10"
129086       case
129087         attribute \src "ls180.v:8540.3-8542.6"
129088         switch \main_sdcore_crc16_checker_crc1_enable
129089           attribute \src "ls180.v:8540.7-8540.44"
129090           case 1'1
129091             assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2
129092           case
129093         end
129094     end
129095     attribute \src "ls180.v:8544.2-8550.5"
129096     switch \main_sdcore_crc16_checker_crc2_clr
129097       attribute \src "ls180.v:8544.6-8544.40"
129098       case 1'1
129099         assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
129100       attribute \src "ls180.v:8546.6-8546.10"
129101       case
129102         attribute \src "ls180.v:8547.3-8549.6"
129103         switch \main_sdcore_crc16_checker_crc2_enable
129104           attribute \src "ls180.v:8547.7-8547.44"
129105           case 1'1
129106             assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2
129107           case
129108         end
129109     end
129110     attribute \src "ls180.v:8551.2-8557.5"
129111     switch \main_sdcore_crc16_checker_crc3_clr
129112       attribute \src "ls180.v:8551.6-8551.40"
129113       case 1'1
129114         assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
129115       attribute \src "ls180.v:8553.6-8553.10"
129116       case
129117         attribute \src "ls180.v:8554.3-8556.6"
129118         switch \main_sdcore_crc16_checker_crc3_enable
129119           attribute \src "ls180.v:8554.7-8554.44"
129120           case 1'1
129121             assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2
129122           case
129123         end
129124     end
129125     attribute \src "ls180.v:8559.2-8561.5"
129126     switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0
129127       attribute \src "ls180.v:8559.6-8559.52"
129128       case 1'1
129129         assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0
129130       case
129131     end
129132     attribute \src "ls180.v:8562.2-8564.5"
129133     switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1
129134       attribute \src "ls180.v:8562.6-8562.53"
129135       case 1'1
129136         assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1
129137       case
129138     end
129139     attribute \src "ls180.v:8565.2-8567.5"
129140     switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2
129141       attribute \src "ls180.v:8565.6-8565.53"
129142       case 1'1
129143         assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2
129144       case
129145     end
129146     attribute \src "ls180.v:8568.2-8570.5"
129147     switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3
129148       attribute \src "ls180.v:8568.6-8568.54"
129149       case 1'1
129150         assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3
129151       case
129152     end
129153     attribute \src "ls180.v:8571.2-8573.5"
129154     switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4
129155       attribute \src "ls180.v:8571.6-8571.53"
129156       case 1'1
129157         assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4
129158       case
129159     end
129160     attribute \src "ls180.v:8574.2-8576.5"
129161     switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5
129162       attribute \src "ls180.v:8574.6-8574.55"
129163       case 1'1
129164         assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5
129165       case
129166     end
129167     attribute \src "ls180.v:8577.2-8579.5"
129168     switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6
129169       attribute \src "ls180.v:8577.6-8577.54"
129170       case 1'1
129171         assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6
129172       case
129173     end
129174     attribute \src "ls180.v:8580.2-8582.5"
129175     switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7
129176       attribute \src "ls180.v:8580.6-8580.56"
129177       case 1'1
129178         assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7
129179       case
129180     end
129181     attribute \src "ls180.v:8583.2-8585.5"
129182     switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8
129183       attribute \src "ls180.v:8583.6-8583.63"
129184       case 1'1
129185         assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8
129186       case
129187     end
129188     attribute \src "ls180.v:8586.2-8588.5"
129189     switch $and$ls180.v:8586$2654_Y
129190       attribute \src "ls180.v:8586.6-8586.120"
129191       case 1'1
129192         assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8587$2655_Y
129193       case
129194     end
129195     attribute \src "ls180.v:8589.2-8591.5"
129196     switch \main_sdblock2mem_fifo_do_read
129197       attribute \src "ls180.v:8589.6-8589.35"
129198       case 1'1
129199         assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8590$2656_Y
129200       case
129201     end
129202     attribute \src "ls180.v:8592.2-8600.5"
129203     switch $and$ls180.v:8592$2659_Y
129204       attribute \src "ls180.v:8592.6-8592.120"
129205       case 1'1
129206         attribute \src "ls180.v:8593.3-8595.6"
129207         switch $not$ls180.v:8593$2660_Y
129208           attribute \src "ls180.v:8593.7-8593.39"
129209           case 1'1
129210             assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8594$2661_Y
129211           case
129212         end
129213       attribute \src "ls180.v:8596.6-8596.10"
129214       case
129215         attribute \src "ls180.v:8597.3-8599.6"
129216         switch \main_sdblock2mem_fifo_do_read
129217           attribute \src "ls180.v:8597.7-8597.36"
129218           case 1'1
129219             assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8598$2662_Y
129220           case
129221         end
129222     end
129223     attribute \src "ls180.v:8601.2-8603.5"
129224     switch \main_sdblock2mem_converter_source_ready
129225       attribute \src "ls180.v:8601.6-8601.45"
129226       case 1'1
129227         assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0
129228       case
129229     end
129230     attribute \src "ls180.v:8604.2-8611.5"
129231     switch \main_sdblock2mem_converter_load_part
129232       attribute \src "ls180.v:8604.6-8604.42"
129233       case 1'1
129234         attribute \src "ls180.v:8605.3-8610.6"
129235         switch $or$ls180.v:8605$2664_Y
129236           attribute \src "ls180.v:8605.7-8605.90"
129237           case 1'1
129238             assign $0\main_sdblock2mem_converter_demux[1:0] 2'00
129239             assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1
129240           attribute \src "ls180.v:8608.7-8608.11"
129241           case
129242             assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8609$2665_Y
129243         end
129244       case
129245     end
129246     attribute \src "ls180.v:8612.2-8625.5"
129247     switch $and$ls180.v:8612$2666_Y
129248       attribute \src "ls180.v:8612.6-8612.89"
129249       case 1'1
129250         attribute \src "ls180.v:8613.3-8619.6"
129251         switch $and$ls180.v:8613$2667_Y
129252           attribute \src "ls180.v:8613.7-8613.86"
129253           case 1'1
129254             assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first
129255             assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last
129256           attribute \src "ls180.v:8616.7-8616.11"
129257           case
129258             assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0
129259             assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0
129260         end
129261       attribute \src "ls180.v:8620.6-8620.10"
129262       case
129263         attribute \src "ls180.v:8621.3-8624.6"
129264         switch $and$ls180.v:8621$2668_Y
129265           attribute \src "ls180.v:8621.7-8621.86"
129266           case 1'1
129267             assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8622$2669_Y
129268             assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8623$2670_Y
129269           case
129270         end
129271     end
129272     attribute \src "ls180.v:8626.2-8641.5"
129273     switch \main_sdblock2mem_converter_load_part
129274       attribute \src "ls180.v:8626.6-8626.42"
129275       case 1'1
129276         attribute \src "ls180.v:8627.3-8640.10"
129277         switch \main_sdblock2mem_converter_demux
129278           attribute \src "ls180.v:0.0-0.0"
129279           case 2'00
129280             assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data
129281           attribute \src "ls180.v:0.0-0.0"
129282           case 2'01
129283             assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data
129284           attribute \src "ls180.v:0.0-0.0"
129285           case 2'10
129286             assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data
129287           attribute \src "ls180.v:0.0-0.0"
129288           case 2'11
129289             assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data
129290           case
129291         end
129292       case
129293     end
129294     attribute \src "ls180.v:8642.2-8644.5"
129295     switch \main_sdblock2mem_converter_load_part
129296       attribute \src "ls180.v:8642.6-8642.42"
129297       case 1'1
129298         assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8643$2671_Y
129299       case
129300     end
129301     attribute \src "ls180.v:8646.2-8648.5"
129302     switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce
129303       attribute \src "ls180.v:8646.6-8646.76"
129304       case 1'1
129305         assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value
129306       case
129307     end
129308     attribute \src "ls180.v:8649.2-8652.5"
129309     switch \main_sdblock2mem_wishbonedmawriter_reset
129310       attribute \src "ls180.v:8649.6-8649.46"
129311       case 1'1
129312         assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
129313         assign $0\builder_sdblock2memdma_state[1:0] 2'00
129314       case
129315     end
129316     attribute \src "ls180.v:8654.2-8656.5"
129317     switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce
129318       attribute \src "ls180.v:8654.6-8654.64"
129319       case 1'1
129320         assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value
129321       case
129322     end
129323     attribute \src "ls180.v:8658.2-8660.5"
129324     switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce
129325       attribute \src "ls180.v:8658.6-8658.76"
129326       case 1'1
129327         assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value
129328       case
129329     end
129330     attribute \src "ls180.v:8661.2-8664.5"
129331     switch \main_sdmem2block_dma_reset
129332       attribute \src "ls180.v:8661.6-8661.32"
129333       case 1'1
129334         assign $0\main_sdmem2block_dma_offset[31:0] 0
129335         assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
129336       case
129337     end
129338     attribute \src "ls180.v:8665.2-8671.5"
129339     switch $and$ls180.v:8665$2672_Y
129340       attribute \src "ls180.v:8665.6-8665.89"
129341       case 1'1
129342         attribute \src "ls180.v:8666.3-8670.6"
129343         switch \main_sdmem2block_converter_last
129344           attribute \src "ls180.v:8666.7-8666.38"
129345           case 1'1
129346             assign $0\main_sdmem2block_converter_mux[1:0] 2'00
129347           attribute \src "ls180.v:8668.7-8668.11"
129348           case
129349             assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8669$2673_Y
129350         end
129351       case
129352     end
129353     attribute \src "ls180.v:8672.2-8674.5"
129354     switch $and$ls180.v:8672$2676_Y
129355       attribute \src "ls180.v:8672.6-8672.120"
129356       case 1'1
129357         assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8673$2677_Y
129358       case
129359     end
129360     attribute \src "ls180.v:8675.2-8677.5"
129361     switch \main_sdmem2block_fifo_do_read
129362       attribute \src "ls180.v:8675.6-8675.35"
129363       case 1'1
129364         assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8676$2678_Y
129365       case
129366     end
129367     attribute \src "ls180.v:8678.2-8686.5"
129368     switch $and$ls180.v:8678$2681_Y
129369       attribute \src "ls180.v:8678.6-8678.120"
129370       case 1'1
129371         attribute \src "ls180.v:8679.3-8681.6"
129372         switch $not$ls180.v:8679$2682_Y
129373           attribute \src "ls180.v:8679.7-8679.39"
129374           case 1'1
129375             assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8680$2683_Y
129376           case
129377         end
129378       attribute \src "ls180.v:8682.6-8682.10"
129379       case
129380         attribute \src "ls180.v:8683.3-8685.6"
129381         switch \main_sdmem2block_fifo_do_read
129382           attribute \src "ls180.v:8683.7-8683.36"
129383           case 1'1
129384             assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8684$2684_Y
129385           case
129386         end
129387     end
129388     attribute \src "ls180.v:8688.2-8690.5"
129389     switch \builder_libresocsim_dat_w_next_value_ce0
129390       attribute \src "ls180.v:8688.6-8688.46"
129391       case 1'1
129392         assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0
129393       case
129394     end
129395     attribute \src "ls180.v:8691.2-8693.5"
129396     switch \builder_libresocsim_adr_next_value_ce1
129397       attribute \src "ls180.v:8691.6-8691.44"
129398       case 1'1
129399         assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1
129400       case
129401     end
129402     attribute \src "ls180.v:8694.2-8696.5"
129403     switch \builder_libresocsim_we_next_value_ce2
129404       attribute \src "ls180.v:8694.6-8694.43"
129405       case 1'1
129406         assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2
129407       case
129408     end
129409     attribute \src "ls180.v:8697.2-8793.9"
129410     switch \builder_grant
129411       attribute \src "ls180.v:0.0-0.0"
129412       case 3'000
129413         attribute \src "ls180.v:8699.4-8715.7"
129414         switch $not$ls180.v:8699$2685_Y
129415           attribute \src "ls180.v:8699.8-8699.29"
129416           case 1'1
129417             attribute \src "ls180.v:8700.5-8714.8"
129418             switch \builder_request [1]
129419               attribute \src "ls180.v:8700.9-8700.27"
129420               case 1'1
129421                 assign $0\builder_grant[2:0] 3'001
129422               attribute \src "ls180.v:8702.9-8702.13"
129423               case
129424                 attribute \src "ls180.v:8703.6-8713.9"
129425                 switch \builder_request [2]
129426                   attribute \src "ls180.v:8703.10-8703.28"
129427                   case 1'1
129428                     assign $0\builder_grant[2:0] 3'010
129429                   attribute \src "ls180.v:8705.10-8705.14"
129430                   case
129431                     attribute \src "ls180.v:8706.7-8712.10"
129432                     switch \builder_request [3]
129433                       attribute \src "ls180.v:8706.11-8706.29"
129434                       case 1'1
129435                         assign $0\builder_grant[2:0] 3'011
129436                       attribute \src "ls180.v:8708.11-8708.15"
129437                       case
129438                         attribute \src "ls180.v:8709.8-8711.11"
129439                         switch \builder_request [4]
129440                           attribute \src "ls180.v:8709.12-8709.30"
129441                           case 1'1
129442                             assign $0\builder_grant[2:0] 3'100
129443                           case
129444                         end
129445                     end
129446                 end
129447             end
129448           case
129449         end
129450       attribute \src "ls180.v:0.0-0.0"
129451       case 3'001
129452         attribute \src "ls180.v:8718.4-8734.7"
129453         switch $not$ls180.v:8718$2686_Y
129454           attribute \src "ls180.v:8718.8-8718.29"
129455           case 1'1
129456             attribute \src "ls180.v:8719.5-8733.8"
129457             switch \builder_request [2]
129458               attribute \src "ls180.v:8719.9-8719.27"
129459               case 1'1
129460                 assign $0\builder_grant[2:0] 3'010
129461               attribute \src "ls180.v:8721.9-8721.13"
129462               case
129463                 attribute \src "ls180.v:8722.6-8732.9"
129464                 switch \builder_request [3]
129465                   attribute \src "ls180.v:8722.10-8722.28"
129466                   case 1'1
129467                     assign $0\builder_grant[2:0] 3'011
129468                   attribute \src "ls180.v:8724.10-8724.14"
129469                   case
129470                     attribute \src "ls180.v:8725.7-8731.10"
129471                     switch \builder_request [4]
129472                       attribute \src "ls180.v:8725.11-8725.29"
129473                       case 1'1
129474                         assign $0\builder_grant[2:0] 3'100
129475                       attribute \src "ls180.v:8727.11-8727.15"
129476                       case
129477                         attribute \src "ls180.v:8728.8-8730.11"
129478                         switch \builder_request [0]
129479                           attribute \src "ls180.v:8728.12-8728.30"
129480                           case 1'1
129481                             assign $0\builder_grant[2:0] 3'000
129482                           case
129483                         end
129484                     end
129485                 end
129486             end
129487           case
129488         end
129489       attribute \src "ls180.v:0.0-0.0"
129490       case 3'010
129491         attribute \src "ls180.v:8737.4-8753.7"
129492         switch $not$ls180.v:8737$2687_Y
129493           attribute \src "ls180.v:8737.8-8737.29"
129494           case 1'1
129495             attribute \src "ls180.v:8738.5-8752.8"
129496             switch \builder_request [3]
129497               attribute \src "ls180.v:8738.9-8738.27"
129498               case 1'1
129499                 assign $0\builder_grant[2:0] 3'011
129500               attribute \src "ls180.v:8740.9-8740.13"
129501               case
129502                 attribute \src "ls180.v:8741.6-8751.9"
129503                 switch \builder_request [4]
129504                   attribute \src "ls180.v:8741.10-8741.28"
129505                   case 1'1
129506                     assign $0\builder_grant[2:0] 3'100
129507                   attribute \src "ls180.v:8743.10-8743.14"
129508                   case
129509                     attribute \src "ls180.v:8744.7-8750.10"
129510                     switch \builder_request [0]
129511                       attribute \src "ls180.v:8744.11-8744.29"
129512                       case 1'1
129513                         assign $0\builder_grant[2:0] 3'000
129514                       attribute \src "ls180.v:8746.11-8746.15"
129515                       case
129516                         attribute \src "ls180.v:8747.8-8749.11"
129517                         switch \builder_request [1]
129518                           attribute \src "ls180.v:8747.12-8747.30"
129519                           case 1'1
129520                             assign $0\builder_grant[2:0] 3'001
129521                           case
129522                         end
129523                     end
129524                 end
129525             end
129526           case
129527         end
129528       attribute \src "ls180.v:0.0-0.0"
129529       case 3'011
129530         attribute \src "ls180.v:8756.4-8772.7"
129531         switch $not$ls180.v:8756$2688_Y
129532           attribute \src "ls180.v:8756.8-8756.29"
129533           case 1'1
129534             attribute \src "ls180.v:8757.5-8771.8"
129535             switch \builder_request [4]
129536               attribute \src "ls180.v:8757.9-8757.27"
129537               case 1'1
129538                 assign $0\builder_grant[2:0] 3'100
129539               attribute \src "ls180.v:8759.9-8759.13"
129540               case
129541                 attribute \src "ls180.v:8760.6-8770.9"
129542                 switch \builder_request [0]
129543                   attribute \src "ls180.v:8760.10-8760.28"
129544                   case 1'1
129545                     assign $0\builder_grant[2:0] 3'000
129546                   attribute \src "ls180.v:8762.10-8762.14"
129547                   case
129548                     attribute \src "ls180.v:8763.7-8769.10"
129549                     switch \builder_request [1]
129550                       attribute \src "ls180.v:8763.11-8763.29"
129551                       case 1'1
129552                         assign $0\builder_grant[2:0] 3'001
129553                       attribute \src "ls180.v:8765.11-8765.15"
129554                       case
129555                         attribute \src "ls180.v:8766.8-8768.11"
129556                         switch \builder_request [2]
129557                           attribute \src "ls180.v:8766.12-8766.30"
129558                           case 1'1
129559                             assign $0\builder_grant[2:0] 3'010
129560                           case
129561                         end
129562                     end
129563                 end
129564             end
129565           case
129566         end
129567       attribute \src "ls180.v:0.0-0.0"
129568       case 3'100
129569         attribute \src "ls180.v:8775.4-8791.7"
129570         switch $not$ls180.v:8775$2689_Y
129571           attribute \src "ls180.v:8775.8-8775.29"
129572           case 1'1
129573             attribute \src "ls180.v:8776.5-8790.8"
129574             switch \builder_request [0]
129575               attribute \src "ls180.v:8776.9-8776.27"
129576               case 1'1
129577                 assign $0\builder_grant[2:0] 3'000
129578               attribute \src "ls180.v:8778.9-8778.13"
129579               case
129580                 attribute \src "ls180.v:8779.6-8789.9"
129581                 switch \builder_request [1]
129582                   attribute \src "ls180.v:8779.10-8779.28"
129583                   case 1'1
129584                     assign $0\builder_grant[2:0] 3'001
129585                   attribute \src "ls180.v:8781.10-8781.14"
129586                   case
129587                     attribute \src "ls180.v:8782.7-8788.10"
129588                     switch \builder_request [2]
129589                       attribute \src "ls180.v:8782.11-8782.29"
129590                       case 1'1
129591                         assign $0\builder_grant[2:0] 3'010
129592                       attribute \src "ls180.v:8784.11-8784.15"
129593                       case
129594                         attribute \src "ls180.v:8785.8-8787.11"
129595                         switch \builder_request [3]
129596                           attribute \src "ls180.v:8785.12-8785.30"
129597                           case 1'1
129598                             assign $0\builder_grant[2:0] 3'011
129599                           case
129600                         end
129601                     end
129602                 end
129603             end
129604           case
129605         end
129606       case
129607     end
129608     attribute \src "ls180.v:8795.2-8801.5"
129609     switch \builder_wait
129610       attribute \src "ls180.v:8795.6-8795.18"
129611       case 1'1
129612         attribute \src "ls180.v:8796.3-8798.6"
129613         switch $not$ls180.v:8796$2690_Y
129614           attribute \src "ls180.v:8796.7-8796.22"
129615           case 1'1
129616             assign $0\builder_count[19:0] $sub$ls180.v:8797$2691_Y
129617           case
129618         end
129619       attribute \src "ls180.v:8799.6-8799.10"
129620       case
129621         assign $0\builder_count[19:0] 20'11110100001001000000
129622     end
129623     attribute \src "ls180.v:8803.2-8833.5"
129624     switch \builder_csrbank0_sel
129625       attribute \src "ls180.v:8803.6-8803.26"
129626       case 1'1
129627         attribute \src "ls180.v:8804.3-8832.10"
129628         switch \builder_interface0_bank_bus_adr [3:0]
129629           attribute \src "ls180.v:0.0-0.0"
129630           case 4'0000
129631             assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w }
129632           attribute \src "ls180.v:0.0-0.0"
129633           case 4'0001
129634             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w
129635           attribute \src "ls180.v:0.0-0.0"
129636           case 4'0010
129637             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w
129638           attribute \src "ls180.v:0.0-0.0"
129639           case 4'0011
129640             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w
129641           attribute \src "ls180.v:0.0-0.0"
129642           case 4'0100
129643             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w
129644           attribute \src "ls180.v:0.0-0.0"
129645           case 4'0101
129646             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w
129647           attribute \src "ls180.v:0.0-0.0"
129648           case 4'0110
129649             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w
129650           attribute \src "ls180.v:0.0-0.0"
129651           case 4'0111
129652             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w
129653           attribute \src "ls180.v:0.0-0.0"
129654           case 4'1000
129655             assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w
129656           case
129657         end
129658       case
129659     end
129660     attribute \src "ls180.v:8834.2-8836.5"
129661     switch \builder_csrbank0_reset0_re
129662       attribute \src "ls180.v:8834.6-8834.32"
129663       case 1'1
129664         assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r
129665       case
129666     end
129667     attribute \src "ls180.v:8838.2-8840.5"
129668     switch \builder_csrbank0_scratch3_re
129669       attribute \src "ls180.v:8838.6-8838.34"
129670       case 1'1
129671         assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r
129672       case
129673     end
129674     attribute \src "ls180.v:8841.2-8843.5"
129675     switch \builder_csrbank0_scratch2_re
129676       attribute \src "ls180.v:8841.6-8841.34"
129677       case 1'1
129678         assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r
129679       case
129680     end
129681     attribute \src "ls180.v:8844.2-8846.5"
129682     switch \builder_csrbank0_scratch1_re
129683       attribute \src "ls180.v:8844.6-8844.34"
129684       case 1'1
129685         assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r
129686       case
129687     end
129688     attribute \src "ls180.v:8847.2-8849.5"
129689     switch \builder_csrbank0_scratch0_re
129690       attribute \src "ls180.v:8847.6-8847.34"
129691       case 1'1
129692         assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r
129693       case
129694     end
129695     attribute \src "ls180.v:8852.2-8873.5"
129696     switch \builder_csrbank1_sel
129697       attribute \src "ls180.v:8852.6-8852.26"
129698       case 1'1
129699         attribute \src "ls180.v:8853.3-8872.10"
129700         switch \builder_interface1_bank_bus_adr [2:0]
129701           attribute \src "ls180.v:0.0-0.0"
129702           case 3'000
129703             assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w
129704           attribute \src "ls180.v:0.0-0.0"
129705           case 3'001
129706             assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w
129707           attribute \src "ls180.v:0.0-0.0"
129708           case 3'010
129709             assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w
129710           attribute \src "ls180.v:0.0-0.0"
129711           case 3'011
129712             assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w
129713           attribute \src "ls180.v:0.0-0.0"
129714           case 3'100
129715             assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w
129716           attribute \src "ls180.v:0.0-0.0"
129717           case 3'101
129718             assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w
129719           case
129720         end
129721       case
129722     end
129723     attribute \src "ls180.v:8874.2-8876.5"
129724     switch \builder_csrbank1_oe1_re
129725       attribute \src "ls180.v:8874.6-8874.29"
129726       case 1'1
129727         assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r
129728       case
129729     end
129730     attribute \src "ls180.v:8877.2-8879.5"
129731     switch \builder_csrbank1_oe0_re
129732       attribute \src "ls180.v:8877.6-8877.29"
129733       case 1'1
129734         assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r
129735       case
129736     end
129737     attribute \src "ls180.v:8881.2-8883.5"
129738     switch \builder_csrbank1_out1_re
129739       attribute \src "ls180.v:8881.6-8881.30"
129740       case 1'1
129741         assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r
129742       case
129743     end
129744     attribute \src "ls180.v:8884.2-8886.5"
129745     switch \builder_csrbank1_out0_re
129746       attribute \src "ls180.v:8884.6-8884.30"
129747       case 1'1
129748         assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r
129749       case
129750     end
129751     attribute \src "ls180.v:8889.2-8898.5"
129752     switch \builder_csrbank2_sel
129753       attribute \src "ls180.v:8889.6-8889.26"
129754       case 1'1
129755         attribute \src "ls180.v:8890.3-8897.10"
129756         switch \builder_interface2_bank_bus_adr [0]
129757           attribute \src "ls180.v:0.0-0.0"
129758           case 1'0
129759             assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w }
129760           attribute \src "ls180.v:0.0-0.0"
129761           case 1'1
129762             assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w }
129763           case
129764         end
129765       case
129766     end
129767     attribute \src "ls180.v:8899.2-8901.5"
129768     switch \builder_csrbank2_w0_re
129769       attribute \src "ls180.v:8899.6-8899.28"
129770       case 1'1
129771         assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r
129772       case
129773     end
129774     attribute \src "ls180.v:8904.2-8934.5"
129775     switch \builder_csrbank3_sel
129776       attribute \src "ls180.v:8904.6-8904.26"
129777       case 1'1
129778         attribute \src "ls180.v:8905.3-8933.10"
129779         switch \builder_interface3_bank_bus_adr [3:0]
129780           attribute \src "ls180.v:0.0-0.0"
129781           case 4'0000
129782             assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w }
129783           attribute \src "ls180.v:0.0-0.0"
129784           case 4'0001
129785             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w
129786           attribute \src "ls180.v:0.0-0.0"
129787           case 4'0010
129788             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w
129789           attribute \src "ls180.v:0.0-0.0"
129790           case 4'0011
129791             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w
129792           attribute \src "ls180.v:0.0-0.0"
129793           case 4'0100
129794             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w
129795           attribute \src "ls180.v:0.0-0.0"
129796           case 4'0101
129797             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w
129798           attribute \src "ls180.v:0.0-0.0"
129799           case 4'0110
129800             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w
129801           attribute \src "ls180.v:0.0-0.0"
129802           case 4'0111
129803             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w
129804           attribute \src "ls180.v:0.0-0.0"
129805           case 4'1000
129806             assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w
129807           case
129808         end
129809       case
129810     end
129811     attribute \src "ls180.v:8935.2-8937.5"
129812     switch \builder_csrbank3_enable0_re
129813       attribute \src "ls180.v:8935.6-8935.33"
129814       case 1'1
129815         assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r
129816       case
129817     end
129818     attribute \src "ls180.v:8939.2-8941.5"
129819     switch \builder_csrbank3_width3_re
129820       attribute \src "ls180.v:8939.6-8939.32"
129821       case 1'1
129822         assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r
129823       case
129824     end
129825     attribute \src "ls180.v:8942.2-8944.5"
129826     switch \builder_csrbank3_width2_re
129827       attribute \src "ls180.v:8942.6-8942.32"
129828       case 1'1
129829         assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r
129830       case
129831     end
129832     attribute \src "ls180.v:8945.2-8947.5"
129833     switch \builder_csrbank3_width1_re
129834       attribute \src "ls180.v:8945.6-8945.32"
129835       case 1'1
129836         assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r
129837       case
129838     end
129839     attribute \src "ls180.v:8948.2-8950.5"
129840     switch \builder_csrbank3_width0_re
129841       attribute \src "ls180.v:8948.6-8948.32"
129842       case 1'1
129843         assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r
129844       case
129845     end
129846     attribute \src "ls180.v:8952.2-8954.5"
129847     switch \builder_csrbank3_period3_re
129848       attribute \src "ls180.v:8952.6-8952.33"
129849       case 1'1
129850         assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r
129851       case
129852     end
129853     attribute \src "ls180.v:8955.2-8957.5"
129854     switch \builder_csrbank3_period2_re
129855       attribute \src "ls180.v:8955.6-8955.33"
129856       case 1'1
129857         assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r
129858       case
129859     end
129860     attribute \src "ls180.v:8958.2-8960.5"
129861     switch \builder_csrbank3_period1_re
129862       attribute \src "ls180.v:8958.6-8958.33"
129863       case 1'1
129864         assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r
129865       case
129866     end
129867     attribute \src "ls180.v:8961.2-8963.5"
129868     switch \builder_csrbank3_period0_re
129869       attribute \src "ls180.v:8961.6-8961.33"
129870       case 1'1
129871         assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r
129872       case
129873     end
129874     attribute \src "ls180.v:8966.2-8996.5"
129875     switch \builder_csrbank4_sel
129876       attribute \src "ls180.v:8966.6-8966.26"
129877       case 1'1
129878         attribute \src "ls180.v:8967.3-8995.10"
129879         switch \builder_interface4_bank_bus_adr [3:0]
129880           attribute \src "ls180.v:0.0-0.0"
129881           case 4'0000
129882             assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w }
129883           attribute \src "ls180.v:0.0-0.0"
129884           case 4'0001
129885             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w
129886           attribute \src "ls180.v:0.0-0.0"
129887           case 4'0010
129888             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w
129889           attribute \src "ls180.v:0.0-0.0"
129890           case 4'0011
129891             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w
129892           attribute \src "ls180.v:0.0-0.0"
129893           case 4'0100
129894             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w
129895           attribute \src "ls180.v:0.0-0.0"
129896           case 4'0101
129897             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w
129898           attribute \src "ls180.v:0.0-0.0"
129899           case 4'0110
129900             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w
129901           attribute \src "ls180.v:0.0-0.0"
129902           case 4'0111
129903             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w
129904           attribute \src "ls180.v:0.0-0.0"
129905           case 4'1000
129906             assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w
129907           case
129908         end
129909       case
129910     end
129911     attribute \src "ls180.v:8997.2-8999.5"
129912     switch \builder_csrbank4_enable0_re
129913       attribute \src "ls180.v:8997.6-8997.33"
129914       case 1'1
129915         assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r
129916       case
129917     end
129918     attribute \src "ls180.v:9001.2-9003.5"
129919     switch \builder_csrbank4_width3_re
129920       attribute \src "ls180.v:9001.6-9001.32"
129921       case 1'1
129922         assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r
129923       case
129924     end
129925     attribute \src "ls180.v:9004.2-9006.5"
129926     switch \builder_csrbank4_width2_re
129927       attribute \src "ls180.v:9004.6-9004.32"
129928       case 1'1
129929         assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r
129930       case
129931     end
129932     attribute \src "ls180.v:9007.2-9009.5"
129933     switch \builder_csrbank4_width1_re
129934       attribute \src "ls180.v:9007.6-9007.32"
129935       case 1'1
129936         assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r
129937       case
129938     end
129939     attribute \src "ls180.v:9010.2-9012.5"
129940     switch \builder_csrbank4_width0_re
129941       attribute \src "ls180.v:9010.6-9010.32"
129942       case 1'1
129943         assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r
129944       case
129945     end
129946     attribute \src "ls180.v:9014.2-9016.5"
129947     switch \builder_csrbank4_period3_re
129948       attribute \src "ls180.v:9014.6-9014.33"
129949       case 1'1
129950         assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r
129951       case
129952     end
129953     attribute \src "ls180.v:9017.2-9019.5"
129954     switch \builder_csrbank4_period2_re
129955       attribute \src "ls180.v:9017.6-9017.33"
129956       case 1'1
129957         assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r
129958       case
129959     end
129960     attribute \src "ls180.v:9020.2-9022.5"
129961     switch \builder_csrbank4_period1_re
129962       attribute \src "ls180.v:9020.6-9020.33"
129963       case 1'1
129964         assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r
129965       case
129966     end
129967     attribute \src "ls180.v:9023.2-9025.5"
129968     switch \builder_csrbank4_period0_re
129969       attribute \src "ls180.v:9023.6-9023.33"
129970       case 1'1
129971         assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r
129972       case
129973     end
129974     attribute \src "ls180.v:9028.2-9076.5"
129975     switch \builder_csrbank5_sel
129976       attribute \src "ls180.v:9028.6-9028.26"
129977       case 1'1
129978         attribute \src "ls180.v:9029.3-9075.10"
129979         switch \builder_interface5_bank_bus_adr [3:0]
129980           attribute \src "ls180.v:0.0-0.0"
129981           case 4'0000
129982             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w
129983           attribute \src "ls180.v:0.0-0.0"
129984           case 4'0001
129985             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w
129986           attribute \src "ls180.v:0.0-0.0"
129987           case 4'0010
129988             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w
129989           attribute \src "ls180.v:0.0-0.0"
129990           case 4'0011
129991             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w
129992           attribute \src "ls180.v:0.0-0.0"
129993           case 4'0100
129994             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w
129995           attribute \src "ls180.v:0.0-0.0"
129996           case 4'0101
129997             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w
129998           attribute \src "ls180.v:0.0-0.0"
129999           case 4'0110
130000             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w
130001           attribute \src "ls180.v:0.0-0.0"
130002           case 4'0111
130003             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w
130004           attribute \src "ls180.v:0.0-0.0"
130005           case 4'1000
130006             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w
130007           attribute \src "ls180.v:0.0-0.0"
130008           case 4'1001
130009             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w
130010           attribute \src "ls180.v:0.0-0.0"
130011           case 4'1010
130012             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w
130013           attribute \src "ls180.v:0.0-0.0"
130014           case 4'1011
130015             assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w
130016           attribute \src "ls180.v:0.0-0.0"
130017           case 4'1100
130018             assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w }
130019           attribute \src "ls180.v:0.0-0.0"
130020           case 4'1101
130021             assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w }
130022           attribute \src "ls180.v:0.0-0.0"
130023           case 4'1110
130024             assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w }
130025           case
130026         end
130027       case
130028     end
130029     attribute \src "ls180.v:9077.2-9079.5"
130030     switch \builder_csrbank5_dma_base7_re
130031       attribute \src "ls180.v:9077.6-9077.35"
130032       case 1'1
130033         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r
130034       case
130035     end
130036     attribute \src "ls180.v:9080.2-9082.5"
130037     switch \builder_csrbank5_dma_base6_re
130038       attribute \src "ls180.v:9080.6-9080.35"
130039       case 1'1
130040         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r
130041       case
130042     end
130043     attribute \src "ls180.v:9083.2-9085.5"
130044     switch \builder_csrbank5_dma_base5_re
130045       attribute \src "ls180.v:9083.6-9083.35"
130046       case 1'1
130047         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r
130048       case
130049     end
130050     attribute \src "ls180.v:9086.2-9088.5"
130051     switch \builder_csrbank5_dma_base4_re
130052       attribute \src "ls180.v:9086.6-9086.35"
130053       case 1'1
130054         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r
130055       case
130056     end
130057     attribute \src "ls180.v:9089.2-9091.5"
130058     switch \builder_csrbank5_dma_base3_re
130059       attribute \src "ls180.v:9089.6-9089.35"
130060       case 1'1
130061         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r
130062       case
130063     end
130064     attribute \src "ls180.v:9092.2-9094.5"
130065     switch \builder_csrbank5_dma_base2_re
130066       attribute \src "ls180.v:9092.6-9092.35"
130067       case 1'1
130068         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r
130069       case
130070     end
130071     attribute \src "ls180.v:9095.2-9097.5"
130072     switch \builder_csrbank5_dma_base1_re
130073       attribute \src "ls180.v:9095.6-9095.35"
130074       case 1'1
130075         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r
130076       case
130077     end
130078     attribute \src "ls180.v:9098.2-9100.5"
130079     switch \builder_csrbank5_dma_base0_re
130080       attribute \src "ls180.v:9098.6-9098.35"
130081       case 1'1
130082         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r
130083       case
130084     end
130085     attribute \src "ls180.v:9102.2-9104.5"
130086     switch \builder_csrbank5_dma_length3_re
130087       attribute \src "ls180.v:9102.6-9102.37"
130088       case 1'1
130089         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r
130090       case
130091     end
130092     attribute \src "ls180.v:9105.2-9107.5"
130093     switch \builder_csrbank5_dma_length2_re
130094       attribute \src "ls180.v:9105.6-9105.37"
130095       case 1'1
130096         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r
130097       case
130098     end
130099     attribute \src "ls180.v:9108.2-9110.5"
130100     switch \builder_csrbank5_dma_length1_re
130101       attribute \src "ls180.v:9108.6-9108.37"
130102       case 1'1
130103         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r
130104       case
130105     end
130106     attribute \src "ls180.v:9111.2-9113.5"
130107     switch \builder_csrbank5_dma_length0_re
130108       attribute \src "ls180.v:9111.6-9111.37"
130109       case 1'1
130110         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r
130111       case
130112     end
130113     attribute \src "ls180.v:9115.2-9117.5"
130114     switch \builder_csrbank5_dma_enable0_re
130115       attribute \src "ls180.v:9115.6-9115.37"
130116       case 1'1
130117         assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r
130118       case
130119     end
130120     attribute \src "ls180.v:9119.2-9121.5"
130121     switch \builder_csrbank5_dma_loop0_re
130122       attribute \src "ls180.v:9119.6-9119.35"
130123       case 1'1
130124         assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r
130125       case
130126     end
130127     attribute \src "ls180.v:9124.2-9226.5"
130128     switch \builder_csrbank6_sel
130129       attribute \src "ls180.v:9124.6-9124.26"
130130       case 1'1
130131         attribute \src "ls180.v:9125.3-9225.10"
130132         switch \builder_interface6_bank_bus_adr [5:0]
130133           attribute \src "ls180.v:0.0-0.0"
130134           case 6'000000
130135             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w
130136           attribute \src "ls180.v:0.0-0.0"
130137           case 6'000001
130138             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w
130139           attribute \src "ls180.v:0.0-0.0"
130140           case 6'000010
130141             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w
130142           attribute \src "ls180.v:0.0-0.0"
130143           case 6'000011
130144             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w
130145           attribute \src "ls180.v:0.0-0.0"
130146           case 6'000100
130147             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w
130148           attribute \src "ls180.v:0.0-0.0"
130149           case 6'000101
130150             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w
130151           attribute \src "ls180.v:0.0-0.0"
130152           case 6'000110
130153             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w
130154           attribute \src "ls180.v:0.0-0.0"
130155           case 6'000111
130156             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w
130157           attribute \src "ls180.v:0.0-0.0"
130158           case 6'001000
130159             assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w }
130160           attribute \src "ls180.v:0.0-0.0"
130161           case 6'001001
130162             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w
130163           attribute \src "ls180.v:0.0-0.0"
130164           case 6'001010
130165             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w
130166           attribute \src "ls180.v:0.0-0.0"
130167           case 6'001011
130168             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w
130169           attribute \src "ls180.v:0.0-0.0"
130170           case 6'001100
130171             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w
130172           attribute \src "ls180.v:0.0-0.0"
130173           case 6'001101
130174             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w
130175           attribute \src "ls180.v:0.0-0.0"
130176           case 6'001110
130177             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w
130178           attribute \src "ls180.v:0.0-0.0"
130179           case 6'001111
130180             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w
130181           attribute \src "ls180.v:0.0-0.0"
130182           case 6'010000
130183             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w
130184           attribute \src "ls180.v:0.0-0.0"
130185           case 6'010001
130186             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w
130187           attribute \src "ls180.v:0.0-0.0"
130188           case 6'010010
130189             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w
130190           attribute \src "ls180.v:0.0-0.0"
130191           case 6'010011
130192             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w
130193           attribute \src "ls180.v:0.0-0.0"
130194           case 6'010100
130195             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w
130196           attribute \src "ls180.v:0.0-0.0"
130197           case 6'010101
130198             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w
130199           attribute \src "ls180.v:0.0-0.0"
130200           case 6'010110
130201             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w
130202           attribute \src "ls180.v:0.0-0.0"
130203           case 6'010111
130204             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w
130205           attribute \src "ls180.v:0.0-0.0"
130206           case 6'011000
130207             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w
130208           attribute \src "ls180.v:0.0-0.0"
130209           case 6'011001
130210             assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w }
130211           attribute \src "ls180.v:0.0-0.0"
130212           case 6'011010
130213             assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w }
130214           attribute \src "ls180.v:0.0-0.0"
130215           case 6'011011
130216             assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w }
130217           attribute \src "ls180.v:0.0-0.0"
130218           case 6'011100
130219             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w
130220           attribute \src "ls180.v:0.0-0.0"
130221           case 6'011101
130222             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w
130223           attribute \src "ls180.v:0.0-0.0"
130224           case 6'011110
130225             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w
130226           attribute \src "ls180.v:0.0-0.0"
130227           case 6'011111
130228             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w
130229           attribute \src "ls180.v:0.0-0.0"
130230           case 6'100000
130231             assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w
130232           case
130233         end
130234       case
130235     end
130236     attribute \src "ls180.v:9227.2-9229.5"
130237     switch \builder_csrbank6_cmd_argument3_re
130238       attribute \src "ls180.v:9227.6-9227.39"
130239       case 1'1
130240         assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r
130241       case
130242     end
130243     attribute \src "ls180.v:9230.2-9232.5"
130244     switch \builder_csrbank6_cmd_argument2_re
130245       attribute \src "ls180.v:9230.6-9230.39"
130246       case 1'1
130247         assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r
130248       case
130249     end
130250     attribute \src "ls180.v:9233.2-9235.5"
130251     switch \builder_csrbank6_cmd_argument1_re
130252       attribute \src "ls180.v:9233.6-9233.39"
130253       case 1'1
130254         assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r
130255       case
130256     end
130257     attribute \src "ls180.v:9236.2-9238.5"
130258     switch \builder_csrbank6_cmd_argument0_re
130259       attribute \src "ls180.v:9236.6-9236.39"
130260       case 1'1
130261         assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r
130262       case
130263     end
130264     attribute \src "ls180.v:9240.2-9242.5"
130265     switch \builder_csrbank6_cmd_command3_re
130266       attribute \src "ls180.v:9240.6-9240.38"
130267       case 1'1
130268         assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r
130269       case
130270     end
130271     attribute \src "ls180.v:9243.2-9245.5"
130272     switch \builder_csrbank6_cmd_command2_re
130273       attribute \src "ls180.v:9243.6-9243.38"
130274       case 1'1
130275         assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r
130276       case
130277     end
130278     attribute \src "ls180.v:9246.2-9248.5"
130279     switch \builder_csrbank6_cmd_command1_re
130280       attribute \src "ls180.v:9246.6-9246.38"
130281       case 1'1
130282         assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r
130283       case
130284     end
130285     attribute \src "ls180.v:9249.2-9251.5"
130286     switch \builder_csrbank6_cmd_command0_re
130287       attribute \src "ls180.v:9249.6-9249.38"
130288       case 1'1
130289         assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r
130290       case
130291     end
130292     attribute \src "ls180.v:9253.2-9255.5"
130293     switch \builder_csrbank6_block_length1_re
130294       attribute \src "ls180.v:9253.6-9253.39"
130295       case 1'1
130296         assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r
130297       case
130298     end
130299     attribute \src "ls180.v:9256.2-9258.5"
130300     switch \builder_csrbank6_block_length0_re
130301       attribute \src "ls180.v:9256.6-9256.39"
130302       case 1'1
130303         assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r
130304       case
130305     end
130306     attribute \src "ls180.v:9260.2-9262.5"
130307     switch \builder_csrbank6_block_count3_re
130308       attribute \src "ls180.v:9260.6-9260.38"
130309       case 1'1
130310         assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r
130311       case
130312     end
130313     attribute \src "ls180.v:9263.2-9265.5"
130314     switch \builder_csrbank6_block_count2_re
130315       attribute \src "ls180.v:9263.6-9263.38"
130316       case 1'1
130317         assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r
130318       case
130319     end
130320     attribute \src "ls180.v:9266.2-9268.5"
130321     switch \builder_csrbank6_block_count1_re
130322       attribute \src "ls180.v:9266.6-9266.38"
130323       case 1'1
130324         assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r
130325       case
130326     end
130327     attribute \src "ls180.v:9269.2-9271.5"
130328     switch \builder_csrbank6_block_count0_re
130329       attribute \src "ls180.v:9269.6-9269.38"
130330       case 1'1
130331         assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r
130332       case
130333     end
130334     attribute \src "ls180.v:9274.2-9334.5"
130335     switch \builder_csrbank7_sel
130336       attribute \src "ls180.v:9274.6-9274.26"
130337       case 1'1
130338         attribute \src "ls180.v:9275.3-9333.10"
130339         switch \builder_interface7_bank_bus_adr [4:0]
130340           attribute \src "ls180.v:0.0-0.0"
130341           case 5'00000
130342             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w
130343           attribute \src "ls180.v:0.0-0.0"
130344           case 5'00001
130345             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w
130346           attribute \src "ls180.v:0.0-0.0"
130347           case 5'00010
130348             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w
130349           attribute \src "ls180.v:0.0-0.0"
130350           case 5'00011
130351             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w
130352           attribute \src "ls180.v:0.0-0.0"
130353           case 5'00100
130354             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w
130355           attribute \src "ls180.v:0.0-0.0"
130356           case 5'00101
130357             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w
130358           attribute \src "ls180.v:0.0-0.0"
130359           case 5'00110
130360             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w
130361           attribute \src "ls180.v:0.0-0.0"
130362           case 5'00111
130363             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w
130364           attribute \src "ls180.v:0.0-0.0"
130365           case 5'01000
130366             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w
130367           attribute \src "ls180.v:0.0-0.0"
130368           case 5'01001
130369             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w
130370           attribute \src "ls180.v:0.0-0.0"
130371           case 5'01010
130372             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w
130373           attribute \src "ls180.v:0.0-0.0"
130374           case 5'01011
130375             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w
130376           attribute \src "ls180.v:0.0-0.0"
130377           case 5'01100
130378             assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w }
130379           attribute \src "ls180.v:0.0-0.0"
130380           case 5'01101
130381             assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w }
130382           attribute \src "ls180.v:0.0-0.0"
130383           case 5'01110
130384             assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w }
130385           attribute \src "ls180.v:0.0-0.0"
130386           case 5'01111
130387             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w
130388           attribute \src "ls180.v:0.0-0.0"
130389           case 5'10000
130390             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w
130391           attribute \src "ls180.v:0.0-0.0"
130392           case 5'10001
130393             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w
130394           attribute \src "ls180.v:0.0-0.0"
130395           case 5'10010
130396             assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w
130397           case
130398         end
130399       case
130400     end
130401     attribute \src "ls180.v:9335.2-9337.5"
130402     switch \builder_csrbank7_dma_base7_re
130403       attribute \src "ls180.v:9335.6-9335.35"
130404       case 1'1
130405         assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r
130406       case
130407     end
130408     attribute \src "ls180.v:9338.2-9340.5"
130409     switch \builder_csrbank7_dma_base6_re
130410       attribute \src "ls180.v:9338.6-9338.35"
130411       case 1'1
130412         assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r
130413       case
130414     end
130415     attribute \src "ls180.v:9341.2-9343.5"
130416     switch \builder_csrbank7_dma_base5_re
130417       attribute \src "ls180.v:9341.6-9341.35"
130418       case 1'1
130419         assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r
130420       case
130421     end
130422     attribute \src "ls180.v:9344.2-9346.5"
130423     switch \builder_csrbank7_dma_base4_re
130424       attribute \src "ls180.v:9344.6-9344.35"
130425       case 1'1
130426         assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r
130427       case
130428     end
130429     attribute \src "ls180.v:9347.2-9349.5"
130430     switch \builder_csrbank7_dma_base3_re
130431       attribute \src "ls180.v:9347.6-9347.35"
130432       case 1'1
130433         assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r
130434       case
130435     end
130436     attribute \src "ls180.v:9350.2-9352.5"
130437     switch \builder_csrbank7_dma_base2_re
130438       attribute \src "ls180.v:9350.6-9350.35"
130439       case 1'1
130440         assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r
130441       case
130442     end
130443     attribute \src "ls180.v:9353.2-9355.5"
130444     switch \builder_csrbank7_dma_base1_re
130445       attribute \src "ls180.v:9353.6-9353.35"
130446       case 1'1
130447         assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r
130448       case
130449     end
130450     attribute \src "ls180.v:9356.2-9358.5"
130451     switch \builder_csrbank7_dma_base0_re
130452       attribute \src "ls180.v:9356.6-9356.35"
130453       case 1'1
130454         assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r
130455       case
130456     end
130457     attribute \src "ls180.v:9360.2-9362.5"
130458     switch \builder_csrbank7_dma_length3_re
130459       attribute \src "ls180.v:9360.6-9360.37"
130460       case 1'1
130461         assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r
130462       case
130463     end
130464     attribute \src "ls180.v:9363.2-9365.5"
130465     switch \builder_csrbank7_dma_length2_re
130466       attribute \src "ls180.v:9363.6-9363.37"
130467       case 1'1
130468         assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r
130469       case
130470     end
130471     attribute \src "ls180.v:9366.2-9368.5"
130472     switch \builder_csrbank7_dma_length1_re
130473       attribute \src "ls180.v:9366.6-9366.37"
130474       case 1'1
130475         assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r
130476       case
130477     end
130478     attribute \src "ls180.v:9369.2-9371.5"
130479     switch \builder_csrbank7_dma_length0_re
130480       attribute \src "ls180.v:9369.6-9369.37"
130481       case 1'1
130482         assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r
130483       case
130484     end
130485     attribute \src "ls180.v:9373.2-9375.5"
130486     switch \builder_csrbank7_dma_enable0_re
130487       attribute \src "ls180.v:9373.6-9373.37"
130488       case 1'1
130489         assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r
130490       case
130491     end
130492     attribute \src "ls180.v:9377.2-9379.5"
130493     switch \builder_csrbank7_dma_loop0_re
130494       attribute \src "ls180.v:9377.6-9377.35"
130495       case 1'1
130496         assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r
130497       case
130498     end
130499     attribute \src "ls180.v:9382.2-9397.5"
130500     switch \builder_csrbank8_sel
130501       attribute \src "ls180.v:9382.6-9382.26"
130502       case 1'1
130503         attribute \src "ls180.v:9383.3-9396.10"
130504         switch \builder_interface8_bank_bus_adr [1:0]
130505           attribute \src "ls180.v:0.0-0.0"
130506           case 2'00
130507             assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w }
130508           attribute \src "ls180.v:0.0-0.0"
130509           case 2'01
130510             assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w }
130511           attribute \src "ls180.v:0.0-0.0"
130512           case 2'10
130513             assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w
130514           attribute \src "ls180.v:0.0-0.0"
130515           case 2'11
130516             assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w }
130517           case
130518         end
130519       case
130520     end
130521     attribute \src "ls180.v:9398.2-9400.5"
130522     switch \builder_csrbank8_clocker_divider1_re
130523       attribute \src "ls180.v:9398.6-9398.42"
130524       case 1'1
130525         assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r
130526       case
130527     end
130528     attribute \src "ls180.v:9401.2-9403.5"
130529     switch \builder_csrbank8_clocker_divider0_re
130530       attribute \src "ls180.v:9401.6-9401.42"
130531       case 1'1
130532         assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r
130533       case
130534     end
130535     attribute \src "ls180.v:9406.2-9439.5"
130536     switch \builder_csrbank9_sel
130537       attribute \src "ls180.v:9406.6-9406.26"
130538       case 1'1
130539         attribute \src "ls180.v:9407.3-9438.10"
130540         switch \builder_interface9_bank_bus_adr [3:0]
130541           attribute \src "ls180.v:0.0-0.0"
130542           case 4'0000
130543             assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w }
130544           attribute \src "ls180.v:0.0-0.0"
130545           case 4'0001
130546             assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w }
130547           attribute \src "ls180.v:0.0-0.0"
130548           case 4'0010
130549             assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w }
130550           attribute \src "ls180.v:0.0-0.0"
130551           case 4'0011
130552             assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w }
130553           attribute \src "ls180.v:0.0-0.0"
130554           case 4'0100
130555             assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w
130556           attribute \src "ls180.v:0.0-0.0"
130557           case 4'0101
130558             assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w }
130559           attribute \src "ls180.v:0.0-0.0"
130560           case 4'0110
130561             assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w
130562           attribute \src "ls180.v:0.0-0.0"
130563           case 4'0111
130564             assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w
130565           attribute \src "ls180.v:0.0-0.0"
130566           case 4'1000
130567             assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w
130568           attribute \src "ls180.v:0.0-0.0"
130569           case 4'1001
130570             assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w
130571           case
130572         end
130573       case
130574     end
130575     attribute \src "ls180.v:9440.2-9442.5"
130576     switch \builder_csrbank9_dfii_control0_re
130577       attribute \src "ls180.v:9440.6-9440.39"
130578       case 1'1
130579         assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r
130580       case
130581     end
130582     attribute \src "ls180.v:9444.2-9446.5"
130583     switch \builder_csrbank9_dfii_pi0_command0_re
130584       attribute \src "ls180.v:9444.6-9444.43"
130585       case 1'1
130586         assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r
130587       case
130588     end
130589     attribute \src "ls180.v:9448.2-9450.5"
130590     switch \builder_csrbank9_dfii_pi0_address1_re
130591       attribute \src "ls180.v:9448.6-9448.43"
130592       case 1'1
130593         assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r
130594       case
130595     end
130596     attribute \src "ls180.v:9451.2-9453.5"
130597     switch \builder_csrbank9_dfii_pi0_address0_re
130598       attribute \src "ls180.v:9451.6-9451.43"
130599       case 1'1
130600         assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r
130601       case
130602     end
130603     attribute \src "ls180.v:9455.2-9457.5"
130604     switch \builder_csrbank9_dfii_pi0_baddress0_re
130605       attribute \src "ls180.v:9455.6-9455.44"
130606       case 1'1
130607         assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r
130608       case
130609     end
130610     attribute \src "ls180.v:9459.2-9461.5"
130611     switch \builder_csrbank9_dfii_pi0_wrdata1_re
130612       attribute \src "ls180.v:9459.6-9459.42"
130613       case 1'1
130614         assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r
130615       case
130616     end
130617     attribute \src "ls180.v:9462.2-9464.5"
130618     switch \builder_csrbank9_dfii_pi0_wrdata0_re
130619       attribute \src "ls180.v:9462.6-9462.42"
130620       case 1'1
130621         assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r
130622       case
130623     end
130624     attribute \src "ls180.v:9467.2-9491.5"
130625     switch \builder_csrbank10_sel
130626       attribute \src "ls180.v:9467.6-9467.27"
130627       case 1'1
130628         attribute \src "ls180.v:9468.3-9490.10"
130629         switch \builder_interface10_bank_bus_adr [2:0]
130630           attribute \src "ls180.v:0.0-0.0"
130631           case 3'000
130632             assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w
130633           attribute \src "ls180.v:0.0-0.0"
130634           case 3'001
130635             assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w
130636           attribute \src "ls180.v:0.0-0.0"
130637           case 3'010
130638             assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w }
130639           attribute \src "ls180.v:0.0-0.0"
130640           case 3'011
130641             assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w
130642           attribute \src "ls180.v:0.0-0.0"
130643           case 3'100
130644             assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w
130645           attribute \src "ls180.v:0.0-0.0"
130646           case 3'101
130647             assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w }
130648           attribute \src "ls180.v:0.0-0.0"
130649           case 3'110
130650             assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w }
130651           case
130652         end
130653       case
130654     end
130655     attribute \src "ls180.v:9492.2-9494.5"
130656     switch \builder_csrbank10_control1_re
130657       attribute \src "ls180.v:9492.6-9492.35"
130658       case 1'1
130659         assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r
130660       case
130661     end
130662     attribute \src "ls180.v:9495.2-9497.5"
130663     switch \builder_csrbank10_control0_re
130664       attribute \src "ls180.v:9495.6-9495.35"
130665       case 1'1
130666         assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r
130667       case
130668     end
130669     attribute \src "ls180.v:9499.2-9501.5"
130670     switch \builder_csrbank10_mosi0_re
130671       attribute \src "ls180.v:9499.6-9499.32"
130672       case 1'1
130673         assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r
130674       case
130675     end
130676     attribute \src "ls180.v:9503.2-9505.5"
130677     switch \builder_csrbank10_cs0_re
130678       attribute \src "ls180.v:9503.6-9503.30"
130679       case 1'1
130680         assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r
130681       case
130682     end
130683     attribute \src "ls180.v:9507.2-9509.5"
130684     switch \builder_csrbank10_loopback0_re
130685       attribute \src "ls180.v:9507.6-9507.36"
130686       case 1'1
130687         assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r
130688       case
130689     end
130690     attribute \src "ls180.v:9512.2-9542.5"
130691     switch \builder_csrbank11_sel
130692       attribute \src "ls180.v:9512.6-9512.27"
130693       case 1'1
130694         attribute \src "ls180.v:9513.3-9541.10"
130695         switch \builder_interface11_bank_bus_adr [3:0]
130696           attribute \src "ls180.v:0.0-0.0"
130697           case 4'0000
130698             assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w
130699           attribute \src "ls180.v:0.0-0.0"
130700           case 4'0001
130701             assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w
130702           attribute \src "ls180.v:0.0-0.0"
130703           case 4'0010
130704             assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w }
130705           attribute \src "ls180.v:0.0-0.0"
130706           case 4'0011
130707             assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w
130708           attribute \src "ls180.v:0.0-0.0"
130709           case 4'0100
130710             assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w
130711           attribute \src "ls180.v:0.0-0.0"
130712           case 4'0101
130713             assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w }
130714           attribute \src "ls180.v:0.0-0.0"
130715           case 4'0110
130716             assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w }
130717           attribute \src "ls180.v:0.0-0.0"
130718           case 4'0111
130719             assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w
130720           attribute \src "ls180.v:0.0-0.0"
130721           case 4'1000
130722             assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w
130723           case
130724         end
130725       case
130726     end
130727     attribute \src "ls180.v:9543.2-9545.5"
130728     switch \builder_csrbank11_control1_re
130729       attribute \src "ls180.v:9543.6-9543.35"
130730       case 1'1
130731         assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r
130732       case
130733     end
130734     attribute \src "ls180.v:9546.2-9548.5"
130735     switch \builder_csrbank11_control0_re
130736       attribute \src "ls180.v:9546.6-9546.35"
130737       case 1'1
130738         assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r
130739       case
130740     end
130741     attribute \src "ls180.v:9550.2-9552.5"
130742     switch \builder_csrbank11_mosi0_re
130743       attribute \src "ls180.v:9550.6-9550.32"
130744       case 1'1
130745         assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r
130746       case
130747     end
130748     attribute \src "ls180.v:9554.2-9556.5"
130749     switch \builder_csrbank11_cs0_re
130750       attribute \src "ls180.v:9554.6-9554.30"
130751       case 1'1
130752         assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r
130753       case
130754     end
130755     attribute \src "ls180.v:9558.2-9560.5"
130756     switch \builder_csrbank11_loopback0_re
130757       attribute \src "ls180.v:9558.6-9558.36"
130758       case 1'1
130759         assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r
130760       case
130761     end
130762     attribute \src "ls180.v:9562.2-9564.5"
130763     switch \builder_csrbank11_clk_divider1_re
130764       attribute \src "ls180.v:9562.6-9562.39"
130765       case 1'1
130766         assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r
130767       case
130768     end
130769     attribute \src "ls180.v:9565.2-9567.5"
130770     switch \builder_csrbank11_clk_divider0_re
130771       attribute \src "ls180.v:9565.6-9565.39"
130772       case 1'1
130773         assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r
130774       case
130775     end
130776     attribute \src "ls180.v:9570.2-9624.5"
130777     switch \builder_csrbank12_sel
130778       attribute \src "ls180.v:9570.6-9570.27"
130779       case 1'1
130780         attribute \src "ls180.v:9571.3-9623.10"
130781         switch \builder_interface12_bank_bus_adr [4:0]
130782           attribute \src "ls180.v:0.0-0.0"
130783           case 5'00000
130784             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w
130785           attribute \src "ls180.v:0.0-0.0"
130786           case 5'00001
130787             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w
130788           attribute \src "ls180.v:0.0-0.0"
130789           case 5'00010
130790             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w
130791           attribute \src "ls180.v:0.0-0.0"
130792           case 5'00011
130793             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w
130794           attribute \src "ls180.v:0.0-0.0"
130795           case 5'00100
130796             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w
130797           attribute \src "ls180.v:0.0-0.0"
130798           case 5'00101
130799             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w
130800           attribute \src "ls180.v:0.0-0.0"
130801           case 5'00110
130802             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w
130803           attribute \src "ls180.v:0.0-0.0"
130804           case 5'00111
130805             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w
130806           attribute \src "ls180.v:0.0-0.0"
130807           case 5'01000
130808             assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w }
130809           attribute \src "ls180.v:0.0-0.0"
130810           case 5'01001
130811             assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w }
130812           attribute \src "ls180.v:0.0-0.0"
130813           case 5'01010
130814             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w
130815           attribute \src "ls180.v:0.0-0.0"
130816           case 5'01011
130817             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w
130818           attribute \src "ls180.v:0.0-0.0"
130819           case 5'01100
130820             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w
130821           attribute \src "ls180.v:0.0-0.0"
130822           case 5'01101
130823             assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w
130824           attribute \src "ls180.v:0.0-0.0"
130825           case 5'01110
130826             assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w }
130827           attribute \src "ls180.v:0.0-0.0"
130828           case 5'01111
130829             assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w }
130830           attribute \src "ls180.v:0.0-0.0"
130831           case 5'10000
130832             assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w }
130833           case
130834         end
130835       case
130836     end
130837     attribute \src "ls180.v:9625.2-9627.5"
130838     switch \builder_csrbank12_load3_re
130839       attribute \src "ls180.v:9625.6-9625.32"
130840       case 1'1
130841         assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r
130842       case
130843     end
130844     attribute \src "ls180.v:9628.2-9630.5"
130845     switch \builder_csrbank12_load2_re
130846       attribute \src "ls180.v:9628.6-9628.32"
130847       case 1'1
130848         assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r
130849       case
130850     end
130851     attribute \src "ls180.v:9631.2-9633.5"
130852     switch \builder_csrbank12_load1_re
130853       attribute \src "ls180.v:9631.6-9631.32"
130854       case 1'1
130855         assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r
130856       case
130857     end
130858     attribute \src "ls180.v:9634.2-9636.5"
130859     switch \builder_csrbank12_load0_re
130860       attribute \src "ls180.v:9634.6-9634.32"
130861       case 1'1
130862         assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r
130863       case
130864     end
130865     attribute \src "ls180.v:9638.2-9640.5"
130866     switch \builder_csrbank12_reload3_re
130867       attribute \src "ls180.v:9638.6-9638.34"
130868       case 1'1
130869         assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r
130870       case
130871     end
130872     attribute \src "ls180.v:9641.2-9643.5"
130873     switch \builder_csrbank12_reload2_re
130874       attribute \src "ls180.v:9641.6-9641.34"
130875       case 1'1
130876         assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r
130877       case
130878     end
130879     attribute \src "ls180.v:9644.2-9646.5"
130880     switch \builder_csrbank12_reload1_re
130881       attribute \src "ls180.v:9644.6-9644.34"
130882       case 1'1
130883         assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r
130884       case
130885     end
130886     attribute \src "ls180.v:9647.2-9649.5"
130887     switch \builder_csrbank12_reload0_re
130888       attribute \src "ls180.v:9647.6-9647.34"
130889       case 1'1
130890         assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r
130891       case
130892     end
130893     attribute \src "ls180.v:9651.2-9653.5"
130894     switch \builder_csrbank12_en0_re
130895       attribute \src "ls180.v:9651.6-9651.30"
130896       case 1'1
130897         assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r
130898       case
130899     end
130900     attribute \src "ls180.v:9655.2-9657.5"
130901     switch \builder_csrbank12_update_value0_re
130902       attribute \src "ls180.v:9655.6-9655.40"
130903       case 1'1
130904         assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r
130905       case
130906     end
130907     attribute \src "ls180.v:9659.2-9661.5"
130908     switch \builder_csrbank12_ev_enable0_re
130909       attribute \src "ls180.v:9659.6-9659.37"
130910       case 1'1
130911         assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r
130912       case
130913     end
130914     attribute \src "ls180.v:9664.2-9691.5"
130915     switch \builder_csrbank13_sel
130916       attribute \src "ls180.v:9664.6-9664.27"
130917       case 1'1
130918         attribute \src "ls180.v:9665.3-9690.10"
130919         switch \builder_interface13_bank_bus_adr [2:0]
130920           attribute \src "ls180.v:0.0-0.0"
130921           case 3'000
130922             assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w
130923           attribute \src "ls180.v:0.0-0.0"
130924           case 3'001
130925             assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w }
130926           attribute \src "ls180.v:0.0-0.0"
130927           case 3'010
130928             assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w }
130929           attribute \src "ls180.v:0.0-0.0"
130930           case 3'011
130931             assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w }
130932           attribute \src "ls180.v:0.0-0.0"
130933           case 3'100
130934             assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w }
130935           attribute \src "ls180.v:0.0-0.0"
130936           case 3'101
130937             assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w }
130938           attribute \src "ls180.v:0.0-0.0"
130939           case 3'110
130940             assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w }
130941           attribute \src "ls180.v:0.0-0.0"
130942           case 3'111
130943             assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w }
130944           case
130945         end
130946       case
130947     end
130948     attribute \src "ls180.v:9692.2-9694.5"
130949     switch \builder_csrbank13_ev_enable0_re
130950       attribute \src "ls180.v:9692.6-9692.37"
130951       case 1'1
130952         assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r
130953       case
130954     end
130955     attribute \src "ls180.v:9697.2-9712.5"
130956     switch \builder_csrbank14_sel
130957       attribute \src "ls180.v:9697.6-9697.27"
130958       case 1'1
130959         attribute \src "ls180.v:9698.3-9711.10"
130960         switch \builder_interface14_bank_bus_adr [1:0]
130961           attribute \src "ls180.v:0.0-0.0"
130962           case 2'00
130963             assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w
130964           attribute \src "ls180.v:0.0-0.0"
130965           case 2'01
130966             assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w
130967           attribute \src "ls180.v:0.0-0.0"
130968           case 2'10
130969             assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w
130970           attribute \src "ls180.v:0.0-0.0"
130971           case 2'11
130972             assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w
130973           case
130974         end
130975       case
130976     end
130977     attribute \src "ls180.v:9713.2-9715.5"
130978     switch \builder_csrbank14_tuning_word3_re
130979       attribute \src "ls180.v:9713.6-9713.39"
130980       case 1'1
130981         assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r
130982       case
130983     end
130984     attribute \src "ls180.v:9716.2-9718.5"
130985     switch \builder_csrbank14_tuning_word2_re
130986       attribute \src "ls180.v:9716.6-9716.39"
130987       case 1'1
130988         assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r
130989       case
130990     end
130991     attribute \src "ls180.v:9719.2-9721.5"
130992     switch \builder_csrbank14_tuning_word1_re
130993       attribute \src "ls180.v:9719.6-9719.39"
130994       case 1'1
130995         assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r
130996       case
130997     end
130998     attribute \src "ls180.v:9722.2-9724.5"
130999     switch \builder_csrbank14_tuning_word0_re
131000       attribute \src "ls180.v:9722.6-9722.39"
131001       case 1'1
131002         assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r
131003       case
131004     end
131005     attribute \src "ls180.v:9726.2-10020.5"
131006     switch \sys_rst_1
131007       attribute \src "ls180.v:9726.6-9726.15"
131008       case 1'1
131009         assign $0\main_libresocsim_reset_storage[0:0] 1'0
131010         assign $0\main_libresocsim_reset_re[0:0] 1'0
131011         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
131012         assign $0\main_libresocsim_scratch_re[0:0] 1'0
131013         assign $0\main_libresocsim_bus_errors[31:0] 0
131014         assign $0\spisdcard_clk[0:0] 1'0
131015         assign $0\spisdcard_mosi[0:0] 1'0
131016         assign $0\spisdcard_cs_n[0:0] 1'0
131017         assign $0\uart_tx[0:0] 1'1
131018         assign $0\pwm[1:0] 2'00
131019         assign $0\spimaster_clk[0:0] 1'0
131020         assign $0\spimaster_mosi[0:0] 1'0
131021         assign $0\spimaster_cs_n[0:0] 1'0
131022         assign $0\main_libresocsim_converter0_counter[0:0] 1'0
131023         assign $0\main_libresocsim_converter1_counter[0:0] 1'0
131024         assign $0\main_libresocsim_converter2_counter[0:0] 1'0
131025         assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0
131026         assign $0\main_libresocsim_load_storage[31:0] 0
131027         assign $0\main_libresocsim_load_re[0:0] 1'0
131028         assign $0\main_libresocsim_reload_storage[31:0] 0
131029         assign $0\main_libresocsim_reload_re[0:0] 1'0
131030         assign $0\main_libresocsim_en_storage[0:0] 1'0
131031         assign $0\main_libresocsim_en_re[0:0] 1'0
131032         assign $0\main_libresocsim_update_value_storage[0:0] 1'0
131033         assign $0\main_libresocsim_update_value_re[0:0] 1'0
131034         assign $0\main_libresocsim_value_status[31:0] 0
131035         assign $0\main_libresocsim_zero_pending[0:0] 1'0
131036         assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0
131037         assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0
131038         assign $0\main_libresocsim_eventmanager_re[0:0] 1'0
131039         assign $0\main_libresocsim_value[31:0] 0
131040         assign $0\main_dfi_p0_rddata_valid[0:0] 1'0
131041         assign $0\main_rddata_en[2:0] 3'000
131042         assign $0\main_sdram_storage[3:0] 4'0001
131043         assign $0\main_sdram_re[0:0] 1'0
131044         assign $0\main_sdram_command_storage[5:0] 6'000000
131045         assign $0\main_sdram_command_re[0:0] 1'0
131046         assign $0\main_sdram_address_re[0:0] 1'0
131047         assign $0\main_sdram_baddress_re[0:0] 1'0
131048         assign $0\main_sdram_wrdata_re[0:0] 1'0
131049         assign $0\main_sdram_status[15:0] 16'0000000000000000
131050         assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000
131051         assign $0\main_sdram_dfi_p0_bank[1:0] 2'00
131052         assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1
131053         assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1
131054         assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1
131055         assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1
131056         assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
131057         assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0
131058         assign $0\main_sdram_timer_count1[9:0] 10'1100001101
131059         assign $0\main_sdram_postponer_req_o[0:0] 1'0
131060         assign $0\main_sdram_postponer_count[0:0] 1'0
131061         assign $0\main_sdram_sequencer_done1[0:0] 1'0
131062         assign $0\main_sdram_sequencer_counter[3:0] 4'0000
131063         assign $0\main_sdram_sequencer_count[0:0] 1'0
131064         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
131065         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
131066         assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
131067         assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
131068         assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000
131069         assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0
131070         assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
131071         assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
131072         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
131073         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
131074         assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
131075         assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
131076         assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000
131077         assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0
131078         assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
131079         assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
131080         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
131081         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
131082         assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
131083         assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
131084         assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000
131085         assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0
131086         assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
131087         assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
131088         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
131089         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
131090         assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
131091         assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
131092         assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000
131093         assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0
131094         assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
131095         assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
131096         assign $0\main_sdram_choose_cmd_grant[1:0] 2'00
131097         assign $0\main_sdram_choose_req_grant[1:0] 2'00
131098         assign $0\main_sdram_tccdcon_ready[0:0] 1'0
131099         assign $0\main_sdram_tccdcon_count[0:0] 1'0
131100         assign $0\main_sdram_twtrcon_ready[0:0] 1'0
131101         assign $0\main_sdram_twtrcon_count[2:0] 3'000
131102         assign $0\main_sdram_time0[4:0] 5'00000
131103         assign $0\main_sdram_time1[3:0] 4'0000
131104         assign $0\main_converter_counter[0:0] 1'0
131105         assign $0\main_cmd_consumed[0:0] 1'0
131106         assign $0\main_wdata_consumed[0:0] 1'0
131107         assign $0\main_uart_phy_storage[31:0] 9895604
131108         assign $0\main_uart_phy_re[0:0] 1'0
131109         assign $0\main_uart_phy_sink_ready[0:0] 1'0
131110         assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0
131111         assign $0\main_uart_phy_tx_busy[0:0] 1'0
131112         assign $0\main_uart_phy_source_valid[0:0] 1'0
131113         assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0
131114         assign $0\main_uart_phy_rx_r[0:0] 1'0
131115         assign $0\main_uart_phy_rx_busy[0:0] 1'0
131116         assign $0\main_uart_tx_pending[0:0] 1'0
131117         assign $0\main_uart_tx_old_trigger[0:0] 1'0
131118         assign $0\main_uart_rx_pending[0:0] 1'0
131119         assign $0\main_uart_rx_old_trigger[0:0] 1'0
131120         assign $0\main_uart_eventmanager_storage[1:0] 2'00
131121         assign $0\main_uart_eventmanager_re[0:0] 1'0
131122         assign $0\main_uart_tx_fifo_readable[0:0] 1'0
131123         assign $0\main_uart_tx_fifo_level0[4:0] 5'00000
131124         assign $0\main_uart_tx_fifo_produce[3:0] 4'0000
131125         assign $0\main_uart_tx_fifo_consume[3:0] 4'0000
131126         assign $0\main_uart_rx_fifo_readable[0:0] 1'0
131127         assign $0\main_uart_rx_fifo_level0[4:0] 5'00000
131128         assign $0\main_uart_rx_fifo_produce[3:0] 4'0000
131129         assign $0\main_uart_rx_fifo_consume[3:0] 4'0000
131130         assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000
131131         assign $0\main_gpio_oe_re[0:0] 1'0
131132         assign $0\main_gpio_out_storage[15:0] 16'0000000000000000
131133         assign $0\main_gpio_out_re[0:0] 1'0
131134         assign $0\main_spimaster5_miso[7:0] 8'00000000
131135         assign $0\main_spimaster11_storage[15:0] 16'0000000000000000
131136         assign $0\main_spimaster12_re[0:0] 1'0
131137         assign $0\main_spimaster17_re[0:0] 1'0
131138         assign $0\main_spimaster21_storage[0:0] 1'1
131139         assign $0\main_spimaster22_re[0:0] 1'0
131140         assign $0\main_spimaster23_storage[0:0] 1'0
131141         assign $0\main_spimaster24_re[0:0] 1'0
131142         assign $0\main_spimaster27_count[2:0] 3'000
131143         assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000
131144         assign $0\main_spimaster33_mosi_data[7:0] 8'00000000
131145         assign $0\main_spimaster34_mosi_sel[2:0] 3'000
131146         assign $0\main_spimaster35_miso_data[7:0] 8'00000000
131147         assign $0\main_spisdcard_miso[7:0] 8'00000000
131148         assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000
131149         assign $0\main_spisdcard_control_re[0:0] 1'0
131150         assign $0\main_spisdcard_mosi_re[0:0] 1'0
131151         assign $0\main_spisdcard_cs_storage[0:0] 1'1
131152         assign $0\main_spisdcard_cs_re[0:0] 1'0
131153         assign $0\main_spisdcard_loopback_storage[0:0] 1'0
131154         assign $0\main_spisdcard_loopback_re[0:0] 1'0
131155         assign $0\main_spisdcard_count[2:0] 3'000
131156         assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
131157         assign $0\main_spisdcard_mosi_data[7:0] 8'00000000
131158         assign $0\main_spisdcard_mosi_sel[2:0] 3'000
131159         assign $0\main_spisdcard_miso_data[7:0] 8'00000000
131160         assign $0\main_spimaster1_storage[15:0] 16'0000000001111101
131161         assign $0\main_spimaster1_re[0:0] 1'0
131162         assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000
131163         assign $0\main_pwm0_enable_storage[0:0] 1'0
131164         assign $0\main_pwm0_enable_re[0:0] 1'0
131165         assign $0\main_pwm0_width_re[0:0] 1'0
131166         assign $0\main_pwm0_period_re[0:0] 1'0
131167         assign $0\main_pwm1_enable_storage[0:0] 1'0
131168         assign $0\main_pwm1_enable_re[0:0] 1'0
131169         assign $0\main_pwm1_width_re[0:0] 1'0
131170         assign $0\main_pwm1_period_re[0:0] 1'0
131171         assign $0\main_i2c_storage[2:0] 3'000
131172         assign $0\main_i2c_re[0:0] 1'0
131173         assign $0\main_sdphy_clocker_storage[8:0] 9'100000000
131174         assign $0\main_sdphy_clocker_re[0:0] 1'0
131175         assign $0\main_sdphy_clocker_clk0[0:0] 1'0
131176         assign $0\main_sdphy_clocker_clks[8:0] 9'000000000
131177         assign $0\main_sdphy_clocker_clk_d[0:0] 1'0
131178         assign $0\main_sdphy_init_count[7:0] 8'00000000
131179         assign $0\main_sdphy_cmdw_count[7:0] 8'00000000
131180         assign $0\main_sdphy_cmdr_timeout[31:0] 500000
131181         assign $0\main_sdphy_cmdr_count[7:0] 8'00000000
131182         assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0
131183         assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
131184         assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
131185         assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
131186         assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
131187         assign $0\main_sdphy_dataw_count[7:0] 8'00000000
131188         assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0
131189         assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
131190         assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
131191         assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
131192         assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0
131193         assign $0\main_sdphy_datar_timeout[31:0] 500000
131194         assign $0\main_sdphy_datar_count[9:0] 10'0000000000
131195         assign $0\main_sdphy_datar_datar_run[0:0] 1'0
131196         assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0
131197         assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
131198         assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
131199         assign $0\main_sdphy_datar_datar_reset[0:0] 1'0
131200         assign $0\main_sdcore_cmd_argument_storage[31:0] 0
131201         assign $0\main_sdcore_cmd_argument_re[0:0] 1'0
131202         assign $0\main_sdcore_cmd_command_storage[31:0] 0
131203         assign $0\main_sdcore_cmd_command_re[0:0] 1'0
131204         assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
131205         assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000
131206         assign $0\main_sdcore_block_length_re[0:0] 1'0
131207         assign $0\main_sdcore_block_count_storage[31:0] 0
131208         assign $0\main_sdcore_block_count_re[0:0] 1'0
131209         assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
131210         assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000
131211         assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
131212         assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
131213         assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
131214         assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
131215         assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
131216         assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
131217         assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
131218         assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
131219         assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000
131220         assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000
131221         assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
131222         assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
131223         assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
131224         assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
131225         assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
131226         assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
131227         assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
131228         assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
131229         assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
131230         assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
131231         assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
131232         assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
131233         assign $0\main_sdcore_cmd_count[2:0] 3'000
131234         assign $0\main_sdcore_cmd_done[0:0] 1'0
131235         assign $0\main_sdcore_cmd_error[0:0] 1'0
131236         assign $0\main_sdcore_cmd_timeout[0:0] 1'0
131237         assign $0\main_sdcore_data_count[31:0] 0
131238         assign $0\main_sdcore_data_done[0:0] 1'0
131239         assign $0\main_sdcore_data_error[0:0] 1'0
131240         assign $0\main_sdcore_data_timeout[0:0] 1'0
131241         assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000
131242         assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000
131243         assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000
131244         assign $0\main_sdblock2mem_converter_demux[1:0] 2'00
131245         assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0
131246         assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
131247         assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
131248         assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
131249         assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
131250         assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
131251         assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
131252         assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
131253         assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
131254         assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
131255         assign $0\main_sdmem2block_dma_data[31:0] 0
131256         assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
131257         assign $0\main_sdmem2block_dma_base_re[0:0] 1'0
131258         assign $0\main_sdmem2block_dma_length_storage[31:0] 0
131259         assign $0\main_sdmem2block_dma_length_re[0:0] 1'0
131260         assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0
131261         assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0
131262         assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0
131263         assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0
131264         assign $0\main_sdmem2block_dma_offset[31:0] 0
131265         assign $0\main_sdmem2block_converter_mux[1:0] 2'00
131266         assign $0\main_sdmem2block_fifo_level[5:0] 6'000000
131267         assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000
131268         assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000
131269         assign $0\builder_converter0_state[0:0] 1'0
131270         assign $0\builder_converter1_state[0:0] 1'0
131271         assign $0\builder_converter2_state[0:0] 1'0
131272         assign $0\builder_refresher_state[1:0] 2'00
131273         assign $0\builder_bankmachine0_state[2:0] 3'000
131274         assign $0\builder_bankmachine1_state[2:0] 3'000
131275         assign $0\builder_bankmachine2_state[2:0] 3'000
131276         assign $0\builder_bankmachine3_state[2:0] 3'000
131277         assign $0\builder_multiplexer_state[2:0] 3'000
131278         assign $0\builder_new_master_wdata_ready[0:0] 1'0
131279         assign $0\builder_new_master_rdata_valid0[0:0] 1'0
131280         assign $0\builder_new_master_rdata_valid1[0:0] 1'0
131281         assign $0\builder_new_master_rdata_valid2[0:0] 1'0
131282         assign $0\builder_new_master_rdata_valid3[0:0] 1'0
131283         assign $0\builder_converter_state[0:0] 1'0
131284         assign $0\builder_spimaster0_state[1:0] 2'00
131285         assign $0\builder_spimaster1_state[1:0] 2'00
131286         assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0
131287         assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00
131288         assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000
131289         assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0
131290         assign $0\builder_sdphy_fsm_state[2:0] 3'000
131291         assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000
131292         assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
131293         assign $0\builder_sdcore_fsm_state[2:0] 3'000
131294         assign $0\builder_sdblock2memdma_state[1:0] 2'00
131295         assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0
131296         assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
131297         assign $0\builder_libresocsim_we[0:0] 1'0
131298         assign $0\builder_grant[2:0] 3'000
131299         assign $0\builder_slave_sel_r[4:0] 5'00000
131300         assign $0\builder_count[19:0] 20'11110100001001000000
131301         assign $0\builder_state[1:0] 2'00
131302       case
131303     end
131304     sync posedge \sys_clk_1
131305       update \spisdcard_clk $0\spisdcard_clk[0:0]
131306       update \spisdcard_mosi $0\spisdcard_mosi[0:0]
131307       update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
131308       update \uart_tx $0\uart_tx[0:0]
131309       update \pwm $0\pwm[1:0]
131310       update \spimaster_clk $0\spimaster_clk[0:0]
131311       update \spimaster_mosi $0\spimaster_mosi[0:0]
131312       update \spimaster_cs_n $0\spimaster_cs_n[0:0]
131313       update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
131314       update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
131315       update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
131316       update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0]
131317       update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0]
131318       update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0]
131319       update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0]
131320       update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0]
131321       update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0]
131322       update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0]
131323       update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0]
131324       update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0]
131325       update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0]
131326       update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0]
131327       update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0]
131328       update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0]
131329       update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0]
131330       update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0]
131331       update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0]
131332       update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0]
131333       update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0]
131334       update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0]
131335       update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0]
131336       update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0]
131337       update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0]
131338       update \main_libresocsim_value $0\main_libresocsim_value[31:0]
131339       update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0]
131340       update \main_rddata_en $0\main_rddata_en[2:0]
131341       update \main_sdram_storage $0\main_sdram_storage[3:0]
131342       update \main_sdram_re $0\main_sdram_re[0:0]
131343       update \main_sdram_command_storage $0\main_sdram_command_storage[5:0]
131344       update \main_sdram_command_re $0\main_sdram_command_re[0:0]
131345       update \main_sdram_address_storage $0\main_sdram_address_storage[12:0]
131346       update \main_sdram_address_re $0\main_sdram_address_re[0:0]
131347       update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0]
131348       update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0]
131349       update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0]
131350       update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0]
131351       update \main_sdram_status $0\main_sdram_status[15:0]
131352       update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0]
131353       update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0]
131354       update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0]
131355       update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0]
131356       update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0]
131357       update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0]
131358       update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0]
131359       update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0]
131360       update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0]
131361       update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0]
131362       update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0]
131363       update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0]
131364       update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0]
131365       update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0]
131366       update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0]
131367       update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0]
131368       update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0]
131369       update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0]
131370       update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0]
131371       update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
131372       update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
131373       update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
131374       update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
131375       update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
131376       update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
131377       update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
131378       update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
131379       update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0]
131380       update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0]
131381       update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0]
131382       update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0]
131383       update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
131384       update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
131385       update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
131386       update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]
131387       update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
131388       update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
131389       update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
131390       update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
131391       update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0]
131392       update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0]
131393       update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0]
131394       update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0]
131395       update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
131396       update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
131397       update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
131398       update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
131399       update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
131400       update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
131401       update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
131402       update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
131403       update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0]
131404       update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0]
131405       update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0]
131406       update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0]
131407       update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
131408       update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
131409       update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
131410       update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]
131411       update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
131412       update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
131413       update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
131414       update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
131415       update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0]
131416       update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0]
131417       update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0]
131418       update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0]
131419       update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0]
131420       update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0]
131421       update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0]
131422       update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0]
131423       update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0]
131424       update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0]
131425       update \main_sdram_time0 $0\main_sdram_time0[4:0]
131426       update \main_sdram_time1 $0\main_sdram_time1[3:0]
131427       update \main_converter_counter $0\main_converter_counter[0:0]
131428       update \main_converter_dat_r $0\main_converter_dat_r[31:0]
131429       update \main_cmd_consumed $0\main_cmd_consumed[0:0]
131430       update \main_wdata_consumed $0\main_wdata_consumed[0:0]
131431       update \main_uart_phy_storage $0\main_uart_phy_storage[31:0]
131432       update \main_uart_phy_re $0\main_uart_phy_re[0:0]
131433       update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0]
131434       update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0]
131435       update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0]
131436       update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0]
131437       update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0]
131438       update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0]
131439       update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0]
131440       update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0]
131441       update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0]
131442       update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0]
131443       update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0]
131444       update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0]
131445       update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0]
131446       update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0]
131447       update \main_uart_tx_pending $0\main_uart_tx_pending[0:0]
131448       update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0]
131449       update \main_uart_rx_pending $0\main_uart_rx_pending[0:0]
131450       update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0]
131451       update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0]
131452       update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0]
131453       update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0]
131454       update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0]
131455       update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0]
131456       update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0]
131457       update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0]
131458       update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0]
131459       update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0]
131460       update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0]
131461       update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0]
131462       update \main_gpio_oe_re $0\main_gpio_oe_re[0:0]
131463       update \main_gpio_out_storage $0\main_gpio_out_storage[15:0]
131464       update \main_gpio_out_re $0\main_gpio_out_re[0:0]
131465       update \main_spimaster5_miso $0\main_spimaster5_miso[7:0]
131466       update \main_spimaster11_storage $0\main_spimaster11_storage[15:0]
131467       update \main_spimaster12_re $0\main_spimaster12_re[0:0]
131468       update \main_spimaster16_storage $0\main_spimaster16_storage[7:0]
131469       update \main_spimaster17_re $0\main_spimaster17_re[0:0]
131470       update \main_spimaster21_storage $0\main_spimaster21_storage[0:0]
131471       update \main_spimaster22_re $0\main_spimaster22_re[0:0]
131472       update \main_spimaster23_storage $0\main_spimaster23_storage[0:0]
131473       update \main_spimaster24_re $0\main_spimaster24_re[0:0]
131474       update \main_spimaster27_count $0\main_spimaster27_count[2:0]
131475       update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0]
131476       update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0]
131477       update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0]
131478       update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0]
131479       update \main_spisdcard_miso $0\main_spisdcard_miso[7:0]
131480       update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0]
131481       update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0]
131482       update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0]
131483       update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0]
131484       update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0]
131485       update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0]
131486       update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0]
131487       update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0]
131488       update \main_spisdcard_count $0\main_spisdcard_count[2:0]
131489       update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0]
131490       update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0]
131491       update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0]
131492       update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0]
131493       update \main_spimaster1_storage $0\main_spimaster1_storage[15:0]
131494       update \main_spimaster1_re $0\main_spimaster1_re[0:0]
131495       update \main_dummy $0\main_dummy[35:0]
131496       update \main_pwm0_counter $0\main_pwm0_counter[31:0]
131497       update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0]
131498       update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0]
131499       update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0]
131500       update \main_pwm0_width_re $0\main_pwm0_width_re[0:0]
131501       update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0]
131502       update \main_pwm0_period_re $0\main_pwm0_period_re[0:0]
131503       update \main_pwm1_counter $0\main_pwm1_counter[31:0]
131504       update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0]
131505       update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0]
131506       update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0]
131507       update \main_pwm1_width_re $0\main_pwm1_width_re[0:0]
131508       update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0]
131509       update \main_pwm1_period_re $0\main_pwm1_period_re[0:0]
131510       update \main_i2c_storage $0\main_i2c_storage[2:0]
131511       update \main_i2c_re $0\main_i2c_re[0:0]
131512       update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0]
131513       update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0]
131514       update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0]
131515       update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0]
131516       update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0]
131517       update \main_sdphy_init_count $0\main_sdphy_init_count[7:0]
131518       update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0]
131519       update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0]
131520       update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0]
131521       update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0]
131522       update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
131523       update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
131524       update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
131525       update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
131526       update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0]
131527       update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
131528       update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
131529       update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
131530       update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
131531       update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
131532       update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0]
131533       update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0]
131534       update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0]
131535       update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0]
131536       update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0]
131537       update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
131538       update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
131539       update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0]
131540       update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
131541       update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0]
131542       update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0]
131543       update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0]
131544       update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
131545       update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0]
131546       update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0]
131547       update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0]
131548       update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0]
131549       update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0]
131550       update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0]
131551       update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0]
131552       update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
131553       update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0]
131554       update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0]
131555       update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0]
131556       update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0]
131557       update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0]
131558       update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0]
131559       update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0]
131560       update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0]
131561       update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0]
131562       update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0]
131563       update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0]
131564       update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0]
131565       update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0]
131566       update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0]
131567       update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0]
131568       update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0]
131569       update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0]
131570       update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0]
131571       update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
131572       update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
131573       update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
131574       update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
131575       update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0]
131576       update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0]
131577       update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0]
131578       update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0]
131579       update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0]
131580       update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0]
131581       update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
131582       update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
131583       update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
131584       update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
131585       update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0]
131586       update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0]
131587       update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0]
131588       update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0]
131589       update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0]
131590       update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0]
131591       update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0]
131592       update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0]
131593       update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0]
131594       update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0]
131595       update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0]
131596       update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0]
131597       update \main_sdcore_data_count $0\main_sdcore_data_count[31:0]
131598       update \main_sdcore_data_done $0\main_sdcore_data_done[0:0]
131599       update \main_sdcore_data_error $0\main_sdcore_data_error[0:0]
131600       update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0]
131601       update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0]
131602       update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0]
131603       update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0]
131604       update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0]
131605       update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0]
131606       update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0]
131607       update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
131608       update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0]
131609       update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0]
131610       update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
131611       update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
131612       update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
131613       update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
131614       update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
131615       update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
131616       update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
131617       update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
131618       update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0]
131619       update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0]
131620       update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0]
131621       update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0]
131622       update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0]
131623       update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0]
131624       update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0]
131625       update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0]
131626       update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0]
131627       update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0]
131628       update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0]
131629       update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0]
131630       update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0]
131631       update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0]
131632       update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0]
131633       update \builder_converter0_state $0\builder_converter0_state[0:0]
131634       update \builder_converter1_state $0\builder_converter1_state[0:0]
131635       update \builder_converter2_state $0\builder_converter2_state[0:0]
131636       update \builder_refresher_state $0\builder_refresher_state[1:0]
131637       update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0]
131638       update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0]
131639       update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0]
131640       update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0]
131641       update \builder_multiplexer_state $0\builder_multiplexer_state[2:0]
131642       update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0]
131643       update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0]
131644       update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0]
131645       update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0]
131646       update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0]
131647       update \builder_converter_state $0\builder_converter_state[0:0]
131648       update \builder_spimaster0_state $0\builder_spimaster0_state[1:0]
131649       update \builder_spimaster1_state $0\builder_spimaster1_state[1:0]
131650       update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0]
131651       update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0]
131652       update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0]
131653       update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0]
131654       update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0]
131655       update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0]
131656       update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0]
131657       update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0]
131658       update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0]
131659       update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0]
131660       update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0]
131661       update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0]
131662       update \builder_libresocsim_we $0\builder_libresocsim_we[0:0]
131663       update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0]
131664       update \builder_grant $0\builder_grant[2:0]
131665       update \builder_slave_sel_r $0\builder_slave_sel_r[4:0]
131666       update \builder_count $0\builder_count[19:0]
131667       update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0]
131668       update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0]
131669       update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0]
131670       update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0]
131671       update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0]
131672       update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0]
131673       update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0]
131674       update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0]
131675       update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0]
131676       update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0]
131677       update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0]
131678       update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0]
131679       update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0]
131680       update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0]
131681       update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0]
131682       update \builder_state $0\builder_state[1:0]
131683       update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0]
131684       update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0]
131685       update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0]
131686       update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0]
131687       update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0]
131688       update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0]
131689       update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0]
131690       update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0]
131691       update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0]
131692       update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0]
131693       update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0]
131694       update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0]
131695       update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0]
131696       update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0]
131697       update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0]
131698       update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0]
131699       update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0]
131700       update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0]
131701       update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0]
131702       update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0]
131703       update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0]
131704       update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0]
131705       update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0]
131706       update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0]
131707       update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0]
131708       update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0]
131709       update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0]
131710       update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0]
131711       update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0]
131712       update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0]
131713       update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0]
131714       update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0]
131715       update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0]
131716       update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0]
131717   end
131718   attribute \src "ls180.v:745.5-745.43"
131719   process $proc$ls180.v:745$3052
131720     assign { } { }
131721     assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
131722     sync always
131723       update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0]
131724     sync init
131725   end
131726   attribute \src "ls180.v:748.5-748.49"
131727   process $proc$ls180.v:748$3053
131728     assign { } { }
131729     assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
131730     sync always
131731     sync init
131732       update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
131733   end
131734   attribute \src "ls180.v:749.5-749.49"
131735   process $proc$ls180.v:749$3054
131736     assign { } { }
131737     assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
131738     sync always
131739     sync init
131740       update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
131741   end
131742   attribute \src "ls180.v:750.5-750.48"
131743   process $proc$ls180.v:750$3055
131744     assign { } { }
131745     assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
131746     sync always
131747     sync init
131748       update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
131749   end
131750   attribute \src "ls180.v:754.11-754.46"
131751   process $proc$ls180.v:754$3056
131752     assign { } { }
131753     assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
131754     sync always
131755     sync init
131756       update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
131757   end
131758   attribute \src "ls180.v:756.11-756.45"
131759   process $proc$ls180.v:756$3057
131760     assign { } { }
131761     assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
131762     sync always
131763     sync init
131764       update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
131765   end
131766   attribute \src "ls180.v:758.5-758.44"
131767   process $proc$ls180.v:758$3058
131768     assign { } { }
131769     assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
131770     sync always
131771     sync init
131772       update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
131773   end
131774   attribute \src "ls180.v:759.5-759.45"
131775   process $proc$ls180.v:759$3059
131776     assign { } { }
131777     assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
131778     sync always
131779     sync init
131780       update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0]
131781   end
131782   attribute \src "ls180.v:76.5-76.46"
131783   process $proc$ls180.v:76$2782
131784     assign { } { }
131785     assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0
131786     sync always
131787       update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0]
131788     sync init
131789   end
131790   attribute \src "ls180.v:761.5-761.48"
131791   process $proc$ls180.v:761$3060
131792     assign { } { }
131793     assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
131794     sync always
131795     sync init
131796       update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0]
131797   end
131798   attribute \src "ls180.v:763.5-763.43"
131799   process $proc$ls180.v:763$3061
131800     assign { } { }
131801     assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
131802     sync always
131803     sync init
131804       update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
131805   end
131806   attribute \src "ls180.v:766.5-766.49"
131807   process $proc$ls180.v:766$3062
131808     assign { } { }
131809     assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
131810     sync always
131811     sync init
131812       update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
131813   end
131814   attribute \src "ls180.v:767.5-767.49"
131815   process $proc$ls180.v:767$3063
131816     assign { } { }
131817     assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
131818     sync always
131819     sync init
131820       update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
131821   end
131822   attribute \src "ls180.v:768.5-768.48"
131823   process $proc$ls180.v:768$3064
131824     assign { } { }
131825     assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
131826     sync always
131827     sync init
131828       update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0]
131829   end
131830   attribute \src "ls180.v:772.11-772.46"
131831   process $proc$ls180.v:772$3065
131832     assign { } { }
131833     assign $1\main_sdram_choose_req_valids[3:0] 4'0000
131834     sync always
131835     sync init
131836       update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0]
131837   end
131838   attribute \src "ls180.v:774.11-774.45"
131839   process $proc$ls180.v:774$3066
131840     assign { } { }
131841     assign $1\main_sdram_choose_req_grant[1:0] 2'00
131842     sync always
131843     sync init
131844       update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0]
131845   end
131846   attribute \src "ls180.v:776.12-776.36"
131847   process $proc$ls180.v:776$3067
131848     assign { } { }
131849     assign $0\main_sdram_nop_a[12:0] 13'0000000000000
131850     sync always
131851       update \main_sdram_nop_a $0\main_sdram_nop_a[12:0]
131852     sync init
131853   end
131854   attribute \src "ls180.v:777.11-777.35"
131855   process $proc$ls180.v:777$3068
131856     assign { } { }
131857     assign $0\main_sdram_nop_ba[1:0] 2'00
131858     sync always
131859       update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0]
131860     sync init
131861   end
131862   attribute \src "ls180.v:778.11-778.40"
131863   process $proc$ls180.v:778$3069
131864     assign { } { }
131865     assign $1\main_sdram_steerer_sel[1:0] 2'00
131866     sync always
131867     sync init
131868       update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0]
131869   end
131870   attribute \src "ls180.v:779.5-779.31"
131871   process $proc$ls180.v:779$3070
131872     assign { } { }
131873     assign $0\main_sdram_steerer0[0:0] 1'1
131874     sync always
131875       update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0]
131876     sync init
131877   end
131878   attribute \src "ls180.v:780.5-780.31"
131879   process $proc$ls180.v:780$3071
131880     assign { } { }
131881     assign $0\main_sdram_steerer1[0:0] 1'1
131882     sync always
131883       update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0]
131884     sync init
131885   end
131886   attribute \src "ls180.v:782.32-782.63"
131887   process $proc$ls180.v:782$3072
131888     assign { } { }
131889     assign $0\main_sdram_trrdcon_ready[0:0] 1'1
131890     sync always
131891       update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0]
131892     sync init
131893   end
131894   attribute \src "ls180.v:784.32-784.63"
131895   process $proc$ls180.v:784$3073
131896     assign { } { }
131897     assign $0\main_sdram_tfawcon_ready[0:0] 1'1
131898     sync always
131899       update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0]
131900     sync init
131901   end
131902   attribute \src "ls180.v:786.32-786.63"
131903   process $proc$ls180.v:786$3074
131904     assign { } { }
131905     assign $1\main_sdram_tccdcon_ready[0:0] 1'0
131906     sync always
131907     sync init
131908       update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0]
131909   end
131910   attribute \src "ls180.v:787.5-787.36"
131911   process $proc$ls180.v:787$3075
131912     assign { } { }
131913     assign $1\main_sdram_tccdcon_count[0:0] 1'0
131914     sync always
131915     sync init
131916       update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0]
131917   end
131918   attribute \src "ls180.v:789.32-789.63"
131919   process $proc$ls180.v:789$3076
131920     assign { } { }
131921     assign $1\main_sdram_twtrcon_ready[0:0] 1'0
131922     sync always
131923     sync init
131924       update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0]
131925   end
131926   attribute \src "ls180.v:790.11-790.42"
131927   process $proc$ls180.v:790$3077
131928     assign { } { }
131929     assign $1\main_sdram_twtrcon_count[2:0] 3'000
131930     sync always
131931     sync init
131932       update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0]
131933   end
131934   attribute \src "ls180.v:793.5-793.26"
131935   process $proc$ls180.v:793$3078
131936     assign { } { }
131937     assign $1\main_sdram_en0[0:0] 1'0
131938     sync always
131939     sync init
131940       update \main_sdram_en0 $1\main_sdram_en0[0:0]
131941   end
131942   attribute \src "ls180.v:795.11-795.34"
131943   process $proc$ls180.v:795$3079
131944     assign { } { }
131945     assign $1\main_sdram_time0[4:0] 5'00000
131946     sync always
131947     sync init
131948       update \main_sdram_time0 $1\main_sdram_time0[4:0]
131949   end
131950   attribute \src "ls180.v:796.5-796.26"
131951   process $proc$ls180.v:796$3080
131952     assign { } { }
131953     assign $1\main_sdram_en1[0:0] 1'0
131954     sync always
131955     sync init
131956       update \main_sdram_en1 $1\main_sdram_en1[0:0]
131957   end
131958   attribute \src "ls180.v:798.11-798.34"
131959   process $proc$ls180.v:798$3081
131960     assign { } { }
131961     assign $1\main_sdram_time1[3:0] 4'0000
131962     sync always
131963     sync init
131964       update \main_sdram_time1 $1\main_sdram_time1[3:0]
131965   end
131966   attribute \src "ls180.v:819.5-819.29"
131967   process $proc$ls180.v:819$3082
131968     assign { } { }
131969     assign $1\main_wb_sdram_ack[0:0] 1'0
131970     sync always
131971     sync init
131972       update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0]
131973   end
131974   attribute \src "ls180.v:823.5-823.29"
131975   process $proc$ls180.v:823$3083
131976     assign { } { }
131977     assign $0\main_wb_sdram_err[0:0] 1'0
131978     sync always
131979       update \main_wb_sdram_err $0\main_wb_sdram_err[0:0]
131980     sync init
131981   end
131982   attribute \src "ls180.v:824.12-824.40"
131983   process $proc$ls180.v:824$3084
131984     assign { } { }
131985     assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
131986     sync always
131987     sync init
131988       update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0]
131989   end
131990   attribute \src "ls180.v:825.12-825.42"
131991   process $proc$ls180.v:825$3085
131992     assign { } { }
131993     assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000
131994     sync always
131995     sync init
131996       update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0]
131997   end
131998   attribute \src "ls180.v:827.11-827.38"
131999   process $proc$ls180.v:827$3086
132000     assign { } { }
132001     assign $1\main_litedram_wb_sel[1:0] 2'00
132002     sync always
132003     sync init
132004       update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0]
132005   end
132006   attribute \src "ls180.v:828.5-828.32"
132007   process $proc$ls180.v:828$3087
132008     assign { } { }
132009     assign $1\main_litedram_wb_cyc[0:0] 1'0
132010     sync always
132011     sync init
132012       update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0]
132013   end
132014   attribute \src "ls180.v:829.5-829.32"
132015   process $proc$ls180.v:829$3088
132016     assign { } { }
132017     assign $1\main_litedram_wb_stb[0:0] 1'0
132018     sync always
132019     sync init
132020       update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0]
132021   end
132022   attribute \src "ls180.v:83.5-83.46"
132023   process $proc$ls180.v:83$2783
132024     assign { } { }
132025     assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0
132026     sync always
132027     sync init
132028       update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
132029   end
132030   attribute \src "ls180.v:831.5-831.31"
132031   process $proc$ls180.v:831$3089
132032     assign { } { }
132033     assign $1\main_litedram_wb_we[0:0] 1'0
132034     sync always
132035     sync init
132036       update \main_litedram_wb_we $1\main_litedram_wb_we[0:0]
132037   end
132038   attribute \src "ls180.v:832.5-832.31"
132039   process $proc$ls180.v:832$3090
132040     assign { } { }
132041     assign $1\main_converter_skip[0:0] 1'0
132042     sync always
132043     sync init
132044       update \main_converter_skip $1\main_converter_skip[0:0]
132045   end
132046   attribute \src "ls180.v:833.5-833.34"
132047   process $proc$ls180.v:833$3091
132048     assign { } { }
132049     assign $1\main_converter_counter[0:0] 1'0
132050     sync always
132051     sync init
132052       update \main_converter_counter $1\main_converter_counter[0:0]
132053   end
132054   attribute \src "ls180.v:835.12-835.40"
132055   process $proc$ls180.v:835$3092
132056     assign { } { }
132057     assign $1\main_converter_dat_r[31:0] 0
132058     sync always
132059     sync init
132060       update \main_converter_dat_r $1\main_converter_dat_r[31:0]
132061   end
132062   attribute \src "ls180.v:836.5-836.29"
132063   process $proc$ls180.v:836$3093
132064     assign { } { }
132065     assign $1\main_cmd_consumed[0:0] 1'0
132066     sync always
132067     sync init
132068       update \main_cmd_consumed $1\main_cmd_consumed[0:0]
132069   end
132070   attribute \src "ls180.v:837.5-837.31"
132071   process $proc$ls180.v:837$3094
132072     assign { } { }
132073     assign $1\main_wdata_consumed[0:0] 1'0
132074     sync always
132075     sync init
132076       update \main_wdata_consumed $1\main_wdata_consumed[0:0]
132077   end
132078   attribute \src "ls180.v:841.12-841.47"
132079   process $proc$ls180.v:841$3095
132080     assign { } { }
132081     assign $1\main_uart_phy_storage[31:0] 9895604
132082     sync always
132083     sync init
132084       update \main_uart_phy_storage $1\main_uart_phy_storage[31:0]
132085   end
132086   attribute \src "ls180.v:842.5-842.28"
132087   process $proc$ls180.v:842$3096
132088     assign { } { }
132089     assign $1\main_uart_phy_re[0:0] 1'0
132090     sync always
132091     sync init
132092       update \main_uart_phy_re $1\main_uart_phy_re[0:0]
132093   end
132094   attribute \src "ls180.v:844.5-844.36"
132095   process $proc$ls180.v:844$3097
132096     assign { } { }
132097     assign $1\main_uart_phy_sink_ready[0:0] 1'0
132098     sync always
132099     sync init
132100       update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0]
132101   end
132102   attribute \src "ls180.v:848.5-848.39"
132103   process $proc$ls180.v:848$3098
132104     assign { } { }
132105     assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0
132106     sync always
132107     sync init
132108       update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0]
132109   end
132110   attribute \src "ls180.v:849.12-849.54"
132111   process $proc$ls180.v:849$3099
132112     assign { } { }
132113     assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0
132114     sync always
132115     sync init
132116       update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0]
132117   end
132118   attribute \src "ls180.v:850.11-850.38"
132119   process $proc$ls180.v:850$3100
132120     assign { } { }
132121     assign $1\main_uart_phy_tx_reg[7:0] 8'00000000
132122     sync always
132123     sync init
132124       update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0]
132125   end
132126   attribute \src "ls180.v:851.11-851.43"
132127   process $proc$ls180.v:851$3101
132128     assign { } { }
132129     assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000
132130     sync always
132131     sync init
132132       update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0]
132133   end
132134   attribute \src "ls180.v:852.5-852.33"
132135   process $proc$ls180.v:852$3102
132136     assign { } { }
132137     assign $1\main_uart_phy_tx_busy[0:0] 1'0
132138     sync always
132139     sync init
132140       update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0]
132141   end
132142   attribute \src "ls180.v:853.5-853.38"
132143   process $proc$ls180.v:853$3103
132144     assign { } { }
132145     assign $1\main_uart_phy_source_valid[0:0] 1'0
132146     sync always
132147     sync init
132148       update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0]
132149   end
132150   attribute \src "ls180.v:855.5-855.38"
132151   process $proc$ls180.v:855$3104
132152     assign { } { }
132153     assign $0\main_uart_phy_source_first[0:0] 1'0
132154     sync always
132155       update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0]
132156     sync init
132157   end
132158   attribute \src "ls180.v:856.5-856.37"
132159   process $proc$ls180.v:856$3105
132160     assign { } { }
132161     assign $0\main_uart_phy_source_last[0:0] 1'0
132162     sync always
132163       update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0]
132164     sync init
132165   end
132166   attribute \src "ls180.v:857.11-857.51"
132167   process $proc$ls180.v:857$3106
132168     assign { } { }
132169     assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000
132170     sync always
132171     sync init
132172       update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0]
132173   end
132174   attribute \src "ls180.v:858.5-858.39"
132175   process $proc$ls180.v:858$3107
132176     assign { } { }
132177     assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0
132178     sync always
132179     sync init
132180       update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0]
132181   end
132182   attribute \src "ls180.v:859.12-859.54"
132183   process $proc$ls180.v:859$3108
132184     assign { } { }
132185     assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0
132186     sync always
132187     sync init
132188       update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0]
132189   end
132190   attribute \src "ls180.v:861.5-861.30"
132191   process $proc$ls180.v:861$3109
132192     assign { } { }
132193     assign $1\main_uart_phy_rx_r[0:0] 1'0
132194     sync always
132195     sync init
132196       update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0]
132197   end
132198   attribute \src "ls180.v:862.11-862.38"
132199   process $proc$ls180.v:862$3110
132200     assign { } { }
132201     assign $1\main_uart_phy_rx_reg[7:0] 8'00000000
132202     sync always
132203     sync init
132204       update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0]
132205   end
132206   attribute \src "ls180.v:863.11-863.43"
132207   process $proc$ls180.v:863$3111
132208     assign { } { }
132209     assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000
132210     sync always
132211     sync init
132212       update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0]
132213   end
132214   attribute \src "ls180.v:864.5-864.33"
132215   process $proc$ls180.v:864$3112
132216     assign { } { }
132217     assign $1\main_uart_phy_rx_busy[0:0] 1'0
132218     sync always
132219     sync init
132220       update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0]
132221   end
132222   attribute \src "ls180.v:87.5-87.46"
132223   process $proc$ls180.v:87$2784
132224     assign { } { }
132225     assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0
132226     sync always
132227       update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0]
132228     sync init
132229   end
132230   attribute \src "ls180.v:875.5-875.32"
132231   process $proc$ls180.v:875$3113
132232     assign { } { }
132233     assign $1\main_uart_tx_pending[0:0] 1'0
132234     sync always
132235     sync init
132236       update \main_uart_tx_pending $1\main_uart_tx_pending[0:0]
132237   end
132238   attribute \src "ls180.v:877.5-877.30"
132239   process $proc$ls180.v:877$3114
132240     assign { } { }
132241     assign $1\main_uart_tx_clear[0:0] 1'0
132242     sync always
132243     sync init
132244       update \main_uart_tx_clear $1\main_uart_tx_clear[0:0]
132245   end
132246   attribute \src "ls180.v:878.5-878.36"
132247   process $proc$ls180.v:878$3115
132248     assign { } { }
132249     assign $1\main_uart_tx_old_trigger[0:0] 1'0
132250     sync always
132251     sync init
132252       update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0]
132253   end
132254   attribute \src "ls180.v:880.5-880.32"
132255   process $proc$ls180.v:880$3116
132256     assign { } { }
132257     assign $1\main_uart_rx_pending[0:0] 1'0
132258     sync always
132259     sync init
132260       update \main_uart_rx_pending $1\main_uart_rx_pending[0:0]
132261   end
132262   attribute \src "ls180.v:882.5-882.30"
132263   process $proc$ls180.v:882$3117
132264     assign { } { }
132265     assign $1\main_uart_rx_clear[0:0] 1'0
132266     sync always
132267     sync init
132268       update \main_uart_rx_clear $1\main_uart_rx_clear[0:0]
132269   end
132270   attribute \src "ls180.v:883.5-883.36"
132271   process $proc$ls180.v:883$3118
132272     assign { } { }
132273     assign $1\main_uart_rx_old_trigger[0:0] 1'0
132274     sync always
132275     sync init
132276       update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0]
132277   end
132278   attribute \src "ls180.v:887.11-887.49"
132279   process $proc$ls180.v:887$3119
132280     assign { } { }
132281     assign $1\main_uart_eventmanager_status_w[1:0] 2'00
132282     sync always
132283     sync init
132284       update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0]
132285   end
132286   attribute \src "ls180.v:891.11-891.50"
132287   process $proc$ls180.v:891$3120
132288     assign { } { }
132289     assign $1\main_uart_eventmanager_pending_w[1:0] 2'00
132290     sync always
132291     sync init
132292       update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0]
132293   end
132294   attribute \src "ls180.v:892.11-892.48"
132295   process $proc$ls180.v:892$3121
132296     assign { } { }
132297     assign $1\main_uart_eventmanager_storage[1:0] 2'00
132298     sync always
132299     sync init
132300       update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0]
132301   end
132302   attribute \src "ls180.v:893.5-893.37"
132303   process $proc$ls180.v:893$3122
132304     assign { } { }
132305     assign $1\main_uart_eventmanager_re[0:0] 1'0
132306     sync always
132307     sync init
132308       update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0]
132309   end
132310   attribute \src "ls180.v:910.5-910.40"
132311   process $proc$ls180.v:910$3123
132312     assign { } { }
132313     assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0
132314     sync always
132315       update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0]
132316     sync init
132317   end
132318   attribute \src "ls180.v:911.5-911.39"
132319   process $proc$ls180.v:911$3124
132320     assign { } { }
132321     assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0
132322     sync always
132323       update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0]
132324     sync init
132325   end
132326   attribute \src "ls180.v:919.5-919.38"
132327   process $proc$ls180.v:919$3125
132328     assign { } { }
132329     assign $1\main_uart_tx_fifo_readable[0:0] 1'0
132330     sync always
132331     sync init
132332       update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0]
132333   end
132334   attribute \src "ls180.v:926.11-926.42"
132335   process $proc$ls180.v:926$3126
132336     assign { } { }
132337     assign $1\main_uart_tx_fifo_level0[4:0] 5'00000
132338     sync always
132339     sync init
132340       update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0]
132341   end
132342   attribute \src "ls180.v:927.5-927.37"
132343   process $proc$ls180.v:927$3127
132344     assign { } { }
132345     assign $0\main_uart_tx_fifo_replace[0:0] 1'0
132346     sync always
132347       update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0]
132348     sync init
132349   end
132350   attribute \src "ls180.v:928.11-928.43"
132351   process $proc$ls180.v:928$3128
132352     assign { } { }
132353     assign $1\main_uart_tx_fifo_produce[3:0] 4'0000
132354     sync always
132355     sync init
132356       update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0]
132357   end
132358   attribute \src "ls180.v:929.11-929.43"
132359   process $proc$ls180.v:929$3129
132360     assign { } { }
132361     assign $1\main_uart_tx_fifo_consume[3:0] 4'0000
132362     sync always
132363     sync init
132364       update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0]
132365   end
132366   attribute \src "ls180.v:930.11-930.46"
132367   process $proc$ls180.v:930$3130
132368     assign { } { }
132369     assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
132370     sync always
132371     sync init
132372       update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0]
132373   end
132374   attribute \src "ls180.v:956.5-956.38"
132375   process $proc$ls180.v:956$3131
132376     assign { } { }
132377     assign $1\main_uart_rx_fifo_readable[0:0] 1'0
132378     sync always
132379     sync init
132380       update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0]
132381   end
132382   attribute \src "ls180.v:963.11-963.42"
132383   process $proc$ls180.v:963$3132
132384     assign { } { }
132385     assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
132386     sync always
132387     sync init
132388       update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
132389   end
132390   attribute \src "ls180.v:964.5-964.37"
132391   process $proc$ls180.v:964$3133
132392     assign { } { }
132393     assign $0\main_uart_rx_fifo_replace[0:0] 1'0
132394     sync always
132395       update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0]
132396     sync init
132397   end
132398   attribute \src "ls180.v:965.11-965.43"
132399   process $proc$ls180.v:965$3134
132400     assign { } { }
132401     assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
132402     sync always
132403     sync init
132404       update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
132405   end
132406   attribute \src "ls180.v:966.11-966.43"
132407   process $proc$ls180.v:966$3135
132408     assign { } { }
132409     assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
132410     sync always
132411     sync init
132412       update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
132413   end
132414   attribute \src "ls180.v:967.11-967.46"
132415   process $proc$ls180.v:967$3136
132416     assign { } { }
132417     assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
132418     sync always
132419     sync init
132420       update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
132421   end
132422   attribute \src "ls180.v:982.5-982.27"
132423   process $proc$ls180.v:982$3137
132424     assign { } { }
132425     assign $0\main_uart_reset[0:0] 1'0
132426     sync always
132427       update \main_uart_reset $0\main_uart_reset[0:0]
132428     sync init
132429   end
132430   attribute \src "ls180.v:983.12-983.40"
132431   process $proc$ls180.v:983$3138
132432     assign { } { }
132433     assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000
132434     sync always
132435     sync init
132436       update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0]
132437   end
132438   attribute \src "ls180.v:984.5-984.27"
132439   process $proc$ls180.v:984$3139
132440     assign { } { }
132441     assign $1\main_gpio_oe_re[0:0] 1'0
132442     sync always
132443     sync init
132444       update \main_gpio_oe_re $1\main_gpio_oe_re[0:0]
132445   end
132446   attribute \src "ls180.v:985.12-985.36"
132447   process $proc$ls180.v:985$3140
132448     assign { } { }
132449     assign $1\main_gpio_status[15:0] 16'0000000000000000
132450     sync always
132451     sync init
132452       update \main_gpio_status $1\main_gpio_status[15:0]
132453   end
132454   attribute \src "ls180.v:987.12-987.41"
132455   process $proc$ls180.v:987$3141
132456     assign { } { }
132457     assign $1\main_gpio_out_storage[15:0] 16'0000000000000000
132458     sync always
132459     sync init
132460       update \main_gpio_out_storage $1\main_gpio_out_storage[15:0]
132461   end
132462   attribute \src "ls180.v:988.5-988.28"
132463   process $proc$ls180.v:988$3142
132464     assign { } { }
132465     assign $1\main_gpio_out_re[0:0] 1'0
132466     sync always
132467     sync init
132468       update \main_gpio_out_re $1\main_gpio_out_re[0:0]
132469   end
132470   attribute \src "ls180.v:994.5-994.32"
132471   process $proc$ls180.v:994$3143
132472     assign { } { }
132473     assign $1\main_spimaster2_done[0:0] 1'0
132474     sync always
132475     sync init
132476       update \main_spimaster2_done $1\main_spimaster2_done[0:0]
132477   end
132478   attribute \src "ls180.v:995.5-995.31"
132479   process $proc$ls180.v:995$3144
132480     assign { } { }
132481     assign $1\main_spimaster3_irq[0:0] 1'0
132482     sync always
132483     sync init
132484       update \main_spimaster3_irq $1\main_spimaster3_irq[0:0]
132485   end
132486   attribute \src "ls180.v:997.11-997.38"
132487   process $proc$ls180.v:997$3145
132488     assign { } { }
132489     assign $1\main_spimaster5_miso[7:0] 8'00000000
132490     sync always
132491     sync init
132492       update \main_spimaster5_miso $1\main_spimaster5_miso[7:0]
132493   end
132494   connect \main_libresocsim_libresoc_reset \main_libresocsim_reset
132495   connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i
132496   connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o
132497   connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o
132498   connect \main_libresocsim_libresoc_jtag_tck \jtag_tck
132499   connect \main_libresocsim_libresoc_jtag_tms \jtag_tms
132500   connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi
132501   connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo
132502   connect \main_nc \nc
132503   connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid
132504   connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0
132505   connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first
132506   connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last
132507   connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data
132508   connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0
132509   connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready
132510   connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0
132511   connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0
132512   connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0
132513   connect \main_libresocsim_bus_error \builder_error
132514   connect \main_libresocsim_converter0_reset $not$ls180.v:2777$14_Y
132515   connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] }
132516   connect \main_libresocsim_converter1_reset $not$ls180.v:2837$25_Y
132517   connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] }
132518   connect \main_libresocsim_converter2_reset $not$ls180.v:2897$36_Y
132519   connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] }
132520   connect \main_libresocsim_reset \main_libresocsim_reset_re
132521   connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors
132522   connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0]
132523   connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r
132524   connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w
132525   connect \main_libresocsim_zero_trigger $ne$ls180.v:2969$60_Y
132526   connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status
132527   connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending
132528   connect \main_libresocsim_irq $and$ls180.v:2978$63_Y
132529   connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger
132530   connect \sys_clk_1 \sys_clk
132531   connect \por_clk \sys_clk
132532   connect \sys_rst_1 \main_int_rst
132533   connect \main_dfi_p0_address \main_sdram_master_p0_address
132534   connect \main_dfi_p0_bank \main_sdram_master_p0_bank
132535   connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n
132536   connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n
132537   connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n
132538   connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n
132539   connect \main_dfi_p0_cke \main_sdram_master_p0_cke
132540   connect \main_dfi_p0_odt \main_sdram_master_p0_odt
132541   connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n
132542   connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n
132543   connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata
132544   connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en
132545   connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask
132546   connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en
132547   connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata
132548   connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid
132549   connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address
132550   connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank
132551   connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n
132552   connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n
132553   connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n
132554   connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n
132555   connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke
132556   connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt
132557   connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n
132558   connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n
132559   connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata
132560   connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en
132561   connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask
132562   connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en
132563   connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata
132564   connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid
132565   connect \main_sdram_inti_p0_cke \main_sdram_cke
132566   connect \main_sdram_inti_p0_odt \main_sdram_odt
132567   connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n
132568   connect \main_sdram_inti_p0_address \main_sdram_address_storage
132569   connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage
132570   connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3092$70_Y
132571   connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3093$71_Y
132572   connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage
132573   connect \main_sdram_inti_p0_wrdata_mask 2'00
132574   connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid
132575   connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready
132576   connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we
132577   connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr
132578   connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock
132579   connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready
132580   connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid
132581   connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid
132582   connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready
132583   connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we
132584   connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr
132585   connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock
132586   connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready
132587   connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid
132588   connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid
132589   connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready
132590   connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we
132591   connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr
132592   connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock
132593   connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready
132594   connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid
132595   connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid
132596   connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready
132597   connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we
132598   connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr
132599   connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock
132600   connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready
132601   connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid
132602   connect \main_sdram_timer_wait $not$ls180.v:3124$72_Y
132603   connect \main_sdram_postponer_req_i \main_sdram_timer_done0
132604   connect \main_sdram_wants_refresh \main_sdram_postponer_req_o
132605   connect \main_sdram_timer_done1 $eq$ls180.v:3127$73_Y
132606   connect \main_sdram_timer_done0 \main_sdram_timer_done1
132607   connect \main_sdram_timer_count0 \main_sdram_timer_count1
132608   connect \main_sdram_sequencer_start1 $or$ls180.v:3130$75_Y
132609   connect \main_sdram_sequencer_done0 $and$ls180.v:3131$77_Y
132610   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid
132611   connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
132612   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we
132613   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr
132614   connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid
132615   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready
132616   connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first
132617   connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last
132618   connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
132619   connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
132620   connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3173$79_Y
132621   connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3174$80_Y
132622   connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3175$81_Y
132623   connect \main_sdram_bankmachine0_cmd_payload_ba 2'00
132624   connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3185$86_Y
132625   connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3186$88_Y
132626   connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3187$90_Y
132627   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we }
132628   connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
132629   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
132630   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid
132631   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first
132632   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last
132633   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we
132634   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr
132635   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
132636   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first
132637   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last
132638   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we
132639   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
132640   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready
132641   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
132642   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3219$98_Y
132643   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3220$99_Y
132644   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume
132645   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
132646   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3223$100_Y
132647   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3224$101_Y
132648   connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3225$103_Y
132649   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid
132650   connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
132651   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we
132652   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr
132653   connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid
132654   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready
132655   connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first
132656   connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last
132657   connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
132658   connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
132659   connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3330$109_Y
132660   connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3331$110_Y
132661   connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3332$111_Y
132662   connect \main_sdram_bankmachine1_cmd_payload_ba 2'01
132663   connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3342$116_Y
132664   connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3343$118_Y
132665   connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3344$120_Y
132666   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we }
132667   connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
132668   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
132669   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid
132670   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first
132671   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last
132672   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we
132673   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr
132674   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
132675   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first
132676   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last
132677   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we
132678   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
132679   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready
132680   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
132681   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3376$128_Y
132682   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3377$129_Y
132683   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume
132684   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
132685   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3380$130_Y
132686   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3381$131_Y
132687   connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3382$133_Y
132688   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid
132689   connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
132690   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we
132691   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr
132692   connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid
132693   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready
132694   connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first
132695   connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last
132696   connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
132697   connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
132698   connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3487$139_Y
132699   connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3488$140_Y
132700   connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3489$141_Y
132701   connect \main_sdram_bankmachine2_cmd_payload_ba 2'10
132702   connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3499$146_Y
132703   connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3500$148_Y
132704   connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3501$150_Y
132705   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we }
132706   connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
132707   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
132708   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid
132709   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first
132710   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last
132711   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we
132712   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr
132713   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
132714   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first
132715   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last
132716   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we
132717   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
132718   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready
132719   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
132720   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3533$158_Y
132721   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3534$159_Y
132722   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume
132723   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
132724   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3537$160_Y
132725   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3538$161_Y
132726   connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3539$163_Y
132727   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid
132728   connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
132729   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we
132730   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr
132731   connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid
132732   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready
132733   connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first
132734   connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last
132735   connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
132736   connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
132737   connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3644$169_Y
132738   connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3645$170_Y
132739   connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3646$171_Y
132740   connect \main_sdram_bankmachine3_cmd_payload_ba 2'11
132741   connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3656$176_Y
132742   connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3657$178_Y
132743   connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3658$180_Y
132744   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we }
132745   connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
132746   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
132747   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid
132748   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first
132749   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last
132750   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we
132751   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr
132752   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
132753   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first
132754   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last
132755   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we
132756   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
132757   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready
132758   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
132759   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3690$188_Y
132760   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3691$189_Y
132761   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume
132762   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
132763   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3694$190_Y
132764   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3695$191_Y
132765   connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3696$193_Y
132766   connect \main_sdram_choose_req_want_cmds 1'1
132767   connect \main_sdram_trrdcon_valid $and$ls180.v:3792$204_Y
132768   connect \main_sdram_tfawcon_valid $and$ls180.v:3793$210_Y
132769   connect \main_sdram_ras_allowed $and$ls180.v:3794$211_Y
132770   connect \main_sdram_tccdcon_valid $and$ls180.v:3795$214_Y
132771   connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready
132772   connect \main_sdram_twtrcon_valid $and$ls180.v:3797$216_Y
132773   connect \main_sdram_read_available $or$ls180.v:3798$223_Y
132774   connect \main_sdram_write_available $or$ls180.v:3799$230_Y
132775   connect \main_sdram_max_time0 $eq$ls180.v:3800$231_Y
132776   connect \main_sdram_max_time1 $eq$ls180.v:3801$232_Y
132777   connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid
132778   connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid
132779   connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid
132780   connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid
132781   connect \main_sdram_go_to_refresh $and$ls180.v:3806$235_Y
132782   connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata
132783   connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata
132784   connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3809$236_Y
132785   connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids
132786   connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0
132787   connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1
132788   connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2
132789   connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3
132790   connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4
132791   connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5
132792   connect \main_sdram_choose_cmd_ce $or$ls180.v:3842$294_Y
132793   connect \main_sdram_choose_req_request \main_sdram_choose_req_valids
132794   connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6
132795   connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7
132796   connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8
132797   connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9
132798   connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10
132799   connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11
132800   connect \main_sdram_choose_req_ce $or$ls180.v:3911$380_Y
132801   connect \main_sdram_dfi_p0_reset_n 1'1
132802   connect \main_sdram_dfi_p0_cke \main_sdram_steerer0
132803   connect \main_sdram_dfi_p0_odt \main_sdram_steerer1
132804   connect \builder_roundrobin0_request $and$ls180.v:3988$412_Y
132805   connect \builder_roundrobin0_ce $and$ls180.v:3989$415_Y
132806   connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12
132807   connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13
132808   connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14
132809   connect \builder_roundrobin1_request $and$ls180.v:3993$428_Y
132810   connect \builder_roundrobin1_ce $and$ls180.v:3994$431_Y
132811   connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15
132812   connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16
132813   connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17
132814   connect \builder_roundrobin2_request $and$ls180.v:3998$444_Y
132815   connect \builder_roundrobin2_ce $and$ls180.v:3999$447_Y
132816   connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18
132817   connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19
132818   connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20
132819   connect \builder_roundrobin3_request $and$ls180.v:4003$460_Y
132820   connect \builder_roundrobin3_ce $and$ls180.v:4004$463_Y
132821   connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21
132822   connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22
132823   connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23
132824   connect \main_port_cmd_ready $or$ls180.v:4008$527_Y
132825   connect \main_port_wdata_ready \builder_new_master_wdata_ready
132826   connect \main_port_rdata_valid \builder_new_master_rdata_valid3
132827   connect \main_port_rdata_payload_data \main_sdram_interface_rdata
132828   connect \builder_roundrobin0_grant 1'0
132829   connect \builder_roundrobin1_grant 1'0
132830   connect \builder_roundrobin2_grant 1'0
132831   connect \builder_roundrobin3_grant 1'0
132832   connect \main_converter_reset $not$ls180.v:4030$529_Y
132833   connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] }
132834   connect \main_port_cmd_payload_addr $sub$ls180.v:4090$540_Y [23:0]
132835   connect \main_port_cmd_payload_we \main_litedram_wb_we
132836   connect \main_port_wdata_payload_data \main_litedram_wb_dat_w
132837   connect \main_port_wdata_payload_we \main_litedram_wb_sel
132838   connect \main_litedram_wb_dat_r \main_port_rdata_payload_data
132839   connect \main_port_flush $not$ls180.v:4095$541_Y
132840   connect \main_port_cmd_last $not$ls180.v:4096$542_Y
132841   connect \main_port_cmd_valid $and$ls180.v:4097$545_Y
132842   connect \main_port_wdata_valid $and$ls180.v:4098$549_Y
132843   connect \main_port_rdata_ready $and$ls180.v:4099$552_Y
132844   connect \main_litedram_wb_ack $and$ls180.v:4100$557_Y
132845   connect \main_ack_cmd $or$ls180.v:4101$559_Y
132846   connect \main_ack_wdata $or$ls180.v:4102$561_Y
132847   connect \main_ack_rdata $and$ls180.v:4103$562_Y
132848   connect \main_uart_uart_sink_valid \main_uart_phy_source_valid
132849   connect \main_uart_phy_source_ready \main_uart_uart_sink_ready
132850   connect \main_uart_uart_sink_first \main_uart_phy_source_first
132851   connect \main_uart_uart_sink_last \main_uart_phy_source_last
132852   connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data
132853   connect \main_uart_phy_sink_valid \main_uart_uart_source_valid
132854   connect \main_uart_uart_source_ready \main_uart_phy_sink_ready
132855   connect \main_uart_phy_sink_first \main_uart_uart_source_first
132856   connect \main_uart_phy_sink_last \main_uart_uart_source_last
132857   connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data
132858   connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re
132859   connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r
132860   connect \main_uart_txfull_status $not$ls180.v:4116$563_Y
132861   connect \main_uart_txempty_status $not$ls180.v:4117$564_Y
132862   connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid
132863   connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready
132864   connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first
132865   connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last
132866   connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data
132867   connect \main_uart_tx_trigger $not$ls180.v:4123$565_Y
132868   connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid
132869   connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready
132870   connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first
132871   connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last
132872   connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data
132873   connect \main_uart_rxempty_status $not$ls180.v:4129$566_Y
132874   connect \main_uart_rxfull_status $not$ls180.v:4130$567_Y
132875   connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data
132876   connect \main_uart_rx_fifo_source_ready $or$ls180.v:4132$569_Y
132877   connect \main_uart_rx_trigger $not$ls180.v:4133$570_Y
132878   connect \main_uart_irq $or$ls180.v:4156$579_Y
132879   connect \main_uart_tx_status \main_uart_tx_trigger
132880   connect \main_uart_rx_status \main_uart_rx_trigger
132881   connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data }
132882   connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout
132883   connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable
132884   connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid
132885   connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first
132886   connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last
132887   connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data
132888   connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable
132889   connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first
132890   connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last
132891   connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data
132892   connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready
132893   connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4171$582_Y
132894   connect \main_uart_tx_fifo_level1 $add$ls180.v:4172$583_Y
132895   connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din
132896   connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4182$587_Y
132897   connect \main_uart_tx_fifo_do_read $and$ls180.v:4183$588_Y
132898   connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume
132899   connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r
132900   connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read
132901   connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4187$589_Y
132902   connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4188$590_Y
132903   connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data }
132904   connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout
132905   connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable
132906   connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid
132907   connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first
132908   connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last
132909   connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data
132910   connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable
132911   connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first
132912   connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last
132913   connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data
132914   connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready
132915   connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4201$593_Y
132916   connect \main_uart_rx_fifo_level1 $add$ls180.v:4202$594_Y
132917   connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din
132918   connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4212$598_Y
132919   connect \main_uart_rx_fifo_do_read $and$ls180.v:4213$599_Y
132920   connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume
132921   connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r
132922   connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read
132923   connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4217$600_Y
132924   connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4218$601_Y
132925   connect \main_gpio_pads_i \gpio_i
132926   connect \gpio_o \main_gpio_pads_o
132927   connect \gpio_oe \main_gpio_pads_oe
132928   connect \main_gpio_pads_oe \main_gpio_oe_storage
132929   connect \main_gpio_pads_o \main_gpio_out_storage
132930   connect \main_spimaster0_start \main_spimaster9_start
132931   connect \main_spimaster1_length \main_spimaster10_length
132932   connect \main_spimaster4_mosi \main_spimaster16_storage
132933   connect \main_spimaster13_done \main_spimaster2_done
132934   connect \main_spimaster18_status \main_spimaster5_miso
132935   connect \main_spimaster6_cs \main_spimaster21_storage
132936   connect \main_spimaster7_loopback \main_spimaster23_storage
132937   connect \main_spimaster31_clk_rise $eq$ls180.v:4231$603_Y
132938   connect \main_spimaster32_clk_fall $eq$ls180.v:4232$605_Y
132939   connect \main_spisdcard_start0 \main_spisdcard_start1
132940   connect \main_spisdcard_length0 \main_spisdcard_length1
132941   connect \main_spisdcard_mosi \main_spisdcard_mosi_storage
132942   connect \main_spisdcard_done1 \main_spisdcard_done0
132943   connect \main_spisdcard_miso_status \main_spisdcard_miso
132944   connect \main_spisdcard_cs \main_spisdcard_cs_storage
132945   connect \main_spisdcard_loopback \main_spisdcard_loopback_storage
132946   connect \main_spisdcard_clk_rise $eq$ls180.v:4289$611_Y
132947   connect \main_spisdcard_clk_fall $eq$ls180.v:4290$613_Y
132948   connect \main_spisdcard_clk_divider0 \main_spimaster1_storage
132949   connect \i2c_scl \main_i2c_scl
132950   connect \i2c_sda_oe \main_i2c_oe
132951   connect \i2c_sda_o \main_i2c_sda0
132952   connect \main_i2c_sda1 \i2c_sda_i
132953   connect \main_sdphy_status 1'0
132954   connect \main_sdphy_sdpads_clk $or$ls180.v:4346$621_Y
132955   connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4347$625_Y
132956   connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4348$629_Y
132957   connect \main_sdphy_sdpads_data_oe $or$ls180.v:4349$633_Y
132958   connect \main_sdphy_sdpads_data_o $or$ls180.v:4350$637_Y
132959   connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce
132960   connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce
132961   connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce
132962   connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce
132963   connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce
132964   connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce
132965   connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
132966   connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i
132967   connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce
132968   connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
132969   connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i
132970   connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce
132971   connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
132972   connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i
132973   connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce
132974   connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
132975   connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i
132976   connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce
132977   connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i
132978   connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i
132979   connect \main_sdphy_clocker_stop $or$ls180.v:4371$638_Y
132980   connect \main_sdphy_clocker_ce $and$ls180.v:4401$641_Y
132981   connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid
132982   connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready
132983   connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first
132984   connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last
132985   connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk
132986   connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i
132987   connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o
132988   connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe
132989   connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i
132990   connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o
132991   connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe
132992   connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4524$651_Y
132993   connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4525$653_Y
132994   connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i
132995   connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1
132996   connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready
132997   connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1
132998   connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1
132999   connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1
133000   connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid
133001   connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0
133002   connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first
133003   connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last
133004   connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data
133005   connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid
133006   connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1
133007   connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first
133008   connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last
133009   connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data
133010   connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4542$655_Y
133011   connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all
133012   connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4544$656_Y
133013   connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4545$658_Y
133014   connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid
133015   connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready
133016   connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first
133017   connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last
133018   connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk
133019   connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i
133020   connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o
133021   connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe
133022   connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i
133023   connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o
133024   connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe
133025   connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4651$673_Y
133026   connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4652$674_Y
133027   connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0]
133028   connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1
133029   connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready
133030   connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1
133031   connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1
133032   connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1
133033   connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid
133034   connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0
133035   connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first
133036   connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last
133037   connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data
133038   connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid
133039   connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1
133040   connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first
133041   connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last
133042   connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data
133043   connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4669$676_Y
133044   connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all
133045   connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4671$677_Y
133046   connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4672$679_Y
133047   connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid
133048   connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready
133049   connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first
133050   connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last
133051   connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk
133052   connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i
133053   connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o
133054   connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe
133055   connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i
133056   connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o
133057   connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe
133058   connect \main_sdphy_datar_datar_start $eq$ls180.v:4785$688_Y
133059   connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4786$689_Y
133060   connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i
133061   connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1
133062   connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready
133063   connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1
133064   connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1
133065   connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1
133066   connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid
133067   connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0
133068   connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first
133069   connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last
133070   connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data
133071   connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid
133072   connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1
133073   connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first
133074   connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last
133075   connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data
133076   connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4803$691_Y
133077   connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all
133078   connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4805$692_Y
133079   connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4806$694_Y
133080   connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid
133081   connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready
133082   connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first
133083   connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last
133084   connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data
133085   connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid
133086   connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready
133087   connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first
133088   connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last
133089   connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data
133090   connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0]
133091   connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5]
133092   connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done }
133093   connect \main_sdcore_data_event_status { $not$ls180.v:4922$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done }
133094   connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage }
133095   connect \main_sdcore_crc7_inserter_clr 1'1
133096   connect \main_sdcore_crc7_inserter_enable 1'1
133097   connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4926$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4926$710_Y }
133098   connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4927$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4927$713_Y }
133099   connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4928$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4928$716_Y }
133100   connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4929$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4929$719_Y }
133101   connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4930$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4930$722_Y }
133102   connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4931$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4931$725_Y }
133103   connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4932$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4932$728_Y }
133104   connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4933$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4933$731_Y }
133105   connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4934$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4934$734_Y }
133106   connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4935$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4935$737_Y }
133107   connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4936$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4936$740_Y }
133108   connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4937$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4937$743_Y }
133109   connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4938$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4938$746_Y }
133110   connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4939$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4939$749_Y }
133111   connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4940$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4940$752_Y }
133112   connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4941$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4941$755_Y }
133113   connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4942$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4942$758_Y }
133114   connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4943$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4943$761_Y }
133115   connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4944$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4944$764_Y }
133116   connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4945$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4945$767_Y }
133117   connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4946$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4946$770_Y }
133118   connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4947$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4947$773_Y }
133119   connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4948$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4948$776_Y }
133120   connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4949$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4949$779_Y }
133121   connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4950$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4950$782_Y }
133122   connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4951$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4951$785_Y }
133123   connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4952$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4952$788_Y }
133124   connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4953$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4953$791_Y }
133125   connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4954$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4954$794_Y }
133126   connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4955$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4955$797_Y }
133127   connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4956$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4956$800_Y }
133128   connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4957$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4957$803_Y }
133129   connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4958$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4958$806_Y }
133130   connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4959$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4959$809_Y }
133131   connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4960$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4960$812_Y }
133132   connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4961$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4961$815_Y }
133133   connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4962$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4962$818_Y }
133134   connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4963$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4963$821_Y }
133135   connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4964$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4964$824_Y }
133136   connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4965$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4965$827_Y }
133137   connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] }
133138   connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4975$832_Y
133139   connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4976$833_Y
133140   connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] }
133141   connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4978$835_Y
133142   connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4979$836_Y
133143   connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] }
133144   connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4981$838_Y
133145   connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4982$839_Y
133146   connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] }
133147   connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4984$841_Y
133148   connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4985$842_Y
133149   connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4986$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4986$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4986$843_Y }
133150   connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4987$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4987$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4987$848_Y }
133151   connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4996$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4996$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4996$854_Y }
133152   connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4997$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4997$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4997$859_Y }
133153   connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5006$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5006$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5006$865_Y }
133154   connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5007$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5007$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5007$870_Y }
133155   connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5016$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5016$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5016$876_Y }
133156   connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5017$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5017$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5017$881_Y }
133157   connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] }
133158   connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5113$901_Y
133159   connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] }
133160   connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5123$904_Y
133161   connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] }
133162   connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5133$907_Y
133163   connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] }
133164   connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5143$910_Y
133165   connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val
133166   connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last
133167   connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5168$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5168$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5168$918_Y }
133168   connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5169$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5169$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5169$923_Y }
133169   connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5178$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5178$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5178$929_Y }
133170   connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5179$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5179$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5179$934_Y }
133171   connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5188$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5188$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5188$940_Y }
133172   connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5189$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5189$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5189$945_Y }
133173   connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5198$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5198$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5198$951_Y }
133174   connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5199$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5199$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5199$956_Y }
133175   connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0
133176   connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready
133177   connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first
133178   connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last
133179   connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0
133180   connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid
133181   connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready
133182   connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first
133183   connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last
133184   connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data
133185   connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid
133186   connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready
133187   connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first
133188   connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last
133189   connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data
133190   connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data }
133191   connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout
133192   connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable
133193   connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid
133194   connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first
133195   connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last
133196   connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data
133197   connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable
133198   connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first
133199   connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last
133200   connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data
133201   connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready
133202   connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din
133203   connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5435$990_Y
133204   connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5436$991_Y
133205   connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume
133206   connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r
133207   connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5439$992_Y
133208   connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5440$993_Y
133209   connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid
133210   connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready
133211   connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first
133212   connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last
133213   connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data
133214   connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5446$995_Y
133215   connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all
133216   connect \main_sdblock2mem_converter_load_part $and$ls180.v:5448$996_Y
133217   connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1
133218   connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1
133219   connect \main_interface0_bus_we 1'1
133220   connect \main_interface0_bus_sel 4'1111
133221   connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address
133222   connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] }
133223   connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack
133224   connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2]
133225   connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] }
133226   connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5458$997_Y
133227   connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid
133228   connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready
133229   connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first
133230   connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last
133231   connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data
133232   connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1
133233   connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready
133234   connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1
133235   connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1
133236   connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1
133237   connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid
133238   connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0
133239   connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first
133240   connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last
133241   connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data
133242   connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2]
133243   connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] }
133244   connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset
133245   connect \main_sdmem2block_dma_reset $not$ls180.v:5517$1004_Y
133246   connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid
133247   connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1
133248   connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first
133249   connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last
133250   connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data
133251   connect \main_sdmem2block_converter_first $eq$ls180.v:5598$1012_Y
133252   connect \main_sdmem2block_converter_last $eq$ls180.v:5599$1013_Y
133253   connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid
133254   connect \main_sdmem2block_converter_source_first $and$ls180.v:5601$1014_Y
133255   connect \main_sdmem2block_converter_source_last $and$ls180.v:5602$1015_Y
133256   connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5603$1016_Y
133257   connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last
133258   connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data }
133259   connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout
133260   connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable
133261   connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid
133262   connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first
133263   connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last
133264   connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data
133265   connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable
133266   connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first
133267   connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last
133268   connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data
133269   connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready
133270   connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din
133271   connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5643$1021_Y
133272   connect \main_sdmem2block_fifo_do_read $and$ls180.v:5644$1022_Y
133273   connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume
133274   connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r
133275   connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5647$1023_Y
133276   connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5648$1024_Y
133277   connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0]
133278   connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25
133279   connect \builder_shared_sel \builder_comb_rhs_array_muxed26
133280   connect \builder_shared_cyc \builder_comb_rhs_array_muxed27
133281   connect \builder_shared_stb \builder_comb_rhs_array_muxed28
133282   connect \builder_shared_we \builder_comb_rhs_array_muxed29
133283   connect \builder_shared_cti \builder_comb_rhs_array_muxed30
133284   connect \builder_shared_bte \builder_comb_rhs_array_muxed31
133285   connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r
133286   connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r
133287   connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r
133288   connect \main_interface0_bus_dat_r \builder_shared_dat_r
133289   connect \main_interface1_bus_dat_r \builder_shared_dat_r
133290   connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5699$1030_Y
133291   connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5700$1032_Y
133292   connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5701$1034_Y
133293   connect \main_interface0_bus_ack $and$ls180.v:5702$1036_Y
133294   connect \main_interface1_bus_ack $and$ls180.v:5703$1038_Y
133295   connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5704$1040_Y
133296   connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5705$1042_Y
133297   connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5706$1044_Y
133298   connect \main_interface0_bus_err $and$ls180.v:5707$1046_Y
133299   connect \main_interface1_bus_err $and$ls180.v:5708$1048_Y
133300   connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc }
133301   connect \main_libresocsim_ram_bus_adr \builder_shared_adr
133302   connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w
133303   connect \main_libresocsim_ram_bus_sel \builder_shared_sel
133304   connect \main_libresocsim_ram_bus_stb \builder_shared_stb
133305   connect \main_libresocsim_ram_bus_we \builder_shared_we
133306   connect \main_libresocsim_ram_bus_cti \builder_shared_cti
133307   connect \main_libresocsim_ram_bus_bte \builder_shared_bte
133308   connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr
133309   connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w
133310   connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel
133311   connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb
133312   connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we
133313   connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti
133314   connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte
133315   connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr
133316   connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w
133317   connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel
133318   connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb
133319   connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we
133320   connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti
133321   connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte
133322   connect \main_wb_sdram_adr \builder_shared_adr
133323   connect \main_wb_sdram_dat_w \builder_shared_dat_w
133324   connect \main_wb_sdram_sel \builder_shared_sel
133325   connect \main_wb_sdram_stb \builder_shared_stb
133326   connect \main_wb_sdram_we \builder_shared_we
133327   connect \main_wb_sdram_cti \builder_shared_cti
133328   connect \main_wb_sdram_bte \builder_shared_bte
133329   connect \builder_libresocsim_wishbone_adr \builder_shared_adr
133330   connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w
133331   connect \builder_libresocsim_wishbone_sel \builder_shared_sel
133332   connect \builder_libresocsim_wishbone_stb \builder_shared_stb
133333   connect \builder_libresocsim_wishbone_we \builder_shared_we
133334   connect \builder_libresocsim_wishbone_cti \builder_shared_cti
133335   connect \builder_libresocsim_wishbone_bte \builder_shared_bte
133336   connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5753$1055_Y
133337   connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5754$1056_Y
133338   connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5755$1057_Y
133339   connect \main_wb_sdram_cyc $and$ls180.v:5756$1058_Y
133340   connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5757$1059_Y
133341   connect \builder_shared_err $or$ls180.v:5758$1063_Y
133342   connect \builder_wait $and$ls180.v:5759$1066_Y
133343   connect \builder_done $eq$ls180.v:5772$1081_Y
133344   connect \builder_csrbank0_sel $eq$ls180.v:5773$1082_Y
133345   connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0]
133346   connect \builder_csrbank0_reset0_re $and$ls180.v:5775$1085_Y
133347   connect \builder_csrbank0_reset0_we $and$ls180.v:5776$1089_Y
133348   connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w
133349   connect \builder_csrbank0_scratch3_re $and$ls180.v:5778$1092_Y
133350   connect \builder_csrbank0_scratch3_we $and$ls180.v:5779$1096_Y
133351   connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w
133352   connect \builder_csrbank0_scratch2_re $and$ls180.v:5781$1099_Y
133353   connect \builder_csrbank0_scratch2_we $and$ls180.v:5782$1103_Y
133354   connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w
133355   connect \builder_csrbank0_scratch1_re $and$ls180.v:5784$1106_Y
133356   connect \builder_csrbank0_scratch1_we $and$ls180.v:5785$1110_Y
133357   connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w
133358   connect \builder_csrbank0_scratch0_re $and$ls180.v:5787$1113_Y
133359   connect \builder_csrbank0_scratch0_we $and$ls180.v:5788$1117_Y
133360   connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w
133361   connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5790$1120_Y
133362   connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5791$1124_Y
133363   connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w
133364   connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5793$1127_Y
133365   connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5794$1131_Y
133366   connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w
133367   connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5796$1134_Y
133368   connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5797$1138_Y
133369   connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w
133370   connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5799$1141_Y
133371   connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5800$1145_Y
133372   connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage
133373   connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24]
133374   connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16]
133375   connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8]
133376   connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0]
133377   connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24]
133378   connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16]
133379   connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8]
133380   connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0]
133381   connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we
133382   connect \builder_csrbank1_sel $eq$ls180.v:5811$1146_Y
133383   connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w
133384   connect \builder_csrbank1_oe1_re $and$ls180.v:5813$1149_Y
133385   connect \builder_csrbank1_oe1_we $and$ls180.v:5814$1153_Y
133386   connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w
133387   connect \builder_csrbank1_oe0_re $and$ls180.v:5816$1156_Y
133388   connect \builder_csrbank1_oe0_we $and$ls180.v:5817$1160_Y
133389   connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w
133390   connect \builder_csrbank1_in1_re $and$ls180.v:5819$1163_Y
133391   connect \builder_csrbank1_in1_we $and$ls180.v:5820$1167_Y
133392   connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w
133393   connect \builder_csrbank1_in0_re $and$ls180.v:5822$1170_Y
133394   connect \builder_csrbank1_in0_we $and$ls180.v:5823$1174_Y
133395   connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w
133396   connect \builder_csrbank1_out1_re $and$ls180.v:5825$1177_Y
133397   connect \builder_csrbank1_out1_we $and$ls180.v:5826$1181_Y
133398   connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w
133399   connect \builder_csrbank1_out0_re $and$ls180.v:5828$1184_Y
133400   connect \builder_csrbank1_out0_we $and$ls180.v:5829$1188_Y
133401   connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8]
133402   connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0]
133403   connect \builder_csrbank1_in1_w \main_gpio_status [15:8]
133404   connect \builder_csrbank1_in0_w \main_gpio_status [7:0]
133405   connect \main_gpio_we \builder_csrbank1_in0_we
133406   connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8]
133407   connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0]
133408   connect \builder_csrbank2_sel $eq$ls180.v:5837$1189_Y
133409   connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0]
133410   connect \builder_csrbank2_w0_re $and$ls180.v:5839$1192_Y
133411   connect \builder_csrbank2_w0_we $and$ls180.v:5840$1196_Y
133412   connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0]
133413   connect \builder_csrbank2_r_re $and$ls180.v:5842$1199_Y
133414   connect \builder_csrbank2_r_we $and$ls180.v:5843$1203_Y
133415   connect \main_i2c_scl \main_i2c_storage [0]
133416   connect \main_i2c_oe \main_i2c_storage [1]
133417   connect \main_i2c_sda0 \main_i2c_storage [2]
133418   connect \builder_csrbank2_w0_w \main_i2c_storage
133419   connect \main_i2c_status \main_i2c_sda1
133420   connect \builder_csrbank2_r_w \main_i2c_status
133421   connect \main_i2c_we \builder_csrbank2_r_we
133422   connect \builder_csrbank3_sel $eq$ls180.v:5851$1204_Y
133423   connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0]
133424   connect \builder_csrbank3_enable0_re $and$ls180.v:5853$1207_Y
133425   connect \builder_csrbank3_enable0_we $and$ls180.v:5854$1211_Y
133426   connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w
133427   connect \builder_csrbank3_width3_re $and$ls180.v:5856$1214_Y
133428   connect \builder_csrbank3_width3_we $and$ls180.v:5857$1218_Y
133429   connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w
133430   connect \builder_csrbank3_width2_re $and$ls180.v:5859$1221_Y
133431   connect \builder_csrbank3_width2_we $and$ls180.v:5860$1225_Y
133432   connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w
133433   connect \builder_csrbank3_width1_re $and$ls180.v:5862$1228_Y
133434   connect \builder_csrbank3_width1_we $and$ls180.v:5863$1232_Y
133435   connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w
133436   connect \builder_csrbank3_width0_re $and$ls180.v:5865$1235_Y
133437   connect \builder_csrbank3_width0_we $and$ls180.v:5866$1239_Y
133438   connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w
133439   connect \builder_csrbank3_period3_re $and$ls180.v:5868$1242_Y
133440   connect \builder_csrbank3_period3_we $and$ls180.v:5869$1246_Y
133441   connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w
133442   connect \builder_csrbank3_period2_re $and$ls180.v:5871$1249_Y
133443   connect \builder_csrbank3_period2_we $and$ls180.v:5872$1253_Y
133444   connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w
133445   connect \builder_csrbank3_period1_re $and$ls180.v:5874$1256_Y
133446   connect \builder_csrbank3_period1_we $and$ls180.v:5875$1260_Y
133447   connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w
133448   connect \builder_csrbank3_period0_re $and$ls180.v:5877$1263_Y
133449   connect \builder_csrbank3_period0_we $and$ls180.v:5878$1267_Y
133450   connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage
133451   connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24]
133452   connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16]
133453   connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8]
133454   connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0]
133455   connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24]
133456   connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16]
133457   connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8]
133458   connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0]
133459   connect \builder_csrbank4_sel $eq$ls180.v:5888$1268_Y
133460   connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0]
133461   connect \builder_csrbank4_enable0_re $and$ls180.v:5890$1271_Y
133462   connect \builder_csrbank4_enable0_we $and$ls180.v:5891$1275_Y
133463   connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w
133464   connect \builder_csrbank4_width3_re $and$ls180.v:5893$1278_Y
133465   connect \builder_csrbank4_width3_we $and$ls180.v:5894$1282_Y
133466   connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w
133467   connect \builder_csrbank4_width2_re $and$ls180.v:5896$1285_Y
133468   connect \builder_csrbank4_width2_we $and$ls180.v:5897$1289_Y
133469   connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w
133470   connect \builder_csrbank4_width1_re $and$ls180.v:5899$1292_Y
133471   connect \builder_csrbank4_width1_we $and$ls180.v:5900$1296_Y
133472   connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w
133473   connect \builder_csrbank4_width0_re $and$ls180.v:5902$1299_Y
133474   connect \builder_csrbank4_width0_we $and$ls180.v:5903$1303_Y
133475   connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w
133476   connect \builder_csrbank4_period3_re $and$ls180.v:5905$1306_Y
133477   connect \builder_csrbank4_period3_we $and$ls180.v:5906$1310_Y
133478   connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w
133479   connect \builder_csrbank4_period2_re $and$ls180.v:5908$1313_Y
133480   connect \builder_csrbank4_period2_we $and$ls180.v:5909$1317_Y
133481   connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w
133482   connect \builder_csrbank4_period1_re $and$ls180.v:5911$1320_Y
133483   connect \builder_csrbank4_period1_we $and$ls180.v:5912$1324_Y
133484   connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w
133485   connect \builder_csrbank4_period0_re $and$ls180.v:5914$1327_Y
133486   connect \builder_csrbank4_period0_we $and$ls180.v:5915$1331_Y
133487   connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage
133488   connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24]
133489   connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16]
133490   connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8]
133491   connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0]
133492   connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24]
133493   connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16]
133494   connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8]
133495   connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0]
133496   connect \builder_csrbank5_sel $eq$ls180.v:5925$1332_Y
133497   connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w
133498   connect \builder_csrbank5_dma_base7_re $and$ls180.v:5927$1335_Y
133499   connect \builder_csrbank5_dma_base7_we $and$ls180.v:5928$1339_Y
133500   connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w
133501   connect \builder_csrbank5_dma_base6_re $and$ls180.v:5930$1342_Y
133502   connect \builder_csrbank5_dma_base6_we $and$ls180.v:5931$1346_Y
133503   connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w
133504   connect \builder_csrbank5_dma_base5_re $and$ls180.v:5933$1349_Y
133505   connect \builder_csrbank5_dma_base5_we $and$ls180.v:5934$1353_Y
133506   connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w
133507   connect \builder_csrbank5_dma_base4_re $and$ls180.v:5936$1356_Y
133508   connect \builder_csrbank5_dma_base4_we $and$ls180.v:5937$1360_Y
133509   connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w
133510   connect \builder_csrbank5_dma_base3_re $and$ls180.v:5939$1363_Y
133511   connect \builder_csrbank5_dma_base3_we $and$ls180.v:5940$1367_Y
133512   connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w
133513   connect \builder_csrbank5_dma_base2_re $and$ls180.v:5942$1370_Y
133514   connect \builder_csrbank5_dma_base2_we $and$ls180.v:5943$1374_Y
133515   connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w
133516   connect \builder_csrbank5_dma_base1_re $and$ls180.v:5945$1377_Y
133517   connect \builder_csrbank5_dma_base1_we $and$ls180.v:5946$1381_Y
133518   connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w
133519   connect \builder_csrbank5_dma_base0_re $and$ls180.v:5948$1384_Y
133520   connect \builder_csrbank5_dma_base0_we $and$ls180.v:5949$1388_Y
133521   connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w
133522   connect \builder_csrbank5_dma_length3_re $and$ls180.v:5951$1391_Y
133523   connect \builder_csrbank5_dma_length3_we $and$ls180.v:5952$1395_Y
133524   connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w
133525   connect \builder_csrbank5_dma_length2_re $and$ls180.v:5954$1398_Y
133526   connect \builder_csrbank5_dma_length2_we $and$ls180.v:5955$1402_Y
133527   connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w
133528   connect \builder_csrbank5_dma_length1_re $and$ls180.v:5957$1405_Y
133529   connect \builder_csrbank5_dma_length1_we $and$ls180.v:5958$1409_Y
133530   connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w
133531   connect \builder_csrbank5_dma_length0_re $and$ls180.v:5960$1412_Y
133532   connect \builder_csrbank5_dma_length0_we $and$ls180.v:5961$1416_Y
133533   connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0]
133534   connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5963$1419_Y
133535   connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5964$1423_Y
133536   connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0]
133537   connect \builder_csrbank5_dma_done_re $and$ls180.v:5966$1426_Y
133538   connect \builder_csrbank5_dma_done_we $and$ls180.v:5967$1430_Y
133539   connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0]
133540   connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5969$1433_Y
133541   connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5970$1437_Y
133542   connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56]
133543   connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48]
133544   connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40]
133545   connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32]
133546   connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24]
133547   connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16]
133548   connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8]
133549   connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0]
133550   connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24]
133551   connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16]
133552   connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8]
133553   connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0]
133554   connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage
133555   connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status
133556   connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we
133557   connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage
133558   connect \builder_csrbank6_sel $eq$ls180.v:5987$1438_Y
133559   connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w
133560   connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5989$1441_Y
133561   connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5990$1445_Y
133562   connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w
133563   connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5992$1448_Y
133564   connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5993$1452_Y
133565   connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w
133566   connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5995$1455_Y
133567   connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5996$1459_Y
133568   connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w
133569   connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5998$1462_Y
133570   connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5999$1466_Y
133571   connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w
133572   connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6001$1469_Y
133573   connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6002$1473_Y
133574   connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w
133575   connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6004$1476_Y
133576   connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6005$1480_Y
133577   connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w
133578   connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6007$1483_Y
133579   connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6008$1487_Y
133580   connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w
133581   connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6010$1490_Y
133582   connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6011$1494_Y
133583   connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0]
133584   connect \main_sdcore_cmd_send_re $and$ls180.v:6013$1497_Y
133585   connect \main_sdcore_cmd_send_we $and$ls180.v:6014$1501_Y
133586   connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w
133587   connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6016$1504_Y
133588   connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6017$1508_Y
133589   connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w
133590   connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6019$1511_Y
133591   connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6020$1515_Y
133592   connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w
133593   connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6022$1518_Y
133594   connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6023$1522_Y
133595   connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w
133596   connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6025$1525_Y
133597   connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6026$1529_Y
133598   connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w
133599   connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6028$1532_Y
133600   connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6029$1536_Y
133601   connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w
133602   connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6031$1539_Y
133603   connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6032$1543_Y
133604   connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w
133605   connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6034$1546_Y
133606   connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6035$1550_Y
133607   connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w
133608   connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6037$1553_Y
133609   connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6038$1557_Y
133610   connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w
133611   connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6040$1560_Y
133612   connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6041$1564_Y
133613   connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w
133614   connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6043$1567_Y
133615   connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6044$1571_Y
133616   connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w
133617   connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6046$1574_Y
133618   connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6047$1578_Y
133619   connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w
133620   connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6049$1581_Y
133621   connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6050$1585_Y
133622   connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w
133623   connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6052$1588_Y
133624   connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6053$1592_Y
133625   connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w
133626   connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6055$1595_Y
133627   connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6056$1599_Y
133628   connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w
133629   connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6058$1602_Y
133630   connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6059$1606_Y
133631   connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w
133632   connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6061$1609_Y
133633   connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6062$1613_Y
133634   connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0]
133635   connect \builder_csrbank6_cmd_event_re $and$ls180.v:6064$1616_Y
133636   connect \builder_csrbank6_cmd_event_we $and$ls180.v:6065$1620_Y
133637   connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0]
133638   connect \builder_csrbank6_data_event_re $and$ls180.v:6067$1623_Y
133639   connect \builder_csrbank6_data_event_we $and$ls180.v:6068$1627_Y
133640   connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0]
133641   connect \builder_csrbank6_block_length1_re $and$ls180.v:6070$1630_Y
133642   connect \builder_csrbank6_block_length1_we $and$ls180.v:6071$1634_Y
133643   connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w
133644   connect \builder_csrbank6_block_length0_re $and$ls180.v:6073$1637_Y
133645   connect \builder_csrbank6_block_length0_we $and$ls180.v:6074$1641_Y
133646   connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w
133647   connect \builder_csrbank6_block_count3_re $and$ls180.v:6076$1644_Y
133648   connect \builder_csrbank6_block_count3_we $and$ls180.v:6077$1648_Y
133649   connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w
133650   connect \builder_csrbank6_block_count2_re $and$ls180.v:6079$1651_Y
133651   connect \builder_csrbank6_block_count2_we $and$ls180.v:6080$1655_Y
133652   connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w
133653   connect \builder_csrbank6_block_count1_re $and$ls180.v:6082$1658_Y
133654   connect \builder_csrbank6_block_count1_we $and$ls180.v:6083$1662_Y
133655   connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w
133656   connect \builder_csrbank6_block_count0_re $and$ls180.v:6085$1665_Y
133657   connect \builder_csrbank6_block_count0_we $and$ls180.v:6086$1669_Y
133658   connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24]
133659   connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16]
133660   connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8]
133661   connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0]
133662   connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24]
133663   connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16]
133664   connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8]
133665   connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0]
133666   connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120]
133667   connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112]
133668   connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104]
133669   connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96]
133670   connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88]
133671   connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80]
133672   connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72]
133673   connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64]
133674   connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56]
133675   connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48]
133676   connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40]
133677   connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32]
133678   connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24]
133679   connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16]
133680   connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8]
133681   connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0]
133682   connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we
133683   connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status
133684   connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we
133685   connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status
133686   connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we
133687   connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8]
133688   connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0]
133689   connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24]
133690   connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16]
133691   connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8]
133692   connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0]
133693   connect \builder_csrbank7_sel $eq$ls180.v:6122$1670_Y
133694   connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w
133695   connect \builder_csrbank7_dma_base7_re $and$ls180.v:6124$1673_Y
133696   connect \builder_csrbank7_dma_base7_we $and$ls180.v:6125$1677_Y
133697   connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w
133698   connect \builder_csrbank7_dma_base6_re $and$ls180.v:6127$1680_Y
133699   connect \builder_csrbank7_dma_base6_we $and$ls180.v:6128$1684_Y
133700   connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w
133701   connect \builder_csrbank7_dma_base5_re $and$ls180.v:6130$1687_Y
133702   connect \builder_csrbank7_dma_base5_we $and$ls180.v:6131$1691_Y
133703   connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w
133704   connect \builder_csrbank7_dma_base4_re $and$ls180.v:6133$1694_Y
133705   connect \builder_csrbank7_dma_base4_we $and$ls180.v:6134$1698_Y
133706   connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w
133707   connect \builder_csrbank7_dma_base3_re $and$ls180.v:6136$1701_Y
133708   connect \builder_csrbank7_dma_base3_we $and$ls180.v:6137$1705_Y
133709   connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w
133710   connect \builder_csrbank7_dma_base2_re $and$ls180.v:6139$1708_Y
133711   connect \builder_csrbank7_dma_base2_we $and$ls180.v:6140$1712_Y
133712   connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w
133713   connect \builder_csrbank7_dma_base1_re $and$ls180.v:6142$1715_Y
133714   connect \builder_csrbank7_dma_base1_we $and$ls180.v:6143$1719_Y
133715   connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w
133716   connect \builder_csrbank7_dma_base0_re $and$ls180.v:6145$1722_Y
133717   connect \builder_csrbank7_dma_base0_we $and$ls180.v:6146$1726_Y
133718   connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w
133719   connect \builder_csrbank7_dma_length3_re $and$ls180.v:6148$1729_Y
133720   connect \builder_csrbank7_dma_length3_we $and$ls180.v:6149$1733_Y
133721   connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w
133722   connect \builder_csrbank7_dma_length2_re $and$ls180.v:6151$1736_Y
133723   connect \builder_csrbank7_dma_length2_we $and$ls180.v:6152$1740_Y
133724   connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w
133725   connect \builder_csrbank7_dma_length1_re $and$ls180.v:6154$1743_Y
133726   connect \builder_csrbank7_dma_length1_we $and$ls180.v:6155$1747_Y
133727   connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w
133728   connect \builder_csrbank7_dma_length0_re $and$ls180.v:6157$1750_Y
133729   connect \builder_csrbank7_dma_length0_we $and$ls180.v:6158$1754_Y
133730   connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0]
133731   connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6160$1757_Y
133732   connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6161$1761_Y
133733   connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0]
133734   connect \builder_csrbank7_dma_done_re $and$ls180.v:6163$1764_Y
133735   connect \builder_csrbank7_dma_done_we $and$ls180.v:6164$1768_Y
133736   connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0]
133737   connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6166$1771_Y
133738   connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6167$1775_Y
133739   connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w
133740   connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6169$1778_Y
133741   connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6170$1782_Y
133742   connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w
133743   connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6172$1785_Y
133744   connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6173$1789_Y
133745   connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w
133746   connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6175$1792_Y
133747   connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6176$1796_Y
133748   connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w
133749   connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6178$1799_Y
133750   connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6179$1803_Y
133751   connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56]
133752   connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48]
133753   connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40]
133754   connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32]
133755   connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24]
133756   connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16]
133757   connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8]
133758   connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0]
133759   connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24]
133760   connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16]
133761   connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8]
133762   connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0]
133763   connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage
133764   connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status
133765   connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we
133766   connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage
133767   connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24]
133768   connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16]
133769   connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8]
133770   connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0]
133771   connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we
133772   connect \builder_csrbank8_sel $eq$ls180.v:6201$1804_Y
133773   connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0]
133774   connect \builder_csrbank8_card_detect_re $and$ls180.v:6203$1807_Y
133775   connect \builder_csrbank8_card_detect_we $and$ls180.v:6204$1811_Y
133776   connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0]
133777   connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6206$1814_Y
133778   connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6207$1818_Y
133779   connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w
133780   connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6209$1821_Y
133781   connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6210$1825_Y
133782   connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0]
133783   connect \main_sdphy_init_initialize_re $and$ls180.v:6212$1828_Y
133784   connect \main_sdphy_init_initialize_we $and$ls180.v:6213$1832_Y
133785   connect \builder_csrbank8_card_detect_w \main_sdphy_status
133786   connect \main_sdphy_we \builder_csrbank8_card_detect_we
133787   connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8]
133788   connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0]
133789   connect \builder_csrbank9_sel $eq$ls180.v:6218$1833_Y
133790   connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0]
133791   connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6220$1836_Y
133792   connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6221$1840_Y
133793   connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0]
133794   connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6223$1843_Y
133795   connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6224$1847_Y
133796   connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0]
133797   connect \main_sdram_command_issue_re $and$ls180.v:6226$1850_Y
133798   connect \main_sdram_command_issue_we $and$ls180.v:6227$1854_Y
133799   connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0]
133800   connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6229$1857_Y
133801   connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6230$1861_Y
133802   connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w
133803   connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6232$1864_Y
133804   connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6233$1868_Y
133805   connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0]
133806   connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6235$1871_Y
133807   connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6236$1875_Y
133808   connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w
133809   connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6238$1878_Y
133810   connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6239$1882_Y
133811   connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w
133812   connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6241$1885_Y
133813   connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6242$1889_Y
133814   connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w
133815   connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6244$1892_Y
133816   connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6245$1896_Y
133817   connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w
133818   connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6247$1899_Y
133819   connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6248$1903_Y
133820   connect \main_sdram_sel \main_sdram_storage [0]
133821   connect \main_sdram_cke \main_sdram_storage [1]
133822   connect \main_sdram_odt \main_sdram_storage [2]
133823   connect \main_sdram_reset_n \main_sdram_storage [3]
133824   connect \builder_csrbank9_dfii_control0_w \main_sdram_storage
133825   connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage
133826   connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8]
133827   connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0]
133828   connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage
133829   connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8]
133830   connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0]
133831   connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8]
133832   connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0]
133833   connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we
133834   connect \builder_csrbank10_sel $eq$ls180.v:6263$1904_Y
133835   connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w
133836   connect \builder_csrbank10_control1_re $and$ls180.v:6265$1907_Y
133837   connect \builder_csrbank10_control1_we $and$ls180.v:6266$1911_Y
133838   connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w
133839   connect \builder_csrbank10_control0_re $and$ls180.v:6268$1914_Y
133840   connect \builder_csrbank10_control0_we $and$ls180.v:6269$1918_Y
133841   connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0]
133842   connect \builder_csrbank10_status_re $and$ls180.v:6271$1921_Y
133843   connect \builder_csrbank10_status_we $and$ls180.v:6272$1925_Y
133844   connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w
133845   connect \builder_csrbank10_mosi0_re $and$ls180.v:6274$1928_Y
133846   connect \builder_csrbank10_mosi0_we $and$ls180.v:6275$1932_Y
133847   connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w
133848   connect \builder_csrbank10_miso_re $and$ls180.v:6277$1935_Y
133849   connect \builder_csrbank10_miso_we $and$ls180.v:6278$1939_Y
133850   connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0]
133851   connect \builder_csrbank10_cs0_re $and$ls180.v:6280$1942_Y
133852   connect \builder_csrbank10_cs0_we $and$ls180.v:6281$1946_Y
133853   connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0]
133854   connect \builder_csrbank10_loopback0_re $and$ls180.v:6283$1949_Y
133855   connect \builder_csrbank10_loopback0_we $and$ls180.v:6284$1953_Y
133856   connect \main_spimaster10_length \main_spimaster11_storage [15:8]
133857   connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8]
133858   connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0]
133859   connect \main_spimaster14_status \main_spimaster13_done
133860   connect \builder_csrbank10_status_w \main_spimaster14_status
133861   connect \main_spimaster15_we \builder_csrbank10_status_we
133862   connect \builder_csrbank10_mosi0_w \main_spimaster16_storage
133863   connect \builder_csrbank10_miso_w \main_spimaster18_status
133864   connect \main_spimaster19_we \builder_csrbank10_miso_we
133865   connect \main_spimaster20_sel \main_spimaster21_storage
133866   connect \builder_csrbank10_cs0_w \main_spimaster21_storage
133867   connect \builder_csrbank10_loopback0_w \main_spimaster23_storage
133868   connect \builder_csrbank11_sel $eq$ls180.v:6303$1955_Y
133869   connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w
133870   connect \builder_csrbank11_control1_re $and$ls180.v:6305$1958_Y
133871   connect \builder_csrbank11_control1_we $and$ls180.v:6306$1962_Y
133872   connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w
133873   connect \builder_csrbank11_control0_re $and$ls180.v:6308$1965_Y
133874   connect \builder_csrbank11_control0_we $and$ls180.v:6309$1969_Y
133875   connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0]
133876   connect \builder_csrbank11_status_re $and$ls180.v:6311$1972_Y
133877   connect \builder_csrbank11_status_we $and$ls180.v:6312$1976_Y
133878   connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w
133879   connect \builder_csrbank11_mosi0_re $and$ls180.v:6314$1979_Y
133880   connect \builder_csrbank11_mosi0_we $and$ls180.v:6315$1983_Y
133881   connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w
133882   connect \builder_csrbank11_miso_re $and$ls180.v:6317$1986_Y
133883   connect \builder_csrbank11_miso_we $and$ls180.v:6318$1990_Y
133884   connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0]
133885   connect \builder_csrbank11_cs0_re $and$ls180.v:6320$1993_Y
133886   connect \builder_csrbank11_cs0_we $and$ls180.v:6321$1997_Y
133887   connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0]
133888   connect \builder_csrbank11_loopback0_re $and$ls180.v:6323$2000_Y
133889   connect \builder_csrbank11_loopback0_we $and$ls180.v:6324$2004_Y
133890   connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w
133891   connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6326$2007_Y
133892   connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6327$2011_Y
133893   connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w
133894   connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6329$2014_Y
133895   connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6330$2018_Y
133896   connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8]
133897   connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8]
133898   connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0]
133899   connect \main_spisdcard_status_status \main_spisdcard_done1
133900   connect \builder_csrbank11_status_w \main_spisdcard_status_status
133901   connect \main_spisdcard_status_we \builder_csrbank11_status_we
133902   connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage
133903   connect \builder_csrbank11_miso_w \main_spisdcard_miso_status
133904   connect \main_spisdcard_miso_we \builder_csrbank11_miso_we
133905   connect \main_spisdcard_sel \main_spisdcard_cs_storage
133906   connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage
133907   connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage
133908   connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8]
133909   connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0]
133910   connect \builder_csrbank12_sel $eq$ls180.v:6351$2020_Y
133911   connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w
133912   connect \builder_csrbank12_load3_re $and$ls180.v:6353$2023_Y
133913   connect \builder_csrbank12_load3_we $and$ls180.v:6354$2027_Y
133914   connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w
133915   connect \builder_csrbank12_load2_re $and$ls180.v:6356$2030_Y
133916   connect \builder_csrbank12_load2_we $and$ls180.v:6357$2034_Y
133917   connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w
133918   connect \builder_csrbank12_load1_re $and$ls180.v:6359$2037_Y
133919   connect \builder_csrbank12_load1_we $and$ls180.v:6360$2041_Y
133920   connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w
133921   connect \builder_csrbank12_load0_re $and$ls180.v:6362$2044_Y
133922   connect \builder_csrbank12_load0_we $and$ls180.v:6363$2048_Y
133923   connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w
133924   connect \builder_csrbank12_reload3_re $and$ls180.v:6365$2051_Y
133925   connect \builder_csrbank12_reload3_we $and$ls180.v:6366$2055_Y
133926   connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w
133927   connect \builder_csrbank12_reload2_re $and$ls180.v:6368$2058_Y
133928   connect \builder_csrbank12_reload2_we $and$ls180.v:6369$2062_Y
133929   connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w
133930   connect \builder_csrbank12_reload1_re $and$ls180.v:6371$2065_Y
133931   connect \builder_csrbank12_reload1_we $and$ls180.v:6372$2069_Y
133932   connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w
133933   connect \builder_csrbank12_reload0_re $and$ls180.v:6374$2072_Y
133934   connect \builder_csrbank12_reload0_we $and$ls180.v:6375$2076_Y
133935   connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0]
133936   connect \builder_csrbank12_en0_re $and$ls180.v:6377$2079_Y
133937   connect \builder_csrbank12_en0_we $and$ls180.v:6378$2083_Y
133938   connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0]
133939   connect \builder_csrbank12_update_value0_re $and$ls180.v:6380$2086_Y
133940   connect \builder_csrbank12_update_value0_we $and$ls180.v:6381$2090_Y
133941   connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w
133942   connect \builder_csrbank12_value3_re $and$ls180.v:6383$2093_Y
133943   connect \builder_csrbank12_value3_we $and$ls180.v:6384$2097_Y
133944   connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w
133945   connect \builder_csrbank12_value2_re $and$ls180.v:6386$2100_Y
133946   connect \builder_csrbank12_value2_we $and$ls180.v:6387$2104_Y
133947   connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w
133948   connect \builder_csrbank12_value1_re $and$ls180.v:6389$2107_Y
133949   connect \builder_csrbank12_value1_we $and$ls180.v:6390$2111_Y
133950   connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w
133951   connect \builder_csrbank12_value0_re $and$ls180.v:6392$2114_Y
133952   connect \builder_csrbank12_value0_we $and$ls180.v:6393$2118_Y
133953   connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0]
133954   connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6395$2121_Y
133955   connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6396$2125_Y
133956   connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0]
133957   connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6398$2128_Y
133958   connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6399$2132_Y
133959   connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0]
133960   connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6401$2135_Y
133961   connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6402$2139_Y
133962   connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24]
133963   connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16]
133964   connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8]
133965   connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0]
133966   connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24]
133967   connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16]
133968   connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8]
133969   connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0]
133970   connect \builder_csrbank12_en0_w \main_libresocsim_en_storage
133971   connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage
133972   connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24]
133973   connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16]
133974   connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8]
133975   connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0]
133976   connect \main_libresocsim_value_we \builder_csrbank12_value0_we
133977   connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage
133978   connect \builder_csrbank13_sel $eq$ls180.v:6419$2140_Y
133979   connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w
133980   connect \main_uart_rxtx_re $and$ls180.v:6421$2143_Y
133981   connect \main_uart_rxtx_we $and$ls180.v:6422$2147_Y
133982   connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0]
133983   connect \builder_csrbank13_txfull_re $and$ls180.v:6424$2150_Y
133984   connect \builder_csrbank13_txfull_we $and$ls180.v:6425$2154_Y
133985   connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0]
133986   connect \builder_csrbank13_rxempty_re $and$ls180.v:6427$2157_Y
133987   connect \builder_csrbank13_rxempty_we $and$ls180.v:6428$2161_Y
133988   connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0]
133989   connect \main_uart_eventmanager_status_re $and$ls180.v:6430$2164_Y
133990   connect \main_uart_eventmanager_status_we $and$ls180.v:6431$2168_Y
133991   connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0]
133992   connect \main_uart_eventmanager_pending_re $and$ls180.v:6433$2171_Y
133993   connect \main_uart_eventmanager_pending_we $and$ls180.v:6434$2175_Y
133994   connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0]
133995   connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6436$2178_Y
133996   connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6437$2182_Y
133997   connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0]
133998   connect \builder_csrbank13_txempty_re $and$ls180.v:6439$2185_Y
133999   connect \builder_csrbank13_txempty_we $and$ls180.v:6440$2189_Y
134000   connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0]
134001   connect \builder_csrbank13_rxfull_re $and$ls180.v:6442$2192_Y
134002   connect \builder_csrbank13_rxfull_we $and$ls180.v:6443$2196_Y
134003   connect \builder_csrbank13_txfull_w \main_uart_txfull_status
134004   connect \main_uart_txfull_we \builder_csrbank13_txfull_we
134005   connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status
134006   connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we
134007   connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage
134008   connect \builder_csrbank13_txempty_w \main_uart_txempty_status
134009   connect \main_uart_txempty_we \builder_csrbank13_txempty_we
134010   connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status
134011   connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we
134012   connect \builder_csrbank14_sel $eq$ls180.v:6453$2197_Y
134013   connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w
134014   connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6455$2200_Y
134015   connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6456$2204_Y
134016   connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w
134017   connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6458$2207_Y
134018   connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6459$2211_Y
134019   connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w
134020   connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6461$2214_Y
134021   connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6462$2218_Y
134022   connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w
134023   connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6464$2221_Y
134024   connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6465$2225_Y
134025   connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24]
134026   connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16]
134027   connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8]
134028   connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0]
134029   connect \builder_csr_interconnect_adr \builder_libresocsim_adr
134030   connect \builder_csr_interconnect_we \builder_libresocsim_we
134031   connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w
134032   connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r
134033   connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr
134034   connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr
134035   connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr
134036   connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr
134037   connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr
134038   connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr
134039   connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr
134040   connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr
134041   connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr
134042   connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr
134043   connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr
134044   connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr
134045   connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr
134046   connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr
134047   connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr
134048   connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we
134049   connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we
134050   connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we
134051   connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we
134052   connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we
134053   connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we
134054   connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we
134055   connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we
134056   connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we
134057   connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we
134058   connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we
134059   connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we
134060   connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we
134061   connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we
134062   connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we
134063   connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w
134064   connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w
134065   connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w
134066   connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w
134067   connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w
134068   connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w
134069   connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w
134070   connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w
134071   connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w
134072   connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w
134073   connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w
134074   connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w
134075   connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w
134076   connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w
134077   connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w
134078   connect \builder_csr_interconnect_dat_r $or$ls180.v:6519$2239_Y
134079   connect \sdrio_clk \sys_clk_1
134080   connect \sdrio_clk_1 \sys_clk_1
134081   connect \sdrio_clk_2 \sys_clk_1
134082   connect \sdrio_clk_3 \sys_clk_1
134083   connect \sdrio_clk_4 \sys_clk_1
134084   connect \sdrio_clk_5 \sys_clk_1
134085   connect \sdrio_clk_6 \sys_clk_1
134086   connect \sdrio_clk_7 \sys_clk_1
134087   connect \sdrio_clk_8 \sys_clk_1
134088   connect \sdrio_clk_9 \sys_clk_1
134089   connect \sdrio_clk_10 \sys_clk_1
134090   connect \sdrio_clk_11 \sys_clk_1
134091   connect \sdrio_clk_12 \sys_clk_1
134092   connect \sdrio_clk_13 \sys_clk_1
134093   connect \sdrio_clk_14 \sys_clk_1
134094   connect \sdrio_clk_15 \sys_clk_1
134095   connect \sdrio_clk_16 \sys_clk_1
134096   connect \sdrio_clk_17 \sys_clk_1
134097   connect \sdrio_clk_18 \sys_clk_1
134098   connect \sdrio_clk_19 \sys_clk_1
134099   connect \sdrio_clk_20 \sys_clk_1
134100   connect \sdrio_clk_21 \sys_clk_1
134101   connect \sdrio_clk_22 \sys_clk_1
134102   connect \sdrio_clk_23 \sys_clk_1
134103   connect \sdrio_clk_24 \sys_clk_1
134104   connect \sdrio_clk_25 \sys_clk_1
134105   connect \sdrio_clk_26 \sys_clk_1
134106   connect \sdrio_clk_27 \sys_clk_1
134107   connect \sdrio_clk_28 \sys_clk_1
134108   connect \sdrio_clk_29 \sys_clk_1
134109   connect \sdrio_clk_30 \sys_clk_1
134110   connect \sdrio_clk_31 \sys_clk_1
134111   connect \sdrio_clk_32 \sys_clk_1
134112   connect \sdrio_clk_33 \sys_clk_1
134113   connect \sdrio_clk_34 \sys_clk_1
134114   connect \sdrio_clk_35 \sys_clk_1
134115   connect \sdrio_clk_36 \sys_clk_1
134116   connect \sdrio_clk_37 \sys_clk_1
134117   connect \sdrio_clk_38 \sys_clk_1
134118   connect \sdrio_clk_39 \sys_clk_1
134119   connect \sdrio_clk_40 \sys_clk_1
134120   connect \sdrio_clk_41 \sys_clk_1
134121   connect \sdrio_clk_42 \sys_clk_1
134122   connect \sdrio_clk_43 \sys_clk_1
134123   connect \sdrio_clk_44 \sys_clk_1
134124   connect \sdrio_clk_45 \sys_clk_1
134125   connect \sdrio_clk_46 \sys_clk_1
134126   connect \sdrio_clk_47 \sys_clk_1
134127   connect \sdrio_clk_48 \sys_clk_1
134128   connect \sdrio_clk_49 \sys_clk_1
134129   connect \sdrio_clk_50 \sys_clk_1
134130   connect \sdrio_clk_51 \sys_clk_1
134131   connect \sdrio_clk_52 \sys_clk_1
134132   connect \sdrio_clk_53 \sys_clk_1
134133   connect \sdrio_clk_54 \sys_clk_1
134134   connect \sdrio_clk_55 \sys_clk_1
134135   connect \main_uart_phy_rx \builder_multiregimpl0_regs1
134136   connect \main_pwm0_enable \main_pwm0_enable_storage
134137   connect \main_pwm0_width \main_pwm0_width_storage
134138   connect \main_pwm0_period \main_pwm0_period_storage
134139   connect \main_pwm1_enable \main_pwm1_enable_storage
134140   connect \main_pwm1_width \main_pwm1_width_storage
134141   connect \main_pwm1_period \main_pwm1_period_storage
134142   connect \sdrio_clk_56 \sys_clk_1
134143   connect \sdrio_clk_57 \sys_clk_1
134144   connect \sdrio_clk_58 \sys_clk_1
134145   connect \sdrio_clk_59 \sys_clk_1
134146   connect \sdrio_clk_60 \sys_clk_1
134147   connect \sdrio_clk_61 \sys_clk_1
134148   connect \sdrio_clk_62 \sys_clk_1
134149   connect \sdrio_clk_63 \sys_clk_1
134150   connect \sdrio_clk_64 \sys_clk_1
134151   connect \sdrio_clk_65 \sys_clk_1
134152   connect \sdrio_clk_66 \sys_clk_1
134153   connect \sdrio_clk_67 \sys_clk_1
134154   connect \sdrio_clk_68 \sys_clk_1
134155   connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10071$2705_DATA
134156   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat
134157   connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10089$2712_DATA
134158   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1
134159   connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10103$2719_DATA
134160   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2
134161   connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10117$2726_DATA
134162   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3
134163   connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10131$2733_DATA
134164   connect \main_uart_tx_fifo_wrport_dat_r \memdat_4
134165   connect \main_uart_tx_fifo_rdport_dat_r \memdat_5
134166   connect \main_uart_rx_fifo_wrport_dat_r \memdat_6
134167   connect \main_uart_rx_fifo_rdport_dat_r \memdat_7
134168   connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8
134169   connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10179$2754_DATA
134170   connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9
134171   connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10193$2761_DATA
134172 end
134173 attribute \src "libresoc.v:45741.1-45769.10"
134174 attribute \cells_not_processed 1
134175 attribute \nmigen.hierarchy "test_issuer.pll"
134176 attribute \generator "nMigen"
134177 module \pll
134178   attribute \src "libresoc.v:45742.7-45742.20"
134179   wire $0\initial[0:0]
134180   attribute \src "libresoc.v:45757.3-45766.6"
134181   wire $0\pll_lck_o[0:0]
134182   attribute \src "libresoc.v:45757.3-45766.6"
134183   wire $1\pll_lck_o[0:0]
134184   attribute \src "libresoc.v:45756.17-45756.105"
134185   wire $eq$libresoc.v:45756$1558_Y
134186   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20"
134187   wire \$1
134188   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
134189   wire input 1 \clk_24_i
134190   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11"
134191   wire output 5 \clk_pll_o
134192   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
134193   wire width 2 input 3 \clk_sel_i
134194   attribute \src "libresoc.v:45742.7-45742.15"
134195   wire \initial
134196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
134197   wire output 2 \pll_18_o
134198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
134199   wire output 4 \pll_lck_o
134200   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20"
134201   cell $eq $eq$libresoc.v:45756$1558
134202     parameter \A_SIGNED 0
134203     parameter \A_WIDTH 2
134204     parameter \B_SIGNED 0
134205     parameter \B_WIDTH 2
134206     parameter \Y_WIDTH 1
134207     connect \A \clk_sel_i
134208     connect \B 2'00
134209     connect \Y $eq$libresoc.v:45756$1558_Y
134210   end
134211   attribute \src "libresoc.v:45742.7-45742.20"
134212   process $proc$libresoc.v:45742$1560
134213     assign { } { }
134214     assign $0\initial[0:0] 1'0
134215     sync always
134216       update \initial $0\initial[0:0]
134217     sync init
134218   end
134219   attribute \src "libresoc.v:45757.3-45766.6"
134220   process $proc$libresoc.v:45757$1559
134221     assign { } { }
134222     assign { } { }
134223     assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0]
134224     attribute \src "libresoc.v:45758.5-45758.29"
134225     switch \initial
134226       attribute \src "libresoc.v:45758.9-45758.17"
134227       case 1'1
134228       case
134229     end
134230     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20"
134231     switch \$1
134232       attribute \src "libresoc.v:0.0-0.0"
134233       case 1'1
134234         assign { } { }
134235         assign $1\pll_lck_o[0:0] \clk_24_i
134236       case
134237         assign $1\pll_lck_o[0:0] 1'0
134238     end
134239     sync always
134240       update \pll_lck_o $0\pll_lck_o[0:0]
134241   end
134242   connect \$1 $eq$libresoc.v:45756$1558_Y
134243   connect \pll_18_o \clk_24_i
134244   connect \clk_pll_o \clk_24_i
134245 end
134246 attribute \src "libresoc.v:45773.1-45857.10"
134247 attribute \cells_not_processed 1
134248 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick"
134249 attribute \generator "nMigen"
134250 module \ppick
134251   attribute \src "libresoc.v:45830.17-45830.91"
134252   wire $not$libresoc.v:45830$1561_Y
134253   attribute \src "libresoc.v:45832.18-45832.93"
134254   wire $not$libresoc.v:45832$1563_Y
134255   attribute \src "libresoc.v:45834.18-45834.93"
134256   wire $not$libresoc.v:45834$1565_Y
134257   attribute \src "libresoc.v:45835.17-45835.138"
134258   wire width 8 $not$libresoc.v:45835$1566_Y
134259   attribute \src "libresoc.v:45837.18-45837.93"
134260   wire $not$libresoc.v:45837$1568_Y
134261   attribute \src "libresoc.v:45839.18-45839.93"
134262   wire $not$libresoc.v:45839$1570_Y
134263   attribute \src "libresoc.v:45841.18-45841.93"
134264   wire $not$libresoc.v:45841$1572_Y
134265   attribute \src "libresoc.v:45844.17-45844.91"
134266   wire $not$libresoc.v:45844$1575_Y
134267   attribute \src "libresoc.v:45831.18-45831.116"
134268   wire $reduce_or$libresoc.v:45831$1562_Y
134269   attribute \src "libresoc.v:45833.18-45833.122"
134270   wire $reduce_or$libresoc.v:45833$1564_Y
134271   attribute \src "libresoc.v:45836.18-45836.128"
134272   wire $reduce_or$libresoc.v:45836$1567_Y
134273   attribute \src "libresoc.v:45838.18-45838.134"
134274   wire $reduce_or$libresoc.v:45838$1569_Y
134275   attribute \src "libresoc.v:45840.18-45840.140"
134276   wire $reduce_or$libresoc.v:45840$1571_Y
134277   attribute \src "libresoc.v:45842.18-45842.90"
134278   wire $reduce_or$libresoc.v:45842$1573_Y
134279   attribute \src "libresoc.v:45843.17-45843.103"
134280   wire $reduce_or$libresoc.v:45843$1574_Y
134281   attribute \src "libresoc.v:45845.17-45845.109"
134282   wire $reduce_or$libresoc.v:45845$1576_Y
134283   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
134284   wire width 8 \$1
134285   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134286   wire \$11
134287   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134288   wire \$12
134289   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134290   wire \$15
134291   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134292   wire \$16
134293   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134294   wire \$19
134295   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134296   wire \$20
134297   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134298   wire \$23
134299   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134300   wire \$24
134301   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134302   wire \$27
134303   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134304   wire \$28
134305   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134306   wire \$3
134307   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
134308   wire \$31
134309   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134310   wire \$4
134311   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134312   wire \$7
134313   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134314   wire \$8
134315   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
134316   wire \en_o
134317   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40"
134318   wire width 8 input 2 \i
134319   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49"
134320   wire width 8 \ni
134321   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41"
134322   wire width 8 output 1 \o
134323   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134324   wire \t0
134325   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134326   wire \t1
134327   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134328   wire \t2
134329   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134330   wire \t3
134331   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134332   wire \t4
134333   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134334   wire \t5
134335   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134336   wire \t6
134337   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134338   wire \t7
134339   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134340   cell $not $not$libresoc.v:45830$1561
134341     parameter \A_SIGNED 0
134342     parameter \A_WIDTH 1
134343     parameter \Y_WIDTH 1
134344     connect \A \$8
134345     connect \Y $not$libresoc.v:45830$1561_Y
134346   end
134347   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134348   cell $not $not$libresoc.v:45832$1563
134349     parameter \A_SIGNED 0
134350     parameter \A_WIDTH 1
134351     parameter \Y_WIDTH 1
134352     connect \A \$12
134353     connect \Y $not$libresoc.v:45832$1563_Y
134354   end
134355   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134356   cell $not $not$libresoc.v:45834$1565
134357     parameter \A_SIGNED 0
134358     parameter \A_WIDTH 1
134359     parameter \Y_WIDTH 1
134360     connect \A \$16
134361     connect \Y $not$libresoc.v:45834$1565_Y
134362   end
134363   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
134364   cell $not $not$libresoc.v:45835$1566
134365     parameter \A_SIGNED 0
134366     parameter \A_WIDTH 8
134367     parameter \Y_WIDTH 8
134368     connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
134369     connect \Y $not$libresoc.v:45835$1566_Y
134370   end
134371   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134372   cell $not $not$libresoc.v:45837$1568
134373     parameter \A_SIGNED 0
134374     parameter \A_WIDTH 1
134375     parameter \Y_WIDTH 1
134376     connect \A \$20
134377     connect \Y $not$libresoc.v:45837$1568_Y
134378   end
134379   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134380   cell $not $not$libresoc.v:45839$1570
134381     parameter \A_SIGNED 0
134382     parameter \A_WIDTH 1
134383     parameter \Y_WIDTH 1
134384     connect \A \$24
134385     connect \Y $not$libresoc.v:45839$1570_Y
134386   end
134387   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134388   cell $not $not$libresoc.v:45841$1572
134389     parameter \A_SIGNED 0
134390     parameter \A_WIDTH 1
134391     parameter \Y_WIDTH 1
134392     connect \A \$28
134393     connect \Y $not$libresoc.v:45841$1572_Y
134394   end
134395   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134396   cell $not $not$libresoc.v:45844$1575
134397     parameter \A_SIGNED 0
134398     parameter \A_WIDTH 1
134399     parameter \Y_WIDTH 1
134400     connect \A \$4
134401     connect \Y $not$libresoc.v:45844$1575_Y
134402   end
134403   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134404   cell $reduce_or $reduce_or$libresoc.v:45831$1562
134405     parameter \A_SIGNED 0
134406     parameter \A_WIDTH 4
134407     parameter \Y_WIDTH 1
134408     connect \A { \i [5] \i [6] \i [7] \ni [3] }
134409     connect \Y $reduce_or$libresoc.v:45831$1562_Y
134410   end
134411   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134412   cell $reduce_or $reduce_or$libresoc.v:45833$1564
134413     parameter \A_SIGNED 0
134414     parameter \A_WIDTH 5
134415     parameter \Y_WIDTH 1
134416     connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
134417     connect \Y $reduce_or$libresoc.v:45833$1564_Y
134418   end
134419   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134420   cell $reduce_or $reduce_or$libresoc.v:45836$1567
134421     parameter \A_SIGNED 0
134422     parameter \A_WIDTH 6
134423     parameter \Y_WIDTH 1
134424     connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
134425     connect \Y $reduce_or$libresoc.v:45836$1567_Y
134426   end
134427   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134428   cell $reduce_or $reduce_or$libresoc.v:45838$1569
134429     parameter \A_SIGNED 0
134430     parameter \A_WIDTH 7
134431     parameter \Y_WIDTH 1
134432     connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
134433     connect \Y $reduce_or$libresoc.v:45838$1569_Y
134434   end
134435   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134436   cell $reduce_or $reduce_or$libresoc.v:45840$1571
134437     parameter \A_SIGNED 0
134438     parameter \A_WIDTH 8
134439     parameter \Y_WIDTH 1
134440     connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
134441     connect \Y $reduce_or$libresoc.v:45840$1571_Y
134442   end
134443   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
134444   cell $reduce_or $reduce_or$libresoc.v:45842$1573
134445     parameter \A_SIGNED 0
134446     parameter \A_WIDTH 8
134447     parameter \Y_WIDTH 1
134448     connect \A \o
134449     connect \Y $reduce_or$libresoc.v:45842$1573_Y
134450   end
134451   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134452   cell $reduce_or $reduce_or$libresoc.v:45843$1574
134453     parameter \A_SIGNED 0
134454     parameter \A_WIDTH 2
134455     parameter \Y_WIDTH 1
134456     connect \A { \i [7] \ni [1] }
134457     connect \Y $reduce_or$libresoc.v:45843$1574_Y
134458   end
134459   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134460   cell $reduce_or $reduce_or$libresoc.v:45845$1576
134461     parameter \A_SIGNED 0
134462     parameter \A_WIDTH 3
134463     parameter \Y_WIDTH 1
134464     connect \A { \i [6] \i [7] \ni [2] }
134465     connect \Y $reduce_or$libresoc.v:45845$1576_Y
134466   end
134467   connect \$7 $not$libresoc.v:45830$1561_Y
134468   connect \$12 $reduce_or$libresoc.v:45831$1562_Y
134469   connect \$11 $not$libresoc.v:45832$1563_Y
134470   connect \$16 $reduce_or$libresoc.v:45833$1564_Y
134471   connect \$15 $not$libresoc.v:45834$1565_Y
134472   connect \$1 $not$libresoc.v:45835$1566_Y
134473   connect \$20 $reduce_or$libresoc.v:45836$1567_Y
134474   connect \$19 $not$libresoc.v:45837$1568_Y
134475   connect \$24 $reduce_or$libresoc.v:45838$1569_Y
134476   connect \$23 $not$libresoc.v:45839$1570_Y
134477   connect \$28 $reduce_or$libresoc.v:45840$1571_Y
134478   connect \$27 $not$libresoc.v:45841$1572_Y
134479   connect \$31 $reduce_or$libresoc.v:45842$1573_Y
134480   connect \$4 $reduce_or$libresoc.v:45843$1574_Y
134481   connect \$3 $not$libresoc.v:45844$1575_Y
134482   connect \$8 $reduce_or$libresoc.v:45845$1576_Y
134483   connect \en_o \$31
134484   connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
134485   connect \t7 \$27
134486   connect \t6 \$23
134487   connect \t5 \$19
134488   connect \t4 \$15
134489   connect \t3 \$11
134490   connect \t2 \$7
134491   connect \t1 \$3
134492   connect \t0 \i [7]
134493   connect \ni \$1
134494 end
134495 attribute \src "libresoc.v:45861.1-45945.10"
134496 attribute \cells_not_processed 1
134497 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick"
134498 attribute \generator "nMigen"
134499 module \ppick$1
134500   attribute \src "libresoc.v:45918.17-45918.91"
134501   wire $not$libresoc.v:45918$1577_Y
134502   attribute \src "libresoc.v:45920.18-45920.93"
134503   wire $not$libresoc.v:45920$1579_Y
134504   attribute \src "libresoc.v:45922.18-45922.93"
134505   wire $not$libresoc.v:45922$1581_Y
134506   attribute \src "libresoc.v:45923.17-45923.138"
134507   wire width 8 $not$libresoc.v:45923$1582_Y
134508   attribute \src "libresoc.v:45925.18-45925.93"
134509   wire $not$libresoc.v:45925$1584_Y
134510   attribute \src "libresoc.v:45927.18-45927.93"
134511   wire $not$libresoc.v:45927$1586_Y
134512   attribute \src "libresoc.v:45929.18-45929.93"
134513   wire $not$libresoc.v:45929$1588_Y
134514   attribute \src "libresoc.v:45932.17-45932.91"
134515   wire $not$libresoc.v:45932$1591_Y
134516   attribute \src "libresoc.v:45919.18-45919.116"
134517   wire $reduce_or$libresoc.v:45919$1578_Y
134518   attribute \src "libresoc.v:45921.18-45921.122"
134519   wire $reduce_or$libresoc.v:45921$1580_Y
134520   attribute \src "libresoc.v:45924.18-45924.128"
134521   wire $reduce_or$libresoc.v:45924$1583_Y
134522   attribute \src "libresoc.v:45926.18-45926.134"
134523   wire $reduce_or$libresoc.v:45926$1585_Y
134524   attribute \src "libresoc.v:45928.18-45928.140"
134525   wire $reduce_or$libresoc.v:45928$1587_Y
134526   attribute \src "libresoc.v:45930.18-45930.90"
134527   wire $reduce_or$libresoc.v:45930$1589_Y
134528   attribute \src "libresoc.v:45931.17-45931.103"
134529   wire $reduce_or$libresoc.v:45931$1590_Y
134530   attribute \src "libresoc.v:45933.17-45933.109"
134531   wire $reduce_or$libresoc.v:45933$1592_Y
134532   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
134533   wire width 8 \$1
134534   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134535   wire \$11
134536   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134537   wire \$12
134538   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134539   wire \$15
134540   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134541   wire \$16
134542   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134543   wire \$19
134544   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134545   wire \$20
134546   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134547   wire \$23
134548   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134549   wire \$24
134550   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134551   wire \$27
134552   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134553   wire \$28
134554   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134555   wire \$3
134556   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
134557   wire \$31
134558   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134559   wire \$4
134560   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134561   wire \$7
134562   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134563   wire \$8
134564   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
134565   wire output 1 \en_o
134566   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40"
134567   wire width 8 input 3 \i
134568   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49"
134569   wire width 8 \ni
134570   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41"
134571   wire width 8 output 2 \o
134572   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134573   wire \t0
134574   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134575   wire \t1
134576   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134577   wire \t2
134578   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134579   wire \t3
134580   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134581   wire \t4
134582   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134583   wire \t5
134584   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134585   wire \t6
134586   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
134587   wire \t7
134588   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134589   cell $not $not$libresoc.v:45918$1577
134590     parameter \A_SIGNED 0
134591     parameter \A_WIDTH 1
134592     parameter \Y_WIDTH 1
134593     connect \A \$8
134594     connect \Y $not$libresoc.v:45918$1577_Y
134595   end
134596   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134597   cell $not $not$libresoc.v:45920$1579
134598     parameter \A_SIGNED 0
134599     parameter \A_WIDTH 1
134600     parameter \Y_WIDTH 1
134601     connect \A \$12
134602     connect \Y $not$libresoc.v:45920$1579_Y
134603   end
134604   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134605   cell $not $not$libresoc.v:45922$1581
134606     parameter \A_SIGNED 0
134607     parameter \A_WIDTH 1
134608     parameter \Y_WIDTH 1
134609     connect \A \$16
134610     connect \Y $not$libresoc.v:45922$1581_Y
134611   end
134612   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
134613   cell $not $not$libresoc.v:45923$1582
134614     parameter \A_SIGNED 0
134615     parameter \A_WIDTH 8
134616     parameter \Y_WIDTH 8
134617     connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
134618     connect \Y $not$libresoc.v:45923$1582_Y
134619   end
134620   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134621   cell $not $not$libresoc.v:45925$1584
134622     parameter \A_SIGNED 0
134623     parameter \A_WIDTH 1
134624     parameter \Y_WIDTH 1
134625     connect \A \$20
134626     connect \Y $not$libresoc.v:45925$1584_Y
134627   end
134628   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134629   cell $not $not$libresoc.v:45927$1586
134630     parameter \A_SIGNED 0
134631     parameter \A_WIDTH 1
134632     parameter \Y_WIDTH 1
134633     connect \A \$24
134634     connect \Y $not$libresoc.v:45927$1586_Y
134635   end
134636   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134637   cell $not $not$libresoc.v:45929$1588
134638     parameter \A_SIGNED 0
134639     parameter \A_WIDTH 1
134640     parameter \Y_WIDTH 1
134641     connect \A \$28
134642     connect \Y $not$libresoc.v:45929$1588_Y
134643   end
134644   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134645   cell $not $not$libresoc.v:45932$1591
134646     parameter \A_SIGNED 0
134647     parameter \A_WIDTH 1
134648     parameter \Y_WIDTH 1
134649     connect \A \$4
134650     connect \Y $not$libresoc.v:45932$1591_Y
134651   end
134652   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134653   cell $reduce_or $reduce_or$libresoc.v:45919$1578
134654     parameter \A_SIGNED 0
134655     parameter \A_WIDTH 4
134656     parameter \Y_WIDTH 1
134657     connect \A { \i [5] \i [6] \i [7] \ni [3] }
134658     connect \Y $reduce_or$libresoc.v:45919$1578_Y
134659   end
134660   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134661   cell $reduce_or $reduce_or$libresoc.v:45921$1580
134662     parameter \A_SIGNED 0
134663     parameter \A_WIDTH 5
134664     parameter \Y_WIDTH 1
134665     connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
134666     connect \Y $reduce_or$libresoc.v:45921$1580_Y
134667   end
134668   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134669   cell $reduce_or $reduce_or$libresoc.v:45924$1583
134670     parameter \A_SIGNED 0
134671     parameter \A_WIDTH 6
134672     parameter \Y_WIDTH 1
134673     connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
134674     connect \Y $reduce_or$libresoc.v:45924$1583_Y
134675   end
134676   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134677   cell $reduce_or $reduce_or$libresoc.v:45926$1585
134678     parameter \A_SIGNED 0
134679     parameter \A_WIDTH 7
134680     parameter \Y_WIDTH 1
134681     connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
134682     connect \Y $reduce_or$libresoc.v:45926$1585_Y
134683   end
134684   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134685   cell $reduce_or $reduce_or$libresoc.v:45928$1587
134686     parameter \A_SIGNED 0
134687     parameter \A_WIDTH 8
134688     parameter \Y_WIDTH 1
134689     connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
134690     connect \Y $reduce_or$libresoc.v:45928$1587_Y
134691   end
134692   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
134693   cell $reduce_or $reduce_or$libresoc.v:45930$1589
134694     parameter \A_SIGNED 0
134695     parameter \A_WIDTH 8
134696     parameter \Y_WIDTH 1
134697     connect \A \o
134698     connect \Y $reduce_or$libresoc.v:45930$1589_Y
134699   end
134700   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134701   cell $reduce_or $reduce_or$libresoc.v:45931$1590
134702     parameter \A_SIGNED 0
134703     parameter \A_WIDTH 2
134704     parameter \Y_WIDTH 1
134705     connect \A { \i [7] \ni [1] }
134706     connect \Y $reduce_or$libresoc.v:45931$1590_Y
134707   end
134708   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
134709   cell $reduce_or $reduce_or$libresoc.v:45933$1592
134710     parameter \A_SIGNED 0
134711     parameter \A_WIDTH 3
134712     parameter \Y_WIDTH 1
134713     connect \A { \i [6] \i [7] \ni [2] }
134714     connect \Y $reduce_or$libresoc.v:45933$1592_Y
134715   end
134716   connect \$7 $not$libresoc.v:45918$1577_Y
134717   connect \$12 $reduce_or$libresoc.v:45919$1578_Y
134718   connect \$11 $not$libresoc.v:45920$1579_Y
134719   connect \$16 $reduce_or$libresoc.v:45921$1580_Y
134720   connect \$15 $not$libresoc.v:45922$1581_Y
134721   connect \$1 $not$libresoc.v:45923$1582_Y
134722   connect \$20 $reduce_or$libresoc.v:45924$1583_Y
134723   connect \$19 $not$libresoc.v:45925$1584_Y
134724   connect \$24 $reduce_or$libresoc.v:45926$1585_Y
134725   connect \$23 $not$libresoc.v:45927$1586_Y
134726   connect \$28 $reduce_or$libresoc.v:45928$1587_Y
134727   connect \$27 $not$libresoc.v:45929$1588_Y
134728   connect \$31 $reduce_or$libresoc.v:45930$1589_Y
134729   connect \$4 $reduce_or$libresoc.v:45931$1590_Y
134730   connect \$3 $not$libresoc.v:45932$1591_Y
134731   connect \$8 $reduce_or$libresoc.v:45933$1592_Y
134732   connect \en_o \$31
134733   connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
134734   connect \t7 \$27
134735   connect \t6 \$23
134736   connect \t5 \$19
134737   connect \t4 \$15
134738   connect \t3 \$11
134739   connect \t2 \$7
134740   connect \t1 \$3
134741   connect \t0 \i [7]
134742   connect \ni \$1
134743 end
134744 attribute \src "libresoc.v:45949.1-46764.10"
134745 attribute \cells_not_processed 1
134746 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap"
134747 attribute \generator "nMigen"
134748 module \sprmap
134749   attribute \src "libresoc.v:46076.3-46106.6"
134750   wire width 3 $0\fast_o[2:0]
134751   attribute \src "libresoc.v:46107.3-46137.6"
134752   wire $0\fast_o_ok[0:0]
134753   attribute \src "libresoc.v:45950.7-45950.20"
134754   wire $0\initial[0:0]
134755   attribute \src "libresoc.v:46138.3-46450.6"
134756   wire width 10 $0\spr_o[9:0]
134757   attribute \src "libresoc.v:46451.3-46763.6"
134758   wire $0\spr_o_ok[0:0]
134759   attribute \src "libresoc.v:46076.3-46106.6"
134760   wire width 3 $1\fast_o[2:0]
134761   attribute \src "libresoc.v:46107.3-46137.6"
134762   wire $1\fast_o_ok[0:0]
134763   attribute \src "libresoc.v:46138.3-46450.6"
134764   wire width 10 $1\spr_o[9:0]
134765   attribute \src "libresoc.v:46451.3-46763.6"
134766   wire $1\spr_o_ok[0:0]
134767   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
134768   wire width 3 output 3 \fast_o
134769   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
134770   wire output 4 \fast_o_ok
134771   attribute \src "libresoc.v:45950.7-45950.15"
134772   wire \initial
134773   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
134774   wire width 10 input 5 \spr_i
134775   attribute \enum_base_type "SPR"
134776   attribute \enum_value_0000000001 "XER"
134777   attribute \enum_value_0000000011 "DSCR"
134778   attribute \enum_value_0000001000 "LR"
134779   attribute \enum_value_0000001001 "CTR"
134780   attribute \enum_value_0000001101 "AMR"
134781   attribute \enum_value_0000010001 "DSCR_priv"
134782   attribute \enum_value_0000010010 "DSISR"
134783   attribute \enum_value_0000010011 "DAR"
134784   attribute \enum_value_0000010110 "DEC"
134785   attribute \enum_value_0000011010 "SRR0"
134786   attribute \enum_value_0000011011 "SRR1"
134787   attribute \enum_value_0000011100 "CFAR"
134788   attribute \enum_value_0000011101 "AMR_priv"
134789   attribute \enum_value_0000110000 "PIDR"
134790   attribute \enum_value_0000111101 "IAMR"
134791   attribute \enum_value_0010000000 "TFHAR"
134792   attribute \enum_value_0010000001 "TFIAR"
134793   attribute \enum_value_0010000010 "TEXASR"
134794   attribute \enum_value_0010000011 "TEXASRU"
134795   attribute \enum_value_0010001000 "CTRL"
134796   attribute \enum_value_0010010000 "TIDR"
134797   attribute \enum_value_0010011000 "CTRL_priv"
134798   attribute \enum_value_0010011001 "FSCR"
134799   attribute \enum_value_0010011101 "UAMOR"
134800   attribute \enum_value_0010011110 "GSR"
134801   attribute \enum_value_0010011111 "PSPB"
134802   attribute \enum_value_0010110000 "DPDES"
134803   attribute \enum_value_0010110100 "DAWR0"
134804   attribute \enum_value_0010111010 "RPR"
134805   attribute \enum_value_0010111011 "CIABR"
134806   attribute \enum_value_0010111100 "DAWRX0"
134807   attribute \enum_value_0010111110 "HFSCR"
134808   attribute \enum_value_0100000000 "VRSAVE"
134809   attribute \enum_value_0100000011 "SPRG3"
134810   attribute \enum_value_0100001100 "TB"
134811   attribute \enum_value_0100001101 "TBU"
134812   attribute \enum_value_0100010000 "SPRG0_priv"
134813   attribute \enum_value_0100010001 "SPRG1_priv"
134814   attribute \enum_value_0100010010 "SPRG2_priv"
134815   attribute \enum_value_0100010011 "SPRG3_priv"
134816   attribute \enum_value_0100011011 "CIR"
134817   attribute \enum_value_0100011100 "TBL"
134818   attribute \enum_value_0100011101 "TBU_hypv"
134819   attribute \enum_value_0100011110 "TBU40"
134820   attribute \enum_value_0100011111 "PVR"
134821   attribute \enum_value_0100110000 "HSPRG0"
134822   attribute \enum_value_0100110001 "HSPRG1"
134823   attribute \enum_value_0100110010 "HDSISR"
134824   attribute \enum_value_0100110011 "HDAR"
134825   attribute \enum_value_0100110100 "SPURR"
134826   attribute \enum_value_0100110101 "PURR"
134827   attribute \enum_value_0100110110 "HDEC"
134828   attribute \enum_value_0100111001 "HRMOR"
134829   attribute \enum_value_0100111010 "HSRR0"
134830   attribute \enum_value_0100111011 "HSRR1"
134831   attribute \enum_value_0100111110 "LPCR"
134832   attribute \enum_value_0100111111 "LPIDR"
134833   attribute \enum_value_0101010000 "HMER"
134834   attribute \enum_value_0101010001 "HMEER"
134835   attribute \enum_value_0101010010 "PCR"
134836   attribute \enum_value_0101010011 "HEIR"
134837   attribute \enum_value_0101011101 "AMOR"
134838   attribute \enum_value_0110111110 "TIR"
134839   attribute \enum_value_0111010000 "PTCR"
134840   attribute \enum_value_1100000000 "SIER"
134841   attribute \enum_value_1100000001 "MMCR2"
134842   attribute \enum_value_1100000010 "MMCRA"
134843   attribute \enum_value_1100000011 "PMC1"
134844   attribute \enum_value_1100000100 "PMC2"
134845   attribute \enum_value_1100000101 "PMC3"
134846   attribute \enum_value_1100000110 "PMC4"
134847   attribute \enum_value_1100000111 "PMC5"
134848   attribute \enum_value_1100001000 "PMC6"
134849   attribute \enum_value_1100001011 "MMCR0"
134850   attribute \enum_value_1100001100 "SIAR"
134851   attribute \enum_value_1100001101 "SDAR"
134852   attribute \enum_value_1100001110 "MMCR1"
134853   attribute \enum_value_1100010000 "SIER_priv"
134854   attribute \enum_value_1100010001 "MMCR2_priv"
134855   attribute \enum_value_1100010010 "MMCRA_priv"
134856   attribute \enum_value_1100010011 "PMC1_priv"
134857   attribute \enum_value_1100010100 "PMC2_priv"
134858   attribute \enum_value_1100010101 "PMC3_priv"
134859   attribute \enum_value_1100010110 "PMC4_priv"
134860   attribute \enum_value_1100010111 "PMC5_priv"
134861   attribute \enum_value_1100011000 "PMC6_priv"
134862   attribute \enum_value_1100011011 "MMCR0_priv"
134863   attribute \enum_value_1100011100 "SIAR_priv"
134864   attribute \enum_value_1100011101 "SDAR_priv"
134865   attribute \enum_value_1100011110 "MMCR1_priv"
134866   attribute \enum_value_1100100000 "BESCRS"
134867   attribute \enum_value_1100100001 "BESCRSU"
134868   attribute \enum_value_1100100010 "BESCRR"
134869   attribute \enum_value_1100100011 "BESCRRU"
134870   attribute \enum_value_1100100100 "EBBHR"
134871   attribute \enum_value_1100100101 "EBBRR"
134872   attribute \enum_value_1100100110 "BESCR"
134873   attribute \enum_value_1100101000 "reserved808"
134874   attribute \enum_value_1100101001 "reserved809"
134875   attribute \enum_value_1100101010 "reserved810"
134876   attribute \enum_value_1100101011 "reserved811"
134877   attribute \enum_value_1100101111 "TAR"
134878   attribute \enum_value_1100110000 "ASDR"
134879   attribute \enum_value_1100110111 "PSSCR"
134880   attribute \enum_value_1101010000 "IC"
134881   attribute \enum_value_1101010001 "VTB"
134882   attribute \enum_value_1101010111 "PSSCR_hypv"
134883   attribute \enum_value_1110000000 "PPR"
134884   attribute \enum_value_1110000010 "PPR32"
134885   attribute \enum_value_1111111111 "PIR"
134886   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
134887   wire width 10 output 1 \spr_o
134888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
134889   wire output 2 \spr_o_ok
134890   attribute \src "libresoc.v:45950.7-45950.20"
134891   process $proc$libresoc.v:45950$1597
134892     assign { } { }
134893     assign $0\initial[0:0] 1'0
134894     sync always
134895       update \initial $0\initial[0:0]
134896     sync init
134897   end
134898   attribute \src "libresoc.v:46076.3-46106.6"
134899   process $proc$libresoc.v:46076$1593
134900     assign { } { }
134901     assign { } { }
134902     assign $0\fast_o[2:0] $1\fast_o[2:0]
134903     attribute \src "libresoc.v:46077.5-46077.29"
134904     switch \initial
134905       attribute \src "libresoc.v:46077.9-46077.17"
134906       case 1'1
134907       case
134908     end
134909     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
134910     switch \spr_i
134911       attribute \src "libresoc.v:0.0-0.0"
134912       case 10'0000000001
134913         assign { } { }
134914         assign $1\fast_o[2:0] 3'101
134915       attribute \src "libresoc.v:0.0-0.0"
134916       case 10'0000001000
134917         assign { } { }
134918         assign $1\fast_o[2:0] 3'001
134919       attribute \src "libresoc.v:0.0-0.0"
134920       case 10'0000001001
134921         assign { } { }
134922         assign $1\fast_o[2:0] 3'000
134923       attribute \src "libresoc.v:0.0-0.0"
134924       case 10'0000010110
134925         assign { } { }
134926         assign $1\fast_o[2:0] 3'110
134927       attribute \src "libresoc.v:0.0-0.0"
134928       case 10'0000011010
134929         assign { } { }
134930         assign $1\fast_o[2:0] 3'011
134931       attribute \src "libresoc.v:0.0-0.0"
134932       case 10'0000011011
134933         assign { } { }
134934         assign $1\fast_o[2:0] 3'100
134935       attribute \src "libresoc.v:0.0-0.0"
134936       case 10'0100001100
134937         assign { } { }
134938         assign $1\fast_o[2:0] 3'111
134939       attribute \src "libresoc.v:0.0-0.0"
134940       case 10'1100101111
134941         assign { } { }
134942         assign $1\fast_o[2:0] 3'010
134943       case
134944         assign $1\fast_o[2:0] 3'000
134945     end
134946     sync always
134947       update \fast_o $0\fast_o[2:0]
134948   end
134949   attribute \src "libresoc.v:46107.3-46137.6"
134950   process $proc$libresoc.v:46107$1594
134951     assign { } { }
134952     assign { } { }
134953     assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
134954     attribute \src "libresoc.v:46108.5-46108.29"
134955     switch \initial
134956       attribute \src "libresoc.v:46108.9-46108.17"
134957       case 1'1
134958       case
134959     end
134960     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
134961     switch \spr_i
134962       attribute \src "libresoc.v:0.0-0.0"
134963       case 10'0000000001
134964         assign { } { }
134965         assign $1\fast_o_ok[0:0] 1'1
134966       attribute \src "libresoc.v:0.0-0.0"
134967       case 10'0000001000
134968         assign { } { }
134969         assign $1\fast_o_ok[0:0] 1'1
134970       attribute \src "libresoc.v:0.0-0.0"
134971       case 10'0000001001
134972         assign { } { }
134973         assign $1\fast_o_ok[0:0] 1'1
134974       attribute \src "libresoc.v:0.0-0.0"
134975       case 10'0000010110
134976         assign { } { }
134977         assign $1\fast_o_ok[0:0] 1'1
134978       attribute \src "libresoc.v:0.0-0.0"
134979       case 10'0000011010
134980         assign { } { }
134981         assign $1\fast_o_ok[0:0] 1'1
134982       attribute \src "libresoc.v:0.0-0.0"
134983       case 10'0000011011
134984         assign { } { }
134985         assign $1\fast_o_ok[0:0] 1'1
134986       attribute \src "libresoc.v:0.0-0.0"
134987       case 10'0100001100
134988         assign { } { }
134989         assign $1\fast_o_ok[0:0] 1'1
134990       attribute \src "libresoc.v:0.0-0.0"
134991       case 10'1100101111
134992         assign { } { }
134993         assign $1\fast_o_ok[0:0] 1'1
134994       case
134995         assign $1\fast_o_ok[0:0] 1'0
134996     end
134997     sync always
134998       update \fast_o_ok $0\fast_o_ok[0:0]
134999   end
135000   attribute \src "libresoc.v:46138.3-46450.6"
135001   process $proc$libresoc.v:46138$1595
135002     assign { } { }
135003     assign { } { }
135004     assign $0\spr_o[9:0] $1\spr_o[9:0]
135005     attribute \src "libresoc.v:46139.5-46139.29"
135006     switch \initial
135007       attribute \src "libresoc.v:46139.9-46139.17"
135008       case 1'1
135009       case
135010     end
135011     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
135012     switch \spr_i
135013       attribute \src "libresoc.v:0.0-0.0"
135014       case 10'0000000011
135015         assign { } { }
135016         assign $1\spr_o[9:0] 10'0000000001
135017       attribute \src "libresoc.v:0.0-0.0"
135018       case 10'0000001101
135019         assign { } { }
135020         assign $1\spr_o[9:0] 10'0000000100
135021       attribute \src "libresoc.v:0.0-0.0"
135022       case 10'0000010001
135023         assign { } { }
135024         assign $1\spr_o[9:0] 10'0000000101
135025       attribute \src "libresoc.v:0.0-0.0"
135026       case 10'0000010010
135027         assign { } { }
135028         assign $1\spr_o[9:0] 10'0000000110
135029       attribute \src "libresoc.v:0.0-0.0"
135030       case 10'0000010011
135031         assign { } { }
135032         assign $1\spr_o[9:0] 10'0000000111
135033       attribute \src "libresoc.v:0.0-0.0"
135034       case 10'0000011100
135035         assign { } { }
135036         assign $1\spr_o[9:0] 10'0000001011
135037       attribute \src "libresoc.v:0.0-0.0"
135038       case 10'0000011101
135039         assign { } { }
135040         assign $1\spr_o[9:0] 10'0000001100
135041       attribute \src "libresoc.v:0.0-0.0"
135042       case 10'0000110000
135043         assign { } { }
135044         assign $1\spr_o[9:0] 10'0000001101
135045       attribute \src "libresoc.v:0.0-0.0"
135046       case 10'0000111101
135047         assign { } { }
135048         assign $1\spr_o[9:0] 10'0000001110
135049       attribute \src "libresoc.v:0.0-0.0"
135050       case 10'0010000000
135051         assign { } { }
135052         assign $1\spr_o[9:0] 10'0000001111
135053       attribute \src "libresoc.v:0.0-0.0"
135054       case 10'0010000001
135055         assign { } { }
135056         assign $1\spr_o[9:0] 10'0000010000
135057       attribute \src "libresoc.v:0.0-0.0"
135058       case 10'0010000010
135059         assign { } { }
135060         assign $1\spr_o[9:0] 10'0000010001
135061       attribute \src "libresoc.v:0.0-0.0"
135062       case 10'0010000011
135063         assign { } { }
135064         assign $1\spr_o[9:0] 10'0000010010
135065       attribute \src "libresoc.v:0.0-0.0"
135066       case 10'0010001000
135067         assign { } { }
135068         assign $1\spr_o[9:0] 10'0000010011
135069       attribute \src "libresoc.v:0.0-0.0"
135070       case 10'0010010000
135071         assign { } { }
135072         assign $1\spr_o[9:0] 10'0000010100
135073       attribute \src "libresoc.v:0.0-0.0"
135074       case 10'0010011000
135075         assign { } { }
135076         assign $1\spr_o[9:0] 10'0000010101
135077       attribute \src "libresoc.v:0.0-0.0"
135078       case 10'0010011001
135079         assign { } { }
135080         assign $1\spr_o[9:0] 10'0000010110
135081       attribute \src "libresoc.v:0.0-0.0"
135082       case 10'0010011101
135083         assign { } { }
135084         assign $1\spr_o[9:0] 10'0000010111
135085       attribute \src "libresoc.v:0.0-0.0"
135086       case 10'0010011110
135087         assign { } { }
135088         assign $1\spr_o[9:0] 10'0000011000
135089       attribute \src "libresoc.v:0.0-0.0"
135090       case 10'0010011111
135091         assign { } { }
135092         assign $1\spr_o[9:0] 10'0000011001
135093       attribute \src "libresoc.v:0.0-0.0"
135094       case 10'0010110000
135095         assign { } { }
135096         assign $1\spr_o[9:0] 10'0000011010
135097       attribute \src "libresoc.v:0.0-0.0"
135098       case 10'0010110100
135099         assign { } { }
135100         assign $1\spr_o[9:0] 10'0000011011
135101       attribute \src "libresoc.v:0.0-0.0"
135102       case 10'0010111010
135103         assign { } { }
135104         assign $1\spr_o[9:0] 10'0000011100
135105       attribute \src "libresoc.v:0.0-0.0"
135106       case 10'0010111011
135107         assign { } { }
135108         assign $1\spr_o[9:0] 10'0000011101
135109       attribute \src "libresoc.v:0.0-0.0"
135110       case 10'0010111100
135111         assign { } { }
135112         assign $1\spr_o[9:0] 10'0000011110
135113       attribute \src "libresoc.v:0.0-0.0"
135114       case 10'0010111110
135115         assign { } { }
135116         assign $1\spr_o[9:0] 10'0000011111
135117       attribute \src "libresoc.v:0.0-0.0"
135118       case 10'0100000000
135119         assign { } { }
135120         assign $1\spr_o[9:0] 10'0000100000
135121       attribute \src "libresoc.v:0.0-0.0"
135122       case 10'0100000011
135123         assign { } { }
135124         assign $1\spr_o[9:0] 10'0000100001
135125       attribute \src "libresoc.v:0.0-0.0"
135126       case 10'0100001101
135127         assign { } { }
135128         assign $1\spr_o[9:0] 10'0000100011
135129       attribute \src "libresoc.v:0.0-0.0"
135130       case 10'0100010000
135131         assign { } { }
135132         assign $1\spr_o[9:0] 10'0000100100
135133       attribute \src "libresoc.v:0.0-0.0"
135134       case 10'0100010001
135135         assign { } { }
135136         assign $1\spr_o[9:0] 10'0000100101
135137       attribute \src "libresoc.v:0.0-0.0"
135138       case 10'0100010010
135139         assign { } { }
135140         assign $1\spr_o[9:0] 10'0000100110
135141       attribute \src "libresoc.v:0.0-0.0"
135142       case 10'0100010011
135143         assign { } { }
135144         assign $1\spr_o[9:0] 10'0000100111
135145       attribute \src "libresoc.v:0.0-0.0"
135146       case 10'0100011011
135147         assign { } { }
135148         assign $1\spr_o[9:0] 10'0000101000
135149       attribute \src "libresoc.v:0.0-0.0"
135150       case 10'0100011100
135151         assign { } { }
135152         assign $1\spr_o[9:0] 10'0000101001
135153       attribute \src "libresoc.v:0.0-0.0"
135154       case 10'0100011101
135155         assign { } { }
135156         assign $1\spr_o[9:0] 10'0000101010
135157       attribute \src "libresoc.v:0.0-0.0"
135158       case 10'0100011110
135159         assign { } { }
135160         assign $1\spr_o[9:0] 10'0000101011
135161       attribute \src "libresoc.v:0.0-0.0"
135162       case 10'0100011111
135163         assign { } { }
135164         assign $1\spr_o[9:0] 10'0000101100
135165       attribute \src "libresoc.v:0.0-0.0"
135166       case 10'0100110000
135167         assign { } { }
135168         assign $1\spr_o[9:0] 10'0000101101
135169       attribute \src "libresoc.v:0.0-0.0"
135170       case 10'0100110001
135171         assign { } { }
135172         assign $1\spr_o[9:0] 10'0000101110
135173       attribute \src "libresoc.v:0.0-0.0"
135174       case 10'0100110010
135175         assign { } { }
135176         assign $1\spr_o[9:0] 10'0000101111
135177       attribute \src "libresoc.v:0.0-0.0"
135178       case 10'0100110011
135179         assign { } { }
135180         assign $1\spr_o[9:0] 10'0000110000
135181       attribute \src "libresoc.v:0.0-0.0"
135182       case 10'0100110100
135183         assign { } { }
135184         assign $1\spr_o[9:0] 10'0000110001
135185       attribute \src "libresoc.v:0.0-0.0"
135186       case 10'0100110101
135187         assign { } { }
135188         assign $1\spr_o[9:0] 10'0000110010
135189       attribute \src "libresoc.v:0.0-0.0"
135190       case 10'0100110110
135191         assign { } { }
135192         assign $1\spr_o[9:0] 10'0000110011
135193       attribute \src "libresoc.v:0.0-0.0"
135194       case 10'0100111001
135195         assign { } { }
135196         assign $1\spr_o[9:0] 10'0000110100
135197       attribute \src "libresoc.v:0.0-0.0"
135198       case 10'0100111010
135199         assign { } { }
135200         assign $1\spr_o[9:0] 10'0000110101
135201       attribute \src "libresoc.v:0.0-0.0"
135202       case 10'0100111011
135203         assign { } { }
135204         assign $1\spr_o[9:0] 10'0000110110
135205       attribute \src "libresoc.v:0.0-0.0"
135206       case 10'0100111110
135207         assign { } { }
135208         assign $1\spr_o[9:0] 10'0000110111
135209       attribute \src "libresoc.v:0.0-0.0"
135210       case 10'0100111111
135211         assign { } { }
135212         assign $1\spr_o[9:0] 10'0000111000
135213       attribute \src "libresoc.v:0.0-0.0"
135214       case 10'0101010000
135215         assign { } { }
135216         assign $1\spr_o[9:0] 10'0000111001
135217       attribute \src "libresoc.v:0.0-0.0"
135218       case 10'0101010001
135219         assign { } { }
135220         assign $1\spr_o[9:0] 10'0000111010
135221       attribute \src "libresoc.v:0.0-0.0"
135222       case 10'0101010010
135223         assign { } { }
135224         assign $1\spr_o[9:0] 10'0000111011
135225       attribute \src "libresoc.v:0.0-0.0"
135226       case 10'0101010011
135227         assign { } { }
135228         assign $1\spr_o[9:0] 10'0000111100
135229       attribute \src "libresoc.v:0.0-0.0"
135230       case 10'0101011101
135231         assign { } { }
135232         assign $1\spr_o[9:0] 10'0000111101
135233       attribute \src "libresoc.v:0.0-0.0"
135234       case 10'0110111110
135235         assign { } { }
135236         assign $1\spr_o[9:0] 10'0000111110
135237       attribute \src "libresoc.v:0.0-0.0"
135238       case 10'0111010000
135239         assign { } { }
135240         assign $1\spr_o[9:0] 10'0000111111
135241       attribute \src "libresoc.v:0.0-0.0"
135242       case 10'1100000000
135243         assign { } { }
135244         assign $1\spr_o[9:0] 10'0001000000
135245       attribute \src "libresoc.v:0.0-0.0"
135246       case 10'1100000001
135247         assign { } { }
135248         assign $1\spr_o[9:0] 10'0001000001
135249       attribute \src "libresoc.v:0.0-0.0"
135250       case 10'1100000010
135251         assign { } { }
135252         assign $1\spr_o[9:0] 10'0001000010
135253       attribute \src "libresoc.v:0.0-0.0"
135254       case 10'1100000011
135255         assign { } { }
135256         assign $1\spr_o[9:0] 10'0001000011
135257       attribute \src "libresoc.v:0.0-0.0"
135258       case 10'1100000100
135259         assign { } { }
135260         assign $1\spr_o[9:0] 10'0001000100
135261       attribute \src "libresoc.v:0.0-0.0"
135262       case 10'1100000101
135263         assign { } { }
135264         assign $1\spr_o[9:0] 10'0001000101
135265       attribute \src "libresoc.v:0.0-0.0"
135266       case 10'1100000110
135267         assign { } { }
135268         assign $1\spr_o[9:0] 10'0001000110
135269       attribute \src "libresoc.v:0.0-0.0"
135270       case 10'1100000111
135271         assign { } { }
135272         assign $1\spr_o[9:0] 10'0001000111
135273       attribute \src "libresoc.v:0.0-0.0"
135274       case 10'1100001000
135275         assign { } { }
135276         assign $1\spr_o[9:0] 10'0001001000
135277       attribute \src "libresoc.v:0.0-0.0"
135278       case 10'1100001011
135279         assign { } { }
135280         assign $1\spr_o[9:0] 10'0001001001
135281       attribute \src "libresoc.v:0.0-0.0"
135282       case 10'1100001100
135283         assign { } { }
135284         assign $1\spr_o[9:0] 10'0001001010
135285       attribute \src "libresoc.v:0.0-0.0"
135286       case 10'1100001101
135287         assign { } { }
135288         assign $1\spr_o[9:0] 10'0001001011
135289       attribute \src "libresoc.v:0.0-0.0"
135290       case 10'1100001110
135291         assign { } { }
135292         assign $1\spr_o[9:0] 10'0001001100
135293       attribute \src "libresoc.v:0.0-0.0"
135294       case 10'1100010000
135295         assign { } { }
135296         assign $1\spr_o[9:0] 10'0001001101
135297       attribute \src "libresoc.v:0.0-0.0"
135298       case 10'1100010001
135299         assign { } { }
135300         assign $1\spr_o[9:0] 10'0001001110
135301       attribute \src "libresoc.v:0.0-0.0"
135302       case 10'1100010010
135303         assign { } { }
135304         assign $1\spr_o[9:0] 10'0001001111
135305       attribute \src "libresoc.v:0.0-0.0"
135306       case 10'1100010011
135307         assign { } { }
135308         assign $1\spr_o[9:0] 10'0001010000
135309       attribute \src "libresoc.v:0.0-0.0"
135310       case 10'1100010100
135311         assign { } { }
135312         assign $1\spr_o[9:0] 10'0001010001
135313       attribute \src "libresoc.v:0.0-0.0"
135314       case 10'1100010101
135315         assign { } { }
135316         assign $1\spr_o[9:0] 10'0001010010
135317       attribute \src "libresoc.v:0.0-0.0"
135318       case 10'1100010110
135319         assign { } { }
135320         assign $1\spr_o[9:0] 10'0001010011
135321       attribute \src "libresoc.v:0.0-0.0"
135322       case 10'1100010111
135323         assign { } { }
135324         assign $1\spr_o[9:0] 10'0001010100
135325       attribute \src "libresoc.v:0.0-0.0"
135326       case 10'1100011000
135327         assign { } { }
135328         assign $1\spr_o[9:0] 10'0001010101
135329       attribute \src "libresoc.v:0.0-0.0"
135330       case 10'1100011011
135331         assign { } { }
135332         assign $1\spr_o[9:0] 10'0001010110
135333       attribute \src "libresoc.v:0.0-0.0"
135334       case 10'1100011100
135335         assign { } { }
135336         assign $1\spr_o[9:0] 10'0001010111
135337       attribute \src "libresoc.v:0.0-0.0"
135338       case 10'1100011101
135339         assign { } { }
135340         assign $1\spr_o[9:0] 10'0001011000
135341       attribute \src "libresoc.v:0.0-0.0"
135342       case 10'1100011110
135343         assign { } { }
135344         assign $1\spr_o[9:0] 10'0001011001
135345       attribute \src "libresoc.v:0.0-0.0"
135346       case 10'1100100000
135347         assign { } { }
135348         assign $1\spr_o[9:0] 10'0001011010
135349       attribute \src "libresoc.v:0.0-0.0"
135350       case 10'1100100001
135351         assign { } { }
135352         assign $1\spr_o[9:0] 10'0001011011
135353       attribute \src "libresoc.v:0.0-0.0"
135354       case 10'1100100010
135355         assign { } { }
135356         assign $1\spr_o[9:0] 10'0001011100
135357       attribute \src "libresoc.v:0.0-0.0"
135358       case 10'1100100011
135359         assign { } { }
135360         assign $1\spr_o[9:0] 10'0001011101
135361       attribute \src "libresoc.v:0.0-0.0"
135362       case 10'1100100100
135363         assign { } { }
135364         assign $1\spr_o[9:0] 10'0001011110
135365       attribute \src "libresoc.v:0.0-0.0"
135366       case 10'1100100101
135367         assign { } { }
135368         assign $1\spr_o[9:0] 10'0001011111
135369       attribute \src "libresoc.v:0.0-0.0"
135370       case 10'1100100110
135371         assign { } { }
135372         assign $1\spr_o[9:0] 10'0001100000
135373       attribute \src "libresoc.v:0.0-0.0"
135374       case 10'1100101000
135375         assign { } { }
135376         assign $1\spr_o[9:0] 10'0001100001
135377       attribute \src "libresoc.v:0.0-0.0"
135378       case 10'1100101001
135379         assign { } { }
135380         assign $1\spr_o[9:0] 10'0001100010
135381       attribute \src "libresoc.v:0.0-0.0"
135382       case 10'1100101010
135383         assign { } { }
135384         assign $1\spr_o[9:0] 10'0001100011
135385       attribute \src "libresoc.v:0.0-0.0"
135386       case 10'1100101011
135387         assign { } { }
135388         assign $1\spr_o[9:0] 10'0001100100
135389       attribute \src "libresoc.v:0.0-0.0"
135390       case 10'1100110000
135391         assign { } { }
135392         assign $1\spr_o[9:0] 10'0001100110
135393       attribute \src "libresoc.v:0.0-0.0"
135394       case 10'1100110111
135395         assign { } { }
135396         assign $1\spr_o[9:0] 10'0001100111
135397       attribute \src "libresoc.v:0.0-0.0"
135398       case 10'1101010000
135399         assign { } { }
135400         assign $1\spr_o[9:0] 10'0001101000
135401       attribute \src "libresoc.v:0.0-0.0"
135402       case 10'1101010001
135403         assign { } { }
135404         assign $1\spr_o[9:0] 10'0001101001
135405       attribute \src "libresoc.v:0.0-0.0"
135406       case 10'1101010111
135407         assign { } { }
135408         assign $1\spr_o[9:0] 10'0001101010
135409       attribute \src "libresoc.v:0.0-0.0"
135410       case 10'1110000000
135411         assign { } { }
135412         assign $1\spr_o[9:0] 10'0001101011
135413       attribute \src "libresoc.v:0.0-0.0"
135414       case 10'1110000010
135415         assign { } { }
135416         assign $1\spr_o[9:0] 10'0001101100
135417       attribute \src "libresoc.v:0.0-0.0"
135418       case 10'1111111111
135419         assign { } { }
135420         assign $1\spr_o[9:0] 10'0001101101
135421       case
135422         assign $1\spr_o[9:0] 10'0000000000
135423     end
135424     sync always
135425       update \spr_o $0\spr_o[9:0]
135426   end
135427   attribute \src "libresoc.v:46451.3-46763.6"
135428   process $proc$libresoc.v:46451$1596
135429     assign { } { }
135430     assign { } { }
135431     assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
135432     attribute \src "libresoc.v:46452.5-46452.29"
135433     switch \initial
135434       attribute \src "libresoc.v:46452.9-46452.17"
135435       case 1'1
135436       case
135437     end
135438     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
135439     switch \spr_i
135440       attribute \src "libresoc.v:0.0-0.0"
135441       case 10'0000000011
135442         assign { } { }
135443         assign $1\spr_o_ok[0:0] 1'1
135444       attribute \src "libresoc.v:0.0-0.0"
135445       case 10'0000001101
135446         assign { } { }
135447         assign $1\spr_o_ok[0:0] 1'1
135448       attribute \src "libresoc.v:0.0-0.0"
135449       case 10'0000010001
135450         assign { } { }
135451         assign $1\spr_o_ok[0:0] 1'1
135452       attribute \src "libresoc.v:0.0-0.0"
135453       case 10'0000010010
135454         assign { } { }
135455         assign $1\spr_o_ok[0:0] 1'1
135456       attribute \src "libresoc.v:0.0-0.0"
135457       case 10'0000010011
135458         assign { } { }
135459         assign $1\spr_o_ok[0:0] 1'1
135460       attribute \src "libresoc.v:0.0-0.0"
135461       case 10'0000011100
135462         assign { } { }
135463         assign $1\spr_o_ok[0:0] 1'1
135464       attribute \src "libresoc.v:0.0-0.0"
135465       case 10'0000011101
135466         assign { } { }
135467         assign $1\spr_o_ok[0:0] 1'1
135468       attribute \src "libresoc.v:0.0-0.0"
135469       case 10'0000110000
135470         assign { } { }
135471         assign $1\spr_o_ok[0:0] 1'1
135472       attribute \src "libresoc.v:0.0-0.0"
135473       case 10'0000111101
135474         assign { } { }
135475         assign $1\spr_o_ok[0:0] 1'1
135476       attribute \src "libresoc.v:0.0-0.0"
135477       case 10'0010000000
135478         assign { } { }
135479         assign $1\spr_o_ok[0:0] 1'1
135480       attribute \src "libresoc.v:0.0-0.0"
135481       case 10'0010000001
135482         assign { } { }
135483         assign $1\spr_o_ok[0:0] 1'1
135484       attribute \src "libresoc.v:0.0-0.0"
135485       case 10'0010000010
135486         assign { } { }
135487         assign $1\spr_o_ok[0:0] 1'1
135488       attribute \src "libresoc.v:0.0-0.0"
135489       case 10'0010000011
135490         assign { } { }
135491         assign $1\spr_o_ok[0:0] 1'1
135492       attribute \src "libresoc.v:0.0-0.0"
135493       case 10'0010001000
135494         assign { } { }
135495         assign $1\spr_o_ok[0:0] 1'1
135496       attribute \src "libresoc.v:0.0-0.0"
135497       case 10'0010010000
135498         assign { } { }
135499         assign $1\spr_o_ok[0:0] 1'1
135500       attribute \src "libresoc.v:0.0-0.0"
135501       case 10'0010011000
135502         assign { } { }
135503         assign $1\spr_o_ok[0:0] 1'1
135504       attribute \src "libresoc.v:0.0-0.0"
135505       case 10'0010011001
135506         assign { } { }
135507         assign $1\spr_o_ok[0:0] 1'1
135508       attribute \src "libresoc.v:0.0-0.0"
135509       case 10'0010011101
135510         assign { } { }
135511         assign $1\spr_o_ok[0:0] 1'1
135512       attribute \src "libresoc.v:0.0-0.0"
135513       case 10'0010011110
135514         assign { } { }
135515         assign $1\spr_o_ok[0:0] 1'1
135516       attribute \src "libresoc.v:0.0-0.0"
135517       case 10'0010011111
135518         assign { } { }
135519         assign $1\spr_o_ok[0:0] 1'1
135520       attribute \src "libresoc.v:0.0-0.0"
135521       case 10'0010110000
135522         assign { } { }
135523         assign $1\spr_o_ok[0:0] 1'1
135524       attribute \src "libresoc.v:0.0-0.0"
135525       case 10'0010110100
135526         assign { } { }
135527         assign $1\spr_o_ok[0:0] 1'1
135528       attribute \src "libresoc.v:0.0-0.0"
135529       case 10'0010111010
135530         assign { } { }
135531         assign $1\spr_o_ok[0:0] 1'1
135532       attribute \src "libresoc.v:0.0-0.0"
135533       case 10'0010111011
135534         assign { } { }
135535         assign $1\spr_o_ok[0:0] 1'1
135536       attribute \src "libresoc.v:0.0-0.0"
135537       case 10'0010111100
135538         assign { } { }
135539         assign $1\spr_o_ok[0:0] 1'1
135540       attribute \src "libresoc.v:0.0-0.0"
135541       case 10'0010111110
135542         assign { } { }
135543         assign $1\spr_o_ok[0:0] 1'1
135544       attribute \src "libresoc.v:0.0-0.0"
135545       case 10'0100000000
135546         assign { } { }
135547         assign $1\spr_o_ok[0:0] 1'1
135548       attribute \src "libresoc.v:0.0-0.0"
135549       case 10'0100000011
135550         assign { } { }
135551         assign $1\spr_o_ok[0:0] 1'1
135552       attribute \src "libresoc.v:0.0-0.0"
135553       case 10'0100001101
135554         assign { } { }
135555         assign $1\spr_o_ok[0:0] 1'1
135556       attribute \src "libresoc.v:0.0-0.0"
135557       case 10'0100010000
135558         assign { } { }
135559         assign $1\spr_o_ok[0:0] 1'1
135560       attribute \src "libresoc.v:0.0-0.0"
135561       case 10'0100010001
135562         assign { } { }
135563         assign $1\spr_o_ok[0:0] 1'1
135564       attribute \src "libresoc.v:0.0-0.0"
135565       case 10'0100010010
135566         assign { } { }
135567         assign $1\spr_o_ok[0:0] 1'1
135568       attribute \src "libresoc.v:0.0-0.0"
135569       case 10'0100010011
135570         assign { } { }
135571         assign $1\spr_o_ok[0:0] 1'1
135572       attribute \src "libresoc.v:0.0-0.0"
135573       case 10'0100011011
135574         assign { } { }
135575         assign $1\spr_o_ok[0:0] 1'1
135576       attribute \src "libresoc.v:0.0-0.0"
135577       case 10'0100011100
135578         assign { } { }
135579         assign $1\spr_o_ok[0:0] 1'1
135580       attribute \src "libresoc.v:0.0-0.0"
135581       case 10'0100011101
135582         assign { } { }
135583         assign $1\spr_o_ok[0:0] 1'1
135584       attribute \src "libresoc.v:0.0-0.0"
135585       case 10'0100011110
135586         assign { } { }
135587         assign $1\spr_o_ok[0:0] 1'1
135588       attribute \src "libresoc.v:0.0-0.0"
135589       case 10'0100011111
135590         assign { } { }
135591         assign $1\spr_o_ok[0:0] 1'1
135592       attribute \src "libresoc.v:0.0-0.0"
135593       case 10'0100110000
135594         assign { } { }
135595         assign $1\spr_o_ok[0:0] 1'1
135596       attribute \src "libresoc.v:0.0-0.0"
135597       case 10'0100110001
135598         assign { } { }
135599         assign $1\spr_o_ok[0:0] 1'1
135600       attribute \src "libresoc.v:0.0-0.0"
135601       case 10'0100110010
135602         assign { } { }
135603         assign $1\spr_o_ok[0:0] 1'1
135604       attribute \src "libresoc.v:0.0-0.0"
135605       case 10'0100110011
135606         assign { } { }
135607         assign $1\spr_o_ok[0:0] 1'1
135608       attribute \src "libresoc.v:0.0-0.0"
135609       case 10'0100110100
135610         assign { } { }
135611         assign $1\spr_o_ok[0:0] 1'1
135612       attribute \src "libresoc.v:0.0-0.0"
135613       case 10'0100110101
135614         assign { } { }
135615         assign $1\spr_o_ok[0:0] 1'1
135616       attribute \src "libresoc.v:0.0-0.0"
135617       case 10'0100110110
135618         assign { } { }
135619         assign $1\spr_o_ok[0:0] 1'1
135620       attribute \src "libresoc.v:0.0-0.0"
135621       case 10'0100111001
135622         assign { } { }
135623         assign $1\spr_o_ok[0:0] 1'1
135624       attribute \src "libresoc.v:0.0-0.0"
135625       case 10'0100111010
135626         assign { } { }
135627         assign $1\spr_o_ok[0:0] 1'1
135628       attribute \src "libresoc.v:0.0-0.0"
135629       case 10'0100111011
135630         assign { } { }
135631         assign $1\spr_o_ok[0:0] 1'1
135632       attribute \src "libresoc.v:0.0-0.0"
135633       case 10'0100111110
135634         assign { } { }
135635         assign $1\spr_o_ok[0:0] 1'1
135636       attribute \src "libresoc.v:0.0-0.0"
135637       case 10'0100111111
135638         assign { } { }
135639         assign $1\spr_o_ok[0:0] 1'1
135640       attribute \src "libresoc.v:0.0-0.0"
135641       case 10'0101010000
135642         assign { } { }
135643         assign $1\spr_o_ok[0:0] 1'1
135644       attribute \src "libresoc.v:0.0-0.0"
135645       case 10'0101010001
135646         assign { } { }
135647         assign $1\spr_o_ok[0:0] 1'1
135648       attribute \src "libresoc.v:0.0-0.0"
135649       case 10'0101010010
135650         assign { } { }
135651         assign $1\spr_o_ok[0:0] 1'1
135652       attribute \src "libresoc.v:0.0-0.0"
135653       case 10'0101010011
135654         assign { } { }
135655         assign $1\spr_o_ok[0:0] 1'1
135656       attribute \src "libresoc.v:0.0-0.0"
135657       case 10'0101011101
135658         assign { } { }
135659         assign $1\spr_o_ok[0:0] 1'1
135660       attribute \src "libresoc.v:0.0-0.0"
135661       case 10'0110111110
135662         assign { } { }
135663         assign $1\spr_o_ok[0:0] 1'1
135664       attribute \src "libresoc.v:0.0-0.0"
135665       case 10'0111010000
135666         assign { } { }
135667         assign $1\spr_o_ok[0:0] 1'1
135668       attribute \src "libresoc.v:0.0-0.0"
135669       case 10'1100000000
135670         assign { } { }
135671         assign $1\spr_o_ok[0:0] 1'1
135672       attribute \src "libresoc.v:0.0-0.0"
135673       case 10'1100000001
135674         assign { } { }
135675         assign $1\spr_o_ok[0:0] 1'1
135676       attribute \src "libresoc.v:0.0-0.0"
135677       case 10'1100000010
135678         assign { } { }
135679         assign $1\spr_o_ok[0:0] 1'1
135680       attribute \src "libresoc.v:0.0-0.0"
135681       case 10'1100000011
135682         assign { } { }
135683         assign $1\spr_o_ok[0:0] 1'1
135684       attribute \src "libresoc.v:0.0-0.0"
135685       case 10'1100000100
135686         assign { } { }
135687         assign $1\spr_o_ok[0:0] 1'1
135688       attribute \src "libresoc.v:0.0-0.0"
135689       case 10'1100000101
135690         assign { } { }
135691         assign $1\spr_o_ok[0:0] 1'1
135692       attribute \src "libresoc.v:0.0-0.0"
135693       case 10'1100000110
135694         assign { } { }
135695         assign $1\spr_o_ok[0:0] 1'1
135696       attribute \src "libresoc.v:0.0-0.0"
135697       case 10'1100000111
135698         assign { } { }
135699         assign $1\spr_o_ok[0:0] 1'1
135700       attribute \src "libresoc.v:0.0-0.0"
135701       case 10'1100001000
135702         assign { } { }
135703         assign $1\spr_o_ok[0:0] 1'1
135704       attribute \src "libresoc.v:0.0-0.0"
135705       case 10'1100001011
135706         assign { } { }
135707         assign $1\spr_o_ok[0:0] 1'1
135708       attribute \src "libresoc.v:0.0-0.0"
135709       case 10'1100001100
135710         assign { } { }
135711         assign $1\spr_o_ok[0:0] 1'1
135712       attribute \src "libresoc.v:0.0-0.0"
135713       case 10'1100001101
135714         assign { } { }
135715         assign $1\spr_o_ok[0:0] 1'1
135716       attribute \src "libresoc.v:0.0-0.0"
135717       case 10'1100001110
135718         assign { } { }
135719         assign $1\spr_o_ok[0:0] 1'1
135720       attribute \src "libresoc.v:0.0-0.0"
135721       case 10'1100010000
135722         assign { } { }
135723         assign $1\spr_o_ok[0:0] 1'1
135724       attribute \src "libresoc.v:0.0-0.0"
135725       case 10'1100010001
135726         assign { } { }
135727         assign $1\spr_o_ok[0:0] 1'1
135728       attribute \src "libresoc.v:0.0-0.0"
135729       case 10'1100010010
135730         assign { } { }
135731         assign $1\spr_o_ok[0:0] 1'1
135732       attribute \src "libresoc.v:0.0-0.0"
135733       case 10'1100010011
135734         assign { } { }
135735         assign $1\spr_o_ok[0:0] 1'1
135736       attribute \src "libresoc.v:0.0-0.0"
135737       case 10'1100010100
135738         assign { } { }
135739         assign $1\spr_o_ok[0:0] 1'1
135740       attribute \src "libresoc.v:0.0-0.0"
135741       case 10'1100010101
135742         assign { } { }
135743         assign $1\spr_o_ok[0:0] 1'1
135744       attribute \src "libresoc.v:0.0-0.0"
135745       case 10'1100010110
135746         assign { } { }
135747         assign $1\spr_o_ok[0:0] 1'1
135748       attribute \src "libresoc.v:0.0-0.0"
135749       case 10'1100010111
135750         assign { } { }
135751         assign $1\spr_o_ok[0:0] 1'1
135752       attribute \src "libresoc.v:0.0-0.0"
135753       case 10'1100011000
135754         assign { } { }
135755         assign $1\spr_o_ok[0:0] 1'1
135756       attribute \src "libresoc.v:0.0-0.0"
135757       case 10'1100011011
135758         assign { } { }
135759         assign $1\spr_o_ok[0:0] 1'1
135760       attribute \src "libresoc.v:0.0-0.0"
135761       case 10'1100011100
135762         assign { } { }
135763         assign $1\spr_o_ok[0:0] 1'1
135764       attribute \src "libresoc.v:0.0-0.0"
135765       case 10'1100011101
135766         assign { } { }
135767         assign $1\spr_o_ok[0:0] 1'1
135768       attribute \src "libresoc.v:0.0-0.0"
135769       case 10'1100011110
135770         assign { } { }
135771         assign $1\spr_o_ok[0:0] 1'1
135772       attribute \src "libresoc.v:0.0-0.0"
135773       case 10'1100100000
135774         assign { } { }
135775         assign $1\spr_o_ok[0:0] 1'1
135776       attribute \src "libresoc.v:0.0-0.0"
135777       case 10'1100100001
135778         assign { } { }
135779         assign $1\spr_o_ok[0:0] 1'1
135780       attribute \src "libresoc.v:0.0-0.0"
135781       case 10'1100100010
135782         assign { } { }
135783         assign $1\spr_o_ok[0:0] 1'1
135784       attribute \src "libresoc.v:0.0-0.0"
135785       case 10'1100100011
135786         assign { } { }
135787         assign $1\spr_o_ok[0:0] 1'1
135788       attribute \src "libresoc.v:0.0-0.0"
135789       case 10'1100100100
135790         assign { } { }
135791         assign $1\spr_o_ok[0:0] 1'1
135792       attribute \src "libresoc.v:0.0-0.0"
135793       case 10'1100100101
135794         assign { } { }
135795         assign $1\spr_o_ok[0:0] 1'1
135796       attribute \src "libresoc.v:0.0-0.0"
135797       case 10'1100100110
135798         assign { } { }
135799         assign $1\spr_o_ok[0:0] 1'1
135800       attribute \src "libresoc.v:0.0-0.0"
135801       case 10'1100101000
135802         assign { } { }
135803         assign $1\spr_o_ok[0:0] 1'1
135804       attribute \src "libresoc.v:0.0-0.0"
135805       case 10'1100101001
135806         assign { } { }
135807         assign $1\spr_o_ok[0:0] 1'1
135808       attribute \src "libresoc.v:0.0-0.0"
135809       case 10'1100101010
135810         assign { } { }
135811         assign $1\spr_o_ok[0:0] 1'1
135812       attribute \src "libresoc.v:0.0-0.0"
135813       case 10'1100101011
135814         assign { } { }
135815         assign $1\spr_o_ok[0:0] 1'1
135816       attribute \src "libresoc.v:0.0-0.0"
135817       case 10'1100110000
135818         assign { } { }
135819         assign $1\spr_o_ok[0:0] 1'1
135820       attribute \src "libresoc.v:0.0-0.0"
135821       case 10'1100110111
135822         assign { } { }
135823         assign $1\spr_o_ok[0:0] 1'1
135824       attribute \src "libresoc.v:0.0-0.0"
135825       case 10'1101010000
135826         assign { } { }
135827         assign $1\spr_o_ok[0:0] 1'1
135828       attribute \src "libresoc.v:0.0-0.0"
135829       case 10'1101010001
135830         assign { } { }
135831         assign $1\spr_o_ok[0:0] 1'1
135832       attribute \src "libresoc.v:0.0-0.0"
135833       case 10'1101010111
135834         assign { } { }
135835         assign $1\spr_o_ok[0:0] 1'1
135836       attribute \src "libresoc.v:0.0-0.0"
135837       case 10'1110000000
135838         assign { } { }
135839         assign $1\spr_o_ok[0:0] 1'1
135840       attribute \src "libresoc.v:0.0-0.0"
135841       case 10'1110000010
135842         assign { } { }
135843         assign $1\spr_o_ok[0:0] 1'1
135844       attribute \src "libresoc.v:0.0-0.0"
135845       case 10'1111111111
135846         assign { } { }
135847         assign $1\spr_o_ok[0:0] 1'1
135848       case
135849         assign $1\spr_o_ok[0:0] 1'0
135850     end
135851     sync always
135852       update \spr_o_ok $0\spr_o_ok[0:0]
135853   end
135854 end
135855 attribute \src "libresoc.v:46768.1-47583.10"
135856 attribute \cells_not_processed 1
135857 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap"
135858 attribute \generator "nMigen"
135859 module \sprmap$2
135860   attribute \src "libresoc.v:46895.3-46925.6"
135861   wire width 3 $0\fast_o[2:0]
135862   attribute \src "libresoc.v:46926.3-46956.6"
135863   wire $0\fast_o_ok[0:0]
135864   attribute \src "libresoc.v:46769.7-46769.20"
135865   wire $0\initial[0:0]
135866   attribute \src "libresoc.v:46957.3-47269.6"
135867   wire width 10 $0\spr_o[9:0]
135868   attribute \src "libresoc.v:47270.3-47582.6"
135869   wire $0\spr_o_ok[0:0]
135870   attribute \src "libresoc.v:46895.3-46925.6"
135871   wire width 3 $1\fast_o[2:0]
135872   attribute \src "libresoc.v:46926.3-46956.6"
135873   wire $1\fast_o_ok[0:0]
135874   attribute \src "libresoc.v:46957.3-47269.6"
135875   wire width 10 $1\spr_o[9:0]
135876   attribute \src "libresoc.v:47270.3-47582.6"
135877   wire $1\spr_o_ok[0:0]
135878   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
135879   wire width 3 output 3 \fast_o
135880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
135881   wire output 4 \fast_o_ok
135882   attribute \src "libresoc.v:46769.7-46769.15"
135883   wire \initial
135884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
135885   wire width 10 input 5 \spr_i
135886   attribute \enum_base_type "SPR"
135887   attribute \enum_value_0000000001 "XER"
135888   attribute \enum_value_0000000011 "DSCR"
135889   attribute \enum_value_0000001000 "LR"
135890   attribute \enum_value_0000001001 "CTR"
135891   attribute \enum_value_0000001101 "AMR"
135892   attribute \enum_value_0000010001 "DSCR_priv"
135893   attribute \enum_value_0000010010 "DSISR"
135894   attribute \enum_value_0000010011 "DAR"
135895   attribute \enum_value_0000010110 "DEC"
135896   attribute \enum_value_0000011010 "SRR0"
135897   attribute \enum_value_0000011011 "SRR1"
135898   attribute \enum_value_0000011100 "CFAR"
135899   attribute \enum_value_0000011101 "AMR_priv"
135900   attribute \enum_value_0000110000 "PIDR"
135901   attribute \enum_value_0000111101 "IAMR"
135902   attribute \enum_value_0010000000 "TFHAR"
135903   attribute \enum_value_0010000001 "TFIAR"
135904   attribute \enum_value_0010000010 "TEXASR"
135905   attribute \enum_value_0010000011 "TEXASRU"
135906   attribute \enum_value_0010001000 "CTRL"
135907   attribute \enum_value_0010010000 "TIDR"
135908   attribute \enum_value_0010011000 "CTRL_priv"
135909   attribute \enum_value_0010011001 "FSCR"
135910   attribute \enum_value_0010011101 "UAMOR"
135911   attribute \enum_value_0010011110 "GSR"
135912   attribute \enum_value_0010011111 "PSPB"
135913   attribute \enum_value_0010110000 "DPDES"
135914   attribute \enum_value_0010110100 "DAWR0"
135915   attribute \enum_value_0010111010 "RPR"
135916   attribute \enum_value_0010111011 "CIABR"
135917   attribute \enum_value_0010111100 "DAWRX0"
135918   attribute \enum_value_0010111110 "HFSCR"
135919   attribute \enum_value_0100000000 "VRSAVE"
135920   attribute \enum_value_0100000011 "SPRG3"
135921   attribute \enum_value_0100001100 "TB"
135922   attribute \enum_value_0100001101 "TBU"
135923   attribute \enum_value_0100010000 "SPRG0_priv"
135924   attribute \enum_value_0100010001 "SPRG1_priv"
135925   attribute \enum_value_0100010010 "SPRG2_priv"
135926   attribute \enum_value_0100010011 "SPRG3_priv"
135927   attribute \enum_value_0100011011 "CIR"
135928   attribute \enum_value_0100011100 "TBL"
135929   attribute \enum_value_0100011101 "TBU_hypv"
135930   attribute \enum_value_0100011110 "TBU40"
135931   attribute \enum_value_0100011111 "PVR"
135932   attribute \enum_value_0100110000 "HSPRG0"
135933   attribute \enum_value_0100110001 "HSPRG1"
135934   attribute \enum_value_0100110010 "HDSISR"
135935   attribute \enum_value_0100110011 "HDAR"
135936   attribute \enum_value_0100110100 "SPURR"
135937   attribute \enum_value_0100110101 "PURR"
135938   attribute \enum_value_0100110110 "HDEC"
135939   attribute \enum_value_0100111001 "HRMOR"
135940   attribute \enum_value_0100111010 "HSRR0"
135941   attribute \enum_value_0100111011 "HSRR1"
135942   attribute \enum_value_0100111110 "LPCR"
135943   attribute \enum_value_0100111111 "LPIDR"
135944   attribute \enum_value_0101010000 "HMER"
135945   attribute \enum_value_0101010001 "HMEER"
135946   attribute \enum_value_0101010010 "PCR"
135947   attribute \enum_value_0101010011 "HEIR"
135948   attribute \enum_value_0101011101 "AMOR"
135949   attribute \enum_value_0110111110 "TIR"
135950   attribute \enum_value_0111010000 "PTCR"
135951   attribute \enum_value_1100000000 "SIER"
135952   attribute \enum_value_1100000001 "MMCR2"
135953   attribute \enum_value_1100000010 "MMCRA"
135954   attribute \enum_value_1100000011 "PMC1"
135955   attribute \enum_value_1100000100 "PMC2"
135956   attribute \enum_value_1100000101 "PMC3"
135957   attribute \enum_value_1100000110 "PMC4"
135958   attribute \enum_value_1100000111 "PMC5"
135959   attribute \enum_value_1100001000 "PMC6"
135960   attribute \enum_value_1100001011 "MMCR0"
135961   attribute \enum_value_1100001100 "SIAR"
135962   attribute \enum_value_1100001101 "SDAR"
135963   attribute \enum_value_1100001110 "MMCR1"
135964   attribute \enum_value_1100010000 "SIER_priv"
135965   attribute \enum_value_1100010001 "MMCR2_priv"
135966   attribute \enum_value_1100010010 "MMCRA_priv"
135967   attribute \enum_value_1100010011 "PMC1_priv"
135968   attribute \enum_value_1100010100 "PMC2_priv"
135969   attribute \enum_value_1100010101 "PMC3_priv"
135970   attribute \enum_value_1100010110 "PMC4_priv"
135971   attribute \enum_value_1100010111 "PMC5_priv"
135972   attribute \enum_value_1100011000 "PMC6_priv"
135973   attribute \enum_value_1100011011 "MMCR0_priv"
135974   attribute \enum_value_1100011100 "SIAR_priv"
135975   attribute \enum_value_1100011101 "SDAR_priv"
135976   attribute \enum_value_1100011110 "MMCR1_priv"
135977   attribute \enum_value_1100100000 "BESCRS"
135978   attribute \enum_value_1100100001 "BESCRSU"
135979   attribute \enum_value_1100100010 "BESCRR"
135980   attribute \enum_value_1100100011 "BESCRRU"
135981   attribute \enum_value_1100100100 "EBBHR"
135982   attribute \enum_value_1100100101 "EBBRR"
135983   attribute \enum_value_1100100110 "BESCR"
135984   attribute \enum_value_1100101000 "reserved808"
135985   attribute \enum_value_1100101001 "reserved809"
135986   attribute \enum_value_1100101010 "reserved810"
135987   attribute \enum_value_1100101011 "reserved811"
135988   attribute \enum_value_1100101111 "TAR"
135989   attribute \enum_value_1100110000 "ASDR"
135990   attribute \enum_value_1100110111 "PSSCR"
135991   attribute \enum_value_1101010000 "IC"
135992   attribute \enum_value_1101010001 "VTB"
135993   attribute \enum_value_1101010111 "PSSCR_hypv"
135994   attribute \enum_value_1110000000 "PPR"
135995   attribute \enum_value_1110000010 "PPR32"
135996   attribute \enum_value_1111111111 "PIR"
135997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
135998   wire width 10 output 1 \spr_o
135999   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
136000   wire output 2 \spr_o_ok
136001   attribute \src "libresoc.v:46769.7-46769.20"
136002   process $proc$libresoc.v:46769$1602
136003     assign { } { }
136004     assign $0\initial[0:0] 1'0
136005     sync always
136006       update \initial $0\initial[0:0]
136007     sync init
136008   end
136009   attribute \src "libresoc.v:46895.3-46925.6"
136010   process $proc$libresoc.v:46895$1598
136011     assign { } { }
136012     assign { } { }
136013     assign $0\fast_o[2:0] $1\fast_o[2:0]
136014     attribute \src "libresoc.v:46896.5-46896.29"
136015     switch \initial
136016       attribute \src "libresoc.v:46896.9-46896.17"
136017       case 1'1
136018       case
136019     end
136020     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
136021     switch \spr_i
136022       attribute \src "libresoc.v:0.0-0.0"
136023       case 10'0000000001
136024         assign { } { }
136025         assign $1\fast_o[2:0] 3'101
136026       attribute \src "libresoc.v:0.0-0.0"
136027       case 10'0000001000
136028         assign { } { }
136029         assign $1\fast_o[2:0] 3'001
136030       attribute \src "libresoc.v:0.0-0.0"
136031       case 10'0000001001
136032         assign { } { }
136033         assign $1\fast_o[2:0] 3'000
136034       attribute \src "libresoc.v:0.0-0.0"
136035       case 10'0000010110
136036         assign { } { }
136037         assign $1\fast_o[2:0] 3'110
136038       attribute \src "libresoc.v:0.0-0.0"
136039       case 10'0000011010
136040         assign { } { }
136041         assign $1\fast_o[2:0] 3'011
136042       attribute \src "libresoc.v:0.0-0.0"
136043       case 10'0000011011
136044         assign { } { }
136045         assign $1\fast_o[2:0] 3'100
136046       attribute \src "libresoc.v:0.0-0.0"
136047       case 10'0100001100
136048         assign { } { }
136049         assign $1\fast_o[2:0] 3'111
136050       attribute \src "libresoc.v:0.0-0.0"
136051       case 10'1100101111
136052         assign { } { }
136053         assign $1\fast_o[2:0] 3'010
136054       case
136055         assign $1\fast_o[2:0] 3'000
136056     end
136057     sync always
136058       update \fast_o $0\fast_o[2:0]
136059   end
136060   attribute \src "libresoc.v:46926.3-46956.6"
136061   process $proc$libresoc.v:46926$1599
136062     assign { } { }
136063     assign { } { }
136064     assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
136065     attribute \src "libresoc.v:46927.5-46927.29"
136066     switch \initial
136067       attribute \src "libresoc.v:46927.9-46927.17"
136068       case 1'1
136069       case
136070     end
136071     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
136072     switch \spr_i
136073       attribute \src "libresoc.v:0.0-0.0"
136074       case 10'0000000001
136075         assign { } { }
136076         assign $1\fast_o_ok[0:0] 1'1
136077       attribute \src "libresoc.v:0.0-0.0"
136078       case 10'0000001000
136079         assign { } { }
136080         assign $1\fast_o_ok[0:0] 1'1
136081       attribute \src "libresoc.v:0.0-0.0"
136082       case 10'0000001001
136083         assign { } { }
136084         assign $1\fast_o_ok[0:0] 1'1
136085       attribute \src "libresoc.v:0.0-0.0"
136086       case 10'0000010110
136087         assign { } { }
136088         assign $1\fast_o_ok[0:0] 1'1
136089       attribute \src "libresoc.v:0.0-0.0"
136090       case 10'0000011010
136091         assign { } { }
136092         assign $1\fast_o_ok[0:0] 1'1
136093       attribute \src "libresoc.v:0.0-0.0"
136094       case 10'0000011011
136095         assign { } { }
136096         assign $1\fast_o_ok[0:0] 1'1
136097       attribute \src "libresoc.v:0.0-0.0"
136098       case 10'0100001100
136099         assign { } { }
136100         assign $1\fast_o_ok[0:0] 1'1
136101       attribute \src "libresoc.v:0.0-0.0"
136102       case 10'1100101111
136103         assign { } { }
136104         assign $1\fast_o_ok[0:0] 1'1
136105       case
136106         assign $1\fast_o_ok[0:0] 1'0
136107     end
136108     sync always
136109       update \fast_o_ok $0\fast_o_ok[0:0]
136110   end
136111   attribute \src "libresoc.v:46957.3-47269.6"
136112   process $proc$libresoc.v:46957$1600
136113     assign { } { }
136114     assign { } { }
136115     assign $0\spr_o[9:0] $1\spr_o[9:0]
136116     attribute \src "libresoc.v:46958.5-46958.29"
136117     switch \initial
136118       attribute \src "libresoc.v:46958.9-46958.17"
136119       case 1'1
136120       case
136121     end
136122     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
136123     switch \spr_i
136124       attribute \src "libresoc.v:0.0-0.0"
136125       case 10'0000000011
136126         assign { } { }
136127         assign $1\spr_o[9:0] 10'0000000001
136128       attribute \src "libresoc.v:0.0-0.0"
136129       case 10'0000001101
136130         assign { } { }
136131         assign $1\spr_o[9:0] 10'0000000100
136132       attribute \src "libresoc.v:0.0-0.0"
136133       case 10'0000010001
136134         assign { } { }
136135         assign $1\spr_o[9:0] 10'0000000101
136136       attribute \src "libresoc.v:0.0-0.0"
136137       case 10'0000010010
136138         assign { } { }
136139         assign $1\spr_o[9:0] 10'0000000110
136140       attribute \src "libresoc.v:0.0-0.0"
136141       case 10'0000010011
136142         assign { } { }
136143         assign $1\spr_o[9:0] 10'0000000111
136144       attribute \src "libresoc.v:0.0-0.0"
136145       case 10'0000011100
136146         assign { } { }
136147         assign $1\spr_o[9:0] 10'0000001011
136148       attribute \src "libresoc.v:0.0-0.0"
136149       case 10'0000011101
136150         assign { } { }
136151         assign $1\spr_o[9:0] 10'0000001100
136152       attribute \src "libresoc.v:0.0-0.0"
136153       case 10'0000110000
136154         assign { } { }
136155         assign $1\spr_o[9:0] 10'0000001101
136156       attribute \src "libresoc.v:0.0-0.0"
136157       case 10'0000111101
136158         assign { } { }
136159         assign $1\spr_o[9:0] 10'0000001110
136160       attribute \src "libresoc.v:0.0-0.0"
136161       case 10'0010000000
136162         assign { } { }
136163         assign $1\spr_o[9:0] 10'0000001111
136164       attribute \src "libresoc.v:0.0-0.0"
136165       case 10'0010000001
136166         assign { } { }
136167         assign $1\spr_o[9:0] 10'0000010000
136168       attribute \src "libresoc.v:0.0-0.0"
136169       case 10'0010000010
136170         assign { } { }
136171         assign $1\spr_o[9:0] 10'0000010001
136172       attribute \src "libresoc.v:0.0-0.0"
136173       case 10'0010000011
136174         assign { } { }
136175         assign $1\spr_o[9:0] 10'0000010010
136176       attribute \src "libresoc.v:0.0-0.0"
136177       case 10'0010001000
136178         assign { } { }
136179         assign $1\spr_o[9:0] 10'0000010011
136180       attribute \src "libresoc.v:0.0-0.0"
136181       case 10'0010010000
136182         assign { } { }
136183         assign $1\spr_o[9:0] 10'0000010100
136184       attribute \src "libresoc.v:0.0-0.0"
136185       case 10'0010011000
136186         assign { } { }
136187         assign $1\spr_o[9:0] 10'0000010101
136188       attribute \src "libresoc.v:0.0-0.0"
136189       case 10'0010011001
136190         assign { } { }
136191         assign $1\spr_o[9:0] 10'0000010110
136192       attribute \src "libresoc.v:0.0-0.0"
136193       case 10'0010011101
136194         assign { } { }
136195         assign $1\spr_o[9:0] 10'0000010111
136196       attribute \src "libresoc.v:0.0-0.0"
136197       case 10'0010011110
136198         assign { } { }
136199         assign $1\spr_o[9:0] 10'0000011000
136200       attribute \src "libresoc.v:0.0-0.0"
136201       case 10'0010011111
136202         assign { } { }
136203         assign $1\spr_o[9:0] 10'0000011001
136204       attribute \src "libresoc.v:0.0-0.0"
136205       case 10'0010110000
136206         assign { } { }
136207         assign $1\spr_o[9:0] 10'0000011010
136208       attribute \src "libresoc.v:0.0-0.0"
136209       case 10'0010110100
136210         assign { } { }
136211         assign $1\spr_o[9:0] 10'0000011011
136212       attribute \src "libresoc.v:0.0-0.0"
136213       case 10'0010111010
136214         assign { } { }
136215         assign $1\spr_o[9:0] 10'0000011100
136216       attribute \src "libresoc.v:0.0-0.0"
136217       case 10'0010111011
136218         assign { } { }
136219         assign $1\spr_o[9:0] 10'0000011101
136220       attribute \src "libresoc.v:0.0-0.0"
136221       case 10'0010111100
136222         assign { } { }
136223         assign $1\spr_o[9:0] 10'0000011110
136224       attribute \src "libresoc.v:0.0-0.0"
136225       case 10'0010111110
136226         assign { } { }
136227         assign $1\spr_o[9:0] 10'0000011111
136228       attribute \src "libresoc.v:0.0-0.0"
136229       case 10'0100000000
136230         assign { } { }
136231         assign $1\spr_o[9:0] 10'0000100000
136232       attribute \src "libresoc.v:0.0-0.0"
136233       case 10'0100000011
136234         assign { } { }
136235         assign $1\spr_o[9:0] 10'0000100001
136236       attribute \src "libresoc.v:0.0-0.0"
136237       case 10'0100001101
136238         assign { } { }
136239         assign $1\spr_o[9:0] 10'0000100011
136240       attribute \src "libresoc.v:0.0-0.0"
136241       case 10'0100010000
136242         assign { } { }
136243         assign $1\spr_o[9:0] 10'0000100100
136244       attribute \src "libresoc.v:0.0-0.0"
136245       case 10'0100010001
136246         assign { } { }
136247         assign $1\spr_o[9:0] 10'0000100101
136248       attribute \src "libresoc.v:0.0-0.0"
136249       case 10'0100010010
136250         assign { } { }
136251         assign $1\spr_o[9:0] 10'0000100110
136252       attribute \src "libresoc.v:0.0-0.0"
136253       case 10'0100010011
136254         assign { } { }
136255         assign $1\spr_o[9:0] 10'0000100111
136256       attribute \src "libresoc.v:0.0-0.0"
136257       case 10'0100011011
136258         assign { } { }
136259         assign $1\spr_o[9:0] 10'0000101000
136260       attribute \src "libresoc.v:0.0-0.0"
136261       case 10'0100011100
136262         assign { } { }
136263         assign $1\spr_o[9:0] 10'0000101001
136264       attribute \src "libresoc.v:0.0-0.0"
136265       case 10'0100011101
136266         assign { } { }
136267         assign $1\spr_o[9:0] 10'0000101010
136268       attribute \src "libresoc.v:0.0-0.0"
136269       case 10'0100011110
136270         assign { } { }
136271         assign $1\spr_o[9:0] 10'0000101011
136272       attribute \src "libresoc.v:0.0-0.0"
136273       case 10'0100011111
136274         assign { } { }
136275         assign $1\spr_o[9:0] 10'0000101100
136276       attribute \src "libresoc.v:0.0-0.0"
136277       case 10'0100110000
136278         assign { } { }
136279         assign $1\spr_o[9:0] 10'0000101101
136280       attribute \src "libresoc.v:0.0-0.0"
136281       case 10'0100110001
136282         assign { } { }
136283         assign $1\spr_o[9:0] 10'0000101110
136284       attribute \src "libresoc.v:0.0-0.0"
136285       case 10'0100110010
136286         assign { } { }
136287         assign $1\spr_o[9:0] 10'0000101111
136288       attribute \src "libresoc.v:0.0-0.0"
136289       case 10'0100110011
136290         assign { } { }
136291         assign $1\spr_o[9:0] 10'0000110000
136292       attribute \src "libresoc.v:0.0-0.0"
136293       case 10'0100110100
136294         assign { } { }
136295         assign $1\spr_o[9:0] 10'0000110001
136296       attribute \src "libresoc.v:0.0-0.0"
136297       case 10'0100110101
136298         assign { } { }
136299         assign $1\spr_o[9:0] 10'0000110010
136300       attribute \src "libresoc.v:0.0-0.0"
136301       case 10'0100110110
136302         assign { } { }
136303         assign $1\spr_o[9:0] 10'0000110011
136304       attribute \src "libresoc.v:0.0-0.0"
136305       case 10'0100111001
136306         assign { } { }
136307         assign $1\spr_o[9:0] 10'0000110100
136308       attribute \src "libresoc.v:0.0-0.0"
136309       case 10'0100111010
136310         assign { } { }
136311         assign $1\spr_o[9:0] 10'0000110101
136312       attribute \src "libresoc.v:0.0-0.0"
136313       case 10'0100111011
136314         assign { } { }
136315         assign $1\spr_o[9:0] 10'0000110110
136316       attribute \src "libresoc.v:0.0-0.0"
136317       case 10'0100111110
136318         assign { } { }
136319         assign $1\spr_o[9:0] 10'0000110111
136320       attribute \src "libresoc.v:0.0-0.0"
136321       case 10'0100111111
136322         assign { } { }
136323         assign $1\spr_o[9:0] 10'0000111000
136324       attribute \src "libresoc.v:0.0-0.0"
136325       case 10'0101010000
136326         assign { } { }
136327         assign $1\spr_o[9:0] 10'0000111001
136328       attribute \src "libresoc.v:0.0-0.0"
136329       case 10'0101010001
136330         assign { } { }
136331         assign $1\spr_o[9:0] 10'0000111010
136332       attribute \src "libresoc.v:0.0-0.0"
136333       case 10'0101010010
136334         assign { } { }
136335         assign $1\spr_o[9:0] 10'0000111011
136336       attribute \src "libresoc.v:0.0-0.0"
136337       case 10'0101010011
136338         assign { } { }
136339         assign $1\spr_o[9:0] 10'0000111100
136340       attribute \src "libresoc.v:0.0-0.0"
136341       case 10'0101011101
136342         assign { } { }
136343         assign $1\spr_o[9:0] 10'0000111101
136344       attribute \src "libresoc.v:0.0-0.0"
136345       case 10'0110111110
136346         assign { } { }
136347         assign $1\spr_o[9:0] 10'0000111110
136348       attribute \src "libresoc.v:0.0-0.0"
136349       case 10'0111010000
136350         assign { } { }
136351         assign $1\spr_o[9:0] 10'0000111111
136352       attribute \src "libresoc.v:0.0-0.0"
136353       case 10'1100000000
136354         assign { } { }
136355         assign $1\spr_o[9:0] 10'0001000000
136356       attribute \src "libresoc.v:0.0-0.0"
136357       case 10'1100000001
136358         assign { } { }
136359         assign $1\spr_o[9:0] 10'0001000001
136360       attribute \src "libresoc.v:0.0-0.0"
136361       case 10'1100000010
136362         assign { } { }
136363         assign $1\spr_o[9:0] 10'0001000010
136364       attribute \src "libresoc.v:0.0-0.0"
136365       case 10'1100000011
136366         assign { } { }
136367         assign $1\spr_o[9:0] 10'0001000011
136368       attribute \src "libresoc.v:0.0-0.0"
136369       case 10'1100000100
136370         assign { } { }
136371         assign $1\spr_o[9:0] 10'0001000100
136372       attribute \src "libresoc.v:0.0-0.0"
136373       case 10'1100000101
136374         assign { } { }
136375         assign $1\spr_o[9:0] 10'0001000101
136376       attribute \src "libresoc.v:0.0-0.0"
136377       case 10'1100000110
136378         assign { } { }
136379         assign $1\spr_o[9:0] 10'0001000110
136380       attribute \src "libresoc.v:0.0-0.0"
136381       case 10'1100000111
136382         assign { } { }
136383         assign $1\spr_o[9:0] 10'0001000111
136384       attribute \src "libresoc.v:0.0-0.0"
136385       case 10'1100001000
136386         assign { } { }
136387         assign $1\spr_o[9:0] 10'0001001000
136388       attribute \src "libresoc.v:0.0-0.0"
136389       case 10'1100001011
136390         assign { } { }
136391         assign $1\spr_o[9:0] 10'0001001001
136392       attribute \src "libresoc.v:0.0-0.0"
136393       case 10'1100001100
136394         assign { } { }
136395         assign $1\spr_o[9:0] 10'0001001010
136396       attribute \src "libresoc.v:0.0-0.0"
136397       case 10'1100001101
136398         assign { } { }
136399         assign $1\spr_o[9:0] 10'0001001011
136400       attribute \src "libresoc.v:0.0-0.0"
136401       case 10'1100001110
136402         assign { } { }
136403         assign $1\spr_o[9:0] 10'0001001100
136404       attribute \src "libresoc.v:0.0-0.0"
136405       case 10'1100010000
136406         assign { } { }
136407         assign $1\spr_o[9:0] 10'0001001101
136408       attribute \src "libresoc.v:0.0-0.0"
136409       case 10'1100010001
136410         assign { } { }
136411         assign $1\spr_o[9:0] 10'0001001110
136412       attribute \src "libresoc.v:0.0-0.0"
136413       case 10'1100010010
136414         assign { } { }
136415         assign $1\spr_o[9:0] 10'0001001111
136416       attribute \src "libresoc.v:0.0-0.0"
136417       case 10'1100010011
136418         assign { } { }
136419         assign $1\spr_o[9:0] 10'0001010000
136420       attribute \src "libresoc.v:0.0-0.0"
136421       case 10'1100010100
136422         assign { } { }
136423         assign $1\spr_o[9:0] 10'0001010001
136424       attribute \src "libresoc.v:0.0-0.0"
136425       case 10'1100010101
136426         assign { } { }
136427         assign $1\spr_o[9:0] 10'0001010010
136428       attribute \src "libresoc.v:0.0-0.0"
136429       case 10'1100010110
136430         assign { } { }
136431         assign $1\spr_o[9:0] 10'0001010011
136432       attribute \src "libresoc.v:0.0-0.0"
136433       case 10'1100010111
136434         assign { } { }
136435         assign $1\spr_o[9:0] 10'0001010100
136436       attribute \src "libresoc.v:0.0-0.0"
136437       case 10'1100011000
136438         assign { } { }
136439         assign $1\spr_o[9:0] 10'0001010101
136440       attribute \src "libresoc.v:0.0-0.0"
136441       case 10'1100011011
136442         assign { } { }
136443         assign $1\spr_o[9:0] 10'0001010110
136444       attribute \src "libresoc.v:0.0-0.0"
136445       case 10'1100011100
136446         assign { } { }
136447         assign $1\spr_o[9:0] 10'0001010111
136448       attribute \src "libresoc.v:0.0-0.0"
136449       case 10'1100011101
136450         assign { } { }
136451         assign $1\spr_o[9:0] 10'0001011000
136452       attribute \src "libresoc.v:0.0-0.0"
136453       case 10'1100011110
136454         assign { } { }
136455         assign $1\spr_o[9:0] 10'0001011001
136456       attribute \src "libresoc.v:0.0-0.0"
136457       case 10'1100100000
136458         assign { } { }
136459         assign $1\spr_o[9:0] 10'0001011010
136460       attribute \src "libresoc.v:0.0-0.0"
136461       case 10'1100100001
136462         assign { } { }
136463         assign $1\spr_o[9:0] 10'0001011011
136464       attribute \src "libresoc.v:0.0-0.0"
136465       case 10'1100100010
136466         assign { } { }
136467         assign $1\spr_o[9:0] 10'0001011100
136468       attribute \src "libresoc.v:0.0-0.0"
136469       case 10'1100100011
136470         assign { } { }
136471         assign $1\spr_o[9:0] 10'0001011101
136472       attribute \src "libresoc.v:0.0-0.0"
136473       case 10'1100100100
136474         assign { } { }
136475         assign $1\spr_o[9:0] 10'0001011110
136476       attribute \src "libresoc.v:0.0-0.0"
136477       case 10'1100100101
136478         assign { } { }
136479         assign $1\spr_o[9:0] 10'0001011111
136480       attribute \src "libresoc.v:0.0-0.0"
136481       case 10'1100100110
136482         assign { } { }
136483         assign $1\spr_o[9:0] 10'0001100000
136484       attribute \src "libresoc.v:0.0-0.0"
136485       case 10'1100101000
136486         assign { } { }
136487         assign $1\spr_o[9:0] 10'0001100001
136488       attribute \src "libresoc.v:0.0-0.0"
136489       case 10'1100101001
136490         assign { } { }
136491         assign $1\spr_o[9:0] 10'0001100010
136492       attribute \src "libresoc.v:0.0-0.0"
136493       case 10'1100101010
136494         assign { } { }
136495         assign $1\spr_o[9:0] 10'0001100011
136496       attribute \src "libresoc.v:0.0-0.0"
136497       case 10'1100101011
136498         assign { } { }
136499         assign $1\spr_o[9:0] 10'0001100100
136500       attribute \src "libresoc.v:0.0-0.0"
136501       case 10'1100110000
136502         assign { } { }
136503         assign $1\spr_o[9:0] 10'0001100110
136504       attribute \src "libresoc.v:0.0-0.0"
136505       case 10'1100110111
136506         assign { } { }
136507         assign $1\spr_o[9:0] 10'0001100111
136508       attribute \src "libresoc.v:0.0-0.0"
136509       case 10'1101010000
136510         assign { } { }
136511         assign $1\spr_o[9:0] 10'0001101000
136512       attribute \src "libresoc.v:0.0-0.0"
136513       case 10'1101010001
136514         assign { } { }
136515         assign $1\spr_o[9:0] 10'0001101001
136516       attribute \src "libresoc.v:0.0-0.0"
136517       case 10'1101010111
136518         assign { } { }
136519         assign $1\spr_o[9:0] 10'0001101010
136520       attribute \src "libresoc.v:0.0-0.0"
136521       case 10'1110000000
136522         assign { } { }
136523         assign $1\spr_o[9:0] 10'0001101011
136524       attribute \src "libresoc.v:0.0-0.0"
136525       case 10'1110000010
136526         assign { } { }
136527         assign $1\spr_o[9:0] 10'0001101100
136528       attribute \src "libresoc.v:0.0-0.0"
136529       case 10'1111111111
136530         assign { } { }
136531         assign $1\spr_o[9:0] 10'0001101101
136532       case
136533         assign $1\spr_o[9:0] 10'0000000000
136534     end
136535     sync always
136536       update \spr_o $0\spr_o[9:0]
136537   end
136538   attribute \src "libresoc.v:47270.3-47582.6"
136539   process $proc$libresoc.v:47270$1601
136540     assign { } { }
136541     assign { } { }
136542     assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
136543     attribute \src "libresoc.v:47271.5-47271.29"
136544     switch \initial
136545       attribute \src "libresoc.v:47271.9-47271.17"
136546       case 1'1
136547       case
136548     end
136549     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68"
136550     switch \spr_i
136551       attribute \src "libresoc.v:0.0-0.0"
136552       case 10'0000000011
136553         assign { } { }
136554         assign $1\spr_o_ok[0:0] 1'1
136555       attribute \src "libresoc.v:0.0-0.0"
136556       case 10'0000001101
136557         assign { } { }
136558         assign $1\spr_o_ok[0:0] 1'1
136559       attribute \src "libresoc.v:0.0-0.0"
136560       case 10'0000010001
136561         assign { } { }
136562         assign $1\spr_o_ok[0:0] 1'1
136563       attribute \src "libresoc.v:0.0-0.0"
136564       case 10'0000010010
136565         assign { } { }
136566         assign $1\spr_o_ok[0:0] 1'1
136567       attribute \src "libresoc.v:0.0-0.0"
136568       case 10'0000010011
136569         assign { } { }
136570         assign $1\spr_o_ok[0:0] 1'1
136571       attribute \src "libresoc.v:0.0-0.0"
136572       case 10'0000011100
136573         assign { } { }
136574         assign $1\spr_o_ok[0:0] 1'1
136575       attribute \src "libresoc.v:0.0-0.0"
136576       case 10'0000011101
136577         assign { } { }
136578         assign $1\spr_o_ok[0:0] 1'1
136579       attribute \src "libresoc.v:0.0-0.0"
136580       case 10'0000110000
136581         assign { } { }
136582         assign $1\spr_o_ok[0:0] 1'1
136583       attribute \src "libresoc.v:0.0-0.0"
136584       case 10'0000111101
136585         assign { } { }
136586         assign $1\spr_o_ok[0:0] 1'1
136587       attribute \src "libresoc.v:0.0-0.0"
136588       case 10'0010000000
136589         assign { } { }
136590         assign $1\spr_o_ok[0:0] 1'1
136591       attribute \src "libresoc.v:0.0-0.0"
136592       case 10'0010000001
136593         assign { } { }
136594         assign $1\spr_o_ok[0:0] 1'1
136595       attribute \src "libresoc.v:0.0-0.0"
136596       case 10'0010000010
136597         assign { } { }
136598         assign $1\spr_o_ok[0:0] 1'1
136599       attribute \src "libresoc.v:0.0-0.0"
136600       case 10'0010000011
136601         assign { } { }
136602         assign $1\spr_o_ok[0:0] 1'1
136603       attribute \src "libresoc.v:0.0-0.0"
136604       case 10'0010001000
136605         assign { } { }
136606         assign $1\spr_o_ok[0:0] 1'1
136607       attribute \src "libresoc.v:0.0-0.0"
136608       case 10'0010010000
136609         assign { } { }
136610         assign $1\spr_o_ok[0:0] 1'1
136611       attribute \src "libresoc.v:0.0-0.0"
136612       case 10'0010011000
136613         assign { } { }
136614         assign $1\spr_o_ok[0:0] 1'1
136615       attribute \src "libresoc.v:0.0-0.0"
136616       case 10'0010011001
136617         assign { } { }
136618         assign $1\spr_o_ok[0:0] 1'1
136619       attribute \src "libresoc.v:0.0-0.0"
136620       case 10'0010011101
136621         assign { } { }
136622         assign $1\spr_o_ok[0:0] 1'1
136623       attribute \src "libresoc.v:0.0-0.0"
136624       case 10'0010011110
136625         assign { } { }
136626         assign $1\spr_o_ok[0:0] 1'1
136627       attribute \src "libresoc.v:0.0-0.0"
136628       case 10'0010011111
136629         assign { } { }
136630         assign $1\spr_o_ok[0:0] 1'1
136631       attribute \src "libresoc.v:0.0-0.0"
136632       case 10'0010110000
136633         assign { } { }
136634         assign $1\spr_o_ok[0:0] 1'1
136635       attribute \src "libresoc.v:0.0-0.0"
136636       case 10'0010110100
136637         assign { } { }
136638         assign $1\spr_o_ok[0:0] 1'1
136639       attribute \src "libresoc.v:0.0-0.0"
136640       case 10'0010111010
136641         assign { } { }
136642         assign $1\spr_o_ok[0:0] 1'1
136643       attribute \src "libresoc.v:0.0-0.0"
136644       case 10'0010111011
136645         assign { } { }
136646         assign $1\spr_o_ok[0:0] 1'1
136647       attribute \src "libresoc.v:0.0-0.0"
136648       case 10'0010111100
136649         assign { } { }
136650         assign $1\spr_o_ok[0:0] 1'1
136651       attribute \src "libresoc.v:0.0-0.0"
136652       case 10'0010111110
136653         assign { } { }
136654         assign $1\spr_o_ok[0:0] 1'1
136655       attribute \src "libresoc.v:0.0-0.0"
136656       case 10'0100000000
136657         assign { } { }
136658         assign $1\spr_o_ok[0:0] 1'1
136659       attribute \src "libresoc.v:0.0-0.0"
136660       case 10'0100000011
136661         assign { } { }
136662         assign $1\spr_o_ok[0:0] 1'1
136663       attribute \src "libresoc.v:0.0-0.0"
136664       case 10'0100001101
136665         assign { } { }
136666         assign $1\spr_o_ok[0:0] 1'1
136667       attribute \src "libresoc.v:0.0-0.0"
136668       case 10'0100010000
136669         assign { } { }
136670         assign $1\spr_o_ok[0:0] 1'1
136671       attribute \src "libresoc.v:0.0-0.0"
136672       case 10'0100010001
136673         assign { } { }
136674         assign $1\spr_o_ok[0:0] 1'1
136675       attribute \src "libresoc.v:0.0-0.0"
136676       case 10'0100010010
136677         assign { } { }
136678         assign $1\spr_o_ok[0:0] 1'1
136679       attribute \src "libresoc.v:0.0-0.0"
136680       case 10'0100010011
136681         assign { } { }
136682         assign $1\spr_o_ok[0:0] 1'1
136683       attribute \src "libresoc.v:0.0-0.0"
136684       case 10'0100011011
136685         assign { } { }
136686         assign $1\spr_o_ok[0:0] 1'1
136687       attribute \src "libresoc.v:0.0-0.0"
136688       case 10'0100011100
136689         assign { } { }
136690         assign $1\spr_o_ok[0:0] 1'1
136691       attribute \src "libresoc.v:0.0-0.0"
136692       case 10'0100011101
136693         assign { } { }
136694         assign $1\spr_o_ok[0:0] 1'1
136695       attribute \src "libresoc.v:0.0-0.0"
136696       case 10'0100011110
136697         assign { } { }
136698         assign $1\spr_o_ok[0:0] 1'1
136699       attribute \src "libresoc.v:0.0-0.0"
136700       case 10'0100011111
136701         assign { } { }
136702         assign $1\spr_o_ok[0:0] 1'1
136703       attribute \src "libresoc.v:0.0-0.0"
136704       case 10'0100110000
136705         assign { } { }
136706         assign $1\spr_o_ok[0:0] 1'1
136707       attribute \src "libresoc.v:0.0-0.0"
136708       case 10'0100110001
136709         assign { } { }
136710         assign $1\spr_o_ok[0:0] 1'1
136711       attribute \src "libresoc.v:0.0-0.0"
136712       case 10'0100110010
136713         assign { } { }
136714         assign $1\spr_o_ok[0:0] 1'1
136715       attribute \src "libresoc.v:0.0-0.0"
136716       case 10'0100110011
136717         assign { } { }
136718         assign $1\spr_o_ok[0:0] 1'1
136719       attribute \src "libresoc.v:0.0-0.0"
136720       case 10'0100110100
136721         assign { } { }
136722         assign $1\spr_o_ok[0:0] 1'1
136723       attribute \src "libresoc.v:0.0-0.0"
136724       case 10'0100110101
136725         assign { } { }
136726         assign $1\spr_o_ok[0:0] 1'1
136727       attribute \src "libresoc.v:0.0-0.0"
136728       case 10'0100110110
136729         assign { } { }
136730         assign $1\spr_o_ok[0:0] 1'1
136731       attribute \src "libresoc.v:0.0-0.0"
136732       case 10'0100111001
136733         assign { } { }
136734         assign $1\spr_o_ok[0:0] 1'1
136735       attribute \src "libresoc.v:0.0-0.0"
136736       case 10'0100111010
136737         assign { } { }
136738         assign $1\spr_o_ok[0:0] 1'1
136739       attribute \src "libresoc.v:0.0-0.0"
136740       case 10'0100111011
136741         assign { } { }
136742         assign $1\spr_o_ok[0:0] 1'1
136743       attribute \src "libresoc.v:0.0-0.0"
136744       case 10'0100111110
136745         assign { } { }
136746         assign $1\spr_o_ok[0:0] 1'1
136747       attribute \src "libresoc.v:0.0-0.0"
136748       case 10'0100111111
136749         assign { } { }
136750         assign $1\spr_o_ok[0:0] 1'1
136751       attribute \src "libresoc.v:0.0-0.0"
136752       case 10'0101010000
136753         assign { } { }
136754         assign $1\spr_o_ok[0:0] 1'1
136755       attribute \src "libresoc.v:0.0-0.0"
136756       case 10'0101010001
136757         assign { } { }
136758         assign $1\spr_o_ok[0:0] 1'1
136759       attribute \src "libresoc.v:0.0-0.0"
136760       case 10'0101010010
136761         assign { } { }
136762         assign $1\spr_o_ok[0:0] 1'1
136763       attribute \src "libresoc.v:0.0-0.0"
136764       case 10'0101010011
136765         assign { } { }
136766         assign $1\spr_o_ok[0:0] 1'1
136767       attribute \src "libresoc.v:0.0-0.0"
136768       case 10'0101011101
136769         assign { } { }
136770         assign $1\spr_o_ok[0:0] 1'1
136771       attribute \src "libresoc.v:0.0-0.0"
136772       case 10'0110111110
136773         assign { } { }
136774         assign $1\spr_o_ok[0:0] 1'1
136775       attribute \src "libresoc.v:0.0-0.0"
136776       case 10'0111010000
136777         assign { } { }
136778         assign $1\spr_o_ok[0:0] 1'1
136779       attribute \src "libresoc.v:0.0-0.0"
136780       case 10'1100000000
136781         assign { } { }
136782         assign $1\spr_o_ok[0:0] 1'1
136783       attribute \src "libresoc.v:0.0-0.0"
136784       case 10'1100000001
136785         assign { } { }
136786         assign $1\spr_o_ok[0:0] 1'1
136787       attribute \src "libresoc.v:0.0-0.0"
136788       case 10'1100000010
136789         assign { } { }
136790         assign $1\spr_o_ok[0:0] 1'1
136791       attribute \src "libresoc.v:0.0-0.0"
136792       case 10'1100000011
136793         assign { } { }
136794         assign $1\spr_o_ok[0:0] 1'1
136795       attribute \src "libresoc.v:0.0-0.0"
136796       case 10'1100000100
136797         assign { } { }
136798         assign $1\spr_o_ok[0:0] 1'1
136799       attribute \src "libresoc.v:0.0-0.0"
136800       case 10'1100000101
136801         assign { } { }
136802         assign $1\spr_o_ok[0:0] 1'1
136803       attribute \src "libresoc.v:0.0-0.0"
136804       case 10'1100000110
136805         assign { } { }
136806         assign $1\spr_o_ok[0:0] 1'1
136807       attribute \src "libresoc.v:0.0-0.0"
136808       case 10'1100000111
136809         assign { } { }
136810         assign $1\spr_o_ok[0:0] 1'1
136811       attribute \src "libresoc.v:0.0-0.0"
136812       case 10'1100001000
136813         assign { } { }
136814         assign $1\spr_o_ok[0:0] 1'1
136815       attribute \src "libresoc.v:0.0-0.0"
136816       case 10'1100001011
136817         assign { } { }
136818         assign $1\spr_o_ok[0:0] 1'1
136819       attribute \src "libresoc.v:0.0-0.0"
136820       case 10'1100001100
136821         assign { } { }
136822         assign $1\spr_o_ok[0:0] 1'1
136823       attribute \src "libresoc.v:0.0-0.0"
136824       case 10'1100001101
136825         assign { } { }
136826         assign $1\spr_o_ok[0:0] 1'1
136827       attribute \src "libresoc.v:0.0-0.0"
136828       case 10'1100001110
136829         assign { } { }
136830         assign $1\spr_o_ok[0:0] 1'1
136831       attribute \src "libresoc.v:0.0-0.0"
136832       case 10'1100010000
136833         assign { } { }
136834         assign $1\spr_o_ok[0:0] 1'1
136835       attribute \src "libresoc.v:0.0-0.0"
136836       case 10'1100010001
136837         assign { } { }
136838         assign $1\spr_o_ok[0:0] 1'1
136839       attribute \src "libresoc.v:0.0-0.0"
136840       case 10'1100010010
136841         assign { } { }
136842         assign $1\spr_o_ok[0:0] 1'1
136843       attribute \src "libresoc.v:0.0-0.0"
136844       case 10'1100010011
136845         assign { } { }
136846         assign $1\spr_o_ok[0:0] 1'1
136847       attribute \src "libresoc.v:0.0-0.0"
136848       case 10'1100010100
136849         assign { } { }
136850         assign $1\spr_o_ok[0:0] 1'1
136851       attribute \src "libresoc.v:0.0-0.0"
136852       case 10'1100010101
136853         assign { } { }
136854         assign $1\spr_o_ok[0:0] 1'1
136855       attribute \src "libresoc.v:0.0-0.0"
136856       case 10'1100010110
136857         assign { } { }
136858         assign $1\spr_o_ok[0:0] 1'1
136859       attribute \src "libresoc.v:0.0-0.0"
136860       case 10'1100010111
136861         assign { } { }
136862         assign $1\spr_o_ok[0:0] 1'1
136863       attribute \src "libresoc.v:0.0-0.0"
136864       case 10'1100011000
136865         assign { } { }
136866         assign $1\spr_o_ok[0:0] 1'1
136867       attribute \src "libresoc.v:0.0-0.0"
136868       case 10'1100011011
136869         assign { } { }
136870         assign $1\spr_o_ok[0:0] 1'1
136871       attribute \src "libresoc.v:0.0-0.0"
136872       case 10'1100011100
136873         assign { } { }
136874         assign $1\spr_o_ok[0:0] 1'1
136875       attribute \src "libresoc.v:0.0-0.0"
136876       case 10'1100011101
136877         assign { } { }
136878         assign $1\spr_o_ok[0:0] 1'1
136879       attribute \src "libresoc.v:0.0-0.0"
136880       case 10'1100011110
136881         assign { } { }
136882         assign $1\spr_o_ok[0:0] 1'1
136883       attribute \src "libresoc.v:0.0-0.0"
136884       case 10'1100100000
136885         assign { } { }
136886         assign $1\spr_o_ok[0:0] 1'1
136887       attribute \src "libresoc.v:0.0-0.0"
136888       case 10'1100100001
136889         assign { } { }
136890         assign $1\spr_o_ok[0:0] 1'1
136891       attribute \src "libresoc.v:0.0-0.0"
136892       case 10'1100100010
136893         assign { } { }
136894         assign $1\spr_o_ok[0:0] 1'1
136895       attribute \src "libresoc.v:0.0-0.0"
136896       case 10'1100100011
136897         assign { } { }
136898         assign $1\spr_o_ok[0:0] 1'1
136899       attribute \src "libresoc.v:0.0-0.0"
136900       case 10'1100100100
136901         assign { } { }
136902         assign $1\spr_o_ok[0:0] 1'1
136903       attribute \src "libresoc.v:0.0-0.0"
136904       case 10'1100100101
136905         assign { } { }
136906         assign $1\spr_o_ok[0:0] 1'1
136907       attribute \src "libresoc.v:0.0-0.0"
136908       case 10'1100100110
136909         assign { } { }
136910         assign $1\spr_o_ok[0:0] 1'1
136911       attribute \src "libresoc.v:0.0-0.0"
136912       case 10'1100101000
136913         assign { } { }
136914         assign $1\spr_o_ok[0:0] 1'1
136915       attribute \src "libresoc.v:0.0-0.0"
136916       case 10'1100101001
136917         assign { } { }
136918         assign $1\spr_o_ok[0:0] 1'1
136919       attribute \src "libresoc.v:0.0-0.0"
136920       case 10'1100101010
136921         assign { } { }
136922         assign $1\spr_o_ok[0:0] 1'1
136923       attribute \src "libresoc.v:0.0-0.0"
136924       case 10'1100101011
136925         assign { } { }
136926         assign $1\spr_o_ok[0:0] 1'1
136927       attribute \src "libresoc.v:0.0-0.0"
136928       case 10'1100110000
136929         assign { } { }
136930         assign $1\spr_o_ok[0:0] 1'1
136931       attribute \src "libresoc.v:0.0-0.0"
136932       case 10'1100110111
136933         assign { } { }
136934         assign $1\spr_o_ok[0:0] 1'1
136935       attribute \src "libresoc.v:0.0-0.0"
136936       case 10'1101010000
136937         assign { } { }
136938         assign $1\spr_o_ok[0:0] 1'1
136939       attribute \src "libresoc.v:0.0-0.0"
136940       case 10'1101010001
136941         assign { } { }
136942         assign $1\spr_o_ok[0:0] 1'1
136943       attribute \src "libresoc.v:0.0-0.0"
136944       case 10'1101010111
136945         assign { } { }
136946         assign $1\spr_o_ok[0:0] 1'1
136947       attribute \src "libresoc.v:0.0-0.0"
136948       case 10'1110000000
136949         assign { } { }
136950         assign $1\spr_o_ok[0:0] 1'1
136951       attribute \src "libresoc.v:0.0-0.0"
136952       case 10'1110000010
136953         assign { } { }
136954         assign $1\spr_o_ok[0:0] 1'1
136955       attribute \src "libresoc.v:0.0-0.0"
136956       case 10'1111111111
136957         assign { } { }
136958         assign $1\spr_o_ok[0:0] 1'1
136959       case
136960         assign $1\spr_o_ok[0:0] 1'0
136961     end
136962     sync always
136963       update \spr_o_ok $0\spr_o_ok[0:0]
136964   end
136965 end
136966 attribute \src "libresoc.v:47588.1-48717.10"
136967 attribute \cells_not_processed 1
136968 attribute \top 1
136969 attribute \nmigen.hierarchy "test_issuer"
136970 attribute \generator "nMigen"
136971 module \test_issuer
136972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
136973   wire input 9 \TAP_bus__tck
136974   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
136975   wire input 7 \TAP_bus__tdi
136976   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
136977   wire output 6 \TAP_bus__tdo
136978   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
136979   wire input 8 \TAP_bus__tms
136980   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105"
136981   wire output 5 \busy_o
136982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
136983   wire input 372 \clk
136984   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
136985   wire width 2 input 374 \clk_sel_i
136986   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104"
136987   wire input 4 \core_bigendian_i
136988   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
136989   wire input 344 \dbus__ack
136990   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
136991   wire width 45 input 338 \dbus__adr
136992   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
136993   wire width 2 input 347 \dbus__bte
136994   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
136995   wire width 3 input 346 \dbus__cti
136996   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
136997   wire input 342 \dbus__cyc
136998   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
136999   wire width 64 input 340 \dbus__dat_r
137000   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
137001   wire width 64 input 339 \dbus__dat_w
137002   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
137003   wire input 348 \dbus__err
137004   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
137005   wire width 8 input 341 \dbus__sel
137006   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
137007   wire input 343 \dbus__stb
137008   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
137009   wire input 345 \dbus__we
137010   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137011   wire output 19 \eint_0__core__i
137012   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137013   wire input 20 \eint_0__pad__i
137014   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137015   wire output 21 \eint_1__core__i
137016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137017   wire input 22 \eint_1__pad__i
137018   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137019   wire output 23 \eint_2__core__i
137020   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137021   wire input 24 \eint_2__pad__i
137022   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137023   wire output 37 \gpio_e10__core__i
137024   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137025   wire input 38 \gpio_e10__core__o
137026   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137027   wire input 39 \gpio_e10__core__oe
137028   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137029   wire input 40 \gpio_e10__pad__i
137030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137031   wire output 41 \gpio_e10__pad__o
137032   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137033   wire output 42 \gpio_e10__pad__oe
137034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137035   wire output 43 \gpio_e11__core__i
137036   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137037   wire input 44 \gpio_e11__core__o
137038   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137039   wire input 45 \gpio_e11__core__oe
137040   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137041   wire input 46 \gpio_e11__pad__i
137042   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137043   wire output 47 \gpio_e11__pad__o
137044   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137045   wire output 48 \gpio_e11__pad__oe
137046   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137047   wire output 49 \gpio_e12__core__i
137048   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137049   wire input 50 \gpio_e12__core__o
137050   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137051   wire input 51 \gpio_e12__core__oe
137052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137053   wire input 52 \gpio_e12__pad__i
137054   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137055   wire output 53 \gpio_e12__pad__o
137056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137057   wire output 54 \gpio_e12__pad__oe
137058   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137059   wire output 55 \gpio_e13__core__i
137060   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137061   wire input 56 \gpio_e13__core__o
137062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137063   wire input 57 \gpio_e13__core__oe
137064   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137065   wire input 58 \gpio_e13__pad__i
137066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137067   wire output 59 \gpio_e13__pad__o
137068   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137069   wire output 60 \gpio_e13__pad__oe
137070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137071   wire output 61 \gpio_e14__core__i
137072   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137073   wire input 62 \gpio_e14__core__o
137074   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137075   wire input 63 \gpio_e14__core__oe
137076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137077   wire input 64 \gpio_e14__pad__i
137078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137079   wire output 65 \gpio_e14__pad__o
137080   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137081   wire output 66 \gpio_e14__pad__oe
137082   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137083   wire output 67 \gpio_e15__core__i
137084   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137085   wire input 68 \gpio_e15__core__o
137086   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137087   wire input 69 \gpio_e15__core__oe
137088   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137089   wire input 70 \gpio_e15__pad__i
137090   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137091   wire output 71 \gpio_e15__pad__o
137092   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137093   wire output 72 \gpio_e15__pad__oe
137094   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137095   wire output 25 \gpio_e8__core__i
137096   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137097   wire input 26 \gpio_e8__core__o
137098   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137099   wire input 27 \gpio_e8__core__oe
137100   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137101   wire input 28 \gpio_e8__pad__i
137102   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137103   wire output 29 \gpio_e8__pad__o
137104   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137105   wire output 30 \gpio_e8__pad__oe
137106   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137107   wire output 31 \gpio_e9__core__i
137108   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137109   wire input 32 \gpio_e9__core__o
137110   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137111   wire input 33 \gpio_e9__core__oe
137112   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137113   wire input 34 \gpio_e9__pad__i
137114   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137115   wire output 35 \gpio_e9__pad__o
137116   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137117   wire output 36 \gpio_e9__pad__oe
137118   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137119   wire output 73 \gpio_s0__core__i
137120   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137121   wire input 74 \gpio_s0__core__o
137122   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137123   wire input 75 \gpio_s0__core__oe
137124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137125   wire input 76 \gpio_s0__pad__i
137126   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137127   wire output 77 \gpio_s0__pad__o
137128   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137129   wire output 78 \gpio_s0__pad__oe
137130   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137131   wire output 79 \gpio_s1__core__i
137132   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137133   wire input 80 \gpio_s1__core__o
137134   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137135   wire input 81 \gpio_s1__core__oe
137136   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137137   wire input 82 \gpio_s1__pad__i
137138   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137139   wire output 83 \gpio_s1__pad__o
137140   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137141   wire output 84 \gpio_s1__pad__oe
137142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137143   wire output 85 \gpio_s2__core__i
137144   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137145   wire input 86 \gpio_s2__core__o
137146   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137147   wire input 87 \gpio_s2__core__oe
137148   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137149   wire input 88 \gpio_s2__pad__i
137150   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137151   wire output 89 \gpio_s2__pad__o
137152   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137153   wire output 90 \gpio_s2__pad__oe
137154   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137155   wire output 91 \gpio_s3__core__i
137156   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137157   wire input 92 \gpio_s3__core__o
137158   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137159   wire input 93 \gpio_s3__core__oe
137160   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137161   wire input 94 \gpio_s3__pad__i
137162   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137163   wire output 95 \gpio_s3__pad__o
137164   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137165   wire output 96 \gpio_s3__pad__oe
137166   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137167   wire output 97 \gpio_s4__core__i
137168   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137169   wire input 98 \gpio_s4__core__o
137170   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137171   wire input 99 \gpio_s4__core__oe
137172   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137173   wire input 100 \gpio_s4__pad__i
137174   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137175   wire output 101 \gpio_s4__pad__o
137176   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137177   wire output 102 \gpio_s4__pad__oe
137178   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137179   wire output 103 \gpio_s5__core__i
137180   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137181   wire input 104 \gpio_s5__core__o
137182   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137183   wire input 105 \gpio_s5__core__oe
137184   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137185   wire input 106 \gpio_s5__pad__i
137186   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137187   wire output 107 \gpio_s5__pad__o
137188   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137189   wire output 108 \gpio_s5__pad__oe
137190   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137191   wire output 109 \gpio_s6__core__i
137192   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137193   wire input 110 \gpio_s6__core__o
137194   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137195   wire input 111 \gpio_s6__core__oe
137196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137197   wire input 112 \gpio_s6__pad__i
137198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137199   wire output 113 \gpio_s6__pad__o
137200   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137201   wire output 114 \gpio_s6__pad__oe
137202   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137203   wire output 115 \gpio_s7__core__i
137204   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137205   wire input 116 \gpio_s7__core__o
137206   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137207   wire input 117 \gpio_s7__core__oe
137208   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137209   wire input 118 \gpio_s7__pad__i
137210   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137211   wire output 119 \gpio_s7__pad__o
137212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137213   wire output 120 \gpio_s7__pad__oe
137214   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137215   wire input 333 \ibus__ack
137216   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137217   wire width 45 output 327 \ibus__adr
137218   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137219   wire width 2 input 336 \ibus__bte
137220   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137221   wire width 3 input 335 \ibus__cti
137222   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137223   wire output 331 \ibus__cyc
137224   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137225   wire width 64 input 329 \ibus__dat_r
137226   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137227   wire width 64 input 328 \ibus__dat_w
137228   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137229   wire input 337 \ibus__err
137230   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137231   wire width 8 output 330 \ibus__sel
137232   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137233   wire output 332 \ibus__stb
137234   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
137235   wire input 334 \ibus__we
137236   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137237   wire output 355 \icp_wb__ack
137238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137239   wire width 28 input 349 \icp_wb__adr
137240   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137241   wire width 2 input 358 \icp_wb__bte
137242   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137243   wire width 3 input 357 \icp_wb__cti
137244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137245   wire input 353 \icp_wb__cyc
137246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137247   wire width 32 output 351 \icp_wb__dat_r
137248   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137249   wire width 32 input 350 \icp_wb__dat_w
137250   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137251   wire input 359 \icp_wb__err
137252   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137253   wire width 4 input 352 \icp_wb__sel
137254   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137255   wire input 354 \icp_wb__stb
137256   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
137257   wire input 356 \icp_wb__we
137258   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137259   wire output 366 \ics_wb__ack
137260   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137261   wire width 28 input 360 \ics_wb__adr
137262   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137263   wire width 2 input 369 \ics_wb__bte
137264   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137265   wire width 3 input 368 \ics_wb__cti
137266   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137267   wire input 364 \ics_wb__cyc
137268   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137269   wire width 32 output 362 \ics_wb__dat_r
137270   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137271   wire width 32 input 361 \ics_wb__dat_w
137272   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137273   wire input 370 \ics_wb__err
137274   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137275   wire width 4 input 363 \ics_wb__sel
137276   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137277   wire input 365 \ics_wb__stb
137278   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
137279   wire input 367 \ics_wb__we
137280   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
137281   wire width 16 input 371 \int_level_i
137282   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137283   wire input 17 \jtag_wb__ack
137284   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137285   wire width 29 output 10 \jtag_wb__adr
137286   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137287   wire output 14 \jtag_wb__cyc
137288   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137289   wire width 64 input 12 \jtag_wb__dat_r
137290   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137291   wire width 64 output 11 \jtag_wb__dat_w
137292   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137293   wire input 18 \jtag_wb__err
137294   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137295   wire output 13 \jtag_wb__sel
137296   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137297   wire output 15 \jtag_wb__stb
137298   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
137299   wire output 16 \jtag_wb__we
137300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:106"
137301   wire input 3 \memerr_o
137302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137303   wire input 121 \mspi0_clk__core__o
137304   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137305   wire output 122 \mspi0_clk__pad__o
137306   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137307   wire input 123 \mspi0_cs_n__core__o
137308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137309   wire output 124 \mspi0_cs_n__pad__o
137310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137311   wire output 127 \mspi0_miso__core__i
137312   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137313   wire input 128 \mspi0_miso__pad__i
137314   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137315   wire input 125 \mspi0_mosi__core__o
137316   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137317   wire output 126 \mspi0_mosi__pad__o
137318   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137319   wire input 129 \mspi1_clk__core__o
137320   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137321   wire output 130 \mspi1_clk__pad__o
137322   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137323   wire input 131 \mspi1_cs_n__core__o
137324   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137325   wire output 132 \mspi1_cs_n__pad__o
137326   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137327   wire output 135 \mspi1_miso__core__i
137328   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137329   wire input 136 \mspi1_miso__pad__i
137330   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137331   wire input 133 \mspi1_mosi__core__o
137332   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137333   wire output 134 \mspi1_mosi__pad__o
137334   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137335   wire input 143 \mtwi_scl__core__o
137336   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137337   wire output 144 \mtwi_scl__pad__o
137338   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137339   wire output 137 \mtwi_sda__core__i
137340   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137341   wire input 138 \mtwi_sda__core__o
137342   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137343   wire input 139 \mtwi_sda__core__oe
137344   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137345   wire input 140 \mtwi_sda__pad__i
137346   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137347   wire output 141 \mtwi_sda__pad__o
137348   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137349   wire output 142 \mtwi_sda__pad__oe
137350   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
137351   wire width 64 input 377 \pc_i
137352   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
137353   wire input 1 \pc_i_ok
137354   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102"
137355   wire width 64 output 2 \pc_o
137356   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
137357   wire output 375 \pll_18_o
137358   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
137359   wire \pll_clk_24_i
137360   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11"
137361   wire \pll_clk_pll_o
137362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
137363   wire output 376 \pll_lck_o
137364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480"
137365   wire \pllclk_clk
137366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480"
137367   wire \pllclk_rst
137368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137369   wire input 145 \pwm_0__core__o
137370   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137371   wire output 146 \pwm_0__pad__o
137372   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137373   wire input 147 \pwm_1__core__o
137374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137375   wire output 148 \pwm_1__pad__o
137376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
137377   wire input 373 \rst
137378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137379   wire input 155 \sd0_clk__core__o
137380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137381   wire output 156 \sd0_clk__pad__o
137382   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137383   wire output 149 \sd0_cmd__core__i
137384   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137385   wire input 150 \sd0_cmd__core__o
137386   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137387   wire input 151 \sd0_cmd__core__oe
137388   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137389   wire input 152 \sd0_cmd__pad__i
137390   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137391   wire output 153 \sd0_cmd__pad__o
137392   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137393   wire output 154 \sd0_cmd__pad__oe
137394   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137395   wire output 157 \sd0_data0__core__i
137396   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137397   wire input 158 \sd0_data0__core__o
137398   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137399   wire input 159 \sd0_data0__core__oe
137400   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137401   wire input 160 \sd0_data0__pad__i
137402   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137403   wire output 161 \sd0_data0__pad__o
137404   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137405   wire output 162 \sd0_data0__pad__oe
137406   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137407   wire output 163 \sd0_data1__core__i
137408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137409   wire input 164 \sd0_data1__core__o
137410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137411   wire input 165 \sd0_data1__core__oe
137412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137413   wire input 166 \sd0_data1__pad__i
137414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137415   wire output 167 \sd0_data1__pad__o
137416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137417   wire output 168 \sd0_data1__pad__oe
137418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137419   wire output 169 \sd0_data2__core__i
137420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137421   wire input 170 \sd0_data2__core__o
137422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137423   wire input 171 \sd0_data2__core__oe
137424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137425   wire input 172 \sd0_data2__pad__i
137426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137427   wire output 173 \sd0_data2__pad__o
137428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137429   wire output 174 \sd0_data2__pad__oe
137430   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137431   wire output 175 \sd0_data3__core__i
137432   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137433   wire input 176 \sd0_data3__core__o
137434   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137435   wire input 177 \sd0_data3__core__oe
137436   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137437   wire input 178 \sd0_data3__pad__i
137438   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137439   wire output 179 \sd0_data3__pad__o
137440   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137441   wire output 180 \sd0_data3__pad__oe
137442   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137443   wire input 231 \sdr_a_0__core__o
137444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137445   wire output 232 \sdr_a_0__pad__o
137446   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137447   wire input 267 \sdr_a_10__core__o
137448   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137449   wire output 268 \sdr_a_10__pad__o
137450   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137451   wire input 269 \sdr_a_11__core__o
137452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137453   wire output 270 \sdr_a_11__pad__o
137454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137455   wire input 271 \sdr_a_12__core__o
137456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137457   wire output 272 \sdr_a_12__pad__o
137458   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137459   wire input 233 \sdr_a_1__core__o
137460   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137461   wire output 234 \sdr_a_1__pad__o
137462   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137463   wire input 235 \sdr_a_2__core__o
137464   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137465   wire output 236 \sdr_a_2__pad__o
137466   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137467   wire input 237 \sdr_a_3__core__o
137468   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137469   wire output 238 \sdr_a_3__pad__o
137470   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137471   wire input 239 \sdr_a_4__core__o
137472   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137473   wire output 240 \sdr_a_4__pad__o
137474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137475   wire input 241 \sdr_a_5__core__o
137476   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137477   wire output 242 \sdr_a_5__pad__o
137478   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137479   wire input 243 \sdr_a_6__core__o
137480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137481   wire output 244 \sdr_a_6__pad__o
137482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137483   wire input 245 \sdr_a_7__core__o
137484   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137485   wire output 246 \sdr_a_7__pad__o
137486   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137487   wire input 247 \sdr_a_8__core__o
137488   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137489   wire output 248 \sdr_a_8__pad__o
137490   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137491   wire input 249 \sdr_a_9__core__o
137492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137493   wire output 250 \sdr_a_9__pad__o
137494   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137495   wire input 251 \sdr_ba_0__core__o
137496   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137497   wire output 252 \sdr_ba_0__pad__o
137498   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137499   wire input 253 \sdr_ba_1__core__o
137500   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137501   wire output 254 \sdr_ba_1__pad__o
137502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137503   wire input 261 \sdr_cas_n__core__o
137504   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137505   wire output 262 \sdr_cas_n__pad__o
137506   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137507   wire input 257 \sdr_cke__core__o
137508   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137509   wire output 258 \sdr_cke__pad__o
137510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137511   wire input 255 \sdr_clock__core__o
137512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137513   wire output 256 \sdr_clock__pad__o
137514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137515   wire input 265 \sdr_cs_n__core__o
137516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137517   wire output 266 \sdr_cs_n__pad__o
137518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137519   wire input 181 \sdr_dm_0__core__o
137520   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137521   wire output 182 \sdr_dm_0__pad__o
137522   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137523   wire output 273 \sdr_dm_1__core__i
137524   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137525   wire input 274 \sdr_dm_1__core__o
137526   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137527   wire input 275 \sdr_dm_1__core__oe
137528   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137529   wire input 276 \sdr_dm_1__pad__i
137530   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137531   wire output 277 \sdr_dm_1__pad__o
137532   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137533   wire output 278 \sdr_dm_1__pad__oe
137534   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137535   wire output 183 \sdr_dq_0__core__i
137536   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137537   wire input 184 \sdr_dq_0__core__o
137538   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137539   wire input 185 \sdr_dq_0__core__oe
137540   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137541   wire input 186 \sdr_dq_0__pad__i
137542   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137543   wire output 187 \sdr_dq_0__pad__o
137544   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137545   wire output 188 \sdr_dq_0__pad__oe
137546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137547   wire output 291 \sdr_dq_10__core__i
137548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137549   wire input 292 \sdr_dq_10__core__o
137550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137551   wire input 293 \sdr_dq_10__core__oe
137552   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137553   wire input 294 \sdr_dq_10__pad__i
137554   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137555   wire output 295 \sdr_dq_10__pad__o
137556   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137557   wire output 296 \sdr_dq_10__pad__oe
137558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137559   wire output 297 \sdr_dq_11__core__i
137560   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137561   wire input 298 \sdr_dq_11__core__o
137562   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137563   wire input 299 \sdr_dq_11__core__oe
137564   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137565   wire input 300 \sdr_dq_11__pad__i
137566   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137567   wire output 301 \sdr_dq_11__pad__o
137568   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137569   wire output 302 \sdr_dq_11__pad__oe
137570   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137571   wire output 303 \sdr_dq_12__core__i
137572   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137573   wire input 304 \sdr_dq_12__core__o
137574   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137575   wire input 305 \sdr_dq_12__core__oe
137576   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137577   wire input 306 \sdr_dq_12__pad__i
137578   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137579   wire output 307 \sdr_dq_12__pad__o
137580   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137581   wire output 308 \sdr_dq_12__pad__oe
137582   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137583   wire output 309 \sdr_dq_13__core__i
137584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137585   wire input 310 \sdr_dq_13__core__o
137586   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137587   wire input 311 \sdr_dq_13__core__oe
137588   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137589   wire input 312 \sdr_dq_13__pad__i
137590   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137591   wire output 313 \sdr_dq_13__pad__o
137592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137593   wire output 314 \sdr_dq_13__pad__oe
137594   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137595   wire output 315 \sdr_dq_14__core__i
137596   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137597   wire input 316 \sdr_dq_14__core__o
137598   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137599   wire input 317 \sdr_dq_14__core__oe
137600   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137601   wire input 318 \sdr_dq_14__pad__i
137602   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137603   wire output 319 \sdr_dq_14__pad__o
137604   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137605   wire output 320 \sdr_dq_14__pad__oe
137606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137607   wire output 321 \sdr_dq_15__core__i
137608   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137609   wire input 322 \sdr_dq_15__core__o
137610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137611   wire input 323 \sdr_dq_15__core__oe
137612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137613   wire input 324 \sdr_dq_15__pad__i
137614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137615   wire output 325 \sdr_dq_15__pad__o
137616   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137617   wire output 326 \sdr_dq_15__pad__oe
137618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137619   wire output 189 \sdr_dq_1__core__i
137620   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137621   wire input 190 \sdr_dq_1__core__o
137622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137623   wire input 191 \sdr_dq_1__core__oe
137624   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137625   wire input 192 \sdr_dq_1__pad__i
137626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137627   wire output 193 \sdr_dq_1__pad__o
137628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137629   wire output 194 \sdr_dq_1__pad__oe
137630   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137631   wire output 195 \sdr_dq_2__core__i
137632   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137633   wire input 196 \sdr_dq_2__core__o
137634   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137635   wire input 197 \sdr_dq_2__core__oe
137636   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137637   wire input 198 \sdr_dq_2__pad__i
137638   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137639   wire output 199 \sdr_dq_2__pad__o
137640   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137641   wire output 200 \sdr_dq_2__pad__oe
137642   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137643   wire output 201 \sdr_dq_3__core__i
137644   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137645   wire input 202 \sdr_dq_3__core__o
137646   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137647   wire input 203 \sdr_dq_3__core__oe
137648   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137649   wire input 204 \sdr_dq_3__pad__i
137650   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137651   wire output 205 \sdr_dq_3__pad__o
137652   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137653   wire output 206 \sdr_dq_3__pad__oe
137654   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137655   wire output 207 \sdr_dq_4__core__i
137656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137657   wire input 208 \sdr_dq_4__core__o
137658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137659   wire input 209 \sdr_dq_4__core__oe
137660   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137661   wire input 210 \sdr_dq_4__pad__i
137662   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137663   wire output 211 \sdr_dq_4__pad__o
137664   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137665   wire output 212 \sdr_dq_4__pad__oe
137666   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137667   wire output 213 \sdr_dq_5__core__i
137668   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137669   wire input 214 \sdr_dq_5__core__o
137670   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137671   wire input 215 \sdr_dq_5__core__oe
137672   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137673   wire input 216 \sdr_dq_5__pad__i
137674   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137675   wire output 217 \sdr_dq_5__pad__o
137676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137677   wire output 218 \sdr_dq_5__pad__oe
137678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137679   wire output 219 \sdr_dq_6__core__i
137680   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137681   wire input 220 \sdr_dq_6__core__o
137682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137683   wire input 221 \sdr_dq_6__core__oe
137684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137685   wire input 222 \sdr_dq_6__pad__i
137686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137687   wire output 223 \sdr_dq_6__pad__o
137688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137689   wire output 224 \sdr_dq_6__pad__oe
137690   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137691   wire output 225 \sdr_dq_7__core__i
137692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137693   wire input 226 \sdr_dq_7__core__o
137694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137695   wire input 227 \sdr_dq_7__core__oe
137696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137697   wire input 228 \sdr_dq_7__pad__i
137698   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137699   wire output 229 \sdr_dq_7__pad__o
137700   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137701   wire output 230 \sdr_dq_7__pad__oe
137702   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137703   wire output 279 \sdr_dq_8__core__i
137704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137705   wire input 280 \sdr_dq_8__core__o
137706   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137707   wire input 281 \sdr_dq_8__core__oe
137708   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137709   wire input 282 \sdr_dq_8__pad__i
137710   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137711   wire output 283 \sdr_dq_8__pad__o
137712   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137713   wire output 284 \sdr_dq_8__pad__oe
137714   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137715   wire output 285 \sdr_dq_9__core__i
137716   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137717   wire input 286 \sdr_dq_9__core__o
137718   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137719   wire input 287 \sdr_dq_9__core__oe
137720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137721   wire input 288 \sdr_dq_9__pad__i
137722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137723   wire output 289 \sdr_dq_9__pad__o
137724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137725   wire output 290 \sdr_dq_9__pad__oe
137726   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137727   wire input 259 \sdr_ras_n__core__o
137728   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137729   wire output 260 \sdr_ras_n__pad__o
137730   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137731   wire input 263 \sdr_we_n__core__o
137732   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
137733   wire output 264 \sdr_we_n__pad__o
137734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
137735   wire \ti_coresync_clk
137736   attribute \module_not_derived 1
137737   attribute \src "libresoc.v:48353.7-48359.4"
137738   cell \pll \pll
137739     connect \clk_24_i \pll_clk_24_i
137740     connect \clk_pll_o \pll_clk_pll_o
137741     connect \clk_sel_i \clk_sel_i
137742     connect \pll_18_o \pll_18_o
137743     connect \pll_lck_o \pll_lck_o
137744   end
137745   attribute \module_not_derived 1
137746   attribute \src "libresoc.v:48360.6-48712.4"
137747   cell \ti \ti
137748     connect \TAP_bus__tck \TAP_bus__tck
137749     connect \TAP_bus__tdi \TAP_bus__tdi
137750     connect \TAP_bus__tdo \TAP_bus__tdo
137751     connect \TAP_bus__tms \TAP_bus__tms
137752     connect \busy_o \busy_o
137753     connect \clk \clk
137754     connect \core_bigendian_i \core_bigendian_i
137755     connect \coresync_clk \ti_coresync_clk
137756     connect \eint_0__core__i \eint_0__core__i
137757     connect \eint_0__pad__i \eint_0__pad__i
137758     connect \eint_1__core__i \eint_1__core__i
137759     connect \eint_1__pad__i \eint_1__pad__i
137760     connect \eint_2__core__i \eint_2__core__i
137761     connect \eint_2__pad__i \eint_2__pad__i
137762     connect \gpio_e10__core__i \gpio_e10__core__i
137763     connect \gpio_e10__core__o \gpio_e10__core__o
137764     connect \gpio_e10__core__oe \gpio_e10__core__oe
137765     connect \gpio_e10__pad__i \gpio_e10__pad__i
137766     connect \gpio_e10__pad__o \gpio_e10__pad__o
137767     connect \gpio_e10__pad__oe \gpio_e10__pad__oe
137768     connect \gpio_e11__core__i \gpio_e11__core__i
137769     connect \gpio_e11__core__o \gpio_e11__core__o
137770     connect \gpio_e11__core__oe \gpio_e11__core__oe
137771     connect \gpio_e11__pad__i \gpio_e11__pad__i
137772     connect \gpio_e11__pad__o \gpio_e11__pad__o
137773     connect \gpio_e11__pad__oe \gpio_e11__pad__oe
137774     connect \gpio_e12__core__i \gpio_e12__core__i
137775     connect \gpio_e12__core__o \gpio_e12__core__o
137776     connect \gpio_e12__core__oe \gpio_e12__core__oe
137777     connect \gpio_e12__pad__i \gpio_e12__pad__i
137778     connect \gpio_e12__pad__o \gpio_e12__pad__o
137779     connect \gpio_e12__pad__oe \gpio_e12__pad__oe
137780     connect \gpio_e13__core__i \gpio_e13__core__i
137781     connect \gpio_e13__core__o \gpio_e13__core__o
137782     connect \gpio_e13__core__oe \gpio_e13__core__oe
137783     connect \gpio_e13__pad__i \gpio_e13__pad__i
137784     connect \gpio_e13__pad__o \gpio_e13__pad__o
137785     connect \gpio_e13__pad__oe \gpio_e13__pad__oe
137786     connect \gpio_e14__core__i \gpio_e14__core__i
137787     connect \gpio_e14__core__o \gpio_e14__core__o
137788     connect \gpio_e14__core__oe \gpio_e14__core__oe
137789     connect \gpio_e14__pad__i \gpio_e14__pad__i
137790     connect \gpio_e14__pad__o \gpio_e14__pad__o
137791     connect \gpio_e14__pad__oe \gpio_e14__pad__oe
137792     connect \gpio_e15__core__i \gpio_e15__core__i
137793     connect \gpio_e15__core__o \gpio_e15__core__o
137794     connect \gpio_e15__core__oe \gpio_e15__core__oe
137795     connect \gpio_e15__pad__i \gpio_e15__pad__i
137796     connect \gpio_e15__pad__o \gpio_e15__pad__o
137797     connect \gpio_e15__pad__oe \gpio_e15__pad__oe
137798     connect \gpio_e8__core__i \gpio_e8__core__i
137799     connect \gpio_e8__core__o \gpio_e8__core__o
137800     connect \gpio_e8__core__oe \gpio_e8__core__oe
137801     connect \gpio_e8__pad__i \gpio_e8__pad__i
137802     connect \gpio_e8__pad__o \gpio_e8__pad__o
137803     connect \gpio_e8__pad__oe \gpio_e8__pad__oe
137804     connect \gpio_e9__core__i \gpio_e9__core__i
137805     connect \gpio_e9__core__o \gpio_e9__core__o
137806     connect \gpio_e9__core__oe \gpio_e9__core__oe
137807     connect \gpio_e9__pad__i \gpio_e9__pad__i
137808     connect \gpio_e9__pad__o \gpio_e9__pad__o
137809     connect \gpio_e9__pad__oe \gpio_e9__pad__oe
137810     connect \gpio_s0__core__i \gpio_s0__core__i
137811     connect \gpio_s0__core__o \gpio_s0__core__o
137812     connect \gpio_s0__core__oe \gpio_s0__core__oe
137813     connect \gpio_s0__pad__i \gpio_s0__pad__i
137814     connect \gpio_s0__pad__o \gpio_s0__pad__o
137815     connect \gpio_s0__pad__oe \gpio_s0__pad__oe
137816     connect \gpio_s1__core__i \gpio_s1__core__i
137817     connect \gpio_s1__core__o \gpio_s1__core__o
137818     connect \gpio_s1__core__oe \gpio_s1__core__oe
137819     connect \gpio_s1__pad__i \gpio_s1__pad__i
137820     connect \gpio_s1__pad__o \gpio_s1__pad__o
137821     connect \gpio_s1__pad__oe \gpio_s1__pad__oe
137822     connect \gpio_s2__core__i \gpio_s2__core__i
137823     connect \gpio_s2__core__o \gpio_s2__core__o
137824     connect \gpio_s2__core__oe \gpio_s2__core__oe
137825     connect \gpio_s2__pad__i \gpio_s2__pad__i
137826     connect \gpio_s2__pad__o \gpio_s2__pad__o
137827     connect \gpio_s2__pad__oe \gpio_s2__pad__oe
137828     connect \gpio_s3__core__i \gpio_s3__core__i
137829     connect \gpio_s3__core__o \gpio_s3__core__o
137830     connect \gpio_s3__core__oe \gpio_s3__core__oe
137831     connect \gpio_s3__pad__i \gpio_s3__pad__i
137832     connect \gpio_s3__pad__o \gpio_s3__pad__o
137833     connect \gpio_s3__pad__oe \gpio_s3__pad__oe
137834     connect \gpio_s4__core__i \gpio_s4__core__i
137835     connect \gpio_s4__core__o \gpio_s4__core__o
137836     connect \gpio_s4__core__oe \gpio_s4__core__oe
137837     connect \gpio_s4__pad__i \gpio_s4__pad__i
137838     connect \gpio_s4__pad__o \gpio_s4__pad__o
137839     connect \gpio_s4__pad__oe \gpio_s4__pad__oe
137840     connect \gpio_s5__core__i \gpio_s5__core__i
137841     connect \gpio_s5__core__o \gpio_s5__core__o
137842     connect \gpio_s5__core__oe \gpio_s5__core__oe
137843     connect \gpio_s5__pad__i \gpio_s5__pad__i
137844     connect \gpio_s5__pad__o \gpio_s5__pad__o
137845     connect \gpio_s5__pad__oe \gpio_s5__pad__oe
137846     connect \gpio_s6__core__i \gpio_s6__core__i
137847     connect \gpio_s6__core__o \gpio_s6__core__o
137848     connect \gpio_s6__core__oe \gpio_s6__core__oe
137849     connect \gpio_s6__pad__i \gpio_s6__pad__i
137850     connect \gpio_s6__pad__o \gpio_s6__pad__o
137851     connect \gpio_s6__pad__oe \gpio_s6__pad__oe
137852     connect \gpio_s7__core__i \gpio_s7__core__i
137853     connect \gpio_s7__core__o \gpio_s7__core__o
137854     connect \gpio_s7__core__oe \gpio_s7__core__oe
137855     connect \gpio_s7__pad__i \gpio_s7__pad__i
137856     connect \gpio_s7__pad__o \gpio_s7__pad__o
137857     connect \gpio_s7__pad__oe \gpio_s7__pad__oe
137858     connect \ibus__ack \ibus__ack
137859     connect \ibus__adr \ibus__adr
137860     connect \ibus__cyc \ibus__cyc
137861     connect \ibus__dat_r \ibus__dat_r
137862     connect \ibus__err \ibus__err
137863     connect \ibus__sel \ibus__sel
137864     connect \ibus__stb \ibus__stb
137865     connect \icp_wb__ack \icp_wb__ack
137866     connect \icp_wb__adr \icp_wb__adr
137867     connect \icp_wb__cyc \icp_wb__cyc
137868     connect \icp_wb__dat_r \icp_wb__dat_r
137869     connect \icp_wb__dat_w \icp_wb__dat_w
137870     connect \icp_wb__sel \icp_wb__sel
137871     connect \icp_wb__stb \icp_wb__stb
137872     connect \icp_wb__we \icp_wb__we
137873     connect \ics_wb__ack \ics_wb__ack
137874     connect \ics_wb__adr \ics_wb__adr
137875     connect \ics_wb__cyc \ics_wb__cyc
137876     connect \ics_wb__dat_r \ics_wb__dat_r
137877     connect \ics_wb__dat_w \ics_wb__dat_w
137878     connect \ics_wb__stb \ics_wb__stb
137879     connect \ics_wb__we \ics_wb__we
137880     connect \int_level_i \int_level_i
137881     connect \jtag_wb__ack \jtag_wb__ack
137882     connect \jtag_wb__adr \jtag_wb__adr
137883     connect \jtag_wb__cyc \jtag_wb__cyc
137884     connect \jtag_wb__dat_r \jtag_wb__dat_r
137885     connect \jtag_wb__dat_w \jtag_wb__dat_w
137886     connect \jtag_wb__sel \jtag_wb__sel
137887     connect \jtag_wb__stb \jtag_wb__stb
137888     connect \jtag_wb__we \jtag_wb__we
137889     connect \mspi0_clk__core__o \mspi0_clk__core__o
137890     connect \mspi0_clk__pad__o \mspi0_clk__pad__o
137891     connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o
137892     connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o
137893     connect \mspi0_miso__core__i \mspi0_miso__core__i
137894     connect \mspi0_miso__pad__i \mspi0_miso__pad__i
137895     connect \mspi0_mosi__core__o \mspi0_mosi__core__o
137896     connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o
137897     connect \mspi1_clk__core__o \mspi1_clk__core__o
137898     connect \mspi1_clk__pad__o \mspi1_clk__pad__o
137899     connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o
137900     connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o
137901     connect \mspi1_miso__core__i \mspi1_miso__core__i
137902     connect \mspi1_miso__pad__i \mspi1_miso__pad__i
137903     connect \mspi1_mosi__core__o \mspi1_mosi__core__o
137904     connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o
137905     connect \mtwi_scl__core__o \mtwi_scl__core__o
137906     connect \mtwi_scl__pad__o \mtwi_scl__pad__o
137907     connect \mtwi_sda__core__i \mtwi_sda__core__i
137908     connect \mtwi_sda__core__o \mtwi_sda__core__o
137909     connect \mtwi_sda__core__oe \mtwi_sda__core__oe
137910     connect \mtwi_sda__pad__i \mtwi_sda__pad__i
137911     connect \mtwi_sda__pad__o \mtwi_sda__pad__o
137912     connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe
137913     connect \pc_i \pc_i
137914     connect \pc_i_ok \pc_i_ok
137915     connect \pc_o \pc_o
137916     connect \pwm_0__core__o \pwm_0__core__o
137917     connect \pwm_0__pad__o \pwm_0__pad__o
137918     connect \pwm_1__core__o \pwm_1__core__o
137919     connect \pwm_1__pad__o \pwm_1__pad__o
137920     connect \rst \rst
137921     connect \sd0_clk__core__o \sd0_clk__core__o
137922     connect \sd0_clk__pad__o \sd0_clk__pad__o
137923     connect \sd0_cmd__core__i \sd0_cmd__core__i
137924     connect \sd0_cmd__core__o \sd0_cmd__core__o
137925     connect \sd0_cmd__core__oe \sd0_cmd__core__oe
137926     connect \sd0_cmd__pad__i \sd0_cmd__pad__i
137927     connect \sd0_cmd__pad__o \sd0_cmd__pad__o
137928     connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe
137929     connect \sd0_data0__core__i \sd0_data0__core__i
137930     connect \sd0_data0__core__o \sd0_data0__core__o
137931     connect \sd0_data0__core__oe \sd0_data0__core__oe
137932     connect \sd0_data0__pad__i \sd0_data0__pad__i
137933     connect \sd0_data0__pad__o \sd0_data0__pad__o
137934     connect \sd0_data0__pad__oe \sd0_data0__pad__oe
137935     connect \sd0_data1__core__i \sd0_data1__core__i
137936     connect \sd0_data1__core__o \sd0_data1__core__o
137937     connect \sd0_data1__core__oe \sd0_data1__core__oe
137938     connect \sd0_data1__pad__i \sd0_data1__pad__i
137939     connect \sd0_data1__pad__o \sd0_data1__pad__o
137940     connect \sd0_data1__pad__oe \sd0_data1__pad__oe
137941     connect \sd0_data2__core__i \sd0_data2__core__i
137942     connect \sd0_data2__core__o \sd0_data2__core__o
137943     connect \sd0_data2__core__oe \sd0_data2__core__oe
137944     connect \sd0_data2__pad__i \sd0_data2__pad__i
137945     connect \sd0_data2__pad__o \sd0_data2__pad__o
137946     connect \sd0_data2__pad__oe \sd0_data2__pad__oe
137947     connect \sd0_data3__core__i \sd0_data3__core__i
137948     connect \sd0_data3__core__o \sd0_data3__core__o
137949     connect \sd0_data3__core__oe \sd0_data3__core__oe
137950     connect \sd0_data3__pad__i \sd0_data3__pad__i
137951     connect \sd0_data3__pad__o \sd0_data3__pad__o
137952     connect \sd0_data3__pad__oe \sd0_data3__pad__oe
137953     connect \sdr_a_0__core__o \sdr_a_0__core__o
137954     connect \sdr_a_0__pad__o \sdr_a_0__pad__o
137955     connect \sdr_a_10__core__o \sdr_a_10__core__o
137956     connect \sdr_a_10__pad__o \sdr_a_10__pad__o
137957     connect \sdr_a_11__core__o \sdr_a_11__core__o
137958     connect \sdr_a_11__pad__o \sdr_a_11__pad__o
137959     connect \sdr_a_12__core__o \sdr_a_12__core__o
137960     connect \sdr_a_12__pad__o \sdr_a_12__pad__o
137961     connect \sdr_a_1__core__o \sdr_a_1__core__o
137962     connect \sdr_a_1__pad__o \sdr_a_1__pad__o
137963     connect \sdr_a_2__core__o \sdr_a_2__core__o
137964     connect \sdr_a_2__pad__o \sdr_a_2__pad__o
137965     connect \sdr_a_3__core__o \sdr_a_3__core__o
137966     connect \sdr_a_3__pad__o \sdr_a_3__pad__o
137967     connect \sdr_a_4__core__o \sdr_a_4__core__o
137968     connect \sdr_a_4__pad__o \sdr_a_4__pad__o
137969     connect \sdr_a_5__core__o \sdr_a_5__core__o
137970     connect \sdr_a_5__pad__o \sdr_a_5__pad__o
137971     connect \sdr_a_6__core__o \sdr_a_6__core__o
137972     connect \sdr_a_6__pad__o \sdr_a_6__pad__o
137973     connect \sdr_a_7__core__o \sdr_a_7__core__o
137974     connect \sdr_a_7__pad__o \sdr_a_7__pad__o
137975     connect \sdr_a_8__core__o \sdr_a_8__core__o
137976     connect \sdr_a_8__pad__o \sdr_a_8__pad__o
137977     connect \sdr_a_9__core__o \sdr_a_9__core__o
137978     connect \sdr_a_9__pad__o \sdr_a_9__pad__o
137979     connect \sdr_ba_0__core__o \sdr_ba_0__core__o
137980     connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o
137981     connect \sdr_ba_1__core__o \sdr_ba_1__core__o
137982     connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o
137983     connect \sdr_cas_n__core__o \sdr_cas_n__core__o
137984     connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o
137985     connect \sdr_cke__core__o \sdr_cke__core__o
137986     connect \sdr_cke__pad__o \sdr_cke__pad__o
137987     connect \sdr_clock__core__o \sdr_clock__core__o
137988     connect \sdr_clock__pad__o \sdr_clock__pad__o
137989     connect \sdr_cs_n__core__o \sdr_cs_n__core__o
137990     connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o
137991     connect \sdr_dm_0__core__o \sdr_dm_0__core__o
137992     connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o
137993     connect \sdr_dm_1__core__i \sdr_dm_1__core__i
137994     connect \sdr_dm_1__core__o \sdr_dm_1__core__o
137995     connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe
137996     connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i
137997     connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o
137998     connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe
137999     connect \sdr_dq_0__core__i \sdr_dq_0__core__i
138000     connect \sdr_dq_0__core__o \sdr_dq_0__core__o
138001     connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe
138002     connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i
138003     connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o
138004     connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe
138005     connect \sdr_dq_10__core__i \sdr_dq_10__core__i
138006     connect \sdr_dq_10__core__o \sdr_dq_10__core__o
138007     connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe
138008     connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i
138009     connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o
138010     connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe
138011     connect \sdr_dq_11__core__i \sdr_dq_11__core__i
138012     connect \sdr_dq_11__core__o \sdr_dq_11__core__o
138013     connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe
138014     connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i
138015     connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o
138016     connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe
138017     connect \sdr_dq_12__core__i \sdr_dq_12__core__i
138018     connect \sdr_dq_12__core__o \sdr_dq_12__core__o
138019     connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe
138020     connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i
138021     connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o
138022     connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe
138023     connect \sdr_dq_13__core__i \sdr_dq_13__core__i
138024     connect \sdr_dq_13__core__o \sdr_dq_13__core__o
138025     connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe
138026     connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i
138027     connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o
138028     connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe
138029     connect \sdr_dq_14__core__i \sdr_dq_14__core__i
138030     connect \sdr_dq_14__core__o \sdr_dq_14__core__o
138031     connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe
138032     connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i
138033     connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o
138034     connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe
138035     connect \sdr_dq_15__core__i \sdr_dq_15__core__i
138036     connect \sdr_dq_15__core__o \sdr_dq_15__core__o
138037     connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe
138038     connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i
138039     connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o
138040     connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe
138041     connect \sdr_dq_1__core__i \sdr_dq_1__core__i
138042     connect \sdr_dq_1__core__o \sdr_dq_1__core__o
138043     connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe
138044     connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i
138045     connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o
138046     connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe
138047     connect \sdr_dq_2__core__i \sdr_dq_2__core__i
138048     connect \sdr_dq_2__core__o \sdr_dq_2__core__o
138049     connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe
138050     connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i
138051     connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o
138052     connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe
138053     connect \sdr_dq_3__core__i \sdr_dq_3__core__i
138054     connect \sdr_dq_3__core__o \sdr_dq_3__core__o
138055     connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe
138056     connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i
138057     connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o
138058     connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe
138059     connect \sdr_dq_4__core__i \sdr_dq_4__core__i
138060     connect \sdr_dq_4__core__o \sdr_dq_4__core__o
138061     connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe
138062     connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i
138063     connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o
138064     connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe
138065     connect \sdr_dq_5__core__i \sdr_dq_5__core__i
138066     connect \sdr_dq_5__core__o \sdr_dq_5__core__o
138067     connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe
138068     connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i
138069     connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o
138070     connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe
138071     connect \sdr_dq_6__core__i \sdr_dq_6__core__i
138072     connect \sdr_dq_6__core__o \sdr_dq_6__core__o
138073     connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe
138074     connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i
138075     connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o
138076     connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe
138077     connect \sdr_dq_7__core__i \sdr_dq_7__core__i
138078     connect \sdr_dq_7__core__o \sdr_dq_7__core__o
138079     connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe
138080     connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i
138081     connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o
138082     connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe
138083     connect \sdr_dq_8__core__i \sdr_dq_8__core__i
138084     connect \sdr_dq_8__core__o \sdr_dq_8__core__o
138085     connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe
138086     connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i
138087     connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o
138088     connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe
138089     connect \sdr_dq_9__core__i \sdr_dq_9__core__i
138090     connect \sdr_dq_9__core__o \sdr_dq_9__core__o
138091     connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe
138092     connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i
138093     connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o
138094     connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe
138095     connect \sdr_ras_n__core__o \sdr_ras_n__core__o
138096     connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o
138097     connect \sdr_we_n__core__o \sdr_we_n__core__o
138098     connect \sdr_we_n__pad__o \sdr_we_n__pad__o
138099   end
138100   connect \ti_coresync_clk \pll_clk_pll_o
138101   connect \pllclk_rst \rst
138102   connect \pll_clk_24_i \clk
138103   connect \pllclk_clk \pll_clk_pll_o
138104 end
138105 attribute \src "libresoc.v:48721.1-52499.10"
138106 attribute \cells_not_processed 1
138107 attribute \nmigen.hierarchy "test_issuer.ti"
138108 attribute \generator "nMigen"
138109 module \ti
138110   attribute \src "libresoc.v:52231.3-52267.6"
138111   wire $0\bigendian_i$next[0:0]$2133
138112   attribute \src "libresoc.v:50848.3-50849.39"
138113   wire $0\bigendian_i[0:0]
138114   attribute \src "libresoc.v:51929.3-51941.6"
138115   wire width 4 $0\cia__ren[3:0]
138116   attribute \src "libresoc.v:52034.3-52156.6"
138117   wire width 8 $0\core_asmcode$next[7:0]$1851
138118   attribute \src "libresoc.v:50852.3-50853.41"
138119   wire width 8 $0\core_asmcode[7:0]
138120   attribute \src "libresoc.v:52034.3-52156.6"
138121   wire width 64 $0\core_core_cia$next[63:0]$1852
138122   attribute \src "libresoc.v:50928.3-50929.43"
138123   wire width 64 $0\core_core_cia[63:0]
138124   attribute \src "libresoc.v:52034.3-52156.6"
138125   wire width 8 $0\core_core_cr_rd$next[7:0]$1853
138126   attribute \src "libresoc.v:50972.3-50973.47"
138127   wire width 8 $0\core_core_cr_rd[7:0]
138128   attribute \src "libresoc.v:52034.3-52156.6"
138129   wire $0\core_core_cr_rd_ok$next[0:0]$1854
138130   attribute \src "libresoc.v:50974.3-50975.53"
138131   wire $0\core_core_cr_rd_ok[0:0]
138132   attribute \src "libresoc.v:52034.3-52156.6"
138133   wire width 8 $0\core_core_cr_wr$next[7:0]$1855
138134   attribute \src "libresoc.v:50976.3-50977.47"
138135   wire width 8 $0\core_core_cr_wr[7:0]
138136   attribute \src "libresoc.v:52034.3-52156.6"
138137   wire $0\core_core_cr_wr_ok$next[0:0]$1856
138138   attribute \src "libresoc.v:50978.3-50979.53"
138139   wire $0\core_core_cr_wr_ok[0:0]
138140   attribute \src "libresoc.v:52034.3-52156.6"
138141   wire $0\core_core_exc_$signal$50$next[0:0]$1857
138142   attribute \src "libresoc.v:50954.3-50955.67"
138143   wire $0\core_core_exc_$signal$50[0:0]$1726
138144   attribute \src "libresoc.v:48894.7-48894.40"
138145   wire $0\core_core_exc_$signal$50[0:0]$2172
138146   attribute \src "libresoc.v:52034.3-52156.6"
138147   wire $0\core_core_exc_$signal$51$next[0:0]$1858
138148   attribute \src "libresoc.v:50956.3-50957.67"
138149   wire $0\core_core_exc_$signal$51[0:0]$1728
138150   attribute \src "libresoc.v:48898.7-48898.40"
138151   wire $0\core_core_exc_$signal$51[0:0]$2174
138152   attribute \src "libresoc.v:52034.3-52156.6"
138153   wire $0\core_core_exc_$signal$52$next[0:0]$1859
138154   attribute \src "libresoc.v:50958.3-50959.67"
138155   wire $0\core_core_exc_$signal$52[0:0]$1730
138156   attribute \src "libresoc.v:48902.7-48902.40"
138157   wire $0\core_core_exc_$signal$52[0:0]$2176
138158   attribute \src "libresoc.v:52034.3-52156.6"
138159   wire $0\core_core_exc_$signal$53$next[0:0]$1860
138160   attribute \src "libresoc.v:50960.3-50961.67"
138161   wire $0\core_core_exc_$signal$53[0:0]$1732
138162   attribute \src "libresoc.v:48906.7-48906.40"
138163   wire $0\core_core_exc_$signal$53[0:0]$2178
138164   attribute \src "libresoc.v:52034.3-52156.6"
138165   wire $0\core_core_exc_$signal$54$next[0:0]$1861
138166   attribute \src "libresoc.v:50962.3-50963.67"
138167   wire $0\core_core_exc_$signal$54[0:0]$1734
138168   attribute \src "libresoc.v:48910.7-48910.40"
138169   wire $0\core_core_exc_$signal$54[0:0]$2180
138170   attribute \src "libresoc.v:52034.3-52156.6"
138171   wire $0\core_core_exc_$signal$55$next[0:0]$1862
138172   attribute \src "libresoc.v:50964.3-50965.67"
138173   wire $0\core_core_exc_$signal$55[0:0]$1736
138174   attribute \src "libresoc.v:48914.7-48914.40"
138175   wire $0\core_core_exc_$signal$55[0:0]$2182
138176   attribute \src "libresoc.v:52034.3-52156.6"
138177   wire $0\core_core_exc_$signal$56$next[0:0]$1863
138178   attribute \src "libresoc.v:50966.3-50967.67"
138179   wire $0\core_core_exc_$signal$56[0:0]$1738
138180   attribute \src "libresoc.v:48918.7-48918.40"
138181   wire $0\core_core_exc_$signal$56[0:0]$2184
138182   attribute \src "libresoc.v:52034.3-52156.6"
138183   wire $0\core_core_exc_$signal$next[0:0]$1864
138184   attribute \src "libresoc.v:50952.3-50953.61"
138185   wire $0\core_core_exc_$signal[0:0]$1724
138186   attribute \src "libresoc.v:48892.7-48892.37"
138187   wire $0\core_core_exc_$signal[0:0]$2170
138188   attribute \src "libresoc.v:52034.3-52156.6"
138189   wire width 12 $0\core_core_fn_unit$next[11:0]$1865
138190   attribute \src "libresoc.v:50934.3-50935.51"
138191   wire width 12 $0\core_core_fn_unit[11:0]
138192   attribute \src "libresoc.v:52034.3-52156.6"
138193   wire width 2 $0\core_core_input_carry$next[1:0]$1866
138194   attribute \src "libresoc.v:50948.3-50949.59"
138195   wire width 2 $0\core_core_input_carry[1:0]
138196   attribute \src "libresoc.v:52034.3-52156.6"
138197   wire width 32 $0\core_core_insn$next[31:0]$1867
138198   attribute \src "libresoc.v:50930.3-50931.45"
138199   wire width 32 $0\core_core_insn[31:0]
138200   attribute \src "libresoc.v:52034.3-52156.6"
138201   wire width 7 $0\core_core_insn_type$next[6:0]$1868
138202   attribute \src "libresoc.v:50932.3-50933.55"
138203   wire width 7 $0\core_core_insn_type[6:0]
138204   attribute \src "libresoc.v:52034.3-52156.6"
138205   wire $0\core_core_is_32bit$next[0:0]$1869
138206   attribute \src "libresoc.v:50980.3-50981.53"
138207   wire $0\core_core_is_32bit[0:0]
138208   attribute \src "libresoc.v:52034.3-52156.6"
138209   wire $0\core_core_lk$next[0:0]$1870
138210   attribute \src "libresoc.v:50936.3-50937.41"
138211   wire $0\core_core_lk[0:0]
138212   attribute \src "libresoc.v:52034.3-52156.6"
138213   wire width 64 $0\core_core_msr$next[63:0]$1871
138214   attribute \src "libresoc.v:50926.3-50927.43"
138215   wire width 64 $0\core_core_msr[63:0]
138216   attribute \src "libresoc.v:52034.3-52156.6"
138217   wire $0\core_core_oe$next[0:0]$1872
138218   attribute \src "libresoc.v:50942.3-50943.41"
138219   wire $0\core_core_oe[0:0]
138220   attribute \src "libresoc.v:52034.3-52156.6"
138221   wire $0\core_core_oe_ok$next[0:0]$1873
138222   attribute \src "libresoc.v:50944.3-50945.47"
138223   wire $0\core_core_oe_ok[0:0]
138224   attribute \src "libresoc.v:52034.3-52156.6"
138225   wire $0\core_core_rc$next[0:0]$1874
138226   attribute \src "libresoc.v:50938.3-50939.41"
138227   wire $0\core_core_rc[0:0]
138228   attribute \src "libresoc.v:52034.3-52156.6"
138229   wire $0\core_core_rc_ok$next[0:0]$1875
138230   attribute \src "libresoc.v:50940.3-50941.47"
138231   wire $0\core_core_rc_ok[0:0]
138232   attribute \src "libresoc.v:52034.3-52156.6"
138233   wire width 13 $0\core_core_trapaddr$next[12:0]$1876
138234   attribute \src "libresoc.v:50970.3-50971.53"
138235   wire width 13 $0\core_core_trapaddr[12:0]
138236   attribute \src "libresoc.v:52034.3-52156.6"
138237   wire width 8 $0\core_core_traptype$next[7:0]$1877
138238   attribute \src "libresoc.v:50950.3-50951.53"
138239   wire width 8 $0\core_core_traptype[7:0]
138240   attribute \src "libresoc.v:52034.3-52156.6"
138241   wire width 3 $0\core_cr_in1$next[2:0]$1878
138242   attribute \src "libresoc.v:50908.3-50909.39"
138243   wire width 3 $0\core_cr_in1[2:0]
138244   attribute \src "libresoc.v:52034.3-52156.6"
138245   wire $0\core_cr_in1_ok$next[0:0]$1879
138246   attribute \src "libresoc.v:50910.3-50911.45"
138247   wire $0\core_cr_in1_ok[0:0]
138248   attribute \src "libresoc.v:52034.3-52156.6"
138249   wire width 3 $0\core_cr_in2$48$next[2:0]$1880
138250   attribute \src "libresoc.v:50916.3-50917.47"
138251   wire width 3 $0\core_cr_in2$48[2:0]$1704
138252   attribute \src "libresoc.v:49079.13-49079.36"
138253   wire width 3 $0\core_cr_in2$48[2:0]$2202
138254   attribute \src "libresoc.v:52034.3-52156.6"
138255   wire width 3 $0\core_cr_in2$next[2:0]$1881
138256   attribute \src "libresoc.v:50912.3-50913.39"
138257   wire width 3 $0\core_cr_in2[2:0]
138258   attribute \src "libresoc.v:52034.3-52156.6"
138259   wire $0\core_cr_in2_ok$49$next[0:0]$1882
138260   attribute \src "libresoc.v:50918.3-50919.53"
138261   wire $0\core_cr_in2_ok$49[0:0]$1706
138262   attribute \src "libresoc.v:49087.7-49087.33"
138263   wire $0\core_cr_in2_ok$49[0:0]$2205
138264   attribute \src "libresoc.v:52034.3-52156.6"
138265   wire $0\core_cr_in2_ok$next[0:0]$1883
138266   attribute \src "libresoc.v:50914.3-50915.45"
138267   wire $0\core_cr_in2_ok[0:0]
138268   attribute \src "libresoc.v:52034.3-52156.6"
138269   wire width 3 $0\core_cr_out$next[2:0]$1884
138270   attribute \src "libresoc.v:50920.3-50921.39"
138271   wire width 3 $0\core_cr_out[2:0]
138272   attribute \src "libresoc.v:52034.3-52156.6"
138273   wire $0\core_cr_out_ok$next[0:0]$1885
138274   attribute \src "libresoc.v:50922.3-50923.45"
138275   wire $0\core_cr_out_ok[0:0]
138276   attribute \src "libresoc.v:51540.3-51571.6"
138277   wire width 64 $0\core_dec$next[63:0]$1772
138278   attribute \src "libresoc.v:50838.3-50839.33"
138279   wire width 64 $0\core_dec[63:0]
138280   attribute \src "libresoc.v:52034.3-52156.6"
138281   wire width 5 $0\core_ea$next[4:0]$1886
138282   attribute \src "libresoc.v:50860.3-50861.31"
138283   wire width 5 $0\core_ea[4:0]
138284   attribute \src "libresoc.v:52034.3-52156.6"
138285   wire $0\core_ea_ok$next[0:0]$1887
138286   attribute \src "libresoc.v:50862.3-50863.37"
138287   wire $0\core_ea_ok[0:0]
138288   attribute \src "libresoc.v:51540.3-51571.6"
138289   wire $0\core_eint$next[0:0]$1773
138290   attribute \src "libresoc.v:51006.3-51007.35"
138291   wire $0\core_eint[0:0]
138292   attribute \src "libresoc.v:52034.3-52156.6"
138293   wire width 3 $0\core_fast1$next[2:0]$1888
138294   attribute \src "libresoc.v:50890.3-50891.37"
138295   wire width 3 $0\core_fast1[2:0]
138296   attribute \src "libresoc.v:52034.3-52156.6"
138297   wire $0\core_fast1_ok$next[0:0]$1889
138298   attribute \src "libresoc.v:50892.3-50893.43"
138299   wire $0\core_fast1_ok[0:0]
138300   attribute \src "libresoc.v:52034.3-52156.6"
138301   wire width 3 $0\core_fast2$next[2:0]$1890
138302   attribute \src "libresoc.v:50894.3-50895.37"
138303   wire width 3 $0\core_fast2[2:0]
138304   attribute \src "libresoc.v:52034.3-52156.6"
138305   wire $0\core_fast2_ok$next[0:0]$1891
138306   attribute \src "libresoc.v:50896.3-50897.43"
138307   wire $0\core_fast2_ok[0:0]
138308   attribute \src "libresoc.v:52034.3-52156.6"
138309   wire width 3 $0\core_fasto1$next[2:0]$1892
138310   attribute \src "libresoc.v:50898.3-50899.39"
138311   wire width 3 $0\core_fasto1[2:0]
138312   attribute \src "libresoc.v:52034.3-52156.6"
138313   wire $0\core_fasto1_ok$next[0:0]$1893
138314   attribute \src "libresoc.v:50900.3-50901.45"
138315   wire $0\core_fasto1_ok[0:0]
138316   attribute \src "libresoc.v:52034.3-52156.6"
138317   wire width 3 $0\core_fasto2$next[2:0]$1894
138318   attribute \src "libresoc.v:50904.3-50905.39"
138319   wire width 3 $0\core_fasto2[2:0]
138320   attribute \src "libresoc.v:52034.3-52156.6"
138321   wire $0\core_fasto2_ok$next[0:0]$1895
138322   attribute \src "libresoc.v:50906.3-50907.45"
138323   wire $0\core_fasto2_ok[0:0]
138324   attribute \src "libresoc.v:51540.3-51571.6"
138325   wire width 64 $0\core_msr$next[63:0]$1774
138326   attribute \src "libresoc.v:50990.3-50991.33"
138327   wire width 64 $0\core_msr[63:0]
138328   attribute \src "libresoc.v:51540.3-51571.6"
138329   wire width 64 $0\core_pc$next[63:0]$1775
138330   attribute \src "libresoc.v:50968.3-50969.31"
138331   wire width 64 $0\core_pc[63:0]
138332   attribute \src "libresoc.v:52034.3-52156.6"
138333   wire width 5 $0\core_reg1$next[4:0]$1896
138334   attribute \src "libresoc.v:50864.3-50865.35"
138335   wire width 5 $0\core_reg1[4:0]
138336   attribute \src "libresoc.v:52034.3-52156.6"
138337   wire $0\core_reg1_ok$next[0:0]$1897
138338   attribute \src "libresoc.v:50866.3-50867.41"
138339   wire $0\core_reg1_ok[0:0]
138340   attribute \src "libresoc.v:52034.3-52156.6"
138341   wire width 5 $0\core_reg2$next[4:0]$1898
138342   attribute \src "libresoc.v:50868.3-50869.35"
138343   wire width 5 $0\core_reg2[4:0]
138344   attribute \src "libresoc.v:52034.3-52156.6"
138345   wire $0\core_reg2_ok$next[0:0]$1899
138346   attribute \src "libresoc.v:50870.3-50871.41"
138347   wire $0\core_reg2_ok[0:0]
138348   attribute \src "libresoc.v:52034.3-52156.6"
138349   wire width 5 $0\core_reg3$next[4:0]$1900
138350   attribute \src "libresoc.v:50872.3-50873.35"
138351   wire width 5 $0\core_reg3[4:0]
138352   attribute \src "libresoc.v:52034.3-52156.6"
138353   wire $0\core_reg3_ok$next[0:0]$1901
138354   attribute \src "libresoc.v:50874.3-50875.41"
138355   wire $0\core_reg3_ok[0:0]
138356   attribute \src "libresoc.v:52034.3-52156.6"
138357   wire width 5 $0\core_rego$next[4:0]$1902
138358   attribute \src "libresoc.v:50854.3-50855.35"
138359   wire width 5 $0\core_rego[4:0]
138360   attribute \src "libresoc.v:52034.3-52156.6"
138361   wire $0\core_rego_ok$next[0:0]$1903
138362   attribute \src "libresoc.v:50856.3-50857.41"
138363   wire $0\core_rego_ok[0:0]
138364   attribute \src "libresoc.v:52034.3-52156.6"
138365   wire width 10 $0\core_spr1$next[9:0]$1904
138366   attribute \src "libresoc.v:50882.3-50883.35"
138367   wire width 10 $0\core_spr1[9:0]
138368   attribute \src "libresoc.v:52034.3-52156.6"
138369   wire $0\core_spr1_ok$next[0:0]$1905
138370   attribute \src "libresoc.v:50884.3-50885.41"
138371   wire $0\core_spr1_ok[0:0]
138372   attribute \src "libresoc.v:52034.3-52156.6"
138373   wire width 10 $0\core_spro$next[9:0]$1906
138374   attribute \src "libresoc.v:50876.3-50877.35"
138375   wire width 10 $0\core_spro[9:0]
138376   attribute \src "libresoc.v:52034.3-52156.6"
138377   wire $0\core_spro_ok$next[0:0]$1907
138378   attribute \src "libresoc.v:50878.3-50879.41"
138379   wire $0\core_spro_ok[0:0]
138380   attribute \src "libresoc.v:52431.3-52449.6"
138381   wire $0\core_stopped_i[0:0]
138382   attribute \src "libresoc.v:52034.3-52156.6"
138383   wire width 3 $0\core_xer_in$next[2:0]$1908
138384   attribute \src "libresoc.v:50886.3-50887.39"
138385   wire width 3 $0\core_xer_in[2:0]
138386   attribute \src "libresoc.v:52034.3-52156.6"
138387   wire $0\core_xer_out$next[0:0]$1909
138388   attribute \src "libresoc.v:50888.3-50889.41"
138389   wire $0\core_xer_out[0:0]
138390   attribute \src "libresoc.v:50986.3-50987.30"
138391   wire $0\cu_st__rel_o_dly[0:0]
138392   attribute \src "libresoc.v:51686.3-51694.6"
138393   wire $0\d_cr_delay$next[0:0]$1804
138394   attribute \src "libresoc.v:50902.3-50903.37"
138395   wire $0\d_cr_delay[0:0]
138396   attribute \src "libresoc.v:51647.3-51655.6"
138397   wire $0\d_reg_delay$next[0:0]$1798
138398   attribute \src "libresoc.v:50924.3-50925.39"
138399   wire $0\d_reg_delay[0:0]
138400   attribute \src "libresoc.v:51725.3-51733.6"
138401   wire $0\d_xer_delay$next[0:0]$1810
138402   attribute \src "libresoc.v:50880.3-50881.39"
138403   wire $0\d_xer_delay[0:0]
138404   attribute \src "libresoc.v:51963.3-51983.6"
138405   wire width 64 $0\data_i[63:0]
138406   attribute \src "libresoc.v:52450.3-52468.6"
138407   wire $0\dbg_core_stopped_i[0:0]
138408   attribute \src "libresoc.v:51705.3-51714.6"
138409   wire $0\dbg_d_cr_ack[0:0]
138410   attribute \src "libresoc.v:51695.3-51704.6"
138411   wire width 64 $0\dbg_d_cr_data[63:0]
138412   attribute \src "libresoc.v:51666.3-51675.6"
138413   wire $0\dbg_d_gpr_ack[0:0]
138414   attribute \src "libresoc.v:51656.3-51665.6"
138415   wire width 64 $0\dbg_d_gpr_data[63:0]
138416   attribute \src "libresoc.v:51744.3-51753.6"
138417   wire $0\dbg_d_xer_ack[0:0]
138418   attribute \src "libresoc.v:51734.3-51743.6"
138419   wire width 64 $0\dbg_d_xer_data[63:0]
138420   attribute \src "libresoc.v:51482.3-51490.6"
138421   wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1760
138422   attribute \src "libresoc.v:51004.3-51005.45"
138423   wire width 4 $0\dbg_dmi_addr_i[3:0]
138424   attribute \src "libresoc.v:52000.3-52008.6"
138425   wire width 64 $0\dbg_dmi_din$next[63:0]$1843
138426   attribute \src "libresoc.v:50998.3-50999.39"
138427   wire width 64 $0\dbg_dmi_din[63:0]
138428   attribute \src "libresoc.v:51491.3-51499.6"
138429   wire $0\dbg_dmi_req_i$next[0:0]$1763
138430   attribute \src "libresoc.v:51002.3-51003.43"
138431   wire $0\dbg_dmi_req_i[0:0]
138432   attribute \src "libresoc.v:51895.3-51903.6"
138433   wire $0\dbg_dmi_we_i$next[0:0]$1832
138434   attribute \src "libresoc.v:51000.3-51001.41"
138435   wire $0\dbg_dmi_we_i[0:0]
138436   attribute \src "libresoc.v:51868.3-51883.6"
138437   wire width 64 $0\dec2_cur_dec$next[63:0]$1827
138438   attribute \src "libresoc.v:50836.3-50837.41"
138439   wire width 64 $0\dec2_cur_dec[63:0]
138440   attribute \src "libresoc.v:52175.3-52183.6"
138441   wire $0\dec2_cur_eint$next[0:0]$2121
138442   attribute \src "libresoc.v:50992.3-50993.43"
138443   wire $0\dec2_cur_eint[0:0]
138444   attribute \src "libresoc.v:51500.3-51520.6"
138445   wire width 64 $0\dec2_cur_msr$next[63:0]$1766
138446   attribute \src "libresoc.v:50840.3-50841.41"
138447   wire width 64 $0\dec2_cur_msr[63:0]
138448   attribute \src "libresoc.v:52334.3-52354.6"
138449   wire width 64 $0\dec2_cur_pc$next[63:0]$2142
138450   attribute \src "libresoc.v:50846.3-50847.39"
138451   wire width 64 $0\dec2_cur_pc[63:0]
138452   attribute \src "libresoc.v:51521.3-51539.6"
138453   wire width 32 $0\dec2_raw_opcode_in[31:0]
138454   attribute \src "libresoc.v:52184.3-52193.6"
138455   wire width 2 $0\delay$next[1:0]$2124
138456   attribute \src "libresoc.v:50988.3-50989.27"
138457   wire width 2 $0\delay[1:0]
138458   attribute \src "libresoc.v:51627.3-51636.6"
138459   wire width 5 $0\dmi__addr[4:0]
138460   attribute \src "libresoc.v:51637.3-51646.6"
138461   wire $0\dmi__ren[0:0]
138462   attribute \src "libresoc.v:51784.3-51811.6"
138463   wire width 2 $0\fsm_state$131$next[1:0]$1817
138464   attribute \src "libresoc.v:50858.3-50859.45"
138465   wire width 2 $0\fsm_state$131[1:0]$1674
138466   attribute \src "libresoc.v:49998.13-49998.35"
138467   wire width 2 $0\fsm_state$131[1:0]$2251
138468   attribute \src "libresoc.v:52385.3-52430.6"
138469   wire width 2 $0\fsm_state$next[1:0]$2153
138470   attribute \src "libresoc.v:50842.3-50843.35"
138471   wire width 2 $0\fsm_state[1:0]
138472   attribute \src "libresoc.v:51676.3-51685.6"
138473   wire width 8 $0\full_rd2__ren[7:0]
138474   attribute \src "libresoc.v:51715.3-51724.6"
138475   wire width 3 $0\full_rd__ren[2:0]
138476   attribute \src "libresoc.v:51572.3-51595.6"
138477   wire width 32 $0\ilatch$next[31:0]$1789
138478   attribute \src "libresoc.v:50946.3-50947.29"
138479   wire width 32 $0\ilatch[31:0]
138480   attribute \src "libresoc.v:52268.3-52283.6"
138481   wire width 48 $0\imem_a_pc_i[47:0]
138482   attribute \src "libresoc.v:52284.3-52308.6"
138483   wire $0\imem_a_valid_i[0:0]
138484   attribute \src "libresoc.v:52309.3-52333.6"
138485   wire $0\imem_f_valid_i[0:0]
138486   attribute \src "libresoc.v:48722.7-48722.20"
138487   wire $0\initial[0:0]
138488   attribute \src "libresoc.v:51823.3-51837.6"
138489   wire width 3 $0\issue__addr$135[2:0]$1822
138490   attribute \src "libresoc.v:51754.3-51768.6"
138491   wire width 3 $0\issue__addr[2:0]
138492   attribute \src "libresoc.v:51853.3-51867.6"
138493   wire width 64 $0\issue__data_i[63:0]
138494   attribute \src "libresoc.v:51769.3-51783.6"
138495   wire $0\issue__ren[0:0]
138496   attribute \src "libresoc.v:51838.3-51852.6"
138497   wire $0\issue__wen[0:0]
138498   attribute \src "libresoc.v:51616.3-51626.6"
138499   wire $0\issue_i[0:0]
138500   attribute \src "libresoc.v:51596.3-51615.6"
138501   wire $0\ivalid_i[0:0]
138502   attribute \src "libresoc.v:52157.3-52165.6"
138503   wire $0\jtag_dmi0__ack_o$next[0:0]$2115
138504   attribute \src "libresoc.v:50996.3-50997.49"
138505   wire $0\jtag_dmi0__ack_o[0:0]
138506   attribute \src "libresoc.v:52166.3-52174.6"
138507   wire width 64 $0\jtag_dmi0__dout$next[63:0]$2118
138508   attribute \src "libresoc.v:50994.3-50995.47"
138509   wire width 64 $0\jtag_dmi0__dout[63:0]
138510   attribute \src "libresoc.v:51984.3-51999.6"
138511   wire width 4 $0\msr__ren[3:0]
138512   attribute \src "libresoc.v:52355.3-52384.6"
138513   wire $0\msr_read$next[0:0]$2147
138514   attribute \src "libresoc.v:50844.3-50845.33"
138515   wire $0\msr_read[0:0]
138516   attribute \src "libresoc.v:51812.3-51822.6"
138517   wire width 64 $0\new_dec[63:0]
138518   attribute \src "libresoc.v:51884.3-51894.6"
138519   wire width 64 $0\new_tb[63:0]
138520   attribute \src "libresoc.v:51913.3-51928.6"
138521   wire width 64 $0\pc[63:0]
138522   attribute \src "libresoc.v:52009.3-52033.6"
138523   wire $0\pc_changed$next[0:0]$1846
138524   attribute \src "libresoc.v:50982.3-50983.37"
138525   wire $0\pc_changed[0:0]
138526   attribute \src "libresoc.v:51904.3-51912.6"
138527   wire $0\pc_ok_delay$next[0:0]$1835
138528   attribute \src "libresoc.v:50984.3-50985.39"
138529   wire $0\pc_ok_delay[0:0]
138530   attribute \src "libresoc.v:52194.3-52230.6"
138531   wire width 32 $0\raw_insn_i$next[31:0]$2127
138532   attribute \src "libresoc.v:50850.3-50851.37"
138533   wire width 32 $0\raw_insn_i[31:0]
138534   attribute \src "libresoc.v:51942.3-51962.6"
138535   wire width 4 $0\wen[3:0]
138536   attribute \src "libresoc.v:52231.3-52267.6"
138537   wire $1\bigendian_i$next[0:0]$2134
138538   attribute \src "libresoc.v:48854.7-48854.25"
138539   wire $1\bigendian_i[0:0]
138540   attribute \src "libresoc.v:51929.3-51941.6"
138541   wire width 4 $1\cia__ren[3:0]
138542   attribute \src "libresoc.v:52034.3-52156.6"
138543   wire width 8 $1\core_asmcode$next[7:0]$1910
138544   attribute \src "libresoc.v:48866.13-48866.33"
138545   wire width 8 $1\core_asmcode[7:0]
138546   attribute \src "libresoc.v:52034.3-52156.6"
138547   wire width 64 $1\core_core_cia$next[63:0]$1911
138548   attribute \src "libresoc.v:48872.14-48872.50"
138549   wire width 64 $1\core_core_cia[63:0]
138550   attribute \src "libresoc.v:52034.3-52156.6"
138551   wire width 8 $1\core_core_cr_rd$next[7:0]$1912
138552   attribute \src "libresoc.v:48876.13-48876.36"
138553   wire width 8 $1\core_core_cr_rd[7:0]
138554   attribute \src "libresoc.v:52034.3-52156.6"
138555   wire $1\core_core_cr_rd_ok$next[0:0]$1913
138556   attribute \src "libresoc.v:48880.7-48880.32"
138557   wire $1\core_core_cr_rd_ok[0:0]
138558   attribute \src "libresoc.v:52034.3-52156.6"
138559   wire width 8 $1\core_core_cr_wr$next[7:0]$1914
138560   attribute \src "libresoc.v:48884.13-48884.36"
138561   wire width 8 $1\core_core_cr_wr[7:0]
138562   attribute \src "libresoc.v:52034.3-52156.6"
138563   wire $1\core_core_cr_wr_ok$next[0:0]$1915
138564   attribute \src "libresoc.v:48888.7-48888.32"
138565   wire $1\core_core_cr_wr_ok[0:0]
138566   attribute \src "libresoc.v:52034.3-52156.6"
138567   wire $1\core_core_exc_$signal$50$next[0:0]$1916
138568   attribute \src "libresoc.v:52034.3-52156.6"
138569   wire $1\core_core_exc_$signal$51$next[0:0]$1917
138570   attribute \src "libresoc.v:52034.3-52156.6"
138571   wire $1\core_core_exc_$signal$52$next[0:0]$1918
138572   attribute \src "libresoc.v:52034.3-52156.6"
138573   wire $1\core_core_exc_$signal$53$next[0:0]$1919
138574   attribute \src "libresoc.v:52034.3-52156.6"
138575   wire $1\core_core_exc_$signal$54$next[0:0]$1920
138576   attribute \src "libresoc.v:52034.3-52156.6"
138577   wire $1\core_core_exc_$signal$55$next[0:0]$1921
138578   attribute \src "libresoc.v:52034.3-52156.6"
138579   wire $1\core_core_exc_$signal$56$next[0:0]$1922
138580   attribute \src "libresoc.v:52034.3-52156.6"
138581   wire $1\core_core_exc_$signal$next[0:0]$1923
138582   attribute \src "libresoc.v:52034.3-52156.6"
138583   wire width 12 $1\core_core_fn_unit$next[11:0]$1924
138584   attribute \src "libresoc.v:48937.14-48937.41"
138585   wire width 12 $1\core_core_fn_unit[11:0]
138586   attribute \src "libresoc.v:52034.3-52156.6"
138587   wire width 2 $1\core_core_input_carry$next[1:0]$1925
138588   attribute \src "libresoc.v:48945.13-48945.41"
138589   wire width 2 $1\core_core_input_carry[1:0]
138590   attribute \src "libresoc.v:52034.3-52156.6"
138591   wire width 32 $1\core_core_insn$next[31:0]$1926
138592   attribute \src "libresoc.v:48949.14-48949.36"
138593   wire width 32 $1\core_core_insn[31:0]
138594   attribute \src "libresoc.v:52034.3-52156.6"
138595   wire width 7 $1\core_core_insn_type$next[6:0]$1927
138596   attribute \src "libresoc.v:49027.13-49027.40"
138597   wire width 7 $1\core_core_insn_type[6:0]
138598   attribute \src "libresoc.v:52034.3-52156.6"
138599   wire $1\core_core_is_32bit$next[0:0]$1928
138600   attribute \src "libresoc.v:49031.7-49031.32"
138601   wire $1\core_core_is_32bit[0:0]
138602   attribute \src "libresoc.v:52034.3-52156.6"
138603   wire $1\core_core_lk$next[0:0]$1929
138604   attribute \src "libresoc.v:49035.7-49035.26"
138605   wire $1\core_core_lk[0:0]
138606   attribute \src "libresoc.v:52034.3-52156.6"
138607   wire width 64 $1\core_core_msr$next[63:0]$1930
138608   attribute \src "libresoc.v:49039.14-49039.50"
138609   wire width 64 $1\core_core_msr[63:0]
138610   attribute \src "libresoc.v:52034.3-52156.6"
138611   wire $1\core_core_oe$next[0:0]$1931
138612   attribute \src "libresoc.v:49043.7-49043.26"
138613   wire $1\core_core_oe[0:0]
138614   attribute \src "libresoc.v:52034.3-52156.6"
138615   wire $1\core_core_oe_ok$next[0:0]$1932
138616   attribute \src "libresoc.v:49047.7-49047.29"
138617   wire $1\core_core_oe_ok[0:0]
138618   attribute \src "libresoc.v:52034.3-52156.6"
138619   wire $1\core_core_rc$next[0:0]$1933
138620   attribute \src "libresoc.v:49051.7-49051.26"
138621   wire $1\core_core_rc[0:0]
138622   attribute \src "libresoc.v:52034.3-52156.6"
138623   wire $1\core_core_rc_ok$next[0:0]$1934
138624   attribute \src "libresoc.v:49055.7-49055.29"
138625   wire $1\core_core_rc_ok[0:0]
138626   attribute \src "libresoc.v:52034.3-52156.6"
138627   wire width 13 $1\core_core_trapaddr$next[12:0]$1935
138628   attribute \src "libresoc.v:49059.14-49059.43"
138629   wire width 13 $1\core_core_trapaddr[12:0]
138630   attribute \src "libresoc.v:52034.3-52156.6"
138631   wire width 8 $1\core_core_traptype$next[7:0]$1936
138632   attribute \src "libresoc.v:49063.13-49063.39"
138633   wire width 8 $1\core_core_traptype[7:0]
138634   attribute \src "libresoc.v:52034.3-52156.6"
138635   wire width 3 $1\core_cr_in1$next[2:0]$1937
138636   attribute \src "libresoc.v:49069.13-49069.31"
138637   wire width 3 $1\core_cr_in1[2:0]
138638   attribute \src "libresoc.v:52034.3-52156.6"
138639   wire $1\core_cr_in1_ok$next[0:0]$1938
138640   attribute \src "libresoc.v:49073.7-49073.28"
138641   wire $1\core_cr_in1_ok[0:0]
138642   attribute \src "libresoc.v:52034.3-52156.6"
138643   wire width 3 $1\core_cr_in2$48$next[2:0]$1939
138644   attribute \src "libresoc.v:52034.3-52156.6"
138645   wire width 3 $1\core_cr_in2$next[2:0]$1940
138646   attribute \src "libresoc.v:49077.13-49077.31"
138647   wire width 3 $1\core_cr_in2[2:0]
138648   attribute \src "libresoc.v:52034.3-52156.6"
138649   wire $1\core_cr_in2_ok$49$next[0:0]$1941
138650   attribute \src "libresoc.v:52034.3-52156.6"
138651   wire $1\core_cr_in2_ok$next[0:0]$1942
138652   attribute \src "libresoc.v:49085.7-49085.28"
138653   wire $1\core_cr_in2_ok[0:0]
138654   attribute \src "libresoc.v:52034.3-52156.6"
138655   wire width 3 $1\core_cr_out$next[2:0]$1943
138656   attribute \src "libresoc.v:49093.13-49093.31"
138657   wire width 3 $1\core_cr_out[2:0]
138658   attribute \src "libresoc.v:52034.3-52156.6"
138659   wire $1\core_cr_out_ok$next[0:0]$1944
138660   attribute \src "libresoc.v:49097.7-49097.28"
138661   wire $1\core_cr_out_ok[0:0]
138662   attribute \src "libresoc.v:51540.3-51571.6"
138663   wire width 64 $1\core_dec$next[63:0]$1776
138664   attribute \src "libresoc.v:49101.14-49101.45"
138665   wire width 64 $1\core_dec[63:0]
138666   attribute \src "libresoc.v:52034.3-52156.6"
138667   wire width 5 $1\core_ea$next[4:0]$1945
138668   attribute \src "libresoc.v:49105.13-49105.28"
138669   wire width 5 $1\core_ea[4:0]
138670   attribute \src "libresoc.v:52034.3-52156.6"
138671   wire $1\core_ea_ok$next[0:0]$1946
138672   attribute \src "libresoc.v:49109.7-49109.24"
138673   wire $1\core_ea_ok[0:0]
138674   attribute \src "libresoc.v:51540.3-51571.6"
138675   wire $1\core_eint$next[0:0]$1777
138676   attribute \src "libresoc.v:49113.7-49113.23"
138677   wire $1\core_eint[0:0]
138678   attribute \src "libresoc.v:52034.3-52156.6"
138679   wire width 3 $1\core_fast1$next[2:0]$1947
138680   attribute \src "libresoc.v:49117.13-49117.30"
138681   wire width 3 $1\core_fast1[2:0]
138682   attribute \src "libresoc.v:52034.3-52156.6"
138683   wire $1\core_fast1_ok$next[0:0]$1948
138684   attribute \src "libresoc.v:49121.7-49121.27"
138685   wire $1\core_fast1_ok[0:0]
138686   attribute \src "libresoc.v:52034.3-52156.6"
138687   wire width 3 $1\core_fast2$next[2:0]$1949
138688   attribute \src "libresoc.v:49125.13-49125.30"
138689   wire width 3 $1\core_fast2[2:0]
138690   attribute \src "libresoc.v:52034.3-52156.6"
138691   wire $1\core_fast2_ok$next[0:0]$1950
138692   attribute \src "libresoc.v:49129.7-49129.27"
138693   wire $1\core_fast2_ok[0:0]
138694   attribute \src "libresoc.v:52034.3-52156.6"
138695   wire width 3 $1\core_fasto1$next[2:0]$1951
138696   attribute \src "libresoc.v:49133.13-49133.31"
138697   wire width 3 $1\core_fasto1[2:0]
138698   attribute \src "libresoc.v:52034.3-52156.6"
138699   wire $1\core_fasto1_ok$next[0:0]$1952
138700   attribute \src "libresoc.v:49137.7-49137.28"
138701   wire $1\core_fasto1_ok[0:0]
138702   attribute \src "libresoc.v:52034.3-52156.6"
138703   wire width 3 $1\core_fasto2$next[2:0]$1953
138704   attribute \src "libresoc.v:49141.13-49141.31"
138705   wire width 3 $1\core_fasto2[2:0]
138706   attribute \src "libresoc.v:52034.3-52156.6"
138707   wire $1\core_fasto2_ok$next[0:0]$1954
138708   attribute \src "libresoc.v:49145.7-49145.28"
138709   wire $1\core_fasto2_ok[0:0]
138710   attribute \src "libresoc.v:51540.3-51571.6"
138711   wire width 64 $1\core_msr$next[63:0]$1778
138712   attribute \src "libresoc.v:49149.14-49149.45"
138713   wire width 64 $1\core_msr[63:0]
138714   attribute \src "libresoc.v:51540.3-51571.6"
138715   wire width 64 $1\core_pc$next[63:0]$1779
138716   attribute \src "libresoc.v:49153.14-49153.44"
138717   wire width 64 $1\core_pc[63:0]
138718   attribute \src "libresoc.v:52034.3-52156.6"
138719   wire width 5 $1\core_reg1$next[4:0]$1955
138720   attribute \src "libresoc.v:49157.13-49157.30"
138721   wire width 5 $1\core_reg1[4:0]
138722   attribute \src "libresoc.v:52034.3-52156.6"
138723   wire $1\core_reg1_ok$next[0:0]$1956
138724   attribute \src "libresoc.v:49161.7-49161.26"
138725   wire $1\core_reg1_ok[0:0]
138726   attribute \src "libresoc.v:52034.3-52156.6"
138727   wire width 5 $1\core_reg2$next[4:0]$1957
138728   attribute \src "libresoc.v:49165.13-49165.30"
138729   wire width 5 $1\core_reg2[4:0]
138730   attribute \src "libresoc.v:52034.3-52156.6"
138731   wire $1\core_reg2_ok$next[0:0]$1958
138732   attribute \src "libresoc.v:49169.7-49169.26"
138733   wire $1\core_reg2_ok[0:0]
138734   attribute \src "libresoc.v:52034.3-52156.6"
138735   wire width 5 $1\core_reg3$next[4:0]$1959
138736   attribute \src "libresoc.v:49173.13-49173.30"
138737   wire width 5 $1\core_reg3[4:0]
138738   attribute \src "libresoc.v:52034.3-52156.6"
138739   wire $1\core_reg3_ok$next[0:0]$1960
138740   attribute \src "libresoc.v:49177.7-49177.26"
138741   wire $1\core_reg3_ok[0:0]
138742   attribute \src "libresoc.v:52034.3-52156.6"
138743   wire width 5 $1\core_rego$next[4:0]$1961
138744   attribute \src "libresoc.v:49181.13-49181.30"
138745   wire width 5 $1\core_rego[4:0]
138746   attribute \src "libresoc.v:52034.3-52156.6"
138747   wire $1\core_rego_ok$next[0:0]$1962
138748   attribute \src "libresoc.v:49185.7-49185.26"
138749   wire $1\core_rego_ok[0:0]
138750   attribute \src "libresoc.v:52034.3-52156.6"
138751   wire width 10 $1\core_spr1$next[9:0]$1963
138752   attribute \src "libresoc.v:49300.13-49300.32"
138753   wire width 10 $1\core_spr1[9:0]
138754   attribute \src "libresoc.v:52034.3-52156.6"
138755   wire $1\core_spr1_ok$next[0:0]$1964
138756   attribute \src "libresoc.v:49304.7-49304.26"
138757   wire $1\core_spr1_ok[0:0]
138758   attribute \src "libresoc.v:52034.3-52156.6"
138759   wire width 10 $1\core_spro$next[9:0]$1965
138760   attribute \src "libresoc.v:49419.13-49419.32"
138761   wire width 10 $1\core_spro[9:0]
138762   attribute \src "libresoc.v:52034.3-52156.6"
138763   wire $1\core_spro_ok$next[0:0]$1966
138764   attribute \src "libresoc.v:49423.7-49423.26"
138765   wire $1\core_spro_ok[0:0]
138766   attribute \src "libresoc.v:52431.3-52449.6"
138767   wire $1\core_stopped_i[0:0]
138768   attribute \src "libresoc.v:52034.3-52156.6"
138769   wire width 3 $1\core_xer_in$next[2:0]$1967
138770   attribute \src "libresoc.v:49431.13-49431.31"
138771   wire width 3 $1\core_xer_in[2:0]
138772   attribute \src "libresoc.v:52034.3-52156.6"
138773   wire $1\core_xer_out$next[0:0]$1968
138774   attribute \src "libresoc.v:49435.7-49435.26"
138775   wire $1\core_xer_out[0:0]
138776   attribute \src "libresoc.v:49451.7-49451.30"
138777   wire $1\cu_st__rel_o_dly[0:0]
138778   attribute \src "libresoc.v:51686.3-51694.6"
138779   wire $1\d_cr_delay$next[0:0]$1805
138780   attribute \src "libresoc.v:49457.7-49457.24"
138781   wire $1\d_cr_delay[0:0]
138782   attribute \src "libresoc.v:51647.3-51655.6"
138783   wire $1\d_reg_delay$next[0:0]$1799
138784   attribute \src "libresoc.v:49461.7-49461.25"
138785   wire $1\d_reg_delay[0:0]
138786   attribute \src "libresoc.v:51725.3-51733.6"
138787   wire $1\d_xer_delay$next[0:0]$1811
138788   attribute \src "libresoc.v:49465.7-49465.25"
138789   wire $1\d_xer_delay[0:0]
138790   attribute \src "libresoc.v:51963.3-51983.6"
138791   wire width 64 $1\data_i[63:0]
138792   attribute \src "libresoc.v:52450.3-52468.6"
138793   wire $1\dbg_core_stopped_i[0:0]
138794   attribute \src "libresoc.v:51705.3-51714.6"
138795   wire $1\dbg_d_cr_ack[0:0]
138796   attribute \src "libresoc.v:51695.3-51704.6"
138797   wire width 64 $1\dbg_d_cr_data[63:0]
138798   attribute \src "libresoc.v:51666.3-51675.6"
138799   wire $1\dbg_d_gpr_ack[0:0]
138800   attribute \src "libresoc.v:51656.3-51665.6"
138801   wire width 64 $1\dbg_d_gpr_data[63:0]
138802   attribute \src "libresoc.v:51744.3-51753.6"
138803   wire $1\dbg_d_xer_ack[0:0]
138804   attribute \src "libresoc.v:51734.3-51743.6"
138805   wire width 64 $1\dbg_d_xer_data[63:0]
138806   attribute \src "libresoc.v:51482.3-51490.6"
138807   wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1761
138808   attribute \src "libresoc.v:49503.13-49503.34"
138809   wire width 4 $1\dbg_dmi_addr_i[3:0]
138810   attribute \src "libresoc.v:52000.3-52008.6"
138811   wire width 64 $1\dbg_dmi_din$next[63:0]$1844
138812   attribute \src "libresoc.v:49507.14-49507.48"
138813   wire width 64 $1\dbg_dmi_din[63:0]
138814   attribute \src "libresoc.v:51491.3-51499.6"
138815   wire $1\dbg_dmi_req_i$next[0:0]$1764
138816   attribute \src "libresoc.v:49513.7-49513.27"
138817   wire $1\dbg_dmi_req_i[0:0]
138818   attribute \src "libresoc.v:51895.3-51903.6"
138819   wire $1\dbg_dmi_we_i$next[0:0]$1833
138820   attribute \src "libresoc.v:49517.7-49517.26"
138821   wire $1\dbg_dmi_we_i[0:0]
138822   attribute \src "libresoc.v:51868.3-51883.6"
138823   wire width 64 $1\dec2_cur_dec$next[63:0]$1828
138824   attribute \src "libresoc.v:49553.14-49553.49"
138825   wire width 64 $1\dec2_cur_dec[63:0]
138826   attribute \src "libresoc.v:52175.3-52183.6"
138827   wire $1\dec2_cur_eint$next[0:0]$2122
138828   attribute \src "libresoc.v:49557.7-49557.27"
138829   wire $1\dec2_cur_eint[0:0]
138830   attribute \src "libresoc.v:51500.3-51520.6"
138831   wire width 64 $1\dec2_cur_msr$next[63:0]$1767
138832   attribute \src "libresoc.v:49561.14-49561.49"
138833   wire width 64 $1\dec2_cur_msr[63:0]
138834   attribute \src "libresoc.v:52334.3-52354.6"
138835   wire width 64 $1\dec2_cur_pc$next[63:0]$2143
138836   attribute \src "libresoc.v:49565.14-49565.48"
138837   wire width 64 $1\dec2_cur_pc[63:0]
138838   attribute \src "libresoc.v:51521.3-51539.6"
138839   wire width 32 $1\dec2_raw_opcode_in[31:0]
138840   attribute \src "libresoc.v:52184.3-52193.6"
138841   wire width 2 $1\delay$next[1:0]$2125
138842   attribute \src "libresoc.v:49974.13-49974.25"
138843   wire width 2 $1\delay[1:0]
138844   attribute \src "libresoc.v:51627.3-51636.6"
138845   wire width 5 $1\dmi__addr[4:0]
138846   attribute \src "libresoc.v:51637.3-51646.6"
138847   wire $1\dmi__ren[0:0]
138848   attribute \src "libresoc.v:51784.3-51811.6"
138849   wire width 2 $1\fsm_state$131$next[1:0]$1818
138850   attribute \src "libresoc.v:52385.3-52430.6"
138851   wire width 2 $1\fsm_state$next[1:0]$2154
138852   attribute \src "libresoc.v:49996.13-49996.29"
138853   wire width 2 $1\fsm_state[1:0]
138854   attribute \src "libresoc.v:51676.3-51685.6"
138855   wire width 8 $1\full_rd2__ren[7:0]
138856   attribute \src "libresoc.v:51715.3-51724.6"
138857   wire width 3 $1\full_rd__ren[2:0]
138858   attribute \src "libresoc.v:51572.3-51595.6"
138859   wire width 32 $1\ilatch$next[31:0]$1790
138860   attribute \src "libresoc.v:50248.14-50248.28"
138861   wire width 32 $1\ilatch[31:0]
138862   attribute \src "libresoc.v:52268.3-52283.6"
138863   wire width 48 $1\imem_a_pc_i[47:0]
138864   attribute \src "libresoc.v:52284.3-52308.6"
138865   wire $1\imem_a_valid_i[0:0]
138866   attribute \src "libresoc.v:52309.3-52333.6"
138867   wire $1\imem_f_valid_i[0:0]
138868   attribute \src "libresoc.v:51823.3-51837.6"
138869   wire width 3 $1\issue__addr$135[2:0]$1823
138870   attribute \src "libresoc.v:51754.3-51768.6"
138871   wire width 3 $1\issue__addr[2:0]
138872   attribute \src "libresoc.v:51853.3-51867.6"
138873   wire width 64 $1\issue__data_i[63:0]
138874   attribute \src "libresoc.v:51769.3-51783.6"
138875   wire $1\issue__ren[0:0]
138876   attribute \src "libresoc.v:51838.3-51852.6"
138877   wire $1\issue__wen[0:0]
138878   attribute \src "libresoc.v:51616.3-51626.6"
138879   wire $1\issue_i[0:0]
138880   attribute \src "libresoc.v:51596.3-51615.6"
138881   wire $1\ivalid_i[0:0]
138882   attribute \src "libresoc.v:52157.3-52165.6"
138883   wire $1\jtag_dmi0__ack_o$next[0:0]$2116
138884   attribute \src "libresoc.v:50282.7-50282.30"
138885   wire $1\jtag_dmi0__ack_o[0:0]
138886   attribute \src "libresoc.v:52166.3-52174.6"
138887   wire width 64 $1\jtag_dmi0__dout$next[63:0]$2119
138888   attribute \src "libresoc.v:50290.14-50290.52"
138889   wire width 64 $1\jtag_dmi0__dout[63:0]
138890   attribute \src "libresoc.v:51984.3-51999.6"
138891   wire width 4 $1\msr__ren[3:0]
138892   attribute \src "libresoc.v:52355.3-52384.6"
138893   wire $1\msr_read$next[0:0]$2148
138894   attribute \src "libresoc.v:50350.7-50350.22"
138895   wire $1\msr_read[0:0]
138896   attribute \src "libresoc.v:51812.3-51822.6"
138897   wire width 64 $1\new_dec[63:0]
138898   attribute \src "libresoc.v:51884.3-51894.6"
138899   wire width 64 $1\new_tb[63:0]
138900   attribute \src "libresoc.v:51913.3-51928.6"
138901   wire width 64 $1\pc[63:0]
138902   attribute \src "libresoc.v:52009.3-52033.6"
138903   wire $1\pc_changed$next[0:0]$1847
138904   attribute \src "libresoc.v:50378.7-50378.24"
138905   wire $1\pc_changed[0:0]
138906   attribute \src "libresoc.v:51904.3-51912.6"
138907   wire $1\pc_ok_delay$next[0:0]$1836
138908   attribute \src "libresoc.v:50388.7-50388.25"
138909   wire $1\pc_ok_delay[0:0]
138910   attribute \src "libresoc.v:52194.3-52230.6"
138911   wire width 32 $1\raw_insn_i$next[31:0]$2128
138912   attribute \src "libresoc.v:50402.14-50402.32"
138913   wire width 32 $1\raw_insn_i[31:0]
138914   attribute \src "libresoc.v:51942.3-51962.6"
138915   wire width 4 $1\wen[3:0]
138916   attribute \src "libresoc.v:52231.3-52267.6"
138917   wire $2\bigendian_i$next[0:0]$2135
138918   attribute \src "libresoc.v:52034.3-52156.6"
138919   wire width 8 $2\core_asmcode$next[7:0]$1969
138920   attribute \src "libresoc.v:52034.3-52156.6"
138921   wire width 64 $2\core_core_cia$next[63:0]$1970
138922   attribute \src "libresoc.v:52034.3-52156.6"
138923   wire width 8 $2\core_core_cr_rd$next[7:0]$1971
138924   attribute \src "libresoc.v:52034.3-52156.6"
138925   wire $2\core_core_cr_rd_ok$next[0:0]$1972
138926   attribute \src "libresoc.v:52034.3-52156.6"
138927   wire width 8 $2\core_core_cr_wr$next[7:0]$1973
138928   attribute \src "libresoc.v:52034.3-52156.6"
138929   wire $2\core_core_cr_wr_ok$next[0:0]$1974
138930   attribute \src "libresoc.v:52034.3-52156.6"
138931   wire $2\core_core_exc_$signal$50$next[0:0]$1975
138932   attribute \src "libresoc.v:52034.3-52156.6"
138933   wire $2\core_core_exc_$signal$51$next[0:0]$1976
138934   attribute \src "libresoc.v:52034.3-52156.6"
138935   wire $2\core_core_exc_$signal$52$next[0:0]$1977
138936   attribute \src "libresoc.v:52034.3-52156.6"
138937   wire $2\core_core_exc_$signal$53$next[0:0]$1978
138938   attribute \src "libresoc.v:52034.3-52156.6"
138939   wire $2\core_core_exc_$signal$54$next[0:0]$1979
138940   attribute \src "libresoc.v:52034.3-52156.6"
138941   wire $2\core_core_exc_$signal$55$next[0:0]$1980
138942   attribute \src "libresoc.v:52034.3-52156.6"
138943   wire $2\core_core_exc_$signal$56$next[0:0]$1981
138944   attribute \src "libresoc.v:52034.3-52156.6"
138945   wire $2\core_core_exc_$signal$next[0:0]$1982
138946   attribute \src "libresoc.v:52034.3-52156.6"
138947   wire width 12 $2\core_core_fn_unit$next[11:0]$1983
138948   attribute \src "libresoc.v:52034.3-52156.6"
138949   wire width 2 $2\core_core_input_carry$next[1:0]$1984
138950   attribute \src "libresoc.v:52034.3-52156.6"
138951   wire width 32 $2\core_core_insn$next[31:0]$1985
138952   attribute \src "libresoc.v:52034.3-52156.6"
138953   wire width 7 $2\core_core_insn_type$next[6:0]$1986
138954   attribute \src "libresoc.v:52034.3-52156.6"
138955   wire $2\core_core_is_32bit$next[0:0]$1987
138956   attribute \src "libresoc.v:52034.3-52156.6"
138957   wire $2\core_core_lk$next[0:0]$1988
138958   attribute \src "libresoc.v:52034.3-52156.6"
138959   wire width 64 $2\core_core_msr$next[63:0]$1989
138960   attribute \src "libresoc.v:52034.3-52156.6"
138961   wire $2\core_core_oe$next[0:0]$1990
138962   attribute \src "libresoc.v:52034.3-52156.6"
138963   wire $2\core_core_oe_ok$next[0:0]$1991
138964   attribute \src "libresoc.v:52034.3-52156.6"
138965   wire $2\core_core_rc$next[0:0]$1992
138966   attribute \src "libresoc.v:52034.3-52156.6"
138967   wire $2\core_core_rc_ok$next[0:0]$1993
138968   attribute \src "libresoc.v:52034.3-52156.6"
138969   wire width 13 $2\core_core_trapaddr$next[12:0]$1994
138970   attribute \src "libresoc.v:52034.3-52156.6"
138971   wire width 8 $2\core_core_traptype$next[7:0]$1995
138972   attribute \src "libresoc.v:52034.3-52156.6"
138973   wire width 3 $2\core_cr_in1$next[2:0]$1996
138974   attribute \src "libresoc.v:52034.3-52156.6"
138975   wire $2\core_cr_in1_ok$next[0:0]$1997
138976   attribute \src "libresoc.v:52034.3-52156.6"
138977   wire width 3 $2\core_cr_in2$48$next[2:0]$1998
138978   attribute \src "libresoc.v:52034.3-52156.6"
138979   wire width 3 $2\core_cr_in2$next[2:0]$1999
138980   attribute \src "libresoc.v:52034.3-52156.6"
138981   wire $2\core_cr_in2_ok$49$next[0:0]$2000
138982   attribute \src "libresoc.v:52034.3-52156.6"
138983   wire $2\core_cr_in2_ok$next[0:0]$2001
138984   attribute \src "libresoc.v:52034.3-52156.6"
138985   wire width 3 $2\core_cr_out$next[2:0]$2002
138986   attribute \src "libresoc.v:52034.3-52156.6"
138987   wire $2\core_cr_out_ok$next[0:0]$2003
138988   attribute \src "libresoc.v:51540.3-51571.6"
138989   wire width 64 $2\core_dec$next[63:0]$1780
138990   attribute \src "libresoc.v:52034.3-52156.6"
138991   wire width 5 $2\core_ea$next[4:0]$2004
138992   attribute \src "libresoc.v:52034.3-52156.6"
138993   wire $2\core_ea_ok$next[0:0]$2005
138994   attribute \src "libresoc.v:51540.3-51571.6"
138995   wire $2\core_eint$next[0:0]$1781
138996   attribute \src "libresoc.v:52034.3-52156.6"
138997   wire width 3 $2\core_fast1$next[2:0]$2006
138998   attribute \src "libresoc.v:52034.3-52156.6"
138999   wire $2\core_fast1_ok$next[0:0]$2007
139000   attribute \src "libresoc.v:52034.3-52156.6"
139001   wire width 3 $2\core_fast2$next[2:0]$2008
139002   attribute \src "libresoc.v:52034.3-52156.6"
139003   wire $2\core_fast2_ok$next[0:0]$2009
139004   attribute \src "libresoc.v:52034.3-52156.6"
139005   wire width 3 $2\core_fasto1$next[2:0]$2010
139006   attribute \src "libresoc.v:52034.3-52156.6"
139007   wire $2\core_fasto1_ok$next[0:0]$2011
139008   attribute \src "libresoc.v:52034.3-52156.6"
139009   wire width 3 $2\core_fasto2$next[2:0]$2012
139010   attribute \src "libresoc.v:52034.3-52156.6"
139011   wire $2\core_fasto2_ok$next[0:0]$2013
139012   attribute \src "libresoc.v:51540.3-51571.6"
139013   wire width 64 $2\core_msr$next[63:0]$1782
139014   attribute \src "libresoc.v:51540.3-51571.6"
139015   wire width 64 $2\core_pc$next[63:0]$1783
139016   attribute \src "libresoc.v:52034.3-52156.6"
139017   wire width 5 $2\core_reg1$next[4:0]$2014
139018   attribute \src "libresoc.v:52034.3-52156.6"
139019   wire $2\core_reg1_ok$next[0:0]$2015
139020   attribute \src "libresoc.v:52034.3-52156.6"
139021   wire width 5 $2\core_reg2$next[4:0]$2016
139022   attribute \src "libresoc.v:52034.3-52156.6"
139023   wire $2\core_reg2_ok$next[0:0]$2017
139024   attribute \src "libresoc.v:52034.3-52156.6"
139025   wire width 5 $2\core_reg3$next[4:0]$2018
139026   attribute \src "libresoc.v:52034.3-52156.6"
139027   wire $2\core_reg3_ok$next[0:0]$2019
139028   attribute \src "libresoc.v:52034.3-52156.6"
139029   wire width 5 $2\core_rego$next[4:0]$2020
139030   attribute \src "libresoc.v:52034.3-52156.6"
139031   wire $2\core_rego_ok$next[0:0]$2021
139032   attribute \src "libresoc.v:52034.3-52156.6"
139033   wire width 10 $2\core_spr1$next[9:0]$2022
139034   attribute \src "libresoc.v:52034.3-52156.6"
139035   wire $2\core_spr1_ok$next[0:0]$2023
139036   attribute \src "libresoc.v:52034.3-52156.6"
139037   wire width 10 $2\core_spro$next[9:0]$2024
139038   attribute \src "libresoc.v:52034.3-52156.6"
139039   wire $2\core_spro_ok$next[0:0]$2025
139040   attribute \src "libresoc.v:52431.3-52449.6"
139041   wire $2\core_stopped_i[0:0]
139042   attribute \src "libresoc.v:52034.3-52156.6"
139043   wire width 3 $2\core_xer_in$next[2:0]$2026
139044   attribute \src "libresoc.v:52034.3-52156.6"
139045   wire $2\core_xer_out$next[0:0]$2027
139046   attribute \src "libresoc.v:51963.3-51983.6"
139047   wire width 64 $2\data_i[63:0]
139048   attribute \src "libresoc.v:52450.3-52468.6"
139049   wire $2\dbg_core_stopped_i[0:0]
139050   attribute \src "libresoc.v:51868.3-51883.6"
139051   wire width 64 $2\dec2_cur_dec$next[63:0]$1829
139052   attribute \src "libresoc.v:51500.3-51520.6"
139053   wire width 64 $2\dec2_cur_msr$next[63:0]$1768
139054   attribute \src "libresoc.v:52334.3-52354.6"
139055   wire width 64 $2\dec2_cur_pc$next[63:0]$2144
139056   attribute \src "libresoc.v:51521.3-51539.6"
139057   wire width 32 $2\dec2_raw_opcode_in[31:0]
139058   attribute \src "libresoc.v:51784.3-51811.6"
139059   wire width 2 $2\fsm_state$131$next[1:0]$1819
139060   attribute \src "libresoc.v:52385.3-52430.6"
139061   wire width 2 $2\fsm_state$next[1:0]$2155
139062   attribute \src "libresoc.v:51572.3-51595.6"
139063   wire width 32 $2\ilatch$next[31:0]$1791
139064   attribute \src "libresoc.v:52268.3-52283.6"
139065   wire width 48 $2\imem_a_pc_i[47:0]
139066   attribute \src "libresoc.v:52284.3-52308.6"
139067   wire $2\imem_a_valid_i[0:0]
139068   attribute \src "libresoc.v:52309.3-52333.6"
139069   wire $2\imem_f_valid_i[0:0]
139070   attribute \src "libresoc.v:51596.3-51615.6"
139071   wire $2\ivalid_i[0:0]
139072   attribute \src "libresoc.v:51984.3-51999.6"
139073   wire width 4 $2\msr__ren[3:0]
139074   attribute \src "libresoc.v:52355.3-52384.6"
139075   wire $2\msr_read$next[0:0]$2149
139076   attribute \src "libresoc.v:51913.3-51928.6"
139077   wire width 64 $2\pc[63:0]
139078   attribute \src "libresoc.v:52009.3-52033.6"
139079   wire $2\pc_changed$next[0:0]$1848
139080   attribute \src "libresoc.v:52194.3-52230.6"
139081   wire width 32 $2\raw_insn_i$next[31:0]$2129
139082   attribute \src "libresoc.v:51942.3-51962.6"
139083   wire width 4 $2\wen[3:0]
139084   attribute \src "libresoc.v:52231.3-52267.6"
139085   wire $3\bigendian_i$next[0:0]$2136
139086   attribute \src "libresoc.v:52034.3-52156.6"
139087   wire width 8 $3\core_asmcode$next[7:0]$2028
139088   attribute \src "libresoc.v:52034.3-52156.6"
139089   wire width 64 $3\core_core_cia$next[63:0]$2029
139090   attribute \src "libresoc.v:52034.3-52156.6"
139091   wire width 8 $3\core_core_cr_rd$next[7:0]$2030
139092   attribute \src "libresoc.v:52034.3-52156.6"
139093   wire $3\core_core_cr_rd_ok$next[0:0]$2031
139094   attribute \src "libresoc.v:52034.3-52156.6"
139095   wire width 8 $3\core_core_cr_wr$next[7:0]$2032
139096   attribute \src "libresoc.v:52034.3-52156.6"
139097   wire $3\core_core_cr_wr_ok$next[0:0]$2033
139098   attribute \src "libresoc.v:52034.3-52156.6"
139099   wire $3\core_core_exc_$signal$50$next[0:0]$2034
139100   attribute \src "libresoc.v:52034.3-52156.6"
139101   wire $3\core_core_exc_$signal$51$next[0:0]$2035
139102   attribute \src "libresoc.v:52034.3-52156.6"
139103   wire $3\core_core_exc_$signal$52$next[0:0]$2036
139104   attribute \src "libresoc.v:52034.3-52156.6"
139105   wire $3\core_core_exc_$signal$53$next[0:0]$2037
139106   attribute \src "libresoc.v:52034.3-52156.6"
139107   wire $3\core_core_exc_$signal$54$next[0:0]$2038
139108   attribute \src "libresoc.v:52034.3-52156.6"
139109   wire $3\core_core_exc_$signal$55$next[0:0]$2039
139110   attribute \src "libresoc.v:52034.3-52156.6"
139111   wire $3\core_core_exc_$signal$56$next[0:0]$2040
139112   attribute \src "libresoc.v:52034.3-52156.6"
139113   wire $3\core_core_exc_$signal$next[0:0]$2041
139114   attribute \src "libresoc.v:52034.3-52156.6"
139115   wire width 12 $3\core_core_fn_unit$next[11:0]$2042
139116   attribute \src "libresoc.v:52034.3-52156.6"
139117   wire width 2 $3\core_core_input_carry$next[1:0]$2043
139118   attribute \src "libresoc.v:52034.3-52156.6"
139119   wire width 32 $3\core_core_insn$next[31:0]$2044
139120   attribute \src "libresoc.v:52034.3-52156.6"
139121   wire width 7 $3\core_core_insn_type$next[6:0]$2045
139122   attribute \src "libresoc.v:52034.3-52156.6"
139123   wire $3\core_core_is_32bit$next[0:0]$2046
139124   attribute \src "libresoc.v:52034.3-52156.6"
139125   wire $3\core_core_lk$next[0:0]$2047
139126   attribute \src "libresoc.v:52034.3-52156.6"
139127   wire width 64 $3\core_core_msr$next[63:0]$2048
139128   attribute \src "libresoc.v:52034.3-52156.6"
139129   wire $3\core_core_oe$next[0:0]$2049
139130   attribute \src "libresoc.v:52034.3-52156.6"
139131   wire $3\core_core_oe_ok$next[0:0]$2050
139132   attribute \src "libresoc.v:52034.3-52156.6"
139133   wire $3\core_core_rc$next[0:0]$2051
139134   attribute \src "libresoc.v:52034.3-52156.6"
139135   wire $3\core_core_rc_ok$next[0:0]$2052
139136   attribute \src "libresoc.v:52034.3-52156.6"
139137   wire width 13 $3\core_core_trapaddr$next[12:0]$2053
139138   attribute \src "libresoc.v:52034.3-52156.6"
139139   wire width 8 $3\core_core_traptype$next[7:0]$2054
139140   attribute \src "libresoc.v:52034.3-52156.6"
139141   wire width 3 $3\core_cr_in1$next[2:0]$2055
139142   attribute \src "libresoc.v:52034.3-52156.6"
139143   wire $3\core_cr_in1_ok$next[0:0]$2056
139144   attribute \src "libresoc.v:52034.3-52156.6"
139145   wire width 3 $3\core_cr_in2$48$next[2:0]$2057
139146   attribute \src "libresoc.v:52034.3-52156.6"
139147   wire width 3 $3\core_cr_in2$next[2:0]$2058
139148   attribute \src "libresoc.v:52034.3-52156.6"
139149   wire $3\core_cr_in2_ok$49$next[0:0]$2059
139150   attribute \src "libresoc.v:52034.3-52156.6"
139151   wire $3\core_cr_in2_ok$next[0:0]$2060
139152   attribute \src "libresoc.v:52034.3-52156.6"
139153   wire width 3 $3\core_cr_out$next[2:0]$2061
139154   attribute \src "libresoc.v:52034.3-52156.6"
139155   wire $3\core_cr_out_ok$next[0:0]$2062
139156   attribute \src "libresoc.v:51540.3-51571.6"
139157   wire width 64 $3\core_dec$next[63:0]$1784
139158   attribute \src "libresoc.v:52034.3-52156.6"
139159   wire width 5 $3\core_ea$next[4:0]$2063
139160   attribute \src "libresoc.v:52034.3-52156.6"
139161   wire $3\core_ea_ok$next[0:0]$2064
139162   attribute \src "libresoc.v:51540.3-51571.6"
139163   wire $3\core_eint$next[0:0]$1785
139164   attribute \src "libresoc.v:52034.3-52156.6"
139165   wire width 3 $3\core_fast1$next[2:0]$2065
139166   attribute \src "libresoc.v:52034.3-52156.6"
139167   wire $3\core_fast1_ok$next[0:0]$2066
139168   attribute \src "libresoc.v:52034.3-52156.6"
139169   wire width 3 $3\core_fast2$next[2:0]$2067
139170   attribute \src "libresoc.v:52034.3-52156.6"
139171   wire $3\core_fast2_ok$next[0:0]$2068
139172   attribute \src "libresoc.v:52034.3-52156.6"
139173   wire width 3 $3\core_fasto1$next[2:0]$2069
139174   attribute \src "libresoc.v:52034.3-52156.6"
139175   wire $3\core_fasto1_ok$next[0:0]$2070
139176   attribute \src "libresoc.v:52034.3-52156.6"
139177   wire width 3 $3\core_fasto2$next[2:0]$2071
139178   attribute \src "libresoc.v:52034.3-52156.6"
139179   wire $3\core_fasto2_ok$next[0:0]$2072
139180   attribute \src "libresoc.v:51540.3-51571.6"
139181   wire width 64 $3\core_msr$next[63:0]$1786
139182   attribute \src "libresoc.v:51540.3-51571.6"
139183   wire width 64 $3\core_pc$next[63:0]$1787
139184   attribute \src "libresoc.v:52034.3-52156.6"
139185   wire width 5 $3\core_reg1$next[4:0]$2073
139186   attribute \src "libresoc.v:52034.3-52156.6"
139187   wire $3\core_reg1_ok$next[0:0]$2074
139188   attribute \src "libresoc.v:52034.3-52156.6"
139189   wire width 5 $3\core_reg2$next[4:0]$2075
139190   attribute \src "libresoc.v:52034.3-52156.6"
139191   wire $3\core_reg2_ok$next[0:0]$2076
139192   attribute \src "libresoc.v:52034.3-52156.6"
139193   wire width 5 $3\core_reg3$next[4:0]$2077
139194   attribute \src "libresoc.v:52034.3-52156.6"
139195   wire $3\core_reg3_ok$next[0:0]$2078
139196   attribute \src "libresoc.v:52034.3-52156.6"
139197   wire width 5 $3\core_rego$next[4:0]$2079
139198   attribute \src "libresoc.v:52034.3-52156.6"
139199   wire $3\core_rego_ok$next[0:0]$2080
139200   attribute \src "libresoc.v:52034.3-52156.6"
139201   wire width 10 $3\core_spr1$next[9:0]$2081
139202   attribute \src "libresoc.v:52034.3-52156.6"
139203   wire $3\core_spr1_ok$next[0:0]$2082
139204   attribute \src "libresoc.v:52034.3-52156.6"
139205   wire width 10 $3\core_spro$next[9:0]$2083
139206   attribute \src "libresoc.v:52034.3-52156.6"
139207   wire $3\core_spro_ok$next[0:0]$2084
139208   attribute \src "libresoc.v:52034.3-52156.6"
139209   wire width 3 $3\core_xer_in$next[2:0]$2085
139210   attribute \src "libresoc.v:52034.3-52156.6"
139211   wire $3\core_xer_out$next[0:0]$2086
139212   attribute \src "libresoc.v:51963.3-51983.6"
139213   wire width 64 $3\data_i[63:0]
139214   attribute \src "libresoc.v:51500.3-51520.6"
139215   wire width 64 $3\dec2_cur_msr$next[63:0]$1769
139216   attribute \src "libresoc.v:52334.3-52354.6"
139217   wire width 64 $3\dec2_cur_pc$next[63:0]$2145
139218   attribute \src "libresoc.v:52385.3-52430.6"
139219   wire width 2 $3\fsm_state$next[1:0]$2156
139220   attribute \src "libresoc.v:51572.3-51595.6"
139221   wire width 32 $3\ilatch$next[31:0]$1792
139222   attribute \src "libresoc.v:52284.3-52308.6"
139223   wire $3\imem_a_valid_i[0:0]
139224   attribute \src "libresoc.v:52309.3-52333.6"
139225   wire $3\imem_f_valid_i[0:0]
139226   attribute \src "libresoc.v:52355.3-52384.6"
139227   wire $3\msr_read$next[0:0]$2150
139228   attribute \src "libresoc.v:52009.3-52033.6"
139229   wire $3\pc_changed$next[0:0]$1849
139230   attribute \src "libresoc.v:52194.3-52230.6"
139231   wire width 32 $3\raw_insn_i$next[31:0]$2130
139232   attribute \src "libresoc.v:51942.3-51962.6"
139233   wire width 4 $3\wen[3:0]
139234   attribute \src "libresoc.v:52231.3-52267.6"
139235   wire $4\bigendian_i$next[0:0]$2137
139236   attribute \src "libresoc.v:52034.3-52156.6"
139237   wire $4\core_core_cr_rd_ok$next[0:0]$2087
139238   attribute \src "libresoc.v:52034.3-52156.6"
139239   wire $4\core_core_cr_wr_ok$next[0:0]$2088
139240   attribute \src "libresoc.v:52034.3-52156.6"
139241   wire $4\core_core_exc_$signal$50$next[0:0]$2089
139242   attribute \src "libresoc.v:52034.3-52156.6"
139243   wire $4\core_core_exc_$signal$51$next[0:0]$2090
139244   attribute \src "libresoc.v:52034.3-52156.6"
139245   wire $4\core_core_exc_$signal$52$next[0:0]$2091
139246   attribute \src "libresoc.v:52034.3-52156.6"
139247   wire $4\core_core_exc_$signal$53$next[0:0]$2092
139248   attribute \src "libresoc.v:52034.3-52156.6"
139249   wire $4\core_core_exc_$signal$54$next[0:0]$2093
139250   attribute \src "libresoc.v:52034.3-52156.6"
139251   wire $4\core_core_exc_$signal$55$next[0:0]$2094
139252   attribute \src "libresoc.v:52034.3-52156.6"
139253   wire $4\core_core_exc_$signal$56$next[0:0]$2095
139254   attribute \src "libresoc.v:52034.3-52156.6"
139255   wire $4\core_core_exc_$signal$next[0:0]$2096
139256   attribute \src "libresoc.v:52034.3-52156.6"
139257   wire $4\core_core_oe_ok$next[0:0]$2097
139258   attribute \src "libresoc.v:52034.3-52156.6"
139259   wire $4\core_core_rc_ok$next[0:0]$2098
139260   attribute \src "libresoc.v:52034.3-52156.6"
139261   wire $4\core_cr_in1_ok$next[0:0]$2099
139262   attribute \src "libresoc.v:52034.3-52156.6"
139263   wire $4\core_cr_in2_ok$49$next[0:0]$2100
139264   attribute \src "libresoc.v:52034.3-52156.6"
139265   wire $4\core_cr_in2_ok$next[0:0]$2101
139266   attribute \src "libresoc.v:52034.3-52156.6"
139267   wire $4\core_cr_out_ok$next[0:0]$2102
139268   attribute \src "libresoc.v:52034.3-52156.6"
139269   wire $4\core_ea_ok$next[0:0]$2103
139270   attribute \src "libresoc.v:52034.3-52156.6"
139271   wire $4\core_fast1_ok$next[0:0]$2104
139272   attribute \src "libresoc.v:52034.3-52156.6"
139273   wire $4\core_fast2_ok$next[0:0]$2105
139274   attribute \src "libresoc.v:52034.3-52156.6"
139275   wire $4\core_fasto1_ok$next[0:0]$2106
139276   attribute \src "libresoc.v:52034.3-52156.6"
139277   wire $4\core_fasto2_ok$next[0:0]$2107
139278   attribute \src "libresoc.v:52034.3-52156.6"
139279   wire $4\core_reg1_ok$next[0:0]$2108
139280   attribute \src "libresoc.v:52034.3-52156.6"
139281   wire $4\core_reg2_ok$next[0:0]$2109
139282   attribute \src "libresoc.v:52034.3-52156.6"
139283   wire $4\core_reg3_ok$next[0:0]$2110
139284   attribute \src "libresoc.v:52034.3-52156.6"
139285   wire $4\core_rego_ok$next[0:0]$2111
139286   attribute \src "libresoc.v:52034.3-52156.6"
139287   wire $4\core_spr1_ok$next[0:0]$2112
139288   attribute \src "libresoc.v:52034.3-52156.6"
139289   wire $4\core_spro_ok$next[0:0]$2113
139290   attribute \src "libresoc.v:52385.3-52430.6"
139291   wire width 2 $4\fsm_state$next[1:0]$2157
139292   attribute \src "libresoc.v:52355.3-52384.6"
139293   wire $4\msr_read$next[0:0]$2151
139294   attribute \src "libresoc.v:52194.3-52230.6"
139295   wire width 32 $4\raw_insn_i$next[31:0]$2131
139296   attribute \src "libresoc.v:52385.3-52430.6"
139297   wire width 2 $5\fsm_state$next[1:0]$2158
139298   attribute \src "libresoc.v:50797.19-50797.110"
139299   wire width 65 $add$libresoc.v:50797$1623_Y
139300   attribute \src "libresoc.v:50804.18-50804.107"
139301   wire width 65 $add$libresoc.v:50804$1630_Y
139302   attribute \src "libresoc.v:50779.18-50779.101"
139303   wire $and$libresoc.v:50779$1603_Y
139304   attribute \src "libresoc.v:50783.19-50783.104"
139305   wire $and$libresoc.v:50783$1607_Y
139306   attribute \src "libresoc.v:50787.19-50787.104"
139307   wire $and$libresoc.v:50787$1611_Y
139308   attribute \src "libresoc.v:50803.18-50803.104"
139309   wire $and$libresoc.v:50803$1629_Y
139310   attribute \src "libresoc.v:50812.18-50812.101"
139311   wire $and$libresoc.v:50812$1638_Y
139312   attribute \src "libresoc.v:50813.18-50813.109"
139313   wire width 4 $and$libresoc.v:50813$1639_Y
139314   attribute \src "libresoc.v:50820.18-50820.101"
139315   wire $and$libresoc.v:50820$1646_Y
139316   attribute \src "libresoc.v:50823.18-50823.101"
139317   wire $and$libresoc.v:50823$1649_Y
139318   attribute \src "libresoc.v:50826.18-50826.101"
139319   wire $and$libresoc.v:50826$1652_Y
139320   attribute \src "libresoc.v:50829.18-50829.101"
139321   wire $and$libresoc.v:50829$1655_Y
139322   attribute \src "libresoc.v:50832.18-50832.101"
139323   wire $and$libresoc.v:50832$1658_Y
139324   attribute \src "libresoc.v:50794.19-50794.109"
139325   wire width 64 $extend$libresoc.v:50794$1618_Y
139326   attribute \src "libresoc.v:50795.19-50795.108"
139327   wire width 64 $extend$libresoc.v:50795$1620_Y
139328   attribute \src "libresoc.v:50789.19-50789.111"
139329   wire width 7 $mul$libresoc.v:50789$1613_Y
139330   attribute \src "libresoc.v:50791.19-50791.111"
139331   wire width 7 $mul$libresoc.v:50791$1615_Y
139332   attribute \src "libresoc.v:50784.18-50784.102"
139333   wire $ne$libresoc.v:50784$1608_Y
139334   attribute \src "libresoc.v:50793.19-50793.118"
139335   wire $ne$libresoc.v:50793$1617_Y
139336   attribute \src "libresoc.v:50801.18-50801.102"
139337   wire $ne$libresoc.v:50801$1627_Y
139338   attribute \src "libresoc.v:50780.19-50780.102"
139339   wire $not$libresoc.v:50780$1604_Y
139340   attribute \src "libresoc.v:50781.19-50781.107"
139341   wire $not$libresoc.v:50781$1605_Y
139342   attribute \src "libresoc.v:50782.19-50782.109"
139343   wire $not$libresoc.v:50782$1606_Y
139344   attribute \src "libresoc.v:50785.19-50785.107"
139345   wire $not$libresoc.v:50785$1609_Y
139346   attribute \src "libresoc.v:50786.19-50786.109"
139347   wire $not$libresoc.v:50786$1610_Y
139348   attribute \src "libresoc.v:50788.19-50788.100"
139349   wire $not$libresoc.v:50788$1612_Y
139350   attribute \src "libresoc.v:50802.18-50802.103"
139351   wire $not$libresoc.v:50802$1628_Y
139352   attribute \src "libresoc.v:50805.18-50805.98"
139353   wire $not$libresoc.v:50805$1631_Y
139354   attribute \src "libresoc.v:50806.18-50806.101"
139355   wire $not$libresoc.v:50806$1632_Y
139356   attribute \src "libresoc.v:50807.18-50807.101"
139357   wire $not$libresoc.v:50807$1633_Y
139358   attribute \src "libresoc.v:50808.18-50808.101"
139359   wire $not$libresoc.v:50808$1634_Y
139360   attribute \src "libresoc.v:50809.18-50809.101"
139361   wire $not$libresoc.v:50809$1635_Y
139362   attribute \src "libresoc.v:50810.18-50810.106"
139363   wire $not$libresoc.v:50810$1636_Y
139364   attribute \src "libresoc.v:50811.18-50811.108"
139365   wire $not$libresoc.v:50811$1637_Y
139366   attribute \src "libresoc.v:50815.18-50815.101"
139367   wire $not$libresoc.v:50815$1641_Y
139368   attribute \src "libresoc.v:50816.18-50816.101"
139369   wire $not$libresoc.v:50816$1642_Y
139370   attribute \src "libresoc.v:50817.18-50817.101"
139371   wire $not$libresoc.v:50817$1643_Y
139372   attribute \src "libresoc.v:50818.18-50818.106"
139373   wire $not$libresoc.v:50818$1644_Y
139374   attribute \src "libresoc.v:50819.18-50819.108"
139375   wire $not$libresoc.v:50819$1645_Y
139376   attribute \src "libresoc.v:50821.18-50821.106"
139377   wire $not$libresoc.v:50821$1647_Y
139378   attribute \src "libresoc.v:50822.18-50822.108"
139379   wire $not$libresoc.v:50822$1648_Y
139380   attribute \src "libresoc.v:50824.18-50824.106"
139381   wire $not$libresoc.v:50824$1650_Y
139382   attribute \src "libresoc.v:50825.18-50825.108"
139383   wire $not$libresoc.v:50825$1651_Y
139384   attribute \src "libresoc.v:50827.18-50827.106"
139385   wire $not$libresoc.v:50827$1653_Y
139386   attribute \src "libresoc.v:50828.18-50828.108"
139387   wire $not$libresoc.v:50828$1654_Y
139388   attribute \src "libresoc.v:50830.18-50830.106"
139389   wire $not$libresoc.v:50830$1656_Y
139390   attribute \src "libresoc.v:50831.18-50831.108"
139391   wire $not$libresoc.v:50831$1657_Y
139392   attribute \src "libresoc.v:50833.18-50833.99"
139393   wire $not$libresoc.v:50833$1659_Y
139394   attribute \src "libresoc.v:50834.18-50834.106"
139395   wire $not$libresoc.v:50834$1660_Y
139396   attribute \src "libresoc.v:50835.18-50835.108"
139397   wire $not$libresoc.v:50835$1661_Y
139398   attribute \src "libresoc.v:50799.18-50799.110"
139399   wire $or$libresoc.v:50799$1625_Y
139400   attribute \src "libresoc.v:50800.18-50800.100"
139401   wire $or$libresoc.v:50800$1626_Y
139402   attribute \src "libresoc.v:50794.19-50794.109"
139403   wire width 64 $pos$libresoc.v:50794$1619_Y
139404   attribute \src "libresoc.v:50795.19-50795.108"
139405   wire width 64 $pos$libresoc.v:50795$1621_Y
139406   attribute \src "libresoc.v:50814.18-50814.91"
139407   wire $reduce_or$libresoc.v:50814$1640_Y
139408   attribute \src "libresoc.v:50790.19-50790.42"
139409   wire width 64 $shr$libresoc.v:50790$1614_Y
139410   attribute \src "libresoc.v:50792.19-50792.42"
139411   wire width 64 $shr$libresoc.v:50792$1616_Y
139412   attribute \src "libresoc.v:50796.19-50796.110"
139413   wire width 65 $sub$libresoc.v:50796$1622_Y
139414   attribute \src "libresoc.v:50798.18-50798.101"
139415   wire width 3 $sub$libresoc.v:50798$1624_Y
139416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174"
139417   wire \$10
139418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
139419   wire \$101
139420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139421   wire \$103
139422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139423   wire \$105
139424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139425   wire \$107
139426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139427   wire \$109
139428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139429   wire \$111
139430   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139431   wire \$113
139432   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
139433   wire \$115
139434   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
139435   wire width 32 \$117
139436   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
139437   wire width 7 \$118
139438   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175"
139439   wire width 3 \$12
139440   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
139441   wire width 32 \$121
139442   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
139443   wire width 7 \$122
139444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307"
139445   wire \$125
139446   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
139447   wire width 64 \$127
139448   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
139449   wire width 64 \$129
139450   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175"
139451   wire width 3 \$13
139452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393"
139453   wire width 65 \$132
139454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393"
139455   wire width 65 \$133
139456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409"
139457   wire width 65 \$136
139458   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409"
139459   wire width 65 \$137
139460   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
139461   wire \$15
139462   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
139463   wire \$17
139464   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
139465   wire \$19
139466   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
139467   wire \$21
139468   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
139469   wire \$23
139470   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201"
139471   wire width 65 \$25
139472   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201"
139473   wire width 65 \$26
139474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206"
139475   wire \$28
139476   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
139477   wire \$30
139478   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
139479   wire \$32
139480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
139481   wire \$34
139482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
139483   wire \$36
139484   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139485   wire \$38
139486   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139487   wire \$40
139488   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139489   wire \$42
139490   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
139491   wire \$44
139492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
139493   wire width 4 \$45
139494   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
139495   wire \$57
139496   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
139497   wire \$59
139498   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
139499   wire \$61
139500   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139501   wire \$63
139502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139503   wire \$65
139504   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139505   wire \$67
139506   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139507   wire \$69
139508   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139509   wire \$71
139510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139511   wire \$73
139512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139513   wire \$75
139514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139515   wire \$77
139516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139517   wire \$79
139518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139519   wire \$81
139520   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139521   wire \$83
139522   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139523   wire \$85
139524   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139525   wire \$87
139526   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139527   wire \$89
139528   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139529   wire \$91
139530   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
139531   wire \$93
139532   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139533   wire \$95
139534   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139535   wire \$97
139536   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
139537   wire \$99
139538   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
139539   wire input 333 \TAP_bus__tck
139540   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
139541   wire input 169 \TAP_bus__tdi
139542   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
139543   wire output 324 \TAP_bus__tdo
139544   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
139545   wire input 334 \TAP_bus__tms
139546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94"
139547   wire \bigendian_i
139548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94"
139549   wire \bigendian_i$next
139550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105"
139551   wire output 3 \busy_o
139552   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
139553   wire width 64 \cia__data_o
139554   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
139555   wire width 4 \cia__ren
139556   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
139557   wire input 351 \clk
139558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
139559   wire width 8 \core_asmcode
139560   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
139561   wire width 8 \core_asmcode$next
139562   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104"
139563   wire input 4 \core_bigendian_i
139564   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
139565   wire width 64 \core_core_cia
139566   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
139567   wire width 64 \core_core_cia$next
139568   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139569   wire width 8 \core_core_cr_rd
139570   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139571   wire width 8 \core_core_cr_rd$next
139572   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139573   wire \core_core_cr_rd_ok
139574   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139575   wire \core_core_cr_rd_ok$next
139576   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139577   wire width 8 \core_core_cr_wr
139578   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139579   wire width 8 \core_core_cr_wr$next
139580   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139581   wire \core_core_cr_wr_ok
139582   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139583   wire \core_core_cr_wr_ok$next
139584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139585   wire \core_core_exc_$signal
139586   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139587   wire \core_core_exc_$signal$50
139588   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139589   wire \core_core_exc_$signal$50$next
139590   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139591   wire \core_core_exc_$signal$51
139592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139593   wire \core_core_exc_$signal$51$next
139594   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139595   wire \core_core_exc_$signal$52
139596   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139597   wire \core_core_exc_$signal$52$next
139598   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139599   wire \core_core_exc_$signal$53
139600   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139601   wire \core_core_exc_$signal$53$next
139602   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139603   wire \core_core_exc_$signal$54
139604   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139605   wire \core_core_exc_$signal$54$next
139606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139607   wire \core_core_exc_$signal$55
139608   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139609   wire \core_core_exc_$signal$55$next
139610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139611   wire \core_core_exc_$signal$56
139612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139613   wire \core_core_exc_$signal$56$next
139614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
139615   wire \core_core_exc_$signal$next
139616   attribute \enum_base_type "Function"
139617   attribute \enum_value_000000000000 "NONE"
139618   attribute \enum_value_000000000010 "ALU"
139619   attribute \enum_value_000000000100 "LDST"
139620   attribute \enum_value_000000001000 "SHIFT_ROT"
139621   attribute \enum_value_000000010000 "LOGICAL"
139622   attribute \enum_value_000000100000 "BRANCH"
139623   attribute \enum_value_000001000000 "CR"
139624   attribute \enum_value_000010000000 "TRAP"
139625   attribute \enum_value_000100000000 "MUL"
139626   attribute \enum_value_001000000000 "DIV"
139627   attribute \enum_value_010000000000 "SPR"
139628   attribute \enum_value_100000000000 "MMU"
139629   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
139630   wire width 12 \core_core_fn_unit
139631   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
139632   wire width 12 \core_core_fn_unit$next
139633   attribute \enum_base_type "CryIn"
139634   attribute \enum_value_00 "ZERO"
139635   attribute \enum_value_01 "ONE"
139636   attribute \enum_value_10 "CA"
139637   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
139638   wire width 2 \core_core_input_carry
139639   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
139640   wire width 2 \core_core_input_carry$next
139641   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
139642   wire width 32 \core_core_insn
139643   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
139644   wire width 32 \core_core_insn$next
139645   attribute \enum_base_type "MicrOp"
139646   attribute \enum_value_0000000 "OP_ILLEGAL"
139647   attribute \enum_value_0000001 "OP_NOP"
139648   attribute \enum_value_0000010 "OP_ADD"
139649   attribute \enum_value_0000011 "OP_ADDPCIS"
139650   attribute \enum_value_0000100 "OP_AND"
139651   attribute \enum_value_0000101 "OP_ATTN"
139652   attribute \enum_value_0000110 "OP_B"
139653   attribute \enum_value_0000111 "OP_BC"
139654   attribute \enum_value_0001000 "OP_BCREG"
139655   attribute \enum_value_0001001 "OP_BPERM"
139656   attribute \enum_value_0001010 "OP_CMP"
139657   attribute \enum_value_0001011 "OP_CMPB"
139658   attribute \enum_value_0001100 "OP_CMPEQB"
139659   attribute \enum_value_0001101 "OP_CMPRB"
139660   attribute \enum_value_0001110 "OP_CNTZ"
139661   attribute \enum_value_0001111 "OP_CRAND"
139662   attribute \enum_value_0010000 "OP_CRANDC"
139663   attribute \enum_value_0010001 "OP_CREQV"
139664   attribute \enum_value_0010010 "OP_CRNAND"
139665   attribute \enum_value_0010011 "OP_CRNOR"
139666   attribute \enum_value_0010100 "OP_CROR"
139667   attribute \enum_value_0010101 "OP_CRORC"
139668   attribute \enum_value_0010110 "OP_CRXOR"
139669   attribute \enum_value_0010111 "OP_DARN"
139670   attribute \enum_value_0011000 "OP_DCBF"
139671   attribute \enum_value_0011001 "OP_DCBST"
139672   attribute \enum_value_0011010 "OP_DCBT"
139673   attribute \enum_value_0011011 "OP_DCBTST"
139674   attribute \enum_value_0011100 "OP_DCBZ"
139675   attribute \enum_value_0011101 "OP_DIV"
139676   attribute \enum_value_0011110 "OP_DIVE"
139677   attribute \enum_value_0011111 "OP_EXTS"
139678   attribute \enum_value_0100000 "OP_EXTSWSLI"
139679   attribute \enum_value_0100001 "OP_ICBI"
139680   attribute \enum_value_0100010 "OP_ICBT"
139681   attribute \enum_value_0100011 "OP_ISEL"
139682   attribute \enum_value_0100100 "OP_ISYNC"
139683   attribute \enum_value_0100101 "OP_LOAD"
139684   attribute \enum_value_0100110 "OP_STORE"
139685   attribute \enum_value_0100111 "OP_MADDHD"
139686   attribute \enum_value_0101000 "OP_MADDHDU"
139687   attribute \enum_value_0101001 "OP_MADDLD"
139688   attribute \enum_value_0101010 "OP_MCRF"
139689   attribute \enum_value_0101011 "OP_MCRXR"
139690   attribute \enum_value_0101100 "OP_MCRXRX"
139691   attribute \enum_value_0101101 "OP_MFCR"
139692   attribute \enum_value_0101110 "OP_MFSPR"
139693   attribute \enum_value_0101111 "OP_MOD"
139694   attribute \enum_value_0110000 "OP_MTCRF"
139695   attribute \enum_value_0110001 "OP_MTSPR"
139696   attribute \enum_value_0110010 "OP_MUL_L64"
139697   attribute \enum_value_0110011 "OP_MUL_H64"
139698   attribute \enum_value_0110100 "OP_MUL_H32"
139699   attribute \enum_value_0110101 "OP_OR"
139700   attribute \enum_value_0110110 "OP_POPCNT"
139701   attribute \enum_value_0110111 "OP_PRTY"
139702   attribute \enum_value_0111000 "OP_RLC"
139703   attribute \enum_value_0111001 "OP_RLCL"
139704   attribute \enum_value_0111010 "OP_RLCR"
139705   attribute \enum_value_0111011 "OP_SETB"
139706   attribute \enum_value_0111100 "OP_SHL"
139707   attribute \enum_value_0111101 "OP_SHR"
139708   attribute \enum_value_0111110 "OP_SYNC"
139709   attribute \enum_value_0111111 "OP_TRAP"
139710   attribute \enum_value_1000011 "OP_XOR"
139711   attribute \enum_value_1000100 "OP_SIM_CONFIG"
139712   attribute \enum_value_1000101 "OP_CROP"
139713   attribute \enum_value_1000110 "OP_RFID"
139714   attribute \enum_value_1000111 "OP_MFMSR"
139715   attribute \enum_value_1001000 "OP_MTMSRD"
139716   attribute \enum_value_1001001 "OP_SC"
139717   attribute \enum_value_1001010 "OP_MTMSR"
139718   attribute \enum_value_1001011 "OP_TLBIE"
139719   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
139720   wire width 7 \core_core_insn_type
139721   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
139722   wire width 7 \core_core_insn_type$next
139723   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
139724   wire \core_core_is_32bit
139725   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
139726   wire \core_core_is_32bit$next
139727   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
139728   wire \core_core_lk
139729   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
139730   wire \core_core_lk$next
139731   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
139732   wire width 64 \core_core_msr
139733   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
139734   wire width 64 \core_core_msr$next
139735   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139736   wire \core_core_oe
139737   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139738   wire \core_core_oe$next
139739   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139740   wire \core_core_oe_ok
139741   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139742   wire \core_core_oe_ok$next
139743   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139744   wire \core_core_rc
139745   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139746   wire \core_core_rc$next
139747   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139748   wire \core_core_rc_ok
139749   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139750   wire \core_core_rc_ok$next
139751   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
139752   wire width 13 \core_core_trapaddr
139753   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
139754   wire width 13 \core_core_trapaddr$next
139755   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
139756   wire width 8 \core_core_traptype
139757   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
139758   wire width 8 \core_core_traptype$next
139759   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
139760   wire \core_coresync_rst
139761   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139762   wire width 3 \core_cr_in1
139763   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139764   wire width 3 \core_cr_in1$next
139765   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139766   wire \core_cr_in1_ok
139767   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139768   wire \core_cr_in1_ok$next
139769   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139770   wire width 3 \core_cr_in2
139771   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139772   wire width 3 \core_cr_in2$48
139773   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139774   wire width 3 \core_cr_in2$48$next
139775   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139776   wire width 3 \core_cr_in2$next
139777   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139778   wire \core_cr_in2_ok
139779   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139780   wire \core_cr_in2_ok$49
139781   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139782   wire \core_cr_in2_ok$49$next
139783   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139784   wire \core_cr_in2_ok$next
139785   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139786   wire width 3 \core_cr_out
139787   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139788   wire width 3 \core_cr_out$next
139789   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139790   wire \core_cr_out_ok
139791   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139792   wire \core_cr_out_ok$next
139793   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11"
139794   wire width 64 \core_dec
139795   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11"
139796   wire width 64 \core_dec$next
139797   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139798   wire width 5 \core_ea
139799   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139800   wire width 5 \core_ea$next
139801   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139802   wire \core_ea_ok
139803   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139804   wire \core_ea_ok$next
139805   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10"
139806   wire \core_eint
139807   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10"
139808   wire \core_eint$next
139809   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139810   wire width 3 \core_fast1
139811   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139812   wire width 3 \core_fast1$next
139813   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139814   wire \core_fast1_ok
139815   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139816   wire \core_fast1_ok$next
139817   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139818   wire width 3 \core_fast2
139819   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139820   wire width 3 \core_fast2$next
139821   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139822   wire \core_fast2_ok
139823   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139824   wire \core_fast2_ok$next
139825   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139826   wire width 3 \core_fasto1
139827   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139828   wire width 3 \core_fasto1$next
139829   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139830   wire \core_fasto1_ok
139831   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139832   wire \core_fasto1_ok$next
139833   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139834   wire width 3 \core_fasto2
139835   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139836   wire width 3 \core_fasto2$next
139837   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139838   wire \core_fasto2_ok
139839   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139840   wire \core_fasto2_ok$next
139841   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
139842   wire width 64 \core_msr
139843   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
139844   wire width 64 \core_msr$next
139845   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
139846   wire width 64 \core_pc
139847   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
139848   wire width 64 \core_pc$next
139849   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139850   wire width 5 \core_reg1
139851   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139852   wire width 5 \core_reg1$next
139853   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139854   wire \core_reg1_ok
139855   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139856   wire \core_reg1_ok$next
139857   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139858   wire width 5 \core_reg2
139859   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139860   wire width 5 \core_reg2$next
139861   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139862   wire \core_reg2_ok
139863   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139864   wire \core_reg2_ok$next
139865   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139866   wire width 5 \core_reg3
139867   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139868   wire width 5 \core_reg3$next
139869   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139870   wire \core_reg3_ok
139871   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139872   wire \core_reg3_ok$next
139873   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139874   wire width 5 \core_rego
139875   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139876   wire width 5 \core_rego$next
139877   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139878   wire \core_rego_ok
139879   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139880   wire \core_rego_ok$next
139881   attribute \enum_base_type "SPR"
139882   attribute \enum_value_0000000001 "XER"
139883   attribute \enum_value_0000000011 "DSCR"
139884   attribute \enum_value_0000001000 "LR"
139885   attribute \enum_value_0000001001 "CTR"
139886   attribute \enum_value_0000001101 "AMR"
139887   attribute \enum_value_0000010001 "DSCR_priv"
139888   attribute \enum_value_0000010010 "DSISR"
139889   attribute \enum_value_0000010011 "DAR"
139890   attribute \enum_value_0000010110 "DEC"
139891   attribute \enum_value_0000011010 "SRR0"
139892   attribute \enum_value_0000011011 "SRR1"
139893   attribute \enum_value_0000011100 "CFAR"
139894   attribute \enum_value_0000011101 "AMR_priv"
139895   attribute \enum_value_0000110000 "PIDR"
139896   attribute \enum_value_0000111101 "IAMR"
139897   attribute \enum_value_0010000000 "TFHAR"
139898   attribute \enum_value_0010000001 "TFIAR"
139899   attribute \enum_value_0010000010 "TEXASR"
139900   attribute \enum_value_0010000011 "TEXASRU"
139901   attribute \enum_value_0010001000 "CTRL"
139902   attribute \enum_value_0010010000 "TIDR"
139903   attribute \enum_value_0010011000 "CTRL_priv"
139904   attribute \enum_value_0010011001 "FSCR"
139905   attribute \enum_value_0010011101 "UAMOR"
139906   attribute \enum_value_0010011110 "GSR"
139907   attribute \enum_value_0010011111 "PSPB"
139908   attribute \enum_value_0010110000 "DPDES"
139909   attribute \enum_value_0010110100 "DAWR0"
139910   attribute \enum_value_0010111010 "RPR"
139911   attribute \enum_value_0010111011 "CIABR"
139912   attribute \enum_value_0010111100 "DAWRX0"
139913   attribute \enum_value_0010111110 "HFSCR"
139914   attribute \enum_value_0100000000 "VRSAVE"
139915   attribute \enum_value_0100000011 "SPRG3"
139916   attribute \enum_value_0100001100 "TB"
139917   attribute \enum_value_0100001101 "TBU"
139918   attribute \enum_value_0100010000 "SPRG0_priv"
139919   attribute \enum_value_0100010001 "SPRG1_priv"
139920   attribute \enum_value_0100010010 "SPRG2_priv"
139921   attribute \enum_value_0100010011 "SPRG3_priv"
139922   attribute \enum_value_0100011011 "CIR"
139923   attribute \enum_value_0100011100 "TBL"
139924   attribute \enum_value_0100011101 "TBU_hypv"
139925   attribute \enum_value_0100011110 "TBU40"
139926   attribute \enum_value_0100011111 "PVR"
139927   attribute \enum_value_0100110000 "HSPRG0"
139928   attribute \enum_value_0100110001 "HSPRG1"
139929   attribute \enum_value_0100110010 "HDSISR"
139930   attribute \enum_value_0100110011 "HDAR"
139931   attribute \enum_value_0100110100 "SPURR"
139932   attribute \enum_value_0100110101 "PURR"
139933   attribute \enum_value_0100110110 "HDEC"
139934   attribute \enum_value_0100111001 "HRMOR"
139935   attribute \enum_value_0100111010 "HSRR0"
139936   attribute \enum_value_0100111011 "HSRR1"
139937   attribute \enum_value_0100111110 "LPCR"
139938   attribute \enum_value_0100111111 "LPIDR"
139939   attribute \enum_value_0101010000 "HMER"
139940   attribute \enum_value_0101010001 "HMEER"
139941   attribute \enum_value_0101010010 "PCR"
139942   attribute \enum_value_0101010011 "HEIR"
139943   attribute \enum_value_0101011101 "AMOR"
139944   attribute \enum_value_0110111110 "TIR"
139945   attribute \enum_value_0111010000 "PTCR"
139946   attribute \enum_value_1100000000 "SIER"
139947   attribute \enum_value_1100000001 "MMCR2"
139948   attribute \enum_value_1100000010 "MMCRA"
139949   attribute \enum_value_1100000011 "PMC1"
139950   attribute \enum_value_1100000100 "PMC2"
139951   attribute \enum_value_1100000101 "PMC3"
139952   attribute \enum_value_1100000110 "PMC4"
139953   attribute \enum_value_1100000111 "PMC5"
139954   attribute \enum_value_1100001000 "PMC6"
139955   attribute \enum_value_1100001011 "MMCR0"
139956   attribute \enum_value_1100001100 "SIAR"
139957   attribute \enum_value_1100001101 "SDAR"
139958   attribute \enum_value_1100001110 "MMCR1"
139959   attribute \enum_value_1100010000 "SIER_priv"
139960   attribute \enum_value_1100010001 "MMCR2_priv"
139961   attribute \enum_value_1100010010 "MMCRA_priv"
139962   attribute \enum_value_1100010011 "PMC1_priv"
139963   attribute \enum_value_1100010100 "PMC2_priv"
139964   attribute \enum_value_1100010101 "PMC3_priv"
139965   attribute \enum_value_1100010110 "PMC4_priv"
139966   attribute \enum_value_1100010111 "PMC5_priv"
139967   attribute \enum_value_1100011000 "PMC6_priv"
139968   attribute \enum_value_1100011011 "MMCR0_priv"
139969   attribute \enum_value_1100011100 "SIAR_priv"
139970   attribute \enum_value_1100011101 "SDAR_priv"
139971   attribute \enum_value_1100011110 "MMCR1_priv"
139972   attribute \enum_value_1100100000 "BESCRS"
139973   attribute \enum_value_1100100001 "BESCRSU"
139974   attribute \enum_value_1100100010 "BESCRR"
139975   attribute \enum_value_1100100011 "BESCRRU"
139976   attribute \enum_value_1100100100 "EBBHR"
139977   attribute \enum_value_1100100101 "EBBRR"
139978   attribute \enum_value_1100100110 "BESCR"
139979   attribute \enum_value_1100101000 "reserved808"
139980   attribute \enum_value_1100101001 "reserved809"
139981   attribute \enum_value_1100101010 "reserved810"
139982   attribute \enum_value_1100101011 "reserved811"
139983   attribute \enum_value_1100101111 "TAR"
139984   attribute \enum_value_1100110000 "ASDR"
139985   attribute \enum_value_1100110111 "PSSCR"
139986   attribute \enum_value_1101010000 "IC"
139987   attribute \enum_value_1101010001 "VTB"
139988   attribute \enum_value_1101010111 "PSSCR_hypv"
139989   attribute \enum_value_1110000000 "PPR"
139990   attribute \enum_value_1110000010 "PPR32"
139991   attribute \enum_value_1111111111 "PIR"
139992   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139993   wire width 10 \core_spr1
139994   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139995   wire width 10 \core_spr1$next
139996   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139997   wire \core_spr1_ok
139998   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
139999   wire \core_spr1_ok$next
140000   attribute \enum_base_type "SPR"
140001   attribute \enum_value_0000000001 "XER"
140002   attribute \enum_value_0000000011 "DSCR"
140003   attribute \enum_value_0000001000 "LR"
140004   attribute \enum_value_0000001001 "CTR"
140005   attribute \enum_value_0000001101 "AMR"
140006   attribute \enum_value_0000010001 "DSCR_priv"
140007   attribute \enum_value_0000010010 "DSISR"
140008   attribute \enum_value_0000010011 "DAR"
140009   attribute \enum_value_0000010110 "DEC"
140010   attribute \enum_value_0000011010 "SRR0"
140011   attribute \enum_value_0000011011 "SRR1"
140012   attribute \enum_value_0000011100 "CFAR"
140013   attribute \enum_value_0000011101 "AMR_priv"
140014   attribute \enum_value_0000110000 "PIDR"
140015   attribute \enum_value_0000111101 "IAMR"
140016   attribute \enum_value_0010000000 "TFHAR"
140017   attribute \enum_value_0010000001 "TFIAR"
140018   attribute \enum_value_0010000010 "TEXASR"
140019   attribute \enum_value_0010000011 "TEXASRU"
140020   attribute \enum_value_0010001000 "CTRL"
140021   attribute \enum_value_0010010000 "TIDR"
140022   attribute \enum_value_0010011000 "CTRL_priv"
140023   attribute \enum_value_0010011001 "FSCR"
140024   attribute \enum_value_0010011101 "UAMOR"
140025   attribute \enum_value_0010011110 "GSR"
140026   attribute \enum_value_0010011111 "PSPB"
140027   attribute \enum_value_0010110000 "DPDES"
140028   attribute \enum_value_0010110100 "DAWR0"
140029   attribute \enum_value_0010111010 "RPR"
140030   attribute \enum_value_0010111011 "CIABR"
140031   attribute \enum_value_0010111100 "DAWRX0"
140032   attribute \enum_value_0010111110 "HFSCR"
140033   attribute \enum_value_0100000000 "VRSAVE"
140034   attribute \enum_value_0100000011 "SPRG3"
140035   attribute \enum_value_0100001100 "TB"
140036   attribute \enum_value_0100001101 "TBU"
140037   attribute \enum_value_0100010000 "SPRG0_priv"
140038   attribute \enum_value_0100010001 "SPRG1_priv"
140039   attribute \enum_value_0100010010 "SPRG2_priv"
140040   attribute \enum_value_0100010011 "SPRG3_priv"
140041   attribute \enum_value_0100011011 "CIR"
140042   attribute \enum_value_0100011100 "TBL"
140043   attribute \enum_value_0100011101 "TBU_hypv"
140044   attribute \enum_value_0100011110 "TBU40"
140045   attribute \enum_value_0100011111 "PVR"
140046   attribute \enum_value_0100110000 "HSPRG0"
140047   attribute \enum_value_0100110001 "HSPRG1"
140048   attribute \enum_value_0100110010 "HDSISR"
140049   attribute \enum_value_0100110011 "HDAR"
140050   attribute \enum_value_0100110100 "SPURR"
140051   attribute \enum_value_0100110101 "PURR"
140052   attribute \enum_value_0100110110 "HDEC"
140053   attribute \enum_value_0100111001 "HRMOR"
140054   attribute \enum_value_0100111010 "HSRR0"
140055   attribute \enum_value_0100111011 "HSRR1"
140056   attribute \enum_value_0100111110 "LPCR"
140057   attribute \enum_value_0100111111 "LPIDR"
140058   attribute \enum_value_0101010000 "HMER"
140059   attribute \enum_value_0101010001 "HMEER"
140060   attribute \enum_value_0101010010 "PCR"
140061   attribute \enum_value_0101010011 "HEIR"
140062   attribute \enum_value_0101011101 "AMOR"
140063   attribute \enum_value_0110111110 "TIR"
140064   attribute \enum_value_0111010000 "PTCR"
140065   attribute \enum_value_1100000000 "SIER"
140066   attribute \enum_value_1100000001 "MMCR2"
140067   attribute \enum_value_1100000010 "MMCRA"
140068   attribute \enum_value_1100000011 "PMC1"
140069   attribute \enum_value_1100000100 "PMC2"
140070   attribute \enum_value_1100000101 "PMC3"
140071   attribute \enum_value_1100000110 "PMC4"
140072   attribute \enum_value_1100000111 "PMC5"
140073   attribute \enum_value_1100001000 "PMC6"
140074   attribute \enum_value_1100001011 "MMCR0"
140075   attribute \enum_value_1100001100 "SIAR"
140076   attribute \enum_value_1100001101 "SDAR"
140077   attribute \enum_value_1100001110 "MMCR1"
140078   attribute \enum_value_1100010000 "SIER_priv"
140079   attribute \enum_value_1100010001 "MMCR2_priv"
140080   attribute \enum_value_1100010010 "MMCRA_priv"
140081   attribute \enum_value_1100010011 "PMC1_priv"
140082   attribute \enum_value_1100010100 "PMC2_priv"
140083   attribute \enum_value_1100010101 "PMC3_priv"
140084   attribute \enum_value_1100010110 "PMC4_priv"
140085   attribute \enum_value_1100010111 "PMC5_priv"
140086   attribute \enum_value_1100011000 "PMC6_priv"
140087   attribute \enum_value_1100011011 "MMCR0_priv"
140088   attribute \enum_value_1100011100 "SIAR_priv"
140089   attribute \enum_value_1100011101 "SDAR_priv"
140090   attribute \enum_value_1100011110 "MMCR1_priv"
140091   attribute \enum_value_1100100000 "BESCRS"
140092   attribute \enum_value_1100100001 "BESCRSU"
140093   attribute \enum_value_1100100010 "BESCRR"
140094   attribute \enum_value_1100100011 "BESCRRU"
140095   attribute \enum_value_1100100100 "EBBHR"
140096   attribute \enum_value_1100100101 "EBBRR"
140097   attribute \enum_value_1100100110 "BESCR"
140098   attribute \enum_value_1100101000 "reserved808"
140099   attribute \enum_value_1100101001 "reserved809"
140100   attribute \enum_value_1100101010 "reserved810"
140101   attribute \enum_value_1100101011 "reserved811"
140102   attribute \enum_value_1100101111 "TAR"
140103   attribute \enum_value_1100110000 "ASDR"
140104   attribute \enum_value_1100110111 "PSSCR"
140105   attribute \enum_value_1101010000 "IC"
140106   attribute \enum_value_1101010001 "VTB"
140107   attribute \enum_value_1101010111 "PSSCR_hypv"
140108   attribute \enum_value_1110000000 "PPR"
140109   attribute \enum_value_1110000010 "PPR32"
140110   attribute \enum_value_1111111111 "PIR"
140111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140112   wire width 10 \core_spro
140113   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140114   wire width 10 \core_spro$next
140115   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140116   wire \core_spro_ok
140117   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140118   wire \core_spro_ok$next
140119   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
140120   wire \core_stopped_i
140121   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
140122   wire \core_terminate_o
140123   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
140124   wire width 3 \core_xer_in
140125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
140126   wire width 3 \core_xer_in$next
140127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
140128   wire \core_xer_out
140129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
140130   wire \core_xer_out$next
140131   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99"
140132   wire \corebusy_o
140133   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
140134   wire input 2 \coresync_clk
140135   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
140136   wire \cu_ad__go_i
140137   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
140138   wire \cu_ad__rel_o
140139   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
140140   wire \cu_st__go_i
140141   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
140142   wire \cu_st__rel_o
140143   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
140144   wire \cu_st__rel_o_dly
140145   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
140146   wire \cu_st__rel_o_dly$next
140147   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
140148   wire \cu_st__rel_o_rise
140149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343"
140150   wire \d_cr_delay
140151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343"
140152   wire \d_cr_delay$next
140153   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333"
140154   wire \d_reg_delay
140155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333"
140156   wire \d_reg_delay$next
140157   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353"
140158   wire \d_xer_delay
140159   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353"
140160   wire \d_xer_delay$next
140161   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140162   wire width 64 \data_i
140163   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
140164   wire width 64 \dbg_core_dbg_msr
140165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
140166   wire width 64 \dbg_core_dbg_pc
140167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98"
140168   wire \dbg_core_rst_o
140169   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97"
140170   wire \dbg_core_stop_o
140171   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103"
140172   wire \dbg_core_stopped_i
140173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
140174   wire \dbg_d_cr_ack
140175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
140176   wire width 64 \dbg_d_cr_data
140177   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
140178   wire \dbg_d_cr_req
140179   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
140180   wire \dbg_d_gpr_ack
140181   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78"
140182   wire width 7 \dbg_d_gpr_addr
140183   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
140184   wire width 64 \dbg_d_gpr_data
140185   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
140186   wire \dbg_d_gpr_req
140187   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77"
140188   wire \dbg_d_xer_ack
140189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
140190   wire width 64 \dbg_d_xer_data
140191   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76"
140192   wire \dbg_d_xer_req
140193   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62"
140194   wire \dbg_dmi_ack_o
140195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
140196   wire width 4 \dbg_dmi_addr_i
140197   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
140198   wire width 4 \dbg_dmi_addr_i$next
140199   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
140200   wire width 64 \dbg_dmi_din
140201   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
140202   wire width 64 \dbg_dmi_din$next
140203   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59"
140204   wire width 64 \dbg_dmi_dout
140205   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
140206   wire \dbg_dmi_req_i
140207   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
140208   wire \dbg_dmi_req_i$next
140209   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
140210   wire \dbg_dmi_we_i
140211   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61"
140212   wire \dbg_dmi_we_i$next
140213   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102"
140214   wire \dbg_terminate_i
140215   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
140216   wire width 8 \dec2_asmcode
140217   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446"
140218   wire \dec2_bigendian
140219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
140220   wire width 64 \dec2_cia
140221   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140222   wire width 3 \dec2_cr_in1
140223   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140224   wire \dec2_cr_in1_ok
140225   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140226   wire width 3 \dec2_cr_in2
140227   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140228   wire width 3 \dec2_cr_in2$1
140229   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140230   wire \dec2_cr_in2_ok
140231   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140232   wire \dec2_cr_in2_ok$2
140233   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140234   wire width 3 \dec2_cr_out
140235   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140236   wire \dec2_cr_out_ok
140237   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140238   wire width 8 \dec2_cr_rd
140239   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140240   wire \dec2_cr_rd_ok
140241   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140242   wire width 8 \dec2_cr_wr
140243   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140244   wire \dec2_cr_wr_ok
140245   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11"
140246   wire width 64 \dec2_cur_dec
140247   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11"
140248   wire width 64 \dec2_cur_dec$next
140249   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10"
140250   wire \dec2_cur_eint
140251   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10"
140252   wire \dec2_cur_eint$next
140253   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
140254   wire width 64 \dec2_cur_msr
140255   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
140256   wire width 64 \dec2_cur_msr$next
140257   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
140258   wire width 64 \dec2_cur_pc
140259   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
140260   wire width 64 \dec2_cur_pc$next
140261   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140262   wire width 5 \dec2_ea
140263   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140264   wire \dec2_ea_ok
140265   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140266   wire \dec2_exc_$signal
140267   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140268   wire \dec2_exc_$signal$3
140269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140270   wire \dec2_exc_$signal$4
140271   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140272   wire \dec2_exc_$signal$5
140273   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140274   wire \dec2_exc_$signal$6
140275   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140276   wire \dec2_exc_$signal$7
140277   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140278   wire \dec2_exc_$signal$8
140279   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
140280   wire \dec2_exc_$signal$9
140281   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140282   wire width 3 \dec2_fast1
140283   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140284   wire \dec2_fast1_ok
140285   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140286   wire width 3 \dec2_fast2
140287   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140288   wire \dec2_fast2_ok
140289   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140290   wire width 3 \dec2_fasto1
140291   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140292   wire \dec2_fasto1_ok
140293   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140294   wire width 3 \dec2_fasto2
140295   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140296   wire \dec2_fasto2_ok
140297   attribute \enum_base_type "Function"
140298   attribute \enum_value_000000000000 "NONE"
140299   attribute \enum_value_000000000010 "ALU"
140300   attribute \enum_value_000000000100 "LDST"
140301   attribute \enum_value_000000001000 "SHIFT_ROT"
140302   attribute \enum_value_000000010000 "LOGICAL"
140303   attribute \enum_value_000000100000 "BRANCH"
140304   attribute \enum_value_000001000000 "CR"
140305   attribute \enum_value_000010000000 "TRAP"
140306   attribute \enum_value_000100000000 "MUL"
140307   attribute \enum_value_001000000000 "DIV"
140308   attribute \enum_value_010000000000 "SPR"
140309   attribute \enum_value_100000000000 "MMU"
140310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
140311   wire width 12 \dec2_fn_unit
140312   attribute \enum_base_type "CryIn"
140313   attribute \enum_value_00 "ZERO"
140314   attribute \enum_value_01 "ONE"
140315   attribute \enum_value_10 "CA"
140316   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
140317   wire width 2 \dec2_input_carry
140318   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
140319   wire width 32 \dec2_insn
140320   attribute \enum_base_type "MicrOp"
140321   attribute \enum_value_0000000 "OP_ILLEGAL"
140322   attribute \enum_value_0000001 "OP_NOP"
140323   attribute \enum_value_0000010 "OP_ADD"
140324   attribute \enum_value_0000011 "OP_ADDPCIS"
140325   attribute \enum_value_0000100 "OP_AND"
140326   attribute \enum_value_0000101 "OP_ATTN"
140327   attribute \enum_value_0000110 "OP_B"
140328   attribute \enum_value_0000111 "OP_BC"
140329   attribute \enum_value_0001000 "OP_BCREG"
140330   attribute \enum_value_0001001 "OP_BPERM"
140331   attribute \enum_value_0001010 "OP_CMP"
140332   attribute \enum_value_0001011 "OP_CMPB"
140333   attribute \enum_value_0001100 "OP_CMPEQB"
140334   attribute \enum_value_0001101 "OP_CMPRB"
140335   attribute \enum_value_0001110 "OP_CNTZ"
140336   attribute \enum_value_0001111 "OP_CRAND"
140337   attribute \enum_value_0010000 "OP_CRANDC"
140338   attribute \enum_value_0010001 "OP_CREQV"
140339   attribute \enum_value_0010010 "OP_CRNAND"
140340   attribute \enum_value_0010011 "OP_CRNOR"
140341   attribute \enum_value_0010100 "OP_CROR"
140342   attribute \enum_value_0010101 "OP_CRORC"
140343   attribute \enum_value_0010110 "OP_CRXOR"
140344   attribute \enum_value_0010111 "OP_DARN"
140345   attribute \enum_value_0011000 "OP_DCBF"
140346   attribute \enum_value_0011001 "OP_DCBST"
140347   attribute \enum_value_0011010 "OP_DCBT"
140348   attribute \enum_value_0011011 "OP_DCBTST"
140349   attribute \enum_value_0011100 "OP_DCBZ"
140350   attribute \enum_value_0011101 "OP_DIV"
140351   attribute \enum_value_0011110 "OP_DIVE"
140352   attribute \enum_value_0011111 "OP_EXTS"
140353   attribute \enum_value_0100000 "OP_EXTSWSLI"
140354   attribute \enum_value_0100001 "OP_ICBI"
140355   attribute \enum_value_0100010 "OP_ICBT"
140356   attribute \enum_value_0100011 "OP_ISEL"
140357   attribute \enum_value_0100100 "OP_ISYNC"
140358   attribute \enum_value_0100101 "OP_LOAD"
140359   attribute \enum_value_0100110 "OP_STORE"
140360   attribute \enum_value_0100111 "OP_MADDHD"
140361   attribute \enum_value_0101000 "OP_MADDHDU"
140362   attribute \enum_value_0101001 "OP_MADDLD"
140363   attribute \enum_value_0101010 "OP_MCRF"
140364   attribute \enum_value_0101011 "OP_MCRXR"
140365   attribute \enum_value_0101100 "OP_MCRXRX"
140366   attribute \enum_value_0101101 "OP_MFCR"
140367   attribute \enum_value_0101110 "OP_MFSPR"
140368   attribute \enum_value_0101111 "OP_MOD"
140369   attribute \enum_value_0110000 "OP_MTCRF"
140370   attribute \enum_value_0110001 "OP_MTSPR"
140371   attribute \enum_value_0110010 "OP_MUL_L64"
140372   attribute \enum_value_0110011 "OP_MUL_H64"
140373   attribute \enum_value_0110100 "OP_MUL_H32"
140374   attribute \enum_value_0110101 "OP_OR"
140375   attribute \enum_value_0110110 "OP_POPCNT"
140376   attribute \enum_value_0110111 "OP_PRTY"
140377   attribute \enum_value_0111000 "OP_RLC"
140378   attribute \enum_value_0111001 "OP_RLCL"
140379   attribute \enum_value_0111010 "OP_RLCR"
140380   attribute \enum_value_0111011 "OP_SETB"
140381   attribute \enum_value_0111100 "OP_SHL"
140382   attribute \enum_value_0111101 "OP_SHR"
140383   attribute \enum_value_0111110 "OP_SYNC"
140384   attribute \enum_value_0111111 "OP_TRAP"
140385   attribute \enum_value_1000011 "OP_XOR"
140386   attribute \enum_value_1000100 "OP_SIM_CONFIG"
140387   attribute \enum_value_1000101 "OP_CROP"
140388   attribute \enum_value_1000110 "OP_RFID"
140389   attribute \enum_value_1000111 "OP_MFMSR"
140390   attribute \enum_value_1001000 "OP_MTMSRD"
140391   attribute \enum_value_1001001 "OP_SC"
140392   attribute \enum_value_1001010 "OP_MTMSR"
140393   attribute \enum_value_1001011 "OP_TLBIE"
140394   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
140395   wire width 7 \dec2_insn_type
140396   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
140397   wire \dec2_is_32bit
140398   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
140399   wire \dec2_lk
140400   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
140401   wire width 64 \dec2_msr
140402   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140403   wire \dec2_oe
140404   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140405   wire \dec2_oe_ok
140406   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445"
140407   wire width 32 \dec2_raw_opcode_in
140408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140409   wire \dec2_rc
140410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140411   wire \dec2_rc_ok
140412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140413   wire width 5 \dec2_reg1
140414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140415   wire \dec2_reg1_ok
140416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140417   wire width 5 \dec2_reg2
140418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140419   wire \dec2_reg2_ok
140420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140421   wire width 5 \dec2_reg3
140422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140423   wire \dec2_reg3_ok
140424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140425   wire width 5 \dec2_rego
140426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140427   wire \dec2_rego_ok
140428   attribute \enum_base_type "SPR"
140429   attribute \enum_value_0000000001 "XER"
140430   attribute \enum_value_0000000011 "DSCR"
140431   attribute \enum_value_0000001000 "LR"
140432   attribute \enum_value_0000001001 "CTR"
140433   attribute \enum_value_0000001101 "AMR"
140434   attribute \enum_value_0000010001 "DSCR_priv"
140435   attribute \enum_value_0000010010 "DSISR"
140436   attribute \enum_value_0000010011 "DAR"
140437   attribute \enum_value_0000010110 "DEC"
140438   attribute \enum_value_0000011010 "SRR0"
140439   attribute \enum_value_0000011011 "SRR1"
140440   attribute \enum_value_0000011100 "CFAR"
140441   attribute \enum_value_0000011101 "AMR_priv"
140442   attribute \enum_value_0000110000 "PIDR"
140443   attribute \enum_value_0000111101 "IAMR"
140444   attribute \enum_value_0010000000 "TFHAR"
140445   attribute \enum_value_0010000001 "TFIAR"
140446   attribute \enum_value_0010000010 "TEXASR"
140447   attribute \enum_value_0010000011 "TEXASRU"
140448   attribute \enum_value_0010001000 "CTRL"
140449   attribute \enum_value_0010010000 "TIDR"
140450   attribute \enum_value_0010011000 "CTRL_priv"
140451   attribute \enum_value_0010011001 "FSCR"
140452   attribute \enum_value_0010011101 "UAMOR"
140453   attribute \enum_value_0010011110 "GSR"
140454   attribute \enum_value_0010011111 "PSPB"
140455   attribute \enum_value_0010110000 "DPDES"
140456   attribute \enum_value_0010110100 "DAWR0"
140457   attribute \enum_value_0010111010 "RPR"
140458   attribute \enum_value_0010111011 "CIABR"
140459   attribute \enum_value_0010111100 "DAWRX0"
140460   attribute \enum_value_0010111110 "HFSCR"
140461   attribute \enum_value_0100000000 "VRSAVE"
140462   attribute \enum_value_0100000011 "SPRG3"
140463   attribute \enum_value_0100001100 "TB"
140464   attribute \enum_value_0100001101 "TBU"
140465   attribute \enum_value_0100010000 "SPRG0_priv"
140466   attribute \enum_value_0100010001 "SPRG1_priv"
140467   attribute \enum_value_0100010010 "SPRG2_priv"
140468   attribute \enum_value_0100010011 "SPRG3_priv"
140469   attribute \enum_value_0100011011 "CIR"
140470   attribute \enum_value_0100011100 "TBL"
140471   attribute \enum_value_0100011101 "TBU_hypv"
140472   attribute \enum_value_0100011110 "TBU40"
140473   attribute \enum_value_0100011111 "PVR"
140474   attribute \enum_value_0100110000 "HSPRG0"
140475   attribute \enum_value_0100110001 "HSPRG1"
140476   attribute \enum_value_0100110010 "HDSISR"
140477   attribute \enum_value_0100110011 "HDAR"
140478   attribute \enum_value_0100110100 "SPURR"
140479   attribute \enum_value_0100110101 "PURR"
140480   attribute \enum_value_0100110110 "HDEC"
140481   attribute \enum_value_0100111001 "HRMOR"
140482   attribute \enum_value_0100111010 "HSRR0"
140483   attribute \enum_value_0100111011 "HSRR1"
140484   attribute \enum_value_0100111110 "LPCR"
140485   attribute \enum_value_0100111111 "LPIDR"
140486   attribute \enum_value_0101010000 "HMER"
140487   attribute \enum_value_0101010001 "HMEER"
140488   attribute \enum_value_0101010010 "PCR"
140489   attribute \enum_value_0101010011 "HEIR"
140490   attribute \enum_value_0101011101 "AMOR"
140491   attribute \enum_value_0110111110 "TIR"
140492   attribute \enum_value_0111010000 "PTCR"
140493   attribute \enum_value_1100000000 "SIER"
140494   attribute \enum_value_1100000001 "MMCR2"
140495   attribute \enum_value_1100000010 "MMCRA"
140496   attribute \enum_value_1100000011 "PMC1"
140497   attribute \enum_value_1100000100 "PMC2"
140498   attribute \enum_value_1100000101 "PMC3"
140499   attribute \enum_value_1100000110 "PMC4"
140500   attribute \enum_value_1100000111 "PMC5"
140501   attribute \enum_value_1100001000 "PMC6"
140502   attribute \enum_value_1100001011 "MMCR0"
140503   attribute \enum_value_1100001100 "SIAR"
140504   attribute \enum_value_1100001101 "SDAR"
140505   attribute \enum_value_1100001110 "MMCR1"
140506   attribute \enum_value_1100010000 "SIER_priv"
140507   attribute \enum_value_1100010001 "MMCR2_priv"
140508   attribute \enum_value_1100010010 "MMCRA_priv"
140509   attribute \enum_value_1100010011 "PMC1_priv"
140510   attribute \enum_value_1100010100 "PMC2_priv"
140511   attribute \enum_value_1100010101 "PMC3_priv"
140512   attribute \enum_value_1100010110 "PMC4_priv"
140513   attribute \enum_value_1100010111 "PMC5_priv"
140514   attribute \enum_value_1100011000 "PMC6_priv"
140515   attribute \enum_value_1100011011 "MMCR0_priv"
140516   attribute \enum_value_1100011100 "SIAR_priv"
140517   attribute \enum_value_1100011101 "SDAR_priv"
140518   attribute \enum_value_1100011110 "MMCR1_priv"
140519   attribute \enum_value_1100100000 "BESCRS"
140520   attribute \enum_value_1100100001 "BESCRSU"
140521   attribute \enum_value_1100100010 "BESCRR"
140522   attribute \enum_value_1100100011 "BESCRRU"
140523   attribute \enum_value_1100100100 "EBBHR"
140524   attribute \enum_value_1100100101 "EBBRR"
140525   attribute \enum_value_1100100110 "BESCR"
140526   attribute \enum_value_1100101000 "reserved808"
140527   attribute \enum_value_1100101001 "reserved809"
140528   attribute \enum_value_1100101010 "reserved810"
140529   attribute \enum_value_1100101011 "reserved811"
140530   attribute \enum_value_1100101111 "TAR"
140531   attribute \enum_value_1100110000 "ASDR"
140532   attribute \enum_value_1100110111 "PSSCR"
140533   attribute \enum_value_1101010000 "IC"
140534   attribute \enum_value_1101010001 "VTB"
140535   attribute \enum_value_1101010111 "PSSCR_hypv"
140536   attribute \enum_value_1110000000 "PPR"
140537   attribute \enum_value_1110000010 "PPR32"
140538   attribute \enum_value_1111111111 "PIR"
140539   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140540   wire width 10 \dec2_spr1
140541   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140542   wire \dec2_spr1_ok
140543   attribute \enum_base_type "SPR"
140544   attribute \enum_value_0000000001 "XER"
140545   attribute \enum_value_0000000011 "DSCR"
140546   attribute \enum_value_0000001000 "LR"
140547   attribute \enum_value_0000001001 "CTR"
140548   attribute \enum_value_0000001101 "AMR"
140549   attribute \enum_value_0000010001 "DSCR_priv"
140550   attribute \enum_value_0000010010 "DSISR"
140551   attribute \enum_value_0000010011 "DAR"
140552   attribute \enum_value_0000010110 "DEC"
140553   attribute \enum_value_0000011010 "SRR0"
140554   attribute \enum_value_0000011011 "SRR1"
140555   attribute \enum_value_0000011100 "CFAR"
140556   attribute \enum_value_0000011101 "AMR_priv"
140557   attribute \enum_value_0000110000 "PIDR"
140558   attribute \enum_value_0000111101 "IAMR"
140559   attribute \enum_value_0010000000 "TFHAR"
140560   attribute \enum_value_0010000001 "TFIAR"
140561   attribute \enum_value_0010000010 "TEXASR"
140562   attribute \enum_value_0010000011 "TEXASRU"
140563   attribute \enum_value_0010001000 "CTRL"
140564   attribute \enum_value_0010010000 "TIDR"
140565   attribute \enum_value_0010011000 "CTRL_priv"
140566   attribute \enum_value_0010011001 "FSCR"
140567   attribute \enum_value_0010011101 "UAMOR"
140568   attribute \enum_value_0010011110 "GSR"
140569   attribute \enum_value_0010011111 "PSPB"
140570   attribute \enum_value_0010110000 "DPDES"
140571   attribute \enum_value_0010110100 "DAWR0"
140572   attribute \enum_value_0010111010 "RPR"
140573   attribute \enum_value_0010111011 "CIABR"
140574   attribute \enum_value_0010111100 "DAWRX0"
140575   attribute \enum_value_0010111110 "HFSCR"
140576   attribute \enum_value_0100000000 "VRSAVE"
140577   attribute \enum_value_0100000011 "SPRG3"
140578   attribute \enum_value_0100001100 "TB"
140579   attribute \enum_value_0100001101 "TBU"
140580   attribute \enum_value_0100010000 "SPRG0_priv"
140581   attribute \enum_value_0100010001 "SPRG1_priv"
140582   attribute \enum_value_0100010010 "SPRG2_priv"
140583   attribute \enum_value_0100010011 "SPRG3_priv"
140584   attribute \enum_value_0100011011 "CIR"
140585   attribute \enum_value_0100011100 "TBL"
140586   attribute \enum_value_0100011101 "TBU_hypv"
140587   attribute \enum_value_0100011110 "TBU40"
140588   attribute \enum_value_0100011111 "PVR"
140589   attribute \enum_value_0100110000 "HSPRG0"
140590   attribute \enum_value_0100110001 "HSPRG1"
140591   attribute \enum_value_0100110010 "HDSISR"
140592   attribute \enum_value_0100110011 "HDAR"
140593   attribute \enum_value_0100110100 "SPURR"
140594   attribute \enum_value_0100110101 "PURR"
140595   attribute \enum_value_0100110110 "HDEC"
140596   attribute \enum_value_0100111001 "HRMOR"
140597   attribute \enum_value_0100111010 "HSRR0"
140598   attribute \enum_value_0100111011 "HSRR1"
140599   attribute \enum_value_0100111110 "LPCR"
140600   attribute \enum_value_0100111111 "LPIDR"
140601   attribute \enum_value_0101010000 "HMER"
140602   attribute \enum_value_0101010001 "HMEER"
140603   attribute \enum_value_0101010010 "PCR"
140604   attribute \enum_value_0101010011 "HEIR"
140605   attribute \enum_value_0101011101 "AMOR"
140606   attribute \enum_value_0110111110 "TIR"
140607   attribute \enum_value_0111010000 "PTCR"
140608   attribute \enum_value_1100000000 "SIER"
140609   attribute \enum_value_1100000001 "MMCR2"
140610   attribute \enum_value_1100000010 "MMCRA"
140611   attribute \enum_value_1100000011 "PMC1"
140612   attribute \enum_value_1100000100 "PMC2"
140613   attribute \enum_value_1100000101 "PMC3"
140614   attribute \enum_value_1100000110 "PMC4"
140615   attribute \enum_value_1100000111 "PMC5"
140616   attribute \enum_value_1100001000 "PMC6"
140617   attribute \enum_value_1100001011 "MMCR0"
140618   attribute \enum_value_1100001100 "SIAR"
140619   attribute \enum_value_1100001101 "SDAR"
140620   attribute \enum_value_1100001110 "MMCR1"
140621   attribute \enum_value_1100010000 "SIER_priv"
140622   attribute \enum_value_1100010001 "MMCR2_priv"
140623   attribute \enum_value_1100010010 "MMCRA_priv"
140624   attribute \enum_value_1100010011 "PMC1_priv"
140625   attribute \enum_value_1100010100 "PMC2_priv"
140626   attribute \enum_value_1100010101 "PMC3_priv"
140627   attribute \enum_value_1100010110 "PMC4_priv"
140628   attribute \enum_value_1100010111 "PMC5_priv"
140629   attribute \enum_value_1100011000 "PMC6_priv"
140630   attribute \enum_value_1100011011 "MMCR0_priv"
140631   attribute \enum_value_1100011100 "SIAR_priv"
140632   attribute \enum_value_1100011101 "SDAR_priv"
140633   attribute \enum_value_1100011110 "MMCR1_priv"
140634   attribute \enum_value_1100100000 "BESCRS"
140635   attribute \enum_value_1100100001 "BESCRSU"
140636   attribute \enum_value_1100100010 "BESCRR"
140637   attribute \enum_value_1100100011 "BESCRRU"
140638   attribute \enum_value_1100100100 "EBBHR"
140639   attribute \enum_value_1100100101 "EBBRR"
140640   attribute \enum_value_1100100110 "BESCR"
140641   attribute \enum_value_1100101000 "reserved808"
140642   attribute \enum_value_1100101001 "reserved809"
140643   attribute \enum_value_1100101010 "reserved810"
140644   attribute \enum_value_1100101011 "reserved811"
140645   attribute \enum_value_1100101111 "TAR"
140646   attribute \enum_value_1100110000 "ASDR"
140647   attribute \enum_value_1100110111 "PSSCR"
140648   attribute \enum_value_1101010000 "IC"
140649   attribute \enum_value_1101010001 "VTB"
140650   attribute \enum_value_1101010111 "PSSCR_hypv"
140651   attribute \enum_value_1110000000 "PPR"
140652   attribute \enum_value_1110000010 "PPR32"
140653   attribute \enum_value_1111111111 "PIR"
140654   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140655   wire width 10 \dec2_spro
140656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
140657   wire \dec2_spro_ok
140658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
140659   wire width 13 \dec2_trapaddr
140660   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
140661   wire width 8 \dec2_traptype
140662   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
140663   wire width 3 \dec2_xer_in
140664   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
140665   wire \dec2_xer_out
140666   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173"
140667   wire width 2 \delay
140668   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173"
140669   wire width 2 \delay$next
140670   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140671   wire width 5 \dmi__addr
140672   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140673   wire width 64 \dmi__data_o
140674   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140675   wire \dmi__ren
140676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140677   wire output 170 \eint_0__core__i
140678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140679   wire input 15 \eint_0__pad__i
140680   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140681   wire output 171 \eint_1__core__i
140682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140683   wire input 16 \eint_1__pad__i
140684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140685   wire output 172 \eint_2__core__i
140686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140687   wire input 17 \eint_2__pad__i
140688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
140689   wire width 2 \fsm_state
140690   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
140691   wire width 2 \fsm_state$131
140692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
140693   wire width 2 \fsm_state$131$next
140694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
140695   wire width 2 \fsm_state$next
140696   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140697   wire width 32 \full_rd2__data_o
140698   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140699   wire width 8 \full_rd2__ren
140700   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140701   wire width 6 \full_rd__data_o
140702   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140703   wire width 3 \full_rd__ren
140704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140705   wire output 179 \gpio_e10__core__i
140706   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140707   wire input 25 \gpio_e10__core__o
140708   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140709   wire input 26 \gpio_e10__core__oe
140710   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140711   wire input 24 \gpio_e10__pad__i
140712   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140713   wire output 180 \gpio_e10__pad__o
140714   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140715   wire output 181 \gpio_e10__pad__oe
140716   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140717   wire output 182 \gpio_e11__core__i
140718   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140719   wire input 28 \gpio_e11__core__o
140720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140721   wire input 29 \gpio_e11__core__oe
140722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140723   wire input 27 \gpio_e11__pad__i
140724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140725   wire output 183 \gpio_e11__pad__o
140726   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140727   wire output 184 \gpio_e11__pad__oe
140728   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140729   wire output 185 \gpio_e12__core__i
140730   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140731   wire input 31 \gpio_e12__core__o
140732   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140733   wire input 32 \gpio_e12__core__oe
140734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140735   wire input 30 \gpio_e12__pad__i
140736   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140737   wire output 186 \gpio_e12__pad__o
140738   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140739   wire output 187 \gpio_e12__pad__oe
140740   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140741   wire output 188 \gpio_e13__core__i
140742   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140743   wire input 34 \gpio_e13__core__o
140744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140745   wire input 35 \gpio_e13__core__oe
140746   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140747   wire input 33 \gpio_e13__pad__i
140748   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140749   wire output 189 \gpio_e13__pad__o
140750   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140751   wire output 190 \gpio_e13__pad__oe
140752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140753   wire output 191 \gpio_e14__core__i
140754   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140755   wire input 37 \gpio_e14__core__o
140756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140757   wire input 38 \gpio_e14__core__oe
140758   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140759   wire input 36 \gpio_e14__pad__i
140760   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140761   wire output 192 \gpio_e14__pad__o
140762   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140763   wire output 193 \gpio_e14__pad__oe
140764   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140765   wire output 194 \gpio_e15__core__i
140766   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140767   wire input 40 \gpio_e15__core__o
140768   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140769   wire input 41 \gpio_e15__core__oe
140770   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140771   wire input 39 \gpio_e15__pad__i
140772   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140773   wire output 195 \gpio_e15__pad__o
140774   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140775   wire output 196 \gpio_e15__pad__oe
140776   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140777   wire output 173 \gpio_e8__core__i
140778   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140779   wire input 19 \gpio_e8__core__o
140780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140781   wire input 20 \gpio_e8__core__oe
140782   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140783   wire input 18 \gpio_e8__pad__i
140784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140785   wire output 174 \gpio_e8__pad__o
140786   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140787   wire output 175 \gpio_e8__pad__oe
140788   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140789   wire output 176 \gpio_e9__core__i
140790   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140791   wire input 22 \gpio_e9__core__o
140792   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140793   wire input 23 \gpio_e9__core__oe
140794   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140795   wire input 21 \gpio_e9__pad__i
140796   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140797   wire output 177 \gpio_e9__pad__o
140798   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140799   wire output 178 \gpio_e9__pad__oe
140800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140801   wire output 197 \gpio_s0__core__i
140802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140803   wire input 43 \gpio_s0__core__o
140804   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140805   wire input 44 \gpio_s0__core__oe
140806   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140807   wire input 42 \gpio_s0__pad__i
140808   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140809   wire output 198 \gpio_s0__pad__o
140810   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140811   wire output 199 \gpio_s0__pad__oe
140812   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140813   wire output 200 \gpio_s1__core__i
140814   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140815   wire input 46 \gpio_s1__core__o
140816   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140817   wire input 47 \gpio_s1__core__oe
140818   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140819   wire input 45 \gpio_s1__pad__i
140820   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140821   wire output 201 \gpio_s1__pad__o
140822   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140823   wire output 202 \gpio_s1__pad__oe
140824   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140825   wire output 203 \gpio_s2__core__i
140826   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140827   wire input 49 \gpio_s2__core__o
140828   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140829   wire input 50 \gpio_s2__core__oe
140830   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140831   wire input 48 \gpio_s2__pad__i
140832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140833   wire output 204 \gpio_s2__pad__o
140834   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140835   wire output 205 \gpio_s2__pad__oe
140836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140837   wire output 206 \gpio_s3__core__i
140838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140839   wire input 52 \gpio_s3__core__o
140840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140841   wire input 53 \gpio_s3__core__oe
140842   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140843   wire input 51 \gpio_s3__pad__i
140844   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140845   wire output 207 \gpio_s3__pad__o
140846   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140847   wire output 208 \gpio_s3__pad__oe
140848   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140849   wire output 209 \gpio_s4__core__i
140850   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140851   wire input 55 \gpio_s4__core__o
140852   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140853   wire input 56 \gpio_s4__core__oe
140854   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140855   wire input 54 \gpio_s4__pad__i
140856   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140857   wire output 210 \gpio_s4__pad__o
140858   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140859   wire output 211 \gpio_s4__pad__oe
140860   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140861   wire output 212 \gpio_s5__core__i
140862   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140863   wire input 58 \gpio_s5__core__o
140864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140865   wire input 59 \gpio_s5__core__oe
140866   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140867   wire input 57 \gpio_s5__pad__i
140868   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140869   wire output 213 \gpio_s5__pad__o
140870   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140871   wire output 214 \gpio_s5__pad__oe
140872   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140873   wire output 215 \gpio_s6__core__i
140874   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140875   wire input 61 \gpio_s6__core__o
140876   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140877   wire input 62 \gpio_s6__core__oe
140878   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140879   wire input 60 \gpio_s6__pad__i
140880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140881   wire output 216 \gpio_s6__pad__o
140882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140883   wire output 217 \gpio_s6__pad__oe
140884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140885   wire output 218 \gpio_s7__core__i
140886   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140887   wire input 64 \gpio_s7__core__o
140888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140889   wire input 65 \gpio_s7__core__oe
140890   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140891   wire input 63 \gpio_s7__pad__i
140892   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140893   wire output 219 \gpio_s7__pad__o
140894   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
140895   wire output 220 \gpio_s7__pad__oe
140896   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
140897   wire input 9 \ibus__ack
140898   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
140899   wire width 45 output 14 \ibus__adr
140900   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
140901   wire output 8 \ibus__cyc
140902   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
140903   wire width 64 input 13 \ibus__dat_r
140904   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
140905   wire input 10 \ibus__err
140906   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
140907   wire width 8 output 12 \ibus__sel
140908   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
140909   wire output 11 \ibus__stb
140910   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140911   wire output 335 \icp_wb__ack
140912   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140913   wire width 28 input 341 \icp_wb__adr
140914   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140915   wire input 336 \icp_wb__cyc
140916   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140917   wire width 32 output 337 \icp_wb__dat_r
140918   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140919   wire width 32 input 338 \icp_wb__dat_w
140920   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140921   wire width 4 input 342 \icp_wb__sel
140922   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140923   wire input 339 \icp_wb__stb
140924   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
140925   wire input 340 \icp_wb__we
140926   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
140927   wire output 348 \ics_wb__ack
140928   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
140929   wire width 28 input 343 \ics_wb__adr
140930   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
140931   wire input 345 \ics_wb__cyc
140932   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
140933   wire width 32 output 347 \ics_wb__dat_r
140934   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
140935   wire width 32 input 349 \ics_wb__dat_w
140936   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
140937   wire input 346 \ics_wb__stb
140938   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
140939   wire input 350 \ics_wb__we
140940   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
140941   wire width 32 \ilatch
140942   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
140943   wire width 32 \ilatch$next
140944   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
140945   wire width 48 \imem_a_pc_i
140946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
140947   wire \imem_a_valid_i
140948   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
140949   wire \imem_f_busy_o
140950   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
140951   wire width 64 \imem_f_instr_o
140952   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
140953   wire \imem_f_valid_i
140954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92"
140955   wire \imem_wb_icache_en
140956   attribute \src "libresoc.v:48722.7-48722.15"
140957   wire \initial
140958   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
140959   wire width 16 input 344 \int_level_i
140960   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140961   wire width 3 \issue__addr
140962   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140963   wire width 3 \issue__addr$135
140964   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140965   wire width 64 \issue__data_i
140966   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140967   wire width 64 \issue__data_o
140968   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140969   wire \issue__ren
140970   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
140971   wire \issue__wen
140972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98"
140973   wire \issue_i
140974   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97"
140975   wire \ivalid_i
140976   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140977   wire \jtag_dmi0__ack_o
140978   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140979   wire \jtag_dmi0__ack_o$next
140980   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140981   wire width 4 \jtag_dmi0__addr_i
140982   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140983   wire width 64 \jtag_dmi0__din
140984   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140985   wire width 64 \jtag_dmi0__dout
140986   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140987   wire width 64 \jtag_dmi0__dout$next
140988   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140989   wire \jtag_dmi0__req_i
140990   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
140991   wire \jtag_dmi0__we_i
140992   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
140993   wire input 331 \jtag_wb__ack
140994   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
140995   wire width 29 output 325 \jtag_wb__adr
140996   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
140997   wire output 327 \jtag_wb__cyc
140998   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
140999   wire width 64 input 332 \jtag_wb__dat_r
141000   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
141001   wire width 64 output 330 \jtag_wb__dat_w
141002   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
141003   wire output 326 \jtag_wb__sel
141004   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
141005   wire output 328 \jtag_wb__stb
141006   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
141007   wire output 329 \jtag_wb__we
141008   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141009   wire input 66 \mspi0_clk__core__o
141010   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141011   wire output 221 \mspi0_clk__pad__o
141012   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141013   wire input 67 \mspi0_cs_n__core__o
141014   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141015   wire output 222 \mspi0_cs_n__pad__o
141016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141017   wire output 224 \mspi0_miso__core__i
141018   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141019   wire input 69 \mspi0_miso__pad__i
141020   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141021   wire input 68 \mspi0_mosi__core__o
141022   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141023   wire output 223 \mspi0_mosi__pad__o
141024   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141025   wire input 70 \mspi1_clk__core__o
141026   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141027   wire output 225 \mspi1_clk__pad__o
141028   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141029   wire input 71 \mspi1_cs_n__core__o
141030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141031   wire output 226 \mspi1_cs_n__pad__o
141032   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141033   wire output 228 \mspi1_miso__core__i
141034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141035   wire input 73 \mspi1_miso__pad__i
141036   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141037   wire input 72 \mspi1_mosi__core__o
141038   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141039   wire output 227 \mspi1_mosi__pad__o
141040   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141041   wire width 64 \msr__data_o
141042   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141043   wire width 4 \msr__ren
141044   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223"
141045   wire \msr_read
141046   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223"
141047   wire \msr_read$next
141048   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141049   wire input 77 \mtwi_scl__core__o
141050   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141051   wire output 232 \mtwi_scl__pad__o
141052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141053   wire output 229 \mtwi_sda__core__i
141054   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141055   wire input 75 \mtwi_sda__core__o
141056   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141057   wire input 76 \mtwi_sda__core__oe
141058   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141059   wire input 74 \mtwi_sda__pad__i
141060   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141061   wire output 230 \mtwi_sda__pad__o
141062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141063   wire output 231 \mtwi_sda__pad__oe
141064   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391"
141065   wire width 64 \new_dec
141066   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408"
141067   wire width 64 \new_tb
141068   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
141069   wire width 64 \nia
141070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204"
141071   wire width 64 \pc
141072   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195"
141073   wire \pc_changed
141074   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195"
141075   wire \pc_changed$next
141076   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
141077   wire width 64 input 7 \pc_i
141078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
141079   wire input 6 \pc_i_ok
141080   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102"
141081   wire width 64 output 5 \pc_o
141082   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205"
141083   wire \pc_ok_delay
141084   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205"
141085   wire \pc_ok_delay$next
141086   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167"
141087   wire \por_clk
141088   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141089   wire input 78 \pwm_0__core__o
141090   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141091   wire output 233 \pwm_0__pad__o
141092   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141093   wire input 79 \pwm_1__core__o
141094   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141095   wire output 234 \pwm_1__pad__o
141096   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
141097   wire width 32 \raw_insn_i
141098   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
141099   wire width 32 \raw_insn_i$next
141100   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
141101   wire input 1 \rst
141102   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141103   wire input 83 \sd0_clk__core__o
141104   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141105   wire output 238 \sd0_clk__pad__o
141106   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141107   wire output 235 \sd0_cmd__core__i
141108   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141109   wire input 81 \sd0_cmd__core__o
141110   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141111   wire input 82 \sd0_cmd__core__oe
141112   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141113   wire input 80 \sd0_cmd__pad__i
141114   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141115   wire output 236 \sd0_cmd__pad__o
141116   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141117   wire output 237 \sd0_cmd__pad__oe
141118   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141119   wire output 239 \sd0_data0__core__i
141120   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141121   wire input 85 \sd0_data0__core__o
141122   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141123   wire input 86 \sd0_data0__core__oe
141124   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141125   wire input 84 \sd0_data0__pad__i
141126   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141127   wire output 240 \sd0_data0__pad__o
141128   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141129   wire output 241 \sd0_data0__pad__oe
141130   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141131   wire output 242 \sd0_data1__core__i
141132   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141133   wire input 88 \sd0_data1__core__o
141134   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141135   wire input 89 \sd0_data1__core__oe
141136   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141137   wire input 87 \sd0_data1__pad__i
141138   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141139   wire output 243 \sd0_data1__pad__o
141140   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141141   wire output 244 \sd0_data1__pad__oe
141142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141143   wire output 245 \sd0_data2__core__i
141144   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141145   wire input 91 \sd0_data2__core__o
141146   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141147   wire input 92 \sd0_data2__core__oe
141148   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141149   wire input 90 \sd0_data2__pad__i
141150   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141151   wire output 246 \sd0_data2__pad__o
141152   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141153   wire output 247 \sd0_data2__pad__oe
141154   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141155   wire output 248 \sd0_data3__core__i
141156   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141157   wire input 94 \sd0_data3__core__o
141158   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141159   wire input 95 \sd0_data3__core__oe
141160   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141161   wire input 93 \sd0_data3__pad__i
141162   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141163   wire output 249 \sd0_data3__pad__o
141164   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141165   wire output 250 \sd0_data3__pad__oe
141166   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141167   wire input 121 \sdr_a_0__core__o
141168   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141169   wire output 276 \sdr_a_0__pad__o
141170   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141171   wire input 139 \sdr_a_10__core__o
141172   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141173   wire output 294 \sdr_a_10__pad__o
141174   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141175   wire input 140 \sdr_a_11__core__o
141176   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141177   wire output 295 \sdr_a_11__pad__o
141178   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141179   wire input 141 \sdr_a_12__core__o
141180   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141181   wire output 296 \sdr_a_12__pad__o
141182   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141183   wire input 122 \sdr_a_1__core__o
141184   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141185   wire output 277 \sdr_a_1__pad__o
141186   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141187   wire input 123 \sdr_a_2__core__o
141188   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141189   wire output 278 \sdr_a_2__pad__o
141190   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141191   wire input 124 \sdr_a_3__core__o
141192   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141193   wire output 279 \sdr_a_3__pad__o
141194   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141195   wire input 125 \sdr_a_4__core__o
141196   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141197   wire output 280 \sdr_a_4__pad__o
141198   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141199   wire input 126 \sdr_a_5__core__o
141200   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141201   wire output 281 \sdr_a_5__pad__o
141202   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141203   wire input 127 \sdr_a_6__core__o
141204   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141205   wire output 282 \sdr_a_6__pad__o
141206   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141207   wire input 128 \sdr_a_7__core__o
141208   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141209   wire output 283 \sdr_a_7__pad__o
141210   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141211   wire input 129 \sdr_a_8__core__o
141212   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141213   wire output 284 \sdr_a_8__pad__o
141214   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141215   wire input 130 \sdr_a_9__core__o
141216   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141217   wire output 285 \sdr_a_9__pad__o
141218   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141219   wire input 131 \sdr_ba_0__core__o
141220   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141221   wire output 286 \sdr_ba_0__pad__o
141222   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141223   wire input 132 \sdr_ba_1__core__o
141224   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141225   wire output 287 \sdr_ba_1__pad__o
141226   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141227   wire input 136 \sdr_cas_n__core__o
141228   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141229   wire output 291 \sdr_cas_n__pad__o
141230   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141231   wire input 134 \sdr_cke__core__o
141232   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141233   wire output 289 \sdr_cke__pad__o
141234   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141235   wire input 133 \sdr_clock__core__o
141236   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141237   wire output 288 \sdr_clock__pad__o
141238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141239   wire input 138 \sdr_cs_n__core__o
141240   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141241   wire output 293 \sdr_cs_n__pad__o
141242   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141243   wire input 96 \sdr_dm_0__core__o
141244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141245   wire output 251 \sdr_dm_0__pad__o
141246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141247   wire output 297 \sdr_dm_1__core__i
141248   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141249   wire input 143 \sdr_dm_1__core__o
141250   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141251   wire input 144 \sdr_dm_1__core__oe
141252   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141253   wire input 142 \sdr_dm_1__pad__i
141254   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141255   wire output 298 \sdr_dm_1__pad__o
141256   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141257   wire output 299 \sdr_dm_1__pad__oe
141258   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141259   wire output 252 \sdr_dq_0__core__i
141260   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141261   wire input 98 \sdr_dq_0__core__o
141262   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141263   wire input 99 \sdr_dq_0__core__oe
141264   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141265   wire input 97 \sdr_dq_0__pad__i
141266   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141267   wire output 253 \sdr_dq_0__pad__o
141268   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141269   wire output 254 \sdr_dq_0__pad__oe
141270   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141271   wire output 306 \sdr_dq_10__core__i
141272   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141273   wire input 152 \sdr_dq_10__core__o
141274   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141275   wire input 153 \sdr_dq_10__core__oe
141276   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141277   wire input 151 \sdr_dq_10__pad__i
141278   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141279   wire output 307 \sdr_dq_10__pad__o
141280   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141281   wire output 308 \sdr_dq_10__pad__oe
141282   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141283   wire output 309 \sdr_dq_11__core__i
141284   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141285   wire input 155 \sdr_dq_11__core__o
141286   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141287   wire input 156 \sdr_dq_11__core__oe
141288   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141289   wire input 154 \sdr_dq_11__pad__i
141290   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141291   wire output 310 \sdr_dq_11__pad__o
141292   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141293   wire output 311 \sdr_dq_11__pad__oe
141294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141295   wire output 312 \sdr_dq_12__core__i
141296   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141297   wire input 158 \sdr_dq_12__core__o
141298   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141299   wire input 159 \sdr_dq_12__core__oe
141300   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141301   wire input 157 \sdr_dq_12__pad__i
141302   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141303   wire output 313 \sdr_dq_12__pad__o
141304   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141305   wire output 314 \sdr_dq_12__pad__oe
141306   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141307   wire output 315 \sdr_dq_13__core__i
141308   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141309   wire input 161 \sdr_dq_13__core__o
141310   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141311   wire input 162 \sdr_dq_13__core__oe
141312   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141313   wire input 160 \sdr_dq_13__pad__i
141314   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141315   wire output 316 \sdr_dq_13__pad__o
141316   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141317   wire output 317 \sdr_dq_13__pad__oe
141318   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141319   wire output 318 \sdr_dq_14__core__i
141320   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141321   wire input 164 \sdr_dq_14__core__o
141322   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141323   wire input 165 \sdr_dq_14__core__oe
141324   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141325   wire input 163 \sdr_dq_14__pad__i
141326   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141327   wire output 319 \sdr_dq_14__pad__o
141328   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141329   wire output 320 \sdr_dq_14__pad__oe
141330   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141331   wire output 321 \sdr_dq_15__core__i
141332   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141333   wire input 167 \sdr_dq_15__core__o
141334   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141335   wire input 168 \sdr_dq_15__core__oe
141336   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141337   wire input 166 \sdr_dq_15__pad__i
141338   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141339   wire output 322 \sdr_dq_15__pad__o
141340   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141341   wire output 323 \sdr_dq_15__pad__oe
141342   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141343   wire output 255 \sdr_dq_1__core__i
141344   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141345   wire input 101 \sdr_dq_1__core__o
141346   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141347   wire input 102 \sdr_dq_1__core__oe
141348   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141349   wire input 100 \sdr_dq_1__pad__i
141350   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141351   wire output 256 \sdr_dq_1__pad__o
141352   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141353   wire output 257 \sdr_dq_1__pad__oe
141354   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141355   wire output 258 \sdr_dq_2__core__i
141356   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141357   wire input 104 \sdr_dq_2__core__o
141358   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141359   wire input 105 \sdr_dq_2__core__oe
141360   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141361   wire input 103 \sdr_dq_2__pad__i
141362   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141363   wire output 259 \sdr_dq_2__pad__o
141364   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141365   wire output 260 \sdr_dq_2__pad__oe
141366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141367   wire output 261 \sdr_dq_3__core__i
141368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141369   wire input 107 \sdr_dq_3__core__o
141370   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141371   wire input 108 \sdr_dq_3__core__oe
141372   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141373   wire input 106 \sdr_dq_3__pad__i
141374   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141375   wire output 262 \sdr_dq_3__pad__o
141376   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141377   wire output 263 \sdr_dq_3__pad__oe
141378   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141379   wire output 264 \sdr_dq_4__core__i
141380   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141381   wire input 110 \sdr_dq_4__core__o
141382   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141383   wire input 111 \sdr_dq_4__core__oe
141384   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141385   wire input 109 \sdr_dq_4__pad__i
141386   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141387   wire output 265 \sdr_dq_4__pad__o
141388   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141389   wire output 266 \sdr_dq_4__pad__oe
141390   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141391   wire output 267 \sdr_dq_5__core__i
141392   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141393   wire input 113 \sdr_dq_5__core__o
141394   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141395   wire input 114 \sdr_dq_5__core__oe
141396   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141397   wire input 112 \sdr_dq_5__pad__i
141398   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141399   wire output 268 \sdr_dq_5__pad__o
141400   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141401   wire output 269 \sdr_dq_5__pad__oe
141402   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141403   wire output 270 \sdr_dq_6__core__i
141404   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141405   wire input 116 \sdr_dq_6__core__o
141406   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141407   wire input 117 \sdr_dq_6__core__oe
141408   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141409   wire input 115 \sdr_dq_6__pad__i
141410   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141411   wire output 271 \sdr_dq_6__pad__o
141412   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141413   wire output 272 \sdr_dq_6__pad__oe
141414   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141415   wire output 273 \sdr_dq_7__core__i
141416   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141417   wire input 119 \sdr_dq_7__core__o
141418   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141419   wire input 120 \sdr_dq_7__core__oe
141420   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141421   wire input 118 \sdr_dq_7__pad__i
141422   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141423   wire output 274 \sdr_dq_7__pad__o
141424   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141425   wire output 275 \sdr_dq_7__pad__oe
141426   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141427   wire output 300 \sdr_dq_8__core__i
141428   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141429   wire input 146 \sdr_dq_8__core__o
141430   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141431   wire input 147 \sdr_dq_8__core__oe
141432   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141433   wire input 145 \sdr_dq_8__pad__i
141434   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141435   wire output 301 \sdr_dq_8__pad__o
141436   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141437   wire output 302 \sdr_dq_8__pad__oe
141438   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141439   wire output 303 \sdr_dq_9__core__i
141440   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141441   wire input 149 \sdr_dq_9__core__o
141442   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141443   wire input 150 \sdr_dq_9__core__oe
141444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141445   wire input 148 \sdr_dq_9__pad__i
141446   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141447   wire output 304 \sdr_dq_9__pad__o
141448   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141449   wire output 305 \sdr_dq_9__pad__oe
141450   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141451   wire input 135 \sdr_ras_n__core__o
141452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141453   wire output 290 \sdr_ras_n__pad__o
141454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141455   wire input 137 \sdr_we_n__core__o
141456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
141457   wire output 292 \sdr_we_n__pad__o
141458   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141459   wire width 4 \state_nia_wen
141460   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
141461   wire \ti_rst
141462   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141463   wire width 4 \wen
141464   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
141465   wire \xics_icp_core_irq_o
141466   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
141467   wire width 8 \xics_icp_ics_i_pri
141468   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
141469   wire width 4 \xics_icp_ics_i_src
141470   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
141471   wire width 8 \xics_ics_icp_o_pri
141472   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
141473   wire width 4 \xics_ics_icp_o_src
141474   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409"
141475   cell $add $add$libresoc.v:50797$1623
141476     parameter \A_SIGNED 0
141477     parameter \A_WIDTH 64
141478     parameter \B_SIGNED 0
141479     parameter \B_WIDTH 1
141480     parameter \Y_WIDTH 65
141481     connect \A \issue__data_o
141482     connect \B 1'1
141483     connect \Y $add$libresoc.v:50797$1623_Y
141484   end
141485   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201"
141486   cell $add $add$libresoc.v:50804$1630
141487     parameter \A_SIGNED 0
141488     parameter \A_WIDTH 64
141489     parameter \B_SIGNED 0
141490     parameter \B_WIDTH 3
141491     parameter \Y_WIDTH 65
141492     connect \A \dec2_cur_pc
141493     connect \B 3'100
141494     connect \Y $add$libresoc.v:50804$1630_Y
141495   end
141496   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141497   cell $and $and$libresoc.v:50779$1603
141498     parameter \A_SIGNED 0
141499     parameter \A_WIDTH 1
141500     parameter \B_SIGNED 0
141501     parameter \B_WIDTH 1
141502     parameter \Y_WIDTH 1
141503     connect \A \$95
141504     connect \B \$97
141505     connect \Y $and$libresoc.v:50779$1603_Y
141506   end
141507   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141508   cell $and $and$libresoc.v:50783$1607
141509     parameter \A_SIGNED 0
141510     parameter \A_WIDTH 1
141511     parameter \B_SIGNED 0
141512     parameter \B_WIDTH 1
141513     parameter \Y_WIDTH 1
141514     connect \A \$103
141515     connect \B \$105
141516     connect \Y $and$libresoc.v:50783$1607_Y
141517   end
141518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141519   cell $and $and$libresoc.v:50787$1611
141520     parameter \A_SIGNED 0
141521     parameter \A_WIDTH 1
141522     parameter \B_SIGNED 0
141523     parameter \B_WIDTH 1
141524     parameter \Y_WIDTH 1
141525     connect \A \$109
141526     connect \B \$111
141527     connect \Y $and$libresoc.v:50787$1611_Y
141528   end
141529   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
141530   cell $and $and$libresoc.v:50803$1629
141531     parameter \A_SIGNED 0
141532     parameter \A_WIDTH 1
141533     parameter \B_SIGNED 0
141534     parameter \B_WIDTH 1
141535     parameter \Y_WIDTH 1
141536     connect \A \cu_st__rel_o
141537     connect \B \$21
141538     connect \Y $and$libresoc.v:50803$1629_Y
141539   end
141540   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141541   cell $and $and$libresoc.v:50812$1638
141542     parameter \A_SIGNED 0
141543     parameter \A_WIDTH 1
141544     parameter \B_SIGNED 0
141545     parameter \B_WIDTH 1
141546     parameter \Y_WIDTH 1
141547     connect \A \$38
141548     connect \B \$40
141549     connect \Y $and$libresoc.v:50812$1638_Y
141550   end
141551   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
141552   cell $and $and$libresoc.v:50813$1639
141553     parameter \A_SIGNED 0
141554     parameter \A_WIDTH 4
141555     parameter \B_SIGNED 0
141556     parameter \B_WIDTH 1
141557     parameter \Y_WIDTH 4
141558     connect \A \state_nia_wen
141559     connect \B 1'1
141560     connect \Y $and$libresoc.v:50813$1639_Y
141561   end
141562   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141563   cell $and $and$libresoc.v:50820$1646
141564     parameter \A_SIGNED 0
141565     parameter \A_WIDTH 1
141566     parameter \B_SIGNED 0
141567     parameter \B_WIDTH 1
141568     parameter \Y_WIDTH 1
141569     connect \A \$63
141570     connect \B \$65
141571     connect \Y $and$libresoc.v:50820$1646_Y
141572   end
141573   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141574   cell $and $and$libresoc.v:50823$1649
141575     parameter \A_SIGNED 0
141576     parameter \A_WIDTH 1
141577     parameter \B_SIGNED 0
141578     parameter \B_WIDTH 1
141579     parameter \Y_WIDTH 1
141580     connect \A \$69
141581     connect \B \$71
141582     connect \Y $and$libresoc.v:50823$1649_Y
141583   end
141584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141585   cell $and $and$libresoc.v:50826$1652
141586     parameter \A_SIGNED 0
141587     parameter \A_WIDTH 1
141588     parameter \B_SIGNED 0
141589     parameter \B_WIDTH 1
141590     parameter \Y_WIDTH 1
141591     connect \A \$75
141592     connect \B \$77
141593     connect \Y $and$libresoc.v:50826$1652_Y
141594   end
141595   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141596   cell $and $and$libresoc.v:50829$1655
141597     parameter \A_SIGNED 0
141598     parameter \A_WIDTH 1
141599     parameter \B_SIGNED 0
141600     parameter \B_WIDTH 1
141601     parameter \Y_WIDTH 1
141602     connect \A \$81
141603     connect \B \$83
141604     connect \Y $and$libresoc.v:50829$1655_Y
141605   end
141606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141607   cell $and $and$libresoc.v:50832$1658
141608     parameter \A_SIGNED 0
141609     parameter \A_WIDTH 1
141610     parameter \B_SIGNED 0
141611     parameter \B_WIDTH 1
141612     parameter \Y_WIDTH 1
141613     connect \A \$87
141614     connect \B \$89
141615     connect \Y $and$libresoc.v:50832$1658_Y
141616   end
141617   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141618   cell $pos $extend$libresoc.v:50794$1618
141619     parameter \A_SIGNED 0
141620     parameter \A_WIDTH 32
141621     parameter \Y_WIDTH 64
141622     connect \A \full_rd2__data_o
141623     connect \Y $extend$libresoc.v:50794$1618_Y
141624   end
141625   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141626   cell $pos $extend$libresoc.v:50795$1620
141627     parameter \A_SIGNED 0
141628     parameter \A_WIDTH 6
141629     parameter \Y_WIDTH 64
141630     connect \A \full_rd__data_o
141631     connect \Y $extend$libresoc.v:50795$1620_Y
141632   end
141633   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
141634   cell $mul $mul$libresoc.v:50789$1613
141635     parameter \A_SIGNED 0
141636     parameter \A_WIDTH 1
141637     parameter \B_SIGNED 0
141638     parameter \B_WIDTH 6
141639     parameter \Y_WIDTH 7
141640     connect \A \dec2_cur_pc [2]
141641     connect \B 6'100000
141642     connect \Y $mul$libresoc.v:50789$1613_Y
141643   end
141644   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
141645   cell $mul $mul$libresoc.v:50791$1615
141646     parameter \A_SIGNED 0
141647     parameter \A_WIDTH 1
141648     parameter \B_SIGNED 0
141649     parameter \B_WIDTH 6
141650     parameter \Y_WIDTH 7
141651     connect \A \dec2_cur_pc [2]
141652     connect \B 6'100000
141653     connect \Y $mul$libresoc.v:50791$1615_Y
141654   end
141655   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174"
141656   cell $ne $ne$libresoc.v:50784$1608
141657     parameter \A_SIGNED 0
141658     parameter \A_WIDTH 2
141659     parameter \B_SIGNED 0
141660     parameter \B_WIDTH 1
141661     parameter \Y_WIDTH 1
141662     connect \A \delay
141663     connect \B 1'0
141664     connect \Y $ne$libresoc.v:50784$1608_Y
141665   end
141666   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307"
141667   cell $ne $ne$libresoc.v:50793$1617
141668     parameter \A_SIGNED 0
141669     parameter \A_WIDTH 7
141670     parameter \B_SIGNED 0
141671     parameter \B_WIDTH 7
141672     parameter \Y_WIDTH 1
141673     connect \A \core_core_insn_type
141674     connect \B 7'0000001
141675     connect \Y $ne$libresoc.v:50793$1617_Y
141676   end
141677   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
141678   cell $ne $ne$libresoc.v:50801$1627
141679     parameter \A_SIGNED 0
141680     parameter \A_WIDTH 2
141681     parameter \B_SIGNED 0
141682     parameter \B_WIDTH 1
141683     parameter \Y_WIDTH 1
141684     connect \A \delay
141685     connect \B \$17
141686     connect \Y $ne$libresoc.v:50801$1627_Y
141687   end
141688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
141689   cell $not $not$libresoc.v:50780$1604
141690     parameter \A_SIGNED 0
141691     parameter \A_WIDTH 1
141692     parameter \Y_WIDTH 1
141693     connect \A \corebusy_o
141694     connect \Y $not$libresoc.v:50780$1604_Y
141695   end
141696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141697   cell $not $not$libresoc.v:50781$1605
141698     parameter \A_SIGNED 0
141699     parameter \A_WIDTH 1
141700     parameter \Y_WIDTH 1
141701     connect \A \dbg_core_stop_o
141702     connect \Y $not$libresoc.v:50781$1605_Y
141703   end
141704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141705   cell $not $not$libresoc.v:50782$1606
141706     parameter \A_SIGNED 0
141707     parameter \A_WIDTH 1
141708     parameter \Y_WIDTH 1
141709     connect \A \core_coresync_rst
141710     connect \Y $not$libresoc.v:50782$1606_Y
141711   end
141712   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141713   cell $not $not$libresoc.v:50785$1609
141714     parameter \A_SIGNED 0
141715     parameter \A_WIDTH 1
141716     parameter \Y_WIDTH 1
141717     connect \A \dbg_core_stop_o
141718     connect \Y $not$libresoc.v:50785$1609_Y
141719   end
141720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141721   cell $not $not$libresoc.v:50786$1610
141722     parameter \A_SIGNED 0
141723     parameter \A_WIDTH 1
141724     parameter \Y_WIDTH 1
141725     connect \A \core_coresync_rst
141726     connect \Y $not$libresoc.v:50786$1610_Y
141727   end
141728   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
141729   cell $not $not$libresoc.v:50788$1612
141730     parameter \A_SIGNED 0
141731     parameter \A_WIDTH 1
141732     parameter \Y_WIDTH 1
141733     connect \A \msr_read
141734     connect \Y $not$libresoc.v:50788$1612_Y
141735   end
141736   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
141737   cell $not $not$libresoc.v:50802$1628
141738     parameter \A_SIGNED 0
141739     parameter \A_WIDTH 1
141740     parameter \Y_WIDTH 1
141741     connect \A \cu_st__rel_o_dly
141742     connect \Y $not$libresoc.v:50802$1628_Y
141743   end
141744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206"
141745   cell $not $not$libresoc.v:50805$1631
141746     parameter \A_SIGNED 0
141747     parameter \A_WIDTH 1
141748     parameter \Y_WIDTH 1
141749     connect \A \pc_i_ok
141750     connect \Y $not$libresoc.v:50805$1631_Y
141751   end
141752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
141753   cell $not $not$libresoc.v:50806$1632
141754     parameter \A_SIGNED 0
141755     parameter \A_WIDTH 1
141756     parameter \Y_WIDTH 1
141757     connect \A \corebusy_o
141758     connect \Y $not$libresoc.v:50806$1632_Y
141759   end
141760   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
141761   cell $not $not$libresoc.v:50807$1633
141762     parameter \A_SIGNED 0
141763     parameter \A_WIDTH 1
141764     parameter \Y_WIDTH 1
141765     connect \A \pc_changed
141766     connect \Y $not$libresoc.v:50807$1633_Y
141767   end
141768   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
141769   cell $not $not$libresoc.v:50808$1634
141770     parameter \A_SIGNED 0
141771     parameter \A_WIDTH 1
141772     parameter \Y_WIDTH 1
141773     connect \A \corebusy_o
141774     connect \Y $not$libresoc.v:50808$1634_Y
141775   end
141776   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
141777   cell $not $not$libresoc.v:50809$1635
141778     parameter \A_SIGNED 0
141779     parameter \A_WIDTH 1
141780     parameter \Y_WIDTH 1
141781     connect \A \pc_changed
141782     connect \Y $not$libresoc.v:50809$1635_Y
141783   end
141784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141785   cell $not $not$libresoc.v:50810$1636
141786     parameter \A_SIGNED 0
141787     parameter \A_WIDTH 1
141788     parameter \Y_WIDTH 1
141789     connect \A \dbg_core_stop_o
141790     connect \Y $not$libresoc.v:50810$1636_Y
141791   end
141792   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141793   cell $not $not$libresoc.v:50811$1637
141794     parameter \A_SIGNED 0
141795     parameter \A_WIDTH 1
141796     parameter \Y_WIDTH 1
141797     connect \A \core_coresync_rst
141798     connect \Y $not$libresoc.v:50811$1637_Y
141799   end
141800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
141801   cell $not $not$libresoc.v:50815$1641
141802     parameter \A_SIGNED 0
141803     parameter \A_WIDTH 1
141804     parameter \Y_WIDTH 1
141805     connect \A \corebusy_o
141806     connect \Y $not$libresoc.v:50815$1641_Y
141807   end
141808   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
141809   cell $not $not$libresoc.v:50816$1642
141810     parameter \A_SIGNED 0
141811     parameter \A_WIDTH 1
141812     parameter \Y_WIDTH 1
141813     connect \A \corebusy_o
141814     connect \Y $not$libresoc.v:50816$1642_Y
141815   end
141816   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
141817   cell $not $not$libresoc.v:50817$1643
141818     parameter \A_SIGNED 0
141819     parameter \A_WIDTH 1
141820     parameter \Y_WIDTH 1
141821     connect \A \corebusy_o
141822     connect \Y $not$libresoc.v:50817$1643_Y
141823   end
141824   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141825   cell $not $not$libresoc.v:50818$1644
141826     parameter \A_SIGNED 0
141827     parameter \A_WIDTH 1
141828     parameter \Y_WIDTH 1
141829     connect \A \dbg_core_stop_o
141830     connect \Y $not$libresoc.v:50818$1644_Y
141831   end
141832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141833   cell $not $not$libresoc.v:50819$1645
141834     parameter \A_SIGNED 0
141835     parameter \A_WIDTH 1
141836     parameter \Y_WIDTH 1
141837     connect \A \core_coresync_rst
141838     connect \Y $not$libresoc.v:50819$1645_Y
141839   end
141840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141841   cell $not $not$libresoc.v:50821$1647
141842     parameter \A_SIGNED 0
141843     parameter \A_WIDTH 1
141844     parameter \Y_WIDTH 1
141845     connect \A \dbg_core_stop_o
141846     connect \Y $not$libresoc.v:50821$1647_Y
141847   end
141848   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141849   cell $not $not$libresoc.v:50822$1648
141850     parameter \A_SIGNED 0
141851     parameter \A_WIDTH 1
141852     parameter \Y_WIDTH 1
141853     connect \A \core_coresync_rst
141854     connect \Y $not$libresoc.v:50822$1648_Y
141855   end
141856   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141857   cell $not $not$libresoc.v:50824$1650
141858     parameter \A_SIGNED 0
141859     parameter \A_WIDTH 1
141860     parameter \Y_WIDTH 1
141861     connect \A \dbg_core_stop_o
141862     connect \Y $not$libresoc.v:50824$1650_Y
141863   end
141864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141865   cell $not $not$libresoc.v:50825$1651
141866     parameter \A_SIGNED 0
141867     parameter \A_WIDTH 1
141868     parameter \Y_WIDTH 1
141869     connect \A \core_coresync_rst
141870     connect \Y $not$libresoc.v:50825$1651_Y
141871   end
141872   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141873   cell $not $not$libresoc.v:50827$1653
141874     parameter \A_SIGNED 0
141875     parameter \A_WIDTH 1
141876     parameter \Y_WIDTH 1
141877     connect \A \dbg_core_stop_o
141878     connect \Y $not$libresoc.v:50827$1653_Y
141879   end
141880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141881   cell $not $not$libresoc.v:50828$1654
141882     parameter \A_SIGNED 0
141883     parameter \A_WIDTH 1
141884     parameter \Y_WIDTH 1
141885     connect \A \core_coresync_rst
141886     connect \Y $not$libresoc.v:50828$1654_Y
141887   end
141888   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141889   cell $not $not$libresoc.v:50830$1656
141890     parameter \A_SIGNED 0
141891     parameter \A_WIDTH 1
141892     parameter \Y_WIDTH 1
141893     connect \A \dbg_core_stop_o
141894     connect \Y $not$libresoc.v:50830$1656_Y
141895   end
141896   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141897   cell $not $not$libresoc.v:50831$1657
141898     parameter \A_SIGNED 0
141899     parameter \A_WIDTH 1
141900     parameter \Y_WIDTH 1
141901     connect \A \core_coresync_rst
141902     connect \Y $not$libresoc.v:50831$1657_Y
141903   end
141904   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
141905   cell $not $not$libresoc.v:50833$1659
141906     parameter \A_SIGNED 0
141907     parameter \A_WIDTH 1
141908     parameter \Y_WIDTH 1
141909     connect \A \msr_read
141910     connect \Y $not$libresoc.v:50833$1659_Y
141911   end
141912   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141913   cell $not $not$libresoc.v:50834$1660
141914     parameter \A_SIGNED 0
141915     parameter \A_WIDTH 1
141916     parameter \Y_WIDTH 1
141917     connect \A \dbg_core_stop_o
141918     connect \Y $not$libresoc.v:50834$1660_Y
141919   end
141920   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
141921   cell $not $not$libresoc.v:50835$1661
141922     parameter \A_SIGNED 0
141923     parameter \A_WIDTH 1
141924     parameter \Y_WIDTH 1
141925     connect \A \core_coresync_rst
141926     connect \Y $not$libresoc.v:50835$1661_Y
141927   end
141928   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
141929   cell $or $or$libresoc.v:50799$1625
141930     parameter \A_SIGNED 0
141931     parameter \A_WIDTH 1
141932     parameter \B_SIGNED 0
141933     parameter \B_WIDTH 1
141934     parameter \Y_WIDTH 1
141935     connect \A 1'0
141936     connect \B \dbg_core_rst_o
141937     connect \Y $or$libresoc.v:50799$1625_Y
141938   end
141939   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
141940   cell $or $or$libresoc.v:50800$1626
141941     parameter \A_SIGNED 0
141942     parameter \A_WIDTH 1
141943     parameter \B_SIGNED 0
141944     parameter \B_WIDTH 1
141945     parameter \Y_WIDTH 1
141946     connect \A \$15
141947     connect \B \rst
141948     connect \Y $or$libresoc.v:50800$1626_Y
141949   end
141950   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141951   cell $pos $pos$libresoc.v:50794$1619
141952     parameter \A_SIGNED 0
141953     parameter \A_WIDTH 64
141954     parameter \Y_WIDTH 64
141955     connect \A $extend$libresoc.v:50794$1618_Y
141956     connect \Y $pos$libresoc.v:50794$1619_Y
141957   end
141958   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
141959   cell $pos $pos$libresoc.v:50795$1621
141960     parameter \A_SIGNED 0
141961     parameter \A_WIDTH 64
141962     parameter \Y_WIDTH 64
141963     connect \A $extend$libresoc.v:50795$1620_Y
141964     connect \Y $pos$libresoc.v:50795$1621_Y
141965   end
141966   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
141967   cell $reduce_or $reduce_or$libresoc.v:50814$1640
141968     parameter \A_SIGNED 0
141969     parameter \A_WIDTH 4
141970     parameter \Y_WIDTH 1
141971     connect \A \$45
141972     connect \Y $reduce_or$libresoc.v:50814$1640_Y
141973   end
141974   attribute \src "libresoc.v:50790.19-50790.42"
141975   cell $shr $shr$libresoc.v:50790$1614
141976     parameter \A_SIGNED 0
141977     parameter \A_WIDTH 64
141978     parameter \B_SIGNED 0
141979     parameter \B_WIDTH 7
141980     parameter \Y_WIDTH 64
141981     connect \A \imem_f_instr_o
141982     connect \B \$118
141983     connect \Y $shr$libresoc.v:50790$1614_Y
141984   end
141985   attribute \src "libresoc.v:50792.19-50792.42"
141986   cell $shr $shr$libresoc.v:50792$1616
141987     parameter \A_SIGNED 0
141988     parameter \A_WIDTH 64
141989     parameter \B_SIGNED 0
141990     parameter \B_WIDTH 7
141991     parameter \Y_WIDTH 64
141992     connect \A \imem_f_instr_o
141993     connect \B \$122
141994     connect \Y $shr$libresoc.v:50792$1616_Y
141995   end
141996   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393"
141997   cell $sub $sub$libresoc.v:50796$1622
141998     parameter \A_SIGNED 0
141999     parameter \A_WIDTH 64
142000     parameter \B_SIGNED 0
142001     parameter \B_WIDTH 1
142002     parameter \Y_WIDTH 65
142003     connect \A \issue__data_o
142004     connect \B 1'1
142005     connect \Y $sub$libresoc.v:50796$1622_Y
142006   end
142007   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175"
142008   cell $sub $sub$libresoc.v:50798$1624
142009     parameter \A_SIGNED 0
142010     parameter \A_WIDTH 2
142011     parameter \B_SIGNED 0
142012     parameter \B_WIDTH 1
142013     parameter \Y_WIDTH 3
142014     connect \A \delay
142015     connect \B 1'1
142016     connect \Y $sub$libresoc.v:50798$1624_Y
142017   end
142018   attribute \module_not_derived 1
142019   attribute \src "libresoc.v:51008.8-51011.4"
142020   cell \core \core
142021     connect \coresync_clk \coresync_clk
142022     connect \coresync_rst \core_coresync_rst
142023   end
142024   attribute \module_not_derived 1
142025   attribute \src "libresoc.v:51012.7-51037.4"
142026   cell \dbg \dbg
142027     connect \clk \clk
142028     connect \core_dbg_msr \dbg_core_dbg_msr
142029     connect \core_dbg_pc \dbg_core_dbg_pc
142030     connect \core_rst_o \dbg_core_rst_o
142031     connect \core_stop_o \dbg_core_stop_o
142032     connect \core_stopped_i \dbg_core_stopped_i
142033     connect \d_cr_ack \dbg_d_cr_ack
142034     connect \d_cr_data \dbg_d_cr_data
142035     connect \d_cr_req \dbg_d_cr_req
142036     connect \d_gpr_ack \dbg_d_gpr_ack
142037     connect \d_gpr_addr \dbg_d_gpr_addr
142038     connect \d_gpr_data \dbg_d_gpr_data
142039     connect \d_gpr_req \dbg_d_gpr_req
142040     connect \d_xer_ack \dbg_d_xer_ack
142041     connect \d_xer_data \dbg_d_xer_data
142042     connect \d_xer_req \dbg_d_xer_req
142043     connect \dmi_ack_o \dbg_dmi_ack_o
142044     connect \dmi_addr_i \dbg_dmi_addr_i
142045     connect \dmi_din \dbg_dmi_din
142046     connect \dmi_dout \dbg_dmi_dout
142047     connect \dmi_req_i \dbg_dmi_req_i
142048     connect \dmi_we_i \dbg_dmi_we_i
142049     connect \rst \rst
142050     connect \terminate_i \dbg_terminate_i
142051   end
142052   attribute \module_not_derived 1
142053   attribute \src "libresoc.v:51038.8-51104.4"
142054   cell \dec2 \dec2
142055     connect \asmcode \dec2_asmcode
142056     connect \bigendian \dec2_bigendian
142057     connect \cia \dec2_cia
142058     connect \cr_in1 \dec2_cr_in1
142059     connect \cr_in1_ok \dec2_cr_in1_ok
142060     connect \cr_in2 \dec2_cr_in2
142061     connect \cr_in2$1 \dec2_cr_in2$1
142062     connect \cr_in2_ok \dec2_cr_in2_ok
142063     connect \cr_in2_ok$2 \dec2_cr_in2_ok$2
142064     connect \cr_out \dec2_cr_out
142065     connect \cr_out_ok \dec2_cr_out_ok
142066     connect \cr_rd \dec2_cr_rd
142067     connect \cr_rd_ok \dec2_cr_rd_ok
142068     connect \cr_wr \dec2_cr_wr
142069     connect \cr_wr_ok \dec2_cr_wr_ok
142070     connect \cur_dec \dec2_cur_dec
142071     connect \cur_eint \dec2_cur_eint
142072     connect \cur_msr \dec2_cur_msr
142073     connect \cur_pc \dec2_cur_pc
142074     connect \ea \dec2_ea
142075     connect \ea_ok \dec2_ea_ok
142076     connect \exc_$signal \dec2_exc_$signal
142077     connect \exc_$signal$3 \dec2_exc_$signal$3
142078     connect \exc_$signal$4 \dec2_exc_$signal$4
142079     connect \exc_$signal$5 \dec2_exc_$signal$5
142080     connect \exc_$signal$6 \dec2_exc_$signal$6
142081     connect \exc_$signal$7 \dec2_exc_$signal$7
142082     connect \exc_$signal$8 \dec2_exc_$signal$8
142083     connect \exc_$signal$9 \dec2_exc_$signal$9
142084     connect \fast1 \dec2_fast1
142085     connect \fast1_ok \dec2_fast1_ok
142086     connect \fast2 \dec2_fast2
142087     connect \fast2_ok \dec2_fast2_ok
142088     connect \fasto1 \dec2_fasto1
142089     connect \fasto1_ok \dec2_fasto1_ok
142090     connect \fasto2 \dec2_fasto2
142091     connect \fasto2_ok \dec2_fasto2_ok
142092     connect \fn_unit \dec2_fn_unit
142093     connect \input_carry \dec2_input_carry
142094     connect \insn \dec2_insn
142095     connect \insn_type \dec2_insn_type
142096     connect \is_32bit \dec2_is_32bit
142097     connect \lk \dec2_lk
142098     connect \msr \dec2_msr
142099     connect \oe \dec2_oe
142100     connect \oe_ok \dec2_oe_ok
142101     connect \raw_opcode_in \dec2_raw_opcode_in
142102     connect \rc \dec2_rc
142103     connect \rc_ok \dec2_rc_ok
142104     connect \reg1 \dec2_reg1
142105     connect \reg1_ok \dec2_reg1_ok
142106     connect \reg2 \dec2_reg2
142107     connect \reg2_ok \dec2_reg2_ok
142108     connect \reg3 \dec2_reg3
142109     connect \reg3_ok \dec2_reg3_ok
142110     connect \rego \dec2_rego
142111     connect \rego_ok \dec2_rego_ok
142112     connect \spr1 \dec2_spr1
142113     connect \spr1_ok \dec2_spr1_ok
142114     connect \spro \dec2_spro
142115     connect \spro_ok \dec2_spro_ok
142116     connect \trapaddr \dec2_trapaddr
142117     connect \traptype \dec2_traptype
142118     connect \xer_in \dec2_xer_in
142119     connect \xer_out \dec2_xer_out
142120   end
142121   attribute \module_not_derived 1
142122   attribute \src "libresoc.v:51105.8-51121.4"
142123   cell \imem \imem
142124     connect \a_pc_i \imem_a_pc_i
142125     connect \a_valid_i \imem_a_valid_i
142126     connect \clk \clk
142127     connect \f_busy_o \imem_f_busy_o
142128     connect \f_instr_o \imem_f_instr_o
142129     connect \f_valid_i \imem_f_valid_i
142130     connect \ibus__ack \ibus__ack
142131     connect \ibus__adr \ibus__adr
142132     connect \ibus__cyc \ibus__cyc
142133     connect \ibus__dat_r \ibus__dat_r
142134     connect \ibus__err \ibus__err
142135     connect \ibus__sel \ibus__sel
142136     connect \ibus__stb \ibus__stb
142137     connect \rst \rst
142138     connect \wb_icache_en \imem_wb_icache_en
142139   end
142140   attribute \module_not_derived 1
142141   attribute \src "libresoc.v:51122.8-51452.4"
142142   cell \jtag \jtag
142143     connect \TAP_bus__tck \TAP_bus__tck
142144     connect \TAP_bus__tdi \TAP_bus__tdi
142145     connect \TAP_bus__tdo \TAP_bus__tdo
142146     connect \TAP_bus__tms \TAP_bus__tms
142147     connect \clk \clk
142148     connect \dmi0__ack_o \jtag_dmi0__ack_o
142149     connect \dmi0__addr_i \jtag_dmi0__addr_i
142150     connect \dmi0__din \jtag_dmi0__din
142151     connect \dmi0__dout \jtag_dmi0__dout
142152     connect \dmi0__req_i \jtag_dmi0__req_i
142153     connect \dmi0__we_i \jtag_dmi0__we_i
142154     connect \eint_0__core__i \eint_0__core__i
142155     connect \eint_0__pad__i \eint_0__pad__i
142156     connect \eint_1__core__i \eint_1__core__i
142157     connect \eint_1__pad__i \eint_1__pad__i
142158     connect \eint_2__core__i \eint_2__core__i
142159     connect \eint_2__pad__i \eint_2__pad__i
142160     connect \gpio_e10__core__i \gpio_e10__core__i
142161     connect \gpio_e10__core__o \gpio_e10__core__o
142162     connect \gpio_e10__core__oe \gpio_e10__core__oe
142163     connect \gpio_e10__pad__i \gpio_e10__pad__i
142164     connect \gpio_e10__pad__o \gpio_e10__pad__o
142165     connect \gpio_e10__pad__oe \gpio_e10__pad__oe
142166     connect \gpio_e11__core__i \gpio_e11__core__i
142167     connect \gpio_e11__core__o \gpio_e11__core__o
142168     connect \gpio_e11__core__oe \gpio_e11__core__oe
142169     connect \gpio_e11__pad__i \gpio_e11__pad__i
142170     connect \gpio_e11__pad__o \gpio_e11__pad__o
142171     connect \gpio_e11__pad__oe \gpio_e11__pad__oe
142172     connect \gpio_e12__core__i \gpio_e12__core__i
142173     connect \gpio_e12__core__o \gpio_e12__core__o
142174     connect \gpio_e12__core__oe \gpio_e12__core__oe
142175     connect \gpio_e12__pad__i \gpio_e12__pad__i
142176     connect \gpio_e12__pad__o \gpio_e12__pad__o
142177     connect \gpio_e12__pad__oe \gpio_e12__pad__oe
142178     connect \gpio_e13__core__i \gpio_e13__core__i
142179     connect \gpio_e13__core__o \gpio_e13__core__o
142180     connect \gpio_e13__core__oe \gpio_e13__core__oe
142181     connect \gpio_e13__pad__i \gpio_e13__pad__i
142182     connect \gpio_e13__pad__o \gpio_e13__pad__o
142183     connect \gpio_e13__pad__oe \gpio_e13__pad__oe
142184     connect \gpio_e14__core__i \gpio_e14__core__i
142185     connect \gpio_e14__core__o \gpio_e14__core__o
142186     connect \gpio_e14__core__oe \gpio_e14__core__oe
142187     connect \gpio_e14__pad__i \gpio_e14__pad__i
142188     connect \gpio_e14__pad__o \gpio_e14__pad__o
142189     connect \gpio_e14__pad__oe \gpio_e14__pad__oe
142190     connect \gpio_e15__core__i \gpio_e15__core__i
142191     connect \gpio_e15__core__o \gpio_e15__core__o
142192     connect \gpio_e15__core__oe \gpio_e15__core__oe
142193     connect \gpio_e15__pad__i \gpio_e15__pad__i
142194     connect \gpio_e15__pad__o \gpio_e15__pad__o
142195     connect \gpio_e15__pad__oe \gpio_e15__pad__oe
142196     connect \gpio_e8__core__i \gpio_e8__core__i
142197     connect \gpio_e8__core__o \gpio_e8__core__o
142198     connect \gpio_e8__core__oe \gpio_e8__core__oe
142199     connect \gpio_e8__pad__i \gpio_e8__pad__i
142200     connect \gpio_e8__pad__o \gpio_e8__pad__o
142201     connect \gpio_e8__pad__oe \gpio_e8__pad__oe
142202     connect \gpio_e9__core__i \gpio_e9__core__i
142203     connect \gpio_e9__core__o \gpio_e9__core__o
142204     connect \gpio_e9__core__oe \gpio_e9__core__oe
142205     connect \gpio_e9__pad__i \gpio_e9__pad__i
142206     connect \gpio_e9__pad__o \gpio_e9__pad__o
142207     connect \gpio_e9__pad__oe \gpio_e9__pad__oe
142208     connect \gpio_s0__core__i \gpio_s0__core__i
142209     connect \gpio_s0__core__o \gpio_s0__core__o
142210     connect \gpio_s0__core__oe \gpio_s0__core__oe
142211     connect \gpio_s0__pad__i \gpio_s0__pad__i
142212     connect \gpio_s0__pad__o \gpio_s0__pad__o
142213     connect \gpio_s0__pad__oe \gpio_s0__pad__oe
142214     connect \gpio_s1__core__i \gpio_s1__core__i
142215     connect \gpio_s1__core__o \gpio_s1__core__o
142216     connect \gpio_s1__core__oe \gpio_s1__core__oe
142217     connect \gpio_s1__pad__i \gpio_s1__pad__i
142218     connect \gpio_s1__pad__o \gpio_s1__pad__o
142219     connect \gpio_s1__pad__oe \gpio_s1__pad__oe
142220     connect \gpio_s2__core__i \gpio_s2__core__i
142221     connect \gpio_s2__core__o \gpio_s2__core__o
142222     connect \gpio_s2__core__oe \gpio_s2__core__oe
142223     connect \gpio_s2__pad__i \gpio_s2__pad__i
142224     connect \gpio_s2__pad__o \gpio_s2__pad__o
142225     connect \gpio_s2__pad__oe \gpio_s2__pad__oe
142226     connect \gpio_s3__core__i \gpio_s3__core__i
142227     connect \gpio_s3__core__o \gpio_s3__core__o
142228     connect \gpio_s3__core__oe \gpio_s3__core__oe
142229     connect \gpio_s3__pad__i \gpio_s3__pad__i
142230     connect \gpio_s3__pad__o \gpio_s3__pad__o
142231     connect \gpio_s3__pad__oe \gpio_s3__pad__oe
142232     connect \gpio_s4__core__i \gpio_s4__core__i
142233     connect \gpio_s4__core__o \gpio_s4__core__o
142234     connect \gpio_s4__core__oe \gpio_s4__core__oe
142235     connect \gpio_s4__pad__i \gpio_s4__pad__i
142236     connect \gpio_s4__pad__o \gpio_s4__pad__o
142237     connect \gpio_s4__pad__oe \gpio_s4__pad__oe
142238     connect \gpio_s5__core__i \gpio_s5__core__i
142239     connect \gpio_s5__core__o \gpio_s5__core__o
142240     connect \gpio_s5__core__oe \gpio_s5__core__oe
142241     connect \gpio_s5__pad__i \gpio_s5__pad__i
142242     connect \gpio_s5__pad__o \gpio_s5__pad__o
142243     connect \gpio_s5__pad__oe \gpio_s5__pad__oe
142244     connect \gpio_s6__core__i \gpio_s6__core__i
142245     connect \gpio_s6__core__o \gpio_s6__core__o
142246     connect \gpio_s6__core__oe \gpio_s6__core__oe
142247     connect \gpio_s6__pad__i \gpio_s6__pad__i
142248     connect \gpio_s6__pad__o \gpio_s6__pad__o
142249     connect \gpio_s6__pad__oe \gpio_s6__pad__oe
142250     connect \gpio_s7__core__i \gpio_s7__core__i
142251     connect \gpio_s7__core__o \gpio_s7__core__o
142252     connect \gpio_s7__core__oe \gpio_s7__core__oe
142253     connect \gpio_s7__pad__i \gpio_s7__pad__i
142254     connect \gpio_s7__pad__o \gpio_s7__pad__o
142255     connect \gpio_s7__pad__oe \gpio_s7__pad__oe
142256     connect \jtag_wb__ack \jtag_wb__ack
142257     connect \jtag_wb__adr \jtag_wb__adr
142258     connect \jtag_wb__cyc \jtag_wb__cyc
142259     connect \jtag_wb__dat_r \jtag_wb__dat_r
142260     connect \jtag_wb__dat_w \jtag_wb__dat_w
142261     connect \jtag_wb__sel \jtag_wb__sel
142262     connect \jtag_wb__stb \jtag_wb__stb
142263     connect \jtag_wb__we \jtag_wb__we
142264     connect \mspi0_clk__core__o \mspi0_clk__core__o
142265     connect \mspi0_clk__pad__o \mspi0_clk__pad__o
142266     connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o
142267     connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o
142268     connect \mspi0_miso__core__i \mspi0_miso__core__i
142269     connect \mspi0_miso__pad__i \mspi0_miso__pad__i
142270     connect \mspi0_mosi__core__o \mspi0_mosi__core__o
142271     connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o
142272     connect \mspi1_clk__core__o \mspi1_clk__core__o
142273     connect \mspi1_clk__pad__o \mspi1_clk__pad__o
142274     connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o
142275     connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o
142276     connect \mspi1_miso__core__i \mspi1_miso__core__i
142277     connect \mspi1_miso__pad__i \mspi1_miso__pad__i
142278     connect \mspi1_mosi__core__o \mspi1_mosi__core__o
142279     connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o
142280     connect \mtwi_scl__core__o \mtwi_scl__core__o
142281     connect \mtwi_scl__pad__o \mtwi_scl__pad__o
142282     connect \mtwi_sda__core__i \mtwi_sda__core__i
142283     connect \mtwi_sda__core__o \mtwi_sda__core__o
142284     connect \mtwi_sda__core__oe \mtwi_sda__core__oe
142285     connect \mtwi_sda__pad__i \mtwi_sda__pad__i
142286     connect \mtwi_sda__pad__o \mtwi_sda__pad__o
142287     connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe
142288     connect \pwm_0__core__o \pwm_0__core__o
142289     connect \pwm_0__pad__o \pwm_0__pad__o
142290     connect \pwm_1__core__o \pwm_1__core__o
142291     connect \pwm_1__pad__o \pwm_1__pad__o
142292     connect \rst \rst
142293     connect \sd0_clk__core__o \sd0_clk__core__o
142294     connect \sd0_clk__pad__o \sd0_clk__pad__o
142295     connect \sd0_cmd__core__i \sd0_cmd__core__i
142296     connect \sd0_cmd__core__o \sd0_cmd__core__o
142297     connect \sd0_cmd__core__oe \sd0_cmd__core__oe
142298     connect \sd0_cmd__pad__i \sd0_cmd__pad__i
142299     connect \sd0_cmd__pad__o \sd0_cmd__pad__o
142300     connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe
142301     connect \sd0_data0__core__i \sd0_data0__core__i
142302     connect \sd0_data0__core__o \sd0_data0__core__o
142303     connect \sd0_data0__core__oe \sd0_data0__core__oe
142304     connect \sd0_data0__pad__i \sd0_data0__pad__i
142305     connect \sd0_data0__pad__o \sd0_data0__pad__o
142306     connect \sd0_data0__pad__oe \sd0_data0__pad__oe
142307     connect \sd0_data1__core__i \sd0_data1__core__i
142308     connect \sd0_data1__core__o \sd0_data1__core__o
142309     connect \sd0_data1__core__oe \sd0_data1__core__oe
142310     connect \sd0_data1__pad__i \sd0_data1__pad__i
142311     connect \sd0_data1__pad__o \sd0_data1__pad__o
142312     connect \sd0_data1__pad__oe \sd0_data1__pad__oe
142313     connect \sd0_data2__core__i \sd0_data2__core__i
142314     connect \sd0_data2__core__o \sd0_data2__core__o
142315     connect \sd0_data2__core__oe \sd0_data2__core__oe
142316     connect \sd0_data2__pad__i \sd0_data2__pad__i
142317     connect \sd0_data2__pad__o \sd0_data2__pad__o
142318     connect \sd0_data2__pad__oe \sd0_data2__pad__oe
142319     connect \sd0_data3__core__i \sd0_data3__core__i
142320     connect \sd0_data3__core__o \sd0_data3__core__o
142321     connect \sd0_data3__core__oe \sd0_data3__core__oe
142322     connect \sd0_data3__pad__i \sd0_data3__pad__i
142323     connect \sd0_data3__pad__o \sd0_data3__pad__o
142324     connect \sd0_data3__pad__oe \sd0_data3__pad__oe
142325     connect \sdr_a_0__core__o \sdr_a_0__core__o
142326     connect \sdr_a_0__pad__o \sdr_a_0__pad__o
142327     connect \sdr_a_10__core__o \sdr_a_10__core__o
142328     connect \sdr_a_10__pad__o \sdr_a_10__pad__o
142329     connect \sdr_a_11__core__o \sdr_a_11__core__o
142330     connect \sdr_a_11__pad__o \sdr_a_11__pad__o
142331     connect \sdr_a_12__core__o \sdr_a_12__core__o
142332     connect \sdr_a_12__pad__o \sdr_a_12__pad__o
142333     connect \sdr_a_1__core__o \sdr_a_1__core__o
142334     connect \sdr_a_1__pad__o \sdr_a_1__pad__o
142335     connect \sdr_a_2__core__o \sdr_a_2__core__o
142336     connect \sdr_a_2__pad__o \sdr_a_2__pad__o
142337     connect \sdr_a_3__core__o \sdr_a_3__core__o
142338     connect \sdr_a_3__pad__o \sdr_a_3__pad__o
142339     connect \sdr_a_4__core__o \sdr_a_4__core__o
142340     connect \sdr_a_4__pad__o \sdr_a_4__pad__o
142341     connect \sdr_a_5__core__o \sdr_a_5__core__o
142342     connect \sdr_a_5__pad__o \sdr_a_5__pad__o
142343     connect \sdr_a_6__core__o \sdr_a_6__core__o
142344     connect \sdr_a_6__pad__o \sdr_a_6__pad__o
142345     connect \sdr_a_7__core__o \sdr_a_7__core__o
142346     connect \sdr_a_7__pad__o \sdr_a_7__pad__o
142347     connect \sdr_a_8__core__o \sdr_a_8__core__o
142348     connect \sdr_a_8__pad__o \sdr_a_8__pad__o
142349     connect \sdr_a_9__core__o \sdr_a_9__core__o
142350     connect \sdr_a_9__pad__o \sdr_a_9__pad__o
142351     connect \sdr_ba_0__core__o \sdr_ba_0__core__o
142352     connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o
142353     connect \sdr_ba_1__core__o \sdr_ba_1__core__o
142354     connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o
142355     connect \sdr_cas_n__core__o \sdr_cas_n__core__o
142356     connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o
142357     connect \sdr_cke__core__o \sdr_cke__core__o
142358     connect \sdr_cke__pad__o \sdr_cke__pad__o
142359     connect \sdr_clock__core__o \sdr_clock__core__o
142360     connect \sdr_clock__pad__o \sdr_clock__pad__o
142361     connect \sdr_cs_n__core__o \sdr_cs_n__core__o
142362     connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o
142363     connect \sdr_dm_0__core__o \sdr_dm_0__core__o
142364     connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o
142365     connect \sdr_dm_1__core__i \sdr_dm_1__core__i
142366     connect \sdr_dm_1__core__o \sdr_dm_1__core__o
142367     connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe
142368     connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i
142369     connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o
142370     connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe
142371     connect \sdr_dq_0__core__i \sdr_dq_0__core__i
142372     connect \sdr_dq_0__core__o \sdr_dq_0__core__o
142373     connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe
142374     connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i
142375     connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o
142376     connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe
142377     connect \sdr_dq_10__core__i \sdr_dq_10__core__i
142378     connect \sdr_dq_10__core__o \sdr_dq_10__core__o
142379     connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe
142380     connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i
142381     connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o
142382     connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe
142383     connect \sdr_dq_11__core__i \sdr_dq_11__core__i
142384     connect \sdr_dq_11__core__o \sdr_dq_11__core__o
142385     connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe
142386     connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i
142387     connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o
142388     connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe
142389     connect \sdr_dq_12__core__i \sdr_dq_12__core__i
142390     connect \sdr_dq_12__core__o \sdr_dq_12__core__o
142391     connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe
142392     connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i
142393     connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o
142394     connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe
142395     connect \sdr_dq_13__core__i \sdr_dq_13__core__i
142396     connect \sdr_dq_13__core__o \sdr_dq_13__core__o
142397     connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe
142398     connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i
142399     connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o
142400     connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe
142401     connect \sdr_dq_14__core__i \sdr_dq_14__core__i
142402     connect \sdr_dq_14__core__o \sdr_dq_14__core__o
142403     connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe
142404     connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i
142405     connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o
142406     connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe
142407     connect \sdr_dq_15__core__i \sdr_dq_15__core__i
142408     connect \sdr_dq_15__core__o \sdr_dq_15__core__o
142409     connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe
142410     connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i
142411     connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o
142412     connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe
142413     connect \sdr_dq_1__core__i \sdr_dq_1__core__i
142414     connect \sdr_dq_1__core__o \sdr_dq_1__core__o
142415     connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe
142416     connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i
142417     connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o
142418     connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe
142419     connect \sdr_dq_2__core__i \sdr_dq_2__core__i
142420     connect \sdr_dq_2__core__o \sdr_dq_2__core__o
142421     connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe
142422     connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i
142423     connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o
142424     connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe
142425     connect \sdr_dq_3__core__i \sdr_dq_3__core__i
142426     connect \sdr_dq_3__core__o \sdr_dq_3__core__o
142427     connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe
142428     connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i
142429     connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o
142430     connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe
142431     connect \sdr_dq_4__core__i \sdr_dq_4__core__i
142432     connect \sdr_dq_4__core__o \sdr_dq_4__core__o
142433     connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe
142434     connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i
142435     connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o
142436     connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe
142437     connect \sdr_dq_5__core__i \sdr_dq_5__core__i
142438     connect \sdr_dq_5__core__o \sdr_dq_5__core__o
142439     connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe
142440     connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i
142441     connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o
142442     connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe
142443     connect \sdr_dq_6__core__i \sdr_dq_6__core__i
142444     connect \sdr_dq_6__core__o \sdr_dq_6__core__o
142445     connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe
142446     connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i
142447     connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o
142448     connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe
142449     connect \sdr_dq_7__core__i \sdr_dq_7__core__i
142450     connect \sdr_dq_7__core__o \sdr_dq_7__core__o
142451     connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe
142452     connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i
142453     connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o
142454     connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe
142455     connect \sdr_dq_8__core__i \sdr_dq_8__core__i
142456     connect \sdr_dq_8__core__o \sdr_dq_8__core__o
142457     connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe
142458     connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i
142459     connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o
142460     connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe
142461     connect \sdr_dq_9__core__i \sdr_dq_9__core__i
142462     connect \sdr_dq_9__core__o \sdr_dq_9__core__o
142463     connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe
142464     connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i
142465     connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o
142466     connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe
142467     connect \sdr_ras_n__core__o \sdr_ras_n__core__o
142468     connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o
142469     connect \sdr_we_n__core__o \sdr_we_n__core__o
142470     connect \sdr_we_n__pad__o \sdr_we_n__pad__o
142471     connect \wb_icache_en \imem_wb_icache_en
142472   end
142473   attribute \module_not_derived 1
142474   attribute \src "libresoc.v:51453.12-51467.4"
142475   cell \xics_icp \xics_icp
142476     connect \clk \clk
142477     connect \core_irq_o \xics_icp_core_irq_o
142478     connect \icp_wb__ack \icp_wb__ack
142479     connect \icp_wb__adr \icp_wb__adr
142480     connect \icp_wb__cyc \icp_wb__cyc
142481     connect \icp_wb__dat_r \icp_wb__dat_r
142482     connect \icp_wb__dat_w \icp_wb__dat_w
142483     connect \icp_wb__sel \icp_wb__sel
142484     connect \icp_wb__stb \icp_wb__stb
142485     connect \icp_wb__we \icp_wb__we
142486     connect \ics_i_pri \xics_icp_ics_i_pri
142487     connect \ics_i_src \xics_icp_ics_i_src
142488     connect \rst \rst
142489   end
142490   attribute \module_not_derived 1
142491   attribute \src "libresoc.v:51468.12-51481.4"
142492   cell \xics_ics \xics_ics
142493     connect \clk \clk
142494     connect \icp_o_pri \xics_ics_icp_o_pri
142495     connect \icp_o_src \xics_ics_icp_o_src
142496     connect \ics_wb__ack \ics_wb__ack
142497     connect \ics_wb__adr \ics_wb__adr
142498     connect \ics_wb__cyc \ics_wb__cyc
142499     connect \ics_wb__dat_r \ics_wb__dat_r
142500     connect \ics_wb__dat_w \ics_wb__dat_w
142501     connect \ics_wb__stb \ics_wb__stb
142502     connect \ics_wb__we \ics_wb__we
142503     connect \int_level_i \int_level_i
142504     connect \rst \rst
142505   end
142506   attribute \src "libresoc.v:48722.7-48722.20"
142507   process $proc$libresoc.v:48722$2161
142508     assign { } { }
142509     assign $0\initial[0:0] 1'0
142510     sync always
142511       update \initial $0\initial[0:0]
142512     sync init
142513   end
142514   attribute \src "libresoc.v:48854.7-48854.25"
142515   process $proc$libresoc.v:48854$2162
142516     assign { } { }
142517     assign $1\bigendian_i[0:0] 1'0
142518     sync always
142519     sync init
142520       update \bigendian_i $1\bigendian_i[0:0]
142521   end
142522   attribute \src "libresoc.v:48866.13-48866.33"
142523   process $proc$libresoc.v:48866$2163
142524     assign { } { }
142525     assign $1\core_asmcode[7:0] 8'00000000
142526     sync always
142527     sync init
142528       update \core_asmcode $1\core_asmcode[7:0]
142529   end
142530   attribute \src "libresoc.v:48872.14-48872.50"
142531   process $proc$libresoc.v:48872$2164
142532     assign { } { }
142533     assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
142534     sync always
142535     sync init
142536       update \core_core_cia $1\core_core_cia[63:0]
142537   end
142538   attribute \src "libresoc.v:48876.13-48876.36"
142539   process $proc$libresoc.v:48876$2165
142540     assign { } { }
142541     assign $1\core_core_cr_rd[7:0] 8'00000000
142542     sync always
142543     sync init
142544       update \core_core_cr_rd $1\core_core_cr_rd[7:0]
142545   end
142546   attribute \src "libresoc.v:48880.7-48880.32"
142547   process $proc$libresoc.v:48880$2166
142548     assign { } { }
142549     assign $1\core_core_cr_rd_ok[0:0] 1'0
142550     sync always
142551     sync init
142552       update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0]
142553   end
142554   attribute \src "libresoc.v:48884.13-48884.36"
142555   process $proc$libresoc.v:48884$2167
142556     assign { } { }
142557     assign $1\core_core_cr_wr[7:0] 8'00000000
142558     sync always
142559     sync init
142560       update \core_core_cr_wr $1\core_core_cr_wr[7:0]
142561   end
142562   attribute \src "libresoc.v:48888.7-48888.32"
142563   process $proc$libresoc.v:48888$2168
142564     assign { } { }
142565     assign $1\core_core_cr_wr_ok[0:0] 1'0
142566     sync always
142567     sync init
142568       update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
142569   end
142570   attribute \src "libresoc.v:48892.7-48892.37"
142571   process $proc$libresoc.v:48892$2169
142572     assign { } { }
142573     assign $0\core_core_exc_$signal[0:0]$2170 1'0
142574     sync always
142575     sync init
142576       update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$2170
142577   end
142578   attribute \src "libresoc.v:48894.7-48894.40"
142579   process $proc$libresoc.v:48894$2171
142580     assign { } { }
142581     assign $0\core_core_exc_$signal$50[0:0]$2172 1'0
142582     sync always
142583     sync init
142584       update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$2172
142585   end
142586   attribute \src "libresoc.v:48898.7-48898.40"
142587   process $proc$libresoc.v:48898$2173
142588     assign { } { }
142589     assign $0\core_core_exc_$signal$51[0:0]$2174 1'0
142590     sync always
142591     sync init
142592       update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$2174
142593   end
142594   attribute \src "libresoc.v:48902.7-48902.40"
142595   process $proc$libresoc.v:48902$2175
142596     assign { } { }
142597     assign $0\core_core_exc_$signal$52[0:0]$2176 1'0
142598     sync always
142599     sync init
142600       update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$2176
142601   end
142602   attribute \src "libresoc.v:48906.7-48906.40"
142603   process $proc$libresoc.v:48906$2177
142604     assign { } { }
142605     assign $0\core_core_exc_$signal$53[0:0]$2178 1'0
142606     sync always
142607     sync init
142608       update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$2178
142609   end
142610   attribute \src "libresoc.v:48910.7-48910.40"
142611   process $proc$libresoc.v:48910$2179
142612     assign { } { }
142613     assign $0\core_core_exc_$signal$54[0:0]$2180 1'0
142614     sync always
142615     sync init
142616       update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$2180
142617   end
142618   attribute \src "libresoc.v:48914.7-48914.40"
142619   process $proc$libresoc.v:48914$2181
142620     assign { } { }
142621     assign $0\core_core_exc_$signal$55[0:0]$2182 1'0
142622     sync always
142623     sync init
142624       update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$2182
142625   end
142626   attribute \src "libresoc.v:48918.7-48918.40"
142627   process $proc$libresoc.v:48918$2183
142628     assign { } { }
142629     assign $0\core_core_exc_$signal$56[0:0]$2184 1'0
142630     sync always
142631     sync init
142632       update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$2184
142633   end
142634   attribute \src "libresoc.v:48937.14-48937.41"
142635   process $proc$libresoc.v:48937$2185
142636     assign { } { }
142637     assign $1\core_core_fn_unit[11:0] 12'000000000000
142638     sync always
142639     sync init
142640       update \core_core_fn_unit $1\core_core_fn_unit[11:0]
142641   end
142642   attribute \src "libresoc.v:48945.13-48945.41"
142643   process $proc$libresoc.v:48945$2186
142644     assign { } { }
142645     assign $1\core_core_input_carry[1:0] 2'00
142646     sync always
142647     sync init
142648       update \core_core_input_carry $1\core_core_input_carry[1:0]
142649   end
142650   attribute \src "libresoc.v:48949.14-48949.36"
142651   process $proc$libresoc.v:48949$2187
142652     assign { } { }
142653     assign $1\core_core_insn[31:0] 0
142654     sync always
142655     sync init
142656       update \core_core_insn $1\core_core_insn[31:0]
142657   end
142658   attribute \src "libresoc.v:49027.13-49027.40"
142659   process $proc$libresoc.v:49027$2188
142660     assign { } { }
142661     assign $1\core_core_insn_type[6:0] 7'0000000
142662     sync always
142663     sync init
142664       update \core_core_insn_type $1\core_core_insn_type[6:0]
142665   end
142666   attribute \src "libresoc.v:49031.7-49031.32"
142667   process $proc$libresoc.v:49031$2189
142668     assign { } { }
142669     assign $1\core_core_is_32bit[0:0] 1'0
142670     sync always
142671     sync init
142672       update \core_core_is_32bit $1\core_core_is_32bit[0:0]
142673   end
142674   attribute \src "libresoc.v:49035.7-49035.26"
142675   process $proc$libresoc.v:49035$2190
142676     assign { } { }
142677     assign $1\core_core_lk[0:0] 1'0
142678     sync always
142679     sync init
142680       update \core_core_lk $1\core_core_lk[0:0]
142681   end
142682   attribute \src "libresoc.v:49039.14-49039.50"
142683   process $proc$libresoc.v:49039$2191
142684     assign { } { }
142685     assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
142686     sync always
142687     sync init
142688       update \core_core_msr $1\core_core_msr[63:0]
142689   end
142690   attribute \src "libresoc.v:49043.7-49043.26"
142691   process $proc$libresoc.v:49043$2192
142692     assign { } { }
142693     assign $1\core_core_oe[0:0] 1'0
142694     sync always
142695     sync init
142696       update \core_core_oe $1\core_core_oe[0:0]
142697   end
142698   attribute \src "libresoc.v:49047.7-49047.29"
142699   process $proc$libresoc.v:49047$2193
142700     assign { } { }
142701     assign $1\core_core_oe_ok[0:0] 1'0
142702     sync always
142703     sync init
142704       update \core_core_oe_ok $1\core_core_oe_ok[0:0]
142705   end
142706   attribute \src "libresoc.v:49051.7-49051.26"
142707   process $proc$libresoc.v:49051$2194
142708     assign { } { }
142709     assign $1\core_core_rc[0:0] 1'0
142710     sync always
142711     sync init
142712       update \core_core_rc $1\core_core_rc[0:0]
142713   end
142714   attribute \src "libresoc.v:49055.7-49055.29"
142715   process $proc$libresoc.v:49055$2195
142716     assign { } { }
142717     assign $1\core_core_rc_ok[0:0] 1'0
142718     sync always
142719     sync init
142720       update \core_core_rc_ok $1\core_core_rc_ok[0:0]
142721   end
142722   attribute \src "libresoc.v:49059.14-49059.43"
142723   process $proc$libresoc.v:49059$2196
142724     assign { } { }
142725     assign $1\core_core_trapaddr[12:0] 13'0000000000000
142726     sync always
142727     sync init
142728       update \core_core_trapaddr $1\core_core_trapaddr[12:0]
142729   end
142730   attribute \src "libresoc.v:49063.13-49063.39"
142731   process $proc$libresoc.v:49063$2197
142732     assign { } { }
142733     assign $1\core_core_traptype[7:0] 8'00000000
142734     sync always
142735     sync init
142736       update \core_core_traptype $1\core_core_traptype[7:0]
142737   end
142738   attribute \src "libresoc.v:49069.13-49069.31"
142739   process $proc$libresoc.v:49069$2198
142740     assign { } { }
142741     assign $1\core_cr_in1[2:0] 3'000
142742     sync always
142743     sync init
142744       update \core_cr_in1 $1\core_cr_in1[2:0]
142745   end
142746   attribute \src "libresoc.v:49073.7-49073.28"
142747   process $proc$libresoc.v:49073$2199
142748     assign { } { }
142749     assign $1\core_cr_in1_ok[0:0] 1'0
142750     sync always
142751     sync init
142752       update \core_cr_in1_ok $1\core_cr_in1_ok[0:0]
142753   end
142754   attribute \src "libresoc.v:49077.13-49077.31"
142755   process $proc$libresoc.v:49077$2200
142756     assign { } { }
142757     assign $1\core_cr_in2[2:0] 3'000
142758     sync always
142759     sync init
142760       update \core_cr_in2 $1\core_cr_in2[2:0]
142761   end
142762   attribute \src "libresoc.v:49079.13-49079.36"
142763   process $proc$libresoc.v:49079$2201
142764     assign { } { }
142765     assign $0\core_cr_in2$48[2:0]$2202 3'000
142766     sync always
142767     sync init
142768       update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$2202
142769   end
142770   attribute \src "libresoc.v:49085.7-49085.28"
142771   process $proc$libresoc.v:49085$2203
142772     assign { } { }
142773     assign $1\core_cr_in2_ok[0:0] 1'0
142774     sync always
142775     sync init
142776       update \core_cr_in2_ok $1\core_cr_in2_ok[0:0]
142777   end
142778   attribute \src "libresoc.v:49087.7-49087.33"
142779   process $proc$libresoc.v:49087$2204
142780     assign { } { }
142781     assign $0\core_cr_in2_ok$49[0:0]$2205 1'0
142782     sync always
142783     sync init
142784       update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$2205
142785   end
142786   attribute \src "libresoc.v:49093.13-49093.31"
142787   process $proc$libresoc.v:49093$2206
142788     assign { } { }
142789     assign $1\core_cr_out[2:0] 3'000
142790     sync always
142791     sync init
142792       update \core_cr_out $1\core_cr_out[2:0]
142793   end
142794   attribute \src "libresoc.v:49097.7-49097.28"
142795   process $proc$libresoc.v:49097$2207
142796     assign { } { }
142797     assign $1\core_cr_out_ok[0:0] 1'0
142798     sync always
142799     sync init
142800       update \core_cr_out_ok $1\core_cr_out_ok[0:0]
142801   end
142802   attribute \src "libresoc.v:49101.14-49101.45"
142803   process $proc$libresoc.v:49101$2208
142804     assign { } { }
142805     assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
142806     sync always
142807     sync init
142808       update \core_dec $1\core_dec[63:0]
142809   end
142810   attribute \src "libresoc.v:49105.13-49105.28"
142811   process $proc$libresoc.v:49105$2209
142812     assign { } { }
142813     assign $1\core_ea[4:0] 5'00000
142814     sync always
142815     sync init
142816       update \core_ea $1\core_ea[4:0]
142817   end
142818   attribute \src "libresoc.v:49109.7-49109.24"
142819   process $proc$libresoc.v:49109$2210
142820     assign { } { }
142821     assign $1\core_ea_ok[0:0] 1'0
142822     sync always
142823     sync init
142824       update \core_ea_ok $1\core_ea_ok[0:0]
142825   end
142826   attribute \src "libresoc.v:49113.7-49113.23"
142827   process $proc$libresoc.v:49113$2211
142828     assign { } { }
142829     assign $1\core_eint[0:0] 1'0
142830     sync always
142831     sync init
142832       update \core_eint $1\core_eint[0:0]
142833   end
142834   attribute \src "libresoc.v:49117.13-49117.30"
142835   process $proc$libresoc.v:49117$2212
142836     assign { } { }
142837     assign $1\core_fast1[2:0] 3'000
142838     sync always
142839     sync init
142840       update \core_fast1 $1\core_fast1[2:0]
142841   end
142842   attribute \src "libresoc.v:49121.7-49121.27"
142843   process $proc$libresoc.v:49121$2213
142844     assign { } { }
142845     assign $1\core_fast1_ok[0:0] 1'0
142846     sync always
142847     sync init
142848       update \core_fast1_ok $1\core_fast1_ok[0:0]
142849   end
142850   attribute \src "libresoc.v:49125.13-49125.30"
142851   process $proc$libresoc.v:49125$2214
142852     assign { } { }
142853     assign $1\core_fast2[2:0] 3'000
142854     sync always
142855     sync init
142856       update \core_fast2 $1\core_fast2[2:0]
142857   end
142858   attribute \src "libresoc.v:49129.7-49129.27"
142859   process $proc$libresoc.v:49129$2215
142860     assign { } { }
142861     assign $1\core_fast2_ok[0:0] 1'0
142862     sync always
142863     sync init
142864       update \core_fast2_ok $1\core_fast2_ok[0:0]
142865   end
142866   attribute \src "libresoc.v:49133.13-49133.31"
142867   process $proc$libresoc.v:49133$2216
142868     assign { } { }
142869     assign $1\core_fasto1[2:0] 3'000
142870     sync always
142871     sync init
142872       update \core_fasto1 $1\core_fasto1[2:0]
142873   end
142874   attribute \src "libresoc.v:49137.7-49137.28"
142875   process $proc$libresoc.v:49137$2217
142876     assign { } { }
142877     assign $1\core_fasto1_ok[0:0] 1'0
142878     sync always
142879     sync init
142880       update \core_fasto1_ok $1\core_fasto1_ok[0:0]
142881   end
142882   attribute \src "libresoc.v:49141.13-49141.31"
142883   process $proc$libresoc.v:49141$2218
142884     assign { } { }
142885     assign $1\core_fasto2[2:0] 3'000
142886     sync always
142887     sync init
142888       update \core_fasto2 $1\core_fasto2[2:0]
142889   end
142890   attribute \src "libresoc.v:49145.7-49145.28"
142891   process $proc$libresoc.v:49145$2219
142892     assign { } { }
142893     assign $1\core_fasto2_ok[0:0] 1'0
142894     sync always
142895     sync init
142896       update \core_fasto2_ok $1\core_fasto2_ok[0:0]
142897   end
142898   attribute \src "libresoc.v:49149.14-49149.45"
142899   process $proc$libresoc.v:49149$2220
142900     assign { } { }
142901     assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
142902     sync always
142903     sync init
142904       update \core_msr $1\core_msr[63:0]
142905   end
142906   attribute \src "libresoc.v:49153.14-49153.44"
142907   process $proc$libresoc.v:49153$2221
142908     assign { } { }
142909     assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
142910     sync always
142911     sync init
142912       update \core_pc $1\core_pc[63:0]
142913   end
142914   attribute \src "libresoc.v:49157.13-49157.30"
142915   process $proc$libresoc.v:49157$2222
142916     assign { } { }
142917     assign $1\core_reg1[4:0] 5'00000
142918     sync always
142919     sync init
142920       update \core_reg1 $1\core_reg1[4:0]
142921   end
142922   attribute \src "libresoc.v:49161.7-49161.26"
142923   process $proc$libresoc.v:49161$2223
142924     assign { } { }
142925     assign $1\core_reg1_ok[0:0] 1'0
142926     sync always
142927     sync init
142928       update \core_reg1_ok $1\core_reg1_ok[0:0]
142929   end
142930   attribute \src "libresoc.v:49165.13-49165.30"
142931   process $proc$libresoc.v:49165$2224
142932     assign { } { }
142933     assign $1\core_reg2[4:0] 5'00000
142934     sync always
142935     sync init
142936       update \core_reg2 $1\core_reg2[4:0]
142937   end
142938   attribute \src "libresoc.v:49169.7-49169.26"
142939   process $proc$libresoc.v:49169$2225
142940     assign { } { }
142941     assign $1\core_reg2_ok[0:0] 1'0
142942     sync always
142943     sync init
142944       update \core_reg2_ok $1\core_reg2_ok[0:0]
142945   end
142946   attribute \src "libresoc.v:49173.13-49173.30"
142947   process $proc$libresoc.v:49173$2226
142948     assign { } { }
142949     assign $1\core_reg3[4:0] 5'00000
142950     sync always
142951     sync init
142952       update \core_reg3 $1\core_reg3[4:0]
142953   end
142954   attribute \src "libresoc.v:49177.7-49177.26"
142955   process $proc$libresoc.v:49177$2227
142956     assign { } { }
142957     assign $1\core_reg3_ok[0:0] 1'0
142958     sync always
142959     sync init
142960       update \core_reg3_ok $1\core_reg3_ok[0:0]
142961   end
142962   attribute \src "libresoc.v:49181.13-49181.30"
142963   process $proc$libresoc.v:49181$2228
142964     assign { } { }
142965     assign $1\core_rego[4:0] 5'00000
142966     sync always
142967     sync init
142968       update \core_rego $1\core_rego[4:0]
142969   end
142970   attribute \src "libresoc.v:49185.7-49185.26"
142971   process $proc$libresoc.v:49185$2229
142972     assign { } { }
142973     assign $1\core_rego_ok[0:0] 1'0
142974     sync always
142975     sync init
142976       update \core_rego_ok $1\core_rego_ok[0:0]
142977   end
142978   attribute \src "libresoc.v:49300.13-49300.32"
142979   process $proc$libresoc.v:49300$2230
142980     assign { } { }
142981     assign $1\core_spr1[9:0] 10'0000000000
142982     sync always
142983     sync init
142984       update \core_spr1 $1\core_spr1[9:0]
142985   end
142986   attribute \src "libresoc.v:49304.7-49304.26"
142987   process $proc$libresoc.v:49304$2231
142988     assign { } { }
142989     assign $1\core_spr1_ok[0:0] 1'0
142990     sync always
142991     sync init
142992       update \core_spr1_ok $1\core_spr1_ok[0:0]
142993   end
142994   attribute \src "libresoc.v:49419.13-49419.32"
142995   process $proc$libresoc.v:49419$2232
142996     assign { } { }
142997     assign $1\core_spro[9:0] 10'0000000000
142998     sync always
142999     sync init
143000       update \core_spro $1\core_spro[9:0]
143001   end
143002   attribute \src "libresoc.v:49423.7-49423.26"
143003   process $proc$libresoc.v:49423$2233
143004     assign { } { }
143005     assign $1\core_spro_ok[0:0] 1'0
143006     sync always
143007     sync init
143008       update \core_spro_ok $1\core_spro_ok[0:0]
143009   end
143010   attribute \src "libresoc.v:49431.13-49431.31"
143011   process $proc$libresoc.v:49431$2234
143012     assign { } { }
143013     assign $1\core_xer_in[2:0] 3'000
143014     sync always
143015     sync init
143016       update \core_xer_in $1\core_xer_in[2:0]
143017   end
143018   attribute \src "libresoc.v:49435.7-49435.26"
143019   process $proc$libresoc.v:49435$2235
143020     assign { } { }
143021     assign $1\core_xer_out[0:0] 1'0
143022     sync always
143023     sync init
143024       update \core_xer_out $1\core_xer_out[0:0]
143025   end
143026   attribute \src "libresoc.v:49451.7-49451.30"
143027   process $proc$libresoc.v:49451$2236
143028     assign { } { }
143029     assign $1\cu_st__rel_o_dly[0:0] 1'0
143030     sync always
143031     sync init
143032       update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
143033   end
143034   attribute \src "libresoc.v:49457.7-49457.24"
143035   process $proc$libresoc.v:49457$2237
143036     assign { } { }
143037     assign $1\d_cr_delay[0:0] 1'0
143038     sync always
143039     sync init
143040       update \d_cr_delay $1\d_cr_delay[0:0]
143041   end
143042   attribute \src "libresoc.v:49461.7-49461.25"
143043   process $proc$libresoc.v:49461$2238
143044     assign { } { }
143045     assign $1\d_reg_delay[0:0] 1'0
143046     sync always
143047     sync init
143048       update \d_reg_delay $1\d_reg_delay[0:0]
143049   end
143050   attribute \src "libresoc.v:49465.7-49465.25"
143051   process $proc$libresoc.v:49465$2239
143052     assign { } { }
143053     assign $1\d_xer_delay[0:0] 1'0
143054     sync always
143055     sync init
143056       update \d_xer_delay $1\d_xer_delay[0:0]
143057   end
143058   attribute \src "libresoc.v:49503.13-49503.34"
143059   process $proc$libresoc.v:49503$2240
143060     assign { } { }
143061     assign $1\dbg_dmi_addr_i[3:0] 4'0000
143062     sync always
143063     sync init
143064       update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
143065   end
143066   attribute \src "libresoc.v:49507.14-49507.48"
143067   process $proc$libresoc.v:49507$2241
143068     assign { } { }
143069     assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
143070     sync always
143071     sync init
143072       update \dbg_dmi_din $1\dbg_dmi_din[63:0]
143073   end
143074   attribute \src "libresoc.v:49513.7-49513.27"
143075   process $proc$libresoc.v:49513$2242
143076     assign { } { }
143077     assign $1\dbg_dmi_req_i[0:0] 1'0
143078     sync always
143079     sync init
143080       update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
143081   end
143082   attribute \src "libresoc.v:49517.7-49517.26"
143083   process $proc$libresoc.v:49517$2243
143084     assign { } { }
143085     assign $1\dbg_dmi_we_i[0:0] 1'0
143086     sync always
143087     sync init
143088       update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
143089   end
143090   attribute \src "libresoc.v:49553.14-49553.49"
143091   process $proc$libresoc.v:49553$2244
143092     assign { } { }
143093     assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
143094     sync always
143095     sync init
143096       update \dec2_cur_dec $1\dec2_cur_dec[63:0]
143097   end
143098   attribute \src "libresoc.v:49557.7-49557.27"
143099   process $proc$libresoc.v:49557$2245
143100     assign { } { }
143101     assign $1\dec2_cur_eint[0:0] 1'0
143102     sync always
143103     sync init
143104       update \dec2_cur_eint $1\dec2_cur_eint[0:0]
143105   end
143106   attribute \src "libresoc.v:49561.14-49561.49"
143107   process $proc$libresoc.v:49561$2246
143108     assign { } { }
143109     assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
143110     sync always
143111     sync init
143112       update \dec2_cur_msr $1\dec2_cur_msr[63:0]
143113   end
143114   attribute \src "libresoc.v:49565.14-49565.48"
143115   process $proc$libresoc.v:49565$2247
143116     assign { } { }
143117     assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
143118     sync always
143119     sync init
143120       update \dec2_cur_pc $1\dec2_cur_pc[63:0]
143121   end
143122   attribute \src "libresoc.v:49974.13-49974.25"
143123   process $proc$libresoc.v:49974$2248
143124     assign { } { }
143125     assign $1\delay[1:0] 2'11
143126     sync always
143127     sync init
143128       update \delay $1\delay[1:0]
143129   end
143130   attribute \src "libresoc.v:49996.13-49996.29"
143131   process $proc$libresoc.v:49996$2249
143132     assign { } { }
143133     assign $1\fsm_state[1:0] 2'00
143134     sync always
143135     sync init
143136       update \fsm_state $1\fsm_state[1:0]
143137   end
143138   attribute \src "libresoc.v:49998.13-49998.35"
143139   process $proc$libresoc.v:49998$2250
143140     assign { } { }
143141     assign $0\fsm_state$131[1:0]$2251 2'00
143142     sync always
143143     sync init
143144       update \fsm_state$131 $0\fsm_state$131[1:0]$2251
143145   end
143146   attribute \src "libresoc.v:50248.14-50248.28"
143147   process $proc$libresoc.v:50248$2252
143148     assign { } { }
143149     assign $1\ilatch[31:0] 0
143150     sync always
143151     sync init
143152       update \ilatch $1\ilatch[31:0]
143153   end
143154   attribute \src "libresoc.v:50282.7-50282.30"
143155   process $proc$libresoc.v:50282$2253
143156     assign { } { }
143157     assign $1\jtag_dmi0__ack_o[0:0] 1'0
143158     sync always
143159     sync init
143160       update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0]
143161   end
143162   attribute \src "libresoc.v:50290.14-50290.52"
143163   process $proc$libresoc.v:50290$2254
143164     assign { } { }
143165     assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
143166     sync always
143167     sync init
143168       update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0]
143169   end
143170   attribute \src "libresoc.v:50350.7-50350.22"
143171   process $proc$libresoc.v:50350$2255
143172     assign { } { }
143173     assign $1\msr_read[0:0] 1'1
143174     sync always
143175     sync init
143176       update \msr_read $1\msr_read[0:0]
143177   end
143178   attribute \src "libresoc.v:50378.7-50378.24"
143179   process $proc$libresoc.v:50378$2256
143180     assign { } { }
143181     assign $1\pc_changed[0:0] 1'0
143182     sync always
143183     sync init
143184       update \pc_changed $1\pc_changed[0:0]
143185   end
143186   attribute \src "libresoc.v:50388.7-50388.25"
143187   process $proc$libresoc.v:50388$2257
143188     assign { } { }
143189     assign $1\pc_ok_delay[0:0] 1'0
143190     sync always
143191     sync init
143192       update \pc_ok_delay $1\pc_ok_delay[0:0]
143193   end
143194   attribute \src "libresoc.v:50402.14-50402.32"
143195   process $proc$libresoc.v:50402$2258
143196     assign { } { }
143197     assign $1\raw_insn_i[31:0] 0
143198     sync always
143199     sync init
143200       update \raw_insn_i $1\raw_insn_i[31:0]
143201   end
143202   attribute \src "libresoc.v:50836.3-50837.41"
143203   process $proc$libresoc.v:50836$1662
143204     assign { } { }
143205     assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
143206     sync posedge \clk
143207       update \dec2_cur_dec $0\dec2_cur_dec[63:0]
143208   end
143209   attribute \src "libresoc.v:50838.3-50839.33"
143210   process $proc$libresoc.v:50838$1663
143211     assign { } { }
143212     assign $0\core_dec[63:0] \core_dec$next
143213     sync posedge \clk
143214       update \core_dec $0\core_dec[63:0]
143215   end
143216   attribute \src "libresoc.v:50840.3-50841.41"
143217   process $proc$libresoc.v:50840$1664
143218     assign { } { }
143219     assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
143220     sync posedge \clk
143221       update \dec2_cur_msr $0\dec2_cur_msr[63:0]
143222   end
143223   attribute \src "libresoc.v:50842.3-50843.35"
143224   process $proc$libresoc.v:50842$1665
143225     assign { } { }
143226     assign $0\fsm_state[1:0] \fsm_state$next
143227     sync posedge \clk
143228       update \fsm_state $0\fsm_state[1:0]
143229   end
143230   attribute \src "libresoc.v:50844.3-50845.33"
143231   process $proc$libresoc.v:50844$1666
143232     assign { } { }
143233     assign $0\msr_read[0:0] \msr_read$next
143234     sync posedge \clk
143235       update \msr_read $0\msr_read[0:0]
143236   end
143237   attribute \src "libresoc.v:50846.3-50847.39"
143238   process $proc$libresoc.v:50846$1667
143239     assign { } { }
143240     assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
143241     sync posedge \clk
143242       update \dec2_cur_pc $0\dec2_cur_pc[63:0]
143243   end
143244   attribute \src "libresoc.v:50848.3-50849.39"
143245   process $proc$libresoc.v:50848$1668
143246     assign { } { }
143247     assign $0\bigendian_i[0:0] \bigendian_i$next
143248     sync posedge \clk
143249       update \bigendian_i $0\bigendian_i[0:0]
143250   end
143251   attribute \src "libresoc.v:50850.3-50851.37"
143252   process $proc$libresoc.v:50850$1669
143253     assign { } { }
143254     assign $0\raw_insn_i[31:0] \raw_insn_i$next
143255     sync posedge \clk
143256       update \raw_insn_i $0\raw_insn_i[31:0]
143257   end
143258   attribute \src "libresoc.v:50852.3-50853.41"
143259   process $proc$libresoc.v:50852$1670
143260     assign { } { }
143261     assign $0\core_asmcode[7:0] \core_asmcode$next
143262     sync posedge \clk
143263       update \core_asmcode $0\core_asmcode[7:0]
143264   end
143265   attribute \src "libresoc.v:50854.3-50855.35"
143266   process $proc$libresoc.v:50854$1671
143267     assign { } { }
143268     assign $0\core_rego[4:0] \core_rego$next
143269     sync posedge \clk
143270       update \core_rego $0\core_rego[4:0]
143271   end
143272   attribute \src "libresoc.v:50856.3-50857.41"
143273   process $proc$libresoc.v:50856$1672
143274     assign { } { }
143275     assign $0\core_rego_ok[0:0] \core_rego_ok$next
143276     sync posedge \clk
143277       update \core_rego_ok $0\core_rego_ok[0:0]
143278   end
143279   attribute \src "libresoc.v:50858.3-50859.45"
143280   process $proc$libresoc.v:50858$1673
143281     assign { } { }
143282     assign $0\fsm_state$131[1:0]$1674 \fsm_state$131$next
143283     sync posedge \clk
143284       update \fsm_state$131 $0\fsm_state$131[1:0]$1674
143285   end
143286   attribute \src "libresoc.v:50860.3-50861.31"
143287   process $proc$libresoc.v:50860$1675
143288     assign { } { }
143289     assign $0\core_ea[4:0] \core_ea$next
143290     sync posedge \clk
143291       update \core_ea $0\core_ea[4:0]
143292   end
143293   attribute \src "libresoc.v:50862.3-50863.37"
143294   process $proc$libresoc.v:50862$1676
143295     assign { } { }
143296     assign $0\core_ea_ok[0:0] \core_ea_ok$next
143297     sync posedge \clk
143298       update \core_ea_ok $0\core_ea_ok[0:0]
143299   end
143300   attribute \src "libresoc.v:50864.3-50865.35"
143301   process $proc$libresoc.v:50864$1677
143302     assign { } { }
143303     assign $0\core_reg1[4:0] \core_reg1$next
143304     sync posedge \clk
143305       update \core_reg1 $0\core_reg1[4:0]
143306   end
143307   attribute \src "libresoc.v:50866.3-50867.41"
143308   process $proc$libresoc.v:50866$1678
143309     assign { } { }
143310     assign $0\core_reg1_ok[0:0] \core_reg1_ok$next
143311     sync posedge \clk
143312       update \core_reg1_ok $0\core_reg1_ok[0:0]
143313   end
143314   attribute \src "libresoc.v:50868.3-50869.35"
143315   process $proc$libresoc.v:50868$1679
143316     assign { } { }
143317     assign $0\core_reg2[4:0] \core_reg2$next
143318     sync posedge \clk
143319       update \core_reg2 $0\core_reg2[4:0]
143320   end
143321   attribute \src "libresoc.v:50870.3-50871.41"
143322   process $proc$libresoc.v:50870$1680
143323     assign { } { }
143324     assign $0\core_reg2_ok[0:0] \core_reg2_ok$next
143325     sync posedge \clk
143326       update \core_reg2_ok $0\core_reg2_ok[0:0]
143327   end
143328   attribute \src "libresoc.v:50872.3-50873.35"
143329   process $proc$libresoc.v:50872$1681
143330     assign { } { }
143331     assign $0\core_reg3[4:0] \core_reg3$next
143332     sync posedge \clk
143333       update \core_reg3 $0\core_reg3[4:0]
143334   end
143335   attribute \src "libresoc.v:50874.3-50875.41"
143336   process $proc$libresoc.v:50874$1682
143337     assign { } { }
143338     assign $0\core_reg3_ok[0:0] \core_reg3_ok$next
143339     sync posedge \clk
143340       update \core_reg3_ok $0\core_reg3_ok[0:0]
143341   end
143342   attribute \src "libresoc.v:50876.3-50877.35"
143343   process $proc$libresoc.v:50876$1683
143344     assign { } { }
143345     assign $0\core_spro[9:0] \core_spro$next
143346     sync posedge \clk
143347       update \core_spro $0\core_spro[9:0]
143348   end
143349   attribute \src "libresoc.v:50878.3-50879.41"
143350   process $proc$libresoc.v:50878$1684
143351     assign { } { }
143352     assign $0\core_spro_ok[0:0] \core_spro_ok$next
143353     sync posedge \clk
143354       update \core_spro_ok $0\core_spro_ok[0:0]
143355   end
143356   attribute \src "libresoc.v:50880.3-50881.39"
143357   process $proc$libresoc.v:50880$1685
143358     assign { } { }
143359     assign $0\d_xer_delay[0:0] \d_xer_delay$next
143360     sync posedge \clk
143361       update \d_xer_delay $0\d_xer_delay[0:0]
143362   end
143363   attribute \src "libresoc.v:50882.3-50883.35"
143364   process $proc$libresoc.v:50882$1686
143365     assign { } { }
143366     assign $0\core_spr1[9:0] \core_spr1$next
143367     sync posedge \clk
143368       update \core_spr1 $0\core_spr1[9:0]
143369   end
143370   attribute \src "libresoc.v:50884.3-50885.41"
143371   process $proc$libresoc.v:50884$1687
143372     assign { } { }
143373     assign $0\core_spr1_ok[0:0] \core_spr1_ok$next
143374     sync posedge \clk
143375       update \core_spr1_ok $0\core_spr1_ok[0:0]
143376   end
143377   attribute \src "libresoc.v:50886.3-50887.39"
143378   process $proc$libresoc.v:50886$1688
143379     assign { } { }
143380     assign $0\core_xer_in[2:0] \core_xer_in$next
143381     sync posedge \clk
143382       update \core_xer_in $0\core_xer_in[2:0]
143383   end
143384   attribute \src "libresoc.v:50888.3-50889.41"
143385   process $proc$libresoc.v:50888$1689
143386     assign { } { }
143387     assign $0\core_xer_out[0:0] \core_xer_out$next
143388     sync posedge \clk
143389       update \core_xer_out $0\core_xer_out[0:0]
143390   end
143391   attribute \src "libresoc.v:50890.3-50891.37"
143392   process $proc$libresoc.v:50890$1690
143393     assign { } { }
143394     assign $0\core_fast1[2:0] \core_fast1$next
143395     sync posedge \clk
143396       update \core_fast1 $0\core_fast1[2:0]
143397   end
143398   attribute \src "libresoc.v:50892.3-50893.43"
143399   process $proc$libresoc.v:50892$1691
143400     assign { } { }
143401     assign $0\core_fast1_ok[0:0] \core_fast1_ok$next
143402     sync posedge \clk
143403       update \core_fast1_ok $0\core_fast1_ok[0:0]
143404   end
143405   attribute \src "libresoc.v:50894.3-50895.37"
143406   process $proc$libresoc.v:50894$1692
143407     assign { } { }
143408     assign $0\core_fast2[2:0] \core_fast2$next
143409     sync posedge \clk
143410       update \core_fast2 $0\core_fast2[2:0]
143411   end
143412   attribute \src "libresoc.v:50896.3-50897.43"
143413   process $proc$libresoc.v:50896$1693
143414     assign { } { }
143415     assign $0\core_fast2_ok[0:0] \core_fast2_ok$next
143416     sync posedge \clk
143417       update \core_fast2_ok $0\core_fast2_ok[0:0]
143418   end
143419   attribute \src "libresoc.v:50898.3-50899.39"
143420   process $proc$libresoc.v:50898$1694
143421     assign { } { }
143422     assign $0\core_fasto1[2:0] \core_fasto1$next
143423     sync posedge \clk
143424       update \core_fasto1 $0\core_fasto1[2:0]
143425   end
143426   attribute \src "libresoc.v:50900.3-50901.45"
143427   process $proc$libresoc.v:50900$1695
143428     assign { } { }
143429     assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
143430     sync posedge \clk
143431       update \core_fasto1_ok $0\core_fasto1_ok[0:0]
143432   end
143433   attribute \src "libresoc.v:50902.3-50903.37"
143434   process $proc$libresoc.v:50902$1696
143435     assign { } { }
143436     assign $0\d_cr_delay[0:0] \d_cr_delay$next
143437     sync posedge \clk
143438       update \d_cr_delay $0\d_cr_delay[0:0]
143439   end
143440   attribute \src "libresoc.v:50904.3-50905.39"
143441   process $proc$libresoc.v:50904$1697
143442     assign { } { }
143443     assign $0\core_fasto2[2:0] \core_fasto2$next
143444     sync posedge \clk
143445       update \core_fasto2 $0\core_fasto2[2:0]
143446   end
143447   attribute \src "libresoc.v:50906.3-50907.45"
143448   process $proc$libresoc.v:50906$1698
143449     assign { } { }
143450     assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
143451     sync posedge \clk
143452       update \core_fasto2_ok $0\core_fasto2_ok[0:0]
143453   end
143454   attribute \src "libresoc.v:50908.3-50909.39"
143455   process $proc$libresoc.v:50908$1699
143456     assign { } { }
143457     assign $0\core_cr_in1[2:0] \core_cr_in1$next
143458     sync posedge \clk
143459       update \core_cr_in1 $0\core_cr_in1[2:0]
143460   end
143461   attribute \src "libresoc.v:50910.3-50911.45"
143462   process $proc$libresoc.v:50910$1700
143463     assign { } { }
143464     assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next
143465     sync posedge \clk
143466       update \core_cr_in1_ok $0\core_cr_in1_ok[0:0]
143467   end
143468   attribute \src "libresoc.v:50912.3-50913.39"
143469   process $proc$libresoc.v:50912$1701
143470     assign { } { }
143471     assign $0\core_cr_in2[2:0] \core_cr_in2$next
143472     sync posedge \clk
143473       update \core_cr_in2 $0\core_cr_in2[2:0]
143474   end
143475   attribute \src "libresoc.v:50914.3-50915.45"
143476   process $proc$libresoc.v:50914$1702
143477     assign { } { }
143478     assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next
143479     sync posedge \clk
143480       update \core_cr_in2_ok $0\core_cr_in2_ok[0:0]
143481   end
143482   attribute \src "libresoc.v:50916.3-50917.47"
143483   process $proc$libresoc.v:50916$1703
143484     assign { } { }
143485     assign $0\core_cr_in2$48[2:0]$1704 \core_cr_in2$48$next
143486     sync posedge \clk
143487       update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$1704
143488   end
143489   attribute \src "libresoc.v:50918.3-50919.53"
143490   process $proc$libresoc.v:50918$1705
143491     assign { } { }
143492     assign $0\core_cr_in2_ok$49[0:0]$1706 \core_cr_in2_ok$49$next
143493     sync posedge \clk
143494       update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$1706
143495   end
143496   attribute \src "libresoc.v:50920.3-50921.39"
143497   process $proc$libresoc.v:50920$1707
143498     assign { } { }
143499     assign $0\core_cr_out[2:0] \core_cr_out$next
143500     sync posedge \clk
143501       update \core_cr_out $0\core_cr_out[2:0]
143502   end
143503   attribute \src "libresoc.v:50922.3-50923.45"
143504   process $proc$libresoc.v:50922$1708
143505     assign { } { }
143506     assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
143507     sync posedge \clk
143508       update \core_cr_out_ok $0\core_cr_out_ok[0:0]
143509   end
143510   attribute \src "libresoc.v:50924.3-50925.39"
143511   process $proc$libresoc.v:50924$1709
143512     assign { } { }
143513     assign $0\d_reg_delay[0:0] \d_reg_delay$next
143514     sync posedge \clk
143515       update \d_reg_delay $0\d_reg_delay[0:0]
143516   end
143517   attribute \src "libresoc.v:50926.3-50927.43"
143518   process $proc$libresoc.v:50926$1710
143519     assign { } { }
143520     assign $0\core_core_msr[63:0] \core_core_msr$next
143521     sync posedge \clk
143522       update \core_core_msr $0\core_core_msr[63:0]
143523   end
143524   attribute \src "libresoc.v:50928.3-50929.43"
143525   process $proc$libresoc.v:50928$1711
143526     assign { } { }
143527     assign $0\core_core_cia[63:0] \core_core_cia$next
143528     sync posedge \clk
143529       update \core_core_cia $0\core_core_cia[63:0]
143530   end
143531   attribute \src "libresoc.v:50930.3-50931.45"
143532   process $proc$libresoc.v:50930$1712
143533     assign { } { }
143534     assign $0\core_core_insn[31:0] \core_core_insn$next
143535     sync posedge \clk
143536       update \core_core_insn $0\core_core_insn[31:0]
143537   end
143538   attribute \src "libresoc.v:50932.3-50933.55"
143539   process $proc$libresoc.v:50932$1713
143540     assign { } { }
143541     assign $0\core_core_insn_type[6:0] \core_core_insn_type$next
143542     sync posedge \clk
143543       update \core_core_insn_type $0\core_core_insn_type[6:0]
143544   end
143545   attribute \src "libresoc.v:50934.3-50935.51"
143546   process $proc$libresoc.v:50934$1714
143547     assign { } { }
143548     assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next
143549     sync posedge \clk
143550       update \core_core_fn_unit $0\core_core_fn_unit[11:0]
143551   end
143552   attribute \src "libresoc.v:50936.3-50937.41"
143553   process $proc$libresoc.v:50936$1715
143554     assign { } { }
143555     assign $0\core_core_lk[0:0] \core_core_lk$next
143556     sync posedge \clk
143557       update \core_core_lk $0\core_core_lk[0:0]
143558   end
143559   attribute \src "libresoc.v:50938.3-50939.41"
143560   process $proc$libresoc.v:50938$1716
143561     assign { } { }
143562     assign $0\core_core_rc[0:0] \core_core_rc$next
143563     sync posedge \clk
143564       update \core_core_rc $0\core_core_rc[0:0]
143565   end
143566   attribute \src "libresoc.v:50940.3-50941.47"
143567   process $proc$libresoc.v:50940$1717
143568     assign { } { }
143569     assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next
143570     sync posedge \clk
143571       update \core_core_rc_ok $0\core_core_rc_ok[0:0]
143572   end
143573   attribute \src "libresoc.v:50942.3-50943.41"
143574   process $proc$libresoc.v:50942$1718
143575     assign { } { }
143576     assign $0\core_core_oe[0:0] \core_core_oe$next
143577     sync posedge \clk
143578       update \core_core_oe $0\core_core_oe[0:0]
143579   end
143580   attribute \src "libresoc.v:50944.3-50945.47"
143581   process $proc$libresoc.v:50944$1719
143582     assign { } { }
143583     assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next
143584     sync posedge \clk
143585       update \core_core_oe_ok $0\core_core_oe_ok[0:0]
143586   end
143587   attribute \src "libresoc.v:50946.3-50947.29"
143588   process $proc$libresoc.v:50946$1720
143589     assign { } { }
143590     assign $0\ilatch[31:0] \ilatch$next
143591     sync posedge \clk
143592       update \ilatch $0\ilatch[31:0]
143593   end
143594   attribute \src "libresoc.v:50948.3-50949.59"
143595   process $proc$libresoc.v:50948$1721
143596     assign { } { }
143597     assign $0\core_core_input_carry[1:0] \core_core_input_carry$next
143598     sync posedge \clk
143599       update \core_core_input_carry $0\core_core_input_carry[1:0]
143600   end
143601   attribute \src "libresoc.v:50950.3-50951.53"
143602   process $proc$libresoc.v:50950$1722
143603     assign { } { }
143604     assign $0\core_core_traptype[7:0] \core_core_traptype$next
143605     sync posedge \clk
143606       update \core_core_traptype $0\core_core_traptype[7:0]
143607   end
143608   attribute \src "libresoc.v:50952.3-50953.61"
143609   process $proc$libresoc.v:50952$1723
143610     assign { } { }
143611     assign $0\core_core_exc_$signal[0:0]$1724 \core_core_exc_$signal$next
143612     sync posedge \clk
143613       update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$1724
143614   end
143615   attribute \src "libresoc.v:50954.3-50955.67"
143616   process $proc$libresoc.v:50954$1725
143617     assign { } { }
143618     assign $0\core_core_exc_$signal$50[0:0]$1726 \core_core_exc_$signal$50$next
143619     sync posedge \clk
143620       update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$1726
143621   end
143622   attribute \src "libresoc.v:50956.3-50957.67"
143623   process $proc$libresoc.v:50956$1727
143624     assign { } { }
143625     assign $0\core_core_exc_$signal$51[0:0]$1728 \core_core_exc_$signal$51$next
143626     sync posedge \clk
143627       update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$1728
143628   end
143629   attribute \src "libresoc.v:50958.3-50959.67"
143630   process $proc$libresoc.v:50958$1729
143631     assign { } { }
143632     assign $0\core_core_exc_$signal$52[0:0]$1730 \core_core_exc_$signal$52$next
143633     sync posedge \clk
143634       update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$1730
143635   end
143636   attribute \src "libresoc.v:50960.3-50961.67"
143637   process $proc$libresoc.v:50960$1731
143638     assign { } { }
143639     assign $0\core_core_exc_$signal$53[0:0]$1732 \core_core_exc_$signal$53$next
143640     sync posedge \clk
143641       update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$1732
143642   end
143643   attribute \src "libresoc.v:50962.3-50963.67"
143644   process $proc$libresoc.v:50962$1733
143645     assign { } { }
143646     assign $0\core_core_exc_$signal$54[0:0]$1734 \core_core_exc_$signal$54$next
143647     sync posedge \clk
143648       update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$1734
143649   end
143650   attribute \src "libresoc.v:50964.3-50965.67"
143651   process $proc$libresoc.v:50964$1735
143652     assign { } { }
143653     assign $0\core_core_exc_$signal$55[0:0]$1736 \core_core_exc_$signal$55$next
143654     sync posedge \clk
143655       update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$1736
143656   end
143657   attribute \src "libresoc.v:50966.3-50967.67"
143658   process $proc$libresoc.v:50966$1737
143659     assign { } { }
143660     assign $0\core_core_exc_$signal$56[0:0]$1738 \core_core_exc_$signal$56$next
143661     sync posedge \clk
143662       update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$1738
143663   end
143664   attribute \src "libresoc.v:50968.3-50969.31"
143665   process $proc$libresoc.v:50968$1739
143666     assign { } { }
143667     assign $0\core_pc[63:0] \core_pc$next
143668     sync posedge \clk
143669       update \core_pc $0\core_pc[63:0]
143670   end
143671   attribute \src "libresoc.v:50970.3-50971.53"
143672   process $proc$libresoc.v:50970$1740
143673     assign { } { }
143674     assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next
143675     sync posedge \clk
143676       update \core_core_trapaddr $0\core_core_trapaddr[12:0]
143677   end
143678   attribute \src "libresoc.v:50972.3-50973.47"
143679   process $proc$libresoc.v:50972$1741
143680     assign { } { }
143681     assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next
143682     sync posedge \clk
143683       update \core_core_cr_rd $0\core_core_cr_rd[7:0]
143684   end
143685   attribute \src "libresoc.v:50974.3-50975.53"
143686   process $proc$libresoc.v:50974$1742
143687     assign { } { }
143688     assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next
143689     sync posedge \clk
143690       update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0]
143691   end
143692   attribute \src "libresoc.v:50976.3-50977.47"
143693   process $proc$libresoc.v:50976$1743
143694     assign { } { }
143695     assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next
143696     sync posedge \clk
143697       update \core_core_cr_wr $0\core_core_cr_wr[7:0]
143698   end
143699   attribute \src "libresoc.v:50978.3-50979.53"
143700   process $proc$libresoc.v:50978$1744
143701     assign { } { }
143702     assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
143703     sync posedge \clk
143704       update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
143705   end
143706   attribute \src "libresoc.v:50980.3-50981.53"
143707   process $proc$libresoc.v:50980$1745
143708     assign { } { }
143709     assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next
143710     sync posedge \clk
143711       update \core_core_is_32bit $0\core_core_is_32bit[0:0]
143712   end
143713   attribute \src "libresoc.v:50982.3-50983.37"
143714   process $proc$libresoc.v:50982$1746
143715     assign { } { }
143716     assign $0\pc_changed[0:0] \pc_changed$next
143717     sync posedge \clk
143718       update \pc_changed $0\pc_changed[0:0]
143719   end
143720   attribute \src "libresoc.v:50984.3-50985.39"
143721   process $proc$libresoc.v:50984$1747
143722     assign { } { }
143723     assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
143724     sync posedge \clk
143725       update \pc_ok_delay $0\pc_ok_delay[0:0]
143726   end
143727   attribute \src "libresoc.v:50986.3-50987.30"
143728   process $proc$libresoc.v:50986$1748
143729     assign { } { }
143730     assign $0\cu_st__rel_o_dly[0:0] 1'0
143731     sync posedge \clk
143732       update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
143733   end
143734   attribute \src "libresoc.v:50988.3-50989.27"
143735   process $proc$libresoc.v:50988$1749
143736     assign { } { }
143737     assign $0\delay[1:0] \delay$next
143738     sync posedge \por_clk
143739       update \delay $0\delay[1:0]
143740   end
143741   attribute \src "libresoc.v:50990.3-50991.33"
143742   process $proc$libresoc.v:50990$1750
143743     assign { } { }
143744     assign $0\core_msr[63:0] \core_msr$next
143745     sync posedge \clk
143746       update \core_msr $0\core_msr[63:0]
143747   end
143748   attribute \src "libresoc.v:50992.3-50993.43"
143749   process $proc$libresoc.v:50992$1751
143750     assign { } { }
143751     assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
143752     sync posedge \clk
143753       update \dec2_cur_eint $0\dec2_cur_eint[0:0]
143754   end
143755   attribute \src "libresoc.v:50994.3-50995.47"
143756   process $proc$libresoc.v:50994$1752
143757     assign { } { }
143758     assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
143759     sync posedge \clk
143760       update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
143761   end
143762   attribute \src "libresoc.v:50996.3-50997.49"
143763   process $proc$libresoc.v:50996$1753
143764     assign { } { }
143765     assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
143766     sync posedge \clk
143767       update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
143768   end
143769   attribute \src "libresoc.v:50998.3-50999.39"
143770   process $proc$libresoc.v:50998$1754
143771     assign { } { }
143772     assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
143773     sync posedge \clk
143774       update \dbg_dmi_din $0\dbg_dmi_din[63:0]
143775   end
143776   attribute \src "libresoc.v:51000.3-51001.41"
143777   process $proc$libresoc.v:51000$1755
143778     assign { } { }
143779     assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
143780     sync posedge \clk
143781       update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
143782   end
143783   attribute \src "libresoc.v:51002.3-51003.43"
143784   process $proc$libresoc.v:51002$1756
143785     assign { } { }
143786     assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
143787     sync posedge \clk
143788       update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
143789   end
143790   attribute \src "libresoc.v:51004.3-51005.45"
143791   process $proc$libresoc.v:51004$1757
143792     assign { } { }
143793     assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
143794     sync posedge \clk
143795       update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
143796   end
143797   attribute \src "libresoc.v:51006.3-51007.35"
143798   process $proc$libresoc.v:51006$1758
143799     assign { } { }
143800     assign $0\core_eint[0:0] \core_eint$next
143801     sync posedge \clk
143802       update \core_eint $0\core_eint[0:0]
143803   end
143804   attribute \src "libresoc.v:51482.3-51490.6"
143805   process $proc$libresoc.v:51482$1759
143806     assign { } { }
143807     assign { } { }
143808     assign $0\dbg_dmi_addr_i$next[3:0]$1760 $1\dbg_dmi_addr_i$next[3:0]$1761
143809     attribute \src "libresoc.v:51483.5-51483.29"
143810     switch \initial
143811       attribute \src "libresoc.v:51483.9-51483.17"
143812       case 1'1
143813       case
143814     end
143815     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
143816     switch \rst
143817       attribute \src "libresoc.v:0.0-0.0"
143818       case 1'1
143819         assign { } { }
143820         assign $1\dbg_dmi_addr_i$next[3:0]$1761 4'0000
143821       case
143822         assign $1\dbg_dmi_addr_i$next[3:0]$1761 \jtag_dmi0__addr_i
143823     end
143824     sync always
143825       update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1760
143826   end
143827   attribute \src "libresoc.v:51491.3-51499.6"
143828   process $proc$libresoc.v:51491$1762
143829     assign { } { }
143830     assign { } { }
143831     assign $0\dbg_dmi_req_i$next[0:0]$1763 $1\dbg_dmi_req_i$next[0:0]$1764
143832     attribute \src "libresoc.v:51492.5-51492.29"
143833     switch \initial
143834       attribute \src "libresoc.v:51492.9-51492.17"
143835       case 1'1
143836       case
143837     end
143838     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
143839     switch \rst
143840       attribute \src "libresoc.v:0.0-0.0"
143841       case 1'1
143842         assign { } { }
143843         assign $1\dbg_dmi_req_i$next[0:0]$1764 1'0
143844       case
143845         assign $1\dbg_dmi_req_i$next[0:0]$1764 \jtag_dmi0__req_i
143846     end
143847     sync always
143848       update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1763
143849   end
143850   attribute \src "libresoc.v:51500.3-51520.6"
143851   process $proc$libresoc.v:51500$1765
143852     assign { } { }
143853     assign { } { }
143854     assign { } { }
143855     assign $0\dec2_cur_msr$next[63:0]$1766 $3\dec2_cur_msr$next[63:0]$1769
143856     attribute \src "libresoc.v:51501.5-51501.29"
143857     switch \initial
143858       attribute \src "libresoc.v:51501.9-51501.17"
143859       case 1'1
143860       case
143861     end
143862     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
143863     switch \fsm_state
143864       attribute \src "libresoc.v:0.0-0.0"
143865       case 2'01
143866         assign { } { }
143867         assign $1\dec2_cur_msr$next[63:0]$1767 $2\dec2_cur_msr$next[63:0]$1768
143868         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
143869         switch \$115
143870           attribute \src "libresoc.v:0.0-0.0"
143871           case 1'1
143872             assign { } { }
143873             assign $2\dec2_cur_msr$next[63:0]$1768 \msr__data_o
143874           case
143875             assign $2\dec2_cur_msr$next[63:0]$1768 \dec2_cur_msr
143876         end
143877       case
143878         assign $1\dec2_cur_msr$next[63:0]$1767 \dec2_cur_msr
143879     end
143880     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
143881     switch \rst
143882       attribute \src "libresoc.v:0.0-0.0"
143883       case 1'1
143884         assign { } { }
143885         assign $3\dec2_cur_msr$next[63:0]$1769 64'0000000000000000000000000000000000000000000000000000000000000000
143886       case
143887         assign $3\dec2_cur_msr$next[63:0]$1769 $1\dec2_cur_msr$next[63:0]$1767
143888     end
143889     sync always
143890       update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1766
143891   end
143892   attribute \src "libresoc.v:51521.3-51539.6"
143893   process $proc$libresoc.v:51521$1770
143894     assign { } { }
143895     assign { } { }
143896     assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0]
143897     attribute \src "libresoc.v:51522.5-51522.29"
143898     switch \initial
143899       attribute \src "libresoc.v:51522.9-51522.17"
143900       case 1'1
143901       case
143902     end
143903     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
143904     switch \fsm_state
143905       attribute \src "libresoc.v:0.0-0.0"
143906       case 2'01
143907         assign { } { }
143908         assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0]
143909         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
143910         switch \imem_f_busy_o
143911           attribute \src "libresoc.v:0.0-0.0"
143912           case 1'1
143913             assign $2\dec2_raw_opcode_in[31:0] 0
143914           attribute \src "libresoc.v:0.0-0.0"
143915           case
143916             assign { } { }
143917             assign $2\dec2_raw_opcode_in[31:0] \$117
143918         end
143919       case
143920         assign $1\dec2_raw_opcode_in[31:0] 0
143921     end
143922     sync always
143923       update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
143924   end
143925   attribute \src "libresoc.v:51540.3-51571.6"
143926   process $proc$libresoc.v:51540$1771
143927     assign { } { }
143928     assign { } { }
143929     assign { } { }
143930     assign { } { }
143931     assign { } { }
143932     assign { } { }
143933     assign { } { }
143934     assign { } { }
143935     assign { } { }
143936     assign { } { }
143937     assign { } { }
143938     assign { } { }
143939     assign $0\core_dec$next[63:0]$1772 $3\core_dec$next[63:0]$1784
143940     assign $0\core_eint$next[0:0]$1773 $3\core_eint$next[0:0]$1785
143941     assign $0\core_msr$next[63:0]$1774 $3\core_msr$next[63:0]$1786
143942     assign $0\core_pc$next[63:0]$1775 $3\core_pc$next[63:0]$1787
143943     attribute \src "libresoc.v:51541.5-51541.29"
143944     switch \initial
143945       attribute \src "libresoc.v:51541.9-51541.17"
143946       case 1'1
143947       case
143948     end
143949     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
143950     switch \fsm_state
143951       attribute \src "libresoc.v:0.0-0.0"
143952       case 2'01
143953         assign { } { }
143954         assign { } { }
143955         assign { } { }
143956         assign { } { }
143957         assign $1\core_dec$next[63:0]$1776 $2\core_dec$next[63:0]$1780
143958         assign $1\core_eint$next[0:0]$1777 $2\core_eint$next[0:0]$1781
143959         assign $1\core_msr$next[63:0]$1778 $2\core_msr$next[63:0]$1782
143960         assign $1\core_pc$next[63:0]$1779 $2\core_pc$next[63:0]$1783
143961         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
143962         switch \imem_f_busy_o
143963           attribute \src "libresoc.v:0.0-0.0"
143964           case 1'1
143965             assign $2\core_dec$next[63:0]$1780 \core_dec
143966             assign $2\core_eint$next[0:0]$1781 \core_eint
143967             assign $2\core_msr$next[63:0]$1782 \core_msr
143968             assign $2\core_pc$next[63:0]$1783 \core_pc
143969           attribute \src "libresoc.v:0.0-0.0"
143970           case
143971             assign { } { }
143972             assign { } { }
143973             assign { } { }
143974             assign { } { }
143975             assign { $2\core_dec$next[63:0]$1780 $2\core_eint$next[0:0]$1781 $2\core_msr$next[63:0]$1782 $2\core_pc$next[63:0]$1783 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
143976         end
143977       case
143978         assign $1\core_dec$next[63:0]$1776 \core_dec
143979         assign $1\core_eint$next[0:0]$1777 \core_eint
143980         assign $1\core_msr$next[63:0]$1778 \core_msr
143981         assign $1\core_pc$next[63:0]$1779 \core_pc
143982     end
143983     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
143984     switch \rst
143985       attribute \src "libresoc.v:0.0-0.0"
143986       case 1'1
143987         assign { } { }
143988         assign { } { }
143989         assign { } { }
143990         assign { } { }
143991         assign $3\core_pc$next[63:0]$1787 64'0000000000000000000000000000000000000000000000000000000000000000
143992         assign $3\core_msr$next[63:0]$1786 64'0000000000000000000000000000000000000000000000000000000000000000
143993         assign $3\core_eint$next[0:0]$1785 1'0
143994         assign $3\core_dec$next[63:0]$1784 64'0000000000000000000000000000000000000000000000000000000000000000
143995       case
143996         assign $3\core_dec$next[63:0]$1784 $1\core_dec$next[63:0]$1776
143997         assign $3\core_eint$next[0:0]$1785 $1\core_eint$next[0:0]$1777
143998         assign $3\core_msr$next[63:0]$1786 $1\core_msr$next[63:0]$1778
143999         assign $3\core_pc$next[63:0]$1787 $1\core_pc$next[63:0]$1779
144000     end
144001     sync always
144002       update \core_dec$next $0\core_dec$next[63:0]$1772
144003       update \core_eint$next $0\core_eint$next[0:0]$1773
144004       update \core_msr$next $0\core_msr$next[63:0]$1774
144005       update \core_pc$next $0\core_pc$next[63:0]$1775
144006   end
144007   attribute \src "libresoc.v:51572.3-51595.6"
144008   process $proc$libresoc.v:51572$1788
144009     assign { } { }
144010     assign { } { }
144011     assign { } { }
144012     assign $0\ilatch$next[31:0]$1789 $3\ilatch$next[31:0]$1792
144013     attribute \src "libresoc.v:51573.5-51573.29"
144014     switch \initial
144015       attribute \src "libresoc.v:51573.9-51573.17"
144016       case 1'1
144017       case
144018     end
144019     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
144020     switch \fsm_state
144021       attribute \src "libresoc.v:0.0-0.0"
144022       case 2'01
144023         assign { } { }
144024         assign $1\ilatch$next[31:0]$1790 $2\ilatch$next[31:0]$1791
144025         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
144026         switch \imem_f_busy_o
144027           attribute \src "libresoc.v:0.0-0.0"
144028           case 1'1
144029             assign $2\ilatch$next[31:0]$1791 \ilatch
144030           attribute \src "libresoc.v:0.0-0.0"
144031           case
144032             assign { } { }
144033             assign $2\ilatch$next[31:0]$1791 \$121
144034         end
144035       case
144036         assign $1\ilatch$next[31:0]$1790 \ilatch
144037     end
144038     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144039     switch \rst
144040       attribute \src "libresoc.v:0.0-0.0"
144041       case 1'1
144042         assign { } { }
144043         assign $3\ilatch$next[31:0]$1792 0
144044       case
144045         assign $3\ilatch$next[31:0]$1792 $1\ilatch$next[31:0]$1790
144046     end
144047     sync always
144048       update \ilatch$next $0\ilatch$next[31:0]$1789
144049   end
144050   attribute \src "libresoc.v:51596.3-51615.6"
144051   process $proc$libresoc.v:51596$1793
144052     assign { } { }
144053     assign { } { }
144054     assign $0\ivalid_i[0:0] $1\ivalid_i[0:0]
144055     attribute \src "libresoc.v:51597.5-51597.29"
144056     switch \initial
144057       attribute \src "libresoc.v:51597.9-51597.17"
144058       case 1'1
144059       case
144060     end
144061     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
144062     switch \fsm_state
144063       attribute \src "libresoc.v:0.0-0.0"
144064       case 2'10
144065         assign { } { }
144066         assign $1\ivalid_i[0:0] 1'1
144067       attribute \src "libresoc.v:0.0-0.0"
144068       case 2'11
144069         assign { } { }
144070         assign $1\ivalid_i[0:0] $2\ivalid_i[0:0]
144071         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307"
144072         switch \$125
144073           attribute \src "libresoc.v:0.0-0.0"
144074           case 1'1
144075             assign { } { }
144076             assign $2\ivalid_i[0:0] 1'1
144077           case
144078             assign $2\ivalid_i[0:0] 1'0
144079         end
144080       case
144081         assign $1\ivalid_i[0:0] 1'0
144082     end
144083     sync always
144084       update \ivalid_i $0\ivalid_i[0:0]
144085   end
144086   attribute \src "libresoc.v:51616.3-51626.6"
144087   process $proc$libresoc.v:51616$1794
144088     assign { } { }
144089     assign { } { }
144090     assign $0\issue_i[0:0] $1\issue_i[0:0]
144091     attribute \src "libresoc.v:51617.5-51617.29"
144092     switch \initial
144093       attribute \src "libresoc.v:51617.9-51617.17"
144094       case 1'1
144095       case
144096     end
144097     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
144098     switch \fsm_state
144099       attribute \src "libresoc.v:0.0-0.0"
144100       case 2'10
144101         assign { } { }
144102         assign $1\issue_i[0:0] 1'1
144103       case
144104         assign $1\issue_i[0:0] 1'0
144105     end
144106     sync always
144107       update \issue_i $0\issue_i[0:0]
144108   end
144109   attribute \src "libresoc.v:51627.3-51636.6"
144110   process $proc$libresoc.v:51627$1795
144111     assign { } { }
144112     assign { } { }
144113     assign $0\dmi__addr[4:0] $1\dmi__addr[4:0]
144114     attribute \src "libresoc.v:51628.5-51628.29"
144115     switch \initial
144116       attribute \src "libresoc.v:51628.9-51628.17"
144117       case 1'1
144118       case
144119     end
144120     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325"
144121     switch \dbg_d_gpr_req
144122       attribute \src "libresoc.v:0.0-0.0"
144123       case 1'1
144124         assign { } { }
144125         assign $1\dmi__addr[4:0] \dbg_d_gpr_addr [4:0]
144126       case
144127         assign $1\dmi__addr[4:0] 5'00000
144128     end
144129     sync always
144130       update \dmi__addr $0\dmi__addr[4:0]
144131   end
144132   attribute \src "libresoc.v:51637.3-51646.6"
144133   process $proc$libresoc.v:51637$1796
144134     assign { } { }
144135     assign { } { }
144136     assign $0\dmi__ren[0:0] $1\dmi__ren[0:0]
144137     attribute \src "libresoc.v:51638.5-51638.29"
144138     switch \initial
144139       attribute \src "libresoc.v:51638.9-51638.17"
144140       case 1'1
144141       case
144142     end
144143     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325"
144144     switch \dbg_d_gpr_req
144145       attribute \src "libresoc.v:0.0-0.0"
144146       case 1'1
144147         assign { } { }
144148         assign $1\dmi__ren[0:0] 1'1
144149       case
144150         assign $1\dmi__ren[0:0] 1'0
144151     end
144152     sync always
144153       update \dmi__ren $0\dmi__ren[0:0]
144154   end
144155   attribute \src "libresoc.v:51647.3-51655.6"
144156   process $proc$libresoc.v:51647$1797
144157     assign { } { }
144158     assign { } { }
144159     assign $0\d_reg_delay$next[0:0]$1798 $1\d_reg_delay$next[0:0]$1799
144160     attribute \src "libresoc.v:51648.5-51648.29"
144161     switch \initial
144162       attribute \src "libresoc.v:51648.9-51648.17"
144163       case 1'1
144164       case
144165     end
144166     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144167     switch \rst
144168       attribute \src "libresoc.v:0.0-0.0"
144169       case 1'1
144170         assign { } { }
144171         assign $1\d_reg_delay$next[0:0]$1799 1'0
144172       case
144173         assign $1\d_reg_delay$next[0:0]$1799 \dbg_d_gpr_req
144174     end
144175     sync always
144176       update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1798
144177   end
144178   attribute \src "libresoc.v:51656.3-51665.6"
144179   process $proc$libresoc.v:51656$1800
144180     assign { } { }
144181     assign { } { }
144182     assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
144183     attribute \src "libresoc.v:51657.5-51657.29"
144184     switch \initial
144185       attribute \src "libresoc.v:51657.9-51657.17"
144186       case 1'1
144187       case
144188     end
144189     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335"
144190     switch \d_reg_delay
144191       attribute \src "libresoc.v:0.0-0.0"
144192       case 1'1
144193         assign { } { }
144194         assign $1\dbg_d_gpr_data[63:0] \dmi__data_o
144195       case
144196         assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144197     end
144198     sync always
144199       update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
144200   end
144201   attribute \src "libresoc.v:51666.3-51675.6"
144202   process $proc$libresoc.v:51666$1801
144203     assign { } { }
144204     assign { } { }
144205     assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
144206     attribute \src "libresoc.v:51667.5-51667.29"
144207     switch \initial
144208       attribute \src "libresoc.v:51667.9-51667.17"
144209       case 1'1
144210       case
144211     end
144212     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335"
144213     switch \d_reg_delay
144214       attribute \src "libresoc.v:0.0-0.0"
144215       case 1'1
144216         assign { } { }
144217         assign $1\dbg_d_gpr_ack[0:0] 1'1
144218       case
144219         assign $1\dbg_d_gpr_ack[0:0] 1'0
144220     end
144221     sync always
144222       update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
144223   end
144224   attribute \src "libresoc.v:51676.3-51685.6"
144225   process $proc$libresoc.v:51676$1802
144226     assign { } { }
144227     assign { } { }
144228     assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0]
144229     attribute \src "libresoc.v:51677.5-51677.29"
144230     switch \initial
144231       attribute \src "libresoc.v:51677.9-51677.17"
144232       case 1'1
144233       case
144234     end
144235     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
144236     switch \dbg_d_cr_req
144237       attribute \src "libresoc.v:0.0-0.0"
144238       case 1'1
144239         assign { } { }
144240         assign $1\full_rd2__ren[7:0] 8'11111111
144241       case
144242         assign $1\full_rd2__ren[7:0] 8'00000000
144243     end
144244     sync always
144245       update \full_rd2__ren $0\full_rd2__ren[7:0]
144246   end
144247   attribute \src "libresoc.v:51686.3-51694.6"
144248   process $proc$libresoc.v:51686$1803
144249     assign { } { }
144250     assign { } { }
144251     assign $0\d_cr_delay$next[0:0]$1804 $1\d_cr_delay$next[0:0]$1805
144252     attribute \src "libresoc.v:51687.5-51687.29"
144253     switch \initial
144254       attribute \src "libresoc.v:51687.9-51687.17"
144255       case 1'1
144256       case
144257     end
144258     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144259     switch \rst
144260       attribute \src "libresoc.v:0.0-0.0"
144261       case 1'1
144262         assign { } { }
144263         assign $1\d_cr_delay$next[0:0]$1805 1'0
144264       case
144265         assign $1\d_cr_delay$next[0:0]$1805 \dbg_d_cr_req
144266     end
144267     sync always
144268       update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1804
144269   end
144270   attribute \src "libresoc.v:51695.3-51704.6"
144271   process $proc$libresoc.v:51695$1806
144272     assign { } { }
144273     assign { } { }
144274     assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
144275     attribute \src "libresoc.v:51696.5-51696.29"
144276     switch \initial
144277       attribute \src "libresoc.v:51696.9-51696.17"
144278       case 1'1
144279       case
144280     end
144281     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345"
144282     switch \d_cr_delay
144283       attribute \src "libresoc.v:0.0-0.0"
144284       case 1'1
144285         assign { } { }
144286         assign $1\dbg_d_cr_data[63:0] \$127
144287       case
144288         assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144289     end
144290     sync always
144291       update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
144292   end
144293   attribute \src "libresoc.v:51705.3-51714.6"
144294   process $proc$libresoc.v:51705$1807
144295     assign { } { }
144296     assign { } { }
144297     assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
144298     attribute \src "libresoc.v:51706.5-51706.29"
144299     switch \initial
144300       attribute \src "libresoc.v:51706.9-51706.17"
144301       case 1'1
144302       case
144303     end
144304     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345"
144305     switch \d_cr_delay
144306       attribute \src "libresoc.v:0.0-0.0"
144307       case 1'1
144308         assign { } { }
144309         assign $1\dbg_d_cr_ack[0:0] 1'1
144310       case
144311         assign $1\dbg_d_cr_ack[0:0] 1'0
144312     end
144313     sync always
144314       update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
144315   end
144316   attribute \src "libresoc.v:51715.3-51724.6"
144317   process $proc$libresoc.v:51715$1808
144318     assign { } { }
144319     assign { } { }
144320     assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0]
144321     attribute \src "libresoc.v:51716.5-51716.29"
144322     switch \initial
144323       attribute \src "libresoc.v:51716.9-51716.17"
144324       case 1'1
144325       case
144326     end
144327     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351"
144328     switch \dbg_d_xer_req
144329       attribute \src "libresoc.v:0.0-0.0"
144330       case 1'1
144331         assign { } { }
144332         assign $1\full_rd__ren[2:0] 3'111
144333       case
144334         assign $1\full_rd__ren[2:0] 3'000
144335     end
144336     sync always
144337       update \full_rd__ren $0\full_rd__ren[2:0]
144338   end
144339   attribute \src "libresoc.v:51725.3-51733.6"
144340   process $proc$libresoc.v:51725$1809
144341     assign { } { }
144342     assign { } { }
144343     assign $0\d_xer_delay$next[0:0]$1810 $1\d_xer_delay$next[0:0]$1811
144344     attribute \src "libresoc.v:51726.5-51726.29"
144345     switch \initial
144346       attribute \src "libresoc.v:51726.9-51726.17"
144347       case 1'1
144348       case
144349     end
144350     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144351     switch \rst
144352       attribute \src "libresoc.v:0.0-0.0"
144353       case 1'1
144354         assign { } { }
144355         assign $1\d_xer_delay$next[0:0]$1811 1'0
144356       case
144357         assign $1\d_xer_delay$next[0:0]$1811 \dbg_d_xer_req
144358     end
144359     sync always
144360       update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1810
144361   end
144362   attribute \src "libresoc.v:51734.3-51743.6"
144363   process $proc$libresoc.v:51734$1812
144364     assign { } { }
144365     assign { } { }
144366     assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
144367     attribute \src "libresoc.v:51735.5-51735.29"
144368     switch \initial
144369       attribute \src "libresoc.v:51735.9-51735.17"
144370       case 1'1
144371       case
144372     end
144373     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355"
144374     switch \d_xer_delay
144375       attribute \src "libresoc.v:0.0-0.0"
144376       case 1'1
144377         assign { } { }
144378         assign $1\dbg_d_xer_data[63:0] \$129
144379       case
144380         assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144381     end
144382     sync always
144383       update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
144384   end
144385   attribute \src "libresoc.v:51744.3-51753.6"
144386   process $proc$libresoc.v:51744$1813
144387     assign { } { }
144388     assign { } { }
144389     assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
144390     attribute \src "libresoc.v:51745.5-51745.29"
144391     switch \initial
144392       attribute \src "libresoc.v:51745.9-51745.17"
144393       case 1'1
144394       case
144395     end
144396     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355"
144397     switch \d_xer_delay
144398       attribute \src "libresoc.v:0.0-0.0"
144399       case 1'1
144400         assign { } { }
144401         assign $1\dbg_d_xer_ack[0:0] 1'1
144402       case
144403         assign $1\dbg_d_xer_ack[0:0] 1'0
144404     end
144405     sync always
144406       update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
144407   end
144408   attribute \src "libresoc.v:51754.3-51768.6"
144409   process $proc$libresoc.v:51754$1814
144410     assign { } { }
144411     assign { } { }
144412     assign $0\issue__addr[2:0] $1\issue__addr[2:0]
144413     attribute \src "libresoc.v:51755.5-51755.29"
144414     switch \initial
144415       attribute \src "libresoc.v:51755.9-51755.17"
144416       case 1'1
144417       case
144418     end
144419     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144420     switch \fsm_state$131
144421       attribute \src "libresoc.v:0.0-0.0"
144422       case 2'00
144423         assign { } { }
144424         assign $1\issue__addr[2:0] 3'110
144425       attribute \src "libresoc.v:0.0-0.0"
144426       case 2'10
144427         assign { } { }
144428         assign $1\issue__addr[2:0] 3'111
144429       case
144430         assign $1\issue__addr[2:0] 3'000
144431     end
144432     sync always
144433       update \issue__addr $0\issue__addr[2:0]
144434   end
144435   attribute \src "libresoc.v:51769.3-51783.6"
144436   process $proc$libresoc.v:51769$1815
144437     assign { } { }
144438     assign { } { }
144439     assign $0\issue__ren[0:0] $1\issue__ren[0:0]
144440     attribute \src "libresoc.v:51770.5-51770.29"
144441     switch \initial
144442       attribute \src "libresoc.v:51770.9-51770.17"
144443       case 1'1
144444       case
144445     end
144446     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144447     switch \fsm_state$131
144448       attribute \src "libresoc.v:0.0-0.0"
144449       case 2'00
144450         assign { } { }
144451         assign $1\issue__ren[0:0] 1'1
144452       attribute \src "libresoc.v:0.0-0.0"
144453       case 2'10
144454         assign { } { }
144455         assign $1\issue__ren[0:0] 1'1
144456       case
144457         assign $1\issue__ren[0:0] 1'0
144458     end
144459     sync always
144460       update \issue__ren $0\issue__ren[0:0]
144461   end
144462   attribute \src "libresoc.v:51784.3-51811.6"
144463   process $proc$libresoc.v:51784$1816
144464     assign { } { }
144465     assign { } { }
144466     assign { } { }
144467     assign $0\fsm_state$131$next[1:0]$1817 $2\fsm_state$131$next[1:0]$1819
144468     attribute \src "libresoc.v:51785.5-51785.29"
144469     switch \initial
144470       attribute \src "libresoc.v:51785.9-51785.17"
144471       case 1'1
144472       case
144473     end
144474     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144475     switch \fsm_state$131
144476       attribute \src "libresoc.v:0.0-0.0"
144477       case 2'00
144478         assign { } { }
144479         assign $1\fsm_state$131$next[1:0]$1818 2'01
144480       attribute \src "libresoc.v:0.0-0.0"
144481       case 2'01
144482         assign { } { }
144483         assign $1\fsm_state$131$next[1:0]$1818 2'10
144484       attribute \src "libresoc.v:0.0-0.0"
144485       case 2'10
144486         assign { } { }
144487         assign $1\fsm_state$131$next[1:0]$1818 2'11
144488       attribute \src "libresoc.v:0.0-0.0"
144489       case 2'11
144490         assign { } { }
144491         assign $1\fsm_state$131$next[1:0]$1818 2'00
144492       case
144493         assign $1\fsm_state$131$next[1:0]$1818 \fsm_state$131
144494     end
144495     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144496     switch \rst
144497       attribute \src "libresoc.v:0.0-0.0"
144498       case 1'1
144499         assign { } { }
144500         assign $2\fsm_state$131$next[1:0]$1819 2'00
144501       case
144502         assign $2\fsm_state$131$next[1:0]$1819 $1\fsm_state$131$next[1:0]$1818
144503     end
144504     sync always
144505       update \fsm_state$131$next $0\fsm_state$131$next[1:0]$1817
144506   end
144507   attribute \src "libresoc.v:51812.3-51822.6"
144508   process $proc$libresoc.v:51812$1820
144509     assign { } { }
144510     assign { } { }
144511     assign $0\new_dec[63:0] $1\new_dec[63:0]
144512     attribute \src "libresoc.v:51813.5-51813.29"
144513     switch \initial
144514       attribute \src "libresoc.v:51813.9-51813.17"
144515       case 1'1
144516       case
144517     end
144518     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144519     switch \fsm_state$131
144520       attribute \src "libresoc.v:0.0-0.0"
144521       case 2'01
144522         assign { } { }
144523         assign $1\new_dec[63:0] \$132 [63:0]
144524       case
144525         assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144526     end
144527     sync always
144528       update \new_dec $0\new_dec[63:0]
144529   end
144530   attribute \src "libresoc.v:51823.3-51837.6"
144531   process $proc$libresoc.v:51823$1821
144532     assign { } { }
144533     assign { } { }
144534     assign $0\issue__addr$135[2:0]$1822 $1\issue__addr$135[2:0]$1823
144535     attribute \src "libresoc.v:51824.5-51824.29"
144536     switch \initial
144537       attribute \src "libresoc.v:51824.9-51824.17"
144538       case 1'1
144539       case
144540     end
144541     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144542     switch \fsm_state$131
144543       attribute \src "libresoc.v:0.0-0.0"
144544       case 2'01
144545         assign { } { }
144546         assign $1\issue__addr$135[2:0]$1823 3'110
144547       attribute \src "libresoc.v:0.0-0.0"
144548       case 2'11
144549         assign { } { }
144550         assign $1\issue__addr$135[2:0]$1823 3'111
144551       case
144552         assign $1\issue__addr$135[2:0]$1823 3'000
144553     end
144554     sync always
144555       update \issue__addr$135 $0\issue__addr$135[2:0]$1822
144556   end
144557   attribute \src "libresoc.v:51838.3-51852.6"
144558   process $proc$libresoc.v:51838$1824
144559     assign { } { }
144560     assign { } { }
144561     assign $0\issue__wen[0:0] $1\issue__wen[0:0]
144562     attribute \src "libresoc.v:51839.5-51839.29"
144563     switch \initial
144564       attribute \src "libresoc.v:51839.9-51839.17"
144565       case 1'1
144566       case
144567     end
144568     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144569     switch \fsm_state$131
144570       attribute \src "libresoc.v:0.0-0.0"
144571       case 2'01
144572         assign { } { }
144573         assign $1\issue__wen[0:0] 1'1
144574       attribute \src "libresoc.v:0.0-0.0"
144575       case 2'11
144576         assign { } { }
144577         assign $1\issue__wen[0:0] 1'1
144578       case
144579         assign $1\issue__wen[0:0] 1'0
144580     end
144581     sync always
144582       update \issue__wen $0\issue__wen[0:0]
144583   end
144584   attribute \src "libresoc.v:51853.3-51867.6"
144585   process $proc$libresoc.v:51853$1825
144586     assign { } { }
144587     assign { } { }
144588     assign $0\issue__data_i[63:0] $1\issue__data_i[63:0]
144589     attribute \src "libresoc.v:51854.5-51854.29"
144590     switch \initial
144591       attribute \src "libresoc.v:51854.9-51854.17"
144592       case 1'1
144593       case
144594     end
144595     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144596     switch \fsm_state$131
144597       attribute \src "libresoc.v:0.0-0.0"
144598       case 2'01
144599         assign { } { }
144600         assign $1\issue__data_i[63:0] \new_dec
144601       attribute \src "libresoc.v:0.0-0.0"
144602       case 2'11
144603         assign { } { }
144604         assign $1\issue__data_i[63:0] \new_tb
144605       case
144606         assign $1\issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144607     end
144608     sync always
144609       update \issue__data_i $0\issue__data_i[63:0]
144610   end
144611   attribute \src "libresoc.v:51868.3-51883.6"
144612   process $proc$libresoc.v:51868$1826
144613     assign { } { }
144614     assign { } { }
144615     assign { } { }
144616     assign $0\dec2_cur_dec$next[63:0]$1827 $2\dec2_cur_dec$next[63:0]$1829
144617     attribute \src "libresoc.v:51869.5-51869.29"
144618     switch \initial
144619       attribute \src "libresoc.v:51869.9-51869.17"
144620       case 1'1
144621       case
144622     end
144623     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144624     switch \fsm_state$131
144625       attribute \src "libresoc.v:0.0-0.0"
144626       case 2'01
144627         assign { } { }
144628         assign $1\dec2_cur_dec$next[63:0]$1828 \new_dec
144629       case
144630         assign $1\dec2_cur_dec$next[63:0]$1828 \dec2_cur_dec
144631     end
144632     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144633     switch \rst
144634       attribute \src "libresoc.v:0.0-0.0"
144635       case 1'1
144636         assign { } { }
144637         assign $2\dec2_cur_dec$next[63:0]$1829 64'0000000000000000000000000000000000000000000000000000000000000000
144638       case
144639         assign $2\dec2_cur_dec$next[63:0]$1829 $1\dec2_cur_dec$next[63:0]$1828
144640     end
144641     sync always
144642       update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1827
144643   end
144644   attribute \src "libresoc.v:51884.3-51894.6"
144645   process $proc$libresoc.v:51884$1830
144646     assign { } { }
144647     assign { } { }
144648     assign $0\new_tb[63:0] $1\new_tb[63:0]
144649     attribute \src "libresoc.v:51885.5-51885.29"
144650     switch \initial
144651       attribute \src "libresoc.v:51885.9-51885.17"
144652       case 1'1
144653       case
144654     end
144655     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381"
144656     switch \fsm_state$131
144657       attribute \src "libresoc.v:0.0-0.0"
144658       case 2'11
144659         assign { } { }
144660         assign $1\new_tb[63:0] \$136 [63:0]
144661       case
144662         assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144663     end
144664     sync always
144665       update \new_tb $0\new_tb[63:0]
144666   end
144667   attribute \src "libresoc.v:51895.3-51903.6"
144668   process $proc$libresoc.v:51895$1831
144669     assign { } { }
144670     assign { } { }
144671     assign $0\dbg_dmi_we_i$next[0:0]$1832 $1\dbg_dmi_we_i$next[0:0]$1833
144672     attribute \src "libresoc.v:51896.5-51896.29"
144673     switch \initial
144674       attribute \src "libresoc.v:51896.9-51896.17"
144675       case 1'1
144676       case
144677     end
144678     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144679     switch \rst
144680       attribute \src "libresoc.v:0.0-0.0"
144681       case 1'1
144682         assign { } { }
144683         assign $1\dbg_dmi_we_i$next[0:0]$1833 1'0
144684       case
144685         assign $1\dbg_dmi_we_i$next[0:0]$1833 \jtag_dmi0__we_i
144686     end
144687     sync always
144688       update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1832
144689   end
144690   attribute \src "libresoc.v:51904.3-51912.6"
144691   process $proc$libresoc.v:51904$1834
144692     assign { } { }
144693     assign { } { }
144694     assign $0\pc_ok_delay$next[0:0]$1835 $1\pc_ok_delay$next[0:0]$1836
144695     attribute \src "libresoc.v:51905.5-51905.29"
144696     switch \initial
144697       attribute \src "libresoc.v:51905.9-51905.17"
144698       case 1'1
144699       case
144700     end
144701     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144702     switch \rst
144703       attribute \src "libresoc.v:0.0-0.0"
144704       case 1'1
144705         assign { } { }
144706         assign $1\pc_ok_delay$next[0:0]$1836 1'0
144707       case
144708         assign $1\pc_ok_delay$next[0:0]$1836 \$28
144709     end
144710     sync always
144711       update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1835
144712   end
144713   attribute \src "libresoc.v:51913.3-51928.6"
144714   process $proc$libresoc.v:51913$1837
144715     assign { } { }
144716     assign { } { }
144717     assign { } { }
144718     assign $0\pc[63:0] $2\pc[63:0]
144719     attribute \src "libresoc.v:51914.5-51914.29"
144720     switch \initial
144721       attribute \src "libresoc.v:51914.9-51914.17"
144722       case 1'1
144723       case
144724     end
144725     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207"
144726     switch \pc_i_ok
144727       attribute \src "libresoc.v:0.0-0.0"
144728       case 1'1
144729         assign { } { }
144730         assign $1\pc[63:0] \pc_i
144731       case
144732         assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144733     end
144734     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
144735     switch \pc_ok_delay
144736       attribute \src "libresoc.v:0.0-0.0"
144737       case 1'1
144738         assign { } { }
144739         assign $2\pc[63:0] \cia__data_o
144740       case
144741         assign $2\pc[63:0] $1\pc[63:0]
144742     end
144743     sync always
144744       update \pc $0\pc[63:0]
144745   end
144746   attribute \src "libresoc.v:51929.3-51941.6"
144747   process $proc$libresoc.v:51929$1838
144748     assign { } { }
144749     assign { } { }
144750     assign $0\cia__ren[3:0] $1\cia__ren[3:0]
144751     attribute \src "libresoc.v:51930.5-51930.29"
144752     switch \initial
144753       attribute \src "libresoc.v:51930.9-51930.17"
144754       case 1'1
144755       case
144756     end
144757     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207"
144758     switch \pc_i_ok
144759       attribute \src "libresoc.v:0.0-0.0"
144760       case 1'1
144761         assign $1\cia__ren[3:0] 4'0000
144762       attribute \src "libresoc.v:0.0-0.0"
144763       case
144764         assign { } { }
144765         assign $1\cia__ren[3:0] 4'0001
144766     end
144767     sync always
144768       update \cia__ren $0\cia__ren[3:0]
144769   end
144770   attribute \src "libresoc.v:51942.3-51962.6"
144771   process $proc$libresoc.v:51942$1839
144772     assign { } { }
144773     assign { } { }
144774     assign $0\wen[3:0] $1\wen[3:0]
144775     attribute \src "libresoc.v:51943.5-51943.29"
144776     switch \initial
144777       attribute \src "libresoc.v:51943.9-51943.17"
144778       case 1'1
144779       case
144780     end
144781     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
144782     switch \fsm_state
144783       attribute \src "libresoc.v:0.0-0.0"
144784       case 2'11
144785         assign { } { }
144786         assign $1\wen[3:0] $2\wen[3:0]
144787         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
144788         switch \$30
144789           attribute \src "libresoc.v:0.0-0.0"
144790           case 1'1
144791             assign { } { }
144792             assign $2\wen[3:0] $3\wen[3:0]
144793             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
144794             switch \$32
144795               attribute \src "libresoc.v:0.0-0.0"
144796               case 1'1
144797                 assign { } { }
144798                 assign $3\wen[3:0] 4'0001
144799               case
144800                 assign $3\wen[3:0] 4'0000
144801             end
144802           case
144803             assign $2\wen[3:0] 4'0000
144804         end
144805       case
144806         assign $1\wen[3:0] 4'0000
144807     end
144808     sync always
144809       update \wen $0\wen[3:0]
144810   end
144811   attribute \src "libresoc.v:51963.3-51983.6"
144812   process $proc$libresoc.v:51963$1840
144813     assign { } { }
144814     assign { } { }
144815     assign $0\data_i[63:0] $1\data_i[63:0]
144816     attribute \src "libresoc.v:51964.5-51964.29"
144817     switch \initial
144818       attribute \src "libresoc.v:51964.9-51964.17"
144819       case 1'1
144820       case
144821     end
144822     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
144823     switch \fsm_state
144824       attribute \src "libresoc.v:0.0-0.0"
144825       case 2'11
144826         assign { } { }
144827         assign $1\data_i[63:0] $2\data_i[63:0]
144828         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
144829         switch \$34
144830           attribute \src "libresoc.v:0.0-0.0"
144831           case 1'1
144832             assign { } { }
144833             assign $2\data_i[63:0] $3\data_i[63:0]
144834             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
144835             switch \$36
144836               attribute \src "libresoc.v:0.0-0.0"
144837               case 1'1
144838                 assign { } { }
144839                 assign $3\data_i[63:0] \nia
144840               case
144841                 assign $3\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144842             end
144843           case
144844             assign $2\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144845         end
144846       case
144847         assign $1\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
144848     end
144849     sync always
144850       update \data_i $0\data_i[63:0]
144851   end
144852   attribute \src "libresoc.v:51984.3-51999.6"
144853   process $proc$libresoc.v:51984$1841
144854     assign { } { }
144855     assign { } { }
144856     assign $0\msr__ren[3:0] $1\msr__ren[3:0]
144857     attribute \src "libresoc.v:51985.5-51985.29"
144858     switch \initial
144859       attribute \src "libresoc.v:51985.9-51985.17"
144860       case 1'1
144861       case
144862     end
144863     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
144864     switch \fsm_state
144865       attribute \src "libresoc.v:0.0-0.0"
144866       case 2'00
144867         assign { } { }
144868         assign $1\msr__ren[3:0] $2\msr__ren[3:0]
144869         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
144870         switch \$42
144871           attribute \src "libresoc.v:0.0-0.0"
144872           case 1'1
144873             assign { } { }
144874             assign $2\msr__ren[3:0] 4'0010
144875           case
144876             assign $2\msr__ren[3:0] 4'0000
144877         end
144878       case
144879         assign $1\msr__ren[3:0] 4'0000
144880     end
144881     sync always
144882       update \msr__ren $0\msr__ren[3:0]
144883   end
144884   attribute \src "libresoc.v:52000.3-52008.6"
144885   process $proc$libresoc.v:52000$1842
144886     assign { } { }
144887     assign { } { }
144888     assign $0\dbg_dmi_din$next[63:0]$1843 $1\dbg_dmi_din$next[63:0]$1844
144889     attribute \src "libresoc.v:52001.5-52001.29"
144890     switch \initial
144891       attribute \src "libresoc.v:52001.9-52001.17"
144892       case 1'1
144893       case
144894     end
144895     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144896     switch \rst
144897       attribute \src "libresoc.v:0.0-0.0"
144898       case 1'1
144899         assign { } { }
144900         assign $1\dbg_dmi_din$next[63:0]$1844 64'0000000000000000000000000000000000000000000000000000000000000000
144901       case
144902         assign $1\dbg_dmi_din$next[63:0]$1844 \jtag_dmi0__din
144903     end
144904     sync always
144905       update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1843
144906   end
144907   attribute \src "libresoc.v:52009.3-52033.6"
144908   process $proc$libresoc.v:52009$1845
144909     assign { } { }
144910     assign { } { }
144911     assign { } { }
144912     assign $0\pc_changed$next[0:0]$1846 $3\pc_changed$next[0:0]$1849
144913     attribute \src "libresoc.v:52010.5-52010.29"
144914     switch \initial
144915       attribute \src "libresoc.v:52010.9-52010.17"
144916       case 1'1
144917       case
144918     end
144919     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
144920     switch \fsm_state
144921       attribute \src "libresoc.v:0.0-0.0"
144922       case 2'00
144923         assign { } { }
144924         assign $1\pc_changed$next[0:0]$1847 1'0
144925       attribute \src "libresoc.v:0.0-0.0"
144926       case 2'11
144927         assign { } { }
144928         assign $1\pc_changed$next[0:0]$1847 $2\pc_changed$next[0:0]$1848
144929         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
144930         switch \$44
144931           attribute \src "libresoc.v:0.0-0.0"
144932           case 1'1
144933             assign { } { }
144934             assign $2\pc_changed$next[0:0]$1848 1'1
144935           case
144936             assign $2\pc_changed$next[0:0]$1848 \pc_changed
144937         end
144938       case
144939         assign $1\pc_changed$next[0:0]$1847 \pc_changed
144940     end
144941     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
144942     switch \rst
144943       attribute \src "libresoc.v:0.0-0.0"
144944       case 1'1
144945         assign { } { }
144946         assign $3\pc_changed$next[0:0]$1849 1'0
144947       case
144948         assign $3\pc_changed$next[0:0]$1849 $1\pc_changed$next[0:0]$1847
144949     end
144950     sync always
144951       update \pc_changed$next $0\pc_changed$next[0:0]$1846
144952   end
144953   attribute \src "libresoc.v:52034.3-52156.6"
144954   process $proc$libresoc.v:52034$1850
144955     assign { } { }
144956     assign { } { }
144957     assign { } { }
144958     assign { } { }
144959     assign { } { }
144960     assign { } { }
144961     assign { } { }
144962     assign { } { }
144963     assign { } { }
144964     assign { } { }
144965     assign { } { }
144966     assign { } { }
144967     assign { } { }
144968     assign { } { }
144969     assign { } { }
144970     assign { } { }
144971     assign { } { }
144972     assign { } { }
144973     assign { } { }
144974     assign { } { }
144975     assign { } { }
144976     assign { } { }
144977     assign { } { }
144978     assign { } { }
144979     assign { } { }
144980     assign { } { }
144981     assign { } { }
144982     assign { } { }
144983     assign { } { }
144984     assign { } { }
144985     assign { } { }
144986     assign { } { }
144987     assign { } { }
144988     assign { } { }
144989     assign { } { }
144990     assign { } { }
144991     assign { } { }
144992     assign { } { }
144993     assign { } { }
144994     assign { } { }
144995     assign { } { }
144996     assign { } { }
144997     assign { } { }
144998     assign { } { }
144999     assign { } { }
145000     assign { } { }
145001     assign { } { }
145002     assign { } { }
145003     assign { } { }
145004     assign { } { }
145005     assign { } { }
145006     assign { } { }
145007     assign { } { }
145008     assign { } { }
145009     assign { } { }
145010     assign { } { }
145011     assign { } { }
145012     assign { } { }
145013     assign { } { }
145014     assign { } { }
145015     assign { } { }
145016     assign { } { }
145017     assign { } { }
145018     assign { } { }
145019     assign { } { }
145020     assign { } { }
145021     assign { } { }
145022     assign { } { }
145023     assign { } { }
145024     assign { } { }
145025     assign { } { }
145026     assign { } { }
145027     assign { } { }
145028     assign { } { }
145029     assign { } { }
145030     assign { } { }
145031     assign { } { }
145032     assign { } { }
145033     assign { } { }
145034     assign { } { }
145035     assign { } { }
145036     assign { } { }
145037     assign { } { }
145038     assign { } { }
145039     assign { } { }
145040     assign { } { }
145041     assign { } { }
145042     assign { } { }
145043     assign { } { }
145044     assign { } { }
145045     assign { } { }
145046     assign { } { }
145047     assign { } { }
145048     assign { } { }
145049     assign { } { }
145050     assign { } { }
145051     assign { } { }
145052     assign { } { }
145053     assign { } { }
145054     assign { } { }
145055     assign { } { }
145056     assign { } { }
145057     assign { } { }
145058     assign { } { }
145059     assign { } { }
145060     assign { } { }
145061     assign { } { }
145062     assign { } { }
145063     assign { } { }
145064     assign { } { }
145065     assign { } { }
145066     assign { } { }
145067     assign { } { }
145068     assign { } { }
145069     assign { } { }
145070     assign { } { }
145071     assign { } { }
145072     assign { } { }
145073     assign $0\core_asmcode$next[7:0]$1851 $1\core_asmcode$next[7:0]$1910
145074     assign $0\core_core_cia$next[63:0]$1852 $1\core_core_cia$next[63:0]$1911
145075     assign $0\core_core_cr_rd$next[7:0]$1853 $1\core_core_cr_rd$next[7:0]$1912
145076     assign { } { }
145077     assign $0\core_core_cr_wr$next[7:0]$1855 $1\core_core_cr_wr$next[7:0]$1914
145078     assign { } { }
145079     assign { } { }
145080     assign { } { }
145081     assign { } { }
145082     assign { } { }
145083     assign { } { }
145084     assign { } { }
145085     assign { } { }
145086     assign { } { }
145087     assign $0\core_core_fn_unit$next[11:0]$1865 $1\core_core_fn_unit$next[11:0]$1924
145088     assign $0\core_core_input_carry$next[1:0]$1866 $1\core_core_input_carry$next[1:0]$1925
145089     assign $0\core_core_insn$next[31:0]$1867 $1\core_core_insn$next[31:0]$1926
145090     assign $0\core_core_insn_type$next[6:0]$1868 $1\core_core_insn_type$next[6:0]$1927
145091     assign $0\core_core_is_32bit$next[0:0]$1869 $1\core_core_is_32bit$next[0:0]$1928
145092     assign $0\core_core_lk$next[0:0]$1870 $1\core_core_lk$next[0:0]$1929
145093     assign $0\core_core_msr$next[63:0]$1871 $1\core_core_msr$next[63:0]$1930
145094     assign $0\core_core_oe$next[0:0]$1872 $1\core_core_oe$next[0:0]$1931
145095     assign { } { }
145096     assign $0\core_core_rc$next[0:0]$1874 $1\core_core_rc$next[0:0]$1933
145097     assign { } { }
145098     assign $0\core_core_trapaddr$next[12:0]$1876 $1\core_core_trapaddr$next[12:0]$1935
145099     assign $0\core_core_traptype$next[7:0]$1877 $1\core_core_traptype$next[7:0]$1936
145100     assign $0\core_cr_in1$next[2:0]$1878 $1\core_cr_in1$next[2:0]$1937
145101     assign { } { }
145102     assign $0\core_cr_in2$48$next[2:0]$1880 $1\core_cr_in2$48$next[2:0]$1939
145103     assign $0\core_cr_in2$next[2:0]$1881 $1\core_cr_in2$next[2:0]$1940
145104     assign { } { }
145105     assign { } { }
145106     assign $0\core_cr_out$next[2:0]$1884 $1\core_cr_out$next[2:0]$1943
145107     assign { } { }
145108     assign $0\core_ea$next[4:0]$1886 $1\core_ea$next[4:0]$1945
145109     assign { } { }
145110     assign $0\core_fast1$next[2:0]$1888 $1\core_fast1$next[2:0]$1947
145111     assign { } { }
145112     assign $0\core_fast2$next[2:0]$1890 $1\core_fast2$next[2:0]$1949
145113     assign { } { }
145114     assign $0\core_fasto1$next[2:0]$1892 $1\core_fasto1$next[2:0]$1951
145115     assign { } { }
145116     assign $0\core_fasto2$next[2:0]$1894 $1\core_fasto2$next[2:0]$1953
145117     assign { } { }
145118     assign $0\core_reg1$next[4:0]$1896 $1\core_reg1$next[4:0]$1955
145119     assign { } { }
145120     assign $0\core_reg2$next[4:0]$1898 $1\core_reg2$next[4:0]$1957
145121     assign { } { }
145122     assign $0\core_reg3$next[4:0]$1900 $1\core_reg3$next[4:0]$1959
145123     assign { } { }
145124     assign $0\core_rego$next[4:0]$1902 $1\core_rego$next[4:0]$1961
145125     assign { } { }
145126     assign $0\core_spr1$next[9:0]$1904 $1\core_spr1$next[9:0]$1963
145127     assign { } { }
145128     assign $0\core_spro$next[9:0]$1906 $1\core_spro$next[9:0]$1965
145129     assign { } { }
145130     assign $0\core_xer_in$next[2:0]$1908 $1\core_xer_in$next[2:0]$1967
145131     assign $0\core_xer_out$next[0:0]$1909 $1\core_xer_out$next[0:0]$1968
145132     assign $0\core_core_cr_rd_ok$next[0:0]$1854 $4\core_core_cr_rd_ok$next[0:0]$2087
145133     assign $0\core_core_cr_wr_ok$next[0:0]$1856 $4\core_core_cr_wr_ok$next[0:0]$2088
145134     assign $0\core_core_exc_$signal$50$next[0:0]$1857 $4\core_core_exc_$signal$50$next[0:0]$2089
145135     assign $0\core_core_exc_$signal$51$next[0:0]$1858 $4\core_core_exc_$signal$51$next[0:0]$2090
145136     assign $0\core_core_exc_$signal$52$next[0:0]$1859 $4\core_core_exc_$signal$52$next[0:0]$2091
145137     assign $0\core_core_exc_$signal$53$next[0:0]$1860 $4\core_core_exc_$signal$53$next[0:0]$2092
145138     assign $0\core_core_exc_$signal$54$next[0:0]$1861 $4\core_core_exc_$signal$54$next[0:0]$2093
145139     assign $0\core_core_exc_$signal$55$next[0:0]$1862 $4\core_core_exc_$signal$55$next[0:0]$2094
145140     assign $0\core_core_exc_$signal$56$next[0:0]$1863 $4\core_core_exc_$signal$56$next[0:0]$2095
145141     assign $0\core_core_exc_$signal$next[0:0]$1864 $4\core_core_exc_$signal$next[0:0]$2096
145142     assign $0\core_core_oe_ok$next[0:0]$1873 $4\core_core_oe_ok$next[0:0]$2097
145143     assign $0\core_core_rc_ok$next[0:0]$1875 $4\core_core_rc_ok$next[0:0]$2098
145144     assign $0\core_cr_in1_ok$next[0:0]$1879 $4\core_cr_in1_ok$next[0:0]$2099
145145     assign $0\core_cr_in2_ok$49$next[0:0]$1882 $4\core_cr_in2_ok$49$next[0:0]$2100
145146     assign $0\core_cr_in2_ok$next[0:0]$1883 $4\core_cr_in2_ok$next[0:0]$2101
145147     assign $0\core_cr_out_ok$next[0:0]$1885 $4\core_cr_out_ok$next[0:0]$2102
145148     assign $0\core_ea_ok$next[0:0]$1887 $4\core_ea_ok$next[0:0]$2103
145149     assign $0\core_fast1_ok$next[0:0]$1889 $4\core_fast1_ok$next[0:0]$2104
145150     assign $0\core_fast2_ok$next[0:0]$1891 $4\core_fast2_ok$next[0:0]$2105
145151     assign $0\core_fasto1_ok$next[0:0]$1893 $4\core_fasto1_ok$next[0:0]$2106
145152     assign $0\core_fasto2_ok$next[0:0]$1895 $4\core_fasto2_ok$next[0:0]$2107
145153     assign $0\core_reg1_ok$next[0:0]$1897 $4\core_reg1_ok$next[0:0]$2108
145154     assign $0\core_reg2_ok$next[0:0]$1899 $4\core_reg2_ok$next[0:0]$2109
145155     assign $0\core_reg3_ok$next[0:0]$1901 $4\core_reg3_ok$next[0:0]$2110
145156     assign $0\core_rego_ok$next[0:0]$1903 $4\core_rego_ok$next[0:0]$2111
145157     assign $0\core_spr1_ok$next[0:0]$1905 $4\core_spr1_ok$next[0:0]$2112
145158     assign $0\core_spro_ok$next[0:0]$1907 $4\core_spro_ok$next[0:0]$2113
145159     attribute \src "libresoc.v:52035.5-52035.29"
145160     switch \initial
145161       attribute \src "libresoc.v:52035.9-52035.17"
145162       case 1'1
145163       case
145164     end
145165     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
145166     switch \fsm_state
145167       attribute \src "libresoc.v:0.0-0.0"
145168       case 2'00
145169         assign { } { }
145170         assign { } { }
145171         assign { } { }
145172         assign { } { }
145173         assign { } { }
145174         assign { } { }
145175         assign { } { }
145176         assign { } { }
145177         assign { } { }
145178         assign { } { }
145179         assign { } { }
145180         assign { } { }
145181         assign { } { }
145182         assign { } { }
145183         assign { } { }
145184         assign { } { }
145185         assign { } { }
145186         assign { } { }
145187         assign { } { }
145188         assign { } { }
145189         assign { } { }
145190         assign { } { }
145191         assign { } { }
145192         assign { } { }
145193         assign { } { }
145194         assign { } { }
145195         assign { } { }
145196         assign { } { }
145197         assign { } { }
145198         assign { } { }
145199         assign { } { }
145200         assign { } { }
145201         assign { } { }
145202         assign { } { }
145203         assign { } { }
145204         assign { } { }
145205         assign { } { }
145206         assign { } { }
145207         assign { } { }
145208         assign { } { }
145209         assign { } { }
145210         assign { } { }
145211         assign { } { }
145212         assign { } { }
145213         assign { } { }
145214         assign { } { }
145215         assign { } { }
145216         assign { } { }
145217         assign { } { }
145218         assign { } { }
145219         assign { } { }
145220         assign { } { }
145221         assign { } { }
145222         assign { } { }
145223         assign { } { }
145224         assign { } { }
145225         assign { } { }
145226         assign { } { }
145227         assign { } { }
145228         assign { $1\core_core_is_32bit$next[0:0]$1928 $1\core_core_cr_wr_ok$next[0:0]$1915 $1\core_core_cr_wr$next[7:0]$1914 $1\core_core_cr_rd_ok$next[0:0]$1913 $1\core_core_cr_rd$next[7:0]$1912 $1\core_core_trapaddr$next[12:0]$1935 $1\core_core_exc_$signal$56$next[0:0]$1922 $1\core_core_exc_$signal$55$next[0:0]$1921 $1\core_core_exc_$signal$54$next[0:0]$1920 $1\core_core_exc_$signal$53$next[0:0]$1919 $1\core_core_exc_$signal$52$next[0:0]$1918 $1\core_core_exc_$signal$51$next[0:0]$1917 $1\core_core_exc_$signal$50$next[0:0]$1916 $1\core_core_exc_$signal$next[0:0]$1923 $1\core_core_traptype$next[7:0]$1936 $1\core_core_input_carry$next[1:0]$1925 $1\core_core_oe_ok$next[0:0]$1932 $1\core_core_oe$next[0:0]$1931 $1\core_core_rc_ok$next[0:0]$1934 $1\core_core_rc$next[0:0]$1933 $1\core_core_lk$next[0:0]$1929 $1\core_core_fn_unit$next[11:0]$1924 $1\core_core_insn_type$next[6:0]$1927 $1\core_core_insn$next[31:0]$1926 $1\core_core_cia$next[63:0]$1911 $1\core_core_msr$next[63:0]$1930 $1\core_cr_out_ok$next[0:0]$1944 $1\core_cr_out$next[2:0]$1943 $1\core_cr_in2_ok$49$next[0:0]$1941 $1\core_cr_in2$48$next[2:0]$1939 $1\core_cr_in2_ok$next[0:0]$1942 $1\core_cr_in2$next[2:0]$1940 $1\core_cr_in1_ok$next[0:0]$1938 $1\core_cr_in1$next[2:0]$1937 $1\core_fasto2_ok$next[0:0]$1954 $1\core_fasto2$next[2:0]$1953 $1\core_fasto1_ok$next[0:0]$1952 $1\core_fasto1$next[2:0]$1951 $1\core_fast2_ok$next[0:0]$1950 $1\core_fast2$next[2:0]$1949 $1\core_fast1_ok$next[0:0]$1948 $1\core_fast1$next[2:0]$1947 $1\core_xer_out$next[0:0]$1968 $1\core_xer_in$next[2:0]$1967 $1\core_spr1_ok$next[0:0]$1964 $1\core_spr1$next[9:0]$1963 $1\core_spro_ok$next[0:0]$1966 $1\core_spro$next[9:0]$1965 $1\core_reg3_ok$next[0:0]$1960 $1\core_reg3$next[4:0]$1959 $1\core_reg2_ok$next[0:0]$1958 $1\core_reg2$next[4:0]$1957 $1\core_reg1_ok$next[0:0]$1956 $1\core_reg1$next[4:0]$1955 $1\core_ea_ok$next[0:0]$1946 $1\core_ea$next[4:0]$1945 $1\core_rego_ok$next[0:0]$1962 $1\core_rego$next[4:0]$1961 $1\core_asmcode$next[7:0]$1910 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
145229       attribute \src "libresoc.v:0.0-0.0"
145230       case 2'01
145231         assign { } { }
145232         assign { } { }
145233         assign { } { }
145234         assign { } { }
145235         assign { } { }
145236         assign { } { }
145237         assign { } { }
145238         assign { } { }
145239         assign { } { }
145240         assign { } { }
145241         assign { } { }
145242         assign { } { }
145243         assign { } { }
145244         assign { } { }
145245         assign { } { }
145246         assign { } { }
145247         assign { } { }
145248         assign { } { }
145249         assign { } { }
145250         assign { } { }
145251         assign { } { }
145252         assign { } { }
145253         assign { } { }
145254         assign { } { }
145255         assign { } { }
145256         assign { } { }
145257         assign { } { }
145258         assign { } { }
145259         assign { } { }
145260         assign { } { }
145261         assign { } { }
145262         assign { } { }
145263         assign { } { }
145264         assign { } { }
145265         assign { } { }
145266         assign { } { }
145267         assign { } { }
145268         assign { } { }
145269         assign { } { }
145270         assign { } { }
145271         assign { } { }
145272         assign { } { }
145273         assign { } { }
145274         assign { } { }
145275         assign { } { }
145276         assign { } { }
145277         assign { } { }
145278         assign { } { }
145279         assign { } { }
145280         assign { } { }
145281         assign { } { }
145282         assign { } { }
145283         assign { } { }
145284         assign { } { }
145285         assign { } { }
145286         assign { } { }
145287         assign { } { }
145288         assign { } { }
145289         assign { } { }
145290         assign $1\core_asmcode$next[7:0]$1910 $2\core_asmcode$next[7:0]$1969
145291         assign $1\core_core_cia$next[63:0]$1911 $2\core_core_cia$next[63:0]$1970
145292         assign $1\core_core_cr_rd$next[7:0]$1912 $2\core_core_cr_rd$next[7:0]$1971
145293         assign $1\core_core_cr_rd_ok$next[0:0]$1913 $2\core_core_cr_rd_ok$next[0:0]$1972
145294         assign $1\core_core_cr_wr$next[7:0]$1914 $2\core_core_cr_wr$next[7:0]$1973
145295         assign $1\core_core_cr_wr_ok$next[0:0]$1915 $2\core_core_cr_wr_ok$next[0:0]$1974
145296         assign $1\core_core_exc_$signal$50$next[0:0]$1916 $2\core_core_exc_$signal$50$next[0:0]$1975
145297         assign $1\core_core_exc_$signal$51$next[0:0]$1917 $2\core_core_exc_$signal$51$next[0:0]$1976
145298         assign $1\core_core_exc_$signal$52$next[0:0]$1918 $2\core_core_exc_$signal$52$next[0:0]$1977
145299         assign $1\core_core_exc_$signal$53$next[0:0]$1919 $2\core_core_exc_$signal$53$next[0:0]$1978
145300         assign $1\core_core_exc_$signal$54$next[0:0]$1920 $2\core_core_exc_$signal$54$next[0:0]$1979
145301         assign $1\core_core_exc_$signal$55$next[0:0]$1921 $2\core_core_exc_$signal$55$next[0:0]$1980
145302         assign $1\core_core_exc_$signal$56$next[0:0]$1922 $2\core_core_exc_$signal$56$next[0:0]$1981
145303         assign $1\core_core_exc_$signal$next[0:0]$1923 $2\core_core_exc_$signal$next[0:0]$1982
145304         assign $1\core_core_fn_unit$next[11:0]$1924 $2\core_core_fn_unit$next[11:0]$1983
145305         assign $1\core_core_input_carry$next[1:0]$1925 $2\core_core_input_carry$next[1:0]$1984
145306         assign $1\core_core_insn$next[31:0]$1926 $2\core_core_insn$next[31:0]$1985
145307         assign $1\core_core_insn_type$next[6:0]$1927 $2\core_core_insn_type$next[6:0]$1986
145308         assign $1\core_core_is_32bit$next[0:0]$1928 $2\core_core_is_32bit$next[0:0]$1987
145309         assign $1\core_core_lk$next[0:0]$1929 $2\core_core_lk$next[0:0]$1988
145310         assign $1\core_core_msr$next[63:0]$1930 $2\core_core_msr$next[63:0]$1989
145311         assign $1\core_core_oe$next[0:0]$1931 $2\core_core_oe$next[0:0]$1990
145312         assign $1\core_core_oe_ok$next[0:0]$1932 $2\core_core_oe_ok$next[0:0]$1991
145313         assign $1\core_core_rc$next[0:0]$1933 $2\core_core_rc$next[0:0]$1992
145314         assign $1\core_core_rc_ok$next[0:0]$1934 $2\core_core_rc_ok$next[0:0]$1993
145315         assign $1\core_core_trapaddr$next[12:0]$1935 $2\core_core_trapaddr$next[12:0]$1994
145316         assign $1\core_core_traptype$next[7:0]$1936 $2\core_core_traptype$next[7:0]$1995
145317         assign $1\core_cr_in1$next[2:0]$1937 $2\core_cr_in1$next[2:0]$1996
145318         assign $1\core_cr_in1_ok$next[0:0]$1938 $2\core_cr_in1_ok$next[0:0]$1997
145319         assign $1\core_cr_in2$48$next[2:0]$1939 $2\core_cr_in2$48$next[2:0]$1998
145320         assign $1\core_cr_in2$next[2:0]$1940 $2\core_cr_in2$next[2:0]$1999
145321         assign $1\core_cr_in2_ok$49$next[0:0]$1941 $2\core_cr_in2_ok$49$next[0:0]$2000
145322         assign $1\core_cr_in2_ok$next[0:0]$1942 $2\core_cr_in2_ok$next[0:0]$2001
145323         assign $1\core_cr_out$next[2:0]$1943 $2\core_cr_out$next[2:0]$2002
145324         assign $1\core_cr_out_ok$next[0:0]$1944 $2\core_cr_out_ok$next[0:0]$2003
145325         assign $1\core_ea$next[4:0]$1945 $2\core_ea$next[4:0]$2004
145326         assign $1\core_ea_ok$next[0:0]$1946 $2\core_ea_ok$next[0:0]$2005
145327         assign $1\core_fast1$next[2:0]$1947 $2\core_fast1$next[2:0]$2006
145328         assign $1\core_fast1_ok$next[0:0]$1948 $2\core_fast1_ok$next[0:0]$2007
145329         assign $1\core_fast2$next[2:0]$1949 $2\core_fast2$next[2:0]$2008
145330         assign $1\core_fast2_ok$next[0:0]$1950 $2\core_fast2_ok$next[0:0]$2009
145331         assign $1\core_fasto1$next[2:0]$1951 $2\core_fasto1$next[2:0]$2010
145332         assign $1\core_fasto1_ok$next[0:0]$1952 $2\core_fasto1_ok$next[0:0]$2011
145333         assign $1\core_fasto2$next[2:0]$1953 $2\core_fasto2$next[2:0]$2012
145334         assign $1\core_fasto2_ok$next[0:0]$1954 $2\core_fasto2_ok$next[0:0]$2013
145335         assign $1\core_reg1$next[4:0]$1955 $2\core_reg1$next[4:0]$2014
145336         assign $1\core_reg1_ok$next[0:0]$1956 $2\core_reg1_ok$next[0:0]$2015
145337         assign $1\core_reg2$next[4:0]$1957 $2\core_reg2$next[4:0]$2016
145338         assign $1\core_reg2_ok$next[0:0]$1958 $2\core_reg2_ok$next[0:0]$2017
145339         assign $1\core_reg3$next[4:0]$1959 $2\core_reg3$next[4:0]$2018
145340         assign $1\core_reg3_ok$next[0:0]$1960 $2\core_reg3_ok$next[0:0]$2019
145341         assign $1\core_rego$next[4:0]$1961 $2\core_rego$next[4:0]$2020
145342         assign $1\core_rego_ok$next[0:0]$1962 $2\core_rego_ok$next[0:0]$2021
145343         assign $1\core_spr1$next[9:0]$1963 $2\core_spr1$next[9:0]$2022
145344         assign $1\core_spr1_ok$next[0:0]$1964 $2\core_spr1_ok$next[0:0]$2023
145345         assign $1\core_spro$next[9:0]$1965 $2\core_spro$next[9:0]$2024
145346         assign $1\core_spro_ok$next[0:0]$1966 $2\core_spro_ok$next[0:0]$2025
145347         assign $1\core_xer_in$next[2:0]$1967 $2\core_xer_in$next[2:0]$2026
145348         assign $1\core_xer_out$next[0:0]$1968 $2\core_xer_out$next[0:0]$2027
145349         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
145350         switch \imem_f_busy_o
145351           attribute \src "libresoc.v:0.0-0.0"
145352           case 1'1
145353             assign $2\core_asmcode$next[7:0]$1969 \core_asmcode
145354             assign $2\core_core_cia$next[63:0]$1970 \core_core_cia
145355             assign $2\core_core_cr_rd$next[7:0]$1971 \core_core_cr_rd
145356             assign $2\core_core_cr_rd_ok$next[0:0]$1972 \core_core_cr_rd_ok
145357             assign $2\core_core_cr_wr$next[7:0]$1973 \core_core_cr_wr
145358             assign $2\core_core_cr_wr_ok$next[0:0]$1974 \core_core_cr_wr_ok
145359             assign $2\core_core_exc_$signal$50$next[0:0]$1975 \core_core_exc_$signal$50
145360             assign $2\core_core_exc_$signal$51$next[0:0]$1976 \core_core_exc_$signal$51
145361             assign $2\core_core_exc_$signal$52$next[0:0]$1977 \core_core_exc_$signal$52
145362             assign $2\core_core_exc_$signal$53$next[0:0]$1978 \core_core_exc_$signal$53
145363             assign $2\core_core_exc_$signal$54$next[0:0]$1979 \core_core_exc_$signal$54
145364             assign $2\core_core_exc_$signal$55$next[0:0]$1980 \core_core_exc_$signal$55
145365             assign $2\core_core_exc_$signal$56$next[0:0]$1981 \core_core_exc_$signal$56
145366             assign $2\core_core_exc_$signal$next[0:0]$1982 \core_core_exc_$signal
145367             assign $2\core_core_fn_unit$next[11:0]$1983 \core_core_fn_unit
145368             assign $2\core_core_input_carry$next[1:0]$1984 \core_core_input_carry
145369             assign $2\core_core_insn$next[31:0]$1985 \core_core_insn
145370             assign $2\core_core_insn_type$next[6:0]$1986 \core_core_insn_type
145371             assign $2\core_core_is_32bit$next[0:0]$1987 \core_core_is_32bit
145372             assign $2\core_core_lk$next[0:0]$1988 \core_core_lk
145373             assign $2\core_core_msr$next[63:0]$1989 \core_core_msr
145374             assign $2\core_core_oe$next[0:0]$1990 \core_core_oe
145375             assign $2\core_core_oe_ok$next[0:0]$1991 \core_core_oe_ok
145376             assign $2\core_core_rc$next[0:0]$1992 \core_core_rc
145377             assign $2\core_core_rc_ok$next[0:0]$1993 \core_core_rc_ok
145378             assign $2\core_core_trapaddr$next[12:0]$1994 \core_core_trapaddr
145379             assign $2\core_core_traptype$next[7:0]$1995 \core_core_traptype
145380             assign $2\core_cr_in1$next[2:0]$1996 \core_cr_in1
145381             assign $2\core_cr_in1_ok$next[0:0]$1997 \core_cr_in1_ok
145382             assign $2\core_cr_in2$48$next[2:0]$1998 \core_cr_in2$48
145383             assign $2\core_cr_in2$next[2:0]$1999 \core_cr_in2
145384             assign $2\core_cr_in2_ok$49$next[0:0]$2000 \core_cr_in2_ok$49
145385             assign $2\core_cr_in2_ok$next[0:0]$2001 \core_cr_in2_ok
145386             assign $2\core_cr_out$next[2:0]$2002 \core_cr_out
145387             assign $2\core_cr_out_ok$next[0:0]$2003 \core_cr_out_ok
145388             assign $2\core_ea$next[4:0]$2004 \core_ea
145389             assign $2\core_ea_ok$next[0:0]$2005 \core_ea_ok
145390             assign $2\core_fast1$next[2:0]$2006 \core_fast1
145391             assign $2\core_fast1_ok$next[0:0]$2007 \core_fast1_ok
145392             assign $2\core_fast2$next[2:0]$2008 \core_fast2
145393             assign $2\core_fast2_ok$next[0:0]$2009 \core_fast2_ok
145394             assign $2\core_fasto1$next[2:0]$2010 \core_fasto1
145395             assign $2\core_fasto1_ok$next[0:0]$2011 \core_fasto1_ok
145396             assign $2\core_fasto2$next[2:0]$2012 \core_fasto2
145397             assign $2\core_fasto2_ok$next[0:0]$2013 \core_fasto2_ok
145398             assign $2\core_reg1$next[4:0]$2014 \core_reg1
145399             assign $2\core_reg1_ok$next[0:0]$2015 \core_reg1_ok
145400             assign $2\core_reg2$next[4:0]$2016 \core_reg2
145401             assign $2\core_reg2_ok$next[0:0]$2017 \core_reg2_ok
145402             assign $2\core_reg3$next[4:0]$2018 \core_reg3
145403             assign $2\core_reg3_ok$next[0:0]$2019 \core_reg3_ok
145404             assign $2\core_rego$next[4:0]$2020 \core_rego
145405             assign $2\core_rego_ok$next[0:0]$2021 \core_rego_ok
145406             assign $2\core_spr1$next[9:0]$2022 \core_spr1
145407             assign $2\core_spr1_ok$next[0:0]$2023 \core_spr1_ok
145408             assign $2\core_spro$next[9:0]$2024 \core_spro
145409             assign $2\core_spro_ok$next[0:0]$2025 \core_spro_ok
145410             assign $2\core_xer_in$next[2:0]$2026 \core_xer_in
145411             assign $2\core_xer_out$next[0:0]$2027 \core_xer_out
145412           attribute \src "libresoc.v:0.0-0.0"
145413           case
145414             assign { } { }
145415             assign { } { }
145416             assign { } { }
145417             assign { } { }
145418             assign { } { }
145419             assign { } { }
145420             assign { } { }
145421             assign { } { }
145422             assign { } { }
145423             assign { } { }
145424             assign { } { }
145425             assign { } { }
145426             assign { } { }
145427             assign { } { }
145428             assign { } { }
145429             assign { } { }
145430             assign { } { }
145431             assign { } { }
145432             assign { } { }
145433             assign { } { }
145434             assign { } { }
145435             assign { } { }
145436             assign { } { }
145437             assign { } { }
145438             assign { } { }
145439             assign { } { }
145440             assign { } { }
145441             assign { } { }
145442             assign { } { }
145443             assign { } { }
145444             assign { } { }
145445             assign { } { }
145446             assign { } { }
145447             assign { } { }
145448             assign { } { }
145449             assign { } { }
145450             assign { } { }
145451             assign { } { }
145452             assign { } { }
145453             assign { } { }
145454             assign { } { }
145455             assign { } { }
145456             assign { } { }
145457             assign { } { }
145458             assign { } { }
145459             assign { } { }
145460             assign { } { }
145461             assign { } { }
145462             assign { } { }
145463             assign { } { }
145464             assign { } { }
145465             assign { } { }
145466             assign { } { }
145467             assign { } { }
145468             assign { } { }
145469             assign { } { }
145470             assign { } { }
145471             assign { } { }
145472             assign { } { }
145473             assign { $2\core_core_is_32bit$next[0:0]$1987 $2\core_core_cr_wr_ok$next[0:0]$1974 $2\core_core_cr_wr$next[7:0]$1973 $2\core_core_cr_rd_ok$next[0:0]$1972 $2\core_core_cr_rd$next[7:0]$1971 $2\core_core_trapaddr$next[12:0]$1994 $2\core_core_exc_$signal$56$next[0:0]$1981 $2\core_core_exc_$signal$55$next[0:0]$1980 $2\core_core_exc_$signal$54$next[0:0]$1979 $2\core_core_exc_$signal$53$next[0:0]$1978 $2\core_core_exc_$signal$52$next[0:0]$1977 $2\core_core_exc_$signal$51$next[0:0]$1976 $2\core_core_exc_$signal$50$next[0:0]$1975 $2\core_core_exc_$signal$next[0:0]$1982 $2\core_core_traptype$next[7:0]$1995 $2\core_core_input_carry$next[1:0]$1984 $2\core_core_oe_ok$next[0:0]$1991 $2\core_core_oe$next[0:0]$1990 $2\core_core_rc_ok$next[0:0]$1993 $2\core_core_rc$next[0:0]$1992 $2\core_core_lk$next[0:0]$1988 $2\core_core_fn_unit$next[11:0]$1983 $2\core_core_insn_type$next[6:0]$1986 $2\core_core_insn$next[31:0]$1985 $2\core_core_cia$next[63:0]$1970 $2\core_core_msr$next[63:0]$1989 $2\core_cr_out_ok$next[0:0]$2003 $2\core_cr_out$next[2:0]$2002 $2\core_cr_in2_ok$49$next[0:0]$2000 $2\core_cr_in2$48$next[2:0]$1998 $2\core_cr_in2_ok$next[0:0]$2001 $2\core_cr_in2$next[2:0]$1999 $2\core_cr_in1_ok$next[0:0]$1997 $2\core_cr_in1$next[2:0]$1996 $2\core_fasto2_ok$next[0:0]$2013 $2\core_fasto2$next[2:0]$2012 $2\core_fasto1_ok$next[0:0]$2011 $2\core_fasto1$next[2:0]$2010 $2\core_fast2_ok$next[0:0]$2009 $2\core_fast2$next[2:0]$2008 $2\core_fast1_ok$next[0:0]$2007 $2\core_fast1$next[2:0]$2006 $2\core_xer_out$next[0:0]$2027 $2\core_xer_in$next[2:0]$2026 $2\core_spr1_ok$next[0:0]$2023 $2\core_spr1$next[9:0]$2022 $2\core_spro_ok$next[0:0]$2025 $2\core_spro$next[9:0]$2024 $2\core_reg3_ok$next[0:0]$2019 $2\core_reg3$next[4:0]$2018 $2\core_reg2_ok$next[0:0]$2017 $2\core_reg2$next[4:0]$2016 $2\core_reg1_ok$next[0:0]$2015 $2\core_reg1$next[4:0]$2014 $2\core_ea_ok$next[0:0]$2005 $2\core_ea$next[4:0]$2004 $2\core_rego_ok$next[0:0]$2021 $2\core_rego$next[4:0]$2020 $2\core_asmcode$next[7:0]$1969 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$9 \dec2_exc_$signal$8 \dec2_exc_$signal$7 \dec2_exc_$signal$6 \dec2_exc_$signal$5 \dec2_exc_$signal$4 \dec2_exc_$signal$3 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
145474         end
145475       attribute \src "libresoc.v:0.0-0.0"
145476       case 2'11
145477         assign { } { }
145478         assign { } { }
145479         assign { } { }
145480         assign { } { }
145481         assign { } { }
145482         assign { } { }
145483         assign { } { }
145484         assign { } { }
145485         assign { } { }
145486         assign { } { }
145487         assign { } { }
145488         assign { } { }
145489         assign { } { }
145490         assign { } { }
145491         assign { } { }
145492         assign { } { }
145493         assign { } { }
145494         assign { } { }
145495         assign { } { }
145496         assign { } { }
145497         assign { } { }
145498         assign { } { }
145499         assign { } { }
145500         assign { } { }
145501         assign { } { }
145502         assign { } { }
145503         assign { } { }
145504         assign { } { }
145505         assign { } { }
145506         assign { } { }
145507         assign { } { }
145508         assign { } { }
145509         assign { } { }
145510         assign { } { }
145511         assign { } { }
145512         assign { } { }
145513         assign { } { }
145514         assign { } { }
145515         assign { } { }
145516         assign { } { }
145517         assign { } { }
145518         assign { } { }
145519         assign { } { }
145520         assign { } { }
145521         assign { } { }
145522         assign { } { }
145523         assign { } { }
145524         assign { } { }
145525         assign { } { }
145526         assign { } { }
145527         assign { } { }
145528         assign { } { }
145529         assign { } { }
145530         assign { } { }
145531         assign { } { }
145532         assign { } { }
145533         assign { } { }
145534         assign { } { }
145535         assign { } { }
145536         assign $1\core_asmcode$next[7:0]$1910 $3\core_asmcode$next[7:0]$2028
145537         assign $1\core_core_cia$next[63:0]$1911 $3\core_core_cia$next[63:0]$2029
145538         assign $1\core_core_cr_rd$next[7:0]$1912 $3\core_core_cr_rd$next[7:0]$2030
145539         assign $1\core_core_cr_rd_ok$next[0:0]$1913 $3\core_core_cr_rd_ok$next[0:0]$2031
145540         assign $1\core_core_cr_wr$next[7:0]$1914 $3\core_core_cr_wr$next[7:0]$2032
145541         assign $1\core_core_cr_wr_ok$next[0:0]$1915 $3\core_core_cr_wr_ok$next[0:0]$2033
145542         assign $1\core_core_exc_$signal$50$next[0:0]$1916 $3\core_core_exc_$signal$50$next[0:0]$2034
145543         assign $1\core_core_exc_$signal$51$next[0:0]$1917 $3\core_core_exc_$signal$51$next[0:0]$2035
145544         assign $1\core_core_exc_$signal$52$next[0:0]$1918 $3\core_core_exc_$signal$52$next[0:0]$2036
145545         assign $1\core_core_exc_$signal$53$next[0:0]$1919 $3\core_core_exc_$signal$53$next[0:0]$2037
145546         assign $1\core_core_exc_$signal$54$next[0:0]$1920 $3\core_core_exc_$signal$54$next[0:0]$2038
145547         assign $1\core_core_exc_$signal$55$next[0:0]$1921 $3\core_core_exc_$signal$55$next[0:0]$2039
145548         assign $1\core_core_exc_$signal$56$next[0:0]$1922 $3\core_core_exc_$signal$56$next[0:0]$2040
145549         assign $1\core_core_exc_$signal$next[0:0]$1923 $3\core_core_exc_$signal$next[0:0]$2041
145550         assign $1\core_core_fn_unit$next[11:0]$1924 $3\core_core_fn_unit$next[11:0]$2042
145551         assign $1\core_core_input_carry$next[1:0]$1925 $3\core_core_input_carry$next[1:0]$2043
145552         assign $1\core_core_insn$next[31:0]$1926 $3\core_core_insn$next[31:0]$2044
145553         assign $1\core_core_insn_type$next[6:0]$1927 $3\core_core_insn_type$next[6:0]$2045
145554         assign $1\core_core_is_32bit$next[0:0]$1928 $3\core_core_is_32bit$next[0:0]$2046
145555         assign $1\core_core_lk$next[0:0]$1929 $3\core_core_lk$next[0:0]$2047
145556         assign $1\core_core_msr$next[63:0]$1930 $3\core_core_msr$next[63:0]$2048
145557         assign $1\core_core_oe$next[0:0]$1931 $3\core_core_oe$next[0:0]$2049
145558         assign $1\core_core_oe_ok$next[0:0]$1932 $3\core_core_oe_ok$next[0:0]$2050
145559         assign $1\core_core_rc$next[0:0]$1933 $3\core_core_rc$next[0:0]$2051
145560         assign $1\core_core_rc_ok$next[0:0]$1934 $3\core_core_rc_ok$next[0:0]$2052
145561         assign $1\core_core_trapaddr$next[12:0]$1935 $3\core_core_trapaddr$next[12:0]$2053
145562         assign $1\core_core_traptype$next[7:0]$1936 $3\core_core_traptype$next[7:0]$2054
145563         assign $1\core_cr_in1$next[2:0]$1937 $3\core_cr_in1$next[2:0]$2055
145564         assign $1\core_cr_in1_ok$next[0:0]$1938 $3\core_cr_in1_ok$next[0:0]$2056
145565         assign $1\core_cr_in2$48$next[2:0]$1939 $3\core_cr_in2$48$next[2:0]$2057
145566         assign $1\core_cr_in2$next[2:0]$1940 $3\core_cr_in2$next[2:0]$2058
145567         assign $1\core_cr_in2_ok$49$next[0:0]$1941 $3\core_cr_in2_ok$49$next[0:0]$2059
145568         assign $1\core_cr_in2_ok$next[0:0]$1942 $3\core_cr_in2_ok$next[0:0]$2060
145569         assign $1\core_cr_out$next[2:0]$1943 $3\core_cr_out$next[2:0]$2061
145570         assign $1\core_cr_out_ok$next[0:0]$1944 $3\core_cr_out_ok$next[0:0]$2062
145571         assign $1\core_ea$next[4:0]$1945 $3\core_ea$next[4:0]$2063
145572         assign $1\core_ea_ok$next[0:0]$1946 $3\core_ea_ok$next[0:0]$2064
145573         assign $1\core_fast1$next[2:0]$1947 $3\core_fast1$next[2:0]$2065
145574         assign $1\core_fast1_ok$next[0:0]$1948 $3\core_fast1_ok$next[0:0]$2066
145575         assign $1\core_fast2$next[2:0]$1949 $3\core_fast2$next[2:0]$2067
145576         assign $1\core_fast2_ok$next[0:0]$1950 $3\core_fast2_ok$next[0:0]$2068
145577         assign $1\core_fasto1$next[2:0]$1951 $3\core_fasto1$next[2:0]$2069
145578         assign $1\core_fasto1_ok$next[0:0]$1952 $3\core_fasto1_ok$next[0:0]$2070
145579         assign $1\core_fasto2$next[2:0]$1953 $3\core_fasto2$next[2:0]$2071
145580         assign $1\core_fasto2_ok$next[0:0]$1954 $3\core_fasto2_ok$next[0:0]$2072
145581         assign $1\core_reg1$next[4:0]$1955 $3\core_reg1$next[4:0]$2073
145582         assign $1\core_reg1_ok$next[0:0]$1956 $3\core_reg1_ok$next[0:0]$2074
145583         assign $1\core_reg2$next[4:0]$1957 $3\core_reg2$next[4:0]$2075
145584         assign $1\core_reg2_ok$next[0:0]$1958 $3\core_reg2_ok$next[0:0]$2076
145585         assign $1\core_reg3$next[4:0]$1959 $3\core_reg3$next[4:0]$2077
145586         assign $1\core_reg3_ok$next[0:0]$1960 $3\core_reg3_ok$next[0:0]$2078
145587         assign $1\core_rego$next[4:0]$1961 $3\core_rego$next[4:0]$2079
145588         assign $1\core_rego_ok$next[0:0]$1962 $3\core_rego_ok$next[0:0]$2080
145589         assign $1\core_spr1$next[9:0]$1963 $3\core_spr1$next[9:0]$2081
145590         assign $1\core_spr1_ok$next[0:0]$1964 $3\core_spr1_ok$next[0:0]$2082
145591         assign $1\core_spro$next[9:0]$1965 $3\core_spro$next[9:0]$2083
145592         assign $1\core_spro_ok$next[0:0]$1966 $3\core_spro_ok$next[0:0]$2084
145593         assign $1\core_xer_in$next[2:0]$1967 $3\core_xer_in$next[2:0]$2085
145594         assign $1\core_xer_out$next[0:0]$1968 $3\core_xer_out$next[0:0]$2086
145595         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
145596         switch \$57
145597           attribute \src "libresoc.v:0.0-0.0"
145598           case 1'1
145599             assign { } { }
145600             assign { } { }
145601             assign { } { }
145602             assign { } { }
145603             assign { } { }
145604             assign { } { }
145605             assign { } { }
145606             assign { } { }
145607             assign { } { }
145608             assign { } { }
145609             assign { } { }
145610             assign { } { }
145611             assign { } { }
145612             assign { } { }
145613             assign { } { }
145614             assign { } { }
145615             assign { } { }
145616             assign { } { }
145617             assign { } { }
145618             assign { } { }
145619             assign { } { }
145620             assign { } { }
145621             assign { } { }
145622             assign { } { }
145623             assign { } { }
145624             assign { } { }
145625             assign { } { }
145626             assign { } { }
145627             assign { } { }
145628             assign { } { }
145629             assign { } { }
145630             assign { } { }
145631             assign { } { }
145632             assign { } { }
145633             assign { } { }
145634             assign { } { }
145635             assign { } { }
145636             assign { } { }
145637             assign { } { }
145638             assign { } { }
145639             assign { } { }
145640             assign { } { }
145641             assign { } { }
145642             assign { } { }
145643             assign { } { }
145644             assign { } { }
145645             assign { } { }
145646             assign { } { }
145647             assign { } { }
145648             assign { } { }
145649             assign { } { }
145650             assign { } { }
145651             assign { } { }
145652             assign { } { }
145653             assign { } { }
145654             assign { } { }
145655             assign { } { }
145656             assign { } { }
145657             assign { } { }
145658             assign { $3\core_core_is_32bit$next[0:0]$2046 $3\core_core_cr_wr_ok$next[0:0]$2033 $3\core_core_cr_wr$next[7:0]$2032 $3\core_core_cr_rd_ok$next[0:0]$2031 $3\core_core_cr_rd$next[7:0]$2030 $3\core_core_trapaddr$next[12:0]$2053 $3\core_core_exc_$signal$56$next[0:0]$2040 $3\core_core_exc_$signal$55$next[0:0]$2039 $3\core_core_exc_$signal$54$next[0:0]$2038 $3\core_core_exc_$signal$53$next[0:0]$2037 $3\core_core_exc_$signal$52$next[0:0]$2036 $3\core_core_exc_$signal$51$next[0:0]$2035 $3\core_core_exc_$signal$50$next[0:0]$2034 $3\core_core_exc_$signal$next[0:0]$2041 $3\core_core_traptype$next[7:0]$2054 $3\core_core_input_carry$next[1:0]$2043 $3\core_core_oe_ok$next[0:0]$2050 $3\core_core_oe$next[0:0]$2049 $3\core_core_rc_ok$next[0:0]$2052 $3\core_core_rc$next[0:0]$2051 $3\core_core_lk$next[0:0]$2047 $3\core_core_fn_unit$next[11:0]$2042 $3\core_core_insn_type$next[6:0]$2045 $3\core_core_insn$next[31:0]$2044 $3\core_core_cia$next[63:0]$2029 $3\core_core_msr$next[63:0]$2048 $3\core_cr_out_ok$next[0:0]$2062 $3\core_cr_out$next[2:0]$2061 $3\core_cr_in2_ok$49$next[0:0]$2059 $3\core_cr_in2$48$next[2:0]$2057 $3\core_cr_in2_ok$next[0:0]$2060 $3\core_cr_in2$next[2:0]$2058 $3\core_cr_in1_ok$next[0:0]$2056 $3\core_cr_in1$next[2:0]$2055 $3\core_fasto2_ok$next[0:0]$2072 $3\core_fasto2$next[2:0]$2071 $3\core_fasto1_ok$next[0:0]$2070 $3\core_fasto1$next[2:0]$2069 $3\core_fast2_ok$next[0:0]$2068 $3\core_fast2$next[2:0]$2067 $3\core_fast1_ok$next[0:0]$2066 $3\core_fast1$next[2:0]$2065 $3\core_xer_out$next[0:0]$2086 $3\core_xer_in$next[2:0]$2085 $3\core_spr1_ok$next[0:0]$2082 $3\core_spr1$next[9:0]$2081 $3\core_spro_ok$next[0:0]$2084 $3\core_spro$next[9:0]$2083 $3\core_reg3_ok$next[0:0]$2078 $3\core_reg3$next[4:0]$2077 $3\core_reg2_ok$next[0:0]$2076 $3\core_reg2$next[4:0]$2075 $3\core_reg1_ok$next[0:0]$2074 $3\core_reg1$next[4:0]$2073 $3\core_ea_ok$next[0:0]$2064 $3\core_ea$next[4:0]$2063 $3\core_rego_ok$next[0:0]$2080 $3\core_rego$next[4:0]$2079 $3\core_asmcode$next[7:0]$2028 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
145659           case
145660             assign $3\core_asmcode$next[7:0]$2028 \core_asmcode
145661             assign $3\core_core_cia$next[63:0]$2029 \core_core_cia
145662             assign $3\core_core_cr_rd$next[7:0]$2030 \core_core_cr_rd
145663             assign $3\core_core_cr_rd_ok$next[0:0]$2031 \core_core_cr_rd_ok
145664             assign $3\core_core_cr_wr$next[7:0]$2032 \core_core_cr_wr
145665             assign $3\core_core_cr_wr_ok$next[0:0]$2033 \core_core_cr_wr_ok
145666             assign $3\core_core_exc_$signal$50$next[0:0]$2034 \core_core_exc_$signal$50
145667             assign $3\core_core_exc_$signal$51$next[0:0]$2035 \core_core_exc_$signal$51
145668             assign $3\core_core_exc_$signal$52$next[0:0]$2036 \core_core_exc_$signal$52
145669             assign $3\core_core_exc_$signal$53$next[0:0]$2037 \core_core_exc_$signal$53
145670             assign $3\core_core_exc_$signal$54$next[0:0]$2038 \core_core_exc_$signal$54
145671             assign $3\core_core_exc_$signal$55$next[0:0]$2039 \core_core_exc_$signal$55
145672             assign $3\core_core_exc_$signal$56$next[0:0]$2040 \core_core_exc_$signal$56
145673             assign $3\core_core_exc_$signal$next[0:0]$2041 \core_core_exc_$signal
145674             assign $3\core_core_fn_unit$next[11:0]$2042 \core_core_fn_unit
145675             assign $3\core_core_input_carry$next[1:0]$2043 \core_core_input_carry
145676             assign $3\core_core_insn$next[31:0]$2044 \core_core_insn
145677             assign $3\core_core_insn_type$next[6:0]$2045 \core_core_insn_type
145678             assign $3\core_core_is_32bit$next[0:0]$2046 \core_core_is_32bit
145679             assign $3\core_core_lk$next[0:0]$2047 \core_core_lk
145680             assign $3\core_core_msr$next[63:0]$2048 \core_core_msr
145681             assign $3\core_core_oe$next[0:0]$2049 \core_core_oe
145682             assign $3\core_core_oe_ok$next[0:0]$2050 \core_core_oe_ok
145683             assign $3\core_core_rc$next[0:0]$2051 \core_core_rc
145684             assign $3\core_core_rc_ok$next[0:0]$2052 \core_core_rc_ok
145685             assign $3\core_core_trapaddr$next[12:0]$2053 \core_core_trapaddr
145686             assign $3\core_core_traptype$next[7:0]$2054 \core_core_traptype
145687             assign $3\core_cr_in1$next[2:0]$2055 \core_cr_in1
145688             assign $3\core_cr_in1_ok$next[0:0]$2056 \core_cr_in1_ok
145689             assign $3\core_cr_in2$48$next[2:0]$2057 \core_cr_in2$48
145690             assign $3\core_cr_in2$next[2:0]$2058 \core_cr_in2
145691             assign $3\core_cr_in2_ok$49$next[0:0]$2059 \core_cr_in2_ok$49
145692             assign $3\core_cr_in2_ok$next[0:0]$2060 \core_cr_in2_ok
145693             assign $3\core_cr_out$next[2:0]$2061 \core_cr_out
145694             assign $3\core_cr_out_ok$next[0:0]$2062 \core_cr_out_ok
145695             assign $3\core_ea$next[4:0]$2063 \core_ea
145696             assign $3\core_ea_ok$next[0:0]$2064 \core_ea_ok
145697             assign $3\core_fast1$next[2:0]$2065 \core_fast1
145698             assign $3\core_fast1_ok$next[0:0]$2066 \core_fast1_ok
145699             assign $3\core_fast2$next[2:0]$2067 \core_fast2
145700             assign $3\core_fast2_ok$next[0:0]$2068 \core_fast2_ok
145701             assign $3\core_fasto1$next[2:0]$2069 \core_fasto1
145702             assign $3\core_fasto1_ok$next[0:0]$2070 \core_fasto1_ok
145703             assign $3\core_fasto2$next[2:0]$2071 \core_fasto2
145704             assign $3\core_fasto2_ok$next[0:0]$2072 \core_fasto2_ok
145705             assign $3\core_reg1$next[4:0]$2073 \core_reg1
145706             assign $3\core_reg1_ok$next[0:0]$2074 \core_reg1_ok
145707             assign $3\core_reg2$next[4:0]$2075 \core_reg2
145708             assign $3\core_reg2_ok$next[0:0]$2076 \core_reg2_ok
145709             assign $3\core_reg3$next[4:0]$2077 \core_reg3
145710             assign $3\core_reg3_ok$next[0:0]$2078 \core_reg3_ok
145711             assign $3\core_rego$next[4:0]$2079 \core_rego
145712             assign $3\core_rego_ok$next[0:0]$2080 \core_rego_ok
145713             assign $3\core_spr1$next[9:0]$2081 \core_spr1
145714             assign $3\core_spr1_ok$next[0:0]$2082 \core_spr1_ok
145715             assign $3\core_spro$next[9:0]$2083 \core_spro
145716             assign $3\core_spro_ok$next[0:0]$2084 \core_spro_ok
145717             assign $3\core_xer_in$next[2:0]$2085 \core_xer_in
145718             assign $3\core_xer_out$next[0:0]$2086 \core_xer_out
145719         end
145720       case
145721         assign $1\core_asmcode$next[7:0]$1910 \core_asmcode
145722         assign $1\core_core_cia$next[63:0]$1911 \core_core_cia
145723         assign $1\core_core_cr_rd$next[7:0]$1912 \core_core_cr_rd
145724         assign $1\core_core_cr_rd_ok$next[0:0]$1913 \core_core_cr_rd_ok
145725         assign $1\core_core_cr_wr$next[7:0]$1914 \core_core_cr_wr
145726         assign $1\core_core_cr_wr_ok$next[0:0]$1915 \core_core_cr_wr_ok
145727         assign $1\core_core_exc_$signal$50$next[0:0]$1916 \core_core_exc_$signal$50
145728         assign $1\core_core_exc_$signal$51$next[0:0]$1917 \core_core_exc_$signal$51
145729         assign $1\core_core_exc_$signal$52$next[0:0]$1918 \core_core_exc_$signal$52
145730         assign $1\core_core_exc_$signal$53$next[0:0]$1919 \core_core_exc_$signal$53
145731         assign $1\core_core_exc_$signal$54$next[0:0]$1920 \core_core_exc_$signal$54
145732         assign $1\core_core_exc_$signal$55$next[0:0]$1921 \core_core_exc_$signal$55
145733         assign $1\core_core_exc_$signal$56$next[0:0]$1922 \core_core_exc_$signal$56
145734         assign $1\core_core_exc_$signal$next[0:0]$1923 \core_core_exc_$signal
145735         assign $1\core_core_fn_unit$next[11:0]$1924 \core_core_fn_unit
145736         assign $1\core_core_input_carry$next[1:0]$1925 \core_core_input_carry
145737         assign $1\core_core_insn$next[31:0]$1926 \core_core_insn
145738         assign $1\core_core_insn_type$next[6:0]$1927 \core_core_insn_type
145739         assign $1\core_core_is_32bit$next[0:0]$1928 \core_core_is_32bit
145740         assign $1\core_core_lk$next[0:0]$1929 \core_core_lk
145741         assign $1\core_core_msr$next[63:0]$1930 \core_core_msr
145742         assign $1\core_core_oe$next[0:0]$1931 \core_core_oe
145743         assign $1\core_core_oe_ok$next[0:0]$1932 \core_core_oe_ok
145744         assign $1\core_core_rc$next[0:0]$1933 \core_core_rc
145745         assign $1\core_core_rc_ok$next[0:0]$1934 \core_core_rc_ok
145746         assign $1\core_core_trapaddr$next[12:0]$1935 \core_core_trapaddr
145747         assign $1\core_core_traptype$next[7:0]$1936 \core_core_traptype
145748         assign $1\core_cr_in1$next[2:0]$1937 \core_cr_in1
145749         assign $1\core_cr_in1_ok$next[0:0]$1938 \core_cr_in1_ok
145750         assign $1\core_cr_in2$48$next[2:0]$1939 \core_cr_in2$48
145751         assign $1\core_cr_in2$next[2:0]$1940 \core_cr_in2
145752         assign $1\core_cr_in2_ok$49$next[0:0]$1941 \core_cr_in2_ok$49
145753         assign $1\core_cr_in2_ok$next[0:0]$1942 \core_cr_in2_ok
145754         assign $1\core_cr_out$next[2:0]$1943 \core_cr_out
145755         assign $1\core_cr_out_ok$next[0:0]$1944 \core_cr_out_ok
145756         assign $1\core_ea$next[4:0]$1945 \core_ea
145757         assign $1\core_ea_ok$next[0:0]$1946 \core_ea_ok
145758         assign $1\core_fast1$next[2:0]$1947 \core_fast1
145759         assign $1\core_fast1_ok$next[0:0]$1948 \core_fast1_ok
145760         assign $1\core_fast2$next[2:0]$1949 \core_fast2
145761         assign $1\core_fast2_ok$next[0:0]$1950 \core_fast2_ok
145762         assign $1\core_fasto1$next[2:0]$1951 \core_fasto1
145763         assign $1\core_fasto1_ok$next[0:0]$1952 \core_fasto1_ok
145764         assign $1\core_fasto2$next[2:0]$1953 \core_fasto2
145765         assign $1\core_fasto2_ok$next[0:0]$1954 \core_fasto2_ok
145766         assign $1\core_reg1$next[4:0]$1955 \core_reg1
145767         assign $1\core_reg1_ok$next[0:0]$1956 \core_reg1_ok
145768         assign $1\core_reg2$next[4:0]$1957 \core_reg2
145769         assign $1\core_reg2_ok$next[0:0]$1958 \core_reg2_ok
145770         assign $1\core_reg3$next[4:0]$1959 \core_reg3
145771         assign $1\core_reg3_ok$next[0:0]$1960 \core_reg3_ok
145772         assign $1\core_rego$next[4:0]$1961 \core_rego
145773         assign $1\core_rego_ok$next[0:0]$1962 \core_rego_ok
145774         assign $1\core_spr1$next[9:0]$1963 \core_spr1
145775         assign $1\core_spr1_ok$next[0:0]$1964 \core_spr1_ok
145776         assign $1\core_spro$next[9:0]$1965 \core_spro
145777         assign $1\core_spro_ok$next[0:0]$1966 \core_spro_ok
145778         assign $1\core_xer_in$next[2:0]$1967 \core_xer_in
145779         assign $1\core_xer_out$next[0:0]$1968 \core_xer_out
145780     end
145781     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
145782     switch \rst
145783       attribute \src "libresoc.v:0.0-0.0"
145784       case 1'1
145785         assign { } { }
145786         assign { } { }
145787         assign { } { }
145788         assign { } { }
145789         assign { } { }
145790         assign { } { }
145791         assign { } { }
145792         assign { } { }
145793         assign { } { }
145794         assign { } { }
145795         assign { } { }
145796         assign { } { }
145797         assign { } { }
145798         assign { } { }
145799         assign { } { }
145800         assign { } { }
145801         assign { } { }
145802         assign { } { }
145803         assign { } { }
145804         assign { } { }
145805         assign { } { }
145806         assign { } { }
145807         assign { } { }
145808         assign { } { }
145809         assign { } { }
145810         assign { } { }
145811         assign { } { }
145812         assign $4\core_rego_ok$next[0:0]$2111 1'0
145813         assign $4\core_ea_ok$next[0:0]$2103 1'0
145814         assign $4\core_reg1_ok$next[0:0]$2108 1'0
145815         assign $4\core_reg2_ok$next[0:0]$2109 1'0
145816         assign $4\core_reg3_ok$next[0:0]$2110 1'0
145817         assign $4\core_spro_ok$next[0:0]$2113 1'0
145818         assign $4\core_spr1_ok$next[0:0]$2112 1'0
145819         assign $4\core_fast1_ok$next[0:0]$2104 1'0
145820         assign $4\core_fast2_ok$next[0:0]$2105 1'0
145821         assign $4\core_fasto1_ok$next[0:0]$2106 1'0
145822         assign $4\core_fasto2_ok$next[0:0]$2107 1'0
145823         assign $4\core_cr_in1_ok$next[0:0]$2099 1'0
145824         assign $4\core_cr_in2_ok$next[0:0]$2101 1'0
145825         assign $4\core_cr_in2_ok$49$next[0:0]$2100 1'0
145826         assign $4\core_cr_out_ok$next[0:0]$2102 1'0
145827         assign $4\core_core_rc_ok$next[0:0]$2098 1'0
145828         assign $4\core_core_oe_ok$next[0:0]$2097 1'0
145829         assign $4\core_core_exc_$signal$next[0:0]$2096 1'0
145830         assign $4\core_core_exc_$signal$50$next[0:0]$2089 1'0
145831         assign $4\core_core_exc_$signal$51$next[0:0]$2090 1'0
145832         assign $4\core_core_exc_$signal$52$next[0:0]$2091 1'0
145833         assign $4\core_core_exc_$signal$53$next[0:0]$2092 1'0
145834         assign $4\core_core_exc_$signal$54$next[0:0]$2093 1'0
145835         assign $4\core_core_exc_$signal$55$next[0:0]$2094 1'0
145836         assign $4\core_core_exc_$signal$56$next[0:0]$2095 1'0
145837         assign $4\core_core_cr_rd_ok$next[0:0]$2087 1'0
145838         assign $4\core_core_cr_wr_ok$next[0:0]$2088 1'0
145839       case
145840         assign $4\core_core_cr_rd_ok$next[0:0]$2087 $1\core_core_cr_rd_ok$next[0:0]$1913
145841         assign $4\core_core_cr_wr_ok$next[0:0]$2088 $1\core_core_cr_wr_ok$next[0:0]$1915
145842         assign $4\core_core_exc_$signal$50$next[0:0]$2089 $1\core_core_exc_$signal$50$next[0:0]$1916
145843         assign $4\core_core_exc_$signal$51$next[0:0]$2090 $1\core_core_exc_$signal$51$next[0:0]$1917
145844         assign $4\core_core_exc_$signal$52$next[0:0]$2091 $1\core_core_exc_$signal$52$next[0:0]$1918
145845         assign $4\core_core_exc_$signal$53$next[0:0]$2092 $1\core_core_exc_$signal$53$next[0:0]$1919
145846         assign $4\core_core_exc_$signal$54$next[0:0]$2093 $1\core_core_exc_$signal$54$next[0:0]$1920
145847         assign $4\core_core_exc_$signal$55$next[0:0]$2094 $1\core_core_exc_$signal$55$next[0:0]$1921
145848         assign $4\core_core_exc_$signal$56$next[0:0]$2095 $1\core_core_exc_$signal$56$next[0:0]$1922
145849         assign $4\core_core_exc_$signal$next[0:0]$2096 $1\core_core_exc_$signal$next[0:0]$1923
145850         assign $4\core_core_oe_ok$next[0:0]$2097 $1\core_core_oe_ok$next[0:0]$1932
145851         assign $4\core_core_rc_ok$next[0:0]$2098 $1\core_core_rc_ok$next[0:0]$1934
145852         assign $4\core_cr_in1_ok$next[0:0]$2099 $1\core_cr_in1_ok$next[0:0]$1938
145853         assign $4\core_cr_in2_ok$49$next[0:0]$2100 $1\core_cr_in2_ok$49$next[0:0]$1941
145854         assign $4\core_cr_in2_ok$next[0:0]$2101 $1\core_cr_in2_ok$next[0:0]$1942
145855         assign $4\core_cr_out_ok$next[0:0]$2102 $1\core_cr_out_ok$next[0:0]$1944
145856         assign $4\core_ea_ok$next[0:0]$2103 $1\core_ea_ok$next[0:0]$1946
145857         assign $4\core_fast1_ok$next[0:0]$2104 $1\core_fast1_ok$next[0:0]$1948
145858         assign $4\core_fast2_ok$next[0:0]$2105 $1\core_fast2_ok$next[0:0]$1950
145859         assign $4\core_fasto1_ok$next[0:0]$2106 $1\core_fasto1_ok$next[0:0]$1952
145860         assign $4\core_fasto2_ok$next[0:0]$2107 $1\core_fasto2_ok$next[0:0]$1954
145861         assign $4\core_reg1_ok$next[0:0]$2108 $1\core_reg1_ok$next[0:0]$1956
145862         assign $4\core_reg2_ok$next[0:0]$2109 $1\core_reg2_ok$next[0:0]$1958
145863         assign $4\core_reg3_ok$next[0:0]$2110 $1\core_reg3_ok$next[0:0]$1960
145864         assign $4\core_rego_ok$next[0:0]$2111 $1\core_rego_ok$next[0:0]$1962
145865         assign $4\core_spr1_ok$next[0:0]$2112 $1\core_spr1_ok$next[0:0]$1964
145866         assign $4\core_spro_ok$next[0:0]$2113 $1\core_spro_ok$next[0:0]$1966
145867     end
145868     sync always
145869       update \core_asmcode$next $0\core_asmcode$next[7:0]$1851
145870       update \core_core_cia$next $0\core_core_cia$next[63:0]$1852
145871       update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1853
145872       update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1854
145873       update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1855
145874       update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1856
145875       update \core_core_exc_$signal$50$next $0\core_core_exc_$signal$50$next[0:0]$1857
145876       update \core_core_exc_$signal$51$next $0\core_core_exc_$signal$51$next[0:0]$1858
145877       update \core_core_exc_$signal$52$next $0\core_core_exc_$signal$52$next[0:0]$1859
145878       update \core_core_exc_$signal$53$next $0\core_core_exc_$signal$53$next[0:0]$1860
145879       update \core_core_exc_$signal$54$next $0\core_core_exc_$signal$54$next[0:0]$1861
145880       update \core_core_exc_$signal$55$next $0\core_core_exc_$signal$55$next[0:0]$1862
145881       update \core_core_exc_$signal$56$next $0\core_core_exc_$signal$56$next[0:0]$1863
145882       update \core_core_exc_$signal$next $0\core_core_exc_$signal$next[0:0]$1864
145883       update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1865
145884       update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1866
145885       update \core_core_insn$next $0\core_core_insn$next[31:0]$1867
145886       update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1868
145887       update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1869
145888       update \core_core_lk$next $0\core_core_lk$next[0:0]$1870
145889       update \core_core_msr$next $0\core_core_msr$next[63:0]$1871
145890       update \core_core_oe$next $0\core_core_oe$next[0:0]$1872
145891       update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1873
145892       update \core_core_rc$next $0\core_core_rc$next[0:0]$1874
145893       update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1875
145894       update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1876
145895       update \core_core_traptype$next $0\core_core_traptype$next[7:0]$1877
145896       update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1878
145897       update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1879
145898       update \core_cr_in2$48$next $0\core_cr_in2$48$next[2:0]$1880
145899       update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1881
145900       update \core_cr_in2_ok$49$next $0\core_cr_in2_ok$49$next[0:0]$1882
145901       update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1883
145902       update \core_cr_out$next $0\core_cr_out$next[2:0]$1884
145903       update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1885
145904       update \core_ea$next $0\core_ea$next[4:0]$1886
145905       update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1887
145906       update \core_fast1$next $0\core_fast1$next[2:0]$1888
145907       update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1889
145908       update \core_fast2$next $0\core_fast2$next[2:0]$1890
145909       update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1891
145910       update \core_fasto1$next $0\core_fasto1$next[2:0]$1892
145911       update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1893
145912       update \core_fasto2$next $0\core_fasto2$next[2:0]$1894
145913       update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1895
145914       update \core_reg1$next $0\core_reg1$next[4:0]$1896
145915       update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1897
145916       update \core_reg2$next $0\core_reg2$next[4:0]$1898
145917       update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1899
145918       update \core_reg3$next $0\core_reg3$next[4:0]$1900
145919       update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1901
145920       update \core_rego$next $0\core_rego$next[4:0]$1902
145921       update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1903
145922       update \core_spr1$next $0\core_spr1$next[9:0]$1904
145923       update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1905
145924       update \core_spro$next $0\core_spro$next[9:0]$1906
145925       update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1907
145926       update \core_xer_in$next $0\core_xer_in$next[2:0]$1908
145927       update \core_xer_out$next $0\core_xer_out$next[0:0]$1909
145928   end
145929   attribute \src "libresoc.v:52157.3-52165.6"
145930   process $proc$libresoc.v:52157$2114
145931     assign { } { }
145932     assign { } { }
145933     assign $0\jtag_dmi0__ack_o$next[0:0]$2115 $1\jtag_dmi0__ack_o$next[0:0]$2116
145934     attribute \src "libresoc.v:52158.5-52158.29"
145935     switch \initial
145936       attribute \src "libresoc.v:52158.9-52158.17"
145937       case 1'1
145938       case
145939     end
145940     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
145941     switch \rst
145942       attribute \src "libresoc.v:0.0-0.0"
145943       case 1'1
145944         assign { } { }
145945         assign $1\jtag_dmi0__ack_o$next[0:0]$2116 1'0
145946       case
145947         assign $1\jtag_dmi0__ack_o$next[0:0]$2116 \dbg_dmi_ack_o
145948     end
145949     sync always
145950       update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$2115
145951   end
145952   attribute \src "libresoc.v:52166.3-52174.6"
145953   process $proc$libresoc.v:52166$2117
145954     assign { } { }
145955     assign { } { }
145956     assign $0\jtag_dmi0__dout$next[63:0]$2118 $1\jtag_dmi0__dout$next[63:0]$2119
145957     attribute \src "libresoc.v:52167.5-52167.29"
145958     switch \initial
145959       attribute \src "libresoc.v:52167.9-52167.17"
145960       case 1'1
145961       case
145962     end
145963     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
145964     switch \rst
145965       attribute \src "libresoc.v:0.0-0.0"
145966       case 1'1
145967         assign { } { }
145968         assign $1\jtag_dmi0__dout$next[63:0]$2119 64'0000000000000000000000000000000000000000000000000000000000000000
145969       case
145970         assign $1\jtag_dmi0__dout$next[63:0]$2119 \dbg_dmi_dout
145971     end
145972     sync always
145973       update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$2118
145974   end
145975   attribute \src "libresoc.v:52175.3-52183.6"
145976   process $proc$libresoc.v:52175$2120
145977     assign { } { }
145978     assign { } { }
145979     assign $0\dec2_cur_eint$next[0:0]$2121 $1\dec2_cur_eint$next[0:0]$2122
145980     attribute \src "libresoc.v:52176.5-52176.29"
145981     switch \initial
145982       attribute \src "libresoc.v:52176.9-52176.17"
145983       case 1'1
145984       case
145985     end
145986     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
145987     switch \rst
145988       attribute \src "libresoc.v:0.0-0.0"
145989       case 1'1
145990         assign { } { }
145991         assign $1\dec2_cur_eint$next[0:0]$2122 1'0
145992       case
145993         assign $1\dec2_cur_eint$next[0:0]$2122 \xics_icp_core_irq_o
145994     end
145995     sync always
145996       update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$2121
145997   end
145998   attribute \src "libresoc.v:52184.3-52193.6"
145999   process $proc$libresoc.v:52184$2123
146000     assign { } { }
146001     assign { } { }
146002     assign $0\delay$next[1:0]$2124 $1\delay$next[1:0]$2125
146003     attribute \src "libresoc.v:52185.5-52185.29"
146004     switch \initial
146005       attribute \src "libresoc.v:52185.9-52185.17"
146006       case 1'1
146007       case
146008     end
146009     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174"
146010     switch \$10
146011       attribute \src "libresoc.v:0.0-0.0"
146012       case 1'1
146013         assign { } { }
146014         assign $1\delay$next[1:0]$2125 \$12 [1:0]
146015       case
146016         assign $1\delay$next[1:0]$2125 \delay
146017     end
146018     sync always
146019       update \delay$next $0\delay$next[1:0]$2124
146020   end
146021   attribute \src "libresoc.v:52194.3-52230.6"
146022   process $proc$libresoc.v:52194$2126
146023     assign { } { }
146024     assign { } { }
146025     assign { } { }
146026     assign $0\raw_insn_i$next[31:0]$2127 $4\raw_insn_i$next[31:0]$2131
146027     attribute \src "libresoc.v:52195.5-52195.29"
146028     switch \initial
146029       attribute \src "libresoc.v:52195.9-52195.17"
146030       case 1'1
146031       case
146032     end
146033     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146034     switch \fsm_state
146035       attribute \src "libresoc.v:0.0-0.0"
146036       case 2'00
146037         assign { } { }
146038         assign $1\raw_insn_i$next[31:0]$2128 0
146039       attribute \src "libresoc.v:0.0-0.0"
146040       case 2'01
146041         assign { } { }
146042         assign $1\raw_insn_i$next[31:0]$2128 $2\raw_insn_i$next[31:0]$2129
146043         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
146044         switch \imem_f_busy_o
146045           attribute \src "libresoc.v:0.0-0.0"
146046           case 1'1
146047             assign $2\raw_insn_i$next[31:0]$2129 \raw_insn_i
146048           attribute \src "libresoc.v:0.0-0.0"
146049           case
146050             assign { } { }
146051             assign $2\raw_insn_i$next[31:0]$2129 \dec2_raw_opcode_in
146052         end
146053       attribute \src "libresoc.v:0.0-0.0"
146054       case 2'11
146055         assign { } { }
146056         assign $1\raw_insn_i$next[31:0]$2128 $3\raw_insn_i$next[31:0]$2130
146057         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
146058         switch \$59
146059           attribute \src "libresoc.v:0.0-0.0"
146060           case 1'1
146061             assign { } { }
146062             assign $3\raw_insn_i$next[31:0]$2130 0
146063           case
146064             assign $3\raw_insn_i$next[31:0]$2130 \raw_insn_i
146065         end
146066       case
146067         assign $1\raw_insn_i$next[31:0]$2128 \raw_insn_i
146068     end
146069     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
146070     switch \rst
146071       attribute \src "libresoc.v:0.0-0.0"
146072       case 1'1
146073         assign { } { }
146074         assign $4\raw_insn_i$next[31:0]$2131 0
146075       case
146076         assign $4\raw_insn_i$next[31:0]$2131 $1\raw_insn_i$next[31:0]$2128
146077     end
146078     sync always
146079       update \raw_insn_i$next $0\raw_insn_i$next[31:0]$2127
146080   end
146081   attribute \src "libresoc.v:52231.3-52267.6"
146082   process $proc$libresoc.v:52231$2132
146083     assign { } { }
146084     assign { } { }
146085     assign { } { }
146086     assign $0\bigendian_i$next[0:0]$2133 $4\bigendian_i$next[0:0]$2137
146087     attribute \src "libresoc.v:52232.5-52232.29"
146088     switch \initial
146089       attribute \src "libresoc.v:52232.9-52232.17"
146090       case 1'1
146091       case
146092     end
146093     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146094     switch \fsm_state
146095       attribute \src "libresoc.v:0.0-0.0"
146096       case 2'00
146097         assign { } { }
146098         assign $1\bigendian_i$next[0:0]$2134 1'0
146099       attribute \src "libresoc.v:0.0-0.0"
146100       case 2'01
146101         assign { } { }
146102         assign $1\bigendian_i$next[0:0]$2134 $2\bigendian_i$next[0:0]$2135
146103         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
146104         switch \imem_f_busy_o
146105           attribute \src "libresoc.v:0.0-0.0"
146106           case 1'1
146107             assign $2\bigendian_i$next[0:0]$2135 \bigendian_i
146108           attribute \src "libresoc.v:0.0-0.0"
146109           case
146110             assign { } { }
146111             assign $2\bigendian_i$next[0:0]$2135 \core_bigendian_i
146112         end
146113       attribute \src "libresoc.v:0.0-0.0"
146114       case 2'11
146115         assign { } { }
146116         assign $1\bigendian_i$next[0:0]$2134 $3\bigendian_i$next[0:0]$2136
146117         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
146118         switch \$61
146119           attribute \src "libresoc.v:0.0-0.0"
146120           case 1'1
146121             assign { } { }
146122             assign $3\bigendian_i$next[0:0]$2136 1'0
146123           case
146124             assign $3\bigendian_i$next[0:0]$2136 \bigendian_i
146125         end
146126       case
146127         assign $1\bigendian_i$next[0:0]$2134 \bigendian_i
146128     end
146129     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
146130     switch \rst
146131       attribute \src "libresoc.v:0.0-0.0"
146132       case 1'1
146133         assign { } { }
146134         assign $4\bigendian_i$next[0:0]$2137 1'0
146135       case
146136         assign $4\bigendian_i$next[0:0]$2137 $1\bigendian_i$next[0:0]$2134
146137     end
146138     sync always
146139       update \bigendian_i$next $0\bigendian_i$next[0:0]$2133
146140   end
146141   attribute \src "libresoc.v:52268.3-52283.6"
146142   process $proc$libresoc.v:52268$2138
146143     assign { } { }
146144     assign { } { }
146145     assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
146146     attribute \src "libresoc.v:52269.5-52269.29"
146147     switch \initial
146148       attribute \src "libresoc.v:52269.9-52269.17"
146149       case 1'1
146150       case
146151     end
146152     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146153     switch \fsm_state
146154       attribute \src "libresoc.v:0.0-0.0"
146155       case 2'00
146156         assign { } { }
146157         assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0]
146158         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146159         switch \$67
146160           attribute \src "libresoc.v:0.0-0.0"
146161           case 1'1
146162             assign { } { }
146163             assign $2\imem_a_pc_i[47:0] \pc [47:0]
146164           case
146165             assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000
146166         end
146167       case
146168         assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000
146169     end
146170     sync always
146171       update \imem_a_pc_i $0\imem_a_pc_i[47:0]
146172   end
146173   attribute \src "libresoc.v:52284.3-52308.6"
146174   process $proc$libresoc.v:52284$2139
146175     assign { } { }
146176     assign { } { }
146177     assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
146178     attribute \src "libresoc.v:52285.5-52285.29"
146179     switch \initial
146180       attribute \src "libresoc.v:52285.9-52285.17"
146181       case 1'1
146182       case
146183     end
146184     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146185     switch \fsm_state
146186       attribute \src "libresoc.v:0.0-0.0"
146187       case 2'00
146188         assign { } { }
146189         assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0]
146190         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146191         switch \$73
146192           attribute \src "libresoc.v:0.0-0.0"
146193           case 1'1
146194             assign { } { }
146195             assign $2\imem_a_valid_i[0:0] 1'1
146196           case
146197             assign $2\imem_a_valid_i[0:0] 1'0
146198         end
146199       attribute \src "libresoc.v:0.0-0.0"
146200       case 2'01
146201         assign { } { }
146202         assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0]
146203         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
146204         switch \imem_f_busy_o
146205           attribute \src "libresoc.v:0.0-0.0"
146206           case 1'1
146207             assign { } { }
146208             assign $3\imem_a_valid_i[0:0] 1'1
146209           case
146210             assign $3\imem_a_valid_i[0:0] 1'0
146211         end
146212       case
146213         assign $1\imem_a_valid_i[0:0] 1'0
146214     end
146215     sync always
146216       update \imem_a_valid_i $0\imem_a_valid_i[0:0]
146217   end
146218   attribute \src "libresoc.v:52309.3-52333.6"
146219   process $proc$libresoc.v:52309$2140
146220     assign { } { }
146221     assign { } { }
146222     assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
146223     attribute \src "libresoc.v:52310.5-52310.29"
146224     switch \initial
146225       attribute \src "libresoc.v:52310.9-52310.17"
146226       case 1'1
146227       case
146228     end
146229     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146230     switch \fsm_state
146231       attribute \src "libresoc.v:0.0-0.0"
146232       case 2'00
146233         assign { } { }
146234         assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0]
146235         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146236         switch \$79
146237           attribute \src "libresoc.v:0.0-0.0"
146238           case 1'1
146239             assign { } { }
146240             assign $2\imem_f_valid_i[0:0] 1'1
146241           case
146242             assign $2\imem_f_valid_i[0:0] 1'0
146243         end
146244       attribute \src "libresoc.v:0.0-0.0"
146245       case 2'01
146246         assign { } { }
146247         assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0]
146248         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
146249         switch \imem_f_busy_o
146250           attribute \src "libresoc.v:0.0-0.0"
146251           case 1'1
146252             assign { } { }
146253             assign $3\imem_f_valid_i[0:0] 1'1
146254           case
146255             assign $3\imem_f_valid_i[0:0] 1'0
146256         end
146257       case
146258         assign $1\imem_f_valid_i[0:0] 1'0
146259     end
146260     sync always
146261       update \imem_f_valid_i $0\imem_f_valid_i[0:0]
146262   end
146263   attribute \src "libresoc.v:52334.3-52354.6"
146264   process $proc$libresoc.v:52334$2141
146265     assign { } { }
146266     assign { } { }
146267     assign { } { }
146268     assign $0\dec2_cur_pc$next[63:0]$2142 $3\dec2_cur_pc$next[63:0]$2145
146269     attribute \src "libresoc.v:52335.5-52335.29"
146270     switch \initial
146271       attribute \src "libresoc.v:52335.9-52335.17"
146272       case 1'1
146273       case
146274     end
146275     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146276     switch \fsm_state
146277       attribute \src "libresoc.v:0.0-0.0"
146278       case 2'00
146279         assign { } { }
146280         assign $1\dec2_cur_pc$next[63:0]$2143 $2\dec2_cur_pc$next[63:0]$2144
146281         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146282         switch \$85
146283           attribute \src "libresoc.v:0.0-0.0"
146284           case 1'1
146285             assign { } { }
146286             assign $2\dec2_cur_pc$next[63:0]$2144 \pc
146287           case
146288             assign $2\dec2_cur_pc$next[63:0]$2144 \dec2_cur_pc
146289         end
146290       case
146291         assign $1\dec2_cur_pc$next[63:0]$2143 \dec2_cur_pc
146292     end
146293     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
146294     switch \rst
146295       attribute \src "libresoc.v:0.0-0.0"
146296       case 1'1
146297         assign { } { }
146298         assign $3\dec2_cur_pc$next[63:0]$2145 64'0000000000000000000000000000000000000000000000000000000000000000
146299       case
146300         assign $3\dec2_cur_pc$next[63:0]$2145 $1\dec2_cur_pc$next[63:0]$2143
146301     end
146302     sync always
146303       update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$2142
146304   end
146305   attribute \src "libresoc.v:52355.3-52384.6"
146306   process $proc$libresoc.v:52355$2146
146307     assign { } { }
146308     assign { } { }
146309     assign { } { }
146310     assign $0\msr_read$next[0:0]$2147 $4\msr_read$next[0:0]$2151
146311     attribute \src "libresoc.v:52356.5-52356.29"
146312     switch \initial
146313       attribute \src "libresoc.v:52356.9-52356.17"
146314       case 1'1
146315       case
146316     end
146317     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146318     switch \fsm_state
146319       attribute \src "libresoc.v:0.0-0.0"
146320       case 2'00
146321         assign { } { }
146322         assign $1\msr_read$next[0:0]$2148 $2\msr_read$next[0:0]$2149
146323         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146324         switch \$91
146325           attribute \src "libresoc.v:0.0-0.0"
146326           case 1'1
146327             assign { } { }
146328             assign $2\msr_read$next[0:0]$2149 1'0
146329           case
146330             assign $2\msr_read$next[0:0]$2149 \msr_read
146331         end
146332       attribute \src "libresoc.v:0.0-0.0"
146333       case 2'01
146334         assign { } { }
146335         assign $1\msr_read$next[0:0]$2148 $3\msr_read$next[0:0]$2150
146336         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
146337         switch \$93
146338           attribute \src "libresoc.v:0.0-0.0"
146339           case 1'1
146340             assign { } { }
146341             assign $3\msr_read$next[0:0]$2150 1'1
146342           case
146343             assign $3\msr_read$next[0:0]$2150 \msr_read
146344         end
146345       case
146346         assign $1\msr_read$next[0:0]$2148 \msr_read
146347     end
146348     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
146349     switch \rst
146350       attribute \src "libresoc.v:0.0-0.0"
146351       case 1'1
146352         assign { } { }
146353         assign $4\msr_read$next[0:0]$2151 1'1
146354       case
146355         assign $4\msr_read$next[0:0]$2151 $1\msr_read$next[0:0]$2148
146356     end
146357     sync always
146358       update \msr_read$next $0\msr_read$next[0:0]$2147
146359   end
146360   attribute \src "libresoc.v:52385.3-52430.6"
146361   process $proc$libresoc.v:52385$2152
146362     assign { } { }
146363     assign { } { }
146364     assign { } { }
146365     assign $0\fsm_state$next[1:0]$2153 $5\fsm_state$next[1:0]$2158
146366     attribute \src "libresoc.v:52386.5-52386.29"
146367     switch \initial
146368       attribute \src "libresoc.v:52386.9-52386.17"
146369       case 1'1
146370       case
146371     end
146372     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146373     switch \fsm_state
146374       attribute \src "libresoc.v:0.0-0.0"
146375       case 2'00
146376         assign { } { }
146377         assign $1\fsm_state$next[1:0]$2154 $2\fsm_state$next[1:0]$2155
146378         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146379         switch \$99
146380           attribute \src "libresoc.v:0.0-0.0"
146381           case 1'1
146382             assign { } { }
146383             assign $2\fsm_state$next[1:0]$2155 2'01
146384           case
146385             assign $2\fsm_state$next[1:0]$2155 \fsm_state
146386         end
146387       attribute \src "libresoc.v:0.0-0.0"
146388       case 2'01
146389         assign { } { }
146390         assign $1\fsm_state$next[1:0]$2154 $3\fsm_state$next[1:0]$2156
146391         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
146392         switch \imem_f_busy_o
146393           attribute \src "libresoc.v:0.0-0.0"
146394           case 1'1
146395             assign $3\fsm_state$next[1:0]$2156 \fsm_state
146396           attribute \src "libresoc.v:0.0-0.0"
146397           case
146398             assign { } { }
146399             assign $3\fsm_state$next[1:0]$2156 2'10
146400         end
146401       attribute \src "libresoc.v:0.0-0.0"
146402       case 2'10
146403         assign { } { }
146404         assign $1\fsm_state$next[1:0]$2154 2'11
146405       attribute \src "libresoc.v:0.0-0.0"
146406       case 2'11
146407         assign { } { }
146408         assign $1\fsm_state$next[1:0]$2154 $4\fsm_state$next[1:0]$2157
146409         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
146410         switch \$101
146411           attribute \src "libresoc.v:0.0-0.0"
146412           case 1'1
146413             assign { } { }
146414             assign $4\fsm_state$next[1:0]$2157 2'00
146415           case
146416             assign $4\fsm_state$next[1:0]$2157 \fsm_state
146417         end
146418       case
146419         assign $1\fsm_state$next[1:0]$2154 \fsm_state
146420     end
146421     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
146422     switch \rst
146423       attribute \src "libresoc.v:0.0-0.0"
146424       case 1'1
146425         assign { } { }
146426         assign $5\fsm_state$next[1:0]$2158 2'00
146427       case
146428         assign $5\fsm_state$next[1:0]$2158 $1\fsm_state$next[1:0]$2154
146429     end
146430     sync always
146431       update \fsm_state$next $0\fsm_state$next[1:0]$2153
146432   end
146433   attribute \src "libresoc.v:52431.3-52449.6"
146434   process $proc$libresoc.v:52431$2159
146435     assign { } { }
146436     assign { } { }
146437     assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
146438     attribute \src "libresoc.v:52432.5-52432.29"
146439     switch \initial
146440       attribute \src "libresoc.v:52432.9-52432.17"
146441       case 1'1
146442       case
146443     end
146444     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146445     switch \fsm_state
146446       attribute \src "libresoc.v:0.0-0.0"
146447       case 2'00
146448         assign { } { }
146449         assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0]
146450         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146451         switch \$107
146452           attribute \src "libresoc.v:0.0-0.0"
146453           case 1'1
146454             assign $2\core_stopped_i[0:0] 1'0
146455           attribute \src "libresoc.v:0.0-0.0"
146456           case
146457             assign { } { }
146458             assign $2\core_stopped_i[0:0] 1'1
146459         end
146460       case
146461         assign $1\core_stopped_i[0:0] 1'0
146462     end
146463     sync always
146464       update \core_stopped_i $0\core_stopped_i[0:0]
146465   end
146466   attribute \src "libresoc.v:52450.3-52468.6"
146467   process $proc$libresoc.v:52450$2160
146468     assign { } { }
146469     assign { } { }
146470     assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
146471     attribute \src "libresoc.v:52451.5-52451.29"
146472     switch \initial
146473       attribute \src "libresoc.v:52451.9-52451.17"
146474       case 1'1
146475       case
146476     end
146477     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245"
146478     switch \fsm_state
146479       attribute \src "libresoc.v:0.0-0.0"
146480       case 2'00
146481         assign { } { }
146482         assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0]
146483         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
146484         switch \$113
146485           attribute \src "libresoc.v:0.0-0.0"
146486           case 1'1
146487             assign $2\dbg_core_stopped_i[0:0] 1'0
146488           attribute \src "libresoc.v:0.0-0.0"
146489           case
146490             assign { } { }
146491             assign $2\dbg_core_stopped_i[0:0] 1'1
146492         end
146493       case
146494         assign $1\dbg_core_stopped_i[0:0] 1'0
146495     end
146496     sync always
146497       update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
146498   end
146499   connect \$99 $and$libresoc.v:50779$1603_Y
146500   connect \$101 $not$libresoc.v:50780$1604_Y
146501   connect \$103 $not$libresoc.v:50781$1605_Y
146502   connect \$105 $not$libresoc.v:50782$1606_Y
146503   connect \$107 $and$libresoc.v:50783$1607_Y
146504   connect \$10 $ne$libresoc.v:50784$1608_Y
146505   connect \$109 $not$libresoc.v:50785$1609_Y
146506   connect \$111 $not$libresoc.v:50786$1610_Y
146507   connect \$113 $and$libresoc.v:50787$1611_Y
146508   connect \$115 $not$libresoc.v:50788$1612_Y
146509   connect \$118 $mul$libresoc.v:50789$1613_Y
146510   connect \$117 $shr$libresoc.v:50790$1614_Y [31:0]
146511   connect \$122 $mul$libresoc.v:50791$1615_Y
146512   connect \$121 $shr$libresoc.v:50792$1616_Y [31:0]
146513   connect \$125 $ne$libresoc.v:50793$1617_Y
146514   connect \$127 $pos$libresoc.v:50794$1619_Y
146515   connect \$129 $pos$libresoc.v:50795$1621_Y
146516   connect \$133 $sub$libresoc.v:50796$1622_Y
146517   connect \$137 $add$libresoc.v:50797$1623_Y
146518   connect \$13 $sub$libresoc.v:50798$1624_Y
146519   connect \$15 $or$libresoc.v:50799$1625_Y
146520   connect \$17 $or$libresoc.v:50800$1626_Y
146521   connect \$19 $ne$libresoc.v:50801$1627_Y
146522   connect \$21 $not$libresoc.v:50802$1628_Y
146523   connect \$23 $and$libresoc.v:50803$1629_Y
146524   connect \$26 $add$libresoc.v:50804$1630_Y
146525   connect \$28 $not$libresoc.v:50805$1631_Y
146526   connect \$30 $not$libresoc.v:50806$1632_Y
146527   connect \$32 $not$libresoc.v:50807$1633_Y
146528   connect \$34 $not$libresoc.v:50808$1634_Y
146529   connect \$36 $not$libresoc.v:50809$1635_Y
146530   connect \$38 $not$libresoc.v:50810$1636_Y
146531   connect \$40 $not$libresoc.v:50811$1637_Y
146532   connect \$42 $and$libresoc.v:50812$1638_Y
146533   connect \$45 $and$libresoc.v:50813$1639_Y
146534   connect \$44 $reduce_or$libresoc.v:50814$1640_Y
146535   connect \$57 $not$libresoc.v:50815$1641_Y
146536   connect \$59 $not$libresoc.v:50816$1642_Y
146537   connect \$61 $not$libresoc.v:50817$1643_Y
146538   connect \$63 $not$libresoc.v:50818$1644_Y
146539   connect \$65 $not$libresoc.v:50819$1645_Y
146540   connect \$67 $and$libresoc.v:50820$1646_Y
146541   connect \$69 $not$libresoc.v:50821$1647_Y
146542   connect \$71 $not$libresoc.v:50822$1648_Y
146543   connect \$73 $and$libresoc.v:50823$1649_Y
146544   connect \$75 $not$libresoc.v:50824$1650_Y
146545   connect \$77 $not$libresoc.v:50825$1651_Y
146546   connect \$79 $and$libresoc.v:50826$1652_Y
146547   connect \$81 $not$libresoc.v:50827$1653_Y
146548   connect \$83 $not$libresoc.v:50828$1654_Y
146549   connect \$85 $and$libresoc.v:50829$1655_Y
146550   connect \$87 $not$libresoc.v:50830$1656_Y
146551   connect \$89 $not$libresoc.v:50831$1657_Y
146552   connect \$91 $and$libresoc.v:50832$1658_Y
146553   connect \$93 $not$libresoc.v:50833$1659_Y
146554   connect \$95 $not$libresoc.v:50834$1660_Y
146555   connect \$97 $not$libresoc.v:50835$1661_Y
146556   connect \$12 \$13
146557   connect \$25 \$26
146558   connect \$132 \$133
146559   connect \$136 \$137
146560   connect \corebusy_o 1'0
146561   connect \cu_st__rel_o 1'0
146562   connect \cu_ad__rel_o 1'0
146563   connect \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
146564   connect \core_terminate_o 1'0
146565   connect \state_nia_wen 4'0000
146566   connect \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
146567   connect \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
146568   connect \full_rd2__data_o 0
146569   connect \full_rd__data_o 6'000000
146570   connect \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
146571   connect \dbg_core_dbg_msr \dec2_cur_msr
146572   connect \dbg_core_dbg_pc \pc
146573   connect \dbg_terminate_i 1'0
146574   connect \nia \$26 [63:0]
146575   connect \pc_o \dec2_cur_pc
146576   connect \cu_st__go_i \cu_st__rel_o_rise
146577   connect \cu_ad__go_i 1'0
146578   connect \cu_st__rel_o_rise \$23
146579   connect \cu_st__rel_o_dly$next 1'0
146580   connect \dec2_bigendian \core_bigendian_i
146581   connect \busy_o 1'0
146582   connect \core_coresync_rst \ti_rst
146583   connect \ti_rst \$19
146584   connect \por_clk \clk
146585   connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src }
146586 end
146587 attribute \src "libresoc.v:52503.1-52817.10"
146588 attribute \cells_not_processed 1
146589 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
146590 attribute \generator "nMigen"
146591 module \xics_icp
146592   attribute \src "libresoc.v:52681.3-52709.6"
146593   wire width 32 $0\be_out[31:0]
146594   attribute \src "libresoc.v:52732.3-52740.6"
146595   wire $0\core_irq_o$next[0:0]$2294
146596   attribute \src "libresoc.v:52623.3-52624.37"
146597   wire $0\core_irq_o[0:0]
146598   attribute \src "libresoc.v:52751.3-52813.6"
146599   wire width 8 $0\cppr$10[7:0]$2298
146600   attribute \src "libresoc.v:52637.3-52652.6"
146601   wire width 8 $0\cppr$next[7:0]$2277
146602   attribute \src "libresoc.v:52627.3-52628.25"
146603   wire width 8 $0\cppr[7:0]
146604   attribute \src "libresoc.v:52741.3-52750.6"
146605   wire width 32 $0\icp_wb__dat_r[31:0]
146606   attribute \src "libresoc.v:52504.7-52504.20"
146607   wire $0\initial[0:0]
146608   attribute \src "libresoc.v:52751.3-52813.6"
146609   wire $0\irq$12[0:0]$2299
146610   attribute \src "libresoc.v:52637.3-52652.6"
146611   wire $0\irq$next[0:0]$2278
146612   attribute \src "libresoc.v:52631.3-52632.23"
146613   wire $0\irq[0:0]
146614   attribute \src "libresoc.v:52751.3-52813.6"
146615   wire width 8 $0\mfrr$11[7:0]$2300
146616   attribute \src "libresoc.v:52637.3-52652.6"
146617   wire width 8 $0\mfrr$next[7:0]$2279
146618   attribute \src "libresoc.v:52629.3-52630.25"
146619   wire width 8 $0\mfrr[7:0]
146620   attribute \src "libresoc.v:52720.3-52731.6"
146621   wire width 8 $0\min_pri[7:0]
146622   attribute \src "libresoc.v:52710.3-52719.6"
146623   wire width 8 $0\pending_priority[7:0]
146624   attribute \src "libresoc.v:52751.3-52813.6"
146625   wire $0\wb_ack$14[0:0]$2301
146626   attribute \src "libresoc.v:52637.3-52652.6"
146627   wire $0\wb_ack$next[0:0]$2280
146628   attribute \src "libresoc.v:52635.3-52636.29"
146629   wire $0\wb_ack[0:0]
146630   attribute \src "libresoc.v:52751.3-52813.6"
146631   wire width 32 $0\wb_rd_data$13[31:0]$2302
146632   attribute \src "libresoc.v:52637.3-52652.6"
146633   wire width 32 $0\wb_rd_data$next[31:0]$2281
146634   attribute \src "libresoc.v:52633.3-52634.37"
146635   wire width 32 $0\wb_rd_data[31:0]
146636   attribute \src "libresoc.v:52653.3-52680.6"
146637   wire $0\xirr_accept_rd[0:0]
146638   attribute \src "libresoc.v:52751.3-52813.6"
146639   wire width 24 $0\xisr$9[23:0]$2303
146640   attribute \src "libresoc.v:52637.3-52652.6"
146641   wire width 24 $0\xisr$next[23:0]$2282
146642   attribute \src "libresoc.v:52625.3-52626.25"
146643   wire width 24 $0\xisr[23:0]
146644   attribute \src "libresoc.v:52681.3-52709.6"
146645   wire width 32 $1\be_out[31:0]
146646   attribute \src "libresoc.v:52732.3-52740.6"
146647   wire $1\core_irq_o$next[0:0]$2295
146648   attribute \src "libresoc.v:52533.7-52533.24"
146649   wire $1\core_irq_o[0:0]
146650   attribute \src "libresoc.v:52751.3-52813.6"
146651   wire width 8 $1\cppr$10[7:0]$2304
146652   attribute \src "libresoc.v:52637.3-52652.6"
146653   wire width 8 $1\cppr$next[7:0]$2283
146654   attribute \src "libresoc.v:52537.13-52537.25"
146655   wire width 8 $1\cppr[7:0]
146656   attribute \src "libresoc.v:52741.3-52750.6"
146657   wire width 32 $1\icp_wb__dat_r[31:0]
146658   attribute \src "libresoc.v:52751.3-52813.6"
146659   wire $1\irq$12[0:0]$2314
146660   attribute \src "libresoc.v:52637.3-52652.6"
146661   wire $1\irq$next[0:0]$2284
146662   attribute \src "libresoc.v:52566.7-52566.17"
146663   wire $1\irq[0:0]
146664   attribute \src "libresoc.v:52751.3-52813.6"
146665   wire width 8 $1\mfrr$11[7:0]$2305
146666   attribute \src "libresoc.v:52637.3-52652.6"
146667   wire width 8 $1\mfrr$next[7:0]$2285
146668   attribute \src "libresoc.v:52574.13-52574.25"
146669   wire width 8 $1\mfrr[7:0]
146670   attribute \src "libresoc.v:52720.3-52731.6"
146671   wire width 8 $1\min_pri[7:0]
146672   attribute \src "libresoc.v:52710.3-52719.6"
146673   wire width 8 $1\pending_priority[7:0]
146674   attribute \src "libresoc.v:52751.3-52813.6"
146675   wire $1\wb_ack$14[0:0]$2306
146676   attribute \src "libresoc.v:52637.3-52652.6"
146677   wire $1\wb_ack$next[0:0]$2286
146678   attribute \src "libresoc.v:52588.7-52588.20"
146679   wire $1\wb_ack[0:0]
146680   attribute \src "libresoc.v:52637.3-52652.6"
146681   wire width 32 $1\wb_rd_data$next[31:0]$2287
146682   attribute \src "libresoc.v:52596.14-52596.32"
146683   wire width 32 $1\wb_rd_data[31:0]
146684   attribute \src "libresoc.v:52653.3-52680.6"
146685   wire $1\xirr_accept_rd[0:0]
146686   attribute \src "libresoc.v:52751.3-52813.6"
146687   wire width 24 $1\xisr$9[23:0]$2311
146688   attribute \src "libresoc.v:52637.3-52652.6"
146689   wire width 24 $1\xisr$next[23:0]$2288
146690   attribute \src "libresoc.v:52606.14-52606.31"
146691   wire width 24 $1\xisr[23:0]
146692   attribute \src "libresoc.v:52681.3-52709.6"
146693   wire width 32 $2\be_out[31:0]
146694   attribute \src "libresoc.v:52751.3-52813.6"
146695   wire width 8 $2\cppr$10[7:0]$2307
146696   attribute \src "libresoc.v:52751.3-52813.6"
146697   wire width 8 $2\mfrr$11[7:0]$2308
146698   attribute \src "libresoc.v:52653.3-52680.6"
146699   wire $2\xirr_accept_rd[0:0]
146700   attribute \src "libresoc.v:52751.3-52813.6"
146701   wire width 24 $2\xisr$9[23:0]$2312
146702   attribute \src "libresoc.v:52681.3-52709.6"
146703   wire width 32 $3\be_out[31:0]
146704   attribute \src "libresoc.v:52751.3-52813.6"
146705   wire width 8 $3\cppr$10[7:0]$2309
146706   attribute \src "libresoc.v:52751.3-52813.6"
146707   wire width 8 $3\mfrr$11[7:0]$2310
146708   attribute \src "libresoc.v:52653.3-52680.6"
146709   wire $3\xirr_accept_rd[0:0]
146710   attribute \src "libresoc.v:52751.3-52813.6"
146711   wire width 8 $4\cppr$10[7:0]$2313
146712   attribute \src "libresoc.v:52653.3-52680.6"
146713   wire $4\xirr_accept_rd[0:0]
146714   attribute \src "libresoc.v:52613.18-52613.116"
146715   wire $and$libresoc.v:52613$2259_Y
146716   attribute \src "libresoc.v:52617.18-52617.116"
146717   wire $and$libresoc.v:52617$2263_Y
146718   attribute \src "libresoc.v:52619.18-52619.116"
146719   wire $and$libresoc.v:52619$2265_Y
146720   attribute \src "libresoc.v:52622.17-52622.109"
146721   wire $and$libresoc.v:52622$2268_Y
146722   attribute \src "libresoc.v:52618.18-52618.110"
146723   wire $eq$libresoc.v:52618$2264_Y
146724   attribute \src "libresoc.v:52615.18-52615.114"
146725   wire $lt$libresoc.v:52615$2261_Y
146726   attribute \src "libresoc.v:52616.18-52616.109"
146727   wire $lt$libresoc.v:52616$2262_Y
146728   attribute \src "libresoc.v:52621.18-52621.114"
146729   wire $lt$libresoc.v:52621$2267_Y
146730   attribute \src "libresoc.v:52614.18-52614.109"
146731   wire $ne$libresoc.v:52614$2260_Y
146732   attribute \src "libresoc.v:52620.18-52620.109"
146733   wire $ne$libresoc.v:52620$2266_Y
146734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
146735   wire \$15
146736   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
146737   wire \$17
146738   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
146739   wire \$19
146740   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
146741   wire \$21
146742   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
146743   wire \$23
146744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
146745   wire \$25
146746   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
146747   wire \$27
146748   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
146749   wire \$29
146750   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
146751   wire \$31
146752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
146753   wire \$7
146754   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103"
146755   wire width 32 \be_in
146756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104"
146757   wire width 32 \be_out
146758   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
146759   wire input 13 \clk
146760   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
146761   wire output 4 \core_irq_o
146762   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
146763   wire \core_irq_o$next
146764   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62"
146765   wire width 8 \cppr
146766   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62"
146767   wire width 8 \cppr$10
146768   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62"
146769   wire width 8 \cppr$2
146770   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62"
146771   wire width 8 \cppr$next
146772   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146773   wire output 5 \icp_wb__ack
146774   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146775   wire width 28 input 11 \icp_wb__adr
146776   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146777   wire input 6 \icp_wb__cyc
146778   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146779   wire width 32 output 7 \icp_wb__dat_r
146780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146781   wire width 32 input 8 \icp_wb__dat_w
146782   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146783   wire width 4 input 12 \icp_wb__sel
146784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146785   wire input 9 \icp_wb__stb
146786   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
146787   wire input 10 \icp_wb__we
146788   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
146789   wire width 8 input 3 \ics_i_pri
146790   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
146791   wire width 4 input 2 \ics_i_src
146792   attribute \src "libresoc.v:52504.7-52504.15"
146793   wire \initial
146794   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
146795   wire \irq
146796   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
146797   wire \irq$12
146798   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
146799   wire \irq$4
146800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
146801   wire \irq$next
146802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63"
146803   wire width 8 \mfrr
146804   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63"
146805   wire width 8 \mfrr$11
146806   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63"
146807   wire width 8 \mfrr$3
146808   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63"
146809   wire width 8 \mfrr$next
146810   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107"
146811   wire width 8 \min_pri
146812   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106"
146813   wire width 8 \pending_priority
146814   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
146815   wire input 1 \rst
146816   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
146817   wire \wb_ack
146818   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
146819   wire \wb_ack$14
146820   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
146821   wire \wb_ack$6
146822   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
146823   wire \wb_ack$next
146824   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65"
146825   wire width 32 \wb_rd_data
146826   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65"
146827   wire width 32 \wb_rd_data$13
146828   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65"
146829   wire width 32 \wb_rd_data$5
146830   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65"
146831   wire width 32 \wb_rd_data$next
146832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101"
146833   wire \xirr_accept_rd
146834   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
146835   wire width 24 \xisr
146836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
146837   wire width 24 \xisr$1
146838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
146839   wire width 24 \xisr$9
146840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
146841   wire width 24 \xisr$next
146842   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
146843   cell $and $and$libresoc.v:52613$2259
146844     parameter \A_SIGNED 0
146845     parameter \A_WIDTH 1
146846     parameter \B_SIGNED 0
146847     parameter \B_WIDTH 1
146848     parameter \Y_WIDTH 1
146849     connect \A \icp_wb__cyc
146850     connect \B \icp_wb__stb
146851     connect \Y $and$libresoc.v:52613$2259_Y
146852   end
146853   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
146854   cell $and $and$libresoc.v:52617$2263
146855     parameter \A_SIGNED 0
146856     parameter \A_WIDTH 1
146857     parameter \B_SIGNED 0
146858     parameter \B_WIDTH 1
146859     parameter \Y_WIDTH 1
146860     connect \A \icp_wb__cyc
146861     connect \B \icp_wb__stb
146862     connect \Y $and$libresoc.v:52617$2263_Y
146863   end
146864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
146865   cell $and $and$libresoc.v:52619$2265
146866     parameter \A_SIGNED 0
146867     parameter \A_WIDTH 1
146868     parameter \B_SIGNED 0
146869     parameter \B_WIDTH 1
146870     parameter \Y_WIDTH 1
146871     connect \A \icp_wb__cyc
146872     connect \B \icp_wb__stb
146873     connect \Y $and$libresoc.v:52619$2265_Y
146874   end
146875   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
146876   cell $and $and$libresoc.v:52622$2268
146877     parameter \A_SIGNED 0
146878     parameter \A_WIDTH 1
146879     parameter \B_SIGNED 0
146880     parameter \B_WIDTH 1
146881     parameter \Y_WIDTH 1
146882     connect \A \wb_ack
146883     connect \B \icp_wb__cyc
146884     connect \Y $and$libresoc.v:52622$2268_Y
146885   end
146886   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
146887   cell $eq $eq$libresoc.v:52618$2264
146888     parameter \A_SIGNED 0
146889     parameter \A_WIDTH 4
146890     parameter \B_SIGNED 0
146891     parameter \B_WIDTH 4
146892     parameter \Y_WIDTH 1
146893     connect \A \icp_wb__sel
146894     connect \B 4'1111
146895     connect \Y $eq$libresoc.v:52618$2264_Y
146896   end
146897   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
146898   cell $lt $lt$libresoc.v:52615$2261
146899     parameter \A_SIGNED 0
146900     parameter \A_WIDTH 8
146901     parameter \B_SIGNED 0
146902     parameter \B_WIDTH 8
146903     parameter \Y_WIDTH 1
146904     connect \A \mfrr
146905     connect \B \pending_priority
146906     connect \Y $lt$libresoc.v:52615$2261_Y
146907   end
146908   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
146909   cell $lt $lt$libresoc.v:52616$2262
146910     parameter \A_SIGNED 0
146911     parameter \A_WIDTH 8
146912     parameter \B_SIGNED 0
146913     parameter \B_WIDTH 8
146914     parameter \Y_WIDTH 1
146915     connect \A \min_pri
146916     connect \B \cppr$10
146917     connect \Y $lt$libresoc.v:52616$2262_Y
146918   end
146919   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
146920   cell $lt $lt$libresoc.v:52621$2267
146921     parameter \A_SIGNED 0
146922     parameter \A_WIDTH 8
146923     parameter \B_SIGNED 0
146924     parameter \B_WIDTH 8
146925     parameter \Y_WIDTH 1
146926     connect \A \mfrr
146927     connect \B \pending_priority
146928     connect \Y $lt$libresoc.v:52621$2267_Y
146929   end
146930   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
146931   cell $ne $ne$libresoc.v:52614$2260
146932     parameter \A_SIGNED 0
146933     parameter \A_WIDTH 8
146934     parameter \B_SIGNED 0
146935     parameter \B_WIDTH 8
146936     parameter \Y_WIDTH 1
146937     connect \A \ics_i_pri
146938     connect \B 8'11111111
146939     connect \Y $ne$libresoc.v:52614$2260_Y
146940   end
146941   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
146942   cell $ne $ne$libresoc.v:52620$2266
146943     parameter \A_SIGNED 0
146944     parameter \A_WIDTH 8
146945     parameter \B_SIGNED 0
146946     parameter \B_WIDTH 8
146947     parameter \Y_WIDTH 1
146948     connect \A \ics_i_pri
146949     connect \B 8'11111111
146950     connect \Y $ne$libresoc.v:52620$2266_Y
146951   end
146952   attribute \src "libresoc.v:52504.7-52504.20"
146953   process $proc$libresoc.v:52504$2315
146954     assign { } { }
146955     assign $0\initial[0:0] 1'0
146956     sync always
146957       update \initial $0\initial[0:0]
146958     sync init
146959   end
146960   attribute \src "libresoc.v:52533.7-52533.24"
146961   process $proc$libresoc.v:52533$2316
146962     assign { } { }
146963     assign $1\core_irq_o[0:0] 1'0
146964     sync always
146965     sync init
146966       update \core_irq_o $1\core_irq_o[0:0]
146967   end
146968   attribute \src "libresoc.v:52537.13-52537.25"
146969   process $proc$libresoc.v:52537$2317
146970     assign { } { }
146971     assign $1\cppr[7:0] 8'00000000
146972     sync always
146973     sync init
146974       update \cppr $1\cppr[7:0]
146975   end
146976   attribute \src "libresoc.v:52566.7-52566.17"
146977   process $proc$libresoc.v:52566$2318
146978     assign { } { }
146979     assign $1\irq[0:0] 1'0
146980     sync always
146981     sync init
146982       update \irq $1\irq[0:0]
146983   end
146984   attribute \src "libresoc.v:52574.13-52574.25"
146985   process $proc$libresoc.v:52574$2319
146986     assign { } { }
146987     assign $1\mfrr[7:0] 8'11111111
146988     sync always
146989     sync init
146990       update \mfrr $1\mfrr[7:0]
146991   end
146992   attribute \src "libresoc.v:52588.7-52588.20"
146993   process $proc$libresoc.v:52588$2320
146994     assign { } { }
146995     assign $1\wb_ack[0:0] 1'0
146996     sync always
146997     sync init
146998       update \wb_ack $1\wb_ack[0:0]
146999   end
147000   attribute \src "libresoc.v:52596.14-52596.32"
147001   process $proc$libresoc.v:52596$2321
147002     assign { } { }
147003     assign $1\wb_rd_data[31:0] 0
147004     sync always
147005     sync init
147006       update \wb_rd_data $1\wb_rd_data[31:0]
147007   end
147008   attribute \src "libresoc.v:52606.14-52606.31"
147009   process $proc$libresoc.v:52606$2322
147010     assign { } { }
147011     assign $1\xisr[23:0] 24'000000000000000000000000
147012     sync always
147013     sync init
147014       update \xisr $1\xisr[23:0]
147015   end
147016   attribute \src "libresoc.v:52623.3-52624.37"
147017   process $proc$libresoc.v:52623$2269
147018     assign { } { }
147019     assign $0\core_irq_o[0:0] \core_irq_o$next
147020     sync posedge \clk
147021       update \core_irq_o $0\core_irq_o[0:0]
147022   end
147023   attribute \src "libresoc.v:52625.3-52626.25"
147024   process $proc$libresoc.v:52625$2270
147025     assign { } { }
147026     assign $0\xisr[23:0] \xisr$next
147027     sync posedge \clk
147028       update \xisr $0\xisr[23:0]
147029   end
147030   attribute \src "libresoc.v:52627.3-52628.25"
147031   process $proc$libresoc.v:52627$2271
147032     assign { } { }
147033     assign $0\cppr[7:0] \cppr$next
147034     sync posedge \clk
147035       update \cppr $0\cppr[7:0]
147036   end
147037   attribute \src "libresoc.v:52629.3-52630.25"
147038   process $proc$libresoc.v:52629$2272
147039     assign { } { }
147040     assign $0\mfrr[7:0] \mfrr$next
147041     sync posedge \clk
147042       update \mfrr $0\mfrr[7:0]
147043   end
147044   attribute \src "libresoc.v:52631.3-52632.23"
147045   process $proc$libresoc.v:52631$2273
147046     assign { } { }
147047     assign $0\irq[0:0] \irq$next
147048     sync posedge \clk
147049       update \irq $0\irq[0:0]
147050   end
147051   attribute \src "libresoc.v:52633.3-52634.37"
147052   process $proc$libresoc.v:52633$2274
147053     assign { } { }
147054     assign $0\wb_rd_data[31:0] \wb_rd_data$next
147055     sync posedge \clk
147056       update \wb_rd_data $0\wb_rd_data[31:0]
147057   end
147058   attribute \src "libresoc.v:52635.3-52636.29"
147059   process $proc$libresoc.v:52635$2275
147060     assign { } { }
147061     assign $0\wb_ack[0:0] \wb_ack$next
147062     sync posedge \clk
147063       update \wb_ack $0\wb_ack[0:0]
147064   end
147065   attribute \src "libresoc.v:52637.3-52652.6"
147066   process $proc$libresoc.v:52637$2276
147067     assign { } { }
147068     assign { } { }
147069     assign { } { }
147070     assign { } { }
147071     assign { } { }
147072     assign { } { }
147073     assign { } { }
147074     assign $0\cppr$next[7:0]$2277 $1\cppr$next[7:0]$2283
147075     assign $0\irq$next[0:0]$2278 $1\irq$next[0:0]$2284
147076     assign $0\mfrr$next[7:0]$2279 $1\mfrr$next[7:0]$2285
147077     assign $0\wb_ack$next[0:0]$2280 $1\wb_ack$next[0:0]$2286
147078     assign $0\wb_rd_data$next[31:0]$2281 $1\wb_rd_data$next[31:0]$2287
147079     assign $0\xisr$next[23:0]$2282 $1\xisr$next[23:0]$2288
147080     attribute \src "libresoc.v:52638.5-52638.29"
147081     switch \initial
147082       attribute \src "libresoc.v:52638.9-52638.17"
147083       case 1'1
147084       case
147085     end
147086     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
147087     switch \rst
147088       attribute \src "libresoc.v:0.0-0.0"
147089       case 1'1
147090         assign { } { }
147091         assign { } { }
147092         assign { } { }
147093         assign { } { }
147094         assign { } { }
147095         assign { } { }
147096         assign $1\xisr$next[23:0]$2288 24'000000000000000000000000
147097         assign $1\cppr$next[7:0]$2283 8'00000000
147098         assign $1\mfrr$next[7:0]$2285 8'11111111
147099         assign $1\irq$next[0:0]$2284 1'0
147100         assign $1\wb_rd_data$next[31:0]$2287 0
147101         assign $1\wb_ack$next[0:0]$2286 1'0
147102       case
147103         assign $1\cppr$next[7:0]$2283 \cppr$2
147104         assign $1\irq$next[0:0]$2284 \irq$4
147105         assign $1\mfrr$next[7:0]$2285 \mfrr$3
147106         assign $1\wb_ack$next[0:0]$2286 \wb_ack$6
147107         assign $1\wb_rd_data$next[31:0]$2287 \wb_rd_data$5
147108         assign $1\xisr$next[23:0]$2288 \xisr$1
147109     end
147110     sync always
147111       update \cppr$next $0\cppr$next[7:0]$2277
147112       update \irq$next $0\irq$next[0:0]$2278
147113       update \mfrr$next $0\mfrr$next[7:0]$2279
147114       update \wb_ack$next $0\wb_ack$next[0:0]$2280
147115       update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2281
147116       update \xisr$next $0\xisr$next[23:0]$2282
147117   end
147118   attribute \src "libresoc.v:52653.3-52680.6"
147119   process $proc$libresoc.v:52653$2289
147120     assign { } { }
147121     assign { } { }
147122     assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
147123     attribute \src "libresoc.v:52654.5-52654.29"
147124     switch \initial
147125       attribute \src "libresoc.v:52654.9-52654.17"
147126       case 1'1
147127       case
147128     end
147129     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
147130     switch \$23
147131       attribute \src "libresoc.v:0.0-0.0"
147132       case 1'1
147133         assign { } { }
147134         assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0]
147135         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
147136         switch \icp_wb__we
147137           attribute \src "libresoc.v:0.0-0.0"
147138           case 1'1
147139             assign $2\xirr_accept_rd[0:0] 1'0
147140           attribute \src "libresoc.v:0.0-0.0"
147141           case
147142             assign { } { }
147143             assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0]
147144             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155"
147145             switch \icp_wb__adr [5:0]
147146               attribute \src "libresoc.v:0.0-0.0"
147147               case 6'000001
147148                 assign { } { }
147149                 assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0]
147150                 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
147151                 switch \$25
147152                   attribute \src "libresoc.v:0.0-0.0"
147153                   case 1'1
147154                     assign { } { }
147155                     assign $4\xirr_accept_rd[0:0] 1'1
147156                   case
147157                     assign $4\xirr_accept_rd[0:0] 1'0
147158                 end
147159               case
147160                 assign $3\xirr_accept_rd[0:0] 1'0
147161             end
147162         end
147163       case
147164         assign $1\xirr_accept_rd[0:0] 1'0
147165     end
147166     sync always
147167       update \xirr_accept_rd $0\xirr_accept_rd[0:0]
147168   end
147169   attribute \src "libresoc.v:52681.3-52709.6"
147170   process $proc$libresoc.v:52681$2290
147171     assign { } { }
147172     assign { } { }
147173     assign $0\be_out[31:0] $1\be_out[31:0]
147174     attribute \src "libresoc.v:52682.5-52682.29"
147175     switch \initial
147176       attribute \src "libresoc.v:52682.9-52682.17"
147177       case 1'1
147178       case
147179     end
147180     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
147181     switch \$27
147182       attribute \src "libresoc.v:0.0-0.0"
147183       case 1'1
147184         assign { } { }
147185         assign $1\be_out[31:0] $2\be_out[31:0]
147186         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
147187         switch \icp_wb__we
147188           attribute \src "libresoc.v:0.0-0.0"
147189           case 1'1
147190             assign $2\be_out[31:0] 0
147191           attribute \src "libresoc.v:0.0-0.0"
147192           case
147193             assign { } { }
147194             assign $2\be_out[31:0] $3\be_out[31:0]
147195             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155"
147196             switch \icp_wb__adr [5:0]
147197               attribute \src "libresoc.v:0.0-0.0"
147198               case 6'000000
147199                 assign { } { }
147200                 assign $3\be_out[31:0] { \cppr \xisr }
147201               attribute \src "libresoc.v:0.0-0.0"
147202               case 6'000001
147203                 assign { } { }
147204                 assign $3\be_out[31:0] { \cppr \xisr }
147205               attribute \src "libresoc.v:0.0-0.0"
147206               case 6'000011
147207                 assign $3\be_out[31:0] [23:0] 24'000000000000000000000000
147208                 assign $3\be_out[31:0] [31:24] \mfrr
147209               case
147210                 assign $3\be_out[31:0] 0
147211             end
147212         end
147213       case
147214         assign $1\be_out[31:0] 0
147215     end
147216     sync always
147217       update \be_out $0\be_out[31:0]
147218   end
147219   attribute \src "libresoc.v:52710.3-52719.6"
147220   process $proc$libresoc.v:52710$2291
147221     assign { } { }
147222     assign { } { }
147223     assign $0\pending_priority[7:0] $1\pending_priority[7:0]
147224     attribute \src "libresoc.v:52711.5-52711.29"
147225     switch \initial
147226       attribute \src "libresoc.v:52711.9-52711.17"
147227       case 1'1
147228       case
147229     end
147230     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
147231     switch \$29
147232       attribute \src "libresoc.v:0.0-0.0"
147233       case 1'1
147234         assign { } { }
147235         assign $1\pending_priority[7:0] \ics_i_pri
147236       case
147237         assign $1\pending_priority[7:0] 8'11111111
147238     end
147239     sync always
147240       update \pending_priority $0\pending_priority[7:0]
147241   end
147242   attribute \src "libresoc.v:52720.3-52731.6"
147243   process $proc$libresoc.v:52720$2292
147244     assign { } { }
147245     assign $0\min_pri[7:0] $1\min_pri[7:0]
147246     attribute \src "libresoc.v:52721.5-52721.29"
147247     switch \initial
147248       attribute \src "libresoc.v:52721.9-52721.17"
147249       case 1'1
147250       case
147251     end
147252     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
147253     switch \$31
147254       attribute \src "libresoc.v:0.0-0.0"
147255       case 1'1
147256         assign { } { }
147257         assign $1\min_pri[7:0] \mfrr
147258       attribute \src "libresoc.v:0.0-0.0"
147259       case
147260         assign { } { }
147261         assign $1\min_pri[7:0] \pending_priority
147262     end
147263     sync always
147264       update \min_pri $0\min_pri[7:0]
147265   end
147266   attribute \src "libresoc.v:52732.3-52740.6"
147267   process $proc$libresoc.v:52732$2293
147268     assign { } { }
147269     assign { } { }
147270     assign $0\core_irq_o$next[0:0]$2294 $1\core_irq_o$next[0:0]$2295
147271     attribute \src "libresoc.v:52733.5-52733.29"
147272     switch \initial
147273       attribute \src "libresoc.v:52733.9-52733.17"
147274       case 1'1
147275       case
147276     end
147277     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
147278     switch \rst
147279       attribute \src "libresoc.v:0.0-0.0"
147280       case 1'1
147281         assign { } { }
147282         assign $1\core_irq_o$next[0:0]$2295 1'0
147283       case
147284         assign $1\core_irq_o$next[0:0]$2295 \irq
147285     end
147286     sync always
147287       update \core_irq_o$next $0\core_irq_o$next[0:0]$2294
147288   end
147289   attribute \src "libresoc.v:52741.3-52750.6"
147290   process $proc$libresoc.v:52741$2296
147291     assign { } { }
147292     assign { } { }
147293     assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
147294     attribute \src "libresoc.v:52742.5-52742.29"
147295     switch \initial
147296       attribute \src "libresoc.v:52742.9-52742.17"
147297       case 1'1
147298       case
147299     end
147300     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97"
147301     switch \icp_wb__ack
147302       attribute \src "libresoc.v:0.0-0.0"
147303       case 1'1
147304         assign { } { }
147305         assign $1\icp_wb__dat_r[31:0] \wb_rd_data
147306       case
147307         assign $1\icp_wb__dat_r[31:0] 0
147308     end
147309     sync always
147310       update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
147311   end
147312   attribute \src "libresoc.v:52751.3-52813.6"
147313   process $proc$libresoc.v:52751$2297
147314     assign { } { }
147315     assign { } { }
147316     assign { } { }
147317     assign { } { }
147318     assign { } { }
147319     assign { } { }
147320     assign { } { }
147321     assign { } { }
147322     assign { } { }
147323     assign $0\mfrr$11[7:0]$2300 $1\mfrr$11[7:0]$2305
147324     assign $0\wb_ack$14[0:0]$2301 $1\wb_ack$14[0:0]$2306
147325     assign { } { }
147326     assign { } { }
147327     assign { } { }
147328     assign $0\xisr$9[23:0]$2303 $2\xisr$9[23:0]$2312
147329     assign $0\cppr$10[7:0]$2298 $4\cppr$10[7:0]$2313
147330     assign $0\wb_rd_data$13[31:0]$2302 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
147331     assign $0\irq$12[0:0]$2299 $1\irq$12[0:0]$2314
147332     attribute \src "libresoc.v:52752.5-52752.29"
147333     switch \initial
147334       attribute \src "libresoc.v:52752.9-52752.17"
147335       case 1'1
147336       case
147337     end
147338     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
147339     switch \$15
147340       attribute \src "libresoc.v:0.0-0.0"
147341       case 1'1
147342         assign { } { }
147343         assign { } { }
147344         assign { } { }
147345         assign $1\wb_ack$14[0:0]$2306 1'1
147346         assign $1\cppr$10[7:0]$2304 $2\cppr$10[7:0]$2307
147347         assign $1\mfrr$11[7:0]$2305 $2\mfrr$11[7:0]$2308
147348         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
147349         switch \icp_wb__we
147350           attribute \src "libresoc.v:0.0-0.0"
147351           case 1'1
147352             assign { } { }
147353             assign { } { }
147354             assign $2\cppr$10[7:0]$2307 $3\cppr$10[7:0]$2309
147355             assign $2\mfrr$11[7:0]$2308 $3\mfrr$11[7:0]$2310
147356             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121"
147357             switch \icp_wb__adr [5:0]
147358               attribute \src "libresoc.v:0.0-0.0"
147359               case 6'000000
147360                 assign { } { }
147361                 assign $3\mfrr$11[7:0]$2310 \mfrr
147362                 assign $3\cppr$10[7:0]$2309 \be_in [31:24]
147363               attribute \src "libresoc.v:0.0-0.0"
147364               case 6'000001
147365                 assign { } { }
147366                 assign $3\mfrr$11[7:0]$2310 \mfrr
147367                 assign $3\cppr$10[7:0]$2309 \be_in [31:24]
147368               attribute \src "libresoc.v:0.0-0.0"
147369               case 6'000011
147370                 assign $3\cppr$10[7:0]$2309 \cppr
147371                 assign { } { }
147372                 assign $3\mfrr$11[7:0]$2310 \be_in [31:24]
147373               case
147374                 assign $3\cppr$10[7:0]$2309 \cppr
147375                 assign $3\mfrr$11[7:0]$2310 \mfrr
147376             end
147377           case
147378             assign $2\cppr$10[7:0]$2307 \cppr
147379             assign $2\mfrr$11[7:0]$2308 \mfrr
147380         end
147381       case
147382         assign $1\cppr$10[7:0]$2304 \cppr
147383         assign $1\mfrr$11[7:0]$2305 \mfrr
147384         assign $1\wb_ack$14[0:0]$2306 1'0
147385     end
147386     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
147387     switch \$17
147388       attribute \src "libresoc.v:0.0-0.0"
147389       case 1'1
147390         assign { } { }
147391         assign $1\xisr$9[23:0]$2311 { 20'00000000000000000001 \ics_i_src }
147392       case
147393         assign $1\xisr$9[23:0]$2311 24'000000000000000000000000
147394     end
147395     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
147396     switch \$19
147397       attribute \src "libresoc.v:0.0-0.0"
147398       case 1'1
147399         assign { } { }
147400         assign $2\xisr$9[23:0]$2312 24'000000000000000000000010
147401       case
147402         assign $2\xisr$9[23:0]$2312 $1\xisr$9[23:0]$2311
147403     end
147404     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185"
147405     switch \xirr_accept_rd
147406       attribute \src "libresoc.v:0.0-0.0"
147407       case 1'1
147408         assign { } { }
147409         assign $4\cppr$10[7:0]$2313 \min_pri
147410       case
147411         assign $4\cppr$10[7:0]$2313 $1\cppr$10[7:0]$2304
147412     end
147413     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
147414     switch { \irq \$21 }
147415       attribute \src "libresoc.v:0.0-0.0"
147416       case 2'-1
147417         assign { } { }
147418         assign $1\irq$12[0:0]$2314 1'1
147419       case
147420         assign $1\irq$12[0:0]$2314 1'0
147421     end
147422     sync always
147423       update \cppr$10 $0\cppr$10[7:0]$2298
147424       update \irq$12 $0\irq$12[0:0]$2299
147425       update \mfrr$11 $0\mfrr$11[7:0]$2300
147426       update \wb_ack$14 $0\wb_ack$14[0:0]$2301
147427       update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2302
147428       update \xisr$9 $0\xisr$9[23:0]$2303
147429   end
147430   connect \$15 $and$libresoc.v:52613$2259_Y
147431   connect \$17 $ne$libresoc.v:52614$2260_Y
147432   connect \$19 $lt$libresoc.v:52615$2261_Y
147433   connect \$21 $lt$libresoc.v:52616$2262_Y
147434   connect \$23 $and$libresoc.v:52617$2263_Y
147435   connect \$25 $eq$libresoc.v:52618$2264_Y
147436   connect \$27 $and$libresoc.v:52619$2265_Y
147437   connect \$29 $ne$libresoc.v:52620$2266_Y
147438   connect \$31 $lt$libresoc.v:52621$2267_Y
147439   connect \$7 $and$libresoc.v:52622$2268_Y
147440   connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
147441   connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
147442   connect \icp_wb__ack \$7
147443 end
147444 attribute \src "libresoc.v:52821.1-53870.10"
147445 attribute \cells_not_processed 1
147446 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
147447 attribute \generator "nMigen"
147448 module \xics_ics
147449   attribute \src "libresoc.v:53751.3-53800.6"
147450   wire width 32 $0\be_out[31:0]
147451   attribute \src "libresoc.v:53462.3-53471.6"
147452   wire width 4 $0\cur_idx0[3:0]
147453   attribute \src "libresoc.v:53671.3-53680.6"
147454   wire width 4 $0\cur_idx10[3:0]
147455   attribute \src "libresoc.v:53691.3-53700.6"
147456   wire width 4 $0\cur_idx11[3:0]
147457   attribute \src "libresoc.v:53711.3-53720.6"
147458   wire width 4 $0\cur_idx12[3:0]
147459   attribute \src "libresoc.v:53731.3-53740.6"
147460   wire width 4 $0\cur_idx13[3:0]
147461   attribute \src "libresoc.v:53801.3-53810.6"
147462   wire width 4 $0\cur_idx14[3:0]
147463   attribute \src "libresoc.v:53821.3-53830.6"
147464   wire width 4 $0\cur_idx15[3:0]
147465   attribute \src "libresoc.v:53482.3-53491.6"
147466   wire width 4 $0\cur_idx1[3:0]
147467   attribute \src "libresoc.v:53502.3-53511.6"
147468   wire width 4 $0\cur_idx2[3:0]
147469   attribute \src "libresoc.v:53522.3-53531.6"
147470   wire width 4 $0\cur_idx3[3:0]
147471   attribute \src "libresoc.v:53551.3-53560.6"
147472   wire width 4 $0\cur_idx4[3:0]
147473   attribute \src "libresoc.v:53571.3-53580.6"
147474   wire width 4 $0\cur_idx5[3:0]
147475   attribute \src "libresoc.v:53591.3-53600.6"
147476   wire width 4 $0\cur_idx6[3:0]
147477   attribute \src "libresoc.v:53611.3-53620.6"
147478   wire width 4 $0\cur_idx7[3:0]
147479   attribute \src "libresoc.v:53631.3-53640.6"
147480   wire width 4 $0\cur_idx8[3:0]
147481   attribute \src "libresoc.v:53651.3-53660.6"
147482   wire width 4 $0\cur_idx9[3:0]
147483   attribute \src "libresoc.v:53452.3-53461.6"
147484   wire width 8 $0\cur_pri0[7:0]
147485   attribute \src "libresoc.v:53661.3-53670.6"
147486   wire width 8 $0\cur_pri10[7:0]
147487   attribute \src "libresoc.v:53681.3-53690.6"
147488   wire width 8 $0\cur_pri11[7:0]
147489   attribute \src "libresoc.v:53701.3-53710.6"
147490   wire width 8 $0\cur_pri12[7:0]
147491   attribute \src "libresoc.v:53721.3-53730.6"
147492   wire width 8 $0\cur_pri13[7:0]
147493   attribute \src "libresoc.v:53741.3-53750.6"
147494   wire width 8 $0\cur_pri14[7:0]
147495   attribute \src "libresoc.v:53811.3-53820.6"
147496   wire width 8 $0\cur_pri15[7:0]
147497   attribute \src "libresoc.v:53472.3-53481.6"
147498   wire width 8 $0\cur_pri1[7:0]
147499   attribute \src "libresoc.v:53492.3-53501.6"
147500   wire width 8 $0\cur_pri2[7:0]
147501   attribute \src "libresoc.v:53512.3-53521.6"
147502   wire width 8 $0\cur_pri3[7:0]
147503   attribute \src "libresoc.v:53532.3-53541.6"
147504   wire width 8 $0\cur_pri4[7:0]
147505   attribute \src "libresoc.v:53561.3-53570.6"
147506   wire width 8 $0\cur_pri5[7:0]
147507   attribute \src "libresoc.v:53581.3-53590.6"
147508   wire width 8 $0\cur_pri6[7:0]
147509   attribute \src "libresoc.v:53601.3-53610.6"
147510   wire width 8 $0\cur_pri7[7:0]
147511   attribute \src "libresoc.v:53621.3-53630.6"
147512   wire width 8 $0\cur_pri8[7:0]
147513   attribute \src "libresoc.v:53641.3-53650.6"
147514   wire width 8 $0\cur_pri9[7:0]
147515   attribute \src "libresoc.v:53831.3-53840.6"
147516   wire $0\ibit[0:0]
147517   attribute \src "libresoc.v:53342.3-53343.25"
147518   wire width 8 $0\icp_o_pri[7:0]
147519   attribute \src "libresoc.v:53340.3-53341.28"
147520   wire width 4 $0\icp_o_src[3:0]
147521   attribute \src "libresoc.v:53850.3-53858.6"
147522   wire $0\ics_wb__ack$next[0:0]$2569
147523   attribute \src "libresoc.v:53334.3-53335.39"
147524   wire $0\ics_wb__ack[0:0]
147525   attribute \src "libresoc.v:53841.3-53849.6"
147526   wire width 32 $0\ics_wb__dat_r$next[31:0]$2566
147527   attribute \src "libresoc.v:53336.3-53337.43"
147528   wire width 32 $0\ics_wb__dat_r[31:0]
147529   attribute \src "libresoc.v:52822.7-52822.20"
147530   wire $0\initial[0:0]
147531   attribute \src "libresoc.v:53542.3-53550.6"
147532   wire width 16 $0\int_level_l$next[15:0]$2538
147533   attribute \src "libresoc.v:53338.3-53339.39"
147534   wire width 16 $0\int_level_l[15:0]
147535   attribute \src "libresoc.v:53366.3-53451.6"
147536   wire width 8 $0\xive0_pri$next[7:0]$2448
147537   attribute \src "libresoc.v:53344.3-53345.35"
147538   wire width 8 $0\xive0_pri[7:0]
147539   attribute \src "libresoc.v:53366.3-53451.6"
147540   wire width 8 $0\xive10_pri$next[7:0]$2449
147541   attribute \src "libresoc.v:53364.3-53365.37"
147542   wire width 8 $0\xive10_pri[7:0]
147543   attribute \src "libresoc.v:53366.3-53451.6"
147544   wire width 8 $0\xive11_pri$next[7:0]$2450
147545   attribute \src "libresoc.v:53324.3-53325.37"
147546   wire width 8 $0\xive11_pri[7:0]
147547   attribute \src "libresoc.v:53366.3-53451.6"
147548   wire width 8 $0\xive12_pri$next[7:0]$2451
147549   attribute \src "libresoc.v:53326.3-53327.37"
147550   wire width 8 $0\xive12_pri[7:0]
147551   attribute \src "libresoc.v:53366.3-53451.6"
147552   wire width 8 $0\xive13_pri$next[7:0]$2452
147553   attribute \src "libresoc.v:53328.3-53329.37"
147554   wire width 8 $0\xive13_pri[7:0]
147555   attribute \src "libresoc.v:53366.3-53451.6"
147556   wire width 8 $0\xive14_pri$next[7:0]$2453
147557   attribute \src "libresoc.v:53330.3-53331.37"
147558   wire width 8 $0\xive14_pri[7:0]
147559   attribute \src "libresoc.v:53366.3-53451.6"
147560   wire width 8 $0\xive15_pri$next[7:0]$2454
147561   attribute \src "libresoc.v:53332.3-53333.37"
147562   wire width 8 $0\xive15_pri[7:0]
147563   attribute \src "libresoc.v:53366.3-53451.6"
147564   wire width 8 $0\xive1_pri$next[7:0]$2455
147565   attribute \src "libresoc.v:53346.3-53347.35"
147566   wire width 8 $0\xive1_pri[7:0]
147567   attribute \src "libresoc.v:53366.3-53451.6"
147568   wire width 8 $0\xive2_pri$next[7:0]$2456
147569   attribute \src "libresoc.v:53348.3-53349.35"
147570   wire width 8 $0\xive2_pri[7:0]
147571   attribute \src "libresoc.v:53366.3-53451.6"
147572   wire width 8 $0\xive3_pri$next[7:0]$2457
147573   attribute \src "libresoc.v:53350.3-53351.35"
147574   wire width 8 $0\xive3_pri[7:0]
147575   attribute \src "libresoc.v:53366.3-53451.6"
147576   wire width 8 $0\xive4_pri$next[7:0]$2458
147577   attribute \src "libresoc.v:53352.3-53353.35"
147578   wire width 8 $0\xive4_pri[7:0]
147579   attribute \src "libresoc.v:53366.3-53451.6"
147580   wire width 8 $0\xive5_pri$next[7:0]$2459
147581   attribute \src "libresoc.v:53354.3-53355.35"
147582   wire width 8 $0\xive5_pri[7:0]
147583   attribute \src "libresoc.v:53366.3-53451.6"
147584   wire width 8 $0\xive6_pri$next[7:0]$2460
147585   attribute \src "libresoc.v:53356.3-53357.35"
147586   wire width 8 $0\xive6_pri[7:0]
147587   attribute \src "libresoc.v:53366.3-53451.6"
147588   wire width 8 $0\xive7_pri$next[7:0]$2461
147589   attribute \src "libresoc.v:53358.3-53359.35"
147590   wire width 8 $0\xive7_pri[7:0]
147591   attribute \src "libresoc.v:53366.3-53451.6"
147592   wire width 8 $0\xive8_pri$next[7:0]$2462
147593   attribute \src "libresoc.v:53360.3-53361.35"
147594   wire width 8 $0\xive8_pri[7:0]
147595   attribute \src "libresoc.v:53366.3-53451.6"
147596   wire width 8 $0\xive9_pri$next[7:0]$2463
147597   attribute \src "libresoc.v:53362.3-53363.35"
147598   wire width 8 $0\xive9_pri[7:0]
147599   attribute \src "libresoc.v:53751.3-53800.6"
147600   wire width 32 $1\be_out[31:0]
147601   attribute \src "libresoc.v:53462.3-53471.6"
147602   wire width 4 $1\cur_idx0[3:0]
147603   attribute \src "libresoc.v:53671.3-53680.6"
147604   wire width 4 $1\cur_idx10[3:0]
147605   attribute \src "libresoc.v:53691.3-53700.6"
147606   wire width 4 $1\cur_idx11[3:0]
147607   attribute \src "libresoc.v:53711.3-53720.6"
147608   wire width 4 $1\cur_idx12[3:0]
147609   attribute \src "libresoc.v:53731.3-53740.6"
147610   wire width 4 $1\cur_idx13[3:0]
147611   attribute \src "libresoc.v:53801.3-53810.6"
147612   wire width 4 $1\cur_idx14[3:0]
147613   attribute \src "libresoc.v:53821.3-53830.6"
147614   wire width 4 $1\cur_idx15[3:0]
147615   attribute \src "libresoc.v:53482.3-53491.6"
147616   wire width 4 $1\cur_idx1[3:0]
147617   attribute \src "libresoc.v:53502.3-53511.6"
147618   wire width 4 $1\cur_idx2[3:0]
147619   attribute \src "libresoc.v:53522.3-53531.6"
147620   wire width 4 $1\cur_idx3[3:0]
147621   attribute \src "libresoc.v:53551.3-53560.6"
147622   wire width 4 $1\cur_idx4[3:0]
147623   attribute \src "libresoc.v:53571.3-53580.6"
147624   wire width 4 $1\cur_idx5[3:0]
147625   attribute \src "libresoc.v:53591.3-53600.6"
147626   wire width 4 $1\cur_idx6[3:0]
147627   attribute \src "libresoc.v:53611.3-53620.6"
147628   wire width 4 $1\cur_idx7[3:0]
147629   attribute \src "libresoc.v:53631.3-53640.6"
147630   wire width 4 $1\cur_idx8[3:0]
147631   attribute \src "libresoc.v:53651.3-53660.6"
147632   wire width 4 $1\cur_idx9[3:0]
147633   attribute \src "libresoc.v:53452.3-53461.6"
147634   wire width 8 $1\cur_pri0[7:0]
147635   attribute \src "libresoc.v:53661.3-53670.6"
147636   wire width 8 $1\cur_pri10[7:0]
147637   attribute \src "libresoc.v:53681.3-53690.6"
147638   wire width 8 $1\cur_pri11[7:0]
147639   attribute \src "libresoc.v:53701.3-53710.6"
147640   wire width 8 $1\cur_pri12[7:0]
147641   attribute \src "libresoc.v:53721.3-53730.6"
147642   wire width 8 $1\cur_pri13[7:0]
147643   attribute \src "libresoc.v:53741.3-53750.6"
147644   wire width 8 $1\cur_pri14[7:0]
147645   attribute \src "libresoc.v:53811.3-53820.6"
147646   wire width 8 $1\cur_pri15[7:0]
147647   attribute \src "libresoc.v:53472.3-53481.6"
147648   wire width 8 $1\cur_pri1[7:0]
147649   attribute \src "libresoc.v:53492.3-53501.6"
147650   wire width 8 $1\cur_pri2[7:0]
147651   attribute \src "libresoc.v:53512.3-53521.6"
147652   wire width 8 $1\cur_pri3[7:0]
147653   attribute \src "libresoc.v:53532.3-53541.6"
147654   wire width 8 $1\cur_pri4[7:0]
147655   attribute \src "libresoc.v:53561.3-53570.6"
147656   wire width 8 $1\cur_pri5[7:0]
147657   attribute \src "libresoc.v:53581.3-53590.6"
147658   wire width 8 $1\cur_pri6[7:0]
147659   attribute \src "libresoc.v:53601.3-53610.6"
147660   wire width 8 $1\cur_pri7[7:0]
147661   attribute \src "libresoc.v:53621.3-53630.6"
147662   wire width 8 $1\cur_pri8[7:0]
147663   attribute \src "libresoc.v:53641.3-53650.6"
147664   wire width 8 $1\cur_pri9[7:0]
147665   attribute \src "libresoc.v:53831.3-53840.6"
147666   wire $1\ibit[0:0]
147667   attribute \src "libresoc.v:53103.13-53103.30"
147668   wire width 8 $1\icp_o_pri[7:0]
147669   attribute \src "libresoc.v:53108.13-53108.29"
147670   wire width 4 $1\icp_o_src[3:0]
147671   attribute \src "libresoc.v:53850.3-53858.6"
147672   wire $1\ics_wb__ack$next[0:0]$2570
147673   attribute \src "libresoc.v:53117.7-53117.25"
147674   wire $1\ics_wb__ack[0:0]
147675   attribute \src "libresoc.v:53841.3-53849.6"
147676   wire width 32 $1\ics_wb__dat_r$next[31:0]$2567
147677   attribute \src "libresoc.v:53126.14-53126.35"
147678   wire width 32 $1\ics_wb__dat_r[31:0]
147679   attribute \src "libresoc.v:53542.3-53550.6"
147680   wire width 16 $1\int_level_l$next[15:0]$2539
147681   attribute \src "libresoc.v:53138.14-53138.36"
147682   wire width 16 $1\int_level_l[15:0]
147683   attribute \src "libresoc.v:53366.3-53451.6"
147684   wire width 8 $1\xive0_pri$next[7:0]$2464
147685   attribute \src "libresoc.v:53158.13-53158.30"
147686   wire width 8 $1\xive0_pri[7:0]
147687   attribute \src "libresoc.v:53366.3-53451.6"
147688   wire width 8 $1\xive10_pri$next[7:0]$2465
147689   attribute \src "libresoc.v:53162.13-53162.31"
147690   wire width 8 $1\xive10_pri[7:0]
147691   attribute \src "libresoc.v:53366.3-53451.6"
147692   wire width 8 $1\xive11_pri$next[7:0]$2466
147693   attribute \src "libresoc.v:53166.13-53166.31"
147694   wire width 8 $1\xive11_pri[7:0]
147695   attribute \src "libresoc.v:53366.3-53451.6"
147696   wire width 8 $1\xive12_pri$next[7:0]$2467
147697   attribute \src "libresoc.v:53170.13-53170.31"
147698   wire width 8 $1\xive12_pri[7:0]
147699   attribute \src "libresoc.v:53366.3-53451.6"
147700   wire width 8 $1\xive13_pri$next[7:0]$2468
147701   attribute \src "libresoc.v:53174.13-53174.31"
147702   wire width 8 $1\xive13_pri[7:0]
147703   attribute \src "libresoc.v:53366.3-53451.6"
147704   wire width 8 $1\xive14_pri$next[7:0]$2469
147705   attribute \src "libresoc.v:53178.13-53178.31"
147706   wire width 8 $1\xive14_pri[7:0]
147707   attribute \src "libresoc.v:53366.3-53451.6"
147708   wire width 8 $1\xive15_pri$next[7:0]$2470
147709   attribute \src "libresoc.v:53182.13-53182.31"
147710   wire width 8 $1\xive15_pri[7:0]
147711   attribute \src "libresoc.v:53366.3-53451.6"
147712   wire width 8 $1\xive1_pri$next[7:0]$2471
147713   attribute \src "libresoc.v:53186.13-53186.30"
147714   wire width 8 $1\xive1_pri[7:0]
147715   attribute \src "libresoc.v:53366.3-53451.6"
147716   wire width 8 $1\xive2_pri$next[7:0]$2472
147717   attribute \src "libresoc.v:53190.13-53190.30"
147718   wire width 8 $1\xive2_pri[7:0]
147719   attribute \src "libresoc.v:53366.3-53451.6"
147720   wire width 8 $1\xive3_pri$next[7:0]$2473
147721   attribute \src "libresoc.v:53194.13-53194.30"
147722   wire width 8 $1\xive3_pri[7:0]
147723   attribute \src "libresoc.v:53366.3-53451.6"
147724   wire width 8 $1\xive4_pri$next[7:0]$2474
147725   attribute \src "libresoc.v:53198.13-53198.30"
147726   wire width 8 $1\xive4_pri[7:0]
147727   attribute \src "libresoc.v:53366.3-53451.6"
147728   wire width 8 $1\xive5_pri$next[7:0]$2475
147729   attribute \src "libresoc.v:53202.13-53202.30"
147730   wire width 8 $1\xive5_pri[7:0]
147731   attribute \src "libresoc.v:53366.3-53451.6"
147732   wire width 8 $1\xive6_pri$next[7:0]$2476
147733   attribute \src "libresoc.v:53206.13-53206.30"
147734   wire width 8 $1\xive6_pri[7:0]
147735   attribute \src "libresoc.v:53366.3-53451.6"
147736   wire width 8 $1\xive7_pri$next[7:0]$2477
147737   attribute \src "libresoc.v:53210.13-53210.30"
147738   wire width 8 $1\xive7_pri[7:0]
147739   attribute \src "libresoc.v:53366.3-53451.6"
147740   wire width 8 $1\xive8_pri$next[7:0]$2478
147741   attribute \src "libresoc.v:53214.13-53214.30"
147742   wire width 8 $1\xive8_pri[7:0]
147743   attribute \src "libresoc.v:53366.3-53451.6"
147744   wire width 8 $1\xive9_pri$next[7:0]$2479
147745   attribute \src "libresoc.v:53218.13-53218.30"
147746   wire width 8 $1\xive9_pri[7:0]
147747   attribute \src "libresoc.v:53751.3-53800.6"
147748   wire width 32 $2\be_out[31:0]
147749   attribute \src "libresoc.v:53366.3-53451.6"
147750   wire width 8 $2\xive0_pri$next[7:0]$2480
147751   attribute \src "libresoc.v:53366.3-53451.6"
147752   wire width 8 $2\xive10_pri$next[7:0]$2481
147753   attribute \src "libresoc.v:53366.3-53451.6"
147754   wire width 8 $2\xive11_pri$next[7:0]$2482
147755   attribute \src "libresoc.v:53366.3-53451.6"
147756   wire width 8 $2\xive12_pri$next[7:0]$2483
147757   attribute \src "libresoc.v:53366.3-53451.6"
147758   wire width 8 $2\xive13_pri$next[7:0]$2484
147759   attribute \src "libresoc.v:53366.3-53451.6"
147760   wire width 8 $2\xive14_pri$next[7:0]$2485
147761   attribute \src "libresoc.v:53366.3-53451.6"
147762   wire width 8 $2\xive15_pri$next[7:0]$2486
147763   attribute \src "libresoc.v:53366.3-53451.6"
147764   wire width 8 $2\xive1_pri$next[7:0]$2487
147765   attribute \src "libresoc.v:53366.3-53451.6"
147766   wire width 8 $2\xive2_pri$next[7:0]$2488
147767   attribute \src "libresoc.v:53366.3-53451.6"
147768   wire width 8 $2\xive3_pri$next[7:0]$2489
147769   attribute \src "libresoc.v:53366.3-53451.6"
147770   wire width 8 $2\xive4_pri$next[7:0]$2490
147771   attribute \src "libresoc.v:53366.3-53451.6"
147772   wire width 8 $2\xive5_pri$next[7:0]$2491
147773   attribute \src "libresoc.v:53366.3-53451.6"
147774   wire width 8 $2\xive6_pri$next[7:0]$2492
147775   attribute \src "libresoc.v:53366.3-53451.6"
147776   wire width 8 $2\xive7_pri$next[7:0]$2493
147777   attribute \src "libresoc.v:53366.3-53451.6"
147778   wire width 8 $2\xive8_pri$next[7:0]$2494
147779   attribute \src "libresoc.v:53366.3-53451.6"
147780   wire width 8 $2\xive9_pri$next[7:0]$2495
147781   attribute \src "libresoc.v:53366.3-53451.6"
147782   wire width 8 $3\xive0_pri$next[7:0]$2496
147783   attribute \src "libresoc.v:53366.3-53451.6"
147784   wire width 8 $3\xive10_pri$next[7:0]$2497
147785   attribute \src "libresoc.v:53366.3-53451.6"
147786   wire width 8 $3\xive11_pri$next[7:0]$2498
147787   attribute \src "libresoc.v:53366.3-53451.6"
147788   wire width 8 $3\xive12_pri$next[7:0]$2499
147789   attribute \src "libresoc.v:53366.3-53451.6"
147790   wire width 8 $3\xive13_pri$next[7:0]$2500
147791   attribute \src "libresoc.v:53366.3-53451.6"
147792   wire width 8 $3\xive14_pri$next[7:0]$2501
147793   attribute \src "libresoc.v:53366.3-53451.6"
147794   wire width 8 $3\xive15_pri$next[7:0]$2502
147795   attribute \src "libresoc.v:53366.3-53451.6"
147796   wire width 8 $3\xive1_pri$next[7:0]$2503
147797   attribute \src "libresoc.v:53366.3-53451.6"
147798   wire width 8 $3\xive2_pri$next[7:0]$2504
147799   attribute \src "libresoc.v:53366.3-53451.6"
147800   wire width 8 $3\xive3_pri$next[7:0]$2505
147801   attribute \src "libresoc.v:53366.3-53451.6"
147802   wire width 8 $3\xive4_pri$next[7:0]$2506
147803   attribute \src "libresoc.v:53366.3-53451.6"
147804   wire width 8 $3\xive5_pri$next[7:0]$2507
147805   attribute \src "libresoc.v:53366.3-53451.6"
147806   wire width 8 $3\xive6_pri$next[7:0]$2508
147807   attribute \src "libresoc.v:53366.3-53451.6"
147808   wire width 8 $3\xive7_pri$next[7:0]$2509
147809   attribute \src "libresoc.v:53366.3-53451.6"
147810   wire width 8 $3\xive8_pri$next[7:0]$2510
147811   attribute \src "libresoc.v:53366.3-53451.6"
147812   wire width 8 $3\xive9_pri$next[7:0]$2511
147813   attribute \src "libresoc.v:53366.3-53451.6"
147814   wire width 8 $4\xive0_pri$next[7:0]$2512
147815   attribute \src "libresoc.v:53366.3-53451.6"
147816   wire width 8 $4\xive10_pri$next[7:0]$2513
147817   attribute \src "libresoc.v:53366.3-53451.6"
147818   wire width 8 $4\xive11_pri$next[7:0]$2514
147819   attribute \src "libresoc.v:53366.3-53451.6"
147820   wire width 8 $4\xive12_pri$next[7:0]$2515
147821   attribute \src "libresoc.v:53366.3-53451.6"
147822   wire width 8 $4\xive13_pri$next[7:0]$2516
147823   attribute \src "libresoc.v:53366.3-53451.6"
147824   wire width 8 $4\xive14_pri$next[7:0]$2517
147825   attribute \src "libresoc.v:53366.3-53451.6"
147826   wire width 8 $4\xive15_pri$next[7:0]$2518
147827   attribute \src "libresoc.v:53366.3-53451.6"
147828   wire width 8 $4\xive1_pri$next[7:0]$2519
147829   attribute \src "libresoc.v:53366.3-53451.6"
147830   wire width 8 $4\xive2_pri$next[7:0]$2520
147831   attribute \src "libresoc.v:53366.3-53451.6"
147832   wire width 8 $4\xive3_pri$next[7:0]$2521
147833   attribute \src "libresoc.v:53366.3-53451.6"
147834   wire width 8 $4\xive4_pri$next[7:0]$2522
147835   attribute \src "libresoc.v:53366.3-53451.6"
147836   wire width 8 $4\xive5_pri$next[7:0]$2523
147837   attribute \src "libresoc.v:53366.3-53451.6"
147838   wire width 8 $4\xive6_pri$next[7:0]$2524
147839   attribute \src "libresoc.v:53366.3-53451.6"
147840   wire width 8 $4\xive7_pri$next[7:0]$2525
147841   attribute \src "libresoc.v:53366.3-53451.6"
147842   wire width 8 $4\xive8_pri$next[7:0]$2526
147843   attribute \src "libresoc.v:53366.3-53451.6"
147844   wire width 8 $4\xive9_pri$next[7:0]$2527
147845   attribute \src "libresoc.v:53223.19-53223.113"
147846   wire $and$libresoc.v:53223$2325_Y
147847   attribute \src "libresoc.v:53225.19-53225.114"
147848   wire $and$libresoc.v:53225$2327_Y
147849   attribute \src "libresoc.v:53227.19-53227.114"
147850   wire $and$libresoc.v:53227$2329_Y
147851   attribute \src "libresoc.v:53229.19-53229.114"
147852   wire $and$libresoc.v:53229$2331_Y
147853   attribute \src "libresoc.v:53231.19-53231.114"
147854   wire $and$libresoc.v:53231$2333_Y
147855   attribute \src "libresoc.v:53233.19-53233.114"
147856   wire $and$libresoc.v:53233$2335_Y
147857   attribute \src "libresoc.v:53235.19-53235.114"
147858   wire $and$libresoc.v:53235$2337_Y
147859   attribute \src "libresoc.v:53238.19-53238.114"
147860   wire $and$libresoc.v:53238$2340_Y
147861   attribute \src "libresoc.v:53240.19-53240.114"
147862   wire $and$libresoc.v:53240$2342_Y
147863   attribute \src "libresoc.v:53242.19-53242.114"
147864   wire $and$libresoc.v:53242$2344_Y
147865   attribute \src "libresoc.v:53245.19-53245.114"
147866   wire $and$libresoc.v:53245$2347_Y
147867   attribute \src "libresoc.v:53247.19-53247.114"
147868   wire $and$libresoc.v:53247$2349_Y
147869   attribute \src "libresoc.v:53249.19-53249.114"
147870   wire $and$libresoc.v:53249$2351_Y
147871   attribute \src "libresoc.v:53251.19-53251.114"
147872   wire $and$libresoc.v:53251$2353_Y
147873   attribute \src "libresoc.v:53253.19-53253.115"
147874   wire $and$libresoc.v:53253$2355_Y
147875   attribute \src "libresoc.v:53255.19-53255.115"
147876   wire $and$libresoc.v:53255$2357_Y
147877   attribute \src "libresoc.v:53257.19-53257.115"
147878   wire $and$libresoc.v:53257$2359_Y
147879   attribute \src "libresoc.v:53260.19-53260.115"
147880   wire $and$libresoc.v:53260$2362_Y
147881   attribute \src "libresoc.v:53262.19-53262.115"
147882   wire $and$libresoc.v:53262$2364_Y
147883   attribute \src "libresoc.v:53264.19-53264.115"
147884   wire $and$libresoc.v:53264$2366_Y
147885   attribute \src "libresoc.v:53267.19-53267.115"
147886   wire $and$libresoc.v:53267$2369_Y
147887   attribute \src "libresoc.v:53269.19-53269.115"
147888   wire $and$libresoc.v:53269$2371_Y
147889   attribute \src "libresoc.v:53271.19-53271.115"
147890   wire $and$libresoc.v:53271$2373_Y
147891   attribute \src "libresoc.v:53273.19-53273.115"
147892   wire $and$libresoc.v:53273$2375_Y
147893   attribute \src "libresoc.v:53275.19-53275.115"
147894   wire $and$libresoc.v:53275$2377_Y
147895   attribute \src "libresoc.v:53278.19-53278.115"
147896   wire $and$libresoc.v:53278$2380_Y
147897   attribute \src "libresoc.v:53302.17-53302.115"
147898   wire $and$libresoc.v:53302$2404_Y
147899   attribute \src "libresoc.v:53310.18-53310.112"
147900   wire $and$libresoc.v:53310$2412_Y
147901   attribute \src "libresoc.v:53312.18-53312.112"
147902   wire $and$libresoc.v:53312$2414_Y
147903   attribute \src "libresoc.v:53314.18-53314.112"
147904   wire $and$libresoc.v:53314$2416_Y
147905   attribute \src "libresoc.v:53316.18-53316.112"
147906   wire $and$libresoc.v:53316$2418_Y
147907   attribute \src "libresoc.v:53319.18-53319.112"
147908   wire $and$libresoc.v:53319$2421_Y
147909   attribute \src "libresoc.v:53321.18-53321.112"
147910   wire $and$libresoc.v:53321$2423_Y
147911   attribute \src "libresoc.v:53323.18-53323.112"
147912   wire $and$libresoc.v:53323$2425_Y
147913   attribute \src "libresoc.v:53237.18-53237.109"
147914   wire $eq$libresoc.v:53237$2339_Y
147915   attribute \src "libresoc.v:53259.18-53259.109"
147916   wire $eq$libresoc.v:53259$2361_Y
147917   attribute \src "libresoc.v:53276.17-53276.114"
147918   wire $eq$libresoc.v:53276$2378_Y
147919   attribute \src "libresoc.v:53279.19-53279.110"
147920   wire $eq$libresoc.v:53279$2381_Y
147921   attribute \src "libresoc.v:53281.18-53281.109"
147922   wire $eq$libresoc.v:53281$2383_Y
147923   attribute \src "libresoc.v:53283.18-53283.109"
147924   wire $eq$libresoc.v:53283$2385_Y
147925   attribute \src "libresoc.v:53285.18-53285.109"
147926   wire $eq$libresoc.v:53285$2387_Y
147927   attribute \src "libresoc.v:53287.18-53287.109"
147928   wire $eq$libresoc.v:53287$2389_Y
147929   attribute \src "libresoc.v:53289.18-53289.109"
147930   wire $eq$libresoc.v:53289$2391_Y
147931   attribute \src "libresoc.v:53291.17-53291.114"
147932   wire $eq$libresoc.v:53291$2393_Y
147933   attribute \src "libresoc.v:53292.18-53292.109"
147934   wire $eq$libresoc.v:53292$2394_Y
147935   attribute \src "libresoc.v:53294.18-53294.109"
147936   wire $eq$libresoc.v:53294$2396_Y
147937   attribute \src "libresoc.v:53296.18-53296.110"
147938   wire $eq$libresoc.v:53296$2398_Y
147939   attribute \src "libresoc.v:53298.18-53298.110"
147940   wire $eq$libresoc.v:53298$2400_Y
147941   attribute \src "libresoc.v:53300.18-53300.110"
147942   wire $eq$libresoc.v:53300$2402_Y
147943   attribute \src "libresoc.v:53303.18-53303.110"
147944   wire $eq$libresoc.v:53303$2405_Y
147945   attribute \src "libresoc.v:53305.18-53305.110"
147946   wire $eq$libresoc.v:53305$2407_Y
147947   attribute \src "libresoc.v:53307.18-53307.110"
147948   wire $eq$libresoc.v:53307$2409_Y
147949   attribute \src "libresoc.v:53318.17-53318.108"
147950   wire $eq$libresoc.v:53318$2420_Y
147951   attribute \src "libresoc.v:53222.18-53222.111"
147952   wire $lt$libresoc.v:53222$2324_Y
147953   attribute \src "libresoc.v:53224.19-53224.112"
147954   wire $lt$libresoc.v:53224$2326_Y
147955   attribute \src "libresoc.v:53226.19-53226.112"
147956   wire $lt$libresoc.v:53226$2328_Y
147957   attribute \src "libresoc.v:53228.19-53228.112"
147958   wire $lt$libresoc.v:53228$2330_Y
147959   attribute \src "libresoc.v:53230.19-53230.112"
147960   wire $lt$libresoc.v:53230$2332_Y
147961   attribute \src "libresoc.v:53232.19-53232.112"
147962   wire $lt$libresoc.v:53232$2334_Y
147963   attribute \src "libresoc.v:53234.19-53234.112"
147964   wire $lt$libresoc.v:53234$2336_Y
147965   attribute \src "libresoc.v:53236.19-53236.112"
147966   wire $lt$libresoc.v:53236$2338_Y
147967   attribute \src "libresoc.v:53239.19-53239.112"
147968   wire $lt$libresoc.v:53239$2341_Y
147969   attribute \src "libresoc.v:53241.19-53241.112"
147970   wire $lt$libresoc.v:53241$2343_Y
147971   attribute \src "libresoc.v:53244.19-53244.112"
147972   wire $lt$libresoc.v:53244$2346_Y
147973   attribute \src "libresoc.v:53246.19-53246.112"
147974   wire $lt$libresoc.v:53246$2348_Y
147975   attribute \src "libresoc.v:53248.19-53248.112"
147976   wire $lt$libresoc.v:53248$2350_Y
147977   attribute \src "libresoc.v:53250.19-53250.112"
147978   wire $lt$libresoc.v:53250$2352_Y
147979   attribute \src "libresoc.v:53252.19-53252.113"
147980   wire $lt$libresoc.v:53252$2354_Y
147981   attribute \src "libresoc.v:53254.19-53254.113"
147982   wire $lt$libresoc.v:53254$2356_Y
147983   attribute \src "libresoc.v:53256.19-53256.114"
147984   wire $lt$libresoc.v:53256$2358_Y
147985   attribute \src "libresoc.v:53258.19-53258.114"
147986   wire $lt$libresoc.v:53258$2360_Y
147987   attribute \src "libresoc.v:53261.19-53261.114"
147988   wire $lt$libresoc.v:53261$2363_Y
147989   attribute \src "libresoc.v:53263.19-53263.114"
147990   wire $lt$libresoc.v:53263$2365_Y
147991   attribute \src "libresoc.v:53266.19-53266.114"
147992   wire $lt$libresoc.v:53266$2368_Y
147993   attribute \src "libresoc.v:53268.19-53268.114"
147994   wire $lt$libresoc.v:53268$2370_Y
147995   attribute \src "libresoc.v:53270.19-53270.114"
147996   wire $lt$libresoc.v:53270$2372_Y
147997   attribute \src "libresoc.v:53272.19-53272.114"
147998   wire $lt$libresoc.v:53272$2374_Y
147999   attribute \src "libresoc.v:53274.19-53274.114"
148000   wire $lt$libresoc.v:53274$2376_Y
148001   attribute \src "libresoc.v:53277.19-53277.114"
148002   wire $lt$libresoc.v:53277$2379_Y
148003   attribute \src "libresoc.v:53311.18-53311.110"
148004   wire $lt$libresoc.v:53311$2413_Y
148005   attribute \src "libresoc.v:53313.18-53313.110"
148006   wire $lt$libresoc.v:53313$2415_Y
148007   attribute \src "libresoc.v:53315.18-53315.111"
148008   wire $lt$libresoc.v:53315$2417_Y
148009   attribute \src "libresoc.v:53317.18-53317.111"
148010   wire $lt$libresoc.v:53317$2419_Y
148011   attribute \src "libresoc.v:53320.18-53320.111"
148012   wire $lt$libresoc.v:53320$2422_Y
148013   attribute \src "libresoc.v:53322.18-53322.111"
148014   wire $lt$libresoc.v:53322$2424_Y
148015   attribute \src "libresoc.v:53309.18-53309.40"
148016   wire width 16 $shr$libresoc.v:53309$2411_Y
148017   attribute \src "libresoc.v:53221.17-53221.114"
148018   wire width 8 $ternary$libresoc.v:53221$2323_Y
148019   attribute \src "libresoc.v:53243.18-53243.116"
148020   wire width 8 $ternary$libresoc.v:53243$2345_Y
148021   attribute \src "libresoc.v:53265.18-53265.116"
148022   wire width 8 $ternary$libresoc.v:53265$2367_Y
148023   attribute \src "libresoc.v:53280.19-53280.118"
148024   wire width 8 $ternary$libresoc.v:53280$2382_Y
148025   attribute \src "libresoc.v:53282.18-53282.116"
148026   wire width 8 $ternary$libresoc.v:53282$2384_Y
148027   attribute \src "libresoc.v:53284.18-53284.116"
148028   wire width 8 $ternary$libresoc.v:53284$2386_Y
148029   attribute \src "libresoc.v:53286.18-53286.116"
148030   wire width 8 $ternary$libresoc.v:53286$2388_Y
148031   attribute \src "libresoc.v:53288.18-53288.116"
148032   wire width 8 $ternary$libresoc.v:53288$2390_Y
148033   attribute \src "libresoc.v:53290.18-53290.116"
148034   wire width 8 $ternary$libresoc.v:53290$2392_Y
148035   attribute \src "libresoc.v:53293.18-53293.116"
148036   wire width 8 $ternary$libresoc.v:53293$2395_Y
148037   attribute \src "libresoc.v:53295.18-53295.116"
148038   wire width 8 $ternary$libresoc.v:53295$2397_Y
148039   attribute \src "libresoc.v:53297.18-53297.117"
148040   wire width 8 $ternary$libresoc.v:53297$2399_Y
148041   attribute \src "libresoc.v:53299.18-53299.117"
148042   wire width 8 $ternary$libresoc.v:53299$2401_Y
148043   attribute \src "libresoc.v:53301.18-53301.117"
148044   wire width 8 $ternary$libresoc.v:53301$2403_Y
148045   attribute \src "libresoc.v:53304.18-53304.117"
148046   wire width 8 $ternary$libresoc.v:53304$2406_Y
148047   attribute \src "libresoc.v:53306.18-53306.117"
148048   wire width 8 $ternary$libresoc.v:53306$2408_Y
148049   attribute \src "libresoc.v:53308.18-53308.117"
148050   wire width 8 $ternary$libresoc.v:53308$2410_Y
148051   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
148052   wire \$1
148053   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148054   wire \$101
148055   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148056   wire \$103
148057   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148058   wire \$105
148059   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148060   wire \$107
148061   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148062   wire \$109
148063   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148064   wire width 8 \$11
148065   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148066   wire \$111
148067   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148068   wire \$113
148069   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148070   wire \$115
148071   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148072   wire \$117
148073   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148074   wire \$119
148075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148076   wire \$12
148077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148078   wire \$121
148079   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148080   wire \$123
148081   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148082   wire \$125
148083   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148084   wire \$127
148085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148086   wire \$129
148087   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148088   wire \$131
148089   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148090   wire \$133
148091   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148092   wire \$135
148093   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148094   wire \$137
148095   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148096   wire \$139
148097   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148098   wire \$141
148099   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148100   wire \$143
148101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148102   wire \$145
148103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148104   wire \$147
148105   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148106   wire \$149
148107   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148108   wire width 8 \$15
148109   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148110   wire \$151
148111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148112   wire \$153
148113   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148114   wire \$155
148115   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148116   wire \$157
148117   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148118   wire \$159
148119   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148120   wire \$16
148121   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148122   wire \$161
148123   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148124   wire \$163
148125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148126   wire \$165
148127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148128   wire \$167
148129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148130   wire \$169
148131   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148132   wire \$171
148133   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148134   wire \$173
148135   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148136   wire \$175
148137   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148138   wire \$177
148139   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148140   wire \$179
148141   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148142   wire \$181
148143   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148144   wire \$183
148145   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148146   wire \$185
148147   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148148   wire \$187
148149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148150   wire \$189
148151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148152   wire width 8 \$19
148153   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148154   wire \$191
148155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148156   wire \$193
148157   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148158   wire \$195
148159   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148160   wire \$197
148161   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148162   wire \$199
148163   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148164   wire \$20
148165   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148166   wire \$201
148167   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148168   wire width 8 \$203
148169   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148170   wire \$204
148171   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148172   wire width 8 \$23
148173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148174   wire \$24
148175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148176   wire width 8 \$27
148177   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148178   wire \$28
148179   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
148180   wire \$3
148181   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148182   wire width 8 \$31
148183   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148184   wire \$32
148185   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148186   wire width 8 \$35
148187   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148188   wire \$36
148189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148190   wire width 8 \$39
148191   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148192   wire \$40
148193   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148194   wire width 8 \$43
148195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148196   wire \$44
148197   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148198   wire width 8 \$47
148199   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148200   wire \$48
148201   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
148202   wire \$5
148203   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148204   wire width 8 \$51
148205   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148206   wire \$52
148207   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148208   wire width 8 \$55
148209   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148210   wire \$56
148211   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148212   wire width 8 \$59
148213   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148214   wire \$60
148215   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148216   wire width 8 \$63
148217   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148218   wire \$64
148219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148220   wire width 8 \$67
148221   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148222   wire \$68
148223   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148224   wire width 8 \$7
148225   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:315"
148226   wire \$71
148227   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
148228   wire \$73
148229   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148230   wire \$75
148231   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148232   wire \$77
148233   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148234   wire \$79
148235   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148236   wire \$8
148237   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148238   wire \$81
148239   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148240   wire \$83
148241   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148242   wire \$85
148243   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148244   wire \$87
148245   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148246   wire \$89
148247   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148248   wire \$91
148249   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148250   wire \$93
148251   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148252   wire \$95
148253   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148254   wire \$97
148255   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
148256   wire \$99
148257   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:337"
148258   wire width 32 \be_in
148259   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308"
148260   wire width 32 \be_out
148261   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
148262   wire input 12 \clk
148263   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148264   wire width 4 \cur_idx0
148265   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148266   wire width 4 \cur_idx1
148267   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148268   wire width 4 \cur_idx10
148269   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148270   wire width 4 \cur_idx11
148271   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148272   wire width 4 \cur_idx12
148273   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148274   wire width 4 \cur_idx13
148275   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148276   wire width 4 \cur_idx14
148277   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148278   wire width 4 \cur_idx15
148279   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148280   wire width 4 \cur_idx2
148281   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148282   wire width 4 \cur_idx3
148283   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148284   wire width 4 \cur_idx4
148285   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148286   wire width 4 \cur_idx5
148287   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148288   wire width 4 \cur_idx6
148289   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148290   wire width 4 \cur_idx7
148291   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148292   wire width 4 \cur_idx8
148293   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
148294   wire width 4 \cur_idx9
148295   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148296   wire width 8 \cur_pri0
148297   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148298   wire width 8 \cur_pri1
148299   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148300   wire width 8 \cur_pri10
148301   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148302   wire width 8 \cur_pri11
148303   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148304   wire width 8 \cur_pri12
148305   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148306   wire width 8 \cur_pri13
148307   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148308   wire width 8 \cur_pri14
148309   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148310   wire width 8 \cur_pri15
148311   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148312   wire width 8 \cur_pri2
148313   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148314   wire width 8 \cur_pri3
148315   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148316   wire width 8 \cur_pri4
148317   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148318   wire width 8 \cur_pri5
148319   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148320   wire width 8 \cur_pri6
148321   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148322   wire width 8 \cur_pri7
148323   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148324   wire width 8 \cur_pri8
148325   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366"
148326   wire width 8 \cur_pri9
148327   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314"
148328   wire \ibit
148329   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
148330   wire width 8 output 3 \icp_o_pri
148331   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
148332   wire width 8 \icp_o_pri$next
148333   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
148334   wire width 4 output 2 \icp_o_src
148335   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
148336   wire width 4 \icp_o_src$next
148337   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46"
148338   wire width 8 \icp_r_pri
148339   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
148340   wire width 4 \icp_r_src
148341   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148342   wire output 9 \ics_wb__ack
148343   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148344   wire \ics_wb__ack$next
148345   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148346   wire width 28 input 4 \ics_wb__adr
148347   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148348   wire input 6 \ics_wb__cyc
148349   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148350   wire width 32 output 8 \ics_wb__dat_r
148351   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148352   wire width 32 \ics_wb__dat_r$next
148353   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148354   wire width 32 input 10 \ics_wb__dat_w
148355   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148356   wire input 7 \ics_wb__stb
148357   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
148358   wire input 11 \ics_wb__we
148359   attribute \src "libresoc.v:52822.7-52822.15"
148360   wire \initial
148361   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
148362   wire width 16 input 5 \int_level_i
148363   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263"
148364   wire width 16 \int_level_l
148365   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263"
148366   wire width 16 \int_level_l$next
148367   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358"
148368   wire width 4 \max_idx
148369   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359"
148370   wire width 8 \max_pri
148371   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:261"
148372   wire width 4 \reg_idx
148373   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:287"
148374   wire \reg_is_config
148375   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:288"
148376   wire \reg_is_debug
148377   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286"
148378   wire \reg_is_xive
148379   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168"
148380   wire input 1 \rst
148381   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260"
148382   wire \wb_valid
148383   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148384   wire width 8 \xive0_pri
148385   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148386   wire width 8 \xive0_pri$next
148387   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148388   wire width 8 \xive10_pri
148389   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148390   wire width 8 \xive10_pri$next
148391   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148392   wire width 8 \xive11_pri
148393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148394   wire width 8 \xive11_pri$next
148395   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148396   wire width 8 \xive12_pri
148397   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148398   wire width 8 \xive12_pri$next
148399   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148400   wire width 8 \xive13_pri
148401   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148402   wire width 8 \xive13_pri$next
148403   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148404   wire width 8 \xive14_pri
148405   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148406   wire width 8 \xive14_pri$next
148407   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148408   wire width 8 \xive15_pri
148409   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148410   wire width 8 \xive15_pri$next
148411   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148412   wire width 8 \xive1_pri
148413   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148414   wire width 8 \xive1_pri$next
148415   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148416   wire width 8 \xive2_pri
148417   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148418   wire width 8 \xive2_pri$next
148419   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148420   wire width 8 \xive3_pri
148421   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148422   wire width 8 \xive3_pri$next
148423   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148424   wire width 8 \xive4_pri
148425   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148426   wire width 8 \xive4_pri$next
148427   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148428   wire width 8 \xive5_pri
148429   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148430   wire width 8 \xive5_pri$next
148431   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148432   wire width 8 \xive6_pri
148433   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148434   wire width 8 \xive6_pri$next
148435   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148436   wire width 8 \xive7_pri
148437   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148438   wire width 8 \xive7_pri$next
148439   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148440   wire width 8 \xive8_pri
148441   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148442   wire width 8 \xive8_pri$next
148443   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148444   wire width 8 \xive9_pri
148445   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
148446   wire width 8 \xive9_pri$next
148447   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148448   cell $and $and$libresoc.v:53223$2325
148449     parameter \A_SIGNED 0
148450     parameter \A_WIDTH 1
148451     parameter \B_SIGNED 0
148452     parameter \B_WIDTH 1
148453     parameter \Y_WIDTH 1
148454     connect \A \int_level_l [3]
148455     connect \B \$99
148456     connect \Y $and$libresoc.v:53223$2325_Y
148457   end
148458   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148459   cell $and $and$libresoc.v:53225$2327
148460     parameter \A_SIGNED 0
148461     parameter \A_WIDTH 1
148462     parameter \B_SIGNED 0
148463     parameter \B_WIDTH 1
148464     parameter \Y_WIDTH 1
148465     connect \A \int_level_l [3]
148466     connect \B \$103
148467     connect \Y $and$libresoc.v:53225$2327_Y
148468   end
148469   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148470   cell $and $and$libresoc.v:53227$2329
148471     parameter \A_SIGNED 0
148472     parameter \A_WIDTH 1
148473     parameter \B_SIGNED 0
148474     parameter \B_WIDTH 1
148475     parameter \Y_WIDTH 1
148476     connect \A \int_level_l [4]
148477     connect \B \$107
148478     connect \Y $and$libresoc.v:53227$2329_Y
148479   end
148480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148481   cell $and $and$libresoc.v:53229$2331
148482     parameter \A_SIGNED 0
148483     parameter \A_WIDTH 1
148484     parameter \B_SIGNED 0
148485     parameter \B_WIDTH 1
148486     parameter \Y_WIDTH 1
148487     connect \A \int_level_l [4]
148488     connect \B \$111
148489     connect \Y $and$libresoc.v:53229$2331_Y
148490   end
148491   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148492   cell $and $and$libresoc.v:53231$2333
148493     parameter \A_SIGNED 0
148494     parameter \A_WIDTH 1
148495     parameter \B_SIGNED 0
148496     parameter \B_WIDTH 1
148497     parameter \Y_WIDTH 1
148498     connect \A \int_level_l [5]
148499     connect \B \$115
148500     connect \Y $and$libresoc.v:53231$2333_Y
148501   end
148502   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148503   cell $and $and$libresoc.v:53233$2335
148504     parameter \A_SIGNED 0
148505     parameter \A_WIDTH 1
148506     parameter \B_SIGNED 0
148507     parameter \B_WIDTH 1
148508     parameter \Y_WIDTH 1
148509     connect \A \int_level_l [5]
148510     connect \B \$119
148511     connect \Y $and$libresoc.v:53233$2335_Y
148512   end
148513   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148514   cell $and $and$libresoc.v:53235$2337
148515     parameter \A_SIGNED 0
148516     parameter \A_WIDTH 1
148517     parameter \B_SIGNED 0
148518     parameter \B_WIDTH 1
148519     parameter \Y_WIDTH 1
148520     connect \A \int_level_l [6]
148521     connect \B \$123
148522     connect \Y $and$libresoc.v:53235$2337_Y
148523   end
148524   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148525   cell $and $and$libresoc.v:53238$2340
148526     parameter \A_SIGNED 0
148527     parameter \A_WIDTH 1
148528     parameter \B_SIGNED 0
148529     parameter \B_WIDTH 1
148530     parameter \Y_WIDTH 1
148531     connect \A \int_level_l [6]
148532     connect \B \$127
148533     connect \Y $and$libresoc.v:53238$2340_Y
148534   end
148535   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148536   cell $and $and$libresoc.v:53240$2342
148537     parameter \A_SIGNED 0
148538     parameter \A_WIDTH 1
148539     parameter \B_SIGNED 0
148540     parameter \B_WIDTH 1
148541     parameter \Y_WIDTH 1
148542     connect \A \int_level_l [7]
148543     connect \B \$131
148544     connect \Y $and$libresoc.v:53240$2342_Y
148545   end
148546   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148547   cell $and $and$libresoc.v:53242$2344
148548     parameter \A_SIGNED 0
148549     parameter \A_WIDTH 1
148550     parameter \B_SIGNED 0
148551     parameter \B_WIDTH 1
148552     parameter \Y_WIDTH 1
148553     connect \A \int_level_l [7]
148554     connect \B \$135
148555     connect \Y $and$libresoc.v:53242$2344_Y
148556   end
148557   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148558   cell $and $and$libresoc.v:53245$2347
148559     parameter \A_SIGNED 0
148560     parameter \A_WIDTH 1
148561     parameter \B_SIGNED 0
148562     parameter \B_WIDTH 1
148563     parameter \Y_WIDTH 1
148564     connect \A \int_level_l [8]
148565     connect \B \$139
148566     connect \Y $and$libresoc.v:53245$2347_Y
148567   end
148568   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148569   cell $and $and$libresoc.v:53247$2349
148570     parameter \A_SIGNED 0
148571     parameter \A_WIDTH 1
148572     parameter \B_SIGNED 0
148573     parameter \B_WIDTH 1
148574     parameter \Y_WIDTH 1
148575     connect \A \int_level_l [8]
148576     connect \B \$143
148577     connect \Y $and$libresoc.v:53247$2349_Y
148578   end
148579   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148580   cell $and $and$libresoc.v:53249$2351
148581     parameter \A_SIGNED 0
148582     parameter \A_WIDTH 1
148583     parameter \B_SIGNED 0
148584     parameter \B_WIDTH 1
148585     parameter \Y_WIDTH 1
148586     connect \A \int_level_l [9]
148587     connect \B \$147
148588     connect \Y $and$libresoc.v:53249$2351_Y
148589   end
148590   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148591   cell $and $and$libresoc.v:53251$2353
148592     parameter \A_SIGNED 0
148593     parameter \A_WIDTH 1
148594     parameter \B_SIGNED 0
148595     parameter \B_WIDTH 1
148596     parameter \Y_WIDTH 1
148597     connect \A \int_level_l [9]
148598     connect \B \$151
148599     connect \Y $and$libresoc.v:53251$2353_Y
148600   end
148601   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148602   cell $and $and$libresoc.v:53253$2355
148603     parameter \A_SIGNED 0
148604     parameter \A_WIDTH 1
148605     parameter \B_SIGNED 0
148606     parameter \B_WIDTH 1
148607     parameter \Y_WIDTH 1
148608     connect \A \int_level_l [10]
148609     connect \B \$155
148610     connect \Y $and$libresoc.v:53253$2355_Y
148611   end
148612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148613   cell $and $and$libresoc.v:53255$2357
148614     parameter \A_SIGNED 0
148615     parameter \A_WIDTH 1
148616     parameter \B_SIGNED 0
148617     parameter \B_WIDTH 1
148618     parameter \Y_WIDTH 1
148619     connect \A \int_level_l [10]
148620     connect \B \$159
148621     connect \Y $and$libresoc.v:53255$2357_Y
148622   end
148623   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148624   cell $and $and$libresoc.v:53257$2359
148625     parameter \A_SIGNED 0
148626     parameter \A_WIDTH 1
148627     parameter \B_SIGNED 0
148628     parameter \B_WIDTH 1
148629     parameter \Y_WIDTH 1
148630     connect \A \int_level_l [11]
148631     connect \B \$163
148632     connect \Y $and$libresoc.v:53257$2359_Y
148633   end
148634   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148635   cell $and $and$libresoc.v:53260$2362
148636     parameter \A_SIGNED 0
148637     parameter \A_WIDTH 1
148638     parameter \B_SIGNED 0
148639     parameter \B_WIDTH 1
148640     parameter \Y_WIDTH 1
148641     connect \A \int_level_l [11]
148642     connect \B \$167
148643     connect \Y $and$libresoc.v:53260$2362_Y
148644   end
148645   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148646   cell $and $and$libresoc.v:53262$2364
148647     parameter \A_SIGNED 0
148648     parameter \A_WIDTH 1
148649     parameter \B_SIGNED 0
148650     parameter \B_WIDTH 1
148651     parameter \Y_WIDTH 1
148652     connect \A \int_level_l [12]
148653     connect \B \$171
148654     connect \Y $and$libresoc.v:53262$2364_Y
148655   end
148656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148657   cell $and $and$libresoc.v:53264$2366
148658     parameter \A_SIGNED 0
148659     parameter \A_WIDTH 1
148660     parameter \B_SIGNED 0
148661     parameter \B_WIDTH 1
148662     parameter \Y_WIDTH 1
148663     connect \A \int_level_l [12]
148664     connect \B \$175
148665     connect \Y $and$libresoc.v:53264$2366_Y
148666   end
148667   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148668   cell $and $and$libresoc.v:53267$2369
148669     parameter \A_SIGNED 0
148670     parameter \A_WIDTH 1
148671     parameter \B_SIGNED 0
148672     parameter \B_WIDTH 1
148673     parameter \Y_WIDTH 1
148674     connect \A \int_level_l [13]
148675     connect \B \$179
148676     connect \Y $and$libresoc.v:53267$2369_Y
148677   end
148678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148679   cell $and $and$libresoc.v:53269$2371
148680     parameter \A_SIGNED 0
148681     parameter \A_WIDTH 1
148682     parameter \B_SIGNED 0
148683     parameter \B_WIDTH 1
148684     parameter \Y_WIDTH 1
148685     connect \A \int_level_l [13]
148686     connect \B \$183
148687     connect \Y $and$libresoc.v:53269$2371_Y
148688   end
148689   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148690   cell $and $and$libresoc.v:53271$2373
148691     parameter \A_SIGNED 0
148692     parameter \A_WIDTH 1
148693     parameter \B_SIGNED 0
148694     parameter \B_WIDTH 1
148695     parameter \Y_WIDTH 1
148696     connect \A \int_level_l [14]
148697     connect \B \$187
148698     connect \Y $and$libresoc.v:53271$2373_Y
148699   end
148700   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148701   cell $and $and$libresoc.v:53273$2375
148702     parameter \A_SIGNED 0
148703     parameter \A_WIDTH 1
148704     parameter \B_SIGNED 0
148705     parameter \B_WIDTH 1
148706     parameter \Y_WIDTH 1
148707     connect \A \int_level_l [14]
148708     connect \B \$191
148709     connect \Y $and$libresoc.v:53273$2375_Y
148710   end
148711   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148712   cell $and $and$libresoc.v:53275$2377
148713     parameter \A_SIGNED 0
148714     parameter \A_WIDTH 1
148715     parameter \B_SIGNED 0
148716     parameter \B_WIDTH 1
148717     parameter \Y_WIDTH 1
148718     connect \A \int_level_l [15]
148719     connect \B \$195
148720     connect \Y $and$libresoc.v:53275$2377_Y
148721   end
148722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148723   cell $and $and$libresoc.v:53278$2380
148724     parameter \A_SIGNED 0
148725     parameter \A_WIDTH 1
148726     parameter \B_SIGNED 0
148727     parameter \B_WIDTH 1
148728     parameter \Y_WIDTH 1
148729     connect \A \int_level_l [15]
148730     connect \B \$199
148731     connect \Y $and$libresoc.v:53278$2380_Y
148732   end
148733   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
148734   cell $and $and$libresoc.v:53302$2404
148735     parameter \A_SIGNED 0
148736     parameter \A_WIDTH 1
148737     parameter \B_SIGNED 0
148738     parameter \B_WIDTH 1
148739     parameter \Y_WIDTH 1
148740     connect \A \ics_wb__cyc
148741     connect \B \ics_wb__stb
148742     connect \Y $and$libresoc.v:53302$2404_Y
148743   end
148744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
148745   cell $and $and$libresoc.v:53310$2412
148746     parameter \A_SIGNED 0
148747     parameter \A_WIDTH 1
148748     parameter \B_SIGNED 0
148749     parameter \B_WIDTH 1
148750     parameter \Y_WIDTH 1
148751     connect \A \wb_valid
148752     connect \B \ics_wb__we
148753     connect \Y $and$libresoc.v:53310$2412_Y
148754   end
148755   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148756   cell $and $and$libresoc.v:53312$2414
148757     parameter \A_SIGNED 0
148758     parameter \A_WIDTH 1
148759     parameter \B_SIGNED 0
148760     parameter \B_WIDTH 1
148761     parameter \Y_WIDTH 1
148762     connect \A \int_level_l [0]
148763     connect \B \$75
148764     connect \Y $and$libresoc.v:53312$2414_Y
148765   end
148766   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148767   cell $and $and$libresoc.v:53314$2416
148768     parameter \A_SIGNED 0
148769     parameter \A_WIDTH 1
148770     parameter \B_SIGNED 0
148771     parameter \B_WIDTH 1
148772     parameter \Y_WIDTH 1
148773     connect \A \int_level_l [0]
148774     connect \B \$79
148775     connect \Y $and$libresoc.v:53314$2416_Y
148776   end
148777   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148778   cell $and $and$libresoc.v:53316$2418
148779     parameter \A_SIGNED 0
148780     parameter \A_WIDTH 1
148781     parameter \B_SIGNED 0
148782     parameter \B_WIDTH 1
148783     parameter \Y_WIDTH 1
148784     connect \A \int_level_l [1]
148785     connect \B \$83
148786     connect \Y $and$libresoc.v:53316$2418_Y
148787   end
148788   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148789   cell $and $and$libresoc.v:53319$2421
148790     parameter \A_SIGNED 0
148791     parameter \A_WIDTH 1
148792     parameter \B_SIGNED 0
148793     parameter \B_WIDTH 1
148794     parameter \Y_WIDTH 1
148795     connect \A \int_level_l [1]
148796     connect \B \$87
148797     connect \Y $and$libresoc.v:53319$2421_Y
148798   end
148799   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148800   cell $and $and$libresoc.v:53321$2423
148801     parameter \A_SIGNED 0
148802     parameter \A_WIDTH 1
148803     parameter \B_SIGNED 0
148804     parameter \B_WIDTH 1
148805     parameter \Y_WIDTH 1
148806     connect \A \int_level_l [2]
148807     connect \B \$91
148808     connect \Y $and$libresoc.v:53321$2423_Y
148809   end
148810   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
148811   cell $and $and$libresoc.v:53323$2425
148812     parameter \A_SIGNED 0
148813     parameter \A_WIDTH 1
148814     parameter \B_SIGNED 0
148815     parameter \B_WIDTH 1
148816     parameter \Y_WIDTH 1
148817     connect \A \int_level_l [2]
148818     connect \B \$95
148819     connect \Y $and$libresoc.v:53323$2425_Y
148820   end
148821   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148822   cell $eq $eq$libresoc.v:53237$2339
148823     parameter \A_SIGNED 0
148824     parameter \A_WIDTH 8
148825     parameter \B_SIGNED 0
148826     parameter \B_WIDTH 8
148827     parameter \Y_WIDTH 1
148828     connect \A \xive1_pri
148829     connect \B 8'11111111
148830     connect \Y $eq$libresoc.v:53237$2339_Y
148831   end
148832   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148833   cell $eq $eq$libresoc.v:53259$2361
148834     parameter \A_SIGNED 0
148835     parameter \A_WIDTH 8
148836     parameter \B_SIGNED 0
148837     parameter \B_WIDTH 8
148838     parameter \Y_WIDTH 1
148839     connect \A \xive2_pri
148840     connect \B 8'11111111
148841     connect \Y $eq$libresoc.v:53259$2361_Y
148842   end
148843   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
148844   cell $eq $eq$libresoc.v:53276$2378
148845     parameter \A_SIGNED 0
148846     parameter \A_WIDTH 10
148847     parameter \B_SIGNED 0
148848     parameter \B_WIDTH 1
148849     parameter \Y_WIDTH 1
148850     connect \A \ics_wb__adr [9:0]
148851     connect \B 1'0
148852     connect \Y $eq$libresoc.v:53276$2378_Y
148853   end
148854   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148855   cell $eq $eq$libresoc.v:53279$2381
148856     parameter \A_SIGNED 0
148857     parameter \A_WIDTH 8
148858     parameter \B_SIGNED 0
148859     parameter \B_WIDTH 8
148860     parameter \Y_WIDTH 1
148861     connect \A \cur_pri15
148862     connect \B 8'11111111
148863     connect \Y $eq$libresoc.v:53279$2381_Y
148864   end
148865   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148866   cell $eq $eq$libresoc.v:53281$2383
148867     parameter \A_SIGNED 0
148868     parameter \A_WIDTH 8
148869     parameter \B_SIGNED 0
148870     parameter \B_WIDTH 8
148871     parameter \Y_WIDTH 1
148872     connect \A \xive3_pri
148873     connect \B 8'11111111
148874     connect \Y $eq$libresoc.v:53281$2383_Y
148875   end
148876   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148877   cell $eq $eq$libresoc.v:53283$2385
148878     parameter \A_SIGNED 0
148879     parameter \A_WIDTH 8
148880     parameter \B_SIGNED 0
148881     parameter \B_WIDTH 8
148882     parameter \Y_WIDTH 1
148883     connect \A \xive4_pri
148884     connect \B 8'11111111
148885     connect \Y $eq$libresoc.v:53283$2385_Y
148886   end
148887   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148888   cell $eq $eq$libresoc.v:53285$2387
148889     parameter \A_SIGNED 0
148890     parameter \A_WIDTH 8
148891     parameter \B_SIGNED 0
148892     parameter \B_WIDTH 8
148893     parameter \Y_WIDTH 1
148894     connect \A \xive5_pri
148895     connect \B 8'11111111
148896     connect \Y $eq$libresoc.v:53285$2387_Y
148897   end
148898   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148899   cell $eq $eq$libresoc.v:53287$2389
148900     parameter \A_SIGNED 0
148901     parameter \A_WIDTH 8
148902     parameter \B_SIGNED 0
148903     parameter \B_WIDTH 8
148904     parameter \Y_WIDTH 1
148905     connect \A \xive6_pri
148906     connect \B 8'11111111
148907     connect \Y $eq$libresoc.v:53287$2389_Y
148908   end
148909   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148910   cell $eq $eq$libresoc.v:53289$2391
148911     parameter \A_SIGNED 0
148912     parameter \A_WIDTH 8
148913     parameter \B_SIGNED 0
148914     parameter \B_WIDTH 8
148915     parameter \Y_WIDTH 1
148916     connect \A \xive7_pri
148917     connect \B 8'11111111
148918     connect \Y $eq$libresoc.v:53289$2391_Y
148919   end
148920   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
148921   cell $eq $eq$libresoc.v:53291$2393
148922     parameter \A_SIGNED 0
148923     parameter \A_WIDTH 10
148924     parameter \B_SIGNED 0
148925     parameter \B_WIDTH 3
148926     parameter \Y_WIDTH 1
148927     connect \A \ics_wb__adr [9:0]
148928     connect \B 3'100
148929     connect \Y $eq$libresoc.v:53291$2393_Y
148930   end
148931   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148932   cell $eq $eq$libresoc.v:53292$2394
148933     parameter \A_SIGNED 0
148934     parameter \A_WIDTH 8
148935     parameter \B_SIGNED 0
148936     parameter \B_WIDTH 8
148937     parameter \Y_WIDTH 1
148938     connect \A \xive8_pri
148939     connect \B 8'11111111
148940     connect \Y $eq$libresoc.v:53292$2394_Y
148941   end
148942   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148943   cell $eq $eq$libresoc.v:53294$2396
148944     parameter \A_SIGNED 0
148945     parameter \A_WIDTH 8
148946     parameter \B_SIGNED 0
148947     parameter \B_WIDTH 8
148948     parameter \Y_WIDTH 1
148949     connect \A \xive9_pri
148950     connect \B 8'11111111
148951     connect \Y $eq$libresoc.v:53294$2396_Y
148952   end
148953   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148954   cell $eq $eq$libresoc.v:53296$2398
148955     parameter \A_SIGNED 0
148956     parameter \A_WIDTH 8
148957     parameter \B_SIGNED 0
148958     parameter \B_WIDTH 8
148959     parameter \Y_WIDTH 1
148960     connect \A \xive10_pri
148961     connect \B 8'11111111
148962     connect \Y $eq$libresoc.v:53296$2398_Y
148963   end
148964   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148965   cell $eq $eq$libresoc.v:53298$2400
148966     parameter \A_SIGNED 0
148967     parameter \A_WIDTH 8
148968     parameter \B_SIGNED 0
148969     parameter \B_WIDTH 8
148970     parameter \Y_WIDTH 1
148971     connect \A \xive11_pri
148972     connect \B 8'11111111
148973     connect \Y $eq$libresoc.v:53298$2400_Y
148974   end
148975   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148976   cell $eq $eq$libresoc.v:53300$2402
148977     parameter \A_SIGNED 0
148978     parameter \A_WIDTH 8
148979     parameter \B_SIGNED 0
148980     parameter \B_WIDTH 8
148981     parameter \Y_WIDTH 1
148982     connect \A \xive12_pri
148983     connect \B 8'11111111
148984     connect \Y $eq$libresoc.v:53300$2402_Y
148985   end
148986   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148987   cell $eq $eq$libresoc.v:53303$2405
148988     parameter \A_SIGNED 0
148989     parameter \A_WIDTH 8
148990     parameter \B_SIGNED 0
148991     parameter \B_WIDTH 8
148992     parameter \Y_WIDTH 1
148993     connect \A \xive13_pri
148994     connect \B 8'11111111
148995     connect \Y $eq$libresoc.v:53303$2405_Y
148996   end
148997   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
148998   cell $eq $eq$libresoc.v:53305$2407
148999     parameter \A_SIGNED 0
149000     parameter \A_WIDTH 8
149001     parameter \B_SIGNED 0
149002     parameter \B_WIDTH 8
149003     parameter \Y_WIDTH 1
149004     connect \A \xive14_pri
149005     connect \B 8'11111111
149006     connect \Y $eq$libresoc.v:53305$2407_Y
149007   end
149008   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149009   cell $eq $eq$libresoc.v:53307$2409
149010     parameter \A_SIGNED 0
149011     parameter \A_WIDTH 8
149012     parameter \B_SIGNED 0
149013     parameter \B_WIDTH 8
149014     parameter \Y_WIDTH 1
149015     connect \A \xive15_pri
149016     connect \B 8'11111111
149017     connect \Y $eq$libresoc.v:53307$2409_Y
149018   end
149019   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149020   cell $eq $eq$libresoc.v:53318$2420
149021     parameter \A_SIGNED 0
149022     parameter \A_WIDTH 8
149023     parameter \B_SIGNED 0
149024     parameter \B_WIDTH 8
149025     parameter \Y_WIDTH 1
149026     connect \A \xive0_pri
149027     connect \B 8'11111111
149028     connect \Y $eq$libresoc.v:53318$2420_Y
149029   end
149030   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149031   cell $lt $lt$libresoc.v:53222$2324
149032     parameter \A_SIGNED 0
149033     parameter \A_WIDTH 8
149034     parameter \B_SIGNED 0
149035     parameter \B_WIDTH 8
149036     parameter \Y_WIDTH 1
149037     connect \A \xive3_pri
149038     connect \B \cur_pri2
149039     connect \Y $lt$libresoc.v:53222$2324_Y
149040   end
149041   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149042   cell $lt $lt$libresoc.v:53224$2326
149043     parameter \A_SIGNED 0
149044     parameter \A_WIDTH 8
149045     parameter \B_SIGNED 0
149046     parameter \B_WIDTH 8
149047     parameter \Y_WIDTH 1
149048     connect \A \xive3_pri
149049     connect \B \cur_pri2
149050     connect \Y $lt$libresoc.v:53224$2326_Y
149051   end
149052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149053   cell $lt $lt$libresoc.v:53226$2328
149054     parameter \A_SIGNED 0
149055     parameter \A_WIDTH 8
149056     parameter \B_SIGNED 0
149057     parameter \B_WIDTH 8
149058     parameter \Y_WIDTH 1
149059     connect \A \xive4_pri
149060     connect \B \cur_pri3
149061     connect \Y $lt$libresoc.v:53226$2328_Y
149062   end
149063   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149064   cell $lt $lt$libresoc.v:53228$2330
149065     parameter \A_SIGNED 0
149066     parameter \A_WIDTH 8
149067     parameter \B_SIGNED 0
149068     parameter \B_WIDTH 8
149069     parameter \Y_WIDTH 1
149070     connect \A \xive4_pri
149071     connect \B \cur_pri3
149072     connect \Y $lt$libresoc.v:53228$2330_Y
149073   end
149074   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149075   cell $lt $lt$libresoc.v:53230$2332
149076     parameter \A_SIGNED 0
149077     parameter \A_WIDTH 8
149078     parameter \B_SIGNED 0
149079     parameter \B_WIDTH 8
149080     parameter \Y_WIDTH 1
149081     connect \A \xive5_pri
149082     connect \B \cur_pri4
149083     connect \Y $lt$libresoc.v:53230$2332_Y
149084   end
149085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149086   cell $lt $lt$libresoc.v:53232$2334
149087     parameter \A_SIGNED 0
149088     parameter \A_WIDTH 8
149089     parameter \B_SIGNED 0
149090     parameter \B_WIDTH 8
149091     parameter \Y_WIDTH 1
149092     connect \A \xive5_pri
149093     connect \B \cur_pri4
149094     connect \Y $lt$libresoc.v:53232$2334_Y
149095   end
149096   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149097   cell $lt $lt$libresoc.v:53234$2336
149098     parameter \A_SIGNED 0
149099     parameter \A_WIDTH 8
149100     parameter \B_SIGNED 0
149101     parameter \B_WIDTH 8
149102     parameter \Y_WIDTH 1
149103     connect \A \xive6_pri
149104     connect \B \cur_pri5
149105     connect \Y $lt$libresoc.v:53234$2336_Y
149106   end
149107   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149108   cell $lt $lt$libresoc.v:53236$2338
149109     parameter \A_SIGNED 0
149110     parameter \A_WIDTH 8
149111     parameter \B_SIGNED 0
149112     parameter \B_WIDTH 8
149113     parameter \Y_WIDTH 1
149114     connect \A \xive6_pri
149115     connect \B \cur_pri5
149116     connect \Y $lt$libresoc.v:53236$2338_Y
149117   end
149118   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149119   cell $lt $lt$libresoc.v:53239$2341
149120     parameter \A_SIGNED 0
149121     parameter \A_WIDTH 8
149122     parameter \B_SIGNED 0
149123     parameter \B_WIDTH 8
149124     parameter \Y_WIDTH 1
149125     connect \A \xive7_pri
149126     connect \B \cur_pri6
149127     connect \Y $lt$libresoc.v:53239$2341_Y
149128   end
149129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149130   cell $lt $lt$libresoc.v:53241$2343
149131     parameter \A_SIGNED 0
149132     parameter \A_WIDTH 8
149133     parameter \B_SIGNED 0
149134     parameter \B_WIDTH 8
149135     parameter \Y_WIDTH 1
149136     connect \A \xive7_pri
149137     connect \B \cur_pri6
149138     connect \Y $lt$libresoc.v:53241$2343_Y
149139   end
149140   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149141   cell $lt $lt$libresoc.v:53244$2346
149142     parameter \A_SIGNED 0
149143     parameter \A_WIDTH 8
149144     parameter \B_SIGNED 0
149145     parameter \B_WIDTH 8
149146     parameter \Y_WIDTH 1
149147     connect \A \xive8_pri
149148     connect \B \cur_pri7
149149     connect \Y $lt$libresoc.v:53244$2346_Y
149150   end
149151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149152   cell $lt $lt$libresoc.v:53246$2348
149153     parameter \A_SIGNED 0
149154     parameter \A_WIDTH 8
149155     parameter \B_SIGNED 0
149156     parameter \B_WIDTH 8
149157     parameter \Y_WIDTH 1
149158     connect \A \xive8_pri
149159     connect \B \cur_pri7
149160     connect \Y $lt$libresoc.v:53246$2348_Y
149161   end
149162   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149163   cell $lt $lt$libresoc.v:53248$2350
149164     parameter \A_SIGNED 0
149165     parameter \A_WIDTH 8
149166     parameter \B_SIGNED 0
149167     parameter \B_WIDTH 8
149168     parameter \Y_WIDTH 1
149169     connect \A \xive9_pri
149170     connect \B \cur_pri8
149171     connect \Y $lt$libresoc.v:53248$2350_Y
149172   end
149173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149174   cell $lt $lt$libresoc.v:53250$2352
149175     parameter \A_SIGNED 0
149176     parameter \A_WIDTH 8
149177     parameter \B_SIGNED 0
149178     parameter \B_WIDTH 8
149179     parameter \Y_WIDTH 1
149180     connect \A \xive9_pri
149181     connect \B \cur_pri8
149182     connect \Y $lt$libresoc.v:53250$2352_Y
149183   end
149184   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149185   cell $lt $lt$libresoc.v:53252$2354
149186     parameter \A_SIGNED 0
149187     parameter \A_WIDTH 8
149188     parameter \B_SIGNED 0
149189     parameter \B_WIDTH 8
149190     parameter \Y_WIDTH 1
149191     connect \A \xive10_pri
149192     connect \B \cur_pri9
149193     connect \Y $lt$libresoc.v:53252$2354_Y
149194   end
149195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149196   cell $lt $lt$libresoc.v:53254$2356
149197     parameter \A_SIGNED 0
149198     parameter \A_WIDTH 8
149199     parameter \B_SIGNED 0
149200     parameter \B_WIDTH 8
149201     parameter \Y_WIDTH 1
149202     connect \A \xive10_pri
149203     connect \B \cur_pri9
149204     connect \Y $lt$libresoc.v:53254$2356_Y
149205   end
149206   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149207   cell $lt $lt$libresoc.v:53256$2358
149208     parameter \A_SIGNED 0
149209     parameter \A_WIDTH 8
149210     parameter \B_SIGNED 0
149211     parameter \B_WIDTH 8
149212     parameter \Y_WIDTH 1
149213     connect \A \xive11_pri
149214     connect \B \cur_pri10
149215     connect \Y $lt$libresoc.v:53256$2358_Y
149216   end
149217   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149218   cell $lt $lt$libresoc.v:53258$2360
149219     parameter \A_SIGNED 0
149220     parameter \A_WIDTH 8
149221     parameter \B_SIGNED 0
149222     parameter \B_WIDTH 8
149223     parameter \Y_WIDTH 1
149224     connect \A \xive11_pri
149225     connect \B \cur_pri10
149226     connect \Y $lt$libresoc.v:53258$2360_Y
149227   end
149228   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149229   cell $lt $lt$libresoc.v:53261$2363
149230     parameter \A_SIGNED 0
149231     parameter \A_WIDTH 8
149232     parameter \B_SIGNED 0
149233     parameter \B_WIDTH 8
149234     parameter \Y_WIDTH 1
149235     connect \A \xive12_pri
149236     connect \B \cur_pri11
149237     connect \Y $lt$libresoc.v:53261$2363_Y
149238   end
149239   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149240   cell $lt $lt$libresoc.v:53263$2365
149241     parameter \A_SIGNED 0
149242     parameter \A_WIDTH 8
149243     parameter \B_SIGNED 0
149244     parameter \B_WIDTH 8
149245     parameter \Y_WIDTH 1
149246     connect \A \xive12_pri
149247     connect \B \cur_pri11
149248     connect \Y $lt$libresoc.v:53263$2365_Y
149249   end
149250   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149251   cell $lt $lt$libresoc.v:53266$2368
149252     parameter \A_SIGNED 0
149253     parameter \A_WIDTH 8
149254     parameter \B_SIGNED 0
149255     parameter \B_WIDTH 8
149256     parameter \Y_WIDTH 1
149257     connect \A \xive13_pri
149258     connect \B \cur_pri12
149259     connect \Y $lt$libresoc.v:53266$2368_Y
149260   end
149261   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149262   cell $lt $lt$libresoc.v:53268$2370
149263     parameter \A_SIGNED 0
149264     parameter \A_WIDTH 8
149265     parameter \B_SIGNED 0
149266     parameter \B_WIDTH 8
149267     parameter \Y_WIDTH 1
149268     connect \A \xive13_pri
149269     connect \B \cur_pri12
149270     connect \Y $lt$libresoc.v:53268$2370_Y
149271   end
149272   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149273   cell $lt $lt$libresoc.v:53270$2372
149274     parameter \A_SIGNED 0
149275     parameter \A_WIDTH 8
149276     parameter \B_SIGNED 0
149277     parameter \B_WIDTH 8
149278     parameter \Y_WIDTH 1
149279     connect \A \xive14_pri
149280     connect \B \cur_pri13
149281     connect \Y $lt$libresoc.v:53270$2372_Y
149282   end
149283   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149284   cell $lt $lt$libresoc.v:53272$2374
149285     parameter \A_SIGNED 0
149286     parameter \A_WIDTH 8
149287     parameter \B_SIGNED 0
149288     parameter \B_WIDTH 8
149289     parameter \Y_WIDTH 1
149290     connect \A \xive14_pri
149291     connect \B \cur_pri13
149292     connect \Y $lt$libresoc.v:53272$2374_Y
149293   end
149294   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149295   cell $lt $lt$libresoc.v:53274$2376
149296     parameter \A_SIGNED 0
149297     parameter \A_WIDTH 8
149298     parameter \B_SIGNED 0
149299     parameter \B_WIDTH 8
149300     parameter \Y_WIDTH 1
149301     connect \A \xive15_pri
149302     connect \B \cur_pri14
149303     connect \Y $lt$libresoc.v:53274$2376_Y
149304   end
149305   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149306   cell $lt $lt$libresoc.v:53277$2379
149307     parameter \A_SIGNED 0
149308     parameter \A_WIDTH 8
149309     parameter \B_SIGNED 0
149310     parameter \B_WIDTH 8
149311     parameter \Y_WIDTH 1
149312     connect \A \xive15_pri
149313     connect \B \cur_pri14
149314     connect \Y $lt$libresoc.v:53277$2379_Y
149315   end
149316   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149317   cell $lt $lt$libresoc.v:53311$2413
149318     parameter \A_SIGNED 0
149319     parameter \A_WIDTH 8
149320     parameter \B_SIGNED 0
149321     parameter \B_WIDTH 8
149322     parameter \Y_WIDTH 1
149323     connect \A \xive0_pri
149324     connect \B \max_pri
149325     connect \Y $lt$libresoc.v:53311$2413_Y
149326   end
149327   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149328   cell $lt $lt$libresoc.v:53313$2415
149329     parameter \A_SIGNED 0
149330     parameter \A_WIDTH 8
149331     parameter \B_SIGNED 0
149332     parameter \B_WIDTH 8
149333     parameter \Y_WIDTH 1
149334     connect \A \xive0_pri
149335     connect \B \max_pri
149336     connect \Y $lt$libresoc.v:53313$2415_Y
149337   end
149338   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149339   cell $lt $lt$libresoc.v:53315$2417
149340     parameter \A_SIGNED 0
149341     parameter \A_WIDTH 8
149342     parameter \B_SIGNED 0
149343     parameter \B_WIDTH 8
149344     parameter \Y_WIDTH 1
149345     connect \A \xive1_pri
149346     connect \B \cur_pri0
149347     connect \Y $lt$libresoc.v:53315$2417_Y
149348   end
149349   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149350   cell $lt $lt$libresoc.v:53317$2419
149351     parameter \A_SIGNED 0
149352     parameter \A_WIDTH 8
149353     parameter \B_SIGNED 0
149354     parameter \B_WIDTH 8
149355     parameter \Y_WIDTH 1
149356     connect \A \xive1_pri
149357     connect \B \cur_pri0
149358     connect \Y $lt$libresoc.v:53317$2419_Y
149359   end
149360   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149361   cell $lt $lt$libresoc.v:53320$2422
149362     parameter \A_SIGNED 0
149363     parameter \A_WIDTH 8
149364     parameter \B_SIGNED 0
149365     parameter \B_WIDTH 8
149366     parameter \Y_WIDTH 1
149367     connect \A \xive2_pri
149368     connect \B \cur_pri1
149369     connect \Y $lt$libresoc.v:53320$2422_Y
149370   end
149371   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
149372   cell $lt $lt$libresoc.v:53322$2424
149373     parameter \A_SIGNED 0
149374     parameter \A_WIDTH 8
149375     parameter \B_SIGNED 0
149376     parameter \B_WIDTH 8
149377     parameter \Y_WIDTH 1
149378     connect \A \xive2_pri
149379     connect \B \cur_pri1
149380     connect \Y $lt$libresoc.v:53322$2424_Y
149381   end
149382   attribute \src "libresoc.v:53309.18-53309.40"
149383   cell $shr $shr$libresoc.v:53309$2411
149384     parameter \A_SIGNED 0
149385     parameter \A_WIDTH 16
149386     parameter \B_SIGNED 0
149387     parameter \B_WIDTH 4
149388     parameter \Y_WIDTH 16
149389     connect \A \int_level_l
149390     connect \B \reg_idx
149391     connect \Y $shr$libresoc.v:53309$2411_Y
149392   end
149393   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149394   cell $mux $ternary$libresoc.v:53221$2323
149395     parameter \WIDTH 8
149396     connect \A \xive0_pri
149397     connect \B 8'11111111
149398     connect \S \$8
149399     connect \Y $ternary$libresoc.v:53221$2323_Y
149400   end
149401   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149402   cell $mux $ternary$libresoc.v:53243$2345
149403     parameter \WIDTH 8
149404     connect \A \xive1_pri
149405     connect \B 8'11111111
149406     connect \S \$12
149407     connect \Y $ternary$libresoc.v:53243$2345_Y
149408   end
149409   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149410   cell $mux $ternary$libresoc.v:53265$2367
149411     parameter \WIDTH 8
149412     connect \A \xive2_pri
149413     connect \B 8'11111111
149414     connect \S \$16
149415     connect \Y $ternary$libresoc.v:53265$2367_Y
149416   end
149417   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149418   cell $mux $ternary$libresoc.v:53280$2382
149419     parameter \WIDTH 8
149420     connect \A \cur_pri15
149421     connect \B 8'11111111
149422     connect \S \$204
149423     connect \Y $ternary$libresoc.v:53280$2382_Y
149424   end
149425   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149426   cell $mux $ternary$libresoc.v:53282$2384
149427     parameter \WIDTH 8
149428     connect \A \xive3_pri
149429     connect \B 8'11111111
149430     connect \S \$20
149431     connect \Y $ternary$libresoc.v:53282$2384_Y
149432   end
149433   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149434   cell $mux $ternary$libresoc.v:53284$2386
149435     parameter \WIDTH 8
149436     connect \A \xive4_pri
149437     connect \B 8'11111111
149438     connect \S \$24
149439     connect \Y $ternary$libresoc.v:53284$2386_Y
149440   end
149441   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149442   cell $mux $ternary$libresoc.v:53286$2388
149443     parameter \WIDTH 8
149444     connect \A \xive5_pri
149445     connect \B 8'11111111
149446     connect \S \$28
149447     connect \Y $ternary$libresoc.v:53286$2388_Y
149448   end
149449   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149450   cell $mux $ternary$libresoc.v:53288$2390
149451     parameter \WIDTH 8
149452     connect \A \xive6_pri
149453     connect \B 8'11111111
149454     connect \S \$32
149455     connect \Y $ternary$libresoc.v:53288$2390_Y
149456   end
149457   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149458   cell $mux $ternary$libresoc.v:53290$2392
149459     parameter \WIDTH 8
149460     connect \A \xive7_pri
149461     connect \B 8'11111111
149462     connect \S \$36
149463     connect \Y $ternary$libresoc.v:53290$2392_Y
149464   end
149465   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149466   cell $mux $ternary$libresoc.v:53293$2395
149467     parameter \WIDTH 8
149468     connect \A \xive8_pri
149469     connect \B 8'11111111
149470     connect \S \$40
149471     connect \Y $ternary$libresoc.v:53293$2395_Y
149472   end
149473   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149474   cell $mux $ternary$libresoc.v:53295$2397
149475     parameter \WIDTH 8
149476     connect \A \xive9_pri
149477     connect \B 8'11111111
149478     connect \S \$44
149479     connect \Y $ternary$libresoc.v:53295$2397_Y
149480   end
149481   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149482   cell $mux $ternary$libresoc.v:53297$2399
149483     parameter \WIDTH 8
149484     connect \A \xive10_pri
149485     connect \B 8'11111111
149486     connect \S \$48
149487     connect \Y $ternary$libresoc.v:53297$2399_Y
149488   end
149489   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149490   cell $mux $ternary$libresoc.v:53299$2401
149491     parameter \WIDTH 8
149492     connect \A \xive11_pri
149493     connect \B 8'11111111
149494     connect \S \$52
149495     connect \Y $ternary$libresoc.v:53299$2401_Y
149496   end
149497   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149498   cell $mux $ternary$libresoc.v:53301$2403
149499     parameter \WIDTH 8
149500     connect \A \xive12_pri
149501     connect \B 8'11111111
149502     connect \S \$56
149503     connect \Y $ternary$libresoc.v:53301$2403_Y
149504   end
149505   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149506   cell $mux $ternary$libresoc.v:53304$2406
149507     parameter \WIDTH 8
149508     connect \A \xive13_pri
149509     connect \B 8'11111111
149510     connect \S \$60
149511     connect \Y $ternary$libresoc.v:53304$2406_Y
149512   end
149513   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149514   cell $mux $ternary$libresoc.v:53306$2408
149515     parameter \WIDTH 8
149516     connect \A \xive14_pri
149517     connect \B 8'11111111
149518     connect \S \$64
149519     connect \Y $ternary$libresoc.v:53306$2408_Y
149520   end
149521   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
149522   cell $mux $ternary$libresoc.v:53308$2410
149523     parameter \WIDTH 8
149524     connect \A \xive15_pri
149525     connect \B 8'11111111
149526     connect \S \$68
149527     connect \Y $ternary$libresoc.v:53308$2410_Y
149528   end
149529   attribute \src "libresoc.v:52822.7-52822.20"
149530   process $proc$libresoc.v:52822$2571
149531     assign { } { }
149532     assign $0\initial[0:0] 1'0
149533     sync always
149534       update \initial $0\initial[0:0]
149535     sync init
149536   end
149537   attribute \src "libresoc.v:53103.13-53103.30"
149538   process $proc$libresoc.v:53103$2572
149539     assign { } { }
149540     assign $1\icp_o_pri[7:0] 8'00000000
149541     sync always
149542     sync init
149543       update \icp_o_pri $1\icp_o_pri[7:0]
149544   end
149545   attribute \src "libresoc.v:53108.13-53108.29"
149546   process $proc$libresoc.v:53108$2573
149547     assign { } { }
149548     assign $1\icp_o_src[3:0] 4'0000
149549     sync always
149550     sync init
149551       update \icp_o_src $1\icp_o_src[3:0]
149552   end
149553   attribute \src "libresoc.v:53117.7-53117.25"
149554   process $proc$libresoc.v:53117$2574
149555     assign { } { }
149556     assign $1\ics_wb__ack[0:0] 1'0
149557     sync always
149558     sync init
149559       update \ics_wb__ack $1\ics_wb__ack[0:0]
149560   end
149561   attribute \src "libresoc.v:53126.14-53126.35"
149562   process $proc$libresoc.v:53126$2575
149563     assign { } { }
149564     assign $1\ics_wb__dat_r[31:0] 0
149565     sync always
149566     sync init
149567       update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
149568   end
149569   attribute \src "libresoc.v:53138.14-53138.36"
149570   process $proc$libresoc.v:53138$2576
149571     assign { } { }
149572     assign $1\int_level_l[15:0] 16'0000000000000000
149573     sync always
149574     sync init
149575       update \int_level_l $1\int_level_l[15:0]
149576   end
149577   attribute \src "libresoc.v:53158.13-53158.30"
149578   process $proc$libresoc.v:53158$2577
149579     assign { } { }
149580     assign $1\xive0_pri[7:0] 8'11111111
149581     sync always
149582     sync init
149583       update \xive0_pri $1\xive0_pri[7:0]
149584   end
149585   attribute \src "libresoc.v:53162.13-53162.31"
149586   process $proc$libresoc.v:53162$2578
149587     assign { } { }
149588     assign $1\xive10_pri[7:0] 8'11111111
149589     sync always
149590     sync init
149591       update \xive10_pri $1\xive10_pri[7:0]
149592   end
149593   attribute \src "libresoc.v:53166.13-53166.31"
149594   process $proc$libresoc.v:53166$2579
149595     assign { } { }
149596     assign $1\xive11_pri[7:0] 8'11111111
149597     sync always
149598     sync init
149599       update \xive11_pri $1\xive11_pri[7:0]
149600   end
149601   attribute \src "libresoc.v:53170.13-53170.31"
149602   process $proc$libresoc.v:53170$2580
149603     assign { } { }
149604     assign $1\xive12_pri[7:0] 8'11111111
149605     sync always
149606     sync init
149607       update \xive12_pri $1\xive12_pri[7:0]
149608   end
149609   attribute \src "libresoc.v:53174.13-53174.31"
149610   process $proc$libresoc.v:53174$2581
149611     assign { } { }
149612     assign $1\xive13_pri[7:0] 8'11111111
149613     sync always
149614     sync init
149615       update \xive13_pri $1\xive13_pri[7:0]
149616   end
149617   attribute \src "libresoc.v:53178.13-53178.31"
149618   process $proc$libresoc.v:53178$2582
149619     assign { } { }
149620     assign $1\xive14_pri[7:0] 8'11111111
149621     sync always
149622     sync init
149623       update \xive14_pri $1\xive14_pri[7:0]
149624   end
149625   attribute \src "libresoc.v:53182.13-53182.31"
149626   process $proc$libresoc.v:53182$2583
149627     assign { } { }
149628     assign $1\xive15_pri[7:0] 8'11111111
149629     sync always
149630     sync init
149631       update \xive15_pri $1\xive15_pri[7:0]
149632   end
149633   attribute \src "libresoc.v:53186.13-53186.30"
149634   process $proc$libresoc.v:53186$2584
149635     assign { } { }
149636     assign $1\xive1_pri[7:0] 8'11111111
149637     sync always
149638     sync init
149639       update \xive1_pri $1\xive1_pri[7:0]
149640   end
149641   attribute \src "libresoc.v:53190.13-53190.30"
149642   process $proc$libresoc.v:53190$2585
149643     assign { } { }
149644     assign $1\xive2_pri[7:0] 8'11111111
149645     sync always
149646     sync init
149647       update \xive2_pri $1\xive2_pri[7:0]
149648   end
149649   attribute \src "libresoc.v:53194.13-53194.30"
149650   process $proc$libresoc.v:53194$2586
149651     assign { } { }
149652     assign $1\xive3_pri[7:0] 8'11111111
149653     sync always
149654     sync init
149655       update \xive3_pri $1\xive3_pri[7:0]
149656   end
149657   attribute \src "libresoc.v:53198.13-53198.30"
149658   process $proc$libresoc.v:53198$2587
149659     assign { } { }
149660     assign $1\xive4_pri[7:0] 8'11111111
149661     sync always
149662     sync init
149663       update \xive4_pri $1\xive4_pri[7:0]
149664   end
149665   attribute \src "libresoc.v:53202.13-53202.30"
149666   process $proc$libresoc.v:53202$2588
149667     assign { } { }
149668     assign $1\xive5_pri[7:0] 8'11111111
149669     sync always
149670     sync init
149671       update \xive5_pri $1\xive5_pri[7:0]
149672   end
149673   attribute \src "libresoc.v:53206.13-53206.30"
149674   process $proc$libresoc.v:53206$2589
149675     assign { } { }
149676     assign $1\xive6_pri[7:0] 8'11111111
149677     sync always
149678     sync init
149679       update \xive6_pri $1\xive6_pri[7:0]
149680   end
149681   attribute \src "libresoc.v:53210.13-53210.30"
149682   process $proc$libresoc.v:53210$2590
149683     assign { } { }
149684     assign $1\xive7_pri[7:0] 8'11111111
149685     sync always
149686     sync init
149687       update \xive7_pri $1\xive7_pri[7:0]
149688   end
149689   attribute \src "libresoc.v:53214.13-53214.30"
149690   process $proc$libresoc.v:53214$2591
149691     assign { } { }
149692     assign $1\xive8_pri[7:0] 8'11111111
149693     sync always
149694     sync init
149695       update \xive8_pri $1\xive8_pri[7:0]
149696   end
149697   attribute \src "libresoc.v:53218.13-53218.30"
149698   process $proc$libresoc.v:53218$2592
149699     assign { } { }
149700     assign $1\xive9_pri[7:0] 8'11111111
149701     sync always
149702     sync init
149703       update \xive9_pri $1\xive9_pri[7:0]
149704   end
149705   attribute \src "libresoc.v:53324.3-53325.37"
149706   process $proc$libresoc.v:53324$2426
149707     assign { } { }
149708     assign $0\xive11_pri[7:0] \xive11_pri$next
149709     sync posedge \clk
149710       update \xive11_pri $0\xive11_pri[7:0]
149711   end
149712   attribute \src "libresoc.v:53326.3-53327.37"
149713   process $proc$libresoc.v:53326$2427
149714     assign { } { }
149715     assign $0\xive12_pri[7:0] \xive12_pri$next
149716     sync posedge \clk
149717       update \xive12_pri $0\xive12_pri[7:0]
149718   end
149719   attribute \src "libresoc.v:53328.3-53329.37"
149720   process $proc$libresoc.v:53328$2428
149721     assign { } { }
149722     assign $0\xive13_pri[7:0] \xive13_pri$next
149723     sync posedge \clk
149724       update \xive13_pri $0\xive13_pri[7:0]
149725   end
149726   attribute \src "libresoc.v:53330.3-53331.37"
149727   process $proc$libresoc.v:53330$2429
149728     assign { } { }
149729     assign $0\xive14_pri[7:0] \xive14_pri$next
149730     sync posedge \clk
149731       update \xive14_pri $0\xive14_pri[7:0]
149732   end
149733   attribute \src "libresoc.v:53332.3-53333.37"
149734   process $proc$libresoc.v:53332$2430
149735     assign { } { }
149736     assign $0\xive15_pri[7:0] \xive15_pri$next
149737     sync posedge \clk
149738       update \xive15_pri $0\xive15_pri[7:0]
149739   end
149740   attribute \src "libresoc.v:53334.3-53335.39"
149741   process $proc$libresoc.v:53334$2431
149742     assign { } { }
149743     assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
149744     sync posedge \clk
149745       update \ics_wb__ack $0\ics_wb__ack[0:0]
149746   end
149747   attribute \src "libresoc.v:53336.3-53337.43"
149748   process $proc$libresoc.v:53336$2432
149749     assign { } { }
149750     assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
149751     sync posedge \clk
149752       update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
149753   end
149754   attribute \src "libresoc.v:53338.3-53339.39"
149755   process $proc$libresoc.v:53338$2433
149756     assign { } { }
149757     assign $0\int_level_l[15:0] \int_level_l$next
149758     sync posedge \clk
149759       update \int_level_l $0\int_level_l[15:0]
149760   end
149761   attribute \src "libresoc.v:53340.3-53341.28"
149762   process $proc$libresoc.v:53340$2434
149763     assign { } { }
149764     assign $0\icp_o_src[3:0] \cur_idx15
149765     sync posedge \clk
149766       update \icp_o_src $0\icp_o_src[3:0]
149767   end
149768   attribute \src "libresoc.v:53342.3-53343.25"
149769   process $proc$libresoc.v:53342$2435
149770     assign { } { }
149771     assign $0\icp_o_pri[7:0] \$203
149772     sync posedge \clk
149773       update \icp_o_pri $0\icp_o_pri[7:0]
149774   end
149775   attribute \src "libresoc.v:53344.3-53345.35"
149776   process $proc$libresoc.v:53344$2436
149777     assign { } { }
149778     assign $0\xive0_pri[7:0] \xive0_pri$next
149779     sync posedge \clk
149780       update \xive0_pri $0\xive0_pri[7:0]
149781   end
149782   attribute \src "libresoc.v:53346.3-53347.35"
149783   process $proc$libresoc.v:53346$2437
149784     assign { } { }
149785     assign $0\xive1_pri[7:0] \xive1_pri$next
149786     sync posedge \clk
149787       update \xive1_pri $0\xive1_pri[7:0]
149788   end
149789   attribute \src "libresoc.v:53348.3-53349.35"
149790   process $proc$libresoc.v:53348$2438
149791     assign { } { }
149792     assign $0\xive2_pri[7:0] \xive2_pri$next
149793     sync posedge \clk
149794       update \xive2_pri $0\xive2_pri[7:0]
149795   end
149796   attribute \src "libresoc.v:53350.3-53351.35"
149797   process $proc$libresoc.v:53350$2439
149798     assign { } { }
149799     assign $0\xive3_pri[7:0] \xive3_pri$next
149800     sync posedge \clk
149801       update \xive3_pri $0\xive3_pri[7:0]
149802   end
149803   attribute \src "libresoc.v:53352.3-53353.35"
149804   process $proc$libresoc.v:53352$2440
149805     assign { } { }
149806     assign $0\xive4_pri[7:0] \xive4_pri$next
149807     sync posedge \clk
149808       update \xive4_pri $0\xive4_pri[7:0]
149809   end
149810   attribute \src "libresoc.v:53354.3-53355.35"
149811   process $proc$libresoc.v:53354$2441
149812     assign { } { }
149813     assign $0\xive5_pri[7:0] \xive5_pri$next
149814     sync posedge \clk
149815       update \xive5_pri $0\xive5_pri[7:0]
149816   end
149817   attribute \src "libresoc.v:53356.3-53357.35"
149818   process $proc$libresoc.v:53356$2442
149819     assign { } { }
149820     assign $0\xive6_pri[7:0] \xive6_pri$next
149821     sync posedge \clk
149822       update \xive6_pri $0\xive6_pri[7:0]
149823   end
149824   attribute \src "libresoc.v:53358.3-53359.35"
149825   process $proc$libresoc.v:53358$2443
149826     assign { } { }
149827     assign $0\xive7_pri[7:0] \xive7_pri$next
149828     sync posedge \clk
149829       update \xive7_pri $0\xive7_pri[7:0]
149830   end
149831   attribute \src "libresoc.v:53360.3-53361.35"
149832   process $proc$libresoc.v:53360$2444
149833     assign { } { }
149834     assign $0\xive8_pri[7:0] \xive8_pri$next
149835     sync posedge \clk
149836       update \xive8_pri $0\xive8_pri[7:0]
149837   end
149838   attribute \src "libresoc.v:53362.3-53363.35"
149839   process $proc$libresoc.v:53362$2445
149840     assign { } { }
149841     assign $0\xive9_pri[7:0] \xive9_pri$next
149842     sync posedge \clk
149843       update \xive9_pri $0\xive9_pri[7:0]
149844   end
149845   attribute \src "libresoc.v:53364.3-53365.37"
149846   process $proc$libresoc.v:53364$2446
149847     assign { } { }
149848     assign $0\xive10_pri[7:0] \xive10_pri$next
149849     sync posedge \clk
149850       update \xive10_pri $0\xive10_pri[7:0]
149851   end
149852   attribute \src "libresoc.v:53366.3-53451.6"
149853   process $proc$libresoc.v:53366$2447
149854     assign { } { }
149855     assign { } { }
149856     assign { } { }
149857     assign { } { }
149858     assign { } { }
149859     assign { } { }
149860     assign { } { }
149861     assign { } { }
149862     assign { } { }
149863     assign { } { }
149864     assign { } { }
149865     assign { } { }
149866     assign { } { }
149867     assign { } { }
149868     assign { } { }
149869     assign { } { }
149870     assign { } { }
149871     assign { } { }
149872     assign { } { }
149873     assign { } { }
149874     assign { } { }
149875     assign { } { }
149876     assign { } { }
149877     assign { } { }
149878     assign { } { }
149879     assign { } { }
149880     assign { } { }
149881     assign { } { }
149882     assign { } { }
149883     assign { } { }
149884     assign { } { }
149885     assign { } { }
149886     assign { } { }
149887     assign { } { }
149888     assign { } { }
149889     assign { } { }
149890     assign { } { }
149891     assign { } { }
149892     assign { } { }
149893     assign { } { }
149894     assign { } { }
149895     assign { } { }
149896     assign { } { }
149897     assign { } { }
149898     assign { } { }
149899     assign { } { }
149900     assign { } { }
149901     assign { } { }
149902     assign $0\xive0_pri$next[7:0]$2448 $4\xive0_pri$next[7:0]$2512
149903     assign $0\xive10_pri$next[7:0]$2449 $4\xive10_pri$next[7:0]$2513
149904     assign $0\xive11_pri$next[7:0]$2450 $4\xive11_pri$next[7:0]$2514
149905     assign $0\xive12_pri$next[7:0]$2451 $4\xive12_pri$next[7:0]$2515
149906     assign $0\xive13_pri$next[7:0]$2452 $4\xive13_pri$next[7:0]$2516
149907     assign $0\xive14_pri$next[7:0]$2453 $4\xive14_pri$next[7:0]$2517
149908     assign $0\xive15_pri$next[7:0]$2454 $4\xive15_pri$next[7:0]$2518
149909     assign $0\xive1_pri$next[7:0]$2455 $4\xive1_pri$next[7:0]$2519
149910     assign $0\xive2_pri$next[7:0]$2456 $4\xive2_pri$next[7:0]$2520
149911     assign $0\xive3_pri$next[7:0]$2457 $4\xive3_pri$next[7:0]$2521
149912     assign $0\xive4_pri$next[7:0]$2458 $4\xive4_pri$next[7:0]$2522
149913     assign $0\xive5_pri$next[7:0]$2459 $4\xive5_pri$next[7:0]$2523
149914     assign $0\xive6_pri$next[7:0]$2460 $4\xive6_pri$next[7:0]$2524
149915     assign $0\xive7_pri$next[7:0]$2461 $4\xive7_pri$next[7:0]$2525
149916     assign $0\xive8_pri$next[7:0]$2462 $4\xive8_pri$next[7:0]$2526
149917     assign $0\xive9_pri$next[7:0]$2463 $4\xive9_pri$next[7:0]$2527
149918     attribute \src "libresoc.v:53367.5-53367.29"
149919     switch \initial
149920       attribute \src "libresoc.v:53367.9-53367.17"
149921       case 1'1
149922       case
149923     end
149924     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
149925     switch \$73
149926       attribute \src "libresoc.v:0.0-0.0"
149927       case 1'1
149928         assign { } { }
149929         assign { } { }
149930         assign { } { }
149931         assign { } { }
149932         assign { } { }
149933         assign { } { }
149934         assign { } { }
149935         assign { } { }
149936         assign { } { }
149937         assign { } { }
149938         assign { } { }
149939         assign { } { }
149940         assign { } { }
149941         assign { } { }
149942         assign { } { }
149943         assign { } { }
149944         assign $1\xive0_pri$next[7:0]$2464 $2\xive0_pri$next[7:0]$2480
149945         assign $1\xive10_pri$next[7:0]$2465 $2\xive10_pri$next[7:0]$2481
149946         assign $1\xive11_pri$next[7:0]$2466 $2\xive11_pri$next[7:0]$2482
149947         assign $1\xive12_pri$next[7:0]$2467 $2\xive12_pri$next[7:0]$2483
149948         assign $1\xive13_pri$next[7:0]$2468 $2\xive13_pri$next[7:0]$2484
149949         assign $1\xive14_pri$next[7:0]$2469 $2\xive14_pri$next[7:0]$2485
149950         assign $1\xive15_pri$next[7:0]$2470 $2\xive15_pri$next[7:0]$2486
149951         assign $1\xive1_pri$next[7:0]$2471 $2\xive1_pri$next[7:0]$2487
149952         assign $1\xive2_pri$next[7:0]$2472 $2\xive2_pri$next[7:0]$2488
149953         assign $1\xive3_pri$next[7:0]$2473 $2\xive3_pri$next[7:0]$2489
149954         assign $1\xive4_pri$next[7:0]$2474 $2\xive4_pri$next[7:0]$2490
149955         assign $1\xive5_pri$next[7:0]$2475 $2\xive5_pri$next[7:0]$2491
149956         assign $1\xive6_pri$next[7:0]$2476 $2\xive6_pri$next[7:0]$2492
149957         assign $1\xive7_pri$next[7:0]$2477 $2\xive7_pri$next[7:0]$2493
149958         assign $1\xive8_pri$next[7:0]$2478 $2\xive8_pri$next[7:0]$2494
149959         assign $1\xive9_pri$next[7:0]$2479 $2\xive9_pri$next[7:0]$2495
149960         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342"
149961         switch \reg_is_xive
149962           attribute \src "libresoc.v:0.0-0.0"
149963           case 1'1
149964             assign { } { }
149965             assign { } { }
149966             assign { } { }
149967             assign { } { }
149968             assign { } { }
149969             assign { } { }
149970             assign { } { }
149971             assign { } { }
149972             assign { } { }
149973             assign { } { }
149974             assign { } { }
149975             assign { } { }
149976             assign { } { }
149977             assign { } { }
149978             assign { } { }
149979             assign { } { }
149980             assign $2\xive0_pri$next[7:0]$2480 $3\xive0_pri$next[7:0]$2496
149981             assign $2\xive10_pri$next[7:0]$2481 $3\xive10_pri$next[7:0]$2497
149982             assign $2\xive11_pri$next[7:0]$2482 $3\xive11_pri$next[7:0]$2498
149983             assign $2\xive12_pri$next[7:0]$2483 $3\xive12_pri$next[7:0]$2499
149984             assign $2\xive13_pri$next[7:0]$2484 $3\xive13_pri$next[7:0]$2500
149985             assign $2\xive14_pri$next[7:0]$2485 $3\xive14_pri$next[7:0]$2501
149986             assign $2\xive15_pri$next[7:0]$2486 $3\xive15_pri$next[7:0]$2502
149987             assign $2\xive1_pri$next[7:0]$2487 $3\xive1_pri$next[7:0]$2503
149988             assign $2\xive2_pri$next[7:0]$2488 $3\xive2_pri$next[7:0]$2504
149989             assign $2\xive3_pri$next[7:0]$2489 $3\xive3_pri$next[7:0]$2505
149990             assign $2\xive4_pri$next[7:0]$2490 $3\xive4_pri$next[7:0]$2506
149991             assign $2\xive5_pri$next[7:0]$2491 $3\xive5_pri$next[7:0]$2507
149992             assign $2\xive6_pri$next[7:0]$2492 $3\xive6_pri$next[7:0]$2508
149993             assign $2\xive7_pri$next[7:0]$2493 $3\xive7_pri$next[7:0]$2509
149994             assign $2\xive8_pri$next[7:0]$2494 $3\xive8_pri$next[7:0]$2510
149995             assign $2\xive9_pri$next[7:0]$2495 $3\xive9_pri$next[7:0]$2511
149996             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345"
149997             switch \reg_idx
149998               attribute \src "libresoc.v:0.0-0.0"
149999               case 4'0000
150000                 assign { } { }
150001                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150002                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150003                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150004                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150005                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150006                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150007                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150008                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150009                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150010                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150011                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150012                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150013                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150014                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150015                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150016                 assign $3\xive0_pri$next[7:0]$2496 \be_in [7:0]
150017               attribute \src "libresoc.v:0.0-0.0"
150018               case 4'0001
150019                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150020                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150021                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150022                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150023                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150024                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150025                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150026                 assign { } { }
150027                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150028                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150029                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150030                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150031                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150032                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150033                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150034                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150035                 assign $3\xive1_pri$next[7:0]$2503 \be_in [7:0]
150036               attribute \src "libresoc.v:0.0-0.0"
150037               case 4'0010
150038                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150039                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150040                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150041                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150042                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150043                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150044                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150045                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150046                 assign { } { }
150047                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150048                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150049                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150050                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150051                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150052                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150053                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150054                 assign $3\xive2_pri$next[7:0]$2504 \be_in [7:0]
150055               attribute \src "libresoc.v:0.0-0.0"
150056               case 4'0011
150057                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150058                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150059                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150060                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150061                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150062                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150063                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150064                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150065                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150066                 assign { } { }
150067                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150068                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150069                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150070                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150071                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150072                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150073                 assign $3\xive3_pri$next[7:0]$2505 \be_in [7:0]
150074               attribute \src "libresoc.v:0.0-0.0"
150075               case 4'0100
150076                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150077                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150078                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150079                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150080                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150081                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150082                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150083                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150084                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150085                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150086                 assign { } { }
150087                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150088                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150089                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150090                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150091                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150092                 assign $3\xive4_pri$next[7:0]$2506 \be_in [7:0]
150093               attribute \src "libresoc.v:0.0-0.0"
150094               case 4'0101
150095                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150096                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150097                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150098                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150099                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150100                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150101                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150102                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150103                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150104                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150105                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150106                 assign { } { }
150107                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150108                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150109                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150110                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150111                 assign $3\xive5_pri$next[7:0]$2507 \be_in [7:0]
150112               attribute \src "libresoc.v:0.0-0.0"
150113               case 4'0110
150114                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150115                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150116                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150117                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150118                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150119                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150120                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150121                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150122                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150123                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150124                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150125                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150126                 assign { } { }
150127                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150128                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150129                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150130                 assign $3\xive6_pri$next[7:0]$2508 \be_in [7:0]
150131               attribute \src "libresoc.v:0.0-0.0"
150132               case 4'0111
150133                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150134                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150135                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150136                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150137                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150138                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150139                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150140                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150141                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150142                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150143                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150144                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150145                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150146                 assign { } { }
150147                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150148                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150149                 assign $3\xive7_pri$next[7:0]$2509 \be_in [7:0]
150150               attribute \src "libresoc.v:0.0-0.0"
150151               case 4'1000
150152                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150153                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150154                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150155                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150156                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150157                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150158                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150159                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150160                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150161                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150162                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150163                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150164                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150165                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150166                 assign { } { }
150167                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150168                 assign $3\xive8_pri$next[7:0]$2510 \be_in [7:0]
150169               attribute \src "libresoc.v:0.0-0.0"
150170               case 4'1001
150171                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150172                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150173                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150174                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150175                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150176                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150177                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150178                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150179                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150180                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150181                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150182                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150183                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150184                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150185                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150186                 assign { } { }
150187                 assign $3\xive9_pri$next[7:0]$2511 \be_in [7:0]
150188               attribute \src "libresoc.v:0.0-0.0"
150189               case 4'1010
150190                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150191                 assign { } { }
150192                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150193                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150194                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150195                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150196                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150197                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150198                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150199                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150200                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150201                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150202                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150203                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150204                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150205                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150206                 assign $3\xive10_pri$next[7:0]$2497 \be_in [7:0]
150207               attribute \src "libresoc.v:0.0-0.0"
150208               case 4'1011
150209                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150210                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150211                 assign { } { }
150212                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150213                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150214                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150215                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150216                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150217                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150218                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150219                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150220                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150221                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150222                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150223                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150224                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150225                 assign $3\xive11_pri$next[7:0]$2498 \be_in [7:0]
150226               attribute \src "libresoc.v:0.0-0.0"
150227               case 4'1100
150228                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150229                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150230                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150231                 assign { } { }
150232                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150233                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150234                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150235                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150236                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150237                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150238                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150239                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150240                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150241                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150242                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150243                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150244                 assign $3\xive12_pri$next[7:0]$2499 \be_in [7:0]
150245               attribute \src "libresoc.v:0.0-0.0"
150246               case 4'1101
150247                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150248                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150249                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150250                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150251                 assign { } { }
150252                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150253                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150254                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150255                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150256                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150257                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150258                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150259                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150260                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150261                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150262                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150263                 assign $3\xive13_pri$next[7:0]$2500 \be_in [7:0]
150264               attribute \src "libresoc.v:0.0-0.0"
150265               case 4'1110
150266                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150267                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150268                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150269                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150270                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150271                 assign { } { }
150272                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150273                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150274                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150275                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150276                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150277                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150278                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150279                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150280                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150281                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150282                 assign $3\xive14_pri$next[7:0]$2501 \be_in [7:0]
150283               attribute \src "libresoc.v:0.0-0.0"
150284               case 4'----
150285                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150286                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150287                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150288                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150289                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150290                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150291                 assign { } { }
150292                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150293                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150294                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150295                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150296                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150297                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150298                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150299                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150300                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150301                 assign $3\xive15_pri$next[7:0]$2502 \be_in [7:0]
150302               case
150303                 assign $3\xive0_pri$next[7:0]$2496 \xive0_pri
150304                 assign $3\xive10_pri$next[7:0]$2497 \xive10_pri
150305                 assign $3\xive11_pri$next[7:0]$2498 \xive11_pri
150306                 assign $3\xive12_pri$next[7:0]$2499 \xive12_pri
150307                 assign $3\xive13_pri$next[7:0]$2500 \xive13_pri
150308                 assign $3\xive14_pri$next[7:0]$2501 \xive14_pri
150309                 assign $3\xive15_pri$next[7:0]$2502 \xive15_pri
150310                 assign $3\xive1_pri$next[7:0]$2503 \xive1_pri
150311                 assign $3\xive2_pri$next[7:0]$2504 \xive2_pri
150312                 assign $3\xive3_pri$next[7:0]$2505 \xive3_pri
150313                 assign $3\xive4_pri$next[7:0]$2506 \xive4_pri
150314                 assign $3\xive5_pri$next[7:0]$2507 \xive5_pri
150315                 assign $3\xive6_pri$next[7:0]$2508 \xive6_pri
150316                 assign $3\xive7_pri$next[7:0]$2509 \xive7_pri
150317                 assign $3\xive8_pri$next[7:0]$2510 \xive8_pri
150318                 assign $3\xive9_pri$next[7:0]$2511 \xive9_pri
150319             end
150320           case
150321             assign $2\xive0_pri$next[7:0]$2480 \xive0_pri
150322             assign $2\xive10_pri$next[7:0]$2481 \xive10_pri
150323             assign $2\xive11_pri$next[7:0]$2482 \xive11_pri
150324             assign $2\xive12_pri$next[7:0]$2483 \xive12_pri
150325             assign $2\xive13_pri$next[7:0]$2484 \xive13_pri
150326             assign $2\xive14_pri$next[7:0]$2485 \xive14_pri
150327             assign $2\xive15_pri$next[7:0]$2486 \xive15_pri
150328             assign $2\xive1_pri$next[7:0]$2487 \xive1_pri
150329             assign $2\xive2_pri$next[7:0]$2488 \xive2_pri
150330             assign $2\xive3_pri$next[7:0]$2489 \xive3_pri
150331             assign $2\xive4_pri$next[7:0]$2490 \xive4_pri
150332             assign $2\xive5_pri$next[7:0]$2491 \xive5_pri
150333             assign $2\xive6_pri$next[7:0]$2492 \xive6_pri
150334             assign $2\xive7_pri$next[7:0]$2493 \xive7_pri
150335             assign $2\xive8_pri$next[7:0]$2494 \xive8_pri
150336             assign $2\xive9_pri$next[7:0]$2495 \xive9_pri
150337         end
150338       case
150339         assign $1\xive0_pri$next[7:0]$2464 \xive0_pri
150340         assign $1\xive10_pri$next[7:0]$2465 \xive10_pri
150341         assign $1\xive11_pri$next[7:0]$2466 \xive11_pri
150342         assign $1\xive12_pri$next[7:0]$2467 \xive12_pri
150343         assign $1\xive13_pri$next[7:0]$2468 \xive13_pri
150344         assign $1\xive14_pri$next[7:0]$2469 \xive14_pri
150345         assign $1\xive15_pri$next[7:0]$2470 \xive15_pri
150346         assign $1\xive1_pri$next[7:0]$2471 \xive1_pri
150347         assign $1\xive2_pri$next[7:0]$2472 \xive2_pri
150348         assign $1\xive3_pri$next[7:0]$2473 \xive3_pri
150349         assign $1\xive4_pri$next[7:0]$2474 \xive4_pri
150350         assign $1\xive5_pri$next[7:0]$2475 \xive5_pri
150351         assign $1\xive6_pri$next[7:0]$2476 \xive6_pri
150352         assign $1\xive7_pri$next[7:0]$2477 \xive7_pri
150353         assign $1\xive8_pri$next[7:0]$2478 \xive8_pri
150354         assign $1\xive9_pri$next[7:0]$2479 \xive9_pri
150355     end
150356     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
150357     switch \rst
150358       attribute \src "libresoc.v:0.0-0.0"
150359       case 1'1
150360         assign { } { }
150361         assign { } { }
150362         assign { } { }
150363         assign { } { }
150364         assign { } { }
150365         assign { } { }
150366         assign { } { }
150367         assign { } { }
150368         assign { } { }
150369         assign { } { }
150370         assign { } { }
150371         assign { } { }
150372         assign { } { }
150373         assign { } { }
150374         assign { } { }
150375         assign { } { }
150376         assign $4\xive0_pri$next[7:0]$2512 8'11111111
150377         assign $4\xive1_pri$next[7:0]$2519 8'11111111
150378         assign $4\xive2_pri$next[7:0]$2520 8'11111111
150379         assign $4\xive3_pri$next[7:0]$2521 8'11111111
150380         assign $4\xive4_pri$next[7:0]$2522 8'11111111
150381         assign $4\xive5_pri$next[7:0]$2523 8'11111111
150382         assign $4\xive6_pri$next[7:0]$2524 8'11111111
150383         assign $4\xive7_pri$next[7:0]$2525 8'11111111
150384         assign $4\xive8_pri$next[7:0]$2526 8'11111111
150385         assign $4\xive9_pri$next[7:0]$2527 8'11111111
150386         assign $4\xive10_pri$next[7:0]$2513 8'11111111
150387         assign $4\xive11_pri$next[7:0]$2514 8'11111111
150388         assign $4\xive12_pri$next[7:0]$2515 8'11111111
150389         assign $4\xive13_pri$next[7:0]$2516 8'11111111
150390         assign $4\xive14_pri$next[7:0]$2517 8'11111111
150391         assign $4\xive15_pri$next[7:0]$2518 8'11111111
150392       case
150393         assign $4\xive0_pri$next[7:0]$2512 $1\xive0_pri$next[7:0]$2464
150394         assign $4\xive10_pri$next[7:0]$2513 $1\xive10_pri$next[7:0]$2465
150395         assign $4\xive11_pri$next[7:0]$2514 $1\xive11_pri$next[7:0]$2466
150396         assign $4\xive12_pri$next[7:0]$2515 $1\xive12_pri$next[7:0]$2467
150397         assign $4\xive13_pri$next[7:0]$2516 $1\xive13_pri$next[7:0]$2468
150398         assign $4\xive14_pri$next[7:0]$2517 $1\xive14_pri$next[7:0]$2469
150399         assign $4\xive15_pri$next[7:0]$2518 $1\xive15_pri$next[7:0]$2470
150400         assign $4\xive1_pri$next[7:0]$2519 $1\xive1_pri$next[7:0]$2471
150401         assign $4\xive2_pri$next[7:0]$2520 $1\xive2_pri$next[7:0]$2472
150402         assign $4\xive3_pri$next[7:0]$2521 $1\xive3_pri$next[7:0]$2473
150403         assign $4\xive4_pri$next[7:0]$2522 $1\xive4_pri$next[7:0]$2474
150404         assign $4\xive5_pri$next[7:0]$2523 $1\xive5_pri$next[7:0]$2475
150405         assign $4\xive6_pri$next[7:0]$2524 $1\xive6_pri$next[7:0]$2476
150406         assign $4\xive7_pri$next[7:0]$2525 $1\xive7_pri$next[7:0]$2477
150407         assign $4\xive8_pri$next[7:0]$2526 $1\xive8_pri$next[7:0]$2478
150408         assign $4\xive9_pri$next[7:0]$2527 $1\xive9_pri$next[7:0]$2479
150409     end
150410     sync always
150411       update \xive0_pri$next $0\xive0_pri$next[7:0]$2448
150412       update \xive10_pri$next $0\xive10_pri$next[7:0]$2449
150413       update \xive11_pri$next $0\xive11_pri$next[7:0]$2450
150414       update \xive12_pri$next $0\xive12_pri$next[7:0]$2451
150415       update \xive13_pri$next $0\xive13_pri$next[7:0]$2452
150416       update \xive14_pri$next $0\xive14_pri$next[7:0]$2453
150417       update \xive15_pri$next $0\xive15_pri$next[7:0]$2454
150418       update \xive1_pri$next $0\xive1_pri$next[7:0]$2455
150419       update \xive2_pri$next $0\xive2_pri$next[7:0]$2456
150420       update \xive3_pri$next $0\xive3_pri$next[7:0]$2457
150421       update \xive4_pri$next $0\xive4_pri$next[7:0]$2458
150422       update \xive5_pri$next $0\xive5_pri$next[7:0]$2459
150423       update \xive6_pri$next $0\xive6_pri$next[7:0]$2460
150424       update \xive7_pri$next $0\xive7_pri$next[7:0]$2461
150425       update \xive8_pri$next $0\xive8_pri$next[7:0]$2462
150426       update \xive9_pri$next $0\xive9_pri$next[7:0]$2463
150427   end
150428   attribute \src "libresoc.v:53452.3-53461.6"
150429   process $proc$libresoc.v:53452$2528
150430     assign { } { }
150431     assign { } { }
150432     assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
150433     attribute \src "libresoc.v:53453.5-53453.29"
150434     switch \initial
150435       attribute \src "libresoc.v:53453.9-53453.17"
150436       case 1'1
150437       case
150438     end
150439     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150440     switch \$77
150441       attribute \src "libresoc.v:0.0-0.0"
150442       case 1'1
150443         assign { } { }
150444         assign $1\cur_pri0[7:0] \xive0_pri
150445       case
150446         assign $1\cur_pri0[7:0] \max_pri
150447     end
150448     sync always
150449       update \cur_pri0 $0\cur_pri0[7:0]
150450   end
150451   attribute \src "libresoc.v:53462.3-53471.6"
150452   process $proc$libresoc.v:53462$2529
150453     assign { } { }
150454     assign { } { }
150455     assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
150456     attribute \src "libresoc.v:53463.5-53463.29"
150457     switch \initial
150458       attribute \src "libresoc.v:53463.9-53463.17"
150459       case 1'1
150460       case
150461     end
150462     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150463     switch \$81
150464       attribute \src "libresoc.v:0.0-0.0"
150465       case 1'1
150466         assign { } { }
150467         assign $1\cur_idx0[3:0] 4'0000
150468       case
150469         assign $1\cur_idx0[3:0] \max_idx
150470     end
150471     sync always
150472       update \cur_idx0 $0\cur_idx0[3:0]
150473   end
150474   attribute \src "libresoc.v:53472.3-53481.6"
150475   process $proc$libresoc.v:53472$2530
150476     assign { } { }
150477     assign { } { }
150478     assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
150479     attribute \src "libresoc.v:53473.5-53473.29"
150480     switch \initial
150481       attribute \src "libresoc.v:53473.9-53473.17"
150482       case 1'1
150483       case
150484     end
150485     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150486     switch \$85
150487       attribute \src "libresoc.v:0.0-0.0"
150488       case 1'1
150489         assign { } { }
150490         assign $1\cur_pri1[7:0] \xive1_pri
150491       case
150492         assign $1\cur_pri1[7:0] \cur_pri0
150493     end
150494     sync always
150495       update \cur_pri1 $0\cur_pri1[7:0]
150496   end
150497   attribute \src "libresoc.v:53482.3-53491.6"
150498   process $proc$libresoc.v:53482$2531
150499     assign { } { }
150500     assign { } { }
150501     assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
150502     attribute \src "libresoc.v:53483.5-53483.29"
150503     switch \initial
150504       attribute \src "libresoc.v:53483.9-53483.17"
150505       case 1'1
150506       case
150507     end
150508     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150509     switch \$89
150510       attribute \src "libresoc.v:0.0-0.0"
150511       case 1'1
150512         assign { } { }
150513         assign $1\cur_idx1[3:0] 4'0001
150514       case
150515         assign $1\cur_idx1[3:0] \cur_idx0
150516     end
150517     sync always
150518       update \cur_idx1 $0\cur_idx1[3:0]
150519   end
150520   attribute \src "libresoc.v:53492.3-53501.6"
150521   process $proc$libresoc.v:53492$2532
150522     assign { } { }
150523     assign { } { }
150524     assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
150525     attribute \src "libresoc.v:53493.5-53493.29"
150526     switch \initial
150527       attribute \src "libresoc.v:53493.9-53493.17"
150528       case 1'1
150529       case
150530     end
150531     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150532     switch \$93
150533       attribute \src "libresoc.v:0.0-0.0"
150534       case 1'1
150535         assign { } { }
150536         assign $1\cur_pri2[7:0] \xive2_pri
150537       case
150538         assign $1\cur_pri2[7:0] \cur_pri1
150539     end
150540     sync always
150541       update \cur_pri2 $0\cur_pri2[7:0]
150542   end
150543   attribute \src "libresoc.v:53502.3-53511.6"
150544   process $proc$libresoc.v:53502$2533
150545     assign { } { }
150546     assign { } { }
150547     assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
150548     attribute \src "libresoc.v:53503.5-53503.29"
150549     switch \initial
150550       attribute \src "libresoc.v:53503.9-53503.17"
150551       case 1'1
150552       case
150553     end
150554     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150555     switch \$97
150556       attribute \src "libresoc.v:0.0-0.0"
150557       case 1'1
150558         assign { } { }
150559         assign $1\cur_idx2[3:0] 4'0010
150560       case
150561         assign $1\cur_idx2[3:0] \cur_idx1
150562     end
150563     sync always
150564       update \cur_idx2 $0\cur_idx2[3:0]
150565   end
150566   attribute \src "libresoc.v:53512.3-53521.6"
150567   process $proc$libresoc.v:53512$2534
150568     assign { } { }
150569     assign { } { }
150570     assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
150571     attribute \src "libresoc.v:53513.5-53513.29"
150572     switch \initial
150573       attribute \src "libresoc.v:53513.9-53513.17"
150574       case 1'1
150575       case
150576     end
150577     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150578     switch \$101
150579       attribute \src "libresoc.v:0.0-0.0"
150580       case 1'1
150581         assign { } { }
150582         assign $1\cur_pri3[7:0] \xive3_pri
150583       case
150584         assign $1\cur_pri3[7:0] \cur_pri2
150585     end
150586     sync always
150587       update \cur_pri3 $0\cur_pri3[7:0]
150588   end
150589   attribute \src "libresoc.v:53522.3-53531.6"
150590   process $proc$libresoc.v:53522$2535
150591     assign { } { }
150592     assign { } { }
150593     assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
150594     attribute \src "libresoc.v:53523.5-53523.29"
150595     switch \initial
150596       attribute \src "libresoc.v:53523.9-53523.17"
150597       case 1'1
150598       case
150599     end
150600     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150601     switch \$105
150602       attribute \src "libresoc.v:0.0-0.0"
150603       case 1'1
150604         assign { } { }
150605         assign $1\cur_idx3[3:0] 4'0011
150606       case
150607         assign $1\cur_idx3[3:0] \cur_idx2
150608     end
150609     sync always
150610       update \cur_idx3 $0\cur_idx3[3:0]
150611   end
150612   attribute \src "libresoc.v:53532.3-53541.6"
150613   process $proc$libresoc.v:53532$2536
150614     assign { } { }
150615     assign { } { }
150616     assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
150617     attribute \src "libresoc.v:53533.5-53533.29"
150618     switch \initial
150619       attribute \src "libresoc.v:53533.9-53533.17"
150620       case 1'1
150621       case
150622     end
150623     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150624     switch \$109
150625       attribute \src "libresoc.v:0.0-0.0"
150626       case 1'1
150627         assign { } { }
150628         assign $1\cur_pri4[7:0] \xive4_pri
150629       case
150630         assign $1\cur_pri4[7:0] \cur_pri3
150631     end
150632     sync always
150633       update \cur_pri4 $0\cur_pri4[7:0]
150634   end
150635   attribute \src "libresoc.v:53542.3-53550.6"
150636   process $proc$libresoc.v:53542$2537
150637     assign { } { }
150638     assign { } { }
150639     assign $0\int_level_l$next[15:0]$2538 $1\int_level_l$next[15:0]$2539
150640     attribute \src "libresoc.v:53543.5-53543.29"
150641     switch \initial
150642       attribute \src "libresoc.v:53543.9-53543.17"
150643       case 1'1
150644       case
150645     end
150646     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
150647     switch \rst
150648       attribute \src "libresoc.v:0.0-0.0"
150649       case 1'1
150650         assign { } { }
150651         assign $1\int_level_l$next[15:0]$2539 16'0000000000000000
150652       case
150653         assign $1\int_level_l$next[15:0]$2539 \int_level_i
150654     end
150655     sync always
150656       update \int_level_l$next $0\int_level_l$next[15:0]$2538
150657   end
150658   attribute \src "libresoc.v:53551.3-53560.6"
150659   process $proc$libresoc.v:53551$2540
150660     assign { } { }
150661     assign { } { }
150662     assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
150663     attribute \src "libresoc.v:53552.5-53552.29"
150664     switch \initial
150665       attribute \src "libresoc.v:53552.9-53552.17"
150666       case 1'1
150667       case
150668     end
150669     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150670     switch \$113
150671       attribute \src "libresoc.v:0.0-0.0"
150672       case 1'1
150673         assign { } { }
150674         assign $1\cur_idx4[3:0] 4'0100
150675       case
150676         assign $1\cur_idx4[3:0] \cur_idx3
150677     end
150678     sync always
150679       update \cur_idx4 $0\cur_idx4[3:0]
150680   end
150681   attribute \src "libresoc.v:53561.3-53570.6"
150682   process $proc$libresoc.v:53561$2541
150683     assign { } { }
150684     assign { } { }
150685     assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
150686     attribute \src "libresoc.v:53562.5-53562.29"
150687     switch \initial
150688       attribute \src "libresoc.v:53562.9-53562.17"
150689       case 1'1
150690       case
150691     end
150692     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150693     switch \$117
150694       attribute \src "libresoc.v:0.0-0.0"
150695       case 1'1
150696         assign { } { }
150697         assign $1\cur_pri5[7:0] \xive5_pri
150698       case
150699         assign $1\cur_pri5[7:0] \cur_pri4
150700     end
150701     sync always
150702       update \cur_pri5 $0\cur_pri5[7:0]
150703   end
150704   attribute \src "libresoc.v:53571.3-53580.6"
150705   process $proc$libresoc.v:53571$2542
150706     assign { } { }
150707     assign { } { }
150708     assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
150709     attribute \src "libresoc.v:53572.5-53572.29"
150710     switch \initial
150711       attribute \src "libresoc.v:53572.9-53572.17"
150712       case 1'1
150713       case
150714     end
150715     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150716     switch \$121
150717       attribute \src "libresoc.v:0.0-0.0"
150718       case 1'1
150719         assign { } { }
150720         assign $1\cur_idx5[3:0] 4'0101
150721       case
150722         assign $1\cur_idx5[3:0] \cur_idx4
150723     end
150724     sync always
150725       update \cur_idx5 $0\cur_idx5[3:0]
150726   end
150727   attribute \src "libresoc.v:53581.3-53590.6"
150728   process $proc$libresoc.v:53581$2543
150729     assign { } { }
150730     assign { } { }
150731     assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
150732     attribute \src "libresoc.v:53582.5-53582.29"
150733     switch \initial
150734       attribute \src "libresoc.v:53582.9-53582.17"
150735       case 1'1
150736       case
150737     end
150738     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150739     switch \$125
150740       attribute \src "libresoc.v:0.0-0.0"
150741       case 1'1
150742         assign { } { }
150743         assign $1\cur_pri6[7:0] \xive6_pri
150744       case
150745         assign $1\cur_pri6[7:0] \cur_pri5
150746     end
150747     sync always
150748       update \cur_pri6 $0\cur_pri6[7:0]
150749   end
150750   attribute \src "libresoc.v:53591.3-53600.6"
150751   process $proc$libresoc.v:53591$2544
150752     assign { } { }
150753     assign { } { }
150754     assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
150755     attribute \src "libresoc.v:53592.5-53592.29"
150756     switch \initial
150757       attribute \src "libresoc.v:53592.9-53592.17"
150758       case 1'1
150759       case
150760     end
150761     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150762     switch \$129
150763       attribute \src "libresoc.v:0.0-0.0"
150764       case 1'1
150765         assign { } { }
150766         assign $1\cur_idx6[3:0] 4'0110
150767       case
150768         assign $1\cur_idx6[3:0] \cur_idx5
150769     end
150770     sync always
150771       update \cur_idx6 $0\cur_idx6[3:0]
150772   end
150773   attribute \src "libresoc.v:53601.3-53610.6"
150774   process $proc$libresoc.v:53601$2545
150775     assign { } { }
150776     assign { } { }
150777     assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
150778     attribute \src "libresoc.v:53602.5-53602.29"
150779     switch \initial
150780       attribute \src "libresoc.v:53602.9-53602.17"
150781       case 1'1
150782       case
150783     end
150784     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150785     switch \$133
150786       attribute \src "libresoc.v:0.0-0.0"
150787       case 1'1
150788         assign { } { }
150789         assign $1\cur_pri7[7:0] \xive7_pri
150790       case
150791         assign $1\cur_pri7[7:0] \cur_pri6
150792     end
150793     sync always
150794       update \cur_pri7 $0\cur_pri7[7:0]
150795   end
150796   attribute \src "libresoc.v:53611.3-53620.6"
150797   process $proc$libresoc.v:53611$2546
150798     assign { } { }
150799     assign { } { }
150800     assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
150801     attribute \src "libresoc.v:53612.5-53612.29"
150802     switch \initial
150803       attribute \src "libresoc.v:53612.9-53612.17"
150804       case 1'1
150805       case
150806     end
150807     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150808     switch \$137
150809       attribute \src "libresoc.v:0.0-0.0"
150810       case 1'1
150811         assign { } { }
150812         assign $1\cur_idx7[3:0] 4'0111
150813       case
150814         assign $1\cur_idx7[3:0] \cur_idx6
150815     end
150816     sync always
150817       update \cur_idx7 $0\cur_idx7[3:0]
150818   end
150819   attribute \src "libresoc.v:53621.3-53630.6"
150820   process $proc$libresoc.v:53621$2547
150821     assign { } { }
150822     assign { } { }
150823     assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
150824     attribute \src "libresoc.v:53622.5-53622.29"
150825     switch \initial
150826       attribute \src "libresoc.v:53622.9-53622.17"
150827       case 1'1
150828       case
150829     end
150830     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150831     switch \$141
150832       attribute \src "libresoc.v:0.0-0.0"
150833       case 1'1
150834         assign { } { }
150835         assign $1\cur_pri8[7:0] \xive8_pri
150836       case
150837         assign $1\cur_pri8[7:0] \cur_pri7
150838     end
150839     sync always
150840       update \cur_pri8 $0\cur_pri8[7:0]
150841   end
150842   attribute \src "libresoc.v:53631.3-53640.6"
150843   process $proc$libresoc.v:53631$2548
150844     assign { } { }
150845     assign { } { }
150846     assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
150847     attribute \src "libresoc.v:53632.5-53632.29"
150848     switch \initial
150849       attribute \src "libresoc.v:53632.9-53632.17"
150850       case 1'1
150851       case
150852     end
150853     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150854     switch \$145
150855       attribute \src "libresoc.v:0.0-0.0"
150856       case 1'1
150857         assign { } { }
150858         assign $1\cur_idx8[3:0] 4'1000
150859       case
150860         assign $1\cur_idx8[3:0] \cur_idx7
150861     end
150862     sync always
150863       update \cur_idx8 $0\cur_idx8[3:0]
150864   end
150865   attribute \src "libresoc.v:53641.3-53650.6"
150866   process $proc$libresoc.v:53641$2549
150867     assign { } { }
150868     assign { } { }
150869     assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
150870     attribute \src "libresoc.v:53642.5-53642.29"
150871     switch \initial
150872       attribute \src "libresoc.v:53642.9-53642.17"
150873       case 1'1
150874       case
150875     end
150876     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150877     switch \$149
150878       attribute \src "libresoc.v:0.0-0.0"
150879       case 1'1
150880         assign { } { }
150881         assign $1\cur_pri9[7:0] \xive9_pri
150882       case
150883         assign $1\cur_pri9[7:0] \cur_pri8
150884     end
150885     sync always
150886       update \cur_pri9 $0\cur_pri9[7:0]
150887   end
150888   attribute \src "libresoc.v:53651.3-53660.6"
150889   process $proc$libresoc.v:53651$2550
150890     assign { } { }
150891     assign { } { }
150892     assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
150893     attribute \src "libresoc.v:53652.5-53652.29"
150894     switch \initial
150895       attribute \src "libresoc.v:53652.9-53652.17"
150896       case 1'1
150897       case
150898     end
150899     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150900     switch \$153
150901       attribute \src "libresoc.v:0.0-0.0"
150902       case 1'1
150903         assign { } { }
150904         assign $1\cur_idx9[3:0] 4'1001
150905       case
150906         assign $1\cur_idx9[3:0] \cur_idx8
150907     end
150908     sync always
150909       update \cur_idx9 $0\cur_idx9[3:0]
150910   end
150911   attribute \src "libresoc.v:53661.3-53670.6"
150912   process $proc$libresoc.v:53661$2551
150913     assign { } { }
150914     assign { } { }
150915     assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
150916     attribute \src "libresoc.v:53662.5-53662.29"
150917     switch \initial
150918       attribute \src "libresoc.v:53662.9-53662.17"
150919       case 1'1
150920       case
150921     end
150922     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150923     switch \$157
150924       attribute \src "libresoc.v:0.0-0.0"
150925       case 1'1
150926         assign { } { }
150927         assign $1\cur_pri10[7:0] \xive10_pri
150928       case
150929         assign $1\cur_pri10[7:0] \cur_pri9
150930     end
150931     sync always
150932       update \cur_pri10 $0\cur_pri10[7:0]
150933   end
150934   attribute \src "libresoc.v:53671.3-53680.6"
150935   process $proc$libresoc.v:53671$2552
150936     assign { } { }
150937     assign { } { }
150938     assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
150939     attribute \src "libresoc.v:53672.5-53672.29"
150940     switch \initial
150941       attribute \src "libresoc.v:53672.9-53672.17"
150942       case 1'1
150943       case
150944     end
150945     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150946     switch \$161
150947       attribute \src "libresoc.v:0.0-0.0"
150948       case 1'1
150949         assign { } { }
150950         assign $1\cur_idx10[3:0] 4'1010
150951       case
150952         assign $1\cur_idx10[3:0] \cur_idx9
150953     end
150954     sync always
150955       update \cur_idx10 $0\cur_idx10[3:0]
150956   end
150957   attribute \src "libresoc.v:53681.3-53690.6"
150958   process $proc$libresoc.v:53681$2553
150959     assign { } { }
150960     assign { } { }
150961     assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
150962     attribute \src "libresoc.v:53682.5-53682.29"
150963     switch \initial
150964       attribute \src "libresoc.v:53682.9-53682.17"
150965       case 1'1
150966       case
150967     end
150968     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150969     switch \$165
150970       attribute \src "libresoc.v:0.0-0.0"
150971       case 1'1
150972         assign { } { }
150973         assign $1\cur_pri11[7:0] \xive11_pri
150974       case
150975         assign $1\cur_pri11[7:0] \cur_pri10
150976     end
150977     sync always
150978       update \cur_pri11 $0\cur_pri11[7:0]
150979   end
150980   attribute \src "libresoc.v:53691.3-53700.6"
150981   process $proc$libresoc.v:53691$2554
150982     assign { } { }
150983     assign { } { }
150984     assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
150985     attribute \src "libresoc.v:53692.5-53692.29"
150986     switch \initial
150987       attribute \src "libresoc.v:53692.9-53692.17"
150988       case 1'1
150989       case
150990     end
150991     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
150992     switch \$169
150993       attribute \src "libresoc.v:0.0-0.0"
150994       case 1'1
150995         assign { } { }
150996         assign $1\cur_idx11[3:0] 4'1011
150997       case
150998         assign $1\cur_idx11[3:0] \cur_idx10
150999     end
151000     sync always
151001       update \cur_idx11 $0\cur_idx11[3:0]
151002   end
151003   attribute \src "libresoc.v:53701.3-53710.6"
151004   process $proc$libresoc.v:53701$2555
151005     assign { } { }
151006     assign { } { }
151007     assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
151008     attribute \src "libresoc.v:53702.5-53702.29"
151009     switch \initial
151010       attribute \src "libresoc.v:53702.9-53702.17"
151011       case 1'1
151012       case
151013     end
151014     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151015     switch \$173
151016       attribute \src "libresoc.v:0.0-0.0"
151017       case 1'1
151018         assign { } { }
151019         assign $1\cur_pri12[7:0] \xive12_pri
151020       case
151021         assign $1\cur_pri12[7:0] \cur_pri11
151022     end
151023     sync always
151024       update \cur_pri12 $0\cur_pri12[7:0]
151025   end
151026   attribute \src "libresoc.v:53711.3-53720.6"
151027   process $proc$libresoc.v:53711$2556
151028     assign { } { }
151029     assign { } { }
151030     assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
151031     attribute \src "libresoc.v:53712.5-53712.29"
151032     switch \initial
151033       attribute \src "libresoc.v:53712.9-53712.17"
151034       case 1'1
151035       case
151036     end
151037     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151038     switch \$177
151039       attribute \src "libresoc.v:0.0-0.0"
151040       case 1'1
151041         assign { } { }
151042         assign $1\cur_idx12[3:0] 4'1100
151043       case
151044         assign $1\cur_idx12[3:0] \cur_idx11
151045     end
151046     sync always
151047       update \cur_idx12 $0\cur_idx12[3:0]
151048   end
151049   attribute \src "libresoc.v:53721.3-53730.6"
151050   process $proc$libresoc.v:53721$2557
151051     assign { } { }
151052     assign { } { }
151053     assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
151054     attribute \src "libresoc.v:53722.5-53722.29"
151055     switch \initial
151056       attribute \src "libresoc.v:53722.9-53722.17"
151057       case 1'1
151058       case
151059     end
151060     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151061     switch \$181
151062       attribute \src "libresoc.v:0.0-0.0"
151063       case 1'1
151064         assign { } { }
151065         assign $1\cur_pri13[7:0] \xive13_pri
151066       case
151067         assign $1\cur_pri13[7:0] \cur_pri12
151068     end
151069     sync always
151070       update \cur_pri13 $0\cur_pri13[7:0]
151071   end
151072   attribute \src "libresoc.v:53731.3-53740.6"
151073   process $proc$libresoc.v:53731$2558
151074     assign { } { }
151075     assign { } { }
151076     assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
151077     attribute \src "libresoc.v:53732.5-53732.29"
151078     switch \initial
151079       attribute \src "libresoc.v:53732.9-53732.17"
151080       case 1'1
151081       case
151082     end
151083     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151084     switch \$185
151085       attribute \src "libresoc.v:0.0-0.0"
151086       case 1'1
151087         assign { } { }
151088         assign $1\cur_idx13[3:0] 4'1101
151089       case
151090         assign $1\cur_idx13[3:0] \cur_idx12
151091     end
151092     sync always
151093       update \cur_idx13 $0\cur_idx13[3:0]
151094   end
151095   attribute \src "libresoc.v:53741.3-53750.6"
151096   process $proc$libresoc.v:53741$2559
151097     assign { } { }
151098     assign { } { }
151099     assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
151100     attribute \src "libresoc.v:53742.5-53742.29"
151101     switch \initial
151102       attribute \src "libresoc.v:53742.9-53742.17"
151103       case 1'1
151104       case
151105     end
151106     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151107     switch \$189
151108       attribute \src "libresoc.v:0.0-0.0"
151109       case 1'1
151110         assign { } { }
151111         assign $1\cur_pri14[7:0] \xive14_pri
151112       case
151113         assign $1\cur_pri14[7:0] \cur_pri13
151114     end
151115     sync always
151116       update \cur_pri14 $0\cur_pri14[7:0]
151117   end
151118   attribute \src "libresoc.v:53751.3-53800.6"
151119   process $proc$libresoc.v:53751$2560
151120     assign { } { }
151121     assign { } { }
151122     assign $0\be_out[31:0] $1\be_out[31:0]
151123     attribute \src "libresoc.v:53752.5-53752.29"
151124     switch \initial
151125       attribute \src "libresoc.v:53752.9-53752.17"
151126       case 1'1
151127       case
151128     end
151129     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312"
151130     switch { \reg_is_debug \reg_is_config \reg_is_xive }
151131       attribute \src "libresoc.v:0.0-0.0"
151132       case 3'--1
151133         assign { } { }
151134         assign $1\be_out[31:0] $2\be_out[31:0]
151135         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
151136         switch \reg_idx
151137           attribute \src "libresoc.v:0.0-0.0"
151138           case 4'0000
151139             assign { } { }
151140             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 }
151141           attribute \src "libresoc.v:0.0-0.0"
151142           case 4'0001
151143             assign { } { }
151144             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 }
151145           attribute \src "libresoc.v:0.0-0.0"
151146           case 4'0010
151147             assign { } { }
151148             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 }
151149           attribute \src "libresoc.v:0.0-0.0"
151150           case 4'0011
151151             assign { } { }
151152             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 }
151153           attribute \src "libresoc.v:0.0-0.0"
151154           case 4'0100
151155             assign { } { }
151156             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 }
151157           attribute \src "libresoc.v:0.0-0.0"
151158           case 4'0101
151159             assign { } { }
151160             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 }
151161           attribute \src "libresoc.v:0.0-0.0"
151162           case 4'0110
151163             assign { } { }
151164             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 }
151165           attribute \src "libresoc.v:0.0-0.0"
151166           case 4'0111
151167             assign { } { }
151168             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 }
151169           attribute \src "libresoc.v:0.0-0.0"
151170           case 4'1000
151171             assign { } { }
151172             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 }
151173           attribute \src "libresoc.v:0.0-0.0"
151174           case 4'1001
151175             assign { } { }
151176             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 }
151177           attribute \src "libresoc.v:0.0-0.0"
151178           case 4'1010
151179             assign { } { }
151180             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 }
151181           attribute \src "libresoc.v:0.0-0.0"
151182           case 4'1011
151183             assign { } { }
151184             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 }
151185           attribute \src "libresoc.v:0.0-0.0"
151186           case 4'1100
151187             assign { } { }
151188             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 }
151189           attribute \src "libresoc.v:0.0-0.0"
151190           case 4'1101
151191             assign { } { }
151192             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 }
151193           attribute \src "libresoc.v:0.0-0.0"
151194           case 4'1110
151195             assign { } { }
151196             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 }
151197           attribute \src "libresoc.v:0.0-0.0"
151198           case 4'----
151199             assign { } { }
151200             assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 }
151201           case
151202             assign $2\be_out[31:0] 0
151203         end
151204       attribute \src "libresoc.v:0.0-0.0"
151205       case 3'-1-
151206         assign { } { }
151207         assign $1\be_out[31:0] 134217744
151208       attribute \src "libresoc.v:0.0-0.0"
151209       case 3'1--
151210         assign { } { }
151211         assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri }
151212       case
151213         assign $1\be_out[31:0] 0
151214     end
151215     sync always
151216       update \be_out $0\be_out[31:0]
151217   end
151218   attribute \src "libresoc.v:53801.3-53810.6"
151219   process $proc$libresoc.v:53801$2561
151220     assign { } { }
151221     assign { } { }
151222     assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
151223     attribute \src "libresoc.v:53802.5-53802.29"
151224     switch \initial
151225       attribute \src "libresoc.v:53802.9-53802.17"
151226       case 1'1
151227       case
151228     end
151229     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151230     switch \$193
151231       attribute \src "libresoc.v:0.0-0.0"
151232       case 1'1
151233         assign { } { }
151234         assign $1\cur_idx14[3:0] 4'1110
151235       case
151236         assign $1\cur_idx14[3:0] \cur_idx13
151237     end
151238     sync always
151239       update \cur_idx14 $0\cur_idx14[3:0]
151240   end
151241   attribute \src "libresoc.v:53811.3-53820.6"
151242   process $proc$libresoc.v:53811$2562
151243     assign { } { }
151244     assign { } { }
151245     assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
151246     attribute \src "libresoc.v:53812.5-53812.29"
151247     switch \initial
151248       attribute \src "libresoc.v:53812.9-53812.17"
151249       case 1'1
151250       case
151251     end
151252     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151253     switch \$197
151254       attribute \src "libresoc.v:0.0-0.0"
151255       case 1'1
151256         assign { } { }
151257         assign $1\cur_pri15[7:0] \xive15_pri
151258       case
151259         assign $1\cur_pri15[7:0] \cur_pri14
151260     end
151261     sync always
151262       update \cur_pri15 $0\cur_pri15[7:0]
151263   end
151264   attribute \src "libresoc.v:53821.3-53830.6"
151265   process $proc$libresoc.v:53821$2563
151266     assign { } { }
151267     assign { } { }
151268     assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
151269     attribute \src "libresoc.v:53822.5-53822.29"
151270     switch \initial
151271       attribute \src "libresoc.v:53822.9-53822.17"
151272       case 1'1
151273       case
151274     end
151275     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
151276     switch \$201
151277       attribute \src "libresoc.v:0.0-0.0"
151278       case 1'1
151279         assign { } { }
151280         assign $1\cur_idx15[3:0] 4'1111
151281       case
151282         assign $1\cur_idx15[3:0] \cur_idx14
151283     end
151284     sync always
151285       update \cur_idx15 $0\cur_idx15[3:0]
151286   end
151287   attribute \src "libresoc.v:53831.3-53840.6"
151288   process $proc$libresoc.v:53831$2564
151289     assign { } { }
151290     assign { } { }
151291     assign $0\ibit[0:0] $1\ibit[0:0]
151292     attribute \src "libresoc.v:53832.5-53832.29"
151293     switch \initial
151294       attribute \src "libresoc.v:53832.9-53832.17"
151295       case 1'1
151296       case
151297     end
151298     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312"
151299     switch { \reg_is_debug \reg_is_config \reg_is_xive }
151300       attribute \src "libresoc.v:0.0-0.0"
151301       case 3'--1
151302         assign { } { }
151303         assign $1\ibit[0:0] \$71
151304       case
151305         assign $1\ibit[0:0] 1'0
151306     end
151307     sync always
151308       update \ibit $0\ibit[0:0]
151309   end
151310   attribute \src "libresoc.v:53841.3-53849.6"
151311   process $proc$libresoc.v:53841$2565
151312     assign { } { }
151313     assign { } { }
151314     assign $0\ics_wb__dat_r$next[31:0]$2566 $1\ics_wb__dat_r$next[31:0]$2567
151315     attribute \src "libresoc.v:53842.5-53842.29"
151316     switch \initial
151317       attribute \src "libresoc.v:53842.9-53842.17"
151318       case 1'1
151319       case
151320     end
151321     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
151322     switch \rst
151323       attribute \src "libresoc.v:0.0-0.0"
151324       case 1'1
151325         assign { } { }
151326         assign $1\ics_wb__dat_r$next[31:0]$2567 0
151327       case
151328         assign $1\ics_wb__dat_r$next[31:0]$2567 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
151329     end
151330     sync always
151331       update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2566
151332   end
151333   attribute \src "libresoc.v:53850.3-53858.6"
151334   process $proc$libresoc.v:53850$2568
151335     assign { } { }
151336     assign { } { }
151337     assign $0\ics_wb__ack$next[0:0]$2569 $1\ics_wb__ack$next[0:0]$2570
151338     attribute \src "libresoc.v:53851.5-53851.29"
151339     switch \initial
151340       attribute \src "libresoc.v:53851.9-53851.17"
151341       case 1'1
151342       case
151343     end
151344     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
151345     switch \rst
151346       attribute \src "libresoc.v:0.0-0.0"
151347       case 1'1
151348         assign { } { }
151349         assign $1\ics_wb__ack$next[0:0]$2570 1'0
151350       case
151351         assign $1\ics_wb__ack$next[0:0]$2570 \wb_valid
151352     end
151353     sync always
151354       update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2569
151355   end
151356   connect \$7 $ternary$libresoc.v:53221$2323_Y
151357   connect \$99 $lt$libresoc.v:53222$2324_Y
151358   connect \$101 $and$libresoc.v:53223$2325_Y
151359   connect \$103 $lt$libresoc.v:53224$2326_Y
151360   connect \$105 $and$libresoc.v:53225$2327_Y
151361   connect \$107 $lt$libresoc.v:53226$2328_Y
151362   connect \$109 $and$libresoc.v:53227$2329_Y
151363   connect \$111 $lt$libresoc.v:53228$2330_Y
151364   connect \$113 $and$libresoc.v:53229$2331_Y
151365   connect \$115 $lt$libresoc.v:53230$2332_Y
151366   connect \$117 $and$libresoc.v:53231$2333_Y
151367   connect \$119 $lt$libresoc.v:53232$2334_Y
151368   connect \$121 $and$libresoc.v:53233$2335_Y
151369   connect \$123 $lt$libresoc.v:53234$2336_Y
151370   connect \$125 $and$libresoc.v:53235$2337_Y
151371   connect \$127 $lt$libresoc.v:53236$2338_Y
151372   connect \$12 $eq$libresoc.v:53237$2339_Y
151373   connect \$129 $and$libresoc.v:53238$2340_Y
151374   connect \$131 $lt$libresoc.v:53239$2341_Y
151375   connect \$133 $and$libresoc.v:53240$2342_Y
151376   connect \$135 $lt$libresoc.v:53241$2343_Y
151377   connect \$137 $and$libresoc.v:53242$2344_Y
151378   connect \$11 $ternary$libresoc.v:53243$2345_Y
151379   connect \$139 $lt$libresoc.v:53244$2346_Y
151380   connect \$141 $and$libresoc.v:53245$2347_Y
151381   connect \$143 $lt$libresoc.v:53246$2348_Y
151382   connect \$145 $and$libresoc.v:53247$2349_Y
151383   connect \$147 $lt$libresoc.v:53248$2350_Y
151384   connect \$149 $and$libresoc.v:53249$2351_Y
151385   connect \$151 $lt$libresoc.v:53250$2352_Y
151386   connect \$153 $and$libresoc.v:53251$2353_Y
151387   connect \$155 $lt$libresoc.v:53252$2354_Y
151388   connect \$157 $and$libresoc.v:53253$2355_Y
151389   connect \$159 $lt$libresoc.v:53254$2356_Y
151390   connect \$161 $and$libresoc.v:53255$2357_Y
151391   connect \$163 $lt$libresoc.v:53256$2358_Y
151392   connect \$165 $and$libresoc.v:53257$2359_Y
151393   connect \$167 $lt$libresoc.v:53258$2360_Y
151394   connect \$16 $eq$libresoc.v:53259$2361_Y
151395   connect \$169 $and$libresoc.v:53260$2362_Y
151396   connect \$171 $lt$libresoc.v:53261$2363_Y
151397   connect \$173 $and$libresoc.v:53262$2364_Y
151398   connect \$175 $lt$libresoc.v:53263$2365_Y
151399   connect \$177 $and$libresoc.v:53264$2366_Y
151400   connect \$15 $ternary$libresoc.v:53265$2367_Y
151401   connect \$179 $lt$libresoc.v:53266$2368_Y
151402   connect \$181 $and$libresoc.v:53267$2369_Y
151403   connect \$183 $lt$libresoc.v:53268$2370_Y
151404   connect \$185 $and$libresoc.v:53269$2371_Y
151405   connect \$187 $lt$libresoc.v:53270$2372_Y
151406   connect \$189 $and$libresoc.v:53271$2373_Y
151407   connect \$191 $lt$libresoc.v:53272$2374_Y
151408   connect \$193 $and$libresoc.v:53273$2375_Y
151409   connect \$195 $lt$libresoc.v:53274$2376_Y
151410   connect \$197 $and$libresoc.v:53275$2377_Y
151411   connect \$1 $eq$libresoc.v:53276$2378_Y
151412   connect \$199 $lt$libresoc.v:53277$2379_Y
151413   connect \$201 $and$libresoc.v:53278$2380_Y
151414   connect \$204 $eq$libresoc.v:53279$2381_Y
151415   connect \$203 $ternary$libresoc.v:53280$2382_Y
151416   connect \$20 $eq$libresoc.v:53281$2383_Y
151417   connect \$19 $ternary$libresoc.v:53282$2384_Y
151418   connect \$24 $eq$libresoc.v:53283$2385_Y
151419   connect \$23 $ternary$libresoc.v:53284$2386_Y
151420   connect \$28 $eq$libresoc.v:53285$2387_Y
151421   connect \$27 $ternary$libresoc.v:53286$2388_Y
151422   connect \$32 $eq$libresoc.v:53287$2389_Y
151423   connect \$31 $ternary$libresoc.v:53288$2390_Y
151424   connect \$36 $eq$libresoc.v:53289$2391_Y
151425   connect \$35 $ternary$libresoc.v:53290$2392_Y
151426   connect \$3 $eq$libresoc.v:53291$2393_Y
151427   connect \$40 $eq$libresoc.v:53292$2394_Y
151428   connect \$39 $ternary$libresoc.v:53293$2395_Y
151429   connect \$44 $eq$libresoc.v:53294$2396_Y
151430   connect \$43 $ternary$libresoc.v:53295$2397_Y
151431   connect \$48 $eq$libresoc.v:53296$2398_Y
151432   connect \$47 $ternary$libresoc.v:53297$2399_Y
151433   connect \$52 $eq$libresoc.v:53298$2400_Y
151434   connect \$51 $ternary$libresoc.v:53299$2401_Y
151435   connect \$56 $eq$libresoc.v:53300$2402_Y
151436   connect \$55 $ternary$libresoc.v:53301$2403_Y
151437   connect \$5 $and$libresoc.v:53302$2404_Y
151438   connect \$60 $eq$libresoc.v:53303$2405_Y
151439   connect \$59 $ternary$libresoc.v:53304$2406_Y
151440   connect \$64 $eq$libresoc.v:53305$2407_Y
151441   connect \$63 $ternary$libresoc.v:53306$2408_Y
151442   connect \$68 $eq$libresoc.v:53307$2409_Y
151443   connect \$67 $ternary$libresoc.v:53308$2410_Y
151444   connect \$71 $shr$libresoc.v:53309$2411_Y [0]
151445   connect \$73 $and$libresoc.v:53310$2412_Y
151446   connect \$75 $lt$libresoc.v:53311$2413_Y
151447   connect \$77 $and$libresoc.v:53312$2414_Y
151448   connect \$79 $lt$libresoc.v:53313$2415_Y
151449   connect \$81 $and$libresoc.v:53314$2416_Y
151450   connect \$83 $lt$libresoc.v:53315$2417_Y
151451   connect \$85 $and$libresoc.v:53316$2418_Y
151452   connect \$87 $lt$libresoc.v:53317$2419_Y
151453   connect \$8 $eq$libresoc.v:53318$2420_Y
151454   connect \$89 $and$libresoc.v:53319$2421_Y
151455   connect \$91 $lt$libresoc.v:53320$2422_Y
151456   connect \$93 $and$libresoc.v:53321$2423_Y
151457   connect \$95 $lt$libresoc.v:53322$2424_Y
151458   connect \$97 $and$libresoc.v:53323$2425_Y
151459   connect \icp_r_pri \$203
151460   connect \icp_r_src \cur_idx15
151461   connect \max_idx 4'0000
151462   connect \max_pri 8'11111111
151463   connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src }
151464   connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] }
151465   connect \wb_valid \$5
151466   connect \reg_idx \ics_wb__adr [3:0]
151467   connect \reg_is_debug \$3
151468   connect \reg_is_config \$1
151469   connect \reg_is_xive \ics_wb__adr [9]
151470 end