connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
connect \output_muxid \muxid
end
-attribute \src "ls180.v:4.1-5963.10"
+attribute \src "ls180.v:4.1-5982.10"
attribute \cells_not_processed 1
module \ls180
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1460
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1461
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5493$1_EN[63:0]$1462
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1463
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1464
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5495$2_EN[63:0]$1465
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1466
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1467
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5497$3_EN[63:0]$1468
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1469
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1470
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5499$4_EN[63:0]$1471
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1472
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1473
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5501$5_EN[63:0]$1474
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1475
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1476
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5503$6_EN[63:0]$1477
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1478
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1479
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5505$7_EN[63:0]$1480
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $0$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1481
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1482
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $0$memwr$\mem$ls180.v:5507$8_EN[63:0]$1483
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1510
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1511
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1512
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1513
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1514
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1515
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1516
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1517
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1518
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1519
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1520
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1521
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1522
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1523
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1524
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1525
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1526
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1527
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1528
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1529
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1530
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $0$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1531
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1532
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $0$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1533
- attribute \src "ls180.v:5547.1-5551.4"
- wire width 3 $0$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1560
- attribute \src "ls180.v:5547.1-5551.4"
- wire width 25 $0$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1561
- attribute \src "ls180.v:5547.1-5551.4"
- wire width 25 $0$memwr$\storage$ls180.v:5549$17_EN[24:0]$1562
- attribute \src "ls180.v:5561.1-5565.4"
- wire width 3 $0$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1570
- attribute \src "ls180.v:5561.1-5565.4"
- wire width 25 $0$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1571
- attribute \src "ls180.v:5561.1-5565.4"
- wire width 25 $0$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1572
- attribute \src "ls180.v:5575.1-5579.4"
- wire width 3 $0$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1580
- attribute \src "ls180.v:5575.1-5579.4"
- wire width 25 $0$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1581
- attribute \src "ls180.v:5575.1-5579.4"
- wire width 25 $0$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1582
- attribute \src "ls180.v:5589.1-5593.4"
- wire width 3 $0$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1590
- attribute \src "ls180.v:5589.1-5593.4"
- wire width 25 $0$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1591
- attribute \src "ls180.v:5589.1-5593.4"
- wire width 25 $0$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1592
- attribute \src "ls180.v:5604.1-5608.4"
- wire width 4 $0$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1600
- attribute \src "ls180.v:5604.1-5608.4"
- wire width 10 $0$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1601
- attribute \src "ls180.v:5604.1-5608.4"
- wire width 10 $0$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1602
- attribute \src "ls180.v:5621.1-5625.4"
- wire width 4 $0$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1610
- attribute \src "ls180.v:5621.1-5625.4"
- wire width 10 $0$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1611
- attribute \src "ls180.v:5621.1-5625.4"
- wire width 10 $0$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1612
- attribute \src "ls180.v:3951.1-3967.4"
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1467
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1468
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5512$1_EN[63:0]$1469
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1470
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1471
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5514$2_EN[63:0]$1472
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1473
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1474
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5516$3_EN[63:0]$1475
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1476
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1477
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5518$4_EN[63:0]$1478
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1479
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1480
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5520$5_EN[63:0]$1481
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1482
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1483
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5522$6_EN[63:0]$1484
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1485
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1486
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5524$7_EN[63:0]$1487
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $0$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1488
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1489
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $0$memwr$\mem$ls180.v:5526$8_EN[63:0]$1490
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1517
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1518
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1519
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1520
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1521
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1522
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1523
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1524
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1525
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1526
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1527
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1528
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1529
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1530
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1531
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1532
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1533
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1534
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1535
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1536
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1537
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $0$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1538
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1539
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $0$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1540
+ attribute \src "ls180.v:5566.1-5570.4"
+ wire width 3 $0$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1567
+ attribute \src "ls180.v:5566.1-5570.4"
+ wire width 25 $0$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1568
+ attribute \src "ls180.v:5566.1-5570.4"
+ wire width 25 $0$memwr$\storage$ls180.v:5568$17_EN[24:0]$1569
+ attribute \src "ls180.v:5580.1-5584.4"
+ wire width 3 $0$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1577
+ attribute \src "ls180.v:5580.1-5584.4"
+ wire width 25 $0$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1578
+ attribute \src "ls180.v:5580.1-5584.4"
+ wire width 25 $0$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1579
+ attribute \src "ls180.v:5594.1-5598.4"
+ wire width 3 $0$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1587
+ attribute \src "ls180.v:5594.1-5598.4"
+ wire width 25 $0$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1588
+ attribute \src "ls180.v:5594.1-5598.4"
+ wire width 25 $0$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1589
+ attribute \src "ls180.v:5608.1-5612.4"
+ wire width 3 $0$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1597
+ attribute \src "ls180.v:5608.1-5612.4"
+ wire width 25 $0$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1598
+ attribute \src "ls180.v:5608.1-5612.4"
+ wire width 25 $0$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1599
+ attribute \src "ls180.v:5623.1-5627.4"
+ wire width 4 $0$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1607
+ attribute \src "ls180.v:5623.1-5627.4"
+ wire width 10 $0$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1608
+ attribute \src "ls180.v:5623.1-5627.4"
+ wire width 10 $0$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1609
+ attribute \src "ls180.v:5640.1-5644.4"
+ wire width 4 $0$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1617
+ attribute \src "ls180.v:5640.1-5644.4"
+ wire width 10 $0$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1618
+ attribute \src "ls180.v:5640.1-5644.4"
+ wire width 10 $0$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1619
+ attribute \src "ls180.v:3964.1-3980.4"
wire width 2 $0\array_muxed0[1:0]
- attribute \src "ls180.v:3968.1-3984.4"
+ attribute \src "ls180.v:3981.1-3997.4"
wire width 13 $0\array_muxed1[12:0]
- attribute \src "ls180.v:3985.1-4001.4"
+ attribute \src "ls180.v:3998.1-4014.4"
wire $0\array_muxed2[0:0]
- attribute \src "ls180.v:4002.1-4018.4"
+ attribute \src "ls180.v:4015.1-4031.4"
wire $0\array_muxed3[0:0]
- attribute \src "ls180.v:4019.1-4035.4"
+ attribute \src "ls180.v:4032.1-4048.4"
wire $0\array_muxed4[0:0]
- attribute \src "ls180.v:4036.1-4052.4"
+ attribute \src "ls180.v:4049.1-4065.4"
wire $0\array_muxed5[0:0]
- attribute \src "ls180.v:4053.1-4069.4"
+ attribute \src "ls180.v:4066.1-4082.4"
wire $0\array_muxed6[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\cmd_consumed[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\converter0_counter[0:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\converter0_counter_subfragments_converter0_next_value[0:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\converter0_counter_subfragments_converter0_next_value_ce[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 64 $0\converter0_dat_r[63:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\converter0_skip[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\converter1_counter[0:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\converter1_counter_subfragments_converter1_next_value[0:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\converter1_counter_subfragments_converter1_next_value_ce[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 64 $0\converter1_dat_r[63:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\converter1_skip[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\converter_counter[0:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\converter_counter_subfragments_next_value[0:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\converter_counter_subfragments_next_value_ce[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\converter_dat_r[31:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\converter_skip[0:0]
- attribute \src "ls180.v:4180.1-4285.4"
+ attribute \src "ls180.v:4193.1-4298.4"
wire width 16 $0\dfi_p0_rddata[15:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\dfi_p0_rddata_valid[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
- wire width 30 $0\dummy[29:0]
- attribute \src "ls180.v:2905.1-2909.4"
+ attribute \src "ls180.v:4300.1-5506.4"
+ wire width 36 $0\dummy[35:0]
+ attribute \src "ls180.v:1506.1-1511.4"
+ wire width 3 $0\eint_tmp[2:0]
+ attribute \src "ls180.v:2918.1-2922.4"
wire width 2 $0\eventmanager_pending_w[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\eventmanager_re[0:0]
- attribute \src "ls180.v:2894.1-2898.4"
+ attribute \src "ls180.v:2907.1-2911.4"
wire width 2 $0\eventmanager_status_w[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\eventmanager_storage[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\gpio0_oe_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\gpio0_oe_storage[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\gpio0_out_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\gpio0_out_storage[7:0]
- attribute \src "ls180.v:2973.1-2983.4"
+ attribute \src "ls180.v:2986.1-2996.4"
wire width 8 $0\gpio0_pads_gpio0i[7:0]
- attribute \src "ls180.v:4180.1-4285.4"
+ attribute \src "ls180.v:4193.1-4298.4"
wire width 8 $0\gpio0_pads_gpio0o[7:0]
- attribute \src "ls180.v:4180.1-4285.4"
+ attribute \src "ls180.v:4193.1-4298.4"
wire width 8 $0\gpio0_pads_gpio0oe[7:0]
- attribute \src "ls180.v:4180.1-4285.4"
+ attribute \src "ls180.v:4193.1-4298.4"
wire width 8 $0\gpio0_status[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\gpio1_oe_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\gpio1_oe_storage[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\gpio1_out_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\gpio1_out_storage[7:0]
- attribute \src "ls180.v:2984.1-2994.4"
+ attribute \src "ls180.v:2997.1-3007.4"
wire width 8 $0\gpio1_pads_gpio1i[7:0]
- attribute \src "ls180.v:4180.1-4285.4"
+ attribute \src "ls180.v:4193.1-4298.4"
wire width 8 $0\gpio1_pads_gpio1o[7:0]
- attribute \src "ls180.v:4180.1-4285.4"
+ attribute \src "ls180.v:4193.1-4298.4"
wire width 8 $0\gpio1_pads_gpio1oe[7:0]
- attribute \src "ls180.v:4180.1-4285.4"
+ attribute \src "ls180.v:4193.1-4298.4"
wire width 8 $0\gpio1_status[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\i2c_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\i2c_storage[2:0]
- attribute \src "ls180.v:4176.1-4178.4"
+ attribute \src "ls180.v:4189.1-4191.4"
wire $0\int_rst[0:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\interface0_converted_interface_ack[0:0]
- attribute \src "ls180.v:208.5-208.46"
+ attribute \src "ls180.v:212.5-212.46"
wire $0\interface0_converted_interface_err[0:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\interface1_converted_interface_ack[0:0]
- attribute \src "ls180.v:223.5-223.46"
+ attribute \src "ls180.v:227.5-227.46"
wire $0\interface1_converted_interface_err[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\libresocsim_bus_errors[31:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 20 $0\libresocsim_count[19:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_en_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_en_storage[0:0]
- attribute \src "ls180.v:3151.1-3162.4"
+ attribute \src "ls180.v:3164.1-3175.4"
wire $0\libresocsim_error[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_eventmanager_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_eventmanager_storage[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\libresocsim_grant[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface0_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface1_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface2_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface3_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface4_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface5_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface6_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:2995.1-3013.4"
- wire width 16 $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0]
- attribute \src "ls180.v:3014.1-3032.4"
- wire width 16 $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire width 13 $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire width 2 $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire width 2 $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire width 16 $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0]
- attribute \src "ls180.v:118.5-118.68"
- wire $0\libresocsim_libresoc_constraintmanager_obj_spimaster_clk[0:0]
- attribute \src "ls180.v:120.5-120.69"
- wire $0\libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n[0:0]
- attribute \src "ls180.v:119.5-119.69"
- wire $0\libresocsim_libresoc_constraintmanager_obj_spimaster_mosi[0:0]
- attribute \src "ls180.v:123.5-123.62"
- wire $0\libresocsim_libresoc_constraintmanager_obj_uart_rx[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
- wire $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0]
- attribute \src "ls180.v:63.11-63.47"
+ attribute \src "ls180.v:3008.1-3026.4"
+ wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+ attribute \src "ls180.v:3027.1-3045.4"
+ wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire width 13 $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire width 16 $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
+ attribute \src "ls180.v:4193.1-4298.4"
+ wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
+ attribute \src "ls180.v:129.5-129.64"
+ wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
+ attribute \src "ls180.v:131.5-131.65"
+ wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
+ attribute \src "ls180.v:130.5-130.65"
+ wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
+ attribute \src "ls180.v:122.5-122.58"
+ wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
+ attribute \src "ls180.v:4300.1-5506.4"
+ wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+ attribute \src "ls180.v:65.11-65.47"
wire width 2 $0\libresocsim_libresoc_dbus_bte[1:0]
- attribute \src "ls180.v:62.11-62.47"
+ attribute \src "ls180.v:64.11-64.47"
wire width 3 $0\libresocsim_libresoc_dbus_cti[2:0]
- attribute \src "ls180.v:74.11-74.47"
+ attribute \src "ls180.v:76.11-76.47"
wire width 2 $0\libresocsim_libresoc_ibus_bte[1:0]
- attribute \src "ls180.v:73.11-73.47"
+ attribute \src "ls180.v:75.11-75.47"
wire width 3 $0\libresocsim_libresoc_ibus_cti[2:0]
- attribute \src "ls180.v:1507.1-1512.4"
+ attribute \src "ls180.v:1518.1-1525.4"
wire width 16 $0\libresocsim_libresoc_interrupt[15:0]
- attribute \src "ls180.v:103.11-103.50"
+ attribute \src "ls180.v:105.11-105.50"
wire width 2 $0\libresocsim_libresoc_jtag_wb_bte[1:0]
- attribute \src "ls180.v:102.11-102.50"
+ attribute \src "ls180.v:104.11-104.50"
wire width 3 $0\libresocsim_libresoc_jtag_wb_cti[2:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire width 30 $0\libresocsim_libresoc_xics_icp_adr[29:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\libresocsim_libresoc_xics_icp_cyc[0:0]
- attribute \src "ls180.v:1514.1-1524.4"
+ attribute \src "ls180.v:1527.1-1537.4"
wire width 32 $0\libresocsim_libresoc_xics_icp_dat_w[31:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire width 4 $0\libresocsim_libresoc_xics_icp_sel[3:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\libresocsim_libresoc_xics_icp_stb[0:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\libresocsim_libresoc_xics_icp_we[0:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire width 30 $0\libresocsim_libresoc_xics_ics_adr[29:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\libresocsim_libresoc_xics_ics_cyc[0:0]
- attribute \src "ls180.v:1574.1-1584.4"
+ attribute \src "ls180.v:1587.1-1597.4"
wire width 32 $0\libresocsim_libresoc_xics_ics_dat_w[31:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire width 4 $0\libresocsim_libresoc_xics_ics_sel[3:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\libresocsim_libresoc_xics_ics_stb[0:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\libresocsim_libresoc_xics_ics_we[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 14 $0\libresocsim_libresocsim_adr[13:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire width 14 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0]
- attribute \src "ls180.v:1069.5-1069.59"
+ attribute \src "ls180.v:1074.5-1074.59"
wire $0\libresocsim_libresocsim_converted_interface_ack[0:0]
- attribute \src "ls180.v:1065.12-1065.69"
+ attribute \src "ls180.v:1070.12-1070.69"
wire width 64 $0\libresocsim_libresocsim_converted_interface_dat_r[63:0]
- attribute \src "ls180.v:1073.5-1073.59"
+ attribute \src "ls180.v:1078.5-1078.59"
wire $0\libresocsim_libresocsim_converted_interface_err[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\libresocsim_libresocsim_dat_w[7:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire width 8 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_libresocsim_we[0:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire $0\libresocsim_libresocsim_wishbone_ack[0:0]
- attribute \src "ls180.v:1055.12-1055.56"
+ attribute \src "ls180.v:1060.12-1060.56"
wire width 30 $0\libresocsim_libresocsim_wishbone_adr[29:0]
- attribute \src "ls180.v:1059.5-1059.48"
+ attribute \src "ls180.v:1064.5-1064.48"
wire $0\libresocsim_libresocsim_wishbone_cyc[0:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire width 32 $0\libresocsim_libresocsim_wishbone_dat_r[31:0]
- attribute \src "ls180.v:1056.12-1056.58"
+ attribute \src "ls180.v:1061.12-1061.58"
wire width 32 $0\libresocsim_libresocsim_wishbone_dat_w[31:0]
- attribute \src "ls180.v:1058.11-1058.54"
+ attribute \src "ls180.v:1063.11-1063.54"
wire width 4 $0\libresocsim_libresocsim_wishbone_sel[3:0]
- attribute \src "ls180.v:1060.5-1060.48"
+ attribute \src "ls180.v:1065.5-1065.48"
wire $0\libresocsim_libresocsim_wishbone_stb[0:0]
- attribute \src "ls180.v:1062.5-1062.47"
+ attribute \src "ls180.v:1067.5-1067.47"
wire $0\libresocsim_libresocsim_wishbone_we[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_load_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\libresocsim_load_storage[31:0]
- attribute \src "ls180.v:3037.1-3073.4"
+ attribute \src "ls180.v:3050.1-3086.4"
wire width 2 $0\libresocsim_next_state[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_ram_bus_ack[0:0]
- attribute \src "ls180.v:151.5-151.35"
+ attribute \src "ls180.v:155.5-155.35"
wire $0\libresocsim_ram_bus_err[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_reload_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\libresocsim_reload_storage[31:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_reset_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_reset_storage[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_scratch_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\libresocsim_scratch_storage[31:0]
- attribute \src "ls180.v:3151.1-3162.4"
+ attribute \src "ls180.v:3164.1-3175.4"
wire $0\libresocsim_shared_ack[0:0]
- attribute \src "ls180.v:3151.1-3162.4"
+ attribute \src "ls180.v:3164.1-3175.4"
wire width 32 $0\libresocsim_shared_dat_r[31:0]
- attribute \src "ls180.v:3092.1-3100.4"
+ attribute \src "ls180.v:3105.1-3113.4"
wire width 6 $0\libresocsim_slave_sel[5:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 6 $0\libresocsim_slave_sel_r[5:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\libresocsim_state[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_update_value_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_update_value_storage[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\libresocsim_value[31:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\libresocsim_value_status[31:0]
- attribute \src "ls180.v:1695.1-1705.4"
+ attribute \src "ls180.v:1708.1-1718.4"
wire width 8 $0\libresocsim_we[7:0]
- attribute \src "ls180.v:1711.1-1716.4"
+ attribute \src "ls180.v:1724.1-1729.4"
wire $0\libresocsim_zero_clear[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_zero_old_trigger[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_zero_pending[0:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire width 30 $0\litedram_wb_adr[29:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\litedram_wb_cyc[0:0]
- attribute \src "ls180.v:2785.1-2795.4"
+ attribute \src "ls180.v:2798.1-2808.4"
wire width 16 $0\litedram_wb_dat_w[15:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire width 2 $0\litedram_wb_sel[1:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\litedram_wb_stb[0:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\litedram_wb_we[0:0]
- attribute \src "ls180.v:5491.1-5509.4"
+ attribute \src "ls180.v:5510.1-5528.4"
wire width 6 $0\memadr[5:0]
- attribute \src "ls180.v:5519.1-5537.4"
+ attribute \src "ls180.v:5538.1-5556.4"
wire width 4 $0\memadr_1[3:0]
- attribute \src "ls180.v:5547.1-5551.4"
+ attribute \src "ls180.v:5566.1-5570.4"
wire width 25 $0\memdat[24:0]
- attribute \src "ls180.v:5561.1-5565.4"
+ attribute \src "ls180.v:5580.1-5584.4"
wire width 25 $0\memdat_1[24:0]
- attribute \src "ls180.v:5575.1-5579.4"
+ attribute \src "ls180.v:5594.1-5598.4"
wire width 25 $0\memdat_2[24:0]
- attribute \src "ls180.v:5589.1-5593.4"
+ attribute \src "ls180.v:5608.1-5612.4"
wire width 25 $0\memdat_3[24:0]
- attribute \src "ls180.v:5604.1-5608.4"
+ attribute \src "ls180.v:5623.1-5627.4"
wire width 10 $0\memdat_4[9:0]
- attribute \src "ls180.v:5610.1-5613.4"
+ attribute \src "ls180.v:5629.1-5632.4"
wire width 10 $0\memdat_5[9:0]
- attribute \src "ls180.v:5621.1-5625.4"
+ attribute \src "ls180.v:5640.1-5644.4"
wire width 10 $0\memdat_6[9:0]
- attribute \src "ls180.v:5627.1-5630.4"
+ attribute \src "ls180.v:5646.1-5649.4"
wire width 10 $0\memdat_7[9:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\ram_bus_ram_bus_ack[0:0]
- attribute \src "ls180.v:193.5-193.31"
+ attribute \src "ls180.v:197.5-197.31"
wire $0\ram_bus_ram_bus_err[0:0]
- attribute \src "ls180.v:1720.1-1730.4"
+ attribute \src "ls180.v:1733.1-1743.4"
wire width 8 $0\ram_we[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\rddata_en[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\regs0[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\regs1[0:0]
- attribute \src "ls180.v:973.5-973.17"
+ attribute \src "ls180.v:977.5-977.17"
wire $0\reset[0:0]
- attribute \src "ls180.v:3437.1-3453.4"
+ attribute \src "ls180.v:3450.1-3466.4"
wire $0\rhs_array_muxed0[0:0]
- attribute \src "ls180.v:3658.1-3674.4"
+ attribute \src "ls180.v:3671.1-3687.4"
wire $0\rhs_array_muxed10[0:0]
- attribute \src "ls180.v:3675.1-3691.4"
+ attribute \src "ls180.v:3688.1-3704.4"
wire $0\rhs_array_muxed11[0:0]
- attribute \src "ls180.v:3743.1-3750.4"
+ attribute \src "ls180.v:3756.1-3763.4"
wire width 22 $0\rhs_array_muxed12[21:0]
- attribute \src "ls180.v:3751.1-3758.4"
+ attribute \src "ls180.v:3764.1-3771.4"
wire $0\rhs_array_muxed13[0:0]
- attribute \src "ls180.v:3759.1-3766.4"
+ attribute \src "ls180.v:3772.1-3779.4"
wire $0\rhs_array_muxed14[0:0]
- attribute \src "ls180.v:3767.1-3774.4"
+ attribute \src "ls180.v:3780.1-3787.4"
wire width 22 $0\rhs_array_muxed15[21:0]
- attribute \src "ls180.v:3775.1-3782.4"
+ attribute \src "ls180.v:3788.1-3795.4"
wire $0\rhs_array_muxed16[0:0]
- attribute \src "ls180.v:3783.1-3790.4"
+ attribute \src "ls180.v:3796.1-3803.4"
wire $0\rhs_array_muxed17[0:0]
- attribute \src "ls180.v:3791.1-3798.4"
+ attribute \src "ls180.v:3804.1-3811.4"
wire width 22 $0\rhs_array_muxed18[21:0]
- attribute \src "ls180.v:3799.1-3806.4"
+ attribute \src "ls180.v:3812.1-3819.4"
wire $0\rhs_array_muxed19[0:0]
- attribute \src "ls180.v:3454.1-3470.4"
+ attribute \src "ls180.v:3467.1-3483.4"
wire width 13 $0\rhs_array_muxed1[12:0]
- attribute \src "ls180.v:3807.1-3814.4"
+ attribute \src "ls180.v:3820.1-3827.4"
wire $0\rhs_array_muxed20[0:0]
- attribute \src "ls180.v:3815.1-3822.4"
+ attribute \src "ls180.v:3828.1-3835.4"
wire width 22 $0\rhs_array_muxed21[21:0]
- attribute \src "ls180.v:3823.1-3830.4"
+ attribute \src "ls180.v:3836.1-3843.4"
wire $0\rhs_array_muxed22[0:0]
- attribute \src "ls180.v:3831.1-3838.4"
+ attribute \src "ls180.v:3844.1-3851.4"
wire $0\rhs_array_muxed23[0:0]
- attribute \src "ls180.v:3839.1-3852.4"
+ attribute \src "ls180.v:3852.1-3865.4"
wire width 29 $0\rhs_array_muxed24[28:0]
- attribute \src "ls180.v:3853.1-3866.4"
+ attribute \src "ls180.v:3866.1-3879.4"
wire width 64 $0\rhs_array_muxed25[63:0]
- attribute \src "ls180.v:3867.1-3880.4"
+ attribute \src "ls180.v:3880.1-3893.4"
wire width 8 $0\rhs_array_muxed26[7:0]
- attribute \src "ls180.v:3881.1-3894.4"
+ attribute \src "ls180.v:3894.1-3907.4"
wire $0\rhs_array_muxed27[0:0]
- attribute \src "ls180.v:3895.1-3908.4"
+ attribute \src "ls180.v:3908.1-3921.4"
wire $0\rhs_array_muxed28[0:0]
- attribute \src "ls180.v:3909.1-3922.4"
+ attribute \src "ls180.v:3922.1-3935.4"
wire $0\rhs_array_muxed29[0:0]
- attribute \src "ls180.v:3471.1-3487.4"
+ attribute \src "ls180.v:3484.1-3500.4"
wire width 2 $0\rhs_array_muxed2[1:0]
- attribute \src "ls180.v:3923.1-3936.4"
+ attribute \src "ls180.v:3936.1-3949.4"
wire width 3 $0\rhs_array_muxed30[2:0]
- attribute \src "ls180.v:3937.1-3950.4"
+ attribute \src "ls180.v:3950.1-3963.4"
wire width 2 $0\rhs_array_muxed31[1:0]
- attribute \src "ls180.v:3488.1-3504.4"
+ attribute \src "ls180.v:3501.1-3517.4"
wire $0\rhs_array_muxed3[0:0]
- attribute \src "ls180.v:3505.1-3521.4"
+ attribute \src "ls180.v:3518.1-3534.4"
wire $0\rhs_array_muxed4[0:0]
- attribute \src "ls180.v:3522.1-3538.4"
+ attribute \src "ls180.v:3535.1-3551.4"
wire $0\rhs_array_muxed5[0:0]
- attribute \src "ls180.v:3590.1-3606.4"
+ attribute \src "ls180.v:3603.1-3619.4"
wire $0\rhs_array_muxed6[0:0]
- attribute \src "ls180.v:3607.1-3623.4"
+ attribute \src "ls180.v:3620.1-3636.4"
wire width 13 $0\rhs_array_muxed7[12:0]
- attribute \src "ls180.v:3624.1-3640.4"
+ attribute \src "ls180.v:3637.1-3653.4"
wire width 2 $0\rhs_array_muxed8[1:0]
- attribute \src "ls180.v:3641.1-3657.4"
+ attribute \src "ls180.v:3654.1-3670.4"
wire $0\rhs_array_muxed9[0:0]
- attribute \src "ls180.v:2899.1-2904.4"
+ attribute \src "ls180.v:2912.1-2917.4"
wire $0\rx_clear[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\rx_fifo_consume[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 5 $0\rx_fifo_level0[4:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\rx_fifo_produce[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\rx_fifo_readable[0:0]
- attribute \src "ls180.v:955.5-955.27"
+ attribute \src "ls180.v:959.5-959.27"
wire $0\rx_fifo_replace[0:0]
- attribute \src "ls180.v:2957.1-2964.4"
+ attribute \src "ls180.v:2970.1-2977.4"
wire width 4 $0\rx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\rx_old_trigger[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\rx_pending[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_address_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 13 $0\sdram_address_storage[12:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_baddress_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\sdram_baddress_storage[1:0]
- attribute \src "ls180.v:1942.1-1949.4"
+ attribute \src "ls180.v:1955.1-1962.4"
wire $0\sdram_bankmachine0_auto_precharge[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:428.5-428.59"
+ attribute \src "ls180.v:432.5-432.59"
wire $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:411.5-411.62"
+ attribute \src "ls180.v:415.5-415.62"
wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:412.5-412.61"
+ attribute \src "ls180.v:416.5-416.61"
wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:1964.1-1971.4"
+ attribute \src "ls180.v:1977.1-1984.4"
wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine0_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine0_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 22 $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:1931.1-1938.4"
+ attribute \src "ls180.v:1944.1-1951.4"
wire width 13 $0\sdram_bankmachine0_cmd_payload_a[12:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_cmd_payload_cas[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_cmd_payload_ras[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_cmd_payload_we[0:0]
- attribute \src "ls180.v:2629.1-2637.4"
+ attribute \src "ls180.v:2642.1-2650.4"
wire $0\sdram_bankmachine0_cmd_ready[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_cmd_valid[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_refresh_gnt[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_req_rdata_valid[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_req_wdata_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 13 $0\sdram_bankmachine0_row[12:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_row_close[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire $0\sdram_bankmachine0_row_open[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine0_row_opened[0:0]
- attribute \src "ls180.v:470.32-470.71"
+ attribute \src "ls180.v:474.32-474.71"
wire $0\sdram_bankmachine0_trascon_ready[0:0]
- attribute \src "ls180.v:468.32-468.70"
+ attribute \src "ls180.v:472.32-472.70"
wire $0\sdram_bankmachine0_trccon_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine0_twtpcon_count[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine0_twtpcon_ready[0:0]
- attribute \src "ls180.v:2099.1-2106.4"
+ attribute \src "ls180.v:2112.1-2119.4"
wire $0\sdram_bankmachine1_auto_precharge[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:510.5-510.59"
+ attribute \src "ls180.v:514.5-514.59"
wire $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:493.5-493.62"
+ attribute \src "ls180.v:497.5-497.62"
wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:494.5-494.61"
+ attribute \src "ls180.v:498.5-498.61"
wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:2121.1-2128.4"
+ attribute \src "ls180.v:2134.1-2141.4"
wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine1_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine1_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 22 $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:2088.1-2095.4"
+ attribute \src "ls180.v:2101.1-2108.4"
wire width 13 $0\sdram_bankmachine1_cmd_payload_a[12:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_cmd_payload_cas[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_cmd_payload_ras[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_cmd_payload_we[0:0]
- attribute \src "ls180.v:2638.1-2646.4"
+ attribute \src "ls180.v:2651.1-2659.4"
wire $0\sdram_bankmachine1_cmd_ready[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_cmd_valid[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_refresh_gnt[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_req_rdata_valid[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_req_wdata_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 13 $0\sdram_bankmachine1_row[12:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_row_close[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire $0\sdram_bankmachine1_row_open[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine1_row_opened[0:0]
- attribute \src "ls180.v:552.32-552.71"
+ attribute \src "ls180.v:556.32-556.71"
wire $0\sdram_bankmachine1_trascon_ready[0:0]
- attribute \src "ls180.v:550.32-550.70"
+ attribute \src "ls180.v:554.32-554.70"
wire $0\sdram_bankmachine1_trccon_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine1_twtpcon_count[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine1_twtpcon_ready[0:0]
- attribute \src "ls180.v:2256.1-2263.4"
+ attribute \src "ls180.v:2269.1-2276.4"
wire $0\sdram_bankmachine2_auto_precharge[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:592.5-592.59"
+ attribute \src "ls180.v:596.5-596.59"
wire $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:575.5-575.62"
+ attribute \src "ls180.v:579.5-579.62"
wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:576.5-576.61"
+ attribute \src "ls180.v:580.5-580.61"
wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:2278.1-2285.4"
+ attribute \src "ls180.v:2291.1-2298.4"
wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine2_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine2_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 22 $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:2245.1-2252.4"
+ attribute \src "ls180.v:2258.1-2265.4"
wire width 13 $0\sdram_bankmachine2_cmd_payload_a[12:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_cmd_payload_cas[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_cmd_payload_ras[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_cmd_payload_we[0:0]
- attribute \src "ls180.v:2647.1-2655.4"
+ attribute \src "ls180.v:2660.1-2668.4"
wire $0\sdram_bankmachine2_cmd_ready[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_cmd_valid[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_refresh_gnt[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_req_rdata_valid[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_req_wdata_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 13 $0\sdram_bankmachine2_row[12:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_row_close[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire $0\sdram_bankmachine2_row_open[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine2_row_opened[0:0]
- attribute \src "ls180.v:634.32-634.71"
+ attribute \src "ls180.v:638.32-638.71"
wire $0\sdram_bankmachine2_trascon_ready[0:0]
- attribute \src "ls180.v:632.32-632.70"
+ attribute \src "ls180.v:636.32-636.70"
wire $0\sdram_bankmachine2_trccon_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine2_twtpcon_count[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine2_twtpcon_ready[0:0]
- attribute \src "ls180.v:2413.1-2420.4"
+ attribute \src "ls180.v:2426.1-2433.4"
wire $0\sdram_bankmachine3_auto_precharge[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:674.5-674.59"
+ attribute \src "ls180.v:678.5-678.59"
wire $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
- attribute \src "ls180.v:657.5-657.62"
+ attribute \src "ls180.v:661.5-661.62"
wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
- attribute \src "ls180.v:658.5-658.61"
+ attribute \src "ls180.v:662.5-662.61"
wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
- attribute \src "ls180.v:2435.1-2442.4"
+ attribute \src "ls180.v:2448.1-2455.4"
wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine3_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine3_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 22 $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:2402.1-2409.4"
+ attribute \src "ls180.v:2415.1-2422.4"
wire width 13 $0\sdram_bankmachine3_cmd_payload_a[12:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_cmd_payload_cas[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_cmd_payload_ras[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_cmd_payload_we[0:0]
- attribute \src "ls180.v:2656.1-2664.4"
+ attribute \src "ls180.v:2669.1-2677.4"
wire $0\sdram_bankmachine3_cmd_ready[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_cmd_valid[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_refresh_gnt[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_req_rdata_valid[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_req_wdata_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 13 $0\sdram_bankmachine3_row[12:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_row_close[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire $0\sdram_bankmachine3_row_open[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine3_row_opened[0:0]
- attribute \src "ls180.v:716.32-716.71"
+ attribute \src "ls180.v:720.32-720.71"
wire $0\sdram_bankmachine3_trascon_ready[0:0]
- attribute \src "ls180.v:714.32-714.70"
+ attribute \src "ls180.v:718.32-718.70"
wire $0\sdram_bankmachine3_trccon_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_bankmachine3_twtpcon_count[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_bankmachine3_twtpcon_ready[0:0]
- attribute \src "ls180.v:2578.1-2583.4"
+ attribute \src "ls180.v:2591.1-2596.4"
wire $0\sdram_choose_cmd_cmd_payload_cas[0:0]
- attribute \src "ls180.v:2584.1-2589.4"
+ attribute \src "ls180.v:2597.1-2602.4"
wire $0\sdram_choose_cmd_cmd_payload_ras[0:0]
- attribute \src "ls180.v:2590.1-2595.4"
+ attribute \src "ls180.v:2603.1-2608.4"
wire $0\sdram_choose_cmd_cmd_payload_we[0:0]
- attribute \src "ls180.v:724.5-724.38"
+ attribute \src "ls180.v:728.5-728.38"
wire $0\sdram_choose_cmd_cmd_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\sdram_choose_cmd_grant[1:0]
- attribute \src "ls180.v:2564.1-2570.4"
+ attribute \src "ls180.v:2577.1-2583.4"
wire width 4 $0\sdram_choose_cmd_valids[3:0]
- attribute \src "ls180.v:722.5-722.43"
+ attribute \src "ls180.v:726.5-726.43"
wire $0\sdram_choose_cmd_want_activates[0:0]
- attribute \src "ls180.v:721.5-721.38"
+ attribute \src "ls180.v:725.5-725.38"
wire $0\sdram_choose_cmd_want_cmds[0:0]
- attribute \src "ls180.v:719.5-719.39"
+ attribute \src "ls180.v:723.5-723.39"
wire $0\sdram_choose_cmd_want_reads[0:0]
- attribute \src "ls180.v:720.5-720.40"
+ attribute \src "ls180.v:724.5-724.40"
wire $0\sdram_choose_cmd_want_writes[0:0]
- attribute \src "ls180.v:2611.1-2616.4"
+ attribute \src "ls180.v:2624.1-2629.4"
wire $0\sdram_choose_req_cmd_payload_cas[0:0]
- attribute \src "ls180.v:2617.1-2622.4"
+ attribute \src "ls180.v:2630.1-2635.4"
wire $0\sdram_choose_req_cmd_payload_ras[0:0]
- attribute \src "ls180.v:2623.1-2628.4"
+ attribute \src "ls180.v:2636.1-2641.4"
wire $0\sdram_choose_req_cmd_payload_we[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire $0\sdram_choose_req_cmd_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\sdram_choose_req_grant[1:0]
- attribute \src "ls180.v:2597.1-2603.4"
+ attribute \src "ls180.v:2610.1-2616.4"
wire width 4 $0\sdram_choose_req_valids[3:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire $0\sdram_choose_req_want_activates[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire $0\sdram_choose_req_want_reads[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire $0\sdram_choose_req_want_writes[0:0]
- attribute \src "ls180.v:4180.1-4285.4"
- wire $0\sdram_clock[0:0]
- attribute \src "ls180.v:1886.1-1916.4"
+ attribute \src "ls180.v:1899.1-1929.4"
wire $0\sdram_cmd_last[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 13 $0\sdram_cmd_payload_a[12:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\sdram_cmd_payload_ba[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_cmd_payload_cas[0:0]
- attribute \src "ls180.v:372.5-372.37"
+ attribute \src "ls180.v:376.5-376.37"
wire $0\sdram_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:373.5-373.38"
+ attribute \src "ls180.v:377.5-377.38"
wire $0\sdram_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_cmd_payload_ras[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_cmd_payload_we[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire $0\sdram_cmd_ready[0:0]
- attribute \src "ls180.v:1886.1-1916.4"
+ attribute \src "ls180.v:1899.1-1929.4"
wire $0\sdram_cmd_valid[0:0]
- attribute \src "ls180.v:308.5-308.33"
+ attribute \src "ls180.v:312.5-312.33"
wire $0\sdram_command_issue_w[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_command_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 6 $0\sdram_command_storage[5:0]
- attribute \src "ls180.v:357.5-357.30"
+ attribute \src "ls180.v:361.5-361.30"
wire $0\sdram_dfi_p0_act_n[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 13 $0\sdram_dfi_p0_address[12:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\sdram_dfi_p0_bank[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_dfi_p0_cas_n[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_dfi_p0_cs_n[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_dfi_p0_ras_n[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_dfi_p0_rddata_en[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_dfi_p0_we_n[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_dfi_p0_wrdata_en[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire $0\sdram_en0[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire $0\sdram_en1[0:0]
- attribute \src "ls180.v:2765.1-2778.4"
+ attribute \src "ls180.v:2778.1-2791.4"
wire width 16 $0\sdram_interface_wdata[15:0]
- attribute \src "ls180.v:2765.1-2778.4"
+ attribute \src "ls180.v:2778.1-2791.4"
wire width 2 $0\sdram_interface_wdata_we[1:0]
- attribute \src "ls180.v:258.5-258.31"
+ attribute \src "ls180.v:262.5-262.31"
wire $0\sdram_inti_p0_act_n[0:0]
- attribute \src "ls180.v:1827.1-1843.4"
+ attribute \src "ls180.v:1840.1-1856.4"
wire $0\sdram_inti_p0_cas_n[0:0]
- attribute \src "ls180.v:1827.1-1843.4"
+ attribute \src "ls180.v:1840.1-1856.4"
wire $0\sdram_inti_p0_cs_n[0:0]
- attribute \src "ls180.v:1827.1-1843.4"
+ attribute \src "ls180.v:1840.1-1856.4"
wire $0\sdram_inti_p0_ras_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire width 16 $0\sdram_inti_p0_rddata[15:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_inti_p0_rddata_valid[0:0]
- attribute \src "ls180.v:1827.1-1843.4"
+ attribute \src "ls180.v:1840.1-1856.4"
wire $0\sdram_inti_p0_we_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_act_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire width 13 $0\sdram_master_p0_address[12:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire width 2 $0\sdram_master_p0_bank[1:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_cas_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_cke[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_cs_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_odt[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_ras_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_rddata_en[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_reset_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_we_n[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire width 16 $0\sdram_master_p0_wrdata[15:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_master_p0_wrdata_en[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire width 2 $0\sdram_master_p0_wrdata_mask[1:0]
- attribute \src "ls180.v:755.12-755.31"
+ attribute \src "ls180.v:759.12-759.31"
wire width 13 $0\sdram_nop_a[12:0]
- attribute \src "ls180.v:756.11-756.30"
+ attribute \src "ls180.v:760.11-760.30"
wire width 2 $0\sdram_nop_ba[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_postponer_count[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_postponer_req_o[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_sequencer_count[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\sdram_sequencer_counter[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_sequencer_done1[0:0]
- attribute \src "ls180.v:1886.1-1916.4"
+ attribute \src "ls180.v:1899.1-1929.4"
wire $0\sdram_sequencer_start0[0:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire width 16 $0\sdram_slave_p0_rddata[15:0]
- attribute \src "ls180.v:1769.1-1823.4"
+ attribute \src "ls180.v:1782.1-1836.4"
wire $0\sdram_slave_p0_rddata_valid[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 16 $0\sdram_status[15:0]
- attribute \src "ls180.v:758.5-758.26"
+ attribute \src "ls180.v:762.5-762.26"
wire $0\sdram_steerer0[0:0]
- attribute \src "ls180.v:759.5-759.26"
+ attribute \src "ls180.v:763.5-763.26"
wire $0\sdram_steerer1[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire width 2 $0\sdram_steerer_sel[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\sdram_storage[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_tccdcon_count[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_tccdcon_ready[0:0]
- attribute \src "ls180.v:763.32-763.58"
+ attribute \src "ls180.v:767.32-767.58"
wire $0\sdram_tfawcon_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 5 $0\sdram_time0[4:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\sdram_time1[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 10 $0\sdram_timer_count1[9:0]
- attribute \src "ls180.v:761.32-761.58"
+ attribute \src "ls180.v:765.32-765.58"
wire $0\sdram_trrdcon_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\sdram_twtrcon_count[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_twtrcon_ready[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\sdram_wrdata_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 16 $0\sdram_wrdata_storage[15:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\socbushandler_converted_interface_ack[0:0]
- attribute \src "ls180.v:810.5-810.49"
+ attribute \src "ls180.v:814.5-814.49"
wire $0\socbushandler_converted_interface_err[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\socbushandler_counter[0:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\socbushandler_counter_subfragments_converter2_next_value[0:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 64 $0\socbushandler_dat_r[63:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\socbushandler_skip[0:0]
- attribute \src "ls180.v:1980.1-2073.4"
+ attribute \src "ls180.v:1993.1-2086.4"
wire width 3 $0\subfragments_bankmachine0_next_state[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\subfragments_bankmachine0_state[2:0]
- attribute \src "ls180.v:2137.1-2230.4"
+ attribute \src "ls180.v:2150.1-2243.4"
wire width 3 $0\subfragments_bankmachine1_next_state[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\subfragments_bankmachine1_state[2:0]
- attribute \src "ls180.v:2294.1-2387.4"
+ attribute \src "ls180.v:2307.1-2400.4"
wire width 3 $0\subfragments_bankmachine2_next_state[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\subfragments_bankmachine2_state[2:0]
- attribute \src "ls180.v:2451.1-2544.4"
+ attribute \src "ls180.v:2464.1-2557.4"
wire width 3 $0\subfragments_bankmachine3_next_state[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\subfragments_bankmachine3_state[2:0]
- attribute \src "ls180.v:1526.1-1572.4"
+ attribute \src "ls180.v:1539.1-1585.4"
wire $0\subfragments_converter0_next_state[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_converter0_state[0:0]
- attribute \src "ls180.v:1586.1-1632.4"
+ attribute \src "ls180.v:1599.1-1645.4"
wire $0\subfragments_converter1_next_state[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_converter1_state[0:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\subfragments_converter2_next_state[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_converter2_state[0:0]
- attribute \src "ls180.v:1038.5-1038.32"
+ attribute \src "ls180.v:1043.5-1043.32"
wire $0\subfragments_locked0[0:0]
- attribute \src "ls180.v:1039.5-1039.32"
+ attribute \src "ls180.v:1044.5-1044.32"
wire $0\subfragments_locked1[0:0]
- attribute \src "ls180.v:1040.5-1040.32"
+ attribute \src "ls180.v:1045.5-1045.32"
wire $0\subfragments_locked2[0:0]
- attribute \src "ls180.v:1041.5-1041.32"
+ attribute \src "ls180.v:1046.5-1046.32"
wire $0\subfragments_locked3[0:0]
- attribute \src "ls180.v:2669.1-2741.4"
+ attribute \src "ls180.v:2682.1-2754.4"
wire width 3 $0\subfragments_multiplexer_next_state[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 3 $0\subfragments_multiplexer_state[2:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_new_master_rdata_valid0[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_new_master_rdata_valid1[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_new_master_rdata_valid2[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_new_master_rdata_valid3[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_new_master_wdata_ready[0:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\subfragments_next_state[0:0]
- attribute \src "ls180.v:1886.1-1916.4"
+ attribute \src "ls180.v:1899.1-1929.4"
wire width 2 $0\subfragments_refresher_next_state[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 2 $0\subfragments_refresher_state[1:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\subfragments_state[0:0]
- attribute \src "ls180.v:3539.1-3555.4"
+ attribute \src "ls180.v:3552.1-3568.4"
wire $0\t_array_muxed0[0:0]
- attribute \src "ls180.v:3556.1-3572.4"
+ attribute \src "ls180.v:3569.1-3585.4"
wire $0\t_array_muxed1[0:0]
- attribute \src "ls180.v:3573.1-3589.4"
+ attribute \src "ls180.v:3586.1-3602.4"
wire $0\t_array_muxed2[0:0]
- attribute \src "ls180.v:3692.1-3708.4"
+ attribute \src "ls180.v:3705.1-3721.4"
wire $0\t_array_muxed3[0:0]
- attribute \src "ls180.v:3709.1-3725.4"
+ attribute \src "ls180.v:3722.1-3738.4"
wire $0\t_array_muxed4[0:0]
- attribute \src "ls180.v:3726.1-3742.4"
+ attribute \src "ls180.v:3739.1-3755.4"
wire $0\t_array_muxed5[0:0]
- attribute \src "ls180.v:2888.1-2893.4"
+ attribute \src "ls180.v:2901.1-2906.4"
wire $0\tx_clear[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\tx_fifo_consume[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 5 $0\tx_fifo_level0[4:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\tx_fifo_produce[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\tx_fifo_readable[0:0]
- attribute \src "ls180.v:918.5-918.27"
+ attribute \src "ls180.v:922.5-922.27"
wire $0\tx_fifo_replace[0:0]
- attribute \src "ls180.v:901.5-901.30"
+ attribute \src "ls180.v:905.5-905.30"
wire $0\tx_fifo_sink_first[0:0]
- attribute \src "ls180.v:902.5-902.29"
+ attribute \src "ls180.v:906.5-906.29"
wire $0\tx_fifo_sink_last[0:0]
- attribute \src "ls180.v:2927.1-2934.4"
+ attribute \src "ls180.v:2940.1-2947.4"
wire width 4 $0\tx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\tx_old_trigger[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\tx_pending[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\uart_phy_phase_accumulator_rx[31:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\uart_phy_phase_accumulator_tx[31:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_re[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\uart_phy_rx_bitcount[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_rx_busy[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_rx_r[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\uart_phy_rx_reg[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_sink_ready[0:0]
- attribute \src "ls180.v:846.5-846.33"
+ attribute \src "ls180.v:850.5-850.33"
wire $0\uart_phy_source_first[0:0]
- attribute \src "ls180.v:847.5-847.32"
+ attribute \src "ls180.v:851.5-851.32"
wire $0\uart_phy_source_last[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\uart_phy_source_payload_data[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_source_valid[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 32 $0\uart_phy_storage[31:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 4 $0\uart_phy_tx_bitcount[3:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_tx_busy[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire width 8 $0\uart_phy_tx_reg[7:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_uart_clk_rxen[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\uart_phy_uart_clk_txen[0:0]
- attribute \src "ls180.v:2797.1-2843.4"
+ attribute \src "ls180.v:2810.1-2856.4"
wire $0\wb_sdram_ack[0:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire width 30 $0\wb_sdram_adr[29:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\wb_sdram_cyc[0:0]
- attribute \src "ls180.v:1634.1-1644.4"
+ attribute \src "ls180.v:1647.1-1657.4"
wire width 32 $0\wb_sdram_dat_w[31:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire width 4 $0\wb_sdram_sel[3:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\wb_sdram_stb[0:0]
- attribute \src "ls180.v:1646.1-1692.4"
+ attribute \src "ls180.v:1659.1-1705.4"
wire $0\wb_sdram_we[0:0]
- attribute \src "ls180.v:4287.1-5487.4"
+ attribute \src "ls180.v:4300.1-5506.4"
wire $0\wdata_consumed[0:0]
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 6 $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506
- attribute \src "ls180.v:5491.1-5509.4"
- wire width 64 $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 4 $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556
- attribute \src "ls180.v:5519.1-5537.4"
- wire width 64 $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557
- attribute \src "ls180.v:5547.1-5551.4"
- wire width 3 $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563
- attribute \src "ls180.v:5547.1-5551.4"
- wire width 25 $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564
- attribute \src "ls180.v:5547.1-5551.4"
- wire width 25 $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565
- attribute \src "ls180.v:5561.1-5565.4"
- wire width 3 $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573
- attribute \src "ls180.v:5561.1-5565.4"
- wire width 25 $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574
- attribute \src "ls180.v:5561.1-5565.4"
- wire width 25 $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575
- attribute \src "ls180.v:5575.1-5579.4"
- wire width 3 $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583
- attribute \src "ls180.v:5575.1-5579.4"
- wire width 25 $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584
- attribute \src "ls180.v:5575.1-5579.4"
- wire width 25 $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585
- attribute \src "ls180.v:5589.1-5593.4"
- wire width 3 $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593
- attribute \src "ls180.v:5589.1-5593.4"
- wire width 25 $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594
- attribute \src "ls180.v:5589.1-5593.4"
- wire width 25 $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595
- attribute \src "ls180.v:5604.1-5608.4"
- wire width 4 $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603
- attribute \src "ls180.v:5604.1-5608.4"
- wire width 10 $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604
- attribute \src "ls180.v:5604.1-5608.4"
- wire width 10 $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605
- attribute \src "ls180.v:5621.1-5625.4"
- wire width 4 $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613
- attribute \src "ls180.v:5621.1-5625.4"
- wire width 10 $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614
- attribute \src "ls180.v:5621.1-5625.4"
- wire width 10 $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615
- attribute \src "ls180.v:1383.11-1383.30"
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 6 $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513
+ attribute \src "ls180.v:5510.1-5528.4"
+ wire width 64 $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 4 $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563
+ attribute \src "ls180.v:5538.1-5556.4"
+ wire width 64 $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564
+ attribute \src "ls180.v:5566.1-5570.4"
+ wire width 3 $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570
+ attribute \src "ls180.v:5566.1-5570.4"
+ wire width 25 $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571
+ attribute \src "ls180.v:5566.1-5570.4"
+ wire width 25 $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572
+ attribute \src "ls180.v:5580.1-5584.4"
+ wire width 3 $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580
+ attribute \src "ls180.v:5580.1-5584.4"
+ wire width 25 $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581
+ attribute \src "ls180.v:5580.1-5584.4"
+ wire width 25 $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582
+ attribute \src "ls180.v:5594.1-5598.4"
+ wire width 3 $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590
+ attribute \src "ls180.v:5594.1-5598.4"
+ wire width 25 $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591
+ attribute \src "ls180.v:5594.1-5598.4"
+ wire width 25 $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592
+ attribute \src "ls180.v:5608.1-5612.4"
+ wire width 3 $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600
+ attribute \src "ls180.v:5608.1-5612.4"
+ wire width 25 $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601
+ attribute \src "ls180.v:5608.1-5612.4"
+ wire width 25 $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602
+ attribute \src "ls180.v:5623.1-5627.4"
+ wire width 4 $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610
+ attribute \src "ls180.v:5623.1-5627.4"
+ wire width 10 $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611
+ attribute \src "ls180.v:5623.1-5627.4"
+ wire width 10 $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612
+ attribute \src "ls180.v:5640.1-5644.4"
+ wire width 4 $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620
+ attribute \src "ls180.v:5640.1-5644.4"
+ wire width 10 $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621
+ attribute \src "ls180.v:5640.1-5644.4"
+ wire width 10 $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622
+ attribute \src "ls180.v:1388.11-1388.30"
wire width 2 $1\array_muxed0[1:0]
- attribute \src "ls180.v:1384.12-1384.32"
+ attribute \src "ls180.v:1389.12-1389.32"
wire width 13 $1\array_muxed1[12:0]
- attribute \src "ls180.v:1385.5-1385.24"
+ attribute \src "ls180.v:1390.5-1390.24"
wire $1\array_muxed2[0:0]
- attribute \src "ls180.v:1386.5-1386.24"
+ attribute \src "ls180.v:1391.5-1391.24"
wire $1\array_muxed3[0:0]
- attribute \src "ls180.v:1387.5-1387.24"
+ attribute \src "ls180.v:1392.5-1392.24"
wire $1\array_muxed4[0:0]
- attribute \src "ls180.v:1388.5-1388.24"
+ attribute \src "ls180.v:1393.5-1393.24"
wire $1\array_muxed5[0:0]
- attribute \src "ls180.v:1389.5-1389.24"
+ attribute \src "ls180.v:1394.5-1394.24"
wire $1\array_muxed6[0:0]
- attribute \src "ls180.v:827.5-827.24"
+ attribute \src "ls180.v:831.5-831.24"
wire $1\cmd_consumed[0:0]
- attribute \src "ls180.v:210.5-210.30"
+ attribute \src "ls180.v:214.5-214.30"
wire $1\converter0_counter[0:0]
- attribute \src "ls180.v:1004.5-1004.65"
+ attribute \src "ls180.v:1009.5-1009.65"
wire $1\converter0_counter_subfragments_converter0_next_value[0:0]
- attribute \src "ls180.v:1005.5-1005.68"
+ attribute \src "ls180.v:1010.5-1010.68"
wire $1\converter0_counter_subfragments_converter0_next_value_ce[0:0]
- attribute \src "ls180.v:212.12-212.36"
+ attribute \src "ls180.v:216.12-216.36"
wire width 64 $1\converter0_dat_r[63:0]
- attribute \src "ls180.v:209.5-209.27"
+ attribute \src "ls180.v:213.5-213.27"
wire $1\converter0_skip[0:0]
- attribute \src "ls180.v:225.5-225.30"
+ attribute \src "ls180.v:229.5-229.30"
wire $1\converter1_counter[0:0]
- attribute \src "ls180.v:1008.5-1008.65"
+ attribute \src "ls180.v:1013.5-1013.65"
wire $1\converter1_counter_subfragments_converter1_next_value[0:0]
- attribute \src "ls180.v:1009.5-1009.68"
+ attribute \src "ls180.v:1014.5-1014.68"
wire $1\converter1_counter_subfragments_converter1_next_value_ce[0:0]
- attribute \src "ls180.v:227.12-227.36"
+ attribute \src "ls180.v:231.12-231.36"
wire width 64 $1\converter1_dat_r[63:0]
- attribute \src "ls180.v:224.5-224.27"
+ attribute \src "ls180.v:228.5-228.27"
wire $1\converter1_skip[0:0]
- attribute \src "ls180.v:824.5-824.29"
+ attribute \src "ls180.v:828.5-828.29"
wire $1\converter_counter[0:0]
- attribute \src "ls180.v:1049.5-1049.53"
+ attribute \src "ls180.v:1054.5-1054.53"
wire $1\converter_counter_subfragments_next_value[0:0]
- attribute \src "ls180.v:1050.5-1050.56"
+ attribute \src "ls180.v:1055.5-1055.56"
wire $1\converter_counter_subfragments_next_value_ce[0:0]
- attribute \src "ls180.v:826.12-826.35"
+ attribute \src "ls180.v:830.12-830.35"
wire width 32 $1\converter_dat_r[31:0]
- attribute \src "ls180.v:823.5-823.26"
+ attribute \src "ls180.v:827.5-827.26"
wire $1\converter_skip[0:0]
- attribute \src "ls180.v:246.12-246.33"
+ attribute \src "ls180.v:250.12-250.33"
wire width 16 $1\dfi_p0_rddata[15:0]
- attribute \src "ls180.v:247.5-247.31"
+ attribute \src "ls180.v:251.5-251.31"
wire $1\dfi_p0_rddata_valid[0:0]
- attribute \src "ls180.v:993.12-993.25"
- wire width 30 $1\dummy[29:0]
- attribute \src "ls180.v:882.11-882.40"
+ attribute \src "ls180.v:998.12-998.25"
+ wire width 36 $1\dummy[35:0]
+ attribute \src "ls180.v:996.11-996.26"
+ wire width 3 $1\eint_tmp[2:0]
+ attribute \src "ls180.v:886.11-886.40"
wire width 2 $1\eventmanager_pending_w[1:0]
- attribute \src "ls180.v:884.5-884.27"
+ attribute \src "ls180.v:888.5-888.27"
wire $1\eventmanager_re[0:0]
- attribute \src "ls180.v:878.11-878.39"
+ attribute \src "ls180.v:882.11-882.39"
wire width 2 $1\eventmanager_status_w[1:0]
- attribute \src "ls180.v:883.11-883.38"
+ attribute \src "ls180.v:887.11-887.38"
wire width 2 $1\eventmanager_storage[1:0]
- attribute \src "ls180.v:975.5-975.23"
+ attribute \src "ls180.v:979.5-979.23"
wire $1\gpio0_oe_re[0:0]
- attribute \src "ls180.v:974.11-974.34"
+ attribute \src "ls180.v:978.11-978.34"
wire width 8 $1\gpio0_oe_storage[7:0]
- attribute \src "ls180.v:979.5-979.24"
+ attribute \src "ls180.v:983.5-983.24"
wire $1\gpio0_out_re[0:0]
- attribute \src "ls180.v:978.11-978.35"
+ attribute \src "ls180.v:982.11-982.35"
wire width 8 $1\gpio0_out_storage[7:0]
- attribute \src "ls180.v:980.11-980.35"
+ attribute \src "ls180.v:984.11-984.35"
wire width 8 $1\gpio0_pads_gpio0i[7:0]
- attribute \src "ls180.v:981.11-981.35"
+ attribute \src "ls180.v:985.11-985.35"
wire width 8 $1\gpio0_pads_gpio0o[7:0]
- attribute \src "ls180.v:982.11-982.36"
+ attribute \src "ls180.v:986.11-986.36"
wire width 8 $1\gpio0_pads_gpio0oe[7:0]
- attribute \src "ls180.v:976.11-976.30"
+ attribute \src "ls180.v:980.11-980.30"
wire width 8 $1\gpio0_status[7:0]
- attribute \src "ls180.v:984.5-984.23"
+ attribute \src "ls180.v:988.5-988.23"
wire $1\gpio1_oe_re[0:0]
- attribute \src "ls180.v:983.11-983.34"
+ attribute \src "ls180.v:987.11-987.34"
wire width 8 $1\gpio1_oe_storage[7:0]
- attribute \src "ls180.v:988.5-988.24"
+ attribute \src "ls180.v:992.5-992.24"
wire $1\gpio1_out_re[0:0]
- attribute \src "ls180.v:987.11-987.35"
+ attribute \src "ls180.v:991.11-991.35"
wire width 8 $1\gpio1_out_storage[7:0]
- attribute \src "ls180.v:989.11-989.35"
+ attribute \src "ls180.v:993.11-993.35"
wire width 8 $1\gpio1_pads_gpio1i[7:0]
- attribute \src "ls180.v:990.11-990.35"
+ attribute \src "ls180.v:994.11-994.35"
wire width 8 $1\gpio1_pads_gpio1o[7:0]
- attribute \src "ls180.v:991.11-991.36"
+ attribute \src "ls180.v:995.11-995.36"
wire width 8 $1\gpio1_pads_gpio1oe[7:0]
- attribute \src "ls180.v:985.11-985.30"
+ attribute \src "ls180.v:989.11-989.30"
wire width 8 $1\gpio1_status[7:0]
- attribute \src "ls180.v:998.5-998.18"
+ attribute \src "ls180.v:1003.5-1003.18"
wire $1\i2c_re[0:0]
- attribute \src "ls180.v:997.11-997.29"
+ attribute \src "ls180.v:1002.11-1002.29"
wire width 3 $1\i2c_storage[2:0]
- attribute \src "ls180.v:231.5-231.19"
+ attribute \src "ls180.v:235.5-235.19"
wire $1\int_rst[0:0]
- attribute \src "ls180.v:204.5-204.46"
+ attribute \src "ls180.v:208.5-208.46"
wire $1\interface0_converted_interface_ack[0:0]
- attribute \src "ls180.v:219.5-219.46"
+ attribute \src "ls180.v:223.5-223.46"
wire $1\interface1_converted_interface_ack[0:0]
- attribute \src "ls180.v:51.12-51.42"
+ attribute \src "ls180.v:53.12-53.42"
wire width 32 $1\libresocsim_bus_errors[31:0]
- attribute \src "ls180.v:1092.12-1092.43"
+ attribute \src "ls180.v:1097.12-1097.43"
wire width 20 $1\libresocsim_count[19:0]
- attribute \src "ls180.v:161.5-161.29"
+ attribute \src "ls180.v:165.5-165.29"
wire $1\libresocsim_en_re[0:0]
- attribute \src "ls180.v:160.5-160.34"
+ attribute \src "ls180.v:164.5-164.34"
wire $1\libresocsim_en_storage[0:0]
- attribute \src "ls180.v:1089.5-1089.29"
+ attribute \src "ls180.v:1094.5-1094.29"
wire $1\libresocsim_error[0:0]
- attribute \src "ls180.v:181.5-181.39"
+ attribute \src "ls180.v:185.5-185.39"
wire $1\libresocsim_eventmanager_re[0:0]
- attribute \src "ls180.v:180.5-180.44"
+ attribute \src "ls180.v:184.5-184.44"
wire $1\libresocsim_eventmanager_storage[0:0]
- attribute \src "ls180.v:1086.11-1086.35"
+ attribute \src "ls180.v:1091.11-1091.35"
wire width 2 $1\libresocsim_grant[1:0]
- attribute \src "ls180.v:1096.11-1096.55"
+ attribute \src "ls180.v:1101.11-1101.55"
wire width 8 $1\libresocsim_interface0_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1137.11-1137.55"
+ attribute \src "ls180.v:1142.11-1142.55"
wire width 8 $1\libresocsim_interface1_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1154.11-1154.55"
+ attribute \src "ls180.v:1159.11-1159.55"
wire width 8 $1\libresocsim_interface2_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1171.11-1171.55"
+ attribute \src "ls180.v:1176.11-1176.55"
wire width 8 $1\libresocsim_interface3_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1184.11-1184.55"
+ attribute \src "ls180.v:1189.11-1189.55"
wire width 8 $1\libresocsim_interface4_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1225.11-1225.55"
+ attribute \src "ls180.v:1230.11-1230.55"
wire width 8 $1\libresocsim_interface5_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1290.11-1290.55"
+ attribute \src "ls180.v:1295.11-1295.55"
wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:1315.11-1315.55"
+ attribute \src "ls180.v:1320.11-1320.55"
wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:116.12-116.69"
- wire width 16 $1\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0]
- attribute \src "ls180.v:117.12-117.70"
- wire width 16 $1\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0]
- attribute \src "ls180.v:125.12-125.70"
- wire width 13 $1\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0]
- attribute \src "ls180.v:134.11-134.69"
- wire width 2 $1\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0]
- attribute \src "ls180.v:131.5-131.66"
- wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0]
- attribute \src "ls180.v:133.5-133.64"
- wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0]
- attribute \src "ls180.v:132.5-132.65"
- wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0]
- attribute \src "ls180.v:135.11-135.69"
- wire width 2 $1\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0]
- attribute \src "ls180.v:127.12-127.73"
- wire width 16 $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0]
- attribute \src "ls180.v:128.5-128.66"
- wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0]
- attribute \src "ls180.v:130.5-130.66"
- wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0]
- attribute \src "ls180.v:129.5-129.65"
- wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0]
- attribute \src "ls180.v:122.5-122.62"
- wire $1\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0]
- attribute \src "ls180.v:53.12-53.50"
+ attribute \src "ls180.v:124.12-124.65"
+ wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+ attribute \src "ls180.v:125.12-125.66"
+ wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+ attribute \src "ls180.v:133.12-133.66"
+ wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
+ attribute \src "ls180.v:142.11-142.65"
+ wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
+ attribute \src "ls180.v:139.5-139.62"
+ wire $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
+ attribute \src "ls180.v:141.5-141.60"
+ wire $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
+ attribute \src "ls180.v:144.5-144.62"
+ wire $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
+ attribute \src "ls180.v:140.5-140.61"
+ wire $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
+ attribute \src "ls180.v:143.11-143.65"
+ wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
+ attribute \src "ls180.v:135.12-135.69"
+ wire width 16 $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
+ attribute \src "ls180.v:136.5-136.62"
+ wire $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
+ attribute \src "ls180.v:138.5-138.62"
+ wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
+ attribute \src "ls180.v:137.5-137.61"
+ wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
+ attribute \src "ls180.v:121.5-121.58"
+ wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+ attribute \src "ls180.v:55.12-55.50"
wire width 16 $1\libresocsim_libresoc_interrupt[15:0]
- attribute \src "ls180.v:76.12-76.53"
+ attribute \src "ls180.v:78.12-78.53"
wire width 30 $1\libresocsim_libresoc_xics_icp_adr[29:0]
- attribute \src "ls180.v:80.5-80.45"
+ attribute \src "ls180.v:82.5-82.45"
wire $1\libresocsim_libresoc_xics_icp_cyc[0:0]
- attribute \src "ls180.v:77.12-77.55"
+ attribute \src "ls180.v:79.12-79.55"
wire width 32 $1\libresocsim_libresoc_xics_icp_dat_w[31:0]
- attribute \src "ls180.v:79.11-79.51"
+ attribute \src "ls180.v:81.11-81.51"
wire width 4 $1\libresocsim_libresoc_xics_icp_sel[3:0]
- attribute \src "ls180.v:81.5-81.45"
+ attribute \src "ls180.v:83.5-83.45"
wire $1\libresocsim_libresoc_xics_icp_stb[0:0]
- attribute \src "ls180.v:83.5-83.44"
+ attribute \src "ls180.v:85.5-85.44"
wire $1\libresocsim_libresoc_xics_icp_we[0:0]
- attribute \src "ls180.v:85.12-85.53"
+ attribute \src "ls180.v:87.12-87.53"
wire width 30 $1\libresocsim_libresoc_xics_ics_adr[29:0]
- attribute \src "ls180.v:89.5-89.45"
+ attribute \src "ls180.v:91.5-91.45"
wire $1\libresocsim_libresoc_xics_ics_cyc[0:0]
- attribute \src "ls180.v:86.12-86.55"
+ attribute \src "ls180.v:88.12-88.55"
wire width 32 $1\libresocsim_libresoc_xics_ics_dat_w[31:0]
- attribute \src "ls180.v:88.11-88.51"
+ attribute \src "ls180.v:90.11-90.51"
wire width 4 $1\libresocsim_libresoc_xics_ics_sel[3:0]
- attribute \src "ls180.v:90.5-90.45"
+ attribute \src "ls180.v:92.5-92.45"
wire $1\libresocsim_libresoc_xics_ics_stb[0:0]
- attribute \src "ls180.v:92.5-92.44"
+ attribute \src "ls180.v:94.5-94.44"
wire $1\libresocsim_libresoc_xics_ics_we[0:0]
- attribute \src "ls180.v:1051.12-1051.47"
+ attribute \src "ls180.v:1056.12-1056.47"
wire width 14 $1\libresocsim_libresocsim_adr[13:0]
- attribute \src "ls180.v:1341.12-1341.71"
+ attribute \src "ls180.v:1346.12-1346.71"
wire width 14 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0]
- attribute \src "ls180.v:1342.5-1342.66"
+ attribute \src "ls180.v:1347.5-1347.66"
wire $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0]
- attribute \src "ls180.v:1053.11-1053.47"
+ attribute \src "ls180.v:1058.11-1058.47"
wire width 8 $1\libresocsim_libresocsim_dat_w[7:0]
- attribute \src "ls180.v:1339.11-1339.71"
+ attribute \src "ls180.v:1344.11-1344.71"
wire width 8 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0]
- attribute \src "ls180.v:1340.5-1340.68"
+ attribute \src "ls180.v:1345.5-1345.68"
wire $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0]
- attribute \src "ls180.v:1052.5-1052.38"
+ attribute \src "ls180.v:1057.5-1057.38"
wire $1\libresocsim_libresocsim_we[0:0]
- attribute \src "ls180.v:1343.5-1343.62"
+ attribute \src "ls180.v:1348.5-1348.62"
wire $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
- attribute \src "ls180.v:1344.5-1344.65"
+ attribute \src "ls180.v:1349.5-1349.65"
wire $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
- attribute \src "ls180.v:1061.5-1061.48"
+ attribute \src "ls180.v:1066.5-1066.48"
wire $1\libresocsim_libresocsim_wishbone_ack[0:0]
- attribute \src "ls180.v:1057.12-1057.58"
+ attribute \src "ls180.v:1062.12-1062.58"
wire width 32 $1\libresocsim_libresocsim_wishbone_dat_r[31:0]
- attribute \src "ls180.v:157.5-157.31"
+ attribute \src "ls180.v:161.5-161.31"
wire $1\libresocsim_load_re[0:0]
- attribute \src "ls180.v:156.12-156.44"
+ attribute \src "ls180.v:160.12-160.44"
wire width 32 $1\libresocsim_load_storage[31:0]
- attribute \src "ls180.v:1338.11-1338.40"
+ attribute \src "ls180.v:1343.11-1343.40"
wire width 2 $1\libresocsim_next_state[1:0]
- attribute \src "ls180.v:147.5-147.35"
+ attribute \src "ls180.v:151.5-151.35"
wire $1\libresocsim_ram_bus_ack[0:0]
- attribute \src "ls180.v:159.5-159.33"
+ attribute \src "ls180.v:163.5-163.33"
wire $1\libresocsim_reload_re[0:0]
- attribute \src "ls180.v:158.12-158.46"
+ attribute \src "ls180.v:162.12-162.46"
wire width 32 $1\libresocsim_reload_storage[31:0]
- attribute \src "ls180.v:44.5-44.32"
+ attribute \src "ls180.v:46.5-46.32"
wire $1\libresocsim_reset_re[0:0]
- attribute \src "ls180.v:43.5-43.37"
+ attribute \src "ls180.v:45.5-45.37"
wire $1\libresocsim_reset_storage[0:0]
- attribute \src "ls180.v:46.5-46.34"
+ attribute \src "ls180.v:48.5-48.34"
wire $1\libresocsim_scratch_re[0:0]
- attribute \src "ls180.v:45.12-45.55"
+ attribute \src "ls180.v:47.12-47.55"
wire width 32 $1\libresocsim_scratch_storage[31:0]
- attribute \src "ls180.v:1080.5-1080.34"
+ attribute \src "ls180.v:1085.5-1085.34"
wire $1\libresocsim_shared_ack[0:0]
- attribute \src "ls180.v:1076.12-1076.44"
+ attribute \src "ls180.v:1081.12-1081.44"
wire width 32 $1\libresocsim_shared_dat_r[31:0]
- attribute \src "ls180.v:1087.11-1087.39"
+ attribute \src "ls180.v:1092.11-1092.39"
wire width 6 $1\libresocsim_slave_sel[5:0]
- attribute \src "ls180.v:1088.11-1088.41"
+ attribute \src "ls180.v:1093.11-1093.41"
wire width 6 $1\libresocsim_slave_sel_r[5:0]
- attribute \src "ls180.v:1337.11-1337.35"
+ attribute \src "ls180.v:1342.11-1342.35"
wire width 2 $1\libresocsim_state[1:0]
- attribute \src "ls180.v:163.5-163.39"
+ attribute \src "ls180.v:167.5-167.39"
wire $1\libresocsim_update_value_re[0:0]
- attribute \src "ls180.v:162.5-162.44"
+ attribute \src "ls180.v:166.5-166.44"
wire $1\libresocsim_update_value_storage[0:0]
- attribute \src "ls180.v:182.12-182.37"
+ attribute \src "ls180.v:186.12-186.37"
wire width 32 $1\libresocsim_value[31:0]
- attribute \src "ls180.v:164.12-164.44"
+ attribute \src "ls180.v:168.12-168.44"
wire width 32 $1\libresocsim_value_status[31:0]
- attribute \src "ls180.v:154.11-154.32"
+ attribute \src "ls180.v:158.11-158.32"
wire width 8 $1\libresocsim_we[7:0]
- attribute \src "ls180.v:170.5-170.34"
+ attribute \src "ls180.v:174.5-174.34"
wire $1\libresocsim_zero_clear[0:0]
- attribute \src "ls180.v:171.5-171.40"
+ attribute \src "ls180.v:175.5-175.40"
wire $1\libresocsim_zero_old_trigger[0:0]
- attribute \src "ls180.v:168.5-168.36"
+ attribute \src "ls180.v:172.5-172.36"
wire $1\libresocsim_zero_pending[0:0]
- attribute \src "ls180.v:815.12-815.35"
+ attribute \src "ls180.v:819.12-819.35"
wire width 30 $1\litedram_wb_adr[29:0]
- attribute \src "ls180.v:819.5-819.27"
+ attribute \src "ls180.v:823.5-823.27"
wire $1\litedram_wb_cyc[0:0]
- attribute \src "ls180.v:816.12-816.37"
+ attribute \src "ls180.v:820.12-820.37"
wire width 16 $1\litedram_wb_dat_w[15:0]
- attribute \src "ls180.v:818.11-818.33"
+ attribute \src "ls180.v:822.11-822.33"
wire width 2 $1\litedram_wb_sel[1:0]
- attribute \src "ls180.v:820.5-820.27"
+ attribute \src "ls180.v:824.5-824.27"
wire $1\litedram_wb_stb[0:0]
- attribute \src "ls180.v:822.5-822.26"
+ attribute \src "ls180.v:826.5-826.26"
wire $1\litedram_wb_we[0:0]
- attribute \src "ls180.v:189.5-189.31"
+ attribute \src "ls180.v:193.5-193.31"
wire $1\ram_bus_ram_bus_ack[0:0]
- attribute \src "ls180.v:196.11-196.24"
+ attribute \src "ls180.v:200.11-200.24"
wire width 8 $1\ram_we[7:0]
- attribute \src "ls180.v:248.11-248.27"
+ attribute \src "ls180.v:252.11-252.27"
wire width 3 $1\rddata_en[2:0]
- attribute \src "ls180.v:1446.32-1446.44"
+ attribute \src "ls180.v:1451.32-1451.44"
wire $1\regs0[0:0]
- attribute \src "ls180.v:1447.32-1447.44"
+ attribute \src "ls180.v:1452.32-1452.44"
wire $1\regs1[0:0]
- attribute \src "ls180.v:1345.5-1345.28"
+ attribute \src "ls180.v:1350.5-1350.28"
wire $1\rhs_array_muxed0[0:0]
- attribute \src "ls180.v:1358.5-1358.29"
+ attribute \src "ls180.v:1363.5-1363.29"
wire $1\rhs_array_muxed10[0:0]
- attribute \src "ls180.v:1359.5-1359.29"
+ attribute \src "ls180.v:1364.5-1364.29"
wire $1\rhs_array_muxed11[0:0]
- attribute \src "ls180.v:1363.12-1363.37"
+ attribute \src "ls180.v:1368.12-1368.37"
wire width 22 $1\rhs_array_muxed12[21:0]
- attribute \src "ls180.v:1364.5-1364.29"
+ attribute \src "ls180.v:1369.5-1369.29"
wire $1\rhs_array_muxed13[0:0]
- attribute \src "ls180.v:1365.5-1365.29"
+ attribute \src "ls180.v:1370.5-1370.29"
wire $1\rhs_array_muxed14[0:0]
- attribute \src "ls180.v:1366.12-1366.37"
+ attribute \src "ls180.v:1371.12-1371.37"
wire width 22 $1\rhs_array_muxed15[21:0]
- attribute \src "ls180.v:1367.5-1367.29"
+ attribute \src "ls180.v:1372.5-1372.29"
wire $1\rhs_array_muxed16[0:0]
- attribute \src "ls180.v:1368.5-1368.29"
+ attribute \src "ls180.v:1373.5-1373.29"
wire $1\rhs_array_muxed17[0:0]
- attribute \src "ls180.v:1369.12-1369.37"
+ attribute \src "ls180.v:1374.12-1374.37"
wire width 22 $1\rhs_array_muxed18[21:0]
- attribute \src "ls180.v:1370.5-1370.29"
+ attribute \src "ls180.v:1375.5-1375.29"
wire $1\rhs_array_muxed19[0:0]
- attribute \src "ls180.v:1346.12-1346.36"
+ attribute \src "ls180.v:1351.12-1351.36"
wire width 13 $1\rhs_array_muxed1[12:0]
- attribute \src "ls180.v:1371.5-1371.29"
+ attribute \src "ls180.v:1376.5-1376.29"
wire $1\rhs_array_muxed20[0:0]
- attribute \src "ls180.v:1372.12-1372.37"
+ attribute \src "ls180.v:1377.12-1377.37"
wire width 22 $1\rhs_array_muxed21[21:0]
- attribute \src "ls180.v:1373.5-1373.29"
+ attribute \src "ls180.v:1378.5-1378.29"
wire $1\rhs_array_muxed22[0:0]
- attribute \src "ls180.v:1374.5-1374.29"
+ attribute \src "ls180.v:1379.5-1379.29"
wire $1\rhs_array_muxed23[0:0]
- attribute \src "ls180.v:1375.12-1375.37"
+ attribute \src "ls180.v:1380.12-1380.37"
wire width 29 $1\rhs_array_muxed24[28:0]
- attribute \src "ls180.v:1376.12-1376.37"
+ attribute \src "ls180.v:1381.12-1381.37"
wire width 64 $1\rhs_array_muxed25[63:0]
- attribute \src "ls180.v:1377.11-1377.35"
+ attribute \src "ls180.v:1382.11-1382.35"
wire width 8 $1\rhs_array_muxed26[7:0]
- attribute \src "ls180.v:1378.5-1378.29"
+ attribute \src "ls180.v:1383.5-1383.29"
wire $1\rhs_array_muxed27[0:0]
- attribute \src "ls180.v:1379.5-1379.29"
+ attribute \src "ls180.v:1384.5-1384.29"
wire $1\rhs_array_muxed28[0:0]
- attribute \src "ls180.v:1380.5-1380.29"
+ attribute \src "ls180.v:1385.5-1385.29"
wire $1\rhs_array_muxed29[0:0]
- attribute \src "ls180.v:1347.11-1347.34"
+ attribute \src "ls180.v:1352.11-1352.34"
wire width 2 $1\rhs_array_muxed2[1:0]
- attribute \src "ls180.v:1381.11-1381.35"
+ attribute \src "ls180.v:1386.11-1386.35"
wire width 3 $1\rhs_array_muxed30[2:0]
- attribute \src "ls180.v:1382.11-1382.35"
+ attribute \src "ls180.v:1387.11-1387.35"
wire width 2 $1\rhs_array_muxed31[1:0]
- attribute \src "ls180.v:1348.5-1348.28"
+ attribute \src "ls180.v:1353.5-1353.28"
wire $1\rhs_array_muxed3[0:0]
- attribute \src "ls180.v:1349.5-1349.28"
+ attribute \src "ls180.v:1354.5-1354.28"
wire $1\rhs_array_muxed4[0:0]
- attribute \src "ls180.v:1350.5-1350.28"
+ attribute \src "ls180.v:1355.5-1355.28"
wire $1\rhs_array_muxed5[0:0]
- attribute \src "ls180.v:1354.5-1354.28"
+ attribute \src "ls180.v:1359.5-1359.28"
wire $1\rhs_array_muxed6[0:0]
- attribute \src "ls180.v:1355.12-1355.36"
+ attribute \src "ls180.v:1360.12-1360.36"
wire width 13 $1\rhs_array_muxed7[12:0]
- attribute \src "ls180.v:1356.11-1356.34"
+ attribute \src "ls180.v:1361.11-1361.34"
wire width 2 $1\rhs_array_muxed8[1:0]
- attribute \src "ls180.v:1357.5-1357.28"
+ attribute \src "ls180.v:1362.5-1362.28"
wire $1\rhs_array_muxed9[0:0]
- attribute \src "ls180.v:873.5-873.20"
+ attribute \src "ls180.v:877.5-877.20"
wire $1\rx_clear[0:0]
- attribute \src "ls180.v:957.11-957.33"
+ attribute \src "ls180.v:961.11-961.33"
wire width 4 $1\rx_fifo_consume[3:0]
- attribute \src "ls180.v:954.11-954.32"
+ attribute \src "ls180.v:958.11-958.32"
wire width 5 $1\rx_fifo_level0[4:0]
- attribute \src "ls180.v:956.11-956.33"
+ attribute \src "ls180.v:960.11-960.33"
wire width 4 $1\rx_fifo_produce[3:0]
- attribute \src "ls180.v:947.5-947.28"
+ attribute \src "ls180.v:951.5-951.28"
wire $1\rx_fifo_readable[0:0]
- attribute \src "ls180.v:958.11-958.36"
+ attribute \src "ls180.v:962.11-962.36"
wire width 4 $1\rx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:874.5-874.26"
+ attribute \src "ls180.v:878.5-878.26"
wire $1\rx_old_trigger[0:0]
- attribute \src "ls180.v:871.5-871.22"
+ attribute \src "ls180.v:875.5-875.22"
wire $1\rx_pending[0:0]
- attribute \src "ls180.v:310.5-310.28"
+ attribute \src "ls180.v:314.5-314.28"
wire $1\sdram_address_re[0:0]
- attribute \src "ls180.v:309.12-309.41"
+ attribute \src "ls180.v:313.12-313.41"
wire width 13 $1\sdram_address_storage[12:0]
- attribute \src "ls180.v:312.5-312.29"
+ attribute \src "ls180.v:316.5-316.29"
wire $1\sdram_baddress_re[0:0]
- attribute \src "ls180.v:311.11-311.40"
+ attribute \src "ls180.v:315.11-315.40"
wire width 2 $1\sdram_baddress_storage[1:0]
- attribute \src "ls180.v:408.5-408.45"
+ attribute \src "ls180.v:412.5-412.45"
wire $1\sdram_bankmachine0_auto_precharge[0:0]
- attribute \src "ls180.v:430.11-430.65"
+ attribute \src "ls180.v:434.11-434.65"
wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:427.11-427.63"
+ attribute \src "ls180.v:431.11-431.63"
wire width 4 $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:429.11-429.65"
+ attribute \src "ls180.v:433.11-433.65"
wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:431.11-431.68"
+ attribute \src "ls180.v:435.11-435.68"
wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:454.5-454.54"
+ attribute \src "ls180.v:458.5-458.54"
wire $1\sdram_bankmachine0_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:455.5-455.53"
+ attribute \src "ls180.v:459.5-459.53"
wire $1\sdram_bankmachine0_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:457.12-457.69"
+ attribute \src "ls180.v:461.12-461.69"
wire width 22 $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:456.5-456.59"
+ attribute \src "ls180.v:460.5-460.59"
wire $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:452.5-452.54"
+ attribute \src "ls180.v:456.5-456.54"
wire $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:400.12-400.52"
+ attribute \src "ls180.v:404.12-404.52"
wire width 13 $1\sdram_bankmachine0_cmd_payload_a[12:0]
- attribute \src "ls180.v:402.5-402.46"
+ attribute \src "ls180.v:406.5-406.46"
wire $1\sdram_bankmachine0_cmd_payload_cas[0:0]
- attribute \src "ls180.v:405.5-405.49"
+ attribute \src "ls180.v:409.5-409.49"
wire $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:406.5-406.50"
+ attribute \src "ls180.v:410.5-410.50"
wire $1\sdram_bankmachine0_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:407.5-407.51"
+ attribute \src "ls180.v:411.5-411.51"
wire $1\sdram_bankmachine0_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:403.5-403.46"
+ attribute \src "ls180.v:407.5-407.46"
wire $1\sdram_bankmachine0_cmd_payload_ras[0:0]
- attribute \src "ls180.v:404.5-404.45"
+ attribute \src "ls180.v:408.5-408.45"
wire $1\sdram_bankmachine0_cmd_payload_we[0:0]
- attribute \src "ls180.v:399.5-399.40"
+ attribute \src "ls180.v:403.5-403.40"
wire $1\sdram_bankmachine0_cmd_ready[0:0]
- attribute \src "ls180.v:398.5-398.40"
+ attribute \src "ls180.v:402.5-402.40"
wire $1\sdram_bankmachine0_cmd_valid[0:0]
- attribute \src "ls180.v:397.5-397.42"
+ attribute \src "ls180.v:401.5-401.42"
wire $1\sdram_bankmachine0_refresh_gnt[0:0]
- attribute \src "ls180.v:395.5-395.46"
+ attribute \src "ls180.v:399.5-399.46"
wire $1\sdram_bankmachine0_req_rdata_valid[0:0]
- attribute \src "ls180.v:394.5-394.46"
+ attribute \src "ls180.v:398.5-398.46"
wire $1\sdram_bankmachine0_req_wdata_ready[0:0]
- attribute \src "ls180.v:458.12-458.42"
+ attribute \src "ls180.v:462.12-462.42"
wire width 13 $1\sdram_bankmachine0_row[12:0]
- attribute \src "ls180.v:462.5-462.40"
+ attribute \src "ls180.v:466.5-466.40"
wire $1\sdram_bankmachine0_row_close[0:0]
- attribute \src "ls180.v:463.5-463.49"
+ attribute \src "ls180.v:467.5-467.49"
wire $1\sdram_bankmachine0_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:461.5-461.39"
+ attribute \src "ls180.v:465.5-465.39"
wire $1\sdram_bankmachine0_row_open[0:0]
- attribute \src "ls180.v:459.5-459.41"
+ attribute \src "ls180.v:463.5-463.41"
wire $1\sdram_bankmachine0_row_opened[0:0]
- attribute \src "ls180.v:466.11-466.50"
+ attribute \src "ls180.v:470.11-470.50"
wire width 3 $1\sdram_bankmachine0_twtpcon_count[2:0]
- attribute \src "ls180.v:465.32-465.71"
+ attribute \src "ls180.v:469.32-469.71"
wire $1\sdram_bankmachine0_twtpcon_ready[0:0]
- attribute \src "ls180.v:490.5-490.45"
+ attribute \src "ls180.v:494.5-494.45"
wire $1\sdram_bankmachine1_auto_precharge[0:0]
- attribute \src "ls180.v:512.11-512.65"
+ attribute \src "ls180.v:516.11-516.65"
wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:509.11-509.63"
+ attribute \src "ls180.v:513.11-513.63"
wire width 4 $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:511.11-511.65"
+ attribute \src "ls180.v:515.11-515.65"
wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:513.11-513.68"
+ attribute \src "ls180.v:517.11-517.68"
wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:536.5-536.54"
+ attribute \src "ls180.v:540.5-540.54"
wire $1\sdram_bankmachine1_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:537.5-537.53"
+ attribute \src "ls180.v:541.5-541.53"
wire $1\sdram_bankmachine1_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:539.12-539.69"
+ attribute \src "ls180.v:543.12-543.69"
wire width 22 $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:538.5-538.59"
+ attribute \src "ls180.v:542.5-542.59"
wire $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:534.5-534.54"
+ attribute \src "ls180.v:538.5-538.54"
wire $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:482.12-482.52"
+ attribute \src "ls180.v:486.12-486.52"
wire width 13 $1\sdram_bankmachine1_cmd_payload_a[12:0]
- attribute \src "ls180.v:484.5-484.46"
+ attribute \src "ls180.v:488.5-488.46"
wire $1\sdram_bankmachine1_cmd_payload_cas[0:0]
- attribute \src "ls180.v:487.5-487.49"
+ attribute \src "ls180.v:491.5-491.49"
wire $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:488.5-488.50"
+ attribute \src "ls180.v:492.5-492.50"
wire $1\sdram_bankmachine1_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:489.5-489.51"
+ attribute \src "ls180.v:493.5-493.51"
wire $1\sdram_bankmachine1_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:485.5-485.46"
+ attribute \src "ls180.v:489.5-489.46"
wire $1\sdram_bankmachine1_cmd_payload_ras[0:0]
- attribute \src "ls180.v:486.5-486.45"
+ attribute \src "ls180.v:490.5-490.45"
wire $1\sdram_bankmachine1_cmd_payload_we[0:0]
- attribute \src "ls180.v:481.5-481.40"
+ attribute \src "ls180.v:485.5-485.40"
wire $1\sdram_bankmachine1_cmd_ready[0:0]
- attribute \src "ls180.v:480.5-480.40"
+ attribute \src "ls180.v:484.5-484.40"
wire $1\sdram_bankmachine1_cmd_valid[0:0]
- attribute \src "ls180.v:479.5-479.42"
+ attribute \src "ls180.v:483.5-483.42"
wire $1\sdram_bankmachine1_refresh_gnt[0:0]
- attribute \src "ls180.v:477.5-477.46"
+ attribute \src "ls180.v:481.5-481.46"
wire $1\sdram_bankmachine1_req_rdata_valid[0:0]
- attribute \src "ls180.v:476.5-476.46"
+ attribute \src "ls180.v:480.5-480.46"
wire $1\sdram_bankmachine1_req_wdata_ready[0:0]
- attribute \src "ls180.v:540.12-540.42"
+ attribute \src "ls180.v:544.12-544.42"
wire width 13 $1\sdram_bankmachine1_row[12:0]
- attribute \src "ls180.v:544.5-544.40"
+ attribute \src "ls180.v:548.5-548.40"
wire $1\sdram_bankmachine1_row_close[0:0]
- attribute \src "ls180.v:545.5-545.49"
+ attribute \src "ls180.v:549.5-549.49"
wire $1\sdram_bankmachine1_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:543.5-543.39"
+ attribute \src "ls180.v:547.5-547.39"
wire $1\sdram_bankmachine1_row_open[0:0]
- attribute \src "ls180.v:541.5-541.41"
+ attribute \src "ls180.v:545.5-545.41"
wire $1\sdram_bankmachine1_row_opened[0:0]
- attribute \src "ls180.v:548.11-548.50"
+ attribute \src "ls180.v:552.11-552.50"
wire width 3 $1\sdram_bankmachine1_twtpcon_count[2:0]
- attribute \src "ls180.v:547.32-547.71"
+ attribute \src "ls180.v:551.32-551.71"
wire $1\sdram_bankmachine1_twtpcon_ready[0:0]
- attribute \src "ls180.v:572.5-572.45"
+ attribute \src "ls180.v:576.5-576.45"
wire $1\sdram_bankmachine2_auto_precharge[0:0]
- attribute \src "ls180.v:594.11-594.65"
+ attribute \src "ls180.v:598.11-598.65"
wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:591.11-591.63"
+ attribute \src "ls180.v:595.11-595.63"
wire width 4 $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:593.11-593.65"
+ attribute \src "ls180.v:597.11-597.65"
wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:595.11-595.68"
+ attribute \src "ls180.v:599.11-599.68"
wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:618.5-618.54"
+ attribute \src "ls180.v:622.5-622.54"
wire $1\sdram_bankmachine2_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:619.5-619.53"
+ attribute \src "ls180.v:623.5-623.53"
wire $1\sdram_bankmachine2_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:621.12-621.69"
+ attribute \src "ls180.v:625.12-625.69"
wire width 22 $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:620.5-620.59"
+ attribute \src "ls180.v:624.5-624.59"
wire $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:616.5-616.54"
+ attribute \src "ls180.v:620.5-620.54"
wire $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:564.12-564.52"
+ attribute \src "ls180.v:568.12-568.52"
wire width 13 $1\sdram_bankmachine2_cmd_payload_a[12:0]
- attribute \src "ls180.v:566.5-566.46"
+ attribute \src "ls180.v:570.5-570.46"
wire $1\sdram_bankmachine2_cmd_payload_cas[0:0]
- attribute \src "ls180.v:569.5-569.49"
+ attribute \src "ls180.v:573.5-573.49"
wire $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:570.5-570.50"
+ attribute \src "ls180.v:574.5-574.50"
wire $1\sdram_bankmachine2_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:571.5-571.51"
+ attribute \src "ls180.v:575.5-575.51"
wire $1\sdram_bankmachine2_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:567.5-567.46"
+ attribute \src "ls180.v:571.5-571.46"
wire $1\sdram_bankmachine2_cmd_payload_ras[0:0]
- attribute \src "ls180.v:568.5-568.45"
+ attribute \src "ls180.v:572.5-572.45"
wire $1\sdram_bankmachine2_cmd_payload_we[0:0]
- attribute \src "ls180.v:563.5-563.40"
+ attribute \src "ls180.v:567.5-567.40"
wire $1\sdram_bankmachine2_cmd_ready[0:0]
- attribute \src "ls180.v:562.5-562.40"
+ attribute \src "ls180.v:566.5-566.40"
wire $1\sdram_bankmachine2_cmd_valid[0:0]
- attribute \src "ls180.v:561.5-561.42"
+ attribute \src "ls180.v:565.5-565.42"
wire $1\sdram_bankmachine2_refresh_gnt[0:0]
- attribute \src "ls180.v:559.5-559.46"
+ attribute \src "ls180.v:563.5-563.46"
wire $1\sdram_bankmachine2_req_rdata_valid[0:0]
- attribute \src "ls180.v:558.5-558.46"
+ attribute \src "ls180.v:562.5-562.46"
wire $1\sdram_bankmachine2_req_wdata_ready[0:0]
- attribute \src "ls180.v:622.12-622.42"
+ attribute \src "ls180.v:626.12-626.42"
wire width 13 $1\sdram_bankmachine2_row[12:0]
- attribute \src "ls180.v:626.5-626.40"
+ attribute \src "ls180.v:630.5-630.40"
wire $1\sdram_bankmachine2_row_close[0:0]
- attribute \src "ls180.v:627.5-627.49"
+ attribute \src "ls180.v:631.5-631.49"
wire $1\sdram_bankmachine2_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:625.5-625.39"
+ attribute \src "ls180.v:629.5-629.39"
wire $1\sdram_bankmachine2_row_open[0:0]
- attribute \src "ls180.v:623.5-623.41"
+ attribute \src "ls180.v:627.5-627.41"
wire $1\sdram_bankmachine2_row_opened[0:0]
- attribute \src "ls180.v:630.11-630.50"
+ attribute \src "ls180.v:634.11-634.50"
wire width 3 $1\sdram_bankmachine2_twtpcon_count[2:0]
- attribute \src "ls180.v:629.32-629.71"
+ attribute \src "ls180.v:633.32-633.71"
wire $1\sdram_bankmachine2_twtpcon_ready[0:0]
- attribute \src "ls180.v:654.5-654.45"
+ attribute \src "ls180.v:658.5-658.45"
wire $1\sdram_bankmachine3_auto_precharge[0:0]
- attribute \src "ls180.v:676.11-676.65"
+ attribute \src "ls180.v:680.11-680.65"
wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
- attribute \src "ls180.v:673.11-673.63"
+ attribute \src "ls180.v:677.11-677.63"
wire width 4 $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
- attribute \src "ls180.v:675.11-675.65"
+ attribute \src "ls180.v:679.11-679.65"
wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
- attribute \src "ls180.v:677.11-677.68"
+ attribute \src "ls180.v:681.11-681.68"
wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
- attribute \src "ls180.v:700.5-700.54"
+ attribute \src "ls180.v:704.5-704.54"
wire $1\sdram_bankmachine3_cmd_buffer_source_first[0:0]
- attribute \src "ls180.v:701.5-701.53"
+ attribute \src "ls180.v:705.5-705.53"
wire $1\sdram_bankmachine3_cmd_buffer_source_last[0:0]
- attribute \src "ls180.v:703.12-703.69"
+ attribute \src "ls180.v:707.12-707.69"
wire width 22 $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
- attribute \src "ls180.v:702.5-702.59"
+ attribute \src "ls180.v:706.5-706.59"
wire $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
- attribute \src "ls180.v:698.5-698.54"
+ attribute \src "ls180.v:702.5-702.54"
wire $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0]
- attribute \src "ls180.v:646.12-646.52"
+ attribute \src "ls180.v:650.12-650.52"
wire width 13 $1\sdram_bankmachine3_cmd_payload_a[12:0]
- attribute \src "ls180.v:648.5-648.46"
+ attribute \src "ls180.v:652.5-652.46"
wire $1\sdram_bankmachine3_cmd_payload_cas[0:0]
- attribute \src "ls180.v:651.5-651.49"
+ attribute \src "ls180.v:655.5-655.49"
wire $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0]
- attribute \src "ls180.v:652.5-652.50"
+ attribute \src "ls180.v:656.5-656.50"
wire $1\sdram_bankmachine3_cmd_payload_is_read[0:0]
- attribute \src "ls180.v:653.5-653.51"
+ attribute \src "ls180.v:657.5-657.51"
wire $1\sdram_bankmachine3_cmd_payload_is_write[0:0]
- attribute \src "ls180.v:649.5-649.46"
+ attribute \src "ls180.v:653.5-653.46"
wire $1\sdram_bankmachine3_cmd_payload_ras[0:0]
- attribute \src "ls180.v:650.5-650.45"
+ attribute \src "ls180.v:654.5-654.45"
wire $1\sdram_bankmachine3_cmd_payload_we[0:0]
- attribute \src "ls180.v:645.5-645.40"
+ attribute \src "ls180.v:649.5-649.40"
wire $1\sdram_bankmachine3_cmd_ready[0:0]
- attribute \src "ls180.v:644.5-644.40"
+ attribute \src "ls180.v:648.5-648.40"
wire $1\sdram_bankmachine3_cmd_valid[0:0]
- attribute \src "ls180.v:643.5-643.42"
+ attribute \src "ls180.v:647.5-647.42"
wire $1\sdram_bankmachine3_refresh_gnt[0:0]
- attribute \src "ls180.v:641.5-641.46"
+ attribute \src "ls180.v:645.5-645.46"
wire $1\sdram_bankmachine3_req_rdata_valid[0:0]
- attribute \src "ls180.v:640.5-640.46"
+ attribute \src "ls180.v:644.5-644.46"
wire $1\sdram_bankmachine3_req_wdata_ready[0:0]
- attribute \src "ls180.v:704.12-704.42"
+ attribute \src "ls180.v:708.12-708.42"
wire width 13 $1\sdram_bankmachine3_row[12:0]
- attribute \src "ls180.v:708.5-708.40"
+ attribute \src "ls180.v:712.5-712.40"
wire $1\sdram_bankmachine3_row_close[0:0]
- attribute \src "ls180.v:709.5-709.49"
+ attribute \src "ls180.v:713.5-713.49"
wire $1\sdram_bankmachine3_row_col_n_addr_sel[0:0]
- attribute \src "ls180.v:707.5-707.39"
+ attribute \src "ls180.v:711.5-711.39"
wire $1\sdram_bankmachine3_row_open[0:0]
- attribute \src "ls180.v:705.5-705.41"
+ attribute \src "ls180.v:709.5-709.41"
wire $1\sdram_bankmachine3_row_opened[0:0]
- attribute \src "ls180.v:712.11-712.50"
+ attribute \src "ls180.v:716.11-716.50"
wire width 3 $1\sdram_bankmachine3_twtpcon_count[2:0]
- attribute \src "ls180.v:711.32-711.71"
+ attribute \src "ls180.v:715.32-715.71"
wire $1\sdram_bankmachine3_twtpcon_ready[0:0]
- attribute \src "ls180.v:727.5-727.44"
+ attribute \src "ls180.v:731.5-731.44"
wire $1\sdram_choose_cmd_cmd_payload_cas[0:0]
- attribute \src "ls180.v:728.5-728.44"
+ attribute \src "ls180.v:732.5-732.44"
wire $1\sdram_choose_cmd_cmd_payload_ras[0:0]
- attribute \src "ls180.v:729.5-729.43"
+ attribute \src "ls180.v:733.5-733.43"
wire $1\sdram_choose_cmd_cmd_payload_we[0:0]
- attribute \src "ls180.v:735.11-735.40"
+ attribute \src "ls180.v:739.11-739.40"
wire width 2 $1\sdram_choose_cmd_grant[1:0]
- attribute \src "ls180.v:733.11-733.41"
+ attribute \src "ls180.v:737.11-737.41"
wire width 4 $1\sdram_choose_cmd_valids[3:0]
- attribute \src "ls180.v:745.5-745.44"
+ attribute \src "ls180.v:749.5-749.44"
wire $1\sdram_choose_req_cmd_payload_cas[0:0]
- attribute \src "ls180.v:746.5-746.44"
+ attribute \src "ls180.v:750.5-750.44"
wire $1\sdram_choose_req_cmd_payload_ras[0:0]
- attribute \src "ls180.v:747.5-747.43"
+ attribute \src "ls180.v:751.5-751.43"
wire $1\sdram_choose_req_cmd_payload_we[0:0]
- attribute \src "ls180.v:742.5-742.38"
+ attribute \src "ls180.v:746.5-746.38"
wire $1\sdram_choose_req_cmd_ready[0:0]
- attribute \src "ls180.v:753.11-753.40"
+ attribute \src "ls180.v:757.11-757.40"
wire width 2 $1\sdram_choose_req_grant[1:0]
- attribute \src "ls180.v:751.11-751.41"
+ attribute \src "ls180.v:755.11-755.41"
wire width 4 $1\sdram_choose_req_valids[3:0]
- attribute \src "ls180.v:740.5-740.43"
+ attribute \src "ls180.v:744.5-744.43"
wire $1\sdram_choose_req_want_activates[0:0]
- attribute \src "ls180.v:737.5-737.39"
+ attribute \src "ls180.v:741.5-741.39"
wire $1\sdram_choose_req_want_reads[0:0]
- attribute \src "ls180.v:738.5-738.40"
+ attribute \src "ls180.v:742.5-742.40"
wire $1\sdram_choose_req_want_writes[0:0]
- attribute \src "ls180.v:136.5-136.23"
- wire $1\sdram_clock[0:0]
- attribute \src "ls180.v:366.5-366.26"
+ attribute \src "ls180.v:370.5-370.26"
wire $1\sdram_cmd_last[0:0]
- attribute \src "ls180.v:367.12-367.39"
+ attribute \src "ls180.v:371.12-371.39"
wire width 13 $1\sdram_cmd_payload_a[12:0]
- attribute \src "ls180.v:368.11-368.38"
+ attribute \src "ls180.v:372.11-372.38"
wire width 2 $1\sdram_cmd_payload_ba[1:0]
- attribute \src "ls180.v:369.5-369.33"
+ attribute \src "ls180.v:373.5-373.33"
wire $1\sdram_cmd_payload_cas[0:0]
- attribute \src "ls180.v:370.5-370.33"
+ attribute \src "ls180.v:374.5-374.33"
wire $1\sdram_cmd_payload_ras[0:0]
- attribute \src "ls180.v:371.5-371.32"
+ attribute \src "ls180.v:375.5-375.32"
wire $1\sdram_cmd_payload_we[0:0]
- attribute \src "ls180.v:365.5-365.27"
+ attribute \src "ls180.v:369.5-369.27"
wire $1\sdram_cmd_ready[0:0]
- attribute \src "ls180.v:364.5-364.27"
+ attribute \src "ls180.v:368.5-368.27"
wire $1\sdram_cmd_valid[0:0]
- attribute \src "ls180.v:304.5-304.28"
+ attribute \src "ls180.v:308.5-308.28"
wire $1\sdram_command_re[0:0]
- attribute \src "ls180.v:303.11-303.39"
+ attribute \src "ls180.v:307.11-307.39"
wire width 6 $1\sdram_command_storage[5:0]
- attribute \src "ls180.v:348.12-348.40"
+ attribute \src "ls180.v:352.12-352.40"
wire width 13 $1\sdram_dfi_p0_address[12:0]
- attribute \src "ls180.v:349.11-349.35"
+ attribute \src "ls180.v:353.11-353.35"
wire width 2 $1\sdram_dfi_p0_bank[1:0]
- attribute \src "ls180.v:350.5-350.30"
+ attribute \src "ls180.v:354.5-354.30"
wire $1\sdram_dfi_p0_cas_n[0:0]
- attribute \src "ls180.v:351.5-351.29"
+ attribute \src "ls180.v:355.5-355.29"
wire $1\sdram_dfi_p0_cs_n[0:0]
- attribute \src "ls180.v:352.5-352.30"
+ attribute \src "ls180.v:356.5-356.30"
wire $1\sdram_dfi_p0_ras_n[0:0]
- attribute \src "ls180.v:361.5-361.34"
+ attribute \src "ls180.v:365.5-365.34"
wire $1\sdram_dfi_p0_rddata_en[0:0]
- attribute \src "ls180.v:353.5-353.29"
+ attribute \src "ls180.v:357.5-357.29"
wire $1\sdram_dfi_p0_we_n[0:0]
- attribute \src "ls180.v:359.5-359.34"
+ attribute \src "ls180.v:363.5-363.34"
wire $1\sdram_dfi_p0_wrdata_en[0:0]
- attribute \src "ls180.v:772.5-772.21"
+ attribute \src "ls180.v:776.5-776.21"
wire $1\sdram_en0[0:0]
- attribute \src "ls180.v:775.5-775.21"
+ attribute \src "ls180.v:779.5-779.21"
wire $1\sdram_en1[0:0]
- attribute \src "ls180.v:345.12-345.41"
+ attribute \src "ls180.v:349.12-349.41"
wire width 16 $1\sdram_interface_wdata[15:0]
- attribute \src "ls180.v:346.11-346.42"
+ attribute \src "ls180.v:350.11-350.42"
wire width 2 $1\sdram_interface_wdata_we[1:0]
- attribute \src "ls180.v:251.5-251.31"
+ attribute \src "ls180.v:255.5-255.31"
wire $1\sdram_inti_p0_cas_n[0:0]
- attribute \src "ls180.v:252.5-252.30"
+ attribute \src "ls180.v:256.5-256.30"
wire $1\sdram_inti_p0_cs_n[0:0]
- attribute \src "ls180.v:253.5-253.31"
+ attribute \src "ls180.v:257.5-257.31"
wire $1\sdram_inti_p0_ras_n[0:0]
- attribute \src "ls180.v:263.12-263.40"
+ attribute \src "ls180.v:267.12-267.40"
wire width 16 $1\sdram_inti_p0_rddata[15:0]
- attribute \src "ls180.v:264.5-264.38"
+ attribute \src "ls180.v:268.5-268.38"
wire $1\sdram_inti_p0_rddata_valid[0:0]
- attribute \src "ls180.v:254.5-254.30"
+ attribute \src "ls180.v:258.5-258.30"
wire $1\sdram_inti_p0_we_n[0:0]
- attribute \src "ls180.v:290.5-290.33"
+ attribute \src "ls180.v:294.5-294.33"
wire $1\sdram_master_p0_act_n[0:0]
- attribute \src "ls180.v:281.12-281.43"
+ attribute \src "ls180.v:285.12-285.43"
wire width 13 $1\sdram_master_p0_address[12:0]
- attribute \src "ls180.v:282.11-282.38"
+ attribute \src "ls180.v:286.11-286.38"
wire width 2 $1\sdram_master_p0_bank[1:0]
- attribute \src "ls180.v:283.5-283.33"
+ attribute \src "ls180.v:287.5-287.33"
wire $1\sdram_master_p0_cas_n[0:0]
- attribute \src "ls180.v:287.5-287.31"
+ attribute \src "ls180.v:291.5-291.31"
wire $1\sdram_master_p0_cke[0:0]
- attribute \src "ls180.v:284.5-284.32"
+ attribute \src "ls180.v:288.5-288.32"
wire $1\sdram_master_p0_cs_n[0:0]
- attribute \src "ls180.v:288.5-288.31"
+ attribute \src "ls180.v:292.5-292.31"
wire $1\sdram_master_p0_odt[0:0]
- attribute \src "ls180.v:285.5-285.33"
+ attribute \src "ls180.v:289.5-289.33"
wire $1\sdram_master_p0_ras_n[0:0]
- attribute \src "ls180.v:294.5-294.37"
+ attribute \src "ls180.v:298.5-298.37"
wire $1\sdram_master_p0_rddata_en[0:0]
- attribute \src "ls180.v:289.5-289.35"
+ attribute \src "ls180.v:293.5-293.35"
wire $1\sdram_master_p0_reset_n[0:0]
- attribute \src "ls180.v:286.5-286.32"
+ attribute \src "ls180.v:290.5-290.32"
wire $1\sdram_master_p0_we_n[0:0]
- attribute \src "ls180.v:291.12-291.42"
+ attribute \src "ls180.v:295.12-295.42"
wire width 16 $1\sdram_master_p0_wrdata[15:0]
- attribute \src "ls180.v:292.5-292.37"
+ attribute \src "ls180.v:296.5-296.37"
wire $1\sdram_master_p0_wrdata_en[0:0]
- attribute \src "ls180.v:293.11-293.45"
+ attribute \src "ls180.v:297.11-297.45"
wire width 2 $1\sdram_master_p0_wrdata_mask[1:0]
- attribute \src "ls180.v:382.5-382.33"
+ attribute \src "ls180.v:386.5-386.33"
wire $1\sdram_postponer_count[0:0]
- attribute \src "ls180.v:381.5-381.33"
+ attribute \src "ls180.v:385.5-385.33"
wire $1\sdram_postponer_req_o[0:0]
- attribute \src "ls180.v:302.5-302.20"
+ attribute \src "ls180.v:306.5-306.20"
wire $1\sdram_re[0:0]
- attribute \src "ls180.v:388.5-388.33"
+ attribute \src "ls180.v:392.5-392.33"
wire $1\sdram_sequencer_count[0:0]
- attribute \src "ls180.v:387.11-387.41"
+ attribute \src "ls180.v:391.11-391.41"
wire width 4 $1\sdram_sequencer_counter[3:0]
- attribute \src "ls180.v:386.5-386.33"
+ attribute \src "ls180.v:390.5-390.33"
wire $1\sdram_sequencer_done1[0:0]
- attribute \src "ls180.v:383.5-383.34"
+ attribute \src "ls180.v:387.5-387.34"
wire $1\sdram_sequencer_start0[0:0]
- attribute \src "ls180.v:279.12-279.41"
+ attribute \src "ls180.v:283.12-283.41"
wire width 16 $1\sdram_slave_p0_rddata[15:0]
- attribute \src "ls180.v:280.5-280.39"
+ attribute \src "ls180.v:284.5-284.39"
wire $1\sdram_slave_p0_rddata_valid[0:0]
- attribute \src "ls180.v:315.12-315.32"
+ attribute \src "ls180.v:319.12-319.32"
wire width 16 $1\sdram_status[15:0]
- attribute \src "ls180.v:757.11-757.35"
+ attribute \src "ls180.v:761.11-761.35"
wire width 2 $1\sdram_steerer_sel[1:0]
- attribute \src "ls180.v:301.11-301.31"
+ attribute \src "ls180.v:305.11-305.31"
wire width 4 $1\sdram_storage[3:0]
- attribute \src "ls180.v:766.5-766.31"
+ attribute \src "ls180.v:770.5-770.31"
wire $1\sdram_tccdcon_count[0:0]
- attribute \src "ls180.v:765.32-765.58"
+ attribute \src "ls180.v:769.32-769.58"
wire $1\sdram_tccdcon_ready[0:0]
- attribute \src "ls180.v:774.11-774.29"
+ attribute \src "ls180.v:778.11-778.29"
wire width 5 $1\sdram_time0[4:0]
- attribute \src "ls180.v:777.11-777.29"
+ attribute \src "ls180.v:781.11-781.29"
wire width 4 $1\sdram_time1[3:0]
- attribute \src "ls180.v:379.11-379.39"
+ attribute \src "ls180.v:383.11-383.39"
wire width 10 $1\sdram_timer_count1[9:0]
- attribute \src "ls180.v:769.11-769.37"
+ attribute \src "ls180.v:773.11-773.37"
wire width 3 $1\sdram_twtrcon_count[2:0]
- attribute \src "ls180.v:768.32-768.58"
+ attribute \src "ls180.v:772.32-772.58"
wire $1\sdram_twtrcon_ready[0:0]
- attribute \src "ls180.v:314.5-314.27"
+ attribute \src "ls180.v:318.5-318.27"
wire $1\sdram_wrdata_re[0:0]
- attribute \src "ls180.v:313.12-313.40"
+ attribute \src "ls180.v:317.12-317.40"
wire width 16 $1\sdram_wrdata_storage[15:0]
- attribute \src "ls180.v:806.5-806.49"
+ attribute \src "ls180.v:810.5-810.49"
wire $1\socbushandler_converted_interface_ack[0:0]
- attribute \src "ls180.v:812.5-812.33"
+ attribute \src "ls180.v:816.5-816.33"
wire $1\socbushandler_counter[0:0]
- attribute \src "ls180.v:1012.5-1012.68"
+ attribute \src "ls180.v:1017.5-1017.68"
wire $1\socbushandler_counter_subfragments_converter2_next_value[0:0]
- attribute \src "ls180.v:1013.5-1013.71"
+ attribute \src "ls180.v:1018.5-1018.71"
wire $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
- attribute \src "ls180.v:814.12-814.39"
+ attribute \src "ls180.v:818.12-818.39"
wire width 64 $1\socbushandler_dat_r[63:0]
- attribute \src "ls180.v:811.5-811.30"
+ attribute \src "ls180.v:815.5-815.30"
wire $1\socbushandler_skip[0:0]
- attribute \src "ls180.v:1017.11-1017.54"
+ attribute \src "ls180.v:1022.11-1022.54"
wire width 3 $1\subfragments_bankmachine0_next_state[2:0]
- attribute \src "ls180.v:1016.11-1016.49"
+ attribute \src "ls180.v:1021.11-1021.49"
wire width 3 $1\subfragments_bankmachine0_state[2:0]
- attribute \src "ls180.v:1019.11-1019.54"
+ attribute \src "ls180.v:1024.11-1024.54"
wire width 3 $1\subfragments_bankmachine1_next_state[2:0]
- attribute \src "ls180.v:1018.11-1018.49"
+ attribute \src "ls180.v:1023.11-1023.49"
wire width 3 $1\subfragments_bankmachine1_state[2:0]
- attribute \src "ls180.v:1021.11-1021.54"
+ attribute \src "ls180.v:1026.11-1026.54"
wire width 3 $1\subfragments_bankmachine2_next_state[2:0]
- attribute \src "ls180.v:1020.11-1020.49"
+ attribute \src "ls180.v:1025.11-1025.49"
wire width 3 $1\subfragments_bankmachine2_state[2:0]
- attribute \src "ls180.v:1023.11-1023.54"
+ attribute \src "ls180.v:1028.11-1028.54"
wire width 3 $1\subfragments_bankmachine3_next_state[2:0]
- attribute \src "ls180.v:1022.11-1022.49"
+ attribute \src "ls180.v:1027.11-1027.49"
wire width 3 $1\subfragments_bankmachine3_state[2:0]
- attribute \src "ls180.v:1003.5-1003.46"
+ attribute \src "ls180.v:1008.5-1008.46"
wire $1\subfragments_converter0_next_state[0:0]
- attribute \src "ls180.v:1002.5-1002.41"
+ attribute \src "ls180.v:1007.5-1007.41"
wire $1\subfragments_converter0_state[0:0]
- attribute \src "ls180.v:1007.5-1007.46"
+ attribute \src "ls180.v:1012.5-1012.46"
wire $1\subfragments_converter1_next_state[0:0]
- attribute \src "ls180.v:1006.5-1006.41"
+ attribute \src "ls180.v:1011.5-1011.41"
wire $1\subfragments_converter1_state[0:0]
- attribute \src "ls180.v:1011.5-1011.46"
+ attribute \src "ls180.v:1016.5-1016.46"
wire $1\subfragments_converter2_next_state[0:0]
- attribute \src "ls180.v:1010.5-1010.41"
+ attribute \src "ls180.v:1015.5-1015.41"
wire $1\subfragments_converter2_state[0:0]
- attribute \src "ls180.v:1025.11-1025.53"
+ attribute \src "ls180.v:1030.11-1030.53"
wire width 3 $1\subfragments_multiplexer_next_state[2:0]
- attribute \src "ls180.v:1024.11-1024.48"
+ attribute \src "ls180.v:1029.11-1029.48"
wire width 3 $1\subfragments_multiplexer_state[2:0]
- attribute \src "ls180.v:1043.5-1043.48"
+ attribute \src "ls180.v:1048.5-1048.48"
wire $1\subfragments_new_master_rdata_valid0[0:0]
- attribute \src "ls180.v:1044.5-1044.48"
+ attribute \src "ls180.v:1049.5-1049.48"
wire $1\subfragments_new_master_rdata_valid1[0:0]
- attribute \src "ls180.v:1045.5-1045.48"
+ attribute \src "ls180.v:1050.5-1050.48"
wire $1\subfragments_new_master_rdata_valid2[0:0]
- attribute \src "ls180.v:1046.5-1046.48"
+ attribute \src "ls180.v:1051.5-1051.48"
wire $1\subfragments_new_master_rdata_valid3[0:0]
- attribute \src "ls180.v:1042.5-1042.47"
+ attribute \src "ls180.v:1047.5-1047.47"
wire $1\subfragments_new_master_wdata_ready[0:0]
- attribute \src "ls180.v:1048.5-1048.35"
+ attribute \src "ls180.v:1053.5-1053.35"
wire $1\subfragments_next_state[0:0]
- attribute \src "ls180.v:1015.11-1015.51"
+ attribute \src "ls180.v:1020.11-1020.51"
wire width 2 $1\subfragments_refresher_next_state[1:0]
- attribute \src "ls180.v:1014.11-1014.46"
+ attribute \src "ls180.v:1019.11-1019.46"
wire width 2 $1\subfragments_refresher_state[1:0]
- attribute \src "ls180.v:1047.5-1047.30"
+ attribute \src "ls180.v:1052.5-1052.30"
wire $1\subfragments_state[0:0]
- attribute \src "ls180.v:1351.5-1351.26"
+ attribute \src "ls180.v:1356.5-1356.26"
wire $1\t_array_muxed0[0:0]
- attribute \src "ls180.v:1352.5-1352.26"
+ attribute \src "ls180.v:1357.5-1357.26"
wire $1\t_array_muxed1[0:0]
- attribute \src "ls180.v:1353.5-1353.26"
+ attribute \src "ls180.v:1358.5-1358.26"
wire $1\t_array_muxed2[0:0]
- attribute \src "ls180.v:1360.5-1360.26"
+ attribute \src "ls180.v:1365.5-1365.26"
wire $1\t_array_muxed3[0:0]
- attribute \src "ls180.v:1361.5-1361.26"
+ attribute \src "ls180.v:1366.5-1366.26"
wire $1\t_array_muxed4[0:0]
- attribute \src "ls180.v:1362.5-1362.26"
+ attribute \src "ls180.v:1367.5-1367.26"
wire $1\t_array_muxed5[0:0]
- attribute \src "ls180.v:868.5-868.20"
+ attribute \src "ls180.v:872.5-872.20"
wire $1\tx_clear[0:0]
- attribute \src "ls180.v:920.11-920.33"
+ attribute \src "ls180.v:924.11-924.33"
wire width 4 $1\tx_fifo_consume[3:0]
- attribute \src "ls180.v:917.11-917.32"
+ attribute \src "ls180.v:921.11-921.32"
wire width 5 $1\tx_fifo_level0[4:0]
- attribute \src "ls180.v:919.11-919.33"
+ attribute \src "ls180.v:923.11-923.33"
wire width 4 $1\tx_fifo_produce[3:0]
- attribute \src "ls180.v:910.5-910.28"
+ attribute \src "ls180.v:914.5-914.28"
wire $1\tx_fifo_readable[0:0]
- attribute \src "ls180.v:921.11-921.36"
+ attribute \src "ls180.v:925.11-925.36"
wire width 4 $1\tx_fifo_wrport_adr[3:0]
- attribute \src "ls180.v:869.5-869.26"
+ attribute \src "ls180.v:873.5-873.26"
wire $1\tx_old_trigger[0:0]
- attribute \src "ls180.v:866.5-866.22"
+ attribute \src "ls180.v:870.5-870.22"
wire $1\tx_pending[0:0]
- attribute \src "ls180.v:850.12-850.49"
+ attribute \src "ls180.v:854.12-854.49"
wire width 32 $1\uart_phy_phase_accumulator_rx[31:0]
- attribute \src "ls180.v:840.12-840.49"
+ attribute \src "ls180.v:844.12-844.49"
wire width 32 $1\uart_phy_phase_accumulator_tx[31:0]
- attribute \src "ls180.v:833.5-833.23"
+ attribute \src "ls180.v:837.5-837.23"
wire $1\uart_phy_re[0:0]
- attribute \src "ls180.v:854.11-854.38"
+ attribute \src "ls180.v:858.11-858.38"
wire width 4 $1\uart_phy_rx_bitcount[3:0]
- attribute \src "ls180.v:855.5-855.28"
+ attribute \src "ls180.v:859.5-859.28"
wire $1\uart_phy_rx_busy[0:0]
- attribute \src "ls180.v:852.5-852.25"
+ attribute \src "ls180.v:856.5-856.25"
wire $1\uart_phy_rx_r[0:0]
- attribute \src "ls180.v:853.11-853.33"
+ attribute \src "ls180.v:857.11-857.33"
wire width 8 $1\uart_phy_rx_reg[7:0]
- attribute \src "ls180.v:835.5-835.31"
+ attribute \src "ls180.v:839.5-839.31"
wire $1\uart_phy_sink_ready[0:0]
- attribute \src "ls180.v:848.11-848.46"
+ attribute \src "ls180.v:852.11-852.46"
wire width 8 $1\uart_phy_source_payload_data[7:0]
- attribute \src "ls180.v:844.5-844.33"
+ attribute \src "ls180.v:848.5-848.33"
wire $1\uart_phy_source_valid[0:0]
- attribute \src "ls180.v:832.12-832.42"
+ attribute \src "ls180.v:836.12-836.42"
wire width 32 $1\uart_phy_storage[31:0]
- attribute \src "ls180.v:842.11-842.38"
+ attribute \src "ls180.v:846.11-846.38"
wire width 4 $1\uart_phy_tx_bitcount[3:0]
- attribute \src "ls180.v:843.5-843.28"
+ attribute \src "ls180.v:847.5-847.28"
wire $1\uart_phy_tx_busy[0:0]
- attribute \src "ls180.v:841.11-841.33"
+ attribute \src "ls180.v:845.11-845.33"
wire width 8 $1\uart_phy_tx_reg[7:0]
- attribute \src "ls180.v:849.5-849.34"
+ attribute \src "ls180.v:853.5-853.34"
wire $1\uart_phy_uart_clk_rxen[0:0]
- attribute \src "ls180.v:839.5-839.34"
+ attribute \src "ls180.v:843.5-843.34"
wire $1\uart_phy_uart_clk_txen[0:0]
- attribute \src "ls180.v:798.5-798.24"
+ attribute \src "ls180.v:802.5-802.24"
wire $1\wb_sdram_ack[0:0]
- attribute \src "ls180.v:792.12-792.32"
+ attribute \src "ls180.v:796.12-796.32"
wire width 30 $1\wb_sdram_adr[29:0]
- attribute \src "ls180.v:796.5-796.24"
+ attribute \src "ls180.v:800.5-800.24"
wire $1\wb_sdram_cyc[0:0]
- attribute \src "ls180.v:793.12-793.34"
+ attribute \src "ls180.v:797.12-797.34"
wire width 32 $1\wb_sdram_dat_w[31:0]
- attribute \src "ls180.v:795.11-795.30"
+ attribute \src "ls180.v:799.11-799.30"
wire width 4 $1\wb_sdram_sel[3:0]
- attribute \src "ls180.v:797.5-797.24"
+ attribute \src "ls180.v:801.5-801.24"
wire $1\wb_sdram_stb[0:0]
- attribute \src "ls180.v:799.5-799.23"
+ attribute \src "ls180.v:803.5-803.23"
wire $1\wb_sdram_we[0:0]
- attribute \src "ls180.v:828.5-828.26"
+ attribute \src "ls180.v:832.5-832.26"
wire $1\wdata_consumed[0:0]
- attribute \src "ls180.v:1555.64-1555.89"
- wire $add$ls180.v:1555$32_Y
- attribute \src "ls180.v:1615.64-1615.89"
- wire $add$ls180.v:1615$43_Y
- attribute \src "ls180.v:1675.67-1675.95"
- wire $add$ls180.v:1675$54_Y
- attribute \src "ls180.v:2826.52-2826.76"
- wire $add$ls180.v:2826$584_Y
- attribute \src "ls180.v:2926.26-2926.59"
- wire width 5 $add$ls180.v:2926$630_Y
- attribute \src "ls180.v:2956.26-2956.59"
- wire width 5 $add$ls180.v:2956$641_Y
- attribute \src "ls180.v:4353.31-4353.60"
- wire width 32 $add$ls180.v:4353$1281_Y
- attribute \src "ls180.v:4442.32-4442.62"
- wire width 4 $add$ls180.v:4442$1305_Y
- attribute \src "ls180.v:4459.55-4459.109"
- wire width 3 $add$ls180.v:4459$1309_Y
- attribute \src "ls180.v:4462.55-4462.109"
- wire width 3 $add$ls180.v:4462$1310_Y
- attribute \src "ls180.v:4466.54-4466.106"
- wire width 4 $add$ls180.v:4466$1315_Y
- attribute \src "ls180.v:4505.55-4505.109"
- wire width 3 $add$ls180.v:4505$1325_Y
- attribute \src "ls180.v:4508.55-4508.109"
- wire width 3 $add$ls180.v:4508$1326_Y
- attribute \src "ls180.v:4512.54-4512.106"
- wire width 4 $add$ls180.v:4512$1331_Y
- attribute \src "ls180.v:4551.55-4551.109"
- wire width 3 $add$ls180.v:4551$1341_Y
- attribute \src "ls180.v:4554.55-4554.109"
- wire width 3 $add$ls180.v:4554$1342_Y
- attribute \src "ls180.v:4558.54-4558.106"
- wire width 4 $add$ls180.v:4558$1347_Y
- attribute \src "ls180.v:4597.55-4597.109"
- wire width 3 $add$ls180.v:4597$1357_Y
- attribute \src "ls180.v:4600.55-4600.109"
- wire width 3 $add$ls180.v:4600$1358_Y
- attribute \src "ls180.v:4604.54-4604.106"
- wire width 4 $add$ls180.v:4604$1363_Y
- attribute \src "ls180.v:4834.29-4834.56"
- wire width 4 $add$ls180.v:4834$1417_Y
- attribute \src "ls180.v:4850.63-4850.111"
- wire width 33 $add$ls180.v:4850$1420_Y
- attribute \src "ls180.v:4863.29-4863.56"
- wire width 4 $add$ls180.v:4863$1424_Y
- attribute \src "ls180.v:4882.63-4882.111"
- wire width 33 $add$ls180.v:4882$1427_Y
- attribute \src "ls180.v:4908.23-4908.45"
- wire width 4 $add$ls180.v:4908$1435_Y
- attribute \src "ls180.v:4911.23-4911.45"
- wire width 4 $add$ls180.v:4911$1436_Y
- attribute \src "ls180.v:4915.23-4915.44"
- wire width 5 $add$ls180.v:4915$1441_Y
+ attribute \src "ls180.v:1568.64-1568.89"
+ wire $add$ls180.v:1568$33_Y
+ attribute \src "ls180.v:1628.64-1628.89"
+ wire $add$ls180.v:1628$44_Y
+ attribute \src "ls180.v:1688.67-1688.95"
+ wire $add$ls180.v:1688$55_Y
+ attribute \src "ls180.v:2839.52-2839.76"
+ wire $add$ls180.v:2839$585_Y
+ attribute \src "ls180.v:2939.26-2939.59"
+ wire width 5 $add$ls180.v:2939$631_Y
+ attribute \src "ls180.v:2969.26-2969.59"
+ wire width 5 $add$ls180.v:2969$642_Y
+ attribute \src "ls180.v:4372.31-4372.60"
+ wire width 32 $add$ls180.v:4372$1288_Y
+ attribute \src "ls180.v:4461.32-4461.62"
+ wire width 4 $add$ls180.v:4461$1312_Y
+ attribute \src "ls180.v:4478.55-4478.109"
+ wire width 3 $add$ls180.v:4478$1316_Y
+ attribute \src "ls180.v:4481.55-4481.109"
+ wire width 3 $add$ls180.v:4481$1317_Y
+ attribute \src "ls180.v:4485.54-4485.106"
+ wire width 4 $add$ls180.v:4485$1322_Y
+ attribute \src "ls180.v:4524.55-4524.109"
+ wire width 3 $add$ls180.v:4524$1332_Y
+ attribute \src "ls180.v:4527.55-4527.109"
+ wire width 3 $add$ls180.v:4527$1333_Y
+ attribute \src "ls180.v:4531.54-4531.106"
+ wire width 4 $add$ls180.v:4531$1338_Y
+ attribute \src "ls180.v:4570.55-4570.109"
+ wire width 3 $add$ls180.v:4570$1348_Y
+ attribute \src "ls180.v:4573.55-4573.109"
+ wire width 3 $add$ls180.v:4573$1349_Y
+ attribute \src "ls180.v:4577.54-4577.106"
+ wire width 4 $add$ls180.v:4577$1354_Y
+ attribute \src "ls180.v:4616.55-4616.109"
+ wire width 3 $add$ls180.v:4616$1364_Y
+ attribute \src "ls180.v:4619.55-4619.109"
+ wire width 3 $add$ls180.v:4619$1365_Y
+ attribute \src "ls180.v:4623.54-4623.106"
+ wire width 4 $add$ls180.v:4623$1370_Y
+ attribute \src "ls180.v:4853.29-4853.56"
+ wire width 4 $add$ls180.v:4853$1424_Y
+ attribute \src "ls180.v:4869.63-4869.111"
+ wire width 33 $add$ls180.v:4869$1427_Y
+ attribute \src "ls180.v:4882.29-4882.56"
+ wire width 4 $add$ls180.v:4882$1431_Y
+ attribute \src "ls180.v:4901.63-4901.111"
+ wire width 33 $add$ls180.v:4901$1434_Y
+ attribute \src "ls180.v:4927.23-4927.45"
+ wire width 4 $add$ls180.v:4927$1442_Y
attribute \src "ls180.v:4930.23-4930.45"
- wire width 4 $add$ls180.v:4930$1446_Y
- attribute \src "ls180.v:4933.23-4933.45"
- wire width 4 $add$ls180.v:4933$1447_Y
- attribute \src "ls180.v:4937.23-4937.44"
- wire width 5 $add$ls180.v:4937$1452_Y
- attribute \src "ls180.v:1549.9-1549.80"
- wire $and$ls180.v:1549$27_Y
- attribute \src "ls180.v:1567.9-1567.80"
- wire $and$ls180.v:1567$34_Y
- attribute \src "ls180.v:1609.9-1609.80"
- wire $and$ls180.v:1609$38_Y
- attribute \src "ls180.v:1627.9-1627.80"
- wire $and$ls180.v:1627$45_Y
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+ wire $or$ls180.v:4307$1254_Y
+ attribute \src "ls180.v:4308.15-4308.58"
+ wire $or$ls180.v:4308$1255_Y
+ attribute \src "ls180.v:4309.15-4309.58"
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+ attribute \src "ls180.v:4310.15-4310.58"
+ wire $or$ls180.v:4310$1257_Y
attribute \src "ls180.v:4311.16-4311.60"
- wire $or$ls180.v:4311$1270_Y
+ wire $or$ls180.v:4311$1258_Y
attribute \src "ls180.v:4312.16-4312.60"
- wire $or$ls180.v:4312$1271_Y
+ wire $or$ls180.v:4312$1259_Y
attribute \src "ls180.v:4313.16-4313.60"
- wire $or$ls180.v:4313$1272_Y
+ wire $or$ls180.v:4313$1260_Y
attribute \src "ls180.v:4314.16-4314.60"
- wire $or$ls180.v:4314$1273_Y
+ wire $or$ls180.v:4314$1261_Y
attribute \src "ls180.v:4315.16-4315.60"
- wire $or$ls180.v:4315$1274_Y
+ wire $or$ls180.v:4315$1262_Y
attribute \src "ls180.v:4316.16-4316.60"
- wire $or$ls180.v:4316$1275_Y
+ wire $or$ls180.v:4316$1263_Y
attribute \src "ls180.v:4317.16-4317.60"
- wire $or$ls180.v:4317$1276_Y
- attribute \src "ls180.v:4318.7-4318.58"
- wire $or$ls180.v:4318$1277_Y
- attribute \src "ls180.v:4329.7-4329.58"
- wire $or$ls180.v:4329$1278_Y
- attribute \src "ls180.v:4340.7-4340.40"
- wire $or$ls180.v:4340$1279_Y
- attribute \src "ls180.v:4473.7-4473.97"
- wire $or$ls180.v:4473$1318_Y
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- wire $or$ls180.v:4519$1334_Y
- attribute \src "ls180.v:4565.7-4565.97"
- wire $or$ls180.v:4565$1350_Y
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- wire $or$ls180.v:4611$1366_Y
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- wire $or$ls180.v:4799$1393_Y
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- wire $or$ls180.v:4799$1396_Y
- attribute \src "ls180.v:4800.46-4800.131"
- wire $or$ls180.v:4800$1399_Y
- attribute \src "ls180.v:4800.45-4800.213"
- wire $or$ls180.v:4800$1402_Y
- attribute \src "ls180.v:4800.44-4800.295"
- wire $or$ls180.v:4800$1405_Y
- attribute \src "ls180.v:4800.43-4800.377"
- wire $or$ls180.v:4800$1408_Y
- attribute \src "ls180.v:4804.7-4804.39"
- wire $or$ls180.v:4804$1409_Y
- attribute \src "ls180.v:5729.8-5729.46"
- wire $or$ls180.v:5729$1619_Y
- attribute \src "ls180.v:1936.41-1936.84"
- wire width 13 $sshl$ls180.v:1936$130_Y
- attribute \src "ls180.v:2093.41-2093.84"
- wire width 13 $sshl$ls180.v:2093$160_Y
- attribute \src "ls180.v:2250.41-2250.84"
- wire width 13 $sshl$ls180.v:2250$190_Y
- attribute \src "ls180.v:2407.41-2407.84"
- wire width 13 $sshl$ls180.v:2407$220_Y
- attribute \src "ls180.v:1967.58-1967.112"
- wire width 3 $sub$ls180.v:1967$143_Y
- attribute \src "ls180.v:2124.58-2124.112"
- wire width 3 $sub$ls180.v:2124$173_Y
- attribute \src "ls180.v:2281.58-2281.112"
- wire width 3 $sub$ls180.v:2281$203_Y
- attribute \src "ls180.v:2438.58-2438.112"
- wire width 3 $sub$ls180.v:2438$233_Y
- attribute \src "ls180.v:2844.33-2844.65"
- wire width 31 $sub$ls180.v:2844$587_Y
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- wire width 4 $sub$ls180.v:2930$632_Y
- attribute \src "ls180.v:2960.26-2960.48"
- wire width 4 $sub$ls180.v:2960$643_Y
- attribute \src "ls180.v:4364.26-4364.50"
- wire width 32 $sub$ls180.v:4364$1286_Y
- attribute \src "ls180.v:4389.26-4389.51"
- wire width 10 $sub$ls180.v:4389$1294_Y
- attribute \src "ls180.v:4395.29-4395.57"
- wire $sub$ls180.v:4395$1295_Y
- attribute \src "ls180.v:4406.31-4406.59"
- wire $sub$ls180.v:4406$1298_Y
- attribute \src "ls180.v:4470.54-4470.106"
- wire width 4 $sub$ls180.v:4470$1316_Y
- attribute \src "ls180.v:4489.41-4489.80"
- wire width 3 $sub$ls180.v:4489$1320_Y
- attribute \src "ls180.v:4516.54-4516.106"
- wire width 4 $sub$ls180.v:4516$1332_Y
- attribute \src "ls180.v:4535.41-4535.80"
- wire width 3 $sub$ls180.v:4535$1336_Y
- attribute \src "ls180.v:4562.54-4562.106"
- wire width 4 $sub$ls180.v:4562$1348_Y
- attribute \src "ls180.v:4581.41-4581.80"
- wire width 3 $sub$ls180.v:4581$1352_Y
- attribute \src "ls180.v:4608.54-4608.106"
- wire width 4 $sub$ls180.v:4608$1364_Y
- attribute \src "ls180.v:4627.41-4627.80"
- wire width 3 $sub$ls180.v:4627$1368_Y
- attribute \src "ls180.v:4638.20-4638.38"
- wire width 5 $sub$ls180.v:4638$1372_Y
- attribute \src "ls180.v:4645.20-4645.38"
- wire width 4 $sub$ls180.v:4645$1375_Y
- attribute \src "ls180.v:4777.28-4777.54"
- wire $sub$ls180.v:4777$1380_Y
- attribute \src "ls180.v:4792.28-4792.54"
- wire width 3 $sub$ls180.v:4792$1383_Y
- attribute \src "ls180.v:4919.23-4919.44"
- wire width 5 $sub$ls180.v:4919$1442_Y
- attribute \src "ls180.v:4941.23-4941.44"
- wire width 5 $sub$ls180.v:4941$1453_Y
- attribute \src "ls180.v:5006.26-5006.50"
- wire width 20 $sub$ls180.v:5006$1458_Y
- attribute \src "ls180.v:829.6-829.13"
+ wire $or$ls180.v:4317$1264_Y
+ attribute \src "ls180.v:4318.16-4318.60"
+ wire $or$ls180.v:4318$1265_Y
+ attribute \src "ls180.v:4319.16-4319.60"
+ wire $or$ls180.v:4319$1266_Y
+ attribute \src "ls180.v:4320.16-4320.60"
+ wire $or$ls180.v:4320$1267_Y
+ attribute \src "ls180.v:4321.16-4321.60"
+ wire $or$ls180.v:4321$1268_Y
+ attribute \src "ls180.v:4322.16-4322.60"
+ wire $or$ls180.v:4322$1269_Y
+ attribute \src "ls180.v:4323.16-4323.60"
+ wire $or$ls180.v:4323$1270_Y
+ attribute \src "ls180.v:4324.16-4324.60"
+ wire $or$ls180.v:4324$1271_Y
+ attribute \src "ls180.v:4325.16-4325.60"
+ wire $or$ls180.v:4325$1272_Y
+ attribute \src "ls180.v:4326.16-4326.60"
+ wire $or$ls180.v:4326$1273_Y
+ attribute \src "ls180.v:4327.16-4327.60"
+ wire $or$ls180.v:4327$1274_Y
+ attribute \src "ls180.v:4328.16-4328.60"
+ wire $or$ls180.v:4328$1275_Y
+ attribute \src "ls180.v:4329.16-4329.60"
+ wire $or$ls180.v:4329$1276_Y
+ attribute \src "ls180.v:4330.16-4330.60"
+ wire $or$ls180.v:4330$1277_Y
+ attribute \src "ls180.v:4331.16-4331.60"
+ wire $or$ls180.v:4331$1278_Y
+ attribute \src "ls180.v:4332.16-4332.60"
+ wire $or$ls180.v:4332$1279_Y
+ attribute \src "ls180.v:4333.16-4333.60"
+ wire $or$ls180.v:4333$1280_Y
+ attribute \src "ls180.v:4334.16-4334.60"
+ wire $or$ls180.v:4334$1281_Y
+ attribute \src "ls180.v:4335.16-4335.60"
+ wire $or$ls180.v:4335$1282_Y
+ attribute \src "ls180.v:4336.16-4336.60"
+ wire $or$ls180.v:4336$1283_Y
+ attribute \src "ls180.v:4337.7-4337.58"
+ wire $or$ls180.v:4337$1284_Y
+ attribute \src "ls180.v:4348.7-4348.58"
+ wire $or$ls180.v:4348$1285_Y
+ attribute \src "ls180.v:4359.7-4359.40"
+ wire $or$ls180.v:4359$1286_Y
+ attribute \src "ls180.v:4492.7-4492.97"
+ wire $or$ls180.v:4492$1325_Y
+ attribute \src "ls180.v:4538.7-4538.97"
+ wire $or$ls180.v:4538$1341_Y
+ attribute \src "ls180.v:4584.7-4584.97"
+ wire $or$ls180.v:4584$1357_Y
+ attribute \src "ls180.v:4630.7-4630.97"
+ wire $or$ls180.v:4630$1373_Y
+ attribute \src "ls180.v:4818.45-4818.130"
+ wire $or$ls180.v:4818$1394_Y
+ attribute \src "ls180.v:4818.44-4818.212"
+ wire $or$ls180.v:4818$1397_Y
+ attribute \src "ls180.v:4818.43-4818.294"
+ wire $or$ls180.v:4818$1400_Y
+ attribute \src "ls180.v:4818.42-4818.376"
+ wire $or$ls180.v:4818$1403_Y
+ attribute \src "ls180.v:4819.46-4819.131"
+ wire $or$ls180.v:4819$1406_Y
+ attribute \src "ls180.v:4819.45-4819.213"
+ wire $or$ls180.v:4819$1409_Y
+ attribute \src "ls180.v:4819.44-4819.295"
+ wire $or$ls180.v:4819$1412_Y
+ attribute \src "ls180.v:4819.43-4819.377"
+ wire $or$ls180.v:4819$1415_Y
+ attribute \src "ls180.v:4823.7-4823.39"
+ wire $or$ls180.v:4823$1416_Y
+ attribute \src "ls180.v:5748.8-5748.46"
+ wire $or$ls180.v:5748$1626_Y
+ attribute \src "ls180.v:1949.41-1949.84"
+ wire width 13 $sshl$ls180.v:1949$131_Y
+ attribute \src "ls180.v:2106.41-2106.84"
+ wire width 13 $sshl$ls180.v:2106$161_Y
+ attribute \src "ls180.v:2263.41-2263.84"
+ wire width 13 $sshl$ls180.v:2263$191_Y
+ attribute \src "ls180.v:2420.41-2420.84"
+ wire width 13 $sshl$ls180.v:2420$221_Y
+ attribute \src "ls180.v:1980.58-1980.112"
+ wire width 3 $sub$ls180.v:1980$144_Y
+ attribute \src "ls180.v:2137.58-2137.112"
+ wire width 3 $sub$ls180.v:2137$174_Y
+ attribute \src "ls180.v:2294.58-2294.112"
+ wire width 3 $sub$ls180.v:2294$204_Y
+ attribute \src "ls180.v:2451.58-2451.112"
+ wire width 3 $sub$ls180.v:2451$234_Y
+ attribute \src "ls180.v:2857.33-2857.65"
+ wire width 31 $sub$ls180.v:2857$588_Y
+ attribute \src "ls180.v:2943.26-2943.48"
+ wire width 4 $sub$ls180.v:2943$633_Y
+ attribute \src "ls180.v:2973.26-2973.48"
+ wire width 4 $sub$ls180.v:2973$644_Y
+ attribute \src "ls180.v:4383.26-4383.50"
+ wire width 32 $sub$ls180.v:4383$1293_Y
+ attribute \src "ls180.v:4408.26-4408.51"
+ wire width 10 $sub$ls180.v:4408$1301_Y
+ attribute \src "ls180.v:4414.29-4414.57"
+ wire $sub$ls180.v:4414$1302_Y
+ attribute \src "ls180.v:4425.31-4425.59"
+ wire $sub$ls180.v:4425$1305_Y
+ attribute \src "ls180.v:4489.54-4489.106"
+ wire width 4 $sub$ls180.v:4489$1323_Y
+ attribute \src "ls180.v:4508.41-4508.80"
+ wire width 3 $sub$ls180.v:4508$1327_Y
+ attribute \src "ls180.v:4535.54-4535.106"
+ wire width 4 $sub$ls180.v:4535$1339_Y
+ attribute \src "ls180.v:4554.41-4554.80"
+ wire width 3 $sub$ls180.v:4554$1343_Y
+ attribute \src "ls180.v:4581.54-4581.106"
+ wire width 4 $sub$ls180.v:4581$1355_Y
+ attribute \src "ls180.v:4600.41-4600.80"
+ wire width 3 $sub$ls180.v:4600$1359_Y
+ attribute \src "ls180.v:4627.54-4627.106"
+ wire width 4 $sub$ls180.v:4627$1371_Y
+ attribute \src "ls180.v:4646.41-4646.80"
+ wire width 3 $sub$ls180.v:4646$1375_Y
+ attribute \src "ls180.v:4657.20-4657.38"
+ wire width 5 $sub$ls180.v:4657$1379_Y
+ attribute \src "ls180.v:4664.20-4664.38"
+ wire width 4 $sub$ls180.v:4664$1382_Y
+ attribute \src "ls180.v:4796.28-4796.54"
+ wire $sub$ls180.v:4796$1387_Y
+ attribute \src "ls180.v:4811.28-4811.54"
+ wire width 3 $sub$ls180.v:4811$1390_Y
+ attribute \src "ls180.v:4938.23-4938.44"
+ wire width 5 $sub$ls180.v:4938$1449_Y
+ attribute \src "ls180.v:4960.23-4960.44"
+ wire width 5 $sub$ls180.v:4960$1460_Y
+ attribute \src "ls180.v:5025.26-5025.50"
+ wire width 20 $sub$ls180.v:5025$1465_Y
+ attribute \src "ls180.v:833.6-833.13"
wire \ack_cmd
- attribute \src "ls180.v:831.6-831.15"
+ attribute \src "ls180.v:835.6-835.15"
wire \ack_rdata
- attribute \src "ls180.v:830.6-830.15"
+ attribute \src "ls180.v:834.6-834.15"
wire \ack_wdata
- attribute \src "ls180.v:1383.11-1383.23"
+ attribute \src "ls180.v:1388.11-1388.23"
wire width 2 \array_muxed0
- attribute \src "ls180.v:1384.12-1384.24"
+ attribute \src "ls180.v:1389.12-1389.24"
wire width 13 \array_muxed1
- attribute \src "ls180.v:1385.5-1385.17"
+ attribute \src "ls180.v:1390.5-1390.17"
wire \array_muxed2
- attribute \src "ls180.v:1386.5-1386.17"
+ attribute \src "ls180.v:1391.5-1391.17"
wire \array_muxed3
- attribute \src "ls180.v:1387.5-1387.17"
+ attribute \src "ls180.v:1392.5-1392.17"
wire \array_muxed4
- attribute \src "ls180.v:1388.5-1388.17"
+ attribute \src "ls180.v:1393.5-1393.17"
wire \array_muxed5
- attribute \src "ls180.v:1389.5-1389.17"
+ attribute \src "ls180.v:1394.5-1394.17"
wire \array_muxed6
- attribute \src "ls180.v:827.5-827.17"
+ attribute \src "ls180.v:831.5-831.17"
wire \cmd_consumed
- attribute \src "ls180.v:210.5-210.23"
+ attribute \src "ls180.v:214.5-214.23"
wire \converter0_counter
- attribute \src "ls180.v:1004.5-1004.58"
+ attribute \src "ls180.v:1009.5-1009.58"
wire \converter0_counter_subfragments_converter0_next_value
- attribute \src "ls180.v:1005.5-1005.61"
+ attribute \src "ls180.v:1010.5-1010.61"
wire \converter0_counter_subfragments_converter0_next_value_ce
- attribute \src "ls180.v:212.12-212.28"
+ attribute \src "ls180.v:216.12-216.28"
wire width 64 \converter0_dat_r
- attribute \src "ls180.v:211.6-211.22"
+ attribute \src "ls180.v:215.6-215.22"
wire \converter0_reset
- attribute \src "ls180.v:209.5-209.20"
+ attribute \src "ls180.v:213.5-213.20"
wire \converter0_skip
- attribute \src "ls180.v:225.5-225.23"
+ attribute \src "ls180.v:229.5-229.23"
wire \converter1_counter
- attribute \src "ls180.v:1008.5-1008.58"
+ attribute \src "ls180.v:1013.5-1013.58"
wire \converter1_counter_subfragments_converter1_next_value
- attribute \src "ls180.v:1009.5-1009.61"
+ attribute \src "ls180.v:1014.5-1014.61"
wire \converter1_counter_subfragments_converter1_next_value_ce
- attribute \src "ls180.v:227.12-227.28"
+ attribute \src "ls180.v:231.12-231.28"
wire width 64 \converter1_dat_r
- attribute \src "ls180.v:226.6-226.22"
+ attribute \src "ls180.v:230.6-230.22"
wire \converter1_reset
- attribute \src "ls180.v:224.5-224.20"
+ attribute \src "ls180.v:228.5-228.20"
wire \converter1_skip
- attribute \src "ls180.v:824.5-824.22"
+ attribute \src "ls180.v:828.5-828.22"
wire \converter_counter
- attribute \src "ls180.v:1049.5-1049.46"
+ attribute \src "ls180.v:1054.5-1054.46"
wire \converter_counter_subfragments_next_value
- attribute \src "ls180.v:1050.5-1050.49"
+ attribute \src "ls180.v:1055.5-1055.49"
wire \converter_counter_subfragments_next_value_ce
- attribute \src "ls180.v:826.12-826.27"
+ attribute \src "ls180.v:830.12-830.27"
wire width 32 \converter_dat_r
- attribute \src "ls180.v:825.6-825.21"
+ attribute \src "ls180.v:829.6-829.21"
wire \converter_reset
- attribute \src "ls180.v:823.5-823.19"
+ attribute \src "ls180.v:827.5-827.19"
wire \converter_skip
- attribute \src "ls180.v:241.6-241.18"
+ attribute \src "ls180.v:245.6-245.18"
wire \dfi_p0_act_n
- attribute \src "ls180.v:232.13-232.27"
+ attribute \src "ls180.v:236.13-236.27"
wire width 13 \dfi_p0_address
- attribute \src "ls180.v:233.12-233.23"
+ attribute \src "ls180.v:237.12-237.23"
wire width 2 \dfi_p0_bank
- attribute \src "ls180.v:234.6-234.18"
+ attribute \src "ls180.v:238.6-238.18"
wire \dfi_p0_cas_n
- attribute \src "ls180.v:238.6-238.16"
+ attribute \src "ls180.v:242.6-242.16"
wire \dfi_p0_cke
- attribute \src "ls180.v:235.6-235.17"
+ attribute \src "ls180.v:239.6-239.17"
wire \dfi_p0_cs_n
- attribute \src "ls180.v:239.6-239.16"
+ attribute \src "ls180.v:243.6-243.16"
wire \dfi_p0_odt
- attribute \src "ls180.v:236.6-236.18"
+ attribute \src "ls180.v:240.6-240.18"
wire \dfi_p0_ras_n
- attribute \src "ls180.v:246.12-246.25"
+ attribute \src "ls180.v:250.12-250.25"
wire width 16 \dfi_p0_rddata
- attribute \src "ls180.v:245.6-245.22"
+ attribute \src "ls180.v:249.6-249.22"
wire \dfi_p0_rddata_en
- attribute \src "ls180.v:247.5-247.24"
+ attribute \src "ls180.v:251.5-251.24"
wire \dfi_p0_rddata_valid
- attribute \src "ls180.v:240.6-240.20"
+ attribute \src "ls180.v:244.6-244.20"
wire \dfi_p0_reset_n
- attribute \src "ls180.v:237.6-237.17"
+ attribute \src "ls180.v:241.6-241.17"
wire \dfi_p0_we_n
- attribute \src "ls180.v:242.13-242.26"
+ attribute \src "ls180.v:246.13-246.26"
wire width 16 \dfi_p0_wrdata
- attribute \src "ls180.v:243.6-243.22"
+ attribute \src "ls180.v:247.6-247.22"
wire \dfi_p0_wrdata_en
- attribute \src "ls180.v:244.12-244.30"
+ attribute \src "ls180.v:248.12-248.30"
wire width 2 \dfi_p0_wrdata_mask
- attribute \src "ls180.v:993.12-993.17"
- wire width 30 \dummy
- attribute \src "ls180.v:124.12-124.16"
- wire width 3 \eint
- attribute \src "ls180.v:14.19-14.25"
- wire width 3 input 10 \eint_1
- attribute \src "ls180.v:880.12-880.34"
+ attribute \src "ls180.v:998.12-998.17"
+ wire width 36 \dummy
+ attribute \src "ls180.v:14.13-14.19"
+ wire input 10 \eint_0
+ attribute \src "ls180.v:15.13-15.19"
+ wire input 11 \eint_1
+ attribute \src "ls180.v:16.13-16.19"
+ wire input 12 \eint_2
+ attribute \src "ls180.v:996.11-996.19"
+ wire width 3 \eint_tmp
+ attribute \src "ls180.v:884.12-884.34"
wire width 2 \eventmanager_pending_r
- attribute \src "ls180.v:879.6-879.29"
+ attribute \src "ls180.v:883.6-883.29"
wire \eventmanager_pending_re
- attribute \src "ls180.v:882.11-882.33"
+ attribute \src "ls180.v:886.11-886.33"
wire width 2 \eventmanager_pending_w
- attribute \src "ls180.v:881.6-881.29"
+ attribute \src "ls180.v:885.6-885.29"
wire \eventmanager_pending_we
- attribute \src "ls180.v:884.5-884.20"
+ attribute \src "ls180.v:888.5-888.20"
wire \eventmanager_re
- attribute \src "ls180.v:876.12-876.33"
+ attribute \src "ls180.v:880.12-880.33"
wire width 2 \eventmanager_status_r
- attribute \src "ls180.v:875.6-875.28"
+ attribute \src "ls180.v:879.6-879.28"
wire \eventmanager_status_re
- attribute \src "ls180.v:878.11-878.32"
+ attribute \src "ls180.v:882.11-882.32"
wire width 2 \eventmanager_status_w
- attribute \src "ls180.v:877.6-877.28"
+ attribute \src "ls180.v:881.6-881.28"
wire \eventmanager_status_we
- attribute \src "ls180.v:883.11-883.31"
+ attribute \src "ls180.v:887.11-887.31"
wire width 2 \eventmanager_storage
- attribute \src "ls180.v:975.5-975.16"
+ attribute \src "ls180.v:979.5-979.16"
wire \gpio0_oe_re
- attribute \src "ls180.v:974.11-974.27"
+ attribute \src "ls180.v:978.11-978.27"
wire width 8 \gpio0_oe_storage
- attribute \src "ls180.v:979.5-979.17"
+ attribute \src "ls180.v:983.5-983.17"
wire \gpio0_out_re
- attribute \src "ls180.v:978.11-978.28"
+ attribute \src "ls180.v:982.11-982.28"
wire width 8 \gpio0_out_storage
- attribute \src "ls180.v:980.11-980.28"
+ attribute \src "ls180.v:984.11-984.28"
wire width 8 \gpio0_pads_gpio0i
- attribute \src "ls180.v:981.11-981.28"
+ attribute \src "ls180.v:985.11-985.28"
wire width 8 \gpio0_pads_gpio0o
- attribute \src "ls180.v:982.11-982.29"
+ attribute \src "ls180.v:986.11-986.29"
wire width 8 \gpio0_pads_gpio0oe
- attribute \src "ls180.v:976.11-976.23"
+ attribute \src "ls180.v:980.11-980.23"
wire width 8 \gpio0_status
- attribute \src "ls180.v:977.6-977.14"
+ attribute \src "ls180.v:981.6-981.14"
wire \gpio0_we
- attribute \src "ls180.v:984.5-984.16"
+ attribute \src "ls180.v:988.5-988.16"
wire \gpio1_oe_re
- attribute \src "ls180.v:983.11-983.27"
+ attribute \src "ls180.v:987.11-987.27"
wire width 8 \gpio1_oe_storage
- attribute \src "ls180.v:988.5-988.17"
+ attribute \src "ls180.v:992.5-992.17"
wire \gpio1_out_re
- attribute \src "ls180.v:987.11-987.28"
+ attribute \src "ls180.v:991.11-991.28"
wire width 8 \gpio1_out_storage
- attribute \src "ls180.v:989.11-989.28"
+ attribute \src "ls180.v:993.11-993.28"
wire width 8 \gpio1_pads_gpio1i
- attribute \src "ls180.v:990.11-990.28"
+ attribute \src "ls180.v:994.11-994.28"
wire width 8 \gpio1_pads_gpio1o
- attribute \src "ls180.v:991.11-991.29"
+ attribute \src "ls180.v:995.11-995.29"
wire width 8 \gpio1_pads_gpio1oe
- attribute \src "ls180.v:985.11-985.23"
+ attribute \src "ls180.v:989.11-989.23"
wire width 8 \gpio1_status
- attribute \src "ls180.v:986.6-986.14"
+ attribute \src "ls180.v:990.6-990.14"
wire \gpio1_we
- attribute \src "ls180.v:5.20-5.26"
- wire width 16 input 1 \gpio_i
- attribute \src "ls180.v:6.21-6.27"
- wire width 16 output 2 \gpio_o
- attribute \src "ls180.v:7.21-7.28"
- wire width 16 output 3 \gpio_oe
- attribute \src "ls180.v:995.6-995.12"
+ attribute \src "ls180.v:11.20-11.26"
+ wire width 16 input 7 \gpio_i
+ attribute \src "ls180.v:12.21-12.27"
+ wire width 16 output 8 \gpio_o
+ attribute \src "ls180.v:13.21-13.28"
+ wire width 16 output 9 \gpio_oe
+ attribute \src "ls180.v:1000.6-1000.12"
wire \i2c_oe
- attribute \src "ls180.v:998.5-998.11"
+ attribute \src "ls180.v:1003.5-1003.11"
wire \i2c_re
- attribute \src "ls180.v:27.14-27.21"
- wire output 23 \i2c_scl
- attribute \src "ls180.v:994.6-994.15"
+ attribute \src "ls180.v:5.14-5.21"
+ wire output 1 \i2c_scl
+ attribute \src "ls180.v:999.6-999.15"
wire \i2c_scl_1
- attribute \src "ls180.v:996.6-996.14"
+ attribute \src "ls180.v:1001.6-1001.14"
wire \i2c_sda0
- attribute \src "ls180.v:999.6-999.14"
+ attribute \src "ls180.v:1004.6-1004.14"
wire \i2c_sda1
- attribute \src "ls180.v:28.13-28.22"
- wire input 24 \i2c_sda_i
- attribute \src "ls180.v:29.14-29.23"
- wire output 25 \i2c_sda_o
- attribute \src "ls180.v:30.14-30.24"
- wire output 26 \i2c_sda_oe
- attribute \src "ls180.v:1000.6-1000.16"
+ attribute \src "ls180.v:6.13-6.22"
+ wire input 2 \i2c_sda_i
+ attribute \src "ls180.v:7.14-7.23"
+ wire output 3 \i2c_sda_o
+ attribute \src "ls180.v:8.14-8.24"
+ wire output 4 \i2c_sda_oe
+ attribute \src "ls180.v:1005.6-1005.16"
wire \i2c_status
- attribute \src "ls180.v:997.11-997.22"
+ attribute \src "ls180.v:1002.11-1002.22"
wire width 3 \i2c_storage
- attribute \src "ls180.v:1001.6-1001.12"
+ attribute \src "ls180.v:1006.6-1006.12"
wire \i2c_we
- attribute \src "ls180.v:231.5-231.12"
+ attribute \src "ls180.v:235.5-235.12"
wire \int_rst
- attribute \src "ls180.v:204.5-204.39"
+ attribute \src "ls180.v:208.5-208.39"
wire \interface0_converted_interface_ack
- attribute \src "ls180.v:198.13-198.47"
+ attribute \src "ls180.v:202.13-202.47"
wire width 30 \interface0_converted_interface_adr
- attribute \src "ls180.v:207.12-207.46"
+ attribute \src "ls180.v:211.12-211.46"
wire width 2 \interface0_converted_interface_bte
- attribute \src "ls180.v:206.12-206.46"
+ attribute \src "ls180.v:210.12-210.46"
wire width 3 \interface0_converted_interface_cti
- attribute \src "ls180.v:202.6-202.40"
+ attribute \src "ls180.v:206.6-206.40"
wire \interface0_converted_interface_cyc
- attribute \src "ls180.v:200.13-200.49"
+ attribute \src "ls180.v:204.13-204.49"
wire width 64 \interface0_converted_interface_dat_r
- attribute \src "ls180.v:199.13-199.49"
+ attribute \src "ls180.v:203.13-203.49"
wire width 64 \interface0_converted_interface_dat_w
- attribute \src "ls180.v:208.5-208.39"
+ attribute \src "ls180.v:212.5-212.39"
wire \interface0_converted_interface_err
- attribute \src "ls180.v:201.12-201.46"
+ attribute \src "ls180.v:205.12-205.46"
wire width 8 \interface0_converted_interface_sel
- attribute \src "ls180.v:203.6-203.40"
+ attribute \src "ls180.v:207.6-207.40"
wire \interface0_converted_interface_stb
- attribute \src "ls180.v:205.6-205.39"
+ attribute \src "ls180.v:209.6-209.39"
wire \interface0_converted_interface_we
- attribute \src "ls180.v:219.5-219.39"
+ attribute \src "ls180.v:223.5-223.39"
wire \interface1_converted_interface_ack
- attribute \src "ls180.v:213.13-213.47"
+ attribute \src "ls180.v:217.13-217.47"
wire width 30 \interface1_converted_interface_adr
- attribute \src "ls180.v:222.12-222.46"
+ attribute \src "ls180.v:226.12-226.46"
wire width 2 \interface1_converted_interface_bte
- attribute \src "ls180.v:221.12-221.46"
+ attribute \src "ls180.v:225.12-225.46"
wire width 3 \interface1_converted_interface_cti
- attribute \src "ls180.v:217.6-217.40"
+ attribute \src "ls180.v:221.6-221.40"
wire \interface1_converted_interface_cyc
- attribute \src "ls180.v:215.13-215.49"
+ attribute \src "ls180.v:219.13-219.49"
wire width 64 \interface1_converted_interface_dat_r
- attribute \src "ls180.v:214.13-214.49"
+ attribute \src "ls180.v:218.13-218.49"
wire width 64 \interface1_converted_interface_dat_w
- attribute \src "ls180.v:223.5-223.39"
+ attribute \src "ls180.v:227.5-227.39"
wire \interface1_converted_interface_err
- attribute \src "ls180.v:216.12-216.46"
+ attribute \src "ls180.v:220.12-220.46"
wire width 8 \interface1_converted_interface_sel
- attribute \src "ls180.v:218.6-218.40"
+ attribute \src "ls180.v:222.6-222.40"
wire \interface1_converted_interface_stb
- attribute \src "ls180.v:220.6-220.39"
+ attribute \src "ls180.v:224.6-224.39"
wire \interface1_converted_interface_we
- attribute \src "ls180.v:864.6-864.9"
+ attribute \src "ls180.v:868.6-868.9"
wire \irq
- attribute \src "ls180.v:37.13-37.21"
- wire input 33 \jtag_tck
+ attribute \src "ls180.v:39.13-39.21"
+ wire input 35 \jtag_tck
+ attribute \src "ls180.v:40.13-40.21"
+ wire input 36 \jtag_tdi
+ attribute \src "ls180.v:41.14-41.22"
+ wire output 37 \jtag_tdo
attribute \src "ls180.v:38.13-38.21"
- wire input 34 \jtag_tdi
- attribute \src "ls180.v:39.14-39.22"
- wire output 35 \jtag_tdo
- attribute \src "ls180.v:36.13-36.21"
- wire input 32 \jtag_tms
- attribute \src "ls180.v:152.12-152.27"
+ wire input 34 \jtag_tms
+ attribute \src "ls180.v:156.12-156.27"
wire width 6 \libresocsim_adr
- attribute \src "ls180.v:50.6-50.27"
+ attribute \src "ls180.v:52.6-52.27"
wire \libresocsim_bus_error
- attribute \src "ls180.v:51.12-51.34"
+ attribute \src "ls180.v:53.12-53.34"
wire width 32 \libresocsim_bus_errors
- attribute \src "ls180.v:47.13-47.42"
+ attribute \src "ls180.v:49.13-49.42"
wire width 32 \libresocsim_bus_errors_status
- attribute \src "ls180.v:48.6-48.31"
+ attribute \src "ls180.v:50.6-50.31"
wire \libresocsim_bus_errors_we
- attribute \src "ls180.v:1092.12-1092.29"
+ attribute \src "ls180.v:1097.12-1097.29"
wire width 20 \libresocsim_count
- attribute \src "ls180.v:1333.13-1333.45"
+ attribute \src "ls180.v:1338.13-1338.45"
wire width 14 \libresocsim_csr_interconnect_adr
- attribute \src "ls180.v:1336.12-1336.46"
+ attribute \src "ls180.v:1341.12-1341.46"
wire width 8 \libresocsim_csr_interconnect_dat_r
- attribute \src "ls180.v:1335.12-1335.46"
+ attribute \src "ls180.v:1340.12-1340.46"
wire width 8 \libresocsim_csr_interconnect_dat_w
- attribute \src "ls180.v:1334.6-1334.37"
+ attribute \src "ls180.v:1339.6-1339.37"
wire \libresocsim_csr_interconnect_we
- attribute \src "ls180.v:1130.12-1130.46"
+ attribute \src "ls180.v:1135.12-1135.46"
wire width 8 \libresocsim_csrbank0_bus_errors0_r
- attribute \src "ls180.v:1129.6-1129.41"
+ attribute \src "ls180.v:1134.6-1134.41"
wire \libresocsim_csrbank0_bus_errors0_re
- attribute \src "ls180.v:1132.12-1132.46"
+ attribute \src "ls180.v:1137.12-1137.46"
wire width 8 \libresocsim_csrbank0_bus_errors0_w
- attribute \src "ls180.v:1131.6-1131.41"
+ attribute \src "ls180.v:1136.6-1136.41"
wire \libresocsim_csrbank0_bus_errors0_we
- attribute \src "ls180.v:1126.12-1126.46"
+ attribute \src "ls180.v:1131.12-1131.46"
wire width 8 \libresocsim_csrbank0_bus_errors1_r
- attribute \src "ls180.v:1125.6-1125.41"
+ attribute \src "ls180.v:1130.6-1130.41"
wire \libresocsim_csrbank0_bus_errors1_re
- attribute \src "ls180.v:1128.12-1128.46"
+ attribute \src "ls180.v:1133.12-1133.46"
wire width 8 \libresocsim_csrbank0_bus_errors1_w
- attribute \src "ls180.v:1127.6-1127.41"
+ attribute \src "ls180.v:1132.6-1132.41"
wire \libresocsim_csrbank0_bus_errors1_we
- attribute \src "ls180.v:1122.12-1122.46"
+ attribute \src "ls180.v:1127.12-1127.46"
wire width 8 \libresocsim_csrbank0_bus_errors2_r
- attribute \src "ls180.v:1121.6-1121.41"
+ attribute \src "ls180.v:1126.6-1126.41"
wire \libresocsim_csrbank0_bus_errors2_re
- attribute \src "ls180.v:1124.12-1124.46"
+ attribute \src "ls180.v:1129.12-1129.46"
wire width 8 \libresocsim_csrbank0_bus_errors2_w
- attribute \src "ls180.v:1123.6-1123.41"
+ attribute \src "ls180.v:1128.6-1128.41"
wire \libresocsim_csrbank0_bus_errors2_we
- attribute \src "ls180.v:1118.12-1118.46"
+ attribute \src "ls180.v:1123.12-1123.46"
wire width 8 \libresocsim_csrbank0_bus_errors3_r
- attribute \src "ls180.v:1117.6-1117.41"
+ attribute \src "ls180.v:1122.6-1122.41"
wire \libresocsim_csrbank0_bus_errors3_re
- attribute \src "ls180.v:1120.12-1120.46"
+ attribute \src "ls180.v:1125.12-1125.46"
wire width 8 \libresocsim_csrbank0_bus_errors3_w
- attribute \src "ls180.v:1119.6-1119.41"
+ attribute \src "ls180.v:1124.6-1124.41"
wire \libresocsim_csrbank0_bus_errors3_we
- attribute \src "ls180.v:1098.6-1098.35"
+ attribute \src "ls180.v:1103.6-1103.35"
wire \libresocsim_csrbank0_reset0_r
- attribute \src "ls180.v:1097.6-1097.36"
+ attribute \src "ls180.v:1102.6-1102.36"
wire \libresocsim_csrbank0_reset0_re
- attribute \src "ls180.v:1100.6-1100.35"
+ attribute \src "ls180.v:1105.6-1105.35"
wire \libresocsim_csrbank0_reset0_w
- attribute \src "ls180.v:1099.6-1099.36"
+ attribute \src "ls180.v:1104.6-1104.36"
wire \libresocsim_csrbank0_reset0_we
- attribute \src "ls180.v:1114.12-1114.43"
+ attribute \src "ls180.v:1119.12-1119.43"
wire width 8 \libresocsim_csrbank0_scratch0_r
- attribute \src "ls180.v:1113.6-1113.38"
+ attribute \src "ls180.v:1118.6-1118.38"
wire \libresocsim_csrbank0_scratch0_re
- attribute \src "ls180.v:1116.12-1116.43"
+ attribute \src "ls180.v:1121.12-1121.43"
wire width 8 \libresocsim_csrbank0_scratch0_w
- attribute \src "ls180.v:1115.6-1115.38"
+ attribute \src "ls180.v:1120.6-1120.38"
wire \libresocsim_csrbank0_scratch0_we
- attribute \src "ls180.v:1110.12-1110.43"
+ attribute \src "ls180.v:1115.12-1115.43"
wire width 8 \libresocsim_csrbank0_scratch1_r
- attribute \src "ls180.v:1109.6-1109.38"
+ attribute \src "ls180.v:1114.6-1114.38"
wire \libresocsim_csrbank0_scratch1_re
- attribute \src "ls180.v:1112.12-1112.43"
+ attribute \src "ls180.v:1117.12-1117.43"
wire width 8 \libresocsim_csrbank0_scratch1_w
- attribute \src "ls180.v:1111.6-1111.38"
+ attribute \src "ls180.v:1116.6-1116.38"
wire \libresocsim_csrbank0_scratch1_we
- attribute \src "ls180.v:1106.12-1106.43"
+ attribute \src "ls180.v:1111.12-1111.43"
wire width 8 \libresocsim_csrbank0_scratch2_r
- attribute \src "ls180.v:1105.6-1105.38"
+ attribute \src "ls180.v:1110.6-1110.38"
wire \libresocsim_csrbank0_scratch2_re
- attribute \src "ls180.v:1108.12-1108.43"
+ attribute \src "ls180.v:1113.12-1113.43"
wire width 8 \libresocsim_csrbank0_scratch2_w
- attribute \src "ls180.v:1107.6-1107.38"
+ attribute \src "ls180.v:1112.6-1112.38"
wire \libresocsim_csrbank0_scratch2_we
- attribute \src "ls180.v:1102.12-1102.43"
+ attribute \src "ls180.v:1107.12-1107.43"
wire width 8 \libresocsim_csrbank0_scratch3_r
- attribute \src "ls180.v:1101.6-1101.38"
+ attribute \src "ls180.v:1106.6-1106.38"
wire \libresocsim_csrbank0_scratch3_re
- attribute \src "ls180.v:1104.12-1104.43"
+ attribute \src "ls180.v:1109.12-1109.43"
wire width 8 \libresocsim_csrbank0_scratch3_w
- attribute \src "ls180.v:1103.6-1103.38"
+ attribute \src "ls180.v:1108.6-1108.38"
wire \libresocsim_csrbank0_scratch3_we
- attribute \src "ls180.v:1133.6-1133.30"
+ attribute \src "ls180.v:1138.6-1138.30"
wire \libresocsim_csrbank0_sel
- attribute \src "ls180.v:1143.12-1143.37"
+ attribute \src "ls180.v:1148.12-1148.37"
wire width 8 \libresocsim_csrbank1_in_r
- attribute \src "ls180.v:1142.6-1142.32"
+ attribute \src "ls180.v:1147.6-1147.32"
wire \libresocsim_csrbank1_in_re
- attribute \src "ls180.v:1145.12-1145.37"
+ attribute \src "ls180.v:1150.12-1150.37"
wire width 8 \libresocsim_csrbank1_in_w
- attribute \src "ls180.v:1144.6-1144.32"
+ attribute \src "ls180.v:1149.6-1149.32"
wire \libresocsim_csrbank1_in_we
- attribute \src "ls180.v:1139.12-1139.38"
+ attribute \src "ls180.v:1144.12-1144.38"
wire width 8 \libresocsim_csrbank1_oe0_r
- attribute \src "ls180.v:1138.6-1138.33"
+ attribute \src "ls180.v:1143.6-1143.33"
wire \libresocsim_csrbank1_oe0_re
- attribute \src "ls180.v:1141.12-1141.38"
+ attribute \src "ls180.v:1146.12-1146.38"
wire width 8 \libresocsim_csrbank1_oe0_w
- attribute \src "ls180.v:1140.6-1140.33"
+ attribute \src "ls180.v:1145.6-1145.33"
wire \libresocsim_csrbank1_oe0_we
- attribute \src "ls180.v:1147.12-1147.39"
+ attribute \src "ls180.v:1152.12-1152.39"
wire width 8 \libresocsim_csrbank1_out0_r
- attribute \src "ls180.v:1146.6-1146.34"
+ attribute \src "ls180.v:1151.6-1151.34"
wire \libresocsim_csrbank1_out0_re
- attribute \src "ls180.v:1149.12-1149.39"
+ attribute \src "ls180.v:1154.12-1154.39"
wire width 8 \libresocsim_csrbank1_out0_w
- attribute \src "ls180.v:1148.6-1148.34"
+ attribute \src "ls180.v:1153.6-1153.34"
wire \libresocsim_csrbank1_out0_we
- attribute \src "ls180.v:1150.6-1150.30"
+ attribute \src "ls180.v:1155.6-1155.30"
wire \libresocsim_csrbank1_sel
- attribute \src "ls180.v:1160.12-1160.37"
+ attribute \src "ls180.v:1165.12-1165.37"
wire width 8 \libresocsim_csrbank2_in_r
- attribute \src "ls180.v:1159.6-1159.32"
+ attribute \src "ls180.v:1164.6-1164.32"
wire \libresocsim_csrbank2_in_re
- attribute \src "ls180.v:1162.12-1162.37"
+ attribute \src "ls180.v:1167.12-1167.37"
wire width 8 \libresocsim_csrbank2_in_w
- attribute \src "ls180.v:1161.6-1161.32"
+ attribute \src "ls180.v:1166.6-1166.32"
wire \libresocsim_csrbank2_in_we
- attribute \src "ls180.v:1156.12-1156.38"
+ attribute \src "ls180.v:1161.12-1161.38"
wire width 8 \libresocsim_csrbank2_oe0_r
- attribute \src "ls180.v:1155.6-1155.33"
+ attribute \src "ls180.v:1160.6-1160.33"
wire \libresocsim_csrbank2_oe0_re
- attribute \src "ls180.v:1158.12-1158.38"
+ attribute \src "ls180.v:1163.12-1163.38"
wire width 8 \libresocsim_csrbank2_oe0_w
- attribute \src "ls180.v:1157.6-1157.33"
+ attribute \src "ls180.v:1162.6-1162.33"
wire \libresocsim_csrbank2_oe0_we
- attribute \src "ls180.v:1164.12-1164.39"
+ attribute \src "ls180.v:1169.12-1169.39"
wire width 8 \libresocsim_csrbank2_out0_r
- attribute \src "ls180.v:1163.6-1163.34"
+ attribute \src "ls180.v:1168.6-1168.34"
wire \libresocsim_csrbank2_out0_re
- attribute \src "ls180.v:1166.12-1166.39"
+ attribute \src "ls180.v:1171.12-1171.39"
wire width 8 \libresocsim_csrbank2_out0_w
- attribute \src "ls180.v:1165.6-1165.34"
+ attribute \src "ls180.v:1170.6-1170.34"
wire \libresocsim_csrbank2_out0_we
- attribute \src "ls180.v:1167.6-1167.30"
+ attribute \src "ls180.v:1172.6-1172.30"
wire \libresocsim_csrbank2_sel
- attribute \src "ls180.v:1177.6-1177.30"
+ attribute \src "ls180.v:1182.6-1182.30"
wire \libresocsim_csrbank3_r_r
- attribute \src "ls180.v:1176.6-1176.31"
+ attribute \src "ls180.v:1181.6-1181.31"
wire \libresocsim_csrbank3_r_re
- attribute \src "ls180.v:1179.6-1179.30"
+ attribute \src "ls180.v:1184.6-1184.30"
wire \libresocsim_csrbank3_r_w
- attribute \src "ls180.v:1178.6-1178.31"
+ attribute \src "ls180.v:1183.6-1183.31"
wire \libresocsim_csrbank3_r_we
- attribute \src "ls180.v:1180.6-1180.30"
+ attribute \src "ls180.v:1185.6-1185.30"
wire \libresocsim_csrbank3_sel
- attribute \src "ls180.v:1173.12-1173.37"
+ attribute \src "ls180.v:1178.12-1178.37"
wire width 3 \libresocsim_csrbank3_w0_r
- attribute \src "ls180.v:1172.6-1172.32"
+ attribute \src "ls180.v:1177.6-1177.32"
wire \libresocsim_csrbank3_w0_re
- attribute \src "ls180.v:1175.12-1175.37"
+ attribute \src "ls180.v:1180.12-1180.37"
wire width 3 \libresocsim_csrbank3_w0_w
- attribute \src "ls180.v:1174.6-1174.32"
+ attribute \src "ls180.v:1179.6-1179.32"
wire \libresocsim_csrbank3_w0_we
- attribute \src "ls180.v:1186.12-1186.48"
+ attribute \src "ls180.v:1191.12-1191.48"
wire width 4 \libresocsim_csrbank4_dfii_control0_r
- attribute \src "ls180.v:1185.6-1185.43"
+ attribute \src "ls180.v:1190.6-1190.43"
wire \libresocsim_csrbank4_dfii_control0_re
- attribute \src "ls180.v:1188.12-1188.48"
+ attribute \src "ls180.v:1193.12-1193.48"
wire width 4 \libresocsim_csrbank4_dfii_control0_w
- attribute \src "ls180.v:1187.6-1187.43"
+ attribute \src "ls180.v:1192.6-1192.43"
wire \libresocsim_csrbank4_dfii_control0_we
- attribute \src "ls180.v:1198.12-1198.52"
+ attribute \src "ls180.v:1203.12-1203.52"
wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_r
- attribute \src "ls180.v:1197.6-1197.47"
+ attribute \src "ls180.v:1202.6-1202.47"
wire \libresocsim_csrbank4_dfii_pi0_address0_re
- attribute \src "ls180.v:1200.12-1200.52"
+ attribute \src "ls180.v:1205.12-1205.52"
wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_w
- attribute \src "ls180.v:1199.6-1199.47"
+ attribute \src "ls180.v:1204.6-1204.47"
wire \libresocsim_csrbank4_dfii_pi0_address0_we
- attribute \src "ls180.v:1194.12-1194.52"
+ attribute \src "ls180.v:1199.12-1199.52"
wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_r
- attribute \src "ls180.v:1193.6-1193.47"
+ attribute \src "ls180.v:1198.6-1198.47"
wire \libresocsim_csrbank4_dfii_pi0_address1_re
- attribute \src "ls180.v:1196.12-1196.52"
+ attribute \src "ls180.v:1201.12-1201.52"
wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_w
- attribute \src "ls180.v:1195.6-1195.47"
+ attribute \src "ls180.v:1200.6-1200.47"
wire \libresocsim_csrbank4_dfii_pi0_address1_we
- attribute \src "ls180.v:1202.12-1202.53"
+ attribute \src "ls180.v:1207.12-1207.53"
wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_r
- attribute \src "ls180.v:1201.6-1201.48"
+ attribute \src "ls180.v:1206.6-1206.48"
wire \libresocsim_csrbank4_dfii_pi0_baddress0_re
- attribute \src "ls180.v:1204.12-1204.53"
+ attribute \src "ls180.v:1209.12-1209.53"
wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_w
- attribute \src "ls180.v:1203.6-1203.48"
+ attribute \src "ls180.v:1208.6-1208.48"
wire \libresocsim_csrbank4_dfii_pi0_baddress0_we
- attribute \src "ls180.v:1190.12-1190.52"
+ attribute \src "ls180.v:1195.12-1195.52"
wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_r
- attribute \src "ls180.v:1189.6-1189.47"
+ attribute \src "ls180.v:1194.6-1194.47"
wire \libresocsim_csrbank4_dfii_pi0_command0_re
- attribute \src "ls180.v:1192.12-1192.52"
+ attribute \src "ls180.v:1197.12-1197.52"
wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_w
- attribute \src "ls180.v:1191.6-1191.47"
+ attribute \src "ls180.v:1196.6-1196.47"
wire \libresocsim_csrbank4_dfii_pi0_command0_we
- attribute \src "ls180.v:1218.12-1218.51"
+ attribute \src "ls180.v:1223.12-1223.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_r
- attribute \src "ls180.v:1217.6-1217.46"
+ attribute \src "ls180.v:1222.6-1222.46"
wire \libresocsim_csrbank4_dfii_pi0_rddata0_re
- attribute \src "ls180.v:1220.12-1220.51"
+ attribute \src "ls180.v:1225.12-1225.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_w
- attribute \src "ls180.v:1219.6-1219.46"
+ attribute \src "ls180.v:1224.6-1224.46"
wire \libresocsim_csrbank4_dfii_pi0_rddata0_we
- attribute \src "ls180.v:1214.12-1214.51"
+ attribute \src "ls180.v:1219.12-1219.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_r
- attribute \src "ls180.v:1213.6-1213.46"
+ attribute \src "ls180.v:1218.6-1218.46"
wire \libresocsim_csrbank4_dfii_pi0_rddata1_re
- attribute \src "ls180.v:1216.12-1216.51"
+ attribute \src "ls180.v:1221.12-1221.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_w
- attribute \src "ls180.v:1215.6-1215.46"
+ attribute \src "ls180.v:1220.6-1220.46"
wire \libresocsim_csrbank4_dfii_pi0_rddata1_we
- attribute \src "ls180.v:1210.12-1210.51"
+ attribute \src "ls180.v:1215.12-1215.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_r
- attribute \src "ls180.v:1209.6-1209.46"
+ attribute \src "ls180.v:1214.6-1214.46"
wire \libresocsim_csrbank4_dfii_pi0_wrdata0_re
- attribute \src "ls180.v:1212.12-1212.51"
+ attribute \src "ls180.v:1217.12-1217.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_w
- attribute \src "ls180.v:1211.6-1211.46"
+ attribute \src "ls180.v:1216.6-1216.46"
wire \libresocsim_csrbank4_dfii_pi0_wrdata0_we
- attribute \src "ls180.v:1206.12-1206.51"
+ attribute \src "ls180.v:1211.12-1211.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_r
- attribute \src "ls180.v:1205.6-1205.46"
+ attribute \src "ls180.v:1210.6-1210.46"
wire \libresocsim_csrbank4_dfii_pi0_wrdata1_re
- attribute \src "ls180.v:1208.12-1208.51"
+ attribute \src "ls180.v:1213.12-1213.51"
wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_w
- attribute \src "ls180.v:1207.6-1207.46"
+ attribute \src "ls180.v:1212.6-1212.46"
wire \libresocsim_csrbank4_dfii_pi0_wrdata1_we
- attribute \src "ls180.v:1221.6-1221.30"
+ attribute \src "ls180.v:1226.6-1226.30"
wire \libresocsim_csrbank4_sel
- attribute \src "ls180.v:1259.6-1259.32"
+ attribute \src "ls180.v:1264.6-1264.32"
wire \libresocsim_csrbank5_en0_r
- attribute \src "ls180.v:1258.6-1258.33"
+ attribute \src "ls180.v:1263.6-1263.33"
wire \libresocsim_csrbank5_en0_re
- attribute \src "ls180.v:1261.6-1261.32"
+ attribute \src "ls180.v:1266.6-1266.32"
wire \libresocsim_csrbank5_en0_w
- attribute \src "ls180.v:1260.6-1260.33"
+ attribute \src "ls180.v:1265.6-1265.33"
wire \libresocsim_csrbank5_en0_we
- attribute \src "ls180.v:1283.6-1283.39"
+ attribute \src "ls180.v:1288.6-1288.39"
wire \libresocsim_csrbank5_ev_enable0_r
- attribute \src "ls180.v:1282.6-1282.40"
+ attribute \src "ls180.v:1287.6-1287.40"
wire \libresocsim_csrbank5_ev_enable0_re
- attribute \src "ls180.v:1285.6-1285.39"
+ attribute \src "ls180.v:1290.6-1290.39"
wire \libresocsim_csrbank5_ev_enable0_w
- attribute \src "ls180.v:1284.6-1284.40"
+ attribute \src "ls180.v:1289.6-1289.40"
wire \libresocsim_csrbank5_ev_enable0_we
- attribute \src "ls180.v:1239.12-1239.40"
+ attribute \src "ls180.v:1244.12-1244.40"
wire width 8 \libresocsim_csrbank5_load0_r
- attribute \src "ls180.v:1238.6-1238.35"
+ attribute \src "ls180.v:1243.6-1243.35"
wire \libresocsim_csrbank5_load0_re
- attribute \src "ls180.v:1241.12-1241.40"
+ attribute \src "ls180.v:1246.12-1246.40"
wire width 8 \libresocsim_csrbank5_load0_w
- attribute \src "ls180.v:1240.6-1240.35"
+ attribute \src "ls180.v:1245.6-1245.35"
wire \libresocsim_csrbank5_load0_we
- attribute \src "ls180.v:1235.12-1235.40"
+ attribute \src "ls180.v:1240.12-1240.40"
wire width 8 \libresocsim_csrbank5_load1_r
- attribute \src "ls180.v:1234.6-1234.35"
+ attribute \src "ls180.v:1239.6-1239.35"
wire \libresocsim_csrbank5_load1_re
- attribute \src "ls180.v:1237.12-1237.40"
+ attribute \src "ls180.v:1242.12-1242.40"
wire width 8 \libresocsim_csrbank5_load1_w
- attribute \src "ls180.v:1236.6-1236.35"
+ attribute \src "ls180.v:1241.6-1241.35"
wire \libresocsim_csrbank5_load1_we
- attribute \src "ls180.v:1231.12-1231.40"
+ attribute \src "ls180.v:1236.12-1236.40"
wire width 8 \libresocsim_csrbank5_load2_r
- attribute \src "ls180.v:1230.6-1230.35"
+ attribute \src "ls180.v:1235.6-1235.35"
wire \libresocsim_csrbank5_load2_re
- attribute \src "ls180.v:1233.12-1233.40"
+ attribute \src "ls180.v:1238.12-1238.40"
wire width 8 \libresocsim_csrbank5_load2_w
- attribute \src "ls180.v:1232.6-1232.35"
+ attribute \src "ls180.v:1237.6-1237.35"
wire \libresocsim_csrbank5_load2_we
- attribute \src "ls180.v:1227.12-1227.40"
+ attribute \src "ls180.v:1232.12-1232.40"
wire width 8 \libresocsim_csrbank5_load3_r
- attribute \src "ls180.v:1226.6-1226.35"
+ attribute \src "ls180.v:1231.6-1231.35"
wire \libresocsim_csrbank5_load3_re
- attribute \src "ls180.v:1229.12-1229.40"
+ attribute \src "ls180.v:1234.12-1234.40"
wire width 8 \libresocsim_csrbank5_load3_w
- attribute \src "ls180.v:1228.6-1228.35"
+ attribute \src "ls180.v:1233.6-1233.35"
wire \libresocsim_csrbank5_load3_we
- attribute \src "ls180.v:1255.12-1255.42"
+ attribute \src "ls180.v:1260.12-1260.42"
wire width 8 \libresocsim_csrbank5_reload0_r
- attribute \src "ls180.v:1254.6-1254.37"
+ attribute \src "ls180.v:1259.6-1259.37"
wire \libresocsim_csrbank5_reload0_re
- attribute \src "ls180.v:1257.12-1257.42"
+ attribute \src "ls180.v:1262.12-1262.42"
wire width 8 \libresocsim_csrbank5_reload0_w
- attribute \src "ls180.v:1256.6-1256.37"
+ attribute \src "ls180.v:1261.6-1261.37"
wire \libresocsim_csrbank5_reload0_we
- attribute \src "ls180.v:1251.12-1251.42"
+ attribute \src "ls180.v:1256.12-1256.42"
wire width 8 \libresocsim_csrbank5_reload1_r
- attribute \src "ls180.v:1250.6-1250.37"
+ attribute \src "ls180.v:1255.6-1255.37"
wire \libresocsim_csrbank5_reload1_re
- attribute \src "ls180.v:1253.12-1253.42"
+ attribute \src "ls180.v:1258.12-1258.42"
wire width 8 \libresocsim_csrbank5_reload1_w
- attribute \src "ls180.v:1252.6-1252.37"
+ attribute \src "ls180.v:1257.6-1257.37"
wire \libresocsim_csrbank5_reload1_we
- attribute \src "ls180.v:1247.12-1247.42"
+ attribute \src "ls180.v:1252.12-1252.42"
wire width 8 \libresocsim_csrbank5_reload2_r
- attribute \src "ls180.v:1246.6-1246.37"
+ attribute \src "ls180.v:1251.6-1251.37"
wire \libresocsim_csrbank5_reload2_re
- attribute \src "ls180.v:1249.12-1249.42"
+ attribute \src "ls180.v:1254.12-1254.42"
wire width 8 \libresocsim_csrbank5_reload2_w
- attribute \src "ls180.v:1248.6-1248.37"
+ attribute \src "ls180.v:1253.6-1253.37"
wire \libresocsim_csrbank5_reload2_we
- attribute \src "ls180.v:1243.12-1243.42"
+ attribute \src "ls180.v:1248.12-1248.42"
wire width 8 \libresocsim_csrbank5_reload3_r
- attribute \src "ls180.v:1242.6-1242.37"
+ attribute \src "ls180.v:1247.6-1247.37"
wire \libresocsim_csrbank5_reload3_re
- attribute \src "ls180.v:1245.12-1245.42"
+ attribute \src "ls180.v:1250.12-1250.42"
wire width 8 \libresocsim_csrbank5_reload3_w
- attribute \src "ls180.v:1244.6-1244.37"
+ attribute \src "ls180.v:1249.6-1249.37"
wire \libresocsim_csrbank5_reload3_we
- attribute \src "ls180.v:1286.6-1286.30"
+ attribute \src "ls180.v:1291.6-1291.30"
wire \libresocsim_csrbank5_sel
- attribute \src "ls180.v:1263.6-1263.42"
+ attribute \src "ls180.v:1268.6-1268.42"
wire \libresocsim_csrbank5_update_value0_r
- attribute \src "ls180.v:1262.6-1262.43"
+ attribute \src "ls180.v:1267.6-1267.43"
wire \libresocsim_csrbank5_update_value0_re
- attribute \src "ls180.v:1265.6-1265.42"
+ attribute \src "ls180.v:1270.6-1270.42"
wire \libresocsim_csrbank5_update_value0_w
- attribute \src "ls180.v:1264.6-1264.43"
+ attribute \src "ls180.v:1269.6-1269.43"
wire \libresocsim_csrbank5_update_value0_we
- attribute \src "ls180.v:1279.12-1279.41"
+ attribute \src "ls180.v:1284.12-1284.41"
wire width 8 \libresocsim_csrbank5_value0_r
- attribute \src "ls180.v:1278.6-1278.36"
+ attribute \src "ls180.v:1283.6-1283.36"
wire \libresocsim_csrbank5_value0_re
- attribute \src "ls180.v:1281.12-1281.41"
+ attribute \src "ls180.v:1286.12-1286.41"
wire width 8 \libresocsim_csrbank5_value0_w
- attribute \src "ls180.v:1280.6-1280.36"
+ attribute \src "ls180.v:1285.6-1285.36"
wire \libresocsim_csrbank5_value0_we
- attribute \src "ls180.v:1275.12-1275.41"
+ attribute \src "ls180.v:1280.12-1280.41"
wire width 8 \libresocsim_csrbank5_value1_r
- attribute \src "ls180.v:1274.6-1274.36"
+ attribute \src "ls180.v:1279.6-1279.36"
wire \libresocsim_csrbank5_value1_re
- attribute \src "ls180.v:1277.12-1277.41"
+ attribute \src "ls180.v:1282.12-1282.41"
wire width 8 \libresocsim_csrbank5_value1_w
- attribute \src "ls180.v:1276.6-1276.36"
+ attribute \src "ls180.v:1281.6-1281.36"
wire \libresocsim_csrbank5_value1_we
- attribute \src "ls180.v:1271.12-1271.41"
+ attribute \src "ls180.v:1276.12-1276.41"
wire width 8 \libresocsim_csrbank5_value2_r
- attribute \src "ls180.v:1270.6-1270.36"
+ attribute \src "ls180.v:1275.6-1275.36"
wire \libresocsim_csrbank5_value2_re
- attribute \src "ls180.v:1273.12-1273.41"
+ attribute \src "ls180.v:1278.12-1278.41"
wire width 8 \libresocsim_csrbank5_value2_w
- attribute \src "ls180.v:1272.6-1272.36"
+ attribute \src "ls180.v:1277.6-1277.36"
wire \libresocsim_csrbank5_value2_we
- attribute \src "ls180.v:1267.12-1267.41"
+ attribute \src "ls180.v:1272.12-1272.41"
wire width 8 \libresocsim_csrbank5_value3_r
- attribute \src "ls180.v:1266.6-1266.36"
+ attribute \src "ls180.v:1271.6-1271.36"
wire \libresocsim_csrbank5_value3_re
- attribute \src "ls180.v:1269.12-1269.41"
+ attribute \src "ls180.v:1274.12-1274.41"
wire width 8 \libresocsim_csrbank5_value3_w
- attribute \src "ls180.v:1268.6-1268.36"
+ attribute \src "ls180.v:1273.6-1273.36"
wire \libresocsim_csrbank5_value3_we
- attribute \src "ls180.v:1300.12-1300.45"
+ attribute \src "ls180.v:1305.12-1305.45"
wire width 2 \libresocsim_csrbank6_ev_enable0_r
- attribute \src "ls180.v:1299.6-1299.40"
+ attribute \src "ls180.v:1304.6-1304.40"
wire \libresocsim_csrbank6_ev_enable0_re
- attribute \src "ls180.v:1302.12-1302.45"
+ attribute \src "ls180.v:1307.12-1307.45"
wire width 2 \libresocsim_csrbank6_ev_enable0_w
- attribute \src "ls180.v:1301.6-1301.40"
+ attribute \src "ls180.v:1306.6-1306.40"
wire \libresocsim_csrbank6_ev_enable0_we
- attribute \src "ls180.v:1296.6-1296.36"
+ attribute \src "ls180.v:1301.6-1301.36"
wire \libresocsim_csrbank6_rxempty_r
- attribute \src "ls180.v:1295.6-1295.37"
+ attribute \src "ls180.v:1300.6-1300.37"
wire \libresocsim_csrbank6_rxempty_re
- attribute \src "ls180.v:1298.6-1298.36"
+ attribute \src "ls180.v:1303.6-1303.36"
wire \libresocsim_csrbank6_rxempty_w
- attribute \src "ls180.v:1297.6-1297.37"
+ attribute \src "ls180.v:1302.6-1302.37"
wire \libresocsim_csrbank6_rxempty_we
- attribute \src "ls180.v:1308.6-1308.35"
+ attribute \src "ls180.v:1313.6-1313.35"
wire \libresocsim_csrbank6_rxfull_r
- attribute \src "ls180.v:1307.6-1307.36"
+ attribute \src "ls180.v:1312.6-1312.36"
wire \libresocsim_csrbank6_rxfull_re
- attribute \src "ls180.v:1310.6-1310.35"
+ attribute \src "ls180.v:1315.6-1315.35"
wire \libresocsim_csrbank6_rxfull_w
- attribute \src "ls180.v:1309.6-1309.36"
+ attribute \src "ls180.v:1314.6-1314.36"
wire \libresocsim_csrbank6_rxfull_we
- attribute \src "ls180.v:1311.6-1311.30"
+ attribute \src "ls180.v:1316.6-1316.30"
wire \libresocsim_csrbank6_sel
- attribute \src "ls180.v:1304.6-1304.36"
+ attribute \src "ls180.v:1309.6-1309.36"
wire \libresocsim_csrbank6_txempty_r
- attribute \src "ls180.v:1303.6-1303.37"
+ attribute \src "ls180.v:1308.6-1308.37"
wire \libresocsim_csrbank6_txempty_re
- attribute \src "ls180.v:1306.6-1306.36"
+ attribute \src "ls180.v:1311.6-1311.36"
wire \libresocsim_csrbank6_txempty_w
- attribute \src "ls180.v:1305.6-1305.37"
+ attribute \src "ls180.v:1310.6-1310.37"
wire \libresocsim_csrbank6_txempty_we
- attribute \src "ls180.v:1292.6-1292.35"
+ attribute \src "ls180.v:1297.6-1297.35"
wire \libresocsim_csrbank6_txfull_r
- attribute \src "ls180.v:1291.6-1291.36"
+ attribute \src "ls180.v:1296.6-1296.36"
wire \libresocsim_csrbank6_txfull_re
- attribute \src "ls180.v:1294.6-1294.35"
+ attribute \src "ls180.v:1299.6-1299.35"
wire \libresocsim_csrbank6_txfull_w
- attribute \src "ls180.v:1293.6-1293.36"
+ attribute \src "ls180.v:1298.6-1298.36"
wire \libresocsim_csrbank6_txfull_we
- attribute \src "ls180.v:1332.6-1332.30"
+ attribute \src "ls180.v:1337.6-1337.30"
wire \libresocsim_csrbank7_sel
- attribute \src "ls180.v:1329.12-1329.47"
+ attribute \src "ls180.v:1334.12-1334.47"
wire width 8 \libresocsim_csrbank7_tuning_word0_r
- attribute \src "ls180.v:1328.6-1328.42"
+ attribute \src "ls180.v:1333.6-1333.42"
wire \libresocsim_csrbank7_tuning_word0_re
- attribute \src "ls180.v:1331.12-1331.47"
+ attribute \src "ls180.v:1336.12-1336.47"
wire width 8 \libresocsim_csrbank7_tuning_word0_w
- attribute \src "ls180.v:1330.6-1330.42"
+ attribute \src "ls180.v:1335.6-1335.42"
wire \libresocsim_csrbank7_tuning_word0_we
- attribute \src "ls180.v:1325.12-1325.47"
+ attribute \src "ls180.v:1330.12-1330.47"
wire width 8 \libresocsim_csrbank7_tuning_word1_r
- attribute \src "ls180.v:1324.6-1324.42"
+ attribute \src "ls180.v:1329.6-1329.42"
wire \libresocsim_csrbank7_tuning_word1_re
- attribute \src "ls180.v:1327.12-1327.47"
+ attribute \src "ls180.v:1332.12-1332.47"
wire width 8 \libresocsim_csrbank7_tuning_word1_w
- attribute \src "ls180.v:1326.6-1326.42"
+ attribute \src "ls180.v:1331.6-1331.42"
wire \libresocsim_csrbank7_tuning_word1_we
- attribute \src "ls180.v:1321.12-1321.47"
+ attribute \src "ls180.v:1326.12-1326.47"
wire width 8 \libresocsim_csrbank7_tuning_word2_r
- attribute \src "ls180.v:1320.6-1320.42"
+ attribute \src "ls180.v:1325.6-1325.42"
wire \libresocsim_csrbank7_tuning_word2_re
- attribute \src "ls180.v:1323.12-1323.47"
+ attribute \src "ls180.v:1328.12-1328.47"
wire width 8 \libresocsim_csrbank7_tuning_word2_w
- attribute \src "ls180.v:1322.6-1322.42"
+ attribute \src "ls180.v:1327.6-1327.42"
wire \libresocsim_csrbank7_tuning_word2_we
- attribute \src "ls180.v:1317.12-1317.47"
+ attribute \src "ls180.v:1322.12-1322.47"
wire width 8 \libresocsim_csrbank7_tuning_word3_r
- attribute \src "ls180.v:1316.6-1316.42"
+ attribute \src "ls180.v:1321.6-1321.42"
wire \libresocsim_csrbank7_tuning_word3_re
- attribute \src "ls180.v:1319.12-1319.47"
+ attribute \src "ls180.v:1324.12-1324.47"
wire width 8 \libresocsim_csrbank7_tuning_word3_w
- attribute \src "ls180.v:1318.6-1318.42"
+ attribute \src "ls180.v:1323.6-1323.42"
wire \libresocsim_csrbank7_tuning_word3_we
- attribute \src "ls180.v:153.13-153.30"
+ attribute \src "ls180.v:157.13-157.30"
wire width 64 \libresocsim_dat_r
- attribute \src "ls180.v:155.13-155.30"
+ attribute \src "ls180.v:159.13-159.30"
wire width 64 \libresocsim_dat_w
- attribute \src "ls180.v:1091.6-1091.22"
+ attribute \src "ls180.v:1096.6-1096.22"
wire \libresocsim_done
- attribute \src "ls180.v:161.5-161.22"
+ attribute \src "ls180.v:165.5-165.22"
wire \libresocsim_en_re
- attribute \src "ls180.v:160.5-160.27"
+ attribute \src "ls180.v:164.5-164.27"
wire \libresocsim_en_storage
- attribute \src "ls180.v:1089.5-1089.22"
+ attribute \src "ls180.v:1094.5-1094.22"
wire \libresocsim_error
- attribute \src "ls180.v:177.6-177.40"
+ attribute \src "ls180.v:181.6-181.40"
wire \libresocsim_eventmanager_pending_r
- attribute \src "ls180.v:176.6-176.41"
+ attribute \src "ls180.v:180.6-180.41"
wire \libresocsim_eventmanager_pending_re
- attribute \src "ls180.v:179.6-179.40"
+ attribute \src "ls180.v:183.6-183.40"
wire \libresocsim_eventmanager_pending_w
- attribute \src "ls180.v:178.6-178.41"
+ attribute \src "ls180.v:182.6-182.41"
wire \libresocsim_eventmanager_pending_we
- attribute \src "ls180.v:181.5-181.32"
+ attribute \src "ls180.v:185.5-185.32"
wire \libresocsim_eventmanager_re
- attribute \src "ls180.v:173.6-173.39"
+ attribute \src "ls180.v:177.6-177.39"
wire \libresocsim_eventmanager_status_r
- attribute \src "ls180.v:172.6-172.40"
+ attribute \src "ls180.v:176.6-176.40"
wire \libresocsim_eventmanager_status_re
- attribute \src "ls180.v:175.6-175.39"
+ attribute \src "ls180.v:179.6-179.39"
wire \libresocsim_eventmanager_status_w
- attribute \src "ls180.v:174.6-174.40"
+ attribute \src "ls180.v:178.6-178.40"
wire \libresocsim_eventmanager_status_we
- attribute \src "ls180.v:180.5-180.37"
+ attribute \src "ls180.v:184.5-184.37"
wire \libresocsim_eventmanager_storage
- attribute \src "ls180.v:1086.11-1086.28"
+ attribute \src "ls180.v:1091.11-1091.28"
wire width 2 \libresocsim_grant
- attribute \src "ls180.v:1093.13-1093.48"
+ attribute \src "ls180.v:1098.13-1098.48"
wire width 14 \libresocsim_interface0_bank_bus_adr
- attribute \src "ls180.v:1096.11-1096.48"
+ attribute \src "ls180.v:1101.11-1101.48"
wire width 8 \libresocsim_interface0_bank_bus_dat_r
- attribute \src "ls180.v:1095.12-1095.49"
+ attribute \src "ls180.v:1100.12-1100.49"
wire width 8 \libresocsim_interface0_bank_bus_dat_w
- attribute \src "ls180.v:1094.6-1094.40"
+ attribute \src "ls180.v:1099.6-1099.40"
wire \libresocsim_interface0_bank_bus_we
- attribute \src "ls180.v:1134.13-1134.48"
+ attribute \src "ls180.v:1139.13-1139.48"
wire width 14 \libresocsim_interface1_bank_bus_adr
- attribute \src "ls180.v:1137.11-1137.48"
+ attribute \src "ls180.v:1142.11-1142.48"
wire width 8 \libresocsim_interface1_bank_bus_dat_r
- attribute \src "ls180.v:1136.12-1136.49"
+ attribute \src "ls180.v:1141.12-1141.49"
wire width 8 \libresocsim_interface1_bank_bus_dat_w
- attribute \src "ls180.v:1135.6-1135.40"
+ attribute \src "ls180.v:1140.6-1140.40"
wire \libresocsim_interface1_bank_bus_we
- attribute \src "ls180.v:1151.13-1151.48"
+ attribute \src "ls180.v:1156.13-1156.48"
wire width 14 \libresocsim_interface2_bank_bus_adr
- attribute \src "ls180.v:1154.11-1154.48"
+ attribute \src "ls180.v:1159.11-1159.48"
wire width 8 \libresocsim_interface2_bank_bus_dat_r
- attribute \src "ls180.v:1153.12-1153.49"
+ attribute \src "ls180.v:1158.12-1158.49"
wire width 8 \libresocsim_interface2_bank_bus_dat_w
- attribute \src "ls180.v:1152.6-1152.40"
+ attribute \src "ls180.v:1157.6-1157.40"
wire \libresocsim_interface2_bank_bus_we
- attribute \src "ls180.v:1168.13-1168.48"
+ attribute \src "ls180.v:1173.13-1173.48"
wire width 14 \libresocsim_interface3_bank_bus_adr
- attribute \src "ls180.v:1171.11-1171.48"
+ attribute \src "ls180.v:1176.11-1176.48"
wire width 8 \libresocsim_interface3_bank_bus_dat_r
- attribute \src "ls180.v:1170.12-1170.49"
+ attribute \src "ls180.v:1175.12-1175.49"
wire width 8 \libresocsim_interface3_bank_bus_dat_w
- attribute \src "ls180.v:1169.6-1169.40"
+ attribute \src "ls180.v:1174.6-1174.40"
wire \libresocsim_interface3_bank_bus_we
- attribute \src "ls180.v:1181.13-1181.48"
+ attribute \src "ls180.v:1186.13-1186.48"
wire width 14 \libresocsim_interface4_bank_bus_adr
- attribute \src "ls180.v:1184.11-1184.48"
+ attribute \src "ls180.v:1189.11-1189.48"
wire width 8 \libresocsim_interface4_bank_bus_dat_r
- attribute \src "ls180.v:1183.12-1183.49"
+ attribute \src "ls180.v:1188.12-1188.49"
wire width 8 \libresocsim_interface4_bank_bus_dat_w
- attribute \src "ls180.v:1182.6-1182.40"
+ attribute \src "ls180.v:1187.6-1187.40"
wire \libresocsim_interface4_bank_bus_we
- attribute \src "ls180.v:1222.13-1222.48"
+ attribute \src "ls180.v:1227.13-1227.48"
wire width 14 \libresocsim_interface5_bank_bus_adr
- attribute \src "ls180.v:1225.11-1225.48"
+ attribute \src "ls180.v:1230.11-1230.48"
wire width 8 \libresocsim_interface5_bank_bus_dat_r
- attribute \src "ls180.v:1224.12-1224.49"
+ attribute \src "ls180.v:1229.12-1229.49"
wire width 8 \libresocsim_interface5_bank_bus_dat_w
- attribute \src "ls180.v:1223.6-1223.40"
+ attribute \src "ls180.v:1228.6-1228.40"
wire \libresocsim_interface5_bank_bus_we
- attribute \src "ls180.v:1287.13-1287.48"
+ attribute \src "ls180.v:1292.13-1292.48"
wire width 14 \libresocsim_interface6_bank_bus_adr
- attribute \src "ls180.v:1290.11-1290.48"
+ attribute \src "ls180.v:1295.11-1295.48"
wire width 8 \libresocsim_interface6_bank_bus_dat_r
- attribute \src "ls180.v:1289.12-1289.49"
+ attribute \src "ls180.v:1294.12-1294.49"
wire width 8 \libresocsim_interface6_bank_bus_dat_w
- attribute \src "ls180.v:1288.6-1288.40"
+ attribute \src "ls180.v:1293.6-1293.40"
wire \libresocsim_interface6_bank_bus_we
- attribute \src "ls180.v:1312.13-1312.48"
+ attribute \src "ls180.v:1317.13-1317.48"
wire width 14 \libresocsim_interface7_bank_bus_adr
- attribute \src "ls180.v:1315.11-1315.48"
+ attribute \src "ls180.v:1320.11-1320.48"
wire width 8 \libresocsim_interface7_bank_bus_dat_r
- attribute \src "ls180.v:1314.12-1314.49"
+ attribute \src "ls180.v:1319.12-1319.49"
wire width 8 \libresocsim_interface7_bank_bus_dat_w
- attribute \src "ls180.v:1313.6-1313.40"
+ attribute \src "ls180.v:1318.6-1318.40"
wire \libresocsim_interface7_bank_bus_we
- attribute \src "ls180.v:166.6-166.21"
+ attribute \src "ls180.v:170.6-170.21"
wire \libresocsim_irq
- attribute \src "ls180.v:109.6-109.27"
+ attribute \src "ls180.v:111.6-111.27"
wire \libresocsim_libresoc0
- attribute \src "ls180.v:110.6-110.27"
+ attribute \src "ls180.v:112.6-112.27"
wire \libresocsim_libresoc1
- attribute \src "ls180.v:111.13-111.34"
+ attribute \src "ls180.v:113.13-113.34"
wire width 64 \libresocsim_libresoc2
- attribute \src "ls180.v:113.12-113.40"
+ attribute \src "ls180.v:115.12-115.40"
wire width 2 \libresocsim_libresoc_clk_sel
- attribute \src "ls180.v:115.13-115.62"
- wire width 16 \libresocsim_libresoc_constraintmanager_obj_gpio_i
- attribute \src "ls180.v:116.12-116.61"
- wire width 16 \libresocsim_libresoc_constraintmanager_obj_gpio_o
- attribute \src "ls180.v:117.12-117.62"
- wire width 16 \libresocsim_libresoc_constraintmanager_obj_gpio_oe
- attribute \src "ls180.v:137.6-137.56"
- wire \libresocsim_libresoc_constraintmanager_obj_i2c_scl
- attribute \src "ls180.v:138.6-138.58"
- wire \libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
- attribute \src "ls180.v:139.6-139.58"
- wire \libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
- attribute \src "ls180.v:140.6-140.59"
- wire \libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
- attribute \src "ls180.v:125.12-125.62"
- wire width 13 \libresocsim_libresoc_constraintmanager_obj_sdram_a
- attribute \src "ls180.v:134.11-134.62"
- wire width 2 \libresocsim_libresoc_constraintmanager_obj_sdram_ba
- attribute \src "ls180.v:131.5-131.59"
- wire \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
- attribute \src "ls180.v:133.5-133.57"
- wire \libresocsim_libresoc_constraintmanager_obj_sdram_cke
- attribute \src "ls180.v:132.5-132.58"
- wire \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
- attribute \src "ls180.v:135.11-135.62"
- wire width 2 \libresocsim_libresoc_constraintmanager_obj_sdram_dm
- attribute \src "ls180.v:126.13-126.66"
- wire width 16 \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
- attribute \src "ls180.v:127.12-127.65"
- wire width 16 \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
- attribute \src "ls180.v:128.5-128.59"
- wire \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
- attribute \src "ls180.v:130.5-130.59"
- wire \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
- attribute \src "ls180.v:129.5-129.58"
- wire \libresocsim_libresoc_constraintmanager_obj_sdram_we_n
- attribute \src "ls180.v:118.5-118.61"
- wire \libresocsim_libresoc_constraintmanager_obj_spimaster_clk
- attribute \src "ls180.v:120.5-120.62"
- wire \libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
- attribute \src "ls180.v:121.6-121.63"
- wire \libresocsim_libresoc_constraintmanager_obj_spimaster_miso
- attribute \src "ls180.v:119.5-119.62"
- wire \libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
- attribute \src "ls180.v:123.5-123.55"
- wire \libresocsim_libresoc_constraintmanager_obj_uart_rx
- attribute \src "ls180.v:122.5-122.55"
- wire \libresocsim_libresoc_constraintmanager_obj_uart_tx
- attribute \src "ls180.v:60.6-60.35"
+ attribute \src "ls180.v:126.6-126.51"
+ wire \libresocsim_libresoc_constraintmanager_eint_0
+ attribute \src "ls180.v:127.6-127.51"
+ wire \libresocsim_libresoc_constraintmanager_eint_1
+ attribute \src "ls180.v:128.6-128.51"
+ wire \libresocsim_libresoc_constraintmanager_eint_2
+ attribute \src "ls180.v:123.13-123.58"
+ wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i
+ attribute \src "ls180.v:124.12-124.57"
+ wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o
+ attribute \src "ls180.v:125.12-125.58"
+ wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe
+ attribute \src "ls180.v:117.6-117.52"
+ wire \libresocsim_libresoc_constraintmanager_i2c_scl
+ attribute \src "ls180.v:118.6-118.54"
+ wire \libresocsim_libresoc_constraintmanager_i2c_sda_i
+ attribute \src "ls180.v:119.6-119.54"
+ wire \libresocsim_libresoc_constraintmanager_i2c_sda_o
+ attribute \src "ls180.v:120.6-120.55"
+ wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe
+ attribute \src "ls180.v:133.12-133.58"
+ wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a
+ attribute \src "ls180.v:142.11-142.58"
+ wire width 2 \libresocsim_libresoc_constraintmanager_sdram_ba
+ attribute \src "ls180.v:139.5-139.55"
+ wire \libresocsim_libresoc_constraintmanager_sdram_cas_n
+ attribute \src "ls180.v:141.5-141.53"
+ wire \libresocsim_libresoc_constraintmanager_sdram_cke
+ attribute \src "ls180.v:144.5-144.55"
+ wire \libresocsim_libresoc_constraintmanager_sdram_clock
+ attribute \src "ls180.v:140.5-140.54"
+ wire \libresocsim_libresoc_constraintmanager_sdram_cs_n
+ attribute \src "ls180.v:143.11-143.58"
+ wire width 2 \libresocsim_libresoc_constraintmanager_sdram_dm
+ attribute \src "ls180.v:134.13-134.62"
+ wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_i
+ attribute \src "ls180.v:135.12-135.61"
+ wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_o
+ attribute \src "ls180.v:136.5-136.55"
+ wire \libresocsim_libresoc_constraintmanager_sdram_dq_oe
+ attribute \src "ls180.v:138.5-138.55"
+ wire \libresocsim_libresoc_constraintmanager_sdram_ras_n
+ attribute \src "ls180.v:137.5-137.54"
+ wire \libresocsim_libresoc_constraintmanager_sdram_we_n
+ attribute \src "ls180.v:129.5-129.57"
+ wire \libresocsim_libresoc_constraintmanager_spimaster_clk
+ attribute \src "ls180.v:131.5-131.58"
+ wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n
+ attribute \src "ls180.v:132.6-132.59"
+ wire \libresocsim_libresoc_constraintmanager_spimaster_miso
+ attribute \src "ls180.v:130.5-130.58"
+ wire \libresocsim_libresoc_constraintmanager_spimaster_mosi
+ attribute \src "ls180.v:122.5-122.51"
+ wire \libresocsim_libresoc_constraintmanager_uart_rx
+ attribute \src "ls180.v:121.5-121.51"
+ wire \libresocsim_libresoc_constraintmanager_uart_tx
+ attribute \src "ls180.v:62.6-62.35"
wire \libresocsim_libresoc_dbus_ack
- attribute \src "ls180.v:54.13-54.42"
+ attribute \src "ls180.v:56.13-56.42"
wire width 29 \libresocsim_libresoc_dbus_adr
- attribute \src "ls180.v:63.11-63.40"
+ attribute \src "ls180.v:65.11-65.40"
wire width 2 \libresocsim_libresoc_dbus_bte
- attribute \src "ls180.v:62.11-62.40"
+ attribute \src "ls180.v:64.11-64.40"
wire width 3 \libresocsim_libresoc_dbus_cti
- attribute \src "ls180.v:58.6-58.35"
+ attribute \src "ls180.v:60.6-60.35"
wire \libresocsim_libresoc_dbus_cyc
- attribute \src "ls180.v:56.13-56.44"
+ attribute \src "ls180.v:58.13-58.44"
wire width 64 \libresocsim_libresoc_dbus_dat_r
- attribute \src "ls180.v:55.13-55.44"
+ attribute \src "ls180.v:57.13-57.44"
wire width 64 \libresocsim_libresoc_dbus_dat_w
- attribute \src "ls180.v:64.6-64.35"
+ attribute \src "ls180.v:66.6-66.35"
wire \libresocsim_libresoc_dbus_err
- attribute \src "ls180.v:57.12-57.41"
+ attribute \src "ls180.v:59.12-59.41"
wire width 8 \libresocsim_libresoc_dbus_sel
- attribute \src "ls180.v:59.6-59.35"
+ attribute \src "ls180.v:61.6-61.35"
wire \libresocsim_libresoc_dbus_stb
- attribute \src "ls180.v:61.6-61.34"
+ attribute \src "ls180.v:63.6-63.34"
wire \libresocsim_libresoc_dbus_we
- attribute \src "ls180.v:71.6-71.35"
+ attribute \src "ls180.v:73.6-73.35"
wire \libresocsim_libresoc_ibus_ack
- attribute \src "ls180.v:65.13-65.42"
+ attribute \src "ls180.v:67.13-67.42"
wire width 29 \libresocsim_libresoc_ibus_adr
- attribute \src "ls180.v:74.11-74.40"
+ attribute \src "ls180.v:76.11-76.40"
wire width 2 \libresocsim_libresoc_ibus_bte
- attribute \src "ls180.v:73.11-73.40"
+ attribute \src "ls180.v:75.11-75.40"
wire width 3 \libresocsim_libresoc_ibus_cti
- attribute \src "ls180.v:69.6-69.35"
+ attribute \src "ls180.v:71.6-71.35"
wire \libresocsim_libresoc_ibus_cyc
- attribute \src "ls180.v:67.13-67.44"
+ attribute \src "ls180.v:69.13-69.44"
wire width 64 \libresocsim_libresoc_ibus_dat_r
- attribute \src "ls180.v:66.13-66.44"
+ attribute \src "ls180.v:68.13-68.44"
wire width 64 \libresocsim_libresoc_ibus_dat_w
- attribute \src "ls180.v:75.6-75.35"
+ attribute \src "ls180.v:77.6-77.35"
wire \libresocsim_libresoc_ibus_err
- attribute \src "ls180.v:68.12-68.41"
+ attribute \src "ls180.v:70.12-70.41"
wire width 8 \libresocsim_libresoc_ibus_sel
- attribute \src "ls180.v:70.6-70.35"
+ attribute \src "ls180.v:72.6-72.35"
wire \libresocsim_libresoc_ibus_stb
- attribute \src "ls180.v:72.6-72.34"
+ attribute \src "ls180.v:74.6-74.34"
wire \libresocsim_libresoc_ibus_we
- attribute \src "ls180.v:53.12-53.42"
+ attribute \src "ls180.v:55.12-55.42"
wire width 16 \libresocsim_libresoc_interrupt
- attribute \src "ls180.v:105.6-105.35"
- wire \libresocsim_libresoc_jtag_tck
attribute \src "ls180.v:107.6-107.35"
+ wire \libresocsim_libresoc_jtag_tck
+ attribute \src "ls180.v:109.6-109.35"
wire \libresocsim_libresoc_jtag_tdi
- attribute \src "ls180.v:108.6-108.35"
+ attribute \src "ls180.v:110.6-110.35"
wire \libresocsim_libresoc_jtag_tdo
- attribute \src "ls180.v:106.6-106.35"
+ attribute \src "ls180.v:108.6-108.35"
wire \libresocsim_libresoc_jtag_tms
- attribute \src "ls180.v:100.6-100.38"
+ attribute \src "ls180.v:102.6-102.38"
wire \libresocsim_libresoc_jtag_wb_ack
- attribute \src "ls180.v:94.13-94.45"
+ attribute \src "ls180.v:96.13-96.45"
wire width 29 \libresocsim_libresoc_jtag_wb_adr
- attribute \src "ls180.v:103.11-103.43"
+ attribute \src "ls180.v:105.11-105.43"
wire width 2 \libresocsim_libresoc_jtag_wb_bte
- attribute \src "ls180.v:102.11-102.43"
+ attribute \src "ls180.v:104.11-104.43"
wire width 3 \libresocsim_libresoc_jtag_wb_cti
- attribute \src "ls180.v:98.6-98.38"
+ attribute \src "ls180.v:100.6-100.38"
wire \libresocsim_libresoc_jtag_wb_cyc
- attribute \src "ls180.v:96.13-96.47"
+ attribute \src "ls180.v:98.13-98.47"
wire width 64 \libresocsim_libresoc_jtag_wb_dat_r
- attribute \src "ls180.v:95.13-95.47"
+ attribute \src "ls180.v:97.13-97.47"
wire width 64 \libresocsim_libresoc_jtag_wb_dat_w
- attribute \src "ls180.v:104.6-104.38"
+ attribute \src "ls180.v:106.6-106.38"
wire \libresocsim_libresoc_jtag_wb_err
- attribute \src "ls180.v:97.12-97.44"
+ attribute \src "ls180.v:99.12-99.44"
wire width 8 \libresocsim_libresoc_jtag_wb_sel
- attribute \src "ls180.v:99.6-99.38"
+ attribute \src "ls180.v:101.6-101.38"
wire \libresocsim_libresoc_jtag_wb_stb
- attribute \src "ls180.v:101.6-101.37"
+ attribute \src "ls180.v:103.6-103.37"
wire \libresocsim_libresoc_jtag_wb_we
- attribute \src "ls180.v:112.6-112.35"
+ attribute \src "ls180.v:114.6-114.35"
wire \libresocsim_libresoc_pll_18_o
- attribute \src "ls180.v:114.6-114.36"
+ attribute \src "ls180.v:116.6-116.36"
wire \libresocsim_libresoc_pll_lck_o
- attribute \src "ls180.v:52.6-52.32"
+ attribute \src "ls180.v:54.6-54.32"
wire \libresocsim_libresoc_reset
- attribute \src "ls180.v:82.6-82.39"
+ attribute \src "ls180.v:84.6-84.39"
wire \libresocsim_libresoc_xics_icp_ack
- attribute \src "ls180.v:76.12-76.45"
+ attribute \src "ls180.v:78.12-78.45"
wire width 30 \libresocsim_libresoc_xics_icp_adr
- attribute \src "ls180.v:80.5-80.38"
+ attribute \src "ls180.v:82.5-82.38"
wire \libresocsim_libresoc_xics_icp_cyc
- attribute \src "ls180.v:78.13-78.48"
+ attribute \src "ls180.v:80.13-80.48"
wire width 32 \libresocsim_libresoc_xics_icp_dat_r
- attribute \src "ls180.v:77.12-77.47"
+ attribute \src "ls180.v:79.12-79.47"
wire width 32 \libresocsim_libresoc_xics_icp_dat_w
- attribute \src "ls180.v:84.6-84.39"
+ attribute \src "ls180.v:86.6-86.39"
wire \libresocsim_libresoc_xics_icp_err
- attribute \src "ls180.v:79.11-79.44"
+ attribute \src "ls180.v:81.11-81.44"
wire width 4 \libresocsim_libresoc_xics_icp_sel
- attribute \src "ls180.v:81.5-81.38"
+ attribute \src "ls180.v:83.5-83.38"
wire \libresocsim_libresoc_xics_icp_stb
- attribute \src "ls180.v:83.5-83.37"
+ attribute \src "ls180.v:85.5-85.37"
wire \libresocsim_libresoc_xics_icp_we
- attribute \src "ls180.v:91.6-91.39"
+ attribute \src "ls180.v:93.6-93.39"
wire \libresocsim_libresoc_xics_ics_ack
- attribute \src "ls180.v:85.12-85.45"
+ attribute \src "ls180.v:87.12-87.45"
wire width 30 \libresocsim_libresoc_xics_ics_adr
- attribute \src "ls180.v:89.5-89.38"
+ attribute \src "ls180.v:91.5-91.38"
wire \libresocsim_libresoc_xics_ics_cyc
- attribute \src "ls180.v:87.13-87.48"
+ attribute \src "ls180.v:89.13-89.48"
wire width 32 \libresocsim_libresoc_xics_ics_dat_r
- attribute \src "ls180.v:86.12-86.47"
+ attribute \src "ls180.v:88.12-88.47"
wire width 32 \libresocsim_libresoc_xics_ics_dat_w
- attribute \src "ls180.v:93.6-93.39"
+ attribute \src "ls180.v:95.6-95.39"
wire \libresocsim_libresoc_xics_ics_err
- attribute \src "ls180.v:88.11-88.44"
+ attribute \src "ls180.v:90.11-90.44"
wire width 4 \libresocsim_libresoc_xics_ics_sel
- attribute \src "ls180.v:90.5-90.38"
+ attribute \src "ls180.v:92.5-92.38"
wire \libresocsim_libresoc_xics_ics_stb
- attribute \src "ls180.v:92.5-92.37"
+ attribute \src "ls180.v:94.5-94.37"
wire \libresocsim_libresoc_xics_ics_we
- attribute \src "ls180.v:1051.12-1051.39"
+ attribute \src "ls180.v:1056.12-1056.39"
wire width 14 \libresocsim_libresocsim_adr
- attribute \src "ls180.v:1341.12-1341.63"
+ attribute \src "ls180.v:1346.12-1346.63"
wire width 14 \libresocsim_libresocsim_adr_libresocsim_next_value1
- attribute \src "ls180.v:1342.5-1342.59"
+ attribute \src "ls180.v:1347.5-1347.59"
wire \libresocsim_libresocsim_adr_libresocsim_next_value_ce1
- attribute \src "ls180.v:1069.5-1069.52"
+ attribute \src "ls180.v:1074.5-1074.52"
wire \libresocsim_libresocsim_converted_interface_ack
- attribute \src "ls180.v:1063.13-1063.60"
+ attribute \src "ls180.v:1068.13-1068.60"
wire width 30 \libresocsim_libresocsim_converted_interface_adr
- attribute \src "ls180.v:1072.12-1072.59"
+ attribute \src "ls180.v:1077.12-1077.59"
wire width 2 \libresocsim_libresocsim_converted_interface_bte
- attribute \src "ls180.v:1071.12-1071.59"
+ attribute \src "ls180.v:1076.12-1076.59"
wire width 3 \libresocsim_libresocsim_converted_interface_cti
- attribute \src "ls180.v:1067.6-1067.53"
+ attribute \src "ls180.v:1072.6-1072.53"
wire \libresocsim_libresocsim_converted_interface_cyc
- attribute \src "ls180.v:1065.12-1065.61"
+ attribute \src "ls180.v:1070.12-1070.61"
wire width 64 \libresocsim_libresocsim_converted_interface_dat_r
- attribute \src "ls180.v:1064.13-1064.62"
+ attribute \src "ls180.v:1069.13-1069.62"
wire width 64 \libresocsim_libresocsim_converted_interface_dat_w
- attribute \src "ls180.v:1073.5-1073.52"
+ attribute \src "ls180.v:1078.5-1078.52"
wire \libresocsim_libresocsim_converted_interface_err
- attribute \src "ls180.v:1066.12-1066.59"
+ attribute \src "ls180.v:1071.12-1071.59"
wire width 8 \libresocsim_libresocsim_converted_interface_sel
- attribute \src "ls180.v:1068.6-1068.53"
+ attribute \src "ls180.v:1073.6-1073.53"
wire \libresocsim_libresocsim_converted_interface_stb
- attribute \src "ls180.v:1070.6-1070.52"
+ attribute \src "ls180.v:1075.6-1075.52"
wire \libresocsim_libresocsim_converted_interface_we
- attribute \src "ls180.v:1054.12-1054.41"
+ attribute \src "ls180.v:1059.12-1059.41"
wire width 8 \libresocsim_libresocsim_dat_r
- attribute \src "ls180.v:1053.11-1053.40"
+ attribute \src "ls180.v:1058.11-1058.40"
wire width 8 \libresocsim_libresocsim_dat_w
- attribute \src "ls180.v:1339.11-1339.64"
+ attribute \src "ls180.v:1344.11-1344.64"
wire width 8 \libresocsim_libresocsim_dat_w_libresocsim_next_value0
- attribute \src "ls180.v:1340.5-1340.61"
+ attribute \src "ls180.v:1345.5-1345.61"
wire \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0
- attribute \src "ls180.v:1052.5-1052.31"
+ attribute \src "ls180.v:1057.5-1057.31"
wire \libresocsim_libresocsim_we
- attribute \src "ls180.v:1343.5-1343.55"
+ attribute \src "ls180.v:1348.5-1348.55"
wire \libresocsim_libresocsim_we_libresocsim_next_value2
- attribute \src "ls180.v:1344.5-1344.58"
+ attribute \src "ls180.v:1349.5-1349.58"
wire \libresocsim_libresocsim_we_libresocsim_next_value_ce2
- attribute \src "ls180.v:1061.5-1061.41"
+ attribute \src "ls180.v:1066.5-1066.41"
wire \libresocsim_libresocsim_wishbone_ack
- attribute \src "ls180.v:1055.12-1055.48"
+ attribute \src "ls180.v:1060.12-1060.48"
wire width 30 \libresocsim_libresocsim_wishbone_adr
- attribute \src "ls180.v:1059.5-1059.41"
+ attribute \src "ls180.v:1064.5-1064.41"
wire \libresocsim_libresocsim_wishbone_cyc
- attribute \src "ls180.v:1057.12-1057.50"
+ attribute \src "ls180.v:1062.12-1062.50"
wire width 32 \libresocsim_libresocsim_wishbone_dat_r
- attribute \src "ls180.v:1056.12-1056.50"
+ attribute \src "ls180.v:1061.12-1061.50"
wire width 32 \libresocsim_libresocsim_wishbone_dat_w
- attribute \src "ls180.v:1058.11-1058.47"
+ attribute \src "ls180.v:1063.11-1063.47"
wire width 4 \libresocsim_libresocsim_wishbone_sel
- attribute \src "ls180.v:1060.5-1060.41"
+ attribute \src "ls180.v:1065.5-1065.41"
wire \libresocsim_libresocsim_wishbone_stb
- attribute \src "ls180.v:1062.5-1062.40"
+ attribute \src "ls180.v:1067.5-1067.40"
wire \libresocsim_libresocsim_wishbone_we
- attribute \src "ls180.v:157.5-157.24"
+ attribute \src "ls180.v:161.5-161.24"
wire \libresocsim_load_re
- attribute \src "ls180.v:156.12-156.36"
+ attribute \src "ls180.v:160.12-160.36"
wire width 32 \libresocsim_load_storage
- attribute \src "ls180.v:1338.11-1338.33"
+ attribute \src "ls180.v:1343.11-1343.33"
wire width 2 \libresocsim_next_state
- attribute \src "ls180.v:147.5-147.28"
+ attribute \src "ls180.v:151.5-151.28"
wire \libresocsim_ram_bus_ack
- attribute \src "ls180.v:141.13-141.36"
+ attribute \src "ls180.v:145.13-145.36"
wire width 30 \libresocsim_ram_bus_adr
- attribute \src "ls180.v:150.12-150.35"
+ attribute \src "ls180.v:154.12-154.35"
wire width 2 \libresocsim_ram_bus_bte
- attribute \src "ls180.v:149.12-149.35"
+ attribute \src "ls180.v:153.12-153.35"
wire width 3 \libresocsim_ram_bus_cti
- attribute \src "ls180.v:145.6-145.29"
+ attribute \src "ls180.v:149.6-149.29"
wire \libresocsim_ram_bus_cyc
- attribute \src "ls180.v:143.13-143.38"
+ attribute \src "ls180.v:147.13-147.38"
wire width 64 \libresocsim_ram_bus_dat_r
- attribute \src "ls180.v:142.13-142.38"
+ attribute \src "ls180.v:146.13-146.38"
wire width 64 \libresocsim_ram_bus_dat_w
- attribute \src "ls180.v:151.5-151.28"
+ attribute \src "ls180.v:155.5-155.28"
wire \libresocsim_ram_bus_err
- attribute \src "ls180.v:144.12-144.35"
+ attribute \src "ls180.v:148.12-148.35"
wire width 8 \libresocsim_ram_bus_sel
- attribute \src "ls180.v:146.6-146.29"
+ attribute \src "ls180.v:150.6-150.29"
wire \libresocsim_ram_bus_stb
- attribute \src "ls180.v:148.6-148.28"
+ attribute \src "ls180.v:152.6-152.28"
wire \libresocsim_ram_bus_we
- attribute \src "ls180.v:159.5-159.26"
+ attribute \src "ls180.v:163.5-163.26"
wire \libresocsim_reload_re
- attribute \src "ls180.v:158.12-158.38"
+ attribute \src "ls180.v:162.12-162.38"
wire width 32 \libresocsim_reload_storage
- attribute \src "ls180.v:1085.12-1085.31"
+ attribute \src "ls180.v:1090.12-1090.31"
wire width 3 \libresocsim_request
- attribute \src "ls180.v:49.6-49.23"
+ attribute \src "ls180.v:51.6-51.23"
wire \libresocsim_reset
- attribute \src "ls180.v:44.5-44.25"
+ attribute \src "ls180.v:46.5-46.25"
wire \libresocsim_reset_re
- attribute \src "ls180.v:43.5-43.30"
+ attribute \src "ls180.v:45.5-45.30"
wire \libresocsim_reset_storage
- attribute \src "ls180.v:46.5-46.27"
+ attribute \src "ls180.v:48.5-48.27"
wire \libresocsim_scratch_re
- attribute \src "ls180.v:45.12-45.39"
+ attribute \src "ls180.v:47.12-47.39"
wire width 32 \libresocsim_scratch_storage
- attribute \src "ls180.v:1080.5-1080.27"
+ attribute \src "ls180.v:1085.5-1085.27"
wire \libresocsim_shared_ack
- attribute \src "ls180.v:1074.13-1074.35"
+ attribute \src "ls180.v:1079.13-1079.35"
wire width 30 \libresocsim_shared_adr
- attribute \src "ls180.v:1083.12-1083.34"
+ attribute \src "ls180.v:1088.12-1088.34"
wire width 2 \libresocsim_shared_bte
- attribute \src "ls180.v:1082.12-1082.34"
+ attribute \src "ls180.v:1087.12-1087.34"
wire width 3 \libresocsim_shared_cti
- attribute \src "ls180.v:1078.6-1078.28"
+ attribute \src "ls180.v:1083.6-1083.28"
wire \libresocsim_shared_cyc
- attribute \src "ls180.v:1076.12-1076.36"
+ attribute \src "ls180.v:1081.12-1081.36"
wire width 32 \libresocsim_shared_dat_r
- attribute \src "ls180.v:1075.13-1075.37"
+ attribute \src "ls180.v:1080.13-1080.37"
wire width 32 \libresocsim_shared_dat_w
- attribute \src "ls180.v:1084.6-1084.28"
+ attribute \src "ls180.v:1089.6-1089.28"
wire \libresocsim_shared_err
- attribute \src "ls180.v:1077.12-1077.34"
+ attribute \src "ls180.v:1082.12-1082.34"
wire width 4 \libresocsim_shared_sel
- attribute \src "ls180.v:1079.6-1079.28"
+ attribute \src "ls180.v:1084.6-1084.28"
wire \libresocsim_shared_stb
- attribute \src "ls180.v:1081.6-1081.27"
+ attribute \src "ls180.v:1086.6-1086.27"
wire \libresocsim_shared_we
- attribute \src "ls180.v:1087.11-1087.32"
+ attribute \src "ls180.v:1092.11-1092.32"
wire width 6 \libresocsim_slave_sel
- attribute \src "ls180.v:1088.11-1088.34"
+ attribute \src "ls180.v:1093.11-1093.34"
wire width 6 \libresocsim_slave_sel_r
- attribute \src "ls180.v:1337.11-1337.28"
+ attribute \src "ls180.v:1342.11-1342.28"
wire width 2 \libresocsim_state
- attribute \src "ls180.v:163.5-163.32"
+ attribute \src "ls180.v:167.5-167.32"
wire \libresocsim_update_value_re
- attribute \src "ls180.v:162.5-162.37"
+ attribute \src "ls180.v:166.5-166.37"
wire \libresocsim_update_value_storage
- attribute \src "ls180.v:182.12-182.29"
+ attribute \src "ls180.v:186.12-186.29"
wire width 32 \libresocsim_value
- attribute \src "ls180.v:164.12-164.36"
+ attribute \src "ls180.v:168.12-168.36"
wire width 32 \libresocsim_value_status
- attribute \src "ls180.v:165.6-165.26"
+ attribute \src "ls180.v:169.6-169.26"
wire \libresocsim_value_we
- attribute \src "ls180.v:1090.6-1090.22"
+ attribute \src "ls180.v:1095.6-1095.22"
wire \libresocsim_wait
- attribute \src "ls180.v:154.11-154.25"
+ attribute \src "ls180.v:158.11-158.25"
wire width 8 \libresocsim_we
- attribute \src "ls180.v:170.5-170.27"
+ attribute \src "ls180.v:174.5-174.27"
wire \libresocsim_zero_clear
- attribute \src "ls180.v:171.5-171.33"
+ attribute \src "ls180.v:175.5-175.33"
wire \libresocsim_zero_old_trigger
- attribute \src "ls180.v:168.5-168.29"
+ attribute \src "ls180.v:172.5-172.29"
wire \libresocsim_zero_pending
- attribute \src "ls180.v:167.6-167.29"
+ attribute \src "ls180.v:171.6-171.29"
wire \libresocsim_zero_status
- attribute \src "ls180.v:169.6-169.30"
+ attribute \src "ls180.v:173.6-173.30"
wire \libresocsim_zero_trigger
- attribute \src "ls180.v:821.6-821.21"
+ attribute \src "ls180.v:825.6-825.21"
wire \litedram_wb_ack
- attribute \src "ls180.v:815.12-815.27"
+ attribute \src "ls180.v:819.12-819.27"
wire width 30 \litedram_wb_adr
- attribute \src "ls180.v:819.5-819.20"
+ attribute \src "ls180.v:823.5-823.20"
wire \litedram_wb_cyc
- attribute \src "ls180.v:817.13-817.30"
+ attribute \src "ls180.v:821.13-821.30"
wire width 16 \litedram_wb_dat_r
- attribute \src "ls180.v:816.12-816.29"
+ attribute \src "ls180.v:820.12-820.29"
wire width 16 \litedram_wb_dat_w
- attribute \src "ls180.v:818.11-818.26"
+ attribute \src "ls180.v:822.11-822.26"
wire width 2 \litedram_wb_sel
- attribute \src "ls180.v:820.5-820.20"
+ attribute \src "ls180.v:824.5-824.20"
wire \litedram_wb_stb
- attribute \src "ls180.v:822.5-822.19"
+ attribute \src "ls180.v:826.5-826.19"
wire \litedram_wb_we
- attribute \src "ls180.v:5490.11-5490.17"
+ attribute \src "ls180.v:5509.11-5509.17"
wire width 6 \memadr
- attribute \src "ls180.v:5518.11-5518.19"
+ attribute \src "ls180.v:5537.11-5537.19"
wire width 4 \memadr_1
- attribute \src "ls180.v:5546.12-5546.18"
+ attribute \src "ls180.v:5565.12-5565.18"
wire width 25 \memdat
- attribute \src "ls180.v:5560.12-5560.20"
+ attribute \src "ls180.v:5579.12-5579.20"
wire width 25 \memdat_1
- attribute \src "ls180.v:5574.12-5574.20"
+ attribute \src "ls180.v:5593.12-5593.20"
wire width 25 \memdat_2
- attribute \src "ls180.v:5588.12-5588.20"
+ attribute \src "ls180.v:5607.12-5607.20"
wire width 25 \memdat_3
- attribute \src "ls180.v:5602.11-5602.19"
+ attribute \src "ls180.v:5621.11-5621.19"
wire width 10 \memdat_4
- attribute \src "ls180.v:5603.11-5603.19"
+ attribute \src "ls180.v:5622.11-5622.19"
wire width 10 \memdat_5
- attribute \src "ls180.v:5619.11-5619.19"
+ attribute \src "ls180.v:5638.11-5638.19"
wire width 10 \memdat_6
- attribute \src "ls180.v:5620.11-5620.19"
+ attribute \src "ls180.v:5639.11-5639.19"
wire width 10 \memdat_7
- attribute \src "ls180.v:40.20-40.22"
- wire width 30 input 36 \nc
- attribute \src "ls180.v:992.13-992.17"
- wire width 30 \nc_1
- attribute \src "ls180.v:230.6-230.13"
+ attribute \src "ls180.v:42.20-42.22"
+ wire width 36 input 38 \nc
+ attribute \src "ls180.v:997.13-997.17"
+ wire width 36 \nc_1
+ attribute \src "ls180.v:234.6-234.13"
wire \por_clk
- attribute \src "ls180.v:782.6-782.19"
+ attribute \src "ls180.v:786.6-786.19"
wire \port_cmd_last
- attribute \src "ls180.v:784.13-784.34"
+ attribute \src "ls180.v:788.13-788.34"
wire width 24 \port_cmd_payload_addr
- attribute \src "ls180.v:783.6-783.25"
+ attribute \src "ls180.v:787.6-787.25"
wire \port_cmd_payload_we
- attribute \src "ls180.v:781.6-781.20"
+ attribute \src "ls180.v:785.6-785.20"
wire \port_cmd_ready
- attribute \src "ls180.v:780.6-780.20"
+ attribute \src "ls180.v:784.6-784.20"
wire \port_cmd_valid
- attribute \src "ls180.v:779.6-779.16"
+ attribute \src "ls180.v:783.6-783.16"
wire \port_flush
- attribute \src "ls180.v:791.13-791.36"
+ attribute \src "ls180.v:795.13-795.36"
wire width 16 \port_rdata_payload_data
- attribute \src "ls180.v:790.6-790.22"
+ attribute \src "ls180.v:794.6-794.22"
wire \port_rdata_ready
- attribute \src "ls180.v:789.6-789.22"
+ attribute \src "ls180.v:793.6-793.22"
wire \port_rdata_valid
- attribute \src "ls180.v:787.13-787.36"
+ attribute \src "ls180.v:791.13-791.36"
wire width 16 \port_wdata_payload_data
- attribute \src "ls180.v:788.12-788.33"
+ attribute \src "ls180.v:792.12-792.33"
wire width 2 \port_wdata_payload_we
- attribute \src "ls180.v:786.6-786.22"
+ attribute \src "ls180.v:790.6-790.22"
wire \port_wdata_ready
- attribute \src "ls180.v:785.6-785.22"
+ attribute \src "ls180.v:789.6-789.22"
wire \port_wdata_valid
- attribute \src "ls180.v:194.12-194.19"
+ attribute \src "ls180.v:198.12-198.19"
wire width 4 \ram_adr
- attribute \src "ls180.v:189.5-189.24"
+ attribute \src "ls180.v:193.5-193.24"
wire \ram_bus_ram_bus_ack
- attribute \src "ls180.v:183.13-183.32"
+ attribute \src "ls180.v:187.13-187.32"
wire width 30 \ram_bus_ram_bus_adr
- attribute \src "ls180.v:192.12-192.31"
+ attribute \src "ls180.v:196.12-196.31"
wire width 2 \ram_bus_ram_bus_bte
- attribute \src "ls180.v:191.12-191.31"
+ attribute \src "ls180.v:195.12-195.31"
wire width 3 \ram_bus_ram_bus_cti
- attribute \src "ls180.v:187.6-187.25"
+ attribute \src "ls180.v:191.6-191.25"
wire \ram_bus_ram_bus_cyc
- attribute \src "ls180.v:185.13-185.34"
+ attribute \src "ls180.v:189.13-189.34"
wire width 64 \ram_bus_ram_bus_dat_r
- attribute \src "ls180.v:184.13-184.34"
+ attribute \src "ls180.v:188.13-188.34"
wire width 64 \ram_bus_ram_bus_dat_w
- attribute \src "ls180.v:193.5-193.24"
+ attribute \src "ls180.v:197.5-197.24"
wire \ram_bus_ram_bus_err
- attribute \src "ls180.v:186.12-186.31"
+ attribute \src "ls180.v:190.12-190.31"
wire width 8 \ram_bus_ram_bus_sel
- attribute \src "ls180.v:188.6-188.25"
+ attribute \src "ls180.v:192.6-192.25"
wire \ram_bus_ram_bus_stb
- attribute \src "ls180.v:190.6-190.24"
+ attribute \src "ls180.v:194.6-194.24"
wire \ram_bus_ram_bus_we
- attribute \src "ls180.v:195.13-195.22"
+ attribute \src "ls180.v:199.13-199.22"
wire width 64 \ram_dat_r
- attribute \src "ls180.v:197.13-197.22"
+ attribute \src "ls180.v:201.13-201.22"
wire width 64 \ram_dat_w
- attribute \src "ls180.v:196.11-196.17"
+ attribute \src "ls180.v:200.11-200.17"
wire width 8 \ram_we
- attribute \src "ls180.v:248.11-248.20"
+ attribute \src "ls180.v:252.11-252.20"
wire width 3 \rddata_en
attribute \no_retiming "true"
- attribute \src "ls180.v:1446.32-1446.37"
+ attribute \src "ls180.v:1451.32-1451.37"
wire \regs0
attribute \no_retiming "true"
- attribute \src "ls180.v:1447.32-1447.37"
+ attribute \src "ls180.v:1452.32-1452.37"
wire \regs1
- attribute \src "ls180.v:973.5-973.10"
+ attribute \src "ls180.v:977.5-977.10"
wire \reset
- attribute \src "ls180.v:1345.5-1345.21"
+ attribute \src "ls180.v:1350.5-1350.21"
wire \rhs_array_muxed0
- attribute \src "ls180.v:1346.12-1346.28"
+ attribute \src "ls180.v:1351.12-1351.28"
wire width 13 \rhs_array_muxed1
- attribute \src "ls180.v:1358.5-1358.22"
+ attribute \src "ls180.v:1363.5-1363.22"
wire \rhs_array_muxed10
- attribute \src "ls180.v:1359.5-1359.22"
+ attribute \src "ls180.v:1364.5-1364.22"
wire \rhs_array_muxed11
- attribute \src "ls180.v:1363.12-1363.29"
+ attribute \src "ls180.v:1368.12-1368.29"
wire width 22 \rhs_array_muxed12
- attribute \src "ls180.v:1364.5-1364.22"
+ attribute \src "ls180.v:1369.5-1369.22"
wire \rhs_array_muxed13
- attribute \src "ls180.v:1365.5-1365.22"
+ attribute \src "ls180.v:1370.5-1370.22"
wire \rhs_array_muxed14
- attribute \src "ls180.v:1366.12-1366.29"
+ attribute \src "ls180.v:1371.12-1371.29"
wire width 22 \rhs_array_muxed15
- attribute \src "ls180.v:1367.5-1367.22"
+ attribute \src "ls180.v:1372.5-1372.22"
wire \rhs_array_muxed16
- attribute \src "ls180.v:1368.5-1368.22"
+ attribute \src "ls180.v:1373.5-1373.22"
wire \rhs_array_muxed17
- attribute \src "ls180.v:1369.12-1369.29"
+ attribute \src "ls180.v:1374.12-1374.29"
wire width 22 \rhs_array_muxed18
- attribute \src "ls180.v:1370.5-1370.22"
+ attribute \src "ls180.v:1375.5-1375.22"
wire \rhs_array_muxed19
- attribute \src "ls180.v:1347.11-1347.27"
+ attribute \src "ls180.v:1352.11-1352.27"
wire width 2 \rhs_array_muxed2
- attribute \src "ls180.v:1371.5-1371.22"
+ attribute \src "ls180.v:1376.5-1376.22"
wire \rhs_array_muxed20
- attribute \src "ls180.v:1372.12-1372.29"
+ attribute \src "ls180.v:1377.12-1377.29"
wire width 22 \rhs_array_muxed21
- attribute \src "ls180.v:1373.5-1373.22"
+ attribute \src "ls180.v:1378.5-1378.22"
wire \rhs_array_muxed22
- attribute \src "ls180.v:1374.5-1374.22"
+ attribute \src "ls180.v:1379.5-1379.22"
wire \rhs_array_muxed23
- attribute \src "ls180.v:1375.12-1375.29"
+ attribute \src "ls180.v:1380.12-1380.29"
wire width 29 \rhs_array_muxed24
- attribute \src "ls180.v:1376.12-1376.29"
+ attribute \src "ls180.v:1381.12-1381.29"
wire width 64 \rhs_array_muxed25
- attribute \src "ls180.v:1377.11-1377.28"
+ attribute \src "ls180.v:1382.11-1382.28"
wire width 8 \rhs_array_muxed26
- attribute \src "ls180.v:1378.5-1378.22"
+ attribute \src "ls180.v:1383.5-1383.22"
wire \rhs_array_muxed27
- attribute \src "ls180.v:1379.5-1379.22"
+ attribute \src "ls180.v:1384.5-1384.22"
wire \rhs_array_muxed28
- attribute \src "ls180.v:1380.5-1380.22"
+ attribute \src "ls180.v:1385.5-1385.22"
wire \rhs_array_muxed29
- attribute \src "ls180.v:1348.5-1348.21"
+ attribute \src "ls180.v:1353.5-1353.21"
wire \rhs_array_muxed3
- attribute \src "ls180.v:1381.11-1381.28"
+ attribute \src "ls180.v:1386.11-1386.28"
wire width 3 \rhs_array_muxed30
- attribute \src "ls180.v:1382.11-1382.28"
+ attribute \src "ls180.v:1387.11-1387.28"
wire width 2 \rhs_array_muxed31
- attribute \src "ls180.v:1349.5-1349.21"
+ attribute \src "ls180.v:1354.5-1354.21"
wire \rhs_array_muxed4
- attribute \src "ls180.v:1350.5-1350.21"
+ attribute \src "ls180.v:1355.5-1355.21"
wire \rhs_array_muxed5
- attribute \src "ls180.v:1354.5-1354.21"
+ attribute \src "ls180.v:1359.5-1359.21"
wire \rhs_array_muxed6
- attribute \src "ls180.v:1355.12-1355.28"
+ attribute \src "ls180.v:1360.12-1360.28"
wire width 13 \rhs_array_muxed7
- attribute \src "ls180.v:1356.11-1356.27"
+ attribute \src "ls180.v:1361.11-1361.27"
wire width 2 \rhs_array_muxed8
- attribute \src "ls180.v:1357.5-1357.21"
+ attribute \src "ls180.v:1362.5-1362.21"
wire \rhs_array_muxed9
- attribute \src "ls180.v:873.5-873.13"
+ attribute \src "ls180.v:877.5-877.13"
wire \rx_clear
- attribute \src "ls180.v:957.11-957.26"
+ attribute \src "ls180.v:961.11-961.26"
wire width 4 \rx_fifo_consume
- attribute \src "ls180.v:962.6-962.21"
+ attribute \src "ls180.v:966.6-966.21"
wire \rx_fifo_do_read
- attribute \src "ls180.v:968.6-968.27"
+ attribute \src "ls180.v:972.6-972.27"
wire \rx_fifo_fifo_in_first
- attribute \src "ls180.v:969.6-969.26"
+ attribute \src "ls180.v:973.6-973.26"
wire \rx_fifo_fifo_in_last
- attribute \src "ls180.v:967.12-967.40"
+ attribute \src "ls180.v:971.12-971.40"
wire width 8 \rx_fifo_fifo_in_payload_data
- attribute \src "ls180.v:971.6-971.28"
+ attribute \src "ls180.v:975.6-975.28"
wire \rx_fifo_fifo_out_first
- attribute \src "ls180.v:972.6-972.27"
+ attribute \src "ls180.v:976.6-976.27"
wire \rx_fifo_fifo_out_last
- attribute \src "ls180.v:970.12-970.41"
+ attribute \src "ls180.v:974.12-974.41"
wire width 8 \rx_fifo_fifo_out_payload_data
- attribute \src "ls180.v:954.11-954.25"
+ attribute \src "ls180.v:958.11-958.25"
wire width 5 \rx_fifo_level0
- attribute \src "ls180.v:966.12-966.26"
+ attribute \src "ls180.v:970.12-970.26"
wire width 5 \rx_fifo_level1
- attribute \src "ls180.v:956.11-956.26"
+ attribute \src "ls180.v:960.11-960.26"
wire width 4 \rx_fifo_produce
- attribute \src "ls180.v:963.12-963.30"
+ attribute \src "ls180.v:967.12-967.30"
wire width 4 \rx_fifo_rdport_adr
- attribute \src "ls180.v:964.12-964.32"
+ attribute \src "ls180.v:968.12-968.32"
wire width 10 \rx_fifo_rdport_dat_r
- attribute \src "ls180.v:965.6-965.23"
+ attribute \src "ls180.v:969.6-969.23"
wire \rx_fifo_rdport_re
- attribute \src "ls180.v:946.6-946.16"
+ attribute \src "ls180.v:950.6-950.16"
wire \rx_fifo_re
- attribute \src "ls180.v:947.5-947.21"
+ attribute \src "ls180.v:951.5-951.21"
wire \rx_fifo_readable
- attribute \src "ls180.v:955.5-955.20"
+ attribute \src "ls180.v:959.5-959.20"
wire \rx_fifo_replace
- attribute \src "ls180.v:938.6-938.24"
+ attribute \src "ls180.v:942.6-942.24"
wire \rx_fifo_sink_first
- attribute \src "ls180.v:939.6-939.23"
+ attribute \src "ls180.v:943.6-943.23"
wire \rx_fifo_sink_last
- attribute \src "ls180.v:940.12-940.37"
+ attribute \src "ls180.v:944.12-944.37"
wire width 8 \rx_fifo_sink_payload_data
- attribute \src "ls180.v:937.6-937.24"
+ attribute \src "ls180.v:941.6-941.24"
wire \rx_fifo_sink_ready
- attribute \src "ls180.v:936.6-936.24"
+ attribute \src "ls180.v:940.6-940.24"
wire \rx_fifo_sink_valid
- attribute \src "ls180.v:943.6-943.26"
+ attribute \src "ls180.v:947.6-947.26"
wire \rx_fifo_source_first
- attribute \src "ls180.v:944.6-944.25"
+ attribute \src "ls180.v:948.6-948.25"
wire \rx_fifo_source_last
- attribute \src "ls180.v:945.12-945.39"
+ attribute \src "ls180.v:949.12-949.39"
wire width 8 \rx_fifo_source_payload_data
- attribute \src "ls180.v:942.6-942.26"
+ attribute \src "ls180.v:946.6-946.26"
wire \rx_fifo_source_ready
- attribute \src "ls180.v:941.6-941.26"
+ attribute \src "ls180.v:945.6-945.26"
wire \rx_fifo_source_valid
- attribute \src "ls180.v:952.12-952.32"
+ attribute \src "ls180.v:956.12-956.32"
wire width 10 \rx_fifo_syncfifo_din
- attribute \src "ls180.v:953.12-953.33"
+ attribute \src "ls180.v:957.12-957.33"
wire width 10 \rx_fifo_syncfifo_dout
- attribute \src "ls180.v:950.6-950.25"
+ attribute \src "ls180.v:954.6-954.25"
wire \rx_fifo_syncfifo_re
- attribute \src "ls180.v:951.6-951.31"
+ attribute \src "ls180.v:955.6-955.31"
wire \rx_fifo_syncfifo_readable
- attribute \src "ls180.v:948.6-948.25"
+ attribute \src "ls180.v:952.6-952.25"
wire \rx_fifo_syncfifo_we
- attribute \src "ls180.v:949.6-949.31"
+ attribute \src "ls180.v:953.6-953.31"
wire \rx_fifo_syncfifo_writable
- attribute \src "ls180.v:958.11-958.29"
+ attribute \src "ls180.v:962.11-962.29"
wire width 4 \rx_fifo_wrport_adr
- attribute \src "ls180.v:959.12-959.32"
+ attribute \src "ls180.v:963.12-963.32"
wire width 10 \rx_fifo_wrport_dat_r
- attribute \src "ls180.v:961.12-961.32"
+ attribute \src "ls180.v:965.12-965.32"
wire width 10 \rx_fifo_wrport_dat_w
- attribute \src "ls180.v:960.6-960.23"
+ attribute \src "ls180.v:964.6-964.23"
wire \rx_fifo_wrport_we
- attribute \src "ls180.v:874.5-874.19"
+ attribute \src "ls180.v:878.5-878.19"
wire \rx_old_trigger
- attribute \src "ls180.v:871.5-871.15"
+ attribute \src "ls180.v:875.5-875.15"
wire \rx_pending
- attribute \src "ls180.v:870.6-870.15"
+ attribute \src "ls180.v:874.6-874.15"
wire \rx_status
- attribute \src "ls180.v:872.6-872.16"
+ attribute \src "ls180.v:876.6-876.16"
wire \rx_trigger
- attribute \src "ls180.v:862.6-862.20"
+ attribute \src "ls180.v:866.6-866.20"
wire \rxempty_status
- attribute \src "ls180.v:863.6-863.16"
+ attribute \src "ls180.v:867.6-867.16"
wire \rxempty_we
- attribute \src "ls180.v:887.6-887.19"
+ attribute \src "ls180.v:891.6-891.19"
wire \rxfull_status
- attribute \src "ls180.v:888.6-888.15"
+ attribute \src "ls180.v:892.6-892.15"
wire \rxfull_we
- attribute \src "ls180.v:857.12-857.18"
+ attribute \src "ls180.v:861.12-861.18"
wire width 8 \rxtx_r
- attribute \src "ls180.v:856.6-856.13"
+ attribute \src "ls180.v:860.6-860.13"
wire \rxtx_re
- attribute \src "ls180.v:859.12-859.18"
+ attribute \src "ls180.v:863.12-863.18"
wire width 8 \rxtx_w
- attribute \src "ls180.v:858.6-858.13"
+ attribute \src "ls180.v:862.6-862.13"
wire \rxtx_we
- attribute \src "ls180.v:15.21-15.28"
- wire width 13 output 11 \sdram_a
- attribute \src "ls180.v:310.5-310.21"
+ attribute \src "ls180.v:21.21-21.28"
+ wire width 13 output 17 \sdram_a
+ attribute \src "ls180.v:314.5-314.21"
wire \sdram_address_re
- attribute \src "ls180.v:309.12-309.33"
+ attribute \src "ls180.v:313.12-313.33"
wire width 13 \sdram_address_storage
- attribute \src "ls180.v:24.20-24.28"
- wire width 2 output 20 \sdram_ba
- attribute \src "ls180.v:312.5-312.22"
+ attribute \src "ls180.v:30.20-30.28"
+ wire width 2 output 26 \sdram_ba
+ attribute \src "ls180.v:316.5-316.22"
wire \sdram_baddress_re
- attribute \src "ls180.v:311.11-311.33"
+ attribute \src "ls180.v:315.11-315.33"
wire width 2 \sdram_baddress_storage
- attribute \src "ls180.v:408.5-408.38"
+ attribute \src "ls180.v:412.5-412.38"
wire \sdram_bankmachine0_auto_precharge
- attribute \src "ls180.v:430.11-430.58"
+ attribute \src "ls180.v:434.11-434.58"
wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:435.6-435.53"
+ attribute \src "ls180.v:439.6-439.53"
wire \sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:440.6-440.59"
+ attribute \src "ls180.v:444.6-444.59"
wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:441.6-441.58"
+ attribute \src "ls180.v:445.6-445.58"
wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:439.13-439.73"
+ attribute \src "ls180.v:443.13-443.73"
wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:438.6-438.64"
+ attribute \src "ls180.v:442.6-442.64"
wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:444.6-444.60"
+ attribute \src "ls180.v:448.6-448.60"
wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:445.6-445.59"
+ attribute \src "ls180.v:449.6-449.59"
wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:443.13-443.74"
+ attribute \src "ls180.v:447.13-447.74"
wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:442.6-442.65"
+ attribute \src "ls180.v:446.6-446.65"
wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:427.11-427.56"
+ attribute \src "ls180.v:431.11-431.56"
wire width 4 \sdram_bankmachine0_cmd_buffer_lookahead_level
- attribute \src "ls180.v:429.11-429.58"
+ attribute \src "ls180.v:433.11-433.58"
wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:436.12-436.62"
+ attribute \src "ls180.v:440.12-440.62"
wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:437.13-437.65"
+ attribute \src "ls180.v:441.13-441.65"
wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:428.5-428.52"
+ attribute \src "ls180.v:432.5-432.52"
wire \sdram_bankmachine0_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:411.5-411.55"
+ attribute \src "ls180.v:415.5-415.55"
wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:412.5-412.54"
+ attribute \src "ls180.v:416.5-416.54"
wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:414.13-414.70"
+ attribute \src "ls180.v:418.13-418.70"
wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:413.6-413.61"
+ attribute \src "ls180.v:417.6-417.61"
wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:410.6-410.56"
+ attribute \src "ls180.v:414.6-414.56"
wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:409.6-409.56"
+ attribute \src "ls180.v:413.6-413.56"
wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:417.6-417.58"
+ attribute \src "ls180.v:421.6-421.58"
wire \sdram_bankmachine0_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:418.6-418.57"
+ attribute \src "ls180.v:422.6-422.57"
wire \sdram_bankmachine0_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:420.13-420.72"
+ attribute \src "ls180.v:424.13-424.72"
wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:419.6-419.63"
+ attribute \src "ls180.v:423.6-423.63"
wire \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:416.6-416.58"
+ attribute \src "ls180.v:420.6-420.58"
wire \sdram_bankmachine0_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:415.6-415.58"
+ attribute \src "ls180.v:419.6-419.58"
wire \sdram_bankmachine0_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:425.13-425.66"
+ attribute \src "ls180.v:429.13-429.66"
wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
- attribute \src "ls180.v:426.13-426.67"
+ attribute \src "ls180.v:430.13-430.67"
wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
- attribute \src "ls180.v:423.6-423.58"
+ attribute \src "ls180.v:427.6-427.58"
wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
- attribute \src "ls180.v:424.6-424.64"
+ attribute \src "ls180.v:428.6-428.64"
wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
- attribute \src "ls180.v:421.6-421.58"
+ attribute \src "ls180.v:425.6-425.58"
wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
- attribute \src "ls180.v:422.6-422.64"
+ attribute \src "ls180.v:426.6-426.64"
wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- attribute \src "ls180.v:431.11-431.61"
+ attribute \src "ls180.v:435.11-435.61"
wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:432.13-432.65"
+ attribute \src "ls180.v:436.13-436.65"
wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:434.13-434.65"
+ attribute \src "ls180.v:438.13-438.65"
wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:433.6-433.55"
+ attribute \src "ls180.v:437.6-437.55"
wire \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:448.6-448.46"
+ attribute \src "ls180.v:452.6-452.46"
wire \sdram_bankmachine0_cmd_buffer_sink_first
- attribute \src "ls180.v:449.6-449.45"
+ attribute \src "ls180.v:453.6-453.45"
wire \sdram_bankmachine0_cmd_buffer_sink_last
- attribute \src "ls180.v:451.13-451.60"
+ attribute \src "ls180.v:455.13-455.60"
wire width 22 \sdram_bankmachine0_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:450.6-450.51"
+ attribute \src "ls180.v:454.6-454.51"
wire \sdram_bankmachine0_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:447.6-447.46"
+ attribute \src "ls180.v:451.6-451.46"
wire \sdram_bankmachine0_cmd_buffer_sink_ready
- attribute \src "ls180.v:446.6-446.46"
+ attribute \src "ls180.v:450.6-450.46"
wire \sdram_bankmachine0_cmd_buffer_sink_valid
- attribute \src "ls180.v:454.5-454.47"
+ attribute \src "ls180.v:458.5-458.47"
wire \sdram_bankmachine0_cmd_buffer_source_first
- attribute \src "ls180.v:455.5-455.46"
+ attribute \src "ls180.v:459.5-459.46"
wire \sdram_bankmachine0_cmd_buffer_source_last
- attribute \src "ls180.v:457.12-457.61"
+ attribute \src "ls180.v:461.12-461.61"
wire width 22 \sdram_bankmachine0_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:456.5-456.52"
+ attribute \src "ls180.v:460.5-460.52"
wire \sdram_bankmachine0_cmd_buffer_source_payload_we
- attribute \src "ls180.v:453.6-453.48"
+ attribute \src "ls180.v:457.6-457.48"
wire \sdram_bankmachine0_cmd_buffer_source_ready
- attribute \src "ls180.v:452.5-452.47"
+ attribute \src "ls180.v:456.5-456.47"
wire \sdram_bankmachine0_cmd_buffer_source_valid
- attribute \src "ls180.v:400.12-400.44"
+ attribute \src "ls180.v:404.12-404.44"
wire width 13 \sdram_bankmachine0_cmd_payload_a
- attribute \src "ls180.v:401.12-401.45"
+ attribute \src "ls180.v:405.12-405.45"
wire width 2 \sdram_bankmachine0_cmd_payload_ba
- attribute \src "ls180.v:402.5-402.39"
+ attribute \src "ls180.v:406.5-406.39"
wire \sdram_bankmachine0_cmd_payload_cas
- attribute \src "ls180.v:405.5-405.42"
+ attribute \src "ls180.v:409.5-409.42"
wire \sdram_bankmachine0_cmd_payload_is_cmd
- attribute \src "ls180.v:406.5-406.43"
+ attribute \src "ls180.v:410.5-410.43"
wire \sdram_bankmachine0_cmd_payload_is_read
- attribute \src "ls180.v:407.5-407.44"
+ attribute \src "ls180.v:411.5-411.44"
wire \sdram_bankmachine0_cmd_payload_is_write
- attribute \src "ls180.v:403.5-403.39"
+ attribute \src "ls180.v:407.5-407.39"
wire \sdram_bankmachine0_cmd_payload_ras
- attribute \src "ls180.v:404.5-404.38"
+ attribute \src "ls180.v:408.5-408.38"
wire \sdram_bankmachine0_cmd_payload_we
- attribute \src "ls180.v:399.5-399.33"
+ attribute \src "ls180.v:403.5-403.33"
wire \sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:398.5-398.33"
+ attribute \src "ls180.v:402.5-402.33"
wire \sdram_bankmachine0_cmd_valid
- attribute \src "ls180.v:397.5-397.35"
+ attribute \src "ls180.v:401.5-401.35"
wire \sdram_bankmachine0_refresh_gnt
- attribute \src "ls180.v:396.6-396.36"
+ attribute \src "ls180.v:400.6-400.36"
wire \sdram_bankmachine0_refresh_req
- attribute \src "ls180.v:392.13-392.40"
+ attribute \src "ls180.v:396.13-396.40"
wire width 22 \sdram_bankmachine0_req_addr
- attribute \src "ls180.v:393.6-393.33"
+ attribute \src "ls180.v:397.6-397.33"
wire \sdram_bankmachine0_req_lock
- attribute \src "ls180.v:395.5-395.39"
+ attribute \src "ls180.v:399.5-399.39"
wire \sdram_bankmachine0_req_rdata_valid
- attribute \src "ls180.v:390.6-390.34"
+ attribute \src "ls180.v:394.6-394.34"
wire \sdram_bankmachine0_req_ready
- attribute \src "ls180.v:389.6-389.34"
+ attribute \src "ls180.v:393.6-393.34"
wire \sdram_bankmachine0_req_valid
- attribute \src "ls180.v:394.5-394.39"
+ attribute \src "ls180.v:398.5-398.39"
wire \sdram_bankmachine0_req_wdata_ready
- attribute \src "ls180.v:391.6-391.31"
+ attribute \src "ls180.v:395.6-395.31"
wire \sdram_bankmachine0_req_we
- attribute \src "ls180.v:458.12-458.34"
+ attribute \src "ls180.v:462.12-462.34"
wire width 13 \sdram_bankmachine0_row
- attribute \src "ls180.v:462.5-462.33"
+ attribute \src "ls180.v:466.5-466.33"
wire \sdram_bankmachine0_row_close
- attribute \src "ls180.v:463.5-463.42"
+ attribute \src "ls180.v:467.5-467.42"
wire \sdram_bankmachine0_row_col_n_addr_sel
- attribute \src "ls180.v:460.6-460.32"
+ attribute \src "ls180.v:464.6-464.32"
wire \sdram_bankmachine0_row_hit
- attribute \src "ls180.v:461.5-461.32"
+ attribute \src "ls180.v:465.5-465.32"
wire \sdram_bankmachine0_row_open
- attribute \src "ls180.v:459.5-459.34"
+ attribute \src "ls180.v:463.5-463.34"
wire \sdram_bankmachine0_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:470.32-470.64"
+ attribute \src "ls180.v:474.32-474.64"
wire \sdram_bankmachine0_trascon_ready
- attribute \src "ls180.v:469.6-469.38"
+ attribute \src "ls180.v:473.6-473.38"
wire \sdram_bankmachine0_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:468.32-468.63"
+ attribute \src "ls180.v:472.32-472.63"
wire \sdram_bankmachine0_trccon_ready
- attribute \src "ls180.v:467.6-467.37"
+ attribute \src "ls180.v:471.6-471.37"
wire \sdram_bankmachine0_trccon_valid
- attribute \src "ls180.v:466.11-466.43"
+ attribute \src "ls180.v:470.11-470.43"
wire width 3 \sdram_bankmachine0_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:465.32-465.64"
+ attribute \src "ls180.v:469.32-469.64"
wire \sdram_bankmachine0_twtpcon_ready
- attribute \src "ls180.v:464.6-464.38"
+ attribute \src "ls180.v:468.6-468.38"
wire \sdram_bankmachine0_twtpcon_valid
- attribute \src "ls180.v:490.5-490.38"
+ attribute \src "ls180.v:494.5-494.38"
wire \sdram_bankmachine1_auto_precharge
- attribute \src "ls180.v:512.11-512.58"
+ attribute \src "ls180.v:516.11-516.58"
wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:517.6-517.53"
+ attribute \src "ls180.v:521.6-521.53"
wire \sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:522.6-522.59"
+ attribute \src "ls180.v:526.6-526.59"
wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:523.6-523.58"
+ attribute \src "ls180.v:527.6-527.58"
wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:521.13-521.73"
+ attribute \src "ls180.v:525.13-525.73"
wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:520.6-520.64"
+ attribute \src "ls180.v:524.6-524.64"
wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:526.6-526.60"
+ attribute \src "ls180.v:530.6-530.60"
wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:527.6-527.59"
+ attribute \src "ls180.v:531.6-531.59"
wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:525.13-525.74"
+ attribute \src "ls180.v:529.13-529.74"
wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:524.6-524.65"
+ attribute \src "ls180.v:528.6-528.65"
wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:509.11-509.56"
+ attribute \src "ls180.v:513.11-513.56"
wire width 4 \sdram_bankmachine1_cmd_buffer_lookahead_level
- attribute \src "ls180.v:511.11-511.58"
+ attribute \src "ls180.v:515.11-515.58"
wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:518.12-518.62"
+ attribute \src "ls180.v:522.12-522.62"
wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:519.13-519.65"
+ attribute \src "ls180.v:523.13-523.65"
wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:510.5-510.52"
+ attribute \src "ls180.v:514.5-514.52"
wire \sdram_bankmachine1_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:493.5-493.55"
+ attribute \src "ls180.v:497.5-497.55"
wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:494.5-494.54"
+ attribute \src "ls180.v:498.5-498.54"
wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:496.13-496.70"
+ attribute \src "ls180.v:500.13-500.70"
wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:495.6-495.61"
+ attribute \src "ls180.v:499.6-499.61"
wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:492.6-492.56"
+ attribute \src "ls180.v:496.6-496.56"
wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:491.6-491.56"
+ attribute \src "ls180.v:495.6-495.56"
wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:499.6-499.58"
+ attribute \src "ls180.v:503.6-503.58"
wire \sdram_bankmachine1_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:500.6-500.57"
+ attribute \src "ls180.v:504.6-504.57"
wire \sdram_bankmachine1_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:502.13-502.72"
+ attribute \src "ls180.v:506.13-506.72"
wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:501.6-501.63"
+ attribute \src "ls180.v:505.6-505.63"
wire \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:498.6-498.58"
+ attribute \src "ls180.v:502.6-502.58"
wire \sdram_bankmachine1_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:497.6-497.58"
+ attribute \src "ls180.v:501.6-501.58"
wire \sdram_bankmachine1_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:507.13-507.66"
+ attribute \src "ls180.v:511.13-511.66"
wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
- attribute \src "ls180.v:508.13-508.67"
+ attribute \src "ls180.v:512.13-512.67"
wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
- attribute \src "ls180.v:505.6-505.58"
+ attribute \src "ls180.v:509.6-509.58"
wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
- attribute \src "ls180.v:506.6-506.64"
+ attribute \src "ls180.v:510.6-510.64"
wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
- attribute \src "ls180.v:503.6-503.58"
+ attribute \src "ls180.v:507.6-507.58"
wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
- attribute \src "ls180.v:504.6-504.64"
+ attribute \src "ls180.v:508.6-508.64"
wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- attribute \src "ls180.v:513.11-513.61"
+ attribute \src "ls180.v:517.11-517.61"
wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:514.13-514.65"
+ attribute \src "ls180.v:518.13-518.65"
wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:516.13-516.65"
+ attribute \src "ls180.v:520.13-520.65"
wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:515.6-515.55"
+ attribute \src "ls180.v:519.6-519.55"
wire \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:530.6-530.46"
+ attribute \src "ls180.v:534.6-534.46"
wire \sdram_bankmachine1_cmd_buffer_sink_first
- attribute \src "ls180.v:531.6-531.45"
+ attribute \src "ls180.v:535.6-535.45"
wire \sdram_bankmachine1_cmd_buffer_sink_last
- attribute \src "ls180.v:533.13-533.60"
+ attribute \src "ls180.v:537.13-537.60"
wire width 22 \sdram_bankmachine1_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:532.6-532.51"
+ attribute \src "ls180.v:536.6-536.51"
wire \sdram_bankmachine1_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:529.6-529.46"
+ attribute \src "ls180.v:533.6-533.46"
wire \sdram_bankmachine1_cmd_buffer_sink_ready
- attribute \src "ls180.v:528.6-528.46"
+ attribute \src "ls180.v:532.6-532.46"
wire \sdram_bankmachine1_cmd_buffer_sink_valid
- attribute \src "ls180.v:536.5-536.47"
+ attribute \src "ls180.v:540.5-540.47"
wire \sdram_bankmachine1_cmd_buffer_source_first
- attribute \src "ls180.v:537.5-537.46"
+ attribute \src "ls180.v:541.5-541.46"
wire \sdram_bankmachine1_cmd_buffer_source_last
- attribute \src "ls180.v:539.12-539.61"
+ attribute \src "ls180.v:543.12-543.61"
wire width 22 \sdram_bankmachine1_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:538.5-538.52"
+ attribute \src "ls180.v:542.5-542.52"
wire \sdram_bankmachine1_cmd_buffer_source_payload_we
- attribute \src "ls180.v:535.6-535.48"
+ attribute \src "ls180.v:539.6-539.48"
wire \sdram_bankmachine1_cmd_buffer_source_ready
- attribute \src "ls180.v:534.5-534.47"
+ attribute \src "ls180.v:538.5-538.47"
wire \sdram_bankmachine1_cmd_buffer_source_valid
- attribute \src "ls180.v:482.12-482.44"
+ attribute \src "ls180.v:486.12-486.44"
wire width 13 \sdram_bankmachine1_cmd_payload_a
- attribute \src "ls180.v:483.12-483.45"
+ attribute \src "ls180.v:487.12-487.45"
wire width 2 \sdram_bankmachine1_cmd_payload_ba
- attribute \src "ls180.v:484.5-484.39"
+ attribute \src "ls180.v:488.5-488.39"
wire \sdram_bankmachine1_cmd_payload_cas
- attribute \src "ls180.v:487.5-487.42"
+ attribute \src "ls180.v:491.5-491.42"
wire \sdram_bankmachine1_cmd_payload_is_cmd
- attribute \src "ls180.v:488.5-488.43"
+ attribute \src "ls180.v:492.5-492.43"
wire \sdram_bankmachine1_cmd_payload_is_read
- attribute \src "ls180.v:489.5-489.44"
+ attribute \src "ls180.v:493.5-493.44"
wire \sdram_bankmachine1_cmd_payload_is_write
- attribute \src "ls180.v:485.5-485.39"
+ attribute \src "ls180.v:489.5-489.39"
wire \sdram_bankmachine1_cmd_payload_ras
- attribute \src "ls180.v:486.5-486.38"
+ attribute \src "ls180.v:490.5-490.38"
wire \sdram_bankmachine1_cmd_payload_we
- attribute \src "ls180.v:481.5-481.33"
+ attribute \src "ls180.v:485.5-485.33"
wire \sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:480.5-480.33"
+ attribute \src "ls180.v:484.5-484.33"
wire \sdram_bankmachine1_cmd_valid
- attribute \src "ls180.v:479.5-479.35"
+ attribute \src "ls180.v:483.5-483.35"
wire \sdram_bankmachine1_refresh_gnt
- attribute \src "ls180.v:478.6-478.36"
+ attribute \src "ls180.v:482.6-482.36"
wire \sdram_bankmachine1_refresh_req
- attribute \src "ls180.v:474.13-474.40"
+ attribute \src "ls180.v:478.13-478.40"
wire width 22 \sdram_bankmachine1_req_addr
- attribute \src "ls180.v:475.6-475.33"
+ attribute \src "ls180.v:479.6-479.33"
wire \sdram_bankmachine1_req_lock
- attribute \src "ls180.v:477.5-477.39"
+ attribute \src "ls180.v:481.5-481.39"
wire \sdram_bankmachine1_req_rdata_valid
- attribute \src "ls180.v:472.6-472.34"
+ attribute \src "ls180.v:476.6-476.34"
wire \sdram_bankmachine1_req_ready
- attribute \src "ls180.v:471.6-471.34"
+ attribute \src "ls180.v:475.6-475.34"
wire \sdram_bankmachine1_req_valid
- attribute \src "ls180.v:476.5-476.39"
+ attribute \src "ls180.v:480.5-480.39"
wire \sdram_bankmachine1_req_wdata_ready
- attribute \src "ls180.v:473.6-473.31"
+ attribute \src "ls180.v:477.6-477.31"
wire \sdram_bankmachine1_req_we
- attribute \src "ls180.v:540.12-540.34"
+ attribute \src "ls180.v:544.12-544.34"
wire width 13 \sdram_bankmachine1_row
- attribute \src "ls180.v:544.5-544.33"
+ attribute \src "ls180.v:548.5-548.33"
wire \sdram_bankmachine1_row_close
- attribute \src "ls180.v:545.5-545.42"
+ attribute \src "ls180.v:549.5-549.42"
wire \sdram_bankmachine1_row_col_n_addr_sel
- attribute \src "ls180.v:542.6-542.32"
+ attribute \src "ls180.v:546.6-546.32"
wire \sdram_bankmachine1_row_hit
- attribute \src "ls180.v:543.5-543.32"
+ attribute \src "ls180.v:547.5-547.32"
wire \sdram_bankmachine1_row_open
- attribute \src "ls180.v:541.5-541.34"
+ attribute \src "ls180.v:545.5-545.34"
wire \sdram_bankmachine1_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:552.32-552.64"
+ attribute \src "ls180.v:556.32-556.64"
wire \sdram_bankmachine1_trascon_ready
- attribute \src "ls180.v:551.6-551.38"
+ attribute \src "ls180.v:555.6-555.38"
wire \sdram_bankmachine1_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:550.32-550.63"
+ attribute \src "ls180.v:554.32-554.63"
wire \sdram_bankmachine1_trccon_ready
- attribute \src "ls180.v:549.6-549.37"
+ attribute \src "ls180.v:553.6-553.37"
wire \sdram_bankmachine1_trccon_valid
- attribute \src "ls180.v:548.11-548.43"
+ attribute \src "ls180.v:552.11-552.43"
wire width 3 \sdram_bankmachine1_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:547.32-547.64"
+ attribute \src "ls180.v:551.32-551.64"
wire \sdram_bankmachine1_twtpcon_ready
- attribute \src "ls180.v:546.6-546.38"
+ attribute \src "ls180.v:550.6-550.38"
wire \sdram_bankmachine1_twtpcon_valid
- attribute \src "ls180.v:572.5-572.38"
+ attribute \src "ls180.v:576.5-576.38"
wire \sdram_bankmachine2_auto_precharge
- attribute \src "ls180.v:594.11-594.58"
+ attribute \src "ls180.v:598.11-598.58"
wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:599.6-599.53"
+ attribute \src "ls180.v:603.6-603.53"
wire \sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:604.6-604.59"
+ attribute \src "ls180.v:608.6-608.59"
wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:605.6-605.58"
+ attribute \src "ls180.v:609.6-609.58"
wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:603.13-603.73"
+ attribute \src "ls180.v:607.13-607.73"
wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:602.6-602.64"
+ attribute \src "ls180.v:606.6-606.64"
wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:608.6-608.60"
+ attribute \src "ls180.v:612.6-612.60"
wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:609.6-609.59"
+ attribute \src "ls180.v:613.6-613.59"
wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:607.13-607.74"
+ attribute \src "ls180.v:611.13-611.74"
wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:606.6-606.65"
+ attribute \src "ls180.v:610.6-610.65"
wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:591.11-591.56"
+ attribute \src "ls180.v:595.11-595.56"
wire width 4 \sdram_bankmachine2_cmd_buffer_lookahead_level
- attribute \src "ls180.v:593.11-593.58"
+ attribute \src "ls180.v:597.11-597.58"
wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:600.12-600.62"
+ attribute \src "ls180.v:604.12-604.62"
wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:601.13-601.65"
+ attribute \src "ls180.v:605.13-605.65"
wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:592.5-592.52"
+ attribute \src "ls180.v:596.5-596.52"
wire \sdram_bankmachine2_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:575.5-575.55"
+ attribute \src "ls180.v:579.5-579.55"
wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:576.5-576.54"
+ attribute \src "ls180.v:580.5-580.54"
wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:578.13-578.70"
+ attribute \src "ls180.v:582.13-582.70"
wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:577.6-577.61"
+ attribute \src "ls180.v:581.6-581.61"
wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:574.6-574.56"
+ attribute \src "ls180.v:578.6-578.56"
wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:573.6-573.56"
+ attribute \src "ls180.v:577.6-577.56"
wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:581.6-581.58"
+ attribute \src "ls180.v:585.6-585.58"
wire \sdram_bankmachine2_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:582.6-582.57"
+ attribute \src "ls180.v:586.6-586.57"
wire \sdram_bankmachine2_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:584.13-584.72"
+ attribute \src "ls180.v:588.13-588.72"
wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:583.6-583.63"
+ attribute \src "ls180.v:587.6-587.63"
wire \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:580.6-580.58"
+ attribute \src "ls180.v:584.6-584.58"
wire \sdram_bankmachine2_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:579.6-579.58"
+ attribute \src "ls180.v:583.6-583.58"
wire \sdram_bankmachine2_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:589.13-589.66"
+ attribute \src "ls180.v:593.13-593.66"
wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
- attribute \src "ls180.v:590.13-590.67"
+ attribute \src "ls180.v:594.13-594.67"
wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
- attribute \src "ls180.v:587.6-587.58"
+ attribute \src "ls180.v:591.6-591.58"
wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
- attribute \src "ls180.v:588.6-588.64"
+ attribute \src "ls180.v:592.6-592.64"
wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
- attribute \src "ls180.v:585.6-585.58"
+ attribute \src "ls180.v:589.6-589.58"
wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
- attribute \src "ls180.v:586.6-586.64"
+ attribute \src "ls180.v:590.6-590.64"
wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- attribute \src "ls180.v:595.11-595.61"
+ attribute \src "ls180.v:599.11-599.61"
wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:596.13-596.65"
+ attribute \src "ls180.v:600.13-600.65"
wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:598.13-598.65"
+ attribute \src "ls180.v:602.13-602.65"
wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:597.6-597.55"
+ attribute \src "ls180.v:601.6-601.55"
wire \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:612.6-612.46"
+ attribute \src "ls180.v:616.6-616.46"
wire \sdram_bankmachine2_cmd_buffer_sink_first
- attribute \src "ls180.v:613.6-613.45"
+ attribute \src "ls180.v:617.6-617.45"
wire \sdram_bankmachine2_cmd_buffer_sink_last
- attribute \src "ls180.v:615.13-615.60"
+ attribute \src "ls180.v:619.13-619.60"
wire width 22 \sdram_bankmachine2_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:614.6-614.51"
+ attribute \src "ls180.v:618.6-618.51"
wire \sdram_bankmachine2_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:611.6-611.46"
+ attribute \src "ls180.v:615.6-615.46"
wire \sdram_bankmachine2_cmd_buffer_sink_ready
- attribute \src "ls180.v:610.6-610.46"
+ attribute \src "ls180.v:614.6-614.46"
wire \sdram_bankmachine2_cmd_buffer_sink_valid
- attribute \src "ls180.v:618.5-618.47"
+ attribute \src "ls180.v:622.5-622.47"
wire \sdram_bankmachine2_cmd_buffer_source_first
- attribute \src "ls180.v:619.5-619.46"
+ attribute \src "ls180.v:623.5-623.46"
wire \sdram_bankmachine2_cmd_buffer_source_last
- attribute \src "ls180.v:621.12-621.61"
+ attribute \src "ls180.v:625.12-625.61"
wire width 22 \sdram_bankmachine2_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:620.5-620.52"
+ attribute \src "ls180.v:624.5-624.52"
wire \sdram_bankmachine2_cmd_buffer_source_payload_we
- attribute \src "ls180.v:617.6-617.48"
+ attribute \src "ls180.v:621.6-621.48"
wire \sdram_bankmachine2_cmd_buffer_source_ready
- attribute \src "ls180.v:616.5-616.47"
+ attribute \src "ls180.v:620.5-620.47"
wire \sdram_bankmachine2_cmd_buffer_source_valid
- attribute \src "ls180.v:564.12-564.44"
+ attribute \src "ls180.v:568.12-568.44"
wire width 13 \sdram_bankmachine2_cmd_payload_a
- attribute \src "ls180.v:565.12-565.45"
+ attribute \src "ls180.v:569.12-569.45"
wire width 2 \sdram_bankmachine2_cmd_payload_ba
- attribute \src "ls180.v:566.5-566.39"
+ attribute \src "ls180.v:570.5-570.39"
wire \sdram_bankmachine2_cmd_payload_cas
- attribute \src "ls180.v:569.5-569.42"
+ attribute \src "ls180.v:573.5-573.42"
wire \sdram_bankmachine2_cmd_payload_is_cmd
- attribute \src "ls180.v:570.5-570.43"
+ attribute \src "ls180.v:574.5-574.43"
wire \sdram_bankmachine2_cmd_payload_is_read
- attribute \src "ls180.v:571.5-571.44"
+ attribute \src "ls180.v:575.5-575.44"
wire \sdram_bankmachine2_cmd_payload_is_write
- attribute \src "ls180.v:567.5-567.39"
+ attribute \src "ls180.v:571.5-571.39"
wire \sdram_bankmachine2_cmd_payload_ras
- attribute \src "ls180.v:568.5-568.38"
+ attribute \src "ls180.v:572.5-572.38"
wire \sdram_bankmachine2_cmd_payload_we
- attribute \src "ls180.v:563.5-563.33"
+ attribute \src "ls180.v:567.5-567.33"
wire \sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:562.5-562.33"
+ attribute \src "ls180.v:566.5-566.33"
wire \sdram_bankmachine2_cmd_valid
- attribute \src "ls180.v:561.5-561.35"
+ attribute \src "ls180.v:565.5-565.35"
wire \sdram_bankmachine2_refresh_gnt
- attribute \src "ls180.v:560.6-560.36"
+ attribute \src "ls180.v:564.6-564.36"
wire \sdram_bankmachine2_refresh_req
- attribute \src "ls180.v:556.13-556.40"
+ attribute \src "ls180.v:560.13-560.40"
wire width 22 \sdram_bankmachine2_req_addr
- attribute \src "ls180.v:557.6-557.33"
+ attribute \src "ls180.v:561.6-561.33"
wire \sdram_bankmachine2_req_lock
- attribute \src "ls180.v:559.5-559.39"
+ attribute \src "ls180.v:563.5-563.39"
wire \sdram_bankmachine2_req_rdata_valid
- attribute \src "ls180.v:554.6-554.34"
+ attribute \src "ls180.v:558.6-558.34"
wire \sdram_bankmachine2_req_ready
- attribute \src "ls180.v:553.6-553.34"
+ attribute \src "ls180.v:557.6-557.34"
wire \sdram_bankmachine2_req_valid
- attribute \src "ls180.v:558.5-558.39"
+ attribute \src "ls180.v:562.5-562.39"
wire \sdram_bankmachine2_req_wdata_ready
- attribute \src "ls180.v:555.6-555.31"
+ attribute \src "ls180.v:559.6-559.31"
wire \sdram_bankmachine2_req_we
- attribute \src "ls180.v:622.12-622.34"
+ attribute \src "ls180.v:626.12-626.34"
wire width 13 \sdram_bankmachine2_row
- attribute \src "ls180.v:626.5-626.33"
+ attribute \src "ls180.v:630.5-630.33"
wire \sdram_bankmachine2_row_close
- attribute \src "ls180.v:627.5-627.42"
+ attribute \src "ls180.v:631.5-631.42"
wire \sdram_bankmachine2_row_col_n_addr_sel
- attribute \src "ls180.v:624.6-624.32"
+ attribute \src "ls180.v:628.6-628.32"
wire \sdram_bankmachine2_row_hit
- attribute \src "ls180.v:625.5-625.32"
+ attribute \src "ls180.v:629.5-629.32"
wire \sdram_bankmachine2_row_open
- attribute \src "ls180.v:623.5-623.34"
+ attribute \src "ls180.v:627.5-627.34"
wire \sdram_bankmachine2_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:634.32-634.64"
+ attribute \src "ls180.v:638.32-638.64"
wire \sdram_bankmachine2_trascon_ready
- attribute \src "ls180.v:633.6-633.38"
+ attribute \src "ls180.v:637.6-637.38"
wire \sdram_bankmachine2_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:632.32-632.63"
+ attribute \src "ls180.v:636.32-636.63"
wire \sdram_bankmachine2_trccon_ready
- attribute \src "ls180.v:631.6-631.37"
+ attribute \src "ls180.v:635.6-635.37"
wire \sdram_bankmachine2_trccon_valid
- attribute \src "ls180.v:630.11-630.43"
+ attribute \src "ls180.v:634.11-634.43"
wire width 3 \sdram_bankmachine2_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:629.32-629.64"
+ attribute \src "ls180.v:633.32-633.64"
wire \sdram_bankmachine2_twtpcon_ready
- attribute \src "ls180.v:628.6-628.38"
+ attribute \src "ls180.v:632.6-632.38"
wire \sdram_bankmachine2_twtpcon_valid
- attribute \src "ls180.v:654.5-654.38"
+ attribute \src "ls180.v:658.5-658.38"
wire \sdram_bankmachine3_auto_precharge
- attribute \src "ls180.v:676.11-676.58"
+ attribute \src "ls180.v:680.11-680.58"
wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_consume
- attribute \src "ls180.v:681.6-681.53"
+ attribute \src "ls180.v:685.6-685.53"
wire \sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:686.6-686.59"
+ attribute \src "ls180.v:690.6-690.59"
wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first
- attribute \src "ls180.v:687.6-687.58"
+ attribute \src "ls180.v:691.6-691.58"
wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last
- attribute \src "ls180.v:685.13-685.73"
+ attribute \src "ls180.v:689.13-689.73"
wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr
- attribute \src "ls180.v:684.6-684.64"
+ attribute \src "ls180.v:688.6-688.64"
wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we
- attribute \src "ls180.v:690.6-690.60"
+ attribute \src "ls180.v:694.6-694.60"
wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first
- attribute \src "ls180.v:691.6-691.59"
+ attribute \src "ls180.v:695.6-695.59"
wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last
- attribute \src "ls180.v:689.13-689.74"
+ attribute \src "ls180.v:693.13-693.74"
wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
- attribute \src "ls180.v:688.6-688.65"
+ attribute \src "ls180.v:692.6-692.65"
wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we
- attribute \src "ls180.v:673.11-673.56"
+ attribute \src "ls180.v:677.11-677.56"
wire width 4 \sdram_bankmachine3_cmd_buffer_lookahead_level
- attribute \src "ls180.v:675.11-675.58"
+ attribute \src "ls180.v:679.11-679.58"
wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_produce
- attribute \src "ls180.v:682.12-682.62"
+ attribute \src "ls180.v:686.12-686.62"
wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
- attribute \src "ls180.v:683.13-683.65"
+ attribute \src "ls180.v:687.13-687.65"
wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
- attribute \src "ls180.v:674.5-674.52"
+ attribute \src "ls180.v:678.5-678.52"
wire \sdram_bankmachine3_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:657.5-657.55"
+ attribute \src "ls180.v:661.5-661.55"
wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_first
- attribute \src "ls180.v:658.5-658.54"
+ attribute \src "ls180.v:662.5-662.54"
wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_last
- attribute \src "ls180.v:660.13-660.70"
+ attribute \src "ls180.v:664.13-664.70"
wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr
- attribute \src "ls180.v:659.6-659.61"
+ attribute \src "ls180.v:663.6-663.61"
wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we
- attribute \src "ls180.v:656.6-656.56"
+ attribute \src "ls180.v:660.6-660.56"
wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
- attribute \src "ls180.v:655.6-655.56"
+ attribute \src "ls180.v:659.6-659.56"
wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid
- attribute \src "ls180.v:663.6-663.58"
+ attribute \src "ls180.v:667.6-667.58"
wire \sdram_bankmachine3_cmd_buffer_lookahead_source_first
- attribute \src "ls180.v:664.6-664.57"
+ attribute \src "ls180.v:668.6-668.57"
wire \sdram_bankmachine3_cmd_buffer_lookahead_source_last
- attribute \src "ls180.v:666.13-666.72"
+ attribute \src "ls180.v:670.13-670.72"
wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
- attribute \src "ls180.v:665.6-665.63"
+ attribute \src "ls180.v:669.6-669.63"
wire \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
- attribute \src "ls180.v:662.6-662.58"
+ attribute \src "ls180.v:666.6-666.58"
wire \sdram_bankmachine3_cmd_buffer_lookahead_source_ready
- attribute \src "ls180.v:661.6-661.58"
+ attribute \src "ls180.v:665.6-665.58"
wire \sdram_bankmachine3_cmd_buffer_lookahead_source_valid
- attribute \src "ls180.v:671.13-671.66"
+ attribute \src "ls180.v:675.13-675.66"
wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
- attribute \src "ls180.v:672.13-672.67"
+ attribute \src "ls180.v:676.13-676.67"
wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
- attribute \src "ls180.v:669.6-669.58"
+ attribute \src "ls180.v:673.6-673.58"
wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
- attribute \src "ls180.v:670.6-670.64"
+ attribute \src "ls180.v:674.6-674.64"
wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
- attribute \src "ls180.v:667.6-667.58"
+ attribute \src "ls180.v:671.6-671.58"
wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
- attribute \src "ls180.v:668.6-668.64"
+ attribute \src "ls180.v:672.6-672.64"
wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- attribute \src "ls180.v:677.11-677.61"
+ attribute \src "ls180.v:681.11-681.61"
wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
- attribute \src "ls180.v:678.13-678.65"
+ attribute \src "ls180.v:682.13-682.65"
wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r
- attribute \src "ls180.v:680.13-680.65"
+ attribute \src "ls180.v:684.13-684.65"
wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
- attribute \src "ls180.v:679.6-679.55"
+ attribute \src "ls180.v:683.6-683.55"
wire \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:694.6-694.46"
+ attribute \src "ls180.v:698.6-698.46"
wire \sdram_bankmachine3_cmd_buffer_sink_first
- attribute \src "ls180.v:695.6-695.45"
+ attribute \src "ls180.v:699.6-699.45"
wire \sdram_bankmachine3_cmd_buffer_sink_last
- attribute \src "ls180.v:697.13-697.60"
+ attribute \src "ls180.v:701.13-701.60"
wire width 22 \sdram_bankmachine3_cmd_buffer_sink_payload_addr
- attribute \src "ls180.v:696.6-696.51"
+ attribute \src "ls180.v:700.6-700.51"
wire \sdram_bankmachine3_cmd_buffer_sink_payload_we
- attribute \src "ls180.v:693.6-693.46"
+ attribute \src "ls180.v:697.6-697.46"
wire \sdram_bankmachine3_cmd_buffer_sink_ready
- attribute \src "ls180.v:692.6-692.46"
+ attribute \src "ls180.v:696.6-696.46"
wire \sdram_bankmachine3_cmd_buffer_sink_valid
- attribute \src "ls180.v:700.5-700.47"
+ attribute \src "ls180.v:704.5-704.47"
wire \sdram_bankmachine3_cmd_buffer_source_first
- attribute \src "ls180.v:701.5-701.46"
+ attribute \src "ls180.v:705.5-705.46"
wire \sdram_bankmachine3_cmd_buffer_source_last
- attribute \src "ls180.v:703.12-703.61"
+ attribute \src "ls180.v:707.12-707.61"
wire width 22 \sdram_bankmachine3_cmd_buffer_source_payload_addr
- attribute \src "ls180.v:702.5-702.52"
+ attribute \src "ls180.v:706.5-706.52"
wire \sdram_bankmachine3_cmd_buffer_source_payload_we
- attribute \src "ls180.v:699.6-699.48"
+ attribute \src "ls180.v:703.6-703.48"
wire \sdram_bankmachine3_cmd_buffer_source_ready
- attribute \src "ls180.v:698.5-698.47"
+ attribute \src "ls180.v:702.5-702.47"
wire \sdram_bankmachine3_cmd_buffer_source_valid
- attribute \src "ls180.v:646.12-646.44"
+ attribute \src "ls180.v:650.12-650.44"
wire width 13 \sdram_bankmachine3_cmd_payload_a
- attribute \src "ls180.v:647.12-647.45"
+ attribute \src "ls180.v:651.12-651.45"
wire width 2 \sdram_bankmachine3_cmd_payload_ba
- attribute \src "ls180.v:648.5-648.39"
+ attribute \src "ls180.v:652.5-652.39"
wire \sdram_bankmachine3_cmd_payload_cas
- attribute \src "ls180.v:651.5-651.42"
+ attribute \src "ls180.v:655.5-655.42"
wire \sdram_bankmachine3_cmd_payload_is_cmd
- attribute \src "ls180.v:652.5-652.43"
+ attribute \src "ls180.v:656.5-656.43"
wire \sdram_bankmachine3_cmd_payload_is_read
- attribute \src "ls180.v:653.5-653.44"
+ attribute \src "ls180.v:657.5-657.44"
wire \sdram_bankmachine3_cmd_payload_is_write
- attribute \src "ls180.v:649.5-649.39"
+ attribute \src "ls180.v:653.5-653.39"
wire \sdram_bankmachine3_cmd_payload_ras
- attribute \src "ls180.v:650.5-650.38"
+ attribute \src "ls180.v:654.5-654.38"
wire \sdram_bankmachine3_cmd_payload_we
- attribute \src "ls180.v:645.5-645.33"
+ attribute \src "ls180.v:649.5-649.33"
wire \sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:644.5-644.33"
+ attribute \src "ls180.v:648.5-648.33"
wire \sdram_bankmachine3_cmd_valid
- attribute \src "ls180.v:643.5-643.35"
+ attribute \src "ls180.v:647.5-647.35"
wire \sdram_bankmachine3_refresh_gnt
- attribute \src "ls180.v:642.6-642.36"
+ attribute \src "ls180.v:646.6-646.36"
wire \sdram_bankmachine3_refresh_req
- attribute \src "ls180.v:638.13-638.40"
+ attribute \src "ls180.v:642.13-642.40"
wire width 22 \sdram_bankmachine3_req_addr
- attribute \src "ls180.v:639.6-639.33"
+ attribute \src "ls180.v:643.6-643.33"
wire \sdram_bankmachine3_req_lock
- attribute \src "ls180.v:641.5-641.39"
+ attribute \src "ls180.v:645.5-645.39"
wire \sdram_bankmachine3_req_rdata_valid
- attribute \src "ls180.v:636.6-636.34"
+ attribute \src "ls180.v:640.6-640.34"
wire \sdram_bankmachine3_req_ready
- attribute \src "ls180.v:635.6-635.34"
+ attribute \src "ls180.v:639.6-639.34"
wire \sdram_bankmachine3_req_valid
- attribute \src "ls180.v:640.5-640.39"
+ attribute \src "ls180.v:644.5-644.39"
wire \sdram_bankmachine3_req_wdata_ready
- attribute \src "ls180.v:637.6-637.31"
+ attribute \src "ls180.v:641.6-641.31"
wire \sdram_bankmachine3_req_we
- attribute \src "ls180.v:704.12-704.34"
+ attribute \src "ls180.v:708.12-708.34"
wire width 13 \sdram_bankmachine3_row
- attribute \src "ls180.v:708.5-708.33"
+ attribute \src "ls180.v:712.5-712.33"
wire \sdram_bankmachine3_row_close
- attribute \src "ls180.v:709.5-709.42"
+ attribute \src "ls180.v:713.5-713.42"
wire \sdram_bankmachine3_row_col_n_addr_sel
- attribute \src "ls180.v:706.6-706.32"
+ attribute \src "ls180.v:710.6-710.32"
wire \sdram_bankmachine3_row_hit
- attribute \src "ls180.v:707.5-707.32"
+ attribute \src "ls180.v:711.5-711.32"
wire \sdram_bankmachine3_row_open
- attribute \src "ls180.v:705.5-705.34"
+ attribute \src "ls180.v:709.5-709.34"
wire \sdram_bankmachine3_row_opened
attribute \no_retiming "true"
- attribute \src "ls180.v:716.32-716.64"
+ attribute \src "ls180.v:720.32-720.64"
wire \sdram_bankmachine3_trascon_ready
- attribute \src "ls180.v:715.6-715.38"
+ attribute \src "ls180.v:719.6-719.38"
wire \sdram_bankmachine3_trascon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:714.32-714.63"
+ attribute \src "ls180.v:718.32-718.63"
wire \sdram_bankmachine3_trccon_ready
- attribute \src "ls180.v:713.6-713.37"
+ attribute \src "ls180.v:717.6-717.37"
wire \sdram_bankmachine3_trccon_valid
- attribute \src "ls180.v:712.11-712.43"
+ attribute \src "ls180.v:716.11-716.43"
wire width 3 \sdram_bankmachine3_twtpcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:711.32-711.64"
+ attribute \src "ls180.v:715.32-715.64"
wire \sdram_bankmachine3_twtpcon_ready
- attribute \src "ls180.v:710.6-710.38"
+ attribute \src "ls180.v:714.6-714.38"
wire \sdram_bankmachine3_twtpcon_valid
- attribute \src "ls180.v:718.6-718.23"
+ attribute \src "ls180.v:722.6-722.23"
wire \sdram_cas_allowed
- attribute \src "ls180.v:21.14-21.25"
- wire output 17 \sdram_cas_n
- attribute \src "ls180.v:736.6-736.25"
+ attribute \src "ls180.v:27.14-27.25"
+ wire output 23 \sdram_cas_n
+ attribute \src "ls180.v:740.6-740.25"
wire \sdram_choose_cmd_ce
- attribute \src "ls180.v:725.13-725.43"
+ attribute \src "ls180.v:729.13-729.43"
wire width 13 \sdram_choose_cmd_cmd_payload_a
- attribute \src "ls180.v:726.12-726.43"
+ attribute \src "ls180.v:730.12-730.43"
wire width 2 \sdram_choose_cmd_cmd_payload_ba
- attribute \src "ls180.v:727.5-727.37"
+ attribute \src "ls180.v:731.5-731.37"
wire \sdram_choose_cmd_cmd_payload_cas
- attribute \src "ls180.v:730.6-730.41"
+ attribute \src "ls180.v:734.6-734.41"
wire \sdram_choose_cmd_cmd_payload_is_cmd
- attribute \src "ls180.v:731.6-731.42"
+ attribute \src "ls180.v:735.6-735.42"
wire \sdram_choose_cmd_cmd_payload_is_read
- attribute \src "ls180.v:732.6-732.43"
+ attribute \src "ls180.v:736.6-736.43"
wire \sdram_choose_cmd_cmd_payload_is_write
- attribute \src "ls180.v:728.5-728.37"
+ attribute \src "ls180.v:732.5-732.37"
wire \sdram_choose_cmd_cmd_payload_ras
- attribute \src "ls180.v:729.5-729.36"
+ attribute \src "ls180.v:733.5-733.36"
wire \sdram_choose_cmd_cmd_payload_we
- attribute \src "ls180.v:724.5-724.31"
+ attribute \src "ls180.v:728.5-728.31"
wire \sdram_choose_cmd_cmd_ready
- attribute \src "ls180.v:723.6-723.32"
+ attribute \src "ls180.v:727.6-727.32"
wire \sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:735.11-735.33"
+ attribute \src "ls180.v:739.11-739.33"
wire width 2 \sdram_choose_cmd_grant
- attribute \src "ls180.v:734.12-734.36"
+ attribute \src "ls180.v:738.12-738.36"
wire width 4 \sdram_choose_cmd_request
- attribute \src "ls180.v:733.11-733.34"
+ attribute \src "ls180.v:737.11-737.34"
wire width 4 \sdram_choose_cmd_valids
- attribute \src "ls180.v:722.5-722.36"
+ attribute \src "ls180.v:726.5-726.36"
wire \sdram_choose_cmd_want_activates
- attribute \src "ls180.v:721.5-721.31"
+ attribute \src "ls180.v:725.5-725.31"
wire \sdram_choose_cmd_want_cmds
- attribute \src "ls180.v:719.5-719.32"
+ attribute \src "ls180.v:723.5-723.32"
wire \sdram_choose_cmd_want_reads
- attribute \src "ls180.v:720.5-720.33"
+ attribute \src "ls180.v:724.5-724.33"
wire \sdram_choose_cmd_want_writes
- attribute \src "ls180.v:754.6-754.25"
+ attribute \src "ls180.v:758.6-758.25"
wire \sdram_choose_req_ce
- attribute \src "ls180.v:743.13-743.43"
+ attribute \src "ls180.v:747.13-747.43"
wire width 13 \sdram_choose_req_cmd_payload_a
- attribute \src "ls180.v:744.12-744.43"
+ attribute \src "ls180.v:748.12-748.43"
wire width 2 \sdram_choose_req_cmd_payload_ba
- attribute \src "ls180.v:745.5-745.37"
+ attribute \src "ls180.v:749.5-749.37"
wire \sdram_choose_req_cmd_payload_cas
- attribute \src "ls180.v:748.6-748.41"
+ attribute \src "ls180.v:752.6-752.41"
wire \sdram_choose_req_cmd_payload_is_cmd
- attribute \src "ls180.v:749.6-749.42"
+ attribute \src "ls180.v:753.6-753.42"
wire \sdram_choose_req_cmd_payload_is_read
- attribute \src "ls180.v:750.6-750.43"
+ attribute \src "ls180.v:754.6-754.43"
wire \sdram_choose_req_cmd_payload_is_write
- attribute \src "ls180.v:746.5-746.37"
+ attribute \src "ls180.v:750.5-750.37"
wire \sdram_choose_req_cmd_payload_ras
- attribute \src "ls180.v:747.5-747.36"
+ attribute \src "ls180.v:751.5-751.36"
wire \sdram_choose_req_cmd_payload_we
- attribute \src "ls180.v:742.5-742.31"
+ attribute \src "ls180.v:746.5-746.31"
wire \sdram_choose_req_cmd_ready
- attribute \src "ls180.v:741.6-741.32"
+ attribute \src "ls180.v:745.6-745.32"
wire \sdram_choose_req_cmd_valid
- attribute \src "ls180.v:753.11-753.33"
+ attribute \src "ls180.v:757.11-757.33"
wire width 2 \sdram_choose_req_grant
- attribute \src "ls180.v:752.12-752.36"
+ attribute \src "ls180.v:756.12-756.36"
wire width 4 \sdram_choose_req_request
- attribute \src "ls180.v:751.11-751.34"
+ attribute \src "ls180.v:755.11-755.34"
wire width 4 \sdram_choose_req_valids
- attribute \src "ls180.v:740.5-740.36"
+ attribute \src "ls180.v:744.5-744.36"
wire \sdram_choose_req_want_activates
- attribute \src "ls180.v:739.6-739.32"
+ attribute \src "ls180.v:743.6-743.32"
wire \sdram_choose_req_want_cmds
- attribute \src "ls180.v:737.5-737.32"
+ attribute \src "ls180.v:741.5-741.32"
wire \sdram_choose_req_want_reads
- attribute \src "ls180.v:738.5-738.33"
+ attribute \src "ls180.v:742.5-742.33"
wire \sdram_choose_req_want_writes
- attribute \src "ls180.v:23.14-23.23"
- wire output 19 \sdram_cke
- attribute \src "ls180.v:298.6-298.17"
+ attribute \src "ls180.v:29.14-29.23"
+ wire output 25 \sdram_cke
+ attribute \src "ls180.v:302.6-302.17"
wire \sdram_cke_1
- attribute \src "ls180.v:136.5-136.16"
- wire \sdram_clock
- attribute \src "ls180.v:26.14-26.27"
- wire output 22 \sdram_clock_1
- attribute \src "ls180.v:366.5-366.19"
+ attribute \src "ls180.v:32.14-32.25"
+ wire output 28 \sdram_clock
+ attribute \src "ls180.v:370.5-370.19"
wire \sdram_cmd_last
- attribute \src "ls180.v:367.12-367.31"
+ attribute \src "ls180.v:371.12-371.31"
wire width 13 \sdram_cmd_payload_a
- attribute \src "ls180.v:368.11-368.31"
+ attribute \src "ls180.v:372.11-372.31"
wire width 2 \sdram_cmd_payload_ba
- attribute \src "ls180.v:369.5-369.26"
+ attribute \src "ls180.v:373.5-373.26"
wire \sdram_cmd_payload_cas
- attribute \src "ls180.v:372.5-372.30"
+ attribute \src "ls180.v:376.5-376.30"
wire \sdram_cmd_payload_is_read
- attribute \src "ls180.v:373.5-373.31"
+ attribute \src "ls180.v:377.5-377.31"
wire \sdram_cmd_payload_is_write
- attribute \src "ls180.v:370.5-370.26"
+ attribute \src "ls180.v:374.5-374.26"
wire \sdram_cmd_payload_ras
- attribute \src "ls180.v:371.5-371.25"
+ attribute \src "ls180.v:375.5-375.25"
wire \sdram_cmd_payload_we
- attribute \src "ls180.v:365.5-365.20"
+ attribute \src "ls180.v:369.5-369.20"
wire \sdram_cmd_ready
- attribute \src "ls180.v:364.5-364.20"
+ attribute \src "ls180.v:368.5-368.20"
wire \sdram_cmd_valid
- attribute \src "ls180.v:306.6-306.27"
+ attribute \src "ls180.v:310.6-310.27"
wire \sdram_command_issue_r
- attribute \src "ls180.v:305.6-305.28"
+ attribute \src "ls180.v:309.6-309.28"
wire \sdram_command_issue_re
- attribute \src "ls180.v:308.5-308.26"
+ attribute \src "ls180.v:312.5-312.26"
wire \sdram_command_issue_w
- attribute \src "ls180.v:307.6-307.28"
+ attribute \src "ls180.v:311.6-311.28"
wire \sdram_command_issue_we
- attribute \src "ls180.v:304.5-304.21"
+ attribute \src "ls180.v:308.5-308.21"
wire \sdram_command_re
- attribute \src "ls180.v:303.11-303.32"
+ attribute \src "ls180.v:307.11-307.32"
wire width 6 \sdram_command_storage
- attribute \src "ls180.v:22.14-22.24"
- wire output 18 \sdram_cs_n
- attribute \src "ls180.v:357.5-357.23"
+ attribute \src "ls180.v:28.14-28.24"
+ wire output 24 \sdram_cs_n
+ attribute \src "ls180.v:361.5-361.23"
wire \sdram_dfi_p0_act_n
- attribute \src "ls180.v:348.12-348.32"
+ attribute \src "ls180.v:352.12-352.32"
wire width 13 \sdram_dfi_p0_address
- attribute \src "ls180.v:349.11-349.28"
+ attribute \src "ls180.v:353.11-353.28"
wire width 2 \sdram_dfi_p0_bank
- attribute \src "ls180.v:350.5-350.23"
+ attribute \src "ls180.v:354.5-354.23"
wire \sdram_dfi_p0_cas_n
- attribute \src "ls180.v:354.6-354.22"
+ attribute \src "ls180.v:358.6-358.22"
wire \sdram_dfi_p0_cke
- attribute \src "ls180.v:351.5-351.22"
+ attribute \src "ls180.v:355.5-355.22"
wire \sdram_dfi_p0_cs_n
- attribute \src "ls180.v:355.6-355.22"
+ attribute \src "ls180.v:359.6-359.22"
wire \sdram_dfi_p0_odt
- attribute \src "ls180.v:352.5-352.23"
+ attribute \src "ls180.v:356.5-356.23"
wire \sdram_dfi_p0_ras_n
- attribute \src "ls180.v:362.13-362.32"
+ attribute \src "ls180.v:366.13-366.32"
wire width 16 \sdram_dfi_p0_rddata
- attribute \src "ls180.v:361.5-361.27"
+ attribute \src "ls180.v:365.5-365.27"
wire \sdram_dfi_p0_rddata_en
- attribute \src "ls180.v:363.6-363.31"
+ attribute \src "ls180.v:367.6-367.31"
wire \sdram_dfi_p0_rddata_valid
- attribute \src "ls180.v:356.6-356.26"
+ attribute \src "ls180.v:360.6-360.26"
wire \sdram_dfi_p0_reset_n
- attribute \src "ls180.v:353.5-353.22"
+ attribute \src "ls180.v:357.5-357.22"
wire \sdram_dfi_p0_we_n
- attribute \src "ls180.v:358.13-358.32"
+ attribute \src "ls180.v:362.13-362.32"
wire width 16 \sdram_dfi_p0_wrdata
- attribute \src "ls180.v:359.5-359.27"
+ attribute \src "ls180.v:363.5-363.27"
wire \sdram_dfi_p0_wrdata_en
- attribute \src "ls180.v:360.12-360.36"
+ attribute \src "ls180.v:364.12-364.36"
wire width 2 \sdram_dfi_p0_wrdata_mask
- attribute \src "ls180.v:25.20-25.28"
- wire width 2 output 21 \sdram_dm
- attribute \src "ls180.v:16.20-16.30"
- wire width 16 input 12 \sdram_dq_i
- attribute \src "ls180.v:17.21-17.31"
- wire width 16 output 13 \sdram_dq_o
- attribute \src "ls180.v:18.14-18.25"
- wire output 14 \sdram_dq_oe
- attribute \src "ls180.v:772.5-772.14"
+ attribute \src "ls180.v:31.20-31.28"
+ wire width 2 output 27 \sdram_dm
+ attribute \src "ls180.v:22.20-22.30"
+ wire width 16 input 18 \sdram_dq_i
+ attribute \src "ls180.v:23.21-23.31"
+ wire width 16 output 19 \sdram_dq_o
+ attribute \src "ls180.v:24.14-24.25"
+ wire output 20 \sdram_dq_oe
+ attribute \src "ls180.v:776.5-776.14"
wire \sdram_en0
- attribute \src "ls180.v:775.5-775.14"
+ attribute \src "ls180.v:779.5-779.14"
wire \sdram_en1
- attribute \src "ls180.v:778.6-778.25"
+ attribute \src "ls180.v:782.6-782.25"
wire \sdram_go_to_refresh
- attribute \src "ls180.v:320.13-320.39"
+ attribute \src "ls180.v:324.13-324.39"
wire width 22 \sdram_interface_bank0_addr
- attribute \src "ls180.v:321.6-321.32"
+ attribute \src "ls180.v:325.6-325.32"
wire \sdram_interface_bank0_lock
- attribute \src "ls180.v:323.6-323.39"
+ attribute \src "ls180.v:327.6-327.39"
wire \sdram_interface_bank0_rdata_valid
- attribute \src "ls180.v:318.6-318.33"
+ attribute \src "ls180.v:322.6-322.33"
wire \sdram_interface_bank0_ready
- attribute \src "ls180.v:317.6-317.33"
+ attribute \src "ls180.v:321.6-321.33"
wire \sdram_interface_bank0_valid
- attribute \src "ls180.v:322.6-322.39"
+ attribute \src "ls180.v:326.6-326.39"
wire \sdram_interface_bank0_wdata_ready
- attribute \src "ls180.v:319.6-319.30"
+ attribute \src "ls180.v:323.6-323.30"
wire \sdram_interface_bank0_we
- attribute \src "ls180.v:327.13-327.39"
+ attribute \src "ls180.v:331.13-331.39"
wire width 22 \sdram_interface_bank1_addr
- attribute \src "ls180.v:328.6-328.32"
+ attribute \src "ls180.v:332.6-332.32"
wire \sdram_interface_bank1_lock
- attribute \src "ls180.v:330.6-330.39"
+ attribute \src "ls180.v:334.6-334.39"
wire \sdram_interface_bank1_rdata_valid
- attribute \src "ls180.v:325.6-325.33"
+ attribute \src "ls180.v:329.6-329.33"
wire \sdram_interface_bank1_ready
- attribute \src "ls180.v:324.6-324.33"
+ attribute \src "ls180.v:328.6-328.33"
wire \sdram_interface_bank1_valid
- attribute \src "ls180.v:329.6-329.39"
+ attribute \src "ls180.v:333.6-333.39"
wire \sdram_interface_bank1_wdata_ready
- attribute \src "ls180.v:326.6-326.30"
+ attribute \src "ls180.v:330.6-330.30"
wire \sdram_interface_bank1_we
- attribute \src "ls180.v:334.13-334.39"
+ attribute \src "ls180.v:338.13-338.39"
wire width 22 \sdram_interface_bank2_addr
- attribute \src "ls180.v:335.6-335.32"
+ attribute \src "ls180.v:339.6-339.32"
wire \sdram_interface_bank2_lock
- attribute \src "ls180.v:337.6-337.39"
+ attribute \src "ls180.v:341.6-341.39"
wire \sdram_interface_bank2_rdata_valid
- attribute \src "ls180.v:332.6-332.33"
+ attribute \src "ls180.v:336.6-336.33"
wire \sdram_interface_bank2_ready
- attribute \src "ls180.v:331.6-331.33"
+ attribute \src "ls180.v:335.6-335.33"
wire \sdram_interface_bank2_valid
- attribute \src "ls180.v:336.6-336.39"
+ attribute \src "ls180.v:340.6-340.39"
wire \sdram_interface_bank2_wdata_ready
- attribute \src "ls180.v:333.6-333.30"
+ attribute \src "ls180.v:337.6-337.30"
wire \sdram_interface_bank2_we
- attribute \src "ls180.v:341.13-341.39"
+ attribute \src "ls180.v:345.13-345.39"
wire width 22 \sdram_interface_bank3_addr
- attribute \src "ls180.v:342.6-342.32"
+ attribute \src "ls180.v:346.6-346.32"
wire \sdram_interface_bank3_lock
- attribute \src "ls180.v:344.6-344.39"
+ attribute \src "ls180.v:348.6-348.39"
wire \sdram_interface_bank3_rdata_valid
- attribute \src "ls180.v:339.6-339.33"
+ attribute \src "ls180.v:343.6-343.33"
wire \sdram_interface_bank3_ready
- attribute \src "ls180.v:338.6-338.33"
+ attribute \src "ls180.v:342.6-342.33"
wire \sdram_interface_bank3_valid
- attribute \src "ls180.v:343.6-343.39"
+ attribute \src "ls180.v:347.6-347.39"
wire \sdram_interface_bank3_wdata_ready
- attribute \src "ls180.v:340.6-340.30"
+ attribute \src "ls180.v:344.6-344.30"
wire \sdram_interface_bank3_we
- attribute \src "ls180.v:347.13-347.34"
+ attribute \src "ls180.v:351.13-351.34"
wire width 16 \sdram_interface_rdata
- attribute \src "ls180.v:345.12-345.33"
+ attribute \src "ls180.v:349.12-349.33"
wire width 16 \sdram_interface_wdata
- attribute \src "ls180.v:346.11-346.35"
+ attribute \src "ls180.v:350.11-350.35"
wire width 2 \sdram_interface_wdata_we
- attribute \src "ls180.v:258.5-258.24"
+ attribute \src "ls180.v:262.5-262.24"
wire \sdram_inti_p0_act_n
- attribute \src "ls180.v:249.13-249.34"
+ attribute \src "ls180.v:253.13-253.34"
wire width 13 \sdram_inti_p0_address
- attribute \src "ls180.v:250.12-250.30"
+ attribute \src "ls180.v:254.12-254.30"
wire width 2 \sdram_inti_p0_bank
- attribute \src "ls180.v:251.5-251.24"
+ attribute \src "ls180.v:255.5-255.24"
wire \sdram_inti_p0_cas_n
- attribute \src "ls180.v:255.6-255.23"
+ attribute \src "ls180.v:259.6-259.23"
wire \sdram_inti_p0_cke
- attribute \src "ls180.v:252.5-252.23"
+ attribute \src "ls180.v:256.5-256.23"
wire \sdram_inti_p0_cs_n
- attribute \src "ls180.v:256.6-256.23"
+ attribute \src "ls180.v:260.6-260.23"
wire \sdram_inti_p0_odt
- attribute \src "ls180.v:253.5-253.24"
+ attribute \src "ls180.v:257.5-257.24"
wire \sdram_inti_p0_ras_n
- attribute \src "ls180.v:263.12-263.32"
+ attribute \src "ls180.v:267.12-267.32"
wire width 16 \sdram_inti_p0_rddata
- attribute \src "ls180.v:262.6-262.29"
+ attribute \src "ls180.v:266.6-266.29"
wire \sdram_inti_p0_rddata_en
- attribute \src "ls180.v:264.5-264.31"
+ attribute \src "ls180.v:268.5-268.31"
wire \sdram_inti_p0_rddata_valid
- attribute \src "ls180.v:257.6-257.27"
+ attribute \src "ls180.v:261.6-261.27"
wire \sdram_inti_p0_reset_n
- attribute \src "ls180.v:254.5-254.23"
+ attribute \src "ls180.v:258.5-258.23"
wire \sdram_inti_p0_we_n
- attribute \src "ls180.v:259.13-259.33"
+ attribute \src "ls180.v:263.13-263.33"
wire width 16 \sdram_inti_p0_wrdata
- attribute \src "ls180.v:260.6-260.29"
+ attribute \src "ls180.v:264.6-264.29"
wire \sdram_inti_p0_wrdata_en
- attribute \src "ls180.v:261.12-261.37"
+ attribute \src "ls180.v:265.12-265.37"
wire width 2 \sdram_inti_p0_wrdata_mask
- attribute \src "ls180.v:290.5-290.26"
+ attribute \src "ls180.v:294.5-294.26"
wire \sdram_master_p0_act_n
- attribute \src "ls180.v:281.12-281.35"
+ attribute \src "ls180.v:285.12-285.35"
wire width 13 \sdram_master_p0_address
- attribute \src "ls180.v:282.11-282.31"
+ attribute \src "ls180.v:286.11-286.31"
wire width 2 \sdram_master_p0_bank
- attribute \src "ls180.v:283.5-283.26"
+ attribute \src "ls180.v:287.5-287.26"
wire \sdram_master_p0_cas_n
- attribute \src "ls180.v:287.5-287.24"
+ attribute \src "ls180.v:291.5-291.24"
wire \sdram_master_p0_cke
- attribute \src "ls180.v:284.5-284.25"
+ attribute \src "ls180.v:288.5-288.25"
wire \sdram_master_p0_cs_n
- attribute \src "ls180.v:288.5-288.24"
+ attribute \src "ls180.v:292.5-292.24"
wire \sdram_master_p0_odt
- attribute \src "ls180.v:285.5-285.26"
+ attribute \src "ls180.v:289.5-289.26"
wire \sdram_master_p0_ras_n
- attribute \src "ls180.v:295.13-295.35"
+ attribute \src "ls180.v:299.13-299.35"
wire width 16 \sdram_master_p0_rddata
- attribute \src "ls180.v:294.5-294.30"
+ attribute \src "ls180.v:298.5-298.30"
wire \sdram_master_p0_rddata_en
- attribute \src "ls180.v:296.6-296.34"
+ attribute \src "ls180.v:300.6-300.34"
wire \sdram_master_p0_rddata_valid
- attribute \src "ls180.v:289.5-289.28"
+ attribute \src "ls180.v:293.5-293.28"
wire \sdram_master_p0_reset_n
- attribute \src "ls180.v:286.5-286.25"
+ attribute \src "ls180.v:290.5-290.25"
wire \sdram_master_p0_we_n
- attribute \src "ls180.v:291.12-291.34"
+ attribute \src "ls180.v:295.12-295.34"
wire width 16 \sdram_master_p0_wrdata
- attribute \src "ls180.v:292.5-292.30"
+ attribute \src "ls180.v:296.5-296.30"
wire \sdram_master_p0_wrdata_en
- attribute \src "ls180.v:293.11-293.38"
+ attribute \src "ls180.v:297.11-297.38"
wire width 2 \sdram_master_p0_wrdata_mask
- attribute \src "ls180.v:773.6-773.21"
+ attribute \src "ls180.v:777.6-777.21"
wire \sdram_max_time0
- attribute \src "ls180.v:776.6-776.21"
+ attribute \src "ls180.v:780.6-780.21"
wire \sdram_max_time1
- attribute \src "ls180.v:755.12-755.23"
+ attribute \src "ls180.v:759.12-759.23"
wire width 13 \sdram_nop_a
- attribute \src "ls180.v:756.11-756.23"
+ attribute \src "ls180.v:760.11-760.23"
wire width 2 \sdram_nop_ba
- attribute \src "ls180.v:299.6-299.15"
+ attribute \src "ls180.v:303.6-303.15"
wire \sdram_odt
- attribute \src "ls180.v:382.5-382.26"
+ attribute \src "ls180.v:386.5-386.26"
wire \sdram_postponer_count
- attribute \src "ls180.v:380.6-380.27"
+ attribute \src "ls180.v:384.6-384.27"
wire \sdram_postponer_req_i
- attribute \src "ls180.v:381.5-381.26"
+ attribute \src "ls180.v:385.5-385.26"
wire \sdram_postponer_req_o
- attribute \src "ls180.v:717.6-717.23"
+ attribute \src "ls180.v:721.6-721.23"
wire \sdram_ras_allowed
- attribute \src "ls180.v:20.14-20.25"
- wire output 16 \sdram_ras_n
- attribute \src "ls180.v:302.5-302.13"
+ attribute \src "ls180.v:26.14-26.25"
+ wire output 22 \sdram_ras_n
+ attribute \src "ls180.v:306.5-306.13"
wire \sdram_re
- attribute \src "ls180.v:770.6-770.26"
+ attribute \src "ls180.v:774.6-774.26"
wire \sdram_read_available
- attribute \src "ls180.v:300.6-300.19"
+ attribute \src "ls180.v:304.6-304.19"
wire \sdram_reset_n
- attribute \src "ls180.v:297.6-297.15"
+ attribute \src "ls180.v:301.6-301.15"
wire \sdram_sel
- attribute \src "ls180.v:388.5-388.26"
+ attribute \src "ls180.v:392.5-392.26"
wire \sdram_sequencer_count
- attribute \src "ls180.v:387.11-387.34"
+ attribute \src "ls180.v:391.11-391.34"
wire width 4 \sdram_sequencer_counter
- attribute \src "ls180.v:384.6-384.27"
+ attribute \src "ls180.v:388.6-388.27"
wire \sdram_sequencer_done0
- attribute \src "ls180.v:386.5-386.26"
+ attribute \src "ls180.v:390.5-390.26"
wire \sdram_sequencer_done1
- attribute \src "ls180.v:383.5-383.27"
+ attribute \src "ls180.v:387.5-387.27"
wire \sdram_sequencer_start0
- attribute \src "ls180.v:385.6-385.28"
+ attribute \src "ls180.v:389.6-389.28"
wire \sdram_sequencer_start1
- attribute \src "ls180.v:274.6-274.26"
+ attribute \src "ls180.v:278.6-278.26"
wire \sdram_slave_p0_act_n
- attribute \src "ls180.v:265.13-265.35"
+ attribute \src "ls180.v:269.13-269.35"
wire width 13 \sdram_slave_p0_address
- attribute \src "ls180.v:266.12-266.31"
+ attribute \src "ls180.v:270.12-270.31"
wire width 2 \sdram_slave_p0_bank
- attribute \src "ls180.v:267.6-267.26"
+ attribute \src "ls180.v:271.6-271.26"
wire \sdram_slave_p0_cas_n
- attribute \src "ls180.v:271.6-271.24"
+ attribute \src "ls180.v:275.6-275.24"
wire \sdram_slave_p0_cke
- attribute \src "ls180.v:268.6-268.25"
+ attribute \src "ls180.v:272.6-272.25"
wire \sdram_slave_p0_cs_n
- attribute \src "ls180.v:272.6-272.24"
+ attribute \src "ls180.v:276.6-276.24"
wire \sdram_slave_p0_odt
- attribute \src "ls180.v:269.6-269.26"
+ attribute \src "ls180.v:273.6-273.26"
wire \sdram_slave_p0_ras_n
- attribute \src "ls180.v:279.12-279.33"
+ attribute \src "ls180.v:283.12-283.33"
wire width 16 \sdram_slave_p0_rddata
- attribute \src "ls180.v:278.6-278.30"
+ attribute \src "ls180.v:282.6-282.30"
wire \sdram_slave_p0_rddata_en
- attribute \src "ls180.v:280.5-280.32"
+ attribute \src "ls180.v:284.5-284.32"
wire \sdram_slave_p0_rddata_valid
- attribute \src "ls180.v:273.6-273.28"
+ attribute \src "ls180.v:277.6-277.28"
wire \sdram_slave_p0_reset_n
- attribute \src "ls180.v:270.6-270.25"
+ attribute \src "ls180.v:274.6-274.25"
wire \sdram_slave_p0_we_n
- attribute \src "ls180.v:275.13-275.34"
+ attribute \src "ls180.v:279.13-279.34"
wire width 16 \sdram_slave_p0_wrdata
- attribute \src "ls180.v:276.6-276.30"
+ attribute \src "ls180.v:280.6-280.30"
wire \sdram_slave_p0_wrdata_en
- attribute \src "ls180.v:277.12-277.38"
+ attribute \src "ls180.v:281.12-281.38"
wire width 2 \sdram_slave_p0_wrdata_mask
- attribute \src "ls180.v:315.12-315.24"
+ attribute \src "ls180.v:319.12-319.24"
wire width 16 \sdram_status
- attribute \src "ls180.v:758.5-758.19"
+ attribute \src "ls180.v:762.5-762.19"
wire \sdram_steerer0
- attribute \src "ls180.v:759.5-759.19"
+ attribute \src "ls180.v:763.5-763.19"
wire \sdram_steerer1
- attribute \src "ls180.v:757.11-757.28"
+ attribute \src "ls180.v:761.11-761.28"
wire width 2 \sdram_steerer_sel
- attribute \src "ls180.v:301.11-301.24"
+ attribute \src "ls180.v:305.11-305.24"
wire width 4 \sdram_storage
- attribute \src "ls180.v:766.5-766.24"
+ attribute \src "ls180.v:770.5-770.24"
wire \sdram_tccdcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:765.32-765.51"
+ attribute \src "ls180.v:769.32-769.51"
wire \sdram_tccdcon_ready
- attribute \src "ls180.v:764.6-764.25"
+ attribute \src "ls180.v:768.6-768.25"
wire \sdram_tccdcon_valid
attribute \no_retiming "true"
- attribute \src "ls180.v:763.32-763.51"
+ attribute \src "ls180.v:767.32-767.51"
wire \sdram_tfawcon_ready
- attribute \src "ls180.v:762.6-762.25"
+ attribute \src "ls180.v:766.6-766.25"
wire \sdram_tfawcon_valid
- attribute \src "ls180.v:774.11-774.22"
+ attribute \src "ls180.v:778.11-778.22"
wire width 5 \sdram_time0
- attribute \src "ls180.v:777.11-777.22"
+ attribute \src "ls180.v:781.11-781.22"
wire width 4 \sdram_time1
- attribute \src "ls180.v:377.12-377.30"
+ attribute \src "ls180.v:381.12-381.30"
wire width 10 \sdram_timer_count0
- attribute \src "ls180.v:379.11-379.29"
+ attribute \src "ls180.v:383.11-383.29"
wire width 10 \sdram_timer_count1
- attribute \src "ls180.v:376.6-376.23"
+ attribute \src "ls180.v:380.6-380.23"
wire \sdram_timer_done0
- attribute \src "ls180.v:378.6-378.23"
+ attribute \src "ls180.v:382.6-382.23"
wire \sdram_timer_done1
- attribute \src "ls180.v:375.6-375.22"
+ attribute \src "ls180.v:379.6-379.22"
wire \sdram_timer_wait
attribute \no_retiming "true"
- attribute \src "ls180.v:761.32-761.51"
+ attribute \src "ls180.v:765.32-765.51"
wire \sdram_trrdcon_ready
- attribute \src "ls180.v:760.6-760.25"
+ attribute \src "ls180.v:764.6-764.25"
wire \sdram_trrdcon_valid
- attribute \src "ls180.v:769.11-769.30"
+ attribute \src "ls180.v:773.11-773.30"
wire width 3 \sdram_twtrcon_count
attribute \no_retiming "true"
- attribute \src "ls180.v:768.32-768.51"
+ attribute \src "ls180.v:772.32-772.51"
wire \sdram_twtrcon_ready
- attribute \src "ls180.v:767.6-767.25"
+ attribute \src "ls180.v:771.6-771.25"
wire \sdram_twtrcon_valid
- attribute \src "ls180.v:374.6-374.25"
+ attribute \src "ls180.v:378.6-378.25"
wire \sdram_wants_refresh
- attribute \src "ls180.v:316.6-316.14"
+ attribute \src "ls180.v:320.6-320.14"
wire \sdram_we
- attribute \src "ls180.v:19.14-19.24"
- wire output 15 \sdram_we_n
- attribute \src "ls180.v:314.5-314.20"
+ attribute \src "ls180.v:25.14-25.24"
+ wire output 21 \sdram_we_n
+ attribute \src "ls180.v:318.5-318.20"
wire \sdram_wrdata_re
- attribute \src "ls180.v:313.12-313.32"
+ attribute \src "ls180.v:317.12-317.32"
wire width 16 \sdram_wrdata_storage
- attribute \src "ls180.v:771.6-771.27"
+ attribute \src "ls180.v:775.6-775.27"
wire \sdram_write_available
- attribute \src "ls180.v:1390.6-1390.15"
+ attribute \src "ls180.v:1395.6-1395.15"
wire \sdrio_clk
- attribute \src "ls180.v:1391.6-1391.17"
+ attribute \src "ls180.v:1396.6-1396.17"
wire \sdrio_clk_1
- attribute \src "ls180.v:1400.6-1400.18"
+ attribute \src "ls180.v:1405.6-1405.18"
wire \sdrio_clk_10
- attribute \src "ls180.v:1492.6-1492.19"
+ attribute \src "ls180.v:1497.6-1497.19"
wire \sdrio_clk_100
- attribute \src "ls180.v:1493.6-1493.19"
+ attribute \src "ls180.v:1498.6-1498.19"
wire \sdrio_clk_101
- attribute \src "ls180.v:1494.6-1494.19"
+ attribute \src "ls180.v:1499.6-1499.19"
wire \sdrio_clk_102
- attribute \src "ls180.v:1495.6-1495.19"
+ attribute \src "ls180.v:1500.6-1500.19"
wire \sdrio_clk_103
- attribute \src "ls180.v:1401.6-1401.18"
+ attribute \src "ls180.v:1406.6-1406.18"
wire \sdrio_clk_11
- attribute \src "ls180.v:1402.6-1402.18"
+ attribute \src "ls180.v:1407.6-1407.18"
wire \sdrio_clk_12
- attribute \src "ls180.v:1403.6-1403.18"
+ attribute \src "ls180.v:1408.6-1408.18"
wire \sdrio_clk_13
- attribute \src "ls180.v:1404.6-1404.18"
+ attribute \src "ls180.v:1409.6-1409.18"
wire \sdrio_clk_14
- attribute \src "ls180.v:1405.6-1405.18"
+ attribute \src "ls180.v:1410.6-1410.18"
wire \sdrio_clk_15
- attribute \src "ls180.v:1406.6-1406.18"
+ attribute \src "ls180.v:1411.6-1411.18"
wire \sdrio_clk_16
- attribute \src "ls180.v:1407.6-1407.18"
+ attribute \src "ls180.v:1412.6-1412.18"
wire \sdrio_clk_17
- attribute \src "ls180.v:1408.6-1408.18"
+ attribute \src "ls180.v:1413.6-1413.18"
wire \sdrio_clk_18
- attribute \src "ls180.v:1409.6-1409.18"
+ attribute \src "ls180.v:1414.6-1414.18"
wire \sdrio_clk_19
- attribute \src "ls180.v:1392.6-1392.17"
+ attribute \src "ls180.v:1397.6-1397.17"
wire \sdrio_clk_2
- attribute \src "ls180.v:1410.6-1410.18"
+ attribute \src "ls180.v:1415.6-1415.18"
wire \sdrio_clk_20
- attribute \src "ls180.v:1411.6-1411.18"
+ attribute \src "ls180.v:1416.6-1416.18"
wire \sdrio_clk_21
- attribute \src "ls180.v:1412.6-1412.18"
+ attribute \src "ls180.v:1417.6-1417.18"
wire \sdrio_clk_22
- attribute \src "ls180.v:1413.6-1413.18"
+ attribute \src "ls180.v:1418.6-1418.18"
wire \sdrio_clk_23
- attribute \src "ls180.v:1414.6-1414.18"
+ attribute \src "ls180.v:1419.6-1419.18"
wire \sdrio_clk_24
- attribute \src "ls180.v:1415.6-1415.18"
+ attribute \src "ls180.v:1420.6-1420.18"
wire \sdrio_clk_25
- attribute \src "ls180.v:1416.6-1416.18"
+ attribute \src "ls180.v:1421.6-1421.18"
wire \sdrio_clk_26
- attribute \src "ls180.v:1417.6-1417.18"
+ attribute \src "ls180.v:1422.6-1422.18"
wire \sdrio_clk_27
- attribute \src "ls180.v:1418.6-1418.18"
+ attribute \src "ls180.v:1423.6-1423.18"
wire \sdrio_clk_28
- attribute \src "ls180.v:1419.6-1419.18"
+ attribute \src "ls180.v:1424.6-1424.18"
wire \sdrio_clk_29
- attribute \src "ls180.v:1393.6-1393.17"
+ attribute \src "ls180.v:1398.6-1398.17"
wire \sdrio_clk_3
- attribute \src "ls180.v:1420.6-1420.18"
+ attribute \src "ls180.v:1425.6-1425.18"
wire \sdrio_clk_30
- attribute \src "ls180.v:1421.6-1421.18"
+ attribute \src "ls180.v:1426.6-1426.18"
wire \sdrio_clk_31
- attribute \src "ls180.v:1422.6-1422.18"
+ attribute \src "ls180.v:1427.6-1427.18"
wire \sdrio_clk_32
- attribute \src "ls180.v:1423.6-1423.18"
+ attribute \src "ls180.v:1428.6-1428.18"
wire \sdrio_clk_33
- attribute \src "ls180.v:1424.6-1424.18"
+ attribute \src "ls180.v:1429.6-1429.18"
wire \sdrio_clk_34
- attribute \src "ls180.v:1425.6-1425.18"
+ attribute \src "ls180.v:1430.6-1430.18"
wire \sdrio_clk_35
- attribute \src "ls180.v:1426.6-1426.18"
+ attribute \src "ls180.v:1431.6-1431.18"
wire \sdrio_clk_36
- attribute \src "ls180.v:1427.6-1427.18"
+ attribute \src "ls180.v:1432.6-1432.18"
wire \sdrio_clk_37
- attribute \src "ls180.v:1428.6-1428.18"
+ attribute \src "ls180.v:1433.6-1433.18"
wire \sdrio_clk_38
- attribute \src "ls180.v:1429.6-1429.18"
+ attribute \src "ls180.v:1434.6-1434.18"
wire \sdrio_clk_39
- attribute \src "ls180.v:1394.6-1394.17"
+ attribute \src "ls180.v:1399.6-1399.17"
wire \sdrio_clk_4
- attribute \src "ls180.v:1430.6-1430.18"
+ attribute \src "ls180.v:1435.6-1435.18"
wire \sdrio_clk_40
- attribute \src "ls180.v:1431.6-1431.18"
+ attribute \src "ls180.v:1436.6-1436.18"
wire \sdrio_clk_41
- attribute \src "ls180.v:1432.6-1432.18"
+ attribute \src "ls180.v:1437.6-1437.18"
wire \sdrio_clk_42
- attribute \src "ls180.v:1433.6-1433.18"
+ attribute \src "ls180.v:1438.6-1438.18"
wire \sdrio_clk_43
- attribute \src "ls180.v:1434.6-1434.18"
+ attribute \src "ls180.v:1439.6-1439.18"
wire \sdrio_clk_44
- attribute \src "ls180.v:1435.6-1435.18"
+ attribute \src "ls180.v:1440.6-1440.18"
wire \sdrio_clk_45
- attribute \src "ls180.v:1436.6-1436.18"
+ attribute \src "ls180.v:1441.6-1441.18"
wire \sdrio_clk_46
- attribute \src "ls180.v:1437.6-1437.18"
+ attribute \src "ls180.v:1442.6-1442.18"
wire \sdrio_clk_47
- attribute \src "ls180.v:1438.6-1438.18"
+ attribute \src "ls180.v:1443.6-1443.18"
wire \sdrio_clk_48
- attribute \src "ls180.v:1439.6-1439.18"
+ attribute \src "ls180.v:1444.6-1444.18"
wire \sdrio_clk_49
- attribute \src "ls180.v:1395.6-1395.17"
+ attribute \src "ls180.v:1400.6-1400.17"
wire \sdrio_clk_5
- attribute \src "ls180.v:1440.6-1440.18"
+ attribute \src "ls180.v:1445.6-1445.18"
wire \sdrio_clk_50
- attribute \src "ls180.v:1441.6-1441.18"
+ attribute \src "ls180.v:1446.6-1446.18"
wire \sdrio_clk_51
- attribute \src "ls180.v:1442.6-1442.18"
+ attribute \src "ls180.v:1447.6-1447.18"
wire \sdrio_clk_52
- attribute \src "ls180.v:1443.6-1443.18"
+ attribute \src "ls180.v:1448.6-1448.18"
wire \sdrio_clk_53
- attribute \src "ls180.v:1444.6-1444.18"
+ attribute \src "ls180.v:1449.6-1449.18"
wire \sdrio_clk_54
- attribute \src "ls180.v:1445.6-1445.18"
+ attribute \src "ls180.v:1450.6-1450.18"
wire \sdrio_clk_55
- attribute \src "ls180.v:1448.6-1448.18"
+ attribute \src "ls180.v:1453.6-1453.18"
wire \sdrio_clk_56
- attribute \src "ls180.v:1449.6-1449.18"
+ attribute \src "ls180.v:1454.6-1454.18"
wire \sdrio_clk_57
- attribute \src "ls180.v:1450.6-1450.18"
+ attribute \src "ls180.v:1455.6-1455.18"
wire \sdrio_clk_58
- attribute \src "ls180.v:1451.6-1451.18"
+ attribute \src "ls180.v:1456.6-1456.18"
wire \sdrio_clk_59
- attribute \src "ls180.v:1396.6-1396.17"
+ attribute \src "ls180.v:1401.6-1401.17"
wire \sdrio_clk_6
- attribute \src "ls180.v:1452.6-1452.18"
+ attribute \src "ls180.v:1457.6-1457.18"
wire \sdrio_clk_60
- attribute \src "ls180.v:1453.6-1453.18"
+ attribute \src "ls180.v:1458.6-1458.18"
wire \sdrio_clk_61
- attribute \src "ls180.v:1454.6-1454.18"
+ attribute \src "ls180.v:1459.6-1459.18"
wire \sdrio_clk_62
- attribute \src "ls180.v:1455.6-1455.18"
+ attribute \src "ls180.v:1460.6-1460.18"
wire \sdrio_clk_63
- attribute \src "ls180.v:1456.6-1456.18"
+ attribute \src "ls180.v:1461.6-1461.18"
wire \sdrio_clk_64
- attribute \src "ls180.v:1457.6-1457.18"
+ attribute \src "ls180.v:1462.6-1462.18"
wire \sdrio_clk_65
- attribute \src "ls180.v:1458.6-1458.18"
+ attribute \src "ls180.v:1463.6-1463.18"
wire \sdrio_clk_66
- attribute \src "ls180.v:1459.6-1459.18"
+ attribute \src "ls180.v:1464.6-1464.18"
wire \sdrio_clk_67
- attribute \src "ls180.v:1460.6-1460.18"
+ attribute \src "ls180.v:1465.6-1465.18"
wire \sdrio_clk_68
- attribute \src "ls180.v:1461.6-1461.18"
+ attribute \src "ls180.v:1466.6-1466.18"
wire \sdrio_clk_69
- attribute \src "ls180.v:1397.6-1397.17"
+ attribute \src "ls180.v:1402.6-1402.17"
wire \sdrio_clk_7
- attribute \src "ls180.v:1462.6-1462.18"
+ attribute \src "ls180.v:1467.6-1467.18"
wire \sdrio_clk_70
- attribute \src "ls180.v:1463.6-1463.18"
+ attribute \src "ls180.v:1468.6-1468.18"
wire \sdrio_clk_71
- attribute \src "ls180.v:1464.6-1464.18"
+ attribute \src "ls180.v:1469.6-1469.18"
wire \sdrio_clk_72
- attribute \src "ls180.v:1465.6-1465.18"
+ attribute \src "ls180.v:1470.6-1470.18"
wire \sdrio_clk_73
- attribute \src "ls180.v:1466.6-1466.18"
+ attribute \src "ls180.v:1471.6-1471.18"
wire \sdrio_clk_74
- attribute \src "ls180.v:1467.6-1467.18"
+ attribute \src "ls180.v:1472.6-1472.18"
wire \sdrio_clk_75
- attribute \src "ls180.v:1468.6-1468.18"
+ attribute \src "ls180.v:1473.6-1473.18"
wire \sdrio_clk_76
- attribute \src "ls180.v:1469.6-1469.18"
+ attribute \src "ls180.v:1474.6-1474.18"
wire \sdrio_clk_77
- attribute \src "ls180.v:1470.6-1470.18"
+ attribute \src "ls180.v:1475.6-1475.18"
wire \sdrio_clk_78
- attribute \src "ls180.v:1471.6-1471.18"
+ attribute \src "ls180.v:1476.6-1476.18"
wire \sdrio_clk_79
- attribute \src "ls180.v:1398.6-1398.17"
+ attribute \src "ls180.v:1403.6-1403.17"
wire \sdrio_clk_8
- attribute \src "ls180.v:1472.6-1472.18"
+ attribute \src "ls180.v:1477.6-1477.18"
wire \sdrio_clk_80
- attribute \src "ls180.v:1473.6-1473.18"
+ attribute \src "ls180.v:1478.6-1478.18"
wire \sdrio_clk_81
- attribute \src "ls180.v:1474.6-1474.18"
+ attribute \src "ls180.v:1479.6-1479.18"
wire \sdrio_clk_82
- attribute \src "ls180.v:1475.6-1475.18"
+ attribute \src "ls180.v:1480.6-1480.18"
wire \sdrio_clk_83
- attribute \src "ls180.v:1476.6-1476.18"
+ attribute \src "ls180.v:1481.6-1481.18"
wire \sdrio_clk_84
- attribute \src "ls180.v:1477.6-1477.18"
+ attribute \src "ls180.v:1482.6-1482.18"
wire \sdrio_clk_85
- attribute \src "ls180.v:1478.6-1478.18"
+ attribute \src "ls180.v:1483.6-1483.18"
wire \sdrio_clk_86
- attribute \src "ls180.v:1479.6-1479.18"
+ attribute \src "ls180.v:1484.6-1484.18"
wire \sdrio_clk_87
- attribute \src "ls180.v:1480.6-1480.18"
+ attribute \src "ls180.v:1485.6-1485.18"
wire \sdrio_clk_88
- attribute \src "ls180.v:1481.6-1481.18"
+ attribute \src "ls180.v:1486.6-1486.18"
wire \sdrio_clk_89
- attribute \src "ls180.v:1399.6-1399.17"
+ attribute \src "ls180.v:1404.6-1404.17"
wire \sdrio_clk_9
- attribute \src "ls180.v:1482.6-1482.18"
+ attribute \src "ls180.v:1487.6-1487.18"
wire \sdrio_clk_90
- attribute \src "ls180.v:1483.6-1483.18"
+ attribute \src "ls180.v:1488.6-1488.18"
wire \sdrio_clk_91
- attribute \src "ls180.v:1484.6-1484.18"
+ attribute \src "ls180.v:1489.6-1489.18"
wire \sdrio_clk_92
- attribute \src "ls180.v:1485.6-1485.18"
+ attribute \src "ls180.v:1490.6-1490.18"
wire \sdrio_clk_93
- attribute \src "ls180.v:1486.6-1486.18"
+ attribute \src "ls180.v:1491.6-1491.18"
wire \sdrio_clk_94
- attribute \src "ls180.v:1487.6-1487.18"
+ attribute \src "ls180.v:1492.6-1492.18"
wire \sdrio_clk_95
- attribute \src "ls180.v:1488.6-1488.18"
+ attribute \src "ls180.v:1493.6-1493.18"
wire \sdrio_clk_96
- attribute \src "ls180.v:1489.6-1489.18"
+ attribute \src "ls180.v:1494.6-1494.18"
wire \sdrio_clk_97
- attribute \src "ls180.v:1490.6-1490.18"
+ attribute \src "ls180.v:1495.6-1495.18"
wire \sdrio_clk_98
- attribute \src "ls180.v:1491.6-1491.18"
+ attribute \src "ls180.v:1496.6-1496.18"
wire \sdrio_clk_99
- attribute \src "ls180.v:806.5-806.42"
+ attribute \src "ls180.v:810.5-810.42"
wire \socbushandler_converted_interface_ack
- attribute \src "ls180.v:800.13-800.50"
+ attribute \src "ls180.v:804.13-804.50"
wire width 30 \socbushandler_converted_interface_adr
- attribute \src "ls180.v:809.12-809.49"
+ attribute \src "ls180.v:813.12-813.49"
wire width 2 \socbushandler_converted_interface_bte
- attribute \src "ls180.v:808.12-808.49"
+ attribute \src "ls180.v:812.12-812.49"
wire width 3 \socbushandler_converted_interface_cti
- attribute \src "ls180.v:804.6-804.43"
+ attribute \src "ls180.v:808.6-808.43"
wire \socbushandler_converted_interface_cyc
- attribute \src "ls180.v:802.13-802.52"
+ attribute \src "ls180.v:806.13-806.52"
wire width 64 \socbushandler_converted_interface_dat_r
- attribute \src "ls180.v:801.13-801.52"
+ attribute \src "ls180.v:805.13-805.52"
wire width 64 \socbushandler_converted_interface_dat_w
- attribute \src "ls180.v:810.5-810.42"
+ attribute \src "ls180.v:814.5-814.42"
wire \socbushandler_converted_interface_err
- attribute \src "ls180.v:803.12-803.49"
+ attribute \src "ls180.v:807.12-807.49"
wire width 8 \socbushandler_converted_interface_sel
- attribute \src "ls180.v:805.6-805.43"
+ attribute \src "ls180.v:809.6-809.43"
wire \socbushandler_converted_interface_stb
- attribute \src "ls180.v:807.6-807.42"
+ attribute \src "ls180.v:811.6-811.42"
wire \socbushandler_converted_interface_we
- attribute \src "ls180.v:812.5-812.26"
+ attribute \src "ls180.v:816.5-816.26"
wire \socbushandler_counter
- attribute \src "ls180.v:1012.5-1012.61"
+ attribute \src "ls180.v:1017.5-1017.61"
wire \socbushandler_counter_subfragments_converter2_next_value
- attribute \src "ls180.v:1013.5-1013.64"
+ attribute \src "ls180.v:1018.5-1018.64"
wire \socbushandler_counter_subfragments_converter2_next_value_ce
- attribute \src "ls180.v:814.12-814.31"
+ attribute \src "ls180.v:818.12-818.31"
wire width 64 \socbushandler_dat_r
- attribute \src "ls180.v:813.6-813.25"
+ attribute \src "ls180.v:817.6-817.25"
wire \socbushandler_reset
- attribute \src "ls180.v:811.5-811.23"
+ attribute \src "ls180.v:815.5-815.23"
wire \socbushandler_skip
- attribute \src "ls180.v:8.14-8.27"
- wire output 4 \spimaster_clk
- attribute \src "ls180.v:10.14-10.28"
- wire output 6 \spimaster_cs_n
- attribute \src "ls180.v:11.13-11.27"
- wire input 7 \spimaster_miso
- attribute \src "ls180.v:9.14-9.28"
- wire output 5 \spimaster_mosi
- attribute \src "ls180.v:1017.11-1017.47"
+ attribute \src "ls180.v:17.14-17.27"
+ wire output 13 \spimaster_clk
+ attribute \src "ls180.v:19.14-19.28"
+ wire output 15 \spimaster_cs_n
+ attribute \src "ls180.v:20.13-20.27"
+ wire input 16 \spimaster_miso
+ attribute \src "ls180.v:18.14-18.28"
+ wire output 14 \spimaster_mosi
+ attribute \src "ls180.v:1022.11-1022.47"
wire width 3 \subfragments_bankmachine0_next_state
- attribute \src "ls180.v:1016.11-1016.42"
+ attribute \src "ls180.v:1021.11-1021.42"
wire width 3 \subfragments_bankmachine0_state
- attribute \src "ls180.v:1019.11-1019.47"
+ attribute \src "ls180.v:1024.11-1024.47"
wire width 3 \subfragments_bankmachine1_next_state
- attribute \src "ls180.v:1018.11-1018.42"
+ attribute \src "ls180.v:1023.11-1023.42"
wire width 3 \subfragments_bankmachine1_state
- attribute \src "ls180.v:1021.11-1021.47"
+ attribute \src "ls180.v:1026.11-1026.47"
wire width 3 \subfragments_bankmachine2_next_state
- attribute \src "ls180.v:1020.11-1020.42"
+ attribute \src "ls180.v:1025.11-1025.42"
wire width 3 \subfragments_bankmachine2_state
- attribute \src "ls180.v:1023.11-1023.47"
+ attribute \src "ls180.v:1028.11-1028.47"
wire width 3 \subfragments_bankmachine3_next_state
- attribute \src "ls180.v:1022.11-1022.42"
+ attribute \src "ls180.v:1027.11-1027.42"
wire width 3 \subfragments_bankmachine3_state
- attribute \src "ls180.v:1003.5-1003.39"
+ attribute \src "ls180.v:1008.5-1008.39"
wire \subfragments_converter0_next_state
- attribute \src "ls180.v:1002.5-1002.34"
+ attribute \src "ls180.v:1007.5-1007.34"
wire \subfragments_converter0_state
- attribute \src "ls180.v:1007.5-1007.39"
+ attribute \src "ls180.v:1012.5-1012.39"
wire \subfragments_converter1_next_state
- attribute \src "ls180.v:1006.5-1006.34"
+ attribute \src "ls180.v:1011.5-1011.34"
wire \subfragments_converter1_state
- attribute \src "ls180.v:1011.5-1011.39"
+ attribute \src "ls180.v:1016.5-1016.39"
wire \subfragments_converter2_next_state
- attribute \src "ls180.v:1010.5-1010.34"
+ attribute \src "ls180.v:1015.5-1015.34"
wire \subfragments_converter2_state
- attribute \src "ls180.v:1038.5-1038.25"
+ attribute \src "ls180.v:1043.5-1043.25"
wire \subfragments_locked0
- attribute \src "ls180.v:1039.5-1039.25"
+ attribute \src "ls180.v:1044.5-1044.25"
wire \subfragments_locked1
- attribute \src "ls180.v:1040.5-1040.25"
+ attribute \src "ls180.v:1045.5-1045.25"
wire \subfragments_locked2
- attribute \src "ls180.v:1041.5-1041.25"
+ attribute \src "ls180.v:1046.5-1046.25"
wire \subfragments_locked3
- attribute \src "ls180.v:1025.11-1025.46"
+ attribute \src "ls180.v:1030.11-1030.46"
wire width 3 \subfragments_multiplexer_next_state
- attribute \src "ls180.v:1024.11-1024.41"
+ attribute \src "ls180.v:1029.11-1029.41"
wire width 3 \subfragments_multiplexer_state
- attribute \src "ls180.v:1043.5-1043.41"
+ attribute \src "ls180.v:1048.5-1048.41"
wire \subfragments_new_master_rdata_valid0
- attribute \src "ls180.v:1044.5-1044.41"
+ attribute \src "ls180.v:1049.5-1049.41"
wire \subfragments_new_master_rdata_valid1
- attribute \src "ls180.v:1045.5-1045.41"
+ attribute \src "ls180.v:1050.5-1050.41"
wire \subfragments_new_master_rdata_valid2
- attribute \src "ls180.v:1046.5-1046.41"
+ attribute \src "ls180.v:1051.5-1051.41"
wire \subfragments_new_master_rdata_valid3
- attribute \src "ls180.v:1042.5-1042.40"
+ attribute \src "ls180.v:1047.5-1047.40"
wire \subfragments_new_master_wdata_ready
- attribute \src "ls180.v:1048.5-1048.28"
+ attribute \src "ls180.v:1053.5-1053.28"
wire \subfragments_next_state
- attribute \src "ls180.v:1015.11-1015.44"
+ attribute \src "ls180.v:1020.11-1020.44"
wire width 2 \subfragments_refresher_next_state
- attribute \src "ls180.v:1014.11-1014.39"
+ attribute \src "ls180.v:1019.11-1019.39"
wire width 2 \subfragments_refresher_state
- attribute \src "ls180.v:1028.6-1028.33"
+ attribute \src "ls180.v:1033.6-1033.33"
wire \subfragments_roundrobin0_ce
- attribute \src "ls180.v:1027.6-1027.36"
+ attribute \src "ls180.v:1032.6-1032.36"
wire \subfragments_roundrobin0_grant
- attribute \src "ls180.v:1026.6-1026.38"
+ attribute \src "ls180.v:1031.6-1031.38"
wire \subfragments_roundrobin0_request
- attribute \src "ls180.v:1031.6-1031.33"
+ attribute \src "ls180.v:1036.6-1036.33"
wire \subfragments_roundrobin1_ce
- attribute \src "ls180.v:1030.6-1030.36"
+ attribute \src "ls180.v:1035.6-1035.36"
wire \subfragments_roundrobin1_grant
- attribute \src "ls180.v:1029.6-1029.38"
+ attribute \src "ls180.v:1034.6-1034.38"
wire \subfragments_roundrobin1_request
- attribute \src "ls180.v:1034.6-1034.33"
+ attribute \src "ls180.v:1039.6-1039.33"
wire \subfragments_roundrobin2_ce
- attribute \src "ls180.v:1033.6-1033.36"
+ attribute \src "ls180.v:1038.6-1038.36"
wire \subfragments_roundrobin2_grant
- attribute \src "ls180.v:1032.6-1032.38"
+ attribute \src "ls180.v:1037.6-1037.38"
wire \subfragments_roundrobin2_request
- attribute \src "ls180.v:1037.6-1037.33"
+ attribute \src "ls180.v:1042.6-1042.33"
wire \subfragments_roundrobin3_ce
- attribute \src "ls180.v:1036.6-1036.36"
+ attribute \src "ls180.v:1041.6-1041.36"
wire \subfragments_roundrobin3_grant
- attribute \src "ls180.v:1035.6-1035.38"
+ attribute \src "ls180.v:1040.6-1040.38"
wire \subfragments_roundrobin3_request
- attribute \src "ls180.v:1047.5-1047.23"
+ attribute \src "ls180.v:1052.5-1052.23"
wire \subfragments_state
- attribute \src "ls180.v:31.13-31.20"
- wire input 27 \sys_clk
- attribute \src "ls180.v:228.6-228.15"
+ attribute \src "ls180.v:33.13-33.20"
+ wire input 29 \sys_clk
+ attribute \src "ls180.v:232.6-232.15"
wire \sys_clk_1
- attribute \src "ls180.v:33.19-33.31"
- wire width 2 input 29 \sys_clksel_i
- attribute \src "ls180.v:34.14-34.26"
- wire output 30 \sys_pll_18_o
- attribute \src "ls180.v:35.14-35.27"
- wire output 31 \sys_pll_lck_o
- attribute \src "ls180.v:32.13-32.20"
- wire input 28 \sys_rst
- attribute \src "ls180.v:229.6-229.15"
+ attribute \src "ls180.v:35.19-35.31"
+ wire width 2 input 31 \sys_clksel_i
+ attribute \src "ls180.v:36.14-36.26"
+ wire output 32 \sys_pll_18_o
+ attribute \src "ls180.v:37.14-37.27"
+ wire output 33 \sys_pll_lck_o
+ attribute \src "ls180.v:34.13-34.20"
+ wire input 30 \sys_rst
+ attribute \src "ls180.v:233.6-233.15"
wire \sys_rst_1
- attribute \src "ls180.v:1351.5-1351.19"
+ attribute \src "ls180.v:1356.5-1356.19"
wire \t_array_muxed0
- attribute \src "ls180.v:1352.5-1352.19"
+ attribute \src "ls180.v:1357.5-1357.19"
wire \t_array_muxed1
- attribute \src "ls180.v:1353.5-1353.19"
+ attribute \src "ls180.v:1358.5-1358.19"
wire \t_array_muxed2
- attribute \src "ls180.v:1360.5-1360.19"
+ attribute \src "ls180.v:1365.5-1365.19"
wire \t_array_muxed3
- attribute \src "ls180.v:1361.5-1361.19"
+ attribute \src "ls180.v:1366.5-1366.19"
wire \t_array_muxed4
- attribute \src "ls180.v:1362.5-1362.19"
+ attribute \src "ls180.v:1367.5-1367.19"
wire \t_array_muxed5
- attribute \src "ls180.v:868.5-868.13"
+ attribute \src "ls180.v:872.5-872.13"
wire \tx_clear
- attribute \src "ls180.v:920.11-920.26"
+ attribute \src "ls180.v:924.11-924.26"
wire width 4 \tx_fifo_consume
- attribute \src "ls180.v:925.6-925.21"
+ attribute \src "ls180.v:929.6-929.21"
wire \tx_fifo_do_read
- attribute \src "ls180.v:931.6-931.27"
+ attribute \src "ls180.v:935.6-935.27"
wire \tx_fifo_fifo_in_first
- attribute \src "ls180.v:932.6-932.26"
+ attribute \src "ls180.v:936.6-936.26"
wire \tx_fifo_fifo_in_last
- attribute \src "ls180.v:930.12-930.40"
+ attribute \src "ls180.v:934.12-934.40"
wire width 8 \tx_fifo_fifo_in_payload_data
- attribute \src "ls180.v:934.6-934.28"
+ attribute \src "ls180.v:938.6-938.28"
wire \tx_fifo_fifo_out_first
- attribute \src "ls180.v:935.6-935.27"
+ attribute \src "ls180.v:939.6-939.27"
wire \tx_fifo_fifo_out_last
- attribute \src "ls180.v:933.12-933.41"
+ attribute \src "ls180.v:937.12-937.41"
wire width 8 \tx_fifo_fifo_out_payload_data
- attribute \src "ls180.v:917.11-917.25"
+ attribute \src "ls180.v:921.11-921.25"
wire width 5 \tx_fifo_level0
- attribute \src "ls180.v:929.12-929.26"
+ attribute \src "ls180.v:933.12-933.26"
wire width 5 \tx_fifo_level1
- attribute \src "ls180.v:919.11-919.26"
+ attribute \src "ls180.v:923.11-923.26"
wire width 4 \tx_fifo_produce
- attribute \src "ls180.v:926.12-926.30"
+ attribute \src "ls180.v:930.12-930.30"
wire width 4 \tx_fifo_rdport_adr
- attribute \src "ls180.v:927.12-927.32"
+ attribute \src "ls180.v:931.12-931.32"
wire width 10 \tx_fifo_rdport_dat_r
- attribute \src "ls180.v:928.6-928.23"
+ attribute \src "ls180.v:932.6-932.23"
wire \tx_fifo_rdport_re
- attribute \src "ls180.v:909.6-909.16"
+ attribute \src "ls180.v:913.6-913.16"
wire \tx_fifo_re
- attribute \src "ls180.v:910.5-910.21"
+ attribute \src "ls180.v:914.5-914.21"
wire \tx_fifo_readable
- attribute \src "ls180.v:918.5-918.20"
+ attribute \src "ls180.v:922.5-922.20"
wire \tx_fifo_replace
- attribute \src "ls180.v:901.5-901.23"
+ attribute \src "ls180.v:905.5-905.23"
wire \tx_fifo_sink_first
- attribute \src "ls180.v:902.5-902.22"
+ attribute \src "ls180.v:906.5-906.22"
wire \tx_fifo_sink_last
- attribute \src "ls180.v:903.12-903.37"
+ attribute \src "ls180.v:907.12-907.37"
wire width 8 \tx_fifo_sink_payload_data
- attribute \src "ls180.v:900.6-900.24"
+ attribute \src "ls180.v:904.6-904.24"
wire \tx_fifo_sink_ready
- attribute \src "ls180.v:899.6-899.24"
+ attribute \src "ls180.v:903.6-903.24"
wire \tx_fifo_sink_valid
- attribute \src "ls180.v:906.6-906.26"
+ attribute \src "ls180.v:910.6-910.26"
wire \tx_fifo_source_first
- attribute \src "ls180.v:907.6-907.25"
+ attribute \src "ls180.v:911.6-911.25"
wire \tx_fifo_source_last
- attribute \src "ls180.v:908.12-908.39"
+ attribute \src "ls180.v:912.12-912.39"
wire width 8 \tx_fifo_source_payload_data
- attribute \src "ls180.v:905.6-905.26"
+ attribute \src "ls180.v:909.6-909.26"
wire \tx_fifo_source_ready
- attribute \src "ls180.v:904.6-904.26"
+ attribute \src "ls180.v:908.6-908.26"
wire \tx_fifo_source_valid
- attribute \src "ls180.v:915.12-915.32"
+ attribute \src "ls180.v:919.12-919.32"
wire width 10 \tx_fifo_syncfifo_din
- attribute \src "ls180.v:916.12-916.33"
+ attribute \src "ls180.v:920.12-920.33"
wire width 10 \tx_fifo_syncfifo_dout
- attribute \src "ls180.v:913.6-913.25"
+ attribute \src "ls180.v:917.6-917.25"
wire \tx_fifo_syncfifo_re
- attribute \src "ls180.v:914.6-914.31"
+ attribute \src "ls180.v:918.6-918.31"
wire \tx_fifo_syncfifo_readable
- attribute \src "ls180.v:911.6-911.25"
+ attribute \src "ls180.v:915.6-915.25"
wire \tx_fifo_syncfifo_we
- attribute \src "ls180.v:912.6-912.31"
+ attribute \src "ls180.v:916.6-916.31"
wire \tx_fifo_syncfifo_writable
- attribute \src "ls180.v:921.11-921.29"
+ attribute \src "ls180.v:925.11-925.29"
wire width 4 \tx_fifo_wrport_adr
- attribute \src "ls180.v:922.12-922.32"
+ attribute \src "ls180.v:926.12-926.32"
wire width 10 \tx_fifo_wrport_dat_r
- attribute \src "ls180.v:924.12-924.32"
+ attribute \src "ls180.v:928.12-928.32"
wire width 10 \tx_fifo_wrport_dat_w
- attribute \src "ls180.v:923.6-923.23"
+ attribute \src "ls180.v:927.6-927.23"
wire \tx_fifo_wrport_we
- attribute \src "ls180.v:869.5-869.19"
+ attribute \src "ls180.v:873.5-873.19"
wire \tx_old_trigger
- attribute \src "ls180.v:866.5-866.15"
+ attribute \src "ls180.v:870.5-870.15"
wire \tx_pending
- attribute \src "ls180.v:865.6-865.15"
+ attribute \src "ls180.v:869.6-869.15"
wire \tx_status
- attribute \src "ls180.v:867.6-867.16"
+ attribute \src "ls180.v:871.6-871.16"
wire \tx_trigger
- attribute \src "ls180.v:885.6-885.20"
+ attribute \src "ls180.v:889.6-889.20"
wire \txempty_status
- attribute \src "ls180.v:886.6-886.16"
+ attribute \src "ls180.v:890.6-890.16"
wire \txempty_we
- attribute \src "ls180.v:860.6-860.19"
+ attribute \src "ls180.v:864.6-864.19"
wire \txfull_status
- attribute \src "ls180.v:861.6-861.15"
+ attribute \src "ls180.v:865.6-865.15"
wire \txfull_we
- attribute \src "ls180.v:850.12-850.41"
+ attribute \src "ls180.v:854.12-854.41"
wire width 32 \uart_phy_phase_accumulator_rx
- attribute \src "ls180.v:840.12-840.41"
+ attribute \src "ls180.v:844.12-844.41"
wire width 32 \uart_phy_phase_accumulator_tx
- attribute \src "ls180.v:833.5-833.16"
+ attribute \src "ls180.v:837.5-837.16"
wire \uart_phy_re
- attribute \src "ls180.v:851.6-851.17"
+ attribute \src "ls180.v:855.6-855.17"
wire \uart_phy_rx
- attribute \src "ls180.v:854.11-854.31"
+ attribute \src "ls180.v:858.11-858.31"
wire width 4 \uart_phy_rx_bitcount
- attribute \src "ls180.v:855.5-855.21"
+ attribute \src "ls180.v:859.5-859.21"
wire \uart_phy_rx_busy
- attribute \src "ls180.v:852.5-852.18"
+ attribute \src "ls180.v:856.5-856.18"
wire \uart_phy_rx_r
- attribute \src "ls180.v:853.11-853.26"
+ attribute \src "ls180.v:857.11-857.26"
wire width 8 \uart_phy_rx_reg
- attribute \src "ls180.v:836.6-836.25"
+ attribute \src "ls180.v:840.6-840.25"
wire \uart_phy_sink_first
- attribute \src "ls180.v:837.6-837.24"
+ attribute \src "ls180.v:841.6-841.24"
wire \uart_phy_sink_last
- attribute \src "ls180.v:838.12-838.38"
+ attribute \src "ls180.v:842.12-842.38"
wire width 8 \uart_phy_sink_payload_data
- attribute \src "ls180.v:835.5-835.24"
+ attribute \src "ls180.v:839.5-839.24"
wire \uart_phy_sink_ready
- attribute \src "ls180.v:834.6-834.25"
+ attribute \src "ls180.v:838.6-838.25"
wire \uart_phy_sink_valid
- attribute \src "ls180.v:846.5-846.26"
+ attribute \src "ls180.v:850.5-850.26"
wire \uart_phy_source_first
- attribute \src "ls180.v:847.5-847.25"
+ attribute \src "ls180.v:851.5-851.25"
wire \uart_phy_source_last
- attribute \src "ls180.v:848.11-848.39"
+ attribute \src "ls180.v:852.11-852.39"
wire width 8 \uart_phy_source_payload_data
- attribute \src "ls180.v:845.6-845.27"
+ attribute \src "ls180.v:849.6-849.27"
wire \uart_phy_source_ready
- attribute \src "ls180.v:844.5-844.26"
+ attribute \src "ls180.v:848.5-848.26"
wire \uart_phy_source_valid
- attribute \src "ls180.v:832.12-832.28"
+ attribute \src "ls180.v:836.12-836.28"
wire width 32 \uart_phy_storage
- attribute \src "ls180.v:842.11-842.31"
+ attribute \src "ls180.v:846.11-846.31"
wire width 4 \uart_phy_tx_bitcount
- attribute \src "ls180.v:843.5-843.21"
+ attribute \src "ls180.v:847.5-847.21"
wire \uart_phy_tx_busy
- attribute \src "ls180.v:841.11-841.26"
+ attribute \src "ls180.v:845.11-845.26"
wire width 8 \uart_phy_tx_reg
- attribute \src "ls180.v:849.5-849.27"
+ attribute \src "ls180.v:853.5-853.27"
wire \uart_phy_uart_clk_rxen
- attribute \src "ls180.v:839.5-839.27"
+ attribute \src "ls180.v:843.5-843.27"
wire \uart_phy_uart_clk_txen
- attribute \src "ls180.v:13.13-13.20"
- wire input 9 \uart_rx
- attribute \src "ls180.v:891.6-891.21"
+ attribute \src "ls180.v:10.13-10.20"
+ wire input 6 \uart_rx
+ attribute \src "ls180.v:895.6-895.21"
wire \uart_sink_first
- attribute \src "ls180.v:892.6-892.20"
+ attribute \src "ls180.v:896.6-896.20"
wire \uart_sink_last
- attribute \src "ls180.v:893.12-893.34"
+ attribute \src "ls180.v:897.12-897.34"
wire width 8 \uart_sink_payload_data
- attribute \src "ls180.v:890.6-890.21"
+ attribute \src "ls180.v:894.6-894.21"
wire \uart_sink_ready
- attribute \src "ls180.v:889.6-889.21"
+ attribute \src "ls180.v:893.6-893.21"
wire \uart_sink_valid
- attribute \src "ls180.v:896.6-896.23"
+ attribute \src "ls180.v:900.6-900.23"
wire \uart_source_first
- attribute \src "ls180.v:897.6-897.22"
+ attribute \src "ls180.v:901.6-901.22"
wire \uart_source_last
- attribute \src "ls180.v:898.12-898.36"
+ attribute \src "ls180.v:902.12-902.36"
wire width 8 \uart_source_payload_data
- attribute \src "ls180.v:895.6-895.23"
+ attribute \src "ls180.v:899.6-899.23"
wire \uart_source_ready
- attribute \src "ls180.v:894.6-894.23"
+ attribute \src "ls180.v:898.6-898.23"
wire \uart_source_valid
- attribute \src "ls180.v:12.13-12.20"
- wire input 8 \uart_tx
- attribute \src "ls180.v:798.5-798.17"
+ attribute \src "ls180.v:9.13-9.20"
+ wire input 5 \uart_tx
+ attribute \src "ls180.v:802.5-802.17"
wire \wb_sdram_ack
- attribute \src "ls180.v:792.12-792.24"
+ attribute \src "ls180.v:796.12-796.24"
wire width 30 \wb_sdram_adr
- attribute \src "ls180.v:796.5-796.17"
+ attribute \src "ls180.v:800.5-800.17"
wire \wb_sdram_cyc
- attribute \src "ls180.v:794.13-794.27"
+ attribute \src "ls180.v:798.13-798.27"
wire width 32 \wb_sdram_dat_r
- attribute \src "ls180.v:793.12-793.26"
+ attribute \src "ls180.v:797.12-797.26"
wire width 32 \wb_sdram_dat_w
- attribute \src "ls180.v:795.11-795.23"
+ attribute \src "ls180.v:799.11-799.23"
wire width 4 \wb_sdram_sel
- attribute \src "ls180.v:797.5-797.17"
+ attribute \src "ls180.v:801.5-801.17"
wire \wb_sdram_stb
- attribute \src "ls180.v:799.5-799.16"
+ attribute \src "ls180.v:803.5-803.16"
wire \wb_sdram_we
- attribute \src "ls180.v:828.5-828.19"
+ attribute \src "ls180.v:832.5-832.19"
wire \wdata_consumed
- attribute \src "ls180.v:5489.12-5489.15"
+ attribute \src "ls180.v:5508.12-5508.15"
memory width 64 size 64 \mem
- attribute \src "ls180.v:5517.12-5517.17"
+ attribute \src "ls180.v:5536.12-5536.17"
memory width 64 size 16 \mem_1
- attribute \src "ls180.v:5545.12-5545.19"
+ attribute \src "ls180.v:5564.12-5564.19"
memory width 25 size 8 \storage
- attribute \src "ls180.v:5559.12-5559.21"
+ attribute \src "ls180.v:5578.12-5578.21"
memory width 25 size 8 \storage_1
- attribute \src "ls180.v:5573.12-5573.21"
+ attribute \src "ls180.v:5592.12-5592.21"
memory width 25 size 8 \storage_2
- attribute \src "ls180.v:5587.12-5587.21"
+ attribute \src "ls180.v:5606.12-5606.21"
memory width 25 size 8 \storage_3
- attribute \src "ls180.v:5601.11-5601.20"
+ attribute \src "ls180.v:5620.11-5620.20"
memory width 10 size 16 \storage_4
- attribute \src "ls180.v:5618.11-5618.20"
+ attribute \src "ls180.v:5637.11-5637.20"
memory width 10 size 16 \storage_5
- attribute \src "ls180.v:1555.64-1555.89"
- cell $add $add$ls180.v:1555$32
+ attribute \src "ls180.v:1568.64-1568.89"
+ cell $add $add$ls180.v:1568$33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \converter0_counter
connect \B 1'1
- connect \Y $add$ls180.v:1555$32_Y
+ connect \Y $add$ls180.v:1568$33_Y
end
- attribute \src "ls180.v:1615.64-1615.89"
- cell $add $add$ls180.v:1615$43
+ attribute \src "ls180.v:1628.64-1628.89"
+ cell $add $add$ls180.v:1628$44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \converter1_counter
connect \B 1'1
- connect \Y $add$ls180.v:1615$43_Y
+ connect \Y $add$ls180.v:1628$44_Y
end
- attribute \src "ls180.v:1675.67-1675.95"
- cell $add $add$ls180.v:1675$54
+ attribute \src "ls180.v:1688.67-1688.95"
+ cell $add $add$ls180.v:1688$55
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \socbushandler_counter
connect \B 1'1
- connect \Y $add$ls180.v:1675$54_Y
+ connect \Y $add$ls180.v:1688$55_Y
end
- attribute \src "ls180.v:2826.52-2826.76"
- cell $add $add$ls180.v:2826$584
+ attribute \src "ls180.v:2839.52-2839.76"
+ cell $add $add$ls180.v:2839$585
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \converter_counter
connect \B 1'1
- connect \Y $add$ls180.v:2826$584_Y
+ connect \Y $add$ls180.v:2839$585_Y
end
- attribute \src "ls180.v:2926.26-2926.59"
- cell $add $add$ls180.v:2926$630
+ attribute \src "ls180.v:2939.26-2939.59"
+ cell $add $add$ls180.v:2939$631
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \tx_fifo_level0
connect \B \tx_fifo_readable
- connect \Y $add$ls180.v:2926$630_Y
+ connect \Y $add$ls180.v:2939$631_Y
end
- attribute \src "ls180.v:2956.26-2956.59"
- cell $add $add$ls180.v:2956$641
+ attribute \src "ls180.v:2969.26-2969.59"
+ cell $add $add$ls180.v:2969$642
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \rx_fifo_level0
connect \B \rx_fifo_readable
- connect \Y $add$ls180.v:2956$641_Y
+ connect \Y $add$ls180.v:2969$642_Y
end
- attribute \src "ls180.v:4353.31-4353.60"
- cell $add $add$ls180.v:4353$1281
+ attribute \src "ls180.v:4372.31-4372.60"
+ cell $add $add$ls180.v:4372$1288
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \libresocsim_bus_errors
connect \B 1'1
- connect \Y $add$ls180.v:4353$1281_Y
+ connect \Y $add$ls180.v:4372$1288_Y
end
- attribute \src "ls180.v:4442.32-4442.62"
- cell $add $add$ls180.v:4442$1305
+ attribute \src "ls180.v:4461.32-4461.62"
+ cell $add $add$ls180.v:4461$1312
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_sequencer_counter
connect \B 1'1
- connect \Y $add$ls180.v:4442$1305_Y
+ connect \Y $add$ls180.v:4461$1312_Y
end
- attribute \src "ls180.v:4459.55-4459.109"
- cell $add $add$ls180.v:4459$1309
+ attribute \src "ls180.v:4478.55-4478.109"
+ cell $add $add$ls180.v:4478$1316
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:4459$1309_Y
+ connect \Y $add$ls180.v:4478$1316_Y
end
- attribute \src "ls180.v:4462.55-4462.109"
- cell $add $add$ls180.v:4462$1310
+ attribute \src "ls180.v:4481.55-4481.109"
+ cell $add $add$ls180.v:4481$1317
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:4462$1310_Y
+ connect \Y $add$ls180.v:4481$1317_Y
end
- attribute \src "ls180.v:4466.54-4466.106"
- cell $add $add$ls180.v:4466$1315
+ attribute \src "ls180.v:4485.54-4485.106"
+ cell $add $add$ls180.v:4485$1322
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:4466$1315_Y
+ connect \Y $add$ls180.v:4485$1322_Y
end
- attribute \src "ls180.v:4505.55-4505.109"
- cell $add $add$ls180.v:4505$1325
+ attribute \src "ls180.v:4524.55-4524.109"
+ cell $add $add$ls180.v:4524$1332
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:4505$1325_Y
+ connect \Y $add$ls180.v:4524$1332_Y
end
- attribute \src "ls180.v:4508.55-4508.109"
- cell $add $add$ls180.v:4508$1326
+ attribute \src "ls180.v:4527.55-4527.109"
+ cell $add $add$ls180.v:4527$1333
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:4508$1326_Y
+ connect \Y $add$ls180.v:4527$1333_Y
end
- attribute \src "ls180.v:4512.54-4512.106"
- cell $add $add$ls180.v:4512$1331
+ attribute \src "ls180.v:4531.54-4531.106"
+ cell $add $add$ls180.v:4531$1338
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:4512$1331_Y
+ connect \Y $add$ls180.v:4531$1338_Y
end
- attribute \src "ls180.v:4551.55-4551.109"
- cell $add $add$ls180.v:4551$1341
+ attribute \src "ls180.v:4570.55-4570.109"
+ cell $add $add$ls180.v:4570$1348
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:4551$1341_Y
+ connect \Y $add$ls180.v:4570$1348_Y
end
- attribute \src "ls180.v:4554.55-4554.109"
- cell $add $add$ls180.v:4554$1342
+ attribute \src "ls180.v:4573.55-4573.109"
+ cell $add $add$ls180.v:4573$1349
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:4554$1342_Y
+ connect \Y $add$ls180.v:4573$1349_Y
end
- attribute \src "ls180.v:4558.54-4558.106"
- cell $add $add$ls180.v:4558$1347
+ attribute \src "ls180.v:4577.54-4577.106"
+ cell $add $add$ls180.v:4577$1354
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:4558$1347_Y
+ connect \Y $add$ls180.v:4577$1354_Y
end
- attribute \src "ls180.v:4597.55-4597.109"
- cell $add $add$ls180.v:4597$1357
+ attribute \src "ls180.v:4616.55-4616.109"
+ cell $add $add$ls180.v:4616$1364
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $add$ls180.v:4597$1357_Y
+ connect \Y $add$ls180.v:4616$1364_Y
end
- attribute \src "ls180.v:4600.55-4600.109"
- cell $add $add$ls180.v:4600$1358
+ attribute \src "ls180.v:4619.55-4619.109"
+ cell $add $add$ls180.v:4619$1365
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_consume
connect \B 1'1
- connect \Y $add$ls180.v:4600$1358_Y
+ connect \Y $add$ls180.v:4619$1365_Y
end
- attribute \src "ls180.v:4604.54-4604.106"
- cell $add $add$ls180.v:4604$1363
+ attribute \src "ls180.v:4623.54-4623.106"
+ cell $add $add$ls180.v:4623$1370
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $add$ls180.v:4604$1363_Y
+ connect \Y $add$ls180.v:4623$1370_Y
end
- attribute \src "ls180.v:4834.29-4834.56"
- cell $add $add$ls180.v:4834$1417
+ attribute \src "ls180.v:4853.29-4853.56"
+ cell $add $add$ls180.v:4853$1424
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \uart_phy_tx_bitcount
connect \B 1'1
- connect \Y $add$ls180.v:4834$1417_Y
+ connect \Y $add$ls180.v:4853$1424_Y
end
- attribute \src "ls180.v:4850.63-4850.111"
- cell $add $add$ls180.v:4850$1420
+ attribute \src "ls180.v:4869.63-4869.111"
+ cell $add $add$ls180.v:4869$1427
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 33
connect \A \uart_phy_phase_accumulator_tx
connect \B \uart_phy_storage
- connect \Y $add$ls180.v:4850$1420_Y
+ connect \Y $add$ls180.v:4869$1427_Y
end
- attribute \src "ls180.v:4863.29-4863.56"
- cell $add $add$ls180.v:4863$1424
+ attribute \src "ls180.v:4882.29-4882.56"
+ cell $add $add$ls180.v:4882$1431
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \uart_phy_rx_bitcount
connect \B 1'1
- connect \Y $add$ls180.v:4863$1424_Y
+ connect \Y $add$ls180.v:4882$1431_Y
end
- attribute \src "ls180.v:4882.63-4882.111"
- cell $add $add$ls180.v:4882$1427
+ attribute \src "ls180.v:4901.63-4901.111"
+ cell $add $add$ls180.v:4901$1434
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 33
connect \A \uart_phy_phase_accumulator_rx
connect \B \uart_phy_storage
- connect \Y $add$ls180.v:4882$1427_Y
+ connect \Y $add$ls180.v:4901$1434_Y
end
- attribute \src "ls180.v:4908.23-4908.45"
- cell $add $add$ls180.v:4908$1435
+ attribute \src "ls180.v:4927.23-4927.45"
+ cell $add $add$ls180.v:4927$1442
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \tx_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:4908$1435_Y
+ connect \Y $add$ls180.v:4927$1442_Y
end
- attribute \src "ls180.v:4911.23-4911.45"
- cell $add $add$ls180.v:4911$1436
+ attribute \src "ls180.v:4930.23-4930.45"
+ cell $add $add$ls180.v:4930$1443
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \tx_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:4911$1436_Y
+ connect \Y $add$ls180.v:4930$1443_Y
end
- attribute \src "ls180.v:4915.23-4915.44"
- cell $add $add$ls180.v:4915$1441
+ attribute \src "ls180.v:4934.23-4934.44"
+ cell $add $add$ls180.v:4934$1448
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \tx_fifo_level0
connect \B 1'1
- connect \Y $add$ls180.v:4915$1441_Y
+ connect \Y $add$ls180.v:4934$1448_Y
end
- attribute \src "ls180.v:4930.23-4930.45"
- cell $add $add$ls180.v:4930$1446
+ attribute \src "ls180.v:4949.23-4949.45"
+ cell $add $add$ls180.v:4949$1453
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \rx_fifo_produce
connect \B 1'1
- connect \Y $add$ls180.v:4930$1446_Y
+ connect \Y $add$ls180.v:4949$1453_Y
end
- attribute \src "ls180.v:4933.23-4933.45"
- cell $add $add$ls180.v:4933$1447
+ attribute \src "ls180.v:4952.23-4952.45"
+ cell $add $add$ls180.v:4952$1454
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \rx_fifo_consume
connect \B 1'1
- connect \Y $add$ls180.v:4933$1447_Y
+ connect \Y $add$ls180.v:4952$1454_Y
end
- attribute \src "ls180.v:4937.23-4937.44"
- cell $add $add$ls180.v:4937$1452
+ attribute \src "ls180.v:4956.23-4956.44"
+ cell $add $add$ls180.v:4956$1459
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \rx_fifo_level0
connect \B 1'1
- connect \Y $add$ls180.v:4937$1452_Y
+ connect \Y $add$ls180.v:4956$1459_Y
end
- attribute \src "ls180.v:1549.9-1549.80"
- cell $and $and$ls180.v:1549$27
+ attribute \src "ls180.v:1562.9-1562.80"
+ cell $and $and$ls180.v:1562$28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \interface0_converted_interface_stb
connect \B \interface0_converted_interface_cyc
- connect \Y $and$ls180.v:1549$27_Y
+ connect \Y $and$ls180.v:1562$28_Y
end
- attribute \src "ls180.v:1567.9-1567.80"
- cell $and $and$ls180.v:1567$34
+ attribute \src "ls180.v:1580.9-1580.80"
+ cell $and $and$ls180.v:1580$35
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \interface0_converted_interface_stb
connect \B \interface0_converted_interface_cyc
- connect \Y $and$ls180.v:1567$34_Y
+ connect \Y $and$ls180.v:1580$35_Y
end
- attribute \src "ls180.v:1609.9-1609.80"
- cell $and $and$ls180.v:1609$38
+ attribute \src "ls180.v:1622.9-1622.80"
+ cell $and $and$ls180.v:1622$39
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \interface1_converted_interface_stb
connect \B \interface1_converted_interface_cyc
- connect \Y $and$ls180.v:1609$38_Y
+ connect \Y $and$ls180.v:1622$39_Y
end
- attribute \src "ls180.v:1627.9-1627.80"
- cell $and $and$ls180.v:1627$45
+ attribute \src "ls180.v:1640.9-1640.80"
+ cell $and $and$ls180.v:1640$46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \interface1_converted_interface_stb
connect \B \interface1_converted_interface_cyc
- connect \Y $and$ls180.v:1627$45_Y
+ connect \Y $and$ls180.v:1640$46_Y
end
- attribute \src "ls180.v:1669.9-1669.86"
- cell $and $and$ls180.v:1669$49
+ attribute \src "ls180.v:1682.9-1682.86"
+ cell $and $and$ls180.v:1682$50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \socbushandler_converted_interface_stb
connect \B \socbushandler_converted_interface_cyc
- connect \Y $and$ls180.v:1669$49_Y
+ connect \Y $and$ls180.v:1682$50_Y
end
- attribute \src "ls180.v:1687.9-1687.86"
- cell $and $and$ls180.v:1687$56
+ attribute \src "ls180.v:1700.9-1700.86"
+ cell $and $and$ls180.v:1700$57
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \socbushandler_converted_interface_stb
connect \B \socbushandler_converted_interface_cyc
- connect \Y $and$ls180.v:1687$56_Y
+ connect \Y $and$ls180.v:1700$57_Y
end
- attribute \src "ls180.v:1697.26-1697.75"
- cell $and $and$ls180.v:1697$58
+ attribute \src "ls180.v:1710.26-1710.75"
+ cell $and $and$ls180.v:1710$59
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1697$58_Y
+ connect \Y $and$ls180.v:1710$59_Y
end
- attribute \src "ls180.v:1697.25-1697.101"
- cell $and $and$ls180.v:1697$59
+ attribute \src "ls180.v:1710.25-1710.101"
+ cell $and $and$ls180.v:1710$60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1697$58_Y
+ connect \A $and$ls180.v:1710$59_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1697$59_Y
+ connect \Y $and$ls180.v:1710$60_Y
end
- attribute \src "ls180.v:1697.24-1697.131"
- cell $and $and$ls180.v:1697$60
+ attribute \src "ls180.v:1710.24-1710.131"
+ cell $and $and$ls180.v:1710$61
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1697$59_Y
+ connect \A $and$ls180.v:1710$60_Y
connect \B \libresocsim_ram_bus_sel [0]
- connect \Y $and$ls180.v:1697$60_Y
+ connect \Y $and$ls180.v:1710$61_Y
end
- attribute \src "ls180.v:1698.26-1698.75"
- cell $and $and$ls180.v:1698$61
+ attribute \src "ls180.v:1711.26-1711.75"
+ cell $and $and$ls180.v:1711$62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1698$61_Y
+ connect \Y $and$ls180.v:1711$62_Y
end
- attribute \src "ls180.v:1698.25-1698.101"
- cell $and $and$ls180.v:1698$62
+ attribute \src "ls180.v:1711.25-1711.101"
+ cell $and $and$ls180.v:1711$63
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1698$61_Y
+ connect \A $and$ls180.v:1711$62_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1698$62_Y
+ connect \Y $and$ls180.v:1711$63_Y
end
- attribute \src "ls180.v:1698.24-1698.131"
- cell $and $and$ls180.v:1698$63
+ attribute \src "ls180.v:1711.24-1711.131"
+ cell $and $and$ls180.v:1711$64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1698$62_Y
+ connect \A $and$ls180.v:1711$63_Y
connect \B \libresocsim_ram_bus_sel [1]
- connect \Y $and$ls180.v:1698$63_Y
+ connect \Y $and$ls180.v:1711$64_Y
end
- attribute \src "ls180.v:1699.26-1699.75"
- cell $and $and$ls180.v:1699$64
+ attribute \src "ls180.v:1712.26-1712.75"
+ cell $and $and$ls180.v:1712$65
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1699$64_Y
+ connect \Y $and$ls180.v:1712$65_Y
end
- attribute \src "ls180.v:1699.25-1699.101"
- cell $and $and$ls180.v:1699$65
+ attribute \src "ls180.v:1712.25-1712.101"
+ cell $and $and$ls180.v:1712$66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1699$64_Y
+ connect \A $and$ls180.v:1712$65_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1699$65_Y
+ connect \Y $and$ls180.v:1712$66_Y
end
- attribute \src "ls180.v:1699.24-1699.131"
- cell $and $and$ls180.v:1699$66
+ attribute \src "ls180.v:1712.24-1712.131"
+ cell $and $and$ls180.v:1712$67
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1699$65_Y
+ connect \A $and$ls180.v:1712$66_Y
connect \B \libresocsim_ram_bus_sel [2]
- connect \Y $and$ls180.v:1699$66_Y
+ connect \Y $and$ls180.v:1712$67_Y
end
- attribute \src "ls180.v:1700.26-1700.75"
- cell $and $and$ls180.v:1700$67
+ attribute \src "ls180.v:1713.26-1713.75"
+ cell $and $and$ls180.v:1713$68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1700$67_Y
+ connect \Y $and$ls180.v:1713$68_Y
end
- attribute \src "ls180.v:1700.25-1700.101"
- cell $and $and$ls180.v:1700$68
+ attribute \src "ls180.v:1713.25-1713.101"
+ cell $and $and$ls180.v:1713$69
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1700$67_Y
+ connect \A $and$ls180.v:1713$68_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1700$68_Y
+ connect \Y $and$ls180.v:1713$69_Y
end
- attribute \src "ls180.v:1700.24-1700.131"
- cell $and $and$ls180.v:1700$69
+ attribute \src "ls180.v:1713.24-1713.131"
+ cell $and $and$ls180.v:1713$70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1700$68_Y
+ connect \A $and$ls180.v:1713$69_Y
connect \B \libresocsim_ram_bus_sel [3]
- connect \Y $and$ls180.v:1700$69_Y
+ connect \Y $and$ls180.v:1713$70_Y
end
- attribute \src "ls180.v:1701.26-1701.75"
- cell $and $and$ls180.v:1701$70
+ attribute \src "ls180.v:1714.26-1714.75"
+ cell $and $and$ls180.v:1714$71
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1701$70_Y
+ connect \Y $and$ls180.v:1714$71_Y
end
- attribute \src "ls180.v:1701.25-1701.101"
- cell $and $and$ls180.v:1701$71
+ attribute \src "ls180.v:1714.25-1714.101"
+ cell $and $and$ls180.v:1714$72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1701$70_Y
+ connect \A $and$ls180.v:1714$71_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1701$71_Y
+ connect \Y $and$ls180.v:1714$72_Y
end
- attribute \src "ls180.v:1701.24-1701.131"
- cell $and $and$ls180.v:1701$72
+ attribute \src "ls180.v:1714.24-1714.131"
+ cell $and $and$ls180.v:1714$73
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1701$71_Y
+ connect \A $and$ls180.v:1714$72_Y
connect \B \libresocsim_ram_bus_sel [4]
- connect \Y $and$ls180.v:1701$72_Y
+ connect \Y $and$ls180.v:1714$73_Y
end
- attribute \src "ls180.v:1702.26-1702.75"
- cell $and $and$ls180.v:1702$73
+ attribute \src "ls180.v:1715.26-1715.75"
+ cell $and $and$ls180.v:1715$74
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1702$73_Y
+ connect \Y $and$ls180.v:1715$74_Y
end
- attribute \src "ls180.v:1702.25-1702.101"
- cell $and $and$ls180.v:1702$74
+ attribute \src "ls180.v:1715.25-1715.101"
+ cell $and $and$ls180.v:1715$75
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1702$73_Y
+ connect \A $and$ls180.v:1715$74_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1702$74_Y
+ connect \Y $and$ls180.v:1715$75_Y
end
- attribute \src "ls180.v:1702.24-1702.131"
- cell $and $and$ls180.v:1702$75
+ attribute \src "ls180.v:1715.24-1715.131"
+ cell $and $and$ls180.v:1715$76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1702$74_Y
+ connect \A $and$ls180.v:1715$75_Y
connect \B \libresocsim_ram_bus_sel [5]
- connect \Y $and$ls180.v:1702$75_Y
+ connect \Y $and$ls180.v:1715$76_Y
end
- attribute \src "ls180.v:1703.26-1703.75"
- cell $and $and$ls180.v:1703$76
+ attribute \src "ls180.v:1716.26-1716.75"
+ cell $and $and$ls180.v:1716$77
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1703$76_Y
+ connect \Y $and$ls180.v:1716$77_Y
end
- attribute \src "ls180.v:1703.25-1703.101"
- cell $and $and$ls180.v:1703$77
+ attribute \src "ls180.v:1716.25-1716.101"
+ cell $and $and$ls180.v:1716$78
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1703$76_Y
+ connect \A $and$ls180.v:1716$77_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1703$77_Y
+ connect \Y $and$ls180.v:1716$78_Y
end
- attribute \src "ls180.v:1703.24-1703.131"
- cell $and $and$ls180.v:1703$78
+ attribute \src "ls180.v:1716.24-1716.131"
+ cell $and $and$ls180.v:1716$79
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1703$77_Y
+ connect \A $and$ls180.v:1716$78_Y
connect \B \libresocsim_ram_bus_sel [6]
- connect \Y $and$ls180.v:1703$78_Y
+ connect \Y $and$ls180.v:1716$79_Y
end
- attribute \src "ls180.v:1704.26-1704.75"
- cell $and $and$ls180.v:1704$79
+ attribute \src "ls180.v:1717.26-1717.75"
+ cell $and $and$ls180.v:1717$80
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:1704$79_Y
+ connect \Y $and$ls180.v:1717$80_Y
end
- attribute \src "ls180.v:1704.25-1704.101"
- cell $and $and$ls180.v:1704$80
+ attribute \src "ls180.v:1717.25-1717.101"
+ cell $and $and$ls180.v:1717$81
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1704$79_Y
+ connect \A $and$ls180.v:1717$80_Y
connect \B \libresocsim_ram_bus_we
- connect \Y $and$ls180.v:1704$80_Y
+ connect \Y $and$ls180.v:1717$81_Y
end
- attribute \src "ls180.v:1704.24-1704.131"
- cell $and $and$ls180.v:1704$81
+ attribute \src "ls180.v:1717.24-1717.131"
+ cell $and $and$ls180.v:1717$82
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1704$80_Y
+ connect \A $and$ls180.v:1717$81_Y
connect \B \libresocsim_ram_bus_sel [7]
- connect \Y $and$ls180.v:1704$81_Y
+ connect \Y $and$ls180.v:1717$82_Y
end
- attribute \src "ls180.v:1713.7-1713.79"
- cell $and $and$ls180.v:1713$84
+ attribute \src "ls180.v:1726.7-1726.79"
+ cell $and $and$ls180.v:1726$85
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_eventmanager_pending_re
connect \B \libresocsim_eventmanager_pending_r
- connect \Y $and$ls180.v:1713$84_Y
+ connect \Y $and$ls180.v:1726$85_Y
end
- attribute \src "ls180.v:1718.27-1718.96"
- cell $and $and$ls180.v:1718$85
+ attribute \src "ls180.v:1731.27-1731.96"
+ cell $and $and$ls180.v:1731$86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_eventmanager_pending_w
connect \B \libresocsim_eventmanager_storage
- connect \Y $and$ls180.v:1718$85_Y
+ connect \Y $and$ls180.v:1731$86_Y
end
- attribute \src "ls180.v:1722.18-1722.59"
- cell $and $and$ls180.v:1722$87
+ attribute \src "ls180.v:1735.18-1735.59"
+ cell $and $and$ls180.v:1735$88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1722$87_Y
+ connect \Y $and$ls180.v:1735$88_Y
end
- attribute \src "ls180.v:1722.17-1722.81"
- cell $and $and$ls180.v:1722$88
+ attribute \src "ls180.v:1735.17-1735.81"
+ cell $and $and$ls180.v:1735$89
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1722$87_Y
+ connect \A $and$ls180.v:1735$88_Y
connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1722$88_Y
+ connect \Y $and$ls180.v:1735$89_Y
end
- attribute \src "ls180.v:1722.16-1722.107"
- cell $and $and$ls180.v:1722$89
+ attribute \src "ls180.v:1735.16-1735.107"
+ cell $and $and$ls180.v:1735$90
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1722$88_Y
+ connect \A $and$ls180.v:1735$89_Y
connect \B \ram_bus_ram_bus_sel [0]
- connect \Y $and$ls180.v:1722$89_Y
+ connect \Y $and$ls180.v:1735$90_Y
end
- attribute \src "ls180.v:1723.18-1723.59"
- cell $and $and$ls180.v:1723$90
+ attribute \src "ls180.v:1736.18-1736.59"
+ cell $and $and$ls180.v:1736$91
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1723$90_Y
+ connect \Y $and$ls180.v:1736$91_Y
end
- attribute \src "ls180.v:1723.17-1723.81"
- cell $and $and$ls180.v:1723$91
+ attribute \src "ls180.v:1736.17-1736.81"
+ cell $and $and$ls180.v:1736$92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1723$90_Y
+ connect \A $and$ls180.v:1736$91_Y
connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1723$91_Y
+ connect \Y $and$ls180.v:1736$92_Y
end
- attribute \src "ls180.v:1723.16-1723.107"
- cell $and $and$ls180.v:1723$92
+ attribute \src "ls180.v:1736.16-1736.107"
+ cell $and $and$ls180.v:1736$93
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1723$91_Y
+ connect \A $and$ls180.v:1736$92_Y
connect \B \ram_bus_ram_bus_sel [1]
- connect \Y $and$ls180.v:1723$92_Y
+ connect \Y $and$ls180.v:1736$93_Y
end
- attribute \src "ls180.v:1724.18-1724.59"
- cell $and $and$ls180.v:1724$93
+ attribute \src "ls180.v:1737.18-1737.59"
+ cell $and $and$ls180.v:1737$94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1724$93_Y
+ connect \Y $and$ls180.v:1737$94_Y
end
- attribute \src "ls180.v:1724.17-1724.81"
- cell $and $and$ls180.v:1724$94
+ attribute \src "ls180.v:1737.17-1737.81"
+ cell $and $and$ls180.v:1737$95
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1724$93_Y
+ connect \A $and$ls180.v:1737$94_Y
connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1724$94_Y
+ connect \Y $and$ls180.v:1737$95_Y
end
- attribute \src "ls180.v:1724.16-1724.107"
- cell $and $and$ls180.v:1724$95
+ attribute \src "ls180.v:1737.16-1737.107"
+ cell $and $and$ls180.v:1737$96
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1724$94_Y
+ connect \A $and$ls180.v:1737$95_Y
connect \B \ram_bus_ram_bus_sel [2]
- connect \Y $and$ls180.v:1724$95_Y
+ connect \Y $and$ls180.v:1737$96_Y
end
- attribute \src "ls180.v:1725.18-1725.59"
- cell $and $and$ls180.v:1725$96
+ attribute \src "ls180.v:1738.18-1738.59"
+ cell $and $and$ls180.v:1738$97
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1725$96_Y
+ connect \Y $and$ls180.v:1738$97_Y
end
- attribute \src "ls180.v:1725.17-1725.81"
- cell $and $and$ls180.v:1725$97
+ attribute \src "ls180.v:1738.17-1738.81"
+ cell $and $and$ls180.v:1738$98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1725$96_Y
+ connect \A $and$ls180.v:1738$97_Y
connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1725$97_Y
+ connect \Y $and$ls180.v:1738$98_Y
end
- attribute \src "ls180.v:1725.16-1725.107"
- cell $and $and$ls180.v:1725$98
+ attribute \src "ls180.v:1738.16-1738.107"
+ cell $and $and$ls180.v:1738$99
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1725$97_Y
+ connect \A $and$ls180.v:1738$98_Y
connect \B \ram_bus_ram_bus_sel [3]
- connect \Y $and$ls180.v:1725$98_Y
+ connect \Y $and$ls180.v:1738$99_Y
end
- attribute \src "ls180.v:1726.17-1726.81"
- cell $and $and$ls180.v:1726$100
+ attribute \src "ls180.v:1739.18-1739.59"
+ cell $and $and$ls180.v:1739$100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1726$99_Y
- connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1726$100_Y
+ connect \A \ram_bus_ram_bus_cyc
+ connect \B \ram_bus_ram_bus_stb
+ connect \Y $and$ls180.v:1739$100_Y
end
- attribute \src "ls180.v:1726.16-1726.107"
- cell $and $and$ls180.v:1726$101
+ attribute \src "ls180.v:1739.17-1739.81"
+ cell $and $and$ls180.v:1739$101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1726$100_Y
- connect \B \ram_bus_ram_bus_sel [4]
- connect \Y $and$ls180.v:1726$101_Y
+ connect \A $and$ls180.v:1739$100_Y
+ connect \B \ram_bus_ram_bus_we
+ connect \Y $and$ls180.v:1739$101_Y
end
- attribute \src "ls180.v:1726.18-1726.59"
- cell $and $and$ls180.v:1726$99
+ attribute \src "ls180.v:1739.16-1739.107"
+ cell $and $and$ls180.v:1739$102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ram_bus_ram_bus_cyc
- connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1726$99_Y
+ connect \A $and$ls180.v:1739$101_Y
+ connect \B \ram_bus_ram_bus_sel [4]
+ connect \Y $and$ls180.v:1739$102_Y
end
- attribute \src "ls180.v:1727.18-1727.59"
- cell $and $and$ls180.v:1727$102
+ attribute \src "ls180.v:1740.18-1740.59"
+ cell $and $and$ls180.v:1740$103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1727$102_Y
+ connect \Y $and$ls180.v:1740$103_Y
end
- attribute \src "ls180.v:1727.17-1727.81"
- cell $and $and$ls180.v:1727$103
+ attribute \src "ls180.v:1740.17-1740.81"
+ cell $and $and$ls180.v:1740$104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1727$102_Y
+ connect \A $and$ls180.v:1740$103_Y
connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1727$103_Y
+ connect \Y $and$ls180.v:1740$104_Y
end
- attribute \src "ls180.v:1727.16-1727.107"
- cell $and $and$ls180.v:1727$104
+ attribute \src "ls180.v:1740.16-1740.107"
+ cell $and $and$ls180.v:1740$105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1727$103_Y
+ connect \A $and$ls180.v:1740$104_Y
connect \B \ram_bus_ram_bus_sel [5]
- connect \Y $and$ls180.v:1727$104_Y
+ connect \Y $and$ls180.v:1740$105_Y
end
- attribute \src "ls180.v:1728.18-1728.59"
- cell $and $and$ls180.v:1728$105
+ attribute \src "ls180.v:1741.18-1741.59"
+ cell $and $and$ls180.v:1741$106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1728$105_Y
+ connect \Y $and$ls180.v:1741$106_Y
end
- attribute \src "ls180.v:1728.17-1728.81"
- cell $and $and$ls180.v:1728$106
+ attribute \src "ls180.v:1741.17-1741.81"
+ cell $and $and$ls180.v:1741$107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1728$105_Y
+ connect \A $and$ls180.v:1741$106_Y
connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1728$106_Y
+ connect \Y $and$ls180.v:1741$107_Y
end
- attribute \src "ls180.v:1728.16-1728.107"
- cell $and $and$ls180.v:1728$107
+ attribute \src "ls180.v:1741.16-1741.107"
+ cell $and $and$ls180.v:1741$108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1728$106_Y
+ connect \A $and$ls180.v:1741$107_Y
connect \B \ram_bus_ram_bus_sel [6]
- connect \Y $and$ls180.v:1728$107_Y
+ connect \Y $and$ls180.v:1741$108_Y
end
- attribute \src "ls180.v:1729.18-1729.59"
- cell $and $and$ls180.v:1729$108
+ attribute \src "ls180.v:1742.18-1742.59"
+ cell $and $and$ls180.v:1742$109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:1729$108_Y
+ connect \Y $and$ls180.v:1742$109_Y
end
- attribute \src "ls180.v:1729.17-1729.81"
- cell $and $and$ls180.v:1729$109
+ attribute \src "ls180.v:1742.17-1742.81"
+ cell $and $and$ls180.v:1742$110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1729$108_Y
+ connect \A $and$ls180.v:1742$109_Y
connect \B \ram_bus_ram_bus_we
- connect \Y $and$ls180.v:1729$109_Y
+ connect \Y $and$ls180.v:1742$110_Y
end
- attribute \src "ls180.v:1729.16-1729.107"
- cell $and $and$ls180.v:1729$110
+ attribute \src "ls180.v:1742.16-1742.107"
+ cell $and $and$ls180.v:1742$111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1729$109_Y
+ connect \A $and$ls180.v:1742$110_Y
connect \B \ram_bus_ram_bus_sel [7]
- connect \Y $and$ls180.v:1729$110_Y
+ connect \Y $and$ls180.v:1742$111_Y
end
- attribute \src "ls180.v:1846.35-1846.84"
- cell $and $and$ls180.v:1846$117
+ attribute \src "ls180.v:1859.35-1859.84"
+ cell $and $and$ls180.v:1859$118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_command_issue_re
connect \B \sdram_command_storage [4]
- connect \Y $and$ls180.v:1846$117_Y
+ connect \Y $and$ls180.v:1859$118_Y
end
- attribute \src "ls180.v:1847.35-1847.84"
- cell $and $and$ls180.v:1847$118
+ attribute \src "ls180.v:1860.35-1860.84"
+ cell $and $and$ls180.v:1860$119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_command_issue_re
connect \B \sdram_command_storage [5]
- connect \Y $and$ls180.v:1847$118_Y
+ connect \Y $and$ls180.v:1860$119_Y
end
- attribute \src "ls180.v:1885.33-1885.88"
- cell $and $and$ls180.v:1885$124
+ attribute \src "ls180.v:1898.33-1898.88"
+ cell $and $and$ls180.v:1898$125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_done1
- connect \B $eq$ls180.v:1885$123_Y
- connect \Y $and$ls180.v:1885$124_Y
+ connect \B $eq$ls180.v:1898$124_Y
+ connect \Y $and$ls180.v:1898$125_Y
end
- attribute \src "ls180.v:1939.45-1939.104"
- cell $and $and$ls180.v:1939$132
+ attribute \src "ls180.v:1952.45-1952.104"
+ cell $and $and$ls180.v:1952$133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_valid
connect \B \sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:1939$132_Y
+ connect \Y $and$ls180.v:1952$133_Y
end
- attribute \src "ls180.v:1939.44-1939.147"
- cell $and $and$ls180.v:1939$133
+ attribute \src "ls180.v:1952.44-1952.147"
+ cell $and $and$ls180.v:1952$134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1939$132_Y
+ connect \A $and$ls180.v:1952$133_Y
connect \B \sdram_bankmachine0_cmd_payload_is_write
- connect \Y $and$ls180.v:1939$133_Y
+ connect \Y $and$ls180.v:1952$134_Y
end
- attribute \src "ls180.v:1940.44-1940.103"
- cell $and $and$ls180.v:1940$134
+ attribute \src "ls180.v:1953.44-1953.103"
+ cell $and $and$ls180.v:1953$135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_valid
connect \B \sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:1940$134_Y
+ connect \Y $and$ls180.v:1953$135_Y
end
- attribute \src "ls180.v:1940.43-1940.134"
- cell $and $and$ls180.v:1940$135
+ attribute \src "ls180.v:1953.43-1953.134"
+ cell $and $and$ls180.v:1953$136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1940$134_Y
+ connect \A $and$ls180.v:1953$135_Y
connect \B \sdram_bankmachine0_row_open
- connect \Y $and$ls180.v:1940$135_Y
+ connect \Y $and$ls180.v:1953$136_Y
end
- attribute \src "ls180.v:1941.45-1941.104"
- cell $and $and$ls180.v:1941$136
+ attribute \src "ls180.v:1954.45-1954.104"
+ cell $and $and$ls180.v:1954$137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_valid
connect \B \sdram_bankmachine0_cmd_ready
- connect \Y $and$ls180.v:1941$136_Y
+ connect \Y $and$ls180.v:1954$137_Y
end
- attribute \src "ls180.v:1941.44-1941.135"
- cell $and $and$ls180.v:1941$137
+ attribute \src "ls180.v:1954.44-1954.135"
+ cell $and $and$ls180.v:1954$138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:1941$136_Y
+ connect \A $and$ls180.v:1954$137_Y
connect \B \sdram_bankmachine0_row_open
- connect \Y $and$ls180.v:1941$137_Y
+ connect \Y $and$ls180.v:1954$138_Y
end
- attribute \src "ls180.v:1944.7-1944.104"
- cell $and $and$ls180.v:1944$139
+ attribute \src "ls180.v:1957.7-1957.104"
+ cell $and $and$ls180.v:1957$140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $and$ls180.v:1944$139_Y
+ connect \Y $and$ls180.v:1957$140_Y
end
- attribute \src "ls180.v:1973.61-1973.226"
- cell $and $and$ls180.v:1973$145
+ attribute \src "ls180.v:1986.61-1986.226"
+ cell $and $and$ls180.v:1986$146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
- connect \B $or$ls180.v:1973$144_Y
- connect \Y $and$ls180.v:1973$145_Y
+ connect \B $or$ls180.v:1986$145_Y
+ connect \Y $and$ls180.v:1986$146_Y
end
- attribute \src "ls180.v:1974.59-1974.172"
- cell $and $and$ls180.v:1974$146
+ attribute \src "ls180.v:1987.59-1987.172"
+ cell $and $and$ls180.v:1987$147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable
connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re
- connect \Y $and$ls180.v:1974$146_Y
+ connect \Y $and$ls180.v:1987$147_Y
end
- attribute \src "ls180.v:1998.9-1998.76"
- cell $and $and$ls180.v:1998$152
+ attribute \src "ls180.v:2011.9-2011.76"
+ cell $and $and$ls180.v:2011$153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_twtpcon_ready
connect \B \sdram_bankmachine0_trascon_ready
- connect \Y $and$ls180.v:1998$152_Y
+ connect \Y $and$ls180.v:2011$153_Y
end
- attribute \src "ls180.v:2010.9-2010.76"
- cell $and $and$ls180.v:2010$153
+ attribute \src "ls180.v:2023.9-2023.76"
+ cell $and $and$ls180.v:2023$154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_twtpcon_ready
connect \B \sdram_bankmachine0_trascon_ready
- connect \Y $and$ls180.v:2010$153_Y
+ connect \Y $and$ls180.v:2023$154_Y
end
- attribute \src "ls180.v:2060.13-2060.77"
- cell $and $and$ls180.v:2060$155
+ attribute \src "ls180.v:2073.13-2073.77"
+ cell $and $and$ls180.v:2073$156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_ready
connect \B \sdram_bankmachine0_auto_precharge
- connect \Y $and$ls180.v:2060$155_Y
+ connect \Y $and$ls180.v:2073$156_Y
end
- attribute \src "ls180.v:2096.45-2096.104"
- cell $and $and$ls180.v:2096$162
+ attribute \src "ls180.v:2109.45-2109.104"
+ cell $and $and$ls180.v:2109$163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_valid
connect \B \sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:2096$162_Y
+ connect \Y $and$ls180.v:2109$163_Y
end
- attribute \src "ls180.v:2096.44-2096.147"
- cell $and $and$ls180.v:2096$163
+ attribute \src "ls180.v:2109.44-2109.147"
+ cell $and $and$ls180.v:2109$164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2096$162_Y
+ connect \A $and$ls180.v:2109$163_Y
connect \B \sdram_bankmachine1_cmd_payload_is_write
- connect \Y $and$ls180.v:2096$163_Y
+ connect \Y $and$ls180.v:2109$164_Y
end
- attribute \src "ls180.v:2097.44-2097.103"
- cell $and $and$ls180.v:2097$164
+ attribute \src "ls180.v:2110.44-2110.103"
+ cell $and $and$ls180.v:2110$165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_valid
connect \B \sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:2097$164_Y
+ connect \Y $and$ls180.v:2110$165_Y
end
- attribute \src "ls180.v:2097.43-2097.134"
- cell $and $and$ls180.v:2097$165
+ attribute \src "ls180.v:2110.43-2110.134"
+ cell $and $and$ls180.v:2110$166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2097$164_Y
+ connect \A $and$ls180.v:2110$165_Y
connect \B \sdram_bankmachine1_row_open
- connect \Y $and$ls180.v:2097$165_Y
+ connect \Y $and$ls180.v:2110$166_Y
end
- attribute \src "ls180.v:2098.45-2098.104"
- cell $and $and$ls180.v:2098$166
+ attribute \src "ls180.v:2111.45-2111.104"
+ cell $and $and$ls180.v:2111$167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_valid
connect \B \sdram_bankmachine1_cmd_ready
- connect \Y $and$ls180.v:2098$166_Y
+ connect \Y $and$ls180.v:2111$167_Y
end
- attribute \src "ls180.v:2098.44-2098.135"
- cell $and $and$ls180.v:2098$167
+ attribute \src "ls180.v:2111.44-2111.135"
+ cell $and $and$ls180.v:2111$168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2098$166_Y
+ connect \A $and$ls180.v:2111$167_Y
connect \B \sdram_bankmachine1_row_open
- connect \Y $and$ls180.v:2098$167_Y
+ connect \Y $and$ls180.v:2111$168_Y
end
- attribute \src "ls180.v:2101.7-2101.104"
- cell $and $and$ls180.v:2101$169
+ attribute \src "ls180.v:2114.7-2114.104"
+ cell $and $and$ls180.v:2114$170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $and$ls180.v:2101$169_Y
+ connect \Y $and$ls180.v:2114$170_Y
end
- attribute \src "ls180.v:2130.61-2130.226"
- cell $and $and$ls180.v:2130$175
+ attribute \src "ls180.v:2143.61-2143.226"
+ cell $and $and$ls180.v:2143$176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
- connect \B $or$ls180.v:2130$174_Y
- connect \Y $and$ls180.v:2130$175_Y
+ connect \B $or$ls180.v:2143$175_Y
+ connect \Y $and$ls180.v:2143$176_Y
end
- attribute \src "ls180.v:2131.59-2131.172"
- cell $and $and$ls180.v:2131$176
+ attribute \src "ls180.v:2144.59-2144.172"
+ cell $and $and$ls180.v:2144$177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable
connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re
- connect \Y $and$ls180.v:2131$176_Y
+ connect \Y $and$ls180.v:2144$177_Y
end
- attribute \src "ls180.v:2155.9-2155.76"
- cell $and $and$ls180.v:2155$182
+ attribute \src "ls180.v:2168.9-2168.76"
+ cell $and $and$ls180.v:2168$183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_twtpcon_ready
connect \B \sdram_bankmachine1_trascon_ready
- connect \Y $and$ls180.v:2155$182_Y
+ connect \Y $and$ls180.v:2168$183_Y
end
- attribute \src "ls180.v:2167.9-2167.76"
- cell $and $and$ls180.v:2167$183
+ attribute \src "ls180.v:2180.9-2180.76"
+ cell $and $and$ls180.v:2180$184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_twtpcon_ready
connect \B \sdram_bankmachine1_trascon_ready
- connect \Y $and$ls180.v:2167$183_Y
+ connect \Y $and$ls180.v:2180$184_Y
end
- attribute \src "ls180.v:2217.13-2217.77"
- cell $and $and$ls180.v:2217$185
+ attribute \src "ls180.v:2230.13-2230.77"
+ cell $and $and$ls180.v:2230$186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_ready
connect \B \sdram_bankmachine1_auto_precharge
- connect \Y $and$ls180.v:2217$185_Y
+ connect \Y $and$ls180.v:2230$186_Y
end
- attribute \src "ls180.v:2253.45-2253.104"
- cell $and $and$ls180.v:2253$192
+ attribute \src "ls180.v:2266.45-2266.104"
+ cell $and $and$ls180.v:2266$193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_valid
connect \B \sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:2253$192_Y
+ connect \Y $and$ls180.v:2266$193_Y
end
- attribute \src "ls180.v:2253.44-2253.147"
- cell $and $and$ls180.v:2253$193
+ attribute \src "ls180.v:2266.44-2266.147"
+ cell $and $and$ls180.v:2266$194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2253$192_Y
+ connect \A $and$ls180.v:2266$193_Y
connect \B \sdram_bankmachine2_cmd_payload_is_write
- connect \Y $and$ls180.v:2253$193_Y
+ connect \Y $and$ls180.v:2266$194_Y
end
- attribute \src "ls180.v:2254.44-2254.103"
- cell $and $and$ls180.v:2254$194
+ attribute \src "ls180.v:2267.44-2267.103"
+ cell $and $and$ls180.v:2267$195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_valid
connect \B \sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:2254$194_Y
+ connect \Y $and$ls180.v:2267$195_Y
end
- attribute \src "ls180.v:2254.43-2254.134"
- cell $and $and$ls180.v:2254$195
+ attribute \src "ls180.v:2267.43-2267.134"
+ cell $and $and$ls180.v:2267$196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2254$194_Y
+ connect \A $and$ls180.v:2267$195_Y
connect \B \sdram_bankmachine2_row_open
- connect \Y $and$ls180.v:2254$195_Y
+ connect \Y $and$ls180.v:2267$196_Y
end
- attribute \src "ls180.v:2255.45-2255.104"
- cell $and $and$ls180.v:2255$196
+ attribute \src "ls180.v:2268.45-2268.104"
+ cell $and $and$ls180.v:2268$197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_valid
connect \B \sdram_bankmachine2_cmd_ready
- connect \Y $and$ls180.v:2255$196_Y
+ connect \Y $and$ls180.v:2268$197_Y
end
- attribute \src "ls180.v:2255.44-2255.135"
- cell $and $and$ls180.v:2255$197
+ attribute \src "ls180.v:2268.44-2268.135"
+ cell $and $and$ls180.v:2268$198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2255$196_Y
+ connect \A $and$ls180.v:2268$197_Y
connect \B \sdram_bankmachine2_row_open
- connect \Y $and$ls180.v:2255$197_Y
+ connect \Y $and$ls180.v:2268$198_Y
end
- attribute \src "ls180.v:2258.7-2258.104"
- cell $and $and$ls180.v:2258$199
+ attribute \src "ls180.v:2271.7-2271.104"
+ cell $and $and$ls180.v:2271$200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $and$ls180.v:2258$199_Y
+ connect \Y $and$ls180.v:2271$200_Y
end
- attribute \src "ls180.v:2287.61-2287.226"
- cell $and $and$ls180.v:2287$205
+ attribute \src "ls180.v:2300.61-2300.226"
+ cell $and $and$ls180.v:2300$206
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
- connect \B $or$ls180.v:2287$204_Y
- connect \Y $and$ls180.v:2287$205_Y
+ connect \B $or$ls180.v:2300$205_Y
+ connect \Y $and$ls180.v:2300$206_Y
end
- attribute \src "ls180.v:2288.59-2288.172"
- cell $and $and$ls180.v:2288$206
+ attribute \src "ls180.v:2301.59-2301.172"
+ cell $and $and$ls180.v:2301$207
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable
connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re
- connect \Y $and$ls180.v:2288$206_Y
+ connect \Y $and$ls180.v:2301$207_Y
end
- attribute \src "ls180.v:2312.9-2312.76"
- cell $and $and$ls180.v:2312$212
+ attribute \src "ls180.v:2325.9-2325.76"
+ cell $and $and$ls180.v:2325$213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_twtpcon_ready
connect \B \sdram_bankmachine2_trascon_ready
- connect \Y $and$ls180.v:2312$212_Y
+ connect \Y $and$ls180.v:2325$213_Y
end
- attribute \src "ls180.v:2324.9-2324.76"
- cell $and $and$ls180.v:2324$213
+ attribute \src "ls180.v:2337.9-2337.76"
+ cell $and $and$ls180.v:2337$214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_twtpcon_ready
connect \B \sdram_bankmachine2_trascon_ready
- connect \Y $and$ls180.v:2324$213_Y
+ connect \Y $and$ls180.v:2337$214_Y
end
- attribute \src "ls180.v:2374.13-2374.77"
- cell $and $and$ls180.v:2374$215
+ attribute \src "ls180.v:2387.13-2387.77"
+ cell $and $and$ls180.v:2387$216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_ready
connect \B \sdram_bankmachine2_auto_precharge
- connect \Y $and$ls180.v:2374$215_Y
+ connect \Y $and$ls180.v:2387$216_Y
end
- attribute \src "ls180.v:2410.45-2410.104"
- cell $and $and$ls180.v:2410$222
+ attribute \src "ls180.v:2423.45-2423.104"
+ cell $and $and$ls180.v:2423$223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_valid
connect \B \sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:2410$222_Y
+ connect \Y $and$ls180.v:2423$223_Y
end
- attribute \src "ls180.v:2410.44-2410.147"
- cell $and $and$ls180.v:2410$223
+ attribute \src "ls180.v:2423.44-2423.147"
+ cell $and $and$ls180.v:2423$224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2410$222_Y
+ connect \A $and$ls180.v:2423$223_Y
connect \B \sdram_bankmachine3_cmd_payload_is_write
- connect \Y $and$ls180.v:2410$223_Y
+ connect \Y $and$ls180.v:2423$224_Y
end
- attribute \src "ls180.v:2411.44-2411.103"
- cell $and $and$ls180.v:2411$224
+ attribute \src "ls180.v:2424.44-2424.103"
+ cell $and $and$ls180.v:2424$225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_valid
connect \B \sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:2411$224_Y
+ connect \Y $and$ls180.v:2424$225_Y
end
- attribute \src "ls180.v:2411.43-2411.134"
- cell $and $and$ls180.v:2411$225
+ attribute \src "ls180.v:2424.43-2424.134"
+ cell $and $and$ls180.v:2424$226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2411$224_Y
+ connect \A $and$ls180.v:2424$225_Y
connect \B \sdram_bankmachine3_row_open
- connect \Y $and$ls180.v:2411$225_Y
+ connect \Y $and$ls180.v:2424$226_Y
end
- attribute \src "ls180.v:2412.45-2412.104"
- cell $and $and$ls180.v:2412$226
+ attribute \src "ls180.v:2425.45-2425.104"
+ cell $and $and$ls180.v:2425$227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_valid
connect \B \sdram_bankmachine3_cmd_ready
- connect \Y $and$ls180.v:2412$226_Y
+ connect \Y $and$ls180.v:2425$227_Y
end
- attribute \src "ls180.v:2412.44-2412.135"
- cell $and $and$ls180.v:2412$227
+ attribute \src "ls180.v:2425.44-2425.135"
+ cell $and $and$ls180.v:2425$228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2412$226_Y
+ connect \A $and$ls180.v:2425$227_Y
connect \B \sdram_bankmachine3_row_open
- connect \Y $and$ls180.v:2412$227_Y
+ connect \Y $and$ls180.v:2425$228_Y
end
- attribute \src "ls180.v:2415.7-2415.104"
- cell $and $and$ls180.v:2415$229
+ attribute \src "ls180.v:2428.7-2428.104"
+ cell $and $and$ls180.v:2428$230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $and$ls180.v:2415$229_Y
+ connect \Y $and$ls180.v:2428$230_Y
end
- attribute \src "ls180.v:2444.61-2444.226"
- cell $and $and$ls180.v:2444$235
+ attribute \src "ls180.v:2457.61-2457.226"
+ cell $and $and$ls180.v:2457$236
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
- connect \B $or$ls180.v:2444$234_Y
- connect \Y $and$ls180.v:2444$235_Y
+ connect \B $or$ls180.v:2457$235_Y
+ connect \Y $and$ls180.v:2457$236_Y
end
- attribute \src "ls180.v:2445.59-2445.172"
- cell $and $and$ls180.v:2445$236
+ attribute \src "ls180.v:2458.59-2458.172"
+ cell $and $and$ls180.v:2458$237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable
connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re
- connect \Y $and$ls180.v:2445$236_Y
+ connect \Y $and$ls180.v:2458$237_Y
end
- attribute \src "ls180.v:2469.9-2469.76"
- cell $and $and$ls180.v:2469$242
+ attribute \src "ls180.v:2482.9-2482.76"
+ cell $and $and$ls180.v:2482$243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_twtpcon_ready
connect \B \sdram_bankmachine3_trascon_ready
- connect \Y $and$ls180.v:2469$242_Y
+ connect \Y $and$ls180.v:2482$243_Y
end
- attribute \src "ls180.v:2481.9-2481.76"
- cell $and $and$ls180.v:2481$243
+ attribute \src "ls180.v:2494.9-2494.76"
+ cell $and $and$ls180.v:2494$244
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_twtpcon_ready
connect \B \sdram_bankmachine3_trascon_ready
- connect \Y $and$ls180.v:2481$243_Y
+ connect \Y $and$ls180.v:2494$244_Y
end
- attribute \src "ls180.v:2531.13-2531.77"
- cell $and $and$ls180.v:2531$245
+ attribute \src "ls180.v:2544.13-2544.77"
+ cell $and $and$ls180.v:2544$246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_ready
connect \B \sdram_bankmachine3_auto_precharge
- connect \Y $and$ls180.v:2531$245_Y
+ connect \Y $and$ls180.v:2544$246_Y
end
- attribute \src "ls180.v:2546.32-2546.87"
- cell $and $and$ls180.v:2546$246
+ attribute \src "ls180.v:2559.32-2559.87"
+ cell $and $and$ls180.v:2559$247
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2546$246_Y
+ connect \Y $and$ls180.v:2559$247_Y
end
- attribute \src "ls180.v:2546.93-2546.163"
- cell $and $and$ls180.v:2546$248
+ attribute \src "ls180.v:2559.93-2559.163"
+ cell $and $and$ls180.v:2559$249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:2546$247_Y
- connect \Y $and$ls180.v:2546$248_Y
+ connect \B $not$ls180.v:2559$248_Y
+ connect \Y $and$ls180.v:2559$249_Y
end
- attribute \src "ls180.v:2546.92-2546.201"
- cell $and $and$ls180.v:2546$250
+ attribute \src "ls180.v:2559.92-2559.201"
+ cell $and $and$ls180.v:2559$251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2546$248_Y
- connect \B $not$ls180.v:2546$249_Y
- connect \Y $and$ls180.v:2546$250_Y
+ connect \A $and$ls180.v:2559$249_Y
+ connect \B $not$ls180.v:2559$250_Y
+ connect \Y $and$ls180.v:2559$251_Y
end
- attribute \src "ls180.v:2546.31-2546.202"
- cell $and $and$ls180.v:2546$251
+ attribute \src "ls180.v:2559.31-2559.202"
+ cell $and $and$ls180.v:2559$252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2546$246_Y
- connect \B $and$ls180.v:2546$250_Y
- connect \Y $and$ls180.v:2546$251_Y
+ connect \A $and$ls180.v:2559$247_Y
+ connect \B $and$ls180.v:2559$251_Y
+ connect \Y $and$ls180.v:2559$252_Y
end
- attribute \src "ls180.v:2547.32-2547.87"
- cell $and $and$ls180.v:2547$252
+ attribute \src "ls180.v:2560.32-2560.87"
+ cell $and $and$ls180.v:2560$253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2547$252_Y
+ connect \Y $and$ls180.v:2560$253_Y
end
- attribute \src "ls180.v:2547.93-2547.163"
- cell $and $and$ls180.v:2547$254
+ attribute \src "ls180.v:2560.93-2560.163"
+ cell $and $and$ls180.v:2560$255
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:2547$253_Y
- connect \Y $and$ls180.v:2547$254_Y
+ connect \B $not$ls180.v:2560$254_Y
+ connect \Y $and$ls180.v:2560$255_Y
end
- attribute \src "ls180.v:2547.92-2547.201"
- cell $and $and$ls180.v:2547$256
+ attribute \src "ls180.v:2560.92-2560.201"
+ cell $and $and$ls180.v:2560$257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2547$254_Y
- connect \B $not$ls180.v:2547$255_Y
- connect \Y $and$ls180.v:2547$256_Y
+ connect \A $and$ls180.v:2560$255_Y
+ connect \B $not$ls180.v:2560$256_Y
+ connect \Y $and$ls180.v:2560$257_Y
end
- attribute \src "ls180.v:2547.31-2547.202"
- cell $and $and$ls180.v:2547$257
+ attribute \src "ls180.v:2560.31-2560.202"
+ cell $and $and$ls180.v:2560$258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2547$252_Y
- connect \B $and$ls180.v:2547$256_Y
- connect \Y $and$ls180.v:2547$257_Y
+ connect \A $and$ls180.v:2560$253_Y
+ connect \B $and$ls180.v:2560$257_Y
+ connect \Y $and$ls180.v:2560$258_Y
end
- attribute \src "ls180.v:2548.29-2548.70"
- cell $and $and$ls180.v:2548$258
+ attribute \src "ls180.v:2561.29-2561.70"
+ cell $and $and$ls180.v:2561$259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_trrdcon_ready
connect \B \sdram_tfawcon_ready
- connect \Y $and$ls180.v:2548$258_Y
+ connect \Y $and$ls180.v:2561$259_Y
end
- attribute \src "ls180.v:2549.32-2549.87"
- cell $and $and$ls180.v:2549$259
+ attribute \src "ls180.v:2562.32-2562.87"
+ cell $and $and$ls180.v:2562$260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2549$259_Y
+ connect \Y $and$ls180.v:2562$260_Y
end
- attribute \src "ls180.v:2549.31-2549.169"
- cell $and $and$ls180.v:2549$261
+ attribute \src "ls180.v:2562.31-2562.169"
+ cell $and $and$ls180.v:2562$262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2549$259_Y
- connect \B $or$ls180.v:2549$260_Y
- connect \Y $and$ls180.v:2549$261_Y
+ connect \A $and$ls180.v:2562$260_Y
+ connect \B $or$ls180.v:2562$261_Y
+ connect \Y $and$ls180.v:2562$262_Y
end
- attribute \src "ls180.v:2551.32-2551.87"
- cell $and $and$ls180.v:2551$262
+ attribute \src "ls180.v:2564.32-2564.87"
+ cell $and $and$ls180.v:2564$263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2551$262_Y
+ connect \Y $and$ls180.v:2564$263_Y
end
- attribute \src "ls180.v:2551.31-2551.128"
- cell $and $and$ls180.v:2551$263
+ attribute \src "ls180.v:2564.31-2564.128"
+ cell $and $and$ls180.v:2564$264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2551$262_Y
+ connect \A $and$ls180.v:2564$263_Y
connect \B \sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:2551$263_Y
+ connect \Y $and$ls180.v:2564$264_Y
end
- attribute \src "ls180.v:2552.35-2552.104"
- cell $and $and$ls180.v:2552$264
+ attribute \src "ls180.v:2565.35-2565.104"
+ cell $and $and$ls180.v:2565$265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_valid
connect \B \sdram_bankmachine0_cmd_payload_is_read
- connect \Y $and$ls180.v:2552$264_Y
+ connect \Y $and$ls180.v:2565$265_Y
end
- attribute \src "ls180.v:2552.109-2552.178"
- cell $and $and$ls180.v:2552$265
+ attribute \src "ls180.v:2565.109-2565.178"
+ cell $and $and$ls180.v:2565$266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_valid
connect \B \sdram_bankmachine1_cmd_payload_is_read
- connect \Y $and$ls180.v:2552$265_Y
+ connect \Y $and$ls180.v:2565$266_Y
end
- attribute \src "ls180.v:2552.184-2552.253"
- cell $and $and$ls180.v:2552$267
+ attribute \src "ls180.v:2565.184-2565.253"
+ cell $and $and$ls180.v:2565$268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_valid
connect \B \sdram_bankmachine2_cmd_payload_is_read
- connect \Y $and$ls180.v:2552$267_Y
+ connect \Y $and$ls180.v:2565$268_Y
end
- attribute \src "ls180.v:2552.259-2552.328"
- cell $and $and$ls180.v:2552$269
+ attribute \src "ls180.v:2565.259-2565.328"
+ cell $and $and$ls180.v:2565$270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_valid
connect \B \sdram_bankmachine3_cmd_payload_is_read
- connect \Y $and$ls180.v:2552$269_Y
+ connect \Y $and$ls180.v:2565$270_Y
end
- attribute \src "ls180.v:2553.36-2553.106"
- cell $and $and$ls180.v:2553$271
+ attribute \src "ls180.v:2566.36-2566.106"
+ cell $and $and$ls180.v:2566$272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_valid
connect \B \sdram_bankmachine0_cmd_payload_is_write
- connect \Y $and$ls180.v:2553$271_Y
+ connect \Y $and$ls180.v:2566$272_Y
end
- attribute \src "ls180.v:2553.111-2553.181"
- cell $and $and$ls180.v:2553$272
+ attribute \src "ls180.v:2566.111-2566.181"
+ cell $and $and$ls180.v:2566$273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_valid
connect \B \sdram_bankmachine1_cmd_payload_is_write
- connect \Y $and$ls180.v:2553$272_Y
+ connect \Y $and$ls180.v:2566$273_Y
end
- attribute \src "ls180.v:2553.187-2553.257"
- cell $and $and$ls180.v:2553$274
+ attribute \src "ls180.v:2566.187-2566.257"
+ cell $and $and$ls180.v:2566$275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_valid
connect \B \sdram_bankmachine2_cmd_payload_is_write
- connect \Y $and$ls180.v:2553$274_Y
+ connect \Y $and$ls180.v:2566$275_Y
end
- attribute \src "ls180.v:2553.263-2553.333"
- cell $and $and$ls180.v:2553$276
+ attribute \src "ls180.v:2566.263-2566.333"
+ cell $and $and$ls180.v:2566$277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_valid
connect \B \sdram_bankmachine3_cmd_payload_is_write
- connect \Y $and$ls180.v:2553$276_Y
+ connect \Y $and$ls180.v:2566$277_Y
end
- attribute \src "ls180.v:2560.33-2560.96"
- cell $and $and$ls180.v:2560$280
+ attribute \src "ls180.v:2573.33-2573.96"
+ cell $and $and$ls180.v:2573$281
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_refresh_gnt
connect \B \sdram_bankmachine1_refresh_gnt
- connect \Y $and$ls180.v:2560$280_Y
+ connect \Y $and$ls180.v:2573$281_Y
end
- attribute \src "ls180.v:2560.32-2560.130"
- cell $and $and$ls180.v:2560$281
+ attribute \src "ls180.v:2573.32-2573.130"
+ cell $and $and$ls180.v:2573$282
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2560$280_Y
+ connect \A $and$ls180.v:2573$281_Y
connect \B \sdram_bankmachine2_refresh_gnt
- connect \Y $and$ls180.v:2560$281_Y
+ connect \Y $and$ls180.v:2573$282_Y
end
- attribute \src "ls180.v:2560.31-2560.164"
- cell $and $and$ls180.v:2560$282
+ attribute \src "ls180.v:2573.31-2573.164"
+ cell $and $and$ls180.v:2573$283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2560$281_Y
+ connect \A $and$ls180.v:2573$282_Y
connect \B \sdram_bankmachine3_refresh_gnt
- connect \Y $and$ls180.v:2560$282_Y
+ connect \Y $and$ls180.v:2573$283_Y
end
- attribute \src "ls180.v:2566.67-2566.133"
- cell $and $and$ls180.v:2566$285
+ attribute \src "ls180.v:2579.67-2579.133"
+ cell $and $and$ls180.v:2579$286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_is_cmd
connect \B \sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:2566$285_Y
+ connect \Y $and$ls180.v:2579$286_Y
end
- attribute \src "ls180.v:2566.142-2566.216"
- cell $and $and$ls180.v:2566$287
+ attribute \src "ls180.v:2579.142-2579.216"
+ cell $and $and$ls180.v:2579$288
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_ras
- connect \B $not$ls180.v:2566$286_Y
- connect \Y $and$ls180.v:2566$287_Y
+ connect \B $not$ls180.v:2579$287_Y
+ connect \Y $and$ls180.v:2579$288_Y
end
- attribute \src "ls180.v:2566.141-2566.256"
- cell $and $and$ls180.v:2566$289
+ attribute \src "ls180.v:2579.141-2579.256"
+ cell $and $and$ls180.v:2579$290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2566$287_Y
- connect \B $not$ls180.v:2566$288_Y
- connect \Y $and$ls180.v:2566$289_Y
+ connect \A $and$ls180.v:2579$288_Y
+ connect \B $not$ls180.v:2579$289_Y
+ connect \Y $and$ls180.v:2579$290_Y
end
- attribute \src "ls180.v:2566.66-2566.293"
- cell $and $and$ls180.v:2566$292
+ attribute \src "ls180.v:2579.66-2579.293"
+ cell $and $and$ls180.v:2579$293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2566$285_Y
- connect \B $or$ls180.v:2566$291_Y
- connect \Y $and$ls180.v:2566$292_Y
+ connect \A $and$ls180.v:2579$286_Y
+ connect \B $or$ls180.v:2579$292_Y
+ connect \Y $and$ls180.v:2579$293_Y
end
- attribute \src "ls180.v:2566.298-2566.445"
- cell $and $and$ls180.v:2566$295
+ attribute \src "ls180.v:2579.298-2579.445"
+ cell $and $and$ls180.v:2579$296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2566$293_Y
- connect \B $eq$ls180.v:2566$294_Y
- connect \Y $and$ls180.v:2566$295_Y
+ connect \A $eq$ls180.v:2579$294_Y
+ connect \B $eq$ls180.v:2579$295_Y
+ connect \Y $and$ls180.v:2579$296_Y
end
- attribute \src "ls180.v:2566.33-2566.447"
- cell $and $and$ls180.v:2566$297
+ attribute \src "ls180.v:2579.33-2579.447"
+ cell $and $and$ls180.v:2579$298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_valid
- connect \B $or$ls180.v:2566$296_Y
- connect \Y $and$ls180.v:2566$297_Y
+ connect \B $or$ls180.v:2579$297_Y
+ connect \Y $and$ls180.v:2579$298_Y
end
- attribute \src "ls180.v:2567.67-2567.133"
- cell $and $and$ls180.v:2567$298
+ attribute \src "ls180.v:2580.67-2580.133"
+ cell $and $and$ls180.v:2580$299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_is_cmd
connect \B \sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:2567$298_Y
+ connect \Y $and$ls180.v:2580$299_Y
end
- attribute \src "ls180.v:2567.142-2567.216"
- cell $and $and$ls180.v:2567$300
+ attribute \src "ls180.v:2580.142-2580.216"
+ cell $and $and$ls180.v:2580$301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_ras
- connect \B $not$ls180.v:2567$299_Y
- connect \Y $and$ls180.v:2567$300_Y
+ connect \B $not$ls180.v:2580$300_Y
+ connect \Y $and$ls180.v:2580$301_Y
end
- attribute \src "ls180.v:2567.141-2567.256"
- cell $and $and$ls180.v:2567$302
+ attribute \src "ls180.v:2580.141-2580.256"
+ cell $and $and$ls180.v:2580$303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2567$300_Y
- connect \B $not$ls180.v:2567$301_Y
- connect \Y $and$ls180.v:2567$302_Y
+ connect \A $and$ls180.v:2580$301_Y
+ connect \B $not$ls180.v:2580$302_Y
+ connect \Y $and$ls180.v:2580$303_Y
end
- attribute \src "ls180.v:2567.66-2567.293"
- cell $and $and$ls180.v:2567$305
+ attribute \src "ls180.v:2580.66-2580.293"
+ cell $and $and$ls180.v:2580$306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2567$298_Y
- connect \B $or$ls180.v:2567$304_Y
- connect \Y $and$ls180.v:2567$305_Y
+ connect \A $and$ls180.v:2580$299_Y
+ connect \B $or$ls180.v:2580$305_Y
+ connect \Y $and$ls180.v:2580$306_Y
end
- attribute \src "ls180.v:2567.298-2567.445"
- cell $and $and$ls180.v:2567$308
+ attribute \src "ls180.v:2580.298-2580.445"
+ cell $and $and$ls180.v:2580$309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2567$306_Y
- connect \B $eq$ls180.v:2567$307_Y
- connect \Y $and$ls180.v:2567$308_Y
+ connect \A $eq$ls180.v:2580$307_Y
+ connect \B $eq$ls180.v:2580$308_Y
+ connect \Y $and$ls180.v:2580$309_Y
end
- attribute \src "ls180.v:2567.33-2567.447"
- cell $and $and$ls180.v:2567$310
+ attribute \src "ls180.v:2580.33-2580.447"
+ cell $and $and$ls180.v:2580$311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_valid
- connect \B $or$ls180.v:2567$309_Y
- connect \Y $and$ls180.v:2567$310_Y
+ connect \B $or$ls180.v:2580$310_Y
+ connect \Y $and$ls180.v:2580$311_Y
end
- attribute \src "ls180.v:2568.67-2568.133"
- cell $and $and$ls180.v:2568$311
+ attribute \src "ls180.v:2581.67-2581.133"
+ cell $and $and$ls180.v:2581$312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_is_cmd
connect \B \sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:2568$311_Y
+ connect \Y $and$ls180.v:2581$312_Y
end
- attribute \src "ls180.v:2568.142-2568.216"
- cell $and $and$ls180.v:2568$313
+ attribute \src "ls180.v:2581.142-2581.216"
+ cell $and $and$ls180.v:2581$314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_ras
- connect \B $not$ls180.v:2568$312_Y
- connect \Y $and$ls180.v:2568$313_Y
+ connect \B $not$ls180.v:2581$313_Y
+ connect \Y $and$ls180.v:2581$314_Y
end
- attribute \src "ls180.v:2568.141-2568.256"
- cell $and $and$ls180.v:2568$315
+ attribute \src "ls180.v:2581.141-2581.256"
+ cell $and $and$ls180.v:2581$316
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2568$313_Y
- connect \B $not$ls180.v:2568$314_Y
- connect \Y $and$ls180.v:2568$315_Y
+ connect \A $and$ls180.v:2581$314_Y
+ connect \B $not$ls180.v:2581$315_Y
+ connect \Y $and$ls180.v:2581$316_Y
end
- attribute \src "ls180.v:2568.66-2568.293"
- cell $and $and$ls180.v:2568$318
+ attribute \src "ls180.v:2581.66-2581.293"
+ cell $and $and$ls180.v:2581$319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2568$311_Y
- connect \B $or$ls180.v:2568$317_Y
- connect \Y $and$ls180.v:2568$318_Y
+ connect \A $and$ls180.v:2581$312_Y
+ connect \B $or$ls180.v:2581$318_Y
+ connect \Y $and$ls180.v:2581$319_Y
end
- attribute \src "ls180.v:2568.298-2568.445"
- cell $and $and$ls180.v:2568$321
+ attribute \src "ls180.v:2581.298-2581.445"
+ cell $and $and$ls180.v:2581$322
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2568$319_Y
- connect \B $eq$ls180.v:2568$320_Y
- connect \Y $and$ls180.v:2568$321_Y
+ connect \A $eq$ls180.v:2581$320_Y
+ connect \B $eq$ls180.v:2581$321_Y
+ connect \Y $and$ls180.v:2581$322_Y
end
- attribute \src "ls180.v:2568.33-2568.447"
- cell $and $and$ls180.v:2568$323
+ attribute \src "ls180.v:2581.33-2581.447"
+ cell $and $and$ls180.v:2581$324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_valid
- connect \B $or$ls180.v:2568$322_Y
- connect \Y $and$ls180.v:2568$323_Y
+ connect \B $or$ls180.v:2581$323_Y
+ connect \Y $and$ls180.v:2581$324_Y
end
- attribute \src "ls180.v:2569.67-2569.133"
- cell $and $and$ls180.v:2569$324
+ attribute \src "ls180.v:2582.67-2582.133"
+ cell $and $and$ls180.v:2582$325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_is_cmd
connect \B \sdram_choose_cmd_want_cmds
- connect \Y $and$ls180.v:2569$324_Y
+ connect \Y $and$ls180.v:2582$325_Y
end
- attribute \src "ls180.v:2569.142-2569.216"
- cell $and $and$ls180.v:2569$326
+ attribute \src "ls180.v:2582.142-2582.216"
+ cell $and $and$ls180.v:2582$327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_ras
- connect \B $not$ls180.v:2569$325_Y
- connect \Y $and$ls180.v:2569$326_Y
+ connect \B $not$ls180.v:2582$326_Y
+ connect \Y $and$ls180.v:2582$327_Y
end
- attribute \src "ls180.v:2569.141-2569.256"
- cell $and $and$ls180.v:2569$328
+ attribute \src "ls180.v:2582.141-2582.256"
+ cell $and $and$ls180.v:2582$329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2569$326_Y
- connect \B $not$ls180.v:2569$327_Y
- connect \Y $and$ls180.v:2569$328_Y
+ connect \A $and$ls180.v:2582$327_Y
+ connect \B $not$ls180.v:2582$328_Y
+ connect \Y $and$ls180.v:2582$329_Y
end
- attribute \src "ls180.v:2569.66-2569.293"
- cell $and $and$ls180.v:2569$331
+ attribute \src "ls180.v:2582.66-2582.293"
+ cell $and $and$ls180.v:2582$332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2569$324_Y
- connect \B $or$ls180.v:2569$330_Y
- connect \Y $and$ls180.v:2569$331_Y
+ connect \A $and$ls180.v:2582$325_Y
+ connect \B $or$ls180.v:2582$331_Y
+ connect \Y $and$ls180.v:2582$332_Y
end
- attribute \src "ls180.v:2569.298-2569.445"
- cell $and $and$ls180.v:2569$334
+ attribute \src "ls180.v:2582.298-2582.445"
+ cell $and $and$ls180.v:2582$335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2569$332_Y
- connect \B $eq$ls180.v:2569$333_Y
- connect \Y $and$ls180.v:2569$334_Y
+ connect \A $eq$ls180.v:2582$333_Y
+ connect \B $eq$ls180.v:2582$334_Y
+ connect \Y $and$ls180.v:2582$335_Y
end
- attribute \src "ls180.v:2569.33-2569.447"
- cell $and $and$ls180.v:2569$336
+ attribute \src "ls180.v:2582.33-2582.447"
+ cell $and $and$ls180.v:2582$337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_valid
- connect \B $or$ls180.v:2569$335_Y
- connect \Y $and$ls180.v:2569$336_Y
+ connect \B $or$ls180.v:2582$336_Y
+ connect \Y $and$ls180.v:2582$337_Y
end
- attribute \src "ls180.v:2599.67-2599.133"
- cell $and $and$ls180.v:2599$343
+ attribute \src "ls180.v:2612.67-2612.133"
+ cell $and $and$ls180.v:2612$344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_is_cmd
connect \B \sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:2599$343_Y
+ connect \Y $and$ls180.v:2612$344_Y
end
- attribute \src "ls180.v:2599.142-2599.216"
- cell $and $and$ls180.v:2599$345
+ attribute \src "ls180.v:2612.142-2612.216"
+ cell $and $and$ls180.v:2612$346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_ras
- connect \B $not$ls180.v:2599$344_Y
- connect \Y $and$ls180.v:2599$345_Y
+ connect \B $not$ls180.v:2612$345_Y
+ connect \Y $and$ls180.v:2612$346_Y
end
- attribute \src "ls180.v:2599.141-2599.256"
- cell $and $and$ls180.v:2599$347
+ attribute \src "ls180.v:2612.141-2612.256"
+ cell $and $and$ls180.v:2612$348
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2599$345_Y
- connect \B $not$ls180.v:2599$346_Y
- connect \Y $and$ls180.v:2599$347_Y
+ connect \A $and$ls180.v:2612$346_Y
+ connect \B $not$ls180.v:2612$347_Y
+ connect \Y $and$ls180.v:2612$348_Y
end
- attribute \src "ls180.v:2599.66-2599.293"
- cell $and $and$ls180.v:2599$350
+ attribute \src "ls180.v:2612.66-2612.293"
+ cell $and $and$ls180.v:2612$351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2599$343_Y
- connect \B $or$ls180.v:2599$349_Y
- connect \Y $and$ls180.v:2599$350_Y
+ connect \A $and$ls180.v:2612$344_Y
+ connect \B $or$ls180.v:2612$350_Y
+ connect \Y $and$ls180.v:2612$351_Y
end
- attribute \src "ls180.v:2599.298-2599.445"
- cell $and $and$ls180.v:2599$353
+ attribute \src "ls180.v:2612.298-2612.445"
+ cell $and $and$ls180.v:2612$354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2599$351_Y
- connect \B $eq$ls180.v:2599$352_Y
- connect \Y $and$ls180.v:2599$353_Y
+ connect \A $eq$ls180.v:2612$352_Y
+ connect \B $eq$ls180.v:2612$353_Y
+ connect \Y $and$ls180.v:2612$354_Y
end
- attribute \src "ls180.v:2599.33-2599.447"
- cell $and $and$ls180.v:2599$355
+ attribute \src "ls180.v:2612.33-2612.447"
+ cell $and $and$ls180.v:2612$356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_valid
- connect \B $or$ls180.v:2599$354_Y
- connect \Y $and$ls180.v:2599$355_Y
+ connect \B $or$ls180.v:2612$355_Y
+ connect \Y $and$ls180.v:2612$356_Y
end
- attribute \src "ls180.v:2600.67-2600.133"
- cell $and $and$ls180.v:2600$356
+ attribute \src "ls180.v:2613.67-2613.133"
+ cell $and $and$ls180.v:2613$357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_is_cmd
connect \B \sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:2600$356_Y
+ connect \Y $and$ls180.v:2613$357_Y
end
- attribute \src "ls180.v:2600.142-2600.216"
- cell $and $and$ls180.v:2600$358
+ attribute \src "ls180.v:2613.142-2613.216"
+ cell $and $and$ls180.v:2613$359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_ras
- connect \B $not$ls180.v:2600$357_Y
- connect \Y $and$ls180.v:2600$358_Y
+ connect \B $not$ls180.v:2613$358_Y
+ connect \Y $and$ls180.v:2613$359_Y
end
- attribute \src "ls180.v:2600.141-2600.256"
- cell $and $and$ls180.v:2600$360
+ attribute \src "ls180.v:2613.141-2613.256"
+ cell $and $and$ls180.v:2613$361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2600$358_Y
- connect \B $not$ls180.v:2600$359_Y
- connect \Y $and$ls180.v:2600$360_Y
+ connect \A $and$ls180.v:2613$359_Y
+ connect \B $not$ls180.v:2613$360_Y
+ connect \Y $and$ls180.v:2613$361_Y
end
- attribute \src "ls180.v:2600.66-2600.293"
- cell $and $and$ls180.v:2600$363
+ attribute \src "ls180.v:2613.66-2613.293"
+ cell $and $and$ls180.v:2613$364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2600$356_Y
- connect \B $or$ls180.v:2600$362_Y
- connect \Y $and$ls180.v:2600$363_Y
+ connect \A $and$ls180.v:2613$357_Y
+ connect \B $or$ls180.v:2613$363_Y
+ connect \Y $and$ls180.v:2613$364_Y
end
- attribute \src "ls180.v:2600.298-2600.445"
- cell $and $and$ls180.v:2600$366
+ attribute \src "ls180.v:2613.298-2613.445"
+ cell $and $and$ls180.v:2613$367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2600$364_Y
- connect \B $eq$ls180.v:2600$365_Y
- connect \Y $and$ls180.v:2600$366_Y
+ connect \A $eq$ls180.v:2613$365_Y
+ connect \B $eq$ls180.v:2613$366_Y
+ connect \Y $and$ls180.v:2613$367_Y
end
- attribute \src "ls180.v:2600.33-2600.447"
- cell $and $and$ls180.v:2600$368
+ attribute \src "ls180.v:2613.33-2613.447"
+ cell $and $and$ls180.v:2613$369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_valid
- connect \B $or$ls180.v:2600$367_Y
- connect \Y $and$ls180.v:2600$368_Y
+ connect \B $or$ls180.v:2613$368_Y
+ connect \Y $and$ls180.v:2613$369_Y
end
- attribute \src "ls180.v:2601.67-2601.133"
- cell $and $and$ls180.v:2601$369
+ attribute \src "ls180.v:2614.67-2614.133"
+ cell $and $and$ls180.v:2614$370
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_is_cmd
connect \B \sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:2601$369_Y
+ connect \Y $and$ls180.v:2614$370_Y
end
- attribute \src "ls180.v:2601.142-2601.216"
- cell $and $and$ls180.v:2601$371
+ attribute \src "ls180.v:2614.142-2614.216"
+ cell $and $and$ls180.v:2614$372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_ras
- connect \B $not$ls180.v:2601$370_Y
- connect \Y $and$ls180.v:2601$371_Y
+ connect \B $not$ls180.v:2614$371_Y
+ connect \Y $and$ls180.v:2614$372_Y
end
- attribute \src "ls180.v:2601.141-2601.256"
- cell $and $and$ls180.v:2601$373
+ attribute \src "ls180.v:2614.141-2614.256"
+ cell $and $and$ls180.v:2614$374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2601$371_Y
- connect \B $not$ls180.v:2601$372_Y
- connect \Y $and$ls180.v:2601$373_Y
+ connect \A $and$ls180.v:2614$372_Y
+ connect \B $not$ls180.v:2614$373_Y
+ connect \Y $and$ls180.v:2614$374_Y
end
- attribute \src "ls180.v:2601.66-2601.293"
- cell $and $and$ls180.v:2601$376
+ attribute \src "ls180.v:2614.66-2614.293"
+ cell $and $and$ls180.v:2614$377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2601$369_Y
- connect \B $or$ls180.v:2601$375_Y
- connect \Y $and$ls180.v:2601$376_Y
+ connect \A $and$ls180.v:2614$370_Y
+ connect \B $or$ls180.v:2614$376_Y
+ connect \Y $and$ls180.v:2614$377_Y
end
- attribute \src "ls180.v:2601.298-2601.445"
- cell $and $and$ls180.v:2601$379
+ attribute \src "ls180.v:2614.298-2614.445"
+ cell $and $and$ls180.v:2614$380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2601$377_Y
- connect \B $eq$ls180.v:2601$378_Y
- connect \Y $and$ls180.v:2601$379_Y
+ connect \A $eq$ls180.v:2614$378_Y
+ connect \B $eq$ls180.v:2614$379_Y
+ connect \Y $and$ls180.v:2614$380_Y
end
- attribute \src "ls180.v:2601.33-2601.447"
- cell $and $and$ls180.v:2601$381
+ attribute \src "ls180.v:2614.33-2614.447"
+ cell $and $and$ls180.v:2614$382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_valid
- connect \B $or$ls180.v:2601$380_Y
- connect \Y $and$ls180.v:2601$381_Y
+ connect \B $or$ls180.v:2614$381_Y
+ connect \Y $and$ls180.v:2614$382_Y
end
- attribute \src "ls180.v:2602.67-2602.133"
- cell $and $and$ls180.v:2602$382
+ attribute \src "ls180.v:2615.67-2615.133"
+ cell $and $and$ls180.v:2615$383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_is_cmd
connect \B \sdram_choose_req_want_cmds
- connect \Y $and$ls180.v:2602$382_Y
+ connect \Y $and$ls180.v:2615$383_Y
end
- attribute \src "ls180.v:2602.142-2602.216"
- cell $and $and$ls180.v:2602$384
+ attribute \src "ls180.v:2615.142-2615.216"
+ cell $and $and$ls180.v:2615$385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_ras
- connect \B $not$ls180.v:2602$383_Y
- connect \Y $and$ls180.v:2602$384_Y
+ connect \B $not$ls180.v:2615$384_Y
+ connect \Y $and$ls180.v:2615$385_Y
end
- attribute \src "ls180.v:2602.141-2602.256"
- cell $and $and$ls180.v:2602$386
+ attribute \src "ls180.v:2615.141-2615.256"
+ cell $and $and$ls180.v:2615$387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2602$384_Y
- connect \B $not$ls180.v:2602$385_Y
- connect \Y $and$ls180.v:2602$386_Y
+ connect \A $and$ls180.v:2615$385_Y
+ connect \B $not$ls180.v:2615$386_Y
+ connect \Y $and$ls180.v:2615$387_Y
end
- attribute \src "ls180.v:2602.66-2602.293"
- cell $and $and$ls180.v:2602$389
+ attribute \src "ls180.v:2615.66-2615.293"
+ cell $and $and$ls180.v:2615$390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2602$382_Y
- connect \B $or$ls180.v:2602$388_Y
- connect \Y $and$ls180.v:2602$389_Y
+ connect \A $and$ls180.v:2615$383_Y
+ connect \B $or$ls180.v:2615$389_Y
+ connect \Y $and$ls180.v:2615$390_Y
end
- attribute \src "ls180.v:2602.298-2602.445"
- cell $and $and$ls180.v:2602$392
+ attribute \src "ls180.v:2615.298-2615.445"
+ cell $and $and$ls180.v:2615$393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2602$390_Y
- connect \B $eq$ls180.v:2602$391_Y
- connect \Y $and$ls180.v:2602$392_Y
+ connect \A $eq$ls180.v:2615$391_Y
+ connect \B $eq$ls180.v:2615$392_Y
+ connect \Y $and$ls180.v:2615$393_Y
end
- attribute \src "ls180.v:2602.33-2602.447"
- cell $and $and$ls180.v:2602$394
+ attribute \src "ls180.v:2615.33-2615.447"
+ cell $and $and$ls180.v:2615$395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_valid
- connect \B $or$ls180.v:2602$393_Y
- connect \Y $and$ls180.v:2602$394_Y
+ connect \B $or$ls180.v:2615$394_Y
+ connect \Y $and$ls180.v:2615$395_Y
end
- attribute \src "ls180.v:2631.8-2631.63"
- cell $and $and$ls180.v:2631$399
+ attribute \src "ls180.v:2644.8-2644.63"
+ cell $and $and$ls180.v:2644$400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_cmd_valid
connect \B \sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:2631$399_Y
+ connect \Y $and$ls180.v:2644$400_Y
end
- attribute \src "ls180.v:2631.7-2631.99"
- cell $and $and$ls180.v:2631$401
+ attribute \src "ls180.v:2644.7-2644.99"
+ cell $and $and$ls180.v:2644$402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2631$399_Y
- connect \B $eq$ls180.v:2631$400_Y
- connect \Y $and$ls180.v:2631$401_Y
+ connect \A $and$ls180.v:2644$400_Y
+ connect \B $eq$ls180.v:2644$401_Y
+ connect \Y $and$ls180.v:2644$402_Y
end
- attribute \src "ls180.v:2634.8-2634.63"
- cell $and $and$ls180.v:2634$402
+ attribute \src "ls180.v:2647.8-2647.63"
+ cell $and $and$ls180.v:2647$403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2634$402_Y
+ connect \Y $and$ls180.v:2647$403_Y
end
- attribute \src "ls180.v:2634.7-2634.99"
- cell $and $and$ls180.v:2634$404
+ attribute \src "ls180.v:2647.7-2647.99"
+ cell $and $and$ls180.v:2647$405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2634$402_Y
- connect \B $eq$ls180.v:2634$403_Y
- connect \Y $and$ls180.v:2634$404_Y
+ connect \A $and$ls180.v:2647$403_Y
+ connect \B $eq$ls180.v:2647$404_Y
+ connect \Y $and$ls180.v:2647$405_Y
end
- attribute \src "ls180.v:2640.8-2640.63"
- cell $and $and$ls180.v:2640$406
+ attribute \src "ls180.v:2653.8-2653.63"
+ cell $and $and$ls180.v:2653$407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_cmd_valid
connect \B \sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:2640$406_Y
+ connect \Y $and$ls180.v:2653$407_Y
end
- attribute \src "ls180.v:2640.7-2640.99"
- cell $and $and$ls180.v:2640$408
+ attribute \src "ls180.v:2653.7-2653.99"
+ cell $and $and$ls180.v:2653$409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2640$406_Y
- connect \B $eq$ls180.v:2640$407_Y
- connect \Y $and$ls180.v:2640$408_Y
+ connect \A $and$ls180.v:2653$407_Y
+ connect \B $eq$ls180.v:2653$408_Y
+ connect \Y $and$ls180.v:2653$409_Y
end
- attribute \src "ls180.v:2643.8-2643.63"
- cell $and $and$ls180.v:2643$409
+ attribute \src "ls180.v:2656.8-2656.63"
+ cell $and $and$ls180.v:2656$410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2643$409_Y
+ connect \Y $and$ls180.v:2656$410_Y
end
- attribute \src "ls180.v:2643.7-2643.99"
- cell $and $and$ls180.v:2643$411
+ attribute \src "ls180.v:2656.7-2656.99"
+ cell $and $and$ls180.v:2656$412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2643$409_Y
- connect \B $eq$ls180.v:2643$410_Y
- connect \Y $and$ls180.v:2643$411_Y
+ connect \A $and$ls180.v:2656$410_Y
+ connect \B $eq$ls180.v:2656$411_Y
+ connect \Y $and$ls180.v:2656$412_Y
end
- attribute \src "ls180.v:2649.8-2649.63"
- cell $and $and$ls180.v:2649$413
+ attribute \src "ls180.v:2662.8-2662.63"
+ cell $and $and$ls180.v:2662$414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_cmd_valid
connect \B \sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:2649$413_Y
+ connect \Y $and$ls180.v:2662$414_Y
end
- attribute \src "ls180.v:2649.7-2649.99"
- cell $and $and$ls180.v:2649$415
+ attribute \src "ls180.v:2662.7-2662.99"
+ cell $and $and$ls180.v:2662$416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2649$413_Y
- connect \B $eq$ls180.v:2649$414_Y
- connect \Y $and$ls180.v:2649$415_Y
+ connect \A $and$ls180.v:2662$414_Y
+ connect \B $eq$ls180.v:2662$415_Y
+ connect \Y $and$ls180.v:2662$416_Y
end
- attribute \src "ls180.v:2652.8-2652.63"
- cell $and $and$ls180.v:2652$416
+ attribute \src "ls180.v:2665.8-2665.63"
+ cell $and $and$ls180.v:2665$417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2652$416_Y
+ connect \Y $and$ls180.v:2665$417_Y
end
- attribute \src "ls180.v:2652.7-2652.99"
- cell $and $and$ls180.v:2652$418
+ attribute \src "ls180.v:2665.7-2665.99"
+ cell $and $and$ls180.v:2665$419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2652$416_Y
- connect \B $eq$ls180.v:2652$417_Y
- connect \Y $and$ls180.v:2652$418_Y
+ connect \A $and$ls180.v:2665$417_Y
+ connect \B $eq$ls180.v:2665$418_Y
+ connect \Y $and$ls180.v:2665$419_Y
end
- attribute \src "ls180.v:2658.8-2658.63"
- cell $and $and$ls180.v:2658$420
+ attribute \src "ls180.v:2671.8-2671.63"
+ cell $and $and$ls180.v:2671$421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_cmd_valid
connect \B \sdram_choose_cmd_cmd_ready
- connect \Y $and$ls180.v:2658$420_Y
+ connect \Y $and$ls180.v:2671$421_Y
end
- attribute \src "ls180.v:2658.7-2658.99"
- cell $and $and$ls180.v:2658$422
+ attribute \src "ls180.v:2671.7-2671.99"
+ cell $and $and$ls180.v:2671$423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2658$420_Y
- connect \B $eq$ls180.v:2658$421_Y
- connect \Y $and$ls180.v:2658$422_Y
+ connect \A $and$ls180.v:2671$421_Y
+ connect \B $eq$ls180.v:2671$422_Y
+ connect \Y $and$ls180.v:2671$423_Y
end
- attribute \src "ls180.v:2661.8-2661.63"
- cell $and $and$ls180.v:2661$423
+ attribute \src "ls180.v:2674.8-2674.63"
+ cell $and $and$ls180.v:2674$424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:2661$423_Y
+ connect \Y $and$ls180.v:2674$424_Y
end
- attribute \src "ls180.v:2661.7-2661.99"
- cell $and $and$ls180.v:2661$425
+ attribute \src "ls180.v:2674.7-2674.99"
+ cell $and $and$ls180.v:2674$426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2661$423_Y
- connect \B $eq$ls180.v:2661$424_Y
- connect \Y $and$ls180.v:2661$425_Y
+ connect \A $and$ls180.v:2674$424_Y
+ connect \B $eq$ls180.v:2674$425_Y
+ connect \Y $and$ls180.v:2674$426_Y
end
- attribute \src "ls180.v:2686.61-2686.131"
- cell $and $and$ls180.v:2686$430
+ attribute \src "ls180.v:2699.61-2699.131"
+ cell $and $and$ls180.v:2699$431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:2686$429_Y
- connect \Y $and$ls180.v:2686$430_Y
+ connect \B $not$ls180.v:2699$430_Y
+ connect \Y $and$ls180.v:2699$431_Y
end
- attribute \src "ls180.v:2686.60-2686.169"
- cell $and $and$ls180.v:2686$432
+ attribute \src "ls180.v:2699.60-2699.169"
+ cell $and $and$ls180.v:2699$433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2686$430_Y
- connect \B $not$ls180.v:2686$431_Y
- connect \Y $and$ls180.v:2686$432_Y
+ connect \A $and$ls180.v:2699$431_Y
+ connect \B $not$ls180.v:2699$432_Y
+ connect \Y $and$ls180.v:2699$433_Y
end
- attribute \src "ls180.v:2686.36-2686.192"
- cell $and $and$ls180.v:2686$435
+ attribute \src "ls180.v:2699.36-2699.192"
+ cell $and $and$ls180.v:2699$436
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_cas_allowed
- connect \B $or$ls180.v:2686$434_Y
- connect \Y $and$ls180.v:2686$435_Y
+ connect \B $or$ls180.v:2699$435_Y
+ connect \Y $and$ls180.v:2699$436_Y
end
- attribute \src "ls180.v:2724.61-2724.131"
- cell $and $and$ls180.v:2724$439
+ attribute \src "ls180.v:2737.61-2737.131"
+ cell $and $and$ls180.v:2737$440
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_ras
- connect \B $not$ls180.v:2724$438_Y
- connect \Y $and$ls180.v:2724$439_Y
+ connect \B $not$ls180.v:2737$439_Y
+ connect \Y $and$ls180.v:2737$440_Y
end
- attribute \src "ls180.v:2724.60-2724.169"
- cell $and $and$ls180.v:2724$441
+ attribute \src "ls180.v:2737.60-2737.169"
+ cell $and $and$ls180.v:2737$442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2724$439_Y
- connect \B $not$ls180.v:2724$440_Y
- connect \Y $and$ls180.v:2724$441_Y
+ connect \A $and$ls180.v:2737$440_Y
+ connect \B $not$ls180.v:2737$441_Y
+ connect \Y $and$ls180.v:2737$442_Y
end
- attribute \src "ls180.v:2724.36-2724.192"
- cell $and $and$ls180.v:2724$444
+ attribute \src "ls180.v:2737.36-2737.192"
+ cell $and $and$ls180.v:2737$445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_cas_allowed
- connect \B $or$ls180.v:2724$443_Y
- connect \Y $and$ls180.v:2724$444_Y
+ connect \B $or$ls180.v:2737$444_Y
+ connect \Y $and$ls180.v:2737$445_Y
end
- attribute \src "ls180.v:2742.115-2742.184"
- cell $and $and$ls180.v:2742$449
+ attribute \src "ls180.v:2755.115-2755.184"
+ cell $and $and$ls180.v:2755$450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:2742$448_Y
- connect \Y $and$ls180.v:2742$449_Y
+ connect \B $eq$ls180.v:2755$449_Y
+ connect \Y $and$ls180.v:2755$450_Y
end
- attribute \src "ls180.v:2742.190-2742.259"
- cell $and $and$ls180.v:2742$452
+ attribute \src "ls180.v:2755.190-2755.259"
+ cell $and $and$ls180.v:2755$453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:2742$451_Y
- connect \Y $and$ls180.v:2742$452_Y
+ connect \B $eq$ls180.v:2755$452_Y
+ connect \Y $and$ls180.v:2755$453_Y
end
- attribute \src "ls180.v:2742.265-2742.334"
- cell $and $and$ls180.v:2742$455
+ attribute \src "ls180.v:2755.265-2755.334"
+ cell $and $and$ls180.v:2755$456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:2742$454_Y
- connect \Y $and$ls180.v:2742$455_Y
+ connect \B $eq$ls180.v:2755$455_Y
+ connect \Y $and$ls180.v:2755$456_Y
end
- attribute \src "ls180.v:2742.46-2742.337"
- cell $and $and$ls180.v:2742$458
+ attribute \src "ls180.v:2755.46-2755.337"
+ cell $and $and$ls180.v:2755$459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2742$447_Y
- connect \B $not$ls180.v:2742$457_Y
- connect \Y $and$ls180.v:2742$458_Y
+ connect \A $eq$ls180.v:2755$448_Y
+ connect \B $not$ls180.v:2755$458_Y
+ connect \Y $and$ls180.v:2755$459_Y
end
- attribute \src "ls180.v:2742.45-2742.355"
- cell $and $and$ls180.v:2742$459
+ attribute \src "ls180.v:2755.45-2755.355"
+ cell $and $and$ls180.v:2755$460
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2742$458_Y
+ connect \A $and$ls180.v:2755$459_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:2742$459_Y
+ connect \Y $and$ls180.v:2755$460_Y
end
- attribute \src "ls180.v:2743.39-2743.101"
- cell $and $and$ls180.v:2743$462
+ attribute \src "ls180.v:2756.39-2756.101"
+ cell $and $and$ls180.v:2756$463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2743$460_Y
- connect \B $not$ls180.v:2743$461_Y
- connect \Y $and$ls180.v:2743$462_Y
+ connect \A $not$ls180.v:2756$461_Y
+ connect \B $not$ls180.v:2756$462_Y
+ connect \Y $and$ls180.v:2756$463_Y
end
- attribute \src "ls180.v:2747.115-2747.184"
- cell $and $and$ls180.v:2747$465
+ attribute \src "ls180.v:2760.115-2760.184"
+ cell $and $and$ls180.v:2760$466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:2747$464_Y
- connect \Y $and$ls180.v:2747$465_Y
+ connect \B $eq$ls180.v:2760$465_Y
+ connect \Y $and$ls180.v:2760$466_Y
end
- attribute \src "ls180.v:2747.190-2747.259"
- cell $and $and$ls180.v:2747$468
+ attribute \src "ls180.v:2760.190-2760.259"
+ cell $and $and$ls180.v:2760$469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:2747$467_Y
- connect \Y $and$ls180.v:2747$468_Y
+ connect \B $eq$ls180.v:2760$468_Y
+ connect \Y $and$ls180.v:2760$469_Y
end
- attribute \src "ls180.v:2747.265-2747.334"
- cell $and $and$ls180.v:2747$471
+ attribute \src "ls180.v:2760.265-2760.334"
+ cell $and $and$ls180.v:2760$472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:2747$470_Y
- connect \Y $and$ls180.v:2747$471_Y
+ connect \B $eq$ls180.v:2760$471_Y
+ connect \Y $and$ls180.v:2760$472_Y
end
- attribute \src "ls180.v:2747.46-2747.337"
- cell $and $and$ls180.v:2747$474
+ attribute \src "ls180.v:2760.46-2760.337"
+ cell $and $and$ls180.v:2760$475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2747$463_Y
- connect \B $not$ls180.v:2747$473_Y
- connect \Y $and$ls180.v:2747$474_Y
+ connect \A $eq$ls180.v:2760$464_Y
+ connect \B $not$ls180.v:2760$474_Y
+ connect \Y $and$ls180.v:2760$475_Y
end
- attribute \src "ls180.v:2747.45-2747.355"
- cell $and $and$ls180.v:2747$475
+ attribute \src "ls180.v:2760.45-2760.355"
+ cell $and $and$ls180.v:2760$476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2747$474_Y
+ connect \A $and$ls180.v:2760$475_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:2747$475_Y
+ connect \Y $and$ls180.v:2760$476_Y
end
- attribute \src "ls180.v:2748.39-2748.101"
- cell $and $and$ls180.v:2748$478
+ attribute \src "ls180.v:2761.39-2761.101"
+ cell $and $and$ls180.v:2761$479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2748$476_Y
- connect \B $not$ls180.v:2748$477_Y
- connect \Y $and$ls180.v:2748$478_Y
+ connect \A $not$ls180.v:2761$477_Y
+ connect \B $not$ls180.v:2761$478_Y
+ connect \Y $and$ls180.v:2761$479_Y
end
- attribute \src "ls180.v:2752.115-2752.184"
- cell $and $and$ls180.v:2752$481
+ attribute \src "ls180.v:2765.115-2765.184"
+ cell $and $and$ls180.v:2765$482
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:2752$480_Y
- connect \Y $and$ls180.v:2752$481_Y
+ connect \B $eq$ls180.v:2765$481_Y
+ connect \Y $and$ls180.v:2765$482_Y
end
- attribute \src "ls180.v:2752.190-2752.259"
- cell $and $and$ls180.v:2752$484
+ attribute \src "ls180.v:2765.190-2765.259"
+ cell $and $and$ls180.v:2765$485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:2752$483_Y
- connect \Y $and$ls180.v:2752$484_Y
+ connect \B $eq$ls180.v:2765$484_Y
+ connect \Y $and$ls180.v:2765$485_Y
end
- attribute \src "ls180.v:2752.265-2752.334"
- cell $and $and$ls180.v:2752$487
+ attribute \src "ls180.v:2765.265-2765.334"
+ cell $and $and$ls180.v:2765$488
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:2752$486_Y
- connect \Y $and$ls180.v:2752$487_Y
+ connect \B $eq$ls180.v:2765$487_Y
+ connect \Y $and$ls180.v:2765$488_Y
end
- attribute \src "ls180.v:2752.46-2752.337"
- cell $and $and$ls180.v:2752$490
+ attribute \src "ls180.v:2765.46-2765.337"
+ cell $and $and$ls180.v:2765$491
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2752$479_Y
- connect \B $not$ls180.v:2752$489_Y
- connect \Y $and$ls180.v:2752$490_Y
+ connect \A $eq$ls180.v:2765$480_Y
+ connect \B $not$ls180.v:2765$490_Y
+ connect \Y $and$ls180.v:2765$491_Y
end
- attribute \src "ls180.v:2752.45-2752.355"
- cell $and $and$ls180.v:2752$491
+ attribute \src "ls180.v:2765.45-2765.355"
+ cell $and $and$ls180.v:2765$492
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2752$490_Y
+ connect \A $and$ls180.v:2765$491_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:2752$491_Y
+ connect \Y $and$ls180.v:2765$492_Y
end
- attribute \src "ls180.v:2753.39-2753.101"
- cell $and $and$ls180.v:2753$494
+ attribute \src "ls180.v:2766.39-2766.101"
+ cell $and $and$ls180.v:2766$495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2753$492_Y
- connect \B $not$ls180.v:2753$493_Y
- connect \Y $and$ls180.v:2753$494_Y
+ connect \A $not$ls180.v:2766$493_Y
+ connect \B $not$ls180.v:2766$494_Y
+ connect \Y $and$ls180.v:2766$495_Y
end
- attribute \src "ls180.v:2757.115-2757.184"
- cell $and $and$ls180.v:2757$497
+ attribute \src "ls180.v:2770.115-2770.184"
+ cell $and $and$ls180.v:2770$498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:2757$496_Y
- connect \Y $and$ls180.v:2757$497_Y
+ connect \B $eq$ls180.v:2770$497_Y
+ connect \Y $and$ls180.v:2770$498_Y
end
- attribute \src "ls180.v:2757.190-2757.259"
- cell $and $and$ls180.v:2757$500
+ attribute \src "ls180.v:2770.190-2770.259"
+ cell $and $and$ls180.v:2770$501
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:2757$499_Y
- connect \Y $and$ls180.v:2757$500_Y
+ connect \B $eq$ls180.v:2770$500_Y
+ connect \Y $and$ls180.v:2770$501_Y
end
- attribute \src "ls180.v:2757.265-2757.334"
- cell $and $and$ls180.v:2757$503
+ attribute \src "ls180.v:2770.265-2770.334"
+ cell $and $and$ls180.v:2770$504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:2757$502_Y
- connect \Y $and$ls180.v:2757$503_Y
+ connect \B $eq$ls180.v:2770$503_Y
+ connect \Y $and$ls180.v:2770$504_Y
end
- attribute \src "ls180.v:2757.46-2757.337"
- cell $and $and$ls180.v:2757$506
+ attribute \src "ls180.v:2770.46-2770.337"
+ cell $and $and$ls180.v:2770$507
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2757$495_Y
- connect \B $not$ls180.v:2757$505_Y
- connect \Y $and$ls180.v:2757$506_Y
+ connect \A $eq$ls180.v:2770$496_Y
+ connect \B $not$ls180.v:2770$506_Y
+ connect \Y $and$ls180.v:2770$507_Y
end
- attribute \src "ls180.v:2757.45-2757.355"
- cell $and $and$ls180.v:2757$507
+ attribute \src "ls180.v:2770.45-2770.355"
+ cell $and $and$ls180.v:2770$508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2757$506_Y
+ connect \A $and$ls180.v:2770$507_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:2757$507_Y
+ connect \Y $and$ls180.v:2770$508_Y
end
- attribute \src "ls180.v:2758.39-2758.101"
- cell $and $and$ls180.v:2758$510
+ attribute \src "ls180.v:2771.39-2771.101"
+ cell $and $and$ls180.v:2771$511
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2758$508_Y
- connect \B $not$ls180.v:2758$509_Y
- connect \Y $and$ls180.v:2758$510_Y
+ connect \A $not$ls180.v:2771$509_Y
+ connect \B $not$ls180.v:2771$510_Y
+ connect \Y $and$ls180.v:2771$511_Y
end
- attribute \src "ls180.v:2762.151-2762.220"
- cell $and $and$ls180.v:2762$514
+ attribute \src "ls180.v:2775.151-2775.220"
+ cell $and $and$ls180.v:2775$515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:2762$513_Y
- connect \Y $and$ls180.v:2762$514_Y
+ connect \B $eq$ls180.v:2775$514_Y
+ connect \Y $and$ls180.v:2775$515_Y
end
- attribute \src "ls180.v:2762.226-2762.295"
- cell $and $and$ls180.v:2762$517
+ attribute \src "ls180.v:2775.226-2775.295"
+ cell $and $and$ls180.v:2775$518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:2762$516_Y
- connect \Y $and$ls180.v:2762$517_Y
+ connect \B $eq$ls180.v:2775$517_Y
+ connect \Y $and$ls180.v:2775$518_Y
end
- attribute \src "ls180.v:2762.301-2762.370"
- cell $and $and$ls180.v:2762$520
+ attribute \src "ls180.v:2775.301-2775.370"
+ cell $and $and$ls180.v:2775$521
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:2762$519_Y
- connect \Y $and$ls180.v:2762$520_Y
+ connect \B $eq$ls180.v:2775$520_Y
+ connect \Y $and$ls180.v:2775$521_Y
end
- attribute \src "ls180.v:2762.82-2762.373"
- cell $and $and$ls180.v:2762$523
+ attribute \src "ls180.v:2775.82-2775.373"
+ cell $and $and$ls180.v:2775$524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$512_Y
- connect \B $not$ls180.v:2762$522_Y
- connect \Y $and$ls180.v:2762$523_Y
+ connect \A $eq$ls180.v:2775$513_Y
+ connect \B $not$ls180.v:2775$523_Y
+ connect \Y $and$ls180.v:2775$524_Y
end
- attribute \src "ls180.v:2762.38-2762.374"
- cell $and $and$ls180.v:2762$524
+ attribute \src "ls180.v:2775.38-2775.374"
+ cell $and $and$ls180.v:2775$525
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$511_Y
- connect \B $and$ls180.v:2762$523_Y
- connect \Y $and$ls180.v:2762$524_Y
+ connect \A $eq$ls180.v:2775$512_Y
+ connect \B $and$ls180.v:2775$524_Y
+ connect \Y $and$ls180.v:2775$525_Y
end
- attribute \src "ls180.v:2762.37-2762.405"
- cell $and $and$ls180.v:2762$525
+ attribute \src "ls180.v:2775.37-2775.405"
+ cell $and $and$ls180.v:2775$526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2762$524_Y
+ connect \A $and$ls180.v:2775$525_Y
connect \B \sdram_interface_bank0_ready
- connect \Y $and$ls180.v:2762$525_Y
+ connect \Y $and$ls180.v:2775$526_Y
end
- attribute \src "ls180.v:2762.525-2762.594"
- cell $and $and$ls180.v:2762$530
+ attribute \src "ls180.v:2775.525-2775.594"
+ cell $and $and$ls180.v:2775$531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:2762$529_Y
- connect \Y $and$ls180.v:2762$530_Y
+ connect \B $eq$ls180.v:2775$530_Y
+ connect \Y $and$ls180.v:2775$531_Y
end
- attribute \src "ls180.v:2762.600-2762.669"
- cell $and $and$ls180.v:2762$533
+ attribute \src "ls180.v:2775.600-2775.669"
+ cell $and $and$ls180.v:2775$534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:2762$532_Y
- connect \Y $and$ls180.v:2762$533_Y
+ connect \B $eq$ls180.v:2775$533_Y
+ connect \Y $and$ls180.v:2775$534_Y
end
- attribute \src "ls180.v:2762.675-2762.744"
- cell $and $and$ls180.v:2762$536
+ attribute \src "ls180.v:2775.675-2775.744"
+ cell $and $and$ls180.v:2775$537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:2762$535_Y
- connect \Y $and$ls180.v:2762$536_Y
+ connect \B $eq$ls180.v:2775$536_Y
+ connect \Y $and$ls180.v:2775$537_Y
end
- attribute \src "ls180.v:2762.456-2762.747"
- cell $and $and$ls180.v:2762$539
+ attribute \src "ls180.v:2775.456-2775.747"
+ cell $and $and$ls180.v:2775$540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$528_Y
- connect \B $not$ls180.v:2762$538_Y
- connect \Y $and$ls180.v:2762$539_Y
+ connect \A $eq$ls180.v:2775$529_Y
+ connect \B $not$ls180.v:2775$539_Y
+ connect \Y $and$ls180.v:2775$540_Y
end
- attribute \src "ls180.v:2762.412-2762.748"
- cell $and $and$ls180.v:2762$540
+ attribute \src "ls180.v:2775.412-2775.748"
+ cell $and $and$ls180.v:2775$541
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$527_Y
- connect \B $and$ls180.v:2762$539_Y
- connect \Y $and$ls180.v:2762$540_Y
+ connect \A $eq$ls180.v:2775$528_Y
+ connect \B $and$ls180.v:2775$540_Y
+ connect \Y $and$ls180.v:2775$541_Y
end
- attribute \src "ls180.v:2762.411-2762.779"
- cell $and $and$ls180.v:2762$541
+ attribute \src "ls180.v:2775.411-2775.779"
+ cell $and $and$ls180.v:2775$542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2762$540_Y
+ connect \A $and$ls180.v:2775$541_Y
connect \B \sdram_interface_bank1_ready
- connect \Y $and$ls180.v:2762$541_Y
+ connect \Y $and$ls180.v:2775$542_Y
end
- attribute \src "ls180.v:2762.899-2762.968"
- cell $and $and$ls180.v:2762$546
+ attribute \src "ls180.v:2775.899-2775.968"
+ cell $and $and$ls180.v:2775$547
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:2762$545_Y
- connect \Y $and$ls180.v:2762$546_Y
+ connect \B $eq$ls180.v:2775$546_Y
+ connect \Y $and$ls180.v:2775$547_Y
end
- attribute \src "ls180.v:2762.974-2762.1043"
- cell $and $and$ls180.v:2762$549
+ attribute \src "ls180.v:2775.974-2775.1043"
+ cell $and $and$ls180.v:2775$550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:2762$548_Y
- connect \Y $and$ls180.v:2762$549_Y
+ connect \B $eq$ls180.v:2775$549_Y
+ connect \Y $and$ls180.v:2775$550_Y
end
- attribute \src "ls180.v:2762.1049-2762.1118"
- cell $and $and$ls180.v:2762$552
+ attribute \src "ls180.v:2775.1049-2775.1118"
+ cell $and $and$ls180.v:2775$553
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:2762$551_Y
- connect \Y $and$ls180.v:2762$552_Y
+ connect \B $eq$ls180.v:2775$552_Y
+ connect \Y $and$ls180.v:2775$553_Y
end
- attribute \src "ls180.v:2762.830-2762.1121"
- cell $and $and$ls180.v:2762$555
+ attribute \src "ls180.v:2775.830-2775.1121"
+ cell $and $and$ls180.v:2775$556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$544_Y
- connect \B $not$ls180.v:2762$554_Y
- connect \Y $and$ls180.v:2762$555_Y
+ connect \A $eq$ls180.v:2775$545_Y
+ connect \B $not$ls180.v:2775$555_Y
+ connect \Y $and$ls180.v:2775$556_Y
end
- attribute \src "ls180.v:2762.786-2762.1122"
- cell $and $and$ls180.v:2762$556
+ attribute \src "ls180.v:2775.786-2775.1122"
+ cell $and $and$ls180.v:2775$557
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$543_Y
- connect \B $and$ls180.v:2762$555_Y
- connect \Y $and$ls180.v:2762$556_Y
+ connect \A $eq$ls180.v:2775$544_Y
+ connect \B $and$ls180.v:2775$556_Y
+ connect \Y $and$ls180.v:2775$557_Y
end
- attribute \src "ls180.v:2762.785-2762.1153"
- cell $and $and$ls180.v:2762$557
+ attribute \src "ls180.v:2775.785-2775.1153"
+ cell $and $and$ls180.v:2775$558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2762$556_Y
+ connect \A $and$ls180.v:2775$557_Y
connect \B \sdram_interface_bank2_ready
- connect \Y $and$ls180.v:2762$557_Y
+ connect \Y $and$ls180.v:2775$558_Y
end
- attribute \src "ls180.v:2762.1273-2762.1342"
- cell $and $and$ls180.v:2762$562
+ attribute \src "ls180.v:2775.1273-2775.1342"
+ cell $and $and$ls180.v:2775$563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:2762$561_Y
- connect \Y $and$ls180.v:2762$562_Y
+ connect \B $eq$ls180.v:2775$562_Y
+ connect \Y $and$ls180.v:2775$563_Y
end
- attribute \src "ls180.v:2762.1348-2762.1417"
- cell $and $and$ls180.v:2762$565
+ attribute \src "ls180.v:2775.1348-2775.1417"
+ cell $and $and$ls180.v:2775$566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:2762$564_Y
- connect \Y $and$ls180.v:2762$565_Y
+ connect \B $eq$ls180.v:2775$565_Y
+ connect \Y $and$ls180.v:2775$566_Y
end
- attribute \src "ls180.v:2762.1423-2762.1492"
- cell $and $and$ls180.v:2762$568
+ attribute \src "ls180.v:2775.1423-2775.1492"
+ cell $and $and$ls180.v:2775$569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:2762$567_Y
- connect \Y $and$ls180.v:2762$568_Y
+ connect \B $eq$ls180.v:2775$568_Y
+ connect \Y $and$ls180.v:2775$569_Y
end
- attribute \src "ls180.v:2762.1204-2762.1495"
- cell $and $and$ls180.v:2762$571
+ attribute \src "ls180.v:2775.1204-2775.1495"
+ cell $and $and$ls180.v:2775$572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$560_Y
- connect \B $not$ls180.v:2762$570_Y
- connect \Y $and$ls180.v:2762$571_Y
+ connect \A $eq$ls180.v:2775$561_Y
+ connect \B $not$ls180.v:2775$571_Y
+ connect \Y $and$ls180.v:2775$572_Y
end
- attribute \src "ls180.v:2762.1160-2762.1496"
- cell $and $and$ls180.v:2762$572
+ attribute \src "ls180.v:2775.1160-2775.1496"
+ cell $and $and$ls180.v:2775$573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:2762$559_Y
- connect \B $and$ls180.v:2762$571_Y
- connect \Y $and$ls180.v:2762$572_Y
+ connect \A $eq$ls180.v:2775$560_Y
+ connect \B $and$ls180.v:2775$572_Y
+ connect \Y $and$ls180.v:2775$573_Y
end
- attribute \src "ls180.v:2762.1159-2762.1527"
- cell $and $and$ls180.v:2762$573
+ attribute \src "ls180.v:2775.1159-2775.1527"
+ cell $and $and$ls180.v:2775$574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2762$572_Y
+ connect \A $and$ls180.v:2775$573_Y
connect \B \sdram_interface_bank3_ready
- connect \Y $and$ls180.v:2762$573_Y
+ connect \Y $and$ls180.v:2775$574_Y
end
- attribute \src "ls180.v:2820.9-2820.36"
- cell $and $and$ls180.v:2820$579
+ attribute \src "ls180.v:2833.9-2833.36"
+ cell $and $and$ls180.v:2833$580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_sdram_stb
connect \B \wb_sdram_cyc
- connect \Y $and$ls180.v:2820$579_Y
+ connect \Y $and$ls180.v:2833$580_Y
end
- attribute \src "ls180.v:2838.9-2838.36"
- cell $and $and$ls180.v:2838$586
+ attribute \src "ls180.v:2851.9-2851.36"
+ cell $and $and$ls180.v:2851$587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_sdram_stb
connect \B \wb_sdram_cyc
- connect \Y $and$ls180.v:2838$586_Y
+ connect \Y $and$ls180.v:2851$587_Y
end
- attribute \src "ls180.v:2851.27-2851.60"
- cell $and $and$ls180.v:2851$590
+ attribute \src "ls180.v:2864.27-2864.60"
+ cell $and $and$ls180.v:2864$591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \litedram_wb_cyc
connect \B \litedram_wb_stb
- connect \Y $and$ls180.v:2851$590_Y
+ connect \Y $and$ls180.v:2864$591_Y
end
- attribute \src "ls180.v:2851.26-2851.79"
- cell $and $and$ls180.v:2851$592
+ attribute \src "ls180.v:2864.26-2864.79"
+ cell $and $and$ls180.v:2864$593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2851$590_Y
- connect \B $not$ls180.v:2851$591_Y
- connect \Y $and$ls180.v:2851$592_Y
+ connect \A $and$ls180.v:2864$591_Y
+ connect \B $not$ls180.v:2864$592_Y
+ connect \Y $and$ls180.v:2864$593_Y
end
- attribute \src "ls180.v:2852.29-2852.82"
- cell $and $and$ls180.v:2852$594
+ attribute \src "ls180.v:2865.29-2865.82"
+ cell $and $and$ls180.v:2865$595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2852$593_Y
+ connect \A $or$ls180.v:2865$594_Y
connect \B \port_cmd_payload_we
- connect \Y $and$ls180.v:2852$594_Y
+ connect \Y $and$ls180.v:2865$595_Y
end
- attribute \src "ls180.v:2852.28-2852.103"
- cell $and $and$ls180.v:2852$596
+ attribute \src "ls180.v:2865.28-2865.103"
+ cell $and $and$ls180.v:2865$597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2852$594_Y
- connect \B $not$ls180.v:2852$595_Y
- connect \Y $and$ls180.v:2852$596_Y
+ connect \A $and$ls180.v:2865$595_Y
+ connect \B $not$ls180.v:2865$596_Y
+ connect \Y $and$ls180.v:2865$597_Y
end
- attribute \src "ls180.v:2853.28-2853.84"
- cell $and $and$ls180.v:2853$599
+ attribute \src "ls180.v:2866.28-2866.84"
+ cell $and $and$ls180.v:2866$600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2853$597_Y
- connect \B $not$ls180.v:2853$598_Y
- connect \Y $and$ls180.v:2853$599_Y
+ connect \A $or$ls180.v:2866$598_Y
+ connect \B $not$ls180.v:2866$599_Y
+ connect \Y $and$ls180.v:2866$600_Y
end
- attribute \src "ls180.v:2854.39-2854.65"
- cell $and $and$ls180.v:2854$600
+ attribute \src "ls180.v:2867.39-2867.65"
+ cell $and $and$ls180.v:2867$601
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \litedram_wb_we
connect \B \ack_wdata
- connect \Y $and$ls180.v:2854$600_Y
+ connect \Y $and$ls180.v:2867$601_Y
end
- attribute \src "ls180.v:2854.70-2854.99"
- cell $and $and$ls180.v:2854$602
+ attribute \src "ls180.v:2867.70-2867.99"
+ cell $and $and$ls180.v:2867$603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2854$601_Y
+ connect \A $not$ls180.v:2867$602_Y
connect \B \ack_rdata
- connect \Y $and$ls180.v:2854$602_Y
+ connect \Y $and$ls180.v:2867$603_Y
end
- attribute \src "ls180.v:2854.27-2854.101"
- cell $and $and$ls180.v:2854$604
+ attribute \src "ls180.v:2867.27-2867.101"
+ cell $and $and$ls180.v:2867$605
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ack_cmd
- connect \B $or$ls180.v:2854$603_Y
- connect \Y $and$ls180.v:2854$604_Y
+ connect \B $or$ls180.v:2867$604_Y
+ connect \Y $and$ls180.v:2867$605_Y
end
- attribute \src "ls180.v:2855.20-2855.51"
- cell $and $and$ls180.v:2855$605
+ attribute \src "ls180.v:2868.20-2868.51"
+ cell $and $and$ls180.v:2868$606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_valid
connect \B \port_cmd_ready
- connect \Y $and$ls180.v:2855$605_Y
+ connect \Y $and$ls180.v:2868$606_Y
end
- attribute \src "ls180.v:2856.22-2856.57"
- cell $and $and$ls180.v:2856$607
+ attribute \src "ls180.v:2869.22-2869.57"
+ cell $and $and$ls180.v:2869$608
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_wdata_valid
connect \B \port_wdata_ready
- connect \Y $and$ls180.v:2856$607_Y
+ connect \Y $and$ls180.v:2869$608_Y
end
- attribute \src "ls180.v:2857.21-2857.56"
- cell $and $and$ls180.v:2857$609
+ attribute \src "ls180.v:2870.21-2870.56"
+ cell $and $and$ls180.v:2870$610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_rdata_valid
connect \B \port_rdata_ready
- connect \Y $and$ls180.v:2857$609_Y
+ connect \Y $and$ls180.v:2870$610_Y
end
- attribute \src "ls180.v:2886.44-2886.58"
- cell $and $and$ls180.v:2886$615
+ attribute \src "ls180.v:2899.44-2899.58"
+ cell $and $and$ls180.v:2899$616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \rxtx_we
- connect \Y $and$ls180.v:2886$615_Y
+ connect \Y $and$ls180.v:2899$616_Y
end
- attribute \src "ls180.v:2890.7-2890.58"
- cell $and $and$ls180.v:2890$619
+ attribute \src "ls180.v:2903.7-2903.58"
+ cell $and $and$ls180.v:2903$620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \eventmanager_pending_re
connect \B \eventmanager_pending_r [0]
- connect \Y $and$ls180.v:2890$619_Y
+ connect \Y $and$ls180.v:2903$620_Y
end
- attribute \src "ls180.v:2901.7-2901.58"
- cell $and $and$ls180.v:2901$622
+ attribute \src "ls180.v:2914.7-2914.58"
+ cell $and $and$ls180.v:2914$623
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \eventmanager_pending_re
connect \B \eventmanager_pending_r [1]
- connect \Y $and$ls180.v:2901$622_Y
+ connect \Y $and$ls180.v:2914$623_Y
end
- attribute \src "ls180.v:2910.16-2910.67"
- cell $and $and$ls180.v:2910$624
+ attribute \src "ls180.v:2923.16-2923.67"
+ cell $and $and$ls180.v:2923$625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \eventmanager_pending_w [0]
connect \B \eventmanager_storage [0]
- connect \Y $and$ls180.v:2910$624_Y
+ connect \Y $and$ls180.v:2923$625_Y
end
- attribute \src "ls180.v:2910.72-2910.123"
- cell $and $and$ls180.v:2910$625
+ attribute \src "ls180.v:2923.72-2923.123"
+ cell $and $and$ls180.v:2923$626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \eventmanager_pending_w [1]
connect \B \eventmanager_storage [1]
- connect \Y $and$ls180.v:2910$625_Y
+ connect \Y $and$ls180.v:2923$626_Y
end
- attribute \src "ls180.v:2925.31-2925.93"
- cell $and $and$ls180.v:2925$629
+ attribute \src "ls180.v:2938.31-2938.93"
+ cell $and $and$ls180.v:2938$630
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_syncfifo_readable
- connect \B $or$ls180.v:2925$628_Y
- connect \Y $and$ls180.v:2925$629_Y
+ connect \B $or$ls180.v:2938$629_Y
+ connect \Y $and$ls180.v:2938$630_Y
end
- attribute \src "ls180.v:2936.29-2936.96"
- cell $and $and$ls180.v:2936$634
+ attribute \src "ls180.v:2949.29-2949.96"
+ cell $and $and$ls180.v:2949$635
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_syncfifo_we
- connect \B $or$ls180.v:2936$633_Y
- connect \Y $and$ls180.v:2936$634_Y
+ connect \B $or$ls180.v:2949$634_Y
+ connect \Y $and$ls180.v:2949$635_Y
end
- attribute \src "ls180.v:2937.27-2937.74"
- cell $and $and$ls180.v:2937$635
+ attribute \src "ls180.v:2950.27-2950.74"
+ cell $and $and$ls180.v:2950$636
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \tx_fifo_syncfifo_readable
connect \B \tx_fifo_syncfifo_re
- connect \Y $and$ls180.v:2937$635_Y
+ connect \Y $and$ls180.v:2950$636_Y
end
- attribute \src "ls180.v:2955.31-2955.93"
- cell $and $and$ls180.v:2955$640
+ attribute \src "ls180.v:2968.31-2968.93"
+ cell $and $and$ls180.v:2968$641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_syncfifo_readable
- connect \B $or$ls180.v:2955$639_Y
- connect \Y $and$ls180.v:2955$640_Y
+ connect \B $or$ls180.v:2968$640_Y
+ connect \Y $and$ls180.v:2968$641_Y
end
- attribute \src "ls180.v:2966.29-2966.96"
- cell $and $and$ls180.v:2966$645
+ attribute \src "ls180.v:2979.29-2979.96"
+ cell $and $and$ls180.v:2979$646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_syncfifo_we
- connect \B $or$ls180.v:2966$644_Y
- connect \Y $and$ls180.v:2966$645_Y
+ connect \B $or$ls180.v:2979$645_Y
+ connect \Y $and$ls180.v:2979$646_Y
end
- attribute \src "ls180.v:2967.27-2967.74"
- cell $and $and$ls180.v:2967$646
+ attribute \src "ls180.v:2980.27-2980.74"
+ cell $and $and$ls180.v:2980$647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rx_fifo_syncfifo_readable
connect \B \rx_fifo_syncfifo_re
- connect \Y $and$ls180.v:2967$646_Y
+ connect \Y $and$ls180.v:2980$647_Y
end
- attribute \src "ls180.v:3064.9-3064.84"
- cell $and $and$ls180.v:3064$654
+ attribute \src "ls180.v:3077.9-3077.84"
+ cell $and $and$ls180.v:3077$655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresocsim_wishbone_cyc
connect \B \libresocsim_libresocsim_wishbone_stb
- connect \Y $and$ls180.v:3064$654_Y
+ connect \Y $and$ls180.v:3077$655_Y
end
- attribute \src "ls180.v:3067.60-3067.144"
- cell $and $and$ls180.v:3067$656
+ attribute \src "ls180.v:3080.60-3080.144"
+ cell $and $and$ls180.v:3080$657
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_libresocsim_wishbone_we
- connect \B $ne$ls180.v:3067$655_Y
- connect \Y $and$ls180.v:3067$656_Y
+ connect \B $ne$ls180.v:3080$656_Y
+ connect \Y $and$ls180.v:3080$657_Y
end
- attribute \src "ls180.v:3085.41-3085.93"
- cell $and $and$ls180.v:3085$658
+ attribute \src "ls180.v:3098.41-3098.93"
+ cell $and $and$ls180.v:3098$659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_ack
- connect \B $eq$ls180.v:3085$657_Y
- connect \Y $and$ls180.v:3085$658_Y
+ connect \B $eq$ls180.v:3098$658_Y
+ connect \Y $and$ls180.v:3098$659_Y
end
- attribute \src "ls180.v:3086.41-3086.93"
- cell $and $and$ls180.v:3086$660
+ attribute \src "ls180.v:3099.41-3099.93"
+ cell $and $and$ls180.v:3099$661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_ack
- connect \B $eq$ls180.v:3086$659_Y
- connect \Y $and$ls180.v:3086$660_Y
+ connect \B $eq$ls180.v:3099$660_Y
+ connect \Y $and$ls180.v:3099$661_Y
end
- attribute \src "ls180.v:3087.44-3087.96"
- cell $and $and$ls180.v:3087$662
+ attribute \src "ls180.v:3100.44-3100.96"
+ cell $and $and$ls180.v:3100$663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_ack
- connect \B $eq$ls180.v:3087$661_Y
- connect \Y $and$ls180.v:3087$662_Y
+ connect \B $eq$ls180.v:3100$662_Y
+ connect \Y $and$ls180.v:3100$663_Y
end
- attribute \src "ls180.v:3088.41-3088.93"
- cell $and $and$ls180.v:3088$664
+ attribute \src "ls180.v:3101.41-3101.93"
+ cell $and $and$ls180.v:3101$665
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_err
- connect \B $eq$ls180.v:3088$663_Y
- connect \Y $and$ls180.v:3088$664_Y
+ connect \B $eq$ls180.v:3101$664_Y
+ connect \Y $and$ls180.v:3101$665_Y
end
- attribute \src "ls180.v:3089.41-3089.93"
- cell $and $and$ls180.v:3089$666
+ attribute \src "ls180.v:3102.41-3102.93"
+ cell $and $and$ls180.v:3102$667
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_err
- connect \B $eq$ls180.v:3089$665_Y
- connect \Y $and$ls180.v:3089$666_Y
+ connect \B $eq$ls180.v:3102$666_Y
+ connect \Y $and$ls180.v:3102$667_Y
end
- attribute \src "ls180.v:3090.44-3090.96"
- cell $and $and$ls180.v:3090$668
+ attribute \src "ls180.v:3103.44-3103.96"
+ cell $and $and$ls180.v:3103$669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_err
- connect \B $eq$ls180.v:3090$667_Y
- connect \Y $and$ls180.v:3090$668_Y
+ connect \B $eq$ls180.v:3103$668_Y
+ connect \Y $and$ls180.v:3103$669_Y
end
- attribute \src "ls180.v:3143.35-3143.84"
- cell $and $and$ls180.v:3143$676
+ attribute \src "ls180.v:3156.35-3156.84"
+ cell $and $and$ls180.v:3156$677
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_cyc
connect \B \libresocsim_slave_sel [0]
- connect \Y $and$ls180.v:3143$676_Y
+ connect \Y $and$ls180.v:3156$677_Y
end
- attribute \src "ls180.v:3144.31-3144.80"
- cell $and $and$ls180.v:3144$677
+ attribute \src "ls180.v:3157.31-3157.80"
+ cell $and $and$ls180.v:3157$678
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_cyc
connect \B \libresocsim_slave_sel [1]
- connect \Y $and$ls180.v:3144$677_Y
+ connect \Y $and$ls180.v:3157$678_Y
end
- attribute \src "ls180.v:3145.46-3145.95"
- cell $and $and$ls180.v:3145$678
+ attribute \src "ls180.v:3158.46-3158.95"
+ cell $and $and$ls180.v:3158$679
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_cyc
connect \B \libresocsim_slave_sel [2]
- connect \Y $and$ls180.v:3145$678_Y
+ connect \Y $and$ls180.v:3158$679_Y
end
- attribute \src "ls180.v:3146.46-3146.95"
- cell $and $and$ls180.v:3146$679
+ attribute \src "ls180.v:3159.46-3159.95"
+ cell $and $and$ls180.v:3159$680
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_cyc
connect \B \libresocsim_slave_sel [3]
- connect \Y $and$ls180.v:3146$679_Y
+ connect \Y $and$ls180.v:3159$680_Y
end
- attribute \src "ls180.v:3147.49-3147.98"
- cell $and $and$ls180.v:3147$680
+ attribute \src "ls180.v:3160.49-3160.98"
+ cell $and $and$ls180.v:3160$681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_cyc
connect \B \libresocsim_slave_sel [4]
- connect \Y $and$ls180.v:3147$680_Y
+ connect \Y $and$ls180.v:3160$681_Y
end
- attribute \src "ls180.v:3148.59-3148.108"
- cell $and $and$ls180.v:3148$681
+ attribute \src "ls180.v:3161.59-3161.108"
+ cell $and $and$ls180.v:3161$682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_cyc
connect \B \libresocsim_slave_sel [5]
- connect \Y $and$ls180.v:3148$681_Y
+ connect \Y $and$ls180.v:3161$682_Y
end
- attribute \src "ls180.v:3150.29-3150.76"
- cell $and $and$ls180.v:3150$687
+ attribute \src "ls180.v:3163.29-3163.76"
+ cell $and $and$ls180.v:3163$688
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_stb
connect \B \libresocsim_shared_cyc
- connect \Y $and$ls180.v:3150$687_Y
+ connect \Y $and$ls180.v:3163$688_Y
end
- attribute \src "ls180.v:3150.28-3150.105"
- cell $and $and$ls180.v:3150$689
+ attribute \src "ls180.v:3163.28-3163.105"
+ cell $and $and$ls180.v:3163$690
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3150$687_Y
- connect \B $not$ls180.v:3150$688_Y
- connect \Y $and$ls180.v:3150$689_Y
+ connect \A $and$ls180.v:3163$688_Y
+ connect \B $not$ls180.v:3163$689_Y
+ connect \Y $and$ls180.v:3163$690_Y
end
- attribute \src "ls180.v:3156.36-3156.96"
- cell $and $and$ls180.v:3156$696
+ attribute \src "ls180.v:3169.36-3169.96"
+ cell $and $and$ls180.v:3169$697
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] }
connect \B \libresocsim_ram_bus_dat_r
- connect \Y $and$ls180.v:3156$696_Y
+ connect \Y $and$ls180.v:3169$697_Y
end
- attribute \src "ls180.v:3156.101-3156.157"
- cell $and $and$ls180.v:3156$697
+ attribute \src "ls180.v:3169.101-3169.157"
+ cell $and $and$ls180.v:3169$698
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] }
connect \B \ram_bus_ram_bus_dat_r
- connect \Y $and$ls180.v:3156$697_Y
+ connect \Y $and$ls180.v:3169$698_Y
end
- attribute \src "ls180.v:3156.163-3156.234"
- cell $and $and$ls180.v:3156$699
+ attribute \src "ls180.v:3169.163-3169.234"
+ cell $and $and$ls180.v:3169$700
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] }
connect \B \interface0_converted_interface_dat_r
- connect \Y $and$ls180.v:3156$699_Y
+ connect \Y $and$ls180.v:3169$700_Y
end
- attribute \src "ls180.v:3156.240-3156.311"
- cell $and $and$ls180.v:3156$701
+ attribute \src "ls180.v:3169.240-3169.311"
+ cell $and $and$ls180.v:3169$702
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] }
connect \B \interface1_converted_interface_dat_r
- connect \Y $and$ls180.v:3156$701_Y
+ connect \Y $and$ls180.v:3169$702_Y
end
- attribute \src "ls180.v:3156.317-3156.391"
- cell $and $and$ls180.v:3156$703
+ attribute \src "ls180.v:3169.317-3169.391"
+ cell $and $and$ls180.v:3169$704
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] }
connect \B \socbushandler_converted_interface_dat_r
- connect \Y $and$ls180.v:3156$703_Y
+ connect \Y $and$ls180.v:3169$704_Y
end
- attribute \src "ls180.v:3156.397-3156.481"
- cell $and $and$ls180.v:3156$705
+ attribute \src "ls180.v:3169.397-3169.481"
+ cell $and $and$ls180.v:3169$706
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] }
connect \B \libresocsim_libresocsim_converted_interface_dat_r
- connect \Y $and$ls180.v:3156$705_Y
+ connect \Y $and$ls180.v:3169$706_Y
end
- attribute \src "ls180.v:3166.43-3166.104"
- cell $and $and$ls180.v:3166$709
+ attribute \src "ls180.v:3179.43-3179.104"
+ cell $and $and$ls180.v:3179$710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3166$709_Y
+ connect \Y $and$ls180.v:3179$710_Y
end
- attribute \src "ls180.v:3166.42-3166.158"
- cell $and $and$ls180.v:3166$711
+ attribute \src "ls180.v:3179.42-3179.158"
+ cell $and $and$ls180.v:3179$712
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3166$709_Y
- connect \B $eq$ls180.v:3166$710_Y
- connect \Y $and$ls180.v:3166$711_Y
+ connect \A $and$ls180.v:3179$710_Y
+ connect \B $eq$ls180.v:3179$711_Y
+ connect \Y $and$ls180.v:3179$712_Y
end
- attribute \src "ls180.v:3167.43-3167.107"
- cell $and $and$ls180.v:3167$713
+ attribute \src "ls180.v:3180.43-3180.107"
+ cell $and $and$ls180.v:3180$714
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3167$712_Y
- connect \Y $and$ls180.v:3167$713_Y
+ connect \B $not$ls180.v:3180$713_Y
+ connect \Y $and$ls180.v:3180$714_Y
end
- attribute \src "ls180.v:3167.42-3167.161"
- cell $and $and$ls180.v:3167$715
+ attribute \src "ls180.v:3180.42-3180.161"
+ cell $and $and$ls180.v:3180$716
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3167$713_Y
- connect \B $eq$ls180.v:3167$714_Y
- connect \Y $and$ls180.v:3167$715_Y
+ connect \A $and$ls180.v:3180$714_Y
+ connect \B $eq$ls180.v:3180$715_Y
+ connect \Y $and$ls180.v:3180$716_Y
end
- attribute \src "ls180.v:3169.45-3169.106"
- cell $and $and$ls180.v:3169$716
+ attribute \src "ls180.v:3182.45-3182.106"
+ cell $and $and$ls180.v:3182$717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3169$716_Y
+ connect \Y $and$ls180.v:3182$717_Y
end
- attribute \src "ls180.v:3169.44-3169.160"
- cell $and $and$ls180.v:3169$718
+ attribute \src "ls180.v:3182.44-3182.160"
+ cell $and $and$ls180.v:3182$719
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3169$716_Y
- connect \B $eq$ls180.v:3169$717_Y
- connect \Y $and$ls180.v:3169$718_Y
+ connect \A $and$ls180.v:3182$717_Y
+ connect \B $eq$ls180.v:3182$718_Y
+ connect \Y $and$ls180.v:3182$719_Y
end
- attribute \src "ls180.v:3170.45-3170.109"
- cell $and $and$ls180.v:3170$720
+ attribute \src "ls180.v:3183.45-3183.109"
+ cell $and $and$ls180.v:3183$721
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3170$719_Y
- connect \Y $and$ls180.v:3170$720_Y
+ connect \B $not$ls180.v:3183$720_Y
+ connect \Y $and$ls180.v:3183$721_Y
end
- attribute \src "ls180.v:3170.44-3170.163"
- cell $and $and$ls180.v:3170$722
+ attribute \src "ls180.v:3183.44-3183.163"
+ cell $and $and$ls180.v:3183$723
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3170$720_Y
- connect \B $eq$ls180.v:3170$721_Y
- connect \Y $and$ls180.v:3170$722_Y
+ connect \A $and$ls180.v:3183$721_Y
+ connect \B $eq$ls180.v:3183$722_Y
+ connect \Y $and$ls180.v:3183$723_Y
end
- attribute \src "ls180.v:3172.45-3172.106"
- cell $and $and$ls180.v:3172$723
+ attribute \src "ls180.v:3185.45-3185.106"
+ cell $and $and$ls180.v:3185$724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3172$723_Y
+ connect \Y $and$ls180.v:3185$724_Y
end
- attribute \src "ls180.v:3172.44-3172.160"
- cell $and $and$ls180.v:3172$725
+ attribute \src "ls180.v:3185.44-3185.160"
+ cell $and $and$ls180.v:3185$726
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3172$723_Y
- connect \B $eq$ls180.v:3172$724_Y
- connect \Y $and$ls180.v:3172$725_Y
+ connect \A $and$ls180.v:3185$724_Y
+ connect \B $eq$ls180.v:3185$725_Y
+ connect \Y $and$ls180.v:3185$726_Y
end
- attribute \src "ls180.v:3173.45-3173.109"
- cell $and $and$ls180.v:3173$727
+ attribute \src "ls180.v:3186.45-3186.109"
+ cell $and $and$ls180.v:3186$728
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3173$726_Y
- connect \Y $and$ls180.v:3173$727_Y
+ connect \B $not$ls180.v:3186$727_Y
+ connect \Y $and$ls180.v:3186$728_Y
end
- attribute \src "ls180.v:3173.44-3173.163"
- cell $and $and$ls180.v:3173$729
+ attribute \src "ls180.v:3186.44-3186.163"
+ cell $and $and$ls180.v:3186$730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3173$727_Y
- connect \B $eq$ls180.v:3173$728_Y
- connect \Y $and$ls180.v:3173$729_Y
+ connect \A $and$ls180.v:3186$728_Y
+ connect \B $eq$ls180.v:3186$729_Y
+ connect \Y $and$ls180.v:3186$730_Y
end
- attribute \src "ls180.v:3175.45-3175.106"
- cell $and $and$ls180.v:3175$730
+ attribute \src "ls180.v:3188.45-3188.106"
+ cell $and $and$ls180.v:3188$731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3175$730_Y
+ connect \Y $and$ls180.v:3188$731_Y
end
- attribute \src "ls180.v:3175.44-3175.160"
- cell $and $and$ls180.v:3175$732
+ attribute \src "ls180.v:3188.44-3188.160"
+ cell $and $and$ls180.v:3188$733
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3175$730_Y
- connect \B $eq$ls180.v:3175$731_Y
- connect \Y $and$ls180.v:3175$732_Y
+ connect \A $and$ls180.v:3188$731_Y
+ connect \B $eq$ls180.v:3188$732_Y
+ connect \Y $and$ls180.v:3188$733_Y
end
- attribute \src "ls180.v:3176.45-3176.109"
- cell $and $and$ls180.v:3176$734
+ attribute \src "ls180.v:3189.45-3189.109"
+ cell $and $and$ls180.v:3189$735
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3176$733_Y
- connect \Y $and$ls180.v:3176$734_Y
+ connect \B $not$ls180.v:3189$734_Y
+ connect \Y $and$ls180.v:3189$735_Y
end
- attribute \src "ls180.v:3176.44-3176.163"
- cell $and $and$ls180.v:3176$736
+ attribute \src "ls180.v:3189.44-3189.163"
+ cell $and $and$ls180.v:3189$737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3176$734_Y
- connect \B $eq$ls180.v:3176$735_Y
- connect \Y $and$ls180.v:3176$736_Y
+ connect \A $and$ls180.v:3189$735_Y
+ connect \B $eq$ls180.v:3189$736_Y
+ connect \Y $and$ls180.v:3189$737_Y
end
- attribute \src "ls180.v:3178.45-3178.106"
- cell $and $and$ls180.v:3178$737
+ attribute \src "ls180.v:3191.45-3191.106"
+ cell $and $and$ls180.v:3191$738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3178$737_Y
+ connect \Y $and$ls180.v:3191$738_Y
end
- attribute \src "ls180.v:3178.44-3178.160"
- cell $and $and$ls180.v:3178$739
+ attribute \src "ls180.v:3191.44-3191.160"
+ cell $and $and$ls180.v:3191$740
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3178$737_Y
- connect \B $eq$ls180.v:3178$738_Y
- connect \Y $and$ls180.v:3178$739_Y
+ connect \A $and$ls180.v:3191$738_Y
+ connect \B $eq$ls180.v:3191$739_Y
+ connect \Y $and$ls180.v:3191$740_Y
end
- attribute \src "ls180.v:3179.45-3179.109"
- cell $and $and$ls180.v:3179$741
+ attribute \src "ls180.v:3192.45-3192.109"
+ cell $and $and$ls180.v:3192$742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3179$740_Y
- connect \Y $and$ls180.v:3179$741_Y
+ connect \B $not$ls180.v:3192$741_Y
+ connect \Y $and$ls180.v:3192$742_Y
end
- attribute \src "ls180.v:3179.44-3179.163"
- cell $and $and$ls180.v:3179$743
+ attribute \src "ls180.v:3192.44-3192.163"
+ cell $and $and$ls180.v:3192$744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3179$741_Y
- connect \B $eq$ls180.v:3179$742_Y
- connect \Y $and$ls180.v:3179$743_Y
+ connect \A $and$ls180.v:3192$742_Y
+ connect \B $eq$ls180.v:3192$743_Y
+ connect \Y $and$ls180.v:3192$744_Y
end
- attribute \src "ls180.v:3181.48-3181.109"
- cell $and $and$ls180.v:3181$744
+ attribute \src "ls180.v:3194.48-3194.109"
+ cell $and $and$ls180.v:3194$745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3181$744_Y
+ connect \Y $and$ls180.v:3194$745_Y
end
- attribute \src "ls180.v:3181.47-3181.163"
- cell $and $and$ls180.v:3181$746
+ attribute \src "ls180.v:3194.47-3194.163"
+ cell $and $and$ls180.v:3194$747
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3181$744_Y
- connect \B $eq$ls180.v:3181$745_Y
- connect \Y $and$ls180.v:3181$746_Y
+ connect \A $and$ls180.v:3194$745_Y
+ connect \B $eq$ls180.v:3194$746_Y
+ connect \Y $and$ls180.v:3194$747_Y
end
- attribute \src "ls180.v:3182.48-3182.112"
- cell $and $and$ls180.v:3182$748
+ attribute \src "ls180.v:3195.48-3195.112"
+ cell $and $and$ls180.v:3195$749
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3182$747_Y
- connect \Y $and$ls180.v:3182$748_Y
+ connect \B $not$ls180.v:3195$748_Y
+ connect \Y $and$ls180.v:3195$749_Y
end
- attribute \src "ls180.v:3182.47-3182.166"
- cell $and $and$ls180.v:3182$750
+ attribute \src "ls180.v:3195.47-3195.166"
+ cell $and $and$ls180.v:3195$751
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3182$748_Y
- connect \B $eq$ls180.v:3182$749_Y
- connect \Y $and$ls180.v:3182$750_Y
+ connect \A $and$ls180.v:3195$749_Y
+ connect \B $eq$ls180.v:3195$750_Y
+ connect \Y $and$ls180.v:3195$751_Y
end
- attribute \src "ls180.v:3184.48-3184.109"
- cell $and $and$ls180.v:3184$751
+ attribute \src "ls180.v:3197.48-3197.109"
+ cell $and $and$ls180.v:3197$752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3184$751_Y
+ connect \Y $and$ls180.v:3197$752_Y
end
- attribute \src "ls180.v:3184.47-3184.163"
- cell $and $and$ls180.v:3184$753
+ attribute \src "ls180.v:3197.47-3197.163"
+ cell $and $and$ls180.v:3197$754
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3184$751_Y
- connect \B $eq$ls180.v:3184$752_Y
- connect \Y $and$ls180.v:3184$753_Y
+ connect \A $and$ls180.v:3197$752_Y
+ connect \B $eq$ls180.v:3197$753_Y
+ connect \Y $and$ls180.v:3197$754_Y
end
- attribute \src "ls180.v:3185.48-3185.112"
- cell $and $and$ls180.v:3185$755
+ attribute \src "ls180.v:3198.48-3198.112"
+ cell $and $and$ls180.v:3198$756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3185$754_Y
- connect \Y $and$ls180.v:3185$755_Y
+ connect \B $not$ls180.v:3198$755_Y
+ connect \Y $and$ls180.v:3198$756_Y
end
- attribute \src "ls180.v:3185.47-3185.166"
- cell $and $and$ls180.v:3185$757
+ attribute \src "ls180.v:3198.47-3198.166"
+ cell $and $and$ls180.v:3198$758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3185$755_Y
- connect \B $eq$ls180.v:3185$756_Y
- connect \Y $and$ls180.v:3185$757_Y
+ connect \A $and$ls180.v:3198$756_Y
+ connect \B $eq$ls180.v:3198$757_Y
+ connect \Y $and$ls180.v:3198$758_Y
end
- attribute \src "ls180.v:3187.48-3187.109"
- cell $and $and$ls180.v:3187$758
+ attribute \src "ls180.v:3200.48-3200.109"
+ cell $and $and$ls180.v:3200$759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3187$758_Y
+ connect \Y $and$ls180.v:3200$759_Y
end
- attribute \src "ls180.v:3187.47-3187.163"
- cell $and $and$ls180.v:3187$760
+ attribute \src "ls180.v:3200.47-3200.163"
+ cell $and $and$ls180.v:3200$761
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3187$758_Y
- connect \B $eq$ls180.v:3187$759_Y
- connect \Y $and$ls180.v:3187$760_Y
+ connect \A $and$ls180.v:3200$759_Y
+ connect \B $eq$ls180.v:3200$760_Y
+ connect \Y $and$ls180.v:3200$761_Y
end
- attribute \src "ls180.v:3188.48-3188.112"
- cell $and $and$ls180.v:3188$762
+ attribute \src "ls180.v:3201.48-3201.112"
+ cell $and $and$ls180.v:3201$763
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3188$761_Y
- connect \Y $and$ls180.v:3188$762_Y
+ connect \B $not$ls180.v:3201$762_Y
+ connect \Y $and$ls180.v:3201$763_Y
end
- attribute \src "ls180.v:3188.47-3188.166"
- cell $and $and$ls180.v:3188$764
+ attribute \src "ls180.v:3201.47-3201.166"
+ cell $and $and$ls180.v:3201$765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3188$762_Y
- connect \B $eq$ls180.v:3188$763_Y
- connect \Y $and$ls180.v:3188$764_Y
+ connect \A $and$ls180.v:3201$763_Y
+ connect \B $eq$ls180.v:3201$764_Y
+ connect \Y $and$ls180.v:3201$765_Y
end
- attribute \src "ls180.v:3190.48-3190.109"
- cell $and $and$ls180.v:3190$765
+ attribute \src "ls180.v:3203.48-3203.109"
+ cell $and $and$ls180.v:3203$766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
connect \B \libresocsim_interface0_bank_bus_we
- connect \Y $and$ls180.v:3190$765_Y
+ connect \Y $and$ls180.v:3203$766_Y
end
- attribute \src "ls180.v:3190.47-3190.163"
- cell $and $and$ls180.v:3190$767
+ attribute \src "ls180.v:3203.47-3203.163"
+ cell $and $and$ls180.v:3203$768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3190$765_Y
- connect \B $eq$ls180.v:3190$766_Y
- connect \Y $and$ls180.v:3190$767_Y
+ connect \A $and$ls180.v:3203$766_Y
+ connect \B $eq$ls180.v:3203$767_Y
+ connect \Y $and$ls180.v:3203$768_Y
end
- attribute \src "ls180.v:3191.48-3191.112"
- cell $and $and$ls180.v:3191$769
+ attribute \src "ls180.v:3204.48-3204.112"
+ cell $and $and$ls180.v:3204$770
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank0_sel
- connect \B $not$ls180.v:3191$768_Y
- connect \Y $and$ls180.v:3191$769_Y
+ connect \B $not$ls180.v:3204$769_Y
+ connect \Y $and$ls180.v:3204$770_Y
end
- attribute \src "ls180.v:3191.47-3191.166"
- cell $and $and$ls180.v:3191$771
+ attribute \src "ls180.v:3204.47-3204.166"
+ cell $and $and$ls180.v:3204$772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3191$769_Y
- connect \B $eq$ls180.v:3191$770_Y
- connect \Y $and$ls180.v:3191$771_Y
+ connect \A $and$ls180.v:3204$770_Y
+ connect \B $eq$ls180.v:3204$771_Y
+ connect \Y $and$ls180.v:3204$772_Y
end
- attribute \src "ls180.v:3204.40-3204.101"
- cell $and $and$ls180.v:3204$773
+ attribute \src "ls180.v:3217.40-3217.101"
+ cell $and $and$ls180.v:3217$774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank1_sel
connect \B \libresocsim_interface1_bank_bus_we
- connect \Y $and$ls180.v:3204$773_Y
+ connect \Y $and$ls180.v:3217$774_Y
end
- attribute \src "ls180.v:3204.39-3204.155"
- cell $and $and$ls180.v:3204$775
+ attribute \src "ls180.v:3217.39-3217.155"
+ cell $and $and$ls180.v:3217$776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3204$773_Y
- connect \B $eq$ls180.v:3204$774_Y
- connect \Y $and$ls180.v:3204$775_Y
+ connect \A $and$ls180.v:3217$774_Y
+ connect \B $eq$ls180.v:3217$775_Y
+ connect \Y $and$ls180.v:3217$776_Y
end
- attribute \src "ls180.v:3205.40-3205.104"
- cell $and $and$ls180.v:3205$777
+ attribute \src "ls180.v:3218.40-3218.104"
+ cell $and $and$ls180.v:3218$778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank1_sel
- connect \B $not$ls180.v:3205$776_Y
- connect \Y $and$ls180.v:3205$777_Y
+ connect \B $not$ls180.v:3218$777_Y
+ connect \Y $and$ls180.v:3218$778_Y
end
- attribute \src "ls180.v:3205.39-3205.158"
- cell $and $and$ls180.v:3205$779
+ attribute \src "ls180.v:3218.39-3218.158"
+ cell $and $and$ls180.v:3218$780
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3205$777_Y
- connect \B $eq$ls180.v:3205$778_Y
- connect \Y $and$ls180.v:3205$779_Y
+ connect \A $and$ls180.v:3218$778_Y
+ connect \B $eq$ls180.v:3218$779_Y
+ connect \Y $and$ls180.v:3218$780_Y
end
- attribute \src "ls180.v:3207.39-3207.100"
- cell $and $and$ls180.v:3207$780
+ attribute \src "ls180.v:3220.39-3220.100"
+ cell $and $and$ls180.v:3220$781
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank1_sel
connect \B \libresocsim_interface1_bank_bus_we
- connect \Y $and$ls180.v:3207$780_Y
+ connect \Y $and$ls180.v:3220$781_Y
end
- attribute \src "ls180.v:3207.38-3207.154"
- cell $and $and$ls180.v:3207$782
+ attribute \src "ls180.v:3220.38-3220.154"
+ cell $and $and$ls180.v:3220$783
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3207$780_Y
- connect \B $eq$ls180.v:3207$781_Y
- connect \Y $and$ls180.v:3207$782_Y
+ connect \A $and$ls180.v:3220$781_Y
+ connect \B $eq$ls180.v:3220$782_Y
+ connect \Y $and$ls180.v:3220$783_Y
end
- attribute \src "ls180.v:3208.39-3208.103"
- cell $and $and$ls180.v:3208$784
+ attribute \src "ls180.v:3221.39-3221.103"
+ cell $and $and$ls180.v:3221$785
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank1_sel
- connect \B $not$ls180.v:3208$783_Y
- connect \Y $and$ls180.v:3208$784_Y
+ connect \B $not$ls180.v:3221$784_Y
+ connect \Y $and$ls180.v:3221$785_Y
end
- attribute \src "ls180.v:3208.38-3208.157"
- cell $and $and$ls180.v:3208$786
+ attribute \src "ls180.v:3221.38-3221.157"
+ cell $and $and$ls180.v:3221$787
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3208$784_Y
- connect \B $eq$ls180.v:3208$785_Y
- connect \Y $and$ls180.v:3208$786_Y
+ connect \A $and$ls180.v:3221$785_Y
+ connect \B $eq$ls180.v:3221$786_Y
+ connect \Y $and$ls180.v:3221$787_Y
end
- attribute \src "ls180.v:3210.41-3210.102"
- cell $and $and$ls180.v:3210$787
+ attribute \src "ls180.v:3223.41-3223.102"
+ cell $and $and$ls180.v:3223$788
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank1_sel
connect \B \libresocsim_interface1_bank_bus_we
- connect \Y $and$ls180.v:3210$787_Y
+ connect \Y $and$ls180.v:3223$788_Y
end
- attribute \src "ls180.v:3210.40-3210.156"
- cell $and $and$ls180.v:3210$789
+ attribute \src "ls180.v:3223.40-3223.156"
+ cell $and $and$ls180.v:3223$790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3210$787_Y
- connect \B $eq$ls180.v:3210$788_Y
- connect \Y $and$ls180.v:3210$789_Y
+ connect \A $and$ls180.v:3223$788_Y
+ connect \B $eq$ls180.v:3223$789_Y
+ connect \Y $and$ls180.v:3223$790_Y
end
- attribute \src "ls180.v:3211.41-3211.105"
- cell $and $and$ls180.v:3211$791
+ attribute \src "ls180.v:3224.41-3224.105"
+ cell $and $and$ls180.v:3224$792
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank1_sel
- connect \B $not$ls180.v:3211$790_Y
- connect \Y $and$ls180.v:3211$791_Y
+ connect \B $not$ls180.v:3224$791_Y
+ connect \Y $and$ls180.v:3224$792_Y
end
- attribute \src "ls180.v:3211.40-3211.159"
- cell $and $and$ls180.v:3211$793
+ attribute \src "ls180.v:3224.40-3224.159"
+ cell $and $and$ls180.v:3224$794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3211$791_Y
- connect \B $eq$ls180.v:3211$792_Y
- connect \Y $and$ls180.v:3211$793_Y
+ connect \A $and$ls180.v:3224$792_Y
+ connect \B $eq$ls180.v:3224$793_Y
+ connect \Y $and$ls180.v:3224$794_Y
end
- attribute \src "ls180.v:3218.40-3218.101"
- cell $and $and$ls180.v:3218$795
+ attribute \src "ls180.v:3231.40-3231.101"
+ cell $and $and$ls180.v:3231$796
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank2_sel
connect \B \libresocsim_interface2_bank_bus_we
- connect \Y $and$ls180.v:3218$795_Y
+ connect \Y $and$ls180.v:3231$796_Y
end
- attribute \src "ls180.v:3218.39-3218.155"
- cell $and $and$ls180.v:3218$797
+ attribute \src "ls180.v:3231.39-3231.155"
+ cell $and $and$ls180.v:3231$798
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3218$795_Y
- connect \B $eq$ls180.v:3218$796_Y
- connect \Y $and$ls180.v:3218$797_Y
+ connect \A $and$ls180.v:3231$796_Y
+ connect \B $eq$ls180.v:3231$797_Y
+ connect \Y $and$ls180.v:3231$798_Y
end
- attribute \src "ls180.v:3219.40-3219.104"
- cell $and $and$ls180.v:3219$799
+ attribute \src "ls180.v:3232.40-3232.104"
+ cell $and $and$ls180.v:3232$800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank2_sel
- connect \B $not$ls180.v:3219$798_Y
- connect \Y $and$ls180.v:3219$799_Y
+ connect \B $not$ls180.v:3232$799_Y
+ connect \Y $and$ls180.v:3232$800_Y
end
- attribute \src "ls180.v:3219.39-3219.158"
- cell $and $and$ls180.v:3219$801
+ attribute \src "ls180.v:3232.39-3232.158"
+ cell $and $and$ls180.v:3232$802
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3219$799_Y
- connect \B $eq$ls180.v:3219$800_Y
- connect \Y $and$ls180.v:3219$801_Y
+ connect \A $and$ls180.v:3232$800_Y
+ connect \B $eq$ls180.v:3232$801_Y
+ connect \Y $and$ls180.v:3232$802_Y
end
- attribute \src "ls180.v:3221.39-3221.100"
- cell $and $and$ls180.v:3221$802
+ attribute \src "ls180.v:3234.39-3234.100"
+ cell $and $and$ls180.v:3234$803
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank2_sel
connect \B \libresocsim_interface2_bank_bus_we
- connect \Y $and$ls180.v:3221$802_Y
+ connect \Y $and$ls180.v:3234$803_Y
end
- attribute \src "ls180.v:3221.38-3221.154"
- cell $and $and$ls180.v:3221$804
+ attribute \src "ls180.v:3234.38-3234.154"
+ cell $and $and$ls180.v:3234$805
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3221$802_Y
- connect \B $eq$ls180.v:3221$803_Y
- connect \Y $and$ls180.v:3221$804_Y
+ connect \A $and$ls180.v:3234$803_Y
+ connect \B $eq$ls180.v:3234$804_Y
+ connect \Y $and$ls180.v:3234$805_Y
end
- attribute \src "ls180.v:3222.39-3222.103"
- cell $and $and$ls180.v:3222$806
+ attribute \src "ls180.v:3235.39-3235.103"
+ cell $and $and$ls180.v:3235$807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank2_sel
- connect \B $not$ls180.v:3222$805_Y
- connect \Y $and$ls180.v:3222$806_Y
+ connect \B $not$ls180.v:3235$806_Y
+ connect \Y $and$ls180.v:3235$807_Y
end
- attribute \src "ls180.v:3222.38-3222.157"
- cell $and $and$ls180.v:3222$808
+ attribute \src "ls180.v:3235.38-3235.157"
+ cell $and $and$ls180.v:3235$809
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3222$806_Y
- connect \B $eq$ls180.v:3222$807_Y
- connect \Y $and$ls180.v:3222$808_Y
+ connect \A $and$ls180.v:3235$807_Y
+ connect \B $eq$ls180.v:3235$808_Y
+ connect \Y $and$ls180.v:3235$809_Y
end
- attribute \src "ls180.v:3224.41-3224.102"
- cell $and $and$ls180.v:3224$809
+ attribute \src "ls180.v:3237.41-3237.102"
+ cell $and $and$ls180.v:3237$810
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank2_sel
connect \B \libresocsim_interface2_bank_bus_we
- connect \Y $and$ls180.v:3224$809_Y
+ connect \Y $and$ls180.v:3237$810_Y
end
- attribute \src "ls180.v:3224.40-3224.156"
- cell $and $and$ls180.v:3224$811
+ attribute \src "ls180.v:3237.40-3237.156"
+ cell $and $and$ls180.v:3237$812
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3224$809_Y
- connect \B $eq$ls180.v:3224$810_Y
- connect \Y $and$ls180.v:3224$811_Y
+ connect \A $and$ls180.v:3237$810_Y
+ connect \B $eq$ls180.v:3237$811_Y
+ connect \Y $and$ls180.v:3237$812_Y
end
- attribute \src "ls180.v:3225.41-3225.105"
- cell $and $and$ls180.v:3225$813
+ attribute \src "ls180.v:3238.41-3238.105"
+ cell $and $and$ls180.v:3238$814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank2_sel
- connect \B $not$ls180.v:3225$812_Y
- connect \Y $and$ls180.v:3225$813_Y
+ connect \B $not$ls180.v:3238$813_Y
+ connect \Y $and$ls180.v:3238$814_Y
end
- attribute \src "ls180.v:3225.40-3225.159"
- cell $and $and$ls180.v:3225$815
+ attribute \src "ls180.v:3238.40-3238.159"
+ cell $and $and$ls180.v:3238$816
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3225$813_Y
- connect \B $eq$ls180.v:3225$814_Y
- connect \Y $and$ls180.v:3225$815_Y
+ connect \A $and$ls180.v:3238$814_Y
+ connect \B $eq$ls180.v:3238$815_Y
+ connect \Y $and$ls180.v:3238$816_Y
end
- attribute \src "ls180.v:3232.39-3232.100"
- cell $and $and$ls180.v:3232$817
+ attribute \src "ls180.v:3245.39-3245.100"
+ cell $and $and$ls180.v:3245$818
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank3_sel
connect \B \libresocsim_interface3_bank_bus_we
- connect \Y $and$ls180.v:3232$817_Y
+ connect \Y $and$ls180.v:3245$818_Y
end
- attribute \src "ls180.v:3232.38-3232.152"
- cell $and $and$ls180.v:3232$819
+ attribute \src "ls180.v:3245.38-3245.152"
+ cell $and $and$ls180.v:3245$820
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3232$817_Y
- connect \B $eq$ls180.v:3232$818_Y
- connect \Y $and$ls180.v:3232$819_Y
+ connect \A $and$ls180.v:3245$818_Y
+ connect \B $eq$ls180.v:3245$819_Y
+ connect \Y $and$ls180.v:3245$820_Y
end
- attribute \src "ls180.v:3233.39-3233.103"
- cell $and $and$ls180.v:3233$821
+ attribute \src "ls180.v:3246.39-3246.103"
+ cell $and $and$ls180.v:3246$822
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank3_sel
- connect \B $not$ls180.v:3233$820_Y
- connect \Y $and$ls180.v:3233$821_Y
+ connect \B $not$ls180.v:3246$821_Y
+ connect \Y $and$ls180.v:3246$822_Y
end
- attribute \src "ls180.v:3233.38-3233.155"
- cell $and $and$ls180.v:3233$823
+ attribute \src "ls180.v:3246.38-3246.155"
+ cell $and $and$ls180.v:3246$824
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3233$821_Y
- connect \B $eq$ls180.v:3233$822_Y
- connect \Y $and$ls180.v:3233$823_Y
+ connect \A $and$ls180.v:3246$822_Y
+ connect \B $eq$ls180.v:3246$823_Y
+ connect \Y $and$ls180.v:3246$824_Y
end
- attribute \src "ls180.v:3235.38-3235.99"
- cell $and $and$ls180.v:3235$824
+ attribute \src "ls180.v:3248.38-3248.99"
+ cell $and $and$ls180.v:3248$825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank3_sel
connect \B \libresocsim_interface3_bank_bus_we
- connect \Y $and$ls180.v:3235$824_Y
+ connect \Y $and$ls180.v:3248$825_Y
end
- attribute \src "ls180.v:3235.37-3235.151"
- cell $and $and$ls180.v:3235$826
+ attribute \src "ls180.v:3248.37-3248.151"
+ cell $and $and$ls180.v:3248$827
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3235$824_Y
- connect \B $eq$ls180.v:3235$825_Y
- connect \Y $and$ls180.v:3235$826_Y
+ connect \A $and$ls180.v:3248$825_Y
+ connect \B $eq$ls180.v:3248$826_Y
+ connect \Y $and$ls180.v:3248$827_Y
end
- attribute \src "ls180.v:3236.38-3236.102"
- cell $and $and$ls180.v:3236$828
+ attribute \src "ls180.v:3249.38-3249.102"
+ cell $and $and$ls180.v:3249$829
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank3_sel
- connect \B $not$ls180.v:3236$827_Y
- connect \Y $and$ls180.v:3236$828_Y
+ connect \B $not$ls180.v:3249$828_Y
+ connect \Y $and$ls180.v:3249$829_Y
end
- attribute \src "ls180.v:3236.37-3236.154"
- cell $and $and$ls180.v:3236$830
+ attribute \src "ls180.v:3249.37-3249.154"
+ cell $and $and$ls180.v:3249$831
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3236$828_Y
- connect \B $eq$ls180.v:3236$829_Y
- connect \Y $and$ls180.v:3236$830_Y
+ connect \A $and$ls180.v:3249$829_Y
+ connect \B $eq$ls180.v:3249$830_Y
+ connect \Y $and$ls180.v:3249$831_Y
end
- attribute \src "ls180.v:3246.50-3246.111"
- cell $and $and$ls180.v:3246$832
+ attribute \src "ls180.v:3259.50-3259.111"
+ cell $and $and$ls180.v:3259$833
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3246$832_Y
+ connect \Y $and$ls180.v:3259$833_Y
end
- attribute \src "ls180.v:3246.49-3246.165"
- cell $and $and$ls180.v:3246$834
+ attribute \src "ls180.v:3259.49-3259.165"
+ cell $and $and$ls180.v:3259$835
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3246$832_Y
- connect \B $eq$ls180.v:3246$833_Y
- connect \Y $and$ls180.v:3246$834_Y
+ connect \A $and$ls180.v:3259$833_Y
+ connect \B $eq$ls180.v:3259$834_Y
+ connect \Y $and$ls180.v:3259$835_Y
end
- attribute \src "ls180.v:3247.50-3247.114"
- cell $and $and$ls180.v:3247$836
+ attribute \src "ls180.v:3260.50-3260.114"
+ cell $and $and$ls180.v:3260$837
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3247$835_Y
- connect \Y $and$ls180.v:3247$836_Y
+ connect \B $not$ls180.v:3260$836_Y
+ connect \Y $and$ls180.v:3260$837_Y
end
- attribute \src "ls180.v:3247.49-3247.168"
- cell $and $and$ls180.v:3247$838
+ attribute \src "ls180.v:3260.49-3260.168"
+ cell $and $and$ls180.v:3260$839
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3247$836_Y
- connect \B $eq$ls180.v:3247$837_Y
- connect \Y $and$ls180.v:3247$838_Y
+ connect \A $and$ls180.v:3260$837_Y
+ connect \B $eq$ls180.v:3260$838_Y
+ connect \Y $and$ls180.v:3260$839_Y
end
- attribute \src "ls180.v:3249.54-3249.115"
- cell $and $and$ls180.v:3249$839
+ attribute \src "ls180.v:3262.54-3262.115"
+ cell $and $and$ls180.v:3262$840
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3249$839_Y
+ connect \Y $and$ls180.v:3262$840_Y
end
- attribute \src "ls180.v:3249.53-3249.169"
- cell $and $and$ls180.v:3249$841
+ attribute \src "ls180.v:3262.53-3262.169"
+ cell $and $and$ls180.v:3262$842
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3249$839_Y
- connect \B $eq$ls180.v:3249$840_Y
- connect \Y $and$ls180.v:3249$841_Y
+ connect \A $and$ls180.v:3262$840_Y
+ connect \B $eq$ls180.v:3262$841_Y
+ connect \Y $and$ls180.v:3262$842_Y
end
- attribute \src "ls180.v:3250.54-3250.118"
- cell $and $and$ls180.v:3250$843
+ attribute \src "ls180.v:3263.54-3263.118"
+ cell $and $and$ls180.v:3263$844
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3250$842_Y
- connect \Y $and$ls180.v:3250$843_Y
+ connect \B $not$ls180.v:3263$843_Y
+ connect \Y $and$ls180.v:3263$844_Y
end
- attribute \src "ls180.v:3250.53-3250.172"
- cell $and $and$ls180.v:3250$845
+ attribute \src "ls180.v:3263.53-3263.172"
+ cell $and $and$ls180.v:3263$846
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3250$843_Y
- connect \B $eq$ls180.v:3250$844_Y
- connect \Y $and$ls180.v:3250$845_Y
+ connect \A $and$ls180.v:3263$844_Y
+ connect \B $eq$ls180.v:3263$845_Y
+ connect \Y $and$ls180.v:3263$846_Y
end
- attribute \src "ls180.v:3252.35-3252.96"
- cell $and $and$ls180.v:3252$846
+ attribute \src "ls180.v:3265.35-3265.96"
+ cell $and $and$ls180.v:3265$847
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3252$846_Y
+ connect \Y $and$ls180.v:3265$847_Y
end
- attribute \src "ls180.v:3252.34-3252.150"
- cell $and $and$ls180.v:3252$848
+ attribute \src "ls180.v:3265.34-3265.150"
+ cell $and $and$ls180.v:3265$849
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3252$846_Y
- connect \B $eq$ls180.v:3252$847_Y
- connect \Y $and$ls180.v:3252$848_Y
+ connect \A $and$ls180.v:3265$847_Y
+ connect \B $eq$ls180.v:3265$848_Y
+ connect \Y $and$ls180.v:3265$849_Y
end
- attribute \src "ls180.v:3253.35-3253.99"
- cell $and $and$ls180.v:3253$850
+ attribute \src "ls180.v:3266.35-3266.99"
+ cell $and $and$ls180.v:3266$851
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3253$849_Y
- connect \Y $and$ls180.v:3253$850_Y
+ connect \B $not$ls180.v:3266$850_Y
+ connect \Y $and$ls180.v:3266$851_Y
end
- attribute \src "ls180.v:3253.34-3253.153"
- cell $and $and$ls180.v:3253$852
+ attribute \src "ls180.v:3266.34-3266.153"
+ cell $and $and$ls180.v:3266$853
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3253$850_Y
- connect \B $eq$ls180.v:3253$851_Y
- connect \Y $and$ls180.v:3253$852_Y
+ connect \A $and$ls180.v:3266$851_Y
+ connect \B $eq$ls180.v:3266$852_Y
+ connect \Y $and$ls180.v:3266$853_Y
end
- attribute \src "ls180.v:3255.54-3255.115"
- cell $and $and$ls180.v:3255$853
+ attribute \src "ls180.v:3268.54-3268.115"
+ cell $and $and$ls180.v:3268$854
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3255$853_Y
+ connect \Y $and$ls180.v:3268$854_Y
end
- attribute \src "ls180.v:3255.53-3255.169"
- cell $and $and$ls180.v:3255$855
+ attribute \src "ls180.v:3268.53-3268.169"
+ cell $and $and$ls180.v:3268$856
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3255$853_Y
- connect \B $eq$ls180.v:3255$854_Y
- connect \Y $and$ls180.v:3255$855_Y
+ connect \A $and$ls180.v:3268$854_Y
+ connect \B $eq$ls180.v:3268$855_Y
+ connect \Y $and$ls180.v:3268$856_Y
end
- attribute \src "ls180.v:3256.54-3256.118"
- cell $and $and$ls180.v:3256$857
+ attribute \src "ls180.v:3269.54-3269.118"
+ cell $and $and$ls180.v:3269$858
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3256$856_Y
- connect \Y $and$ls180.v:3256$857_Y
+ connect \B $not$ls180.v:3269$857_Y
+ connect \Y $and$ls180.v:3269$858_Y
end
- attribute \src "ls180.v:3256.53-3256.172"
- cell $and $and$ls180.v:3256$859
+ attribute \src "ls180.v:3269.53-3269.172"
+ cell $and $and$ls180.v:3269$860
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3256$857_Y
- connect \B $eq$ls180.v:3256$858_Y
- connect \Y $and$ls180.v:3256$859_Y
+ connect \A $and$ls180.v:3269$858_Y
+ connect \B $eq$ls180.v:3269$859_Y
+ connect \Y $and$ls180.v:3269$860_Y
end
- attribute \src "ls180.v:3258.54-3258.115"
- cell $and $and$ls180.v:3258$860
+ attribute \src "ls180.v:3271.54-3271.115"
+ cell $and $and$ls180.v:3271$861
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3258$860_Y
+ connect \Y $and$ls180.v:3271$861_Y
end
- attribute \src "ls180.v:3258.53-3258.169"
- cell $and $and$ls180.v:3258$862
+ attribute \src "ls180.v:3271.53-3271.169"
+ cell $and $and$ls180.v:3271$863
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3258$860_Y
- connect \B $eq$ls180.v:3258$861_Y
- connect \Y $and$ls180.v:3258$862_Y
+ connect \A $and$ls180.v:3271$861_Y
+ connect \B $eq$ls180.v:3271$862_Y
+ connect \Y $and$ls180.v:3271$863_Y
end
- attribute \src "ls180.v:3259.54-3259.118"
- cell $and $and$ls180.v:3259$864
+ attribute \src "ls180.v:3272.54-3272.118"
+ cell $and $and$ls180.v:3272$865
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3259$863_Y
- connect \Y $and$ls180.v:3259$864_Y
+ connect \B $not$ls180.v:3272$864_Y
+ connect \Y $and$ls180.v:3272$865_Y
end
- attribute \src "ls180.v:3259.53-3259.172"
- cell $and $and$ls180.v:3259$866
+ attribute \src "ls180.v:3272.53-3272.172"
+ cell $and $and$ls180.v:3272$867
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3259$864_Y
- connect \B $eq$ls180.v:3259$865_Y
- connect \Y $and$ls180.v:3259$866_Y
+ connect \A $and$ls180.v:3272$865_Y
+ connect \B $eq$ls180.v:3272$866_Y
+ connect \Y $and$ls180.v:3272$867_Y
end
- attribute \src "ls180.v:3261.55-3261.116"
- cell $and $and$ls180.v:3261$867
+ attribute \src "ls180.v:3274.55-3274.116"
+ cell $and $and$ls180.v:3274$868
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3261$867_Y
+ connect \Y $and$ls180.v:3274$868_Y
end
- attribute \src "ls180.v:3261.54-3261.170"
- cell $and $and$ls180.v:3261$869
+ attribute \src "ls180.v:3274.54-3274.170"
+ cell $and $and$ls180.v:3274$870
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3261$867_Y
- connect \B $eq$ls180.v:3261$868_Y
- connect \Y $and$ls180.v:3261$869_Y
+ connect \A $and$ls180.v:3274$868_Y
+ connect \B $eq$ls180.v:3274$869_Y
+ connect \Y $and$ls180.v:3274$870_Y
end
- attribute \src "ls180.v:3262.55-3262.119"
- cell $and $and$ls180.v:3262$871
+ attribute \src "ls180.v:3275.55-3275.119"
+ cell $and $and$ls180.v:3275$872
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3262$870_Y
- connect \Y $and$ls180.v:3262$871_Y
+ connect \B $not$ls180.v:3275$871_Y
+ connect \Y $and$ls180.v:3275$872_Y
end
- attribute \src "ls180.v:3262.54-3262.173"
- cell $and $and$ls180.v:3262$873
+ attribute \src "ls180.v:3275.54-3275.173"
+ cell $and $and$ls180.v:3275$874
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3262$871_Y
- connect \B $eq$ls180.v:3262$872_Y
- connect \Y $and$ls180.v:3262$873_Y
+ connect \A $and$ls180.v:3275$872_Y
+ connect \B $eq$ls180.v:3275$873_Y
+ connect \Y $and$ls180.v:3275$874_Y
end
- attribute \src "ls180.v:3264.53-3264.114"
- cell $and $and$ls180.v:3264$874
+ attribute \src "ls180.v:3277.53-3277.114"
+ cell $and $and$ls180.v:3277$875
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3264$874_Y
+ connect \Y $and$ls180.v:3277$875_Y
end
- attribute \src "ls180.v:3264.52-3264.168"
- cell $and $and$ls180.v:3264$876
+ attribute \src "ls180.v:3277.52-3277.168"
+ cell $and $and$ls180.v:3277$877
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3264$874_Y
- connect \B $eq$ls180.v:3264$875_Y
- connect \Y $and$ls180.v:3264$876_Y
+ connect \A $and$ls180.v:3277$875_Y
+ connect \B $eq$ls180.v:3277$876_Y
+ connect \Y $and$ls180.v:3277$877_Y
end
- attribute \src "ls180.v:3265.53-3265.117"
- cell $and $and$ls180.v:3265$878
+ attribute \src "ls180.v:3278.53-3278.117"
+ cell $and $and$ls180.v:3278$879
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3265$877_Y
- connect \Y $and$ls180.v:3265$878_Y
+ connect \B $not$ls180.v:3278$878_Y
+ connect \Y $and$ls180.v:3278$879_Y
end
- attribute \src "ls180.v:3265.52-3265.171"
- cell $and $and$ls180.v:3265$880
+ attribute \src "ls180.v:3278.52-3278.171"
+ cell $and $and$ls180.v:3278$881
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3265$878_Y
- connect \B $eq$ls180.v:3265$879_Y
- connect \Y $and$ls180.v:3265$880_Y
+ connect \A $and$ls180.v:3278$879_Y
+ connect \B $eq$ls180.v:3278$880_Y
+ connect \Y $and$ls180.v:3278$881_Y
end
- attribute \src "ls180.v:3267.53-3267.114"
- cell $and $and$ls180.v:3267$881
+ attribute \src "ls180.v:3280.53-3280.114"
+ cell $and $and$ls180.v:3280$882
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3267$881_Y
+ connect \Y $and$ls180.v:3280$882_Y
end
- attribute \src "ls180.v:3267.52-3267.168"
- cell $and $and$ls180.v:3267$883
+ attribute \src "ls180.v:3280.52-3280.168"
+ cell $and $and$ls180.v:3280$884
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3267$881_Y
- connect \B $eq$ls180.v:3267$882_Y
- connect \Y $and$ls180.v:3267$883_Y
+ connect \A $and$ls180.v:3280$882_Y
+ connect \B $eq$ls180.v:3280$883_Y
+ connect \Y $and$ls180.v:3280$884_Y
end
- attribute \src "ls180.v:3268.53-3268.117"
- cell $and $and$ls180.v:3268$885
+ attribute \src "ls180.v:3281.53-3281.117"
+ cell $and $and$ls180.v:3281$886
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3268$884_Y
- connect \Y $and$ls180.v:3268$885_Y
+ connect \B $not$ls180.v:3281$885_Y
+ connect \Y $and$ls180.v:3281$886_Y
end
- attribute \src "ls180.v:3268.52-3268.171"
- cell $and $and$ls180.v:3268$887
+ attribute \src "ls180.v:3281.52-3281.171"
+ cell $and $and$ls180.v:3281$888
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3268$885_Y
- connect \B $eq$ls180.v:3268$886_Y
- connect \Y $and$ls180.v:3268$887_Y
+ connect \A $and$ls180.v:3281$886_Y
+ connect \B $eq$ls180.v:3281$887_Y
+ connect \Y $and$ls180.v:3281$888_Y
end
- attribute \src "ls180.v:3270.53-3270.114"
- cell $and $and$ls180.v:3270$888
+ attribute \src "ls180.v:3283.53-3283.114"
+ cell $and $and$ls180.v:3283$889
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3270$888_Y
+ connect \Y $and$ls180.v:3283$889_Y
end
- attribute \src "ls180.v:3270.52-3270.168"
- cell $and $and$ls180.v:3270$890
+ attribute \src "ls180.v:3283.52-3283.168"
+ cell $and $and$ls180.v:3283$891
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3270$888_Y
- connect \B $eq$ls180.v:3270$889_Y
- connect \Y $and$ls180.v:3270$890_Y
+ connect \A $and$ls180.v:3283$889_Y
+ connect \B $eq$ls180.v:3283$890_Y
+ connect \Y $and$ls180.v:3283$891_Y
end
- attribute \src "ls180.v:3271.53-3271.117"
- cell $and $and$ls180.v:3271$892
+ attribute \src "ls180.v:3284.53-3284.117"
+ cell $and $and$ls180.v:3284$893
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3271$891_Y
- connect \Y $and$ls180.v:3271$892_Y
+ connect \B $not$ls180.v:3284$892_Y
+ connect \Y $and$ls180.v:3284$893_Y
end
- attribute \src "ls180.v:3271.52-3271.171"
- cell $and $and$ls180.v:3271$894
+ attribute \src "ls180.v:3284.52-3284.171"
+ cell $and $and$ls180.v:3284$895
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3271$892_Y
- connect \B $eq$ls180.v:3271$893_Y
- connect \Y $and$ls180.v:3271$894_Y
+ connect \A $and$ls180.v:3284$893_Y
+ connect \B $eq$ls180.v:3284$894_Y
+ connect \Y $and$ls180.v:3284$895_Y
end
- attribute \src "ls180.v:3273.53-3273.114"
- cell $and $and$ls180.v:3273$895
+ attribute \src "ls180.v:3286.53-3286.114"
+ cell $and $and$ls180.v:3286$896
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
connect \B \libresocsim_interface4_bank_bus_we
- connect \Y $and$ls180.v:3273$895_Y
+ connect \Y $and$ls180.v:3286$896_Y
end
- attribute \src "ls180.v:3273.52-3273.168"
- cell $and $and$ls180.v:3273$897
+ attribute \src "ls180.v:3286.52-3286.168"
+ cell $and $and$ls180.v:3286$898
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3273$895_Y
- connect \B $eq$ls180.v:3273$896_Y
- connect \Y $and$ls180.v:3273$897_Y
+ connect \A $and$ls180.v:3286$896_Y
+ connect \B $eq$ls180.v:3286$897_Y
+ connect \Y $and$ls180.v:3286$898_Y
end
- attribute \src "ls180.v:3274.53-3274.117"
- cell $and $and$ls180.v:3274$899
+ attribute \src "ls180.v:3287.53-3287.117"
+ cell $and $and$ls180.v:3287$900
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank4_sel
- connect \B $not$ls180.v:3274$898_Y
- connect \Y $and$ls180.v:3274$899_Y
+ connect \B $not$ls180.v:3287$899_Y
+ connect \Y $and$ls180.v:3287$900_Y
end
- attribute \src "ls180.v:3274.52-3274.171"
- cell $and $and$ls180.v:3274$901
+ attribute \src "ls180.v:3287.52-3287.171"
+ cell $and $and$ls180.v:3287$902
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3274$899_Y
- connect \B $eq$ls180.v:3274$900_Y
- connect \Y $and$ls180.v:3274$901_Y
+ connect \A $and$ls180.v:3287$900_Y
+ connect \B $eq$ls180.v:3287$901_Y
+ connect \Y $and$ls180.v:3287$902_Y
end
- attribute \src "ls180.v:3291.42-3291.103"
- cell $and $and$ls180.v:3291$903
+ attribute \src "ls180.v:3304.42-3304.103"
+ cell $and $and$ls180.v:3304$904
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3291$903_Y
+ connect \Y $and$ls180.v:3304$904_Y
end
- attribute \src "ls180.v:3291.41-3291.157"
- cell $and $and$ls180.v:3291$905
+ attribute \src "ls180.v:3304.41-3304.157"
+ cell $and $and$ls180.v:3304$906
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3291$903_Y
- connect \B $eq$ls180.v:3291$904_Y
- connect \Y $and$ls180.v:3291$905_Y
+ connect \A $and$ls180.v:3304$904_Y
+ connect \B $eq$ls180.v:3304$905_Y
+ connect \Y $and$ls180.v:3304$906_Y
end
- attribute \src "ls180.v:3292.42-3292.106"
- cell $and $and$ls180.v:3292$907
+ attribute \src "ls180.v:3305.42-3305.106"
+ cell $and $and$ls180.v:3305$908
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3292$906_Y
- connect \Y $and$ls180.v:3292$907_Y
+ connect \B $not$ls180.v:3305$907_Y
+ connect \Y $and$ls180.v:3305$908_Y
end
- attribute \src "ls180.v:3292.41-3292.160"
- cell $and $and$ls180.v:3292$909
+ attribute \src "ls180.v:3305.41-3305.160"
+ cell $and $and$ls180.v:3305$910
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3292$907_Y
- connect \B $eq$ls180.v:3292$908_Y
- connect \Y $and$ls180.v:3292$909_Y
+ connect \A $and$ls180.v:3305$908_Y
+ connect \B $eq$ls180.v:3305$909_Y
+ connect \Y $and$ls180.v:3305$910_Y
end
- attribute \src "ls180.v:3294.42-3294.103"
- cell $and $and$ls180.v:3294$910
+ attribute \src "ls180.v:3307.42-3307.103"
+ cell $and $and$ls180.v:3307$911
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3294$910_Y
+ connect \Y $and$ls180.v:3307$911_Y
end
- attribute \src "ls180.v:3294.41-3294.157"
- cell $and $and$ls180.v:3294$912
+ attribute \src "ls180.v:3307.41-3307.157"
+ cell $and $and$ls180.v:3307$913
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3294$910_Y
- connect \B $eq$ls180.v:3294$911_Y
- connect \Y $and$ls180.v:3294$912_Y
+ connect \A $and$ls180.v:3307$911_Y
+ connect \B $eq$ls180.v:3307$912_Y
+ connect \Y $and$ls180.v:3307$913_Y
end
- attribute \src "ls180.v:3295.42-3295.106"
- cell $and $and$ls180.v:3295$914
+ attribute \src "ls180.v:3308.42-3308.106"
+ cell $and $and$ls180.v:3308$915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3295$913_Y
- connect \Y $and$ls180.v:3295$914_Y
+ connect \B $not$ls180.v:3308$914_Y
+ connect \Y $and$ls180.v:3308$915_Y
end
- attribute \src "ls180.v:3295.41-3295.160"
- cell $and $and$ls180.v:3295$916
+ attribute \src "ls180.v:3308.41-3308.160"
+ cell $and $and$ls180.v:3308$917
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3295$914_Y
- connect \B $eq$ls180.v:3295$915_Y
- connect \Y $and$ls180.v:3295$916_Y
+ connect \A $and$ls180.v:3308$915_Y
+ connect \B $eq$ls180.v:3308$916_Y
+ connect \Y $and$ls180.v:3308$917_Y
end
- attribute \src "ls180.v:3297.42-3297.103"
- cell $and $and$ls180.v:3297$917
+ attribute \src "ls180.v:3310.42-3310.103"
+ cell $and $and$ls180.v:3310$918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3297$917_Y
+ connect \Y $and$ls180.v:3310$918_Y
end
- attribute \src "ls180.v:3297.41-3297.157"
- cell $and $and$ls180.v:3297$919
+ attribute \src "ls180.v:3310.41-3310.157"
+ cell $and $and$ls180.v:3310$920
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3297$917_Y
- connect \B $eq$ls180.v:3297$918_Y
- connect \Y $and$ls180.v:3297$919_Y
+ connect \A $and$ls180.v:3310$918_Y
+ connect \B $eq$ls180.v:3310$919_Y
+ connect \Y $and$ls180.v:3310$920_Y
end
- attribute \src "ls180.v:3298.42-3298.106"
- cell $and $and$ls180.v:3298$921
+ attribute \src "ls180.v:3311.42-3311.106"
+ cell $and $and$ls180.v:3311$922
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3298$920_Y
- connect \Y $and$ls180.v:3298$921_Y
+ connect \B $not$ls180.v:3311$921_Y
+ connect \Y $and$ls180.v:3311$922_Y
end
- attribute \src "ls180.v:3298.41-3298.160"
- cell $and $and$ls180.v:3298$923
+ attribute \src "ls180.v:3311.41-3311.160"
+ cell $and $and$ls180.v:3311$924
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3298$921_Y
- connect \B $eq$ls180.v:3298$922_Y
- connect \Y $and$ls180.v:3298$923_Y
+ connect \A $and$ls180.v:3311$922_Y
+ connect \B $eq$ls180.v:3311$923_Y
+ connect \Y $and$ls180.v:3311$924_Y
end
- attribute \src "ls180.v:3300.42-3300.103"
- cell $and $and$ls180.v:3300$924
+ attribute \src "ls180.v:3313.42-3313.103"
+ cell $and $and$ls180.v:3313$925
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3300$924_Y
+ connect \Y $and$ls180.v:3313$925_Y
end
- attribute \src "ls180.v:3300.41-3300.157"
- cell $and $and$ls180.v:3300$926
+ attribute \src "ls180.v:3313.41-3313.157"
+ cell $and $and$ls180.v:3313$927
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3300$924_Y
- connect \B $eq$ls180.v:3300$925_Y
- connect \Y $and$ls180.v:3300$926_Y
+ connect \A $and$ls180.v:3313$925_Y
+ connect \B $eq$ls180.v:3313$926_Y
+ connect \Y $and$ls180.v:3313$927_Y
end
- attribute \src "ls180.v:3301.42-3301.106"
- cell $and $and$ls180.v:3301$928
+ attribute \src "ls180.v:3314.42-3314.106"
+ cell $and $and$ls180.v:3314$929
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3301$927_Y
- connect \Y $and$ls180.v:3301$928_Y
+ connect \B $not$ls180.v:3314$928_Y
+ connect \Y $and$ls180.v:3314$929_Y
end
- attribute \src "ls180.v:3301.41-3301.160"
- cell $and $and$ls180.v:3301$930
+ attribute \src "ls180.v:3314.41-3314.160"
+ cell $and $and$ls180.v:3314$931
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3301$928_Y
- connect \B $eq$ls180.v:3301$929_Y
- connect \Y $and$ls180.v:3301$930_Y
+ connect \A $and$ls180.v:3314$929_Y
+ connect \B $eq$ls180.v:3314$930_Y
+ connect \Y $and$ls180.v:3314$931_Y
end
- attribute \src "ls180.v:3303.44-3303.105"
- cell $and $and$ls180.v:3303$931
+ attribute \src "ls180.v:3316.44-3316.105"
+ cell $and $and$ls180.v:3316$932
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3303$931_Y
+ connect \Y $and$ls180.v:3316$932_Y
end
- attribute \src "ls180.v:3303.43-3303.159"
- cell $and $and$ls180.v:3303$933
+ attribute \src "ls180.v:3316.43-3316.159"
+ cell $and $and$ls180.v:3316$934
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3303$931_Y
- connect \B $eq$ls180.v:3303$932_Y
- connect \Y $and$ls180.v:3303$933_Y
+ connect \A $and$ls180.v:3316$932_Y
+ connect \B $eq$ls180.v:3316$933_Y
+ connect \Y $and$ls180.v:3316$934_Y
end
- attribute \src "ls180.v:3304.44-3304.108"
- cell $and $and$ls180.v:3304$935
+ attribute \src "ls180.v:3317.44-3317.108"
+ cell $and $and$ls180.v:3317$936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3304$934_Y
- connect \Y $and$ls180.v:3304$935_Y
+ connect \B $not$ls180.v:3317$935_Y
+ connect \Y $and$ls180.v:3317$936_Y
end
- attribute \src "ls180.v:3304.43-3304.162"
- cell $and $and$ls180.v:3304$937
+ attribute \src "ls180.v:3317.43-3317.162"
+ cell $and $and$ls180.v:3317$938
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3304$935_Y
- connect \B $eq$ls180.v:3304$936_Y
- connect \Y $and$ls180.v:3304$937_Y
+ connect \A $and$ls180.v:3317$936_Y
+ connect \B $eq$ls180.v:3317$937_Y
+ connect \Y $and$ls180.v:3317$938_Y
end
- attribute \src "ls180.v:3306.44-3306.105"
- cell $and $and$ls180.v:3306$938
+ attribute \src "ls180.v:3319.44-3319.105"
+ cell $and $and$ls180.v:3319$939
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3306$938_Y
+ connect \Y $and$ls180.v:3319$939_Y
end
- attribute \src "ls180.v:3306.43-3306.159"
- cell $and $and$ls180.v:3306$940
+ attribute \src "ls180.v:3319.43-3319.159"
+ cell $and $and$ls180.v:3319$941
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3306$938_Y
- connect \B $eq$ls180.v:3306$939_Y
- connect \Y $and$ls180.v:3306$940_Y
+ connect \A $and$ls180.v:3319$939_Y
+ connect \B $eq$ls180.v:3319$940_Y
+ connect \Y $and$ls180.v:3319$941_Y
end
- attribute \src "ls180.v:3307.44-3307.108"
- cell $and $and$ls180.v:3307$942
+ attribute \src "ls180.v:3320.44-3320.108"
+ cell $and $and$ls180.v:3320$943
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3307$941_Y
- connect \Y $and$ls180.v:3307$942_Y
+ connect \B $not$ls180.v:3320$942_Y
+ connect \Y $and$ls180.v:3320$943_Y
end
- attribute \src "ls180.v:3307.43-3307.162"
- cell $and $and$ls180.v:3307$944
+ attribute \src "ls180.v:3320.43-3320.162"
+ cell $and $and$ls180.v:3320$945
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3307$942_Y
- connect \B $eq$ls180.v:3307$943_Y
- connect \Y $and$ls180.v:3307$944_Y
+ connect \A $and$ls180.v:3320$943_Y
+ connect \B $eq$ls180.v:3320$944_Y
+ connect \Y $and$ls180.v:3320$945_Y
end
- attribute \src "ls180.v:3309.44-3309.105"
- cell $and $and$ls180.v:3309$945
+ attribute \src "ls180.v:3322.44-3322.105"
+ cell $and $and$ls180.v:3322$946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3309$945_Y
+ connect \Y $and$ls180.v:3322$946_Y
end
- attribute \src "ls180.v:3309.43-3309.159"
- cell $and $and$ls180.v:3309$947
+ attribute \src "ls180.v:3322.43-3322.159"
+ cell $and $and$ls180.v:3322$948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3309$945_Y
- connect \B $eq$ls180.v:3309$946_Y
- connect \Y $and$ls180.v:3309$947_Y
+ connect \A $and$ls180.v:3322$946_Y
+ connect \B $eq$ls180.v:3322$947_Y
+ connect \Y $and$ls180.v:3322$948_Y
end
- attribute \src "ls180.v:3310.44-3310.108"
- cell $and $and$ls180.v:3310$949
+ attribute \src "ls180.v:3323.44-3323.108"
+ cell $and $and$ls180.v:3323$950
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3310$948_Y
- connect \Y $and$ls180.v:3310$949_Y
+ connect \B $not$ls180.v:3323$949_Y
+ connect \Y $and$ls180.v:3323$950_Y
end
- attribute \src "ls180.v:3310.43-3310.162"
- cell $and $and$ls180.v:3310$951
+ attribute \src "ls180.v:3323.43-3323.162"
+ cell $and $and$ls180.v:3323$952
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3310$949_Y
- connect \B $eq$ls180.v:3310$950_Y
- connect \Y $and$ls180.v:3310$951_Y
+ connect \A $and$ls180.v:3323$950_Y
+ connect \B $eq$ls180.v:3323$951_Y
+ connect \Y $and$ls180.v:3323$952_Y
end
- attribute \src "ls180.v:3312.44-3312.105"
- cell $and $and$ls180.v:3312$952
+ attribute \src "ls180.v:3325.44-3325.105"
+ cell $and $and$ls180.v:3325$953
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3312$952_Y
+ connect \Y $and$ls180.v:3325$953_Y
end
- attribute \src "ls180.v:3312.43-3312.159"
- cell $and $and$ls180.v:3312$954
+ attribute \src "ls180.v:3325.43-3325.159"
+ cell $and $and$ls180.v:3325$955
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3312$952_Y
- connect \B $eq$ls180.v:3312$953_Y
- connect \Y $and$ls180.v:3312$954_Y
+ connect \A $and$ls180.v:3325$953_Y
+ connect \B $eq$ls180.v:3325$954_Y
+ connect \Y $and$ls180.v:3325$955_Y
end
- attribute \src "ls180.v:3313.44-3313.108"
- cell $and $and$ls180.v:3313$956
+ attribute \src "ls180.v:3326.44-3326.108"
+ cell $and $and$ls180.v:3326$957
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3313$955_Y
- connect \Y $and$ls180.v:3313$956_Y
+ connect \B $not$ls180.v:3326$956_Y
+ connect \Y $and$ls180.v:3326$957_Y
end
- attribute \src "ls180.v:3313.43-3313.162"
- cell $and $and$ls180.v:3313$958
+ attribute \src "ls180.v:3326.43-3326.162"
+ cell $and $and$ls180.v:3326$959
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3313$956_Y
- connect \B $eq$ls180.v:3313$957_Y
- connect \Y $and$ls180.v:3313$958_Y
+ connect \A $and$ls180.v:3326$957_Y
+ connect \B $eq$ls180.v:3326$958_Y
+ connect \Y $and$ls180.v:3326$959_Y
end
- attribute \src "ls180.v:3315.40-3315.101"
- cell $and $and$ls180.v:3315$959
+ attribute \src "ls180.v:3328.40-3328.101"
+ cell $and $and$ls180.v:3328$960
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3315$959_Y
+ connect \Y $and$ls180.v:3328$960_Y
end
- attribute \src "ls180.v:3315.39-3315.155"
- cell $and $and$ls180.v:3315$961
+ attribute \src "ls180.v:3328.39-3328.155"
+ cell $and $and$ls180.v:3328$962
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3315$959_Y
- connect \B $eq$ls180.v:3315$960_Y
- connect \Y $and$ls180.v:3315$961_Y
+ connect \A $and$ls180.v:3328$960_Y
+ connect \B $eq$ls180.v:3328$961_Y
+ connect \Y $and$ls180.v:3328$962_Y
end
- attribute \src "ls180.v:3316.40-3316.104"
- cell $and $and$ls180.v:3316$963
+ attribute \src "ls180.v:3329.40-3329.104"
+ cell $and $and$ls180.v:3329$964
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3316$962_Y
- connect \Y $and$ls180.v:3316$963_Y
+ connect \B $not$ls180.v:3329$963_Y
+ connect \Y $and$ls180.v:3329$964_Y
end
- attribute \src "ls180.v:3316.39-3316.158"
- cell $and $and$ls180.v:3316$965
+ attribute \src "ls180.v:3329.39-3329.158"
+ cell $and $and$ls180.v:3329$966
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3316$963_Y
- connect \B $eq$ls180.v:3316$964_Y
- connect \Y $and$ls180.v:3316$965_Y
+ connect \A $and$ls180.v:3329$964_Y
+ connect \B $eq$ls180.v:3329$965_Y
+ connect \Y $and$ls180.v:3329$966_Y
end
- attribute \src "ls180.v:3318.50-3318.111"
- cell $and $and$ls180.v:3318$966
+ attribute \src "ls180.v:3331.50-3331.111"
+ cell $and $and$ls180.v:3331$967
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3318$966_Y
+ connect \Y $and$ls180.v:3331$967_Y
end
- attribute \src "ls180.v:3318.49-3318.165"
- cell $and $and$ls180.v:3318$968
+ attribute \src "ls180.v:3331.49-3331.165"
+ cell $and $and$ls180.v:3331$969
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3318$966_Y
- connect \B $eq$ls180.v:3318$967_Y
- connect \Y $and$ls180.v:3318$968_Y
+ connect \A $and$ls180.v:3331$967_Y
+ connect \B $eq$ls180.v:3331$968_Y
+ connect \Y $and$ls180.v:3331$969_Y
end
- attribute \src "ls180.v:3319.50-3319.114"
- cell $and $and$ls180.v:3319$970
+ attribute \src "ls180.v:3332.50-3332.114"
+ cell $and $and$ls180.v:3332$971
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3319$969_Y
- connect \Y $and$ls180.v:3319$970_Y
+ connect \B $not$ls180.v:3332$970_Y
+ connect \Y $and$ls180.v:3332$971_Y
end
- attribute \src "ls180.v:3319.49-3319.168"
- cell $and $and$ls180.v:3319$972
+ attribute \src "ls180.v:3332.49-3332.168"
+ cell $and $and$ls180.v:3332$973
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3319$970_Y
- connect \B $eq$ls180.v:3319$971_Y
- connect \Y $and$ls180.v:3319$972_Y
+ connect \A $and$ls180.v:3332$971_Y
+ connect \B $eq$ls180.v:3332$972_Y
+ connect \Y $and$ls180.v:3332$973_Y
end
- attribute \src "ls180.v:3321.43-3321.104"
- cell $and $and$ls180.v:3321$973
+ attribute \src "ls180.v:3334.43-3334.104"
+ cell $and $and$ls180.v:3334$974
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3321$973_Y
+ connect \Y $and$ls180.v:3334$974_Y
end
- attribute \src "ls180.v:3321.42-3321.159"
- cell $and $and$ls180.v:3321$975
+ attribute \src "ls180.v:3334.42-3334.159"
+ cell $and $and$ls180.v:3334$976
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3321$973_Y
- connect \B $eq$ls180.v:3321$974_Y
- connect \Y $and$ls180.v:3321$975_Y
+ connect \A $and$ls180.v:3334$974_Y
+ connect \B $eq$ls180.v:3334$975_Y
+ connect \Y $and$ls180.v:3334$976_Y
end
- attribute \src "ls180.v:3322.43-3322.107"
- cell $and $and$ls180.v:3322$977
+ attribute \src "ls180.v:3335.43-3335.107"
+ cell $and $and$ls180.v:3335$978
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3322$976_Y
- connect \Y $and$ls180.v:3322$977_Y
+ connect \B $not$ls180.v:3335$977_Y
+ connect \Y $and$ls180.v:3335$978_Y
end
- attribute \src "ls180.v:3322.42-3322.162"
- cell $and $and$ls180.v:3322$979
+ attribute \src "ls180.v:3335.42-3335.162"
+ cell $and $and$ls180.v:3335$980
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3322$977_Y
- connect \B $eq$ls180.v:3322$978_Y
- connect \Y $and$ls180.v:3322$979_Y
+ connect \A $and$ls180.v:3335$978_Y
+ connect \B $eq$ls180.v:3335$979_Y
+ connect \Y $and$ls180.v:3335$980_Y
end
- attribute \src "ls180.v:3324.43-3324.104"
- cell $and $and$ls180.v:3324$980
+ attribute \src "ls180.v:3337.43-3337.104"
+ cell $and $and$ls180.v:3337$981
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3324$980_Y
+ connect \Y $and$ls180.v:3337$981_Y
end
- attribute \src "ls180.v:3324.42-3324.159"
- cell $and $and$ls180.v:3324$982
+ attribute \src "ls180.v:3337.42-3337.159"
+ cell $and $and$ls180.v:3337$983
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3324$980_Y
- connect \B $eq$ls180.v:3324$981_Y
- connect \Y $and$ls180.v:3324$982_Y
+ connect \A $and$ls180.v:3337$981_Y
+ connect \B $eq$ls180.v:3337$982_Y
+ connect \Y $and$ls180.v:3337$983_Y
end
- attribute \src "ls180.v:3325.43-3325.107"
- cell $and $and$ls180.v:3325$984
+ attribute \src "ls180.v:3338.43-3338.107"
+ cell $and $and$ls180.v:3338$985
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3325$983_Y
- connect \Y $and$ls180.v:3325$984_Y
+ connect \B $not$ls180.v:3338$984_Y
+ connect \Y $and$ls180.v:3338$985_Y
end
- attribute \src "ls180.v:3325.42-3325.162"
- cell $and $and$ls180.v:3325$986
+ attribute \src "ls180.v:3338.42-3338.162"
+ cell $and $and$ls180.v:3338$987
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3325$984_Y
- connect \B $eq$ls180.v:3325$985_Y
- connect \Y $and$ls180.v:3325$986_Y
+ connect \A $and$ls180.v:3338$985_Y
+ connect \B $eq$ls180.v:3338$986_Y
+ connect \Y $and$ls180.v:3338$987_Y
end
- attribute \src "ls180.v:3327.43-3327.104"
- cell $and $and$ls180.v:3327$987
+ attribute \src "ls180.v:3340.43-3340.104"
+ cell $and $and$ls180.v:3340$988
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3327$987_Y
+ connect \Y $and$ls180.v:3340$988_Y
end
- attribute \src "ls180.v:3327.42-3327.159"
- cell $and $and$ls180.v:3327$989
+ attribute \src "ls180.v:3340.42-3340.159"
+ cell $and $and$ls180.v:3340$990
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3327$987_Y
- connect \B $eq$ls180.v:3327$988_Y
- connect \Y $and$ls180.v:3327$989_Y
+ connect \A $and$ls180.v:3340$988_Y
+ connect \B $eq$ls180.v:3340$989_Y
+ connect \Y $and$ls180.v:3340$990_Y
end
- attribute \src "ls180.v:3328.43-3328.107"
- cell $and $and$ls180.v:3328$991
+ attribute \src "ls180.v:3341.43-3341.107"
+ cell $and $and$ls180.v:3341$992
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3328$990_Y
- connect \Y $and$ls180.v:3328$991_Y
+ connect \B $not$ls180.v:3341$991_Y
+ connect \Y $and$ls180.v:3341$992_Y
end
- attribute \src "ls180.v:3328.42-3328.162"
- cell $and $and$ls180.v:3328$993
+ attribute \src "ls180.v:3341.42-3341.162"
+ cell $and $and$ls180.v:3341$994
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3328$991_Y
- connect \B $eq$ls180.v:3328$992_Y
- connect \Y $and$ls180.v:3328$993_Y
+ connect \A $and$ls180.v:3341$992_Y
+ connect \B $eq$ls180.v:3341$993_Y
+ connect \Y $and$ls180.v:3341$994_Y
end
- attribute \src "ls180.v:3330.43-3330.104"
- cell $and $and$ls180.v:3330$994
+ attribute \src "ls180.v:3343.43-3343.104"
+ cell $and $and$ls180.v:3343$995
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3330$994_Y
+ connect \Y $and$ls180.v:3343$995_Y
end
- attribute \src "ls180.v:3330.42-3330.159"
- cell $and $and$ls180.v:3330$996
+ attribute \src "ls180.v:3343.42-3343.159"
+ cell $and $and$ls180.v:3343$997
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3330$994_Y
- connect \B $eq$ls180.v:3330$995_Y
- connect \Y $and$ls180.v:3330$996_Y
+ connect \A $and$ls180.v:3343$995_Y
+ connect \B $eq$ls180.v:3343$996_Y
+ connect \Y $and$ls180.v:3343$997_Y
end
- attribute \src "ls180.v:3331.42-3331.162"
- cell $and $and$ls180.v:3331$1000
+ attribute \src "ls180.v:3344.42-3344.162"
+ cell $and $and$ls180.v:3344$1001
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3331$998_Y
- connect \B $eq$ls180.v:3331$999_Y
- connect \Y $and$ls180.v:3331$1000_Y
+ connect \A $and$ls180.v:3344$999_Y
+ connect \B $eq$ls180.v:3344$1000_Y
+ connect \Y $and$ls180.v:3344$1001_Y
end
- attribute \src "ls180.v:3331.43-3331.107"
- cell $and $and$ls180.v:3331$998
+ attribute \src "ls180.v:3344.43-3344.107"
+ cell $and $and$ls180.v:3344$999
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3331$997_Y
- connect \Y $and$ls180.v:3331$998_Y
+ connect \B $not$ls180.v:3344$998_Y
+ connect \Y $and$ls180.v:3344$999_Y
end
- attribute \src "ls180.v:3333.47-3333.108"
- cell $and $and$ls180.v:3333$1001
+ attribute \src "ls180.v:3346.47-3346.108"
+ cell $and $and$ls180.v:3346$1002
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3333$1001_Y
+ connect \Y $and$ls180.v:3346$1002_Y
end
- attribute \src "ls180.v:3333.46-3333.163"
- cell $and $and$ls180.v:3333$1003
+ attribute \src "ls180.v:3346.46-3346.163"
+ cell $and $and$ls180.v:3346$1004
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3333$1001_Y
- connect \B $eq$ls180.v:3333$1002_Y
- connect \Y $and$ls180.v:3333$1003_Y
+ connect \A $and$ls180.v:3346$1002_Y
+ connect \B $eq$ls180.v:3346$1003_Y
+ connect \Y $and$ls180.v:3346$1004_Y
end
- attribute \src "ls180.v:3334.47-3334.111"
- cell $and $and$ls180.v:3334$1005
+ attribute \src "ls180.v:3347.47-3347.111"
+ cell $and $and$ls180.v:3347$1006
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3334$1004_Y
- connect \Y $and$ls180.v:3334$1005_Y
+ connect \B $not$ls180.v:3347$1005_Y
+ connect \Y $and$ls180.v:3347$1006_Y
end
- attribute \src "ls180.v:3334.46-3334.166"
- cell $and $and$ls180.v:3334$1007
+ attribute \src "ls180.v:3347.46-3347.166"
+ cell $and $and$ls180.v:3347$1008
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3334$1005_Y
- connect \B $eq$ls180.v:3334$1006_Y
- connect \Y $and$ls180.v:3334$1007_Y
+ connect \A $and$ls180.v:3347$1006_Y
+ connect \B $eq$ls180.v:3347$1007_Y
+ connect \Y $and$ls180.v:3347$1008_Y
end
- attribute \src "ls180.v:3336.48-3336.109"
- cell $and $and$ls180.v:3336$1008
+ attribute \src "ls180.v:3349.48-3349.109"
+ cell $and $and$ls180.v:3349$1009
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3336$1008_Y
+ connect \Y $and$ls180.v:3349$1009_Y
end
- attribute \src "ls180.v:3336.47-3336.164"
- cell $and $and$ls180.v:3336$1010
+ attribute \src "ls180.v:3349.47-3349.164"
+ cell $and $and$ls180.v:3349$1011
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3336$1008_Y
- connect \B $eq$ls180.v:3336$1009_Y
- connect \Y $and$ls180.v:3336$1010_Y
+ connect \A $and$ls180.v:3349$1009_Y
+ connect \B $eq$ls180.v:3349$1010_Y
+ connect \Y $and$ls180.v:3349$1011_Y
end
- attribute \src "ls180.v:3337.48-3337.112"
- cell $and $and$ls180.v:3337$1012
+ attribute \src "ls180.v:3350.48-3350.112"
+ cell $and $and$ls180.v:3350$1013
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3337$1011_Y
- connect \Y $and$ls180.v:3337$1012_Y
+ connect \B $not$ls180.v:3350$1012_Y
+ connect \Y $and$ls180.v:3350$1013_Y
end
- attribute \src "ls180.v:3337.47-3337.167"
- cell $and $and$ls180.v:3337$1014
+ attribute \src "ls180.v:3350.47-3350.167"
+ cell $and $and$ls180.v:3350$1015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3337$1012_Y
- connect \B $eq$ls180.v:3337$1013_Y
- connect \Y $and$ls180.v:3337$1014_Y
+ connect \A $and$ls180.v:3350$1013_Y
+ connect \B $eq$ls180.v:3350$1014_Y
+ connect \Y $and$ls180.v:3350$1015_Y
end
- attribute \src "ls180.v:3339.47-3339.108"
- cell $and $and$ls180.v:3339$1015
+ attribute \src "ls180.v:3352.47-3352.108"
+ cell $and $and$ls180.v:3352$1016
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
connect \B \libresocsim_interface5_bank_bus_we
- connect \Y $and$ls180.v:3339$1015_Y
+ connect \Y $and$ls180.v:3352$1016_Y
end
- attribute \src "ls180.v:3339.46-3339.163"
- cell $and $and$ls180.v:3339$1017
+ attribute \src "ls180.v:3352.46-3352.163"
+ cell $and $and$ls180.v:3352$1018
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3339$1015_Y
- connect \B $eq$ls180.v:3339$1016_Y
- connect \Y $and$ls180.v:3339$1017_Y
+ connect \A $and$ls180.v:3352$1016_Y
+ connect \B $eq$ls180.v:3352$1017_Y
+ connect \Y $and$ls180.v:3352$1018_Y
end
- attribute \src "ls180.v:3340.47-3340.111"
- cell $and $and$ls180.v:3340$1019
+ attribute \src "ls180.v:3353.47-3353.111"
+ cell $and $and$ls180.v:3353$1020
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank5_sel
- connect \B $not$ls180.v:3340$1018_Y
- connect \Y $and$ls180.v:3340$1019_Y
+ connect \B $not$ls180.v:3353$1019_Y
+ connect \Y $and$ls180.v:3353$1020_Y
end
- attribute \src "ls180.v:3340.46-3340.166"
- cell $and $and$ls180.v:3340$1021
+ attribute \src "ls180.v:3353.46-3353.166"
+ cell $and $and$ls180.v:3353$1022
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3340$1019_Y
- connect \B $eq$ls180.v:3340$1020_Y
- connect \Y $and$ls180.v:3340$1021_Y
+ connect \A $and$ls180.v:3353$1020_Y
+ connect \B $eq$ls180.v:3353$1021_Y
+ connect \Y $and$ls180.v:3353$1022_Y
end
- attribute \src "ls180.v:3359.20-3359.81"
- cell $and $and$ls180.v:3359$1023
+ attribute \src "ls180.v:3372.20-3372.81"
+ cell $and $and$ls180.v:3372$1024
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3359$1023_Y
+ connect \Y $and$ls180.v:3372$1024_Y
end
- attribute \src "ls180.v:3359.19-3359.135"
- cell $and $and$ls180.v:3359$1025
+ attribute \src "ls180.v:3372.19-3372.135"
+ cell $and $and$ls180.v:3372$1026
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3359$1023_Y
- connect \B $eq$ls180.v:3359$1024_Y
- connect \Y $and$ls180.v:3359$1025_Y
+ connect \A $and$ls180.v:3372$1024_Y
+ connect \B $eq$ls180.v:3372$1025_Y
+ connect \Y $and$ls180.v:3372$1026_Y
end
- attribute \src "ls180.v:3360.20-3360.84"
- cell $and $and$ls180.v:3360$1027
+ attribute \src "ls180.v:3373.20-3373.84"
+ cell $and $and$ls180.v:3373$1028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3360$1026_Y
- connect \Y $and$ls180.v:3360$1027_Y
+ connect \B $not$ls180.v:3373$1027_Y
+ connect \Y $and$ls180.v:3373$1028_Y
end
- attribute \src "ls180.v:3360.19-3360.138"
- cell $and $and$ls180.v:3360$1029
+ attribute \src "ls180.v:3373.19-3373.138"
+ cell $and $and$ls180.v:3373$1030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3360$1027_Y
- connect \B $eq$ls180.v:3360$1028_Y
- connect \Y $and$ls180.v:3360$1029_Y
+ connect \A $and$ls180.v:3373$1028_Y
+ connect \B $eq$ls180.v:3373$1029_Y
+ connect \Y $and$ls180.v:3373$1030_Y
end
- attribute \src "ls180.v:3362.43-3362.104"
- cell $and $and$ls180.v:3362$1030
+ attribute \src "ls180.v:3375.43-3375.104"
+ cell $and $and$ls180.v:3375$1031
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3362$1030_Y
+ connect \Y $and$ls180.v:3375$1031_Y
end
- attribute \src "ls180.v:3362.42-3362.158"
- cell $and $and$ls180.v:3362$1032
+ attribute \src "ls180.v:3375.42-3375.158"
+ cell $and $and$ls180.v:3375$1033
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3362$1030_Y
- connect \B $eq$ls180.v:3362$1031_Y
- connect \Y $and$ls180.v:3362$1032_Y
+ connect \A $and$ls180.v:3375$1031_Y
+ connect \B $eq$ls180.v:3375$1032_Y
+ connect \Y $and$ls180.v:3375$1033_Y
end
- attribute \src "ls180.v:3363.43-3363.107"
- cell $and $and$ls180.v:3363$1034
+ attribute \src "ls180.v:3376.43-3376.107"
+ cell $and $and$ls180.v:3376$1035
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3363$1033_Y
- connect \Y $and$ls180.v:3363$1034_Y
+ connect \B $not$ls180.v:3376$1034_Y
+ connect \Y $and$ls180.v:3376$1035_Y
end
- attribute \src "ls180.v:3363.42-3363.161"
- cell $and $and$ls180.v:3363$1036
+ attribute \src "ls180.v:3376.42-3376.161"
+ cell $and $and$ls180.v:3376$1037
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3363$1034_Y
- connect \B $eq$ls180.v:3363$1035_Y
- connect \Y $and$ls180.v:3363$1036_Y
+ connect \A $and$ls180.v:3376$1035_Y
+ connect \B $eq$ls180.v:3376$1036_Y
+ connect \Y $and$ls180.v:3376$1037_Y
end
- attribute \src "ls180.v:3365.44-3365.105"
- cell $and $and$ls180.v:3365$1037
+ attribute \src "ls180.v:3378.44-3378.105"
+ cell $and $and$ls180.v:3378$1038
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3365$1037_Y
+ connect \Y $and$ls180.v:3378$1038_Y
end
- attribute \src "ls180.v:3365.43-3365.159"
- cell $and $and$ls180.v:3365$1039
+ attribute \src "ls180.v:3378.43-3378.159"
+ cell $and $and$ls180.v:3378$1040
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3365$1037_Y
- connect \B $eq$ls180.v:3365$1038_Y
- connect \Y $and$ls180.v:3365$1039_Y
+ connect \A $and$ls180.v:3378$1038_Y
+ connect \B $eq$ls180.v:3378$1039_Y
+ connect \Y $and$ls180.v:3378$1040_Y
end
- attribute \src "ls180.v:3366.44-3366.108"
- cell $and $and$ls180.v:3366$1041
+ attribute \src "ls180.v:3379.44-3379.108"
+ cell $and $and$ls180.v:3379$1042
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3366$1040_Y
- connect \Y $and$ls180.v:3366$1041_Y
+ connect \B $not$ls180.v:3379$1041_Y
+ connect \Y $and$ls180.v:3379$1042_Y
end
- attribute \src "ls180.v:3366.43-3366.162"
- cell $and $and$ls180.v:3366$1043
+ attribute \src "ls180.v:3379.43-3379.162"
+ cell $and $and$ls180.v:3379$1044
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3366$1041_Y
- connect \B $eq$ls180.v:3366$1042_Y
- connect \Y $and$ls180.v:3366$1043_Y
+ connect \A $and$ls180.v:3379$1042_Y
+ connect \B $eq$ls180.v:3379$1043_Y
+ connect \Y $and$ls180.v:3379$1044_Y
end
- attribute \src "ls180.v:3368.35-3368.96"
- cell $and $and$ls180.v:3368$1044
+ attribute \src "ls180.v:3381.35-3381.96"
+ cell $and $and$ls180.v:3381$1045
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3368$1044_Y
+ connect \Y $and$ls180.v:3381$1045_Y
end
- attribute \src "ls180.v:3368.34-3368.150"
- cell $and $and$ls180.v:3368$1046
+ attribute \src "ls180.v:3381.34-3381.150"
+ cell $and $and$ls180.v:3381$1047
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3368$1044_Y
- connect \B $eq$ls180.v:3368$1045_Y
- connect \Y $and$ls180.v:3368$1046_Y
+ connect \A $and$ls180.v:3381$1045_Y
+ connect \B $eq$ls180.v:3381$1046_Y
+ connect \Y $and$ls180.v:3381$1047_Y
end
- attribute \src "ls180.v:3369.35-3369.99"
- cell $and $and$ls180.v:3369$1048
+ attribute \src "ls180.v:3382.35-3382.99"
+ cell $and $and$ls180.v:3382$1049
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3369$1047_Y
- connect \Y $and$ls180.v:3369$1048_Y
+ connect \B $not$ls180.v:3382$1048_Y
+ connect \Y $and$ls180.v:3382$1049_Y
end
- attribute \src "ls180.v:3369.34-3369.153"
- cell $and $and$ls180.v:3369$1050
+ attribute \src "ls180.v:3382.34-3382.153"
+ cell $and $and$ls180.v:3382$1051
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3369$1048_Y
- connect \B $eq$ls180.v:3369$1049_Y
- connect \Y $and$ls180.v:3369$1050_Y
+ connect \A $and$ls180.v:3382$1049_Y
+ connect \B $eq$ls180.v:3382$1050_Y
+ connect \Y $and$ls180.v:3382$1051_Y
end
- attribute \src "ls180.v:3371.36-3371.97"
- cell $and $and$ls180.v:3371$1051
+ attribute \src "ls180.v:3384.36-3384.97"
+ cell $and $and$ls180.v:3384$1052
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3371$1051_Y
+ connect \Y $and$ls180.v:3384$1052_Y
end
- attribute \src "ls180.v:3371.35-3371.151"
- cell $and $and$ls180.v:3371$1053
+ attribute \src "ls180.v:3384.35-3384.151"
+ cell $and $and$ls180.v:3384$1054
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3371$1051_Y
- connect \B $eq$ls180.v:3371$1052_Y
- connect \Y $and$ls180.v:3371$1053_Y
+ connect \A $and$ls180.v:3384$1052_Y
+ connect \B $eq$ls180.v:3384$1053_Y
+ connect \Y $and$ls180.v:3384$1054_Y
end
- attribute \src "ls180.v:3372.36-3372.100"
- cell $and $and$ls180.v:3372$1055
+ attribute \src "ls180.v:3385.36-3385.100"
+ cell $and $and$ls180.v:3385$1056
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3372$1054_Y
- connect \Y $and$ls180.v:3372$1055_Y
+ connect \B $not$ls180.v:3385$1055_Y
+ connect \Y $and$ls180.v:3385$1056_Y
end
- attribute \src "ls180.v:3372.35-3372.154"
- cell $and $and$ls180.v:3372$1057
+ attribute \src "ls180.v:3385.35-3385.154"
+ cell $and $and$ls180.v:3385$1058
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3372$1055_Y
- connect \B $eq$ls180.v:3372$1056_Y
- connect \Y $and$ls180.v:3372$1057_Y
+ connect \A $and$ls180.v:3385$1056_Y
+ connect \B $eq$ls180.v:3385$1057_Y
+ connect \Y $and$ls180.v:3385$1058_Y
end
- attribute \src "ls180.v:3374.47-3374.108"
- cell $and $and$ls180.v:3374$1058
+ attribute \src "ls180.v:3387.47-3387.108"
+ cell $and $and$ls180.v:3387$1059
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3374$1058_Y
+ connect \Y $and$ls180.v:3387$1059_Y
end
- attribute \src "ls180.v:3374.46-3374.162"
- cell $and $and$ls180.v:3374$1060
+ attribute \src "ls180.v:3387.46-3387.162"
+ cell $and $and$ls180.v:3387$1061
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3374$1058_Y
- connect \B $eq$ls180.v:3374$1059_Y
- connect \Y $and$ls180.v:3374$1060_Y
+ connect \A $and$ls180.v:3387$1059_Y
+ connect \B $eq$ls180.v:3387$1060_Y
+ connect \Y $and$ls180.v:3387$1061_Y
end
- attribute \src "ls180.v:3375.47-3375.111"
- cell $and $and$ls180.v:3375$1062
+ attribute \src "ls180.v:3388.47-3388.111"
+ cell $and $and$ls180.v:3388$1063
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3375$1061_Y
- connect \Y $and$ls180.v:3375$1062_Y
+ connect \B $not$ls180.v:3388$1062_Y
+ connect \Y $and$ls180.v:3388$1063_Y
end
- attribute \src "ls180.v:3375.46-3375.165"
- cell $and $and$ls180.v:3375$1064
+ attribute \src "ls180.v:3388.46-3388.165"
+ cell $and $and$ls180.v:3388$1065
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3375$1062_Y
- connect \B $eq$ls180.v:3375$1063_Y
- connect \Y $and$ls180.v:3375$1064_Y
+ connect \A $and$ls180.v:3388$1063_Y
+ connect \B $eq$ls180.v:3388$1064_Y
+ connect \Y $and$ls180.v:3388$1065_Y
end
- attribute \src "ls180.v:3377.44-3377.105"
- cell $and $and$ls180.v:3377$1065
+ attribute \src "ls180.v:3390.44-3390.105"
+ cell $and $and$ls180.v:3390$1066
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3377$1065_Y
+ connect \Y $and$ls180.v:3390$1066_Y
end
- attribute \src "ls180.v:3377.43-3377.159"
- cell $and $and$ls180.v:3377$1067
+ attribute \src "ls180.v:3390.43-3390.159"
+ cell $and $and$ls180.v:3390$1068
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3377$1065_Y
- connect \B $eq$ls180.v:3377$1066_Y
- connect \Y $and$ls180.v:3377$1067_Y
+ connect \A $and$ls180.v:3390$1066_Y
+ connect \B $eq$ls180.v:3390$1067_Y
+ connect \Y $and$ls180.v:3390$1068_Y
end
- attribute \src "ls180.v:3378.44-3378.108"
- cell $and $and$ls180.v:3378$1069
+ attribute \src "ls180.v:3391.44-3391.108"
+ cell $and $and$ls180.v:3391$1070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3378$1068_Y
- connect \Y $and$ls180.v:3378$1069_Y
+ connect \B $not$ls180.v:3391$1069_Y
+ connect \Y $and$ls180.v:3391$1070_Y
end
- attribute \src "ls180.v:3378.43-3378.162"
- cell $and $and$ls180.v:3378$1071
+ attribute \src "ls180.v:3391.43-3391.162"
+ cell $and $and$ls180.v:3391$1072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3378$1069_Y
- connect \B $eq$ls180.v:3378$1070_Y
- connect \Y $and$ls180.v:3378$1071_Y
+ connect \A $and$ls180.v:3391$1070_Y
+ connect \B $eq$ls180.v:3391$1071_Y
+ connect \Y $and$ls180.v:3391$1072_Y
end
- attribute \src "ls180.v:3380.43-3380.104"
- cell $and $and$ls180.v:3380$1072
+ attribute \src "ls180.v:3393.43-3393.104"
+ cell $and $and$ls180.v:3393$1073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
connect \B \libresocsim_interface6_bank_bus_we
- connect \Y $and$ls180.v:3380$1072_Y
+ connect \Y $and$ls180.v:3393$1073_Y
end
- attribute \src "ls180.v:3380.42-3380.158"
- cell $and $and$ls180.v:3380$1074
+ attribute \src "ls180.v:3393.42-3393.158"
+ cell $and $and$ls180.v:3393$1075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3380$1072_Y
- connect \B $eq$ls180.v:3380$1073_Y
- connect \Y $and$ls180.v:3380$1074_Y
+ connect \A $and$ls180.v:3393$1073_Y
+ connect \B $eq$ls180.v:3393$1074_Y
+ connect \Y $and$ls180.v:3393$1075_Y
end
- attribute \src "ls180.v:3381.43-3381.107"
- cell $and $and$ls180.v:3381$1076
+ attribute \src "ls180.v:3394.43-3394.107"
+ cell $and $and$ls180.v:3394$1077
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank6_sel
- connect \B $not$ls180.v:3381$1075_Y
- connect \Y $and$ls180.v:3381$1076_Y
+ connect \B $not$ls180.v:3394$1076_Y
+ connect \Y $and$ls180.v:3394$1077_Y
end
- attribute \src "ls180.v:3381.42-3381.161"
- cell $and $and$ls180.v:3381$1078
+ attribute \src "ls180.v:3394.42-3394.161"
+ cell $and $and$ls180.v:3394$1079
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3381$1076_Y
- connect \B $eq$ls180.v:3381$1077_Y
- connect \Y $and$ls180.v:3381$1078_Y
+ connect \A $and$ls180.v:3394$1077_Y
+ connect \B $eq$ls180.v:3394$1078_Y
+ connect \Y $and$ls180.v:3394$1079_Y
end
- attribute \src "ls180.v:3393.49-3393.110"
- cell $and $and$ls180.v:3393$1080
+ attribute \src "ls180.v:3406.49-3406.110"
+ cell $and $and$ls180.v:3406$1081
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
connect \B \libresocsim_interface7_bank_bus_we
- connect \Y $and$ls180.v:3393$1080_Y
+ connect \Y $and$ls180.v:3406$1081_Y
end
- attribute \src "ls180.v:3393.48-3393.164"
- cell $and $and$ls180.v:3393$1082
+ attribute \src "ls180.v:3406.48-3406.164"
+ cell $and $and$ls180.v:3406$1083
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3393$1080_Y
- connect \B $eq$ls180.v:3393$1081_Y
- connect \Y $and$ls180.v:3393$1082_Y
+ connect \A $and$ls180.v:3406$1081_Y
+ connect \B $eq$ls180.v:3406$1082_Y
+ connect \Y $and$ls180.v:3406$1083_Y
end
- attribute \src "ls180.v:3394.49-3394.113"
- cell $and $and$ls180.v:3394$1084
+ attribute \src "ls180.v:3407.49-3407.113"
+ cell $and $and$ls180.v:3407$1085
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
- connect \B $not$ls180.v:3394$1083_Y
- connect \Y $and$ls180.v:3394$1084_Y
+ connect \B $not$ls180.v:3407$1084_Y
+ connect \Y $and$ls180.v:3407$1085_Y
end
- attribute \src "ls180.v:3394.48-3394.167"
- cell $and $and$ls180.v:3394$1086
+ attribute \src "ls180.v:3407.48-3407.167"
+ cell $and $and$ls180.v:3407$1087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3394$1084_Y
- connect \B $eq$ls180.v:3394$1085_Y
- connect \Y $and$ls180.v:3394$1086_Y
+ connect \A $and$ls180.v:3407$1085_Y
+ connect \B $eq$ls180.v:3407$1086_Y
+ connect \Y $and$ls180.v:3407$1087_Y
end
- attribute \src "ls180.v:3396.49-3396.110"
- cell $and $and$ls180.v:3396$1087
+ attribute \src "ls180.v:3409.49-3409.110"
+ cell $and $and$ls180.v:3409$1088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
connect \B \libresocsim_interface7_bank_bus_we
- connect \Y $and$ls180.v:3396$1087_Y
+ connect \Y $and$ls180.v:3409$1088_Y
end
- attribute \src "ls180.v:3396.48-3396.164"
- cell $and $and$ls180.v:3396$1089
+ attribute \src "ls180.v:3409.48-3409.164"
+ cell $and $and$ls180.v:3409$1090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3396$1087_Y
- connect \B $eq$ls180.v:3396$1088_Y
- connect \Y $and$ls180.v:3396$1089_Y
+ connect \A $and$ls180.v:3409$1088_Y
+ connect \B $eq$ls180.v:3409$1089_Y
+ connect \Y $and$ls180.v:3409$1090_Y
end
- attribute \src "ls180.v:3397.49-3397.113"
- cell $and $and$ls180.v:3397$1091
+ attribute \src "ls180.v:3410.49-3410.113"
+ cell $and $and$ls180.v:3410$1092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
- connect \B $not$ls180.v:3397$1090_Y
- connect \Y $and$ls180.v:3397$1091_Y
+ connect \B $not$ls180.v:3410$1091_Y
+ connect \Y $and$ls180.v:3410$1092_Y
end
- attribute \src "ls180.v:3397.48-3397.167"
- cell $and $and$ls180.v:3397$1093
+ attribute \src "ls180.v:3410.48-3410.167"
+ cell $and $and$ls180.v:3410$1094
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3397$1091_Y
- connect \B $eq$ls180.v:3397$1092_Y
- connect \Y $and$ls180.v:3397$1093_Y
+ connect \A $and$ls180.v:3410$1092_Y
+ connect \B $eq$ls180.v:3410$1093_Y
+ connect \Y $and$ls180.v:3410$1094_Y
end
- attribute \src "ls180.v:3399.49-3399.110"
- cell $and $and$ls180.v:3399$1094
+ attribute \src "ls180.v:3412.49-3412.110"
+ cell $and $and$ls180.v:3412$1095
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
connect \B \libresocsim_interface7_bank_bus_we
- connect \Y $and$ls180.v:3399$1094_Y
+ connect \Y $and$ls180.v:3412$1095_Y
end
- attribute \src "ls180.v:3399.48-3399.164"
- cell $and $and$ls180.v:3399$1096
+ attribute \src "ls180.v:3412.48-3412.164"
+ cell $and $and$ls180.v:3412$1097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3399$1094_Y
- connect \B $eq$ls180.v:3399$1095_Y
- connect \Y $and$ls180.v:3399$1096_Y
+ connect \A $and$ls180.v:3412$1095_Y
+ connect \B $eq$ls180.v:3412$1096_Y
+ connect \Y $and$ls180.v:3412$1097_Y
end
- attribute \src "ls180.v:3400.49-3400.113"
- cell $and $and$ls180.v:3400$1098
+ attribute \src "ls180.v:3413.49-3413.113"
+ cell $and $and$ls180.v:3413$1099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
- connect \B $not$ls180.v:3400$1097_Y
- connect \Y $and$ls180.v:3400$1098_Y
+ connect \B $not$ls180.v:3413$1098_Y
+ connect \Y $and$ls180.v:3413$1099_Y
end
- attribute \src "ls180.v:3400.48-3400.167"
- cell $and $and$ls180.v:3400$1100
+ attribute \src "ls180.v:3413.48-3413.167"
+ cell $and $and$ls180.v:3413$1101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3400$1098_Y
- connect \B $eq$ls180.v:3400$1099_Y
- connect \Y $and$ls180.v:3400$1100_Y
+ connect \A $and$ls180.v:3413$1099_Y
+ connect \B $eq$ls180.v:3413$1100_Y
+ connect \Y $and$ls180.v:3413$1101_Y
end
- attribute \src "ls180.v:3402.49-3402.110"
- cell $and $and$ls180.v:3402$1101
+ attribute \src "ls180.v:3415.49-3415.110"
+ cell $and $and$ls180.v:3415$1102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
connect \B \libresocsim_interface7_bank_bus_we
- connect \Y $and$ls180.v:3402$1101_Y
+ connect \Y $and$ls180.v:3415$1102_Y
end
- attribute \src "ls180.v:3402.48-3402.164"
- cell $and $and$ls180.v:3402$1103
+ attribute \src "ls180.v:3415.48-3415.164"
+ cell $and $and$ls180.v:3415$1104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3402$1101_Y
- connect \B $eq$ls180.v:3402$1102_Y
- connect \Y $and$ls180.v:3402$1103_Y
+ connect \A $and$ls180.v:3415$1102_Y
+ connect \B $eq$ls180.v:3415$1103_Y
+ connect \Y $and$ls180.v:3415$1104_Y
end
- attribute \src "ls180.v:3403.49-3403.113"
- cell $and $and$ls180.v:3403$1105
+ attribute \src "ls180.v:3416.49-3416.113"
+ cell $and $and$ls180.v:3416$1106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_csrbank7_sel
- connect \B $not$ls180.v:3403$1104_Y
- connect \Y $and$ls180.v:3403$1105_Y
+ connect \B $not$ls180.v:3416$1105_Y
+ connect \Y $and$ls180.v:3416$1106_Y
end
- attribute \src "ls180.v:3403.48-3403.167"
- cell $and $and$ls180.v:3403$1107
+ attribute \src "ls180.v:3416.48-3416.167"
+ cell $and $and$ls180.v:3416$1108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3403$1105_Y
- connect \B $eq$ls180.v:3403$1106_Y
- connect \Y $and$ls180.v:3403$1107_Y
+ connect \A $and$ls180.v:3416$1106_Y
+ connect \B $eq$ls180.v:3416$1107_Y
+ connect \Y $and$ls180.v:3416$1108_Y
end
- attribute \src "ls180.v:3763.96-3763.165"
- cell $and $and$ls180.v:3763$1138
+ attribute \src "ls180.v:3776.96-3776.165"
+ cell $and $and$ls180.v:3776$1139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3763$1137_Y
- connect \Y $and$ls180.v:3763$1138_Y
+ connect \B $eq$ls180.v:3776$1138_Y
+ connect \Y $and$ls180.v:3776$1139_Y
end
- attribute \src "ls180.v:3763.171-3763.240"
- cell $and $and$ls180.v:3763$1141
+ attribute \src "ls180.v:3776.171-3776.240"
+ cell $and $and$ls180.v:3776$1142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3763$1140_Y
- connect \Y $and$ls180.v:3763$1141_Y
+ connect \B $eq$ls180.v:3776$1141_Y
+ connect \Y $and$ls180.v:3776$1142_Y
end
- attribute \src "ls180.v:3763.246-3763.315"
- cell $and $and$ls180.v:3763$1144
+ attribute \src "ls180.v:3776.246-3776.315"
+ cell $and $and$ls180.v:3776$1145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3763$1143_Y
- connect \Y $and$ls180.v:3763$1144_Y
+ connect \B $eq$ls180.v:3776$1144_Y
+ connect \Y $and$ls180.v:3776$1145_Y
end
- attribute \src "ls180.v:3763.27-3763.318"
- cell $and $and$ls180.v:3763$1147
+ attribute \src "ls180.v:3776.27-3776.318"
+ cell $and $and$ls180.v:3776$1148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3763$1136_Y
- connect \B $not$ls180.v:3763$1146_Y
- connect \Y $and$ls180.v:3763$1147_Y
+ connect \A $eq$ls180.v:3776$1137_Y
+ connect \B $not$ls180.v:3776$1147_Y
+ connect \Y $and$ls180.v:3776$1148_Y
end
- attribute \src "ls180.v:3763.26-3763.336"
- cell $and $and$ls180.v:3763$1148
+ attribute \src "ls180.v:3776.26-3776.336"
+ cell $and $and$ls180.v:3776$1149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3763$1147_Y
+ connect \A $and$ls180.v:3776$1148_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:3763$1148_Y
+ connect \Y $and$ls180.v:3776$1149_Y
end
- attribute \src "ls180.v:3787.96-3787.165"
- cell $and $and$ls180.v:3787$1154
+ attribute \src "ls180.v:3800.96-3800.165"
+ cell $and $and$ls180.v:3800$1155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3787$1153_Y
- connect \Y $and$ls180.v:3787$1154_Y
+ connect \B $eq$ls180.v:3800$1154_Y
+ connect \Y $and$ls180.v:3800$1155_Y
end
- attribute \src "ls180.v:3787.171-3787.240"
- cell $and $and$ls180.v:3787$1157
+ attribute \src "ls180.v:3800.171-3800.240"
+ cell $and $and$ls180.v:3800$1158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3787$1156_Y
- connect \Y $and$ls180.v:3787$1157_Y
+ connect \B $eq$ls180.v:3800$1157_Y
+ connect \Y $and$ls180.v:3800$1158_Y
end
- attribute \src "ls180.v:3787.246-3787.315"
- cell $and $and$ls180.v:3787$1160
+ attribute \src "ls180.v:3800.246-3800.315"
+ cell $and $and$ls180.v:3800$1161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3787$1159_Y
- connect \Y $and$ls180.v:3787$1160_Y
+ connect \B $eq$ls180.v:3800$1160_Y
+ connect \Y $and$ls180.v:3800$1161_Y
end
- attribute \src "ls180.v:3787.27-3787.318"
- cell $and $and$ls180.v:3787$1163
+ attribute \src "ls180.v:3800.27-3800.318"
+ cell $and $and$ls180.v:3800$1164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3787$1152_Y
- connect \B $not$ls180.v:3787$1162_Y
- connect \Y $and$ls180.v:3787$1163_Y
+ connect \A $eq$ls180.v:3800$1153_Y
+ connect \B $not$ls180.v:3800$1163_Y
+ connect \Y $and$ls180.v:3800$1164_Y
end
- attribute \src "ls180.v:3787.26-3787.336"
- cell $and $and$ls180.v:3787$1164
+ attribute \src "ls180.v:3800.26-3800.336"
+ cell $and $and$ls180.v:3800$1165
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3787$1163_Y
+ connect \A $and$ls180.v:3800$1164_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:3787$1164_Y
+ connect \Y $and$ls180.v:3800$1165_Y
end
- attribute \src "ls180.v:3811.96-3811.165"
- cell $and $and$ls180.v:3811$1170
+ attribute \src "ls180.v:3824.96-3824.165"
+ cell $and $and$ls180.v:3824$1171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3811$1169_Y
- connect \Y $and$ls180.v:3811$1170_Y
+ connect \B $eq$ls180.v:3824$1170_Y
+ connect \Y $and$ls180.v:3824$1171_Y
end
- attribute \src "ls180.v:3811.171-3811.240"
- cell $and $and$ls180.v:3811$1173
+ attribute \src "ls180.v:3824.171-3824.240"
+ cell $and $and$ls180.v:3824$1174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3811$1172_Y
- connect \Y $and$ls180.v:3811$1173_Y
+ connect \B $eq$ls180.v:3824$1173_Y
+ connect \Y $and$ls180.v:3824$1174_Y
end
- attribute \src "ls180.v:3811.246-3811.315"
- cell $and $and$ls180.v:3811$1176
+ attribute \src "ls180.v:3824.246-3824.315"
+ cell $and $and$ls180.v:3824$1177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \B $eq$ls180.v:3811$1175_Y
- connect \Y $and$ls180.v:3811$1176_Y
+ connect \B $eq$ls180.v:3824$1176_Y
+ connect \Y $and$ls180.v:3824$1177_Y
end
- attribute \src "ls180.v:3811.27-3811.318"
- cell $and $and$ls180.v:3811$1179
+ attribute \src "ls180.v:3824.27-3824.318"
+ cell $and $and$ls180.v:3824$1180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3811$1168_Y
- connect \B $not$ls180.v:3811$1178_Y
- connect \Y $and$ls180.v:3811$1179_Y
+ connect \A $eq$ls180.v:3824$1169_Y
+ connect \B $not$ls180.v:3824$1179_Y
+ connect \Y $and$ls180.v:3824$1180_Y
end
- attribute \src "ls180.v:3811.26-3811.336"
- cell $and $and$ls180.v:3811$1180
+ attribute \src "ls180.v:3824.26-3824.336"
+ cell $and $and$ls180.v:3824$1181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3811$1179_Y
+ connect \A $and$ls180.v:3824$1180_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:3811$1180_Y
+ connect \Y $and$ls180.v:3824$1181_Y
end
- attribute \src "ls180.v:3835.96-3835.165"
- cell $and $and$ls180.v:3835$1186
+ attribute \src "ls180.v:3848.96-3848.165"
+ cell $and $and$ls180.v:3848$1187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \B $eq$ls180.v:3835$1185_Y
- connect \Y $and$ls180.v:3835$1186_Y
+ connect \B $eq$ls180.v:3848$1186_Y
+ connect \Y $and$ls180.v:3848$1187_Y
end
- attribute \src "ls180.v:3835.171-3835.240"
- cell $and $and$ls180.v:3835$1189
+ attribute \src "ls180.v:3848.171-3848.240"
+ cell $and $and$ls180.v:3848$1190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \B $eq$ls180.v:3835$1188_Y
- connect \Y $and$ls180.v:3835$1189_Y
+ connect \B $eq$ls180.v:3848$1189_Y
+ connect \Y $and$ls180.v:3848$1190_Y
end
- attribute \src "ls180.v:3835.246-3835.315"
- cell $and $and$ls180.v:3835$1192
+ attribute \src "ls180.v:3848.246-3848.315"
+ cell $and $and$ls180.v:3848$1193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \B $eq$ls180.v:3835$1191_Y
- connect \Y $and$ls180.v:3835$1192_Y
+ connect \B $eq$ls180.v:3848$1192_Y
+ connect \Y $and$ls180.v:3848$1193_Y
end
- attribute \src "ls180.v:3835.27-3835.318"
- cell $and $and$ls180.v:3835$1195
+ attribute \src "ls180.v:3848.27-3848.318"
+ cell $and $and$ls180.v:3848$1196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:3835$1184_Y
- connect \B $not$ls180.v:3835$1194_Y
- connect \Y $and$ls180.v:3835$1195_Y
+ connect \A $eq$ls180.v:3848$1185_Y
+ connect \B $not$ls180.v:3848$1195_Y
+ connect \Y $and$ls180.v:3848$1196_Y
end
- attribute \src "ls180.v:3835.26-3835.336"
- cell $and $and$ls180.v:3835$1196
+ attribute \src "ls180.v:3848.26-3848.336"
+ cell $and $and$ls180.v:3848$1197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3835$1195_Y
+ connect \A $and$ls180.v:3848$1196_Y
connect \B \port_cmd_valid
- connect \Y $and$ls180.v:3835$1196_Y
+ connect \Y $and$ls180.v:3848$1197_Y
end
- attribute \src "ls180.v:3992.22-3992.77"
- cell $and $and$ls180.v:3992$1208
+ attribute \src "ls180.v:4005.22-4005.77"
+ cell $and $and$ls180.v:4005$1209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3992$1208_Y
+ connect \Y $and$ls180.v:4005$1209_Y
end
- attribute \src "ls180.v:3992.21-3992.113"
- cell $and $and$ls180.v:3992$1209
+ attribute \src "ls180.v:4005.21-4005.113"
+ cell $and $and$ls180.v:4005$1210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3992$1208_Y
+ connect \A $and$ls180.v:4005$1209_Y
connect \B \sdram_choose_req_cmd_payload_cas
- connect \Y $and$ls180.v:3992$1209_Y
+ connect \Y $and$ls180.v:4005$1210_Y
end
- attribute \src "ls180.v:3995.22-3995.77"
- cell $and $and$ls180.v:3995$1210
+ attribute \src "ls180.v:4008.22-4008.77"
+ cell $and $and$ls180.v:4008$1211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:3995$1210_Y
+ connect \Y $and$ls180.v:4008$1211_Y
end
- attribute \src "ls180.v:3995.21-3995.113"
- cell $and $and$ls180.v:3995$1211
+ attribute \src "ls180.v:4008.21-4008.113"
+ cell $and $and$ls180.v:4008$1212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3995$1210_Y
+ connect \A $and$ls180.v:4008$1211_Y
connect \B \sdram_choose_req_cmd_payload_cas
- connect \Y $and$ls180.v:3995$1211_Y
+ connect \Y $and$ls180.v:4008$1212_Y
end
- attribute \src "ls180.v:3998.22-3998.55"
- cell $and $and$ls180.v:3998$1212
+ attribute \src "ls180.v:4011.22-4011.55"
+ cell $and $and$ls180.v:4011$1213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_cmd_valid
connect \B \sdram_cmd_ready
- connect \Y $and$ls180.v:3998$1212_Y
+ connect \Y $and$ls180.v:4011$1213_Y
end
- attribute \src "ls180.v:3998.21-3998.80"
- cell $and $and$ls180.v:3998$1213
+ attribute \src "ls180.v:4011.21-4011.80"
+ cell $and $and$ls180.v:4011$1214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:3998$1212_Y
+ connect \A $and$ls180.v:4011$1213_Y
connect \B \sdram_cmd_payload_cas
- connect \Y $and$ls180.v:3998$1213_Y
+ connect \Y $and$ls180.v:4011$1214_Y
end
- attribute \src "ls180.v:4009.22-4009.77"
- cell $and $and$ls180.v:4009$1215
+ attribute \src "ls180.v:4022.22-4022.77"
+ cell $and $and$ls180.v:4022$1216
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4009$1215_Y
+ connect \Y $and$ls180.v:4022$1216_Y
end
- attribute \src "ls180.v:4009.21-4009.113"
- cell $and $and$ls180.v:4009$1216
+ attribute \src "ls180.v:4022.21-4022.113"
+ cell $and $and$ls180.v:4022$1217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4009$1215_Y
+ connect \A $and$ls180.v:4022$1216_Y
connect \B \sdram_choose_req_cmd_payload_ras
- connect \Y $and$ls180.v:4009$1216_Y
+ connect \Y $and$ls180.v:4022$1217_Y
end
- attribute \src "ls180.v:4012.22-4012.77"
- cell $and $and$ls180.v:4012$1217
+ attribute \src "ls180.v:4025.22-4025.77"
+ cell $and $and$ls180.v:4025$1218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4012$1217_Y
+ connect \Y $and$ls180.v:4025$1218_Y
end
- attribute \src "ls180.v:4012.21-4012.113"
- cell $and $and$ls180.v:4012$1218
+ attribute \src "ls180.v:4025.21-4025.113"
+ cell $and $and$ls180.v:4025$1219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4012$1217_Y
+ connect \A $and$ls180.v:4025$1218_Y
connect \B \sdram_choose_req_cmd_payload_ras
- connect \Y $and$ls180.v:4012$1218_Y
+ connect \Y $and$ls180.v:4025$1219_Y
end
- attribute \src "ls180.v:4015.22-4015.55"
- cell $and $and$ls180.v:4015$1219
+ attribute \src "ls180.v:4028.22-4028.55"
+ cell $and $and$ls180.v:4028$1220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_cmd_valid
connect \B \sdram_cmd_ready
- connect \Y $and$ls180.v:4015$1219_Y
+ connect \Y $and$ls180.v:4028$1220_Y
end
- attribute \src "ls180.v:4015.21-4015.80"
- cell $and $and$ls180.v:4015$1220
+ attribute \src "ls180.v:4028.21-4028.80"
+ cell $and $and$ls180.v:4028$1221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4015$1219_Y
+ connect \A $and$ls180.v:4028$1220_Y
connect \B \sdram_cmd_payload_ras
- connect \Y $and$ls180.v:4015$1220_Y
+ connect \Y $and$ls180.v:4028$1221_Y
end
- attribute \src "ls180.v:4026.22-4026.77"
- cell $and $and$ls180.v:4026$1222
+ attribute \src "ls180.v:4039.22-4039.77"
+ cell $and $and$ls180.v:4039$1223
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4026$1222_Y
+ connect \Y $and$ls180.v:4039$1223_Y
end
- attribute \src "ls180.v:4026.21-4026.112"
- cell $and $and$ls180.v:4026$1223
+ attribute \src "ls180.v:4039.21-4039.112"
+ cell $and $and$ls180.v:4039$1224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4026$1222_Y
+ connect \A $and$ls180.v:4039$1223_Y
connect \B \sdram_choose_req_cmd_payload_we
- connect \Y $and$ls180.v:4026$1223_Y
+ connect \Y $and$ls180.v:4039$1224_Y
end
- attribute \src "ls180.v:4029.22-4029.77"
- cell $and $and$ls180.v:4029$1224
+ attribute \src "ls180.v:4042.22-4042.77"
+ cell $and $and$ls180.v:4042$1225
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4029$1224_Y
+ connect \Y $and$ls180.v:4042$1225_Y
end
- attribute \src "ls180.v:4029.21-4029.112"
- cell $and $and$ls180.v:4029$1225
+ attribute \src "ls180.v:4042.21-4042.112"
+ cell $and $and$ls180.v:4042$1226
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4029$1224_Y
+ connect \A $and$ls180.v:4042$1225_Y
connect \B \sdram_choose_req_cmd_payload_we
- connect \Y $and$ls180.v:4029$1225_Y
+ connect \Y $and$ls180.v:4042$1226_Y
end
- attribute \src "ls180.v:4032.22-4032.55"
- cell $and $and$ls180.v:4032$1226
+ attribute \src "ls180.v:4045.22-4045.55"
+ cell $and $and$ls180.v:4045$1227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_cmd_valid
connect \B \sdram_cmd_ready
- connect \Y $and$ls180.v:4032$1226_Y
+ connect \Y $and$ls180.v:4045$1227_Y
end
- attribute \src "ls180.v:4032.21-4032.79"
- cell $and $and$ls180.v:4032$1227
+ attribute \src "ls180.v:4045.21-4045.79"
+ cell $and $and$ls180.v:4045$1228
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4032$1226_Y
+ connect \A $and$ls180.v:4045$1227_Y
connect \B \sdram_cmd_payload_we
- connect \Y $and$ls180.v:4032$1227_Y
+ connect \Y $and$ls180.v:4045$1228_Y
end
- attribute \src "ls180.v:4043.22-4043.77"
- cell $and $and$ls180.v:4043$1229
+ attribute \src "ls180.v:4056.22-4056.77"
+ cell $and $and$ls180.v:4056$1230
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4043$1229_Y
+ connect \Y $and$ls180.v:4056$1230_Y
end
- attribute \src "ls180.v:4043.21-4043.117"
- cell $and $and$ls180.v:4043$1230
+ attribute \src "ls180.v:4056.21-4056.117"
+ cell $and $and$ls180.v:4056$1231
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4043$1229_Y
+ connect \A $and$ls180.v:4056$1230_Y
connect \B \sdram_choose_req_cmd_payload_is_read
- connect \Y $and$ls180.v:4043$1230_Y
+ connect \Y $and$ls180.v:4056$1231_Y
end
- attribute \src "ls180.v:4046.22-4046.77"
- cell $and $and$ls180.v:4046$1231
+ attribute \src "ls180.v:4059.22-4059.77"
+ cell $and $and$ls180.v:4059$1232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4046$1231_Y
+ connect \Y $and$ls180.v:4059$1232_Y
end
- attribute \src "ls180.v:4046.21-4046.117"
- cell $and $and$ls180.v:4046$1232
+ attribute \src "ls180.v:4059.21-4059.117"
+ cell $and $and$ls180.v:4059$1233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4046$1231_Y
+ connect \A $and$ls180.v:4059$1232_Y
connect \B \sdram_choose_req_cmd_payload_is_read
- connect \Y $and$ls180.v:4046$1232_Y
+ connect \Y $and$ls180.v:4059$1233_Y
end
- attribute \src "ls180.v:4049.22-4049.55"
- cell $and $and$ls180.v:4049$1233
+ attribute \src "ls180.v:4062.22-4062.55"
+ cell $and $and$ls180.v:4062$1234
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_cmd_valid
connect \B \sdram_cmd_ready
- connect \Y $and$ls180.v:4049$1233_Y
+ connect \Y $and$ls180.v:4062$1234_Y
end
- attribute \src "ls180.v:4049.21-4049.84"
- cell $and $and$ls180.v:4049$1234
+ attribute \src "ls180.v:4062.21-4062.84"
+ cell $and $and$ls180.v:4062$1235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4049$1233_Y
+ connect \A $and$ls180.v:4062$1234_Y
connect \B \sdram_cmd_payload_is_read
- connect \Y $and$ls180.v:4049$1234_Y
+ connect \Y $and$ls180.v:4062$1235_Y
end
- attribute \src "ls180.v:4060.22-4060.77"
- cell $and $and$ls180.v:4060$1236
+ attribute \src "ls180.v:4073.22-4073.77"
+ cell $and $and$ls180.v:4073$1237
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4060$1236_Y
+ connect \Y $and$ls180.v:4073$1237_Y
end
- attribute \src "ls180.v:4060.21-4060.118"
- cell $and $and$ls180.v:4060$1237
+ attribute \src "ls180.v:4073.21-4073.118"
+ cell $and $and$ls180.v:4073$1238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4060$1236_Y
+ connect \A $and$ls180.v:4073$1237_Y
connect \B \sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:4060$1237_Y
+ connect \Y $and$ls180.v:4073$1238_Y
end
- attribute \src "ls180.v:4063.22-4063.77"
- cell $and $and$ls180.v:4063$1238
+ attribute \src "ls180.v:4076.22-4076.77"
+ cell $and $and$ls180.v:4076$1239
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
connect \B \sdram_choose_req_cmd_ready
- connect \Y $and$ls180.v:4063$1238_Y
+ connect \Y $and$ls180.v:4076$1239_Y
end
- attribute \src "ls180.v:4063.21-4063.118"
- cell $and $and$ls180.v:4063$1239
+ attribute \src "ls180.v:4076.21-4076.118"
+ cell $and $and$ls180.v:4076$1240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4063$1238_Y
+ connect \A $and$ls180.v:4076$1239_Y
connect \B \sdram_choose_req_cmd_payload_is_write
- connect \Y $and$ls180.v:4063$1239_Y
+ connect \Y $and$ls180.v:4076$1240_Y
end
- attribute \src "ls180.v:4066.22-4066.55"
- cell $and $and$ls180.v:4066$1240
+ attribute \src "ls180.v:4079.22-4079.55"
+ cell $and $and$ls180.v:4079$1241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_cmd_valid
connect \B \sdram_cmd_ready
- connect \Y $and$ls180.v:4066$1240_Y
+ connect \Y $and$ls180.v:4079$1241_Y
end
- attribute \src "ls180.v:4066.21-4066.85"
- cell $and $and$ls180.v:4066$1241
+ attribute \src "ls180.v:4079.21-4079.85"
+ cell $and $and$ls180.v:4079$1242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4066$1240_Y
+ connect \A $and$ls180.v:4079$1241_Y
connect \B \sdram_cmd_payload_is_write
- connect \Y $and$ls180.v:4066$1241_Y
+ connect \Y $and$ls180.v:4079$1242_Y
end
- attribute \src "ls180.v:4234.61-4234.101"
- cell $and $and$ls180.v:4234$1244
+ attribute \src "ls180.v:4247.57-4247.97"
+ cell $and $and$ls180.v:4247$1245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dfi_p0_wrdata_en
connect \B \dfi_p0_wrdata_mask [0]
- connect \Y $and$ls180.v:4234$1244_Y
+ connect \Y $and$ls180.v:4247$1245_Y
end
- attribute \src "ls180.v:4235.61-4235.101"
- cell $and $and$ls180.v:4235$1245
+ attribute \src "ls180.v:4248.57-4248.97"
+ cell $and $and$ls180.v:4248$1246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \dfi_p0_wrdata_en
connect \B \dfi_p0_wrdata_mask [1]
- connect \Y $and$ls180.v:4235$1245_Y
+ connect \Y $and$ls180.v:4248$1246_Y
end
- attribute \src "ls180.v:4357.8-4357.57"
- cell $and $and$ls180.v:4357$1282
+ attribute \src "ls180.v:4376.8-4376.57"
+ cell $and $and$ls180.v:4376$1289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_cyc
connect \B \libresocsim_ram_bus_stb
- connect \Y $and$ls180.v:4357$1282_Y
+ connect \Y $and$ls180.v:4376$1289_Y
end
- attribute \src "ls180.v:4357.7-4357.87"
- cell $and $and$ls180.v:4357$1284
+ attribute \src "ls180.v:4376.7-4376.87"
+ cell $and $and$ls180.v:4376$1291
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4357$1282_Y
- connect \B $not$ls180.v:4357$1283_Y
- connect \Y $and$ls180.v:4357$1284_Y
+ connect \A $and$ls180.v:4376$1289_Y
+ connect \B $not$ls180.v:4376$1290_Y
+ connect \Y $and$ls180.v:4376$1291_Y
end
- attribute \src "ls180.v:4376.7-4376.65"
- cell $and $and$ls180.v:4376$1288
+ attribute \src "ls180.v:4395.7-4395.65"
+ cell $and $and$ls180.v:4395$1295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4376$1287_Y
+ connect \A $not$ls180.v:4395$1294_Y
connect \B \libresocsim_zero_old_trigger
- connect \Y $and$ls180.v:4376$1288_Y
+ connect \Y $and$ls180.v:4395$1295_Y
end
- attribute \src "ls180.v:4380.8-4380.49"
- cell $and $and$ls180.v:4380$1289
+ attribute \src "ls180.v:4399.8-4399.49"
+ cell $and $and$ls180.v:4399$1296
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_cyc
connect \B \ram_bus_ram_bus_stb
- connect \Y $and$ls180.v:4380$1289_Y
+ connect \Y $and$ls180.v:4399$1296_Y
end
- attribute \src "ls180.v:4380.7-4380.75"
- cell $and $and$ls180.v:4380$1291
+ attribute \src "ls180.v:4399.7-4399.75"
+ cell $and $and$ls180.v:4399$1298
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4380$1289_Y
- connect \B $not$ls180.v:4380$1290_Y
- connect \Y $and$ls180.v:4380$1291_Y
+ connect \A $and$ls180.v:4399$1296_Y
+ connect \B $not$ls180.v:4399$1297_Y
+ connect \Y $and$ls180.v:4399$1298_Y
end
- attribute \src "ls180.v:4388.7-4388.46"
- cell $and $and$ls180.v:4388$1293
+ attribute \src "ls180.v:4407.7-4407.46"
+ cell $and $and$ls180.v:4407$1300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_timer_wait
- connect \B $not$ls180.v:4388$1292_Y
- connect \Y $and$ls180.v:4388$1293_Y
+ connect \B $not$ls180.v:4407$1299_Y
+ connect \Y $and$ls180.v:4407$1300_Y
end
- attribute \src "ls180.v:4416.7-4416.65"
- cell $and $and$ls180.v:4416$1300
+ attribute \src "ls180.v:4435.7-4435.65"
+ cell $and $and$ls180.v:4435$1307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_start1
- connect \B $eq$ls180.v:4416$1299_Y
- connect \Y $and$ls180.v:4416$1300_Y
+ connect \B $eq$ls180.v:4435$1306_Y
+ connect \Y $and$ls180.v:4435$1307_Y
end
- attribute \src "ls180.v:4458.8-4458.121"
- cell $and $and$ls180.v:4458$1306
+ attribute \src "ls180.v:4477.8-4477.121"
+ cell $and $and$ls180.v:4477$1313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- connect \Y $and$ls180.v:4458$1306_Y
+ connect \Y $and$ls180.v:4477$1313_Y
end
- attribute \src "ls180.v:4458.7-4458.175"
- cell $and $and$ls180.v:4458$1308
+ attribute \src "ls180.v:4477.7-4477.175"
+ cell $and $and$ls180.v:4477$1315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4458$1306_Y
- connect \B $not$ls180.v:4458$1307_Y
- connect \Y $and$ls180.v:4458$1308_Y
+ connect \A $and$ls180.v:4477$1313_Y
+ connect \B $not$ls180.v:4477$1314_Y
+ connect \Y $and$ls180.v:4477$1315_Y
end
- attribute \src "ls180.v:4464.8-4464.121"
- cell $and $and$ls180.v:4464$1311
+ attribute \src "ls180.v:4483.8-4483.121"
+ cell $and $and$ls180.v:4483$1318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we
connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
- connect \Y $and$ls180.v:4464$1311_Y
+ connect \Y $and$ls180.v:4483$1318_Y
end
- attribute \src "ls180.v:4464.7-4464.175"
- cell $and $and$ls180.v:4464$1313
+ attribute \src "ls180.v:4483.7-4483.175"
+ cell $and $and$ls180.v:4483$1320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4464$1311_Y
- connect \B $not$ls180.v:4464$1312_Y
- connect \Y $and$ls180.v:4464$1313_Y
+ connect \A $and$ls180.v:4483$1318_Y
+ connect \B $not$ls180.v:4483$1319_Y
+ connect \Y $and$ls180.v:4483$1320_Y
end
- attribute \src "ls180.v:4504.8-4504.121"
- cell $and $and$ls180.v:4504$1322
+ attribute \src "ls180.v:4523.8-4523.121"
+ cell $and $and$ls180.v:4523$1329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- connect \Y $and$ls180.v:4504$1322_Y
+ connect \Y $and$ls180.v:4523$1329_Y
end
- attribute \src "ls180.v:4504.7-4504.175"
- cell $and $and$ls180.v:4504$1324
+ attribute \src "ls180.v:4523.7-4523.175"
+ cell $and $and$ls180.v:4523$1331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4504$1322_Y
- connect \B $not$ls180.v:4504$1323_Y
- connect \Y $and$ls180.v:4504$1324_Y
+ connect \A $and$ls180.v:4523$1329_Y
+ connect \B $not$ls180.v:4523$1330_Y
+ connect \Y $and$ls180.v:4523$1331_Y
end
- attribute \src "ls180.v:4510.8-4510.121"
- cell $and $and$ls180.v:4510$1327
+ attribute \src "ls180.v:4529.8-4529.121"
+ cell $and $and$ls180.v:4529$1334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we
connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
- connect \Y $and$ls180.v:4510$1327_Y
+ connect \Y $and$ls180.v:4529$1334_Y
end
- attribute \src "ls180.v:4510.7-4510.175"
- cell $and $and$ls180.v:4510$1329
+ attribute \src "ls180.v:4529.7-4529.175"
+ cell $and $and$ls180.v:4529$1336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4510$1327_Y
- connect \B $not$ls180.v:4510$1328_Y
- connect \Y $and$ls180.v:4510$1329_Y
+ connect \A $and$ls180.v:4529$1334_Y
+ connect \B $not$ls180.v:4529$1335_Y
+ connect \Y $and$ls180.v:4529$1336_Y
end
- attribute \src "ls180.v:4550.8-4550.121"
- cell $and $and$ls180.v:4550$1338
+ attribute \src "ls180.v:4569.8-4569.121"
+ cell $and $and$ls180.v:4569$1345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- connect \Y $and$ls180.v:4550$1338_Y
+ connect \Y $and$ls180.v:4569$1345_Y
end
- attribute \src "ls180.v:4550.7-4550.175"
- cell $and $and$ls180.v:4550$1340
+ attribute \src "ls180.v:4569.7-4569.175"
+ cell $and $and$ls180.v:4569$1347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4550$1338_Y
- connect \B $not$ls180.v:4550$1339_Y
- connect \Y $and$ls180.v:4550$1340_Y
+ connect \A $and$ls180.v:4569$1345_Y
+ connect \B $not$ls180.v:4569$1346_Y
+ connect \Y $and$ls180.v:4569$1347_Y
end
- attribute \src "ls180.v:4556.8-4556.121"
- cell $and $and$ls180.v:4556$1343
+ attribute \src "ls180.v:4575.8-4575.121"
+ cell $and $and$ls180.v:4575$1350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we
connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
- connect \Y $and$ls180.v:4556$1343_Y
+ connect \Y $and$ls180.v:4575$1350_Y
end
- attribute \src "ls180.v:4556.7-4556.175"
- cell $and $and$ls180.v:4556$1345
+ attribute \src "ls180.v:4575.7-4575.175"
+ cell $and $and$ls180.v:4575$1352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4556$1343_Y
- connect \B $not$ls180.v:4556$1344_Y
- connect \Y $and$ls180.v:4556$1345_Y
+ connect \A $and$ls180.v:4575$1350_Y
+ connect \B $not$ls180.v:4575$1351_Y
+ connect \Y $and$ls180.v:4575$1352_Y
end
- attribute \src "ls180.v:4596.8-4596.121"
- cell $and $and$ls180.v:4596$1354
+ attribute \src "ls180.v:4615.8-4615.121"
+ cell $and $and$ls180.v:4615$1361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- connect \Y $and$ls180.v:4596$1354_Y
+ connect \Y $and$ls180.v:4615$1361_Y
end
- attribute \src "ls180.v:4596.7-4596.175"
- cell $and $and$ls180.v:4596$1356
+ attribute \src "ls180.v:4615.7-4615.175"
+ cell $and $and$ls180.v:4615$1363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4596$1354_Y
- connect \B $not$ls180.v:4596$1355_Y
- connect \Y $and$ls180.v:4596$1356_Y
+ connect \A $and$ls180.v:4615$1361_Y
+ connect \B $not$ls180.v:4615$1362_Y
+ connect \Y $and$ls180.v:4615$1363_Y
end
- attribute \src "ls180.v:4602.8-4602.121"
- cell $and $and$ls180.v:4602$1359
+ attribute \src "ls180.v:4621.8-4621.121"
+ cell $and $and$ls180.v:4621$1366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we
connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
- connect \Y $and$ls180.v:4602$1359_Y
+ connect \Y $and$ls180.v:4621$1366_Y
end
- attribute \src "ls180.v:4602.7-4602.175"
- cell $and $and$ls180.v:4602$1361
+ attribute \src "ls180.v:4621.7-4621.175"
+ cell $and $and$ls180.v:4621$1368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4602$1359_Y
- connect \B $not$ls180.v:4602$1360_Y
- connect \Y $and$ls180.v:4602$1361_Y
+ connect \A $and$ls180.v:4621$1366_Y
+ connect \B $not$ls180.v:4621$1367_Y
+ connect \Y $and$ls180.v:4621$1368_Y
end
- attribute \src "ls180.v:4799.53-4799.129"
- cell $and $and$ls180.v:4799$1386
+ attribute \src "ls180.v:4818.53-4818.129"
+ cell $and $and$ls180.v:4818$1393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4799$1385_Y
+ connect \A $eq$ls180.v:4818$1392_Y
connect \B \sdram_interface_bank0_wdata_ready
- connect \Y $and$ls180.v:4799$1386_Y
+ connect \Y $and$ls180.v:4818$1393_Y
end
- attribute \src "ls180.v:4799.135-4799.211"
- cell $and $and$ls180.v:4799$1389
+ attribute \src "ls180.v:4818.135-4818.211"
+ cell $and $and$ls180.v:4818$1396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4799$1388_Y
+ connect \A $eq$ls180.v:4818$1395_Y
connect \B \sdram_interface_bank1_wdata_ready
- connect \Y $and$ls180.v:4799$1389_Y
+ connect \Y $and$ls180.v:4818$1396_Y
end
- attribute \src "ls180.v:4799.217-4799.293"
- cell $and $and$ls180.v:4799$1392
+ attribute \src "ls180.v:4818.217-4818.293"
+ cell $and $and$ls180.v:4818$1399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4799$1391_Y
+ connect \A $eq$ls180.v:4818$1398_Y
connect \B \sdram_interface_bank2_wdata_ready
- connect \Y $and$ls180.v:4799$1392_Y
+ connect \Y $and$ls180.v:4818$1399_Y
end
- attribute \src "ls180.v:4799.299-4799.375"
- cell $and $and$ls180.v:4799$1395
+ attribute \src "ls180.v:4818.299-4818.375"
+ cell $and $and$ls180.v:4818$1402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4799$1394_Y
+ connect \A $eq$ls180.v:4818$1401_Y
connect \B \sdram_interface_bank3_wdata_ready
- connect \Y $and$ls180.v:4799$1395_Y
+ connect \Y $and$ls180.v:4818$1402_Y
end
- attribute \src "ls180.v:4800.54-4800.130"
- cell $and $and$ls180.v:4800$1398
+ attribute \src "ls180.v:4819.54-4819.130"
+ cell $and $and$ls180.v:4819$1405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4800$1397_Y
+ connect \A $eq$ls180.v:4819$1404_Y
connect \B \sdram_interface_bank0_rdata_valid
- connect \Y $and$ls180.v:4800$1398_Y
+ connect \Y $and$ls180.v:4819$1405_Y
end
- attribute \src "ls180.v:4800.136-4800.212"
- cell $and $and$ls180.v:4800$1401
+ attribute \src "ls180.v:4819.136-4819.212"
+ cell $and $and$ls180.v:4819$1408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4800$1400_Y
+ connect \A $eq$ls180.v:4819$1407_Y
connect \B \sdram_interface_bank1_rdata_valid
- connect \Y $and$ls180.v:4800$1401_Y
+ connect \Y $and$ls180.v:4819$1408_Y
end
- attribute \src "ls180.v:4800.218-4800.294"
- cell $and $and$ls180.v:4800$1404
+ attribute \src "ls180.v:4819.218-4819.294"
+ cell $and $and$ls180.v:4819$1411
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4800$1403_Y
+ connect \A $eq$ls180.v:4819$1410_Y
connect \B \sdram_interface_bank2_rdata_valid
- connect \Y $and$ls180.v:4800$1404_Y
+ connect \Y $and$ls180.v:4819$1411_Y
end
- attribute \src "ls180.v:4800.300-4800.376"
- cell $and $and$ls180.v:4800$1407
+ attribute \src "ls180.v:4819.300-4819.376"
+ cell $and $and$ls180.v:4819$1414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $eq$ls180.v:4800$1406_Y
+ connect \A $eq$ls180.v:4819$1413_Y
connect \B \sdram_interface_bank3_rdata_valid
- connect \Y $and$ls180.v:4800$1407_Y
+ connect \Y $and$ls180.v:4819$1414_Y
end
- attribute \src "ls180.v:4819.8-4819.39"
- cell $and $and$ls180.v:4819$1410
+ attribute \src "ls180.v:4838.8-4838.39"
+ cell $and $and$ls180.v:4838$1417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_valid
connect \B \port_cmd_ready
- connect \Y $and$ls180.v:4819$1410_Y
+ connect \Y $and$ls180.v:4838$1417_Y
end
- attribute \src "ls180.v:4822.8-4822.43"
- cell $and $and$ls180.v:4822$1411
+ attribute \src "ls180.v:4841.8-4841.43"
+ cell $and $and$ls180.v:4841$1418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_wdata_valid
connect \B \port_wdata_ready
- connect \Y $and$ls180.v:4822$1411_Y
+ connect \Y $and$ls180.v:4841$1418_Y
end
- attribute \src "ls180.v:4827.8-4827.49"
- cell $and $and$ls180.v:4827$1413
+ attribute \src "ls180.v:4846.8-4846.49"
+ cell $and $and$ls180.v:4846$1420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \uart_phy_sink_valid
- connect \B $not$ls180.v:4827$1412_Y
- connect \Y $and$ls180.v:4827$1413_Y
+ connect \B $not$ls180.v:4846$1419_Y
+ connect \Y $and$ls180.v:4846$1420_Y
end
- attribute \src "ls180.v:4827.7-4827.75"
- cell $and $and$ls180.v:4827$1415
+ attribute \src "ls180.v:4846.7-4846.75"
+ cell $and $and$ls180.v:4846$1422
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4827$1413_Y
- connect \B $not$ls180.v:4827$1414_Y
- connect \Y $and$ls180.v:4827$1415_Y
+ connect \A $and$ls180.v:4846$1420_Y
+ connect \B $not$ls180.v:4846$1421_Y
+ connect \Y $and$ls180.v:4846$1422_Y
end
- attribute \src "ls180.v:4833.8-4833.49"
- cell $and $and$ls180.v:4833$1416
+ attribute \src "ls180.v:4852.8-4852.49"
+ cell $and $and$ls180.v:4852$1423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \uart_phy_uart_clk_txen
connect \B \uart_phy_tx_busy
- connect \Y $and$ls180.v:4833$1416_Y
+ connect \Y $and$ls180.v:4852$1423_Y
end
- attribute \src "ls180.v:4857.8-4857.38"
- cell $and $and$ls180.v:4857$1423
+ attribute \src "ls180.v:4876.8-4876.38"
+ cell $and $and$ls180.v:4876$1430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4857$1422_Y
+ connect \A $not$ls180.v:4876$1429_Y
connect \B \uart_phy_rx_r
- connect \Y $and$ls180.v:4857$1423_Y
+ connect \Y $and$ls180.v:4876$1430_Y
end
- attribute \src "ls180.v:4890.7-4890.37"
- cell $and $and$ls180.v:4890$1429
+ attribute \src "ls180.v:4909.7-4909.37"
+ cell $and $and$ls180.v:4909$1436
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4890$1428_Y
+ connect \A $not$ls180.v:4909$1435_Y
connect \B \tx_old_trigger
- connect \Y $and$ls180.v:4890$1429_Y
+ connect \Y $and$ls180.v:4909$1436_Y
end
- attribute \src "ls180.v:4897.7-4897.37"
- cell $and $and$ls180.v:4897$1431
+ attribute \src "ls180.v:4916.7-4916.37"
+ cell $and $and$ls180.v:4916$1438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4897$1430_Y
+ connect \A $not$ls180.v:4916$1437_Y
connect \B \rx_old_trigger
- connect \Y $and$ls180.v:4897$1431_Y
+ connect \Y $and$ls180.v:4916$1438_Y
end
- attribute \src "ls180.v:4907.8-4907.55"
- cell $and $and$ls180.v:4907$1432
+ attribute \src "ls180.v:4926.8-4926.55"
+ cell $and $and$ls180.v:4926$1439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \tx_fifo_syncfifo_we
connect \B \tx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:4907$1432_Y
+ connect \Y $and$ls180.v:4926$1439_Y
end
- attribute \src "ls180.v:4907.7-4907.77"
- cell $and $and$ls180.v:4907$1434
+ attribute \src "ls180.v:4926.7-4926.77"
+ cell $and $and$ls180.v:4926$1441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4907$1432_Y
- connect \B $not$ls180.v:4907$1433_Y
- connect \Y $and$ls180.v:4907$1434_Y
+ connect \A $and$ls180.v:4926$1439_Y
+ connect \B $not$ls180.v:4926$1440_Y
+ connect \Y $and$ls180.v:4926$1441_Y
end
- attribute \src "ls180.v:4913.8-4913.55"
- cell $and $and$ls180.v:4913$1437
+ attribute \src "ls180.v:4932.8-4932.55"
+ cell $and $and$ls180.v:4932$1444
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \tx_fifo_syncfifo_we
connect \B \tx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:4913$1437_Y
+ connect \Y $and$ls180.v:4932$1444_Y
end
- attribute \src "ls180.v:4913.7-4913.77"
- cell $and $and$ls180.v:4913$1439
+ attribute \src "ls180.v:4932.7-4932.77"
+ cell $and $and$ls180.v:4932$1446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4913$1437_Y
- connect \B $not$ls180.v:4913$1438_Y
- connect \Y $and$ls180.v:4913$1439_Y
+ connect \A $and$ls180.v:4932$1444_Y
+ connect \B $not$ls180.v:4932$1445_Y
+ connect \Y $and$ls180.v:4932$1446_Y
end
- attribute \src "ls180.v:4929.8-4929.55"
- cell $and $and$ls180.v:4929$1443
+ attribute \src "ls180.v:4948.8-4948.55"
+ cell $and $and$ls180.v:4948$1450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rx_fifo_syncfifo_we
connect \B \rx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:4929$1443_Y
+ connect \Y $and$ls180.v:4948$1450_Y
end
- attribute \src "ls180.v:4929.7-4929.77"
- cell $and $and$ls180.v:4929$1445
+ attribute \src "ls180.v:4948.7-4948.77"
+ cell $and $and$ls180.v:4948$1452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4929$1443_Y
- connect \B $not$ls180.v:4929$1444_Y
- connect \Y $and$ls180.v:4929$1445_Y
+ connect \A $and$ls180.v:4948$1450_Y
+ connect \B $not$ls180.v:4948$1451_Y
+ connect \Y $and$ls180.v:4948$1452_Y
end
- attribute \src "ls180.v:4935.8-4935.55"
- cell $and $and$ls180.v:4935$1448
+ attribute \src "ls180.v:4954.8-4954.55"
+ cell $and $and$ls180.v:4954$1455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rx_fifo_syncfifo_we
connect \B \rx_fifo_syncfifo_writable
- connect \Y $and$ls180.v:4935$1448_Y
+ connect \Y $and$ls180.v:4954$1455_Y
end
- attribute \src "ls180.v:4935.7-4935.77"
- cell $and $and$ls180.v:4935$1450
+ attribute \src "ls180.v:4954.7-4954.77"
+ cell $and $and$ls180.v:4954$1457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:4935$1448_Y
- connect \B $not$ls180.v:4935$1449_Y
- connect \Y $and$ls180.v:4935$1450_Y
+ connect \A $and$ls180.v:4954$1455_Y
+ connect \B $not$ls180.v:4954$1456_Y
+ connect \Y $and$ls180.v:4954$1457_Y
end
- attribute \src "ls180.v:1550.25-1550.66"
- cell $eq $eq$ls180.v:1550$28
+ attribute \src "ls180.v:1563.25-1563.66"
+ cell $eq $eq$ls180.v:1563$29
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresoc_xics_icp_sel
connect \B 1'0
- connect \Y $eq$ls180.v:1550$28_Y
+ connect \Y $eq$ls180.v:1563$29_Y
end
- attribute \src "ls180.v:1557.11-1557.37"
- cell $eq $eq$ls180.v:1557$33
+ attribute \src "ls180.v:1570.11-1570.37"
+ cell $eq $eq$ls180.v:1570$34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \converter0_counter
connect \B 1'1
- connect \Y $eq$ls180.v:1557$33_Y
+ connect \Y $eq$ls180.v:1570$34_Y
end
- attribute \src "ls180.v:1610.25-1610.66"
- cell $eq $eq$ls180.v:1610$39
+ attribute \src "ls180.v:1623.25-1623.66"
+ cell $eq $eq$ls180.v:1623$40
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresoc_xics_ics_sel
connect \B 1'0
- connect \Y $eq$ls180.v:1610$39_Y
+ connect \Y $eq$ls180.v:1623$40_Y
end
- attribute \src "ls180.v:1617.11-1617.37"
- cell $eq $eq$ls180.v:1617$44
+ attribute \src "ls180.v:1630.11-1630.37"
+ cell $eq $eq$ls180.v:1630$45
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \converter1_counter
connect \B 1'1
- connect \Y $eq$ls180.v:1617$44_Y
+ connect \Y $eq$ls180.v:1630$45_Y
end
- attribute \src "ls180.v:1670.28-1670.48"
- cell $eq $eq$ls180.v:1670$50
+ attribute \src "ls180.v:1683.28-1683.48"
+ cell $eq $eq$ls180.v:1683$51
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_sdram_sel
connect \B 1'0
- connect \Y $eq$ls180.v:1670$50_Y
+ connect \Y $eq$ls180.v:1683$51_Y
end
- attribute \src "ls180.v:1677.11-1677.40"
- cell $eq $eq$ls180.v:1677$55
+ attribute \src "ls180.v:1690.11-1690.40"
+ cell $eq $eq$ls180.v:1690$56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \socbushandler_counter
connect \B 1'1
- connect \Y $eq$ls180.v:1677$55_Y
+ connect \Y $eq$ls180.v:1690$56_Y
end
- attribute \src "ls180.v:1881.29-1881.55"
- cell $eq $eq$ls180.v:1881$120
+ attribute \src "ls180.v:1894.29-1894.55"
+ cell $eq $eq$ls180.v:1894$121
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_timer_count1
connect \B 1'0
- connect \Y $eq$ls180.v:1881$120_Y
+ connect \Y $eq$ls180.v:1894$121_Y
end
- attribute \src "ls180.v:1885.58-1885.87"
- cell $eq $eq$ls180.v:1885$123
+ attribute \src "ls180.v:1898.58-1898.87"
+ cell $eq $eq$ls180.v:1898$124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_count
connect \B 1'0
- connect \Y $eq$ls180.v:1885$123_Y
+ connect \Y $eq$ls180.v:1898$124_Y
end
- attribute \src "ls180.v:1929.38-1929.119"
- cell $eq $eq$ls180.v:1929$128
+ attribute \src "ls180.v:1942.38-1942.119"
+ cell $eq $eq$ls180.v:1942$129
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_row
connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:1929$128_Y
+ connect \Y $eq$ls180.v:1942$129_Y
end
- attribute \src "ls180.v:1946.42-1946.78"
- cell $eq $eq$ls180.v:1946$141
+ attribute \src "ls180.v:1959.42-1959.78"
+ cell $eq $eq$ls180.v:1959$142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:1946$141_Y
+ connect \Y $eq$ls180.v:1959$142_Y
end
- attribute \src "ls180.v:2086.38-2086.119"
- cell $eq $eq$ls180.v:2086$158
+ attribute \src "ls180.v:2099.38-2099.119"
+ cell $eq $eq$ls180.v:2099$159
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_row
connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:2086$158_Y
+ connect \Y $eq$ls180.v:2099$159_Y
end
- attribute \src "ls180.v:2103.42-2103.78"
- cell $eq $eq$ls180.v:2103$171
+ attribute \src "ls180.v:2116.42-2116.78"
+ cell $eq $eq$ls180.v:2116$172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:2103$171_Y
+ connect \Y $eq$ls180.v:2116$172_Y
end
- attribute \src "ls180.v:2243.38-2243.119"
- cell $eq $eq$ls180.v:2243$188
+ attribute \src "ls180.v:2256.38-2256.119"
+ cell $eq $eq$ls180.v:2256$189
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_row
connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:2243$188_Y
+ connect \Y $eq$ls180.v:2256$189_Y
end
- attribute \src "ls180.v:2260.42-2260.78"
- cell $eq $eq$ls180.v:2260$201
+ attribute \src "ls180.v:2273.42-2273.78"
+ cell $eq $eq$ls180.v:2273$202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:2260$201_Y
+ connect \Y $eq$ls180.v:2273$202_Y
end
- attribute \src "ls180.v:2400.38-2400.119"
- cell $eq $eq$ls180.v:2400$218
+ attribute \src "ls180.v:2413.38-2413.119"
+ cell $eq $eq$ls180.v:2413$219
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_row
connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- connect \Y $eq$ls180.v:2400$218_Y
+ connect \Y $eq$ls180.v:2413$219_Y
end
- attribute \src "ls180.v:2417.42-2417.78"
- cell $eq $eq$ls180.v:2417$231
+ attribute \src "ls180.v:2430.42-2430.78"
+ cell $eq $eq$ls180.v:2430$232
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_row_close
connect \B 1'0
- connect \Y $eq$ls180.v:2417$231_Y
+ connect \Y $eq$ls180.v:2430$232_Y
end
- attribute \src "ls180.v:2554.27-2554.46"
- cell $eq $eq$ls180.v:2554$278
+ attribute \src "ls180.v:2567.27-2567.46"
+ cell $eq $eq$ls180.v:2567$279
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_time0
connect \B 1'0
- connect \Y $eq$ls180.v:2554$278_Y
+ connect \Y $eq$ls180.v:2567$279_Y
end
- attribute \src "ls180.v:2555.27-2555.46"
- cell $eq $eq$ls180.v:2555$279
+ attribute \src "ls180.v:2568.27-2568.46"
+ cell $eq $eq$ls180.v:2568$280
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_time1
connect \B 1'0
- connect \Y $eq$ls180.v:2555$279_Y
+ connect \Y $eq$ls180.v:2568$280_Y
end
- attribute \src "ls180.v:2566.299-2566.368"
- cell $eq $eq$ls180.v:2566$293
+ attribute \src "ls180.v:2579.299-2579.368"
+ cell $eq $eq$ls180.v:2579$294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_is_read
connect \B \sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:2566$293_Y
+ connect \Y $eq$ls180.v:2579$294_Y
end
- attribute \src "ls180.v:2566.373-2566.444"
- cell $eq $eq$ls180.v:2566$294
+ attribute \src "ls180.v:2579.373-2579.444"
+ cell $eq $eq$ls180.v:2579$295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_is_write
connect \B \sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:2566$294_Y
+ connect \Y $eq$ls180.v:2579$295_Y
end
- attribute \src "ls180.v:2567.299-2567.368"
- cell $eq $eq$ls180.v:2567$306
+ attribute \src "ls180.v:2580.299-2580.368"
+ cell $eq $eq$ls180.v:2580$307
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_is_read
connect \B \sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:2567$306_Y
+ connect \Y $eq$ls180.v:2580$307_Y
end
- attribute \src "ls180.v:2567.373-2567.444"
- cell $eq $eq$ls180.v:2567$307
+ attribute \src "ls180.v:2580.373-2580.444"
+ cell $eq $eq$ls180.v:2580$308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_is_write
connect \B \sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:2567$307_Y
+ connect \Y $eq$ls180.v:2580$308_Y
end
- attribute \src "ls180.v:2568.299-2568.368"
- cell $eq $eq$ls180.v:2568$319
+ attribute \src "ls180.v:2581.299-2581.368"
+ cell $eq $eq$ls180.v:2581$320
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_is_read
connect \B \sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:2568$319_Y
+ connect \Y $eq$ls180.v:2581$320_Y
end
- attribute \src "ls180.v:2568.373-2568.444"
- cell $eq $eq$ls180.v:2568$320
+ attribute \src "ls180.v:2581.373-2581.444"
+ cell $eq $eq$ls180.v:2581$321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_is_write
connect \B \sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:2568$320_Y
+ connect \Y $eq$ls180.v:2581$321_Y
end
- attribute \src "ls180.v:2569.299-2569.368"
- cell $eq $eq$ls180.v:2569$332
+ attribute \src "ls180.v:2582.299-2582.368"
+ cell $eq $eq$ls180.v:2582$333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_is_read
connect \B \sdram_choose_cmd_want_reads
- connect \Y $eq$ls180.v:2569$332_Y
+ connect \Y $eq$ls180.v:2582$333_Y
end
- attribute \src "ls180.v:2569.373-2569.444"
- cell $eq $eq$ls180.v:2569$333
+ attribute \src "ls180.v:2582.373-2582.444"
+ cell $eq $eq$ls180.v:2582$334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_is_write
connect \B \sdram_choose_cmd_want_writes
- connect \Y $eq$ls180.v:2569$333_Y
+ connect \Y $eq$ls180.v:2582$334_Y
end
- attribute \src "ls180.v:2599.299-2599.368"
- cell $eq $eq$ls180.v:2599$351
+ attribute \src "ls180.v:2612.299-2612.368"
+ cell $eq $eq$ls180.v:2612$352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_is_read
connect \B \sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:2599$351_Y
+ connect \Y $eq$ls180.v:2612$352_Y
end
- attribute \src "ls180.v:2599.373-2599.444"
- cell $eq $eq$ls180.v:2599$352
+ attribute \src "ls180.v:2612.373-2612.444"
+ cell $eq $eq$ls180.v:2612$353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_is_write
connect \B \sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:2599$352_Y
+ connect \Y $eq$ls180.v:2612$353_Y
end
- attribute \src "ls180.v:2600.299-2600.368"
- cell $eq $eq$ls180.v:2600$364
+ attribute \src "ls180.v:2613.299-2613.368"
+ cell $eq $eq$ls180.v:2613$365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_is_read
connect \B \sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:2600$364_Y
+ connect \Y $eq$ls180.v:2613$365_Y
end
- attribute \src "ls180.v:2600.373-2600.444"
- cell $eq $eq$ls180.v:2600$365
+ attribute \src "ls180.v:2613.373-2613.444"
+ cell $eq $eq$ls180.v:2613$366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_is_write
connect \B \sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:2600$365_Y
+ connect \Y $eq$ls180.v:2613$366_Y
end
- attribute \src "ls180.v:2601.299-2601.368"
- cell $eq $eq$ls180.v:2601$377
+ attribute \src "ls180.v:2614.299-2614.368"
+ cell $eq $eq$ls180.v:2614$378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_is_read
connect \B \sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:2601$377_Y
+ connect \Y $eq$ls180.v:2614$378_Y
end
- attribute \src "ls180.v:2601.373-2601.444"
- cell $eq $eq$ls180.v:2601$378
+ attribute \src "ls180.v:2614.373-2614.444"
+ cell $eq $eq$ls180.v:2614$379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_is_write
connect \B \sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:2601$378_Y
+ connect \Y $eq$ls180.v:2614$379_Y
end
- attribute \src "ls180.v:2602.299-2602.368"
- cell $eq $eq$ls180.v:2602$390
+ attribute \src "ls180.v:2615.299-2615.368"
+ cell $eq $eq$ls180.v:2615$391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_is_read
connect \B \sdram_choose_req_want_reads
- connect \Y $eq$ls180.v:2602$390_Y
+ connect \Y $eq$ls180.v:2615$391_Y
end
- attribute \src "ls180.v:2602.373-2602.444"
- cell $eq $eq$ls180.v:2602$391
+ attribute \src "ls180.v:2615.373-2615.444"
+ cell $eq $eq$ls180.v:2615$392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_is_write
connect \B \sdram_choose_req_want_writes
- connect \Y $eq$ls180.v:2602$391_Y
+ connect \Y $eq$ls180.v:2615$392_Y
end
- attribute \src "ls180.v:2631.68-2631.98"
- cell $eq $eq$ls180.v:2631$400
+ attribute \src "ls180.v:2644.68-2644.98"
+ cell $eq $eq$ls180.v:2644$401
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2631$400_Y
+ connect \Y $eq$ls180.v:2644$401_Y
end
- attribute \src "ls180.v:2634.68-2634.98"
- cell $eq $eq$ls180.v:2634$403
+ attribute \src "ls180.v:2647.68-2647.98"
+ cell $eq $eq$ls180.v:2647$404
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2634$403_Y
+ connect \Y $eq$ls180.v:2647$404_Y
end
- attribute \src "ls180.v:2640.68-2640.98"
- cell $eq $eq$ls180.v:2640$407
+ attribute \src "ls180.v:2653.68-2653.98"
+ cell $eq $eq$ls180.v:2653$408
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_grant
connect \B 1'1
- connect \Y $eq$ls180.v:2640$407_Y
+ connect \Y $eq$ls180.v:2653$408_Y
end
- attribute \src "ls180.v:2643.68-2643.98"
- cell $eq $eq$ls180.v:2643$410
+ attribute \src "ls180.v:2656.68-2656.98"
+ cell $eq $eq$ls180.v:2656$411
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_grant
connect \B 1'1
- connect \Y $eq$ls180.v:2643$410_Y
+ connect \Y $eq$ls180.v:2656$411_Y
end
- attribute \src "ls180.v:2649.68-2649.98"
- cell $eq $eq$ls180.v:2649$414
+ attribute \src "ls180.v:2662.68-2662.98"
+ cell $eq $eq$ls180.v:2662$415
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_grant
connect \B 2'10
- connect \Y $eq$ls180.v:2649$414_Y
+ connect \Y $eq$ls180.v:2662$415_Y
end
- attribute \src "ls180.v:2652.68-2652.98"
- cell $eq $eq$ls180.v:2652$417
+ attribute \src "ls180.v:2665.68-2665.98"
+ cell $eq $eq$ls180.v:2665$418
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_grant
connect \B 2'10
- connect \Y $eq$ls180.v:2652$417_Y
+ connect \Y $eq$ls180.v:2665$418_Y
end
- attribute \src "ls180.v:2658.68-2658.98"
- cell $eq $eq$ls180.v:2658$421
+ attribute \src "ls180.v:2671.68-2671.98"
+ cell $eq $eq$ls180.v:2671$422
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_grant
connect \B 2'11
- connect \Y $eq$ls180.v:2658$421_Y
+ connect \Y $eq$ls180.v:2671$422_Y
end
- attribute \src "ls180.v:2661.68-2661.98"
- cell $eq $eq$ls180.v:2661$424
+ attribute \src "ls180.v:2674.68-2674.98"
+ cell $eq $eq$ls180.v:2674$425
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_grant
connect \B 2'11
- connect \Y $eq$ls180.v:2661$424_Y
+ connect \Y $eq$ls180.v:2674$425_Y
end
- attribute \src "ls180.v:2742.47-2742.82"
- cell $eq $eq$ls180.v:2742$447
+ attribute \src "ls180.v:2755.47-2755.82"
+ cell $eq $eq$ls180.v:2755$448
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:2742$447_Y
+ connect \Y $eq$ls180.v:2755$448_Y
end
- attribute \src "ls180.v:2742.145-2742.183"
- cell $eq $eq$ls180.v:2742$448
+ attribute \src "ls180.v:2755.145-2755.183"
+ cell $eq $eq$ls180.v:2755$449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2742$448_Y
+ connect \Y $eq$ls180.v:2755$449_Y
end
- attribute \src "ls180.v:2742.220-2742.258"
- cell $eq $eq$ls180.v:2742$451
+ attribute \src "ls180.v:2755.220-2755.258"
+ cell $eq $eq$ls180.v:2755$452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2742$451_Y
+ connect \Y $eq$ls180.v:2755$452_Y
end
- attribute \src "ls180.v:2742.295-2742.333"
- cell $eq $eq$ls180.v:2742$454
+ attribute \src "ls180.v:2755.295-2755.333"
+ cell $eq $eq$ls180.v:2755$455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2742$454_Y
+ connect \Y $eq$ls180.v:2755$455_Y
end
- attribute \src "ls180.v:2747.47-2747.82"
- cell $eq $eq$ls180.v:2747$463
+ attribute \src "ls180.v:2760.47-2760.82"
+ cell $eq $eq$ls180.v:2760$464
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:2747$463_Y
+ connect \Y $eq$ls180.v:2760$464_Y
end
- attribute \src "ls180.v:2747.145-2747.183"
- cell $eq $eq$ls180.v:2747$464
+ attribute \src "ls180.v:2760.145-2760.183"
+ cell $eq $eq$ls180.v:2760$465
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2747$464_Y
+ connect \Y $eq$ls180.v:2760$465_Y
end
- attribute \src "ls180.v:2747.220-2747.258"
- cell $eq $eq$ls180.v:2747$467
+ attribute \src "ls180.v:2760.220-2760.258"
+ cell $eq $eq$ls180.v:2760$468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2747$467_Y
+ connect \Y $eq$ls180.v:2760$468_Y
end
- attribute \src "ls180.v:2747.295-2747.333"
- cell $eq $eq$ls180.v:2747$470
+ attribute \src "ls180.v:2760.295-2760.333"
+ cell $eq $eq$ls180.v:2760$471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2747$470_Y
+ connect \Y $eq$ls180.v:2760$471_Y
end
- attribute \src "ls180.v:2752.47-2752.82"
- cell $eq $eq$ls180.v:2752$479
+ attribute \src "ls180.v:2765.47-2765.82"
+ cell $eq $eq$ls180.v:2765$480
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:2752$479_Y
+ connect \Y $eq$ls180.v:2765$480_Y
end
- attribute \src "ls180.v:2752.145-2752.183"
- cell $eq $eq$ls180.v:2752$480
+ attribute \src "ls180.v:2765.145-2765.183"
+ cell $eq $eq$ls180.v:2765$481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2752$480_Y
+ connect \Y $eq$ls180.v:2765$481_Y
end
- attribute \src "ls180.v:2752.220-2752.258"
- cell $eq $eq$ls180.v:2752$483
+ attribute \src "ls180.v:2765.220-2765.258"
+ cell $eq $eq$ls180.v:2765$484
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2752$483_Y
+ connect \Y $eq$ls180.v:2765$484_Y
end
- attribute \src "ls180.v:2752.295-2752.333"
- cell $eq $eq$ls180.v:2752$486
+ attribute \src "ls180.v:2765.295-2765.333"
+ cell $eq $eq$ls180.v:2765$487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2752$486_Y
+ connect \Y $eq$ls180.v:2765$487_Y
end
- attribute \src "ls180.v:2757.47-2757.82"
- cell $eq $eq$ls180.v:2757$495
+ attribute \src "ls180.v:2770.47-2770.82"
+ cell $eq $eq$ls180.v:2770$496
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:2757$495_Y
+ connect \Y $eq$ls180.v:2770$496_Y
end
- attribute \src "ls180.v:2757.145-2757.183"
- cell $eq $eq$ls180.v:2757$496
+ attribute \src "ls180.v:2770.145-2770.183"
+ cell $eq $eq$ls180.v:2770$497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2757$496_Y
+ connect \Y $eq$ls180.v:2770$497_Y
end
- attribute \src "ls180.v:2757.220-2757.258"
- cell $eq $eq$ls180.v:2757$499
+ attribute \src "ls180.v:2770.220-2770.258"
+ cell $eq $eq$ls180.v:2770$500
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2757$499_Y
+ connect \Y $eq$ls180.v:2770$500_Y
end
- attribute \src "ls180.v:2757.295-2757.333"
- cell $eq $eq$ls180.v:2757$502
+ attribute \src "ls180.v:2770.295-2770.333"
+ cell $eq $eq$ls180.v:2770$503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2757$502_Y
+ connect \Y $eq$ls180.v:2770$503_Y
end
- attribute \src "ls180.v:2762.39-2762.77"
- cell $eq $eq$ls180.v:2762$511
+ attribute \src "ls180.v:2775.39-2775.77"
+ cell $eq $eq$ls180.v:2775$512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$511_Y
+ connect \Y $eq$ls180.v:2775$512_Y
end
- attribute \src "ls180.v:2762.83-2762.118"
- cell $eq $eq$ls180.v:2762$512
+ attribute \src "ls180.v:2775.83-2775.118"
+ cell $eq $eq$ls180.v:2775$513
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:2762$512_Y
+ connect \Y $eq$ls180.v:2775$513_Y
end
- attribute \src "ls180.v:2762.181-2762.219"
- cell $eq $eq$ls180.v:2762$513
+ attribute \src "ls180.v:2775.181-2775.219"
+ cell $eq $eq$ls180.v:2775$514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$513_Y
+ connect \Y $eq$ls180.v:2775$514_Y
end
- attribute \src "ls180.v:2762.256-2762.294"
- cell $eq $eq$ls180.v:2762$516
+ attribute \src "ls180.v:2775.256-2775.294"
+ cell $eq $eq$ls180.v:2775$517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$516_Y
+ connect \Y $eq$ls180.v:2775$517_Y
end
- attribute \src "ls180.v:2762.331-2762.369"
- cell $eq $eq$ls180.v:2762$519
+ attribute \src "ls180.v:2775.331-2775.369"
+ cell $eq $eq$ls180.v:2775$520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$519_Y
+ connect \Y $eq$ls180.v:2775$520_Y
end
- attribute \src "ls180.v:2762.413-2762.451"
- cell $eq $eq$ls180.v:2762$527
+ attribute \src "ls180.v:2775.413-2775.451"
+ cell $eq $eq$ls180.v:2775$528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$527_Y
+ connect \Y $eq$ls180.v:2775$528_Y
end
- attribute \src "ls180.v:2762.457-2762.492"
- cell $eq $eq$ls180.v:2762$528
+ attribute \src "ls180.v:2775.457-2775.492"
+ cell $eq $eq$ls180.v:2775$529
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:2762$528_Y
+ connect \Y $eq$ls180.v:2775$529_Y
end
- attribute \src "ls180.v:2762.555-2762.593"
- cell $eq $eq$ls180.v:2762$529
+ attribute \src "ls180.v:2775.555-2775.593"
+ cell $eq $eq$ls180.v:2775$530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$529_Y
+ connect \Y $eq$ls180.v:2775$530_Y
end
- attribute \src "ls180.v:2762.630-2762.668"
- cell $eq $eq$ls180.v:2762$532
+ attribute \src "ls180.v:2775.630-2775.668"
+ cell $eq $eq$ls180.v:2775$533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$532_Y
+ connect \Y $eq$ls180.v:2775$533_Y
end
- attribute \src "ls180.v:2762.705-2762.743"
- cell $eq $eq$ls180.v:2762$535
+ attribute \src "ls180.v:2775.705-2775.743"
+ cell $eq $eq$ls180.v:2775$536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$535_Y
+ connect \Y $eq$ls180.v:2775$536_Y
end
- attribute \src "ls180.v:2762.787-2762.825"
- cell $eq $eq$ls180.v:2762$543
+ attribute \src "ls180.v:2775.787-2775.825"
+ cell $eq $eq$ls180.v:2775$544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$543_Y
+ connect \Y $eq$ls180.v:2775$544_Y
end
- attribute \src "ls180.v:2762.831-2762.866"
- cell $eq $eq$ls180.v:2762$544
+ attribute \src "ls180.v:2775.831-2775.866"
+ cell $eq $eq$ls180.v:2775$545
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:2762$544_Y
+ connect \Y $eq$ls180.v:2775$545_Y
end
- attribute \src "ls180.v:2762.929-2762.967"
- cell $eq $eq$ls180.v:2762$545
+ attribute \src "ls180.v:2775.929-2775.967"
+ cell $eq $eq$ls180.v:2775$546
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$545_Y
+ connect \Y $eq$ls180.v:2775$546_Y
end
- attribute \src "ls180.v:2762.1004-2762.1042"
- cell $eq $eq$ls180.v:2762$548
+ attribute \src "ls180.v:2775.1004-2775.1042"
+ cell $eq $eq$ls180.v:2775$549
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$548_Y
+ connect \Y $eq$ls180.v:2775$549_Y
end
- attribute \src "ls180.v:2762.1079-2762.1117"
- cell $eq $eq$ls180.v:2762$551
+ attribute \src "ls180.v:2775.1079-2775.1117"
+ cell $eq $eq$ls180.v:2775$552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$551_Y
+ connect \Y $eq$ls180.v:2775$552_Y
end
- attribute \src "ls180.v:2762.1161-2762.1199"
- cell $eq $eq$ls180.v:2762$559
+ attribute \src "ls180.v:2775.1161-2775.1199"
+ cell $eq $eq$ls180.v:2775$560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$559_Y
+ connect \Y $eq$ls180.v:2775$560_Y
end
- attribute \src "ls180.v:2762.1205-2762.1240"
- cell $eq $eq$ls180.v:2762$560
+ attribute \src "ls180.v:2775.1205-2775.1240"
+ cell $eq $eq$ls180.v:2775$561
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:2762$560_Y
+ connect \Y $eq$ls180.v:2775$561_Y
end
- attribute \src "ls180.v:2762.1303-2762.1341"
- cell $eq $eq$ls180.v:2762$561
+ attribute \src "ls180.v:2775.1303-2775.1341"
+ cell $eq $eq$ls180.v:2775$562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$561_Y
+ connect \Y $eq$ls180.v:2775$562_Y
end
- attribute \src "ls180.v:2762.1378-2762.1416"
- cell $eq $eq$ls180.v:2762$564
+ attribute \src "ls180.v:2775.1378-2775.1416"
+ cell $eq $eq$ls180.v:2775$565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$564_Y
+ connect \Y $eq$ls180.v:2775$565_Y
end
- attribute \src "ls180.v:2762.1453-2762.1491"
- cell $eq $eq$ls180.v:2762$567
+ attribute \src "ls180.v:2775.1453-2775.1491"
+ cell $eq $eq$ls180.v:2775$568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:2762$567_Y
+ connect \Y $eq$ls180.v:2775$568_Y
end
- attribute \src "ls180.v:2821.24-2821.47"
- cell $eq $eq$ls180.v:2821$580
+ attribute \src "ls180.v:2834.24-2834.47"
+ cell $eq $eq$ls180.v:2834$581
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \litedram_wb_sel
connect \B 1'0
- connect \Y $eq$ls180.v:2821$580_Y
+ connect \Y $eq$ls180.v:2834$581_Y
end
- attribute \src "ls180.v:2828.11-2828.36"
- cell $eq $eq$ls180.v:2828$585
+ attribute \src "ls180.v:2841.11-2841.36"
+ cell $eq $eq$ls180.v:2841$586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \converter_counter
connect \B 1'1
- connect \Y $eq$ls180.v:2828$585_Y
+ connect \Y $eq$ls180.v:2841$586_Y
end
- attribute \src "ls180.v:3085.67-3085.92"
- cell $eq $eq$ls180.v:3085$657
+ attribute \src "ls180.v:3098.67-3098.92"
+ cell $eq $eq$ls180.v:3098$658
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3085$657_Y
+ connect \Y $eq$ls180.v:3098$658_Y
end
- attribute \src "ls180.v:3086.67-3086.92"
- cell $eq $eq$ls180.v:3086$659
+ attribute \src "ls180.v:3099.67-3099.92"
+ cell $eq $eq$ls180.v:3099$660
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_grant
connect \B 1'1
- connect \Y $eq$ls180.v:3086$659_Y
+ connect \Y $eq$ls180.v:3099$660_Y
end
- attribute \src "ls180.v:3087.70-3087.95"
- cell $eq $eq$ls180.v:3087$661
+ attribute \src "ls180.v:3100.70-3100.95"
+ cell $eq $eq$ls180.v:3100$662
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_grant
connect \B 2'10
- connect \Y $eq$ls180.v:3087$661_Y
+ connect \Y $eq$ls180.v:3100$662_Y
end
- attribute \src "ls180.v:3088.67-3088.92"
- cell $eq $eq$ls180.v:3088$663
+ attribute \src "ls180.v:3101.67-3101.92"
+ cell $eq $eq$ls180.v:3101$664
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3088$663_Y
+ connect \Y $eq$ls180.v:3101$664_Y
end
- attribute \src "ls180.v:3089.67-3089.92"
- cell $eq $eq$ls180.v:3089$665
+ attribute \src "ls180.v:3102.67-3102.92"
+ cell $eq $eq$ls180.v:3102$666
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_grant
connect \B 1'1
- connect \Y $eq$ls180.v:3089$665_Y
+ connect \Y $eq$ls180.v:3102$666_Y
end
- attribute \src "ls180.v:3090.70-3090.95"
- cell $eq $eq$ls180.v:3090$667
+ attribute \src "ls180.v:3103.70-3103.95"
+ cell $eq $eq$ls180.v:3103$668
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_grant
connect \B 2'10
- connect \Y $eq$ls180.v:3090$667_Y
+ connect \Y $eq$ls180.v:3103$668_Y
end
- attribute \src "ls180.v:3094.31-3094.67"
- cell $eq $eq$ls180.v:3094$670
+ attribute \src "ls180.v:3107.31-3107.67"
+ cell $eq $eq$ls180.v:3107$671
parameter \A_SIGNED 0
parameter \A_WIDTH 24
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_adr [29:6]
connect \B 1'0
- connect \Y $eq$ls180.v:3094$670_Y
+ connect \Y $eq$ls180.v:3107$671_Y
end
- attribute \src "ls180.v:3095.31-3095.68"
- cell $eq $eq$ls180.v:3095$671
+ attribute \src "ls180.v:3108.31-3108.68"
+ cell $eq $eq$ls180.v:3108$672
parameter \A_SIGNED 0
parameter \A_WIDTH 26
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_adr [29:4]
connect \B 4'1110
- connect \Y $eq$ls180.v:3095$671_Y
+ connect \Y $eq$ls180.v:3108$672_Y
end
- attribute \src "ls180.v:3096.31-3096.76"
- cell $eq $eq$ls180.v:3096$672
+ attribute \src "ls180.v:3109.31-3109.76"
+ cell $eq $eq$ls180.v:3109$673
parameter \A_SIGNED 0
parameter \A_WIDTH 28
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_adr [29:2]
connect \B 27'110000000000000100000000000
- connect \Y $eq$ls180.v:3096$672_Y
+ connect \Y $eq$ls180.v:3109$673_Y
end
- attribute \src "ls180.v:3097.31-3097.73"
- cell $eq $eq$ls180.v:3097$673
+ attribute \src "ls180.v:3110.31-3110.73"
+ cell $eq $eq$ls180.v:3110$674
parameter \A_SIGNED 0
parameter \A_WIDTH 21
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_adr [29:9]
connect \B 20'11000000000000010001
- connect \Y $eq$ls180.v:3097$673_Y
+ connect \Y $eq$ls180.v:3110$674_Y
end
- attribute \src "ls180.v:3098.31-3098.69"
- cell $eq $eq$ls180.v:3098$674
+ attribute \src "ls180.v:3111.31-3111.69"
+ cell $eq $eq$ls180.v:3111$675
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_adr [29:22]
connect \B 7'1001000
- connect \Y $eq$ls180.v:3098$674_Y
+ connect \Y $eq$ls180.v:3111$675_Y
end
- attribute \src "ls180.v:3099.31-3099.73"
- cell $eq $eq$ls180.v:3099$675
+ attribute \src "ls180.v:3112.31-3112.73"
+ cell $eq $eq$ls180.v:3112$676
parameter \A_SIGNED 0
parameter \A_WIDTH 17
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_adr [29:13]
connect \B 16'1100000000000000
- connect \Y $eq$ls180.v:3099$675_Y
+ connect \Y $eq$ls180.v:3112$676_Y
end
- attribute \src "ls180.v:3163.28-3163.53"
- cell $eq $eq$ls180.v:3163$707
+ attribute \src "ls180.v:3176.28-3176.53"
+ cell $eq $eq$ls180.v:3176$708
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_count
connect \B 1'0
- connect \Y $eq$ls180.v:3163$707_Y
+ connect \Y $eq$ls180.v:3176$708_Y
end
- attribute \src "ls180.v:3164.36-3164.85"
- cell $eq $eq$ls180.v:3164$708
+ attribute \src "ls180.v:3177.36-3177.85"
+ cell $eq $eq$ls180.v:3177$709
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [13:8]
connect \B 1'0
- connect \Y $eq$ls180.v:3164$708_Y
+ connect \Y $eq$ls180.v:3177$709_Y
end
- attribute \src "ls180.v:3166.109-3166.157"
- cell $eq $eq$ls180.v:3166$710
+ attribute \src "ls180.v:3179.109-3179.157"
+ cell $eq $eq$ls180.v:3179$711
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3166$710_Y
+ connect \Y $eq$ls180.v:3179$711_Y
end
- attribute \src "ls180.v:3167.112-3167.160"
- cell $eq $eq$ls180.v:3167$714
+ attribute \src "ls180.v:3180.112-3180.160"
+ cell $eq $eq$ls180.v:3180$715
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3167$714_Y
+ connect \Y $eq$ls180.v:3180$715_Y
end
- attribute \src "ls180.v:3169.111-3169.159"
- cell $eq $eq$ls180.v:3169$717
+ attribute \src "ls180.v:3182.111-3182.159"
+ cell $eq $eq$ls180.v:3182$718
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3169$717_Y
+ connect \Y $eq$ls180.v:3182$718_Y
end
- attribute \src "ls180.v:3170.114-3170.162"
- cell $eq $eq$ls180.v:3170$721
+ attribute \src "ls180.v:3183.114-3183.162"
+ cell $eq $eq$ls180.v:3183$722
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3170$721_Y
+ connect \Y $eq$ls180.v:3183$722_Y
end
- attribute \src "ls180.v:3172.111-3172.159"
- cell $eq $eq$ls180.v:3172$724
+ attribute \src "ls180.v:3185.111-3185.159"
+ cell $eq $eq$ls180.v:3185$725
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3172$724_Y
+ connect \Y $eq$ls180.v:3185$725_Y
end
- attribute \src "ls180.v:3173.114-3173.162"
- cell $eq $eq$ls180.v:3173$728
+ attribute \src "ls180.v:3186.114-3186.162"
+ cell $eq $eq$ls180.v:3186$729
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3173$728_Y
+ connect \Y $eq$ls180.v:3186$729_Y
end
- attribute \src "ls180.v:3175.111-3175.159"
- cell $eq $eq$ls180.v:3175$731
+ attribute \src "ls180.v:3188.111-3188.159"
+ cell $eq $eq$ls180.v:3188$732
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3175$731_Y
+ connect \Y $eq$ls180.v:3188$732_Y
end
- attribute \src "ls180.v:3176.114-3176.162"
- cell $eq $eq$ls180.v:3176$735
+ attribute \src "ls180.v:3189.114-3189.162"
+ cell $eq $eq$ls180.v:3189$736
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3176$735_Y
+ connect \Y $eq$ls180.v:3189$736_Y
end
- attribute \src "ls180.v:3178.111-3178.159"
- cell $eq $eq$ls180.v:3178$738
+ attribute \src "ls180.v:3191.111-3191.159"
+ cell $eq $eq$ls180.v:3191$739
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3178$738_Y
+ connect \Y $eq$ls180.v:3191$739_Y
end
- attribute \src "ls180.v:3179.114-3179.162"
- cell $eq $eq$ls180.v:3179$742
+ attribute \src "ls180.v:3192.114-3192.162"
+ cell $eq $eq$ls180.v:3192$743
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3179$742_Y
+ connect \Y $eq$ls180.v:3192$743_Y
end
- attribute \src "ls180.v:3181.114-3181.162"
- cell $eq $eq$ls180.v:3181$745
+ attribute \src "ls180.v:3194.114-3194.162"
+ cell $eq $eq$ls180.v:3194$746
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3181$745_Y
+ connect \Y $eq$ls180.v:3194$746_Y
end
- attribute \src "ls180.v:3182.117-3182.165"
- cell $eq $eq$ls180.v:3182$749
+ attribute \src "ls180.v:3195.117-3195.165"
+ cell $eq $eq$ls180.v:3195$750
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3182$749_Y
+ connect \Y $eq$ls180.v:3195$750_Y
end
- attribute \src "ls180.v:3184.114-3184.162"
- cell $eq $eq$ls180.v:3184$752
+ attribute \src "ls180.v:3197.114-3197.162"
+ cell $eq $eq$ls180.v:3197$753
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3184$752_Y
+ connect \Y $eq$ls180.v:3197$753_Y
end
- attribute \src "ls180.v:3185.117-3185.165"
- cell $eq $eq$ls180.v:3185$756
+ attribute \src "ls180.v:3198.117-3198.165"
+ cell $eq $eq$ls180.v:3198$757
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3185$756_Y
+ connect \Y $eq$ls180.v:3198$757_Y
end
- attribute \src "ls180.v:3187.114-3187.162"
- cell $eq $eq$ls180.v:3187$759
+ attribute \src "ls180.v:3200.114-3200.162"
+ cell $eq $eq$ls180.v:3200$760
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3187$759_Y
+ connect \Y $eq$ls180.v:3200$760_Y
end
- attribute \src "ls180.v:3188.117-3188.165"
- cell $eq $eq$ls180.v:3188$763
+ attribute \src "ls180.v:3201.117-3201.165"
+ cell $eq $eq$ls180.v:3201$764
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3188$763_Y
+ connect \Y $eq$ls180.v:3201$764_Y
end
- attribute \src "ls180.v:3190.114-3190.162"
- cell $eq $eq$ls180.v:3190$766
+ attribute \src "ls180.v:3203.114-3203.162"
+ cell $eq $eq$ls180.v:3203$767
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:3190$766_Y
+ connect \Y $eq$ls180.v:3203$767_Y
end
- attribute \src "ls180.v:3191.117-3191.165"
- cell $eq $eq$ls180.v:3191$770
+ attribute \src "ls180.v:3204.117-3204.165"
+ cell $eq $eq$ls180.v:3204$771
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:3191$770_Y
+ connect \Y $eq$ls180.v:3204$771_Y
end
- attribute \src "ls180.v:3202.36-3202.85"
- cell $eq $eq$ls180.v:3202$772
+ attribute \src "ls180.v:3215.36-3215.85"
+ cell $eq $eq$ls180.v:3215$773
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_adr [13:8]
connect \B 3'110
- connect \Y $eq$ls180.v:3202$772_Y
+ connect \Y $eq$ls180.v:3215$773_Y
end
- attribute \src "ls180.v:3204.106-3204.154"
- cell $eq $eq$ls180.v:3204$774
+ attribute \src "ls180.v:3217.106-3217.154"
+ cell $eq $eq$ls180.v:3217$775
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3204$774_Y
+ connect \Y $eq$ls180.v:3217$775_Y
end
- attribute \src "ls180.v:3205.109-3205.157"
- cell $eq $eq$ls180.v:3205$778
+ attribute \src "ls180.v:3218.109-3218.157"
+ cell $eq $eq$ls180.v:3218$779
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3205$778_Y
+ connect \Y $eq$ls180.v:3218$779_Y
end
- attribute \src "ls180.v:3207.105-3207.153"
- cell $eq $eq$ls180.v:3207$781
+ attribute \src "ls180.v:3220.105-3220.153"
+ cell $eq $eq$ls180.v:3220$782
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3207$781_Y
+ connect \Y $eq$ls180.v:3220$782_Y
end
- attribute \src "ls180.v:3208.108-3208.156"
- cell $eq $eq$ls180.v:3208$785
+ attribute \src "ls180.v:3221.108-3221.156"
+ cell $eq $eq$ls180.v:3221$786
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3208$785_Y
+ connect \Y $eq$ls180.v:3221$786_Y
end
- attribute \src "ls180.v:3210.107-3210.155"
- cell $eq $eq$ls180.v:3210$788
+ attribute \src "ls180.v:3223.107-3223.155"
+ cell $eq $eq$ls180.v:3223$789
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3210$788_Y
+ connect \Y $eq$ls180.v:3223$789_Y
end
- attribute \src "ls180.v:3211.110-3211.158"
- cell $eq $eq$ls180.v:3211$792
+ attribute \src "ls180.v:3224.110-3224.158"
+ cell $eq $eq$ls180.v:3224$793
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3211$792_Y
+ connect \Y $eq$ls180.v:3224$793_Y
end
- attribute \src "ls180.v:3216.36-3216.85"
- cell $eq $eq$ls180.v:3216$794
+ attribute \src "ls180.v:3229.36-3229.85"
+ cell $eq $eq$ls180.v:3229$795
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_adr [13:8]
connect \B 3'111
- connect \Y $eq$ls180.v:3216$794_Y
+ connect \Y $eq$ls180.v:3229$795_Y
end
- attribute \src "ls180.v:3218.106-3218.154"
- cell $eq $eq$ls180.v:3218$796
+ attribute \src "ls180.v:3231.106-3231.154"
+ cell $eq $eq$ls180.v:3231$797
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3218$796_Y
+ connect \Y $eq$ls180.v:3231$797_Y
end
- attribute \src "ls180.v:3219.109-3219.157"
- cell $eq $eq$ls180.v:3219$800
+ attribute \src "ls180.v:3232.109-3232.157"
+ cell $eq $eq$ls180.v:3232$801
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3219$800_Y
+ connect \Y $eq$ls180.v:3232$801_Y
end
- attribute \src "ls180.v:3221.105-3221.153"
- cell $eq $eq$ls180.v:3221$803
+ attribute \src "ls180.v:3234.105-3234.153"
+ cell $eq $eq$ls180.v:3234$804
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3221$803_Y
+ connect \Y $eq$ls180.v:3234$804_Y
end
- attribute \src "ls180.v:3222.108-3222.156"
- cell $eq $eq$ls180.v:3222$807
+ attribute \src "ls180.v:3235.108-3235.156"
+ cell $eq $eq$ls180.v:3235$808
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3222$807_Y
+ connect \Y $eq$ls180.v:3235$808_Y
end
- attribute \src "ls180.v:3224.107-3224.155"
- cell $eq $eq$ls180.v:3224$810
+ attribute \src "ls180.v:3237.107-3237.155"
+ cell $eq $eq$ls180.v:3237$811
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3224$810_Y
+ connect \Y $eq$ls180.v:3237$811_Y
end
- attribute \src "ls180.v:3225.110-3225.158"
- cell $eq $eq$ls180.v:3225$814
+ attribute \src "ls180.v:3238.110-3238.158"
+ cell $eq $eq$ls180.v:3238$815
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3225$814_Y
+ connect \Y $eq$ls180.v:3238$815_Y
end
- attribute \src "ls180.v:3230.36-3230.85"
- cell $eq $eq$ls180.v:3230$816
+ attribute \src "ls180.v:3243.36-3243.85"
+ cell $eq $eq$ls180.v:3243$817
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface3_bank_bus_adr [13:8]
connect \B 4'1000
- connect \Y $eq$ls180.v:3230$816_Y
+ connect \Y $eq$ls180.v:3243$817_Y
end
- attribute \src "ls180.v:3232.105-3232.151"
- cell $eq $eq$ls180.v:3232$818
+ attribute \src "ls180.v:3245.105-3245.151"
+ cell $eq $eq$ls180.v:3245$819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface3_bank_bus_adr [0]
connect \B 1'0
- connect \Y $eq$ls180.v:3232$818_Y
+ connect \Y $eq$ls180.v:3245$819_Y
end
- attribute \src "ls180.v:3233.108-3233.154"
- cell $eq $eq$ls180.v:3233$822
+ attribute \src "ls180.v:3246.108-3246.154"
+ cell $eq $eq$ls180.v:3246$823
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface3_bank_bus_adr [0]
connect \B 1'0
- connect \Y $eq$ls180.v:3233$822_Y
+ connect \Y $eq$ls180.v:3246$823_Y
end
- attribute \src "ls180.v:3235.104-3235.150"
- cell $eq $eq$ls180.v:3235$825
+ attribute \src "ls180.v:3248.104-3248.150"
+ cell $eq $eq$ls180.v:3248$826
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface3_bank_bus_adr [0]
connect \B 1'1
- connect \Y $eq$ls180.v:3235$825_Y
+ connect \Y $eq$ls180.v:3248$826_Y
end
- attribute \src "ls180.v:3236.107-3236.153"
- cell $eq $eq$ls180.v:3236$829
+ attribute \src "ls180.v:3249.107-3249.153"
+ cell $eq $eq$ls180.v:3249$830
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface3_bank_bus_adr [0]
connect \B 1'1
- connect \Y $eq$ls180.v:3236$829_Y
+ connect \Y $eq$ls180.v:3249$830_Y
end
- attribute \src "ls180.v:3244.36-3244.85"
- cell $eq $eq$ls180.v:3244$831
+ attribute \src "ls180.v:3257.36-3257.85"
+ cell $eq $eq$ls180.v:3257$832
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [13:8]
connect \B 2'11
- connect \Y $eq$ls180.v:3244$831_Y
+ connect \Y $eq$ls180.v:3257$832_Y
end
- attribute \src "ls180.v:3246.116-3246.164"
- cell $eq $eq$ls180.v:3246$833
+ attribute \src "ls180.v:3259.116-3259.164"
+ cell $eq $eq$ls180.v:3259$834
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3246$833_Y
+ connect \Y $eq$ls180.v:3259$834_Y
end
- attribute \src "ls180.v:3247.119-3247.167"
- cell $eq $eq$ls180.v:3247$837
+ attribute \src "ls180.v:3260.119-3260.167"
+ cell $eq $eq$ls180.v:3260$838
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3247$837_Y
+ connect \Y $eq$ls180.v:3260$838_Y
end
- attribute \src "ls180.v:3249.120-3249.168"
- cell $eq $eq$ls180.v:3249$840
+ attribute \src "ls180.v:3262.120-3262.168"
+ cell $eq $eq$ls180.v:3262$841
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3249$840_Y
+ connect \Y $eq$ls180.v:3262$841_Y
end
- attribute \src "ls180.v:3250.123-3250.171"
- cell $eq $eq$ls180.v:3250$844
+ attribute \src "ls180.v:3263.123-3263.171"
+ cell $eq $eq$ls180.v:3263$845
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3250$844_Y
+ connect \Y $eq$ls180.v:3263$845_Y
end
- attribute \src "ls180.v:3252.101-3252.149"
- cell $eq $eq$ls180.v:3252$847
+ attribute \src "ls180.v:3265.101-3265.149"
+ cell $eq $eq$ls180.v:3265$848
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3252$847_Y
+ connect \Y $eq$ls180.v:3265$848_Y
end
- attribute \src "ls180.v:3253.104-3253.152"
- cell $eq $eq$ls180.v:3253$851
+ attribute \src "ls180.v:3266.104-3266.152"
+ cell $eq $eq$ls180.v:3266$852
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3253$851_Y
+ connect \Y $eq$ls180.v:3266$852_Y
end
- attribute \src "ls180.v:3255.120-3255.168"
- cell $eq $eq$ls180.v:3255$854
+ attribute \src "ls180.v:3268.120-3268.168"
+ cell $eq $eq$ls180.v:3268$855
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3255$854_Y
+ connect \Y $eq$ls180.v:3268$855_Y
end
- attribute \src "ls180.v:3256.123-3256.171"
- cell $eq $eq$ls180.v:3256$858
+ attribute \src "ls180.v:3269.123-3269.171"
+ cell $eq $eq$ls180.v:3269$859
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3256$858_Y
+ connect \Y $eq$ls180.v:3269$859_Y
end
- attribute \src "ls180.v:3258.120-3258.168"
- cell $eq $eq$ls180.v:3258$861
+ attribute \src "ls180.v:3271.120-3271.168"
+ cell $eq $eq$ls180.v:3271$862
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3258$861_Y
+ connect \Y $eq$ls180.v:3271$862_Y
end
- attribute \src "ls180.v:3259.123-3259.171"
- cell $eq $eq$ls180.v:3259$865
+ attribute \src "ls180.v:3272.123-3272.171"
+ cell $eq $eq$ls180.v:3272$866
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3259$865_Y
+ connect \Y $eq$ls180.v:3272$866_Y
end
- attribute \src "ls180.v:3261.121-3261.169"
- cell $eq $eq$ls180.v:3261$868
+ attribute \src "ls180.v:3274.121-3274.169"
+ cell $eq $eq$ls180.v:3274$869
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3261$868_Y
+ connect \Y $eq$ls180.v:3274$869_Y
end
- attribute \src "ls180.v:3262.124-3262.172"
- cell $eq $eq$ls180.v:3262$872
+ attribute \src "ls180.v:3275.124-3275.172"
+ cell $eq $eq$ls180.v:3275$873
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3262$872_Y
+ connect \Y $eq$ls180.v:3275$873_Y
end
- attribute \src "ls180.v:3264.119-3264.167"
- cell $eq $eq$ls180.v:3264$875
+ attribute \src "ls180.v:3277.119-3277.167"
+ cell $eq $eq$ls180.v:3277$876
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3264$875_Y
+ connect \Y $eq$ls180.v:3277$876_Y
end
- attribute \src "ls180.v:3265.122-3265.170"
- cell $eq $eq$ls180.v:3265$879
+ attribute \src "ls180.v:3278.122-3278.170"
+ cell $eq $eq$ls180.v:3278$880
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3265$879_Y
+ connect \Y $eq$ls180.v:3278$880_Y
end
- attribute \src "ls180.v:3267.119-3267.167"
- cell $eq $eq$ls180.v:3267$882
+ attribute \src "ls180.v:3280.119-3280.167"
+ cell $eq $eq$ls180.v:3280$883
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3267$882_Y
+ connect \Y $eq$ls180.v:3280$883_Y
end
- attribute \src "ls180.v:3268.122-3268.170"
- cell $eq $eq$ls180.v:3268$886
+ attribute \src "ls180.v:3281.122-3281.170"
+ cell $eq $eq$ls180.v:3281$887
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3268$886_Y
+ connect \Y $eq$ls180.v:3281$887_Y
end
- attribute \src "ls180.v:3270.119-3270.167"
- cell $eq $eq$ls180.v:3270$889
+ attribute \src "ls180.v:3283.119-3283.167"
+ cell $eq $eq$ls180.v:3283$890
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:3270$889_Y
+ connect \Y $eq$ls180.v:3283$890_Y
end
- attribute \src "ls180.v:3271.122-3271.170"
- cell $eq $eq$ls180.v:3271$893
+ attribute \src "ls180.v:3284.122-3284.170"
+ cell $eq $eq$ls180.v:3284$894
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:3271$893_Y
+ connect \Y $eq$ls180.v:3284$894_Y
end
- attribute \src "ls180.v:3273.119-3273.167"
- cell $eq $eq$ls180.v:3273$896
+ attribute \src "ls180.v:3286.119-3286.167"
+ cell $eq $eq$ls180.v:3286$897
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:3273$896_Y
+ connect \Y $eq$ls180.v:3286$897_Y
end
- attribute \src "ls180.v:3274.122-3274.170"
- cell $eq $eq$ls180.v:3274$900
+ attribute \src "ls180.v:3287.122-3287.170"
+ cell $eq $eq$ls180.v:3287$901
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_adr [3:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:3274$900_Y
+ connect \Y $eq$ls180.v:3287$901_Y
end
- attribute \src "ls180.v:3289.36-3289.85"
- cell $eq $eq$ls180.v:3289$902
+ attribute \src "ls180.v:3302.36-3302.85"
+ cell $eq $eq$ls180.v:3302$903
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [13:8]
connect \B 2'10
- connect \Y $eq$ls180.v:3289$902_Y
+ connect \Y $eq$ls180.v:3302$903_Y
end
- attribute \src "ls180.v:3291.108-3291.156"
- cell $eq $eq$ls180.v:3291$904
+ attribute \src "ls180.v:3304.108-3304.156"
+ cell $eq $eq$ls180.v:3304$905
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3291$904_Y
+ connect \Y $eq$ls180.v:3304$905_Y
end
- attribute \src "ls180.v:3292.111-3292.159"
- cell $eq $eq$ls180.v:3292$908
+ attribute \src "ls180.v:3305.111-3305.159"
+ cell $eq $eq$ls180.v:3305$909
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3292$908_Y
+ connect \Y $eq$ls180.v:3305$909_Y
end
- attribute \src "ls180.v:3294.108-3294.156"
- cell $eq $eq$ls180.v:3294$911
+ attribute \src "ls180.v:3307.108-3307.156"
+ cell $eq $eq$ls180.v:3307$912
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3294$911_Y
+ connect \Y $eq$ls180.v:3307$912_Y
end
- attribute \src "ls180.v:3295.111-3295.159"
- cell $eq $eq$ls180.v:3295$915
+ attribute \src "ls180.v:3308.111-3308.159"
+ cell $eq $eq$ls180.v:3308$916
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3295$915_Y
+ connect \Y $eq$ls180.v:3308$916_Y
end
- attribute \src "ls180.v:3297.108-3297.156"
- cell $eq $eq$ls180.v:3297$918
+ attribute \src "ls180.v:3310.108-3310.156"
+ cell $eq $eq$ls180.v:3310$919
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3297$918_Y
+ connect \Y $eq$ls180.v:3310$919_Y
end
- attribute \src "ls180.v:3298.111-3298.159"
- cell $eq $eq$ls180.v:3298$922
+ attribute \src "ls180.v:3311.111-3311.159"
+ cell $eq $eq$ls180.v:3311$923
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3298$922_Y
+ connect \Y $eq$ls180.v:3311$923_Y
end
- attribute \src "ls180.v:3300.108-3300.156"
- cell $eq $eq$ls180.v:3300$925
+ attribute \src "ls180.v:3313.108-3313.156"
+ cell $eq $eq$ls180.v:3313$926
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3300$925_Y
+ connect \Y $eq$ls180.v:3313$926_Y
end
- attribute \src "ls180.v:3301.111-3301.159"
- cell $eq $eq$ls180.v:3301$929
+ attribute \src "ls180.v:3314.111-3314.159"
+ cell $eq $eq$ls180.v:3314$930
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3301$929_Y
+ connect \Y $eq$ls180.v:3314$930_Y
end
- attribute \src "ls180.v:3303.110-3303.158"
- cell $eq $eq$ls180.v:3303$932
+ attribute \src "ls180.v:3316.110-3316.158"
+ cell $eq $eq$ls180.v:3316$933
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3303$932_Y
+ connect \Y $eq$ls180.v:3316$933_Y
end
- attribute \src "ls180.v:3304.113-3304.161"
- cell $eq $eq$ls180.v:3304$936
+ attribute \src "ls180.v:3317.113-3317.161"
+ cell $eq $eq$ls180.v:3317$937
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3304$936_Y
+ connect \Y $eq$ls180.v:3317$937_Y
end
- attribute \src "ls180.v:3306.110-3306.158"
- cell $eq $eq$ls180.v:3306$939
+ attribute \src "ls180.v:3319.110-3319.158"
+ cell $eq $eq$ls180.v:3319$940
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3306$939_Y
+ connect \Y $eq$ls180.v:3319$940_Y
end
- attribute \src "ls180.v:3307.113-3307.161"
- cell $eq $eq$ls180.v:3307$943
+ attribute \src "ls180.v:3320.113-3320.161"
+ cell $eq $eq$ls180.v:3320$944
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3307$943_Y
+ connect \Y $eq$ls180.v:3320$944_Y
end
- attribute \src "ls180.v:3309.110-3309.158"
- cell $eq $eq$ls180.v:3309$946
+ attribute \src "ls180.v:3322.110-3322.158"
+ cell $eq $eq$ls180.v:3322$947
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3309$946_Y
+ connect \Y $eq$ls180.v:3322$947_Y
end
- attribute \src "ls180.v:3310.113-3310.161"
- cell $eq $eq$ls180.v:3310$950
+ attribute \src "ls180.v:3323.113-3323.161"
+ cell $eq $eq$ls180.v:3323$951
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3310$950_Y
+ connect \Y $eq$ls180.v:3323$951_Y
end
- attribute \src "ls180.v:3312.110-3312.158"
- cell $eq $eq$ls180.v:3312$953
+ attribute \src "ls180.v:3325.110-3325.158"
+ cell $eq $eq$ls180.v:3325$954
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3312$953_Y
+ connect \Y $eq$ls180.v:3325$954_Y
end
- attribute \src "ls180.v:3313.113-3313.161"
- cell $eq $eq$ls180.v:3313$957
+ attribute \src "ls180.v:3326.113-3326.161"
+ cell $eq $eq$ls180.v:3326$958
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3313$957_Y
+ connect \Y $eq$ls180.v:3326$958_Y
end
- attribute \src "ls180.v:3315.106-3315.154"
- cell $eq $eq$ls180.v:3315$960
+ attribute \src "ls180.v:3328.106-3328.154"
+ cell $eq $eq$ls180.v:3328$961
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:3315$960_Y
+ connect \Y $eq$ls180.v:3328$961_Y
end
- attribute \src "ls180.v:3316.109-3316.157"
- cell $eq $eq$ls180.v:3316$964
+ attribute \src "ls180.v:3329.109-3329.157"
+ cell $eq $eq$ls180.v:3329$965
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1000
- connect \Y $eq$ls180.v:3316$964_Y
+ connect \Y $eq$ls180.v:3329$965_Y
end
- attribute \src "ls180.v:3318.116-3318.164"
- cell $eq $eq$ls180.v:3318$967
+ attribute \src "ls180.v:3331.116-3331.164"
+ cell $eq $eq$ls180.v:3331$968
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:3318$967_Y
+ connect \Y $eq$ls180.v:3331$968_Y
end
- attribute \src "ls180.v:3319.119-3319.167"
- cell $eq $eq$ls180.v:3319$971
+ attribute \src "ls180.v:3332.119-3332.167"
+ cell $eq $eq$ls180.v:3332$972
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1001
- connect \Y $eq$ls180.v:3319$971_Y
+ connect \Y $eq$ls180.v:3332$972_Y
end
- attribute \src "ls180.v:3321.109-3321.158"
- cell $eq $eq$ls180.v:3321$974
+ attribute \src "ls180.v:3334.109-3334.158"
+ cell $eq $eq$ls180.v:3334$975
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:3321$974_Y
+ connect \Y $eq$ls180.v:3334$975_Y
end
- attribute \src "ls180.v:3322.112-3322.161"
- cell $eq $eq$ls180.v:3322$978
+ attribute \src "ls180.v:3335.112-3335.161"
+ cell $eq $eq$ls180.v:3335$979
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1010
- connect \Y $eq$ls180.v:3322$978_Y
+ connect \Y $eq$ls180.v:3335$979_Y
end
- attribute \src "ls180.v:3324.109-3324.158"
- cell $eq $eq$ls180.v:3324$981
+ attribute \src "ls180.v:3337.109-3337.158"
+ cell $eq $eq$ls180.v:3337$982
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:3324$981_Y
+ connect \Y $eq$ls180.v:3337$982_Y
end
- attribute \src "ls180.v:3325.112-3325.161"
- cell $eq $eq$ls180.v:3325$985
+ attribute \src "ls180.v:3338.112-3338.161"
+ cell $eq $eq$ls180.v:3338$986
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1011
- connect \Y $eq$ls180.v:3325$985_Y
+ connect \Y $eq$ls180.v:3338$986_Y
end
- attribute \src "ls180.v:3327.109-3327.158"
- cell $eq $eq$ls180.v:3327$988
+ attribute \src "ls180.v:3340.109-3340.158"
+ cell $eq $eq$ls180.v:3340$989
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:3327$988_Y
+ connect \Y $eq$ls180.v:3340$989_Y
end
- attribute \src "ls180.v:3328.112-3328.161"
- cell $eq $eq$ls180.v:3328$992
+ attribute \src "ls180.v:3341.112-3341.161"
+ cell $eq $eq$ls180.v:3341$993
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1100
- connect \Y $eq$ls180.v:3328$992_Y
+ connect \Y $eq$ls180.v:3341$993_Y
end
- attribute \src "ls180.v:3330.109-3330.158"
- cell $eq $eq$ls180.v:3330$995
+ attribute \src "ls180.v:3343.109-3343.158"
+ cell $eq $eq$ls180.v:3343$996
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:3330$995_Y
+ connect \Y $eq$ls180.v:3343$996_Y
end
- attribute \src "ls180.v:3331.112-3331.161"
- cell $eq $eq$ls180.v:3331$999
+ attribute \src "ls180.v:3344.112-3344.161"
+ cell $eq $eq$ls180.v:3344$1000
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1101
- connect \Y $eq$ls180.v:3331$999_Y
+ connect \Y $eq$ls180.v:3344$1000_Y
end
- attribute \src "ls180.v:3333.113-3333.162"
- cell $eq $eq$ls180.v:3333$1002
+ attribute \src "ls180.v:3346.113-3346.162"
+ cell $eq $eq$ls180.v:3346$1003
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:3333$1002_Y
+ connect \Y $eq$ls180.v:3346$1003_Y
end
- attribute \src "ls180.v:3334.116-3334.165"
- cell $eq $eq$ls180.v:3334$1006
+ attribute \src "ls180.v:3347.116-3347.165"
+ cell $eq $eq$ls180.v:3347$1007
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1110
- connect \Y $eq$ls180.v:3334$1006_Y
+ connect \Y $eq$ls180.v:3347$1007_Y
end
- attribute \src "ls180.v:3336.114-3336.163"
- cell $eq $eq$ls180.v:3336$1009
+ attribute \src "ls180.v:3349.114-3349.163"
+ cell $eq $eq$ls180.v:3349$1010
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:3336$1009_Y
+ connect \Y $eq$ls180.v:3349$1010_Y
end
- attribute \src "ls180.v:3337.117-3337.166"
- cell $eq $eq$ls180.v:3337$1013
+ attribute \src "ls180.v:3350.117-3350.166"
+ cell $eq $eq$ls180.v:3350$1014
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 4'1111
- connect \Y $eq$ls180.v:3337$1013_Y
+ connect \Y $eq$ls180.v:3350$1014_Y
end
- attribute \src "ls180.v:3339.113-3339.162"
- cell $eq $eq$ls180.v:3339$1016
+ attribute \src "ls180.v:3352.113-3352.162"
+ cell $eq $eq$ls180.v:3352$1017
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:3339$1016_Y
+ connect \Y $eq$ls180.v:3352$1017_Y
end
- attribute \src "ls180.v:3340.116-3340.165"
- cell $eq $eq$ls180.v:3340$1020
+ attribute \src "ls180.v:3353.116-3353.165"
+ cell $eq $eq$ls180.v:3353$1021
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_adr [4:0]
connect \B 5'10000
- connect \Y $eq$ls180.v:3340$1020_Y
+ connect \Y $eq$ls180.v:3353$1021_Y
end
- attribute \src "ls180.v:3357.36-3357.85"
- cell $eq $eq$ls180.v:3357$1022
+ attribute \src "ls180.v:3370.36-3370.85"
+ cell $eq $eq$ls180.v:3370$1023
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [13:8]
connect \B 3'101
- connect \Y $eq$ls180.v:3357$1022_Y
+ connect \Y $eq$ls180.v:3370$1023_Y
end
- attribute \src "ls180.v:3359.86-3359.134"
- cell $eq $eq$ls180.v:3359$1024
+ attribute \src "ls180.v:3372.86-3372.134"
+ cell $eq $eq$ls180.v:3372$1025
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3359$1024_Y
+ connect \Y $eq$ls180.v:3372$1025_Y
end
- attribute \src "ls180.v:3360.89-3360.137"
- cell $eq $eq$ls180.v:3360$1028
+ attribute \src "ls180.v:3373.89-3373.137"
+ cell $eq $eq$ls180.v:3373$1029
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3360$1028_Y
+ connect \Y $eq$ls180.v:3373$1029_Y
end
- attribute \src "ls180.v:3362.109-3362.157"
- cell $eq $eq$ls180.v:3362$1031
+ attribute \src "ls180.v:3375.109-3375.157"
+ cell $eq $eq$ls180.v:3375$1032
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3362$1031_Y
+ connect \Y $eq$ls180.v:3375$1032_Y
end
- attribute \src "ls180.v:3363.112-3363.160"
- cell $eq $eq$ls180.v:3363$1035
+ attribute \src "ls180.v:3376.112-3376.160"
+ cell $eq $eq$ls180.v:3376$1036
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3363$1035_Y
+ connect \Y $eq$ls180.v:3376$1036_Y
end
- attribute \src "ls180.v:3365.110-3365.158"
- cell $eq $eq$ls180.v:3365$1038
+ attribute \src "ls180.v:3378.110-3378.158"
+ cell $eq $eq$ls180.v:3378$1039
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3365$1038_Y
+ connect \Y $eq$ls180.v:3378$1039_Y
end
- attribute \src "ls180.v:3366.113-3366.161"
- cell $eq $eq$ls180.v:3366$1042
+ attribute \src "ls180.v:3379.113-3379.161"
+ cell $eq $eq$ls180.v:3379$1043
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3366$1042_Y
+ connect \Y $eq$ls180.v:3379$1043_Y
end
- attribute \src "ls180.v:3368.101-3368.149"
- cell $eq $eq$ls180.v:3368$1045
+ attribute \src "ls180.v:3381.101-3381.149"
+ cell $eq $eq$ls180.v:3381$1046
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3368$1045_Y
+ connect \Y $eq$ls180.v:3381$1046_Y
end
- attribute \src "ls180.v:3369.104-3369.152"
- cell $eq $eq$ls180.v:3369$1049
+ attribute \src "ls180.v:3382.104-3382.152"
+ cell $eq $eq$ls180.v:3382$1050
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3369$1049_Y
+ connect \Y $eq$ls180.v:3382$1050_Y
end
- attribute \src "ls180.v:3371.102-3371.150"
- cell $eq $eq$ls180.v:3371$1052
+ attribute \src "ls180.v:3384.102-3384.150"
+ cell $eq $eq$ls180.v:3384$1053
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3371$1052_Y
+ connect \Y $eq$ls180.v:3384$1053_Y
end
- attribute \src "ls180.v:3372.105-3372.153"
- cell $eq $eq$ls180.v:3372$1056
+ attribute \src "ls180.v:3385.105-3385.153"
+ cell $eq $eq$ls180.v:3385$1057
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'100
- connect \Y $eq$ls180.v:3372$1056_Y
+ connect \Y $eq$ls180.v:3385$1057_Y
end
- attribute \src "ls180.v:3374.113-3374.161"
- cell $eq $eq$ls180.v:3374$1059
+ attribute \src "ls180.v:3387.113-3387.161"
+ cell $eq $eq$ls180.v:3387$1060
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3374$1059_Y
+ connect \Y $eq$ls180.v:3387$1060_Y
end
- attribute \src "ls180.v:3375.116-3375.164"
- cell $eq $eq$ls180.v:3375$1063
+ attribute \src "ls180.v:3388.116-3388.164"
+ cell $eq $eq$ls180.v:3388$1064
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'101
- connect \Y $eq$ls180.v:3375$1063_Y
+ connect \Y $eq$ls180.v:3388$1064_Y
end
- attribute \src "ls180.v:3377.110-3377.158"
- cell $eq $eq$ls180.v:3377$1066
+ attribute \src "ls180.v:3390.110-3390.158"
+ cell $eq $eq$ls180.v:3390$1067
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3377$1066_Y
+ connect \Y $eq$ls180.v:3390$1067_Y
end
- attribute \src "ls180.v:3378.113-3378.161"
- cell $eq $eq$ls180.v:3378$1070
+ attribute \src "ls180.v:3391.113-3391.161"
+ cell $eq $eq$ls180.v:3391$1071
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'110
- connect \Y $eq$ls180.v:3378$1070_Y
+ connect \Y $eq$ls180.v:3391$1071_Y
end
- attribute \src "ls180.v:3380.109-3380.157"
- cell $eq $eq$ls180.v:3380$1073
+ attribute \src "ls180.v:3393.109-3393.157"
+ cell $eq $eq$ls180.v:3393$1074
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3380$1073_Y
+ connect \Y $eq$ls180.v:3393$1074_Y
end
- attribute \src "ls180.v:3381.112-3381.160"
- cell $eq $eq$ls180.v:3381$1077
+ attribute \src "ls180.v:3394.112-3394.160"
+ cell $eq $eq$ls180.v:3394$1078
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_adr [2:0]
connect \B 3'111
- connect \Y $eq$ls180.v:3381$1077_Y
+ connect \Y $eq$ls180.v:3394$1078_Y
end
- attribute \src "ls180.v:3391.36-3391.85"
- cell $eq $eq$ls180.v:3391$1079
+ attribute \src "ls180.v:3404.36-3404.85"
+ cell $eq $eq$ls180.v:3404$1080
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [13:8]
connect \B 3'100
- connect \Y $eq$ls180.v:3391$1079_Y
+ connect \Y $eq$ls180.v:3404$1080_Y
end
- attribute \src "ls180.v:3393.115-3393.163"
- cell $eq $eq$ls180.v:3393$1081
+ attribute \src "ls180.v:3406.115-3406.163"
+ cell $eq $eq$ls180.v:3406$1082
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3393$1081_Y
+ connect \Y $eq$ls180.v:3406$1082_Y
end
- attribute \src "ls180.v:3394.118-3394.166"
- cell $eq $eq$ls180.v:3394$1085
+ attribute \src "ls180.v:3407.118-3407.166"
+ cell $eq $eq$ls180.v:3407$1086
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 1'0
- connect \Y $eq$ls180.v:3394$1085_Y
+ connect \Y $eq$ls180.v:3407$1086_Y
end
- attribute \src "ls180.v:3396.115-3396.163"
- cell $eq $eq$ls180.v:3396$1088
+ attribute \src "ls180.v:3409.115-3409.163"
+ cell $eq $eq$ls180.v:3409$1089
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3396$1088_Y
+ connect \Y $eq$ls180.v:3409$1089_Y
end
- attribute \src "ls180.v:3397.118-3397.166"
- cell $eq $eq$ls180.v:3397$1092
+ attribute \src "ls180.v:3410.118-3410.166"
+ cell $eq $eq$ls180.v:3410$1093
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 1'1
- connect \Y $eq$ls180.v:3397$1092_Y
+ connect \Y $eq$ls180.v:3410$1093_Y
end
- attribute \src "ls180.v:3399.115-3399.163"
- cell $eq $eq$ls180.v:3399$1095
+ attribute \src "ls180.v:3412.115-3412.163"
+ cell $eq $eq$ls180.v:3412$1096
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3399$1095_Y
+ connect \Y $eq$ls180.v:3412$1096_Y
end
- attribute \src "ls180.v:3400.118-3400.166"
- cell $eq $eq$ls180.v:3400$1099
+ attribute \src "ls180.v:3413.118-3413.166"
+ cell $eq $eq$ls180.v:3413$1100
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 2'10
- connect \Y $eq$ls180.v:3400$1099_Y
+ connect \Y $eq$ls180.v:3413$1100_Y
end
- attribute \src "ls180.v:3402.115-3402.163"
- cell $eq $eq$ls180.v:3402$1102
+ attribute \src "ls180.v:3415.115-3415.163"
+ cell $eq $eq$ls180.v:3415$1103
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3402$1102_Y
+ connect \Y $eq$ls180.v:3415$1103_Y
end
- attribute \src "ls180.v:3403.118-3403.166"
- cell $eq $eq$ls180.v:3403$1106
+ attribute \src "ls180.v:3416.118-3416.166"
+ cell $eq $eq$ls180.v:3416$1107
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_adr [1:0]
connect \B 2'11
- connect \Y $eq$ls180.v:3403$1106_Y
+ connect \Y $eq$ls180.v:3416$1107_Y
end
- attribute \src "ls180.v:3763.28-3763.63"
- cell $eq $eq$ls180.v:3763$1136
+ attribute \src "ls180.v:3776.28-3776.63"
+ cell $eq $eq$ls180.v:3776$1137
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 1'0
- connect \Y $eq$ls180.v:3763$1136_Y
+ connect \Y $eq$ls180.v:3776$1137_Y
end
- attribute \src "ls180.v:3763.126-3763.164"
- cell $eq $eq$ls180.v:3763$1137
+ attribute \src "ls180.v:3776.126-3776.164"
+ cell $eq $eq$ls180.v:3776$1138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3763$1137_Y
+ connect \Y $eq$ls180.v:3776$1138_Y
end
- attribute \src "ls180.v:3763.201-3763.239"
- cell $eq $eq$ls180.v:3763$1140
+ attribute \src "ls180.v:3776.201-3776.239"
+ cell $eq $eq$ls180.v:3776$1141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3763$1140_Y
+ connect \Y $eq$ls180.v:3776$1141_Y
end
- attribute \src "ls180.v:3763.276-3763.314"
- cell $eq $eq$ls180.v:3763$1143
+ attribute \src "ls180.v:3776.276-3776.314"
+ cell $eq $eq$ls180.v:3776$1144
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3763$1143_Y
+ connect \Y $eq$ls180.v:3776$1144_Y
end
- attribute \src "ls180.v:3787.28-3787.63"
- cell $eq $eq$ls180.v:3787$1152
+ attribute \src "ls180.v:3800.28-3800.63"
+ cell $eq $eq$ls180.v:3800$1153
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 1'1
- connect \Y $eq$ls180.v:3787$1152_Y
+ connect \Y $eq$ls180.v:3800$1153_Y
end
- attribute \src "ls180.v:3787.126-3787.164"
- cell $eq $eq$ls180.v:3787$1153
+ attribute \src "ls180.v:3800.126-3800.164"
+ cell $eq $eq$ls180.v:3800$1154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3787$1153_Y
+ connect \Y $eq$ls180.v:3800$1154_Y
end
- attribute \src "ls180.v:3787.201-3787.239"
- cell $eq $eq$ls180.v:3787$1156
+ attribute \src "ls180.v:3800.201-3800.239"
+ cell $eq $eq$ls180.v:3800$1157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3787$1156_Y
+ connect \Y $eq$ls180.v:3800$1157_Y
end
- attribute \src "ls180.v:3787.276-3787.314"
- cell $eq $eq$ls180.v:3787$1159
+ attribute \src "ls180.v:3800.276-3800.314"
+ cell $eq $eq$ls180.v:3800$1160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3787$1159_Y
+ connect \Y $eq$ls180.v:3800$1160_Y
end
- attribute \src "ls180.v:3811.28-3811.63"
- cell $eq $eq$ls180.v:3811$1168
+ attribute \src "ls180.v:3824.28-3824.63"
+ cell $eq $eq$ls180.v:3824$1169
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 2'10
- connect \Y $eq$ls180.v:3811$1168_Y
+ connect \Y $eq$ls180.v:3824$1169_Y
end
- attribute \src "ls180.v:3811.126-3811.164"
- cell $eq $eq$ls180.v:3811$1169
+ attribute \src "ls180.v:3824.126-3824.164"
+ cell $eq $eq$ls180.v:3824$1170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3811$1169_Y
+ connect \Y $eq$ls180.v:3824$1170_Y
end
- attribute \src "ls180.v:3811.201-3811.239"
- cell $eq $eq$ls180.v:3811$1172
+ attribute \src "ls180.v:3824.201-3824.239"
+ cell $eq $eq$ls180.v:3824$1173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3811$1172_Y
+ connect \Y $eq$ls180.v:3824$1173_Y
end
- attribute \src "ls180.v:3811.276-3811.314"
- cell $eq $eq$ls180.v:3811$1175
+ attribute \src "ls180.v:3824.276-3824.314"
+ cell $eq $eq$ls180.v:3824$1176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3811$1175_Y
+ connect \Y $eq$ls180.v:3824$1176_Y
end
- attribute \src "ls180.v:3835.28-3835.63"
- cell $eq $eq$ls180.v:3835$1184
+ attribute \src "ls180.v:3848.28-3848.63"
+ cell $eq $eq$ls180.v:3848$1185
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_addr [10:9]
connect \B 2'11
- connect \Y $eq$ls180.v:3835$1184_Y
+ connect \Y $eq$ls180.v:3848$1185_Y
end
- attribute \src "ls180.v:3835.126-3835.164"
- cell $eq $eq$ls180.v:3835$1185
+ attribute \src "ls180.v:3848.126-3848.164"
+ cell $eq $eq$ls180.v:3848$1186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3835$1185_Y
+ connect \Y $eq$ls180.v:3848$1186_Y
end
- attribute \src "ls180.v:3835.201-3835.239"
- cell $eq $eq$ls180.v:3835$1188
+ attribute \src "ls180.v:3848.201-3848.239"
+ cell $eq $eq$ls180.v:3848$1189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3835$1188_Y
+ connect \Y $eq$ls180.v:3848$1189_Y
end
- attribute \src "ls180.v:3835.276-3835.314"
- cell $eq $eq$ls180.v:3835$1191
+ attribute \src "ls180.v:3848.276-3848.314"
+ cell $eq $eq$ls180.v:3848$1192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:3835$1191_Y
+ connect \Y $eq$ls180.v:3848$1192_Y
end
- attribute \src "ls180.v:4361.8-4361.33"
- cell $eq $eq$ls180.v:4361$1285
+ attribute \src "ls180.v:4380.8-4380.33"
+ cell $eq $eq$ls180.v:4380$1292
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_value
connect \B 1'0
- connect \Y $eq$ls180.v:4361$1285_Y
+ connect \Y $eq$ls180.v:4380$1292_Y
end
- attribute \src "ls180.v:4396.8-4396.37"
- cell $eq $eq$ls180.v:4396$1296
+ attribute \src "ls180.v:4415.8-4415.37"
+ cell $eq $eq$ls180.v:4415$1303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_postponer_count
connect \B 1'0
- connect \Y $eq$ls180.v:4396$1296_Y
+ connect \Y $eq$ls180.v:4415$1303_Y
end
- attribute \src "ls180.v:4416.33-4416.64"
- cell $eq $eq$ls180.v:4416$1299
+ attribute \src "ls180.v:4435.33-4435.64"
+ cell $eq $eq$ls180.v:4435$1306
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_counter
connect \B 1'0
- connect \Y $eq$ls180.v:4416$1299_Y
+ connect \Y $eq$ls180.v:4435$1306_Y
end
- attribute \src "ls180.v:4423.7-4423.38"
- cell $eq $eq$ls180.v:4423$1301
+ attribute \src "ls180.v:4442.7-4442.38"
+ cell $eq $eq$ls180.v:4442$1308
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_counter
connect \B 2'10
- connect \Y $eq$ls180.v:4423$1301_Y
+ connect \Y $eq$ls180.v:4442$1308_Y
end
- attribute \src "ls180.v:4430.7-4430.38"
- cell $eq $eq$ls180.v:4430$1302
+ attribute \src "ls180.v:4449.7-4449.38"
+ cell $eq $eq$ls180.v:4449$1309
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_counter
connect \B 4'1000
- connect \Y $eq$ls180.v:4430$1302_Y
+ connect \Y $eq$ls180.v:4449$1309_Y
end
- attribute \src "ls180.v:4438.7-4438.38"
- cell $eq $eq$ls180.v:4438$1303
+ attribute \src "ls180.v:4457.7-4457.38"
+ cell $eq $eq$ls180.v:4457$1310
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_counter
connect \B 4'1000
- connect \Y $eq$ls180.v:4438$1303_Y
+ connect \Y $eq$ls180.v:4457$1310_Y
end
- attribute \src "ls180.v:4490.9-4490.49"
- cell $eq $eq$ls180.v:4490$1321
+ attribute \src "ls180.v:4509.9-4509.49"
+ cell $eq $eq$ls180.v:4509$1328
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:4490$1321_Y
+ connect \Y $eq$ls180.v:4509$1328_Y
end
- attribute \src "ls180.v:4536.9-4536.49"
- cell $eq $eq$ls180.v:4536$1337
+ attribute \src "ls180.v:4555.9-4555.49"
+ cell $eq $eq$ls180.v:4555$1344
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:4536$1337_Y
+ connect \Y $eq$ls180.v:4555$1344_Y
end
- attribute \src "ls180.v:4582.9-4582.49"
- cell $eq $eq$ls180.v:4582$1353
+ attribute \src "ls180.v:4601.9-4601.49"
+ cell $eq $eq$ls180.v:4601$1360
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:4582$1353_Y
+ connect \Y $eq$ls180.v:4601$1360_Y
end
- attribute \src "ls180.v:4628.9-4628.49"
- cell $eq $eq$ls180.v:4628$1369
+ attribute \src "ls180.v:4647.9-4647.49"
+ cell $eq $eq$ls180.v:4647$1376
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_twtpcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:4628$1369_Y
+ connect \Y $eq$ls180.v:4647$1376_Y
end
- attribute \src "ls180.v:4778.9-4778.36"
- cell $eq $eq$ls180.v:4778$1381
+ attribute \src "ls180.v:4797.9-4797.36"
+ cell $eq $eq$ls180.v:4797$1388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_tccdcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:4778$1381_Y
+ connect \Y $eq$ls180.v:4797$1388_Y
end
- attribute \src "ls180.v:4793.9-4793.36"
- cell $eq $eq$ls180.v:4793$1384
+ attribute \src "ls180.v:4812.9-4812.36"
+ cell $eq $eq$ls180.v:4812$1391
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_twtrcon_count
connect \B 1'1
- connect \Y $eq$ls180.v:4793$1384_Y
+ connect \Y $eq$ls180.v:4812$1391_Y
end
- attribute \src "ls180.v:4799.54-4799.92"
- cell $eq $eq$ls180.v:4799$1385
+ attribute \src "ls180.v:4818.54-4818.92"
+ cell $eq $eq$ls180.v:4818$1392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4799$1385_Y
+ connect \Y $eq$ls180.v:4818$1392_Y
end
- attribute \src "ls180.v:4799.136-4799.174"
- cell $eq $eq$ls180.v:4799$1388
+ attribute \src "ls180.v:4818.136-4818.174"
+ cell $eq $eq$ls180.v:4818$1395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4799$1388_Y
+ connect \Y $eq$ls180.v:4818$1395_Y
end
- attribute \src "ls180.v:4799.218-4799.256"
- cell $eq $eq$ls180.v:4799$1391
+ attribute \src "ls180.v:4818.218-4818.256"
+ cell $eq $eq$ls180.v:4818$1398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4799$1391_Y
+ connect \Y $eq$ls180.v:4818$1398_Y
end
- attribute \src "ls180.v:4799.300-4799.338"
- cell $eq $eq$ls180.v:4799$1394
+ attribute \src "ls180.v:4818.300-4818.338"
+ cell $eq $eq$ls180.v:4818$1401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4799$1394_Y
+ connect \Y $eq$ls180.v:4818$1401_Y
end
- attribute \src "ls180.v:4800.55-4800.93"
- cell $eq $eq$ls180.v:4800$1397
+ attribute \src "ls180.v:4819.55-4819.93"
+ cell $eq $eq$ls180.v:4819$1404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin0_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4800$1397_Y
+ connect \Y $eq$ls180.v:4819$1404_Y
end
- attribute \src "ls180.v:4800.137-4800.175"
- cell $eq $eq$ls180.v:4800$1400
+ attribute \src "ls180.v:4819.137-4819.175"
+ cell $eq $eq$ls180.v:4819$1407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin1_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4800$1400_Y
+ connect \Y $eq$ls180.v:4819$1407_Y
end
- attribute \src "ls180.v:4800.219-4800.257"
- cell $eq $eq$ls180.v:4800$1403
+ attribute \src "ls180.v:4819.219-4819.257"
+ cell $eq $eq$ls180.v:4819$1410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin2_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4800$1403_Y
+ connect \Y $eq$ls180.v:4819$1410_Y
end
- attribute \src "ls180.v:4800.301-4800.339"
- cell $eq $eq$ls180.v:4800$1406
+ attribute \src "ls180.v:4819.301-4819.339"
+ cell $eq $eq$ls180.v:4819$1413
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \subfragments_roundrobin3_grant
connect \B 1'0
- connect \Y $eq$ls180.v:4800$1406_Y
+ connect \Y $eq$ls180.v:4819$1413_Y
end
- attribute \src "ls180.v:4835.9-4835.37"
- cell $eq $eq$ls180.v:4835$1418
+ attribute \src "ls180.v:4854.9-4854.37"
+ cell $eq $eq$ls180.v:4854$1425
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \uart_phy_tx_bitcount
connect \B 4'1000
- connect \Y $eq$ls180.v:4835$1418_Y
+ connect \Y $eq$ls180.v:4854$1425_Y
end
- attribute \src "ls180.v:4838.10-4838.38"
- cell $eq $eq$ls180.v:4838$1419
+ attribute \src "ls180.v:4857.10-4857.38"
+ cell $eq $eq$ls180.v:4857$1426
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \uart_phy_tx_bitcount
connect \B 4'1001
- connect \Y $eq$ls180.v:4838$1419_Y
+ connect \Y $eq$ls180.v:4857$1426_Y
end
- attribute \src "ls180.v:4864.9-4864.37"
- cell $eq $eq$ls180.v:4864$1425
+ attribute \src "ls180.v:4883.9-4883.37"
+ cell $eq $eq$ls180.v:4883$1432
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \uart_phy_rx_bitcount
connect \B 1'0
- connect \Y $eq$ls180.v:4864$1425_Y
+ connect \Y $eq$ls180.v:4883$1432_Y
end
- attribute \src "ls180.v:4869.10-4869.38"
- cell $eq $eq$ls180.v:4869$1426
+ attribute \src "ls180.v:4888.10-4888.38"
+ cell $eq $eq$ls180.v:4888$1433
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \uart_phy_rx_bitcount
connect \B 4'1001
- connect \Y $eq$ls180.v:4869$1426_Y
+ connect \Y $eq$ls180.v:4888$1433_Y
end
- attribute \src "ls180.v:5511.28-5511.31"
- cell $memrd $memrd$\mem$ls180.v:5511$1508
+ attribute \src "ls180.v:5530.28-5530.31"
+ cell $memrd $memrd$\mem$ls180.v:5530$1515
parameter \ABITS 6
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \memadr
connect \CLK 1'x
- connect \DATA $memrd$\mem$ls180.v:5511$1508_DATA
+ connect \DATA $memrd$\mem$ls180.v:5530$1515_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5539.20-5539.25"
- cell $memrd $memrd$\mem_1$ls180.v:5539$1558
+ attribute \src "ls180.v:5558.20-5558.25"
+ cell $memrd $memrd$\mem_1$ls180.v:5558$1565
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 64
connect \ADDR \memadr_1
connect \CLK 1'x
- connect \DATA $memrd$\mem_1$ls180.v:5539$1558_DATA
+ connect \DATA $memrd$\mem_1$ls180.v:5558$1565_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5550.12-5550.19"
- cell $memrd $memrd$\storage$ls180.v:5550$1566
+ attribute \src "ls180.v:5569.12-5569.19"
+ cell $memrd $memrd$\storage$ls180.v:5569$1573
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage$ls180.v:5550$1566_DATA
+ connect \DATA $memrd$\storage$ls180.v:5569$1573_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5557.63-5557.70"
- cell $memrd $memrd$\storage$ls180.v:5557$1568
+ attribute \src "ls180.v:5576.63-5576.70"
+ cell $memrd $memrd$\storage$ls180.v:5576$1575
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage$ls180.v:5557$1568_DATA
+ connect \DATA $memrd$\storage$ls180.v:5576$1575_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5564.14-5564.23"
- cell $memrd $memrd$\storage_1$ls180.v:5564$1576
+ attribute \src "ls180.v:5583.14-5583.23"
+ cell $memrd $memrd$\storage_1$ls180.v:5583$1583
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_1$ls180.v:5564$1576_DATA
+ connect \DATA $memrd$\storage_1$ls180.v:5583$1583_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5571.63-5571.72"
- cell $memrd $memrd$\storage_1$ls180.v:5571$1578
+ attribute \src "ls180.v:5590.63-5590.72"
+ cell $memrd $memrd$\storage_1$ls180.v:5590$1585
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_1$ls180.v:5571$1578_DATA
+ connect \DATA $memrd$\storage_1$ls180.v:5590$1585_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5578.14-5578.23"
- cell $memrd $memrd$\storage_2$ls180.v:5578$1586
+ attribute \src "ls180.v:5597.14-5597.23"
+ cell $memrd $memrd$\storage_2$ls180.v:5597$1593
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_2$ls180.v:5578$1586_DATA
+ connect \DATA $memrd$\storage_2$ls180.v:5597$1593_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5585.63-5585.72"
- cell $memrd $memrd$\storage_2$ls180.v:5585$1588
+ attribute \src "ls180.v:5604.63-5604.72"
+ cell $memrd $memrd$\storage_2$ls180.v:5604$1595
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_2$ls180.v:5585$1588_DATA
+ connect \DATA $memrd$\storage_2$ls180.v:5604$1595_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5592.14-5592.23"
- cell $memrd $memrd$\storage_3$ls180.v:5592$1596
+ attribute \src "ls180.v:5611.14-5611.23"
+ cell $memrd $memrd$\storage_3$ls180.v:5611$1603
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_3$ls180.v:5592$1596_DATA
+ connect \DATA $memrd$\storage_3$ls180.v:5611$1603_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5599.63-5599.72"
- cell $memrd $memrd$\storage_3$ls180.v:5599$1598
+ attribute \src "ls180.v:5618.63-5618.72"
+ cell $memrd $memrd$\storage_3$ls180.v:5618$1605
parameter \ABITS 3
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 25
connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_3$ls180.v:5599$1598_DATA
+ connect \DATA $memrd$\storage_3$ls180.v:5618$1605_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5607.14-5607.23"
- cell $memrd $memrd$\storage_4$ls180.v:5607$1606
+ attribute \src "ls180.v:5626.14-5626.23"
+ cell $memrd $memrd$\storage_4$ls180.v:5626$1613
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \tx_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_4$ls180.v:5607$1606_DATA
+ connect \DATA $memrd$\storage_4$ls180.v:5626$1613_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5612.15-5612.24"
- cell $memrd $memrd$\storage_4$ls180.v:5612$1608
+ attribute \src "ls180.v:5631.15-5631.24"
+ cell $memrd $memrd$\storage_4$ls180.v:5631$1615
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \tx_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_4$ls180.v:5612$1608_DATA
+ connect \DATA $memrd$\storage_4$ls180.v:5631$1615_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5624.14-5624.23"
- cell $memrd $memrd$\storage_5$ls180.v:5624$1616
+ attribute \src "ls180.v:5643.14-5643.23"
+ cell $memrd $memrd$\storage_5$ls180.v:5643$1623
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \rx_fifo_wrport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_5$ls180.v:5624$1616_DATA
+ connect \DATA $memrd$\storage_5$ls180.v:5643$1623_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:5629.15-5629.24"
- cell $memrd $memrd$\storage_5$ls180.v:5629$1618
+ attribute \src "ls180.v:5648.15-5648.24"
+ cell $memrd $memrd$\storage_5$ls180.v:5648$1625
parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \WIDTH 10
connect \ADDR \rx_fifo_rdport_adr
connect \CLK 1'x
- connect \DATA $memrd$\storage_5$ls180.v:5629$1618_DATA
+ connect \DATA $memrd$\storage_5$ls180.v:5648$1625_DATA
connect \EN 1'x
end
- attribute \src "ls180.v:1709.36-1709.61"
- cell $ne $ne$ls180.v:1709$82
+ attribute \src "ls180.v:1722.36-1722.61"
+ cell $ne $ne$ls180.v:1722$83
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_value
connect \B 1'0
- connect \Y $ne$ls180.v:1709$82_Y
+ connect \Y $ne$ls180.v:1722$83_Y
end
- attribute \src "ls180.v:1884.60-1884.89"
- cell $ne $ne$ls180.v:1884$121
+ attribute \src "ls180.v:1897.60-1897.89"
+ cell $ne $ne$ls180.v:1897$122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_count
connect \B 1'0
- connect \Y $ne$ls180.v:1884$121_Y
+ connect \Y $ne$ls180.v:1897$122_Y
end
- attribute \src "ls180.v:1945.8-1945.132"
- cell $ne $ne$ls180.v:1945$140
+ attribute \src "ls180.v:1958.8-1958.132"
+ cell $ne $ne$ls180.v:1958$141
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:1945$140_Y
+ connect \Y $ne$ls180.v:1958$141_Y
end
- attribute \src "ls180.v:1977.70-1977.123"
- cell $ne $ne$ls180.v:1977$147
+ attribute \src "ls180.v:1990.70-1990.123"
+ cell $ne $ne$ls180.v:1990$148
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:1977$147_Y
+ connect \Y $ne$ls180.v:1990$148_Y
end
- attribute \src "ls180.v:1978.70-1978.123"
- cell $ne $ne$ls180.v:1978$148
+ attribute \src "ls180.v:1991.70-1991.123"
+ cell $ne $ne$ls180.v:1991$149
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:1978$148_Y
+ connect \Y $ne$ls180.v:1991$149_Y
end
- attribute \src "ls180.v:2102.8-2102.132"
- cell $ne $ne$ls180.v:2102$170
+ attribute \src "ls180.v:2115.8-2115.132"
+ cell $ne $ne$ls180.v:2115$171
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:2102$170_Y
+ connect \Y $ne$ls180.v:2115$171_Y
end
- attribute \src "ls180.v:2134.70-2134.123"
- cell $ne $ne$ls180.v:2134$177
+ attribute \src "ls180.v:2147.70-2147.123"
+ cell $ne $ne$ls180.v:2147$178
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:2134$177_Y
+ connect \Y $ne$ls180.v:2147$178_Y
end
- attribute \src "ls180.v:2135.70-2135.123"
- cell $ne $ne$ls180.v:2135$178
+ attribute \src "ls180.v:2148.70-2148.123"
+ cell $ne $ne$ls180.v:2148$179
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:2135$178_Y
+ connect \Y $ne$ls180.v:2148$179_Y
end
- attribute \src "ls180.v:2259.8-2259.132"
- cell $ne $ne$ls180.v:2259$200
+ attribute \src "ls180.v:2272.8-2272.132"
+ cell $ne $ne$ls180.v:2272$201
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:2259$200_Y
+ connect \Y $ne$ls180.v:2272$201_Y
end
- attribute \src "ls180.v:2291.70-2291.123"
- cell $ne $ne$ls180.v:2291$207
+ attribute \src "ls180.v:2304.70-2304.123"
+ cell $ne $ne$ls180.v:2304$208
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:2291$207_Y
+ connect \Y $ne$ls180.v:2304$208_Y
end
- attribute \src "ls180.v:2292.70-2292.123"
- cell $ne $ne$ls180.v:2292$208
+ attribute \src "ls180.v:2305.70-2305.123"
+ cell $ne $ne$ls180.v:2305$209
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:2292$208_Y
+ connect \Y $ne$ls180.v:2305$209_Y
end
- attribute \src "ls180.v:2416.8-2416.132"
- cell $ne $ne$ls180.v:2416$230
+ attribute \src "ls180.v:2429.8-2429.132"
+ cell $ne $ne$ls180.v:2429$231
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9]
connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- connect \Y $ne$ls180.v:2416$230_Y
+ connect \Y $ne$ls180.v:2429$231_Y
end
- attribute \src "ls180.v:2448.70-2448.123"
- cell $ne $ne$ls180.v:2448$237
+ attribute \src "ls180.v:2461.70-2461.123"
+ cell $ne $ne$ls180.v:2461$238
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 4'1000
- connect \Y $ne$ls180.v:2448$237_Y
+ connect \Y $ne$ls180.v:2461$238_Y
end
- attribute \src "ls180.v:2449.70-2449.123"
- cell $ne $ne$ls180.v:2449$238
+ attribute \src "ls180.v:2462.70-2462.123"
+ cell $ne $ne$ls180.v:2462$239
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'0
- connect \Y $ne$ls180.v:2449$238_Y
+ connect \Y $ne$ls180.v:2462$239_Y
end
- attribute \src "ls180.v:2941.37-2941.60"
- cell $ne $ne$ls180.v:2941$636
+ attribute \src "ls180.v:2954.37-2954.60"
+ cell $ne $ne$ls180.v:2954$637
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \tx_fifo_level0
connect \B 5'10000
- connect \Y $ne$ls180.v:2941$636_Y
+ connect \Y $ne$ls180.v:2954$637_Y
end
- attribute \src "ls180.v:2942.37-2942.59"
- cell $ne $ne$ls180.v:2942$637
+ attribute \src "ls180.v:2955.37-2955.59"
+ cell $ne $ne$ls180.v:2955$638
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \tx_fifo_level0
connect \B 1'0
- connect \Y $ne$ls180.v:2942$637_Y
+ connect \Y $ne$ls180.v:2955$638_Y
end
- attribute \src "ls180.v:2971.37-2971.60"
- cell $ne $ne$ls180.v:2971$647
+ attribute \src "ls180.v:2984.37-2984.60"
+ cell $ne $ne$ls180.v:2984$648
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rx_fifo_level0
connect \B 5'10000
- connect \Y $ne$ls180.v:2971$647_Y
+ connect \Y $ne$ls180.v:2984$648_Y
end
- attribute \src "ls180.v:2972.37-2972.59"
- cell $ne $ne$ls180.v:2972$648
+ attribute \src "ls180.v:2985.37-2985.59"
+ cell $ne $ne$ls180.v:2985$649
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rx_fifo_level0
connect \B 1'0
- connect \Y $ne$ls180.v:2972$648_Y
+ connect \Y $ne$ls180.v:2985$649_Y
end
- attribute \src "ls180.v:3067.99-3067.143"
- cell $ne $ne$ls180.v:3067$655
+ attribute \src "ls180.v:3080.99-3080.143"
+ cell $ne $ne$ls180.v:3080$656
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresocsim_wishbone_sel
connect \B 1'0
- connect \Y $ne$ls180.v:3067$655_Y
+ connect \Y $ne$ls180.v:3080$656_Y
end
- attribute \src "ls180.v:4351.7-4351.47"
- cell $ne $ne$ls180.v:4351$1280
+ attribute \src "ls180.v:4370.7-4370.47"
+ cell $ne $ne$ls180.v:4370$1287
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_bus_errors
connect \B 32'11111111111111111111111111111111
- connect \Y $ne$ls180.v:4351$1280_Y
+ connect \Y $ne$ls180.v:4370$1287_Y
end
- attribute \src "ls180.v:4405.9-4405.38"
- cell $ne $ne$ls180.v:4405$1297
+ attribute \src "ls180.v:4424.9-4424.38"
+ cell $ne $ne$ls180.v:4424$1304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_count
connect \B 1'0
- connect \Y $ne$ls180.v:4405$1297_Y
+ connect \Y $ne$ls180.v:4424$1304_Y
end
- attribute \src "ls180.v:4441.8-4441.39"
- cell $ne $ne$ls180.v:4441$1304
+ attribute \src "ls180.v:4460.8-4460.39"
+ cell $ne $ne$ls180.v:4460$1311
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_counter
connect \B 1'0
- connect \Y $ne$ls180.v:4441$1304_Y
+ connect \Y $ne$ls180.v:4460$1311_Y
end
- attribute \src "ls180.v:1513.28-1513.63"
- cell $not $not$ls180.v:1513$24
+ attribute \src "ls180.v:1526.28-1526.63"
+ cell $not $not$ls180.v:1526$25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \interface0_converted_interface_cyc
- connect \Y $not$ls180.v:1513$24_Y
+ connect \Y $not$ls180.v:1526$25_Y
end
- attribute \src "ls180.v:1552.43-1552.59"
- cell $not $not$ls180.v:1552$29
+ attribute \src "ls180.v:1565.43-1565.59"
+ cell $not $not$ls180.v:1565$30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \converter0_skip
- connect \Y $not$ls180.v:1552$29_Y
+ connect \Y $not$ls180.v:1565$30_Y
end
- attribute \src "ls180.v:1553.43-1553.59"
- cell $not $not$ls180.v:1553$30
+ attribute \src "ls180.v:1566.43-1566.59"
+ cell $not $not$ls180.v:1566$31
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \converter0_skip
- connect \Y $not$ls180.v:1553$30_Y
+ connect \Y $not$ls180.v:1566$31_Y
end
- attribute \src "ls180.v:1573.28-1573.63"
- cell $not $not$ls180.v:1573$35
+ attribute \src "ls180.v:1586.28-1586.63"
+ cell $not $not$ls180.v:1586$36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \interface1_converted_interface_cyc
- connect \Y $not$ls180.v:1573$35_Y
+ connect \Y $not$ls180.v:1586$36_Y
end
- attribute \src "ls180.v:1612.43-1612.59"
- cell $not $not$ls180.v:1612$40
+ attribute \src "ls180.v:1625.43-1625.59"
+ cell $not $not$ls180.v:1625$41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \converter1_skip
- connect \Y $not$ls180.v:1612$40_Y
+ connect \Y $not$ls180.v:1625$41_Y
end
- attribute \src "ls180.v:1613.43-1613.59"
- cell $not $not$ls180.v:1613$41
+ attribute \src "ls180.v:1626.43-1626.59"
+ cell $not $not$ls180.v:1626$42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \converter1_skip
- connect \Y $not$ls180.v:1613$41_Y
+ connect \Y $not$ls180.v:1626$42_Y
end
- attribute \src "ls180.v:1633.31-1633.69"
- cell $not $not$ls180.v:1633$46
+ attribute \src "ls180.v:1646.31-1646.69"
+ cell $not $not$ls180.v:1646$47
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \socbushandler_converted_interface_cyc
- connect \Y $not$ls180.v:1633$46_Y
+ connect \Y $not$ls180.v:1646$47_Y
end
- attribute \src "ls180.v:1672.22-1672.41"
- cell $not $not$ls180.v:1672$51
+ attribute \src "ls180.v:1685.22-1685.41"
+ cell $not $not$ls180.v:1685$52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \socbushandler_skip
- connect \Y $not$ls180.v:1672$51_Y
+ connect \Y $not$ls180.v:1685$52_Y
end
- attribute \src "ls180.v:1673.22-1673.41"
- cell $not $not$ls180.v:1673$52
+ attribute \src "ls180.v:1686.22-1686.41"
+ cell $not $not$ls180.v:1686$53
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \socbushandler_skip
- connect \Y $not$ls180.v:1673$52_Y
+ connect \Y $not$ls180.v:1686$53_Y
end
- attribute \src "ls180.v:1833.29-1833.54"
- cell $not $not$ls180.v:1833$113
+ attribute \src "ls180.v:1846.29-1846.54"
+ cell $not $not$ls180.v:1846$114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_command_storage [0]
- connect \Y $not$ls180.v:1833$113_Y
+ connect \Y $not$ls180.v:1846$114_Y
end
- attribute \src "ls180.v:1834.26-1834.51"
- cell $not $not$ls180.v:1834$114
+ attribute \src "ls180.v:1847.26-1847.51"
+ cell $not $not$ls180.v:1847$115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_command_storage [1]
- connect \Y $not$ls180.v:1834$114_Y
+ connect \Y $not$ls180.v:1847$115_Y
end
- attribute \src "ls180.v:1835.27-1835.52"
- cell $not $not$ls180.v:1835$115
+ attribute \src "ls180.v:1848.27-1848.52"
+ cell $not $not$ls180.v:1848$116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_command_storage [2]
- connect \Y $not$ls180.v:1835$115_Y
+ connect \Y $not$ls180.v:1848$116_Y
end
- attribute \src "ls180.v:1836.27-1836.52"
- cell $not $not$ls180.v:1836$116
+ attribute \src "ls180.v:1849.27-1849.52"
+ cell $not $not$ls180.v:1849$117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_command_storage [3]
- connect \Y $not$ls180.v:1836$116_Y
+ connect \Y $not$ls180.v:1849$117_Y
end
- attribute \src "ls180.v:1878.28-1878.46"
- cell $not $not$ls180.v:1878$119
+ attribute \src "ls180.v:1891.28-1891.46"
+ cell $not $not$ls180.v:1891$120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_timer_done0
- connect \Y $not$ls180.v:1878$119_Y
+ connect \Y $not$ls180.v:1891$120_Y
end
- attribute \src "ls180.v:1979.53-1979.96"
- cell $not $not$ls180.v:1979$149
+ attribute \src "ls180.v:1992.53-1992.96"
+ cell $not $not$ls180.v:1992$150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $not$ls180.v:1979$149_Y
+ connect \Y $not$ls180.v:1992$150_Y
end
- attribute \src "ls180.v:2033.9-2033.40"
- cell $not $not$ls180.v:2033$154
+ attribute \src "ls180.v:2046.9-2046.40"
+ cell $not $not$ls180.v:2046$155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_refresh_req
- connect \Y $not$ls180.v:2033$154_Y
+ connect \Y $not$ls180.v:2046$155_Y
end
- attribute \src "ls180.v:2136.53-2136.96"
- cell $not $not$ls180.v:2136$179
+ attribute \src "ls180.v:2149.53-2149.96"
+ cell $not $not$ls180.v:2149$180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $not$ls180.v:2136$179_Y
+ connect \Y $not$ls180.v:2149$180_Y
end
- attribute \src "ls180.v:2190.9-2190.40"
- cell $not $not$ls180.v:2190$184
+ attribute \src "ls180.v:2203.9-2203.40"
+ cell $not $not$ls180.v:2203$185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_refresh_req
- connect \Y $not$ls180.v:2190$184_Y
+ connect \Y $not$ls180.v:2203$185_Y
end
- attribute \src "ls180.v:2293.53-2293.96"
- cell $not $not$ls180.v:2293$209
+ attribute \src "ls180.v:2306.53-2306.96"
+ cell $not $not$ls180.v:2306$210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $not$ls180.v:2293$209_Y
+ connect \Y $not$ls180.v:2306$210_Y
end
- attribute \src "ls180.v:2347.9-2347.40"
- cell $not $not$ls180.v:2347$214
+ attribute \src "ls180.v:2360.9-2360.40"
+ cell $not $not$ls180.v:2360$215
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_refresh_req
- connect \Y $not$ls180.v:2347$214_Y
+ connect \Y $not$ls180.v:2360$215_Y
end
- attribute \src "ls180.v:2450.53-2450.96"
- cell $not $not$ls180.v:2450$239
+ attribute \src "ls180.v:2463.53-2463.96"
+ cell $not $not$ls180.v:2463$240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $not$ls180.v:2450$239_Y
+ connect \Y $not$ls180.v:2463$240_Y
end
- attribute \src "ls180.v:2504.9-2504.40"
- cell $not $not$ls180.v:2504$244
+ attribute \src "ls180.v:2517.9-2517.40"
+ cell $not $not$ls180.v:2517$245
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_refresh_req
- connect \Y $not$ls180.v:2504$244_Y
+ connect \Y $not$ls180.v:2517$245_Y
end
- attribute \src "ls180.v:2546.129-2546.162"
- cell $not $not$ls180.v:2546$247
+ attribute \src "ls180.v:2559.129-2559.162"
+ cell $not $not$ls180.v:2559$248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:2546$247_Y
+ connect \Y $not$ls180.v:2559$248_Y
end
- attribute \src "ls180.v:2546.168-2546.200"
- cell $not $not$ls180.v:2546$249
+ attribute \src "ls180.v:2559.168-2559.200"
+ cell $not $not$ls180.v:2559$250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:2546$249_Y
+ connect \Y $not$ls180.v:2559$250_Y
end
- attribute \src "ls180.v:2547.129-2547.162"
- cell $not $not$ls180.v:2547$253
+ attribute \src "ls180.v:2560.129-2560.162"
+ cell $not $not$ls180.v:2560$254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:2547$253_Y
+ connect \Y $not$ls180.v:2560$254_Y
end
- attribute \src "ls180.v:2547.168-2547.200"
- cell $not $not$ls180.v:2547$255
+ attribute \src "ls180.v:2560.168-2560.200"
+ cell $not $not$ls180.v:2560$256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:2547$255_Y
+ connect \Y $not$ls180.v:2560$256_Y
end
- attribute \src "ls180.v:2563.38-2563.63"
- cell $not $not$ls180.v:2563$283
+ attribute \src "ls180.v:2576.38-2576.63"
+ cell $not $not$ls180.v:2576$284
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \sdram_interface_wdata_we
- connect \Y $not$ls180.v:2563$283_Y
+ connect \Y $not$ls180.v:2576$284_Y
end
- attribute \src "ls180.v:2566.180-2566.215"
- cell $not $not$ls180.v:2566$286
+ attribute \src "ls180.v:2579.180-2579.215"
+ cell $not $not$ls180.v:2579$287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_cas
- connect \Y $not$ls180.v:2566$286_Y
+ connect \Y $not$ls180.v:2579$287_Y
end
- attribute \src "ls180.v:2566.221-2566.255"
- cell $not $not$ls180.v:2566$288
+ attribute \src "ls180.v:2579.221-2579.255"
+ cell $not $not$ls180.v:2579$289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_we
- connect \Y $not$ls180.v:2566$288_Y
+ connect \Y $not$ls180.v:2579$289_Y
end
- attribute \src "ls180.v:2566.139-2566.257"
- cell $not $not$ls180.v:2566$290
+ attribute \src "ls180.v:2579.139-2579.257"
+ cell $not $not$ls180.v:2579$291
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2566$289_Y
- connect \Y $not$ls180.v:2566$290_Y
+ connect \A $and$ls180.v:2579$290_Y
+ connect \Y $not$ls180.v:2579$291_Y
end
- attribute \src "ls180.v:2567.180-2567.215"
- cell $not $not$ls180.v:2567$299
+ attribute \src "ls180.v:2580.180-2580.215"
+ cell $not $not$ls180.v:2580$300
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_cas
- connect \Y $not$ls180.v:2567$299_Y
+ connect \Y $not$ls180.v:2580$300_Y
end
- attribute \src "ls180.v:2567.221-2567.255"
- cell $not $not$ls180.v:2567$301
+ attribute \src "ls180.v:2580.221-2580.255"
+ cell $not $not$ls180.v:2580$302
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_we
- connect \Y $not$ls180.v:2567$301_Y
+ connect \Y $not$ls180.v:2580$302_Y
end
- attribute \src "ls180.v:2567.139-2567.257"
- cell $not $not$ls180.v:2567$303
+ attribute \src "ls180.v:2580.139-2580.257"
+ cell $not $not$ls180.v:2580$304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2567$302_Y
- connect \Y $not$ls180.v:2567$303_Y
+ connect \A $and$ls180.v:2580$303_Y
+ connect \Y $not$ls180.v:2580$304_Y
end
- attribute \src "ls180.v:2568.180-2568.215"
- cell $not $not$ls180.v:2568$312
+ attribute \src "ls180.v:2581.180-2581.215"
+ cell $not $not$ls180.v:2581$313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_cas
- connect \Y $not$ls180.v:2568$312_Y
+ connect \Y $not$ls180.v:2581$313_Y
end
- attribute \src "ls180.v:2568.221-2568.255"
- cell $not $not$ls180.v:2568$314
+ attribute \src "ls180.v:2581.221-2581.255"
+ cell $not $not$ls180.v:2581$315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_we
- connect \Y $not$ls180.v:2568$314_Y
+ connect \Y $not$ls180.v:2581$315_Y
end
- attribute \src "ls180.v:2568.139-2568.257"
- cell $not $not$ls180.v:2568$316
+ attribute \src "ls180.v:2581.139-2581.257"
+ cell $not $not$ls180.v:2581$317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2568$315_Y
- connect \Y $not$ls180.v:2568$316_Y
+ connect \A $and$ls180.v:2581$316_Y
+ connect \Y $not$ls180.v:2581$317_Y
end
- attribute \src "ls180.v:2569.180-2569.215"
- cell $not $not$ls180.v:2569$325
+ attribute \src "ls180.v:2582.180-2582.215"
+ cell $not $not$ls180.v:2582$326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_cas
- connect \Y $not$ls180.v:2569$325_Y
+ connect \Y $not$ls180.v:2582$326_Y
end
- attribute \src "ls180.v:2569.221-2569.255"
- cell $not $not$ls180.v:2569$327
+ attribute \src "ls180.v:2582.221-2582.255"
+ cell $not $not$ls180.v:2582$328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_we
- connect \Y $not$ls180.v:2569$327_Y
+ connect \Y $not$ls180.v:2582$328_Y
end
- attribute \src "ls180.v:2569.139-2569.257"
- cell $not $not$ls180.v:2569$329
+ attribute \src "ls180.v:2582.139-2582.257"
+ cell $not $not$ls180.v:2582$330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2569$328_Y
- connect \Y $not$ls180.v:2569$329_Y
+ connect \A $and$ls180.v:2582$329_Y
+ connect \Y $not$ls180.v:2582$330_Y
end
- attribute \src "ls180.v:2596.61-2596.88"
- cell $not $not$ls180.v:2596$340
+ attribute \src "ls180.v:2609.61-2609.88"
+ cell $not $not$ls180.v:2609$341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_cmd_valid
- connect \Y $not$ls180.v:2596$340_Y
+ connect \Y $not$ls180.v:2609$341_Y
end
- attribute \src "ls180.v:2599.180-2599.215"
- cell $not $not$ls180.v:2599$344
+ attribute \src "ls180.v:2612.180-2612.215"
+ cell $not $not$ls180.v:2612$345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_cas
- connect \Y $not$ls180.v:2599$344_Y
+ connect \Y $not$ls180.v:2612$345_Y
end
- attribute \src "ls180.v:2599.221-2599.255"
- cell $not $not$ls180.v:2599$346
+ attribute \src "ls180.v:2612.221-2612.255"
+ cell $not $not$ls180.v:2612$347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_payload_we
- connect \Y $not$ls180.v:2599$346_Y
+ connect \Y $not$ls180.v:2612$347_Y
end
- attribute \src "ls180.v:2599.139-2599.257"
- cell $not $not$ls180.v:2599$348
+ attribute \src "ls180.v:2612.139-2612.257"
+ cell $not $not$ls180.v:2612$349
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2599$347_Y
- connect \Y $not$ls180.v:2599$348_Y
+ connect \A $and$ls180.v:2612$348_Y
+ connect \Y $not$ls180.v:2612$349_Y
end
- attribute \src "ls180.v:2600.180-2600.215"
- cell $not $not$ls180.v:2600$357
+ attribute \src "ls180.v:2613.180-2613.215"
+ cell $not $not$ls180.v:2613$358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_cas
- connect \Y $not$ls180.v:2600$357_Y
+ connect \Y $not$ls180.v:2613$358_Y
end
- attribute \src "ls180.v:2600.221-2600.255"
- cell $not $not$ls180.v:2600$359
+ attribute \src "ls180.v:2613.221-2613.255"
+ cell $not $not$ls180.v:2613$360
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_payload_we
- connect \Y $not$ls180.v:2600$359_Y
+ connect \Y $not$ls180.v:2613$360_Y
end
- attribute \src "ls180.v:2600.139-2600.257"
- cell $not $not$ls180.v:2600$361
+ attribute \src "ls180.v:2613.139-2613.257"
+ cell $not $not$ls180.v:2613$362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2600$360_Y
- connect \Y $not$ls180.v:2600$361_Y
+ connect \A $and$ls180.v:2613$361_Y
+ connect \Y $not$ls180.v:2613$362_Y
end
- attribute \src "ls180.v:2601.180-2601.215"
- cell $not $not$ls180.v:2601$370
+ attribute \src "ls180.v:2614.180-2614.215"
+ cell $not $not$ls180.v:2614$371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_cas
- connect \Y $not$ls180.v:2601$370_Y
+ connect \Y $not$ls180.v:2614$371_Y
end
- attribute \src "ls180.v:2601.221-2601.255"
- cell $not $not$ls180.v:2601$372
+ attribute \src "ls180.v:2614.221-2614.255"
+ cell $not $not$ls180.v:2614$373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_payload_we
- connect \Y $not$ls180.v:2601$372_Y
+ connect \Y $not$ls180.v:2614$373_Y
end
- attribute \src "ls180.v:2601.139-2601.257"
- cell $not $not$ls180.v:2601$374
+ attribute \src "ls180.v:2614.139-2614.257"
+ cell $not $not$ls180.v:2614$375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2601$373_Y
- connect \Y $not$ls180.v:2601$374_Y
+ connect \A $and$ls180.v:2614$374_Y
+ connect \Y $not$ls180.v:2614$375_Y
end
- attribute \src "ls180.v:2602.180-2602.215"
- cell $not $not$ls180.v:2602$383
+ attribute \src "ls180.v:2615.180-2615.215"
+ cell $not $not$ls180.v:2615$384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_cas
- connect \Y $not$ls180.v:2602$383_Y
+ connect \Y $not$ls180.v:2615$384_Y
end
- attribute \src "ls180.v:2602.221-2602.255"
- cell $not $not$ls180.v:2602$385
+ attribute \src "ls180.v:2615.221-2615.255"
+ cell $not $not$ls180.v:2615$386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_payload_we
- connect \Y $not$ls180.v:2602$385_Y
+ connect \Y $not$ls180.v:2615$386_Y
end
- attribute \src "ls180.v:2602.139-2602.257"
- cell $not $not$ls180.v:2602$387
+ attribute \src "ls180.v:2615.139-2615.257"
+ cell $not $not$ls180.v:2615$388
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2602$386_Y
- connect \Y $not$ls180.v:2602$387_Y
+ connect \A $and$ls180.v:2615$387_Y
+ connect \Y $not$ls180.v:2615$388_Y
end
- attribute \src "ls180.v:2665.61-2665.88"
- cell $not $not$ls180.v:2665$426
+ attribute \src "ls180.v:2678.61-2678.88"
+ cell $not $not$ls180.v:2678$427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_valid
- connect \Y $not$ls180.v:2665$426_Y
+ connect \Y $not$ls180.v:2678$427_Y
end
- attribute \src "ls180.v:2686.97-2686.130"
- cell $not $not$ls180.v:2686$429
+ attribute \src "ls180.v:2699.97-2699.130"
+ cell $not $not$ls180.v:2699$430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:2686$429_Y
+ connect \Y $not$ls180.v:2699$430_Y
end
- attribute \src "ls180.v:2686.136-2686.168"
- cell $not $not$ls180.v:2686$431
+ attribute \src "ls180.v:2699.136-2699.168"
+ cell $not $not$ls180.v:2699$432
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:2686$431_Y
+ connect \Y $not$ls180.v:2699$432_Y
end
- attribute \src "ls180.v:2686.58-2686.170"
- cell $not $not$ls180.v:2686$433
+ attribute \src "ls180.v:2699.58-2699.170"
+ cell $not $not$ls180.v:2699$434
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2686$432_Y
- connect \Y $not$ls180.v:2686$433_Y
+ connect \A $and$ls180.v:2699$433_Y
+ connect \Y $not$ls180.v:2699$434_Y
end
- attribute \src "ls180.v:2694.11-2694.33"
- cell $not $not$ls180.v:2694$436
+ attribute \src "ls180.v:2707.11-2707.33"
+ cell $not $not$ls180.v:2707$437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_write_available
- connect \Y $not$ls180.v:2694$436_Y
+ connect \Y $not$ls180.v:2707$437_Y
end
- attribute \src "ls180.v:2724.97-2724.130"
- cell $not $not$ls180.v:2724$438
+ attribute \src "ls180.v:2737.97-2737.130"
+ cell $not $not$ls180.v:2737$439
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_cas
- connect \Y $not$ls180.v:2724$438_Y
+ connect \Y $not$ls180.v:2737$439_Y
end
- attribute \src "ls180.v:2724.136-2724.168"
- cell $not $not$ls180.v:2724$440
+ attribute \src "ls180.v:2737.136-2737.168"
+ cell $not $not$ls180.v:2737$441
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_we
- connect \Y $not$ls180.v:2724$440_Y
+ connect \Y $not$ls180.v:2737$441_Y
end
- attribute \src "ls180.v:2724.58-2724.170"
- cell $not $not$ls180.v:2724$442
+ attribute \src "ls180.v:2737.58-2737.170"
+ cell $not $not$ls180.v:2737$443
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2724$441_Y
- connect \Y $not$ls180.v:2724$442_Y
+ connect \A $and$ls180.v:2737$442_Y
+ connect \Y $not$ls180.v:2737$443_Y
end
- attribute \src "ls180.v:2732.11-2732.32"
- cell $not $not$ls180.v:2732$445
+ attribute \src "ls180.v:2745.11-2745.32"
+ cell $not $not$ls180.v:2745$446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_read_available
- connect \Y $not$ls180.v:2732$445_Y
+ connect \Y $not$ls180.v:2745$446_Y
end
- attribute \src "ls180.v:2742.87-2742.336"
- cell $not $not$ls180.v:2742$457
+ attribute \src "ls180.v:2755.87-2755.336"
+ cell $not $not$ls180.v:2755$458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2742$456_Y
- connect \Y $not$ls180.v:2742$457_Y
+ connect \A $or$ls180.v:2755$457_Y
+ connect \Y $not$ls180.v:2755$458_Y
end
- attribute \src "ls180.v:2743.40-2743.68"
- cell $not $not$ls180.v:2743$460
+ attribute \src "ls180.v:2756.40-2756.68"
+ cell $not $not$ls180.v:2756$461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_valid
- connect \Y $not$ls180.v:2743$460_Y
+ connect \Y $not$ls180.v:2756$461_Y
end
- attribute \src "ls180.v:2743.73-2743.100"
- cell $not $not$ls180.v:2743$461
+ attribute \src "ls180.v:2756.73-2756.100"
+ cell $not $not$ls180.v:2756$462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank0_lock
- connect \Y $not$ls180.v:2743$461_Y
+ connect \Y $not$ls180.v:2756$462_Y
end
- attribute \src "ls180.v:2747.87-2747.336"
- cell $not $not$ls180.v:2747$473
+ attribute \src "ls180.v:2760.87-2760.336"
+ cell $not $not$ls180.v:2760$474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2747$472_Y
- connect \Y $not$ls180.v:2747$473_Y
+ connect \A $or$ls180.v:2760$473_Y
+ connect \Y $not$ls180.v:2760$474_Y
end
- attribute \src "ls180.v:2748.40-2748.68"
- cell $not $not$ls180.v:2748$476
+ attribute \src "ls180.v:2761.40-2761.68"
+ cell $not $not$ls180.v:2761$477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_valid
- connect \Y $not$ls180.v:2748$476_Y
+ connect \Y $not$ls180.v:2761$477_Y
end
- attribute \src "ls180.v:2748.73-2748.100"
- cell $not $not$ls180.v:2748$477
+ attribute \src "ls180.v:2761.73-2761.100"
+ cell $not $not$ls180.v:2761$478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank1_lock
- connect \Y $not$ls180.v:2748$477_Y
+ connect \Y $not$ls180.v:2761$478_Y
end
- attribute \src "ls180.v:2752.87-2752.336"
- cell $not $not$ls180.v:2752$489
+ attribute \src "ls180.v:2765.87-2765.336"
+ cell $not $not$ls180.v:2765$490
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2752$488_Y
- connect \Y $not$ls180.v:2752$489_Y
+ connect \A $or$ls180.v:2765$489_Y
+ connect \Y $not$ls180.v:2765$490_Y
end
- attribute \src "ls180.v:2753.40-2753.68"
- cell $not $not$ls180.v:2753$492
+ attribute \src "ls180.v:2766.40-2766.68"
+ cell $not $not$ls180.v:2766$493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_valid
- connect \Y $not$ls180.v:2753$492_Y
+ connect \Y $not$ls180.v:2766$493_Y
end
- attribute \src "ls180.v:2753.73-2753.100"
- cell $not $not$ls180.v:2753$493
+ attribute \src "ls180.v:2766.73-2766.100"
+ cell $not $not$ls180.v:2766$494
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank2_lock
- connect \Y $not$ls180.v:2753$493_Y
+ connect \Y $not$ls180.v:2766$494_Y
end
- attribute \src "ls180.v:2757.87-2757.336"
- cell $not $not$ls180.v:2757$505
+ attribute \src "ls180.v:2770.87-2770.336"
+ cell $not $not$ls180.v:2770$506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2757$504_Y
- connect \Y $not$ls180.v:2757$505_Y
+ connect \A $or$ls180.v:2770$505_Y
+ connect \Y $not$ls180.v:2770$506_Y
end
- attribute \src "ls180.v:2758.40-2758.68"
- cell $not $not$ls180.v:2758$508
+ attribute \src "ls180.v:2771.40-2771.68"
+ cell $not $not$ls180.v:2771$509
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_valid
- connect \Y $not$ls180.v:2758$508_Y
+ connect \Y $not$ls180.v:2771$509_Y
end
- attribute \src "ls180.v:2758.73-2758.100"
- cell $not $not$ls180.v:2758$509
+ attribute \src "ls180.v:2771.73-2771.100"
+ cell $not $not$ls180.v:2771$510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_interface_bank3_lock
- connect \Y $not$ls180.v:2758$509_Y
+ connect \Y $not$ls180.v:2771$510_Y
end
- attribute \src "ls180.v:2762.123-2762.372"
- cell $not $not$ls180.v:2762$522
+ attribute \src "ls180.v:2775.123-2775.372"
+ cell $not $not$ls180.v:2775$523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$521_Y
- connect \Y $not$ls180.v:2762$522_Y
+ connect \A $or$ls180.v:2775$522_Y
+ connect \Y $not$ls180.v:2775$523_Y
end
- attribute \src "ls180.v:2762.497-2762.746"
- cell $not $not$ls180.v:2762$538
+ attribute \src "ls180.v:2775.497-2775.746"
+ cell $not $not$ls180.v:2775$539
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$537_Y
- connect \Y $not$ls180.v:2762$538_Y
+ connect \A $or$ls180.v:2775$538_Y
+ connect \Y $not$ls180.v:2775$539_Y
end
- attribute \src "ls180.v:2762.871-2762.1120"
- cell $not $not$ls180.v:2762$554
+ attribute \src "ls180.v:2775.871-2775.1120"
+ cell $not $not$ls180.v:2775$555
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$553_Y
- connect \Y $not$ls180.v:2762$554_Y
+ connect \A $or$ls180.v:2775$554_Y
+ connect \Y $not$ls180.v:2775$555_Y
end
- attribute \src "ls180.v:2762.1245-2762.1494"
- cell $not $not$ls180.v:2762$570
+ attribute \src "ls180.v:2775.1245-2775.1494"
+ cell $not $not$ls180.v:2775$571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$569_Y
- connect \Y $not$ls180.v:2762$570_Y
+ connect \A $or$ls180.v:2775$570_Y
+ connect \Y $not$ls180.v:2775$571_Y
end
- attribute \src "ls180.v:2784.27-2784.40"
- cell $not $not$ls180.v:2784$576
+ attribute \src "ls180.v:2797.27-2797.40"
+ cell $not $not$ls180.v:2797$577
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wb_sdram_cyc
- connect \Y $not$ls180.v:2784$576_Y
+ connect \Y $not$ls180.v:2797$577_Y
end
- attribute \src "ls180.v:2823.25-2823.40"
- cell $not $not$ls180.v:2823$581
+ attribute \src "ls180.v:2836.25-2836.40"
+ cell $not $not$ls180.v:2836$582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \converter_skip
- connect \Y $not$ls180.v:2823$581_Y
+ connect \Y $not$ls180.v:2836$582_Y
end
- attribute \src "ls180.v:2824.25-2824.40"
- cell $not $not$ls180.v:2824$582
+ attribute \src "ls180.v:2837.25-2837.40"
+ cell $not $not$ls180.v:2837$583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \converter_skip
- connect \Y $not$ls180.v:2824$582_Y
+ connect \Y $not$ls180.v:2837$583_Y
end
- attribute \src "ls180.v:2849.22-2849.38"
- cell $not $not$ls180.v:2849$588
+ attribute \src "ls180.v:2862.22-2862.38"
+ cell $not $not$ls180.v:2862$589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \litedram_wb_cyc
- connect \Y $not$ls180.v:2849$588_Y
+ connect \Y $not$ls180.v:2862$589_Y
end
- attribute \src "ls180.v:2850.25-2850.40"
- cell $not $not$ls180.v:2850$589
+ attribute \src "ls180.v:2863.25-2863.40"
+ cell $not $not$ls180.v:2863$590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \litedram_wb_we
- connect \Y $not$ls180.v:2850$589_Y
+ connect \Y $not$ls180.v:2863$590_Y
end
- attribute \src "ls180.v:2851.65-2851.78"
- cell $not $not$ls180.v:2851$591
+ attribute \src "ls180.v:2864.65-2864.78"
+ cell $not $not$ls180.v:2864$592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cmd_consumed
- connect \Y $not$ls180.v:2851$591_Y
+ connect \Y $not$ls180.v:2864$592_Y
end
- attribute \src "ls180.v:2852.87-2852.102"
- cell $not $not$ls180.v:2852$595
+ attribute \src "ls180.v:2865.87-2865.102"
+ cell $not $not$ls180.v:2865$596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wdata_consumed
- connect \Y $not$ls180.v:2852$595_Y
+ connect \Y $not$ls180.v:2865$596_Y
end
- attribute \src "ls180.v:2853.63-2853.83"
- cell $not $not$ls180.v:2853$598
+ attribute \src "ls180.v:2866.63-2866.83"
+ cell $not $not$ls180.v:2866$599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \port_cmd_payload_we
- connect \Y $not$ls180.v:2853$598_Y
+ connect \Y $not$ls180.v:2866$599_Y
end
- attribute \src "ls180.v:2854.71-2854.86"
- cell $not $not$ls180.v:2854$601
+ attribute \src "ls180.v:2867.71-2867.86"
+ cell $not $not$ls180.v:2867$602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \litedram_wb_we
- connect \Y $not$ls180.v:2854$601_Y
+ connect \Y $not$ls180.v:2867$602_Y
end
- attribute \src "ls180.v:2870.25-2870.44"
- cell $not $not$ls180.v:2870$610
+ attribute \src "ls180.v:2883.25-2883.44"
+ cell $not $not$ls180.v:2883$611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_sink_ready
- connect \Y $not$ls180.v:2870$610_Y
+ connect \Y $not$ls180.v:2883$611_Y
end
- attribute \src "ls180.v:2871.26-2871.47"
- cell $not $not$ls180.v:2871$611
+ attribute \src "ls180.v:2884.26-2884.47"
+ cell $not $not$ls180.v:2884$612
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_source_valid
- connect \Y $not$ls180.v:2871$611_Y
+ connect \Y $not$ls180.v:2884$612_Y
end
- attribute \src "ls180.v:2877.22-2877.41"
- cell $not $not$ls180.v:2877$612
+ attribute \src "ls180.v:2890.22-2890.41"
+ cell $not $not$ls180.v:2890$613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_sink_ready
- connect \Y $not$ls180.v:2877$612_Y
+ connect \Y $not$ls180.v:2890$613_Y
end
- attribute \src "ls180.v:2883.26-2883.47"
- cell $not $not$ls180.v:2883$613
+ attribute \src "ls180.v:2896.26-2896.47"
+ cell $not $not$ls180.v:2896$614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_source_valid
- connect \Y $not$ls180.v:2883$613_Y
+ connect \Y $not$ls180.v:2896$614_Y
end
- attribute \src "ls180.v:2884.25-2884.44"
- cell $not $not$ls180.v:2884$614
+ attribute \src "ls180.v:2897.25-2897.44"
+ cell $not $not$ls180.v:2897$615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_sink_ready
- connect \Y $not$ls180.v:2884$614_Y
+ connect \Y $not$ls180.v:2897$615_Y
end
- attribute \src "ls180.v:2887.22-2887.43"
- cell $not $not$ls180.v:2887$617
+ attribute \src "ls180.v:2900.22-2900.43"
+ cell $not $not$ls180.v:2900$618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_source_valid
- connect \Y $not$ls180.v:2887$617_Y
+ connect \Y $not$ls180.v:2900$618_Y
end
- attribute \src "ls180.v:2925.61-2925.78"
- cell $not $not$ls180.v:2925$627
+ attribute \src "ls180.v:2938.61-2938.78"
+ cell $not $not$ls180.v:2938$628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_readable
- connect \Y $not$ls180.v:2925$627_Y
+ connect \Y $not$ls180.v:2938$628_Y
end
- attribute \src "ls180.v:2955.61-2955.78"
- cell $not $not$ls180.v:2955$638
+ attribute \src "ls180.v:2968.61-2968.78"
+ cell $not $not$ls180.v:2968$639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_readable
- connect \Y $not$ls180.v:2955$638_Y
+ connect \Y $not$ls180.v:2968$639_Y
end
- attribute \src "ls180.v:3150.81-3150.104"
- cell $not $not$ls180.v:3150$688
+ attribute \src "ls180.v:3163.81-3163.104"
+ cell $not $not$ls180.v:3163$689
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_shared_ack
- connect \Y $not$ls180.v:3150$688_Y
+ connect \Y $not$ls180.v:3163$689_Y
end
- attribute \src "ls180.v:3167.71-3167.106"
- cell $not $not$ls180.v:3167$712
+ attribute \src "ls180.v:3180.71-3180.106"
+ cell $not $not$ls180.v:3180$713
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3167$712_Y
+ connect \Y $not$ls180.v:3180$713_Y
end
- attribute \src "ls180.v:3170.73-3170.108"
- cell $not $not$ls180.v:3170$719
+ attribute \src "ls180.v:3183.73-3183.108"
+ cell $not $not$ls180.v:3183$720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3170$719_Y
+ connect \Y $not$ls180.v:3183$720_Y
end
- attribute \src "ls180.v:3173.73-3173.108"
- cell $not $not$ls180.v:3173$726
+ attribute \src "ls180.v:3186.73-3186.108"
+ cell $not $not$ls180.v:3186$727
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3173$726_Y
+ connect \Y $not$ls180.v:3186$727_Y
end
- attribute \src "ls180.v:3176.73-3176.108"
- cell $not $not$ls180.v:3176$733
+ attribute \src "ls180.v:3189.73-3189.108"
+ cell $not $not$ls180.v:3189$734
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3176$733_Y
+ connect \Y $not$ls180.v:3189$734_Y
end
- attribute \src "ls180.v:3179.73-3179.108"
- cell $not $not$ls180.v:3179$740
+ attribute \src "ls180.v:3192.73-3192.108"
+ cell $not $not$ls180.v:3192$741
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3179$740_Y
+ connect \Y $not$ls180.v:3192$741_Y
end
- attribute \src "ls180.v:3182.76-3182.111"
- cell $not $not$ls180.v:3182$747
+ attribute \src "ls180.v:3195.76-3195.111"
+ cell $not $not$ls180.v:3195$748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3182$747_Y
+ connect \Y $not$ls180.v:3195$748_Y
end
- attribute \src "ls180.v:3185.76-3185.111"
- cell $not $not$ls180.v:3185$754
+ attribute \src "ls180.v:3198.76-3198.111"
+ cell $not $not$ls180.v:3198$755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3185$754_Y
+ connect \Y $not$ls180.v:3198$755_Y
end
- attribute \src "ls180.v:3188.76-3188.111"
- cell $not $not$ls180.v:3188$761
+ attribute \src "ls180.v:3201.76-3201.111"
+ cell $not $not$ls180.v:3201$762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3188$761_Y
+ connect \Y $not$ls180.v:3201$762_Y
end
- attribute \src "ls180.v:3191.76-3191.111"
- cell $not $not$ls180.v:3191$768
+ attribute \src "ls180.v:3204.76-3204.111"
+ cell $not $not$ls180.v:3204$769
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface0_bank_bus_we
- connect \Y $not$ls180.v:3191$768_Y
+ connect \Y $not$ls180.v:3204$769_Y
end
- attribute \src "ls180.v:3205.68-3205.103"
- cell $not $not$ls180.v:3205$776
+ attribute \src "ls180.v:3218.68-3218.103"
+ cell $not $not$ls180.v:3218$777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_we
- connect \Y $not$ls180.v:3205$776_Y
+ connect \Y $not$ls180.v:3218$777_Y
end
- attribute \src "ls180.v:3208.67-3208.102"
- cell $not $not$ls180.v:3208$783
+ attribute \src "ls180.v:3221.67-3221.102"
+ cell $not $not$ls180.v:3221$784
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_we
- connect \Y $not$ls180.v:3208$783_Y
+ connect \Y $not$ls180.v:3221$784_Y
end
- attribute \src "ls180.v:3211.69-3211.104"
- cell $not $not$ls180.v:3211$790
+ attribute \src "ls180.v:3224.69-3224.104"
+ cell $not $not$ls180.v:3224$791
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface1_bank_bus_we
- connect \Y $not$ls180.v:3211$790_Y
+ connect \Y $not$ls180.v:3224$791_Y
end
- attribute \src "ls180.v:3219.68-3219.103"
- cell $not $not$ls180.v:3219$798
+ attribute \src "ls180.v:3232.68-3232.103"
+ cell $not $not$ls180.v:3232$799
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_we
- connect \Y $not$ls180.v:3219$798_Y
+ connect \Y $not$ls180.v:3232$799_Y
end
- attribute \src "ls180.v:3222.67-3222.102"
- cell $not $not$ls180.v:3222$805
+ attribute \src "ls180.v:3235.67-3235.102"
+ cell $not $not$ls180.v:3235$806
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_we
- connect \Y $not$ls180.v:3222$805_Y
+ connect \Y $not$ls180.v:3235$806_Y
end
- attribute \src "ls180.v:3225.69-3225.104"
- cell $not $not$ls180.v:3225$812
+ attribute \src "ls180.v:3238.69-3238.104"
+ cell $not $not$ls180.v:3238$813
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface2_bank_bus_we
- connect \Y $not$ls180.v:3225$812_Y
+ connect \Y $not$ls180.v:3238$813_Y
end
- attribute \src "ls180.v:3233.67-3233.102"
- cell $not $not$ls180.v:3233$820
+ attribute \src "ls180.v:3246.67-3246.102"
+ cell $not $not$ls180.v:3246$821
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface3_bank_bus_we
- connect \Y $not$ls180.v:3233$820_Y
+ connect \Y $not$ls180.v:3246$821_Y
end
- attribute \src "ls180.v:3236.66-3236.101"
- cell $not $not$ls180.v:3236$827
+ attribute \src "ls180.v:3249.66-3249.101"
+ cell $not $not$ls180.v:3249$828
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface3_bank_bus_we
- connect \Y $not$ls180.v:3236$827_Y
+ connect \Y $not$ls180.v:3249$828_Y
end
- attribute \src "ls180.v:3247.78-3247.113"
- cell $not $not$ls180.v:3247$835
+ attribute \src "ls180.v:3260.78-3260.113"
+ cell $not $not$ls180.v:3260$836
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3247$835_Y
+ connect \Y $not$ls180.v:3260$836_Y
end
- attribute \src "ls180.v:3250.82-3250.117"
- cell $not $not$ls180.v:3250$842
+ attribute \src "ls180.v:3263.82-3263.117"
+ cell $not $not$ls180.v:3263$843
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3250$842_Y
+ connect \Y $not$ls180.v:3263$843_Y
end
- attribute \src "ls180.v:3253.63-3253.98"
- cell $not $not$ls180.v:3253$849
+ attribute \src "ls180.v:3266.63-3266.98"
+ cell $not $not$ls180.v:3266$850
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3253$849_Y
+ connect \Y $not$ls180.v:3266$850_Y
end
- attribute \src "ls180.v:3256.82-3256.117"
- cell $not $not$ls180.v:3256$856
+ attribute \src "ls180.v:3269.82-3269.117"
+ cell $not $not$ls180.v:3269$857
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3256$856_Y
+ connect \Y $not$ls180.v:3269$857_Y
end
- attribute \src "ls180.v:3259.82-3259.117"
- cell $not $not$ls180.v:3259$863
+ attribute \src "ls180.v:3272.82-3272.117"
+ cell $not $not$ls180.v:3272$864
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3259$863_Y
+ connect \Y $not$ls180.v:3272$864_Y
end
- attribute \src "ls180.v:3262.83-3262.118"
- cell $not $not$ls180.v:3262$870
+ attribute \src "ls180.v:3275.83-3275.118"
+ cell $not $not$ls180.v:3275$871
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3262$870_Y
+ connect \Y $not$ls180.v:3275$871_Y
end
- attribute \src "ls180.v:3265.81-3265.116"
- cell $not $not$ls180.v:3265$877
+ attribute \src "ls180.v:3278.81-3278.116"
+ cell $not $not$ls180.v:3278$878
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3265$877_Y
+ connect \Y $not$ls180.v:3278$878_Y
end
- attribute \src "ls180.v:3268.81-3268.116"
- cell $not $not$ls180.v:3268$884
+ attribute \src "ls180.v:3281.81-3281.116"
+ cell $not $not$ls180.v:3281$885
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3268$884_Y
+ connect \Y $not$ls180.v:3281$885_Y
end
- attribute \src "ls180.v:3271.81-3271.116"
- cell $not $not$ls180.v:3271$891
+ attribute \src "ls180.v:3284.81-3284.116"
+ cell $not $not$ls180.v:3284$892
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3271$891_Y
+ connect \Y $not$ls180.v:3284$892_Y
end
- attribute \src "ls180.v:3274.81-3274.116"
- cell $not $not$ls180.v:3274$898
+ attribute \src "ls180.v:3287.81-3287.116"
+ cell $not $not$ls180.v:3287$899
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface4_bank_bus_we
- connect \Y $not$ls180.v:3274$898_Y
+ connect \Y $not$ls180.v:3287$899_Y
end
- attribute \src "ls180.v:3292.70-3292.105"
- cell $not $not$ls180.v:3292$906
+ attribute \src "ls180.v:3305.70-3305.105"
+ cell $not $not$ls180.v:3305$907
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3292$906_Y
+ connect \Y $not$ls180.v:3305$907_Y
end
- attribute \src "ls180.v:3295.70-3295.105"
- cell $not $not$ls180.v:3295$913
+ attribute \src "ls180.v:3308.70-3308.105"
+ cell $not $not$ls180.v:3308$914
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3295$913_Y
+ connect \Y $not$ls180.v:3308$914_Y
end
- attribute \src "ls180.v:3298.70-3298.105"
- cell $not $not$ls180.v:3298$920
+ attribute \src "ls180.v:3311.70-3311.105"
+ cell $not $not$ls180.v:3311$921
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3298$920_Y
+ connect \Y $not$ls180.v:3311$921_Y
end
- attribute \src "ls180.v:3301.70-3301.105"
- cell $not $not$ls180.v:3301$927
+ attribute \src "ls180.v:3314.70-3314.105"
+ cell $not $not$ls180.v:3314$928
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3301$927_Y
+ connect \Y $not$ls180.v:3314$928_Y
end
- attribute \src "ls180.v:3304.72-3304.107"
- cell $not $not$ls180.v:3304$934
+ attribute \src "ls180.v:3317.72-3317.107"
+ cell $not $not$ls180.v:3317$935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3304$934_Y
+ connect \Y $not$ls180.v:3317$935_Y
end
- attribute \src "ls180.v:3307.72-3307.107"
- cell $not $not$ls180.v:3307$941
+ attribute \src "ls180.v:3320.72-3320.107"
+ cell $not $not$ls180.v:3320$942
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3307$941_Y
+ connect \Y $not$ls180.v:3320$942_Y
end
- attribute \src "ls180.v:3310.72-3310.107"
- cell $not $not$ls180.v:3310$948
+ attribute \src "ls180.v:3323.72-3323.107"
+ cell $not $not$ls180.v:3323$949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3310$948_Y
+ connect \Y $not$ls180.v:3323$949_Y
end
- attribute \src "ls180.v:3313.72-3313.107"
- cell $not $not$ls180.v:3313$955
+ attribute \src "ls180.v:3326.72-3326.107"
+ cell $not $not$ls180.v:3326$956
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3313$955_Y
+ connect \Y $not$ls180.v:3326$956_Y
end
- attribute \src "ls180.v:3316.68-3316.103"
- cell $not $not$ls180.v:3316$962
+ attribute \src "ls180.v:3329.68-3329.103"
+ cell $not $not$ls180.v:3329$963
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3316$962_Y
+ connect \Y $not$ls180.v:3329$963_Y
end
- attribute \src "ls180.v:3319.78-3319.113"
- cell $not $not$ls180.v:3319$969
+ attribute \src "ls180.v:3332.78-3332.113"
+ cell $not $not$ls180.v:3332$970
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3319$969_Y
+ connect \Y $not$ls180.v:3332$970_Y
end
- attribute \src "ls180.v:3322.71-3322.106"
- cell $not $not$ls180.v:3322$976
+ attribute \src "ls180.v:3335.71-3335.106"
+ cell $not $not$ls180.v:3335$977
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3322$976_Y
+ connect \Y $not$ls180.v:3335$977_Y
end
- attribute \src "ls180.v:3325.71-3325.106"
- cell $not $not$ls180.v:3325$983
+ attribute \src "ls180.v:3338.71-3338.106"
+ cell $not $not$ls180.v:3338$984
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3325$983_Y
+ connect \Y $not$ls180.v:3338$984_Y
end
- attribute \src "ls180.v:3328.71-3328.106"
- cell $not $not$ls180.v:3328$990
+ attribute \src "ls180.v:3341.71-3341.106"
+ cell $not $not$ls180.v:3341$991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3328$990_Y
+ connect \Y $not$ls180.v:3341$991_Y
end
- attribute \src "ls180.v:3331.71-3331.106"
- cell $not $not$ls180.v:3331$997
+ attribute \src "ls180.v:3344.71-3344.106"
+ cell $not $not$ls180.v:3344$998
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3331$997_Y
+ connect \Y $not$ls180.v:3344$998_Y
end
- attribute \src "ls180.v:3334.75-3334.110"
- cell $not $not$ls180.v:3334$1004
+ attribute \src "ls180.v:3347.75-3347.110"
+ cell $not $not$ls180.v:3347$1005
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3334$1004_Y
+ connect \Y $not$ls180.v:3347$1005_Y
end
- attribute \src "ls180.v:3337.76-3337.111"
- cell $not $not$ls180.v:3337$1011
+ attribute \src "ls180.v:3350.76-3350.111"
+ cell $not $not$ls180.v:3350$1012
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3337$1011_Y
+ connect \Y $not$ls180.v:3350$1012_Y
end
- attribute \src "ls180.v:3340.75-3340.110"
- cell $not $not$ls180.v:3340$1018
+ attribute \src "ls180.v:3353.75-3353.110"
+ cell $not $not$ls180.v:3353$1019
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface5_bank_bus_we
- connect \Y $not$ls180.v:3340$1018_Y
+ connect \Y $not$ls180.v:3353$1019_Y
end
- attribute \src "ls180.v:3360.48-3360.83"
- cell $not $not$ls180.v:3360$1026
+ attribute \src "ls180.v:3373.48-3373.83"
+ cell $not $not$ls180.v:3373$1027
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3360$1026_Y
+ connect \Y $not$ls180.v:3373$1027_Y
end
- attribute \src "ls180.v:3363.71-3363.106"
- cell $not $not$ls180.v:3363$1033
+ attribute \src "ls180.v:3376.71-3376.106"
+ cell $not $not$ls180.v:3376$1034
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3363$1033_Y
+ connect \Y $not$ls180.v:3376$1034_Y
end
- attribute \src "ls180.v:3366.72-3366.107"
- cell $not $not$ls180.v:3366$1040
+ attribute \src "ls180.v:3379.72-3379.107"
+ cell $not $not$ls180.v:3379$1041
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3366$1040_Y
+ connect \Y $not$ls180.v:3379$1041_Y
end
- attribute \src "ls180.v:3369.63-3369.98"
- cell $not $not$ls180.v:3369$1047
+ attribute \src "ls180.v:3382.63-3382.98"
+ cell $not $not$ls180.v:3382$1048
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3369$1047_Y
+ connect \Y $not$ls180.v:3382$1048_Y
end
- attribute \src "ls180.v:3372.64-3372.99"
- cell $not $not$ls180.v:3372$1054
+ attribute \src "ls180.v:3385.64-3385.99"
+ cell $not $not$ls180.v:3385$1055
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3372$1054_Y
+ connect \Y $not$ls180.v:3385$1055_Y
end
- attribute \src "ls180.v:3375.75-3375.110"
- cell $not $not$ls180.v:3375$1061
+ attribute \src "ls180.v:3388.75-3388.110"
+ cell $not $not$ls180.v:3388$1062
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3375$1061_Y
+ connect \Y $not$ls180.v:3388$1062_Y
end
- attribute \src "ls180.v:3378.72-3378.107"
- cell $not $not$ls180.v:3378$1068
+ attribute \src "ls180.v:3391.72-3391.107"
+ cell $not $not$ls180.v:3391$1069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3378$1068_Y
+ connect \Y $not$ls180.v:3391$1069_Y
end
- attribute \src "ls180.v:3381.71-3381.106"
- cell $not $not$ls180.v:3381$1075
+ attribute \src "ls180.v:3394.71-3394.106"
+ cell $not $not$ls180.v:3394$1076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface6_bank_bus_we
- connect \Y $not$ls180.v:3381$1075_Y
+ connect \Y $not$ls180.v:3394$1076_Y
end
- attribute \src "ls180.v:3394.77-3394.112"
- cell $not $not$ls180.v:3394$1083
+ attribute \src "ls180.v:3407.77-3407.112"
+ cell $not $not$ls180.v:3407$1084
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_we
- connect \Y $not$ls180.v:3394$1083_Y
+ connect \Y $not$ls180.v:3407$1084_Y
end
- attribute \src "ls180.v:3397.77-3397.112"
- cell $not $not$ls180.v:3397$1090
+ attribute \src "ls180.v:3410.77-3410.112"
+ cell $not $not$ls180.v:3410$1091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_we
- connect \Y $not$ls180.v:3397$1090_Y
+ connect \Y $not$ls180.v:3410$1091_Y
end
- attribute \src "ls180.v:3400.77-3400.112"
- cell $not $not$ls180.v:3400$1097
+ attribute \src "ls180.v:3413.77-3413.112"
+ cell $not $not$ls180.v:3413$1098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_we
- connect \Y $not$ls180.v:3400$1097_Y
+ connect \Y $not$ls180.v:3413$1098_Y
end
- attribute \src "ls180.v:3403.77-3403.112"
- cell $not $not$ls180.v:3403$1104
+ attribute \src "ls180.v:3416.77-3416.112"
+ cell $not $not$ls180.v:3416$1105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_interface7_bank_bus_we
- connect \Y $not$ls180.v:3403$1104_Y
+ connect \Y $not$ls180.v:3416$1105_Y
end
- attribute \src "ls180.v:3763.68-3763.317"
- cell $not $not$ls180.v:3763$1146
+ attribute \src "ls180.v:3776.68-3776.317"
+ cell $not $not$ls180.v:3776$1147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3763$1145_Y
- connect \Y $not$ls180.v:3763$1146_Y
+ connect \A $or$ls180.v:3776$1146_Y
+ connect \Y $not$ls180.v:3776$1147_Y
end
- attribute \src "ls180.v:3787.68-3787.317"
- cell $not $not$ls180.v:3787$1162
+ attribute \src "ls180.v:3800.68-3800.317"
+ cell $not $not$ls180.v:3800$1163
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3787$1161_Y
- connect \Y $not$ls180.v:3787$1162_Y
+ connect \A $or$ls180.v:3800$1162_Y
+ connect \Y $not$ls180.v:3800$1163_Y
end
- attribute \src "ls180.v:3811.68-3811.317"
- cell $not $not$ls180.v:3811$1178
+ attribute \src "ls180.v:3824.68-3824.317"
+ cell $not $not$ls180.v:3824$1179
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3811$1177_Y
- connect \Y $not$ls180.v:3811$1178_Y
+ connect \A $or$ls180.v:3824$1178_Y
+ connect \Y $not$ls180.v:3824$1179_Y
end
- attribute \src "ls180.v:3835.68-3835.317"
- cell $not $not$ls180.v:3835$1194
+ attribute \src "ls180.v:3848.68-3848.317"
+ cell $not $not$ls180.v:3848$1195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3835$1193_Y
- connect \Y $not$ls180.v:3835$1194_Y
+ connect \A $or$ls180.v:3848$1194_Y
+ connect \Y $not$ls180.v:3848$1195_Y
end
- attribute \src "ls180.v:4357.62-4357.86"
- cell $not $not$ls180.v:4357$1283
+ attribute \src "ls180.v:4376.62-4376.86"
+ cell $not $not$ls180.v:4376$1290
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_ack
- connect \Y $not$ls180.v:4357$1283_Y
+ connect \Y $not$ls180.v:4376$1290_Y
end
- attribute \src "ls180.v:4376.8-4376.33"
- cell $not $not$ls180.v:4376$1287
+ attribute \src "ls180.v:4395.8-4395.33"
+ cell $not $not$ls180.v:4395$1294
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_zero_trigger
- connect \Y $not$ls180.v:4376$1287_Y
+ connect \Y $not$ls180.v:4395$1294_Y
end
- attribute \src "ls180.v:4380.54-4380.74"
- cell $not $not$ls180.v:4380$1290
+ attribute \src "ls180.v:4399.54-4399.74"
+ cell $not $not$ls180.v:4399$1297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ram_bus_ram_bus_ack
- connect \Y $not$ls180.v:4380$1290_Y
+ connect \Y $not$ls180.v:4399$1297_Y
end
- attribute \src "ls180.v:4388.27-4388.45"
- cell $not $not$ls180.v:4388$1292
+ attribute \src "ls180.v:4407.27-4407.45"
+ cell $not $not$ls180.v:4407$1299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_timer_done0
- connect \Y $not$ls180.v:4388$1292_Y
+ connect \Y $not$ls180.v:4407$1299_Y
end
- attribute \src "ls180.v:4458.126-4458.174"
- cell $not $not$ls180.v:4458$1307
+ attribute \src "ls180.v:4477.126-4477.174"
+ cell $not $not$ls180.v:4477$1314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4458$1307_Y
+ connect \Y $not$ls180.v:4477$1314_Y
end
- attribute \src "ls180.v:4464.126-4464.174"
- cell $not $not$ls180.v:4464$1312
+ attribute \src "ls180.v:4483.126-4483.174"
+ cell $not $not$ls180.v:4483$1319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4464$1312_Y
+ connect \Y $not$ls180.v:4483$1319_Y
end
- attribute \src "ls180.v:4465.8-4465.56"
- cell $not $not$ls180.v:4465$1314
+ attribute \src "ls180.v:4484.8-4484.56"
+ cell $not $not$ls180.v:4484$1321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:4465$1314_Y
+ connect \Y $not$ls180.v:4484$1321_Y
end
- attribute \src "ls180.v:4473.8-4473.51"
- cell $not $not$ls180.v:4473$1317
+ attribute \src "ls180.v:4492.8-4492.51"
+ cell $not $not$ls180.v:4492$1324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $not$ls180.v:4473$1317_Y
+ connect \Y $not$ls180.v:4492$1324_Y
end
- attribute \src "ls180.v:4488.8-4488.41"
- cell $not $not$ls180.v:4488$1319
+ attribute \src "ls180.v:4507.8-4507.41"
+ cell $not $not$ls180.v:4507$1326
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_twtpcon_ready
- connect \Y $not$ls180.v:4488$1319_Y
+ connect \Y $not$ls180.v:4507$1326_Y
end
- attribute \src "ls180.v:4504.126-4504.174"
- cell $not $not$ls180.v:4504$1323
+ attribute \src "ls180.v:4523.126-4523.174"
+ cell $not $not$ls180.v:4523$1330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4504$1323_Y
+ connect \Y $not$ls180.v:4523$1330_Y
end
- attribute \src "ls180.v:4510.126-4510.174"
- cell $not $not$ls180.v:4510$1328
+ attribute \src "ls180.v:4529.126-4529.174"
+ cell $not $not$ls180.v:4529$1335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4510$1328_Y
+ connect \Y $not$ls180.v:4529$1335_Y
end
- attribute \src "ls180.v:4511.8-4511.56"
- cell $not $not$ls180.v:4511$1330
+ attribute \src "ls180.v:4530.8-4530.56"
+ cell $not $not$ls180.v:4530$1337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:4511$1330_Y
+ connect \Y $not$ls180.v:4530$1337_Y
end
- attribute \src "ls180.v:4519.8-4519.51"
- cell $not $not$ls180.v:4519$1333
+ attribute \src "ls180.v:4538.8-4538.51"
+ cell $not $not$ls180.v:4538$1340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $not$ls180.v:4519$1333_Y
+ connect \Y $not$ls180.v:4538$1340_Y
end
- attribute \src "ls180.v:4534.8-4534.41"
- cell $not $not$ls180.v:4534$1335
+ attribute \src "ls180.v:4553.8-4553.41"
+ cell $not $not$ls180.v:4553$1342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_twtpcon_ready
- connect \Y $not$ls180.v:4534$1335_Y
+ connect \Y $not$ls180.v:4553$1342_Y
end
- attribute \src "ls180.v:4550.126-4550.174"
- cell $not $not$ls180.v:4550$1339
+ attribute \src "ls180.v:4569.126-4569.174"
+ cell $not $not$ls180.v:4569$1346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4550$1339_Y
+ connect \Y $not$ls180.v:4569$1346_Y
end
- attribute \src "ls180.v:4556.126-4556.174"
- cell $not $not$ls180.v:4556$1344
+ attribute \src "ls180.v:4575.126-4575.174"
+ cell $not $not$ls180.v:4575$1351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4556$1344_Y
+ connect \Y $not$ls180.v:4575$1351_Y
end
- attribute \src "ls180.v:4557.8-4557.56"
- cell $not $not$ls180.v:4557$1346
+ attribute \src "ls180.v:4576.8-4576.56"
+ cell $not $not$ls180.v:4576$1353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:4557$1346_Y
+ connect \Y $not$ls180.v:4576$1353_Y
end
- attribute \src "ls180.v:4565.8-4565.51"
- cell $not $not$ls180.v:4565$1349
+ attribute \src "ls180.v:4584.8-4584.51"
+ cell $not $not$ls180.v:4584$1356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $not$ls180.v:4565$1349_Y
+ connect \Y $not$ls180.v:4584$1356_Y
end
- attribute \src "ls180.v:4580.8-4580.41"
- cell $not $not$ls180.v:4580$1351
+ attribute \src "ls180.v:4599.8-4599.41"
+ cell $not $not$ls180.v:4599$1358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_twtpcon_ready
- connect \Y $not$ls180.v:4580$1351_Y
+ connect \Y $not$ls180.v:4599$1358_Y
end
- attribute \src "ls180.v:4596.126-4596.174"
- cell $not $not$ls180.v:4596$1355
+ attribute \src "ls180.v:4615.126-4615.174"
+ cell $not $not$ls180.v:4615$1362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4596$1355_Y
+ connect \Y $not$ls180.v:4615$1362_Y
end
- attribute \src "ls180.v:4602.126-4602.174"
- cell $not $not$ls180.v:4602$1360
+ attribute \src "ls180.v:4621.126-4621.174"
+ cell $not $not$ls180.v:4621$1367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $not$ls180.v:4602$1360_Y
+ connect \Y $not$ls180.v:4621$1367_Y
end
- attribute \src "ls180.v:4603.8-4603.56"
- cell $not $not$ls180.v:4603$1362
+ attribute \src "ls180.v:4622.8-4622.56"
+ cell $not $not$ls180.v:4622$1369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_do_read
- connect \Y $not$ls180.v:4603$1362_Y
+ connect \Y $not$ls180.v:4622$1369_Y
end
- attribute \src "ls180.v:4611.8-4611.51"
- cell $not $not$ls180.v:4611$1365
+ attribute \src "ls180.v:4630.8-4630.51"
+ cell $not $not$ls180.v:4630$1372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $not$ls180.v:4611$1365_Y
+ connect \Y $not$ls180.v:4630$1372_Y
end
- attribute \src "ls180.v:4626.8-4626.41"
- cell $not $not$ls180.v:4626$1367
+ attribute \src "ls180.v:4645.8-4645.41"
+ cell $not $not$ls180.v:4645$1374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_twtpcon_ready
- connect \Y $not$ls180.v:4626$1367_Y
+ connect \Y $not$ls180.v:4645$1374_Y
end
- attribute \src "ls180.v:4634.7-4634.17"
- cell $not $not$ls180.v:4634$1370
+ attribute \src "ls180.v:4653.7-4653.17"
+ cell $not $not$ls180.v:4653$1377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_en0
- connect \Y $not$ls180.v:4634$1370_Y
+ connect \Y $not$ls180.v:4653$1377_Y
end
- attribute \src "ls180.v:4637.8-4637.24"
- cell $not $not$ls180.v:4637$1371
+ attribute \src "ls180.v:4656.8-4656.24"
+ cell $not $not$ls180.v:4656$1378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_max_time0
- connect \Y $not$ls180.v:4637$1371_Y
+ connect \Y $not$ls180.v:4656$1378_Y
end
- attribute \src "ls180.v:4641.7-4641.17"
- cell $not $not$ls180.v:4641$1373
+ attribute \src "ls180.v:4660.7-4660.17"
+ cell $not $not$ls180.v:4660$1380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_en1
- connect \Y $not$ls180.v:4641$1373_Y
+ connect \Y $not$ls180.v:4660$1380_Y
end
- attribute \src "ls180.v:4644.8-4644.24"
- cell $not $not$ls180.v:4644$1374
+ attribute \src "ls180.v:4663.8-4663.24"
+ cell $not $not$ls180.v:4663$1381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_max_time1
- connect \Y $not$ls180.v:4644$1374_Y
+ connect \Y $not$ls180.v:4663$1381_Y
end
- attribute \src "ls180.v:4763.25-4763.38"
- cell $not $not$ls180.v:4763$1376
+ attribute \src "ls180.v:4782.25-4782.38"
+ cell $not $not$ls180.v:4782$1383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \array_muxed2
- connect \Y $not$ls180.v:4763$1376_Y
+ connect \Y $not$ls180.v:4782$1383_Y
end
- attribute \src "ls180.v:4764.25-4764.38"
- cell $not $not$ls180.v:4764$1377
+ attribute \src "ls180.v:4783.25-4783.38"
+ cell $not $not$ls180.v:4783$1384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \array_muxed3
- connect \Y $not$ls180.v:4764$1377_Y
+ connect \Y $not$ls180.v:4783$1384_Y
end
- attribute \src "ls180.v:4765.24-4765.37"
- cell $not $not$ls180.v:4765$1378
+ attribute \src "ls180.v:4784.24-4784.37"
+ cell $not $not$ls180.v:4784$1385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \array_muxed4
- connect \Y $not$ls180.v:4765$1378_Y
+ connect \Y $not$ls180.v:4784$1385_Y
end
- attribute \src "ls180.v:4776.8-4776.28"
- cell $not $not$ls180.v:4776$1379
+ attribute \src "ls180.v:4795.8-4795.28"
+ cell $not $not$ls180.v:4795$1386
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_tccdcon_ready
- connect \Y $not$ls180.v:4776$1379_Y
+ connect \Y $not$ls180.v:4795$1386_Y
end
- attribute \src "ls180.v:4791.8-4791.28"
- cell $not $not$ls180.v:4791$1382
+ attribute \src "ls180.v:4810.8-4810.28"
+ cell $not $not$ls180.v:4810$1389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_twtrcon_ready
- connect \Y $not$ls180.v:4791$1382_Y
+ connect \Y $not$ls180.v:4810$1389_Y
end
- attribute \src "ls180.v:4827.31-4827.48"
- cell $not $not$ls180.v:4827$1412
+ attribute \src "ls180.v:4846.31-4846.48"
+ cell $not $not$ls180.v:4846$1419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \uart_phy_tx_busy
- connect \Y $not$ls180.v:4827$1412_Y
+ connect \Y $not$ls180.v:4846$1419_Y
end
- attribute \src "ls180.v:4827.54-4827.74"
- cell $not $not$ls180.v:4827$1414
+ attribute \src "ls180.v:4846.54-4846.74"
+ cell $not $not$ls180.v:4846$1421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \uart_phy_sink_ready
- connect \Y $not$ls180.v:4827$1414_Y
+ connect \Y $not$ls180.v:4846$1421_Y
end
- attribute \src "ls180.v:4856.7-4856.24"
- cell $not $not$ls180.v:4856$1421
+ attribute \src "ls180.v:4875.7-4875.24"
+ cell $not $not$ls180.v:4875$1428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \uart_phy_rx_busy
- connect \Y $not$ls180.v:4856$1421_Y
+ connect \Y $not$ls180.v:4875$1428_Y
end
- attribute \src "ls180.v:4857.9-4857.21"
- cell $not $not$ls180.v:4857$1422
+ attribute \src "ls180.v:4876.9-4876.21"
+ cell $not $not$ls180.v:4876$1429
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \uart_phy_rx
- connect \Y $not$ls180.v:4857$1422_Y
+ connect \Y $not$ls180.v:4876$1429_Y
end
- attribute \src "ls180.v:4890.8-4890.19"
- cell $not $not$ls180.v:4890$1428
+ attribute \src "ls180.v:4909.8-4909.19"
+ cell $not $not$ls180.v:4909$1435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_trigger
- connect \Y $not$ls180.v:4890$1428_Y
+ connect \Y $not$ls180.v:4909$1435_Y
end
- attribute \src "ls180.v:4897.8-4897.19"
- cell $not $not$ls180.v:4897$1430
+ attribute \src "ls180.v:4916.8-4916.19"
+ cell $not $not$ls180.v:4916$1437
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_trigger
- connect \Y $not$ls180.v:4897$1430_Y
+ connect \Y $not$ls180.v:4916$1437_Y
end
- attribute \src "ls180.v:4907.60-4907.76"
- cell $not $not$ls180.v:4907$1433
+ attribute \src "ls180.v:4926.60-4926.76"
+ cell $not $not$ls180.v:4926$1440
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_replace
- connect \Y $not$ls180.v:4907$1433_Y
+ connect \Y $not$ls180.v:4926$1440_Y
end
- attribute \src "ls180.v:4913.60-4913.76"
- cell $not $not$ls180.v:4913$1438
+ attribute \src "ls180.v:4932.60-4932.76"
+ cell $not $not$ls180.v:4932$1445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_replace
- connect \Y $not$ls180.v:4913$1438_Y
+ connect \Y $not$ls180.v:4932$1445_Y
end
- attribute \src "ls180.v:4914.8-4914.24"
- cell $not $not$ls180.v:4914$1440
+ attribute \src "ls180.v:4933.8-4933.24"
+ cell $not $not$ls180.v:4933$1447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \tx_fifo_do_read
- connect \Y $not$ls180.v:4914$1440_Y
+ connect \Y $not$ls180.v:4933$1447_Y
end
- attribute \src "ls180.v:4929.60-4929.76"
- cell $not $not$ls180.v:4929$1444
+ attribute \src "ls180.v:4948.60-4948.76"
+ cell $not $not$ls180.v:4948$1451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_replace
- connect \Y $not$ls180.v:4929$1444_Y
+ connect \Y $not$ls180.v:4948$1451_Y
end
- attribute \src "ls180.v:4935.60-4935.76"
- cell $not $not$ls180.v:4935$1449
+ attribute \src "ls180.v:4954.60-4954.76"
+ cell $not $not$ls180.v:4954$1456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_replace
- connect \Y $not$ls180.v:4935$1449_Y
+ connect \Y $not$ls180.v:4954$1456_Y
end
- attribute \src "ls180.v:4936.8-4936.24"
- cell $not $not$ls180.v:4936$1451
+ attribute \src "ls180.v:4955.8-4955.24"
+ cell $not $not$ls180.v:4955$1458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_fifo_do_read
- connect \Y $not$ls180.v:4936$1451_Y
+ connect \Y $not$ls180.v:4955$1458_Y
end
- attribute \src "ls180.v:4970.9-4970.32"
- cell $not $not$ls180.v:4970$1454
+ attribute \src "ls180.v:4989.9-4989.32"
+ cell $not $not$ls180.v:4989$1461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_request [0]
- connect \Y $not$ls180.v:4970$1454_Y
+ connect \Y $not$ls180.v:4989$1461_Y
end
- attribute \src "ls180.v:4981.9-4981.32"
- cell $not $not$ls180.v:4981$1455
+ attribute \src "ls180.v:5000.9-5000.32"
+ cell $not $not$ls180.v:5000$1462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_request [1]
- connect \Y $not$ls180.v:4981$1455_Y
+ connect \Y $not$ls180.v:5000$1462_Y
end
- attribute \src "ls180.v:4992.9-4992.32"
- cell $not $not$ls180.v:4992$1456
+ attribute \src "ls180.v:5011.9-5011.32"
+ cell $not $not$ls180.v:5011$1463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_request [2]
- connect \Y $not$ls180.v:4992$1456_Y
+ connect \Y $not$ls180.v:5011$1463_Y
end
- attribute \src "ls180.v:5005.8-5005.25"
- cell $not $not$ls180.v:5005$1457
+ attribute \src "ls180.v:5024.8-5024.25"
+ cell $not $not$ls180.v:5024$1464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \libresocsim_done
- connect \Y $not$ls180.v:5005$1457_Y
+ connect \Y $not$ls180.v:5024$1464_Y
end
- attribute \src "ls180.v:1554.10-1554.61"
- cell $or $or$ls180.v:1554$31
+ attribute \src "ls180.v:1567.10-1567.61"
+ cell $or $or$ls180.v:1567$32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresoc_xics_icp_ack
connect \B \converter0_skip
- connect \Y $or$ls180.v:1554$31_Y
+ connect \Y $or$ls180.v:1567$32_Y
end
- attribute \src "ls180.v:1614.10-1614.61"
- cell $or $or$ls180.v:1614$42
+ attribute \src "ls180.v:1627.10-1627.61"
+ cell $or $or$ls180.v:1627$43
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresoc_xics_ics_ack
connect \B \converter1_skip
- connect \Y $or$ls180.v:1614$42_Y
+ connect \Y $or$ls180.v:1627$43_Y
end
- attribute \src "ls180.v:1674.10-1674.43"
- cell $or $or$ls180.v:1674$53
+ attribute \src "ls180.v:1687.10-1687.43"
+ cell $or $or$ls180.v:1687$54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_sdram_ack
connect \B \socbushandler_skip
- connect \Y $or$ls180.v:1674$53_Y
+ connect \Y $or$ls180.v:1687$54_Y
end
- attribute \src "ls180.v:1884.34-1884.90"
- cell $or $or$ls180.v:1884$122
+ attribute \src "ls180.v:1897.34-1897.90"
+ cell $or $or$ls180.v:1897$123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_start0
- connect \B $ne$ls180.v:1884$121_Y
- connect \Y $or$ls180.v:1884$122_Y
+ connect \B $ne$ls180.v:1897$122_Y
+ connect \Y $or$ls180.v:1897$123_Y
end
- attribute \src "ls180.v:1927.54-1927.125"
- cell $or $or$ls180.v:1927$126
+ attribute \src "ls180.v:1940.54-1940.125"
+ cell $or $or$ls180.v:1940$127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_req_wdata_ready
connect \B \sdram_bankmachine0_req_rdata_valid
- connect \Y $or$ls180.v:1927$126_Y
+ connect \Y $or$ls180.v:1940$127_Y
end
- attribute \src "ls180.v:1928.39-1928.136"
- cell $or $or$ls180.v:1928$127
+ attribute \src "ls180.v:1941.39-1941.136"
+ cell $or $or$ls180.v:1941$128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine0_cmd_buffer_source_valid
- connect \Y $or$ls180.v:1928$127_Y
+ connect \Y $or$ls180.v:1941$128_Y
end
- attribute \src "ls180.v:1936.40-1936.155"
- cell $or $or$ls180.v:1936$131
+ attribute \src "ls180.v:1949.40-1949.155"
+ cell $or $or$ls180.v:1949$132
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:1936$130_Y
+ connect \A $sshl$ls180.v:1949$131_Y
connect \B { 4'0000 \sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:1936$131_Y
+ connect \Y $or$ls180.v:1949$132_Y
end
- attribute \src "ls180.v:1973.117-1973.225"
- cell $or $or$ls180.v:1973$144
+ attribute \src "ls180.v:1986.117-1986.225"
+ cell $or $or$ls180.v:1986$145
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
connect \B \sdram_bankmachine0_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:1973$144_Y
+ connect \Y $or$ls180.v:1986$145_Y
end
- attribute \src "ls180.v:1979.52-1979.142"
- cell $or $or$ls180.v:1979$150
+ attribute \src "ls180.v:1992.52-1992.142"
+ cell $or $or$ls180.v:1992$151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:1979$149_Y
+ connect \A $not$ls180.v:1992$150_Y
connect \B \sdram_bankmachine0_cmd_buffer_source_ready
- connect \Y $or$ls180.v:1979$150_Y
+ connect \Y $or$ls180.v:1992$151_Y
end
- attribute \src "ls180.v:2084.54-2084.125"
- cell $or $or$ls180.v:2084$156
+ attribute \src "ls180.v:2097.54-2097.125"
+ cell $or $or$ls180.v:2097$157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_req_wdata_ready
connect \B \sdram_bankmachine1_req_rdata_valid
- connect \Y $or$ls180.v:2084$156_Y
+ connect \Y $or$ls180.v:2097$157_Y
end
- attribute \src "ls180.v:2085.39-2085.136"
- cell $or $or$ls180.v:2085$157
+ attribute \src "ls180.v:2098.39-2098.136"
+ cell $or $or$ls180.v:2098$158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine1_cmd_buffer_source_valid
- connect \Y $or$ls180.v:2085$157_Y
+ connect \Y $or$ls180.v:2098$158_Y
end
- attribute \src "ls180.v:2093.40-2093.155"
- cell $or $or$ls180.v:2093$161
+ attribute \src "ls180.v:2106.40-2106.155"
+ cell $or $or$ls180.v:2106$162
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:2093$160_Y
+ connect \A $sshl$ls180.v:2106$161_Y
connect \B { 4'0000 \sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:2093$161_Y
+ connect \Y $or$ls180.v:2106$162_Y
end
- attribute \src "ls180.v:2130.117-2130.225"
- cell $or $or$ls180.v:2130$174
+ attribute \src "ls180.v:2143.117-2143.225"
+ cell $or $or$ls180.v:2143$175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
connect \B \sdram_bankmachine1_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:2130$174_Y
+ connect \Y $or$ls180.v:2143$175_Y
end
- attribute \src "ls180.v:2136.52-2136.142"
- cell $or $or$ls180.v:2136$180
+ attribute \src "ls180.v:2149.52-2149.142"
+ cell $or $or$ls180.v:2149$181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2136$179_Y
+ connect \A $not$ls180.v:2149$180_Y
connect \B \sdram_bankmachine1_cmd_buffer_source_ready
- connect \Y $or$ls180.v:2136$180_Y
+ connect \Y $or$ls180.v:2149$181_Y
end
- attribute \src "ls180.v:2241.54-2241.125"
- cell $or $or$ls180.v:2241$186
+ attribute \src "ls180.v:2254.54-2254.125"
+ cell $or $or$ls180.v:2254$187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_req_wdata_ready
connect \B \sdram_bankmachine2_req_rdata_valid
- connect \Y $or$ls180.v:2241$186_Y
+ connect \Y $or$ls180.v:2254$187_Y
end
- attribute \src "ls180.v:2242.39-2242.136"
- cell $or $or$ls180.v:2242$187
+ attribute \src "ls180.v:2255.39-2255.136"
+ cell $or $or$ls180.v:2255$188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine2_cmd_buffer_source_valid
- connect \Y $or$ls180.v:2242$187_Y
+ connect \Y $or$ls180.v:2255$188_Y
end
- attribute \src "ls180.v:2250.40-2250.155"
- cell $or $or$ls180.v:2250$191
+ attribute \src "ls180.v:2263.40-2263.155"
+ cell $or $or$ls180.v:2263$192
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:2250$190_Y
+ connect \A $sshl$ls180.v:2263$191_Y
connect \B { 4'0000 \sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:2250$191_Y
+ connect \Y $or$ls180.v:2263$192_Y
end
- attribute \src "ls180.v:2287.117-2287.225"
- cell $or $or$ls180.v:2287$204
+ attribute \src "ls180.v:2300.117-2300.225"
+ cell $or $or$ls180.v:2300$205
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
connect \B \sdram_bankmachine2_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:2287$204_Y
+ connect \Y $or$ls180.v:2300$205_Y
end
- attribute \src "ls180.v:2293.52-2293.142"
- cell $or $or$ls180.v:2293$210
+ attribute \src "ls180.v:2306.52-2306.142"
+ cell $or $or$ls180.v:2306$211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2293$209_Y
+ connect \A $not$ls180.v:2306$210_Y
connect \B \sdram_bankmachine2_cmd_buffer_source_ready
- connect \Y $or$ls180.v:2293$210_Y
+ connect \Y $or$ls180.v:2306$211_Y
end
- attribute \src "ls180.v:2398.54-2398.125"
- cell $or $or$ls180.v:2398$216
+ attribute \src "ls180.v:2411.54-2411.125"
+ cell $or $or$ls180.v:2411$217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_req_wdata_ready
connect \B \sdram_bankmachine3_req_rdata_valid
- connect \Y $or$ls180.v:2398$216_Y
+ connect \Y $or$ls180.v:2411$217_Y
end
- attribute \src "ls180.v:2399.39-2399.136"
- cell $or $or$ls180.v:2399$217
+ attribute \src "ls180.v:2412.39-2412.136"
+ cell $or $or$ls180.v:2412$218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid
connect \B \sdram_bankmachine3_cmd_buffer_source_valid
- connect \Y $or$ls180.v:2399$217_Y
+ connect \Y $or$ls180.v:2412$218_Y
end
- attribute \src "ls180.v:2407.40-2407.155"
- cell $or $or$ls180.v:2407$221
+ attribute \src "ls180.v:2420.40-2420.155"
+ cell $or $or$ls180.v:2420$222
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \B_WIDTH 13
parameter \Y_WIDTH 13
- connect \A $sshl$ls180.v:2407$220_Y
+ connect \A $sshl$ls180.v:2420$221_Y
connect \B { 4'0000 \sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] }
- connect \Y $or$ls180.v:2407$221_Y
+ connect \Y $or$ls180.v:2420$222_Y
end
- attribute \src "ls180.v:2444.117-2444.225"
- cell $or $or$ls180.v:2444$234
+ attribute \src "ls180.v:2457.117-2457.225"
+ cell $or $or$ls180.v:2457$235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
connect \B \sdram_bankmachine3_cmd_buffer_lookahead_replace
- connect \Y $or$ls180.v:2444$234_Y
+ connect \Y $or$ls180.v:2457$235_Y
end
- attribute \src "ls180.v:2450.52-2450.142"
- cell $or $or$ls180.v:2450$240
+ attribute \src "ls180.v:2463.52-2463.142"
+ cell $or $or$ls180.v:2463$241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2450$239_Y
+ connect \A $not$ls180.v:2463$240_Y
connect \B \sdram_bankmachine3_cmd_buffer_source_ready
- connect \Y $or$ls180.v:2450$240_Y
+ connect \Y $or$ls180.v:2463$241_Y
end
- attribute \src "ls180.v:2549.92-2549.168"
- cell $or $or$ls180.v:2549$260
+ attribute \src "ls180.v:2562.92-2562.168"
+ cell $or $or$ls180.v:2562$261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_payload_is_write
connect \B \sdram_choose_req_cmd_payload_is_read
- connect \Y $or$ls180.v:2549$260_Y
+ connect \Y $or$ls180.v:2562$261_Y
end
- attribute \src "ls180.v:2552.34-2552.179"
- cell $or $or$ls180.v:2552$266
+ attribute \src "ls180.v:2565.34-2565.179"
+ cell $or $or$ls180.v:2565$267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2552$264_Y
- connect \B $and$ls180.v:2552$265_Y
- connect \Y $or$ls180.v:2552$266_Y
+ connect \A $and$ls180.v:2565$265_Y
+ connect \B $and$ls180.v:2565$266_Y
+ connect \Y $or$ls180.v:2565$267_Y
end
- attribute \src "ls180.v:2552.33-2552.254"
- cell $or $or$ls180.v:2552$268
+ attribute \src "ls180.v:2565.33-2565.254"
+ cell $or $or$ls180.v:2565$269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2552$266_Y
- connect \B $and$ls180.v:2552$267_Y
- connect \Y $or$ls180.v:2552$268_Y
+ connect \A $or$ls180.v:2565$267_Y
+ connect \B $and$ls180.v:2565$268_Y
+ connect \Y $or$ls180.v:2565$269_Y
end
- attribute \src "ls180.v:2552.32-2552.329"
- cell $or $or$ls180.v:2552$270
+ attribute \src "ls180.v:2565.32-2565.329"
+ cell $or $or$ls180.v:2565$271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2552$268_Y
- connect \B $and$ls180.v:2552$269_Y
- connect \Y $or$ls180.v:2552$270_Y
+ connect \A $or$ls180.v:2565$269_Y
+ connect \B $and$ls180.v:2565$270_Y
+ connect \Y $or$ls180.v:2565$271_Y
end
- attribute \src "ls180.v:2553.35-2553.182"
- cell $or $or$ls180.v:2553$273
+ attribute \src "ls180.v:2566.35-2566.182"
+ cell $or $or$ls180.v:2566$274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2553$271_Y
- connect \B $and$ls180.v:2553$272_Y
- connect \Y $or$ls180.v:2553$273_Y
+ connect \A $and$ls180.v:2566$272_Y
+ connect \B $and$ls180.v:2566$273_Y
+ connect \Y $or$ls180.v:2566$274_Y
end
- attribute \src "ls180.v:2553.34-2553.258"
- cell $or $or$ls180.v:2553$275
+ attribute \src "ls180.v:2566.34-2566.258"
+ cell $or $or$ls180.v:2566$276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2553$273_Y
- connect \B $and$ls180.v:2553$274_Y
- connect \Y $or$ls180.v:2553$275_Y
+ connect \A $or$ls180.v:2566$274_Y
+ connect \B $and$ls180.v:2566$275_Y
+ connect \Y $or$ls180.v:2566$276_Y
end
- attribute \src "ls180.v:2553.33-2553.334"
- cell $or $or$ls180.v:2553$277
+ attribute \src "ls180.v:2566.33-2566.334"
+ cell $or $or$ls180.v:2566$278
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2553$275_Y
- connect \B $and$ls180.v:2553$276_Y
- connect \Y $or$ls180.v:2553$277_Y
+ connect \A $or$ls180.v:2566$276_Y
+ connect \B $and$ls180.v:2566$277_Y
+ connect \Y $or$ls180.v:2566$278_Y
end
- attribute \src "ls180.v:2566.138-2566.292"
- cell $or $or$ls180.v:2566$291
+ attribute \src "ls180.v:2579.138-2579.292"
+ cell $or $or$ls180.v:2579$292
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2566$290_Y
+ connect \A $not$ls180.v:2579$291_Y
connect \B \sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:2566$291_Y
+ connect \Y $or$ls180.v:2579$292_Y
end
- attribute \src "ls180.v:2566.65-2566.446"
- cell $or $or$ls180.v:2566$296
+ attribute \src "ls180.v:2579.65-2579.446"
+ cell $or $or$ls180.v:2579$297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2566$292_Y
- connect \B $and$ls180.v:2566$295_Y
- connect \Y $or$ls180.v:2566$296_Y
+ connect \A $and$ls180.v:2579$293_Y
+ connect \B $and$ls180.v:2579$296_Y
+ connect \Y $or$ls180.v:2579$297_Y
end
- attribute \src "ls180.v:2567.138-2567.292"
- cell $or $or$ls180.v:2567$304
+ attribute \src "ls180.v:2580.138-2580.292"
+ cell $or $or$ls180.v:2580$305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2567$303_Y
+ connect \A $not$ls180.v:2580$304_Y
connect \B \sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:2567$304_Y
+ connect \Y $or$ls180.v:2580$305_Y
end
- attribute \src "ls180.v:2567.65-2567.446"
- cell $or $or$ls180.v:2567$309
+ attribute \src "ls180.v:2580.65-2580.446"
+ cell $or $or$ls180.v:2580$310
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2567$305_Y
- connect \B $and$ls180.v:2567$308_Y
- connect \Y $or$ls180.v:2567$309_Y
+ connect \A $and$ls180.v:2580$306_Y
+ connect \B $and$ls180.v:2580$309_Y
+ connect \Y $or$ls180.v:2580$310_Y
end
- attribute \src "ls180.v:2568.138-2568.292"
- cell $or $or$ls180.v:2568$317
+ attribute \src "ls180.v:2581.138-2581.292"
+ cell $or $or$ls180.v:2581$318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2568$316_Y
+ connect \A $not$ls180.v:2581$317_Y
connect \B \sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:2568$317_Y
+ connect \Y $or$ls180.v:2581$318_Y
end
- attribute \src "ls180.v:2568.65-2568.446"
- cell $or $or$ls180.v:2568$322
+ attribute \src "ls180.v:2581.65-2581.446"
+ cell $or $or$ls180.v:2581$323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2568$318_Y
- connect \B $and$ls180.v:2568$321_Y
- connect \Y $or$ls180.v:2568$322_Y
+ connect \A $and$ls180.v:2581$319_Y
+ connect \B $and$ls180.v:2581$322_Y
+ connect \Y $or$ls180.v:2581$323_Y
end
- attribute \src "ls180.v:2569.138-2569.292"
- cell $or $or$ls180.v:2569$330
+ attribute \src "ls180.v:2582.138-2582.292"
+ cell $or $or$ls180.v:2582$331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2569$329_Y
+ connect \A $not$ls180.v:2582$330_Y
connect \B \sdram_choose_cmd_want_activates
- connect \Y $or$ls180.v:2569$330_Y
+ connect \Y $or$ls180.v:2582$331_Y
end
- attribute \src "ls180.v:2569.65-2569.446"
- cell $or $or$ls180.v:2569$335
+ attribute \src "ls180.v:2582.65-2582.446"
+ cell $or $or$ls180.v:2582$336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2569$331_Y
- connect \B $and$ls180.v:2569$334_Y
- connect \Y $or$ls180.v:2569$335_Y
+ connect \A $and$ls180.v:2582$332_Y
+ connect \B $and$ls180.v:2582$335_Y
+ connect \Y $or$ls180.v:2582$336_Y
end
- attribute \src "ls180.v:2596.31-2596.89"
- cell $or $or$ls180.v:2596$341
+ attribute \src "ls180.v:2609.31-2609.89"
+ cell $or $or$ls180.v:2609$342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_cmd_cmd_ready
- connect \B $not$ls180.v:2596$340_Y
- connect \Y $or$ls180.v:2596$341_Y
+ connect \B $not$ls180.v:2609$341_Y
+ connect \Y $or$ls180.v:2609$342_Y
end
- attribute \src "ls180.v:2599.138-2599.292"
- cell $or $or$ls180.v:2599$349
+ attribute \src "ls180.v:2612.138-2612.292"
+ cell $or $or$ls180.v:2612$350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2599$348_Y
+ connect \A $not$ls180.v:2612$349_Y
connect \B \sdram_choose_req_want_activates
- connect \Y $or$ls180.v:2599$349_Y
+ connect \Y $or$ls180.v:2612$350_Y
end
- attribute \src "ls180.v:2599.65-2599.446"
- cell $or $or$ls180.v:2599$354
+ attribute \src "ls180.v:2612.65-2612.446"
+ cell $or $or$ls180.v:2612$355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2599$350_Y
- connect \B $and$ls180.v:2599$353_Y
- connect \Y $or$ls180.v:2599$354_Y
+ connect \A $and$ls180.v:2612$351_Y
+ connect \B $and$ls180.v:2612$354_Y
+ connect \Y $or$ls180.v:2612$355_Y
end
- attribute \src "ls180.v:2600.138-2600.292"
- cell $or $or$ls180.v:2600$362
+ attribute \src "ls180.v:2613.138-2613.292"
+ cell $or $or$ls180.v:2613$363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2600$361_Y
+ connect \A $not$ls180.v:2613$362_Y
connect \B \sdram_choose_req_want_activates
- connect \Y $or$ls180.v:2600$362_Y
+ connect \Y $or$ls180.v:2613$363_Y
end
- attribute \src "ls180.v:2600.65-2600.446"
- cell $or $or$ls180.v:2600$367
+ attribute \src "ls180.v:2613.65-2613.446"
+ cell $or $or$ls180.v:2613$368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2600$363_Y
- connect \B $and$ls180.v:2600$366_Y
- connect \Y $or$ls180.v:2600$367_Y
+ connect \A $and$ls180.v:2613$364_Y
+ connect \B $and$ls180.v:2613$367_Y
+ connect \Y $or$ls180.v:2613$368_Y
end
- attribute \src "ls180.v:2601.138-2601.292"
- cell $or $or$ls180.v:2601$375
+ attribute \src "ls180.v:2614.138-2614.292"
+ cell $or $or$ls180.v:2614$376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2601$374_Y
+ connect \A $not$ls180.v:2614$375_Y
connect \B \sdram_choose_req_want_activates
- connect \Y $or$ls180.v:2601$375_Y
+ connect \Y $or$ls180.v:2614$376_Y
end
- attribute \src "ls180.v:2601.65-2601.446"
- cell $or $or$ls180.v:2601$380
+ attribute \src "ls180.v:2614.65-2614.446"
+ cell $or $or$ls180.v:2614$381
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2601$376_Y
- connect \B $and$ls180.v:2601$379_Y
- connect \Y $or$ls180.v:2601$380_Y
+ connect \A $and$ls180.v:2614$377_Y
+ connect \B $and$ls180.v:2614$380_Y
+ connect \Y $or$ls180.v:2614$381_Y
end
- attribute \src "ls180.v:2602.138-2602.292"
- cell $or $or$ls180.v:2602$388
+ attribute \src "ls180.v:2615.138-2615.292"
+ cell $or $or$ls180.v:2615$389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2602$387_Y
+ connect \A $not$ls180.v:2615$388_Y
connect \B \sdram_choose_req_want_activates
- connect \Y $or$ls180.v:2602$388_Y
+ connect \Y $or$ls180.v:2615$389_Y
end
- attribute \src "ls180.v:2602.65-2602.446"
- cell $or $or$ls180.v:2602$393
+ attribute \src "ls180.v:2615.65-2615.446"
+ cell $or $or$ls180.v:2615$394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2602$389_Y
- connect \B $and$ls180.v:2602$392_Y
- connect \Y $or$ls180.v:2602$393_Y
+ connect \A $and$ls180.v:2615$390_Y
+ connect \B $and$ls180.v:2615$393_Y
+ connect \Y $or$ls180.v:2615$394_Y
end
- attribute \src "ls180.v:2665.31-2665.89"
- cell $or $or$ls180.v:2665$427
+ attribute \src "ls180.v:2678.31-2678.89"
+ cell $or $or$ls180.v:2678$428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \sdram_choose_req_cmd_ready
- connect \B $not$ls180.v:2665$426_Y
- connect \Y $or$ls180.v:2665$427_Y
+ connect \B $not$ls180.v:2678$427_Y
+ connect \Y $or$ls180.v:2678$428_Y
end
- attribute \src "ls180.v:2686.57-2686.191"
- cell $or $or$ls180.v:2686$434
+ attribute \src "ls180.v:2699.57-2699.191"
+ cell $or $or$ls180.v:2699$435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2686$433_Y
+ connect \A $not$ls180.v:2699$434_Y
connect \B \sdram_ras_allowed
- connect \Y $or$ls180.v:2686$434_Y
+ connect \Y $or$ls180.v:2699$435_Y
end
- attribute \src "ls180.v:2694.10-2694.52"
- cell $or $or$ls180.v:2694$437
+ attribute \src "ls180.v:2707.10-2707.52"
+ cell $or $or$ls180.v:2707$438
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2694$436_Y
+ connect \A $not$ls180.v:2707$437_Y
connect \B \sdram_max_time1
- connect \Y $or$ls180.v:2694$437_Y
+ connect \Y $or$ls180.v:2707$438_Y
end
- attribute \src "ls180.v:2724.57-2724.191"
- cell $or $or$ls180.v:2724$443
+ attribute \src "ls180.v:2737.57-2737.191"
+ cell $or $or$ls180.v:2737$444
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2724$442_Y
+ connect \A $not$ls180.v:2737$443_Y
connect \B \sdram_ras_allowed
- connect \Y $or$ls180.v:2724$443_Y
+ connect \Y $or$ls180.v:2737$444_Y
end
- attribute \src "ls180.v:2732.10-2732.51"
- cell $or $or$ls180.v:2732$446
+ attribute \src "ls180.v:2745.10-2745.51"
+ cell $or $or$ls180.v:2745$447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2732$445_Y
+ connect \A $not$ls180.v:2745$446_Y
connect \B \sdram_max_time0
- connect \Y $or$ls180.v:2732$446_Y
+ connect \Y $or$ls180.v:2745$447_Y
end
- attribute \src "ls180.v:2742.91-2742.185"
- cell $or $or$ls180.v:2742$450
+ attribute \src "ls180.v:2755.91-2755.185"
+ cell $or $or$ls180.v:2755$451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked0
- connect \B $and$ls180.v:2742$449_Y
- connect \Y $or$ls180.v:2742$450_Y
+ connect \B $and$ls180.v:2755$450_Y
+ connect \Y $or$ls180.v:2755$451_Y
end
- attribute \src "ls180.v:2742.90-2742.260"
- cell $or $or$ls180.v:2742$453
+ attribute \src "ls180.v:2755.90-2755.260"
+ cell $or $or$ls180.v:2755$454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2742$450_Y
- connect \B $and$ls180.v:2742$452_Y
- connect \Y $or$ls180.v:2742$453_Y
+ connect \A $or$ls180.v:2755$451_Y
+ connect \B $and$ls180.v:2755$453_Y
+ connect \Y $or$ls180.v:2755$454_Y
end
- attribute \src "ls180.v:2742.89-2742.335"
- cell $or $or$ls180.v:2742$456
+ attribute \src "ls180.v:2755.89-2755.335"
+ cell $or $or$ls180.v:2755$457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2742$453_Y
- connect \B $and$ls180.v:2742$455_Y
- connect \Y $or$ls180.v:2742$456_Y
+ connect \A $or$ls180.v:2755$454_Y
+ connect \B $and$ls180.v:2755$456_Y
+ connect \Y $or$ls180.v:2755$457_Y
end
- attribute \src "ls180.v:2747.91-2747.185"
- cell $or $or$ls180.v:2747$466
+ attribute \src "ls180.v:2760.91-2760.185"
+ cell $or $or$ls180.v:2760$467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked1
- connect \B $and$ls180.v:2747$465_Y
- connect \Y $or$ls180.v:2747$466_Y
+ connect \B $and$ls180.v:2760$466_Y
+ connect \Y $or$ls180.v:2760$467_Y
end
- attribute \src "ls180.v:2747.90-2747.260"
- cell $or $or$ls180.v:2747$469
+ attribute \src "ls180.v:2760.90-2760.260"
+ cell $or $or$ls180.v:2760$470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2747$466_Y
- connect \B $and$ls180.v:2747$468_Y
- connect \Y $or$ls180.v:2747$469_Y
+ connect \A $or$ls180.v:2760$467_Y
+ connect \B $and$ls180.v:2760$469_Y
+ connect \Y $or$ls180.v:2760$470_Y
end
- attribute \src "ls180.v:2747.89-2747.335"
- cell $or $or$ls180.v:2747$472
+ attribute \src "ls180.v:2760.89-2760.335"
+ cell $or $or$ls180.v:2760$473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2747$469_Y
- connect \B $and$ls180.v:2747$471_Y
- connect \Y $or$ls180.v:2747$472_Y
+ connect \A $or$ls180.v:2760$470_Y
+ connect \B $and$ls180.v:2760$472_Y
+ connect \Y $or$ls180.v:2760$473_Y
end
- attribute \src "ls180.v:2752.91-2752.185"
- cell $or $or$ls180.v:2752$482
+ attribute \src "ls180.v:2765.91-2765.185"
+ cell $or $or$ls180.v:2765$483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked2
- connect \B $and$ls180.v:2752$481_Y
- connect \Y $or$ls180.v:2752$482_Y
+ connect \B $and$ls180.v:2765$482_Y
+ connect \Y $or$ls180.v:2765$483_Y
end
- attribute \src "ls180.v:2752.90-2752.260"
- cell $or $or$ls180.v:2752$485
+ attribute \src "ls180.v:2765.90-2765.260"
+ cell $or $or$ls180.v:2765$486
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2752$482_Y
- connect \B $and$ls180.v:2752$484_Y
- connect \Y $or$ls180.v:2752$485_Y
+ connect \A $or$ls180.v:2765$483_Y
+ connect \B $and$ls180.v:2765$485_Y
+ connect \Y $or$ls180.v:2765$486_Y
end
- attribute \src "ls180.v:2752.89-2752.335"
- cell $or $or$ls180.v:2752$488
+ attribute \src "ls180.v:2765.89-2765.335"
+ cell $or $or$ls180.v:2765$489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2752$485_Y
- connect \B $and$ls180.v:2752$487_Y
- connect \Y $or$ls180.v:2752$488_Y
+ connect \A $or$ls180.v:2765$486_Y
+ connect \B $and$ls180.v:2765$488_Y
+ connect \Y $or$ls180.v:2765$489_Y
end
- attribute \src "ls180.v:2757.91-2757.185"
- cell $or $or$ls180.v:2757$498
+ attribute \src "ls180.v:2770.91-2770.185"
+ cell $or $or$ls180.v:2770$499
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked3
- connect \B $and$ls180.v:2757$497_Y
- connect \Y $or$ls180.v:2757$498_Y
+ connect \B $and$ls180.v:2770$498_Y
+ connect \Y $or$ls180.v:2770$499_Y
end
- attribute \src "ls180.v:2757.90-2757.260"
- cell $or $or$ls180.v:2757$501
+ attribute \src "ls180.v:2770.90-2770.260"
+ cell $or $or$ls180.v:2770$502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2757$498_Y
- connect \B $and$ls180.v:2757$500_Y
- connect \Y $or$ls180.v:2757$501_Y
+ connect \A $or$ls180.v:2770$499_Y
+ connect \B $and$ls180.v:2770$501_Y
+ connect \Y $or$ls180.v:2770$502_Y
end
- attribute \src "ls180.v:2757.89-2757.335"
- cell $or $or$ls180.v:2757$504
+ attribute \src "ls180.v:2770.89-2770.335"
+ cell $or $or$ls180.v:2770$505
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2757$501_Y
- connect \B $and$ls180.v:2757$503_Y
- connect \Y $or$ls180.v:2757$504_Y
+ connect \A $or$ls180.v:2770$502_Y
+ connect \B $and$ls180.v:2770$504_Y
+ connect \Y $or$ls180.v:2770$505_Y
end
- attribute \src "ls180.v:2762.127-2762.221"
- cell $or $or$ls180.v:2762$515
+ attribute \src "ls180.v:2775.127-2775.221"
+ cell $or $or$ls180.v:2775$516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked0
- connect \B $and$ls180.v:2762$514_Y
- connect \Y $or$ls180.v:2762$515_Y
+ connect \B $and$ls180.v:2775$515_Y
+ connect \Y $or$ls180.v:2775$516_Y
end
- attribute \src "ls180.v:2762.126-2762.296"
- cell $or $or$ls180.v:2762$518
+ attribute \src "ls180.v:2775.126-2775.296"
+ cell $or $or$ls180.v:2775$519
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$515_Y
- connect \B $and$ls180.v:2762$517_Y
- connect \Y $or$ls180.v:2762$518_Y
+ connect \A $or$ls180.v:2775$516_Y
+ connect \B $and$ls180.v:2775$518_Y
+ connect \Y $or$ls180.v:2775$519_Y
end
- attribute \src "ls180.v:2762.125-2762.371"
- cell $or $or$ls180.v:2762$521
+ attribute \src "ls180.v:2775.125-2775.371"
+ cell $or $or$ls180.v:2775$522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$518_Y
- connect \B $and$ls180.v:2762$520_Y
- connect \Y $or$ls180.v:2762$521_Y
+ connect \A $or$ls180.v:2775$519_Y
+ connect \B $and$ls180.v:2775$521_Y
+ connect \Y $or$ls180.v:2775$522_Y
end
- attribute \src "ls180.v:2762.29-2762.406"
- cell $or $or$ls180.v:2762$526
+ attribute \src "ls180.v:2775.29-2775.406"
+ cell $or $or$ls180.v:2775$527
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:2762$525_Y
- connect \Y $or$ls180.v:2762$526_Y
+ connect \B $and$ls180.v:2775$526_Y
+ connect \Y $or$ls180.v:2775$527_Y
end
- attribute \src "ls180.v:2762.501-2762.595"
- cell $or $or$ls180.v:2762$531
+ attribute \src "ls180.v:2775.501-2775.595"
+ cell $or $or$ls180.v:2775$532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked1
- connect \B $and$ls180.v:2762$530_Y
- connect \Y $or$ls180.v:2762$531_Y
+ connect \B $and$ls180.v:2775$531_Y
+ connect \Y $or$ls180.v:2775$532_Y
end
- attribute \src "ls180.v:2762.500-2762.670"
- cell $or $or$ls180.v:2762$534
+ attribute \src "ls180.v:2775.500-2775.670"
+ cell $or $or$ls180.v:2775$535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$531_Y
- connect \B $and$ls180.v:2762$533_Y
- connect \Y $or$ls180.v:2762$534_Y
+ connect \A $or$ls180.v:2775$532_Y
+ connect \B $and$ls180.v:2775$534_Y
+ connect \Y $or$ls180.v:2775$535_Y
end
- attribute \src "ls180.v:2762.499-2762.745"
- cell $or $or$ls180.v:2762$537
+ attribute \src "ls180.v:2775.499-2775.745"
+ cell $or $or$ls180.v:2775$538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$534_Y
- connect \B $and$ls180.v:2762$536_Y
- connect \Y $or$ls180.v:2762$537_Y
+ connect \A $or$ls180.v:2775$535_Y
+ connect \B $and$ls180.v:2775$537_Y
+ connect \Y $or$ls180.v:2775$538_Y
end
- attribute \src "ls180.v:2762.28-2762.780"
- cell $or $or$ls180.v:2762$542
+ attribute \src "ls180.v:2775.28-2775.780"
+ cell $or $or$ls180.v:2775$543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$526_Y
- connect \B $and$ls180.v:2762$541_Y
- connect \Y $or$ls180.v:2762$542_Y
+ connect \A $or$ls180.v:2775$527_Y
+ connect \B $and$ls180.v:2775$542_Y
+ connect \Y $or$ls180.v:2775$543_Y
end
- attribute \src "ls180.v:2762.875-2762.969"
- cell $or $or$ls180.v:2762$547
+ attribute \src "ls180.v:2775.875-2775.969"
+ cell $or $or$ls180.v:2775$548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked2
- connect \B $and$ls180.v:2762$546_Y
- connect \Y $or$ls180.v:2762$547_Y
+ connect \B $and$ls180.v:2775$547_Y
+ connect \Y $or$ls180.v:2775$548_Y
end
- attribute \src "ls180.v:2762.874-2762.1044"
- cell $or $or$ls180.v:2762$550
+ attribute \src "ls180.v:2775.874-2775.1044"
+ cell $or $or$ls180.v:2775$551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$547_Y
- connect \B $and$ls180.v:2762$549_Y
- connect \Y $or$ls180.v:2762$550_Y
+ connect \A $or$ls180.v:2775$548_Y
+ connect \B $and$ls180.v:2775$550_Y
+ connect \Y $or$ls180.v:2775$551_Y
end
- attribute \src "ls180.v:2762.873-2762.1119"
- cell $or $or$ls180.v:2762$553
+ attribute \src "ls180.v:2775.873-2775.1119"
+ cell $or $or$ls180.v:2775$554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$550_Y
- connect \B $and$ls180.v:2762$552_Y
- connect \Y $or$ls180.v:2762$553_Y
+ connect \A $or$ls180.v:2775$551_Y
+ connect \B $and$ls180.v:2775$553_Y
+ connect \Y $or$ls180.v:2775$554_Y
end
- attribute \src "ls180.v:2762.27-2762.1154"
- cell $or $or$ls180.v:2762$558
+ attribute \src "ls180.v:2775.27-2775.1154"
+ cell $or $or$ls180.v:2775$559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$542_Y
- connect \B $and$ls180.v:2762$557_Y
- connect \Y $or$ls180.v:2762$558_Y
+ connect \A $or$ls180.v:2775$543_Y
+ connect \B $and$ls180.v:2775$558_Y
+ connect \Y $or$ls180.v:2775$559_Y
end
- attribute \src "ls180.v:2762.1249-2762.1343"
- cell $or $or$ls180.v:2762$563
+ attribute \src "ls180.v:2775.1249-2775.1343"
+ cell $or $or$ls180.v:2775$564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked3
- connect \B $and$ls180.v:2762$562_Y
- connect \Y $or$ls180.v:2762$563_Y
+ connect \B $and$ls180.v:2775$563_Y
+ connect \Y $or$ls180.v:2775$564_Y
end
- attribute \src "ls180.v:2762.1248-2762.1418"
- cell $or $or$ls180.v:2762$566
+ attribute \src "ls180.v:2775.1248-2775.1418"
+ cell $or $or$ls180.v:2775$567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$563_Y
- connect \B $and$ls180.v:2762$565_Y
- connect \Y $or$ls180.v:2762$566_Y
+ connect \A $or$ls180.v:2775$564_Y
+ connect \B $and$ls180.v:2775$566_Y
+ connect \Y $or$ls180.v:2775$567_Y
end
- attribute \src "ls180.v:2762.1247-2762.1493"
- cell $or $or$ls180.v:2762$569
+ attribute \src "ls180.v:2775.1247-2775.1493"
+ cell $or $or$ls180.v:2775$570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$566_Y
- connect \B $and$ls180.v:2762$568_Y
- connect \Y $or$ls180.v:2762$569_Y
+ connect \A $or$ls180.v:2775$567_Y
+ connect \B $and$ls180.v:2775$569_Y
+ connect \Y $or$ls180.v:2775$570_Y
end
- attribute \src "ls180.v:2762.26-2762.1528"
- cell $or $or$ls180.v:2762$574
+ attribute \src "ls180.v:2775.26-2775.1528"
+ cell $or $or$ls180.v:2775$575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:2762$558_Y
- connect \B $and$ls180.v:2762$573_Y
- connect \Y $or$ls180.v:2762$574_Y
+ connect \A $or$ls180.v:2775$559_Y
+ connect \B $and$ls180.v:2775$574_Y
+ connect \Y $or$ls180.v:2775$575_Y
end
- attribute \src "ls180.v:2825.10-2825.42"
- cell $or $or$ls180.v:2825$583
+ attribute \src "ls180.v:2838.10-2838.42"
+ cell $or $or$ls180.v:2838$584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \litedram_wb_ack
connect \B \converter_skip
- connect \Y $or$ls180.v:2825$583_Y
+ connect \Y $or$ls180.v:2838$584_Y
end
- attribute \src "ls180.v:2852.30-2852.59"
- cell $or $or$ls180.v:2852$593
+ attribute \src "ls180.v:2865.30-2865.59"
+ cell $or $or$ls180.v:2865$594
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_valid
connect \B \cmd_consumed
- connect \Y $or$ls180.v:2852$593_Y
+ connect \Y $or$ls180.v:2865$594_Y
end
- attribute \src "ls180.v:2853.29-2853.58"
- cell $or $or$ls180.v:2853$597
+ attribute \src "ls180.v:2866.29-2866.58"
+ cell $or $or$ls180.v:2866$598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \port_cmd_valid
connect \B \cmd_consumed
- connect \Y $or$ls180.v:2853$597_Y
+ connect \Y $or$ls180.v:2866$598_Y
end
- attribute \src "ls180.v:2854.38-2854.100"
- cell $or $or$ls180.v:2854$603
+ attribute \src "ls180.v:2867.38-2867.100"
+ cell $or $or$ls180.v:2867$604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2854$600_Y
- connect \B $and$ls180.v:2854$602_Y
- connect \Y $or$ls180.v:2854$603_Y
+ connect \A $and$ls180.v:2867$601_Y
+ connect \B $and$ls180.v:2867$603_Y
+ connect \Y $or$ls180.v:2867$604_Y
end
- attribute \src "ls180.v:2855.19-2855.67"
- cell $or $or$ls180.v:2855$606
+ attribute \src "ls180.v:2868.19-2868.67"
+ cell $or $or$ls180.v:2868$607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2855$605_Y
+ connect \A $and$ls180.v:2868$606_Y
connect \B \cmd_consumed
- connect \Y $or$ls180.v:2855$606_Y
+ connect \Y $or$ls180.v:2868$607_Y
end
- attribute \src "ls180.v:2856.21-2856.75"
- cell $or $or$ls180.v:2856$608
+ attribute \src "ls180.v:2869.21-2869.75"
+ cell $or $or$ls180.v:2869$609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2856$607_Y
+ connect \A $and$ls180.v:2869$608_Y
connect \B \wdata_consumed
- connect \Y $or$ls180.v:2856$608_Y
+ connect \Y $or$ls180.v:2869$609_Y
end
- attribute \src "ls180.v:2886.32-2886.59"
- cell $or $or$ls180.v:2886$616
+ attribute \src "ls180.v:2899.32-2899.59"
+ cell $or $or$ls180.v:2899$617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \rx_clear
- connect \B $and$ls180.v:2886$615_Y
- connect \Y $or$ls180.v:2886$616_Y
+ connect \B $and$ls180.v:2899$616_Y
+ connect \Y $or$ls180.v:2899$617_Y
end
- attribute \src "ls180.v:2910.15-2910.124"
- cell $or $or$ls180.v:2910$626
+ attribute \src "ls180.v:2923.15-2923.124"
+ cell $or $or$ls180.v:2923$627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $and$ls180.v:2910$624_Y
- connect \B $and$ls180.v:2910$625_Y
- connect \Y $or$ls180.v:2910$626_Y
+ connect \A $and$ls180.v:2923$625_Y
+ connect \B $and$ls180.v:2923$626_Y
+ connect \Y $or$ls180.v:2923$627_Y
end
- attribute \src "ls180.v:2925.60-2925.92"
- cell $or $or$ls180.v:2925$628
+ attribute \src "ls180.v:2938.60-2938.92"
+ cell $or $or$ls180.v:2938$629
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2925$627_Y
+ connect \A $not$ls180.v:2938$628_Y
connect \B \tx_fifo_re
- connect \Y $or$ls180.v:2925$628_Y
+ connect \Y $or$ls180.v:2938$629_Y
end
- attribute \src "ls180.v:2936.52-2936.95"
- cell $or $or$ls180.v:2936$633
+ attribute \src "ls180.v:2949.52-2949.95"
+ cell $or $or$ls180.v:2949$634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \tx_fifo_syncfifo_writable
connect \B \tx_fifo_replace
- connect \Y $or$ls180.v:2936$633_Y
+ connect \Y $or$ls180.v:2949$634_Y
end
- attribute \src "ls180.v:2955.60-2955.92"
- cell $or $or$ls180.v:2955$639
+ attribute \src "ls180.v:2968.60-2968.92"
+ cell $or $or$ls180.v:2968$640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:2955$638_Y
+ connect \A $not$ls180.v:2968$639_Y
connect \B \rx_fifo_re
- connect \Y $or$ls180.v:2955$639_Y
+ connect \Y $or$ls180.v:2968$640_Y
end
- attribute \src "ls180.v:2966.52-2966.95"
- cell $or $or$ls180.v:2966$644
+ attribute \src "ls180.v:2979.52-2979.95"
+ cell $or $or$ls180.v:2979$645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rx_fifo_syncfifo_writable
connect \B \rx_fifo_replace
- connect \Y $or$ls180.v:2966$644_Y
+ connect \Y $or$ls180.v:2979$645_Y
end
- attribute \src "ls180.v:3149.38-3149.83"
- cell $or $or$ls180.v:3149$682
+ attribute \src "ls180.v:3162.38-3162.83"
+ cell $or $or$ls180.v:3162$683
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_err
connect \B \ram_bus_ram_bus_err
- connect \Y $or$ls180.v:3149$682_Y
+ connect \Y $or$ls180.v:3162$683_Y
end
- attribute \src "ls180.v:3149.37-3149.121"
- cell $or $or$ls180.v:3149$683
+ attribute \src "ls180.v:3162.37-3162.121"
+ cell $or $or$ls180.v:3162$684
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3149$682_Y
+ connect \A $or$ls180.v:3162$683_Y
connect \B \interface0_converted_interface_err
- connect \Y $or$ls180.v:3149$683_Y
+ connect \Y $or$ls180.v:3162$684_Y
end
- attribute \src "ls180.v:3149.36-3149.159"
- cell $or $or$ls180.v:3149$684
+ attribute \src "ls180.v:3162.36-3162.159"
+ cell $or $or$ls180.v:3162$685
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3149$683_Y
+ connect \A $or$ls180.v:3162$684_Y
connect \B \interface1_converted_interface_err
- connect \Y $or$ls180.v:3149$684_Y
+ connect \Y $or$ls180.v:3162$685_Y
end
- attribute \src "ls180.v:3149.35-3149.200"
- cell $or $or$ls180.v:3149$685
+ attribute \src "ls180.v:3162.35-3162.200"
+ cell $or $or$ls180.v:3162$686
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3149$684_Y
+ connect \A $or$ls180.v:3162$685_Y
connect \B \socbushandler_converted_interface_err
- connect \Y $or$ls180.v:3149$685_Y
+ connect \Y $or$ls180.v:3162$686_Y
end
- attribute \src "ls180.v:3149.34-3149.251"
- cell $or $or$ls180.v:3149$686
+ attribute \src "ls180.v:3162.34-3162.251"
+ cell $or $or$ls180.v:3162$687
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3149$685_Y
+ connect \A $or$ls180.v:3162$686_Y
connect \B \libresocsim_libresocsim_converted_interface_err
- connect \Y $or$ls180.v:3149$686_Y
+ connect \Y $or$ls180.v:3162$687_Y
end
- attribute \src "ls180.v:3155.33-3155.78"
- cell $or $or$ls180.v:3155$691
+ attribute \src "ls180.v:3168.33-3168.78"
+ cell $or $or$ls180.v:3168$692
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_ram_bus_ack
connect \B \ram_bus_ram_bus_ack
- connect \Y $or$ls180.v:3155$691_Y
+ connect \Y $or$ls180.v:3168$692_Y
end
- attribute \src "ls180.v:3155.32-3155.116"
- cell $or $or$ls180.v:3155$692
+ attribute \src "ls180.v:3168.32-3168.116"
+ cell $or $or$ls180.v:3168$693
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3155$691_Y
+ connect \A $or$ls180.v:3168$692_Y
connect \B \interface0_converted_interface_ack
- connect \Y $or$ls180.v:3155$692_Y
+ connect \Y $or$ls180.v:3168$693_Y
end
- attribute \src "ls180.v:3155.31-3155.154"
- cell $or $or$ls180.v:3155$693
+ attribute \src "ls180.v:3168.31-3168.154"
+ cell $or $or$ls180.v:3168$694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3155$692_Y
+ connect \A $or$ls180.v:3168$693_Y
connect \B \interface1_converted_interface_ack
- connect \Y $or$ls180.v:3155$693_Y
+ connect \Y $or$ls180.v:3168$694_Y
end
- attribute \src "ls180.v:3155.30-3155.195"
- cell $or $or$ls180.v:3155$694
+ attribute \src "ls180.v:3168.30-3168.195"
+ cell $or $or$ls180.v:3168$695
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3155$693_Y
+ connect \A $or$ls180.v:3168$694_Y
connect \B \socbushandler_converted_interface_ack
- connect \Y $or$ls180.v:3155$694_Y
+ connect \Y $or$ls180.v:3168$695_Y
end
- attribute \src "ls180.v:3155.29-3155.246"
- cell $or $or$ls180.v:3155$695
+ attribute \src "ls180.v:3168.29-3168.246"
+ cell $or $or$ls180.v:3168$696
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3155$694_Y
+ connect \A $or$ls180.v:3168$695_Y
connect \B \libresocsim_libresocsim_converted_interface_ack
- connect \Y $or$ls180.v:3155$695_Y
+ connect \Y $or$ls180.v:3168$696_Y
end
- attribute \src "ls180.v:3156.35-3156.158"
- cell $or $or$ls180.v:3156$698
+ attribute \src "ls180.v:3169.35-3169.158"
+ cell $or $or$ls180.v:3169$699
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $and$ls180.v:3156$696_Y
- connect \B $and$ls180.v:3156$697_Y
- connect \Y $or$ls180.v:3156$698_Y
+ connect \A $and$ls180.v:3169$697_Y
+ connect \B $and$ls180.v:3169$698_Y
+ connect \Y $or$ls180.v:3169$699_Y
end
- attribute \src "ls180.v:3156.34-3156.235"
- cell $or $or$ls180.v:3156$700
+ attribute \src "ls180.v:3169.34-3169.235"
+ cell $or $or$ls180.v:3169$701
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $or$ls180.v:3156$698_Y
- connect \B $and$ls180.v:3156$699_Y
- connect \Y $or$ls180.v:3156$700_Y
+ connect \A $or$ls180.v:3169$699_Y
+ connect \B $and$ls180.v:3169$700_Y
+ connect \Y $or$ls180.v:3169$701_Y
end
- attribute \src "ls180.v:3156.33-3156.312"
- cell $or $or$ls180.v:3156$702
+ attribute \src "ls180.v:3169.33-3169.312"
+ cell $or $or$ls180.v:3169$703
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $or$ls180.v:3156$700_Y
- connect \B $and$ls180.v:3156$701_Y
- connect \Y $or$ls180.v:3156$702_Y
+ connect \A $or$ls180.v:3169$701_Y
+ connect \B $and$ls180.v:3169$702_Y
+ connect \Y $or$ls180.v:3169$703_Y
end
- attribute \src "ls180.v:3156.32-3156.392"
- cell $or $or$ls180.v:3156$704
+ attribute \src "ls180.v:3169.32-3169.392"
+ cell $or $or$ls180.v:3169$705
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $or$ls180.v:3156$702_Y
- connect \B $and$ls180.v:3156$703_Y
- connect \Y $or$ls180.v:3156$704_Y
+ connect \A $or$ls180.v:3169$703_Y
+ connect \B $and$ls180.v:3169$704_Y
+ connect \Y $or$ls180.v:3169$705_Y
end
- attribute \src "ls180.v:3156.31-3156.482"
- cell $or $or$ls180.v:3156$706
+ attribute \src "ls180.v:3169.31-3169.482"
+ cell $or $or$ls180.v:3169$707
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $or$ls180.v:3156$704_Y
- connect \B $and$ls180.v:3156$705_Y
- connect \Y $or$ls180.v:3156$706_Y
+ connect \A $or$ls180.v:3169$705_Y
+ connect \B $and$ls180.v:3169$706_Y
+ connect \Y $or$ls180.v:3169$707_Y
end
- attribute \src "ls180.v:3436.52-3436.129"
- cell $or $or$ls180.v:3436$1108
+ attribute \src "ls180.v:3449.52-3449.129"
+ cell $or $or$ls180.v:3449$1109
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \libresocsim_interface0_bank_bus_dat_r
connect \B \libresocsim_interface1_bank_bus_dat_r
- connect \Y $or$ls180.v:3436$1108_Y
+ connect \Y $or$ls180.v:3449$1109_Y
end
- attribute \src "ls180.v:3436.51-3436.170"
- cell $or $or$ls180.v:3436$1109
+ attribute \src "ls180.v:3449.51-3449.170"
+ cell $or $or$ls180.v:3449$1110
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:3436$1108_Y
+ connect \A $or$ls180.v:3449$1109_Y
connect \B \libresocsim_interface2_bank_bus_dat_r
- connect \Y $or$ls180.v:3436$1109_Y
+ connect \Y $or$ls180.v:3449$1110_Y
end
- attribute \src "ls180.v:3436.50-3436.211"
- cell $or $or$ls180.v:3436$1110
+ attribute \src "ls180.v:3449.50-3449.211"
+ cell $or $or$ls180.v:3449$1111
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:3436$1109_Y
+ connect \A $or$ls180.v:3449$1110_Y
connect \B \libresocsim_interface3_bank_bus_dat_r
- connect \Y $or$ls180.v:3436$1110_Y
+ connect \Y $or$ls180.v:3449$1111_Y
end
- attribute \src "ls180.v:3436.49-3436.252"
- cell $or $or$ls180.v:3436$1111
+ attribute \src "ls180.v:3449.49-3449.252"
+ cell $or $or$ls180.v:3449$1112
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:3436$1110_Y
+ connect \A $or$ls180.v:3449$1111_Y
connect \B \libresocsim_interface4_bank_bus_dat_r
- connect \Y $or$ls180.v:3436$1111_Y
+ connect \Y $or$ls180.v:3449$1112_Y
end
- attribute \src "ls180.v:3436.48-3436.293"
- cell $or $or$ls180.v:3436$1112
+ attribute \src "ls180.v:3449.48-3449.293"
+ cell $or $or$ls180.v:3449$1113
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:3436$1111_Y
+ connect \A $or$ls180.v:3449$1112_Y
connect \B \libresocsim_interface5_bank_bus_dat_r
- connect \Y $or$ls180.v:3436$1112_Y
+ connect \Y $or$ls180.v:3449$1113_Y
end
- attribute \src "ls180.v:3436.47-3436.334"
- cell $or $or$ls180.v:3436$1113
+ attribute \src "ls180.v:3449.47-3449.334"
+ cell $or $or$ls180.v:3449$1114
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:3436$1112_Y
+ connect \A $or$ls180.v:3449$1113_Y
connect \B \libresocsim_interface6_bank_bus_dat_r
- connect \Y $or$ls180.v:3436$1113_Y
+ connect \Y $or$ls180.v:3449$1114_Y
end
- attribute \src "ls180.v:3436.46-3436.375"
- cell $or $or$ls180.v:3436$1114
+ attribute \src "ls180.v:3449.46-3449.375"
+ cell $or $or$ls180.v:3449$1115
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 8
- connect \A $or$ls180.v:3436$1113_Y
+ connect \A $or$ls180.v:3449$1114_Y
connect \B \libresocsim_interface7_bank_bus_dat_r
- connect \Y $or$ls180.v:3436$1114_Y
+ connect \Y $or$ls180.v:3449$1115_Y
end
- attribute \src "ls180.v:3763.72-3763.166"
- cell $or $or$ls180.v:3763$1139
+ attribute \src "ls180.v:3776.72-3776.166"
+ cell $or $or$ls180.v:3776$1140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked0
- connect \B $and$ls180.v:3763$1138_Y
- connect \Y $or$ls180.v:3763$1139_Y
+ connect \B $and$ls180.v:3776$1139_Y
+ connect \Y $or$ls180.v:3776$1140_Y
end
- attribute \src "ls180.v:3763.71-3763.241"
- cell $or $or$ls180.v:3763$1142
+ attribute \src "ls180.v:3776.71-3776.241"
+ cell $or $or$ls180.v:3776$1143
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3763$1139_Y
- connect \B $and$ls180.v:3763$1141_Y
- connect \Y $or$ls180.v:3763$1142_Y
+ connect \A $or$ls180.v:3776$1140_Y
+ connect \B $and$ls180.v:3776$1142_Y
+ connect \Y $or$ls180.v:3776$1143_Y
end
- attribute \src "ls180.v:3763.70-3763.316"
- cell $or $or$ls180.v:3763$1145
+ attribute \src "ls180.v:3776.70-3776.316"
+ cell $or $or$ls180.v:3776$1146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3763$1142_Y
- connect \B $and$ls180.v:3763$1144_Y
- connect \Y $or$ls180.v:3763$1145_Y
+ connect \A $or$ls180.v:3776$1143_Y
+ connect \B $and$ls180.v:3776$1145_Y
+ connect \Y $or$ls180.v:3776$1146_Y
end
- attribute \src "ls180.v:3787.72-3787.166"
- cell $or $or$ls180.v:3787$1155
+ attribute \src "ls180.v:3800.72-3800.166"
+ cell $or $or$ls180.v:3800$1156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked1
- connect \B $and$ls180.v:3787$1154_Y
- connect \Y $or$ls180.v:3787$1155_Y
+ connect \B $and$ls180.v:3800$1155_Y
+ connect \Y $or$ls180.v:3800$1156_Y
end
- attribute \src "ls180.v:3787.71-3787.241"
- cell $or $or$ls180.v:3787$1158
+ attribute \src "ls180.v:3800.71-3800.241"
+ cell $or $or$ls180.v:3800$1159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3787$1155_Y
- connect \B $and$ls180.v:3787$1157_Y
- connect \Y $or$ls180.v:3787$1158_Y
+ connect \A $or$ls180.v:3800$1156_Y
+ connect \B $and$ls180.v:3800$1158_Y
+ connect \Y $or$ls180.v:3800$1159_Y
end
- attribute \src "ls180.v:3787.70-3787.316"
- cell $or $or$ls180.v:3787$1161
+ attribute \src "ls180.v:3800.70-3800.316"
+ cell $or $or$ls180.v:3800$1162
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3787$1158_Y
- connect \B $and$ls180.v:3787$1160_Y
- connect \Y $or$ls180.v:3787$1161_Y
+ connect \A $or$ls180.v:3800$1159_Y
+ connect \B $and$ls180.v:3800$1161_Y
+ connect \Y $or$ls180.v:3800$1162_Y
end
- attribute \src "ls180.v:3811.72-3811.166"
- cell $or $or$ls180.v:3811$1171
+ attribute \src "ls180.v:3824.72-3824.166"
+ cell $or $or$ls180.v:3824$1172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked2
- connect \B $and$ls180.v:3811$1170_Y
- connect \Y $or$ls180.v:3811$1171_Y
+ connect \B $and$ls180.v:3824$1171_Y
+ connect \Y $or$ls180.v:3824$1172_Y
end
- attribute \src "ls180.v:3811.71-3811.241"
- cell $or $or$ls180.v:3811$1174
+ attribute \src "ls180.v:3824.71-3824.241"
+ cell $or $or$ls180.v:3824$1175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3811$1171_Y
- connect \B $and$ls180.v:3811$1173_Y
- connect \Y $or$ls180.v:3811$1174_Y
+ connect \A $or$ls180.v:3824$1172_Y
+ connect \B $and$ls180.v:3824$1174_Y
+ connect \Y $or$ls180.v:3824$1175_Y
end
- attribute \src "ls180.v:3811.70-3811.316"
- cell $or $or$ls180.v:3811$1177
+ attribute \src "ls180.v:3824.70-3824.316"
+ cell $or $or$ls180.v:3824$1178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3811$1174_Y
- connect \B $and$ls180.v:3811$1176_Y
- connect \Y $or$ls180.v:3811$1177_Y
+ connect \A $or$ls180.v:3824$1175_Y
+ connect \B $and$ls180.v:3824$1177_Y
+ connect \Y $or$ls180.v:3824$1178_Y
end
- attribute \src "ls180.v:3835.72-3835.166"
- cell $or $or$ls180.v:3835$1187
+ attribute \src "ls180.v:3848.72-3848.166"
+ cell $or $or$ls180.v:3848$1188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \subfragments_locked3
- connect \B $and$ls180.v:3835$1186_Y
- connect \Y $or$ls180.v:3835$1187_Y
+ connect \B $and$ls180.v:3848$1187_Y
+ connect \Y $or$ls180.v:3848$1188_Y
end
- attribute \src "ls180.v:3835.71-3835.241"
- cell $or $or$ls180.v:3835$1190
+ attribute \src "ls180.v:3848.71-3848.241"
+ cell $or $or$ls180.v:3848$1191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3835$1187_Y
- connect \B $and$ls180.v:3835$1189_Y
- connect \Y $or$ls180.v:3835$1190_Y
+ connect \A $or$ls180.v:3848$1188_Y
+ connect \B $and$ls180.v:3848$1190_Y
+ connect \Y $or$ls180.v:3848$1191_Y
end
- attribute \src "ls180.v:3835.70-3835.316"
- cell $or $or$ls180.v:3835$1193
+ attribute \src "ls180.v:3848.70-3848.316"
+ cell $or $or$ls180.v:3848$1194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:3835$1190_Y
- connect \B $and$ls180.v:3835$1192_Y
- connect \Y $or$ls180.v:3835$1193_Y
+ connect \A $or$ls180.v:3848$1191_Y
+ connect \B $and$ls180.v:3848$1193_Y
+ connect \Y $or$ls180.v:3848$1194_Y
end
- attribute \src "ls180.v:4288.15-4288.58"
- cell $or $or$ls180.v:4288$1247
+ attribute \src "ls180.v:4301.15-4301.58"
+ cell $or $or$ls180.v:4301$1248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [0]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4288$1247_Y
+ connect \Y $or$ls180.v:4301$1248_Y
end
- attribute \src "ls180.v:4289.15-4289.58"
- cell $or $or$ls180.v:4289$1248
+ attribute \src "ls180.v:4302.15-4302.58"
+ cell $or $or$ls180.v:4302$1249
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [1]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4289$1248_Y
+ connect \Y $or$ls180.v:4302$1249_Y
end
- attribute \src "ls180.v:4290.15-4290.58"
- cell $or $or$ls180.v:4290$1249
+ attribute \src "ls180.v:4303.15-4303.58"
+ cell $or $or$ls180.v:4303$1250
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [2]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4290$1249_Y
+ connect \Y $or$ls180.v:4303$1250_Y
end
- attribute \src "ls180.v:4291.15-4291.58"
- cell $or $or$ls180.v:4291$1250
+ attribute \src "ls180.v:4304.15-4304.58"
+ cell $or $or$ls180.v:4304$1251
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [3]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4291$1250_Y
+ connect \Y $or$ls180.v:4304$1251_Y
end
- attribute \src "ls180.v:4292.15-4292.58"
- cell $or $or$ls180.v:4292$1251
+ attribute \src "ls180.v:4305.15-4305.58"
+ cell $or $or$ls180.v:4305$1252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [4]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4292$1251_Y
+ connect \Y $or$ls180.v:4305$1252_Y
end
- attribute \src "ls180.v:4293.15-4293.58"
- cell $or $or$ls180.v:4293$1252
+ attribute \src "ls180.v:4306.15-4306.58"
+ cell $or $or$ls180.v:4306$1253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [5]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4293$1252_Y
+ connect \Y $or$ls180.v:4306$1253_Y
end
- attribute \src "ls180.v:4294.15-4294.58"
- cell $or $or$ls180.v:4294$1253
+ attribute \src "ls180.v:4307.15-4307.58"
+ cell $or $or$ls180.v:4307$1254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [6]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4294$1253_Y
+ connect \Y $or$ls180.v:4307$1254_Y
end
- attribute \src "ls180.v:4295.15-4295.58"
- cell $or $or$ls180.v:4295$1254
+ attribute \src "ls180.v:4308.15-4308.58"
+ cell $or $or$ls180.v:4308$1255
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [7]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4295$1254_Y
+ connect \Y $or$ls180.v:4308$1255_Y
end
- attribute \src "ls180.v:4296.15-4296.58"
- cell $or $or$ls180.v:4296$1255
+ attribute \src "ls180.v:4309.15-4309.58"
+ cell $or $or$ls180.v:4309$1256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [8]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4296$1255_Y
+ connect \Y $or$ls180.v:4309$1256_Y
end
- attribute \src "ls180.v:4297.15-4297.58"
- cell $or $or$ls180.v:4297$1256
+ attribute \src "ls180.v:4310.15-4310.58"
+ cell $or $or$ls180.v:4310$1257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [9]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4297$1256_Y
+ connect \Y $or$ls180.v:4310$1257_Y
end
- attribute \src "ls180.v:4298.16-4298.60"
- cell $or $or$ls180.v:4298$1257
+ attribute \src "ls180.v:4311.16-4311.60"
+ cell $or $or$ls180.v:4311$1258
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [10]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4298$1257_Y
+ connect \Y $or$ls180.v:4311$1258_Y
end
- attribute \src "ls180.v:4299.16-4299.60"
- cell $or $or$ls180.v:4299$1258
+ attribute \src "ls180.v:4312.16-4312.60"
+ cell $or $or$ls180.v:4312$1259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [11]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4299$1258_Y
+ connect \Y $or$ls180.v:4312$1259_Y
end
- attribute \src "ls180.v:4300.16-4300.60"
- cell $or $or$ls180.v:4300$1259
+ attribute \src "ls180.v:4313.16-4313.60"
+ cell $or $or$ls180.v:4313$1260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [12]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4300$1259_Y
+ connect \Y $or$ls180.v:4313$1260_Y
end
- attribute \src "ls180.v:4301.16-4301.60"
- cell $or $or$ls180.v:4301$1260
+ attribute \src "ls180.v:4314.16-4314.60"
+ cell $or $or$ls180.v:4314$1261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [13]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4301$1260_Y
+ connect \Y $or$ls180.v:4314$1261_Y
end
- attribute \src "ls180.v:4302.16-4302.60"
- cell $or $or$ls180.v:4302$1261
+ attribute \src "ls180.v:4315.16-4315.60"
+ cell $or $or$ls180.v:4315$1262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [14]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4302$1261_Y
+ connect \Y $or$ls180.v:4315$1262_Y
end
- attribute \src "ls180.v:4303.16-4303.60"
- cell $or $or$ls180.v:4303$1262
+ attribute \src "ls180.v:4316.16-4316.60"
+ cell $or $or$ls180.v:4316$1263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [15]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4303$1262_Y
+ connect \Y $or$ls180.v:4316$1263_Y
end
- attribute \src "ls180.v:4304.16-4304.60"
- cell $or $or$ls180.v:4304$1263
+ attribute \src "ls180.v:4317.16-4317.60"
+ cell $or $or$ls180.v:4317$1264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [16]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4304$1263_Y
+ connect \Y $or$ls180.v:4317$1264_Y
end
- attribute \src "ls180.v:4305.16-4305.60"
- cell $or $or$ls180.v:4305$1264
+ attribute \src "ls180.v:4318.16-4318.60"
+ cell $or $or$ls180.v:4318$1265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [17]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4305$1264_Y
+ connect \Y $or$ls180.v:4318$1265_Y
end
- attribute \src "ls180.v:4306.16-4306.60"
- cell $or $or$ls180.v:4306$1265
+ attribute \src "ls180.v:4319.16-4319.60"
+ cell $or $or$ls180.v:4319$1266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [18]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4306$1265_Y
+ connect \Y $or$ls180.v:4319$1266_Y
end
- attribute \src "ls180.v:4307.16-4307.60"
- cell $or $or$ls180.v:4307$1266
+ attribute \src "ls180.v:4320.16-4320.60"
+ cell $or $or$ls180.v:4320$1267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [19]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4307$1266_Y
+ connect \Y $or$ls180.v:4320$1267_Y
end
- attribute \src "ls180.v:4308.16-4308.60"
- cell $or $or$ls180.v:4308$1267
+ attribute \src "ls180.v:4321.16-4321.60"
+ cell $or $or$ls180.v:4321$1268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [20]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4308$1267_Y
+ connect \Y $or$ls180.v:4321$1268_Y
end
- attribute \src "ls180.v:4309.16-4309.60"
- cell $or $or$ls180.v:4309$1268
+ attribute \src "ls180.v:4322.16-4322.60"
+ cell $or $or$ls180.v:4322$1269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [21]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4309$1268_Y
+ connect \Y $or$ls180.v:4322$1269_Y
end
- attribute \src "ls180.v:4310.16-4310.60"
- cell $or $or$ls180.v:4310$1269
+ attribute \src "ls180.v:4323.16-4323.60"
+ cell $or $or$ls180.v:4323$1270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [22]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4310$1269_Y
+ connect \Y $or$ls180.v:4323$1270_Y
end
- attribute \src "ls180.v:4311.16-4311.60"
- cell $or $or$ls180.v:4311$1270
+ attribute \src "ls180.v:4324.16-4324.60"
+ cell $or $or$ls180.v:4324$1271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [23]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4311$1270_Y
+ connect \Y $or$ls180.v:4324$1271_Y
end
- attribute \src "ls180.v:4312.16-4312.60"
- cell $or $or$ls180.v:4312$1271
+ attribute \src "ls180.v:4325.16-4325.60"
+ cell $or $or$ls180.v:4325$1272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [24]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4312$1271_Y
+ connect \Y $or$ls180.v:4325$1272_Y
end
- attribute \src "ls180.v:4313.16-4313.60"
- cell $or $or$ls180.v:4313$1272
+ attribute \src "ls180.v:4326.16-4326.60"
+ cell $or $or$ls180.v:4326$1273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [25]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4313$1272_Y
+ connect \Y $or$ls180.v:4326$1273_Y
end
- attribute \src "ls180.v:4314.16-4314.60"
- cell $or $or$ls180.v:4314$1273
+ attribute \src "ls180.v:4327.16-4327.60"
+ cell $or $or$ls180.v:4327$1274
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [26]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4314$1273_Y
+ connect \Y $or$ls180.v:4327$1274_Y
end
- attribute \src "ls180.v:4315.16-4315.60"
- cell $or $or$ls180.v:4315$1274
+ attribute \src "ls180.v:4328.16-4328.60"
+ cell $or $or$ls180.v:4328$1275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [27]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4315$1274_Y
+ connect \Y $or$ls180.v:4328$1275_Y
end
- attribute \src "ls180.v:4316.16-4316.60"
- cell $or $or$ls180.v:4316$1275
+ attribute \src "ls180.v:4329.16-4329.60"
+ cell $or $or$ls180.v:4329$1276
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [28]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4316$1275_Y
+ connect \Y $or$ls180.v:4329$1276_Y
end
- attribute \src "ls180.v:4317.16-4317.60"
- cell $or $or$ls180.v:4317$1276
+ attribute \src "ls180.v:4330.16-4330.60"
+ cell $or $or$ls180.v:4330$1277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nc_1 [29]
connect \B \libresocsim_libresoc_interrupt [0]
- connect \Y $or$ls180.v:4317$1276_Y
+ connect \Y $or$ls180.v:4330$1277_Y
+ end
+ attribute \src "ls180.v:4331.16-4331.60"
+ cell $or $or$ls180.v:4331$1278
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \nc_1 [30]
+ connect \B \libresocsim_libresoc_interrupt [0]
+ connect \Y $or$ls180.v:4331$1278_Y
+ end
+ attribute \src "ls180.v:4332.16-4332.60"
+ cell $or $or$ls180.v:4332$1279
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \nc_1 [31]
+ connect \B \libresocsim_libresoc_interrupt [0]
+ connect \Y $or$ls180.v:4332$1279_Y
+ end
+ attribute \src "ls180.v:4333.16-4333.60"
+ cell $or $or$ls180.v:4333$1280
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \nc_1 [32]
+ connect \B \libresocsim_libresoc_interrupt [0]
+ connect \Y $or$ls180.v:4333$1280_Y
+ end
+ attribute \src "ls180.v:4334.16-4334.60"
+ cell $or $or$ls180.v:4334$1281
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \nc_1 [33]
+ connect \B \libresocsim_libresoc_interrupt [0]
+ connect \Y $or$ls180.v:4334$1281_Y
+ end
+ attribute \src "ls180.v:4335.16-4335.60"
+ cell $or $or$ls180.v:4335$1282
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \nc_1 [34]
+ connect \B \libresocsim_libresoc_interrupt [0]
+ connect \Y $or$ls180.v:4335$1282_Y
+ end
+ attribute \src "ls180.v:4336.16-4336.60"
+ cell $or $or$ls180.v:4336$1283
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \nc_1 [35]
+ connect \B \libresocsim_libresoc_interrupt [0]
+ connect \Y $or$ls180.v:4336$1283_Y
end
- attribute \src "ls180.v:4318.7-4318.58"
- cell $or $or$ls180.v:4318$1277
+ attribute \src "ls180.v:4337.7-4337.58"
+ cell $or $or$ls180.v:4337$1284
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresoc_xics_icp_ack
connect \B \converter0_skip
- connect \Y $or$ls180.v:4318$1277_Y
+ connect \Y $or$ls180.v:4337$1284_Y
end
- attribute \src "ls180.v:4329.7-4329.58"
- cell $or $or$ls180.v:4329$1278
+ attribute \src "ls180.v:4348.7-4348.58"
+ cell $or $or$ls180.v:4348$1285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \libresocsim_libresoc_xics_ics_ack
connect \B \converter1_skip
- connect \Y $or$ls180.v:4329$1278_Y
+ connect \Y $or$ls180.v:4348$1285_Y
end
- attribute \src "ls180.v:4340.7-4340.40"
- cell $or $or$ls180.v:4340$1279
+ attribute \src "ls180.v:4359.7-4359.40"
+ cell $or $or$ls180.v:4359$1286
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_sdram_ack
connect \B \socbushandler_skip
- connect \Y $or$ls180.v:4340$1279_Y
+ connect \Y $or$ls180.v:4359$1286_Y
end
- attribute \src "ls180.v:4473.7-4473.97"
- cell $or $or$ls180.v:4473$1318
+ attribute \src "ls180.v:4492.7-4492.97"
+ cell $or $or$ls180.v:4492$1325
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4473$1317_Y
+ connect \A $not$ls180.v:4492$1324_Y
connect \B \sdram_bankmachine0_cmd_buffer_source_ready
- connect \Y $or$ls180.v:4473$1318_Y
+ connect \Y $or$ls180.v:4492$1325_Y
end
- attribute \src "ls180.v:4519.7-4519.97"
- cell $or $or$ls180.v:4519$1334
+ attribute \src "ls180.v:4538.7-4538.97"
+ cell $or $or$ls180.v:4538$1341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4519$1333_Y
+ connect \A $not$ls180.v:4538$1340_Y
connect \B \sdram_bankmachine1_cmd_buffer_source_ready
- connect \Y $or$ls180.v:4519$1334_Y
+ connect \Y $or$ls180.v:4538$1341_Y
end
- attribute \src "ls180.v:4565.7-4565.97"
- cell $or $or$ls180.v:4565$1350
+ attribute \src "ls180.v:4584.7-4584.97"
+ cell $or $or$ls180.v:4584$1357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4565$1349_Y
+ connect \A $not$ls180.v:4584$1356_Y
connect \B \sdram_bankmachine2_cmd_buffer_source_ready
- connect \Y $or$ls180.v:4565$1350_Y
+ connect \Y $or$ls180.v:4584$1357_Y
end
- attribute \src "ls180.v:4611.7-4611.97"
- cell $or $or$ls180.v:4611$1366
+ attribute \src "ls180.v:4630.7-4630.97"
+ cell $or $or$ls180.v:4630$1373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $not$ls180.v:4611$1365_Y
+ connect \A $not$ls180.v:4630$1372_Y
connect \B \sdram_bankmachine3_cmd_buffer_source_ready
- connect \Y $or$ls180.v:4611$1366_Y
+ connect \Y $or$ls180.v:4630$1373_Y
end
- attribute \src "ls180.v:4799.45-4799.130"
- cell $or $or$ls180.v:4799$1387
+ attribute \src "ls180.v:4818.45-4818.130"
+ cell $or $or$ls180.v:4818$1394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:4799$1386_Y
- connect \Y $or$ls180.v:4799$1387_Y
+ connect \B $and$ls180.v:4818$1393_Y
+ connect \Y $or$ls180.v:4818$1394_Y
end
- attribute \src "ls180.v:4799.44-4799.212"
- cell $or $or$ls180.v:4799$1390
+ attribute \src "ls180.v:4818.44-4818.212"
+ cell $or $or$ls180.v:4818$1397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4799$1387_Y
- connect \B $and$ls180.v:4799$1389_Y
- connect \Y $or$ls180.v:4799$1390_Y
+ connect \A $or$ls180.v:4818$1394_Y
+ connect \B $and$ls180.v:4818$1396_Y
+ connect \Y $or$ls180.v:4818$1397_Y
end
- attribute \src "ls180.v:4799.43-4799.294"
- cell $or $or$ls180.v:4799$1393
+ attribute \src "ls180.v:4818.43-4818.294"
+ cell $or $or$ls180.v:4818$1400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4799$1390_Y
- connect \B $and$ls180.v:4799$1392_Y
- connect \Y $or$ls180.v:4799$1393_Y
+ connect \A $or$ls180.v:4818$1397_Y
+ connect \B $and$ls180.v:4818$1399_Y
+ connect \Y $or$ls180.v:4818$1400_Y
end
- attribute \src "ls180.v:4799.42-4799.376"
- cell $or $or$ls180.v:4799$1396
+ attribute \src "ls180.v:4818.42-4818.376"
+ cell $or $or$ls180.v:4818$1403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4799$1393_Y
- connect \B $and$ls180.v:4799$1395_Y
- connect \Y $or$ls180.v:4799$1396_Y
+ connect \A $or$ls180.v:4818$1400_Y
+ connect \B $and$ls180.v:4818$1402_Y
+ connect \Y $or$ls180.v:4818$1403_Y
end
- attribute \src "ls180.v:4800.46-4800.131"
- cell $or $or$ls180.v:4800$1399
+ attribute \src "ls180.v:4819.46-4819.131"
+ cell $or $or$ls180.v:4819$1406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A 1'0
- connect \B $and$ls180.v:4800$1398_Y
- connect \Y $or$ls180.v:4800$1399_Y
+ connect \B $and$ls180.v:4819$1405_Y
+ connect \Y $or$ls180.v:4819$1406_Y
end
- attribute \src "ls180.v:4800.45-4800.213"
- cell $or $or$ls180.v:4800$1402
+ attribute \src "ls180.v:4819.45-4819.213"
+ cell $or $or$ls180.v:4819$1409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4800$1399_Y
- connect \B $and$ls180.v:4800$1401_Y
- connect \Y $or$ls180.v:4800$1402_Y
+ connect \A $or$ls180.v:4819$1406_Y
+ connect \B $and$ls180.v:4819$1408_Y
+ connect \Y $or$ls180.v:4819$1409_Y
end
- attribute \src "ls180.v:4800.44-4800.295"
- cell $or $or$ls180.v:4800$1405
+ attribute \src "ls180.v:4819.44-4819.295"
+ cell $or $or$ls180.v:4819$1412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4800$1402_Y
- connect \B $and$ls180.v:4800$1404_Y
- connect \Y $or$ls180.v:4800$1405_Y
+ connect \A $or$ls180.v:4819$1409_Y
+ connect \B $and$ls180.v:4819$1411_Y
+ connect \Y $or$ls180.v:4819$1412_Y
end
- attribute \src "ls180.v:4800.43-4800.377"
- cell $or $or$ls180.v:4800$1408
+ attribute \src "ls180.v:4819.43-4819.377"
+ cell $or $or$ls180.v:4819$1415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $or$ls180.v:4800$1405_Y
- connect \B $and$ls180.v:4800$1407_Y
- connect \Y $or$ls180.v:4800$1408_Y
+ connect \A $or$ls180.v:4819$1412_Y
+ connect \B $and$ls180.v:4819$1414_Y
+ connect \Y $or$ls180.v:4819$1415_Y
end
- attribute \src "ls180.v:4804.7-4804.39"
- cell $or $or$ls180.v:4804$1409
+ attribute \src "ls180.v:4823.7-4823.39"
+ cell $or $or$ls180.v:4823$1416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \litedram_wb_ack
connect \B \converter_skip
- connect \Y $or$ls180.v:4804$1409_Y
+ connect \Y $or$ls180.v:4823$1416_Y
end
- attribute \src "ls180.v:5729.8-5729.46"
- cell $or $or$ls180.v:5729$1619
+ attribute \src "ls180.v:5748.8-5748.46"
+ cell $or $or$ls180.v:5748$1626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sys_rst_1
connect \B \libresocsim_libresoc_reset
- connect \Y $or$ls180.v:5729$1619_Y
+ connect \Y $or$ls180.v:5748$1626_Y
end
- attribute \src "ls180.v:1936.41-1936.84"
- cell $sshl $sshl$ls180.v:1936$130
+ attribute \src "ls180.v:1949.41-1949.84"
+ cell $sshl $sshl$ls180.v:1949$131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \sdram_bankmachine0_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:1936$130_Y
+ connect \Y $sshl$ls180.v:1949$131_Y
end
- attribute \src "ls180.v:2093.41-2093.84"
- cell $sshl $sshl$ls180.v:2093$160
+ attribute \src "ls180.v:2106.41-2106.84"
+ cell $sshl $sshl$ls180.v:2106$161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \sdram_bankmachine1_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:2093$160_Y
+ connect \Y $sshl$ls180.v:2106$161_Y
end
- attribute \src "ls180.v:2250.41-2250.84"
- cell $sshl $sshl$ls180.v:2250$190
+ attribute \src "ls180.v:2263.41-2263.84"
+ cell $sshl $sshl$ls180.v:2263$191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \sdram_bankmachine2_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:2250$190_Y
+ connect \Y $sshl$ls180.v:2263$191_Y
end
- attribute \src "ls180.v:2407.41-2407.84"
- cell $sshl $sshl$ls180.v:2407$220
+ attribute \src "ls180.v:2420.41-2420.84"
+ cell $sshl $sshl$ls180.v:2420$221
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 13
connect \A \sdram_bankmachine3_auto_precharge
connect \B 4'1010
- connect \Y $sshl$ls180.v:2407$220_Y
+ connect \Y $sshl$ls180.v:2420$221_Y
end
- attribute \src "ls180.v:1967.58-1967.112"
- cell $sub $sub$ls180.v:1967$143
+ attribute \src "ls180.v:1980.58-1980.112"
+ cell $sub $sub$ls180.v:1980$144
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:1967$143_Y
+ connect \Y $sub$ls180.v:1980$144_Y
end
- attribute \src "ls180.v:2124.58-2124.112"
- cell $sub $sub$ls180.v:2124$173
+ attribute \src "ls180.v:2137.58-2137.112"
+ cell $sub $sub$ls180.v:2137$174
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:2124$173_Y
+ connect \Y $sub$ls180.v:2137$174_Y
end
- attribute \src "ls180.v:2281.58-2281.112"
- cell $sub $sub$ls180.v:2281$203
+ attribute \src "ls180.v:2294.58-2294.112"
+ cell $sub $sub$ls180.v:2294$204
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:2281$203_Y
+ connect \Y $sub$ls180.v:2294$204_Y
end
- attribute \src "ls180.v:2438.58-2438.112"
- cell $sub $sub$ls180.v:2438$233
+ attribute \src "ls180.v:2451.58-2451.112"
+ cell $sub $sub$ls180.v:2451$234
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce
connect \B 1'1
- connect \Y $sub$ls180.v:2438$233_Y
+ connect \Y $sub$ls180.v:2451$234_Y
end
- attribute \src "ls180.v:2844.33-2844.65"
- cell $sub $sub$ls180.v:2844$587
+ attribute \src "ls180.v:2857.33-2857.65"
+ cell $sub $sub$ls180.v:2857$588
parameter \A_SIGNED 0
parameter \A_WIDTH 30
parameter \B_SIGNED 0
parameter \Y_WIDTH 31
connect \A \litedram_wb_adr
connect \B 31'1001000000000000000000000000000
- connect \Y $sub$ls180.v:2844$587_Y
+ connect \Y $sub$ls180.v:2857$588_Y
end
- attribute \src "ls180.v:2930.26-2930.48"
- cell $sub $sub$ls180.v:2930$632
+ attribute \src "ls180.v:2943.26-2943.48"
+ cell $sub $sub$ls180.v:2943$633
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \tx_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:2930$632_Y
+ connect \Y $sub$ls180.v:2943$633_Y
end
- attribute \src "ls180.v:2960.26-2960.48"
- cell $sub $sub$ls180.v:2960$643
+ attribute \src "ls180.v:2973.26-2973.48"
+ cell $sub $sub$ls180.v:2973$644
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \rx_fifo_produce
connect \B 1'1
- connect \Y $sub$ls180.v:2960$643_Y
+ connect \Y $sub$ls180.v:2973$644_Y
end
- attribute \src "ls180.v:4364.26-4364.50"
- cell $sub $sub$ls180.v:4364$1286
+ attribute \src "ls180.v:4383.26-4383.50"
+ cell $sub $sub$ls180.v:4383$1293
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A \libresocsim_value
connect \B 1'1
- connect \Y $sub$ls180.v:4364$1286_Y
+ connect \Y $sub$ls180.v:4383$1293_Y
end
- attribute \src "ls180.v:4389.26-4389.51"
- cell $sub $sub$ls180.v:4389$1294
+ attribute \src "ls180.v:4408.26-4408.51"
+ cell $sub $sub$ls180.v:4408$1301
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \sdram_timer_count1
connect \B 1'1
- connect \Y $sub$ls180.v:4389$1294_Y
+ connect \Y $sub$ls180.v:4408$1301_Y
end
- attribute \src "ls180.v:4395.29-4395.57"
- cell $sub $sub$ls180.v:4395$1295
+ attribute \src "ls180.v:4414.29-4414.57"
+ cell $sub $sub$ls180.v:4414$1302
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_postponer_count
connect \B 1'1
- connect \Y $sub$ls180.v:4395$1295_Y
+ connect \Y $sub$ls180.v:4414$1302_Y
end
- attribute \src "ls180.v:4406.31-4406.59"
- cell $sub $sub$ls180.v:4406$1298
+ attribute \src "ls180.v:4425.31-4425.59"
+ cell $sub $sub$ls180.v:4425$1305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_sequencer_count
connect \B 1'1
- connect \Y $sub$ls180.v:4406$1298_Y
+ connect \Y $sub$ls180.v:4425$1305_Y
end
- attribute \src "ls180.v:4470.54-4470.106"
- cell $sub $sub$ls180.v:4470$1316
+ attribute \src "ls180.v:4489.54-4489.106"
+ cell $sub $sub$ls180.v:4489$1323
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:4470$1316_Y
+ connect \Y $sub$ls180.v:4489$1323_Y
end
- attribute \src "ls180.v:4489.41-4489.80"
- cell $sub $sub$ls180.v:4489$1320
+ attribute \src "ls180.v:4508.41-4508.80"
+ cell $sub $sub$ls180.v:4508$1327
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine0_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:4489$1320_Y
+ connect \Y $sub$ls180.v:4508$1327_Y
end
- attribute \src "ls180.v:4516.54-4516.106"
- cell $sub $sub$ls180.v:4516$1332
+ attribute \src "ls180.v:4535.54-4535.106"
+ cell $sub $sub$ls180.v:4535$1339
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:4516$1332_Y
+ connect \Y $sub$ls180.v:4535$1339_Y
end
- attribute \src "ls180.v:4535.41-4535.80"
- cell $sub $sub$ls180.v:4535$1336
+ attribute \src "ls180.v:4554.41-4554.80"
+ cell $sub $sub$ls180.v:4554$1343
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine1_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:4535$1336_Y
+ connect \Y $sub$ls180.v:4554$1343_Y
end
- attribute \src "ls180.v:4562.54-4562.106"
- cell $sub $sub$ls180.v:4562$1348
+ attribute \src "ls180.v:4581.54-4581.106"
+ cell $sub $sub$ls180.v:4581$1355
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:4562$1348_Y
+ connect \Y $sub$ls180.v:4581$1355_Y
end
- attribute \src "ls180.v:4581.41-4581.80"
- cell $sub $sub$ls180.v:4581$1352
+ attribute \src "ls180.v:4600.41-4600.80"
+ cell $sub $sub$ls180.v:4600$1359
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine2_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:4581$1352_Y
+ connect \Y $sub$ls180.v:4600$1359_Y
end
- attribute \src "ls180.v:4608.54-4608.106"
- cell $sub $sub$ls180.v:4608$1364
+ attribute \src "ls180.v:4627.54-4627.106"
+ cell $sub $sub$ls180.v:4627$1371
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level
connect \B 1'1
- connect \Y $sub$ls180.v:4608$1364_Y
+ connect \Y $sub$ls180.v:4627$1371_Y
end
- attribute \src "ls180.v:4627.41-4627.80"
- cell $sub $sub$ls180.v:4627$1368
+ attribute \src "ls180.v:4646.41-4646.80"
+ cell $sub $sub$ls180.v:4646$1375
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_bankmachine3_twtpcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:4627$1368_Y
+ connect \Y $sub$ls180.v:4646$1375_Y
end
- attribute \src "ls180.v:4638.20-4638.38"
- cell $sub $sub$ls180.v:4638$1372
+ attribute \src "ls180.v:4657.20-4657.38"
+ cell $sub $sub$ls180.v:4657$1379
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \sdram_time0
connect \B 1'1
- connect \Y $sub$ls180.v:4638$1372_Y
+ connect \Y $sub$ls180.v:4657$1379_Y
end
- attribute \src "ls180.v:4645.20-4645.38"
- cell $sub $sub$ls180.v:4645$1375
+ attribute \src "ls180.v:4664.20-4664.38"
+ cell $sub $sub$ls180.v:4664$1382
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \sdram_time1
connect \B 1'1
- connect \Y $sub$ls180.v:4645$1375_Y
+ connect \Y $sub$ls180.v:4664$1382_Y
end
- attribute \src "ls180.v:4777.28-4777.54"
- cell $sub $sub$ls180.v:4777$1380
+ attribute \src "ls180.v:4796.28-4796.54"
+ cell $sub $sub$ls180.v:4796$1387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \sdram_tccdcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:4777$1380_Y
+ connect \Y $sub$ls180.v:4796$1387_Y
end
- attribute \src "ls180.v:4792.28-4792.54"
- cell $sub $sub$ls180.v:4792$1383
+ attribute \src "ls180.v:4811.28-4811.54"
+ cell $sub $sub$ls180.v:4811$1390
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \sdram_twtrcon_count
connect \B 1'1
- connect \Y $sub$ls180.v:4792$1383_Y
+ connect \Y $sub$ls180.v:4811$1390_Y
end
- attribute \src "ls180.v:4919.23-4919.44"
- cell $sub $sub$ls180.v:4919$1442
+ attribute \src "ls180.v:4938.23-4938.44"
+ cell $sub $sub$ls180.v:4938$1449
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \tx_fifo_level0
connect \B 1'1
- connect \Y $sub$ls180.v:4919$1442_Y
+ connect \Y $sub$ls180.v:4938$1449_Y
end
- attribute \src "ls180.v:4941.23-4941.44"
- cell $sub $sub$ls180.v:4941$1453
+ attribute \src "ls180.v:4960.23-4960.44"
+ cell $sub $sub$ls180.v:4960$1460
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \rx_fifo_level0
connect \B 1'1
- connect \Y $sub$ls180.v:4941$1453_Y
+ connect \Y $sub$ls180.v:4960$1460_Y
end
- attribute \src "ls180.v:5006.26-5006.50"
- cell $sub $sub$ls180.v:5006$1458
+ attribute \src "ls180.v:5025.26-5025.50"
+ cell $sub $sub$ls180.v:5025$1465
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A \libresocsim_count
connect \B 1'1
- connect \Y $sub$ls180.v:5006$1458_Y
+ connect \Y $sub$ls180.v:5025$1465_Y
end
attribute \module_not_derived 1
- attribute \src "ls180.v:5635.13-5961.2"
+ attribute \src "ls180.v:5654.13-5980.2"
cell \test_issuer \test_issuer
connect \TAP_bus__tck \libresocsim_libresoc_jtag_tck
connect \TAP_bus__tdi \libresocsim_libresoc_jtag_tdi
connect \dbus__sel \libresocsim_libresoc_dbus_sel
connect \dbus__stb \libresocsim_libresoc_dbus_stb
connect \dbus__we \libresocsim_libresoc_dbus_we
- connect \eint_0__core__i \eint [0]
- connect \eint_0__pad__i \eint_1 [0]
- connect \eint_1__core__i \eint [1]
- connect \eint_1__pad__i \eint_1 [1]
- connect \eint_2__core__i \eint [2]
- connect \eint_2__pad__i \eint_1 [2]
- connect \gpio_e10__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [10]
- connect \gpio_e10__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [10]
- connect \gpio_e10__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [10]
+ connect \eint_0__core__i \libresocsim_libresoc_constraintmanager_eint_0
+ connect \eint_0__pad__i \eint_0
+ connect \eint_1__core__i \libresocsim_libresoc_constraintmanager_eint_1
+ connect \eint_1__pad__i \eint_1
+ connect \eint_2__core__i \libresocsim_libresoc_constraintmanager_eint_2
+ connect \eint_2__pad__i \eint_2
+ connect \gpio_e10__core__i \libresocsim_libresoc_constraintmanager_gpio_i [10]
+ connect \gpio_e10__core__o \libresocsim_libresoc_constraintmanager_gpio_o [10]
+ connect \gpio_e10__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [10]
connect \gpio_e10__pad__i \gpio_i [10]
connect \gpio_e10__pad__o \gpio_o [10]
connect \gpio_e10__pad__oe \gpio_oe [10]
- connect \gpio_e11__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [11]
- connect \gpio_e11__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [11]
- connect \gpio_e11__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [11]
+ connect \gpio_e11__core__i \libresocsim_libresoc_constraintmanager_gpio_i [11]
+ connect \gpio_e11__core__o \libresocsim_libresoc_constraintmanager_gpio_o [11]
+ connect \gpio_e11__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [11]
connect \gpio_e11__pad__i \gpio_i [11]
connect \gpio_e11__pad__o \gpio_o [11]
connect \gpio_e11__pad__oe \gpio_oe [11]
- connect \gpio_e12__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [12]
- connect \gpio_e12__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [12]
- connect \gpio_e12__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [12]
+ connect \gpio_e12__core__i \libresocsim_libresoc_constraintmanager_gpio_i [12]
+ connect \gpio_e12__core__o \libresocsim_libresoc_constraintmanager_gpio_o [12]
+ connect \gpio_e12__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [12]
connect \gpio_e12__pad__i \gpio_i [12]
connect \gpio_e12__pad__o \gpio_o [12]
connect \gpio_e12__pad__oe \gpio_oe [12]
- connect \gpio_e13__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [13]
- connect \gpio_e13__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [13]
- connect \gpio_e13__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [13]
+ connect \gpio_e13__core__i \libresocsim_libresoc_constraintmanager_gpio_i [13]
+ connect \gpio_e13__core__o \libresocsim_libresoc_constraintmanager_gpio_o [13]
+ connect \gpio_e13__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [13]
connect \gpio_e13__pad__i \gpio_i [13]
connect \gpio_e13__pad__o \gpio_o [13]
connect \gpio_e13__pad__oe \gpio_oe [13]
- connect \gpio_e14__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [14]
- connect \gpio_e14__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [14]
- connect \gpio_e14__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [14]
+ connect \gpio_e14__core__i \libresocsim_libresoc_constraintmanager_gpio_i [14]
+ connect \gpio_e14__core__o \libresocsim_libresoc_constraintmanager_gpio_o [14]
+ connect \gpio_e14__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [14]
connect \gpio_e14__pad__i \gpio_i [14]
connect \gpio_e14__pad__o \gpio_o [14]
connect \gpio_e14__pad__oe \gpio_oe [14]
- connect \gpio_e15__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [15]
- connect \gpio_e15__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [15]
- connect \gpio_e15__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [15]
+ connect \gpio_e15__core__i \libresocsim_libresoc_constraintmanager_gpio_i [15]
+ connect \gpio_e15__core__o \libresocsim_libresoc_constraintmanager_gpio_o [15]
+ connect \gpio_e15__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [15]
connect \gpio_e15__pad__i \gpio_i [15]
connect \gpio_e15__pad__o \gpio_o [15]
connect \gpio_e15__pad__oe \gpio_oe [15]
- connect \gpio_e8__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [8]
- connect \gpio_e8__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [8]
- connect \gpio_e8__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [8]
+ connect \gpio_e8__core__i \libresocsim_libresoc_constraintmanager_gpio_i [8]
+ connect \gpio_e8__core__o \libresocsim_libresoc_constraintmanager_gpio_o [8]
+ connect \gpio_e8__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [8]
connect \gpio_e8__pad__i \gpio_i [8]
connect \gpio_e8__pad__o \gpio_o [8]
connect \gpio_e8__pad__oe \gpio_oe [8]
- connect \gpio_e9__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [9]
- connect \gpio_e9__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [9]
- connect \gpio_e9__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [9]
+ connect \gpio_e9__core__i \libresocsim_libresoc_constraintmanager_gpio_i [9]
+ connect \gpio_e9__core__o \libresocsim_libresoc_constraintmanager_gpio_o [9]
+ connect \gpio_e9__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [9]
connect \gpio_e9__pad__i \gpio_i [9]
connect \gpio_e9__pad__o \gpio_o [9]
connect \gpio_e9__pad__oe \gpio_oe [9]
- connect \gpio_s0__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [0]
- connect \gpio_s0__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [0]
- connect \gpio_s0__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [0]
+ connect \gpio_s0__core__i \libresocsim_libresoc_constraintmanager_gpio_i [0]
+ connect \gpio_s0__core__o \libresocsim_libresoc_constraintmanager_gpio_o [0]
+ connect \gpio_s0__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [0]
connect \gpio_s0__pad__i \gpio_i [0]
connect \gpio_s0__pad__o \gpio_o [0]
connect \gpio_s0__pad__oe \gpio_oe [0]
- connect \gpio_s1__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [1]
- connect \gpio_s1__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [1]
- connect \gpio_s1__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [1]
+ connect \gpio_s1__core__i \libresocsim_libresoc_constraintmanager_gpio_i [1]
+ connect \gpio_s1__core__o \libresocsim_libresoc_constraintmanager_gpio_o [1]
+ connect \gpio_s1__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [1]
connect \gpio_s1__pad__i \gpio_i [1]
connect \gpio_s1__pad__o \gpio_o [1]
connect \gpio_s1__pad__oe \gpio_oe [1]
- connect \gpio_s2__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [2]
- connect \gpio_s2__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [2]
- connect \gpio_s2__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [2]
+ connect \gpio_s2__core__i \libresocsim_libresoc_constraintmanager_gpio_i [2]
+ connect \gpio_s2__core__o \libresocsim_libresoc_constraintmanager_gpio_o [2]
+ connect \gpio_s2__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [2]
connect \gpio_s2__pad__i \gpio_i [2]
connect \gpio_s2__pad__o \gpio_o [2]
connect \gpio_s2__pad__oe \gpio_oe [2]
- connect \gpio_s3__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [3]
- connect \gpio_s3__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [3]
- connect \gpio_s3__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [3]
+ connect \gpio_s3__core__i \libresocsim_libresoc_constraintmanager_gpio_i [3]
+ connect \gpio_s3__core__o \libresocsim_libresoc_constraintmanager_gpio_o [3]
+ connect \gpio_s3__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [3]
connect \gpio_s3__pad__i \gpio_i [3]
connect \gpio_s3__pad__o \gpio_o [3]
connect \gpio_s3__pad__oe \gpio_oe [3]
- connect \gpio_s4__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [4]
- connect \gpio_s4__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [4]
- connect \gpio_s4__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [4]
+ connect \gpio_s4__core__i \libresocsim_libresoc_constraintmanager_gpio_i [4]
+ connect \gpio_s4__core__o \libresocsim_libresoc_constraintmanager_gpio_o [4]
+ connect \gpio_s4__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [4]
connect \gpio_s4__pad__i \gpio_i [4]
connect \gpio_s4__pad__o \gpio_o [4]
connect \gpio_s4__pad__oe \gpio_oe [4]
- connect \gpio_s5__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [5]
- connect \gpio_s5__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [5]
- connect \gpio_s5__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [5]
+ connect \gpio_s5__core__i \libresocsim_libresoc_constraintmanager_gpio_i [5]
+ connect \gpio_s5__core__o \libresocsim_libresoc_constraintmanager_gpio_o [5]
+ connect \gpio_s5__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [5]
connect \gpio_s5__pad__i \gpio_i [5]
connect \gpio_s5__pad__o \gpio_o [5]
connect \gpio_s5__pad__oe \gpio_oe [5]
- connect \gpio_s6__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [6]
- connect \gpio_s6__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [6]
- connect \gpio_s6__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [6]
+ connect \gpio_s6__core__i \libresocsim_libresoc_constraintmanager_gpio_i [6]
+ connect \gpio_s6__core__o \libresocsim_libresoc_constraintmanager_gpio_o [6]
+ connect \gpio_s6__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [6]
connect \gpio_s6__pad__i \gpio_i [6]
connect \gpio_s6__pad__o \gpio_o [6]
connect \gpio_s6__pad__oe \gpio_oe [6]
- connect \gpio_s7__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [7]
- connect \gpio_s7__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [7]
- connect \gpio_s7__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [7]
+ connect \gpio_s7__core__i \libresocsim_libresoc_constraintmanager_gpio_i [7]
+ connect \gpio_s7__core__o \libresocsim_libresoc_constraintmanager_gpio_o [7]
+ connect \gpio_s7__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [7]
connect \gpio_s7__pad__i \gpio_i [7]
connect \gpio_s7__pad__o \gpio_o [7]
connect \gpio_s7__pad__oe \gpio_oe [7]
connect \jtag_wb__stb \libresocsim_libresoc_jtag_wb_stb
connect \jtag_wb__we \libresocsim_libresoc_jtag_wb_we
connect \memerr_o \libresocsim_libresoc1
- connect \mspi0_clk__core__o \libresocsim_libresoc_constraintmanager_obj_spimaster_clk
+ connect \mspi0_clk__core__o \libresocsim_libresoc_constraintmanager_spimaster_clk
connect \mspi0_clk__pad__o \spimaster_clk
- connect \mspi0_cs_n__core__o \libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
+ connect \mspi0_cs_n__core__o \libresocsim_libresoc_constraintmanager_spimaster_cs_n
connect \mspi0_cs_n__pad__o \spimaster_cs_n
- connect \mspi0_miso__core__i \libresocsim_libresoc_constraintmanager_obj_spimaster_miso
+ connect \mspi0_miso__core__i \libresocsim_libresoc_constraintmanager_spimaster_miso
connect \mspi0_miso__pad__i \spimaster_miso
- connect \mspi0_mosi__core__o \libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
+ connect \mspi0_mosi__core__o \libresocsim_libresoc_constraintmanager_spimaster_mosi
connect \mspi0_mosi__pad__o \spimaster_mosi
- connect \mtwi_scl__core__o \libresocsim_libresoc_constraintmanager_obj_i2c_scl
+ connect \mtwi_scl__core__o \libresocsim_libresoc_constraintmanager_i2c_scl
connect \mtwi_scl__pad__o \i2c_scl
- connect \mtwi_sda__core__i \libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
- connect \mtwi_sda__core__o \libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
- connect \mtwi_sda__core__oe \libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
+ connect \mtwi_sda__core__i \libresocsim_libresoc_constraintmanager_i2c_sda_i
+ connect \mtwi_sda__core__o \libresocsim_libresoc_constraintmanager_i2c_sda_o
+ connect \mtwi_sda__core__oe \libresocsim_libresoc_constraintmanager_i2c_sda_oe
connect \mtwi_sda__pad__i \i2c_sda_i
connect \mtwi_sda__pad__o \i2c_sda_o
connect \mtwi_sda__pad__oe \i2c_sda_oe
connect \pc_o \libresocsim_libresoc2
connect \pll_18_o \libresocsim_libresoc_pll_18_o
connect \pll_lck_o \libresocsim_libresoc_pll_lck_o
- connect \rst $or$ls180.v:5729$1619_Y
- connect \sdr_a_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [0]
+ connect \rst $or$ls180.v:5748$1626_Y
+ connect \sdr_a_0__core__o \libresocsim_libresoc_constraintmanager_sdram_a [0]
connect \sdr_a_0__pad__o \sdram_a [0]
- connect \sdr_a_10__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [10]
+ connect \sdr_a_10__core__o \libresocsim_libresoc_constraintmanager_sdram_a [10]
connect \sdr_a_10__pad__o \sdram_a [10]
- connect \sdr_a_11__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [11]
+ connect \sdr_a_11__core__o \libresocsim_libresoc_constraintmanager_sdram_a [11]
connect \sdr_a_11__pad__o \sdram_a [11]
- connect \sdr_a_12__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [12]
+ connect \sdr_a_12__core__o \libresocsim_libresoc_constraintmanager_sdram_a [12]
connect \sdr_a_12__pad__o \sdram_a [12]
- connect \sdr_a_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [1]
+ connect \sdr_a_1__core__o \libresocsim_libresoc_constraintmanager_sdram_a [1]
connect \sdr_a_1__pad__o \sdram_a [1]
- connect \sdr_a_2__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [2]
+ connect \sdr_a_2__core__o \libresocsim_libresoc_constraintmanager_sdram_a [2]
connect \sdr_a_2__pad__o \sdram_a [2]
- connect \sdr_a_3__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [3]
+ connect \sdr_a_3__core__o \libresocsim_libresoc_constraintmanager_sdram_a [3]
connect \sdr_a_3__pad__o \sdram_a [3]
- connect \sdr_a_4__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [4]
+ connect \sdr_a_4__core__o \libresocsim_libresoc_constraintmanager_sdram_a [4]
connect \sdr_a_4__pad__o \sdram_a [4]
- connect \sdr_a_5__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [5]
+ connect \sdr_a_5__core__o \libresocsim_libresoc_constraintmanager_sdram_a [5]
connect \sdr_a_5__pad__o \sdram_a [5]
- connect \sdr_a_6__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [6]
+ connect \sdr_a_6__core__o \libresocsim_libresoc_constraintmanager_sdram_a [6]
connect \sdr_a_6__pad__o \sdram_a [6]
- connect \sdr_a_7__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [7]
+ connect \sdr_a_7__core__o \libresocsim_libresoc_constraintmanager_sdram_a [7]
connect \sdr_a_7__pad__o \sdram_a [7]
- connect \sdr_a_8__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [8]
+ connect \sdr_a_8__core__o \libresocsim_libresoc_constraintmanager_sdram_a [8]
connect \sdr_a_8__pad__o \sdram_a [8]
- connect \sdr_a_9__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [9]
+ connect \sdr_a_9__core__o \libresocsim_libresoc_constraintmanager_sdram_a [9]
connect \sdr_a_9__pad__o \sdram_a [9]
- connect \sdr_ba_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_ba [0]
+ connect \sdr_ba_0__core__o \libresocsim_libresoc_constraintmanager_sdram_ba [0]
connect \sdr_ba_0__pad__o \sdram_ba [0]
- connect \sdr_ba_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_ba [1]
+ connect \sdr_ba_1__core__o \libresocsim_libresoc_constraintmanager_sdram_ba [1]
connect \sdr_ba_1__pad__o \sdram_ba [1]
- connect \sdr_cas_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
+ connect \sdr_cas_n__core__o \libresocsim_libresoc_constraintmanager_sdram_cas_n
connect \sdr_cas_n__pad__o \sdram_cas_n
- connect \sdr_cke__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_cke
+ connect \sdr_cke__core__o \libresocsim_libresoc_constraintmanager_sdram_cke
connect \sdr_cke__pad__o \sdram_cke
- connect \sdr_clock__core__o \sdram_clock
- connect \sdr_clock__pad__o \sdram_clock_1
- connect \sdr_cs_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
+ connect \sdr_clock__core__o \libresocsim_libresoc_constraintmanager_sdram_clock
+ connect \sdr_clock__pad__o \sdram_clock
+ connect \sdr_cs_n__core__o \libresocsim_libresoc_constraintmanager_sdram_cs_n
connect \sdr_cs_n__pad__o \sdram_cs_n
- connect \sdr_dm_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dm [0]
+ connect \sdr_dm_0__core__o \libresocsim_libresoc_constraintmanager_sdram_dm [0]
connect \sdr_dm_0__pad__o \sdram_dm [0]
- connect \sdr_dm_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dm [1]
+ connect \sdr_dm_1__core__o \libresocsim_libresoc_constraintmanager_sdram_dm [1]
connect \sdr_dm_1__pad__o \sdram_dm [1]
- connect \sdr_dq_0__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0]
- connect \sdr_dq_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0]
- connect \sdr_dq_0__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_0__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [0]
+ connect \sdr_dq_0__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [0]
+ connect \sdr_dq_0__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_0__pad__i \sdram_dq_i [0]
connect \sdr_dq_0__pad__o \sdram_dq_o [0]
connect \sdr_dq_0__pad__oe \sdram_dq_oe
- connect \sdr_dq_10__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10]
- connect \sdr_dq_10__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10]
- connect \sdr_dq_10__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_10__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [10]
+ connect \sdr_dq_10__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [10]
+ connect \sdr_dq_10__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_10__pad__i \sdram_dq_i [10]
connect \sdr_dq_10__pad__o \sdram_dq_o [10]
connect \sdr_dq_10__pad__oe \sdram_dq_oe
- connect \sdr_dq_11__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11]
- connect \sdr_dq_11__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11]
- connect \sdr_dq_11__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_11__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [11]
+ connect \sdr_dq_11__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [11]
+ connect \sdr_dq_11__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_11__pad__i \sdram_dq_i [11]
connect \sdr_dq_11__pad__o \sdram_dq_o [11]
connect \sdr_dq_11__pad__oe \sdram_dq_oe
- connect \sdr_dq_12__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12]
- connect \sdr_dq_12__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12]
- connect \sdr_dq_12__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_12__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [12]
+ connect \sdr_dq_12__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [12]
+ connect \sdr_dq_12__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_12__pad__i \sdram_dq_i [12]
connect \sdr_dq_12__pad__o \sdram_dq_o [12]
connect \sdr_dq_12__pad__oe \sdram_dq_oe
- connect \sdr_dq_13__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13]
- connect \sdr_dq_13__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13]
- connect \sdr_dq_13__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_13__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [13]
+ connect \sdr_dq_13__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [13]
+ connect \sdr_dq_13__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_13__pad__i \sdram_dq_i [13]
connect \sdr_dq_13__pad__o \sdram_dq_o [13]
connect \sdr_dq_13__pad__oe \sdram_dq_oe
- connect \sdr_dq_14__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14]
- connect \sdr_dq_14__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14]
- connect \sdr_dq_14__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_14__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [14]
+ connect \sdr_dq_14__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [14]
+ connect \sdr_dq_14__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_14__pad__i \sdram_dq_i [14]
connect \sdr_dq_14__pad__o \sdram_dq_o [14]
connect \sdr_dq_14__pad__oe \sdram_dq_oe
- connect \sdr_dq_15__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15]
- connect \sdr_dq_15__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15]
- connect \sdr_dq_15__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_15__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [15]
+ connect \sdr_dq_15__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [15]
+ connect \sdr_dq_15__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_15__pad__i \sdram_dq_i [15]
connect \sdr_dq_15__pad__o \sdram_dq_o [15]
connect \sdr_dq_15__pad__oe \sdram_dq_oe
- connect \sdr_dq_1__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1]
- connect \sdr_dq_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1]
- connect \sdr_dq_1__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_1__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [1]
+ connect \sdr_dq_1__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [1]
+ connect \sdr_dq_1__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_1__pad__i \sdram_dq_i [1]
connect \sdr_dq_1__pad__o \sdram_dq_o [1]
connect \sdr_dq_1__pad__oe \sdram_dq_oe
- connect \sdr_dq_2__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2]
- connect \sdr_dq_2__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2]
- connect \sdr_dq_2__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_2__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [2]
+ connect \sdr_dq_2__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [2]
+ connect \sdr_dq_2__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_2__pad__i \sdram_dq_i [2]
connect \sdr_dq_2__pad__o \sdram_dq_o [2]
connect \sdr_dq_2__pad__oe \sdram_dq_oe
- connect \sdr_dq_3__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3]
- connect \sdr_dq_3__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3]
- connect \sdr_dq_3__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_3__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [3]
+ connect \sdr_dq_3__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [3]
+ connect \sdr_dq_3__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_3__pad__i \sdram_dq_i [3]
connect \sdr_dq_3__pad__o \sdram_dq_o [3]
connect \sdr_dq_3__pad__oe \sdram_dq_oe
- connect \sdr_dq_4__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4]
- connect \sdr_dq_4__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4]
- connect \sdr_dq_4__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_4__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [4]
+ connect \sdr_dq_4__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [4]
+ connect \sdr_dq_4__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_4__pad__i \sdram_dq_i [4]
connect \sdr_dq_4__pad__o \sdram_dq_o [4]
connect \sdr_dq_4__pad__oe \sdram_dq_oe
- connect \sdr_dq_5__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5]
- connect \sdr_dq_5__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5]
- connect \sdr_dq_5__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_5__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [5]
+ connect \sdr_dq_5__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [5]
+ connect \sdr_dq_5__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_5__pad__i \sdram_dq_i [5]
connect \sdr_dq_5__pad__o \sdram_dq_o [5]
connect \sdr_dq_5__pad__oe \sdram_dq_oe
- connect \sdr_dq_6__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6]
- connect \sdr_dq_6__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6]
- connect \sdr_dq_6__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_6__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [6]
+ connect \sdr_dq_6__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [6]
+ connect \sdr_dq_6__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_6__pad__i \sdram_dq_i [6]
connect \sdr_dq_6__pad__o \sdram_dq_o [6]
connect \sdr_dq_6__pad__oe \sdram_dq_oe
- connect \sdr_dq_7__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7]
- connect \sdr_dq_7__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7]
- connect \sdr_dq_7__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_7__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [7]
+ connect \sdr_dq_7__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [7]
+ connect \sdr_dq_7__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_7__pad__i \sdram_dq_i [7]
connect \sdr_dq_7__pad__o \sdram_dq_o [7]
connect \sdr_dq_7__pad__oe \sdram_dq_oe
- connect \sdr_dq_8__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8]
- connect \sdr_dq_8__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8]
- connect \sdr_dq_8__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_8__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [8]
+ connect \sdr_dq_8__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [8]
+ connect \sdr_dq_8__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_8__pad__i \sdram_dq_i [8]
connect \sdr_dq_8__pad__o \sdram_dq_o [8]
connect \sdr_dq_8__pad__oe \sdram_dq_oe
- connect \sdr_dq_9__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9]
- connect \sdr_dq_9__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9]
- connect \sdr_dq_9__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
+ connect \sdr_dq_9__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [9]
+ connect \sdr_dq_9__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [9]
+ connect \sdr_dq_9__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe
connect \sdr_dq_9__pad__i \sdram_dq_i [9]
connect \sdr_dq_9__pad__o \sdram_dq_o [9]
connect \sdr_dq_9__pad__oe \sdram_dq_oe
- connect \sdr_ras_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
+ connect \sdr_ras_n__core__o \libresocsim_libresoc_constraintmanager_sdram_ras_n
connect \sdr_ras_n__pad__o \sdram_ras_n
- connect \sdr_we_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_we_n
+ connect \sdr_we_n__core__o \libresocsim_libresoc_constraintmanager_sdram_we_n
connect \sdr_we_n__pad__o \sdram_we_n
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$2136
+ process $proc$ls180.v:0$2144
sync always
sync init
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$2137
+ process $proc$ls180.v:0$2145
+ sync always
+ sync init
+ end
+ attribute \src "ls180.v:1002.11-1002.29"
+ process $proc$ls180.v:1002$2021
+ assign { } { }
+ assign $1\i2c_storage[2:0] 3'000
+ sync always
+ sync init
+ update \i2c_storage $1\i2c_storage[2:0]
+ end
+ attribute \src "ls180.v:1003.5-1003.18"
+ process $proc$ls180.v:1003$2022
+ assign { } { }
+ assign $1\i2c_re[0:0] 1'0
sync always
sync init
+ update \i2c_re $1\i2c_re[0:0]
end
- attribute \src "ls180.v:1002.5-1002.41"
- process $proc$ls180.v:1002$2015
+ attribute \src "ls180.v:1007.5-1007.41"
+ process $proc$ls180.v:1007$2023
assign { } { }
assign $1\subfragments_converter0_state[0:0] 1'0
sync always
sync init
update \subfragments_converter0_state $1\subfragments_converter0_state[0:0]
end
- attribute \src "ls180.v:1003.5-1003.46"
- process $proc$ls180.v:1003$2016
+ attribute \src "ls180.v:1008.5-1008.46"
+ process $proc$ls180.v:1008$2024
assign { } { }
assign $1\subfragments_converter0_next_state[0:0] 1'0
sync always
sync init
update \subfragments_converter0_next_state $1\subfragments_converter0_next_state[0:0]
end
- attribute \src "ls180.v:1004.5-1004.65"
- process $proc$ls180.v:1004$2017
+ attribute \src "ls180.v:1009.5-1009.65"
+ process $proc$ls180.v:1009$2025
assign { } { }
assign $1\converter0_counter_subfragments_converter0_next_value[0:0] 1'0
sync always
sync init
update \converter0_counter_subfragments_converter0_next_value $1\converter0_counter_subfragments_converter0_next_value[0:0]
end
- attribute \src "ls180.v:1005.5-1005.68"
- process $proc$ls180.v:1005$2018
+ attribute \src "ls180.v:1010.5-1010.68"
+ process $proc$ls180.v:1010$2026
assign { } { }
assign $1\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0
sync always
sync init
update \converter0_counter_subfragments_converter0_next_value_ce $1\converter0_counter_subfragments_converter0_next_value_ce[0:0]
end
- attribute \src "ls180.v:1006.5-1006.41"
- process $proc$ls180.v:1006$2019
+ attribute \src "ls180.v:1011.5-1011.41"
+ process $proc$ls180.v:1011$2027
assign { } { }
assign $1\subfragments_converter1_state[0:0] 1'0
sync always
sync init
update \subfragments_converter1_state $1\subfragments_converter1_state[0:0]
end
- attribute \src "ls180.v:1007.5-1007.46"
- process $proc$ls180.v:1007$2020
+ attribute \src "ls180.v:1012.5-1012.46"
+ process $proc$ls180.v:1012$2028
assign { } { }
assign $1\subfragments_converter1_next_state[0:0] 1'0
sync always
sync init
update \subfragments_converter1_next_state $1\subfragments_converter1_next_state[0:0]
end
- attribute \src "ls180.v:1008.5-1008.65"
- process $proc$ls180.v:1008$2021
+ attribute \src "ls180.v:1013.5-1013.65"
+ process $proc$ls180.v:1013$2029
assign { } { }
assign $1\converter1_counter_subfragments_converter1_next_value[0:0] 1'0
sync always
sync init
update \converter1_counter_subfragments_converter1_next_value $1\converter1_counter_subfragments_converter1_next_value[0:0]
end
- attribute \src "ls180.v:1009.5-1009.68"
- process $proc$ls180.v:1009$2022
+ attribute \src "ls180.v:1014.5-1014.68"
+ process $proc$ls180.v:1014$2030
assign { } { }
assign $1\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0
sync always
sync init
update \converter1_counter_subfragments_converter1_next_value_ce $1\converter1_counter_subfragments_converter1_next_value_ce[0:0]
end
- attribute \src "ls180.v:1010.5-1010.41"
- process $proc$ls180.v:1010$2023
+ attribute \src "ls180.v:1015.5-1015.41"
+ process $proc$ls180.v:1015$2031
assign { } { }
assign $1\subfragments_converter2_state[0:0] 1'0
sync always
sync init
update \subfragments_converter2_state $1\subfragments_converter2_state[0:0]
end
- attribute \src "ls180.v:1011.5-1011.46"
- process $proc$ls180.v:1011$2024
+ attribute \src "ls180.v:1016.5-1016.46"
+ process $proc$ls180.v:1016$2032
assign { } { }
assign $1\subfragments_converter2_next_state[0:0] 1'0
sync always
sync init
update \subfragments_converter2_next_state $1\subfragments_converter2_next_state[0:0]
end
- attribute \src "ls180.v:1012.5-1012.68"
- process $proc$ls180.v:1012$2025
+ attribute \src "ls180.v:1017.5-1017.68"
+ process $proc$ls180.v:1017$2033
assign { } { }
assign $1\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0
sync always
sync init
update \socbushandler_counter_subfragments_converter2_next_value $1\socbushandler_counter_subfragments_converter2_next_value[0:0]
end
- attribute \src "ls180.v:1013.5-1013.71"
- process $proc$ls180.v:1013$2026
+ attribute \src "ls180.v:1018.5-1018.71"
+ process $proc$ls180.v:1018$2034
assign { } { }
assign $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'0
sync always
sync init
update \socbushandler_counter_subfragments_converter2_next_value_ce $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
end
- attribute \src "ls180.v:1014.11-1014.46"
- process $proc$ls180.v:1014$2027
+ attribute \src "ls180.v:1019.11-1019.46"
+ process $proc$ls180.v:1019$2035
assign { } { }
assign $1\subfragments_refresher_state[1:0] 2'00
sync always
sync init
update \subfragments_refresher_state $1\subfragments_refresher_state[1:0]
end
- attribute \src "ls180.v:1015.11-1015.51"
- process $proc$ls180.v:1015$2028
+ attribute \src "ls180.v:1020.11-1020.51"
+ process $proc$ls180.v:1020$2036
assign { } { }
assign $1\subfragments_refresher_next_state[1:0] 2'00
sync always
sync init
update \subfragments_refresher_next_state $1\subfragments_refresher_next_state[1:0]
end
- attribute \src "ls180.v:1016.11-1016.49"
- process $proc$ls180.v:1016$2029
+ attribute \src "ls180.v:1021.11-1021.49"
+ process $proc$ls180.v:1021$2037
assign { } { }
assign $1\subfragments_bankmachine0_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine0_state $1\subfragments_bankmachine0_state[2:0]
end
- attribute \src "ls180.v:1017.11-1017.54"
- process $proc$ls180.v:1017$2030
+ attribute \src "ls180.v:1022.11-1022.54"
+ process $proc$ls180.v:1022$2038
assign { } { }
assign $1\subfragments_bankmachine0_next_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine0_next_state $1\subfragments_bankmachine0_next_state[2:0]
end
- attribute \src "ls180.v:1018.11-1018.49"
- process $proc$ls180.v:1018$2031
+ attribute \src "ls180.v:1023.11-1023.49"
+ process $proc$ls180.v:1023$2039
assign { } { }
assign $1\subfragments_bankmachine1_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine1_state $1\subfragments_bankmachine1_state[2:0]
end
- attribute \src "ls180.v:1019.11-1019.54"
- process $proc$ls180.v:1019$2032
+ attribute \src "ls180.v:1024.11-1024.54"
+ process $proc$ls180.v:1024$2040
assign { } { }
assign $1\subfragments_bankmachine1_next_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine1_next_state $1\subfragments_bankmachine1_next_state[2:0]
end
- attribute \src "ls180.v:102.11-102.50"
- process $proc$ls180.v:102$1642
- assign { } { }
- assign $0\libresocsim_libresoc_jtag_wb_cti[2:0] 3'000
- sync always
- update \libresocsim_libresoc_jtag_wb_cti $0\libresocsim_libresoc_jtag_wb_cti[2:0]
- sync init
- end
- attribute \src "ls180.v:1020.11-1020.49"
- process $proc$ls180.v:1020$2033
+ attribute \src "ls180.v:1025.11-1025.49"
+ process $proc$ls180.v:1025$2041
assign { } { }
assign $1\subfragments_bankmachine2_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine2_state $1\subfragments_bankmachine2_state[2:0]
end
- attribute \src "ls180.v:1021.11-1021.54"
- process $proc$ls180.v:1021$2034
+ attribute \src "ls180.v:1026.11-1026.54"
+ process $proc$ls180.v:1026$2042
assign { } { }
assign $1\subfragments_bankmachine2_next_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine2_next_state $1\subfragments_bankmachine2_next_state[2:0]
end
- attribute \src "ls180.v:1022.11-1022.49"
- process $proc$ls180.v:1022$2035
+ attribute \src "ls180.v:1027.11-1027.49"
+ process $proc$ls180.v:1027$2043
assign { } { }
assign $1\subfragments_bankmachine3_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine3_state $1\subfragments_bankmachine3_state[2:0]
end
- attribute \src "ls180.v:1023.11-1023.54"
- process $proc$ls180.v:1023$2036
+ attribute \src "ls180.v:1028.11-1028.54"
+ process $proc$ls180.v:1028$2044
assign { } { }
assign $1\subfragments_bankmachine3_next_state[2:0] 3'000
sync always
sync init
update \subfragments_bankmachine3_next_state $1\subfragments_bankmachine3_next_state[2:0]
end
- attribute \src "ls180.v:1024.11-1024.48"
- process $proc$ls180.v:1024$2037
+ attribute \src "ls180.v:1029.11-1029.48"
+ process $proc$ls180.v:1029$2045
assign { } { }
assign $1\subfragments_multiplexer_state[2:0] 3'000
sync always
sync init
update \subfragments_multiplexer_state $1\subfragments_multiplexer_state[2:0]
end
- attribute \src "ls180.v:1025.11-1025.53"
- process $proc$ls180.v:1025$2038
+ attribute \src "ls180.v:1030.11-1030.53"
+ process $proc$ls180.v:1030$2046
assign { } { }
assign $1\subfragments_multiplexer_next_state[2:0] 3'000
sync always
sync init
update \subfragments_multiplexer_next_state $1\subfragments_multiplexer_next_state[2:0]
end
- attribute \src "ls180.v:103.11-103.50"
- process $proc$ls180.v:103$1643
+ attribute \src "ls180.v:104.11-104.50"
+ process $proc$ls180.v:104$1649
assign { } { }
- assign $0\libresocsim_libresoc_jtag_wb_bte[1:0] 2'00
+ assign $0\libresocsim_libresoc_jtag_wb_cti[2:0] 3'000
sync always
- update \libresocsim_libresoc_jtag_wb_bte $0\libresocsim_libresoc_jtag_wb_bte[1:0]
+ update \libresocsim_libresoc_jtag_wb_cti $0\libresocsim_libresoc_jtag_wb_cti[2:0]
sync init
end
- attribute \src "ls180.v:1038.5-1038.32"
- process $proc$ls180.v:1038$2039
+ attribute \src "ls180.v:1043.5-1043.32"
+ process $proc$ls180.v:1043$2047
assign { } { }
assign $0\subfragments_locked0[0:0] 1'0
sync always
update \subfragments_locked0 $0\subfragments_locked0[0:0]
sync init
end
- attribute \src "ls180.v:1039.5-1039.32"
- process $proc$ls180.v:1039$2040
+ attribute \src "ls180.v:1044.5-1044.32"
+ process $proc$ls180.v:1044$2048
assign { } { }
assign $0\subfragments_locked1[0:0] 1'0
sync always
update \subfragments_locked1 $0\subfragments_locked1[0:0]
sync init
end
- attribute \src "ls180.v:1040.5-1040.32"
- process $proc$ls180.v:1040$2041
+ attribute \src "ls180.v:1045.5-1045.32"
+ process $proc$ls180.v:1045$2049
assign { } { }
assign $0\subfragments_locked2[0:0] 1'0
sync always
update \subfragments_locked2 $0\subfragments_locked2[0:0]
sync init
end
- attribute \src "ls180.v:1041.5-1041.32"
- process $proc$ls180.v:1041$2042
+ attribute \src "ls180.v:1046.5-1046.32"
+ process $proc$ls180.v:1046$2050
assign { } { }
assign $0\subfragments_locked3[0:0] 1'0
sync always
update \subfragments_locked3 $0\subfragments_locked3[0:0]
sync init
end
- attribute \src "ls180.v:1042.5-1042.47"
- process $proc$ls180.v:1042$2043
+ attribute \src "ls180.v:1047.5-1047.47"
+ process $proc$ls180.v:1047$2051
assign { } { }
assign $1\subfragments_new_master_wdata_ready[0:0] 1'0
sync always
sync init
update \subfragments_new_master_wdata_ready $1\subfragments_new_master_wdata_ready[0:0]
end
- attribute \src "ls180.v:1043.5-1043.48"
- process $proc$ls180.v:1043$2044
+ attribute \src "ls180.v:1048.5-1048.48"
+ process $proc$ls180.v:1048$2052
assign { } { }
assign $1\subfragments_new_master_rdata_valid0[0:0] 1'0
sync always
sync init
update \subfragments_new_master_rdata_valid0 $1\subfragments_new_master_rdata_valid0[0:0]
end
- attribute \src "ls180.v:1044.5-1044.48"
- process $proc$ls180.v:1044$2045
+ attribute \src "ls180.v:1049.5-1049.48"
+ process $proc$ls180.v:1049$2053
assign { } { }
assign $1\subfragments_new_master_rdata_valid1[0:0] 1'0
sync always
sync init
update \subfragments_new_master_rdata_valid1 $1\subfragments_new_master_rdata_valid1[0:0]
end
- attribute \src "ls180.v:1045.5-1045.48"
- process $proc$ls180.v:1045$2046
+ attribute \src "ls180.v:105.11-105.50"
+ process $proc$ls180.v:105$1650
+ assign { } { }
+ assign $0\libresocsim_libresoc_jtag_wb_bte[1:0] 2'00
+ sync always
+ update \libresocsim_libresoc_jtag_wb_bte $0\libresocsim_libresoc_jtag_wb_bte[1:0]
+ sync init
+ end
+ attribute \src "ls180.v:1050.5-1050.48"
+ process $proc$ls180.v:1050$2054
assign { } { }
assign $1\subfragments_new_master_rdata_valid2[0:0] 1'0
sync always
sync init
update \subfragments_new_master_rdata_valid2 $1\subfragments_new_master_rdata_valid2[0:0]
end
- attribute \src "ls180.v:1046.5-1046.48"
- process $proc$ls180.v:1046$2047
+ attribute \src "ls180.v:1051.5-1051.48"
+ process $proc$ls180.v:1051$2055
assign { } { }
assign $1\subfragments_new_master_rdata_valid3[0:0] 1'0
sync always
sync init
update \subfragments_new_master_rdata_valid3 $1\subfragments_new_master_rdata_valid3[0:0]
end
- attribute \src "ls180.v:1047.5-1047.30"
- process $proc$ls180.v:1047$2048
+ attribute \src "ls180.v:1052.5-1052.30"
+ process $proc$ls180.v:1052$2056
assign { } { }
assign $1\subfragments_state[0:0] 1'0
sync always
sync init
update \subfragments_state $1\subfragments_state[0:0]
end
- attribute \src "ls180.v:1048.5-1048.35"
- process $proc$ls180.v:1048$2049
+ attribute \src "ls180.v:1053.5-1053.35"
+ process $proc$ls180.v:1053$2057
assign { } { }
assign $1\subfragments_next_state[0:0] 1'0
sync always
sync init
update \subfragments_next_state $1\subfragments_next_state[0:0]
end
- attribute \src "ls180.v:1049.5-1049.53"
- process $proc$ls180.v:1049$2050
+ attribute \src "ls180.v:1054.5-1054.53"
+ process $proc$ls180.v:1054$2058
assign { } { }
assign $1\converter_counter_subfragments_next_value[0:0] 1'0
sync always
sync init
update \converter_counter_subfragments_next_value $1\converter_counter_subfragments_next_value[0:0]
end
- attribute \src "ls180.v:1050.5-1050.56"
- process $proc$ls180.v:1050$2051
+ attribute \src "ls180.v:1055.5-1055.56"
+ process $proc$ls180.v:1055$2059
assign { } { }
assign $1\converter_counter_subfragments_next_value_ce[0:0] 1'0
sync always
sync init
update \converter_counter_subfragments_next_value_ce $1\converter_counter_subfragments_next_value_ce[0:0]
end
- attribute \src "ls180.v:1051.12-1051.47"
- process $proc$ls180.v:1051$2052
+ attribute \src "ls180.v:1056.12-1056.47"
+ process $proc$ls180.v:1056$2060
assign { } { }
assign $1\libresocsim_libresocsim_adr[13:0] 14'00000000000000
sync always
sync init
update \libresocsim_libresocsim_adr $1\libresocsim_libresocsim_adr[13:0]
end
- attribute \src "ls180.v:1052.5-1052.38"
- process $proc$ls180.v:1052$2053
+ attribute \src "ls180.v:1057.5-1057.38"
+ process $proc$ls180.v:1057$2061
assign { } { }
assign $1\libresocsim_libresocsim_we[0:0] 1'0
sync always
sync init
update \libresocsim_libresocsim_we $1\libresocsim_libresocsim_we[0:0]
end
- attribute \src "ls180.v:1053.11-1053.47"
- process $proc$ls180.v:1053$2054
+ attribute \src "ls180.v:1058.11-1058.47"
+ process $proc$ls180.v:1058$2062
assign { } { }
assign $1\libresocsim_libresocsim_dat_w[7:0] 8'00000000
sync always
sync init
update \libresocsim_libresocsim_dat_w $1\libresocsim_libresocsim_dat_w[7:0]
end
- attribute \src "ls180.v:1055.12-1055.56"
- process $proc$ls180.v:1055$2055
+ attribute \src "ls180.v:1060.12-1060.56"
+ process $proc$ls180.v:1060$2063
assign { } { }
assign $0\libresocsim_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000
sync always
update \libresocsim_libresocsim_wishbone_adr $0\libresocsim_libresocsim_wishbone_adr[29:0]
sync init
end
- attribute \src "ls180.v:1056.12-1056.58"
- process $proc$ls180.v:1056$2056
+ attribute \src "ls180.v:1061.12-1061.58"
+ process $proc$ls180.v:1061$2064
assign { } { }
assign $0\libresocsim_libresocsim_wishbone_dat_w[31:0] 0
sync always
update \libresocsim_libresocsim_wishbone_dat_w $0\libresocsim_libresocsim_wishbone_dat_w[31:0]
sync init
end
- attribute \src "ls180.v:1057.12-1057.58"
- process $proc$ls180.v:1057$2057
+ attribute \src "ls180.v:1062.12-1062.58"
+ process $proc$ls180.v:1062$2065
assign { } { }
assign $1\libresocsim_libresocsim_wishbone_dat_r[31:0] 0
sync always
sync init
update \libresocsim_libresocsim_wishbone_dat_r $1\libresocsim_libresocsim_wishbone_dat_r[31:0]
end
- attribute \src "ls180.v:1058.11-1058.54"
- process $proc$ls180.v:1058$2058
+ attribute \src "ls180.v:1063.11-1063.54"
+ process $proc$ls180.v:1063$2066
assign { } { }
assign $0\libresocsim_libresocsim_wishbone_sel[3:0] 4'0000
sync always
update \libresocsim_libresocsim_wishbone_sel $0\libresocsim_libresocsim_wishbone_sel[3:0]
sync init
end
- attribute \src "ls180.v:1059.5-1059.48"
- process $proc$ls180.v:1059$2059
+ attribute \src "ls180.v:1064.5-1064.48"
+ process $proc$ls180.v:1064$2067
assign { } { }
assign $0\libresocsim_libresocsim_wishbone_cyc[0:0] 1'0
sync always
update \libresocsim_libresocsim_wishbone_cyc $0\libresocsim_libresocsim_wishbone_cyc[0:0]
sync init
end
- attribute \src "ls180.v:1060.5-1060.48"
- process $proc$ls180.v:1060$2060
+ attribute \src "ls180.v:1065.5-1065.48"
+ process $proc$ls180.v:1065$2068
assign { } { }
assign $0\libresocsim_libresocsim_wishbone_stb[0:0] 1'0
sync always
update \libresocsim_libresocsim_wishbone_stb $0\libresocsim_libresocsim_wishbone_stb[0:0]
sync init
end
- attribute \src "ls180.v:1061.5-1061.48"
- process $proc$ls180.v:1061$2061
+ attribute \src "ls180.v:1066.5-1066.48"
+ process $proc$ls180.v:1066$2069
assign { } { }
assign $1\libresocsim_libresocsim_wishbone_ack[0:0] 1'0
sync always
sync init
update \libresocsim_libresocsim_wishbone_ack $1\libresocsim_libresocsim_wishbone_ack[0:0]
end
- attribute \src "ls180.v:1062.5-1062.47"
- process $proc$ls180.v:1062$2062
+ attribute \src "ls180.v:1067.5-1067.47"
+ process $proc$ls180.v:1067$2070
assign { } { }
assign $0\libresocsim_libresocsim_wishbone_we[0:0] 1'0
sync always
update \libresocsim_libresocsim_wishbone_we $0\libresocsim_libresocsim_wishbone_we[0:0]
sync init
end
- attribute \src "ls180.v:1065.12-1065.69"
- process $proc$ls180.v:1065$2063
+ attribute \src "ls180.v:1070.12-1070.69"
+ process $proc$ls180.v:1070$2071
assign { } { }
assign $0\libresocsim_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \libresocsim_libresocsim_converted_interface_dat_r $0\libresocsim_libresocsim_converted_interface_dat_r[63:0]
sync init
end
- attribute \src "ls180.v:1069.5-1069.59"
- process $proc$ls180.v:1069$2064
+ attribute \src "ls180.v:1074.5-1074.59"
+ process $proc$ls180.v:1074$2072
assign { } { }
assign $0\libresocsim_libresocsim_converted_interface_ack[0:0] 1'0
sync always
update \libresocsim_libresocsim_converted_interface_ack $0\libresocsim_libresocsim_converted_interface_ack[0:0]
sync init
end
- attribute \src "ls180.v:1073.5-1073.59"
- process $proc$ls180.v:1073$2065
+ attribute \src "ls180.v:1078.5-1078.59"
+ process $proc$ls180.v:1078$2073
assign { } { }
assign $0\libresocsim_libresocsim_converted_interface_err[0:0] 1'0
sync always
update \libresocsim_libresocsim_converted_interface_err $0\libresocsim_libresocsim_converted_interface_err[0:0]
sync init
end
- attribute \src "ls180.v:1076.12-1076.44"
- process $proc$ls180.v:1076$2066
+ attribute \src "ls180.v:1081.12-1081.44"
+ process $proc$ls180.v:1081$2074
assign { } { }
assign $1\libresocsim_shared_dat_r[31:0] 0
sync always
sync init
update \libresocsim_shared_dat_r $1\libresocsim_shared_dat_r[31:0]
end
- attribute \src "ls180.v:1080.5-1080.34"
- process $proc$ls180.v:1080$2067
+ attribute \src "ls180.v:1085.5-1085.34"
+ process $proc$ls180.v:1085$2075
assign { } { }
assign $1\libresocsim_shared_ack[0:0] 1'0
sync always
sync init
update \libresocsim_shared_ack $1\libresocsim_shared_ack[0:0]
end
- attribute \src "ls180.v:1086.11-1086.35"
- process $proc$ls180.v:1086$2068
+ attribute \src "ls180.v:1091.11-1091.35"
+ process $proc$ls180.v:1091$2076
assign { } { }
assign $1\libresocsim_grant[1:0] 2'00
sync always
sync init
update \libresocsim_grant $1\libresocsim_grant[1:0]
end
- attribute \src "ls180.v:1087.11-1087.39"
- process $proc$ls180.v:1087$2069
+ attribute \src "ls180.v:1092.11-1092.39"
+ process $proc$ls180.v:1092$2077
assign { } { }
assign $1\libresocsim_slave_sel[5:0] 6'000000
sync always
sync init
update \libresocsim_slave_sel $1\libresocsim_slave_sel[5:0]
end
- attribute \src "ls180.v:1088.11-1088.41"
- process $proc$ls180.v:1088$2070
+ attribute \src "ls180.v:1093.11-1093.41"
+ process $proc$ls180.v:1093$2078
assign { } { }
assign $1\libresocsim_slave_sel_r[5:0] 6'000000
sync always
sync init
update \libresocsim_slave_sel_r $1\libresocsim_slave_sel_r[5:0]
end
- attribute \src "ls180.v:1089.5-1089.29"
- process $proc$ls180.v:1089$2071
+ attribute \src "ls180.v:1094.5-1094.29"
+ process $proc$ls180.v:1094$2079
assign { } { }
assign $1\libresocsim_error[0:0] 1'0
sync always
sync init
update \libresocsim_error $1\libresocsim_error[0:0]
end
- attribute \src "ls180.v:1092.12-1092.43"
- process $proc$ls180.v:1092$2072
+ attribute \src "ls180.v:1097.12-1097.43"
+ process $proc$ls180.v:1097$2080
assign { } { }
assign $1\libresocsim_count[19:0] 20'11110100001001000000
sync always
sync init
update \libresocsim_count $1\libresocsim_count[19:0]
end
- attribute \src "ls180.v:1096.11-1096.55"
- process $proc$ls180.v:1096$2073
+ attribute \src "ls180.v:1101.11-1101.55"
+ process $proc$ls180.v:1101$2081
assign { } { }
assign $1\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface0_bank_bus_dat_r $1\libresocsim_interface0_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:1137.11-1137.55"
- process $proc$ls180.v:1137$2074
+ attribute \src "ls180.v:1142.11-1142.55"
+ process $proc$ls180.v:1142$2082
assign { } { }
assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:1154.11-1154.55"
- process $proc$ls180.v:1154$2075
+ attribute \src "ls180.v:1159.11-1159.55"
+ process $proc$ls180.v:1159$2083
assign { } { }
assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:116.12-116.69"
- process $proc$ls180.v:116$1644
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] 16'0000000000000000
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_obj_gpio_o $1\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0]
- end
- attribute \src "ls180.v:117.12-117.70"
- process $proc$ls180.v:117$1645
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] 16'0000000000000000
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_obj_gpio_oe $1\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0]
- end
- attribute \src "ls180.v:1171.11-1171.55"
- process $proc$ls180.v:1171$2076
+ attribute \src "ls180.v:1176.11-1176.55"
+ process $proc$ls180.v:1176$2084
assign { } { }
assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:118.5-118.68"
- process $proc$ls180.v:118$1646
- assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_obj_spimaster_clk[0:0] 1'0
- sync always
- update \libresocsim_libresoc_constraintmanager_obj_spimaster_clk $0\libresocsim_libresoc_constraintmanager_obj_spimaster_clk[0:0]
- sync init
- end
- attribute \src "ls180.v:1184.11-1184.55"
- process $proc$ls180.v:1184$2077
+ attribute \src "ls180.v:1189.11-1189.55"
+ process $proc$ls180.v:1189$2085
assign { } { }
assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:119.5-119.69"
- process $proc$ls180.v:119$1647
- assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_obj_spimaster_mosi[0:0] 1'0
- sync always
- update \libresocsim_libresoc_constraintmanager_obj_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_obj_spimaster_mosi[0:0]
- sync init
- end
- attribute \src "ls180.v:120.5-120.69"
- process $proc$ls180.v:120$1648
+ attribute \src "ls180.v:121.5-121.58"
+ process $proc$ls180.v:121$1651
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
sync always
- update \libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n[0:0]
sync init
+ update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
end
- attribute \src "ls180.v:122.5-122.62"
- process $proc$ls180.v:122$1649
+ attribute \src "ls180.v:122.5-122.58"
+ process $proc$ls180.v:122$1652
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1
+ assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_obj_uart_tx $1\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0]
end
- attribute \src "ls180.v:1225.11-1225.55"
- process $proc$ls180.v:1225$2078
+ attribute \src "ls180.v:1230.11-1230.55"
+ process $proc$ls180.v:1230$2086
assign { } { }
assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:123.5-123.62"
- process $proc$ls180.v:123$1650
- assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_obj_uart_rx[0:0] 1'0
- sync always
- update \libresocsim_libresoc_constraintmanager_obj_uart_rx $0\libresocsim_libresoc_constraintmanager_obj_uart_rx[0:0]
- sync init
- end
- attribute \src "ls180.v:125.12-125.70"
- process $proc$ls180.v:125$1651
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] 13'0000000000000
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_a $1\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0]
- end
- attribute \src "ls180.v:127.12-127.73"
- process $proc$ls180.v:127$1652
+ attribute \src "ls180.v:124.12-124.65"
+ process $proc$ls180.v:124$1653
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] 16'0000000000000000
+ assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0]
+ update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
end
- attribute \src "ls180.v:128.5-128.66"
- process $proc$ls180.v:128$1653
+ attribute \src "ls180.v:125.12-125.66"
+ process $proc$ls180.v:125$1654
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0]
+ update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
end
- attribute \src "ls180.v:129.5-129.65"
- process $proc$ls180.v:129$1654
+ attribute \src "ls180.v:129.5-129.64"
+ process $proc$ls180.v:129$1655
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] 1'0
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_we_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0]
end
- attribute \src "ls180.v:1290.11-1290.55"
- process $proc$ls180.v:1290$2079
+ attribute \src "ls180.v:1295.11-1295.55"
+ process $proc$ls180.v:1295$2087
assign { } { }
assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:130.5-130.66"
- process $proc$ls180.v:130$1655
+ attribute \src "ls180.v:130.5-130.65"
+ process $proc$ls180.v:130$1656
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] 1'0
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0]
end
- attribute \src "ls180.v:131.5-131.66"
- process $proc$ls180.v:131$1656
+ attribute \src "ls180.v:131.5-131.65"
+ process $proc$ls180.v:131$1657
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] 1'0
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0]
end
- attribute \src "ls180.v:1315.11-1315.55"
- process $proc$ls180.v:1315$2080
+ attribute \src "ls180.v:1320.11-1320.55"
+ process $proc$ls180.v:1320$2088
assign { } { }
assign $1\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000
sync always
sync init
update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:132.5-132.65"
- process $proc$ls180.v:132$1657
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0]
- end
- attribute \src "ls180.v:133.5-133.64"
+ attribute \src "ls180.v:133.12-133.66"
process $proc$ls180.v:133$1658
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_cke $1\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
end
- attribute \src "ls180.v:1337.11-1337.35"
- process $proc$ls180.v:1337$2081
+ attribute \src "ls180.v:1342.11-1342.35"
+ process $proc$ls180.v:1342$2089
assign { } { }
assign $1\libresocsim_state[1:0] 2'00
sync always
sync init
update \libresocsim_state $1\libresocsim_state[1:0]
end
- attribute \src "ls180.v:1338.11-1338.40"
- process $proc$ls180.v:1338$2082
+ attribute \src "ls180.v:1343.11-1343.40"
+ process $proc$ls180.v:1343$2090
assign { } { }
assign $1\libresocsim_next_state[1:0] 2'00
sync always
sync init
update \libresocsim_next_state $1\libresocsim_next_state[1:0]
end
- attribute \src "ls180.v:1339.11-1339.71"
- process $proc$ls180.v:1339$2083
+ attribute \src "ls180.v:1344.11-1344.71"
+ process $proc$ls180.v:1344$2091
assign { } { }
assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000
sync always
sync init
update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0]
end
- attribute \src "ls180.v:134.11-134.69"
- process $proc$ls180.v:134$1659
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] 2'00
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_ba $1\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0]
- end
- attribute \src "ls180.v:1340.5-1340.68"
- process $proc$ls180.v:1340$2084
+ attribute \src "ls180.v:1345.5-1345.68"
+ process $proc$ls180.v:1345$2092
assign { } { }
assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0
sync always
sync init
update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0]
end
- attribute \src "ls180.v:1341.12-1341.71"
- process $proc$ls180.v:1341$2085
+ attribute \src "ls180.v:1346.12-1346.71"
+ process $proc$ls180.v:1346$2093
assign { } { }
assign $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000
sync always
sync init
update \libresocsim_libresocsim_adr_libresocsim_next_value1 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0]
end
- attribute \src "ls180.v:1342.5-1342.66"
- process $proc$ls180.v:1342$2086
+ attribute \src "ls180.v:1347.5-1347.66"
+ process $proc$ls180.v:1347$2094
assign { } { }
assign $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0
sync always
sync init
update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0]
end
- attribute \src "ls180.v:1343.5-1343.62"
- process $proc$ls180.v:1343$2087
+ attribute \src "ls180.v:1348.5-1348.62"
+ process $proc$ls180.v:1348$2095
assign { } { }
assign $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0
sync always
sync init
update \libresocsim_libresocsim_we_libresocsim_next_value2 $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
end
- attribute \src "ls180.v:1344.5-1344.65"
- process $proc$ls180.v:1344$2088
+ attribute \src "ls180.v:1349.5-1349.65"
+ process $proc$ls180.v:1349$2096
assign { } { }
assign $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0
sync always
sync init
update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
end
- attribute \src "ls180.v:1345.5-1345.28"
- process $proc$ls180.v:1345$2089
+ attribute \src "ls180.v:135.12-135.69"
+ process $proc$ls180.v:135$1659
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
+ end
+ attribute \src "ls180.v:1350.5-1350.28"
+ process $proc$ls180.v:1350$2097
assign { } { }
assign $1\rhs_array_muxed0[0:0] 1'0
sync always
sync init
update \rhs_array_muxed0 $1\rhs_array_muxed0[0:0]
end
- attribute \src "ls180.v:1346.12-1346.36"
- process $proc$ls180.v:1346$2090
+ attribute \src "ls180.v:1351.12-1351.36"
+ process $proc$ls180.v:1351$2098
assign { } { }
assign $1\rhs_array_muxed1[12:0] 13'0000000000000
sync always
sync init
update \rhs_array_muxed1 $1\rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:1347.11-1347.34"
- process $proc$ls180.v:1347$2091
+ attribute \src "ls180.v:1352.11-1352.34"
+ process $proc$ls180.v:1352$2099
assign { } { }
assign $1\rhs_array_muxed2[1:0] 2'00
sync always
sync init
update \rhs_array_muxed2 $1\rhs_array_muxed2[1:0]
end
- attribute \src "ls180.v:1348.5-1348.28"
- process $proc$ls180.v:1348$2092
+ attribute \src "ls180.v:1353.5-1353.28"
+ process $proc$ls180.v:1353$2100
assign { } { }
assign $1\rhs_array_muxed3[0:0] 1'0
sync always
sync init
update \rhs_array_muxed3 $1\rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:1349.5-1349.28"
- process $proc$ls180.v:1349$2093
+ attribute \src "ls180.v:1354.5-1354.28"
+ process $proc$ls180.v:1354$2101
assign { } { }
assign $1\rhs_array_muxed4[0:0] 1'0
sync always
sync init
update \rhs_array_muxed4 $1\rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:135.11-135.69"
- process $proc$ls180.v:135$1660
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] 2'00
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_obj_sdram_dm $1\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0]
- end
- attribute \src "ls180.v:1350.5-1350.28"
- process $proc$ls180.v:1350$2094
+ attribute \src "ls180.v:1355.5-1355.28"
+ process $proc$ls180.v:1355$2102
assign { } { }
assign $1\rhs_array_muxed5[0:0] 1'0
sync always
sync init
update \rhs_array_muxed5 $1\rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:1351.5-1351.26"
- process $proc$ls180.v:1351$2095
+ attribute \src "ls180.v:1356.5-1356.26"
+ process $proc$ls180.v:1356$2103
assign { } { }
assign $1\t_array_muxed0[0:0] 1'0
sync always
sync init
update \t_array_muxed0 $1\t_array_muxed0[0:0]
end
- attribute \src "ls180.v:1352.5-1352.26"
- process $proc$ls180.v:1352$2096
+ attribute \src "ls180.v:1357.5-1357.26"
+ process $proc$ls180.v:1357$2104
assign { } { }
assign $1\t_array_muxed1[0:0] 1'0
sync always
sync init
update \t_array_muxed1 $1\t_array_muxed1[0:0]
end
- attribute \src "ls180.v:1353.5-1353.26"
- process $proc$ls180.v:1353$2097
+ attribute \src "ls180.v:1358.5-1358.26"
+ process $proc$ls180.v:1358$2105
assign { } { }
assign $1\t_array_muxed2[0:0] 1'0
sync always
sync init
update \t_array_muxed2 $1\t_array_muxed2[0:0]
end
- attribute \src "ls180.v:1354.5-1354.28"
- process $proc$ls180.v:1354$2098
+ attribute \src "ls180.v:1359.5-1359.28"
+ process $proc$ls180.v:1359$2106
assign { } { }
assign $1\rhs_array_muxed6[0:0] 1'0
sync always
sync init
update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:1355.12-1355.36"
- process $proc$ls180.v:1355$2099
+ attribute \src "ls180.v:136.5-136.62"
+ process $proc$ls180.v:136$1660
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
+ end
+ attribute \src "ls180.v:1360.12-1360.36"
+ process $proc$ls180.v:1360$2107
assign { } { }
assign $1\rhs_array_muxed7[12:0] 13'0000000000000
sync always
sync init
update \rhs_array_muxed7 $1\rhs_array_muxed7[12:0]
end
- attribute \src "ls180.v:1356.11-1356.34"
- process $proc$ls180.v:1356$2100
+ attribute \src "ls180.v:1361.11-1361.34"
+ process $proc$ls180.v:1361$2108
assign { } { }
assign $1\rhs_array_muxed8[1:0] 2'00
sync always
sync init
update \rhs_array_muxed8 $1\rhs_array_muxed8[1:0]
end
- attribute \src "ls180.v:1357.5-1357.28"
- process $proc$ls180.v:1357$2101
+ attribute \src "ls180.v:1362.5-1362.28"
+ process $proc$ls180.v:1362$2109
assign { } { }
assign $1\rhs_array_muxed9[0:0] 1'0
sync always
sync init
update \rhs_array_muxed9 $1\rhs_array_muxed9[0:0]
end
- attribute \src "ls180.v:1358.5-1358.29"
- process $proc$ls180.v:1358$2102
+ attribute \src "ls180.v:1363.5-1363.29"
+ process $proc$ls180.v:1363$2110
assign { } { }
assign $1\rhs_array_muxed10[0:0] 1'0
sync always
sync init
update \rhs_array_muxed10 $1\rhs_array_muxed10[0:0]
end
- attribute \src "ls180.v:1359.5-1359.29"
- process $proc$ls180.v:1359$2103
+ attribute \src "ls180.v:1364.5-1364.29"
+ process $proc$ls180.v:1364$2111
assign { } { }
assign $1\rhs_array_muxed11[0:0] 1'0
sync always
sync init
update \rhs_array_muxed11 $1\rhs_array_muxed11[0:0]
end
- attribute \src "ls180.v:136.5-136.23"
- process $proc$ls180.v:136$1661
- assign { } { }
- assign $1\sdram_clock[0:0] 1'0
- sync always
- sync init
- update \sdram_clock $1\sdram_clock[0:0]
- end
- attribute \src "ls180.v:1360.5-1360.26"
- process $proc$ls180.v:1360$2104
+ attribute \src "ls180.v:1365.5-1365.26"
+ process $proc$ls180.v:1365$2112
assign { } { }
assign $1\t_array_muxed3[0:0] 1'0
sync always
sync init
update \t_array_muxed3 $1\t_array_muxed3[0:0]
end
- attribute \src "ls180.v:1361.5-1361.26"
- process $proc$ls180.v:1361$2105
+ attribute \src "ls180.v:1366.5-1366.26"
+ process $proc$ls180.v:1366$2113
assign { } { }
assign $1\t_array_muxed4[0:0] 1'0
sync always
sync init
update \t_array_muxed4 $1\t_array_muxed4[0:0]
end
- attribute \src "ls180.v:1362.5-1362.26"
- process $proc$ls180.v:1362$2106
+ attribute \src "ls180.v:1367.5-1367.26"
+ process $proc$ls180.v:1367$2114
assign { } { }
assign $1\t_array_muxed5[0:0] 1'0
sync always
sync init
update \t_array_muxed5 $1\t_array_muxed5[0:0]
end
- attribute \src "ls180.v:1363.12-1363.37"
- process $proc$ls180.v:1363$2107
+ attribute \src "ls180.v:1368.12-1368.37"
+ process $proc$ls180.v:1368$2115
assign { } { }
assign $1\rhs_array_muxed12[21:0] 22'0000000000000000000000
sync always
sync init
update \rhs_array_muxed12 $1\rhs_array_muxed12[21:0]
end
- attribute \src "ls180.v:1364.5-1364.29"
- process $proc$ls180.v:1364$2108
+ attribute \src "ls180.v:1369.5-1369.29"
+ process $proc$ls180.v:1369$2116
assign { } { }
assign $1\rhs_array_muxed13[0:0] 1'0
sync always
sync init
update \rhs_array_muxed13 $1\rhs_array_muxed13[0:0]
end
- attribute \src "ls180.v:1365.5-1365.29"
- process $proc$ls180.v:1365$2109
+ attribute \src "ls180.v:137.5-137.61"
+ process $proc$ls180.v:137$1661
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
+ end
+ attribute \src "ls180.v:1370.5-1370.29"
+ process $proc$ls180.v:1370$2117
assign { } { }
assign $1\rhs_array_muxed14[0:0] 1'0
sync always
sync init
update \rhs_array_muxed14 $1\rhs_array_muxed14[0:0]
end
- attribute \src "ls180.v:1366.12-1366.37"
- process $proc$ls180.v:1366$2110
+ attribute \src "ls180.v:1371.12-1371.37"
+ process $proc$ls180.v:1371$2118
assign { } { }
assign $1\rhs_array_muxed15[21:0] 22'0000000000000000000000
sync always
sync init
update \rhs_array_muxed15 $1\rhs_array_muxed15[21:0]
end
- attribute \src "ls180.v:1367.5-1367.29"
- process $proc$ls180.v:1367$2111
+ attribute \src "ls180.v:1372.5-1372.29"
+ process $proc$ls180.v:1372$2119
assign { } { }
assign $1\rhs_array_muxed16[0:0] 1'0
sync always
sync init
update \rhs_array_muxed16 $1\rhs_array_muxed16[0:0]
end
- attribute \src "ls180.v:1368.5-1368.29"
- process $proc$ls180.v:1368$2112
+ attribute \src "ls180.v:1373.5-1373.29"
+ process $proc$ls180.v:1373$2120
assign { } { }
assign $1\rhs_array_muxed17[0:0] 1'0
sync always
sync init
update \rhs_array_muxed17 $1\rhs_array_muxed17[0:0]
end
- attribute \src "ls180.v:1369.12-1369.37"
- process $proc$ls180.v:1369$2113
+ attribute \src "ls180.v:1374.12-1374.37"
+ process $proc$ls180.v:1374$2121
assign { } { }
assign $1\rhs_array_muxed18[21:0] 22'0000000000000000000000
sync always
sync init
update \rhs_array_muxed18 $1\rhs_array_muxed18[21:0]
end
- attribute \src "ls180.v:1370.5-1370.29"
- process $proc$ls180.v:1370$2114
+ attribute \src "ls180.v:1375.5-1375.29"
+ process $proc$ls180.v:1375$2122
assign { } { }
assign $1\rhs_array_muxed19[0:0] 1'0
sync always
sync init
update \rhs_array_muxed19 $1\rhs_array_muxed19[0:0]
end
- attribute \src "ls180.v:1371.5-1371.29"
- process $proc$ls180.v:1371$2115
+ attribute \src "ls180.v:1376.5-1376.29"
+ process $proc$ls180.v:1376$2123
assign { } { }
assign $1\rhs_array_muxed20[0:0] 1'0
sync always
sync init
update \rhs_array_muxed20 $1\rhs_array_muxed20[0:0]
end
- attribute \src "ls180.v:1372.12-1372.37"
- process $proc$ls180.v:1372$2116
+ attribute \src "ls180.v:1377.12-1377.37"
+ process $proc$ls180.v:1377$2124
assign { } { }
assign $1\rhs_array_muxed21[21:0] 22'0000000000000000000000
sync always
sync init
update \rhs_array_muxed21 $1\rhs_array_muxed21[21:0]
end
- attribute \src "ls180.v:1373.5-1373.29"
- process $proc$ls180.v:1373$2117
+ attribute \src "ls180.v:1378.5-1378.29"
+ process $proc$ls180.v:1378$2125
assign { } { }
assign $1\rhs_array_muxed22[0:0] 1'0
sync always
sync init
update \rhs_array_muxed22 $1\rhs_array_muxed22[0:0]
end
- attribute \src "ls180.v:1374.5-1374.29"
- process $proc$ls180.v:1374$2118
+ attribute \src "ls180.v:1379.5-1379.29"
+ process $proc$ls180.v:1379$2126
assign { } { }
assign $1\rhs_array_muxed23[0:0] 1'0
sync always
sync init
update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:1375.12-1375.37"
- process $proc$ls180.v:1375$2119
+ attribute \src "ls180.v:138.5-138.62"
+ process $proc$ls180.v:138$1662
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
+ end
+ attribute \src "ls180.v:1380.12-1380.37"
+ process $proc$ls180.v:1380$2127
assign { } { }
assign $1\rhs_array_muxed24[28:0] 29'00000000000000000000000000000
sync always
sync init
update \rhs_array_muxed24 $1\rhs_array_muxed24[28:0]
end
- attribute \src "ls180.v:1376.12-1376.37"
- process $proc$ls180.v:1376$2120
+ attribute \src "ls180.v:1381.12-1381.37"
+ process $proc$ls180.v:1381$2128
assign { } { }
assign $1\rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \rhs_array_muxed25 $1\rhs_array_muxed25[63:0]
end
- attribute \src "ls180.v:1377.11-1377.35"
- process $proc$ls180.v:1377$2121
+ attribute \src "ls180.v:1382.11-1382.35"
+ process $proc$ls180.v:1382$2129
assign { } { }
assign $1\rhs_array_muxed26[7:0] 8'00000000
sync always
sync init
update \rhs_array_muxed26 $1\rhs_array_muxed26[7:0]
end
- attribute \src "ls180.v:1378.5-1378.29"
- process $proc$ls180.v:1378$2122
+ attribute \src "ls180.v:1383.5-1383.29"
+ process $proc$ls180.v:1383$2130
assign { } { }
assign $1\rhs_array_muxed27[0:0] 1'0
sync always
sync init
update \rhs_array_muxed27 $1\rhs_array_muxed27[0:0]
end
- attribute \src "ls180.v:1379.5-1379.29"
- process $proc$ls180.v:1379$2123
+ attribute \src "ls180.v:1384.5-1384.29"
+ process $proc$ls180.v:1384$2131
assign { } { }
assign $1\rhs_array_muxed28[0:0] 1'0
sync always
sync init
update \rhs_array_muxed28 $1\rhs_array_muxed28[0:0]
end
- attribute \src "ls180.v:1380.5-1380.29"
- process $proc$ls180.v:1380$2124
+ attribute \src "ls180.v:1385.5-1385.29"
+ process $proc$ls180.v:1385$2132
assign { } { }
assign $1\rhs_array_muxed29[0:0] 1'0
sync always
sync init
update \rhs_array_muxed29 $1\rhs_array_muxed29[0:0]
end
- attribute \src "ls180.v:1381.11-1381.35"
- process $proc$ls180.v:1381$2125
+ attribute \src "ls180.v:1386.11-1386.35"
+ process $proc$ls180.v:1386$2133
assign { } { }
assign $1\rhs_array_muxed30[2:0] 3'000
sync always
sync init
update \rhs_array_muxed30 $1\rhs_array_muxed30[2:0]
end
- attribute \src "ls180.v:1382.11-1382.35"
- process $proc$ls180.v:1382$2126
+ attribute \src "ls180.v:1387.11-1387.35"
+ process $proc$ls180.v:1387$2134
assign { } { }
assign $1\rhs_array_muxed31[1:0] 2'00
sync always
sync init
update \rhs_array_muxed31 $1\rhs_array_muxed31[1:0]
end
- attribute \src "ls180.v:1383.11-1383.30"
- process $proc$ls180.v:1383$2127
+ attribute \src "ls180.v:1388.11-1388.30"
+ process $proc$ls180.v:1388$2135
assign { } { }
assign $1\array_muxed0[1:0] 2'00
sync always
sync init
update \array_muxed0 $1\array_muxed0[1:0]
end
- attribute \src "ls180.v:1384.12-1384.32"
- process $proc$ls180.v:1384$2128
+ attribute \src "ls180.v:1389.12-1389.32"
+ process $proc$ls180.v:1389$2136
assign { } { }
assign $1\array_muxed1[12:0] 13'0000000000000
sync always
sync init
update \array_muxed1 $1\array_muxed1[12:0]
end
- attribute \src "ls180.v:1385.5-1385.24"
- process $proc$ls180.v:1385$2129
+ attribute \src "ls180.v:139.5-139.62"
+ process $proc$ls180.v:139$1663
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
+ end
+ attribute \src "ls180.v:1390.5-1390.24"
+ process $proc$ls180.v:1390$2137
assign { } { }
assign $1\array_muxed2[0:0] 1'0
sync always
sync init
update \array_muxed2 $1\array_muxed2[0:0]
end
- attribute \src "ls180.v:1386.5-1386.24"
- process $proc$ls180.v:1386$2130
+ attribute \src "ls180.v:1391.5-1391.24"
+ process $proc$ls180.v:1391$2138
assign { } { }
assign $1\array_muxed3[0:0] 1'0
sync always
sync init
update \array_muxed3 $1\array_muxed3[0:0]
end
- attribute \src "ls180.v:1387.5-1387.24"
- process $proc$ls180.v:1387$2131
+ attribute \src "ls180.v:1392.5-1392.24"
+ process $proc$ls180.v:1392$2139
assign { } { }
assign $1\array_muxed4[0:0] 1'0
sync always
sync init
update \array_muxed4 $1\array_muxed4[0:0]
end
- attribute \src "ls180.v:1388.5-1388.24"
- process $proc$ls180.v:1388$2132
+ attribute \src "ls180.v:1393.5-1393.24"
+ process $proc$ls180.v:1393$2140
assign { } { }
assign $1\array_muxed5[0:0] 1'0
sync always
sync init
update \array_muxed5 $1\array_muxed5[0:0]
end
- attribute \src "ls180.v:1389.5-1389.24"
- process $proc$ls180.v:1389$2133
+ attribute \src "ls180.v:1394.5-1394.24"
+ process $proc$ls180.v:1394$2141
assign { } { }
assign $1\array_muxed6[0:0] 1'0
sync always
sync init
update \array_muxed6 $1\array_muxed6[0:0]
end
- attribute \src "ls180.v:1446.32-1446.44"
- process $proc$ls180.v:1446$2134
+ attribute \src "ls180.v:140.5-140.61"
+ process $proc$ls180.v:140$1664
assign { } { }
- assign $1\regs0[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0
sync always
sync init
- update \regs0 $1\regs0[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
end
- attribute \src "ls180.v:1447.32-1447.44"
- process $proc$ls180.v:1447$2135
+ attribute \src "ls180.v:141.5-141.60"
+ process $proc$ls180.v:141$1665
assign { } { }
- assign $1\regs1[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0
sync always
sync init
- update \regs1 $1\regs1[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
end
- attribute \src "ls180.v:147.5-147.35"
- process $proc$ls180.v:147$1662
+ attribute \src "ls180.v:142.11-142.65"
+ process $proc$ls180.v:142$1666
assign { } { }
- assign $1\libresocsim_ram_bus_ack[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00
sync always
sync init
- update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
end
- attribute \src "ls180.v:1507.1-1512.4"
- process $proc$ls180.v:1507$23
+ attribute \src "ls180.v:143.11-143.65"
+ process $proc$ls180.v:143$1667
assign { } { }
- assign $0\libresocsim_libresoc_interrupt[15:0] [12:2] 11'00000000000
- assign $0\libresocsim_libresoc_interrupt[15:0] [15:13] \eint
- assign $0\libresocsim_libresoc_interrupt[15:0] [0] \libresocsim_irq
- assign $0\libresocsim_libresoc_interrupt[15:0] [1] \irq
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00
sync always
- update \libresocsim_libresoc_interrupt $0\libresocsim_libresoc_interrupt[15:0]
+ sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
end
- attribute \src "ls180.v:151.5-151.35"
- process $proc$ls180.v:151$1663
+ attribute \src "ls180.v:144.5-144.62"
+ process $proc$ls180.v:144$1668
assign { } { }
- assign $0\libresocsim_ram_bus_err[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0
sync always
- update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0]
sync init
+ update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
end
- attribute \src "ls180.v:1514.1-1524.4"
- process $proc$ls180.v:1514$25
+ attribute \src "ls180.v:1451.32-1451.44"
+ process $proc$ls180.v:1451$2142
assign { } { }
- assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] 0
- attribute \src "ls180.v:1516.2-1523.9"
+ assign $1\regs0[0:0] 1'0
+ sync always
+ sync init
+ update \regs0 $1\regs0[0:0]
+ end
+ attribute \src "ls180.v:1452.32-1452.44"
+ process $proc$ls180.v:1452$2143
+ assign { } { }
+ assign $1\regs1[0:0] 1'0
+ sync always
+ sync init
+ update \regs1 $1\regs1[0:0]
+ end
+ attribute \src "ls180.v:1506.1-1511.4"
+ process $proc$ls180.v:1506$23
+ assign { } { }
+ assign { } { }
+ assign $0\eint_tmp[2:0] [0] \libresocsim_libresoc_constraintmanager_eint_0
+ assign $0\eint_tmp[2:0] [1] \libresocsim_libresoc_constraintmanager_eint_1
+ assign $0\eint_tmp[2:0] [2] \libresocsim_libresoc_constraintmanager_eint_2
+ sync always
+ update \eint_tmp $0\eint_tmp[2:0]
+ end
+ attribute \src "ls180.v:151.5-151.35"
+ process $proc$ls180.v:151$1669
+ assign { } { }
+ assign $1\libresocsim_ram_bus_ack[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0]
+ end
+ attribute \src "ls180.v:1518.1-1525.4"
+ process $proc$ls180.v:1518$24
+ assign { } { }
+ assign $0\libresocsim_libresoc_interrupt[15:0] [12:2] 11'00000000000
+ assign $0\libresocsim_libresoc_interrupt[15:0] [13] \eint_tmp [0]
+ assign $0\libresocsim_libresoc_interrupt[15:0] [14] \eint_tmp [1]
+ assign $0\libresocsim_libresoc_interrupt[15:0] [15] \eint_tmp [2]
+ assign $0\libresocsim_libresoc_interrupt[15:0] [0] \libresocsim_irq
+ assign $0\libresocsim_libresoc_interrupt[15:0] [1] \irq
+ sync always
+ update \libresocsim_libresoc_interrupt $0\libresocsim_libresoc_interrupt[15:0]
+ end
+ attribute \src "ls180.v:1527.1-1537.4"
+ process $proc$ls180.v:1527$26
+ assign { } { }
+ assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] 0
+ attribute \src "ls180.v:1529.2-1536.9"
switch \converter0_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \libresocsim_libresoc_xics_icp_dat_w $0\libresocsim_libresoc_xics_icp_dat_w[31:0]
end
- attribute \src "ls180.v:1526.1-1572.4"
- process $proc$ls180.v:1526$26
+ attribute \src "ls180.v:1539.1-1585.4"
+ process $proc$ls180.v:1539$27
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0
+ assign { } { }
+ assign $0\converter0_counter_subfragments_converter0_next_value[0:0] 1'0
assign $0\converter0_skip[0:0] 1'0
+ assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0
assign $0\libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000
- assign $0\interface0_converted_interface_ack[0:0] 1'0
assign $0\libresocsim_libresoc_xics_icp_sel[3:0] 4'0000
assign $0\libresocsim_libresoc_xics_icp_cyc[0:0] 1'0
assign $0\libresocsim_libresoc_xics_icp_stb[0:0] 1'0
+ assign $0\interface0_converted_interface_ack[0:0] 1'0
assign $0\libresocsim_libresoc_xics_icp_we[0:0] 1'0
- assign { } { }
- assign $0\converter0_counter_subfragments_converter0_next_value[0:0] 1'0
assign $0\subfragments_converter0_next_state[0:0] \subfragments_converter0_state
- attribute \src "ls180.v:1538.2-1571.9"
+ attribute \src "ls180.v:1551.2-1584.9"
switch \subfragments_converter0_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\libresocsim_libresoc_xics_icp_adr[29:0] { \interface0_converted_interface_adr [28:0] \converter0_counter }
- attribute \src "ls180.v:1541.4-1548.11"
+ attribute \src "ls180.v:1554.4-1561.11"
switch \converter0_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\libresocsim_libresoc_xics_icp_sel[3:0] \interface0_converted_interface_sel [7:4]
case
end
- attribute \src "ls180.v:1549.4-1562.7"
- switch $and$ls180.v:1549$27_Y
- attribute \src "ls180.v:1549.8-1549.81"
+ attribute \src "ls180.v:1562.4-1575.7"
+ switch $and$ls180.v:1562$28_Y
+ attribute \src "ls180.v:1562.8-1562.81"
case 1'1
- assign $0\converter0_skip[0:0] $eq$ls180.v:1550$28_Y
+ assign $0\converter0_skip[0:0] $eq$ls180.v:1563$29_Y
assign $0\libresocsim_libresoc_xics_icp_we[0:0] \interface0_converted_interface_we
- assign $0\libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:1552$29_Y
- assign $0\libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:1553$30_Y
- attribute \src "ls180.v:1554.5-1561.8"
- switch $or$ls180.v:1554$31_Y
- attribute \src "ls180.v:1554.9-1554.62"
+ assign $0\libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:1565$30_Y
+ assign $0\libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:1566$31_Y
+ attribute \src "ls180.v:1567.5-1574.8"
+ switch $or$ls180.v:1567$32_Y
+ attribute \src "ls180.v:1567.9-1567.62"
case 1'1
- assign $0\converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1555$32_Y
+ assign $0\converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1568$33_Y
assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:1557.6-1560.9"
- switch $eq$ls180.v:1557$33_Y
- attribute \src "ls180.v:1557.10-1557.38"
+ attribute \src "ls180.v:1570.6-1573.9"
+ switch $eq$ls180.v:1570$34_Y
+ attribute \src "ls180.v:1570.10-1570.38"
case 1'1
assign $0\interface0_converted_interface_ack[0:0] 1'1
assign $0\subfragments_converter0_next_state[0:0] 1'0
case
assign $0\converter0_counter_subfragments_converter0_next_value[0:0] 1'0
assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:1567.4-1569.7"
- switch $and$ls180.v:1567$34_Y
- attribute \src "ls180.v:1567.8-1567.81"
+ attribute \src "ls180.v:1580.4-1582.7"
+ switch $and$ls180.v:1580$35_Y
+ attribute \src "ls180.v:1580.8-1580.81"
case 1'1
assign $0\subfragments_converter0_next_state[0:0] 1'1
case
update \converter0_counter_subfragments_converter0_next_value $0\converter0_counter_subfragments_converter0_next_value[0:0]
update \converter0_counter_subfragments_converter0_next_value_ce $0\converter0_counter_subfragments_converter0_next_value_ce[0:0]
end
- attribute \src "ls180.v:154.11-154.32"
- process $proc$ls180.v:154$1664
- assign { } { }
- assign $1\libresocsim_we[7:0] 8'00000000
- sync always
- sync init
- update \libresocsim_we $1\libresocsim_we[7:0]
- end
- attribute \src "ls180.v:156.12-156.44"
- process $proc$ls180.v:156$1665
+ attribute \src "ls180.v:155.5-155.35"
+ process $proc$ls180.v:155$1670
assign { } { }
- assign $1\libresocsim_load_storage[31:0] 0
+ assign $0\libresocsim_ram_bus_err[0:0] 1'0
sync always
+ update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0]
sync init
- update \libresocsim_load_storage $1\libresocsim_load_storage[31:0]
end
- attribute \src "ls180.v:157.5-157.31"
- process $proc$ls180.v:157$1666
+ attribute \src "ls180.v:158.11-158.32"
+ process $proc$ls180.v:158$1671
assign { } { }
- assign $1\libresocsim_load_re[0:0] 1'0
+ assign $1\libresocsim_we[7:0] 8'00000000
sync always
sync init
- update \libresocsim_load_re $1\libresocsim_load_re[0:0]
+ update \libresocsim_we $1\libresocsim_we[7:0]
end
- attribute \src "ls180.v:1574.1-1584.4"
- process $proc$ls180.v:1574$36
+ attribute \src "ls180.v:1587.1-1597.4"
+ process $proc$ls180.v:1587$37
assign { } { }
assign $0\libresocsim_libresoc_xics_ics_dat_w[31:0] 0
- attribute \src "ls180.v:1576.2-1583.9"
+ attribute \src "ls180.v:1589.2-1596.9"
switch \converter1_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \libresocsim_libresoc_xics_ics_dat_w $0\libresocsim_libresoc_xics_ics_dat_w[31:0]
end
- attribute \src "ls180.v:158.12-158.46"
- process $proc$ls180.v:158$1667
- assign { } { }
- assign $1\libresocsim_reload_storage[31:0] 0
- sync always
- sync init
- update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0]
- end
- attribute \src "ls180.v:1586.1-1632.4"
- process $proc$ls180.v:1586$37
+ attribute \src "ls180.v:1599.1-1645.4"
+ process $proc$ls180.v:1599$38
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0
assign $0\libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000
assign $0\libresocsim_libresoc_xics_ics_sel[3:0] 4'0000
assign $0\libresocsim_libresoc_xics_ics_cyc[0:0] 1'0
assign $0\converter1_skip[0:0] 1'0
assign { } { }
assign $0\converter1_counter_subfragments_converter1_next_value[0:0] 1'0
- assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0
assign $0\subfragments_converter1_next_state[0:0] \subfragments_converter1_state
- attribute \src "ls180.v:1598.2-1631.9"
+ attribute \src "ls180.v:1611.2-1644.9"
switch \subfragments_converter1_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\libresocsim_libresoc_xics_ics_adr[29:0] { \interface1_converted_interface_adr [28:0] \converter1_counter }
- attribute \src "ls180.v:1601.4-1608.11"
+ attribute \src "ls180.v:1614.4-1621.11"
switch \converter1_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\libresocsim_libresoc_xics_ics_sel[3:0] \interface1_converted_interface_sel [7:4]
case
end
- attribute \src "ls180.v:1609.4-1622.7"
- switch $and$ls180.v:1609$38_Y
- attribute \src "ls180.v:1609.8-1609.81"
+ attribute \src "ls180.v:1622.4-1635.7"
+ switch $and$ls180.v:1622$39_Y
+ attribute \src "ls180.v:1622.8-1622.81"
case 1'1
- assign $0\converter1_skip[0:0] $eq$ls180.v:1610$39_Y
+ assign $0\converter1_skip[0:0] $eq$ls180.v:1623$40_Y
assign $0\libresocsim_libresoc_xics_ics_we[0:0] \interface1_converted_interface_we
- assign $0\libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:1612$40_Y
- assign $0\libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:1613$41_Y
- attribute \src "ls180.v:1614.5-1621.8"
- switch $or$ls180.v:1614$42_Y
- attribute \src "ls180.v:1614.9-1614.62"
+ assign $0\libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:1625$41_Y
+ assign $0\libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:1626$42_Y
+ attribute \src "ls180.v:1627.5-1634.8"
+ switch $or$ls180.v:1627$43_Y
+ attribute \src "ls180.v:1627.9-1627.62"
case 1'1
- assign $0\converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1615$43_Y
+ assign $0\converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1628$44_Y
assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:1617.6-1620.9"
- switch $eq$ls180.v:1617$44_Y
- attribute \src "ls180.v:1617.10-1617.38"
+ attribute \src "ls180.v:1630.6-1633.9"
+ switch $eq$ls180.v:1630$45_Y
+ attribute \src "ls180.v:1630.10-1630.38"
case 1'1
assign $0\interface1_converted_interface_ack[0:0] 1'1
assign $0\subfragments_converter1_next_state[0:0] 1'0
case
assign $0\converter1_counter_subfragments_converter1_next_value[0:0] 1'0
assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:1627.4-1629.7"
- switch $and$ls180.v:1627$45_Y
- attribute \src "ls180.v:1627.8-1627.81"
+ attribute \src "ls180.v:1640.4-1642.7"
+ switch $and$ls180.v:1640$46_Y
+ attribute \src "ls180.v:1640.8-1640.81"
case 1'1
assign $0\subfragments_converter1_next_state[0:0] 1'1
case
update \converter1_counter_subfragments_converter1_next_value $0\converter1_counter_subfragments_converter1_next_value[0:0]
update \converter1_counter_subfragments_converter1_next_value_ce $0\converter1_counter_subfragments_converter1_next_value_ce[0:0]
end
- attribute \src "ls180.v:159.5-159.33"
- process $proc$ls180.v:159$1668
+ attribute \src "ls180.v:160.12-160.44"
+ process $proc$ls180.v:160$1672
assign { } { }
- assign $1\libresocsim_reload_re[0:0] 1'0
+ assign $1\libresocsim_load_storage[31:0] 0
sync always
sync init
- update \libresocsim_reload_re $1\libresocsim_reload_re[0:0]
+ update \libresocsim_load_storage $1\libresocsim_load_storage[31:0]
end
- attribute \src "ls180.v:160.5-160.34"
- process $proc$ls180.v:160$1669
+ attribute \src "ls180.v:161.5-161.31"
+ process $proc$ls180.v:161$1673
assign { } { }
- assign $1\libresocsim_en_storage[0:0] 1'0
+ assign $1\libresocsim_load_re[0:0] 1'0
sync always
sync init
- update \libresocsim_en_storage $1\libresocsim_en_storage[0:0]
+ update \libresocsim_load_re $1\libresocsim_load_re[0:0]
end
- attribute \src "ls180.v:161.5-161.29"
- process $proc$ls180.v:161$1670
+ attribute \src "ls180.v:162.12-162.46"
+ process $proc$ls180.v:162$1674
assign { } { }
- assign $1\libresocsim_en_re[0:0] 1'0
+ assign $1\libresocsim_reload_storage[31:0] 0
sync always
sync init
- update \libresocsim_en_re $1\libresocsim_en_re[0:0]
+ update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0]
end
- attribute \src "ls180.v:162.5-162.44"
- process $proc$ls180.v:162$1671
+ attribute \src "ls180.v:163.5-163.33"
+ process $proc$ls180.v:163$1675
assign { } { }
- assign $1\libresocsim_update_value_storage[0:0] 1'0
+ assign $1\libresocsim_reload_re[0:0] 1'0
sync always
sync init
- update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0]
+ update \libresocsim_reload_re $1\libresocsim_reload_re[0:0]
end
- attribute \src "ls180.v:163.5-163.39"
- process $proc$ls180.v:163$1672
+ attribute \src "ls180.v:164.5-164.34"
+ process $proc$ls180.v:164$1676
assign { } { }
- assign $1\libresocsim_update_value_re[0:0] 1'0
+ assign $1\libresocsim_en_storage[0:0] 1'0
sync always
sync init
- update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0]
+ update \libresocsim_en_storage $1\libresocsim_en_storage[0:0]
end
- attribute \src "ls180.v:1634.1-1644.4"
- process $proc$ls180.v:1634$47
+ attribute \src "ls180.v:1647.1-1657.4"
+ process $proc$ls180.v:1647$48
assign { } { }
assign $0\wb_sdram_dat_w[31:0] 0
- attribute \src "ls180.v:1636.2-1643.9"
+ attribute \src "ls180.v:1649.2-1656.9"
switch \socbushandler_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \wb_sdram_dat_w $0\wb_sdram_dat_w[31:0]
end
- attribute \src "ls180.v:164.12-164.44"
- process $proc$ls180.v:164$1673
+ attribute \src "ls180.v:165.5-165.29"
+ process $proc$ls180.v:165$1677
assign { } { }
- assign $1\libresocsim_value_status[31:0] 0
+ assign $1\libresocsim_en_re[0:0] 1'0
sync always
sync init
- update \libresocsim_value_status $1\libresocsim_value_status[31:0]
+ update \libresocsim_en_re $1\libresocsim_en_re[0:0]
end
- attribute \src "ls180.v:1646.1-1692.4"
- process $proc$ls180.v:1646$48
+ attribute \src "ls180.v:1659.1-1705.4"
+ process $proc$ls180.v:1659$49
assign { } { }
assign { } { }
assign { } { }
assign $0\wb_sdram_we[0:0] 1'0
assign { } { }
assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0
- assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'0
assign $0\wb_sdram_adr[29:0] 30'000000000000000000000000000000
+ assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'0
assign $0\socbushandler_converted_interface_ack[0:0] 1'0
assign $0\subfragments_converter2_next_state[0:0] \subfragments_converter2_state
- attribute \src "ls180.v:1658.2-1691.9"
+ attribute \src "ls180.v:1671.2-1704.9"
switch \subfragments_converter2_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\wb_sdram_adr[29:0] { \socbushandler_converted_interface_adr [28:0] \socbushandler_counter }
- attribute \src "ls180.v:1661.4-1668.11"
+ attribute \src "ls180.v:1674.4-1681.11"
switch \socbushandler_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\wb_sdram_sel[3:0] \socbushandler_converted_interface_sel [7:4]
case
end
- attribute \src "ls180.v:1669.4-1682.7"
- switch $and$ls180.v:1669$49_Y
- attribute \src "ls180.v:1669.8-1669.87"
+ attribute \src "ls180.v:1682.4-1695.7"
+ switch $and$ls180.v:1682$50_Y
+ attribute \src "ls180.v:1682.8-1682.87"
case 1'1
- assign $0\socbushandler_skip[0:0] $eq$ls180.v:1670$50_Y
+ assign $0\socbushandler_skip[0:0] $eq$ls180.v:1683$51_Y
assign $0\wb_sdram_we[0:0] \socbushandler_converted_interface_we
- assign $0\wb_sdram_cyc[0:0] $not$ls180.v:1672$51_Y
- assign $0\wb_sdram_stb[0:0] $not$ls180.v:1673$52_Y
- attribute \src "ls180.v:1674.5-1681.8"
- switch $or$ls180.v:1674$53_Y
- attribute \src "ls180.v:1674.9-1674.44"
+ assign $0\wb_sdram_cyc[0:0] $not$ls180.v:1685$52_Y
+ assign $0\wb_sdram_stb[0:0] $not$ls180.v:1686$53_Y
+ attribute \src "ls180.v:1687.5-1694.8"
+ switch $or$ls180.v:1687$54_Y
+ attribute \src "ls180.v:1687.9-1687.44"
case 1'1
- assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1675$54_Y
+ assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1688$55_Y
assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:1677.6-1680.9"
- switch $eq$ls180.v:1677$55_Y
- attribute \src "ls180.v:1677.10-1677.41"
+ attribute \src "ls180.v:1690.6-1693.9"
+ switch $eq$ls180.v:1690$56_Y
+ attribute \src "ls180.v:1690.10-1690.41"
case 1'1
assign $0\socbushandler_converted_interface_ack[0:0] 1'1
assign $0\subfragments_converter2_next_state[0:0] 1'0
case
assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0
assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:1687.4-1689.7"
- switch $and$ls180.v:1687$56_Y
- attribute \src "ls180.v:1687.8-1687.87"
+ attribute \src "ls180.v:1700.4-1702.7"
+ switch $and$ls180.v:1700$57_Y
+ attribute \src "ls180.v:1700.8-1700.87"
case 1'1
assign $0\subfragments_converter2_next_state[0:0] 1'1
case
update \socbushandler_counter_subfragments_converter2_next_value $0\socbushandler_counter_subfragments_converter2_next_value[0:0]
update \socbushandler_counter_subfragments_converter2_next_value_ce $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0]
end
- attribute \src "ls180.v:168.5-168.36"
- process $proc$ls180.v:168$1674
+ attribute \src "ls180.v:166.5-166.44"
+ process $proc$ls180.v:166$1678
assign { } { }
- assign $1\libresocsim_zero_pending[0:0] 1'0
+ assign $1\libresocsim_update_value_storage[0:0] 1'0
sync always
sync init
- update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0]
+ update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0]
end
- attribute \src "ls180.v:1695.1-1705.4"
- process $proc$ls180.v:1695$57
- assign { } { }
+ attribute \src "ls180.v:167.5-167.39"
+ process $proc$ls180.v:167$1679
assign { } { }
- assign $0\libresocsim_we[7:0] [0] $and$ls180.v:1697$60_Y
- assign $0\libresocsim_we[7:0] [1] $and$ls180.v:1698$63_Y
- assign $0\libresocsim_we[7:0] [2] $and$ls180.v:1699$66_Y
- assign $0\libresocsim_we[7:0] [3] $and$ls180.v:1700$69_Y
- assign $0\libresocsim_we[7:0] [4] $and$ls180.v:1701$72_Y
- assign $0\libresocsim_we[7:0] [5] $and$ls180.v:1702$75_Y
- assign $0\libresocsim_we[7:0] [6] $and$ls180.v:1703$78_Y
- assign $0\libresocsim_we[7:0] [7] $and$ls180.v:1704$81_Y
+ assign $1\libresocsim_update_value_re[0:0] 1'0
sync always
- update \libresocsim_we $0\libresocsim_we[7:0]
+ sync init
+ update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0]
end
- attribute \src "ls180.v:170.5-170.34"
- process $proc$ls180.v:170$1675
+ attribute \src "ls180.v:168.12-168.44"
+ process $proc$ls180.v:168$1680
assign { } { }
- assign $1\libresocsim_zero_clear[0:0] 1'0
+ assign $1\libresocsim_value_status[31:0] 0
sync always
sync init
- update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0]
+ update \libresocsim_value_status $1\libresocsim_value_status[31:0]
end
- attribute \src "ls180.v:171.5-171.40"
- process $proc$ls180.v:171$1676
+ attribute \src "ls180.v:1708.1-1718.4"
+ process $proc$ls180.v:1708$58
assign { } { }
- assign $1\libresocsim_zero_old_trigger[0:0] 1'0
+ assign { } { }
+ assign $0\libresocsim_we[7:0] [0] $and$ls180.v:1710$61_Y
+ assign $0\libresocsim_we[7:0] [1] $and$ls180.v:1711$64_Y
+ assign $0\libresocsim_we[7:0] [2] $and$ls180.v:1712$67_Y
+ assign $0\libresocsim_we[7:0] [3] $and$ls180.v:1713$70_Y
+ assign $0\libresocsim_we[7:0] [4] $and$ls180.v:1714$73_Y
+ assign $0\libresocsim_we[7:0] [5] $and$ls180.v:1715$76_Y
+ assign $0\libresocsim_we[7:0] [6] $and$ls180.v:1716$79_Y
+ assign $0\libresocsim_we[7:0] [7] $and$ls180.v:1717$82_Y
+ sync always
+ update \libresocsim_we $0\libresocsim_we[7:0]
+ end
+ attribute \src "ls180.v:172.5-172.36"
+ process $proc$ls180.v:172$1681
+ assign { } { }
+ assign $1\libresocsim_zero_pending[0:0] 1'0
sync always
sync init
- update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0]
+ update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0]
end
- attribute \src "ls180.v:1711.1-1716.4"
- process $proc$ls180.v:1711$83
+ attribute \src "ls180.v:1724.1-1729.4"
+ process $proc$ls180.v:1724$84
assign { } { }
assign $0\libresocsim_zero_clear[0:0] 1'0
- attribute \src "ls180.v:1713.2-1715.5"
- switch $and$ls180.v:1713$84_Y
- attribute \src "ls180.v:1713.6-1713.80"
+ attribute \src "ls180.v:1726.2-1728.5"
+ switch $and$ls180.v:1726$85_Y
+ attribute \src "ls180.v:1726.6-1726.80"
case 1'1
assign $0\libresocsim_zero_clear[0:0] 1'1
case
sync always
update \libresocsim_zero_clear $0\libresocsim_zero_clear[0:0]
end
- attribute \src "ls180.v:1720.1-1730.4"
- process $proc$ls180.v:1720$86
+ attribute \src "ls180.v:1733.1-1743.4"
+ process $proc$ls180.v:1733$87
assign { } { }
assign { } { }
- assign $0\ram_we[7:0] [0] $and$ls180.v:1722$89_Y
- assign $0\ram_we[7:0] [1] $and$ls180.v:1723$92_Y
- assign $0\ram_we[7:0] [2] $and$ls180.v:1724$95_Y
- assign $0\ram_we[7:0] [3] $and$ls180.v:1725$98_Y
- assign $0\ram_we[7:0] [4] $and$ls180.v:1726$101_Y
- assign $0\ram_we[7:0] [5] $and$ls180.v:1727$104_Y
- assign $0\ram_we[7:0] [6] $and$ls180.v:1728$107_Y
- assign $0\ram_we[7:0] [7] $and$ls180.v:1729$110_Y
+ assign $0\ram_we[7:0] [0] $and$ls180.v:1735$90_Y
+ assign $0\ram_we[7:0] [1] $and$ls180.v:1736$93_Y
+ assign $0\ram_we[7:0] [2] $and$ls180.v:1737$96_Y
+ assign $0\ram_we[7:0] [3] $and$ls180.v:1738$99_Y
+ assign $0\ram_we[7:0] [4] $and$ls180.v:1739$102_Y
+ assign $0\ram_we[7:0] [5] $and$ls180.v:1740$105_Y
+ assign $0\ram_we[7:0] [6] $and$ls180.v:1741$108_Y
+ assign $0\ram_we[7:0] [7] $and$ls180.v:1742$111_Y
sync always
update \ram_we $0\ram_we[7:0]
end
- attribute \src "ls180.v:1769.1-1823.4"
- process $proc$ls180.v:1769$111
+ attribute \src "ls180.v:174.5-174.34"
+ process $proc$ls180.v:174$1682
+ assign { } { }
+ assign $1\libresocsim_zero_clear[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0]
+ end
+ attribute \src "ls180.v:175.5-175.40"
+ process $proc$ls180.v:175$1683
+ assign { } { }
+ assign $1\libresocsim_zero_old_trigger[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0]
+ end
+ attribute \src "ls180.v:1782.1-1836.4"
+ process $proc$ls180.v:1782$112
assign { } { }
assign { } { }
assign { } { }
assign $0\sdram_master_p0_wrdata_en[0:0] 1'0
assign $0\sdram_master_p0_wrdata_mask[1:0] 2'00
assign $0\sdram_master_p0_rddata_en[0:0] 1'0
- attribute \src "ls180.v:1788.2-1822.5"
+ attribute \src "ls180.v:1801.2-1835.5"
switch \sdram_sel
- attribute \src "ls180.v:1788.6-1788.15"
+ attribute \src "ls180.v:1801.6-1801.15"
case 1'1
assign $0\sdram_master_p0_address[12:0] \sdram_slave_p0_address
assign $0\sdram_master_p0_bank[1:0] \sdram_slave_p0_bank
assign $0\sdram_master_p0_rddata_en[0:0] \sdram_slave_p0_rddata_en
assign $0\sdram_slave_p0_rddata[15:0] \sdram_master_p0_rddata
assign $0\sdram_slave_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid
- attribute \src "ls180.v:1805.6-1805.10"
+ attribute \src "ls180.v:1818.6-1818.10"
case
assign $0\sdram_master_p0_address[12:0] \sdram_inti_p0_address
assign $0\sdram_master_p0_bank[1:0] \sdram_inti_p0_bank
update \sdram_master_p0_wrdata_mask $0\sdram_master_p0_wrdata_mask[1:0]
update \sdram_master_p0_rddata_en $0\sdram_master_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:180.5-180.44"
- process $proc$ls180.v:180$1677
+ attribute \src "ls180.v:184.5-184.44"
+ process $proc$ls180.v:184$1684
assign { } { }
assign $1\libresocsim_eventmanager_storage[0:0] 1'0
sync always
sync init
update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0]
end
- attribute \src "ls180.v:181.5-181.39"
- process $proc$ls180.v:181$1678
- assign { } { }
- assign $1\libresocsim_eventmanager_re[0:0] 1'0
- sync always
- sync init
- update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0]
- end
- attribute \src "ls180.v:182.12-182.37"
- process $proc$ls180.v:182$1679
- assign { } { }
- assign $1\libresocsim_value[31:0] 0
- sync always
- sync init
- update \libresocsim_value $1\libresocsim_value[31:0]
- end
- attribute \src "ls180.v:1827.1-1843.4"
- process $proc$ls180.v:1827$112
+ attribute \src "ls180.v:1840.1-1856.4"
+ process $proc$ls180.v:1840$113
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\sdram_inti_p0_ras_n[0:0] 1'1
assign $0\sdram_inti_p0_we_n[0:0] 1'1
assign $0\sdram_inti_p0_cas_n[0:0] 1'1
assign $0\sdram_inti_p0_cs_n[0:0] 1'1
- assign $0\sdram_inti_p0_ras_n[0:0] 1'1
- attribute \src "ls180.v:1832.2-1842.5"
+ attribute \src "ls180.v:1845.2-1855.5"
switch \sdram_command_issue_re
- attribute \src "ls180.v:1832.6-1832.28"
+ attribute \src "ls180.v:1845.6-1845.28"
case 1'1
- assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1833$113_Y
- assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1834$114_Y
- assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1835$115_Y
- assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1836$116_Y
- attribute \src "ls180.v:1837.6-1837.10"
+ assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1846$114_Y
+ assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1847$115_Y
+ assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1848$116_Y
+ assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1849$117_Y
+ attribute \src "ls180.v:1850.6-1850.10"
case
assign $0\sdram_inti_p0_cs_n[0:0] 1'1
assign $0\sdram_inti_p0_we_n[0:0] 1'1
update \sdram_inti_p0_ras_n $0\sdram_inti_p0_ras_n[0:0]
update \sdram_inti_p0_we_n $0\sdram_inti_p0_we_n[0:0]
end
- attribute \src "ls180.v:1886.1-1916.4"
- process $proc$ls180.v:1886$125
+ attribute \src "ls180.v:185.5-185.39"
+ process $proc$ls180.v:185$1685
+ assign { } { }
+ assign $1\libresocsim_eventmanager_re[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0]
+ end
+ attribute \src "ls180.v:186.12-186.37"
+ process $proc$ls180.v:186$1686
+ assign { } { }
+ assign $1\libresocsim_value[31:0] 0
+ sync always
+ sync init
+ update \libresocsim_value $1\libresocsim_value[31:0]
+ end
+ attribute \src "ls180.v:1899.1-1929.4"
+ process $proc$ls180.v:1899$126
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\sdram_cmd_last[0:0] 1'0
assign $0\sdram_sequencer_start0[0:0] 1'0
- assign { } { }
assign $0\sdram_cmd_valid[0:0] 1'0
- assign $0\sdram_cmd_last[0:0] 1'0
+ assign { } { }
assign $0\subfragments_refresher_next_state[1:0] \subfragments_refresher_state
- attribute \src "ls180.v:1892.2-1915.9"
+ attribute \src "ls180.v:1905.2-1928.9"
switch \subfragments_refresher_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
assign $0\sdram_cmd_valid[0:0] 1'1
- attribute \src "ls180.v:1895.4-1898.7"
+ attribute \src "ls180.v:1908.4-1911.7"
switch \sdram_cmd_ready
- attribute \src "ls180.v:1895.8-1895.23"
+ attribute \src "ls180.v:1908.8-1908.23"
case 1'1
assign $0\sdram_sequencer_start0[0:0] 1'1
assign $0\subfragments_refresher_next_state[1:0] 2'10
attribute \src "ls180.v:0.0-0.0"
case 2'10
assign $0\sdram_cmd_valid[0:0] 1'1
- attribute \src "ls180.v:1902.4-1906.7"
+ attribute \src "ls180.v:1915.4-1919.7"
switch \sdram_sequencer_done0
- attribute \src "ls180.v:1902.8-1902.29"
+ attribute \src "ls180.v:1915.8-1915.29"
case 1'1
assign $0\sdram_cmd_valid[0:0] 1'0
assign $0\sdram_cmd_last[0:0] 1'1
end
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:1909.4-1913.7"
+ attribute \src "ls180.v:1922.4-1926.7"
switch 1'1
- attribute \src "ls180.v:1909.8-1909.12"
+ attribute \src "ls180.v:1922.8-1922.12"
case 1'1
- attribute \src "ls180.v:1910.5-1912.8"
+ attribute \src "ls180.v:1923.5-1925.8"
switch \sdram_wants_refresh
- attribute \src "ls180.v:1910.9-1910.28"
+ attribute \src "ls180.v:1923.9-1923.28"
case 1'1
assign $0\subfragments_refresher_next_state[1:0] 2'01
case
update \sdram_sequencer_start0 $0\sdram_sequencer_start0[0:0]
update \subfragments_refresher_next_state $0\subfragments_refresher_next_state[1:0]
end
- attribute \src "ls180.v:189.5-189.31"
- process $proc$ls180.v:189$1680
+ attribute \src "ls180.v:193.5-193.31"
+ process $proc$ls180.v:193$1687
assign { } { }
assign $1\ram_bus_ram_bus_ack[0:0] 1'0
sync always
sync init
update \ram_bus_ram_bus_ack $1\ram_bus_ram_bus_ack[0:0]
end
- attribute \src "ls180.v:193.5-193.31"
- process $proc$ls180.v:193$1681
- assign { } { }
- assign $0\ram_bus_ram_bus_err[0:0] 1'0
- sync always
- update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0]
- sync init
- end
- attribute \src "ls180.v:1931.1-1938.4"
- process $proc$ls180.v:1931$129
+ attribute \src "ls180.v:1944.1-1951.4"
+ process $proc$ls180.v:1944$130
assign { } { }
assign $0\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:1933.2-1937.5"
+ attribute \src "ls180.v:1946.2-1950.5"
switch \sdram_bankmachine0_row_col_n_addr_sel
- attribute \src "ls180.v:1933.6-1933.43"
+ attribute \src "ls180.v:1946.6-1946.43"
case 1'1
assign $0\sdram_bankmachine0_cmd_payload_a[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:1935.6-1935.10"
+ attribute \src "ls180.v:1948.6-1948.10"
case
- assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1936$131_Y
+ assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1949$132_Y
end
sync always
update \sdram_bankmachine0_cmd_payload_a $0\sdram_bankmachine0_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:1942.1-1949.4"
- process $proc$ls180.v:1942$138
+ attribute \src "ls180.v:1955.1-1962.4"
+ process $proc$ls180.v:1955$139
assign { } { }
assign $0\sdram_bankmachine0_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:1944.2-1948.5"
- switch $and$ls180.v:1944$139_Y
- attribute \src "ls180.v:1944.6-1944.105"
+ attribute \src "ls180.v:1957.2-1961.5"
+ switch $and$ls180.v:1957$140_Y
+ attribute \src "ls180.v:1957.6-1957.105"
case 1'1
- attribute \src "ls180.v:1945.3-1947.6"
- switch $ne$ls180.v:1945$140_Y
- attribute \src "ls180.v:1945.7-1945.133"
+ attribute \src "ls180.v:1958.3-1960.6"
+ switch $ne$ls180.v:1958$141_Y
+ attribute \src "ls180.v:1958.7-1958.133"
case 1'1
- assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1946$141_Y
+ assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1959$142_Y
case
end
case
sync always
update \sdram_bankmachine0_auto_precharge $0\sdram_bankmachine0_auto_precharge[0:0]
end
- attribute \src "ls180.v:196.11-196.24"
- process $proc$ls180.v:196$1682
+ attribute \src "ls180.v:197.5-197.31"
+ process $proc$ls180.v:197$1688
assign { } { }
- assign $1\ram_we[7:0] 8'00000000
+ assign $0\ram_bus_ram_bus_err[0:0] 1'0
sync always
+ update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0]
sync init
- update \ram_we $1\ram_we[7:0]
end
- attribute \src "ls180.v:1964.1-1971.4"
- process $proc$ls180.v:1964$142
+ attribute \src "ls180.v:1977.1-1984.4"
+ process $proc$ls180.v:1977$143
assign { } { }
assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:1966.2-1970.5"
+ attribute \src "ls180.v:1979.2-1983.5"
switch \sdram_bankmachine0_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:1966.6-1966.53"
+ attribute \src "ls180.v:1979.6-1979.53"
case 1'1
- assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1967$143_Y
- attribute \src "ls180.v:1968.6-1968.10"
+ assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1980$144_Y
+ attribute \src "ls180.v:1981.6-1981.10"
case
assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce
end
sync always
update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:1980.1-2073.4"
- process $proc$ls180.v:1980$151
+ attribute \src "ls180.v:1993.1-2086.4"
+ process $proc$ls180.v:1993$152
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'0
assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'0
+ assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
assign { } { }
assign $0\sdram_bankmachine0_row_open[0:0] 1'0
assign $0\sdram_bankmachine0_row_close[0:0] 1'0
assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'0
- assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
assign $0\sdram_bankmachine0_req_wdata_ready[0:0] 1'0
- assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
assign $0\subfragments_bankmachine0_next_state[2:0] \subfragments_bankmachine0_state
- attribute \src "ls180.v:1996.2-2072.9"
+ attribute \src "ls180.v:2009.2-2085.9"
switch \subfragments_bankmachine0_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\sdram_bankmachine0_row_close[0:0] 1'1
- attribute \src "ls180.v:1998.4-2006.7"
- switch $and$ls180.v:1998$152_Y
- attribute \src "ls180.v:1998.8-1998.77"
+ attribute \src "ls180.v:2011.4-2019.7"
+ switch $and$ls180.v:2011$153_Y
+ attribute \src "ls180.v:2011.8-2011.77"
case 1'1
assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2000.5-2002.8"
+ attribute \src "ls180.v:2013.5-2015.8"
switch \sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:2000.9-2000.37"
+ attribute \src "ls180.v:2013.9-2013.37"
case 1'1
assign $0\subfragments_bankmachine0_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\sdram_bankmachine0_row_close[0:0] 1'1
- attribute \src "ls180.v:2010.4-2012.7"
- switch $and$ls180.v:2010$153_Y
- attribute \src "ls180.v:2010.8-2010.77"
+ attribute \src "ls180.v:2023.4-2025.7"
+ switch $and$ls180.v:2023$154_Y
+ attribute \src "ls180.v:2023.8-2023.77"
case 1'1
assign $0\subfragments_bankmachine0_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:2016.4-2025.7"
+ attribute \src "ls180.v:2029.4-2038.7"
switch \sdram_bankmachine0_trccon_ready
- attribute \src "ls180.v:2016.8-2016.39"
+ attribute \src "ls180.v:2029.8-2029.39"
case 1'1
assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1
assign $0\sdram_bankmachine0_row_open[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:2021.5-2023.8"
+ attribute \src "ls180.v:2034.5-2036.8"
switch \sdram_bankmachine0_cmd_ready
- attribute \src "ls180.v:2021.9-2021.37"
+ attribute \src "ls180.v:2034.9-2034.37"
case 1'1
assign $0\subfragments_bankmachine0_next_state[2:0] 3'110
case
case 3'100
assign $0\sdram_bankmachine0_row_close[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2028.4-2030.7"
+ attribute \src "ls180.v:2041.4-2043.7"
switch \sdram_bankmachine0_twtpcon_ready
- attribute \src "ls180.v:2028.8-2028.40"
+ attribute \src "ls180.v:2041.8-2041.40"
case 1'1
assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:2033.4-2035.7"
- switch $not$ls180.v:2033$154_Y
- attribute \src "ls180.v:2033.8-2033.41"
+ attribute \src "ls180.v:2046.4-2048.7"
+ switch $not$ls180.v:2046$155_Y
+ attribute \src "ls180.v:2046.8-2046.41"
case 1'1
assign $0\subfragments_bankmachine0_next_state[2:0] 3'000
case
assign $0\subfragments_bankmachine0_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:2044.4-2070.7"
+ attribute \src "ls180.v:2057.4-2083.7"
switch \sdram_bankmachine0_refresh_req
- attribute \src "ls180.v:2044.8-2044.38"
+ attribute \src "ls180.v:2057.8-2057.38"
case 1'1
assign $0\subfragments_bankmachine0_next_state[2:0] 3'100
- attribute \src "ls180.v:2046.8-2046.12"
+ attribute \src "ls180.v:2059.8-2059.12"
case
- attribute \src "ls180.v:2047.5-2069.8"
+ attribute \src "ls180.v:2060.5-2082.8"
switch \sdram_bankmachine0_cmd_buffer_source_valid
- attribute \src "ls180.v:2047.9-2047.51"
+ attribute \src "ls180.v:2060.9-2060.51"
case 1'1
- attribute \src "ls180.v:2048.6-2068.9"
+ attribute \src "ls180.v:2061.6-2081.9"
switch \sdram_bankmachine0_row_opened
- attribute \src "ls180.v:2048.10-2048.39"
+ attribute \src "ls180.v:2061.10-2061.39"
case 1'1
- attribute \src "ls180.v:2049.7-2065.10"
+ attribute \src "ls180.v:2062.7-2078.10"
switch \sdram_bankmachine0_row_hit
- attribute \src "ls180.v:2049.11-2049.37"
+ attribute \src "ls180.v:2062.11-2062.37"
case 1'1
assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:2051.8-2058.11"
+ attribute \src "ls180.v:2064.8-2071.11"
switch \sdram_bankmachine0_cmd_buffer_source_payload_we
- attribute \src "ls180.v:2051.12-2051.59"
+ attribute \src "ls180.v:2064.12-2064.59"
case 1'1
assign $0\sdram_bankmachine0_req_wdata_ready[0:0] \sdram_bankmachine0_cmd_ready
assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1
assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:2055.12-2055.16"
+ attribute \src "ls180.v:2068.12-2068.16"
case
assign $0\sdram_bankmachine0_req_rdata_valid[0:0] \sdram_bankmachine0_cmd_ready
assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:2060.8-2062.11"
- switch $and$ls180.v:2060$155_Y
- attribute \src "ls180.v:2060.12-2060.78"
+ attribute \src "ls180.v:2073.8-2075.11"
+ switch $and$ls180.v:2073$156_Y
+ attribute \src "ls180.v:2073.12-2073.78"
case 1'1
assign $0\subfragments_bankmachine0_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:2063.11-2063.15"
+ attribute \src "ls180.v:2076.11-2076.15"
case
assign $0\subfragments_bankmachine0_next_state[2:0] 3'001
end
- attribute \src "ls180.v:2066.10-2066.14"
+ attribute \src "ls180.v:2079.10-2079.14"
case
assign $0\subfragments_bankmachine0_next_state[2:0] 3'011
end
update \sdram_bankmachine0_row_col_n_addr_sel $0\sdram_bankmachine0_row_col_n_addr_sel[0:0]
update \subfragments_bankmachine0_next_state $0\subfragments_bankmachine0_next_state[2:0]
end
- attribute \src "ls180.v:204.5-204.46"
- process $proc$ls180.v:204$1683
+ attribute \src "ls180.v:200.11-200.24"
+ process $proc$ls180.v:200$1689
assign { } { }
- assign $1\interface0_converted_interface_ack[0:0] 1'0
+ assign $1\ram_we[7:0] 8'00000000
sync always
sync init
- update \interface0_converted_interface_ack $1\interface0_converted_interface_ack[0:0]
+ update \ram_we $1\ram_we[7:0]
end
attribute \src "ls180.v:208.5-208.46"
- process $proc$ls180.v:208$1684
+ process $proc$ls180.v:208$1690
assign { } { }
- assign $0\interface0_converted_interface_err[0:0] 1'0
+ assign $1\interface0_converted_interface_ack[0:0] 1'0
sync always
- update \interface0_converted_interface_err $0\interface0_converted_interface_err[0:0]
sync init
+ update \interface0_converted_interface_ack $1\interface0_converted_interface_ack[0:0]
end
- attribute \src "ls180.v:2088.1-2095.4"
- process $proc$ls180.v:2088$159
+ attribute \src "ls180.v:2101.1-2108.4"
+ process $proc$ls180.v:2101$160
assign { } { }
assign $0\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:2090.2-2094.5"
+ attribute \src "ls180.v:2103.2-2107.5"
switch \sdram_bankmachine1_row_col_n_addr_sel
- attribute \src "ls180.v:2090.6-2090.43"
+ attribute \src "ls180.v:2103.6-2103.43"
case 1'1
assign $0\sdram_bankmachine1_cmd_payload_a[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:2092.6-2092.10"
+ attribute \src "ls180.v:2105.6-2105.10"
case
- assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2093$161_Y
+ assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2106$162_Y
end
sync always
update \sdram_bankmachine1_cmd_payload_a $0\sdram_bankmachine1_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:209.5-209.27"
- process $proc$ls180.v:209$1685
- assign { } { }
- assign $1\converter0_skip[0:0] 1'0
- sync always
- sync init
- update \converter0_skip $1\converter0_skip[0:0]
- end
- attribute \src "ls180.v:2099.1-2106.4"
- process $proc$ls180.v:2099$168
+ attribute \src "ls180.v:2112.1-2119.4"
+ process $proc$ls180.v:2112$169
assign { } { }
assign $0\sdram_bankmachine1_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:2101.2-2105.5"
- switch $and$ls180.v:2101$169_Y
- attribute \src "ls180.v:2101.6-2101.105"
+ attribute \src "ls180.v:2114.2-2118.5"
+ switch $and$ls180.v:2114$170_Y
+ attribute \src "ls180.v:2114.6-2114.105"
case 1'1
- attribute \src "ls180.v:2102.3-2104.6"
- switch $ne$ls180.v:2102$170_Y
- attribute \src "ls180.v:2102.7-2102.133"
+ attribute \src "ls180.v:2115.3-2117.6"
+ switch $ne$ls180.v:2115$171_Y
+ attribute \src "ls180.v:2115.7-2115.133"
case 1'1
- assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2103$171_Y
+ assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2116$172_Y
case
end
case
sync always
update \sdram_bankmachine1_auto_precharge $0\sdram_bankmachine1_auto_precharge[0:0]
end
- attribute \src "ls180.v:210.5-210.30"
- process $proc$ls180.v:210$1686
+ attribute \src "ls180.v:212.5-212.46"
+ process $proc$ls180.v:212$1691
assign { } { }
- assign $1\converter0_counter[0:0] 1'0
+ assign $0\interface0_converted_interface_err[0:0] 1'0
sync always
+ update \interface0_converted_interface_err $0\interface0_converted_interface_err[0:0]
sync init
- update \converter0_counter $1\converter0_counter[0:0]
end
- attribute \src "ls180.v:212.12-212.36"
- process $proc$ls180.v:212$1687
+ attribute \src "ls180.v:213.5-213.27"
+ process $proc$ls180.v:213$1692
assign { } { }
- assign $1\converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\converter0_skip[0:0] 1'0
sync always
sync init
- update \converter0_dat_r $1\converter0_dat_r[63:0]
+ update \converter0_skip $1\converter0_skip[0:0]
end
- attribute \src "ls180.v:2121.1-2128.4"
- process $proc$ls180.v:2121$172
+ attribute \src "ls180.v:2134.1-2141.4"
+ process $proc$ls180.v:2134$173
assign { } { }
assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:2123.2-2127.5"
+ attribute \src "ls180.v:2136.2-2140.5"
switch \sdram_bankmachine1_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:2123.6-2123.53"
+ attribute \src "ls180.v:2136.6-2136.53"
case 1'1
- assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2124$173_Y
- attribute \src "ls180.v:2125.6-2125.10"
+ assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2137$174_Y
+ attribute \src "ls180.v:2138.6-2138.10"
case
assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce
end
sync always
update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:2137.1-2230.4"
- process $proc$ls180.v:2137$181
+ attribute \src "ls180.v:214.5-214.30"
+ process $proc$ls180.v:214$1693
+ assign { } { }
+ assign $1\converter0_counter[0:0] 1'0
+ sync always
+ sync init
+ update \converter0_counter $1\converter0_counter[0:0]
+ end
+ attribute \src "ls180.v:2150.1-2243.4"
+ process $proc$ls180.v:2150$182
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
- assign { } { }
assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
+ assign { } { }
assign $0\sdram_bankmachine1_req_wdata_ready[0:0] 1'0
assign $0\sdram_bankmachine1_req_rdata_valid[0:0] 1'0
assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'0
assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'0
- assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
assign $0\sdram_bankmachine1_row_open[0:0] 1'0
assign $0\sdram_bankmachine1_row_close[0:0] 1'0
+ assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'0
- assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
assign $0\subfragments_bankmachine1_next_state[2:0] \subfragments_bankmachine1_state
- attribute \src "ls180.v:2153.2-2229.9"
+ attribute \src "ls180.v:2166.2-2242.9"
switch \subfragments_bankmachine1_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\sdram_bankmachine1_row_close[0:0] 1'1
- attribute \src "ls180.v:2155.4-2163.7"
- switch $and$ls180.v:2155$182_Y
- attribute \src "ls180.v:2155.8-2155.77"
+ attribute \src "ls180.v:2168.4-2176.7"
+ switch $and$ls180.v:2168$183_Y
+ attribute \src "ls180.v:2168.8-2168.77"
case 1'1
assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2157.5-2159.8"
+ attribute \src "ls180.v:2170.5-2172.8"
switch \sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:2157.9-2157.37"
+ attribute \src "ls180.v:2170.9-2170.37"
case 1'1
assign $0\subfragments_bankmachine1_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\sdram_bankmachine1_row_close[0:0] 1'1
- attribute \src "ls180.v:2167.4-2169.7"
- switch $and$ls180.v:2167$183_Y
- attribute \src "ls180.v:2167.8-2167.77"
+ attribute \src "ls180.v:2180.4-2182.7"
+ switch $and$ls180.v:2180$184_Y
+ attribute \src "ls180.v:2180.8-2180.77"
case 1'1
assign $0\subfragments_bankmachine1_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:2173.4-2182.7"
+ attribute \src "ls180.v:2186.4-2195.7"
switch \sdram_bankmachine1_trccon_ready
- attribute \src "ls180.v:2173.8-2173.39"
+ attribute \src "ls180.v:2186.8-2186.39"
case 1'1
assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1
assign $0\sdram_bankmachine1_row_open[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:2178.5-2180.8"
+ attribute \src "ls180.v:2191.5-2193.8"
switch \sdram_bankmachine1_cmd_ready
- attribute \src "ls180.v:2178.9-2178.37"
+ attribute \src "ls180.v:2191.9-2191.37"
case 1'1
assign $0\subfragments_bankmachine1_next_state[2:0] 3'110
case
case 3'100
assign $0\sdram_bankmachine1_row_close[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2185.4-2187.7"
+ attribute \src "ls180.v:2198.4-2200.7"
switch \sdram_bankmachine1_twtpcon_ready
- attribute \src "ls180.v:2185.8-2185.40"
+ attribute \src "ls180.v:2198.8-2198.40"
case 1'1
assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:2190.4-2192.7"
- switch $not$ls180.v:2190$184_Y
- attribute \src "ls180.v:2190.8-2190.41"
+ attribute \src "ls180.v:2203.4-2205.7"
+ switch $not$ls180.v:2203$185_Y
+ attribute \src "ls180.v:2203.8-2203.41"
case 1'1
assign $0\subfragments_bankmachine1_next_state[2:0] 3'000
case
assign $0\subfragments_bankmachine1_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:2201.4-2227.7"
+ attribute \src "ls180.v:2214.4-2240.7"
switch \sdram_bankmachine1_refresh_req
- attribute \src "ls180.v:2201.8-2201.38"
+ attribute \src "ls180.v:2214.8-2214.38"
case 1'1
assign $0\subfragments_bankmachine1_next_state[2:0] 3'100
- attribute \src "ls180.v:2203.8-2203.12"
+ attribute \src "ls180.v:2216.8-2216.12"
case
- attribute \src "ls180.v:2204.5-2226.8"
+ attribute \src "ls180.v:2217.5-2239.8"
switch \sdram_bankmachine1_cmd_buffer_source_valid
- attribute \src "ls180.v:2204.9-2204.51"
+ attribute \src "ls180.v:2217.9-2217.51"
case 1'1
- attribute \src "ls180.v:2205.6-2225.9"
+ attribute \src "ls180.v:2218.6-2238.9"
switch \sdram_bankmachine1_row_opened
- attribute \src "ls180.v:2205.10-2205.39"
+ attribute \src "ls180.v:2218.10-2218.39"
case 1'1
- attribute \src "ls180.v:2206.7-2222.10"
+ attribute \src "ls180.v:2219.7-2235.10"
switch \sdram_bankmachine1_row_hit
- attribute \src "ls180.v:2206.11-2206.37"
+ attribute \src "ls180.v:2219.11-2219.37"
case 1'1
assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:2208.8-2215.11"
+ attribute \src "ls180.v:2221.8-2228.11"
switch \sdram_bankmachine1_cmd_buffer_source_payload_we
- attribute \src "ls180.v:2208.12-2208.59"
+ attribute \src "ls180.v:2221.12-2221.59"
case 1'1
assign $0\sdram_bankmachine1_req_wdata_ready[0:0] \sdram_bankmachine1_cmd_ready
assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1
assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:2212.12-2212.16"
+ attribute \src "ls180.v:2225.12-2225.16"
case
assign $0\sdram_bankmachine1_req_rdata_valid[0:0] \sdram_bankmachine1_cmd_ready
assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:2217.8-2219.11"
- switch $and$ls180.v:2217$185_Y
- attribute \src "ls180.v:2217.12-2217.78"
+ attribute \src "ls180.v:2230.8-2232.11"
+ switch $and$ls180.v:2230$186_Y
+ attribute \src "ls180.v:2230.12-2230.78"
case 1'1
assign $0\subfragments_bankmachine1_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:2220.11-2220.15"
+ attribute \src "ls180.v:2233.11-2233.15"
case
assign $0\subfragments_bankmachine1_next_state[2:0] 3'001
end
- attribute \src "ls180.v:2223.10-2223.14"
+ attribute \src "ls180.v:2236.10-2236.14"
case
assign $0\subfragments_bankmachine1_next_state[2:0] 3'011
end
update \sdram_bankmachine1_row_col_n_addr_sel $0\sdram_bankmachine1_row_col_n_addr_sel[0:0]
update \subfragments_bankmachine1_next_state $0\subfragments_bankmachine1_next_state[2:0]
end
- attribute \src "ls180.v:219.5-219.46"
- process $proc$ls180.v:219$1688
+ attribute \src "ls180.v:216.12-216.36"
+ process $proc$ls180.v:216$1694
assign { } { }
- assign $1\interface1_converted_interface_ack[0:0] 1'0
+ assign $1\converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
- update \interface1_converted_interface_ack $1\interface1_converted_interface_ack[0:0]
+ update \converter0_dat_r $1\converter0_dat_r[63:0]
end
attribute \src "ls180.v:223.5-223.46"
- process $proc$ls180.v:223$1689
- assign { } { }
- assign $0\interface1_converted_interface_err[0:0] 1'0
- sync always
- update \interface1_converted_interface_err $0\interface1_converted_interface_err[0:0]
- sync init
- end
- attribute \src "ls180.v:224.5-224.27"
- process $proc$ls180.v:224$1690
+ process $proc$ls180.v:223$1695
assign { } { }
- assign $1\converter1_skip[0:0] 1'0
+ assign $1\interface1_converted_interface_ack[0:0] 1'0
sync always
sync init
- update \converter1_skip $1\converter1_skip[0:0]
+ update \interface1_converted_interface_ack $1\interface1_converted_interface_ack[0:0]
end
- attribute \src "ls180.v:2245.1-2252.4"
- process $proc$ls180.v:2245$189
+ attribute \src "ls180.v:2258.1-2265.4"
+ process $proc$ls180.v:2258$190
assign { } { }
assign $0\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:2247.2-2251.5"
+ attribute \src "ls180.v:2260.2-2264.5"
switch \sdram_bankmachine2_row_col_n_addr_sel
- attribute \src "ls180.v:2247.6-2247.43"
+ attribute \src "ls180.v:2260.6-2260.43"
case 1'1
assign $0\sdram_bankmachine2_cmd_payload_a[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:2249.6-2249.10"
+ attribute \src "ls180.v:2262.6-2262.10"
case
- assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2250$191_Y
+ assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2263$192_Y
end
sync always
update \sdram_bankmachine2_cmd_payload_a $0\sdram_bankmachine2_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:225.5-225.30"
- process $proc$ls180.v:225$1691
- assign { } { }
- assign $1\converter1_counter[0:0] 1'0
- sync always
- sync init
- update \converter1_counter $1\converter1_counter[0:0]
- end
- attribute \src "ls180.v:2256.1-2263.4"
- process $proc$ls180.v:2256$198
+ attribute \src "ls180.v:2269.1-2276.4"
+ process $proc$ls180.v:2269$199
assign { } { }
assign $0\sdram_bankmachine2_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:2258.2-2262.5"
- switch $and$ls180.v:2258$199_Y
- attribute \src "ls180.v:2258.6-2258.105"
+ attribute \src "ls180.v:2271.2-2275.5"
+ switch $and$ls180.v:2271$200_Y
+ attribute \src "ls180.v:2271.6-2271.105"
case 1'1
- attribute \src "ls180.v:2259.3-2261.6"
- switch $ne$ls180.v:2259$200_Y
- attribute \src "ls180.v:2259.7-2259.133"
+ attribute \src "ls180.v:2272.3-2274.6"
+ switch $ne$ls180.v:2272$201_Y
+ attribute \src "ls180.v:2272.7-2272.133"
case 1'1
- assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2260$201_Y
+ assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2273$202_Y
case
end
case
sync always
update \sdram_bankmachine2_auto_precharge $0\sdram_bankmachine2_auto_precharge[0:0]
end
- attribute \src "ls180.v:227.12-227.36"
- process $proc$ls180.v:227$1692
+ attribute \src "ls180.v:227.5-227.46"
+ process $proc$ls180.v:227$1696
assign { } { }
- assign $1\converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $0\interface1_converted_interface_err[0:0] 1'0
+ sync always
+ update \interface1_converted_interface_err $0\interface1_converted_interface_err[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:228.5-228.27"
+ process $proc$ls180.v:228$1697
+ assign { } { }
+ assign $1\converter1_skip[0:0] 1'0
sync always
sync init
- update \converter1_dat_r $1\converter1_dat_r[63:0]
+ update \converter1_skip $1\converter1_skip[0:0]
+ end
+ attribute \src "ls180.v:229.5-229.30"
+ process $proc$ls180.v:229$1698
+ assign { } { }
+ assign $1\converter1_counter[0:0] 1'0
+ sync always
+ sync init
+ update \converter1_counter $1\converter1_counter[0:0]
end
- attribute \src "ls180.v:2278.1-2285.4"
- process $proc$ls180.v:2278$202
+ attribute \src "ls180.v:2291.1-2298.4"
+ process $proc$ls180.v:2291$203
assign { } { }
assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:2280.2-2284.5"
+ attribute \src "ls180.v:2293.2-2297.5"
switch \sdram_bankmachine2_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:2280.6-2280.53"
+ attribute \src "ls180.v:2293.6-2293.53"
case 1'1
- assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2281$203_Y
- attribute \src "ls180.v:2282.6-2282.10"
+ assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2294$204_Y
+ attribute \src "ls180.v:2295.6-2295.10"
case
assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce
end
sync always
update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:2294.1-2387.4"
- process $proc$ls180.v:2294$211
+ attribute \src "ls180.v:2307.1-2400.4"
+ process $proc$ls180.v:2307$212
+ assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\sdram_bankmachine2_row_close[0:0] 1'0
assign { } { }
assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0
assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0
assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0
- assign $0\sdram_bankmachine2_row_close[0:0] 1'0
assign $0\sdram_bankmachine2_row_open[0:0] 1'0
- assign { } { }
assign $0\subfragments_bankmachine2_next_state[2:0] \subfragments_bankmachine2_state
- attribute \src "ls180.v:2310.2-2386.9"
+ attribute \src "ls180.v:2323.2-2399.9"
switch \subfragments_bankmachine2_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\sdram_bankmachine2_row_close[0:0] 1'1
- attribute \src "ls180.v:2312.4-2320.7"
- switch $and$ls180.v:2312$212_Y
- attribute \src "ls180.v:2312.8-2312.77"
+ attribute \src "ls180.v:2325.4-2333.7"
+ switch $and$ls180.v:2325$213_Y
+ attribute \src "ls180.v:2325.8-2325.77"
case 1'1
assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2314.5-2316.8"
+ attribute \src "ls180.v:2327.5-2329.8"
switch \sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:2314.9-2314.37"
+ attribute \src "ls180.v:2327.9-2327.37"
case 1'1
assign $0\subfragments_bankmachine2_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\sdram_bankmachine2_row_close[0:0] 1'1
- attribute \src "ls180.v:2324.4-2326.7"
- switch $and$ls180.v:2324$213_Y
- attribute \src "ls180.v:2324.8-2324.77"
+ attribute \src "ls180.v:2337.4-2339.7"
+ switch $and$ls180.v:2337$214_Y
+ attribute \src "ls180.v:2337.8-2337.77"
case 1'1
assign $0\subfragments_bankmachine2_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:2330.4-2339.7"
+ attribute \src "ls180.v:2343.4-2352.7"
switch \sdram_bankmachine2_trccon_ready
- attribute \src "ls180.v:2330.8-2330.39"
+ attribute \src "ls180.v:2343.8-2343.39"
case 1'1
assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1
assign $0\sdram_bankmachine2_row_open[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:2335.5-2337.8"
+ attribute \src "ls180.v:2348.5-2350.8"
switch \sdram_bankmachine2_cmd_ready
- attribute \src "ls180.v:2335.9-2335.37"
+ attribute \src "ls180.v:2348.9-2348.37"
case 1'1
assign $0\subfragments_bankmachine2_next_state[2:0] 3'110
case
case 3'100
assign $0\sdram_bankmachine2_row_close[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2342.4-2344.7"
+ attribute \src "ls180.v:2355.4-2357.7"
switch \sdram_bankmachine2_twtpcon_ready
- attribute \src "ls180.v:2342.8-2342.40"
+ attribute \src "ls180.v:2355.8-2355.40"
case 1'1
assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:2347.4-2349.7"
- switch $not$ls180.v:2347$214_Y
- attribute \src "ls180.v:2347.8-2347.41"
+ attribute \src "ls180.v:2360.4-2362.7"
+ switch $not$ls180.v:2360$215_Y
+ attribute \src "ls180.v:2360.8-2360.41"
case 1'1
assign $0\subfragments_bankmachine2_next_state[2:0] 3'000
case
assign $0\subfragments_bankmachine2_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:2358.4-2384.7"
+ attribute \src "ls180.v:2371.4-2397.7"
switch \sdram_bankmachine2_refresh_req
- attribute \src "ls180.v:2358.8-2358.38"
+ attribute \src "ls180.v:2371.8-2371.38"
case 1'1
assign $0\subfragments_bankmachine2_next_state[2:0] 3'100
- attribute \src "ls180.v:2360.8-2360.12"
+ attribute \src "ls180.v:2373.8-2373.12"
case
- attribute \src "ls180.v:2361.5-2383.8"
+ attribute \src "ls180.v:2374.5-2396.8"
switch \sdram_bankmachine2_cmd_buffer_source_valid
- attribute \src "ls180.v:2361.9-2361.51"
+ attribute \src "ls180.v:2374.9-2374.51"
case 1'1
- attribute \src "ls180.v:2362.6-2382.9"
+ attribute \src "ls180.v:2375.6-2395.9"
switch \sdram_bankmachine2_row_opened
- attribute \src "ls180.v:2362.10-2362.39"
+ attribute \src "ls180.v:2375.10-2375.39"
case 1'1
- attribute \src "ls180.v:2363.7-2379.10"
+ attribute \src "ls180.v:2376.7-2392.10"
switch \sdram_bankmachine2_row_hit
- attribute \src "ls180.v:2363.11-2363.37"
+ attribute \src "ls180.v:2376.11-2376.37"
case 1'1
assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:2365.8-2372.11"
+ attribute \src "ls180.v:2378.8-2385.11"
switch \sdram_bankmachine2_cmd_buffer_source_payload_we
- attribute \src "ls180.v:2365.12-2365.59"
+ attribute \src "ls180.v:2378.12-2378.59"
case 1'1
assign $0\sdram_bankmachine2_req_wdata_ready[0:0] \sdram_bankmachine2_cmd_ready
assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1
assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:2369.12-2369.16"
+ attribute \src "ls180.v:2382.12-2382.16"
case
assign $0\sdram_bankmachine2_req_rdata_valid[0:0] \sdram_bankmachine2_cmd_ready
assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:2374.8-2376.11"
- switch $and$ls180.v:2374$215_Y
- attribute \src "ls180.v:2374.12-2374.78"
+ attribute \src "ls180.v:2387.8-2389.11"
+ switch $and$ls180.v:2387$216_Y
+ attribute \src "ls180.v:2387.12-2387.78"
case 1'1
assign $0\subfragments_bankmachine2_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:2377.11-2377.15"
+ attribute \src "ls180.v:2390.11-2390.15"
case
assign $0\subfragments_bankmachine2_next_state[2:0] 3'001
end
- attribute \src "ls180.v:2380.10-2380.14"
+ attribute \src "ls180.v:2393.10-2393.14"
case
assign $0\subfragments_bankmachine2_next_state[2:0] 3'011
end
update \sdram_bankmachine2_row_col_n_addr_sel $0\sdram_bankmachine2_row_col_n_addr_sel[0:0]
update \subfragments_bankmachine2_next_state $0\subfragments_bankmachine2_next_state[2:0]
end
- attribute \src "ls180.v:231.5-231.19"
- process $proc$ls180.v:231$1693
+ attribute \src "ls180.v:231.12-231.36"
+ process $proc$ls180.v:231$1699
+ assign { } { }
+ assign $1\converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync always
+ sync init
+ update \converter1_dat_r $1\converter1_dat_r[63:0]
+ end
+ attribute \src "ls180.v:235.5-235.19"
+ process $proc$ls180.v:235$1700
assign { } { }
assign $1\int_rst[0:0] 1'1
sync always
sync init
update \int_rst $1\int_rst[0:0]
end
- attribute \src "ls180.v:2402.1-2409.4"
- process $proc$ls180.v:2402$219
+ attribute \src "ls180.v:2415.1-2422.4"
+ process $proc$ls180.v:2415$220
assign { } { }
assign $0\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
- attribute \src "ls180.v:2404.2-2408.5"
+ attribute \src "ls180.v:2417.2-2421.5"
switch \sdram_bankmachine3_row_col_n_addr_sel
- attribute \src "ls180.v:2404.6-2404.43"
+ attribute \src "ls180.v:2417.6-2417.43"
case 1'1
assign $0\sdram_bankmachine3_cmd_payload_a[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
- attribute \src "ls180.v:2406.6-2406.10"
+ attribute \src "ls180.v:2419.6-2419.10"
case
- assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2407$221_Y
+ assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2420$222_Y
end
sync always
update \sdram_bankmachine3_cmd_payload_a $0\sdram_bankmachine3_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:2413.1-2420.4"
- process $proc$ls180.v:2413$228
+ attribute \src "ls180.v:2426.1-2433.4"
+ process $proc$ls180.v:2426$229
assign { } { }
assign $0\sdram_bankmachine3_auto_precharge[0:0] 1'0
- attribute \src "ls180.v:2415.2-2419.5"
- switch $and$ls180.v:2415$229_Y
- attribute \src "ls180.v:2415.6-2415.105"
+ attribute \src "ls180.v:2428.2-2432.5"
+ switch $and$ls180.v:2428$230_Y
+ attribute \src "ls180.v:2428.6-2428.105"
case 1'1
- attribute \src "ls180.v:2416.3-2418.6"
- switch $ne$ls180.v:2416$230_Y
- attribute \src "ls180.v:2416.7-2416.133"
+ attribute \src "ls180.v:2429.3-2431.6"
+ switch $ne$ls180.v:2429$231_Y
+ attribute \src "ls180.v:2429.7-2429.133"
case 1'1
- assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2417$231_Y
+ assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2430$232_Y
case
end
case
sync always
update \sdram_bankmachine3_auto_precharge $0\sdram_bankmachine3_auto_precharge[0:0]
end
- attribute \src "ls180.v:2435.1-2442.4"
- process $proc$ls180.v:2435$232
+ attribute \src "ls180.v:2448.1-2455.4"
+ process $proc$ls180.v:2448$233
assign { } { }
assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
- attribute \src "ls180.v:2437.2-2441.5"
+ attribute \src "ls180.v:2450.2-2454.5"
switch \sdram_bankmachine3_cmd_buffer_lookahead_replace
- attribute \src "ls180.v:2437.6-2437.53"
+ attribute \src "ls180.v:2450.6-2450.53"
case 1'1
- assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2438$233_Y
- attribute \src "ls180.v:2439.6-2439.10"
+ assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2451$234_Y
+ attribute \src "ls180.v:2452.6-2452.10"
case
assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce
end
sync always
update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:2451.1-2544.4"
- process $proc$ls180.v:2451$241
+ attribute \src "ls180.v:2464.1-2557.4"
+ process $proc$ls180.v:2464$242
assign { } { }
assign { } { }
assign { } { }
assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
assign $0\sdram_bankmachine3_req_wdata_ready[0:0] 1'0
assign $0\sdram_bankmachine3_req_rdata_valid[0:0] 1'0
- assign { } { }
assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'0
+ assign { } { }
assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'0
assign $0\subfragments_bankmachine3_next_state[2:0] \subfragments_bankmachine3_state
- attribute \src "ls180.v:2467.2-2543.9"
+ attribute \src "ls180.v:2480.2-2556.9"
switch \subfragments_bankmachine3_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\sdram_bankmachine3_row_close[0:0] 1'1
- attribute \src "ls180.v:2469.4-2477.7"
- switch $and$ls180.v:2469$242_Y
- attribute \src "ls180.v:2469.8-2469.77"
+ attribute \src "ls180.v:2482.4-2490.7"
+ switch $and$ls180.v:2482$243_Y
+ attribute \src "ls180.v:2482.8-2482.77"
case 1'1
assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2471.5-2473.8"
+ attribute \src "ls180.v:2484.5-2486.8"
switch \sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:2471.9-2471.37"
+ attribute \src "ls180.v:2484.9-2484.37"
case 1'1
assign $0\subfragments_bankmachine3_next_state[2:0] 3'101
case
attribute \src "ls180.v:0.0-0.0"
case 3'010
assign $0\sdram_bankmachine3_row_close[0:0] 1'1
- attribute \src "ls180.v:2481.4-2483.7"
- switch $and$ls180.v:2481$243_Y
- attribute \src "ls180.v:2481.8-2481.77"
+ attribute \src "ls180.v:2494.4-2496.7"
+ switch $and$ls180.v:2494$244_Y
+ attribute \src "ls180.v:2494.8-2494.77"
case 1'1
assign $0\subfragments_bankmachine3_next_state[2:0] 3'101
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:2487.4-2496.7"
+ attribute \src "ls180.v:2500.4-2509.7"
switch \sdram_bankmachine3_trccon_ready
- attribute \src "ls180.v:2487.8-2487.39"
+ attribute \src "ls180.v:2500.8-2500.39"
case 1'1
assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1
assign $0\sdram_bankmachine3_row_open[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1
- attribute \src "ls180.v:2492.5-2494.8"
+ attribute \src "ls180.v:2505.5-2507.8"
switch \sdram_bankmachine3_cmd_ready
- attribute \src "ls180.v:2492.9-2492.37"
+ attribute \src "ls180.v:2505.9-2505.37"
case 1'1
assign $0\subfragments_bankmachine3_next_state[2:0] 3'110
case
case 3'100
assign $0\sdram_bankmachine3_row_close[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1
- attribute \src "ls180.v:2499.4-2501.7"
+ attribute \src "ls180.v:2512.4-2514.7"
switch \sdram_bankmachine3_twtpcon_ready
- attribute \src "ls180.v:2499.8-2499.40"
+ attribute \src "ls180.v:2512.8-2512.40"
case 1'1
assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'1
case
end
- attribute \src "ls180.v:2504.4-2506.7"
- switch $not$ls180.v:2504$244_Y
- attribute \src "ls180.v:2504.8-2504.41"
+ attribute \src "ls180.v:2517.4-2519.7"
+ switch $not$ls180.v:2517$245_Y
+ attribute \src "ls180.v:2517.8-2517.41"
case 1'1
assign $0\subfragments_bankmachine3_next_state[2:0] 3'000
case
assign $0\subfragments_bankmachine3_next_state[2:0] 3'000
attribute \src "ls180.v:0.0-0.0"
case
- attribute \src "ls180.v:2515.4-2541.7"
+ attribute \src "ls180.v:2528.4-2554.7"
switch \sdram_bankmachine3_refresh_req
- attribute \src "ls180.v:2515.8-2515.38"
+ attribute \src "ls180.v:2528.8-2528.38"
case 1'1
assign $0\subfragments_bankmachine3_next_state[2:0] 3'100
- attribute \src "ls180.v:2517.8-2517.12"
+ attribute \src "ls180.v:2530.8-2530.12"
case
- attribute \src "ls180.v:2518.5-2540.8"
+ attribute \src "ls180.v:2531.5-2553.8"
switch \sdram_bankmachine3_cmd_buffer_source_valid
- attribute \src "ls180.v:2518.9-2518.51"
+ attribute \src "ls180.v:2531.9-2531.51"
case 1'1
- attribute \src "ls180.v:2519.6-2539.9"
+ attribute \src "ls180.v:2532.6-2552.9"
switch \sdram_bankmachine3_row_opened
- attribute \src "ls180.v:2519.10-2519.39"
+ attribute \src "ls180.v:2532.10-2532.39"
case 1'1
- attribute \src "ls180.v:2520.7-2536.10"
+ attribute \src "ls180.v:2533.7-2549.10"
switch \sdram_bankmachine3_row_hit
- attribute \src "ls180.v:2520.11-2520.37"
+ attribute \src "ls180.v:2533.11-2533.37"
case 1'1
assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'1
- attribute \src "ls180.v:2522.8-2529.11"
+ attribute \src "ls180.v:2535.8-2542.11"
switch \sdram_bankmachine3_cmd_buffer_source_payload_we
- attribute \src "ls180.v:2522.12-2522.59"
+ attribute \src "ls180.v:2535.12-2535.59"
case 1'1
assign $0\sdram_bankmachine3_req_wdata_ready[0:0] \sdram_bankmachine3_cmd_ready
assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1
assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1
- attribute \src "ls180.v:2526.12-2526.16"
+ attribute \src "ls180.v:2539.12-2539.16"
case
assign $0\sdram_bankmachine3_req_rdata_valid[0:0] \sdram_bankmachine3_cmd_ready
assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1
end
- attribute \src "ls180.v:2531.8-2533.11"
- switch $and$ls180.v:2531$245_Y
- attribute \src "ls180.v:2531.12-2531.78"
+ attribute \src "ls180.v:2544.8-2546.11"
+ switch $and$ls180.v:2544$246_Y
+ attribute \src "ls180.v:2544.12-2544.78"
case 1'1
assign $0\subfragments_bankmachine3_next_state[2:0] 3'010
case
end
- attribute \src "ls180.v:2534.11-2534.15"
+ attribute \src "ls180.v:2547.11-2547.15"
case
assign $0\subfragments_bankmachine3_next_state[2:0] 3'001
end
- attribute \src "ls180.v:2537.10-2537.14"
+ attribute \src "ls180.v:2550.10-2550.14"
case
assign $0\subfragments_bankmachine3_next_state[2:0] 3'011
end
update \sdram_bankmachine3_row_col_n_addr_sel $0\sdram_bankmachine3_row_col_n_addr_sel[0:0]
update \subfragments_bankmachine3_next_state $0\subfragments_bankmachine3_next_state[2:0]
end
- attribute \src "ls180.v:246.12-246.33"
- process $proc$ls180.v:246$1694
+ attribute \src "ls180.v:250.12-250.33"
+ process $proc$ls180.v:250$1701
assign { } { }
assign $1\dfi_p0_rddata[15:0] 16'0000000000000000
sync always
sync init
update \dfi_p0_rddata $1\dfi_p0_rddata[15:0]
end
- attribute \src "ls180.v:247.5-247.31"
- process $proc$ls180.v:247$1695
+ attribute \src "ls180.v:251.5-251.31"
+ process $proc$ls180.v:251$1702
assign { } { }
assign $1\dfi_p0_rddata_valid[0:0] 1'0
sync always
sync init
update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0]
end
- attribute \src "ls180.v:248.11-248.27"
- process $proc$ls180.v:248$1696
+ attribute \src "ls180.v:252.11-252.27"
+ process $proc$ls180.v:252$1703
assign { } { }
assign $1\rddata_en[2:0] 3'000
sync always
sync init
update \rddata_en $1\rddata_en[2:0]
end
- attribute \src "ls180.v:251.5-251.31"
- process $proc$ls180.v:251$1697
+ attribute \src "ls180.v:255.5-255.31"
+ process $proc$ls180.v:255$1704
assign { } { }
assign $1\sdram_inti_p0_cas_n[0:0] 1'1
sync always
sync init
update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0]
end
- attribute \src "ls180.v:252.5-252.30"
- process $proc$ls180.v:252$1698
+ attribute \src "ls180.v:256.5-256.30"
+ process $proc$ls180.v:256$1705
assign { } { }
assign $1\sdram_inti_p0_cs_n[0:0] 1'1
sync always
sync init
update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0]
end
- attribute \src "ls180.v:253.5-253.31"
- process $proc$ls180.v:253$1699
+ attribute \src "ls180.v:257.5-257.31"
+ process $proc$ls180.v:257$1706
assign { } { }
assign $1\sdram_inti_p0_ras_n[0:0] 1'1
sync always
sync init
update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0]
end
- attribute \src "ls180.v:254.5-254.30"
- process $proc$ls180.v:254$1700
+ attribute \src "ls180.v:2577.1-2583.4"
+ process $proc$ls180.v:2577$285
+ assign { } { }
+ assign { } { }
+ assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2579$298_Y
+ assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2580$311_Y
+ assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2581$324_Y
+ assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2582$337_Y
+ sync always
+ update \sdram_choose_cmd_valids $0\sdram_choose_cmd_valids[3:0]
+ end
+ attribute \src "ls180.v:258.5-258.30"
+ process $proc$ls180.v:258$1707
assign { } { }
assign $1\sdram_inti_p0_we_n[0:0] 1'1
sync always
sync init
update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0]
end
- attribute \src "ls180.v:2564.1-2570.4"
- process $proc$ls180.v:2564$284
- assign { } { }
- assign { } { }
- assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2566$297_Y
- assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2567$310_Y
- assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2568$323_Y
- assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2569$336_Y
- sync always
- update \sdram_choose_cmd_valids $0\sdram_choose_cmd_valids[3:0]
- end
- attribute \src "ls180.v:2578.1-2583.4"
- process $proc$ls180.v:2578$337
+ attribute \src "ls180.v:2591.1-2596.4"
+ process $proc$ls180.v:2591$338
assign { } { }
assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
- attribute \src "ls180.v:2580.2-2582.5"
+ attribute \src "ls180.v:2593.2-2595.5"
switch \sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:2580.6-2580.32"
+ attribute \src "ls180.v:2593.6-2593.32"
case 1'1
assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] \t_array_muxed0
case
sync always
update \sdram_choose_cmd_cmd_payload_cas $0\sdram_choose_cmd_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:258.5-258.31"
- process $proc$ls180.v:258$1701
- assign { } { }
- assign $0\sdram_inti_p0_act_n[0:0] 1'1
- sync always
- update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0]
- sync init
- end
- attribute \src "ls180.v:2584.1-2589.4"
- process $proc$ls180.v:2584$338
+ attribute \src "ls180.v:2597.1-2602.4"
+ process $proc$ls180.v:2597$339
assign { } { }
assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
- attribute \src "ls180.v:2586.2-2588.5"
+ attribute \src "ls180.v:2599.2-2601.5"
switch \sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:2586.6-2586.32"
+ attribute \src "ls180.v:2599.6-2599.32"
case 1'1
assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] \t_array_muxed1
case
sync always
update \sdram_choose_cmd_cmd_payload_ras $0\sdram_choose_cmd_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:2590.1-2595.4"
- process $proc$ls180.v:2590$339
+ attribute \src "ls180.v:2603.1-2608.4"
+ process $proc$ls180.v:2603$340
assign { } { }
assign $0\sdram_choose_cmd_cmd_payload_we[0:0] 1'0
- attribute \src "ls180.v:2592.2-2594.5"
+ attribute \src "ls180.v:2605.2-2607.5"
switch \sdram_choose_cmd_cmd_valid
- attribute \src "ls180.v:2592.6-2592.32"
+ attribute \src "ls180.v:2605.6-2605.32"
case 1'1
assign $0\sdram_choose_cmd_cmd_payload_we[0:0] \t_array_muxed2
case
sync always
update \sdram_choose_cmd_cmd_payload_we $0\sdram_choose_cmd_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:2597.1-2603.4"
- process $proc$ls180.v:2597$342
+ attribute \src "ls180.v:2610.1-2616.4"
+ process $proc$ls180.v:2610$343
assign { } { }
assign { } { }
- assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2599$355_Y
- assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2600$368_Y
- assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2601$381_Y
- assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2602$394_Y
+ assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2612$356_Y
+ assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2613$369_Y
+ assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2614$382_Y
+ assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2615$395_Y
sync always
update \sdram_choose_req_valids $0\sdram_choose_req_valids[3:0]
end
- attribute \src "ls180.v:2611.1-2616.4"
- process $proc$ls180.v:2611$395
+ attribute \src "ls180.v:262.5-262.31"
+ process $proc$ls180.v:262$1708
+ assign { } { }
+ assign $0\sdram_inti_p0_act_n[0:0] 1'1
+ sync always
+ update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:2624.1-2629.4"
+ process $proc$ls180.v:2624$396
assign { } { }
assign $0\sdram_choose_req_cmd_payload_cas[0:0] 1'0
- attribute \src "ls180.v:2613.2-2615.5"
+ attribute \src "ls180.v:2626.2-2628.5"
switch \sdram_choose_req_cmd_valid
- attribute \src "ls180.v:2613.6-2613.32"
+ attribute \src "ls180.v:2626.6-2626.32"
case 1'1
assign $0\sdram_choose_req_cmd_payload_cas[0:0] \t_array_muxed3
case
sync always
update \sdram_choose_req_cmd_payload_cas $0\sdram_choose_req_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:2617.1-2622.4"
- process $proc$ls180.v:2617$396
+ attribute \src "ls180.v:2630.1-2635.4"
+ process $proc$ls180.v:2630$397
assign { } { }
assign $0\sdram_choose_req_cmd_payload_ras[0:0] 1'0
- attribute \src "ls180.v:2619.2-2621.5"
+ attribute \src "ls180.v:2632.2-2634.5"
switch \sdram_choose_req_cmd_valid
- attribute \src "ls180.v:2619.6-2619.32"
+ attribute \src "ls180.v:2632.6-2632.32"
case 1'1
assign $0\sdram_choose_req_cmd_payload_ras[0:0] \t_array_muxed4
case
sync always
update \sdram_choose_req_cmd_payload_ras $0\sdram_choose_req_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:2623.1-2628.4"
- process $proc$ls180.v:2623$397
+ attribute \src "ls180.v:2636.1-2641.4"
+ process $proc$ls180.v:2636$398
assign { } { }
assign $0\sdram_choose_req_cmd_payload_we[0:0] 1'0
- attribute \src "ls180.v:2625.2-2627.5"
+ attribute \src "ls180.v:2638.2-2640.5"
switch \sdram_choose_req_cmd_valid
- attribute \src "ls180.v:2625.6-2625.32"
+ attribute \src "ls180.v:2638.6-2638.32"
case 1'1
assign $0\sdram_choose_req_cmd_payload_we[0:0] \t_array_muxed5
case
sync always
update \sdram_choose_req_cmd_payload_we $0\sdram_choose_req_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:2629.1-2637.4"
- process $proc$ls180.v:2629$398
+ attribute \src "ls180.v:2642.1-2650.4"
+ process $proc$ls180.v:2642$399
assign { } { }
assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:2631.2-2633.5"
- switch $and$ls180.v:2631$401_Y
- attribute \src "ls180.v:2631.6-2631.100"
+ attribute \src "ls180.v:2644.2-2646.5"
+ switch $and$ls180.v:2644$402_Y
+ attribute \src "ls180.v:2644.6-2644.100"
case 1'1
assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:2634.2-2636.5"
- switch $and$ls180.v:2634$404_Y
- attribute \src "ls180.v:2634.6-2634.100"
+ attribute \src "ls180.v:2647.2-2649.5"
+ switch $and$ls180.v:2647$405_Y
+ attribute \src "ls180.v:2647.6-2647.100"
case 1'1
assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1
case
sync always
update \sdram_bankmachine0_cmd_ready $0\sdram_bankmachine0_cmd_ready[0:0]
end
- attribute \src "ls180.v:263.12-263.40"
- process $proc$ls180.v:263$1702
- assign { } { }
- assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000
- sync always
- sync init
- update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0]
- end
- attribute \src "ls180.v:2638.1-2646.4"
- process $proc$ls180.v:2638$405
+ attribute \src "ls180.v:2651.1-2659.4"
+ process $proc$ls180.v:2651$406
assign { } { }
assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:2640.2-2642.5"
- switch $and$ls180.v:2640$408_Y
- attribute \src "ls180.v:2640.6-2640.100"
+ attribute \src "ls180.v:2653.2-2655.5"
+ switch $and$ls180.v:2653$409_Y
+ attribute \src "ls180.v:2653.6-2653.100"
case 1'1
assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:2643.2-2645.5"
- switch $and$ls180.v:2643$411_Y
- attribute \src "ls180.v:2643.6-2643.100"
+ attribute \src "ls180.v:2656.2-2658.5"
+ switch $and$ls180.v:2656$412_Y
+ attribute \src "ls180.v:2656.6-2656.100"
case 1'1
assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1
case
sync always
update \sdram_bankmachine1_cmd_ready $0\sdram_bankmachine1_cmd_ready[0:0]
end
- attribute \src "ls180.v:264.5-264.38"
- process $proc$ls180.v:264$1703
- assign { } { }
- assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0
- sync always
- sync init
- update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0]
- end
- attribute \src "ls180.v:2647.1-2655.4"
- process $proc$ls180.v:2647$412
+ attribute \src "ls180.v:2660.1-2668.4"
+ process $proc$ls180.v:2660$413
assign { } { }
assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:2649.2-2651.5"
- switch $and$ls180.v:2649$415_Y
- attribute \src "ls180.v:2649.6-2649.100"
+ attribute \src "ls180.v:2662.2-2664.5"
+ switch $and$ls180.v:2662$416_Y
+ attribute \src "ls180.v:2662.6-2662.100"
case 1'1
assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:2652.2-2654.5"
- switch $and$ls180.v:2652$418_Y
- attribute \src "ls180.v:2652.6-2652.100"
+ attribute \src "ls180.v:2665.2-2667.5"
+ switch $and$ls180.v:2665$419_Y
+ attribute \src "ls180.v:2665.6-2665.100"
case 1'1
assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1
case
sync always
update \sdram_bankmachine2_cmd_ready $0\sdram_bankmachine2_cmd_ready[0:0]
end
- attribute \src "ls180.v:2656.1-2664.4"
- process $proc$ls180.v:2656$419
+ attribute \src "ls180.v:2669.1-2677.4"
+ process $proc$ls180.v:2669$420
assign { } { }
assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'0
- attribute \src "ls180.v:2658.2-2660.5"
- switch $and$ls180.v:2658$422_Y
- attribute \src "ls180.v:2658.6-2658.100"
+ attribute \src "ls180.v:2671.2-2673.5"
+ switch $and$ls180.v:2671$423_Y
+ attribute \src "ls180.v:2671.6-2671.100"
case 1'1
assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:2661.2-2663.5"
- switch $and$ls180.v:2661$425_Y
- attribute \src "ls180.v:2661.6-2661.100"
+ attribute \src "ls180.v:2674.2-2676.5"
+ switch $and$ls180.v:2674$426_Y
+ attribute \src "ls180.v:2674.6-2674.100"
case 1'1
assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1
case
sync always
update \sdram_bankmachine3_cmd_ready $0\sdram_bankmachine3_cmd_ready[0:0]
end
- attribute \src "ls180.v:2669.1-2741.4"
- process $proc$ls180.v:2669$428
+ attribute \src "ls180.v:267.12-267.40"
+ process $proc$ls180.v:267$1709
+ assign { } { }
+ assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0]
+ end
+ attribute \src "ls180.v:268.5-268.38"
+ process $proc$ls180.v:268$1710
+ assign { } { }
+ assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0]
+ end
+ attribute \src "ls180.v:2682.1-2754.4"
+ process $proc$ls180.v:2682$429
assign { } { }
assign { } { }
assign { } { }
assign $0\sdram_steerer_sel[1:0] 2'00
assign $0\sdram_en0[0:0] 1'0
assign $0\sdram_en1[0:0] 1'0
+ assign $0\sdram_choose_req_want_writes[0:0] 1'0
assign $0\sdram_choose_req_want_reads[0:0] 1'0
assign { } { }
- assign $0\sdram_choose_req_want_writes[0:0] 1'0
assign $0\sdram_cmd_ready[0:0] 1'0
assign { } { }
assign $0\sdram_choose_req_want_activates[0:0] \sdram_ras_allowed
assign $0\subfragments_multiplexer_next_state[2:0] \subfragments_multiplexer_state
- attribute \src "ls180.v:2681.2-2740.9"
+ attribute \src "ls180.v:2694.2-2753.9"
switch \subfragments_multiplexer_state
attribute \src "ls180.v:0.0-0.0"
case 3'001
assign $0\sdram_en1[0:0] 1'1
assign $0\sdram_choose_req_want_writes[0:0] 1'1
assign $0\sdram_steerer_sel[1:0] 2'10
- attribute \src "ls180.v:2685.4-2691.7"
+ attribute \src "ls180.v:2698.4-2704.7"
switch 1'1
- attribute \src "ls180.v:2685.8-2685.12"
+ attribute \src "ls180.v:2698.8-2698.12"
case 1'1
- assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2686$435_Y
+ assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2699$436_Y
case
end
- attribute \src "ls180.v:2693.4-2697.7"
+ attribute \src "ls180.v:2706.4-2710.7"
switch \sdram_read_available
- attribute \src "ls180.v:2693.8-2693.28"
+ attribute \src "ls180.v:2706.8-2706.28"
case 1'1
- attribute \src "ls180.v:2694.5-2696.8"
- switch $or$ls180.v:2694$437_Y
- attribute \src "ls180.v:2694.9-2694.53"
+ attribute \src "ls180.v:2707.5-2709.8"
+ switch $or$ls180.v:2707$438_Y
+ attribute \src "ls180.v:2707.9-2707.53"
case 1'1
assign $0\subfragments_multiplexer_next_state[2:0] 3'011
case
end
case
end
- attribute \src "ls180.v:2698.4-2700.7"
+ attribute \src "ls180.v:2711.4-2713.7"
switch \sdram_go_to_refresh
- attribute \src "ls180.v:2698.8-2698.27"
+ attribute \src "ls180.v:2711.8-2711.27"
case 1'1
assign $0\subfragments_multiplexer_next_state[2:0] 3'010
case
case 3'010
assign $0\sdram_steerer_sel[1:0] 2'11
assign $0\sdram_cmd_ready[0:0] 1'1
- attribute \src "ls180.v:2705.4-2707.7"
+ attribute \src "ls180.v:2718.4-2720.7"
switch \sdram_cmd_last
- attribute \src "ls180.v:2705.8-2705.22"
+ attribute \src "ls180.v:2718.8-2718.22"
case 1'1
assign $0\subfragments_multiplexer_next_state[2:0] 3'000
case
end
attribute \src "ls180.v:0.0-0.0"
case 3'011
- attribute \src "ls180.v:2710.4-2712.7"
+ attribute \src "ls180.v:2723.4-2725.7"
switch \sdram_twtrcon_ready
- attribute \src "ls180.v:2710.8-2710.27"
+ attribute \src "ls180.v:2723.8-2723.27"
case 1'1
assign $0\subfragments_multiplexer_next_state[2:0] 3'000
case
assign $0\sdram_en0[0:0] 1'1
assign $0\sdram_choose_req_want_reads[0:0] 1'1
assign $0\sdram_steerer_sel[1:0] 2'10
- attribute \src "ls180.v:2723.4-2729.7"
+ attribute \src "ls180.v:2736.4-2742.7"
switch 1'1
- attribute \src "ls180.v:2723.8-2723.12"
+ attribute \src "ls180.v:2736.8-2736.12"
case 1'1
- assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2724$444_Y
+ assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2737$445_Y
case
end
- attribute \src "ls180.v:2731.4-2735.7"
+ attribute \src "ls180.v:2744.4-2748.7"
switch \sdram_write_available
- attribute \src "ls180.v:2731.8-2731.29"
+ attribute \src "ls180.v:2744.8-2744.29"
case 1'1
- attribute \src "ls180.v:2732.5-2734.8"
- switch $or$ls180.v:2732$446_Y
- attribute \src "ls180.v:2732.9-2732.52"
+ attribute \src "ls180.v:2745.5-2747.8"
+ switch $or$ls180.v:2745$447_Y
+ attribute \src "ls180.v:2745.9-2745.52"
case 1'1
assign $0\subfragments_multiplexer_next_state[2:0] 3'100
case
end
case
end
- attribute \src "ls180.v:2736.4-2738.7"
+ attribute \src "ls180.v:2749.4-2751.7"
switch \sdram_go_to_refresh
- attribute \src "ls180.v:2736.8-2736.27"
+ attribute \src "ls180.v:2749.8-2749.27"
case 1'1
assign $0\subfragments_multiplexer_next_state[2:0] 3'010
case
update \sdram_en1 $0\sdram_en1[0:0]
update \subfragments_multiplexer_next_state $0\subfragments_multiplexer_next_state[2:0]
end
- attribute \src "ls180.v:2765.1-2778.4"
- process $proc$ls180.v:2765$575
+ attribute \src "ls180.v:2778.1-2791.4"
+ process $proc$ls180.v:2778$576
assign { } { }
assign { } { }
- assign $0\sdram_interface_wdata_we[1:0] 2'00
assign $0\sdram_interface_wdata[15:0] 16'0000000000000000
- attribute \src "ls180.v:2768.2-2777.9"
+ assign $0\sdram_interface_wdata_we[1:0] 2'00
+ attribute \src "ls180.v:2781.2-2790.9"
switch \subfragments_new_master_wdata_ready
attribute \src "ls180.v:0.0-0.0"
case 1'1
update \sdram_interface_wdata $0\sdram_interface_wdata[15:0]
update \sdram_interface_wdata_we $0\sdram_interface_wdata_we[1:0]
end
- attribute \src "ls180.v:2785.1-2795.4"
- process $proc$ls180.v:2785$577
+ attribute \src "ls180.v:2798.1-2808.4"
+ process $proc$ls180.v:2798$578
assign { } { }
assign $0\litedram_wb_dat_w[15:0] 16'0000000000000000
- attribute \src "ls180.v:2787.2-2794.9"
+ attribute \src "ls180.v:2800.2-2807.9"
switch \converter_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
sync always
update \litedram_wb_dat_w $0\litedram_wb_dat_w[15:0]
end
- attribute \src "ls180.v:279.12-279.41"
- process $proc$ls180.v:279$1704
+ attribute \src "ls180.v:2810.1-2856.4"
+ process $proc$ls180.v:2810$579
assign { } { }
- assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000
- sync always
- sync init
- update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0]
- end
- attribute \src "ls180.v:2797.1-2843.4"
- process $proc$ls180.v:2797$578
assign { } { }
assign { } { }
assign { } { }
assign $0\litedram_wb_stb[0:0] 1'0
assign $0\litedram_wb_we[0:0] 1'0
assign $0\converter_skip[0:0] 1'0
- assign { } { }
assign $0\subfragments_next_state[0:0] \subfragments_state
- attribute \src "ls180.v:2809.2-2842.9"
+ attribute \src "ls180.v:2822.2-2855.9"
switch \subfragments_state
attribute \src "ls180.v:0.0-0.0"
case 1'1
assign $0\litedram_wb_adr[29:0] { \wb_sdram_adr [28:0] \converter_counter }
- attribute \src "ls180.v:2812.4-2819.11"
+ attribute \src "ls180.v:2825.4-2832.11"
switch \converter_counter
attribute \src "ls180.v:0.0-0.0"
case 1'0
assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [3:2]
case
end
- attribute \src "ls180.v:2820.4-2833.7"
- switch $and$ls180.v:2820$579_Y
- attribute \src "ls180.v:2820.8-2820.37"
+ attribute \src "ls180.v:2833.4-2846.7"
+ switch $and$ls180.v:2833$580_Y
+ attribute \src "ls180.v:2833.8-2833.37"
case 1'1
- assign $0\converter_skip[0:0] $eq$ls180.v:2821$580_Y
+ assign $0\converter_skip[0:0] $eq$ls180.v:2834$581_Y
assign $0\litedram_wb_we[0:0] \wb_sdram_we
- assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2823$581_Y
- assign $0\litedram_wb_stb[0:0] $not$ls180.v:2824$582_Y
- attribute \src "ls180.v:2825.5-2832.8"
- switch $or$ls180.v:2825$583_Y
- attribute \src "ls180.v:2825.9-2825.43"
+ assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2836$582_Y
+ assign $0\litedram_wb_stb[0:0] $not$ls180.v:2837$583_Y
+ attribute \src "ls180.v:2838.5-2845.8"
+ switch $or$ls180.v:2838$584_Y
+ attribute \src "ls180.v:2838.9-2838.43"
case 1'1
- assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2826$584_Y
+ assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2839$585_Y
assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2828.6-2831.9"
- switch $eq$ls180.v:2828$585_Y
- attribute \src "ls180.v:2828.10-2828.37"
+ attribute \src "ls180.v:2841.6-2844.9"
+ switch $eq$ls180.v:2841$586_Y
+ attribute \src "ls180.v:2841.10-2841.37"
case 1'1
assign $0\wb_sdram_ack[0:0] 1'1
assign $0\subfragments_next_state[0:0] 1'0
case
assign $0\converter_counter_subfragments_next_value[0:0] 1'0
assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1
- attribute \src "ls180.v:2838.4-2840.7"
- switch $and$ls180.v:2838$586_Y
- attribute \src "ls180.v:2838.8-2838.37"
+ attribute \src "ls180.v:2851.4-2853.7"
+ switch $and$ls180.v:2851$587_Y
+ attribute \src "ls180.v:2851.8-2851.37"
case 1'1
assign $0\subfragments_next_state[0:0] 1'1
case
update \converter_counter_subfragments_next_value $0\converter_counter_subfragments_next_value[0:0]
update \converter_counter_subfragments_next_value_ce $0\converter_counter_subfragments_next_value_ce[0:0]
end
- attribute \src "ls180.v:280.5-280.39"
- process $proc$ls180.v:280$1705
+ attribute \src "ls180.v:283.12-283.41"
+ process $proc$ls180.v:283$1711
+ assign { } { }
+ assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0]
+ end
+ attribute \src "ls180.v:284.5-284.39"
+ process $proc$ls180.v:284$1712
assign { } { }
assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0
sync always
sync init
update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0]
end
- attribute \src "ls180.v:281.12-281.43"
- process $proc$ls180.v:281$1706
+ attribute \src "ls180.v:285.12-285.43"
+ process $proc$ls180.v:285$1713
assign { } { }
assign $1\sdram_master_p0_address[12:0] 13'0000000000000
sync always
sync init
update \sdram_master_p0_address $1\sdram_master_p0_address[12:0]
end
- attribute \src "ls180.v:282.11-282.38"
- process $proc$ls180.v:282$1707
+ attribute \src "ls180.v:286.11-286.38"
+ process $proc$ls180.v:286$1714
assign { } { }
assign $1\sdram_master_p0_bank[1:0] 2'00
sync always
sync init
update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0]
end
- attribute \src "ls180.v:283.5-283.33"
- process $proc$ls180.v:283$1708
+ attribute \src "ls180.v:287.5-287.33"
+ process $proc$ls180.v:287$1715
assign { } { }
assign $1\sdram_master_p0_cas_n[0:0] 1'1
sync always
sync init
update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0]
end
- attribute \src "ls180.v:284.5-284.32"
- process $proc$ls180.v:284$1709
+ attribute \src "ls180.v:288.5-288.32"
+ process $proc$ls180.v:288$1716
assign { } { }
assign $1\sdram_master_p0_cs_n[0:0] 1'1
sync always
sync init
update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0]
end
- attribute \src "ls180.v:285.5-285.33"
- process $proc$ls180.v:285$1710
+ attribute \src "ls180.v:289.5-289.33"
+ process $proc$ls180.v:289$1717
assign { } { }
assign $1\sdram_master_p0_ras_n[0:0] 1'1
sync always
sync init
update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0]
end
- attribute \src "ls180.v:286.5-286.32"
- process $proc$ls180.v:286$1711
+ attribute \src "ls180.v:290.5-290.32"
+ process $proc$ls180.v:290$1718
assign { } { }
assign $1\sdram_master_p0_we_n[0:0] 1'1
sync always
sync init
update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0]
end
- attribute \src "ls180.v:287.5-287.31"
- process $proc$ls180.v:287$1712
- assign { } { }
- assign $1\sdram_master_p0_cke[0:0] 1'0
- sync always
- sync init
- update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0]
- end
- attribute \src "ls180.v:288.5-288.31"
- process $proc$ls180.v:288$1713
- assign { } { }
- assign $1\sdram_master_p0_odt[0:0] 1'0
- sync always
- sync init
- update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0]
- end
- attribute \src "ls180.v:2888.1-2893.4"
- process $proc$ls180.v:2888$618
+ attribute \src "ls180.v:2901.1-2906.4"
+ process $proc$ls180.v:2901$619
assign { } { }
assign $0\tx_clear[0:0] 1'0
- attribute \src "ls180.v:2890.2-2892.5"
- switch $and$ls180.v:2890$619_Y
- attribute \src "ls180.v:2890.6-2890.59"
+ attribute \src "ls180.v:2903.2-2905.5"
+ switch $and$ls180.v:2903$620_Y
+ attribute \src "ls180.v:2903.6-2903.59"
case 1'1
assign $0\tx_clear[0:0] 1'1
case
sync always
update \tx_clear $0\tx_clear[0:0]
end
- attribute \src "ls180.v:289.5-289.35"
- process $proc$ls180.v:289$1714
- assign { } { }
- assign $1\sdram_master_p0_reset_n[0:0] 1'0
- sync always
- sync init
- update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0]
- end
- attribute \src "ls180.v:2894.1-2898.4"
- process $proc$ls180.v:2894$620
+ attribute \src "ls180.v:2907.1-2911.4"
+ process $proc$ls180.v:2907$621
assign { } { }
assign { } { }
assign $0\eventmanager_status_w[1:0] [0] \tx_status
sync always
update \eventmanager_status_w $0\eventmanager_status_w[1:0]
end
- attribute \src "ls180.v:2899.1-2904.4"
- process $proc$ls180.v:2899$621
+ attribute \src "ls180.v:291.5-291.31"
+ process $proc$ls180.v:291$1719
+ assign { } { }
+ assign $1\sdram_master_p0_cke[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0]
+ end
+ attribute \src "ls180.v:2912.1-2917.4"
+ process $proc$ls180.v:2912$622
assign { } { }
assign $0\rx_clear[0:0] 1'0
- attribute \src "ls180.v:2901.2-2903.5"
- switch $and$ls180.v:2901$622_Y
- attribute \src "ls180.v:2901.6-2901.59"
+ attribute \src "ls180.v:2914.2-2916.5"
+ switch $and$ls180.v:2914$623_Y
+ attribute \src "ls180.v:2914.6-2914.59"
case 1'1
assign $0\rx_clear[0:0] 1'1
case
sync always
update \rx_clear $0\rx_clear[0:0]
end
- attribute \src "ls180.v:290.5-290.33"
- process $proc$ls180.v:290$1715
- assign { } { }
- assign $1\sdram_master_p0_act_n[0:0] 1'1
- sync always
- sync init
- update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0]
- end
- attribute \src "ls180.v:2905.1-2909.4"
- process $proc$ls180.v:2905$623
+ attribute \src "ls180.v:2918.1-2922.4"
+ process $proc$ls180.v:2918$624
assign { } { }
assign { } { }
assign $0\eventmanager_pending_w[1:0] [0] \tx_pending
sync always
update \eventmanager_pending_w $0\eventmanager_pending_w[1:0]
end
- attribute \src "ls180.v:291.12-291.42"
- process $proc$ls180.v:291$1716
+ attribute \src "ls180.v:292.5-292.31"
+ process $proc$ls180.v:292$1720
assign { } { }
- assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000
+ assign $1\sdram_master_p0_odt[0:0] 1'0
sync always
sync init
- update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0]
+ update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0]
end
- attribute \src "ls180.v:292.5-292.37"
- process $proc$ls180.v:292$1717
+ attribute \src "ls180.v:293.5-293.35"
+ process $proc$ls180.v:293$1721
assign { } { }
- assign $1\sdram_master_p0_wrdata_en[0:0] 1'0
+ assign $1\sdram_master_p0_reset_n[0:0] 1'0
sync always
sync init
- update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0]
+ update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0]
+ end
+ attribute \src "ls180.v:294.5-294.33"
+ process $proc$ls180.v:294$1722
+ assign { } { }
+ assign $1\sdram_master_p0_act_n[0:0] 1'1
+ sync always
+ sync init
+ update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0]
end
- attribute \src "ls180.v:2927.1-2934.4"
- process $proc$ls180.v:2927$631
+ attribute \src "ls180.v:2940.1-2947.4"
+ process $proc$ls180.v:2940$632
assign { } { }
assign $0\tx_fifo_wrport_adr[3:0] 4'0000
- attribute \src "ls180.v:2929.2-2933.5"
+ attribute \src "ls180.v:2942.2-2946.5"
switch \tx_fifo_replace
- attribute \src "ls180.v:2929.6-2929.21"
+ attribute \src "ls180.v:2942.6-2942.21"
case 1'1
- assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2930$632_Y
- attribute \src "ls180.v:2931.6-2931.10"
+ assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2943$633_Y
+ attribute \src "ls180.v:2944.6-2944.10"
case
assign $0\tx_fifo_wrport_adr[3:0] \tx_fifo_produce
end
sync always
update \tx_fifo_wrport_adr $0\tx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:293.11-293.45"
- process $proc$ls180.v:293$1718
+ attribute \src "ls180.v:295.12-295.42"
+ process $proc$ls180.v:295$1723
assign { } { }
- assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00
+ assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000
sync always
sync init
- update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0]
+ update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0]
end
- attribute \src "ls180.v:294.5-294.37"
- process $proc$ls180.v:294$1719
+ attribute \src "ls180.v:296.5-296.37"
+ process $proc$ls180.v:296$1724
assign { } { }
- assign $1\sdram_master_p0_rddata_en[0:0] 1'0
+ assign $1\sdram_master_p0_wrdata_en[0:0] 1'0
sync always
sync init
- update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0]
+ update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0]
+ end
+ attribute \src "ls180.v:297.11-297.45"
+ process $proc$ls180.v:297$1725
+ assign { } { }
+ assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00
+ sync always
+ sync init
+ update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0]
end
- attribute \src "ls180.v:2957.1-2964.4"
- process $proc$ls180.v:2957$642
+ attribute \src "ls180.v:2970.1-2977.4"
+ process $proc$ls180.v:2970$643
assign { } { }
assign $0\rx_fifo_wrport_adr[3:0] 4'0000
- attribute \src "ls180.v:2959.2-2963.5"
+ attribute \src "ls180.v:2972.2-2976.5"
switch \rx_fifo_replace
- attribute \src "ls180.v:2959.6-2959.21"
+ attribute \src "ls180.v:2972.6-2972.21"
case 1'1
- assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2960$643_Y
- attribute \src "ls180.v:2961.6-2961.10"
+ assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2973$644_Y
+ attribute \src "ls180.v:2974.6-2974.10"
case
assign $0\rx_fifo_wrport_adr[3:0] \rx_fifo_produce
end
sync always
update \rx_fifo_wrport_adr $0\rx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:2973.1-2983.4"
- process $proc$ls180.v:2973$649
+ attribute \src "ls180.v:298.5-298.37"
+ process $proc$ls180.v:298$1726
assign { } { }
- assign { } { }
- assign $0\gpio0_pads_gpio0i[7:0] [0] \libresocsim_libresoc_constraintmanager_obj_gpio_i [0]
- assign $0\gpio0_pads_gpio0i[7:0] [1] \libresocsim_libresoc_constraintmanager_obj_gpio_i [1]
- assign $0\gpio0_pads_gpio0i[7:0] [2] \libresocsim_libresoc_constraintmanager_obj_gpio_i [2]
- assign $0\gpio0_pads_gpio0i[7:0] [3] \libresocsim_libresoc_constraintmanager_obj_gpio_i [3]
- assign $0\gpio0_pads_gpio0i[7:0] [4] \libresocsim_libresoc_constraintmanager_obj_gpio_i [4]
- assign $0\gpio0_pads_gpio0i[7:0] [5] \libresocsim_libresoc_constraintmanager_obj_gpio_i [5]
- assign $0\gpio0_pads_gpio0i[7:0] [6] \libresocsim_libresoc_constraintmanager_obj_gpio_i [6]
- assign $0\gpio0_pads_gpio0i[7:0] [7] \libresocsim_libresoc_constraintmanager_obj_gpio_i [7]
+ assign $1\sdram_master_p0_rddata_en[0:0] 1'0
sync always
- update \gpio0_pads_gpio0i $0\gpio0_pads_gpio0i[7:0]
+ sync init
+ update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:2984.1-2994.4"
- process $proc$ls180.v:2984$650
+ attribute \src "ls180.v:2986.1-2996.4"
+ process $proc$ls180.v:2986$650
assign { } { }
assign { } { }
- assign $0\gpio1_pads_gpio1i[7:0] [0] \libresocsim_libresoc_constraintmanager_obj_gpio_i [8]
- assign $0\gpio1_pads_gpio1i[7:0] [1] \libresocsim_libresoc_constraintmanager_obj_gpio_i [9]
- assign $0\gpio1_pads_gpio1i[7:0] [2] \libresocsim_libresoc_constraintmanager_obj_gpio_i [10]
- assign $0\gpio1_pads_gpio1i[7:0] [3] \libresocsim_libresoc_constraintmanager_obj_gpio_i [11]
- assign $0\gpio1_pads_gpio1i[7:0] [4] \libresocsim_libresoc_constraintmanager_obj_gpio_i [12]
- assign $0\gpio1_pads_gpio1i[7:0] [5] \libresocsim_libresoc_constraintmanager_obj_gpio_i [13]
- assign $0\gpio1_pads_gpio1i[7:0] [6] \libresocsim_libresoc_constraintmanager_obj_gpio_i [14]
- assign $0\gpio1_pads_gpio1i[7:0] [7] \libresocsim_libresoc_constraintmanager_obj_gpio_i [15]
+ assign $0\gpio0_pads_gpio0i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [0]
+ assign $0\gpio0_pads_gpio0i[7:0] [1] \libresocsim_libresoc_constraintmanager_gpio_i [1]
+ assign $0\gpio0_pads_gpio0i[7:0] [2] \libresocsim_libresoc_constraintmanager_gpio_i [2]
+ assign $0\gpio0_pads_gpio0i[7:0] [3] \libresocsim_libresoc_constraintmanager_gpio_i [3]
+ assign $0\gpio0_pads_gpio0i[7:0] [4] \libresocsim_libresoc_constraintmanager_gpio_i [4]
+ assign $0\gpio0_pads_gpio0i[7:0] [5] \libresocsim_libresoc_constraintmanager_gpio_i [5]
+ assign $0\gpio0_pads_gpio0i[7:0] [6] \libresocsim_libresoc_constraintmanager_gpio_i [6]
+ assign $0\gpio0_pads_gpio0i[7:0] [7] \libresocsim_libresoc_constraintmanager_gpio_i [7]
sync always
- update \gpio1_pads_gpio1i $0\gpio1_pads_gpio1i[7:0]
+ update \gpio0_pads_gpio0i $0\gpio0_pads_gpio0i[7:0]
end
- attribute \src "ls180.v:2995.1-3013.4"
- process $proc$ls180.v:2995$651
+ attribute \src "ls180.v:2997.1-3007.4"
+ process $proc$ls180.v:2997$651
assign { } { }
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [0] \gpio0_pads_gpio0o [0]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [1] \gpio0_pads_gpio0o [1]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [2] \gpio0_pads_gpio0o [2]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [3] \gpio0_pads_gpio0o [3]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [4] \gpio0_pads_gpio0o [4]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [5] \gpio0_pads_gpio0o [5]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [6] \gpio0_pads_gpio0o [6]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [7] \gpio0_pads_gpio0o [7]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [8] \gpio1_pads_gpio1o [0]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [9] \gpio1_pads_gpio1o [1]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [10] \gpio1_pads_gpio1o [2]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [11] \gpio1_pads_gpio1o [3]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [12] \gpio1_pads_gpio1o [4]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [13] \gpio1_pads_gpio1o [5]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [14] \gpio1_pads_gpio1o [6]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [15] \gpio1_pads_gpio1o [7]
+ assign $0\gpio1_pads_gpio1i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [8]
+ assign $0\gpio1_pads_gpio1i[7:0] [1] \libresocsim_libresoc_constraintmanager_gpio_i [9]
+ assign $0\gpio1_pads_gpio1i[7:0] [2] \libresocsim_libresoc_constraintmanager_gpio_i [10]
+ assign $0\gpio1_pads_gpio1i[7:0] [3] \libresocsim_libresoc_constraintmanager_gpio_i [11]
+ assign $0\gpio1_pads_gpio1i[7:0] [4] \libresocsim_libresoc_constraintmanager_gpio_i [12]
+ assign $0\gpio1_pads_gpio1i[7:0] [5] \libresocsim_libresoc_constraintmanager_gpio_i [13]
+ assign $0\gpio1_pads_gpio1i[7:0] [6] \libresocsim_libresoc_constraintmanager_gpio_i [14]
+ assign $0\gpio1_pads_gpio1i[7:0] [7] \libresocsim_libresoc_constraintmanager_gpio_i [15]
sync always
- update \libresocsim_libresoc_constraintmanager_obj_gpio_o $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0]
+ update \gpio1_pads_gpio1i $0\gpio1_pads_gpio1i[7:0]
end
- attribute \src "ls180.v:301.11-301.31"
- process $proc$ls180.v:301$1720
+ attribute \src "ls180.v:3008.1-3026.4"
+ process $proc$ls180.v:3008$652
+ assign { } { }
+ assign { } { }
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [0] \gpio0_pads_gpio0o [0]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [1] \gpio0_pads_gpio0o [1]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [2] \gpio0_pads_gpio0o [2]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [3] \gpio0_pads_gpio0o [3]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [4] \gpio0_pads_gpio0o [4]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [5] \gpio0_pads_gpio0o [5]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [6] \gpio0_pads_gpio0o [6]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [7] \gpio0_pads_gpio0o [7]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [8] \gpio1_pads_gpio1o [0]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [9] \gpio1_pads_gpio1o [1]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [10] \gpio1_pads_gpio1o [2]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [11] \gpio1_pads_gpio1o [3]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [12] \gpio1_pads_gpio1o [4]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [13] \gpio1_pads_gpio1o [5]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [14] \gpio1_pads_gpio1o [6]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [15] \gpio1_pads_gpio1o [7]
+ sync always
+ update \libresocsim_libresoc_constraintmanager_gpio_o $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+ end
+ attribute \src "ls180.v:3027.1-3045.4"
+ process $proc$ls180.v:3027$653
+ assign { } { }
+ assign { } { }
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [0] \gpio0_pads_gpio0oe [0]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [1] \gpio0_pads_gpio0oe [1]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [2] \gpio0_pads_gpio0oe [2]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [3] \gpio0_pads_gpio0oe [3]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [4] \gpio0_pads_gpio0oe [4]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [5] \gpio0_pads_gpio0oe [5]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [6] \gpio0_pads_gpio0oe [6]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [7] \gpio0_pads_gpio0oe [7]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [8] \gpio1_pads_gpio1oe [0]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [9] \gpio1_pads_gpio1oe [1]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [10] \gpio1_pads_gpio1oe [2]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [11] \gpio1_pads_gpio1oe [3]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [12] \gpio1_pads_gpio1oe [4]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [13] \gpio1_pads_gpio1oe [5]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [14] \gpio1_pads_gpio1oe [6]
+ assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [15] \gpio1_pads_gpio1oe [7]
+ sync always
+ update \libresocsim_libresoc_constraintmanager_gpio_oe $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+ end
+ attribute \src "ls180.v:305.11-305.31"
+ process $proc$ls180.v:305$1727
assign { } { }
assign $1\sdram_storage[3:0] 4'0001
sync always
sync init
update \sdram_storage $1\sdram_storage[3:0]
end
- attribute \src "ls180.v:3014.1-3032.4"
- process $proc$ls180.v:3014$652
- assign { } { }
- assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [0] \gpio0_pads_gpio0oe [0]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [1] \gpio0_pads_gpio0oe [1]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [2] \gpio0_pads_gpio0oe [2]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [3] \gpio0_pads_gpio0oe [3]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [4] \gpio0_pads_gpio0oe [4]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [5] \gpio0_pads_gpio0oe [5]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [6] \gpio0_pads_gpio0oe [6]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [7] \gpio0_pads_gpio0oe [7]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [8] \gpio1_pads_gpio1oe [0]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [9] \gpio1_pads_gpio1oe [1]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [10] \gpio1_pads_gpio1oe [2]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [11] \gpio1_pads_gpio1oe [3]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [12] \gpio1_pads_gpio1oe [4]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [13] \gpio1_pads_gpio1oe [5]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [14] \gpio1_pads_gpio1oe [6]
- assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [15] \gpio1_pads_gpio1oe [7]
- sync always
- update \libresocsim_libresoc_constraintmanager_obj_gpio_oe $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0]
- end
- attribute \src "ls180.v:302.5-302.20"
- process $proc$ls180.v:302$1721
- assign { } { }
- assign $1\sdram_re[0:0] 1'0
- sync always
- sync init
- update \sdram_re $1\sdram_re[0:0]
- end
- attribute \src "ls180.v:303.11-303.39"
- process $proc$ls180.v:303$1722
- assign { } { }
- assign $1\sdram_command_storage[5:0] 6'000000
- sync always
- sync init
- update \sdram_command_storage $1\sdram_command_storage[5:0]
- end
- attribute \src "ls180.v:3037.1-3073.4"
- process $proc$ls180.v:3037$653
+ attribute \src "ls180.v:3050.1-3086.4"
+ process $proc$ls180.v:3050$654
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
+ assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0
+ assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0
assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] 0
assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'0
assign { } { }
assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0
assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000
assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0
- assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0
- assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0
assign $0\libresocsim_next_state[1:0] \libresocsim_state
- attribute \src "ls180.v:3048.2-3072.9"
+ attribute \src "ls180.v:3061.2-3085.9"
switch \libresocsim_state
attribute \src "ls180.v:0.0-0.0"
case 2'01
case
assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] \libresocsim_libresocsim_wishbone_dat_w [7:0]
assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'1
- attribute \src "ls180.v:3064.4-3070.7"
- switch $and$ls180.v:3064$654_Y
- attribute \src "ls180.v:3064.8-3064.85"
+ attribute \src "ls180.v:3077.4-3083.7"
+ switch $and$ls180.v:3077$655_Y
+ attribute \src "ls180.v:3077.8-3077.85"
case 1'1
assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] \libresocsim_libresocsim_wishbone_adr [13:0]
assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1
- assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3067$656_Y
+ assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3080$657_Y
assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1
assign $0\libresocsim_next_state[1:0] 2'01
case
update \libresocsim_libresocsim_we_libresocsim_next_value2 $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0]
update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
end
- attribute \src "ls180.v:304.5-304.28"
- process $proc$ls180.v:304$1723
+ attribute \src "ls180.v:306.5-306.20"
+ process $proc$ls180.v:306$1728
assign { } { }
- assign $1\sdram_command_re[0:0] 1'0
+ assign $1\sdram_re[0:0] 1'0
sync always
sync init
- update \sdram_command_re $1\sdram_command_re[0:0]
+ update \sdram_re $1\sdram_re[0:0]
end
- attribute \src "ls180.v:308.5-308.33"
- process $proc$ls180.v:308$1724
+ attribute \src "ls180.v:307.11-307.39"
+ process $proc$ls180.v:307$1729
assign { } { }
- assign $0\sdram_command_issue_w[0:0] 1'0
+ assign $1\sdram_command_storage[5:0] 6'000000
sync always
- update \sdram_command_issue_w $0\sdram_command_issue_w[0:0]
sync init
+ update \sdram_command_storage $1\sdram_command_storage[5:0]
end
- attribute \src "ls180.v:309.12-309.41"
- process $proc$ls180.v:309$1725
+ attribute \src "ls180.v:308.5-308.28"
+ process $proc$ls180.v:308$1730
assign { } { }
- assign $1\sdram_address_storage[12:0] 13'0000000000000
+ assign $1\sdram_command_re[0:0] 1'0
sync always
sync init
- update \sdram_address_storage $1\sdram_address_storage[12:0]
+ update \sdram_command_re $1\sdram_command_re[0:0]
end
- attribute \src "ls180.v:3092.1-3100.4"
- process $proc$ls180.v:3092$669
+ attribute \src "ls180.v:3105.1-3113.4"
+ process $proc$ls180.v:3105$670
assign { } { }
assign { } { }
- assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3094$670_Y
- assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3095$671_Y
- assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3096$672_Y
- assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3097$673_Y
- assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3098$674_Y
- assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3099$675_Y
+ assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3107$671_Y
+ assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3108$672_Y
+ assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3109$673_Y
+ assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3110$674_Y
+ assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3111$675_Y
+ assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3112$676_Y
sync always
update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0]
end
- attribute \src "ls180.v:310.5-310.28"
- process $proc$ls180.v:310$1726
- assign { } { }
- assign $1\sdram_address_re[0:0] 1'0
- sync always
- sync init
- update \sdram_address_re $1\sdram_address_re[0:0]
- end
- attribute \src "ls180.v:311.11-311.40"
- process $proc$ls180.v:311$1727
+ attribute \src "ls180.v:312.5-312.33"
+ process $proc$ls180.v:312$1731
assign { } { }
- assign $1\sdram_baddress_storage[1:0] 2'00
+ assign $0\sdram_command_issue_w[0:0] 1'0
sync always
+ update \sdram_command_issue_w $0\sdram_command_issue_w[0:0]
sync init
- update \sdram_baddress_storage $1\sdram_baddress_storage[1:0]
end
- attribute \src "ls180.v:312.5-312.29"
- process $proc$ls180.v:312$1728
+ attribute \src "ls180.v:313.12-313.41"
+ process $proc$ls180.v:313$1732
assign { } { }
- assign $1\sdram_baddress_re[0:0] 1'0
+ assign $1\sdram_address_storage[12:0] 13'0000000000000
sync always
sync init
- update \sdram_baddress_re $1\sdram_baddress_re[0:0]
+ update \sdram_address_storage $1\sdram_address_storage[12:0]
end
- attribute \src "ls180.v:313.12-313.40"
- process $proc$ls180.v:313$1729
+ attribute \src "ls180.v:314.5-314.28"
+ process $proc$ls180.v:314$1733
assign { } { }
- assign $1\sdram_wrdata_storage[15:0] 16'0000000000000000
+ assign $1\sdram_address_re[0:0] 1'0
sync always
sync init
- update \sdram_wrdata_storage $1\sdram_wrdata_storage[15:0]
+ update \sdram_address_re $1\sdram_address_re[0:0]
end
- attribute \src "ls180.v:314.5-314.27"
- process $proc$ls180.v:314$1730
+ attribute \src "ls180.v:315.11-315.40"
+ process $proc$ls180.v:315$1734
assign { } { }
- assign $1\sdram_wrdata_re[0:0] 1'0
+ assign $1\sdram_baddress_storage[1:0] 2'00
sync always
sync init
- update \sdram_wrdata_re $1\sdram_wrdata_re[0:0]
+ update \sdram_baddress_storage $1\sdram_baddress_storage[1:0]
end
- attribute \src "ls180.v:315.12-315.32"
- process $proc$ls180.v:315$1731
+ attribute \src "ls180.v:316.5-316.29"
+ process $proc$ls180.v:316$1735
assign { } { }
- assign $1\sdram_status[15:0] 16'0000000000000000
+ assign $1\sdram_baddress_re[0:0] 1'0
sync always
sync init
- update \sdram_status $1\sdram_status[15:0]
+ update \sdram_baddress_re $1\sdram_baddress_re[0:0]
end
- attribute \src "ls180.v:3151.1-3162.4"
- process $proc$ls180.v:3151$690
+ attribute \src "ls180.v:3164.1-3175.4"
+ process $proc$ls180.v:3164$691
assign { } { }
assign { } { }
assign { } { }
+ assign $0\libresocsim_error[0:0] 1'0
assign { } { }
assign { } { }
- assign $0\libresocsim_error[0:0] 1'0
- assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3155$695_Y
- assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3156$706_Y [31:0]
- attribute \src "ls180.v:3157.2-3161.5"
+ assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3168$696_Y
+ assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3169$707_Y [31:0]
+ attribute \src "ls180.v:3170.2-3174.5"
switch \libresocsim_done
- attribute \src "ls180.v:3157.6-3157.22"
+ attribute \src "ls180.v:3170.6-3170.22"
case 1'1
assign $0\libresocsim_shared_dat_r[31:0] 32'11111111111111111111111111111111
assign $0\libresocsim_shared_ack[0:0] 1'1
update \libresocsim_shared_ack $0\libresocsim_shared_ack[0:0]
update \libresocsim_error $0\libresocsim_error[0:0]
end
- attribute \src "ls180.v:3437.1-3453.4"
- process $proc$ls180.v:3437$1115
+ attribute \src "ls180.v:317.12-317.40"
+ process $proc$ls180.v:317$1736
+ assign { } { }
+ assign $1\sdram_wrdata_storage[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \sdram_wrdata_storage $1\sdram_wrdata_storage[15:0]
+ end
+ attribute \src "ls180.v:318.5-318.27"
+ process $proc$ls180.v:318$1737
+ assign { } { }
+ assign $1\sdram_wrdata_re[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_wrdata_re $1\sdram_wrdata_re[0:0]
+ end
+ attribute \src "ls180.v:319.12-319.32"
+ process $proc$ls180.v:319$1738
+ assign { } { }
+ assign $1\sdram_status[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \sdram_status $1\sdram_status[15:0]
+ end
+ attribute \src "ls180.v:3450.1-3466.4"
+ process $proc$ls180.v:3450$1116
assign { } { }
assign $0\rhs_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:3439.2-3452.9"
+ attribute \src "ls180.v:3452.2-3465.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed0 $0\rhs_array_muxed0[0:0]
end
- attribute \src "ls180.v:345.12-345.41"
- process $proc$ls180.v:345$1732
- assign { } { }
- assign $1\sdram_interface_wdata[15:0] 16'0000000000000000
- sync always
- sync init
- update \sdram_interface_wdata $1\sdram_interface_wdata[15:0]
- end
- attribute \src "ls180.v:3454.1-3470.4"
- process $proc$ls180.v:3454$1116
+ attribute \src "ls180.v:3467.1-3483.4"
+ process $proc$ls180.v:3467$1117
assign { } { }
assign $0\rhs_array_muxed1[12:0] 13'0000000000000
- attribute \src "ls180.v:3456.2-3469.9"
+ attribute \src "ls180.v:3469.2-3482.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed1 $0\rhs_array_muxed1[12:0]
end
- attribute \src "ls180.v:346.11-346.42"
- process $proc$ls180.v:346$1733
- assign { } { }
- assign $1\sdram_interface_wdata_we[1:0] 2'00
- sync always
- sync init
- update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0]
- end
- attribute \src "ls180.v:3471.1-3487.4"
- process $proc$ls180.v:3471$1117
+ attribute \src "ls180.v:3484.1-3500.4"
+ process $proc$ls180.v:3484$1118
assign { } { }
assign $0\rhs_array_muxed2[1:0] 2'00
- attribute \src "ls180.v:3473.2-3486.9"
+ attribute \src "ls180.v:3486.2-3499.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed2 $0\rhs_array_muxed2[1:0]
end
- attribute \src "ls180.v:348.12-348.40"
- process $proc$ls180.v:348$1734
+ attribute \src "ls180.v:349.12-349.41"
+ process $proc$ls180.v:349$1739
assign { } { }
- assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000
+ assign $1\sdram_interface_wdata[15:0] 16'0000000000000000
sync always
sync init
- update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0]
+ update \sdram_interface_wdata $1\sdram_interface_wdata[15:0]
+ end
+ attribute \src "ls180.v:350.11-350.42"
+ process $proc$ls180.v:350$1740
+ assign { } { }
+ assign $1\sdram_interface_wdata_we[1:0] 2'00
+ sync always
+ sync init
+ update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0]
end
- attribute \src "ls180.v:3488.1-3504.4"
- process $proc$ls180.v:3488$1118
+ attribute \src "ls180.v:3501.1-3517.4"
+ process $proc$ls180.v:3501$1119
assign { } { }
assign $0\rhs_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:3490.2-3503.9"
+ attribute \src "ls180.v:3503.2-3516.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed3 $0\rhs_array_muxed3[0:0]
end
- attribute \src "ls180.v:349.11-349.35"
- process $proc$ls180.v:349$1735
- assign { } { }
- assign $1\sdram_dfi_p0_bank[1:0] 2'00
- sync always
- sync init
- update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0]
- end
- attribute \src "ls180.v:350.5-350.30"
- process $proc$ls180.v:350$1736
- assign { } { }
- assign $1\sdram_dfi_p0_cas_n[0:0] 1'1
- sync always
- sync init
- update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0]
- end
- attribute \src "ls180.v:3505.1-3521.4"
- process $proc$ls180.v:3505$1119
+ attribute \src "ls180.v:3518.1-3534.4"
+ process $proc$ls180.v:3518$1120
assign { } { }
assign $0\rhs_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:3507.2-3520.9"
+ attribute \src "ls180.v:3520.2-3533.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed4 $0\rhs_array_muxed4[0:0]
end
- attribute \src "ls180.v:351.5-351.29"
- process $proc$ls180.v:351$1737
+ attribute \src "ls180.v:352.12-352.40"
+ process $proc$ls180.v:352$1741
assign { } { }
- assign $1\sdram_dfi_p0_cs_n[0:0] 1'1
+ assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000
sync always
sync init
- update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0]
+ update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0]
end
- attribute \src "ls180.v:352.5-352.30"
- process $proc$ls180.v:352$1738
+ attribute \src "ls180.v:353.11-353.35"
+ process $proc$ls180.v:353$1742
assign { } { }
- assign $1\sdram_dfi_p0_ras_n[0:0] 1'1
+ assign $1\sdram_dfi_p0_bank[1:0] 2'00
sync always
sync init
- update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0]
+ update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0]
end
- attribute \src "ls180.v:3522.1-3538.4"
- process $proc$ls180.v:3522$1120
+ attribute \src "ls180.v:3535.1-3551.4"
+ process $proc$ls180.v:3535$1121
assign { } { }
assign $0\rhs_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:3524.2-3537.9"
+ attribute \src "ls180.v:3537.2-3550.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed5 $0\rhs_array_muxed5[0:0]
end
- attribute \src "ls180.v:353.5-353.29"
- process $proc$ls180.v:353$1739
+ attribute \src "ls180.v:354.5-354.30"
+ process $proc$ls180.v:354$1743
assign { } { }
- assign $1\sdram_dfi_p0_we_n[0:0] 1'1
+ assign $1\sdram_dfi_p0_cas_n[0:0] 1'1
sync always
sync init
- update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0]
+ update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0]
end
- attribute \src "ls180.v:3539.1-3555.4"
- process $proc$ls180.v:3539$1121
+ attribute \src "ls180.v:355.5-355.29"
+ process $proc$ls180.v:355$1744
+ assign { } { }
+ assign $1\sdram_dfi_p0_cs_n[0:0] 1'1
+ sync always
+ sync init
+ update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0]
+ end
+ attribute \src "ls180.v:3552.1-3568.4"
+ process $proc$ls180.v:3552$1122
assign { } { }
assign $0\t_array_muxed0[0:0] 1'0
- attribute \src "ls180.v:3541.2-3554.9"
+ attribute \src "ls180.v:3554.2-3567.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \t_array_muxed0 $0\t_array_muxed0[0:0]
end
- attribute \src "ls180.v:3556.1-3572.4"
- process $proc$ls180.v:3556$1122
+ attribute \src "ls180.v:356.5-356.30"
+ process $proc$ls180.v:356$1745
+ assign { } { }
+ assign $1\sdram_dfi_p0_ras_n[0:0] 1'1
+ sync always
+ sync init
+ update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0]
+ end
+ attribute \src "ls180.v:3569.1-3585.4"
+ process $proc$ls180.v:3569$1123
assign { } { }
assign $0\t_array_muxed1[0:0] 1'0
- attribute \src "ls180.v:3558.2-3571.9"
+ attribute \src "ls180.v:3571.2-3584.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \t_array_muxed1 $0\t_array_muxed1[0:0]
end
- attribute \src "ls180.v:357.5-357.30"
- process $proc$ls180.v:357$1740
+ attribute \src "ls180.v:357.5-357.29"
+ process $proc$ls180.v:357$1746
assign { } { }
- assign $0\sdram_dfi_p0_act_n[0:0] 1'1
+ assign $1\sdram_dfi_p0_we_n[0:0] 1'1
sync always
- update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0]
sync init
+ update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0]
end
- attribute \src "ls180.v:3573.1-3589.4"
- process $proc$ls180.v:3573$1123
+ attribute \src "ls180.v:3586.1-3602.4"
+ process $proc$ls180.v:3586$1124
assign { } { }
assign $0\t_array_muxed2[0:0] 1'0
- attribute \src "ls180.v:3575.2-3588.9"
+ attribute \src "ls180.v:3588.2-3601.9"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \t_array_muxed2 $0\t_array_muxed2[0:0]
end
- attribute \src "ls180.v:359.5-359.34"
- process $proc$ls180.v:359$1741
- assign { } { }
- assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0
- sync always
- sync init
- update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0]
- end
- attribute \src "ls180.v:3590.1-3606.4"
- process $proc$ls180.v:3590$1124
+ attribute \src "ls180.v:3603.1-3619.4"
+ process $proc$ls180.v:3603$1125
assign { } { }
assign $0\rhs_array_muxed6[0:0] 1'0
- attribute \src "ls180.v:3592.2-3605.9"
+ attribute \src "ls180.v:3605.2-3618.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed6 $0\rhs_array_muxed6[0:0]
end
- attribute \src "ls180.v:3607.1-3623.4"
- process $proc$ls180.v:3607$1125
+ attribute \src "ls180.v:361.5-361.30"
+ process $proc$ls180.v:361$1747
+ assign { } { }
+ assign $0\sdram_dfi_p0_act_n[0:0] 1'1
+ sync always
+ update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:3620.1-3636.4"
+ process $proc$ls180.v:3620$1126
assign { } { }
assign $0\rhs_array_muxed7[12:0] 13'0000000000000
- attribute \src "ls180.v:3609.2-3622.9"
+ attribute \src "ls180.v:3622.2-3635.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed7 $0\rhs_array_muxed7[12:0]
end
- attribute \src "ls180.v:361.5-361.34"
- process $proc$ls180.v:361$1742
+ attribute \src "ls180.v:363.5-363.34"
+ process $proc$ls180.v:363$1748
assign { } { }
- assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0
+ assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0
sync always
sync init
- update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0]
+ update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0]
end
- attribute \src "ls180.v:3624.1-3640.4"
- process $proc$ls180.v:3624$1126
+ attribute \src "ls180.v:3637.1-3653.4"
+ process $proc$ls180.v:3637$1127
assign { } { }
assign $0\rhs_array_muxed8[1:0] 2'00
- attribute \src "ls180.v:3626.2-3639.9"
+ attribute \src "ls180.v:3639.2-3652.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed8 $0\rhs_array_muxed8[1:0]
end
- attribute \src "ls180.v:364.5-364.27"
- process $proc$ls180.v:364$1743
+ attribute \src "ls180.v:365.5-365.34"
+ process $proc$ls180.v:365$1749
assign { } { }
- assign $1\sdram_cmd_valid[0:0] 1'0
+ assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0
sync always
sync init
- update \sdram_cmd_valid $1\sdram_cmd_valid[0:0]
+ update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0]
end
- attribute \src "ls180.v:3641.1-3657.4"
- process $proc$ls180.v:3641$1127
+ attribute \src "ls180.v:3654.1-3670.4"
+ process $proc$ls180.v:3654$1128
assign { } { }
assign $0\rhs_array_muxed9[0:0] 1'0
- attribute \src "ls180.v:3643.2-3656.9"
+ attribute \src "ls180.v:3656.2-3669.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed9 $0\rhs_array_muxed9[0:0]
end
- attribute \src "ls180.v:365.5-365.27"
- process $proc$ls180.v:365$1744
- assign { } { }
- assign $1\sdram_cmd_ready[0:0] 1'0
- sync always
- sync init
- update \sdram_cmd_ready $1\sdram_cmd_ready[0:0]
- end
- attribute \src "ls180.v:3658.1-3674.4"
- process $proc$ls180.v:3658$1128
+ attribute \src "ls180.v:3671.1-3687.4"
+ process $proc$ls180.v:3671$1129
assign { } { }
assign $0\rhs_array_muxed10[0:0] 1'0
- attribute \src "ls180.v:3660.2-3673.9"
+ attribute \src "ls180.v:3673.2-3686.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed10 $0\rhs_array_muxed10[0:0]
end
- attribute \src "ls180.v:366.5-366.26"
- process $proc$ls180.v:366$1745
+ attribute \src "ls180.v:368.5-368.27"
+ process $proc$ls180.v:368$1750
assign { } { }
- assign $1\sdram_cmd_last[0:0] 1'0
- sync always
- sync init
- update \sdram_cmd_last $1\sdram_cmd_last[0:0]
- end
- attribute \src "ls180.v:367.12-367.39"
- process $proc$ls180.v:367$1746
- assign { } { }
- assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\sdram_cmd_valid[0:0] 1'0
sync always
sync init
- update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0]
+ update \sdram_cmd_valid $1\sdram_cmd_valid[0:0]
end
- attribute \src "ls180.v:3675.1-3691.4"
- process $proc$ls180.v:3675$1129
+ attribute \src "ls180.v:3688.1-3704.4"
+ process $proc$ls180.v:3688$1130
assign { } { }
assign $0\rhs_array_muxed11[0:0] 1'0
- attribute \src "ls180.v:3677.2-3690.9"
+ attribute \src "ls180.v:3690.2-3703.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed11 $0\rhs_array_muxed11[0:0]
end
- attribute \src "ls180.v:368.11-368.38"
- process $proc$ls180.v:368$1747
+ attribute \src "ls180.v:369.5-369.27"
+ process $proc$ls180.v:369$1751
assign { } { }
- assign $1\sdram_cmd_payload_ba[1:0] 2'00
+ assign $1\sdram_cmd_ready[0:0] 1'0
sync always
sync init
- update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0]
+ update \sdram_cmd_ready $1\sdram_cmd_ready[0:0]
end
- attribute \src "ls180.v:369.5-369.33"
- process $proc$ls180.v:369$1748
+ attribute \src "ls180.v:370.5-370.26"
+ process $proc$ls180.v:370$1752
assign { } { }
- assign $1\sdram_cmd_payload_cas[0:0] 1'0
+ assign $1\sdram_cmd_last[0:0] 1'0
sync always
sync init
- update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0]
+ update \sdram_cmd_last $1\sdram_cmd_last[0:0]
end
- attribute \src "ls180.v:3692.1-3708.4"
- process $proc$ls180.v:3692$1130
+ attribute \src "ls180.v:3705.1-3721.4"
+ process $proc$ls180.v:3705$1131
assign { } { }
assign $0\t_array_muxed3[0:0] 1'0
- attribute \src "ls180.v:3694.2-3707.9"
+ attribute \src "ls180.v:3707.2-3720.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \t_array_muxed3 $0\t_array_muxed3[0:0]
end
- attribute \src "ls180.v:370.5-370.33"
- process $proc$ls180.v:370$1749
+ attribute \src "ls180.v:371.12-371.39"
+ process $proc$ls180.v:371$1753
assign { } { }
- assign $1\sdram_cmd_payload_ras[0:0] 1'0
+ assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
- update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0]
+ update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0]
+ end
+ attribute \src "ls180.v:372.11-372.38"
+ process $proc$ls180.v:372$1754
+ assign { } { }
+ assign $1\sdram_cmd_payload_ba[1:0] 2'00
+ sync always
+ sync init
+ update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0]
end
- attribute \src "ls180.v:3709.1-3725.4"
- process $proc$ls180.v:3709$1131
+ attribute \src "ls180.v:3722.1-3738.4"
+ process $proc$ls180.v:3722$1132
assign { } { }
assign $0\t_array_muxed4[0:0] 1'0
- attribute \src "ls180.v:3711.2-3724.9"
+ attribute \src "ls180.v:3724.2-3737.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \t_array_muxed4 $0\t_array_muxed4[0:0]
end
- attribute \src "ls180.v:371.5-371.32"
- process $proc$ls180.v:371$1750
- assign { } { }
- assign $1\sdram_cmd_payload_we[0:0] 1'0
- sync always
- sync init
- update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0]
- end
- attribute \src "ls180.v:372.5-372.37"
- process $proc$ls180.v:372$1751
+ attribute \src "ls180.v:373.5-373.33"
+ process $proc$ls180.v:373$1755
assign { } { }
- assign $0\sdram_cmd_payload_is_read[0:0] 1'0
+ assign $1\sdram_cmd_payload_cas[0:0] 1'0
sync always
- update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0]
sync init
+ update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:3726.1-3742.4"
- process $proc$ls180.v:3726$1132
+ attribute \src "ls180.v:3739.1-3755.4"
+ process $proc$ls180.v:3739$1133
assign { } { }
assign $0\t_array_muxed5[0:0] 1'0
- attribute \src "ls180.v:3728.2-3741.9"
+ attribute \src "ls180.v:3741.2-3754.9"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \t_array_muxed5 $0\t_array_muxed5[0:0]
end
- attribute \src "ls180.v:373.5-373.38"
- process $proc$ls180.v:373$1752
+ attribute \src "ls180.v:374.5-374.33"
+ process $proc$ls180.v:374$1756
assign { } { }
- assign $0\sdram_cmd_payload_is_write[0:0] 1'0
+ assign $1\sdram_cmd_payload_ras[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0]
+ end
+ attribute \src "ls180.v:375.5-375.32"
+ process $proc$ls180.v:375$1757
+ assign { } { }
+ assign $1\sdram_cmd_payload_we[0:0] 1'0
sync always
- update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0]
sync init
+ update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:3743.1-3750.4"
- process $proc$ls180.v:3743$1133
+ attribute \src "ls180.v:3756.1-3763.4"
+ process $proc$ls180.v:3756$1134
assign { } { }
assign $0\rhs_array_muxed12[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:3745.2-3749.9"
+ attribute \src "ls180.v:3758.2-3762.9"
switch \subfragments_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed12 $0\rhs_array_muxed12[21:0]
end
- attribute \src "ls180.v:3751.1-3758.4"
- process $proc$ls180.v:3751$1134
+ attribute \src "ls180.v:376.5-376.37"
+ process $proc$ls180.v:376$1758
+ assign { } { }
+ assign $0\sdram_cmd_payload_is_read[0:0] 1'0
+ sync always
+ update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:3764.1-3771.4"
+ process $proc$ls180.v:3764$1135
assign { } { }
assign $0\rhs_array_muxed13[0:0] 1'0
- attribute \src "ls180.v:3753.2-3757.9"
+ attribute \src "ls180.v:3766.2-3770.9"
switch \subfragments_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed13 $0\rhs_array_muxed13[0:0]
end
- attribute \src "ls180.v:3759.1-3766.4"
- process $proc$ls180.v:3759$1135
+ attribute \src "ls180.v:377.5-377.38"
+ process $proc$ls180.v:377$1759
+ assign { } { }
+ assign $0\sdram_cmd_payload_is_write[0:0] 1'0
+ sync always
+ update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:3772.1-3779.4"
+ process $proc$ls180.v:3772$1136
assign { } { }
assign $0\rhs_array_muxed14[0:0] 1'0
- attribute \src "ls180.v:3761.2-3765.9"
+ attribute \src "ls180.v:3774.2-3778.9"
switch \subfragments_roundrobin0_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3763$1148_Y
+ assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3776$1149_Y
end
sync always
update \rhs_array_muxed14 $0\rhs_array_muxed14[0:0]
end
- attribute \src "ls180.v:3767.1-3774.4"
- process $proc$ls180.v:3767$1149
+ attribute \src "ls180.v:3780.1-3787.4"
+ process $proc$ls180.v:3780$1150
assign { } { }
assign $0\rhs_array_muxed15[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:3769.2-3773.9"
+ attribute \src "ls180.v:3782.2-3786.9"
switch \subfragments_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed15 $0\rhs_array_muxed15[21:0]
end
- attribute \src "ls180.v:3775.1-3782.4"
- process $proc$ls180.v:3775$1150
+ attribute \src "ls180.v:3788.1-3795.4"
+ process $proc$ls180.v:3788$1151
assign { } { }
assign $0\rhs_array_muxed16[0:0] 1'0
- attribute \src "ls180.v:3777.2-3781.9"
+ attribute \src "ls180.v:3790.2-3794.9"
switch \subfragments_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed16 $0\rhs_array_muxed16[0:0]
end
- attribute \src "ls180.v:3783.1-3790.4"
- process $proc$ls180.v:3783$1151
+ attribute \src "ls180.v:3796.1-3803.4"
+ process $proc$ls180.v:3796$1152
assign { } { }
assign $0\rhs_array_muxed17[0:0] 1'0
- attribute \src "ls180.v:3785.2-3789.9"
+ attribute \src "ls180.v:3798.2-3802.9"
switch \subfragments_roundrobin1_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3787$1164_Y
+ assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3800$1165_Y
end
sync always
update \rhs_array_muxed17 $0\rhs_array_muxed17[0:0]
end
- attribute \src "ls180.v:379.11-379.39"
- process $proc$ls180.v:379$1753
- assign { } { }
- assign $1\sdram_timer_count1[9:0] 10'1100001101
- sync always
- sync init
- update \sdram_timer_count1 $1\sdram_timer_count1[9:0]
- end
- attribute \src "ls180.v:3791.1-3798.4"
- process $proc$ls180.v:3791$1165
+ attribute \src "ls180.v:3804.1-3811.4"
+ process $proc$ls180.v:3804$1166
assign { } { }
assign $0\rhs_array_muxed18[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:3793.2-3797.9"
+ attribute \src "ls180.v:3806.2-3810.9"
switch \subfragments_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed18 $0\rhs_array_muxed18[21:0]
end
- attribute \src "ls180.v:3799.1-3806.4"
- process $proc$ls180.v:3799$1166
+ attribute \src "ls180.v:3812.1-3819.4"
+ process $proc$ls180.v:3812$1167
assign { } { }
assign $0\rhs_array_muxed19[0:0] 1'0
- attribute \src "ls180.v:3801.2-3805.9"
+ attribute \src "ls180.v:3814.2-3818.9"
switch \subfragments_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed19 $0\rhs_array_muxed19[0:0]
end
- attribute \src "ls180.v:3807.1-3814.4"
- process $proc$ls180.v:3807$1167
+ attribute \src "ls180.v:3820.1-3827.4"
+ process $proc$ls180.v:3820$1168
assign { } { }
assign $0\rhs_array_muxed20[0:0] 1'0
- attribute \src "ls180.v:3809.2-3813.9"
+ attribute \src "ls180.v:3822.2-3826.9"
switch \subfragments_roundrobin2_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3811$1180_Y
+ assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3824$1181_Y
end
sync always
update \rhs_array_muxed20 $0\rhs_array_muxed20[0:0]
end
- attribute \src "ls180.v:381.5-381.33"
- process $proc$ls180.v:381$1754
- assign { } { }
- assign $1\sdram_postponer_req_o[0:0] 1'0
- sync always
- sync init
- update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0]
- end
- attribute \src "ls180.v:3815.1-3822.4"
- process $proc$ls180.v:3815$1181
+ attribute \src "ls180.v:3828.1-3835.4"
+ process $proc$ls180.v:3828$1182
assign { } { }
assign $0\rhs_array_muxed21[21:0] 22'0000000000000000000000
- attribute \src "ls180.v:3817.2-3821.9"
+ attribute \src "ls180.v:3830.2-3834.9"
switch \subfragments_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed21 $0\rhs_array_muxed21[21:0]
end
- attribute \src "ls180.v:382.5-382.33"
- process $proc$ls180.v:382$1755
+ attribute \src "ls180.v:383.11-383.39"
+ process $proc$ls180.v:383$1760
assign { } { }
- assign $1\sdram_postponer_count[0:0] 1'0
+ assign $1\sdram_timer_count1[9:0] 10'1100001101
sync always
sync init
- update \sdram_postponer_count $1\sdram_postponer_count[0:0]
+ update \sdram_timer_count1 $1\sdram_timer_count1[9:0]
end
- attribute \src "ls180.v:3823.1-3830.4"
- process $proc$ls180.v:3823$1182
+ attribute \src "ls180.v:3836.1-3843.4"
+ process $proc$ls180.v:3836$1183
assign { } { }
assign $0\rhs_array_muxed22[0:0] 1'0
- attribute \src "ls180.v:3825.2-3829.9"
+ attribute \src "ls180.v:3838.2-3842.9"
switch \subfragments_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
sync always
update \rhs_array_muxed22 $0\rhs_array_muxed22[0:0]
end
- attribute \src "ls180.v:383.5-383.34"
- process $proc$ls180.v:383$1756
- assign { } { }
- assign $1\sdram_sequencer_start0[0:0] 1'0
- sync always
- sync init
- update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0]
- end
- attribute \src "ls180.v:3831.1-3838.4"
- process $proc$ls180.v:3831$1183
+ attribute \src "ls180.v:3844.1-3851.4"
+ process $proc$ls180.v:3844$1184
assign { } { }
assign $0\rhs_array_muxed23[0:0] 1'0
- attribute \src "ls180.v:3833.2-3837.9"
+ attribute \src "ls180.v:3846.2-3850.9"
switch \subfragments_roundrobin3_grant
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3835$1196_Y
+ assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3848$1197_Y
end
sync always
update \rhs_array_muxed23 $0\rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:3839.1-3852.4"
- process $proc$ls180.v:3839$1197
+ attribute \src "ls180.v:385.5-385.33"
+ process $proc$ls180.v:385$1761
+ assign { } { }
+ assign $1\sdram_postponer_req_o[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0]
+ end
+ attribute \src "ls180.v:3852.1-3865.4"
+ process $proc$ls180.v:3852$1198
assign { } { }
assign $0\rhs_array_muxed24[28:0] 29'00000000000000000000000000000
- attribute \src "ls180.v:3841.2-3851.9"
+ attribute \src "ls180.v:3854.2-3864.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed24 $0\rhs_array_muxed24[28:0]
end
- attribute \src "ls180.v:3853.1-3866.4"
- process $proc$ls180.v:3853$1198
+ attribute \src "ls180.v:386.5-386.33"
+ process $proc$ls180.v:386$1762
+ assign { } { }
+ assign $1\sdram_postponer_count[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_postponer_count $1\sdram_postponer_count[0:0]
+ end
+ attribute \src "ls180.v:3866.1-3879.4"
+ process $proc$ls180.v:3866$1199
assign { } { }
assign $0\rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "ls180.v:3855.2-3865.9"
+ attribute \src "ls180.v:3868.2-3878.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed25 $0\rhs_array_muxed25[63:0]
end
- attribute \src "ls180.v:386.5-386.33"
- process $proc$ls180.v:386$1757
+ attribute \src "ls180.v:387.5-387.34"
+ process $proc$ls180.v:387$1763
assign { } { }
- assign $1\sdram_sequencer_done1[0:0] 1'0
+ assign $1\sdram_sequencer_start0[0:0] 1'0
sync always
sync init
- update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0]
+ update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0]
end
- attribute \src "ls180.v:3867.1-3880.4"
- process $proc$ls180.v:3867$1199
+ attribute \src "ls180.v:3880.1-3893.4"
+ process $proc$ls180.v:3880$1200
assign { } { }
assign $0\rhs_array_muxed26[7:0] 8'00000000
- attribute \src "ls180.v:3869.2-3879.9"
+ attribute \src "ls180.v:3882.2-3892.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed26 $0\rhs_array_muxed26[7:0]
end
- attribute \src "ls180.v:387.11-387.41"
- process $proc$ls180.v:387$1758
- assign { } { }
- assign $1\sdram_sequencer_counter[3:0] 4'0000
- sync always
- sync init
- update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0]
- end
- attribute \src "ls180.v:388.5-388.33"
- process $proc$ls180.v:388$1759
- assign { } { }
- assign $1\sdram_sequencer_count[0:0] 1'0
- sync always
- sync init
- update \sdram_sequencer_count $1\sdram_sequencer_count[0:0]
- end
- attribute \src "ls180.v:3881.1-3894.4"
- process $proc$ls180.v:3881$1200
+ attribute \src "ls180.v:3894.1-3907.4"
+ process $proc$ls180.v:3894$1201
assign { } { }
assign $0\rhs_array_muxed27[0:0] 1'0
- attribute \src "ls180.v:3883.2-3893.9"
+ attribute \src "ls180.v:3896.2-3906.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed27 $0\rhs_array_muxed27[0:0]
end
- attribute \src "ls180.v:3895.1-3908.4"
- process $proc$ls180.v:3895$1201
+ attribute \src "ls180.v:390.5-390.33"
+ process $proc$ls180.v:390$1764
+ assign { } { }
+ assign $1\sdram_sequencer_done1[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0]
+ end
+ attribute \src "ls180.v:3908.1-3921.4"
+ process $proc$ls180.v:3908$1202
assign { } { }
assign $0\rhs_array_muxed28[0:0] 1'0
- attribute \src "ls180.v:3897.2-3907.9"
+ attribute \src "ls180.v:3910.2-3920.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed28 $0\rhs_array_muxed28[0:0]
end
- attribute \src "ls180.v:3909.1-3922.4"
- process $proc$ls180.v:3909$1202
+ attribute \src "ls180.v:391.11-391.41"
+ process $proc$ls180.v:391$1765
+ assign { } { }
+ assign $1\sdram_sequencer_counter[3:0] 4'0000
+ sync always
+ sync init
+ update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0]
+ end
+ attribute \src "ls180.v:392.5-392.33"
+ process $proc$ls180.v:392$1766
+ assign { } { }
+ assign $1\sdram_sequencer_count[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_sequencer_count $1\sdram_sequencer_count[0:0]
+ end
+ attribute \src "ls180.v:3922.1-3935.4"
+ process $proc$ls180.v:3922$1203
assign { } { }
assign $0\rhs_array_muxed29[0:0] 1'0
- attribute \src "ls180.v:3911.2-3921.9"
+ attribute \src "ls180.v:3924.2-3934.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed29 $0\rhs_array_muxed29[0:0]
end
- attribute \src "ls180.v:3923.1-3936.4"
- process $proc$ls180.v:3923$1203
+ attribute \src "ls180.v:3936.1-3949.4"
+ process $proc$ls180.v:3936$1204
assign { } { }
assign $0\rhs_array_muxed30[2:0] 3'000
- attribute \src "ls180.v:3925.2-3935.9"
+ attribute \src "ls180.v:3938.2-3948.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed30 $0\rhs_array_muxed30[2:0]
end
- attribute \src "ls180.v:3937.1-3950.4"
- process $proc$ls180.v:3937$1204
+ attribute \src "ls180.v:3950.1-3963.4"
+ process $proc$ls180.v:3950$1205
assign { } { }
assign $0\rhs_array_muxed31[1:0] 2'00
- attribute \src "ls180.v:3939.2-3949.9"
+ attribute \src "ls180.v:3952.2-3962.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \rhs_array_muxed31 $0\rhs_array_muxed31[1:0]
end
- attribute \src "ls180.v:394.5-394.46"
- process $proc$ls180.v:394$1760
- assign { } { }
- assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0]
- end
- attribute \src "ls180.v:395.5-395.46"
- process $proc$ls180.v:395$1761
- assign { } { }
- assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0]
- end
- attribute \src "ls180.v:3951.1-3967.4"
- process $proc$ls180.v:3951$1205
+ attribute \src "ls180.v:3964.1-3980.4"
+ process $proc$ls180.v:3964$1206
assign { } { }
assign $0\array_muxed0[1:0] 2'00
- attribute \src "ls180.v:3953.2-3966.9"
+ attribute \src "ls180.v:3966.2-3979.9"
switch \sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \array_muxed0 $0\array_muxed0[1:0]
end
- attribute \src "ls180.v:3968.1-3984.4"
- process $proc$ls180.v:3968$1206
+ attribute \src "ls180.v:398.5-398.46"
+ process $proc$ls180.v:398$1767
+ assign { } { }
+ assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0]
+ end
+ attribute \src "ls180.v:3981.1-3997.4"
+ process $proc$ls180.v:3981$1207
assign { } { }
assign $0\array_muxed1[12:0] 13'0000000000000
- attribute \src "ls180.v:3970.2-3983.9"
+ attribute \src "ls180.v:3983.2-3996.9"
switch \sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
sync always
update \array_muxed1 $0\array_muxed1[12:0]
end
- attribute \src "ls180.v:397.5-397.42"
- process $proc$ls180.v:397$1762
+ attribute \src "ls180.v:399.5-399.46"
+ process $proc$ls180.v:399$1768
assign { } { }
- assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:398.5-398.40"
- process $proc$ls180.v:398$1763
- assign { } { }
- assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0
+ assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0
sync always
sync init
- update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0]
+ update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:3985.1-4001.4"
- process $proc$ls180.v:3985$1207
+ attribute \src "ls180.v:3998.1-4014.4"
+ process $proc$ls180.v:3998$1208
assign { } { }
assign $0\array_muxed2[0:0] 1'0
- attribute \src "ls180.v:3987.2-4000.9"
+ attribute \src "ls180.v:4000.2-4013.9"
switch \sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\array_muxed2[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\array_muxed2[0:0] $and$ls180.v:3992$1209_Y
+ assign $0\array_muxed2[0:0] $and$ls180.v:4005$1210_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\array_muxed2[0:0] $and$ls180.v:3995$1211_Y
+ assign $0\array_muxed2[0:0] $and$ls180.v:4008$1212_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\array_muxed2[0:0] $and$ls180.v:3998$1213_Y
+ assign $0\array_muxed2[0:0] $and$ls180.v:4011$1214_Y
end
sync always
update \array_muxed2 $0\array_muxed2[0:0]
end
- attribute \src "ls180.v:399.5-399.40"
- process $proc$ls180.v:399$1764
- assign { } { }
- assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0]
- end
- attribute \src "ls180.v:400.12-400.52"
- process $proc$ls180.v:400$1765
+ attribute \src "ls180.v:401.5-401.42"
+ process $proc$ls180.v:401$1769
assign { } { }
- assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
+ assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0
sync always
sync init
- update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0]
+ update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0]
end
- attribute \src "ls180.v:4002.1-4018.4"
- process $proc$ls180.v:4002$1214
+ attribute \src "ls180.v:4015.1-4031.4"
+ process $proc$ls180.v:4015$1215
assign { } { }
assign $0\array_muxed3[0:0] 1'0
- attribute \src "ls180.v:4004.2-4017.9"
+ attribute \src "ls180.v:4017.2-4030.9"
switch \sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\array_muxed3[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\array_muxed3[0:0] $and$ls180.v:4009$1216_Y
+ assign $0\array_muxed3[0:0] $and$ls180.v:4022$1217_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\array_muxed3[0:0] $and$ls180.v:4012$1218_Y
+ assign $0\array_muxed3[0:0] $and$ls180.v:4025$1219_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\array_muxed3[0:0] $and$ls180.v:4015$1220_Y
+ assign $0\array_muxed3[0:0] $and$ls180.v:4028$1221_Y
end
sync always
update \array_muxed3 $0\array_muxed3[0:0]
end
- attribute \src "ls180.v:4019.1-4035.4"
- process $proc$ls180.v:4019$1221
+ attribute \src "ls180.v:402.5-402.40"
+ process $proc$ls180.v:402$1770
+ assign { } { }
+ assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0]
+ end
+ attribute \src "ls180.v:403.5-403.40"
+ process $proc$ls180.v:403$1771
+ assign { } { }
+ assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0]
+ end
+ attribute \src "ls180.v:4032.1-4048.4"
+ process $proc$ls180.v:4032$1222
assign { } { }
assign $0\array_muxed4[0:0] 1'0
- attribute \src "ls180.v:4021.2-4034.9"
+ attribute \src "ls180.v:4034.2-4047.9"
switch \sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\array_muxed4[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\array_muxed4[0:0] $and$ls180.v:4026$1223_Y
+ assign $0\array_muxed4[0:0] $and$ls180.v:4039$1224_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\array_muxed4[0:0] $and$ls180.v:4029$1225_Y
+ assign $0\array_muxed4[0:0] $and$ls180.v:4042$1226_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\array_muxed4[0:0] $and$ls180.v:4032$1227_Y
+ assign $0\array_muxed4[0:0] $and$ls180.v:4045$1228_Y
end
sync always
update \array_muxed4 $0\array_muxed4[0:0]
end
- attribute \src "ls180.v:402.5-402.46"
- process $proc$ls180.v:402$1766
+ attribute \src "ls180.v:404.12-404.52"
+ process $proc$ls180.v:404$1772
assign { } { }
- assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0]
- end
- attribute \src "ls180.v:403.5-403.46"
- process $proc$ls180.v:403$1767
- assign { } { }
- assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
+ assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
- update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0]
+ update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:4036.1-4052.4"
- process $proc$ls180.v:4036$1228
+ attribute \src "ls180.v:4049.1-4065.4"
+ process $proc$ls180.v:4049$1229
assign { } { }
assign $0\array_muxed5[0:0] 1'0
- attribute \src "ls180.v:4038.2-4051.9"
+ attribute \src "ls180.v:4051.2-4064.9"
switch \sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\array_muxed5[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\array_muxed5[0:0] $and$ls180.v:4043$1230_Y
+ assign $0\array_muxed5[0:0] $and$ls180.v:4056$1231_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\array_muxed5[0:0] $and$ls180.v:4046$1232_Y
+ assign $0\array_muxed5[0:0] $and$ls180.v:4059$1233_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\array_muxed5[0:0] $and$ls180.v:4049$1234_Y
+ assign $0\array_muxed5[0:0] $and$ls180.v:4062$1235_Y
end
sync always
update \array_muxed5 $0\array_muxed5[0:0]
end
- attribute \src "ls180.v:404.5-404.45"
- process $proc$ls180.v:404$1768
- assign { } { }
- assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0]
- end
- attribute \src "ls180.v:405.5-405.49"
- process $proc$ls180.v:405$1769
+ attribute \src "ls180.v:406.5-406.46"
+ process $proc$ls180.v:406$1773
assign { } { }
- assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+ assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
sync always
sync init
- update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+ update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:4053.1-4069.4"
- process $proc$ls180.v:4053$1235
+ attribute \src "ls180.v:4066.1-4082.4"
+ process $proc$ls180.v:4066$1236
assign { } { }
assign $0\array_muxed6[0:0] 1'0
- attribute \src "ls180.v:4055.2-4068.9"
+ attribute \src "ls180.v:4068.2-4081.9"
switch \sdram_steerer_sel
attribute \src "ls180.v:0.0-0.0"
case 2'00
assign $0\array_muxed6[0:0] 1'0
attribute \src "ls180.v:0.0-0.0"
case 2'01
- assign $0\array_muxed6[0:0] $and$ls180.v:4060$1237_Y
+ assign $0\array_muxed6[0:0] $and$ls180.v:4073$1238_Y
attribute \src "ls180.v:0.0-0.0"
case 2'10
- assign $0\array_muxed6[0:0] $and$ls180.v:4063$1239_Y
+ assign $0\array_muxed6[0:0] $and$ls180.v:4076$1240_Y
attribute \src "ls180.v:0.0-0.0"
case
- assign $0\array_muxed6[0:0] $and$ls180.v:4066$1241_Y
+ assign $0\array_muxed6[0:0] $and$ls180.v:4079$1242_Y
end
sync always
update \array_muxed6 $0\array_muxed6[0:0]
end
- attribute \src "ls180.v:406.5-406.50"
- process $proc$ls180.v:406$1770
+ attribute \src "ls180.v:407.5-407.46"
+ process $proc$ls180.v:407$1774
+ assign { } { }
+ assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0]
+ end
+ attribute \src "ls180.v:408.5-408.45"
+ process $proc$ls180.v:408$1775
+ assign { } { }
+ assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0]
+ end
+ attribute \src "ls180.v:409.5-409.49"
+ process $proc$ls180.v:409$1776
+ assign { } { }
+ assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0]
+ end
+ attribute \src "ls180.v:410.5-410.50"
+ process $proc$ls180.v:410$1777
assign { } { }
assign $1\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_cmd_payload_is_read $1\sdram_bankmachine0_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:407.5-407.51"
- process $proc$ls180.v:407$1771
+ attribute \src "ls180.v:411.5-411.51"
+ process $proc$ls180.v:411$1778
assign { } { }
assign $1\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_cmd_payload_is_write $1\sdram_bankmachine0_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:408.5-408.45"
- process $proc$ls180.v:408$1772
+ attribute \src "ls180.v:412.5-412.45"
+ process $proc$ls180.v:412$1779
assign { } { }
assign $1\sdram_bankmachine0_auto_precharge[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_auto_precharge $1\sdram_bankmachine0_auto_precharge[0:0]
end
- attribute \src "ls180.v:411.5-411.62"
- process $proc$ls180.v:411$1773
+ attribute \src "ls180.v:415.5-415.62"
+ process $proc$ls180.v:415$1780
assign { } { }
assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:412.5-412.61"
- process $proc$ls180.v:412$1774
+ attribute \src "ls180.v:416.5-416.61"
+ process $proc$ls180.v:416$1781
assign { } { }
assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:4176.1-4178.4"
- process $proc$ls180.v:4176$1242
+ attribute \src "ls180.v:4189.1-4191.4"
+ process $proc$ls180.v:4189$1243
assign { } { }
assign $0\int_rst[0:0] \sys_rst
sync posedge \por_clk
update \int_rst $0\int_rst[0:0]
end
- attribute \src "ls180.v:4180.1-4285.4"
- process $proc$ls180.v:4180$1243
+ attribute \src "ls180.v:4193.1-4298.4"
+ process $proc$ls180.v:4193$1244
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [0] \dfi_p0_address [0]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [1] \dfi_p0_address [1]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [2] \dfi_p0_address [2]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [3] \dfi_p0_address [3]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [4] \dfi_p0_address [4]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [5] \dfi_p0_address [5]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [6] \dfi_p0_address [6]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [7] \dfi_p0_address [7]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [8] \dfi_p0_address [8]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [9] \dfi_p0_address [9]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [10] \dfi_p0_address [10]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [11] \dfi_p0_address [11]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [12] \dfi_p0_address [12]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] [0] \dfi_p0_bank [0]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] [1] \dfi_p0_bank [1]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] \dfi_p0_cas_n
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] \dfi_p0_ras_n
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] \dfi_p0_we_n
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] \dfi_p0_cke
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] \dfi_p0_cs_n
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] \dfi_p0_wrdata_en
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [0] \dfi_p0_wrdata [0]
- assign $0\dfi_p0_rddata[15:0] [0] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [1] \dfi_p0_wrdata [1]
- assign $0\dfi_p0_rddata[15:0] [1] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [2] \dfi_p0_wrdata [2]
- assign $0\dfi_p0_rddata[15:0] [2] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [3] \dfi_p0_wrdata [3]
- assign $0\dfi_p0_rddata[15:0] [3] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [4] \dfi_p0_wrdata [4]
- assign $0\dfi_p0_rddata[15:0] [4] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [5] \dfi_p0_wrdata [5]
- assign $0\dfi_p0_rddata[15:0] [5] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [6] \dfi_p0_wrdata [6]
- assign $0\dfi_p0_rddata[15:0] [6] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [7] \dfi_p0_wrdata [7]
- assign $0\dfi_p0_rddata[15:0] [7] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [8] \dfi_p0_wrdata [8]
- assign $0\dfi_p0_rddata[15:0] [8] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [9] \dfi_p0_wrdata [9]
- assign $0\dfi_p0_rddata[15:0] [9] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [10] \dfi_p0_wrdata [10]
- assign $0\dfi_p0_rddata[15:0] [10] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [11] \dfi_p0_wrdata [11]
- assign $0\dfi_p0_rddata[15:0] [11] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [12] \dfi_p0_wrdata [12]
- assign $0\dfi_p0_rddata[15:0] [12] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [13] \dfi_p0_wrdata [13]
- assign $0\dfi_p0_rddata[15:0] [13] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [14] \dfi_p0_wrdata [14]
- assign $0\dfi_p0_rddata[15:0] [14] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [15] \dfi_p0_wrdata [15]
- assign $0\dfi_p0_rddata[15:0] [15] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15]
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] [0] $and$ls180.v:4234$1244_Y
- assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] [1] $and$ls180.v:4235$1245_Y
- assign $0\sdram_clock[0:0] \sys_clk_1
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [0] \dfi_p0_address [0]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [1] \dfi_p0_address [1]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [2] \dfi_p0_address [2]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [3] \dfi_p0_address [3]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [4] \dfi_p0_address [4]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [5] \dfi_p0_address [5]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [6] \dfi_p0_address [6]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [7] \dfi_p0_address [7]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [8] \dfi_p0_address [8]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [9] \dfi_p0_address [9]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [10] \dfi_p0_address [10]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [11] \dfi_p0_address [11]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [12] \dfi_p0_address [12]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] [0] \dfi_p0_bank [0]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] [1] \dfi_p0_bank [1]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] \dfi_p0_cas_n
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] \dfi_p0_ras_n
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] \dfi_p0_we_n
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] \dfi_p0_cke
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] \dfi_p0_cs_n
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] \dfi_p0_wrdata_en
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [0] \dfi_p0_wrdata [0]
+ assign $0\dfi_p0_rddata[15:0] [0] \libresocsim_libresoc_constraintmanager_sdram_dq_i [0]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [1] \dfi_p0_wrdata [1]
+ assign $0\dfi_p0_rddata[15:0] [1] \libresocsim_libresoc_constraintmanager_sdram_dq_i [1]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [2] \dfi_p0_wrdata [2]
+ assign $0\dfi_p0_rddata[15:0] [2] \libresocsim_libresoc_constraintmanager_sdram_dq_i [2]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [3] \dfi_p0_wrdata [3]
+ assign $0\dfi_p0_rddata[15:0] [3] \libresocsim_libresoc_constraintmanager_sdram_dq_i [3]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [4] \dfi_p0_wrdata [4]
+ assign $0\dfi_p0_rddata[15:0] [4] \libresocsim_libresoc_constraintmanager_sdram_dq_i [4]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [5] \dfi_p0_wrdata [5]
+ assign $0\dfi_p0_rddata[15:0] [5] \libresocsim_libresoc_constraintmanager_sdram_dq_i [5]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [6] \dfi_p0_wrdata [6]
+ assign $0\dfi_p0_rddata[15:0] [6] \libresocsim_libresoc_constraintmanager_sdram_dq_i [6]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [7] \dfi_p0_wrdata [7]
+ assign $0\dfi_p0_rddata[15:0] [7] \libresocsim_libresoc_constraintmanager_sdram_dq_i [7]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [8] \dfi_p0_wrdata [8]
+ assign $0\dfi_p0_rddata[15:0] [8] \libresocsim_libresoc_constraintmanager_sdram_dq_i [8]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [9] \dfi_p0_wrdata [9]
+ assign $0\dfi_p0_rddata[15:0] [9] \libresocsim_libresoc_constraintmanager_sdram_dq_i [9]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [10] \dfi_p0_wrdata [10]
+ assign $0\dfi_p0_rddata[15:0] [10] \libresocsim_libresoc_constraintmanager_sdram_dq_i [10]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [11] \dfi_p0_wrdata [11]
+ assign $0\dfi_p0_rddata[15:0] [11] \libresocsim_libresoc_constraintmanager_sdram_dq_i [11]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [12] \dfi_p0_wrdata [12]
+ assign $0\dfi_p0_rddata[15:0] [12] \libresocsim_libresoc_constraintmanager_sdram_dq_i [12]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [13] \dfi_p0_wrdata [13]
+ assign $0\dfi_p0_rddata[15:0] [13] \libresocsim_libresoc_constraintmanager_sdram_dq_i [13]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [14] \dfi_p0_wrdata [14]
+ assign $0\dfi_p0_rddata[15:0] [14] \libresocsim_libresoc_constraintmanager_sdram_dq_i [14]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [15] \dfi_p0_wrdata [15]
+ assign $0\dfi_p0_rddata[15:0] [15] \libresocsim_libresoc_constraintmanager_sdram_dq_i [15]
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [0] $and$ls180.v:4247$1245_Y
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [1] $and$ls180.v:4248$1246_Y
+ assign $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] \sys_clk_1
assign $0\gpio0_pads_gpio0oe[7:0] [0] \gpio0_oe_storage [0]
assign $0\gpio0_pads_gpio0o[7:0] [0] \gpio0_out_storage [0]
assign $0\gpio0_status[7:0] [0] \gpio0_pads_gpio0i [0]
assign $0\gpio1_pads_gpio1o[7:0] [7] \gpio1_out_storage [7]
assign $0\gpio1_status[7:0] [7] \gpio1_pads_gpio1i [7]
sync posedge \sdrio_clk
- update \libresocsim_libresoc_constraintmanager_obj_sdram_a $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_we_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_cke $0\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_ba $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0]
- update \libresocsim_libresoc_constraintmanager_obj_sdram_dm $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0]
- update \sdram_clock $0\sdram_clock[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_a $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_dq_o $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_we_n $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_ras_n $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_cas_n $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_cs_n $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_cke $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_ba $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_dm $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
+ update \libresocsim_libresoc_constraintmanager_sdram_clock $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
update \dfi_p0_rddata $0\dfi_p0_rddata[15:0]
update \gpio0_status $0\gpio0_status[7:0]
update \gpio0_pads_gpio0o $0\gpio0_pads_gpio0o[7:0]
update \gpio1_pads_gpio1o $0\gpio1_pads_gpio1o[7:0]
update \gpio1_pads_gpio1oe $0\gpio1_pads_gpio1oe[7:0]
end
- attribute \src "ls180.v:427.11-427.63"
- process $proc$ls180.v:427$1775
- assign { } { }
- assign $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
- sync always
- sync init
- update \sdram_bankmachine0_cmd_buffer_lookahead_level $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
- end
- attribute \src "ls180.v:428.5-428.59"
- process $proc$ls180.v:428$1776
- assign { } { }
- assign $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
- sync always
- update \sdram_bankmachine0_cmd_buffer_lookahead_replace $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
- sync init
- end
- attribute \src "ls180.v:4287.1-5487.4"
- process $proc$ls180.v:4287$1246
+ attribute \src "ls180.v:4300.1-5506.4"
+ process $proc$ls180.v:4300$1247
assign $0\libresocsim_reset_storage[0:0] \libresocsim_reset_storage
assign { } { }
assign $0\libresocsim_scratch_storage[31:0] \libresocsim_scratch_storage
assign { } { }
assign $0\libresocsim_bus_errors[31:0] \libresocsim_bus_errors
- assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] \libresocsim_libresoc_constraintmanager_obj_uart_tx
+ assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \libresocsim_libresoc_constraintmanager_uart_tx
assign { } { }
assign $0\libresocsim_load_storage[31:0] \libresocsim_load_storage
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\dummy[29:0] [0] $or$ls180.v:4288$1247_Y
- assign $0\dummy[29:0] [1] $or$ls180.v:4289$1248_Y
- assign $0\dummy[29:0] [2] $or$ls180.v:4290$1249_Y
- assign $0\dummy[29:0] [3] $or$ls180.v:4291$1250_Y
- assign $0\dummy[29:0] [4] $or$ls180.v:4292$1251_Y
- assign $0\dummy[29:0] [5] $or$ls180.v:4293$1252_Y
- assign $0\dummy[29:0] [6] $or$ls180.v:4294$1253_Y
- assign $0\dummy[29:0] [7] $or$ls180.v:4295$1254_Y
- assign $0\dummy[29:0] [8] $or$ls180.v:4296$1255_Y
- assign $0\dummy[29:0] [9] $or$ls180.v:4297$1256_Y
- assign $0\dummy[29:0] [10] $or$ls180.v:4298$1257_Y
- assign $0\dummy[29:0] [11] $or$ls180.v:4299$1258_Y
- assign $0\dummy[29:0] [12] $or$ls180.v:4300$1259_Y
- assign $0\dummy[29:0] [13] $or$ls180.v:4301$1260_Y
- assign $0\dummy[29:0] [14] $or$ls180.v:4302$1261_Y
- assign $0\dummy[29:0] [15] $or$ls180.v:4303$1262_Y
- assign $0\dummy[29:0] [16] $or$ls180.v:4304$1263_Y
- assign $0\dummy[29:0] [17] $or$ls180.v:4305$1264_Y
- assign $0\dummy[29:0] [18] $or$ls180.v:4306$1265_Y
- assign $0\dummy[29:0] [19] $or$ls180.v:4307$1266_Y
- assign $0\dummy[29:0] [20] $or$ls180.v:4308$1267_Y
- assign $0\dummy[29:0] [21] $or$ls180.v:4309$1268_Y
- assign $0\dummy[29:0] [22] $or$ls180.v:4310$1269_Y
- assign $0\dummy[29:0] [23] $or$ls180.v:4311$1270_Y
- assign $0\dummy[29:0] [24] $or$ls180.v:4312$1271_Y
- assign $0\dummy[29:0] [25] $or$ls180.v:4313$1272_Y
- assign $0\dummy[29:0] [26] $or$ls180.v:4314$1273_Y
- assign $0\dummy[29:0] [27] $or$ls180.v:4315$1274_Y
- assign $0\dummy[29:0] [28] $or$ls180.v:4316$1275_Y
- assign $0\dummy[29:0] [29] $or$ls180.v:4317$1276_Y
+ assign $0\dummy[35:0] [0] $or$ls180.v:4301$1248_Y
+ assign $0\dummy[35:0] [1] $or$ls180.v:4302$1249_Y
+ assign $0\dummy[35:0] [2] $or$ls180.v:4303$1250_Y
+ assign $0\dummy[35:0] [3] $or$ls180.v:4304$1251_Y
+ assign $0\dummy[35:0] [4] $or$ls180.v:4305$1252_Y
+ assign $0\dummy[35:0] [5] $or$ls180.v:4306$1253_Y
+ assign $0\dummy[35:0] [6] $or$ls180.v:4307$1254_Y
+ assign $0\dummy[35:0] [7] $or$ls180.v:4308$1255_Y
+ assign $0\dummy[35:0] [8] $or$ls180.v:4309$1256_Y
+ assign $0\dummy[35:0] [9] $or$ls180.v:4310$1257_Y
+ assign $0\dummy[35:0] [10] $or$ls180.v:4311$1258_Y
+ assign $0\dummy[35:0] [11] $or$ls180.v:4312$1259_Y
+ assign $0\dummy[35:0] [12] $or$ls180.v:4313$1260_Y
+ assign $0\dummy[35:0] [13] $or$ls180.v:4314$1261_Y
+ assign $0\dummy[35:0] [14] $or$ls180.v:4315$1262_Y
+ assign $0\dummy[35:0] [15] $or$ls180.v:4316$1263_Y
+ assign $0\dummy[35:0] [16] $or$ls180.v:4317$1264_Y
+ assign $0\dummy[35:0] [17] $or$ls180.v:4318$1265_Y
+ assign $0\dummy[35:0] [18] $or$ls180.v:4319$1266_Y
+ assign $0\dummy[35:0] [19] $or$ls180.v:4320$1267_Y
+ assign $0\dummy[35:0] [20] $or$ls180.v:4321$1268_Y
+ assign $0\dummy[35:0] [21] $or$ls180.v:4322$1269_Y
+ assign $0\dummy[35:0] [22] $or$ls180.v:4323$1270_Y
+ assign $0\dummy[35:0] [23] $or$ls180.v:4324$1271_Y
+ assign $0\dummy[35:0] [24] $or$ls180.v:4325$1272_Y
+ assign $0\dummy[35:0] [25] $or$ls180.v:4326$1273_Y
+ assign $0\dummy[35:0] [26] $or$ls180.v:4327$1274_Y
+ assign $0\dummy[35:0] [27] $or$ls180.v:4328$1275_Y
+ assign $0\dummy[35:0] [28] $or$ls180.v:4329$1276_Y
+ assign $0\dummy[35:0] [29] $or$ls180.v:4330$1277_Y
+ assign $0\dummy[35:0] [30] $or$ls180.v:4331$1278_Y
+ assign $0\dummy[35:0] [31] $or$ls180.v:4332$1279_Y
+ assign $0\dummy[35:0] [32] $or$ls180.v:4333$1280_Y
+ assign $0\dummy[35:0] [33] $or$ls180.v:4334$1281_Y
+ assign $0\dummy[35:0] [34] $or$ls180.v:4335$1282_Y
+ assign $0\dummy[35:0] [35] $or$ls180.v:4336$1283_Y
assign $0\subfragments_converter0_state[0:0] \subfragments_converter0_next_state
assign $0\subfragments_converter1_state[0:0] \subfragments_converter1_next_state
assign $0\subfragments_converter2_state[0:0] \subfragments_converter2_next_state
assign $0\sdram_dfi_p0_cs_n[0:0] 1'0
assign $0\sdram_dfi_p0_bank[1:0] \array_muxed0
assign $0\sdram_dfi_p0_address[12:0] \array_muxed1
- assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4763$1376_Y
- assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4764$1377_Y
- assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4765$1378_Y
+ assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4782$1383_Y
+ assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4783$1384_Y
+ assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4784$1385_Y
assign $0\sdram_dfi_p0_rddata_en[0:0] \array_muxed5
assign $0\sdram_dfi_p0_wrdata_en[0:0] \array_muxed6
assign $0\subfragments_multiplexer_state[2:0] \subfragments_multiplexer_next_state
- assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4799$1396_Y
- assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4800$1408_Y
+ assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4818$1403_Y
+ assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4819$1415_Y
assign $0\subfragments_new_master_rdata_valid1[0:0] \subfragments_new_master_rdata_valid0
assign $0\subfragments_new_master_rdata_valid2[0:0] \subfragments_new_master_rdata_valid1
assign $0\subfragments_new_master_rdata_valid3[0:0] \subfragments_new_master_rdata_valid2
assign $0\eventmanager_re[0:0] \libresocsim_csrbank6_ev_enable0_re
assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000
assign $0\uart_phy_re[0:0] \libresocsim_csrbank7_tuning_word0_re
- assign $0\regs0[0:0] \libresocsim_libresoc_constraintmanager_obj_uart_rx
+ assign $0\regs0[0:0] \libresocsim_libresoc_constraintmanager_uart_rx
assign $0\regs1[0:0] \regs0
- attribute \src "ls180.v:4318.2-4320.5"
- switch $or$ls180.v:4318$1277_Y
- attribute \src "ls180.v:4318.6-4318.59"
+ attribute \src "ls180.v:4337.2-4339.5"
+ switch $or$ls180.v:4337$1284_Y
+ attribute \src "ls180.v:4337.6-4337.59"
case 1'1
assign $0\converter0_dat_r[63:0] \interface0_converted_interface_dat_r
case
end
- attribute \src "ls180.v:4322.2-4324.5"
+ attribute \src "ls180.v:4341.2-4343.5"
switch \converter0_counter_subfragments_converter0_next_value_ce
- attribute \src "ls180.v:4322.6-4322.62"
+ attribute \src "ls180.v:4341.6-4341.62"
case 1'1
assign $0\converter0_counter[0:0] \converter0_counter_subfragments_converter0_next_value
case
end
- attribute \src "ls180.v:4325.2-4328.5"
+ attribute \src "ls180.v:4344.2-4347.5"
switch \converter0_reset
- attribute \src "ls180.v:4325.6-4325.22"
+ attribute \src "ls180.v:4344.6-4344.22"
case 1'1
assign $0\converter0_counter[0:0] 1'0
assign $0\subfragments_converter0_state[0:0] 1'0
case
end
- attribute \src "ls180.v:4329.2-4331.5"
- switch $or$ls180.v:4329$1278_Y
- attribute \src "ls180.v:4329.6-4329.59"
+ attribute \src "ls180.v:4348.2-4350.5"
+ switch $or$ls180.v:4348$1285_Y
+ attribute \src "ls180.v:4348.6-4348.59"
case 1'1
assign $0\converter1_dat_r[63:0] \interface1_converted_interface_dat_r
case
end
- attribute \src "ls180.v:4333.2-4335.5"
+ attribute \src "ls180.v:4352.2-4354.5"
switch \converter1_counter_subfragments_converter1_next_value_ce
- attribute \src "ls180.v:4333.6-4333.62"
+ attribute \src "ls180.v:4352.6-4352.62"
case 1'1
assign $0\converter1_counter[0:0] \converter1_counter_subfragments_converter1_next_value
case
end
- attribute \src "ls180.v:4336.2-4339.5"
+ attribute \src "ls180.v:4355.2-4358.5"
switch \converter1_reset
- attribute \src "ls180.v:4336.6-4336.22"
+ attribute \src "ls180.v:4355.6-4355.22"
case 1'1
assign $0\converter1_counter[0:0] 1'0
assign $0\subfragments_converter1_state[0:0] 1'0
case
end
- attribute \src "ls180.v:4340.2-4342.5"
- switch $or$ls180.v:4340$1279_Y
- attribute \src "ls180.v:4340.6-4340.41"
+ attribute \src "ls180.v:4359.2-4361.5"
+ switch $or$ls180.v:4359$1286_Y
+ attribute \src "ls180.v:4359.6-4359.41"
case 1'1
assign $0\socbushandler_dat_r[63:0] \socbushandler_converted_interface_dat_r
case
end
- attribute \src "ls180.v:4344.2-4346.5"
+ attribute \src "ls180.v:4363.2-4365.5"
switch \socbushandler_counter_subfragments_converter2_next_value_ce
- attribute \src "ls180.v:4344.6-4344.65"
+ attribute \src "ls180.v:4363.6-4363.65"
case 1'1
assign $0\socbushandler_counter[0:0] \socbushandler_counter_subfragments_converter2_next_value
case
end
- attribute \src "ls180.v:4347.2-4350.5"
+ attribute \src "ls180.v:4366.2-4369.5"
switch \socbushandler_reset
- attribute \src "ls180.v:4347.6-4347.25"
+ attribute \src "ls180.v:4366.6-4366.25"
case 1'1
assign $0\socbushandler_counter[0:0] 1'0
assign $0\subfragments_converter2_state[0:0] 1'0
case
end
- attribute \src "ls180.v:4351.2-4355.5"
- switch $ne$ls180.v:4351$1280_Y
- attribute \src "ls180.v:4351.6-4351.48"
+ attribute \src "ls180.v:4370.2-4374.5"
+ switch $ne$ls180.v:4370$1287_Y
+ attribute \src "ls180.v:4370.6-4370.48"
case 1'1
- attribute \src "ls180.v:4352.3-4354.6"
+ attribute \src "ls180.v:4371.3-4373.6"
switch \libresocsim_bus_error
- attribute \src "ls180.v:4352.7-4352.28"
+ attribute \src "ls180.v:4371.7-4371.28"
case 1'1
- assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4353$1281_Y
+ assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4372$1288_Y
case
end
case
end
- attribute \src "ls180.v:4357.2-4359.5"
- switch $and$ls180.v:4357$1284_Y
- attribute \src "ls180.v:4357.6-4357.88"
+ attribute \src "ls180.v:4376.2-4378.5"
+ switch $and$ls180.v:4376$1291_Y
+ attribute \src "ls180.v:4376.6-4376.88"
case 1'1
assign $0\libresocsim_ram_bus_ack[0:0] 1'1
case
end
- attribute \src "ls180.v:4360.2-4368.5"
+ attribute \src "ls180.v:4379.2-4387.5"
switch \libresocsim_en_storage
- attribute \src "ls180.v:4360.6-4360.28"
+ attribute \src "ls180.v:4379.6-4379.28"
case 1'1
- attribute \src "ls180.v:4361.3-4365.6"
- switch $eq$ls180.v:4361$1285_Y
- attribute \src "ls180.v:4361.7-4361.34"
+ attribute \src "ls180.v:4380.3-4384.6"
+ switch $eq$ls180.v:4380$1292_Y
+ attribute \src "ls180.v:4380.7-4380.34"
case 1'1
assign $0\libresocsim_value[31:0] \libresocsim_reload_storage
- attribute \src "ls180.v:4363.7-4363.11"
+ attribute \src "ls180.v:4382.7-4382.11"
case
- assign $0\libresocsim_value[31:0] $sub$ls180.v:4364$1286_Y
+ assign $0\libresocsim_value[31:0] $sub$ls180.v:4383$1293_Y
end
- attribute \src "ls180.v:4366.6-4366.10"
+ attribute \src "ls180.v:4385.6-4385.10"
case
assign $0\libresocsim_value[31:0] \libresocsim_load_storage
end
- attribute \src "ls180.v:4369.2-4371.5"
+ attribute \src "ls180.v:4388.2-4390.5"
switch \libresocsim_update_value_re
- attribute \src "ls180.v:4369.6-4369.33"
+ attribute \src "ls180.v:4388.6-4388.33"
case 1'1
assign $0\libresocsim_value_status[31:0] \libresocsim_value
case
end
- attribute \src "ls180.v:4372.2-4374.5"
+ attribute \src "ls180.v:4391.2-4393.5"
switch \libresocsim_zero_clear
- attribute \src "ls180.v:4372.6-4372.28"
+ attribute \src "ls180.v:4391.6-4391.28"
case 1'1
assign $0\libresocsim_zero_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:4376.2-4378.5"
- switch $and$ls180.v:4376$1288_Y
- attribute \src "ls180.v:4376.6-4376.66"
+ attribute \src "ls180.v:4395.2-4397.5"
+ switch $and$ls180.v:4395$1295_Y
+ attribute \src "ls180.v:4395.6-4395.66"
case 1'1
assign $0\libresocsim_zero_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:4380.2-4382.5"
- switch $and$ls180.v:4380$1291_Y
- attribute \src "ls180.v:4380.6-4380.76"
+ attribute \src "ls180.v:4399.2-4401.5"
+ switch $and$ls180.v:4399$1298_Y
+ attribute \src "ls180.v:4399.6-4399.76"
case 1'1
assign $0\ram_bus_ram_bus_ack[0:0] 1'1
case
end
- attribute \src "ls180.v:4385.2-4387.5"
+ attribute \src "ls180.v:4404.2-4406.5"
switch \sdram_inti_p0_rddata_valid
- attribute \src "ls180.v:4385.6-4385.32"
+ attribute \src "ls180.v:4404.6-4404.32"
case 1'1
assign $0\sdram_status[15:0] \sdram_inti_p0_rddata
case
end
- attribute \src "ls180.v:4388.2-4392.5"
- switch $and$ls180.v:4388$1293_Y
- attribute \src "ls180.v:4388.6-4388.47"
+ attribute \src "ls180.v:4407.2-4411.5"
+ switch $and$ls180.v:4407$1300_Y
+ attribute \src "ls180.v:4407.6-4407.47"
case 1'1
- assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4389$1294_Y
- attribute \src "ls180.v:4390.6-4390.10"
+ assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4408$1301_Y
+ attribute \src "ls180.v:4409.6-4409.10"
case
assign $0\sdram_timer_count1[9:0] 10'1100001101
end
- attribute \src "ls180.v:4394.2-4400.5"
+ attribute \src "ls180.v:4413.2-4419.5"
switch \sdram_postponer_req_i
- attribute \src "ls180.v:4394.6-4394.27"
+ attribute \src "ls180.v:4413.6-4413.27"
case 1'1
- assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4395$1295_Y
- attribute \src "ls180.v:4396.3-4399.6"
- switch $eq$ls180.v:4396$1296_Y
- attribute \src "ls180.v:4396.7-4396.38"
+ assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4414$1302_Y
+ attribute \src "ls180.v:4415.3-4418.6"
+ switch $eq$ls180.v:4415$1303_Y
+ attribute \src "ls180.v:4415.7-4415.38"
case 1'1
assign $0\sdram_postponer_count[0:0] 1'0
assign $0\sdram_postponer_req_o[0:0] 1'1
end
case
end
- attribute \src "ls180.v:4401.2-4409.5"
+ attribute \src "ls180.v:4420.2-4428.5"
switch \sdram_sequencer_start0
- attribute \src "ls180.v:4401.6-4401.28"
+ attribute \src "ls180.v:4420.6-4420.28"
case 1'1
assign $0\sdram_sequencer_count[0:0] 1'0
- attribute \src "ls180.v:4403.6-4403.10"
+ attribute \src "ls180.v:4422.6-4422.10"
case
- attribute \src "ls180.v:4404.3-4408.6"
+ attribute \src "ls180.v:4423.3-4427.6"
switch \sdram_sequencer_done1
- attribute \src "ls180.v:4404.7-4404.28"
+ attribute \src "ls180.v:4423.7-4423.28"
case 1'1
- attribute \src "ls180.v:4405.4-4407.7"
- switch $ne$ls180.v:4405$1297_Y
- attribute \src "ls180.v:4405.8-4405.39"
+ attribute \src "ls180.v:4424.4-4426.7"
+ switch $ne$ls180.v:4424$1304_Y
+ attribute \src "ls180.v:4424.8-4424.39"
case 1'1
- assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4406$1298_Y
+ assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4425$1305_Y
case
end
case
end
end
- attribute \src "ls180.v:4416.2-4422.5"
- switch $and$ls180.v:4416$1300_Y
- attribute \src "ls180.v:4416.6-4416.66"
+ attribute \src "ls180.v:4435.2-4441.5"
+ switch $and$ls180.v:4435$1307_Y
+ attribute \src "ls180.v:4435.6-4435.66"
case 1'1
assign $0\sdram_cmd_payload_a[12:0] 13'0010000000000
assign $0\sdram_cmd_payload_ba[1:0] 2'00
assign $0\sdram_cmd_payload_we[0:0] 1'1
case
end
- attribute \src "ls180.v:4423.2-4429.5"
- switch $eq$ls180.v:4423$1301_Y
- attribute \src "ls180.v:4423.6-4423.39"
+ attribute \src "ls180.v:4442.2-4448.5"
+ switch $eq$ls180.v:4442$1308_Y
+ attribute \src "ls180.v:4442.6-4442.39"
case 1'1
assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000
assign $0\sdram_cmd_payload_ba[1:0] 2'00
assign $0\sdram_cmd_payload_we[0:0] 1'0
case
end
- attribute \src "ls180.v:4430.2-4437.5"
- switch $eq$ls180.v:4430$1302_Y
- attribute \src "ls180.v:4430.6-4430.39"
+ attribute \src "ls180.v:4449.2-4456.5"
+ switch $eq$ls180.v:4449$1309_Y
+ attribute \src "ls180.v:4449.6-4449.39"
case 1'1
assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000
assign $0\sdram_cmd_payload_ba[1:0] 2'00
assign $0\sdram_sequencer_done1[0:0] 1'1
case
end
- attribute \src "ls180.v:4438.2-4448.5"
- switch $eq$ls180.v:4438$1303_Y
- attribute \src "ls180.v:4438.6-4438.39"
+ attribute \src "ls180.v:4457.2-4467.5"
+ switch $eq$ls180.v:4457$1310_Y
+ attribute \src "ls180.v:4457.6-4457.39"
case 1'1
assign $0\sdram_sequencer_counter[3:0] 4'0000
- attribute \src "ls180.v:4440.6-4440.10"
+ attribute \src "ls180.v:4459.6-4459.10"
case
- attribute \src "ls180.v:4441.3-4447.6"
- switch $ne$ls180.v:4441$1304_Y
- attribute \src "ls180.v:4441.7-4441.40"
+ attribute \src "ls180.v:4460.3-4466.6"
+ switch $ne$ls180.v:4460$1311_Y
+ attribute \src "ls180.v:4460.7-4460.40"
case 1'1
- assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4442$1305_Y
- attribute \src "ls180.v:4443.7-4443.11"
+ assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4461$1312_Y
+ attribute \src "ls180.v:4462.7-4462.11"
case
- attribute \src "ls180.v:4444.4-4446.7"
+ attribute \src "ls180.v:4463.4-4465.7"
switch \sdram_sequencer_start1
- attribute \src "ls180.v:4444.8-4444.30"
+ attribute \src "ls180.v:4463.8-4463.30"
case 1'1
assign $0\sdram_sequencer_counter[3:0] 4'0001
case
end
end
end
- attribute \src "ls180.v:4450.2-4457.5"
+ attribute \src "ls180.v:4469.2-4476.5"
switch \sdram_bankmachine0_row_close
- attribute \src "ls180.v:4450.6-4450.34"
+ attribute \src "ls180.v:4469.6-4469.34"
case 1'1
assign $0\sdram_bankmachine0_row_opened[0:0] 1'0
- attribute \src "ls180.v:4452.6-4452.10"
+ attribute \src "ls180.v:4471.6-4471.10"
case
- attribute \src "ls180.v:4453.3-4456.6"
+ attribute \src "ls180.v:4472.3-4475.6"
switch \sdram_bankmachine0_row_open
- attribute \src "ls180.v:4453.7-4453.34"
+ attribute \src "ls180.v:4472.7-4472.34"
case 1'1
assign $0\sdram_bankmachine0_row_opened[0:0] 1'1
assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:4458.2-4460.5"
- switch $and$ls180.v:4458$1308_Y
- attribute \src "ls180.v:4458.6-4458.176"
+ attribute \src "ls180.v:4477.2-4479.5"
+ switch $and$ls180.v:4477$1315_Y
+ attribute \src "ls180.v:4477.6-4477.176"
case 1'1
- assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4459$1309_Y
+ assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4478$1316_Y
case
end
- attribute \src "ls180.v:4461.2-4463.5"
+ attribute \src "ls180.v:4480.2-4482.5"
switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4461.6-4461.53"
+ attribute \src "ls180.v:4480.6-4480.53"
case 1'1
- assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4462$1310_Y
+ assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4481$1317_Y
case
end
- attribute \src "ls180.v:4464.2-4472.5"
- switch $and$ls180.v:4464$1313_Y
- attribute \src "ls180.v:4464.6-4464.176"
+ attribute \src "ls180.v:4483.2-4491.5"
+ switch $and$ls180.v:4483$1320_Y
+ attribute \src "ls180.v:4483.6-4483.176"
case 1'1
- attribute \src "ls180.v:4465.3-4467.6"
- switch $not$ls180.v:4465$1314_Y
- attribute \src "ls180.v:4465.7-4465.57"
+ attribute \src "ls180.v:4484.3-4486.6"
+ switch $not$ls180.v:4484$1321_Y
+ attribute \src "ls180.v:4484.7-4484.57"
case 1'1
- assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4466$1315_Y
+ assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4485$1322_Y
case
end
- attribute \src "ls180.v:4468.6-4468.10"
+ attribute \src "ls180.v:4487.6-4487.10"
case
- attribute \src "ls180.v:4469.3-4471.6"
+ attribute \src "ls180.v:4488.3-4490.6"
switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4469.7-4469.54"
+ attribute \src "ls180.v:4488.7-4488.54"
case 1'1
- assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4470$1316_Y
+ assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4489$1323_Y
case
end
end
- attribute \src "ls180.v:4473.2-4479.5"
- switch $or$ls180.v:4473$1318_Y
- attribute \src "ls180.v:4473.6-4473.98"
+ attribute \src "ls180.v:4492.2-4498.5"
+ switch $or$ls180.v:4492$1325_Y
+ attribute \src "ls180.v:4492.6-4492.98"
case 1'1
assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_sink_valid
assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_sink_first
assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:4480.2-4494.5"
+ attribute \src "ls180.v:4499.2-4513.5"
switch \sdram_bankmachine0_twtpcon_valid
- attribute \src "ls180.v:4480.6-4480.38"
+ attribute \src "ls180.v:4499.6-4499.38"
case 1'1
assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:4482.3-4486.6"
+ attribute \src "ls180.v:4501.3-4505.6"
switch 1'0
- attribute \src "ls180.v:4484.7-4484.11"
+ attribute \src "ls180.v:4503.7-4503.11"
case
assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:4487.6-4487.10"
+ attribute \src "ls180.v:4506.6-4506.10"
case
- attribute \src "ls180.v:4488.3-4493.6"
- switch $not$ls180.v:4488$1319_Y
- attribute \src "ls180.v:4488.7-4488.42"
+ attribute \src "ls180.v:4507.3-4512.6"
+ switch $not$ls180.v:4507$1326_Y
+ attribute \src "ls180.v:4507.7-4507.42"
case 1'1
- assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4489$1320_Y
- attribute \src "ls180.v:4490.4-4492.7"
- switch $eq$ls180.v:4490$1321_Y
- attribute \src "ls180.v:4490.8-4490.50"
+ assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4508$1327_Y
+ attribute \src "ls180.v:4509.4-4511.7"
+ switch $eq$ls180.v:4509$1328_Y
+ attribute \src "ls180.v:4509.8-4509.50"
case 1'1
assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:4496.2-4503.5"
+ attribute \src "ls180.v:4515.2-4522.5"
switch \sdram_bankmachine1_row_close
- attribute \src "ls180.v:4496.6-4496.34"
+ attribute \src "ls180.v:4515.6-4515.34"
case 1'1
assign $0\sdram_bankmachine1_row_opened[0:0] 1'0
- attribute \src "ls180.v:4498.6-4498.10"
+ attribute \src "ls180.v:4517.6-4517.10"
case
- attribute \src "ls180.v:4499.3-4502.6"
+ attribute \src "ls180.v:4518.3-4521.6"
switch \sdram_bankmachine1_row_open
- attribute \src "ls180.v:4499.7-4499.34"
+ attribute \src "ls180.v:4518.7-4518.34"
case 1'1
assign $0\sdram_bankmachine1_row_opened[0:0] 1'1
assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:4504.2-4506.5"
- switch $and$ls180.v:4504$1324_Y
- attribute \src "ls180.v:4504.6-4504.176"
+ attribute \src "ls180.v:4523.2-4525.5"
+ switch $and$ls180.v:4523$1331_Y
+ attribute \src "ls180.v:4523.6-4523.176"
case 1'1
- assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4505$1325_Y
+ assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4524$1332_Y
case
end
- attribute \src "ls180.v:4507.2-4509.5"
+ attribute \src "ls180.v:4526.2-4528.5"
switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4507.6-4507.53"
+ attribute \src "ls180.v:4526.6-4526.53"
case 1'1
- assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4508$1326_Y
+ assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4527$1333_Y
case
end
- attribute \src "ls180.v:4510.2-4518.5"
- switch $and$ls180.v:4510$1329_Y
- attribute \src "ls180.v:4510.6-4510.176"
+ attribute \src "ls180.v:4529.2-4537.5"
+ switch $and$ls180.v:4529$1336_Y
+ attribute \src "ls180.v:4529.6-4529.176"
case 1'1
- attribute \src "ls180.v:4511.3-4513.6"
- switch $not$ls180.v:4511$1330_Y
- attribute \src "ls180.v:4511.7-4511.57"
+ attribute \src "ls180.v:4530.3-4532.6"
+ switch $not$ls180.v:4530$1337_Y
+ attribute \src "ls180.v:4530.7-4530.57"
case 1'1
- assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4512$1331_Y
+ assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4531$1338_Y
case
end
- attribute \src "ls180.v:4514.6-4514.10"
+ attribute \src "ls180.v:4533.6-4533.10"
case
- attribute \src "ls180.v:4515.3-4517.6"
+ attribute \src "ls180.v:4534.3-4536.6"
switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4515.7-4515.54"
+ attribute \src "ls180.v:4534.7-4534.54"
case 1'1
- assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4516$1332_Y
+ assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4535$1339_Y
case
end
end
- attribute \src "ls180.v:4519.2-4525.5"
- switch $or$ls180.v:4519$1334_Y
- attribute \src "ls180.v:4519.6-4519.98"
+ attribute \src "ls180.v:4538.2-4544.5"
+ switch $or$ls180.v:4538$1341_Y
+ attribute \src "ls180.v:4538.6-4538.98"
case 1'1
assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_sink_valid
assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_sink_first
assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:4526.2-4540.5"
+ attribute \src "ls180.v:4545.2-4559.5"
switch \sdram_bankmachine1_twtpcon_valid
- attribute \src "ls180.v:4526.6-4526.38"
+ attribute \src "ls180.v:4545.6-4545.38"
case 1'1
assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:4528.3-4532.6"
+ attribute \src "ls180.v:4547.3-4551.6"
switch 1'0
- attribute \src "ls180.v:4530.7-4530.11"
+ attribute \src "ls180.v:4549.7-4549.11"
case
assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:4533.6-4533.10"
+ attribute \src "ls180.v:4552.6-4552.10"
case
- attribute \src "ls180.v:4534.3-4539.6"
- switch $not$ls180.v:4534$1335_Y
- attribute \src "ls180.v:4534.7-4534.42"
+ attribute \src "ls180.v:4553.3-4558.6"
+ switch $not$ls180.v:4553$1342_Y
+ attribute \src "ls180.v:4553.7-4553.42"
case 1'1
- assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4535$1336_Y
- attribute \src "ls180.v:4536.4-4538.7"
- switch $eq$ls180.v:4536$1337_Y
- attribute \src "ls180.v:4536.8-4536.50"
+ assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4554$1343_Y
+ attribute \src "ls180.v:4555.4-4557.7"
+ switch $eq$ls180.v:4555$1344_Y
+ attribute \src "ls180.v:4555.8-4555.50"
case 1'1
assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:4542.2-4549.5"
+ attribute \src "ls180.v:4561.2-4568.5"
switch \sdram_bankmachine2_row_close
- attribute \src "ls180.v:4542.6-4542.34"
+ attribute \src "ls180.v:4561.6-4561.34"
case 1'1
assign $0\sdram_bankmachine2_row_opened[0:0] 1'0
- attribute \src "ls180.v:4544.6-4544.10"
+ attribute \src "ls180.v:4563.6-4563.10"
case
- attribute \src "ls180.v:4545.3-4548.6"
+ attribute \src "ls180.v:4564.3-4567.6"
switch \sdram_bankmachine2_row_open
- attribute \src "ls180.v:4545.7-4545.34"
+ attribute \src "ls180.v:4564.7-4564.34"
case 1'1
assign $0\sdram_bankmachine2_row_opened[0:0] 1'1
assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:4550.2-4552.5"
- switch $and$ls180.v:4550$1340_Y
- attribute \src "ls180.v:4550.6-4550.176"
+ attribute \src "ls180.v:4569.2-4571.5"
+ switch $and$ls180.v:4569$1347_Y
+ attribute \src "ls180.v:4569.6-4569.176"
case 1'1
- assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4551$1341_Y
+ assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4570$1348_Y
case
end
- attribute \src "ls180.v:4553.2-4555.5"
+ attribute \src "ls180.v:4572.2-4574.5"
switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4553.6-4553.53"
+ attribute \src "ls180.v:4572.6-4572.53"
case 1'1
- assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4554$1342_Y
+ assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4573$1349_Y
case
end
- attribute \src "ls180.v:4556.2-4564.5"
- switch $and$ls180.v:4556$1345_Y
- attribute \src "ls180.v:4556.6-4556.176"
+ attribute \src "ls180.v:4575.2-4583.5"
+ switch $and$ls180.v:4575$1352_Y
+ attribute \src "ls180.v:4575.6-4575.176"
case 1'1
- attribute \src "ls180.v:4557.3-4559.6"
- switch $not$ls180.v:4557$1346_Y
- attribute \src "ls180.v:4557.7-4557.57"
+ attribute \src "ls180.v:4576.3-4578.6"
+ switch $not$ls180.v:4576$1353_Y
+ attribute \src "ls180.v:4576.7-4576.57"
case 1'1
- assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4558$1347_Y
+ assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4577$1354_Y
case
end
- attribute \src "ls180.v:4560.6-4560.10"
+ attribute \src "ls180.v:4579.6-4579.10"
case
- attribute \src "ls180.v:4561.3-4563.6"
+ attribute \src "ls180.v:4580.3-4582.6"
switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4561.7-4561.54"
+ attribute \src "ls180.v:4580.7-4580.54"
case 1'1
- assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4562$1348_Y
+ assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4581$1355_Y
case
end
end
- attribute \src "ls180.v:4565.2-4571.5"
- switch $or$ls180.v:4565$1350_Y
- attribute \src "ls180.v:4565.6-4565.98"
+ attribute \src "ls180.v:4584.2-4590.5"
+ switch $or$ls180.v:4584$1357_Y
+ attribute \src "ls180.v:4584.6-4584.98"
case 1'1
assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_sink_valid
assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_sink_first
assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:4572.2-4586.5"
+ attribute \src "ls180.v:4591.2-4605.5"
switch \sdram_bankmachine2_twtpcon_valid
- attribute \src "ls180.v:4572.6-4572.38"
+ attribute \src "ls180.v:4591.6-4591.38"
case 1'1
assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:4574.3-4578.6"
+ attribute \src "ls180.v:4593.3-4597.6"
switch 1'0
- attribute \src "ls180.v:4576.7-4576.11"
+ attribute \src "ls180.v:4595.7-4595.11"
case
assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:4579.6-4579.10"
+ attribute \src "ls180.v:4598.6-4598.10"
case
- attribute \src "ls180.v:4580.3-4585.6"
- switch $not$ls180.v:4580$1351_Y
- attribute \src "ls180.v:4580.7-4580.42"
+ attribute \src "ls180.v:4599.3-4604.6"
+ switch $not$ls180.v:4599$1358_Y
+ attribute \src "ls180.v:4599.7-4599.42"
case 1'1
- assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4581$1352_Y
- attribute \src "ls180.v:4582.4-4584.7"
- switch $eq$ls180.v:4582$1353_Y
- attribute \src "ls180.v:4582.8-4582.50"
+ assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4600$1359_Y
+ attribute \src "ls180.v:4601.4-4603.7"
+ switch $eq$ls180.v:4601$1360_Y
+ attribute \src "ls180.v:4601.8-4601.50"
case 1'1
assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:4588.2-4595.5"
+ attribute \src "ls180.v:4607.2-4614.5"
switch \sdram_bankmachine3_row_close
- attribute \src "ls180.v:4588.6-4588.34"
+ attribute \src "ls180.v:4607.6-4607.34"
case 1'1
assign $0\sdram_bankmachine3_row_opened[0:0] 1'0
- attribute \src "ls180.v:4590.6-4590.10"
+ attribute \src "ls180.v:4609.6-4609.10"
case
- attribute \src "ls180.v:4591.3-4594.6"
+ attribute \src "ls180.v:4610.3-4613.6"
switch \sdram_bankmachine3_row_open
- attribute \src "ls180.v:4591.7-4591.34"
+ attribute \src "ls180.v:4610.7-4610.34"
case 1'1
assign $0\sdram_bankmachine3_row_opened[0:0] 1'1
assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9]
case
end
end
- attribute \src "ls180.v:4596.2-4598.5"
- switch $and$ls180.v:4596$1356_Y
- attribute \src "ls180.v:4596.6-4596.176"
+ attribute \src "ls180.v:4615.2-4617.5"
+ switch $and$ls180.v:4615$1363_Y
+ attribute \src "ls180.v:4615.6-4615.176"
case 1'1
- assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4597$1357_Y
+ assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4616$1364_Y
case
end
- attribute \src "ls180.v:4599.2-4601.5"
+ attribute \src "ls180.v:4618.2-4620.5"
switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4599.6-4599.53"
+ attribute \src "ls180.v:4618.6-4618.53"
case 1'1
- assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4600$1358_Y
+ assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4619$1365_Y
case
end
- attribute \src "ls180.v:4602.2-4610.5"
- switch $and$ls180.v:4602$1361_Y
- attribute \src "ls180.v:4602.6-4602.176"
+ attribute \src "ls180.v:4621.2-4629.5"
+ switch $and$ls180.v:4621$1368_Y
+ attribute \src "ls180.v:4621.6-4621.176"
case 1'1
- attribute \src "ls180.v:4603.3-4605.6"
- switch $not$ls180.v:4603$1362_Y
- attribute \src "ls180.v:4603.7-4603.57"
+ attribute \src "ls180.v:4622.3-4624.6"
+ switch $not$ls180.v:4622$1369_Y
+ attribute \src "ls180.v:4622.7-4622.57"
case 1'1
- assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4604$1363_Y
+ assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4623$1370_Y
case
end
- attribute \src "ls180.v:4606.6-4606.10"
+ attribute \src "ls180.v:4625.6-4625.10"
case
- attribute \src "ls180.v:4607.3-4609.6"
+ attribute \src "ls180.v:4626.3-4628.6"
switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read
- attribute \src "ls180.v:4607.7-4607.54"
+ attribute \src "ls180.v:4626.7-4626.54"
case 1'1
- assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4608$1364_Y
+ assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4627$1371_Y
case
end
end
- attribute \src "ls180.v:4611.2-4617.5"
- switch $or$ls180.v:4611$1366_Y
- attribute \src "ls180.v:4611.6-4611.98"
+ attribute \src "ls180.v:4630.2-4636.5"
+ switch $or$ls180.v:4630$1373_Y
+ attribute \src "ls180.v:4630.6-4630.98"
case 1'1
assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_sink_valid
assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_sink_first
assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_sink_payload_addr
case
end
- attribute \src "ls180.v:4618.2-4632.5"
+ attribute \src "ls180.v:4637.2-4651.5"
switch \sdram_bankmachine3_twtpcon_valid
- attribute \src "ls180.v:4618.6-4618.38"
+ attribute \src "ls180.v:4637.6-4637.38"
case 1'1
assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'100
- attribute \src "ls180.v:4620.3-4624.6"
+ attribute \src "ls180.v:4639.3-4643.6"
switch 1'0
- attribute \src "ls180.v:4622.7-4622.11"
+ attribute \src "ls180.v:4641.7-4641.11"
case
assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:4625.6-4625.10"
+ attribute \src "ls180.v:4644.6-4644.10"
case
- attribute \src "ls180.v:4626.3-4631.6"
- switch $not$ls180.v:4626$1367_Y
- attribute \src "ls180.v:4626.7-4626.42"
+ attribute \src "ls180.v:4645.3-4650.6"
+ switch $not$ls180.v:4645$1374_Y
+ attribute \src "ls180.v:4645.7-4645.42"
case 1'1
- assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4627$1368_Y
- attribute \src "ls180.v:4628.4-4630.7"
- switch $eq$ls180.v:4628$1369_Y
- attribute \src "ls180.v:4628.8-4628.50"
+ assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4646$1375_Y
+ attribute \src "ls180.v:4647.4-4649.7"
+ switch $eq$ls180.v:4647$1376_Y
+ attribute \src "ls180.v:4647.8-4647.50"
case 1'1
assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:4634.2-4640.5"
- switch $not$ls180.v:4634$1370_Y
- attribute \src "ls180.v:4634.6-4634.18"
+ attribute \src "ls180.v:4653.2-4659.5"
+ switch $not$ls180.v:4653$1377_Y
+ attribute \src "ls180.v:4653.6-4653.18"
case 1'1
assign $0\sdram_time0[4:0] 5'11111
- attribute \src "ls180.v:4636.6-4636.10"
+ attribute \src "ls180.v:4655.6-4655.10"
case
- attribute \src "ls180.v:4637.3-4639.6"
- switch $not$ls180.v:4637$1371_Y
- attribute \src "ls180.v:4637.7-4637.25"
+ attribute \src "ls180.v:4656.3-4658.6"
+ switch $not$ls180.v:4656$1378_Y
+ attribute \src "ls180.v:4656.7-4656.25"
case 1'1
- assign $0\sdram_time0[4:0] $sub$ls180.v:4638$1372_Y
+ assign $0\sdram_time0[4:0] $sub$ls180.v:4657$1379_Y
case
end
end
- attribute \src "ls180.v:4641.2-4647.5"
- switch $not$ls180.v:4641$1373_Y
- attribute \src "ls180.v:4641.6-4641.18"
+ attribute \src "ls180.v:4660.2-4666.5"
+ switch $not$ls180.v:4660$1380_Y
+ attribute \src "ls180.v:4660.6-4660.18"
case 1'1
assign $0\sdram_time1[3:0] 4'1111
- attribute \src "ls180.v:4643.6-4643.10"
+ attribute \src "ls180.v:4662.6-4662.10"
case
- attribute \src "ls180.v:4644.3-4646.6"
- switch $not$ls180.v:4644$1374_Y
- attribute \src "ls180.v:4644.7-4644.25"
+ attribute \src "ls180.v:4663.3-4665.6"
+ switch $not$ls180.v:4663$1381_Y
+ attribute \src "ls180.v:4663.7-4663.25"
case 1'1
- assign $0\sdram_time1[3:0] $sub$ls180.v:4645$1375_Y
+ assign $0\sdram_time1[3:0] $sub$ls180.v:4664$1382_Y
case
end
end
- attribute \src "ls180.v:4648.2-4703.5"
+ attribute \src "ls180.v:4667.2-4722.5"
switch \sdram_choose_cmd_ce
- attribute \src "ls180.v:4648.6-4648.25"
+ attribute \src "ls180.v:4667.6-4667.25"
case 1'1
- attribute \src "ls180.v:4649.3-4702.10"
+ attribute \src "ls180.v:4668.3-4721.10"
switch \sdram_choose_cmd_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
- attribute \src "ls180.v:4651.5-4661.8"
+ attribute \src "ls180.v:4670.5-4680.8"
switch \sdram_choose_cmd_request [1]
- attribute \src "ls180.v:4651.9-4651.36"
+ attribute \src "ls180.v:4670.9-4670.36"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'01
- attribute \src "ls180.v:4653.9-4653.13"
+ attribute \src "ls180.v:4672.9-4672.13"
case
- attribute \src "ls180.v:4654.6-4660.9"
+ attribute \src "ls180.v:4673.6-4679.9"
switch \sdram_choose_cmd_request [2]
- attribute \src "ls180.v:4654.10-4654.37"
+ attribute \src "ls180.v:4673.10-4673.37"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'10
- attribute \src "ls180.v:4656.10-4656.14"
+ attribute \src "ls180.v:4675.10-4675.14"
case
- attribute \src "ls180.v:4657.7-4659.10"
+ attribute \src "ls180.v:4676.7-4678.10"
switch \sdram_choose_cmd_request [3]
- attribute \src "ls180.v:4657.11-4657.38"
+ attribute \src "ls180.v:4676.11-4676.38"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'11
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'01
- attribute \src "ls180.v:4664.5-4674.8"
+ attribute \src "ls180.v:4683.5-4693.8"
switch \sdram_choose_cmd_request [2]
- attribute \src "ls180.v:4664.9-4664.36"
+ attribute \src "ls180.v:4683.9-4683.36"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'10
- attribute \src "ls180.v:4666.9-4666.13"
+ attribute \src "ls180.v:4685.9-4685.13"
case
- attribute \src "ls180.v:4667.6-4673.9"
+ attribute \src "ls180.v:4686.6-4692.9"
switch \sdram_choose_cmd_request [3]
- attribute \src "ls180.v:4667.10-4667.37"
+ attribute \src "ls180.v:4686.10-4686.37"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'11
- attribute \src "ls180.v:4669.10-4669.14"
+ attribute \src "ls180.v:4688.10-4688.14"
case
- attribute \src "ls180.v:4670.7-4672.10"
+ attribute \src "ls180.v:4689.7-4691.10"
switch \sdram_choose_cmd_request [0]
- attribute \src "ls180.v:4670.11-4670.38"
+ attribute \src "ls180.v:4689.11-4689.38"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'00
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'10
- attribute \src "ls180.v:4677.5-4687.8"
+ attribute \src "ls180.v:4696.5-4706.8"
switch \sdram_choose_cmd_request [3]
- attribute \src "ls180.v:4677.9-4677.36"
+ attribute \src "ls180.v:4696.9-4696.36"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'11
- attribute \src "ls180.v:4679.9-4679.13"
+ attribute \src "ls180.v:4698.9-4698.13"
case
- attribute \src "ls180.v:4680.6-4686.9"
+ attribute \src "ls180.v:4699.6-4705.9"
switch \sdram_choose_cmd_request [0]
- attribute \src "ls180.v:4680.10-4680.37"
+ attribute \src "ls180.v:4699.10-4699.37"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'00
- attribute \src "ls180.v:4682.10-4682.14"
+ attribute \src "ls180.v:4701.10-4701.14"
case
- attribute \src "ls180.v:4683.7-4685.10"
+ attribute \src "ls180.v:4702.7-4704.10"
switch \sdram_choose_cmd_request [1]
- attribute \src "ls180.v:4683.11-4683.38"
+ attribute \src "ls180.v:4702.11-4702.38"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'01
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'11
- attribute \src "ls180.v:4690.5-4700.8"
+ attribute \src "ls180.v:4709.5-4719.8"
switch \sdram_choose_cmd_request [0]
- attribute \src "ls180.v:4690.9-4690.36"
+ attribute \src "ls180.v:4709.9-4709.36"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'00
- attribute \src "ls180.v:4692.9-4692.13"
+ attribute \src "ls180.v:4711.9-4711.13"
case
- attribute \src "ls180.v:4693.6-4699.9"
+ attribute \src "ls180.v:4712.6-4718.9"
switch \sdram_choose_cmd_request [1]
- attribute \src "ls180.v:4693.10-4693.37"
+ attribute \src "ls180.v:4712.10-4712.37"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'01
- attribute \src "ls180.v:4695.10-4695.14"
+ attribute \src "ls180.v:4714.10-4714.14"
case
- attribute \src "ls180.v:4696.7-4698.10"
+ attribute \src "ls180.v:4715.7-4717.10"
switch \sdram_choose_cmd_request [2]
- attribute \src "ls180.v:4696.11-4696.38"
+ attribute \src "ls180.v:4715.11-4715.38"
case 1'1
assign $0\sdram_choose_cmd_grant[1:0] 2'10
case
end
case
end
- attribute \src "ls180.v:4704.2-4759.5"
+ attribute \src "ls180.v:4723.2-4778.5"
switch \sdram_choose_req_ce
- attribute \src "ls180.v:4704.6-4704.25"
+ attribute \src "ls180.v:4723.6-4723.25"
case 1'1
- attribute \src "ls180.v:4705.3-4758.10"
+ attribute \src "ls180.v:4724.3-4777.10"
switch \sdram_choose_req_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
- attribute \src "ls180.v:4707.5-4717.8"
+ attribute \src "ls180.v:4726.5-4736.8"
switch \sdram_choose_req_request [1]
- attribute \src "ls180.v:4707.9-4707.36"
+ attribute \src "ls180.v:4726.9-4726.36"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'01
- attribute \src "ls180.v:4709.9-4709.13"
+ attribute \src "ls180.v:4728.9-4728.13"
case
- attribute \src "ls180.v:4710.6-4716.9"
+ attribute \src "ls180.v:4729.6-4735.9"
switch \sdram_choose_req_request [2]
- attribute \src "ls180.v:4710.10-4710.37"
+ attribute \src "ls180.v:4729.10-4729.37"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'10
- attribute \src "ls180.v:4712.10-4712.14"
+ attribute \src "ls180.v:4731.10-4731.14"
case
- attribute \src "ls180.v:4713.7-4715.10"
+ attribute \src "ls180.v:4732.7-4734.10"
switch \sdram_choose_req_request [3]
- attribute \src "ls180.v:4713.11-4713.38"
+ attribute \src "ls180.v:4732.11-4732.38"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'11
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'01
- attribute \src "ls180.v:4720.5-4730.8"
+ attribute \src "ls180.v:4739.5-4749.8"
switch \sdram_choose_req_request [2]
- attribute \src "ls180.v:4720.9-4720.36"
+ attribute \src "ls180.v:4739.9-4739.36"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'10
- attribute \src "ls180.v:4722.9-4722.13"
+ attribute \src "ls180.v:4741.9-4741.13"
case
- attribute \src "ls180.v:4723.6-4729.9"
+ attribute \src "ls180.v:4742.6-4748.9"
switch \sdram_choose_req_request [3]
- attribute \src "ls180.v:4723.10-4723.37"
+ attribute \src "ls180.v:4742.10-4742.37"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'11
- attribute \src "ls180.v:4725.10-4725.14"
+ attribute \src "ls180.v:4744.10-4744.14"
case
- attribute \src "ls180.v:4726.7-4728.10"
+ attribute \src "ls180.v:4745.7-4747.10"
switch \sdram_choose_req_request [0]
- attribute \src "ls180.v:4726.11-4726.38"
+ attribute \src "ls180.v:4745.11-4745.38"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'00
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'10
- attribute \src "ls180.v:4733.5-4743.8"
+ attribute \src "ls180.v:4752.5-4762.8"
switch \sdram_choose_req_request [3]
- attribute \src "ls180.v:4733.9-4733.36"
+ attribute \src "ls180.v:4752.9-4752.36"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'11
- attribute \src "ls180.v:4735.9-4735.13"
+ attribute \src "ls180.v:4754.9-4754.13"
case
- attribute \src "ls180.v:4736.6-4742.9"
+ attribute \src "ls180.v:4755.6-4761.9"
switch \sdram_choose_req_request [0]
- attribute \src "ls180.v:4736.10-4736.37"
+ attribute \src "ls180.v:4755.10-4755.37"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'00
- attribute \src "ls180.v:4738.10-4738.14"
+ attribute \src "ls180.v:4757.10-4757.14"
case
- attribute \src "ls180.v:4739.7-4741.10"
+ attribute \src "ls180.v:4758.7-4760.10"
switch \sdram_choose_req_request [1]
- attribute \src "ls180.v:4739.11-4739.38"
+ attribute \src "ls180.v:4758.11-4758.38"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'01
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'11
- attribute \src "ls180.v:4746.5-4756.8"
+ attribute \src "ls180.v:4765.5-4775.8"
switch \sdram_choose_req_request [0]
- attribute \src "ls180.v:4746.9-4746.36"
+ attribute \src "ls180.v:4765.9-4765.36"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'00
- attribute \src "ls180.v:4748.9-4748.13"
+ attribute \src "ls180.v:4767.9-4767.13"
case
- attribute \src "ls180.v:4749.6-4755.9"
+ attribute \src "ls180.v:4768.6-4774.9"
switch \sdram_choose_req_request [1]
- attribute \src "ls180.v:4749.10-4749.37"
+ attribute \src "ls180.v:4768.10-4768.37"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'01
- attribute \src "ls180.v:4751.10-4751.14"
+ attribute \src "ls180.v:4770.10-4770.14"
case
- attribute \src "ls180.v:4752.7-4754.10"
+ attribute \src "ls180.v:4771.7-4773.10"
switch \sdram_choose_req_request [2]
- attribute \src "ls180.v:4752.11-4752.38"
+ attribute \src "ls180.v:4771.11-4771.38"
case 1'1
assign $0\sdram_choose_req_grant[1:0] 2'10
case
end
case
end
- attribute \src "ls180.v:4768.2-4782.5"
+ attribute \src "ls180.v:4787.2-4801.5"
switch \sdram_tccdcon_valid
- attribute \src "ls180.v:4768.6-4768.25"
+ attribute \src "ls180.v:4787.6-4787.25"
case 1'1
assign $0\sdram_tccdcon_count[0:0] 1'0
- attribute \src "ls180.v:4770.3-4774.6"
+ attribute \src "ls180.v:4789.3-4793.6"
switch 1'1
- attribute \src "ls180.v:4770.7-4770.11"
+ attribute \src "ls180.v:4789.7-4789.11"
case 1'1
assign $0\sdram_tccdcon_ready[0:0] 1'1
case
end
- attribute \src "ls180.v:4775.6-4775.10"
+ attribute \src "ls180.v:4794.6-4794.10"
case
- attribute \src "ls180.v:4776.3-4781.6"
- switch $not$ls180.v:4776$1379_Y
- attribute \src "ls180.v:4776.7-4776.29"
+ attribute \src "ls180.v:4795.3-4800.6"
+ switch $not$ls180.v:4795$1386_Y
+ attribute \src "ls180.v:4795.7-4795.29"
case 1'1
- assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4777$1380_Y
- attribute \src "ls180.v:4778.4-4780.7"
- switch $eq$ls180.v:4778$1381_Y
- attribute \src "ls180.v:4778.8-4778.37"
+ assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4796$1387_Y
+ attribute \src "ls180.v:4797.4-4799.7"
+ switch $eq$ls180.v:4797$1388_Y
+ attribute \src "ls180.v:4797.8-4797.37"
case 1'1
assign $0\sdram_tccdcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:4783.2-4797.5"
+ attribute \src "ls180.v:4802.2-4816.5"
switch \sdram_twtrcon_valid
- attribute \src "ls180.v:4783.6-4783.25"
+ attribute \src "ls180.v:4802.6-4802.25"
case 1'1
assign $0\sdram_twtrcon_count[2:0] 3'100
- attribute \src "ls180.v:4785.3-4789.6"
+ attribute \src "ls180.v:4804.3-4808.6"
switch 1'0
- attribute \src "ls180.v:4787.7-4787.11"
+ attribute \src "ls180.v:4806.7-4806.11"
case
assign $0\sdram_twtrcon_ready[0:0] 1'0
end
- attribute \src "ls180.v:4790.6-4790.10"
+ attribute \src "ls180.v:4809.6-4809.10"
case
- attribute \src "ls180.v:4791.3-4796.6"
- switch $not$ls180.v:4791$1382_Y
- attribute \src "ls180.v:4791.7-4791.29"
+ attribute \src "ls180.v:4810.3-4815.6"
+ switch $not$ls180.v:4810$1389_Y
+ attribute \src "ls180.v:4810.7-4810.29"
case 1'1
- assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4792$1383_Y
- attribute \src "ls180.v:4793.4-4795.7"
- switch $eq$ls180.v:4793$1384_Y
- attribute \src "ls180.v:4793.8-4793.37"
+ assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4811$1390_Y
+ attribute \src "ls180.v:4812.4-4814.7"
+ switch $eq$ls180.v:4812$1391_Y
+ attribute \src "ls180.v:4812.8-4812.37"
case 1'1
assign $0\sdram_twtrcon_ready[0:0] 1'1
case
case
end
end
- attribute \src "ls180.v:4804.2-4806.5"
- switch $or$ls180.v:4804$1409_Y
- attribute \src "ls180.v:4804.6-4804.40"
+ attribute \src "ls180.v:4823.2-4825.5"
+ switch $or$ls180.v:4823$1416_Y
+ attribute \src "ls180.v:4823.6-4823.40"
case 1'1
assign $0\converter_dat_r[31:0] \wb_sdram_dat_r
case
end
- attribute \src "ls180.v:4808.2-4810.5"
+ attribute \src "ls180.v:4827.2-4829.5"
switch \converter_counter_subfragments_next_value_ce
- attribute \src "ls180.v:4808.6-4808.50"
+ attribute \src "ls180.v:4827.6-4827.50"
case 1'1
assign $0\converter_counter[0:0] \converter_counter_subfragments_next_value
case
end
- attribute \src "ls180.v:4811.2-4814.5"
+ attribute \src "ls180.v:4830.2-4833.5"
switch \converter_reset
- attribute \src "ls180.v:4811.6-4811.21"
+ attribute \src "ls180.v:4830.6-4830.21"
case 1'1
assign $0\converter_counter[0:0] 1'0
assign $0\subfragments_state[0:0] 1'0
case
end
- attribute \src "ls180.v:4815.2-4825.5"
+ attribute \src "ls180.v:4834.2-4844.5"
switch \litedram_wb_ack
- attribute \src "ls180.v:4815.6-4815.21"
+ attribute \src "ls180.v:4834.6-4834.21"
case 1'1
assign $0\cmd_consumed[0:0] 1'0
assign $0\wdata_consumed[0:0] 1'0
- attribute \src "ls180.v:4818.6-4818.10"
+ attribute \src "ls180.v:4837.6-4837.10"
case
- attribute \src "ls180.v:4819.3-4821.6"
- switch $and$ls180.v:4819$1410_Y
- attribute \src "ls180.v:4819.7-4819.40"
+ attribute \src "ls180.v:4838.3-4840.6"
+ switch $and$ls180.v:4838$1417_Y
+ attribute \src "ls180.v:4838.7-4838.40"
case 1'1
assign $0\cmd_consumed[0:0] 1'1
case
end
- attribute \src "ls180.v:4822.3-4824.6"
- switch $and$ls180.v:4822$1411_Y
- attribute \src "ls180.v:4822.7-4822.44"
+ attribute \src "ls180.v:4841.3-4843.6"
+ switch $and$ls180.v:4841$1418_Y
+ attribute \src "ls180.v:4841.7-4841.44"
case 1'1
assign $0\wdata_consumed[0:0] 1'1
case
end
end
- attribute \src "ls180.v:4827.2-4848.5"
- switch $and$ls180.v:4827$1415_Y
- attribute \src "ls180.v:4827.6-4827.76"
+ attribute \src "ls180.v:4846.2-4867.5"
+ switch $and$ls180.v:4846$1422_Y
+ attribute \src "ls180.v:4846.6-4846.76"
case 1'1
assign $0\uart_phy_tx_reg[7:0] \uart_phy_sink_payload_data
assign $0\uart_phy_tx_bitcount[3:0] 4'0000
assign $0\uart_phy_tx_busy[0:0] 1'1
- assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'0
- attribute \src "ls180.v:4832.6-4832.10"
+ assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'0
+ attribute \src "ls180.v:4851.6-4851.10"
case
- attribute \src "ls180.v:4833.3-4847.6"
- switch $and$ls180.v:4833$1416_Y
- attribute \src "ls180.v:4833.7-4833.50"
+ attribute \src "ls180.v:4852.3-4866.6"
+ switch $and$ls180.v:4852$1423_Y
+ attribute \src "ls180.v:4852.7-4852.50"
case 1'1
- assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4834$1417_Y
- attribute \src "ls180.v:4835.4-4846.7"
- switch $eq$ls180.v:4835$1418_Y
- attribute \src "ls180.v:4835.8-4835.38"
+ assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4853$1424_Y
+ attribute \src "ls180.v:4854.4-4865.7"
+ switch $eq$ls180.v:4854$1425_Y
+ attribute \src "ls180.v:4854.8-4854.38"
case 1'1
- assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1
- attribute \src "ls180.v:4837.8-4837.12"
+ assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
+ attribute \src "ls180.v:4856.8-4856.12"
case
- attribute \src "ls180.v:4838.5-4845.8"
- switch $eq$ls180.v:4838$1419_Y
- attribute \src "ls180.v:4838.9-4838.39"
+ attribute \src "ls180.v:4857.5-4864.8"
+ switch $eq$ls180.v:4857$1426_Y
+ attribute \src "ls180.v:4857.9-4857.39"
case 1'1
- assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1
+ assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
assign $0\uart_phy_tx_busy[0:0] 1'0
assign $0\uart_phy_sink_ready[0:0] 1'1
- attribute \src "ls180.v:4842.9-4842.13"
+ attribute \src "ls180.v:4861.9-4861.13"
case
- assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] \uart_phy_tx_reg [0]
+ assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \uart_phy_tx_reg [0]
assign $0\uart_phy_tx_reg[7:0] { 1'0 \uart_phy_tx_reg [7:1] }
end
end
case
end
end
- attribute \src "ls180.v:4849.2-4853.5"
+ attribute \src "ls180.v:4868.2-4872.5"
switch \uart_phy_tx_busy
- attribute \src "ls180.v:4849.6-4849.22"
+ attribute \src "ls180.v:4868.6-4868.22"
case 1'1
- assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4850$1420_Y
- attribute \src "ls180.v:4851.6-4851.10"
+ assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4869$1427_Y
+ attribute \src "ls180.v:4870.6-4870.10"
case
assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } { 1'0 \uart_phy_storage }
end
- attribute \src "ls180.v:4856.2-4880.5"
- switch $not$ls180.v:4856$1421_Y
- attribute \src "ls180.v:4856.6-4856.25"
+ attribute \src "ls180.v:4875.2-4899.5"
+ switch $not$ls180.v:4875$1428_Y
+ attribute \src "ls180.v:4875.6-4875.25"
case 1'1
- attribute \src "ls180.v:4857.3-4860.6"
- switch $and$ls180.v:4857$1423_Y
- attribute \src "ls180.v:4857.7-4857.39"
+ attribute \src "ls180.v:4876.3-4879.6"
+ switch $and$ls180.v:4876$1430_Y
+ attribute \src "ls180.v:4876.7-4876.39"
case 1'1
assign $0\uart_phy_rx_busy[0:0] 1'1
assign $0\uart_phy_rx_bitcount[3:0] 4'0000
case
end
- attribute \src "ls180.v:4861.6-4861.10"
+ attribute \src "ls180.v:4880.6-4880.10"
case
- attribute \src "ls180.v:4862.3-4879.6"
+ attribute \src "ls180.v:4881.3-4898.6"
switch \uart_phy_uart_clk_rxen
- attribute \src "ls180.v:4862.7-4862.29"
+ attribute \src "ls180.v:4881.7-4881.29"
case 1'1
- assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4863$1424_Y
- attribute \src "ls180.v:4864.4-4878.7"
- switch $eq$ls180.v:4864$1425_Y
- attribute \src "ls180.v:4864.8-4864.38"
+ assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4882$1431_Y
+ attribute \src "ls180.v:4883.4-4897.7"
+ switch $eq$ls180.v:4883$1432_Y
+ attribute \src "ls180.v:4883.8-4883.38"
case 1'1
- attribute \src "ls180.v:4865.5-4867.8"
+ attribute \src "ls180.v:4884.5-4886.8"
switch \uart_phy_rx
- attribute \src "ls180.v:4865.9-4865.20"
+ attribute \src "ls180.v:4884.9-4884.20"
case 1'1
assign $0\uart_phy_rx_busy[0:0] 1'0
case
end
- attribute \src "ls180.v:4868.8-4868.12"
+ attribute \src "ls180.v:4887.8-4887.12"
case
- attribute \src "ls180.v:4869.5-4877.8"
- switch $eq$ls180.v:4869$1426_Y
- attribute \src "ls180.v:4869.9-4869.39"
+ attribute \src "ls180.v:4888.5-4896.8"
+ switch $eq$ls180.v:4888$1433_Y
+ attribute \src "ls180.v:4888.9-4888.39"
case 1'1
assign $0\uart_phy_rx_busy[0:0] 1'0
- attribute \src "ls180.v:4871.6-4874.9"
+ attribute \src "ls180.v:4890.6-4893.9"
switch \uart_phy_rx
- attribute \src "ls180.v:4871.10-4871.21"
+ attribute \src "ls180.v:4890.10-4890.21"
case 1'1
assign $0\uart_phy_source_payload_data[7:0] \uart_phy_rx_reg
assign $0\uart_phy_source_valid[0:0] 1'1
case
end
- attribute \src "ls180.v:4875.9-4875.13"
+ attribute \src "ls180.v:4894.9-4894.13"
case
assign $0\uart_phy_rx_reg[7:0] { \uart_phy_rx \uart_phy_rx_reg [7:1] }
end
case
end
end
- attribute \src "ls180.v:4881.2-4885.5"
+ attribute \src "ls180.v:4900.2-4904.5"
switch \uart_phy_rx_busy
- attribute \src "ls180.v:4881.6-4881.22"
+ attribute \src "ls180.v:4900.6-4900.22"
case 1'1
- assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4882$1427_Y
- attribute \src "ls180.v:4883.6-4883.10"
+ assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4901$1434_Y
+ attribute \src "ls180.v:4902.6-4902.10"
case
assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000
end
- attribute \src "ls180.v:4886.2-4888.5"
+ attribute \src "ls180.v:4905.2-4907.5"
switch \tx_clear
- attribute \src "ls180.v:4886.6-4886.14"
+ attribute \src "ls180.v:4905.6-4905.14"
case 1'1
assign $0\tx_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:4890.2-4892.5"
- switch $and$ls180.v:4890$1429_Y
- attribute \src "ls180.v:4890.6-4890.38"
+ attribute \src "ls180.v:4909.2-4911.5"
+ switch $and$ls180.v:4909$1436_Y
+ attribute \src "ls180.v:4909.6-4909.38"
case 1'1
assign $0\tx_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:4893.2-4895.5"
+ attribute \src "ls180.v:4912.2-4914.5"
switch \rx_clear
- attribute \src "ls180.v:4893.6-4893.14"
+ attribute \src "ls180.v:4912.6-4912.14"
case 1'1
assign $0\rx_pending[0:0] 1'0
case
end
- attribute \src "ls180.v:4897.2-4899.5"
- switch $and$ls180.v:4897$1431_Y
- attribute \src "ls180.v:4897.6-4897.38"
+ attribute \src "ls180.v:4916.2-4918.5"
+ switch $and$ls180.v:4916$1438_Y
+ attribute \src "ls180.v:4916.6-4916.38"
case 1'1
assign $0\rx_pending[0:0] 1'1
case
end
- attribute \src "ls180.v:4900.2-4906.5"
+ attribute \src "ls180.v:4919.2-4925.5"
switch \tx_fifo_syncfifo_re
- attribute \src "ls180.v:4900.6-4900.25"
+ attribute \src "ls180.v:4919.6-4919.25"
case 1'1
assign $0\tx_fifo_readable[0:0] 1'1
- attribute \src "ls180.v:4902.6-4902.10"
+ attribute \src "ls180.v:4921.6-4921.10"
case
- attribute \src "ls180.v:4903.3-4905.6"
+ attribute \src "ls180.v:4922.3-4924.6"
switch \tx_fifo_re
- attribute \src "ls180.v:4903.7-4903.17"
+ attribute \src "ls180.v:4922.7-4922.17"
case 1'1
assign $0\tx_fifo_readable[0:0] 1'0
case
end
end
- attribute \src "ls180.v:4907.2-4909.5"
- switch $and$ls180.v:4907$1434_Y
- attribute \src "ls180.v:4907.6-4907.78"
+ attribute \src "ls180.v:4926.2-4928.5"
+ switch $and$ls180.v:4926$1441_Y
+ attribute \src "ls180.v:4926.6-4926.78"
case 1'1
- assign $0\tx_fifo_produce[3:0] $add$ls180.v:4908$1435_Y
+ assign $0\tx_fifo_produce[3:0] $add$ls180.v:4927$1442_Y
case
end
- attribute \src "ls180.v:4910.2-4912.5"
+ attribute \src "ls180.v:4929.2-4931.5"
switch \tx_fifo_do_read
- attribute \src "ls180.v:4910.6-4910.21"
+ attribute \src "ls180.v:4929.6-4929.21"
case 1'1
- assign $0\tx_fifo_consume[3:0] $add$ls180.v:4911$1436_Y
+ assign $0\tx_fifo_consume[3:0] $add$ls180.v:4930$1443_Y
case
end
- attribute \src "ls180.v:4913.2-4921.5"
- switch $and$ls180.v:4913$1439_Y
- attribute \src "ls180.v:4913.6-4913.78"
+ attribute \src "ls180.v:4932.2-4940.5"
+ switch $and$ls180.v:4932$1446_Y
+ attribute \src "ls180.v:4932.6-4932.78"
case 1'1
- attribute \src "ls180.v:4914.3-4916.6"
- switch $not$ls180.v:4914$1440_Y
- attribute \src "ls180.v:4914.7-4914.25"
+ attribute \src "ls180.v:4933.3-4935.6"
+ switch $not$ls180.v:4933$1447_Y
+ attribute \src "ls180.v:4933.7-4933.25"
case 1'1
- assign $0\tx_fifo_level0[4:0] $add$ls180.v:4915$1441_Y
+ assign $0\tx_fifo_level0[4:0] $add$ls180.v:4934$1448_Y
case
end
- attribute \src "ls180.v:4917.6-4917.10"
+ attribute \src "ls180.v:4936.6-4936.10"
case
- attribute \src "ls180.v:4918.3-4920.6"
+ attribute \src "ls180.v:4937.3-4939.6"
switch \tx_fifo_do_read
- attribute \src "ls180.v:4918.7-4918.22"
+ attribute \src "ls180.v:4937.7-4937.22"
case 1'1
- assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4919$1442_Y
+ assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4938$1449_Y
case
end
end
- attribute \src "ls180.v:4922.2-4928.5"
+ attribute \src "ls180.v:4941.2-4947.5"
switch \rx_fifo_syncfifo_re
- attribute \src "ls180.v:4922.6-4922.25"
+ attribute \src "ls180.v:4941.6-4941.25"
case 1'1
assign $0\rx_fifo_readable[0:0] 1'1
- attribute \src "ls180.v:4924.6-4924.10"
+ attribute \src "ls180.v:4943.6-4943.10"
case
- attribute \src "ls180.v:4925.3-4927.6"
+ attribute \src "ls180.v:4944.3-4946.6"
switch \rx_fifo_re
- attribute \src "ls180.v:4925.7-4925.17"
+ attribute \src "ls180.v:4944.7-4944.17"
case 1'1
assign $0\rx_fifo_readable[0:0] 1'0
case
end
end
- attribute \src "ls180.v:4929.2-4931.5"
- switch $and$ls180.v:4929$1445_Y
- attribute \src "ls180.v:4929.6-4929.78"
+ attribute \src "ls180.v:4948.2-4950.5"
+ switch $and$ls180.v:4948$1452_Y
+ attribute \src "ls180.v:4948.6-4948.78"
case 1'1
- assign $0\rx_fifo_produce[3:0] $add$ls180.v:4930$1446_Y
+ assign $0\rx_fifo_produce[3:0] $add$ls180.v:4949$1453_Y
case
end
- attribute \src "ls180.v:4932.2-4934.5"
+ attribute \src "ls180.v:4951.2-4953.5"
switch \rx_fifo_do_read
- attribute \src "ls180.v:4932.6-4932.21"
+ attribute \src "ls180.v:4951.6-4951.21"
case 1'1
- assign $0\rx_fifo_consume[3:0] $add$ls180.v:4933$1447_Y
+ assign $0\rx_fifo_consume[3:0] $add$ls180.v:4952$1454_Y
case
end
- attribute \src "ls180.v:4935.2-4943.5"
- switch $and$ls180.v:4935$1450_Y
- attribute \src "ls180.v:4935.6-4935.78"
+ attribute \src "ls180.v:4954.2-4962.5"
+ switch $and$ls180.v:4954$1457_Y
+ attribute \src "ls180.v:4954.6-4954.78"
case 1'1
- attribute \src "ls180.v:4936.3-4938.6"
- switch $not$ls180.v:4936$1451_Y
- attribute \src "ls180.v:4936.7-4936.25"
+ attribute \src "ls180.v:4955.3-4957.6"
+ switch $not$ls180.v:4955$1458_Y
+ attribute \src "ls180.v:4955.7-4955.25"
case 1'1
- assign $0\rx_fifo_level0[4:0] $add$ls180.v:4937$1452_Y
+ assign $0\rx_fifo_level0[4:0] $add$ls180.v:4956$1459_Y
case
end
- attribute \src "ls180.v:4939.6-4939.10"
+ attribute \src "ls180.v:4958.6-4958.10"
case
- attribute \src "ls180.v:4940.3-4942.6"
+ attribute \src "ls180.v:4959.3-4961.6"
switch \rx_fifo_do_read
- attribute \src "ls180.v:4940.7-4940.22"
+ attribute \src "ls180.v:4959.7-4959.22"
case 1'1
- assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4941$1453_Y
+ assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4960$1460_Y
case
end
end
- attribute \src "ls180.v:4944.2-4957.5"
+ attribute \src "ls180.v:4963.2-4976.5"
switch \reset
- attribute \src "ls180.v:4944.6-4944.11"
+ attribute \src "ls180.v:4963.6-4963.11"
case 1'1
assign $0\tx_pending[0:0] 1'0
assign $0\tx_old_trigger[0:0] 1'0
assign $0\rx_fifo_consume[3:0] 4'0000
case
end
- attribute \src "ls180.v:4959.2-4961.5"
+ attribute \src "ls180.v:4978.2-4980.5"
switch \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0
- attribute \src "ls180.v:4959.6-4959.62"
+ attribute \src "ls180.v:4978.6-4978.62"
case 1'1
assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w_libresocsim_next_value0
case
end
- attribute \src "ls180.v:4962.2-4964.5"
+ attribute \src "ls180.v:4981.2-4983.5"
switch \libresocsim_libresocsim_adr_libresocsim_next_value_ce1
- attribute \src "ls180.v:4962.6-4962.60"
+ attribute \src "ls180.v:4981.6-4981.60"
case 1'1
assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr_libresocsim_next_value1
case
end
- attribute \src "ls180.v:4965.2-4967.5"
+ attribute \src "ls180.v:4984.2-4986.5"
switch \libresocsim_libresocsim_we_libresocsim_next_value_ce2
- attribute \src "ls180.v:4965.6-4965.59"
+ attribute \src "ls180.v:4984.6-4984.59"
case 1'1
assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we_libresocsim_next_value2
case
end
- attribute \src "ls180.v:4968.2-5002.9"
+ attribute \src "ls180.v:4987.2-5021.9"
switch \libresocsim_grant
attribute \src "ls180.v:0.0-0.0"
case 2'00
- attribute \src "ls180.v:4970.4-4978.7"
- switch $not$ls180.v:4970$1454_Y
- attribute \src "ls180.v:4970.8-4970.33"
+ attribute \src "ls180.v:4989.4-4997.7"
+ switch $not$ls180.v:4989$1461_Y
+ attribute \src "ls180.v:4989.8-4989.33"
case 1'1
- attribute \src "ls180.v:4971.5-4977.8"
+ attribute \src "ls180.v:4990.5-4996.8"
switch \libresocsim_request [1]
- attribute \src "ls180.v:4971.9-4971.31"
+ attribute \src "ls180.v:4990.9-4990.31"
case 1'1
assign $0\libresocsim_grant[1:0] 2'01
- attribute \src "ls180.v:4973.9-4973.13"
+ attribute \src "ls180.v:4992.9-4992.13"
case
- attribute \src "ls180.v:4974.6-4976.9"
+ attribute \src "ls180.v:4993.6-4995.9"
switch \libresocsim_request [2]
- attribute \src "ls180.v:4974.10-4974.32"
+ attribute \src "ls180.v:4993.10-4993.32"
case 1'1
assign $0\libresocsim_grant[1:0] 2'10
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'01
- attribute \src "ls180.v:4981.4-4989.7"
- switch $not$ls180.v:4981$1455_Y
- attribute \src "ls180.v:4981.8-4981.33"
+ attribute \src "ls180.v:5000.4-5008.7"
+ switch $not$ls180.v:5000$1462_Y
+ attribute \src "ls180.v:5000.8-5000.33"
case 1'1
- attribute \src "ls180.v:4982.5-4988.8"
+ attribute \src "ls180.v:5001.5-5007.8"
switch \libresocsim_request [2]
- attribute \src "ls180.v:4982.9-4982.31"
+ attribute \src "ls180.v:5001.9-5001.31"
case 1'1
assign $0\libresocsim_grant[1:0] 2'10
- attribute \src "ls180.v:4984.9-4984.13"
+ attribute \src "ls180.v:5003.9-5003.13"
case
- attribute \src "ls180.v:4985.6-4987.9"
+ attribute \src "ls180.v:5004.6-5006.9"
switch \libresocsim_request [0]
- attribute \src "ls180.v:4985.10-4985.32"
+ attribute \src "ls180.v:5004.10-5004.32"
case 1'1
assign $0\libresocsim_grant[1:0] 2'00
case
end
attribute \src "ls180.v:0.0-0.0"
case 2'10
- attribute \src "ls180.v:4992.4-5000.7"
- switch $not$ls180.v:4992$1456_Y
- attribute \src "ls180.v:4992.8-4992.33"
+ attribute \src "ls180.v:5011.4-5019.7"
+ switch $not$ls180.v:5011$1463_Y
+ attribute \src "ls180.v:5011.8-5011.33"
case 1'1
- attribute \src "ls180.v:4993.5-4999.8"
+ attribute \src "ls180.v:5012.5-5018.8"
switch \libresocsim_request [0]
- attribute \src "ls180.v:4993.9-4993.31"
+ attribute \src "ls180.v:5012.9-5012.31"
case 1'1
assign $0\libresocsim_grant[1:0] 2'00
- attribute \src "ls180.v:4995.9-4995.13"
+ attribute \src "ls180.v:5014.9-5014.13"
case
- attribute \src "ls180.v:4996.6-4998.9"
+ attribute \src "ls180.v:5015.6-5017.9"
switch \libresocsim_request [1]
- attribute \src "ls180.v:4996.10-4996.32"
+ attribute \src "ls180.v:5015.10-5015.32"
case 1'1
assign $0\libresocsim_grant[1:0] 2'01
case
end
case
end
- attribute \src "ls180.v:5004.2-5010.5"
+ attribute \src "ls180.v:5023.2-5029.5"
switch \libresocsim_wait
- attribute \src "ls180.v:5004.6-5004.22"
+ attribute \src "ls180.v:5023.6-5023.22"
case 1'1
- attribute \src "ls180.v:5005.3-5007.6"
- switch $not$ls180.v:5005$1457_Y
- attribute \src "ls180.v:5005.7-5005.26"
+ attribute \src "ls180.v:5024.3-5026.6"
+ switch $not$ls180.v:5024$1464_Y
+ attribute \src "ls180.v:5024.7-5024.26"
case 1'1
- assign $0\libresocsim_count[19:0] $sub$ls180.v:5006$1458_Y
+ assign $0\libresocsim_count[19:0] $sub$ls180.v:5025$1465_Y
case
end
- attribute \src "ls180.v:5008.6-5008.10"
+ attribute \src "ls180.v:5027.6-5027.10"
case
assign $0\libresocsim_count[19:0] 20'11110100001001000000
end
- attribute \src "ls180.v:5012.2-5042.5"
+ attribute \src "ls180.v:5031.2-5061.5"
switch \libresocsim_csrbank0_sel
- attribute \src "ls180.v:5012.6-5012.30"
+ attribute \src "ls180.v:5031.6-5031.30"
case 1'1
- attribute \src "ls180.v:5013.3-5041.10"
+ attribute \src "ls180.v:5032.3-5060.10"
switch \libresocsim_interface0_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:5043.2-5045.5"
+ attribute \src "ls180.v:5062.2-5064.5"
switch \libresocsim_csrbank0_reset0_re
- attribute \src "ls180.v:5043.6-5043.36"
+ attribute \src "ls180.v:5062.6-5062.36"
case 1'1
assign $0\libresocsim_reset_storage[0:0] \libresocsim_csrbank0_reset0_r
case
end
- attribute \src "ls180.v:5047.2-5049.5"
+ attribute \src "ls180.v:5066.2-5068.5"
switch \libresocsim_csrbank0_scratch3_re
- attribute \src "ls180.v:5047.6-5047.38"
+ attribute \src "ls180.v:5066.6-5066.38"
case 1'1
assign $0\libresocsim_scratch_storage[31:0] [31:24] \libresocsim_csrbank0_scratch3_r
case
end
- attribute \src "ls180.v:5050.2-5052.5"
+ attribute \src "ls180.v:5069.2-5071.5"
switch \libresocsim_csrbank0_scratch2_re
- attribute \src "ls180.v:5050.6-5050.38"
+ attribute \src "ls180.v:5069.6-5069.38"
case 1'1
assign $0\libresocsim_scratch_storage[31:0] [23:16] \libresocsim_csrbank0_scratch2_r
case
end
- attribute \src "ls180.v:5053.2-5055.5"
+ attribute \src "ls180.v:5072.2-5074.5"
switch \libresocsim_csrbank0_scratch1_re
- attribute \src "ls180.v:5053.6-5053.38"
+ attribute \src "ls180.v:5072.6-5072.38"
case 1'1
assign $0\libresocsim_scratch_storage[31:0] [15:8] \libresocsim_csrbank0_scratch1_r
case
end
- attribute \src "ls180.v:5056.2-5058.5"
+ attribute \src "ls180.v:5075.2-5077.5"
switch \libresocsim_csrbank0_scratch0_re
- attribute \src "ls180.v:5056.6-5056.38"
+ attribute \src "ls180.v:5075.6-5075.38"
case 1'1
assign $0\libresocsim_scratch_storage[31:0] [7:0] \libresocsim_csrbank0_scratch0_r
case
end
- attribute \src "ls180.v:5061.2-5073.5"
+ attribute \src "ls180.v:5080.2-5092.5"
switch \libresocsim_csrbank1_sel
- attribute \src "ls180.v:5061.6-5061.30"
+ attribute \src "ls180.v:5080.6-5080.30"
case 1'1
- attribute \src "ls180.v:5062.3-5072.10"
+ attribute \src "ls180.v:5081.3-5091.10"
switch \libresocsim_interface1_bank_bus_adr [1:0]
attribute \src "ls180.v:0.0-0.0"
case 2'00
end
case
end
- attribute \src "ls180.v:5074.2-5076.5"
+ attribute \src "ls180.v:5093.2-5095.5"
switch \libresocsim_csrbank1_oe0_re
- attribute \src "ls180.v:5074.6-5074.33"
+ attribute \src "ls180.v:5093.6-5093.33"
case 1'1
assign $0\gpio0_oe_storage[7:0] \libresocsim_csrbank1_oe0_r
case
end
- attribute \src "ls180.v:5078.2-5080.5"
+ attribute \src "ls180.v:5097.2-5099.5"
switch \libresocsim_csrbank1_out0_re
- attribute \src "ls180.v:5078.6-5078.34"
+ attribute \src "ls180.v:5097.6-5097.34"
case 1'1
assign $0\gpio0_out_storage[7:0] \libresocsim_csrbank1_out0_r
case
end
- attribute \src "ls180.v:5083.2-5095.5"
+ attribute \src "ls180.v:5102.2-5114.5"
switch \libresocsim_csrbank2_sel
- attribute \src "ls180.v:5083.6-5083.30"
+ attribute \src "ls180.v:5102.6-5102.30"
case 1'1
- attribute \src "ls180.v:5084.3-5094.10"
+ attribute \src "ls180.v:5103.3-5113.10"
switch \libresocsim_interface2_bank_bus_adr [1:0]
attribute \src "ls180.v:0.0-0.0"
case 2'00
end
case
end
- attribute \src "ls180.v:5096.2-5098.5"
+ attribute \src "ls180.v:5115.2-5117.5"
switch \libresocsim_csrbank2_oe0_re
- attribute \src "ls180.v:5096.6-5096.33"
+ attribute \src "ls180.v:5115.6-5115.33"
case 1'1
assign $0\gpio1_oe_storage[7:0] \libresocsim_csrbank2_oe0_r
case
end
- attribute \src "ls180.v:5100.2-5102.5"
+ attribute \src "ls180.v:5119.2-5121.5"
switch \libresocsim_csrbank2_out0_re
- attribute \src "ls180.v:5100.6-5100.34"
+ attribute \src "ls180.v:5119.6-5119.34"
case 1'1
assign $0\gpio1_out_storage[7:0] \libresocsim_csrbank2_out0_r
case
end
- attribute \src "ls180.v:5105.2-5114.5"
+ attribute \src "ls180.v:5124.2-5133.5"
switch \libresocsim_csrbank3_sel
- attribute \src "ls180.v:5105.6-5105.30"
+ attribute \src "ls180.v:5124.6-5124.30"
case 1'1
- attribute \src "ls180.v:5106.3-5113.10"
+ attribute \src "ls180.v:5125.3-5132.10"
switch \libresocsim_interface3_bank_bus_adr [0]
attribute \src "ls180.v:0.0-0.0"
case 1'0
end
case
end
- attribute \src "ls180.v:5115.2-5117.5"
+ attribute \src "ls180.v:5134.2-5136.5"
switch \libresocsim_csrbank3_w0_re
- attribute \src "ls180.v:5115.6-5115.32"
+ attribute \src "ls180.v:5134.6-5134.32"
case 1'1
assign $0\i2c_storage[2:0] \libresocsim_csrbank3_w0_r
case
end
- attribute \src "ls180.v:5120.2-5153.5"
+ attribute \src "ls180.v:5139.2-5172.5"
switch \libresocsim_csrbank4_sel
- attribute \src "ls180.v:5120.6-5120.30"
+ attribute \src "ls180.v:5139.6-5139.30"
case 1'1
- attribute \src "ls180.v:5121.3-5152.10"
+ attribute \src "ls180.v:5140.3-5171.10"
switch \libresocsim_interface4_bank_bus_adr [3:0]
attribute \src "ls180.v:0.0-0.0"
case 4'0000
end
case
end
- attribute \src "ls180.v:5154.2-5156.5"
+ attribute \src "ls180.v:5173.2-5175.5"
switch \libresocsim_csrbank4_dfii_control0_re
- attribute \src "ls180.v:5154.6-5154.43"
+ attribute \src "ls180.v:5173.6-5173.43"
case 1'1
assign $0\sdram_storage[3:0] \libresocsim_csrbank4_dfii_control0_r
case
end
- attribute \src "ls180.v:5158.2-5160.5"
+ attribute \src "ls180.v:5177.2-5179.5"
switch \libresocsim_csrbank4_dfii_pi0_command0_re
- attribute \src "ls180.v:5158.6-5158.47"
+ attribute \src "ls180.v:5177.6-5177.47"
case 1'1
assign $0\sdram_command_storage[5:0] \libresocsim_csrbank4_dfii_pi0_command0_r
case
end
- attribute \src "ls180.v:5162.2-5164.5"
+ attribute \src "ls180.v:5181.2-5183.5"
switch \libresocsim_csrbank4_dfii_pi0_address1_re
- attribute \src "ls180.v:5162.6-5162.47"
+ attribute \src "ls180.v:5181.6-5181.47"
case 1'1
assign $0\sdram_address_storage[12:0] [12:8] \libresocsim_csrbank4_dfii_pi0_address1_r
case
end
- attribute \src "ls180.v:5165.2-5167.5"
+ attribute \src "ls180.v:5184.2-5186.5"
switch \libresocsim_csrbank4_dfii_pi0_address0_re
- attribute \src "ls180.v:5165.6-5165.47"
+ attribute \src "ls180.v:5184.6-5184.47"
case 1'1
assign $0\sdram_address_storage[12:0] [7:0] \libresocsim_csrbank4_dfii_pi0_address0_r
case
end
- attribute \src "ls180.v:5169.2-5171.5"
+ attribute \src "ls180.v:5188.2-5190.5"
switch \libresocsim_csrbank4_dfii_pi0_baddress0_re
- attribute \src "ls180.v:5169.6-5169.48"
+ attribute \src "ls180.v:5188.6-5188.48"
case 1'1
assign $0\sdram_baddress_storage[1:0] \libresocsim_csrbank4_dfii_pi0_baddress0_r
case
end
- attribute \src "ls180.v:5173.2-5175.5"
+ attribute \src "ls180.v:5192.2-5194.5"
switch \libresocsim_csrbank4_dfii_pi0_wrdata1_re
- attribute \src "ls180.v:5173.6-5173.46"
+ attribute \src "ls180.v:5192.6-5192.46"
case 1'1
assign $0\sdram_wrdata_storage[15:0] [15:8] \libresocsim_csrbank4_dfii_pi0_wrdata1_r
case
end
- attribute \src "ls180.v:5176.2-5178.5"
+ attribute \src "ls180.v:5195.2-5197.5"
switch \libresocsim_csrbank4_dfii_pi0_wrdata0_re
- attribute \src "ls180.v:5176.6-5176.46"
+ attribute \src "ls180.v:5195.6-5195.46"
case 1'1
assign $0\sdram_wrdata_storage[15:0] [7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_r
case
end
- attribute \src "ls180.v:5181.2-5235.5"
+ attribute \src "ls180.v:5200.2-5254.5"
switch \libresocsim_csrbank5_sel
- attribute \src "ls180.v:5181.6-5181.30"
+ attribute \src "ls180.v:5200.6-5200.30"
case 1'1
- attribute \src "ls180.v:5182.3-5234.10"
+ attribute \src "ls180.v:5201.3-5253.10"
switch \libresocsim_interface5_bank_bus_adr [4:0]
attribute \src "ls180.v:0.0-0.0"
case 5'00000
end
case
end
- attribute \src "ls180.v:5236.2-5238.5"
+ attribute \src "ls180.v:5255.2-5257.5"
switch \libresocsim_csrbank5_load3_re
- attribute \src "ls180.v:5236.6-5236.35"
+ attribute \src "ls180.v:5255.6-5255.35"
case 1'1
assign $0\libresocsim_load_storage[31:0] [31:24] \libresocsim_csrbank5_load3_r
case
end
- attribute \src "ls180.v:5239.2-5241.5"
+ attribute \src "ls180.v:5258.2-5260.5"
switch \libresocsim_csrbank5_load2_re
- attribute \src "ls180.v:5239.6-5239.35"
+ attribute \src "ls180.v:5258.6-5258.35"
case 1'1
assign $0\libresocsim_load_storage[31:0] [23:16] \libresocsim_csrbank5_load2_r
case
end
- attribute \src "ls180.v:5242.2-5244.5"
+ attribute \src "ls180.v:5261.2-5263.5"
switch \libresocsim_csrbank5_load1_re
- attribute \src "ls180.v:5242.6-5242.35"
+ attribute \src "ls180.v:5261.6-5261.35"
case 1'1
assign $0\libresocsim_load_storage[31:0] [15:8] \libresocsim_csrbank5_load1_r
case
end
- attribute \src "ls180.v:5245.2-5247.5"
+ attribute \src "ls180.v:5264.2-5266.5"
switch \libresocsim_csrbank5_load0_re
- attribute \src "ls180.v:5245.6-5245.35"
+ attribute \src "ls180.v:5264.6-5264.35"
case 1'1
assign $0\libresocsim_load_storage[31:0] [7:0] \libresocsim_csrbank5_load0_r
case
end
- attribute \src "ls180.v:5249.2-5251.5"
+ attribute \src "ls180.v:5268.2-5270.5"
switch \libresocsim_csrbank5_reload3_re
- attribute \src "ls180.v:5249.6-5249.37"
+ attribute \src "ls180.v:5268.6-5268.37"
case 1'1
assign $0\libresocsim_reload_storage[31:0] [31:24] \libresocsim_csrbank5_reload3_r
case
end
- attribute \src "ls180.v:5252.2-5254.5"
+ attribute \src "ls180.v:5271.2-5273.5"
switch \libresocsim_csrbank5_reload2_re
- attribute \src "ls180.v:5252.6-5252.37"
+ attribute \src "ls180.v:5271.6-5271.37"
case 1'1
assign $0\libresocsim_reload_storage[31:0] [23:16] \libresocsim_csrbank5_reload2_r
case
end
- attribute \src "ls180.v:5255.2-5257.5"
+ attribute \src "ls180.v:5274.2-5276.5"
switch \libresocsim_csrbank5_reload1_re
- attribute \src "ls180.v:5255.6-5255.37"
+ attribute \src "ls180.v:5274.6-5274.37"
case 1'1
assign $0\libresocsim_reload_storage[31:0] [15:8] \libresocsim_csrbank5_reload1_r
case
end
- attribute \src "ls180.v:5258.2-5260.5"
+ attribute \src "ls180.v:5277.2-5279.5"
switch \libresocsim_csrbank5_reload0_re
- attribute \src "ls180.v:5258.6-5258.37"
+ attribute \src "ls180.v:5277.6-5277.37"
case 1'1
assign $0\libresocsim_reload_storage[31:0] [7:0] \libresocsim_csrbank5_reload0_r
case
end
- attribute \src "ls180.v:5262.2-5264.5"
+ attribute \src "ls180.v:5281.2-5283.5"
switch \libresocsim_csrbank5_en0_re
- attribute \src "ls180.v:5262.6-5262.33"
+ attribute \src "ls180.v:5281.6-5281.33"
case 1'1
assign $0\libresocsim_en_storage[0:0] \libresocsim_csrbank5_en0_r
case
end
- attribute \src "ls180.v:5266.2-5268.5"
+ attribute \src "ls180.v:5285.2-5287.5"
switch \libresocsim_csrbank5_update_value0_re
- attribute \src "ls180.v:5266.6-5266.43"
+ attribute \src "ls180.v:5285.6-5285.43"
case 1'1
assign $0\libresocsim_update_value_storage[0:0] \libresocsim_csrbank5_update_value0_r
case
end
- attribute \src "ls180.v:5270.2-5272.5"
+ attribute \src "ls180.v:5289.2-5291.5"
switch \libresocsim_csrbank5_ev_enable0_re
- attribute \src "ls180.v:5270.6-5270.40"
+ attribute \src "ls180.v:5289.6-5289.40"
case 1'1
assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_csrbank5_ev_enable0_r
case
end
- attribute \src "ls180.v:5275.2-5302.5"
+ attribute \src "ls180.v:5294.2-5321.5"
switch \libresocsim_csrbank6_sel
- attribute \src "ls180.v:5275.6-5275.30"
+ attribute \src "ls180.v:5294.6-5294.30"
case 1'1
- attribute \src "ls180.v:5276.3-5301.10"
+ attribute \src "ls180.v:5295.3-5320.10"
switch \libresocsim_interface6_bank_bus_adr [2:0]
attribute \src "ls180.v:0.0-0.0"
case 3'000
end
case
end
- attribute \src "ls180.v:5303.2-5305.5"
+ attribute \src "ls180.v:5322.2-5324.5"
switch \libresocsim_csrbank6_ev_enable0_re
- attribute \src "ls180.v:5303.6-5303.40"
+ attribute \src "ls180.v:5322.6-5322.40"
case 1'1
assign $0\eventmanager_storage[1:0] \libresocsim_csrbank6_ev_enable0_r
case
end
- attribute \src "ls180.v:5308.2-5323.5"
+ attribute \src "ls180.v:5327.2-5342.5"
switch \libresocsim_csrbank7_sel
- attribute \src "ls180.v:5308.6-5308.30"
+ attribute \src "ls180.v:5327.6-5327.30"
case 1'1
- attribute \src "ls180.v:5309.3-5322.10"
+ attribute \src "ls180.v:5328.3-5341.10"
switch \libresocsim_interface7_bank_bus_adr [1:0]
attribute \src "ls180.v:0.0-0.0"
case 2'00
end
case
end
- attribute \src "ls180.v:5324.2-5326.5"
+ attribute \src "ls180.v:5343.2-5345.5"
switch \libresocsim_csrbank7_tuning_word3_re
- attribute \src "ls180.v:5324.6-5324.42"
+ attribute \src "ls180.v:5343.6-5343.42"
case 1'1
assign $0\uart_phy_storage[31:0] [31:24] \libresocsim_csrbank7_tuning_word3_r
case
end
- attribute \src "ls180.v:5327.2-5329.5"
+ attribute \src "ls180.v:5346.2-5348.5"
switch \libresocsim_csrbank7_tuning_word2_re
- attribute \src "ls180.v:5327.6-5327.42"
+ attribute \src "ls180.v:5346.6-5346.42"
case 1'1
assign $0\uart_phy_storage[31:0] [23:16] \libresocsim_csrbank7_tuning_word2_r
case
end
- attribute \src "ls180.v:5330.2-5332.5"
+ attribute \src "ls180.v:5349.2-5351.5"
switch \libresocsim_csrbank7_tuning_word1_re
- attribute \src "ls180.v:5330.6-5330.42"
+ attribute \src "ls180.v:5349.6-5349.42"
case 1'1
assign $0\uart_phy_storage[31:0] [15:8] \libresocsim_csrbank7_tuning_word1_r
case
end
- attribute \src "ls180.v:5333.2-5335.5"
+ attribute \src "ls180.v:5352.2-5354.5"
switch \libresocsim_csrbank7_tuning_word0_re
- attribute \src "ls180.v:5333.6-5333.42"
+ attribute \src "ls180.v:5352.6-5352.42"
case 1'1
assign $0\uart_phy_storage[31:0] [7:0] \libresocsim_csrbank7_tuning_word0_r
case
end
- attribute \src "ls180.v:5337.2-5484.5"
+ attribute \src "ls180.v:5356.2-5503.5"
switch \sys_rst_1
- attribute \src "ls180.v:5337.6-5337.15"
+ attribute \src "ls180.v:5356.6-5356.15"
case 1'1
assign $0\libresocsim_reset_storage[0:0] 1'0
assign $0\libresocsim_reset_re[0:0] 1'0
assign $0\libresocsim_scratch_storage[31:0] 305419896
assign $0\libresocsim_scratch_re[0:0] 1'0
assign $0\libresocsim_bus_errors[31:0] 0
- assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1
+ assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
assign $0\libresocsim_ram_bus_ack[0:0] 1'0
assign $0\libresocsim_load_storage[31:0] 0
assign $0\libresocsim_load_re[0:0] 1'0
assign $0\gpio1_oe_re[0:0] 1'0
assign $0\gpio1_out_storage[7:0] 8'00000000
assign $0\gpio1_out_re[0:0] 1'0
- assign $0\dummy[29:0] 30'000000000000000000000000000000
+ assign $0\dummy[35:0] 36'000000000000000000000000000000000000
assign $0\i2c_storage[2:0] 3'000
assign $0\i2c_re[0:0] 1'0
assign $0\subfragments_converter0_state[0:0] 1'0
update \libresocsim_scratch_storage $0\libresocsim_scratch_storage[31:0]
update \libresocsim_scratch_re $0\libresocsim_scratch_re[0:0]
update \libresocsim_bus_errors $0\libresocsim_bus_errors[31:0]
- update \libresocsim_libresoc_constraintmanager_obj_uart_tx $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0]
+ update \libresocsim_libresoc_constraintmanager_uart_tx $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
update \libresocsim_ram_bus_ack $0\libresocsim_ram_bus_ack[0:0]
update \libresocsim_load_storage $0\libresocsim_load_storage[31:0]
update \libresocsim_load_re $0\libresocsim_load_re[0:0]
update \gpio1_oe_re $0\gpio1_oe_re[0:0]
update \gpio1_out_storage $0\gpio1_out_storage[7:0]
update \gpio1_out_re $0\gpio1_out_re[0:0]
- update \dummy $0\dummy[29:0]
+ update \dummy $0\dummy[35:0]
update \i2c_storage $0\i2c_storage[2:0]
update \i2c_re $0\i2c_re[0:0]
update \subfragments_converter0_state $0\subfragments_converter0_state[0:0]
update \regs0 $0\regs0[0:0]
update \regs1 $0\regs1[0:0]
end
- attribute \src "ls180.v:429.11-429.65"
- process $proc$ls180.v:429$1777
+ attribute \src "ls180.v:431.11-431.63"
+ process $proc$ls180.v:431$1782
assign { } { }
- assign $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
+ assign $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
- update \sdram_bankmachine0_cmd_buffer_lookahead_produce $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
+ update \sdram_bankmachine0_cmd_buffer_lookahead_level $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:43.5-43.37"
- process $proc$ls180.v:43$1620
+ attribute \src "ls180.v:432.5-432.59"
+ process $proc$ls180.v:432$1783
assign { } { }
- assign $1\libresocsim_reset_storage[0:0] 1'0
+ assign $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
+ update \sdram_bankmachine0_cmd_buffer_lookahead_replace $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0]
sync init
- update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0]
end
- attribute \src "ls180.v:430.11-430.65"
- process $proc$ls180.v:430$1778
+ attribute \src "ls180.v:433.11-433.65"
+ process $proc$ls180.v:433$1784
assign { } { }
- assign $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
+ assign $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
- update \sdram_bankmachine0_cmd_buffer_lookahead_consume $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
+ update \sdram_bankmachine0_cmd_buffer_lookahead_produce $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:431.11-431.68"
- process $proc$ls180.v:431$1779
+ attribute \src "ls180.v:434.11-434.65"
+ process $proc$ls180.v:434$1785
assign { } { }
- assign $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
+ assign $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
- update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
+ update \sdram_bankmachine0_cmd_buffer_lookahead_consume $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:44.5-44.32"
- process $proc$ls180.v:44$1621
+ attribute \src "ls180.v:435.11-435.68"
+ process $proc$ls180.v:435$1786
assign { } { }
- assign $1\libresocsim_reset_re[0:0] 1'0
+ assign $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
- update \libresocsim_reset_re $1\libresocsim_reset_re[0:0]
+ update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:45.12-45.55"
- process $proc$ls180.v:45$1622
+ attribute \src "ls180.v:45.5-45.37"
+ process $proc$ls180.v:45$1627
assign { } { }
- assign $1\libresocsim_scratch_storage[31:0] 305419896
+ assign $1\libresocsim_reset_storage[0:0] 1'0
sync always
sync init
- update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0]
+ update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0]
end
- attribute \src "ls180.v:452.5-452.54"
- process $proc$ls180.v:452$1780
+ attribute \src "ls180.v:456.5-456.54"
+ process $proc$ls180.v:456$1787
assign { } { }
assign $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_cmd_buffer_source_valid $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:454.5-454.54"
- process $proc$ls180.v:454$1781
+ attribute \src "ls180.v:458.5-458.54"
+ process $proc$ls180.v:458$1788
assign { } { }
assign $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_cmd_buffer_source_first $1\sdram_bankmachine0_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:455.5-455.53"
- process $proc$ls180.v:455$1782
+ attribute \src "ls180.v:459.5-459.53"
+ process $proc$ls180.v:459$1789
assign { } { }
assign $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_cmd_buffer_source_last $1\sdram_bankmachine0_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:456.5-456.59"
- process $proc$ls180.v:456$1783
+ attribute \src "ls180.v:46.5-46.32"
+ process $proc$ls180.v:46$1628
+ assign { } { }
+ assign $1\libresocsim_reset_re[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_reset_re $1\libresocsim_reset_re[0:0]
+ end
+ attribute \src "ls180.v:460.5-460.59"
+ process $proc$ls180.v:460$1790
assign { } { }
assign $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_cmd_buffer_source_payload_we $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:457.12-457.69"
- process $proc$ls180.v:457$1784
+ attribute \src "ls180.v:461.12-461.69"
+ process $proc$ls180.v:461$1791
assign { } { }
assign $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \sdram_bankmachine0_cmd_buffer_source_payload_addr $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:458.12-458.42"
- process $proc$ls180.v:458$1785
+ attribute \src "ls180.v:462.12-462.42"
+ process $proc$ls180.v:462$1792
assign { } { }
assign $1\sdram_bankmachine0_row[12:0] 13'0000000000000
sync always
sync init
update \sdram_bankmachine0_row $1\sdram_bankmachine0_row[12:0]
end
- attribute \src "ls180.v:459.5-459.41"
- process $proc$ls180.v:459$1786
- assign { } { }
- assign $1\sdram_bankmachine0_row_opened[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine0_row_opened $1\sdram_bankmachine0_row_opened[0:0]
- end
- attribute \src "ls180.v:46.5-46.34"
- process $proc$ls180.v:46$1623
+ attribute \src "ls180.v:463.5-463.41"
+ process $proc$ls180.v:463$1793
assign { } { }
- assign $1\libresocsim_scratch_re[0:0] 1'0
+ assign $1\sdram_bankmachine0_row_opened[0:0] 1'0
sync always
sync init
- update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0]
+ update \sdram_bankmachine0_row_opened $1\sdram_bankmachine0_row_opened[0:0]
end
- attribute \src "ls180.v:461.5-461.39"
- process $proc$ls180.v:461$1787
+ attribute \src "ls180.v:465.5-465.39"
+ process $proc$ls180.v:465$1794
assign { } { }
assign $1\sdram_bankmachine0_row_open[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_row_open $1\sdram_bankmachine0_row_open[0:0]
end
- attribute \src "ls180.v:462.5-462.40"
- process $proc$ls180.v:462$1788
+ attribute \src "ls180.v:466.5-466.40"
+ process $proc$ls180.v:466$1795
assign { } { }
assign $1\sdram_bankmachine0_row_close[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_row_close $1\sdram_bankmachine0_row_close[0:0]
end
- attribute \src "ls180.v:463.5-463.49"
- process $proc$ls180.v:463$1789
+ attribute \src "ls180.v:467.5-467.49"
+ process $proc$ls180.v:467$1796
assign { } { }
assign $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_row_col_n_addr_sel $1\sdram_bankmachine0_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:465.32-465.71"
- process $proc$ls180.v:465$1790
+ attribute \src "ls180.v:469.32-469.71"
+ process $proc$ls180.v:469$1797
assign { } { }
assign $1\sdram_bankmachine0_twtpcon_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine0_twtpcon_ready $1\sdram_bankmachine0_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:466.11-466.50"
- process $proc$ls180.v:466$1791
+ attribute \src "ls180.v:47.12-47.55"
+ process $proc$ls180.v:47$1629
+ assign { } { }
+ assign $1\libresocsim_scratch_storage[31:0] 305419896
+ sync always
+ sync init
+ update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0]
+ end
+ attribute \src "ls180.v:470.11-470.50"
+ process $proc$ls180.v:470$1798
assign { } { }
assign $1\sdram_bankmachine0_twtpcon_count[2:0] 3'000
sync always
sync init
update \sdram_bankmachine0_twtpcon_count $1\sdram_bankmachine0_twtpcon_count[2:0]
end
- attribute \src "ls180.v:468.32-468.70"
- process $proc$ls180.v:468$1792
+ attribute \src "ls180.v:472.32-472.70"
+ process $proc$ls180.v:472$1799
assign { } { }
assign $0\sdram_bankmachine0_trccon_ready[0:0] 1'1
sync always
update \sdram_bankmachine0_trccon_ready $0\sdram_bankmachine0_trccon_ready[0:0]
sync init
end
- attribute \src "ls180.v:470.32-470.71"
- process $proc$ls180.v:470$1793
+ attribute \src "ls180.v:474.32-474.71"
+ process $proc$ls180.v:474$1800
assign { } { }
assign $0\sdram_bankmachine0_trascon_ready[0:0] 1'1
sync always
update \sdram_bankmachine0_trascon_ready $0\sdram_bankmachine0_trascon_ready[0:0]
sync init
end
- attribute \src "ls180.v:476.5-476.46"
- process $proc$ls180.v:476$1794
+ attribute \src "ls180.v:48.5-48.34"
+ process $proc$ls180.v:48$1630
+ assign { } { }
+ assign $1\libresocsim_scratch_re[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0]
+ end
+ attribute \src "ls180.v:480.5-480.46"
+ process $proc$ls180.v:480$1801
assign { } { }
assign $1\sdram_bankmachine1_req_wdata_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_req_wdata_ready $1\sdram_bankmachine1_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:477.5-477.46"
- process $proc$ls180.v:477$1795
+ attribute \src "ls180.v:481.5-481.46"
+ process $proc$ls180.v:481$1802
assign { } { }
assign $1\sdram_bankmachine1_req_rdata_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_req_rdata_valid $1\sdram_bankmachine1_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:479.5-479.42"
- process $proc$ls180.v:479$1796
+ attribute \src "ls180.v:483.5-483.42"
+ process $proc$ls180.v:483$1803
assign { } { }
assign $1\sdram_bankmachine1_refresh_gnt[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_refresh_gnt $1\sdram_bankmachine1_refresh_gnt[0:0]
end
- attribute \src "ls180.v:480.5-480.40"
- process $proc$ls180.v:480$1797
+ attribute \src "ls180.v:484.5-484.40"
+ process $proc$ls180.v:484$1804
assign { } { }
assign $1\sdram_bankmachine1_cmd_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_valid $1\sdram_bankmachine1_cmd_valid[0:0]
end
- attribute \src "ls180.v:481.5-481.40"
- process $proc$ls180.v:481$1798
+ attribute \src "ls180.v:485.5-485.40"
+ process $proc$ls180.v:485$1805
assign { } { }
assign $1\sdram_bankmachine1_cmd_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_ready $1\sdram_bankmachine1_cmd_ready[0:0]
end
- attribute \src "ls180.v:482.12-482.52"
- process $proc$ls180.v:482$1799
+ attribute \src "ls180.v:486.12-486.52"
+ process $proc$ls180.v:486$1806
assign { } { }
assign $1\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
update \sdram_bankmachine1_cmd_payload_a $1\sdram_bankmachine1_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:484.5-484.46"
- process $proc$ls180.v:484$1800
+ attribute \src "ls180.v:488.5-488.46"
+ process $proc$ls180.v:488$1807
assign { } { }
assign $1\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_payload_cas $1\sdram_bankmachine1_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:485.5-485.46"
- process $proc$ls180.v:485$1801
+ attribute \src "ls180.v:489.5-489.46"
+ process $proc$ls180.v:489$1808
assign { } { }
assign $1\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_payload_ras $1\sdram_bankmachine1_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:486.5-486.45"
- process $proc$ls180.v:486$1802
+ attribute \src "ls180.v:490.5-490.45"
+ process $proc$ls180.v:490$1809
assign { } { }
assign $1\sdram_bankmachine1_cmd_payload_we[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_payload_we $1\sdram_bankmachine1_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:487.5-487.49"
- process $proc$ls180.v:487$1803
+ attribute \src "ls180.v:491.5-491.49"
+ process $proc$ls180.v:491$1810
assign { } { }
assign $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_payload_is_cmd $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:488.5-488.50"
- process $proc$ls180.v:488$1804
+ attribute \src "ls180.v:492.5-492.50"
+ process $proc$ls180.v:492$1811
assign { } { }
assign $1\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_payload_is_read $1\sdram_bankmachine1_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:489.5-489.51"
- process $proc$ls180.v:489$1805
+ attribute \src "ls180.v:493.5-493.51"
+ process $proc$ls180.v:493$1812
assign { } { }
assign $1\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_payload_is_write $1\sdram_bankmachine1_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:490.5-490.45"
- process $proc$ls180.v:490$1806
+ attribute \src "ls180.v:494.5-494.45"
+ process $proc$ls180.v:494$1813
assign { } { }
assign $1\sdram_bankmachine1_auto_precharge[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_auto_precharge $1\sdram_bankmachine1_auto_precharge[0:0]
end
- attribute \src "ls180.v:493.5-493.62"
- process $proc$ls180.v:493$1807
+ attribute \src "ls180.v:497.5-497.62"
+ process $proc$ls180.v:497$1814
assign { } { }
assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:494.5-494.61"
- process $proc$ls180.v:494$1808
+ attribute \src "ls180.v:498.5-498.61"
+ process $proc$ls180.v:498$1815
assign { } { }
assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:509.11-509.63"
- process $proc$ls180.v:509$1809
+ attribute \src "ls180.v:513.11-513.63"
+ process $proc$ls180.v:513$1816
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_lookahead_level $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:51.12-51.42"
- process $proc$ls180.v:51$1624
- assign { } { }
- assign $1\libresocsim_bus_errors[31:0] 0
- sync always
- sync init
- update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0]
- end
- attribute \src "ls180.v:510.5-510.59"
- process $proc$ls180.v:510$1810
+ attribute \src "ls180.v:514.5-514.59"
+ process $proc$ls180.v:514$1817
assign { } { }
assign $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \sdram_bankmachine1_cmd_buffer_lookahead_replace $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0]
sync init
end
- attribute \src "ls180.v:511.11-511.65"
- process $proc$ls180.v:511$1811
+ attribute \src "ls180.v:515.11-515.65"
+ process $proc$ls180.v:515$1818
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_lookahead_produce $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:512.11-512.65"
- process $proc$ls180.v:512$1812
+ attribute \src "ls180.v:516.11-516.65"
+ process $proc$ls180.v:516$1819
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_lookahead_consume $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:513.11-513.68"
- process $proc$ls180.v:513$1813
+ attribute \src "ls180.v:517.11-517.68"
+ process $proc$ls180.v:517$1820
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:53.12-53.50"
- process $proc$ls180.v:53$1625
+ attribute \src "ls180.v:53.12-53.42"
+ process $proc$ls180.v:53$1631
assign { } { }
- assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
+ assign $1\libresocsim_bus_errors[31:0] 0
sync always
sync init
- update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0]
+ update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0]
end
- attribute \src "ls180.v:534.5-534.54"
- process $proc$ls180.v:534$1814
+ attribute \src "ls180.v:538.5-538.54"
+ process $proc$ls180.v:538$1821
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:536.5-536.54"
- process $proc$ls180.v:536$1815
+ attribute \src "ls180.v:540.5-540.54"
+ process $proc$ls180.v:540$1822
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:537.5-537.53"
- process $proc$ls180.v:537$1816
+ attribute \src "ls180.v:541.5-541.53"
+ process $proc$ls180.v:541$1823
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:538.5-538.59"
- process $proc$ls180.v:538$1817
+ attribute \src "ls180.v:542.5-542.59"
+ process $proc$ls180.v:542$1824
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:539.12-539.69"
- process $proc$ls180.v:539$1818
+ attribute \src "ls180.v:543.12-543.69"
+ process $proc$ls180.v:543$1825
assign { } { }
assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:540.12-540.42"
- process $proc$ls180.v:540$1819
+ attribute \src "ls180.v:544.12-544.42"
+ process $proc$ls180.v:544$1826
assign { } { }
assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000
sync always
sync init
update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0]
end
- attribute \src "ls180.v:541.5-541.41"
- process $proc$ls180.v:541$1820
+ attribute \src "ls180.v:545.5-545.41"
+ process $proc$ls180.v:545$1827
assign { } { }
assign $1\sdram_bankmachine1_row_opened[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0]
end
- attribute \src "ls180.v:543.5-543.39"
- process $proc$ls180.v:543$1821
+ attribute \src "ls180.v:547.5-547.39"
+ process $proc$ls180.v:547$1828
assign { } { }
assign $1\sdram_bankmachine1_row_open[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0]
end
- attribute \src "ls180.v:544.5-544.40"
- process $proc$ls180.v:544$1822
+ attribute \src "ls180.v:548.5-548.40"
+ process $proc$ls180.v:548$1829
assign { } { }
assign $1\sdram_bankmachine1_row_close[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0]
end
- attribute \src "ls180.v:545.5-545.49"
- process $proc$ls180.v:545$1823
+ attribute \src "ls180.v:549.5-549.49"
+ process $proc$ls180.v:549$1830
assign { } { }
assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:547.32-547.71"
- process $proc$ls180.v:547$1824
+ attribute \src "ls180.v:55.12-55.50"
+ process $proc$ls180.v:55$1632
assign { } { }
- assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0
+ assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000
sync always
sync init
- update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0]
+ update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0]
end
- attribute \src "ls180.v:548.11-548.50"
- process $proc$ls180.v:548$1825
+ attribute \src "ls180.v:551.32-551.71"
+ process $proc$ls180.v:551$1831
assign { } { }
- assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000
+ assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0
sync always
sync init
- update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0]
+ update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:5491.1-5509.4"
- process $proc$ls180.v:5491$1459
+ attribute \src "ls180.v:5510.1-5528.4"
+ process $proc$ls180.v:5510$1466
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1460 $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484
- assign $0$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1461 $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485
- assign $0$memwr$\mem$ls180.v:5493$1_EN[63:0]$1462 $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486
- assign $0$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1463 $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487
- assign $0$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1464 $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488
- assign $0$memwr$\mem$ls180.v:5495$2_EN[63:0]$1465 $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489
- assign $0$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1466 $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490
- assign $0$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1467 $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491
- assign $0$memwr$\mem$ls180.v:5497$3_EN[63:0]$1468 $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492
- assign $0$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1469 $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493
- assign $0$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1470 $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494
- assign $0$memwr$\mem$ls180.v:5499$4_EN[63:0]$1471 $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495
- assign $0$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1472 $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496
- assign $0$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1473 $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497
- assign $0$memwr$\mem$ls180.v:5501$5_EN[63:0]$1474 $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498
- assign $0$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1475 $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499
- assign $0$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1476 $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500
- assign $0$memwr$\mem$ls180.v:5503$6_EN[63:0]$1477 $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501
- assign $0$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1478 $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502
- assign $0$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1479 $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503
- assign $0$memwr$\mem$ls180.v:5505$7_EN[63:0]$1480 $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504
- assign $0$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1481 $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505
- assign $0$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1482 $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506
- assign $0$memwr$\mem$ls180.v:5507$8_EN[63:0]$1483 $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507
+ assign $0$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1467 $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491
+ assign $0$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1468 $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492
+ assign $0$memwr$\mem$ls180.v:5512$1_EN[63:0]$1469 $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493
+ assign $0$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1470 $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494
+ assign $0$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1471 $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495
+ assign $0$memwr$\mem$ls180.v:5514$2_EN[63:0]$1472 $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496
+ assign $0$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1473 $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497
+ assign $0$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1474 $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498
+ assign $0$memwr$\mem$ls180.v:5516$3_EN[63:0]$1475 $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499
+ assign $0$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1476 $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500
+ assign $0$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1477 $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501
+ assign $0$memwr$\mem$ls180.v:5518$4_EN[63:0]$1478 $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502
+ assign $0$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1479 $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503
+ assign $0$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1480 $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504
+ assign $0$memwr$\mem$ls180.v:5520$5_EN[63:0]$1481 $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505
+ assign $0$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1482 $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506
+ assign $0$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1483 $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507
+ assign $0$memwr$\mem$ls180.v:5522$6_EN[63:0]$1484 $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508
+ assign $0$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1485 $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509
+ assign $0$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1486 $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510
+ assign $0$memwr$\mem$ls180.v:5524$7_EN[63:0]$1487 $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511
+ assign $0$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1488 $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512
+ assign $0$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1489 $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513
+ assign $0$memwr$\mem$ls180.v:5526$8_EN[63:0]$1490 $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514
assign $0\memadr[5:0] \libresocsim_adr
- attribute \src "ls180.v:5492.2-5493.55"
+ attribute \src "ls180.v:5511.2-5512.55"
switch \libresocsim_we [0]
- attribute \src "ls180.v:5492.6-5492.23"
+ attribute \src "ls180.v:5511.6-5511.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 { 56'00000000000000000000000000000000000000000000000000000000 \libresocsim_dat_w [7:0] }
- assign $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 64'0000000000000000000000000000000000000000000000000000000011111111
+ assign $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492 { 56'00000000000000000000000000000000000000000000000000000000 \libresocsim_dat_w [7:0] }
+ assign $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493 64'0000000000000000000000000000000000000000000000000000000011111111
case
- assign $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5494.2-5495.57"
+ attribute \src "ls180.v:5513.2-5514.57"
switch \libresocsim_we [1]
- attribute \src "ls180.v:5494.6-5494.23"
+ attribute \src "ls180.v:5513.6-5513.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 { 48'000000000000000000000000000000000000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx }
- assign $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 64'0000000000000000000000000000000000000000000000001111111100000000
+ assign $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495 { 48'000000000000000000000000000000000000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx }
+ assign $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496 64'0000000000000000000000000000000000000000000000001111111100000000
case
- assign $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5496.2-5497.59"
+ attribute \src "ls180.v:5515.2-5516.59"
switch \libresocsim_we [2]
- attribute \src "ls180.v:5496.6-5496.23"
+ attribute \src "ls180.v:5515.6-5515.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 { 40'0000000000000000000000000000000000000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 64'0000000000000000000000000000000000000000111111110000000000000000
+ assign $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498 { 40'0000000000000000000000000000000000000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499 64'0000000000000000000000000000000000000000111111110000000000000000
case
- assign $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5498.2-5499.59"
+ attribute \src "ls180.v:5517.2-5518.59"
switch \libresocsim_we [3]
- attribute \src "ls180.v:5498.6-5498.23"
+ attribute \src "ls180.v:5517.6-5517.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 { 32'00000000000000000000000000000000 \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 64'0000000000000000000000000000000011111111000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501 { 32'00000000000000000000000000000000 \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502 64'0000000000000000000000000000000011111111000000000000000000000000
case
- assign $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5500.2-5501.59"
+ attribute \src "ls180.v:5519.2-5520.59"
switch \libresocsim_we [4]
- attribute \src "ls180.v:5500.6-5500.23"
+ attribute \src "ls180.v:5519.6-5519.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 { 24'000000000000000000000000 \libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 64'0000000000000000000000001111111100000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504 { 24'000000000000000000000000 \libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505 64'0000000000000000000000001111111100000000000000000000000000000000
case
- assign $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5502.2-5503.59"
+ attribute \src "ls180.v:5521.2-5522.59"
switch \libresocsim_we [5]
- attribute \src "ls180.v:5502.6-5502.23"
+ attribute \src "ls180.v:5521.6-5521.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 { 16'0000000000000000 \libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 64'0000000000000000111111110000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507 { 16'0000000000000000 \libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508 64'0000000000000000111111110000000000000000000000000000000000000000
case
- assign $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5504.2-5505.59"
+ attribute \src "ls180.v:5523.2-5524.59"
switch \libresocsim_we [6]
- attribute \src "ls180.v:5504.6-5504.23"
+ attribute \src "ls180.v:5523.6-5523.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 { 8'00000000 \libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 64'0000000011111111000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510 { 8'00000000 \libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511 64'0000000011111111000000000000000000000000000000000000000000000000
case
- assign $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5506.2-5507.59"
+ attribute \src "ls180.v:5525.2-5526.59"
switch \libresocsim_we [7]
- attribute \src "ls180.v:5506.6-5506.23"
+ attribute \src "ls180.v:5525.6-5525.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 \libresocsim_adr
- assign $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 { \libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 64'1111111100000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512 \libresocsim_adr
+ assign $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513 { \libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514 64'1111111100000000000000000000000000000000000000000000000000000000
case
- assign $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 6'xxxxxx
- assign $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512 6'xxxxxx
+ assign $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync posedge \sys_clk_1
update \memadr $0\memadr[5:0]
- update $memwr$\mem$ls180.v:5493$1_ADDR $0$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1460
- update $memwr$\mem$ls180.v:5493$1_DATA $0$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1461
- update $memwr$\mem$ls180.v:5493$1_EN $0$memwr$\mem$ls180.v:5493$1_EN[63:0]$1462
- update $memwr$\mem$ls180.v:5495$2_ADDR $0$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1463
- update $memwr$\mem$ls180.v:5495$2_DATA $0$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1464
- update $memwr$\mem$ls180.v:5495$2_EN $0$memwr$\mem$ls180.v:5495$2_EN[63:0]$1465
- update $memwr$\mem$ls180.v:5497$3_ADDR $0$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1466
- update $memwr$\mem$ls180.v:5497$3_DATA $0$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1467
- update $memwr$\mem$ls180.v:5497$3_EN $0$memwr$\mem$ls180.v:5497$3_EN[63:0]$1468
- update $memwr$\mem$ls180.v:5499$4_ADDR $0$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1469
- update $memwr$\mem$ls180.v:5499$4_DATA $0$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1470
- update $memwr$\mem$ls180.v:5499$4_EN $0$memwr$\mem$ls180.v:5499$4_EN[63:0]$1471
- update $memwr$\mem$ls180.v:5501$5_ADDR $0$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1472
- update $memwr$\mem$ls180.v:5501$5_DATA $0$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1473
- update $memwr$\mem$ls180.v:5501$5_EN $0$memwr$\mem$ls180.v:5501$5_EN[63:0]$1474
- update $memwr$\mem$ls180.v:5503$6_ADDR $0$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1475
- update $memwr$\mem$ls180.v:5503$6_DATA $0$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1476
- update $memwr$\mem$ls180.v:5503$6_EN $0$memwr$\mem$ls180.v:5503$6_EN[63:0]$1477
- update $memwr$\mem$ls180.v:5505$7_ADDR $0$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1478
- update $memwr$\mem$ls180.v:5505$7_DATA $0$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1479
- update $memwr$\mem$ls180.v:5505$7_EN $0$memwr$\mem$ls180.v:5505$7_EN[63:0]$1480
- update $memwr$\mem$ls180.v:5507$8_ADDR $0$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1481
- update $memwr$\mem$ls180.v:5507$8_DATA $0$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1482
- update $memwr$\mem$ls180.v:5507$8_EN $0$memwr$\mem$ls180.v:5507$8_EN[63:0]$1483
- attribute \src "ls180.v:5493.3-5493.54"
- memwr \mem $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 0'
- attribute \src "ls180.v:5495.3-5495.56"
- memwr \mem $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 1'1
- attribute \src "ls180.v:5497.3-5497.58"
- memwr \mem $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 2'11
- attribute \src "ls180.v:5499.3-5499.58"
- memwr \mem $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 3'111
- attribute \src "ls180.v:5501.3-5501.58"
- memwr \mem $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 4'1111
- attribute \src "ls180.v:5503.3-5503.58"
- memwr \mem $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 5'11111
- attribute \src "ls180.v:5505.3-5505.58"
- memwr \mem $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 6'111111
- attribute \src "ls180.v:5507.3-5507.58"
- memwr \mem $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 7'1111111
- end
- attribute \src "ls180.v:550.32-550.70"
- process $proc$ls180.v:550$1826
+ update $memwr$\mem$ls180.v:5512$1_ADDR $0$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1467
+ update $memwr$\mem$ls180.v:5512$1_DATA $0$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1468
+ update $memwr$\mem$ls180.v:5512$1_EN $0$memwr$\mem$ls180.v:5512$1_EN[63:0]$1469
+ update $memwr$\mem$ls180.v:5514$2_ADDR $0$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1470
+ update $memwr$\mem$ls180.v:5514$2_DATA $0$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1471
+ update $memwr$\mem$ls180.v:5514$2_EN $0$memwr$\mem$ls180.v:5514$2_EN[63:0]$1472
+ update $memwr$\mem$ls180.v:5516$3_ADDR $0$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1473
+ update $memwr$\mem$ls180.v:5516$3_DATA $0$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1474
+ update $memwr$\mem$ls180.v:5516$3_EN $0$memwr$\mem$ls180.v:5516$3_EN[63:0]$1475
+ update $memwr$\mem$ls180.v:5518$4_ADDR $0$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1476
+ update $memwr$\mem$ls180.v:5518$4_DATA $0$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1477
+ update $memwr$\mem$ls180.v:5518$4_EN $0$memwr$\mem$ls180.v:5518$4_EN[63:0]$1478
+ update $memwr$\mem$ls180.v:5520$5_ADDR $0$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1479
+ update $memwr$\mem$ls180.v:5520$5_DATA $0$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1480
+ update $memwr$\mem$ls180.v:5520$5_EN $0$memwr$\mem$ls180.v:5520$5_EN[63:0]$1481
+ update $memwr$\mem$ls180.v:5522$6_ADDR $0$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1482
+ update $memwr$\mem$ls180.v:5522$6_DATA $0$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1483
+ update $memwr$\mem$ls180.v:5522$6_EN $0$memwr$\mem$ls180.v:5522$6_EN[63:0]$1484
+ update $memwr$\mem$ls180.v:5524$7_ADDR $0$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1485
+ update $memwr$\mem$ls180.v:5524$7_DATA $0$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1486
+ update $memwr$\mem$ls180.v:5524$7_EN $0$memwr$\mem$ls180.v:5524$7_EN[63:0]$1487
+ update $memwr$\mem$ls180.v:5526$8_ADDR $0$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1488
+ update $memwr$\mem$ls180.v:5526$8_DATA $0$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1489
+ update $memwr$\mem$ls180.v:5526$8_EN $0$memwr$\mem$ls180.v:5526$8_EN[63:0]$1490
+ attribute \src "ls180.v:5512.3-5512.54"
+ memwr \mem $1$memwr$\mem$ls180.v:5512$1_ADDR[5:0]$1491 $1$memwr$\mem$ls180.v:5512$1_DATA[63:0]$1492 $1$memwr$\mem$ls180.v:5512$1_EN[63:0]$1493 0'
+ attribute \src "ls180.v:5514.3-5514.56"
+ memwr \mem $1$memwr$\mem$ls180.v:5514$2_ADDR[5:0]$1494 $1$memwr$\mem$ls180.v:5514$2_DATA[63:0]$1495 $1$memwr$\mem$ls180.v:5514$2_EN[63:0]$1496 1'1
+ attribute \src "ls180.v:5516.3-5516.58"
+ memwr \mem $1$memwr$\mem$ls180.v:5516$3_ADDR[5:0]$1497 $1$memwr$\mem$ls180.v:5516$3_DATA[63:0]$1498 $1$memwr$\mem$ls180.v:5516$3_EN[63:0]$1499 2'11
+ attribute \src "ls180.v:5518.3-5518.58"
+ memwr \mem $1$memwr$\mem$ls180.v:5518$4_ADDR[5:0]$1500 $1$memwr$\mem$ls180.v:5518$4_DATA[63:0]$1501 $1$memwr$\mem$ls180.v:5518$4_EN[63:0]$1502 3'111
+ attribute \src "ls180.v:5520.3-5520.58"
+ memwr \mem $1$memwr$\mem$ls180.v:5520$5_ADDR[5:0]$1503 $1$memwr$\mem$ls180.v:5520$5_DATA[63:0]$1504 $1$memwr$\mem$ls180.v:5520$5_EN[63:0]$1505 4'1111
+ attribute \src "ls180.v:5522.3-5522.58"
+ memwr \mem $1$memwr$\mem$ls180.v:5522$6_ADDR[5:0]$1506 $1$memwr$\mem$ls180.v:5522$6_DATA[63:0]$1507 $1$memwr$\mem$ls180.v:5522$6_EN[63:0]$1508 5'11111
+ attribute \src "ls180.v:5524.3-5524.58"
+ memwr \mem $1$memwr$\mem$ls180.v:5524$7_ADDR[5:0]$1509 $1$memwr$\mem$ls180.v:5524$7_DATA[63:0]$1510 $1$memwr$\mem$ls180.v:5524$7_EN[63:0]$1511 6'111111
+ attribute \src "ls180.v:5526.3-5526.58"
+ memwr \mem $1$memwr$\mem$ls180.v:5526$8_ADDR[5:0]$1512 $1$memwr$\mem$ls180.v:5526$8_DATA[63:0]$1513 $1$memwr$\mem$ls180.v:5526$8_EN[63:0]$1514 7'1111111
+ end
+ attribute \src "ls180.v:552.11-552.50"
+ process $proc$ls180.v:552$1832
assign { } { }
- assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1
+ assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000
sync always
- update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0]
sync init
+ update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0]
end
- attribute \src "ls180.v:5519.1-5537.4"
- process $proc$ls180.v:5519$1509
+ attribute \src "ls180.v:5538.1-5556.4"
+ process $proc$ls180.v:5538$1516
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1510 $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534
- assign $0$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1511 $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535
- assign $0$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1512 $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536
- assign $0$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1513 $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537
- assign $0$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1514 $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538
- assign $0$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1515 $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539
- assign $0$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1516 $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540
- assign $0$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1517 $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541
- assign $0$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1518 $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542
- assign $0$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1519 $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543
- assign $0$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1520 $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544
- assign $0$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1521 $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545
- assign $0$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1522 $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546
- assign $0$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1523 $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547
- assign $0$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1524 $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548
- assign $0$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1525 $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549
- assign $0$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1526 $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550
- assign $0$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1527 $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551
- assign $0$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1528 $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552
- assign $0$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1529 $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553
- assign $0$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1530 $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554
- assign $0$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1531 $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555
- assign $0$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1532 $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556
- assign $0$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1533 $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557
+ assign $0$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1517 $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541
+ assign $0$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1518 $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542
+ assign $0$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1519 $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543
+ assign $0$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1520 $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544
+ assign $0$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1521 $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545
+ assign $0$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1522 $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546
+ assign $0$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1523 $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547
+ assign $0$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1524 $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548
+ assign $0$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1525 $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549
+ assign $0$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1526 $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550
+ assign $0$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1527 $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551
+ assign $0$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1528 $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552
+ assign $0$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1529 $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553
+ assign $0$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1530 $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554
+ assign $0$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1531 $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555
+ assign $0$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1532 $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556
+ assign $0$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1533 $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557
+ assign $0$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1534 $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558
+ assign $0$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1535 $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559
+ assign $0$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1536 $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560
+ assign $0$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1537 $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561
+ assign $0$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1538 $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562
+ assign $0$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1539 $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563
+ assign $0$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1540 $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564
assign $0\memadr_1[3:0] \ram_adr
- attribute \src "ls180.v:5520.2-5521.41"
+ attribute \src "ls180.v:5539.2-5540.41"
switch \ram_we [0]
- attribute \src "ls180.v:5520.6-5520.15"
+ attribute \src "ls180.v:5539.6-5539.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 { 56'00000000000000000000000000000000000000000000000000000000 \ram_dat_w [7:0] }
- assign $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 64'0000000000000000000000000000000000000000000000000000000011111111
+ assign $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542 { 56'00000000000000000000000000000000000000000000000000000000 \ram_dat_w [7:0] }
+ assign $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543 64'0000000000000000000000000000000000000000000000000000000011111111
case
- assign $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5522.2-5523.43"
+ attribute \src "ls180.v:5541.2-5542.43"
switch \ram_we [1]
- attribute \src "ls180.v:5522.6-5522.15"
+ attribute \src "ls180.v:5541.6-5541.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 { 48'000000000000000000000000000000000000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx }
- assign $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 64'0000000000000000000000000000000000000000000000001111111100000000
+ assign $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545 { 48'000000000000000000000000000000000000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx }
+ assign $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546 64'0000000000000000000000000000000000000000000000001111111100000000
case
- assign $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5524.2-5525.45"
+ attribute \src "ls180.v:5543.2-5544.45"
switch \ram_we [2]
- attribute \src "ls180.v:5524.6-5524.15"
+ attribute \src "ls180.v:5543.6-5543.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 { 40'0000000000000000000000000000000000000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 64'0000000000000000000000000000000000000000111111110000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548 { 40'0000000000000000000000000000000000000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549 64'0000000000000000000000000000000000000000111111110000000000000000
case
- assign $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5526.2-5527.45"
+ attribute \src "ls180.v:5545.2-5546.45"
switch \ram_we [3]
- attribute \src "ls180.v:5526.6-5526.15"
+ attribute \src "ls180.v:5545.6-5545.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 { 32'00000000000000000000000000000000 \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 64'0000000000000000000000000000000011111111000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551 { 32'00000000000000000000000000000000 \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552 64'0000000000000000000000000000000011111111000000000000000000000000
case
- assign $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5528.2-5529.45"
+ attribute \src "ls180.v:5547.2-5548.45"
switch \ram_we [4]
- attribute \src "ls180.v:5528.6-5528.15"
+ attribute \src "ls180.v:5547.6-5547.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 { 24'000000000000000000000000 \ram_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 64'0000000000000000000000001111111100000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554 { 24'000000000000000000000000 \ram_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555 64'0000000000000000000000001111111100000000000000000000000000000000
case
- assign $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5530.2-5531.45"
+ attribute \src "ls180.v:5549.2-5550.45"
switch \ram_we [5]
- attribute \src "ls180.v:5530.6-5530.15"
+ attribute \src "ls180.v:5549.6-5549.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 { 16'0000000000000000 \ram_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 64'0000000000000000111111110000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557 { 16'0000000000000000 \ram_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558 64'0000000000000000111111110000000000000000000000000000000000000000
case
- assign $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5532.2-5533.45"
+ attribute \src "ls180.v:5551.2-5552.45"
switch \ram_we [6]
- attribute \src "ls180.v:5532.6-5532.15"
+ attribute \src "ls180.v:5551.6-5551.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 { 8'00000000 \ram_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 64'0000000011111111000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560 { 8'00000000 \ram_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561 64'0000000011111111000000000000000000000000000000000000000000000000
case
- assign $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "ls180.v:5534.2-5535.45"
+ attribute \src "ls180.v:5553.2-5554.45"
switch \ram_we [7]
- attribute \src "ls180.v:5534.6-5534.15"
+ attribute \src "ls180.v:5553.6-5553.15"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 \ram_adr
- assign $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 { \ram_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
- assign $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 64'1111111100000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562 \ram_adr
+ assign $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563 { \ram_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
+ assign $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564 64'1111111100000000000000000000000000000000000000000000000000000000
case
- assign $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 4'xxxx
- assign $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562 4'xxxx
+ assign $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync posedge \sys_clk_1
update \memadr_1 $0\memadr_1[3:0]
- update $memwr$\mem_1$ls180.v:5521$9_ADDR $0$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1510
- update $memwr$\mem_1$ls180.v:5521$9_DATA $0$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1511
- update $memwr$\mem_1$ls180.v:5521$9_EN $0$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1512
- update $memwr$\mem_1$ls180.v:5523$10_ADDR $0$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1513
- update $memwr$\mem_1$ls180.v:5523$10_DATA $0$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1514
- update $memwr$\mem_1$ls180.v:5523$10_EN $0$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1515
- update $memwr$\mem_1$ls180.v:5525$11_ADDR $0$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1516
- update $memwr$\mem_1$ls180.v:5525$11_DATA $0$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1517
- update $memwr$\mem_1$ls180.v:5525$11_EN $0$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1518
- update $memwr$\mem_1$ls180.v:5527$12_ADDR $0$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1519
- update $memwr$\mem_1$ls180.v:5527$12_DATA $0$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1520
- update $memwr$\mem_1$ls180.v:5527$12_EN $0$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1521
- update $memwr$\mem_1$ls180.v:5529$13_ADDR $0$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1522
- update $memwr$\mem_1$ls180.v:5529$13_DATA $0$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1523
- update $memwr$\mem_1$ls180.v:5529$13_EN $0$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1524
- update $memwr$\mem_1$ls180.v:5531$14_ADDR $0$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1525
- update $memwr$\mem_1$ls180.v:5531$14_DATA $0$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1526
- update $memwr$\mem_1$ls180.v:5531$14_EN $0$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1527
- update $memwr$\mem_1$ls180.v:5533$15_ADDR $0$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1528
- update $memwr$\mem_1$ls180.v:5533$15_DATA $0$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1529
- update $memwr$\mem_1$ls180.v:5533$15_EN $0$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1530
- update $memwr$\mem_1$ls180.v:5535$16_ADDR $0$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1531
- update $memwr$\mem_1$ls180.v:5535$16_DATA $0$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1532
- update $memwr$\mem_1$ls180.v:5535$16_EN $0$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1533
- attribute \src "ls180.v:5521.3-5521.40"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 0'
- attribute \src "ls180.v:5523.3-5523.42"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 1'1
- attribute \src "ls180.v:5525.3-5525.44"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 2'11
- attribute \src "ls180.v:5527.3-5527.44"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 3'111
- attribute \src "ls180.v:5529.3-5529.44"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 4'1111
- attribute \src "ls180.v:5531.3-5531.44"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 5'11111
- attribute \src "ls180.v:5533.3-5533.44"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 6'111111
- attribute \src "ls180.v:5535.3-5535.44"
- memwr \mem_1 $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 7'1111111
- end
- attribute \src "ls180.v:552.32-552.71"
- process $proc$ls180.v:552$1827
+ update $memwr$\mem_1$ls180.v:5540$9_ADDR $0$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1517
+ update $memwr$\mem_1$ls180.v:5540$9_DATA $0$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1518
+ update $memwr$\mem_1$ls180.v:5540$9_EN $0$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1519
+ update $memwr$\mem_1$ls180.v:5542$10_ADDR $0$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1520
+ update $memwr$\mem_1$ls180.v:5542$10_DATA $0$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1521
+ update $memwr$\mem_1$ls180.v:5542$10_EN $0$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1522
+ update $memwr$\mem_1$ls180.v:5544$11_ADDR $0$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1523
+ update $memwr$\mem_1$ls180.v:5544$11_DATA $0$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1524
+ update $memwr$\mem_1$ls180.v:5544$11_EN $0$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1525
+ update $memwr$\mem_1$ls180.v:5546$12_ADDR $0$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1526
+ update $memwr$\mem_1$ls180.v:5546$12_DATA $0$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1527
+ update $memwr$\mem_1$ls180.v:5546$12_EN $0$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1528
+ update $memwr$\mem_1$ls180.v:5548$13_ADDR $0$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1529
+ update $memwr$\mem_1$ls180.v:5548$13_DATA $0$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1530
+ update $memwr$\mem_1$ls180.v:5548$13_EN $0$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1531
+ update $memwr$\mem_1$ls180.v:5550$14_ADDR $0$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1532
+ update $memwr$\mem_1$ls180.v:5550$14_DATA $0$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1533
+ update $memwr$\mem_1$ls180.v:5550$14_EN $0$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1534
+ update $memwr$\mem_1$ls180.v:5552$15_ADDR $0$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1535
+ update $memwr$\mem_1$ls180.v:5552$15_DATA $0$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1536
+ update $memwr$\mem_1$ls180.v:5552$15_EN $0$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1537
+ update $memwr$\mem_1$ls180.v:5554$16_ADDR $0$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1538
+ update $memwr$\mem_1$ls180.v:5554$16_DATA $0$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1539
+ update $memwr$\mem_1$ls180.v:5554$16_EN $0$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1540
+ attribute \src "ls180.v:5540.3-5540.40"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5540$9_ADDR[3:0]$1541 $1$memwr$\mem_1$ls180.v:5540$9_DATA[63:0]$1542 $1$memwr$\mem_1$ls180.v:5540$9_EN[63:0]$1543 0'
+ attribute \src "ls180.v:5542.3-5542.42"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5542$10_ADDR[3:0]$1544 $1$memwr$\mem_1$ls180.v:5542$10_DATA[63:0]$1545 $1$memwr$\mem_1$ls180.v:5542$10_EN[63:0]$1546 1'1
+ attribute \src "ls180.v:5544.3-5544.44"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5544$11_ADDR[3:0]$1547 $1$memwr$\mem_1$ls180.v:5544$11_DATA[63:0]$1548 $1$memwr$\mem_1$ls180.v:5544$11_EN[63:0]$1549 2'11
+ attribute \src "ls180.v:5546.3-5546.44"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5546$12_ADDR[3:0]$1550 $1$memwr$\mem_1$ls180.v:5546$12_DATA[63:0]$1551 $1$memwr$\mem_1$ls180.v:5546$12_EN[63:0]$1552 3'111
+ attribute \src "ls180.v:5548.3-5548.44"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5548$13_ADDR[3:0]$1553 $1$memwr$\mem_1$ls180.v:5548$13_DATA[63:0]$1554 $1$memwr$\mem_1$ls180.v:5548$13_EN[63:0]$1555 4'1111
+ attribute \src "ls180.v:5550.3-5550.44"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5550$14_ADDR[3:0]$1556 $1$memwr$\mem_1$ls180.v:5550$14_DATA[63:0]$1557 $1$memwr$\mem_1$ls180.v:5550$14_EN[63:0]$1558 5'11111
+ attribute \src "ls180.v:5552.3-5552.44"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5552$15_ADDR[3:0]$1559 $1$memwr$\mem_1$ls180.v:5552$15_DATA[63:0]$1560 $1$memwr$\mem_1$ls180.v:5552$15_EN[63:0]$1561 6'111111
+ attribute \src "ls180.v:5554.3-5554.44"
+ memwr \mem_1 $1$memwr$\mem_1$ls180.v:5554$16_ADDR[3:0]$1562 $1$memwr$\mem_1$ls180.v:5554$16_DATA[63:0]$1563 $1$memwr$\mem_1$ls180.v:5554$16_EN[63:0]$1564 7'1111111
+ end
+ attribute \src "ls180.v:554.32-554.70"
+ process $proc$ls180.v:554$1833
+ assign { } { }
+ assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1
+ sync always
+ update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0]
+ sync init
+ end
+ attribute \src "ls180.v:556.32-556.71"
+ process $proc$ls180.v:556$1834
assign { } { }
assign $0\sdram_bankmachine1_trascon_ready[0:0] 1'1
sync always
update \sdram_bankmachine1_trascon_ready $0\sdram_bankmachine1_trascon_ready[0:0]
sync init
end
- attribute \src "ls180.v:5547.1-5551.4"
- process $proc$ls180.v:5547$1559
+ attribute \src "ls180.v:5566.1-5570.4"
+ process $proc$ls180.v:5566$1566
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1560 $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563
- assign $0$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1561 $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564
- assign $0$memwr$\storage$ls180.v:5549$17_EN[24:0]$1562 $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565
- assign $0\memdat[24:0] $memrd$\storage$ls180.v:5550$1566_DATA
- attribute \src "ls180.v:5548.2-5549.119"
+ assign $0$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1567 $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570
+ assign $0$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1568 $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571
+ assign $0$memwr$\storage$ls180.v:5568$17_EN[24:0]$1569 $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572
+ assign $0\memdat[24:0] $memrd$\storage$ls180.v:5569$1573_DATA
+ attribute \src "ls180.v:5567.2-5568.119"
switch \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:5548.6-5548.55"
+ attribute \src "ls180.v:5567.6-5567.55"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
- assign $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
- assign $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 25'1111111111111111111111111
+ assign $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr
+ assign $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w
+ assign $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572 25'1111111111111111111111111
case
- assign $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 3'xxx
- assign $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 25'0000000000000000000000000
+ assign $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570 3'xxx
+ assign $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572 25'0000000000000000000000000
end
sync posedge \sys_clk_1
update \memdat $0\memdat[24:0]
- update $memwr$\storage$ls180.v:5549$17_ADDR $0$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1560
- update $memwr$\storage$ls180.v:5549$17_DATA $0$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1561
- update $memwr$\storage$ls180.v:5549$17_EN $0$memwr$\storage$ls180.v:5549$17_EN[24:0]$1562
- attribute \src "ls180.v:5549.3-5549.118"
- memwr \storage $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 0'
- end
- attribute \src "ls180.v:5553.1-5554.4"
- process $proc$ls180.v:5553$1567
+ update $memwr$\storage$ls180.v:5568$17_ADDR $0$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1567
+ update $memwr$\storage$ls180.v:5568$17_DATA $0$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1568
+ update $memwr$\storage$ls180.v:5568$17_EN $0$memwr$\storage$ls180.v:5568$17_EN[24:0]$1569
+ attribute \src "ls180.v:5568.3-5568.118"
+ memwr \storage $1$memwr$\storage$ls180.v:5568$17_ADDR[2:0]$1570 $1$memwr$\storage$ls180.v:5568$17_DATA[24:0]$1571 $1$memwr$\storage$ls180.v:5568$17_EN[24:0]$1572 0'
+ end
+ attribute \src "ls180.v:5572.1-5573.4"
+ process $proc$ls180.v:5572$1574
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:5561.1-5565.4"
- process $proc$ls180.v:5561$1569
+ attribute \src "ls180.v:5580.1-5584.4"
+ process $proc$ls180.v:5580$1576
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1570 $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573
- assign $0$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1571 $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574
- assign $0$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1572 $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575
- assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5564$1576_DATA
- attribute \src "ls180.v:5562.2-5563.121"
+ assign $0$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1577 $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580
+ assign $0$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1578 $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581
+ assign $0$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1579 $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582
+ assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5583$1583_DATA
+ attribute \src "ls180.v:5581.2-5582.121"
switch \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:5562.6-5562.55"
+ attribute \src "ls180.v:5581.6-5581.55"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
- assign $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
- assign $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 25'1111111111111111111111111
+ assign $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr
+ assign $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w
+ assign $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582 25'1111111111111111111111111
case
- assign $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 3'xxx
- assign $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 25'0000000000000000000000000
+ assign $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580 3'xxx
+ assign $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582 25'0000000000000000000000000
end
sync posedge \sys_clk_1
update \memdat_1 $0\memdat_1[24:0]
- update $memwr$\storage_1$ls180.v:5563$18_ADDR $0$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1570
- update $memwr$\storage_1$ls180.v:5563$18_DATA $0$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1571
- update $memwr$\storage_1$ls180.v:5563$18_EN $0$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1572
- attribute \src "ls180.v:5563.3-5563.120"
- memwr \storage_1 $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 0'
- end
- attribute \src "ls180.v:5567.1-5568.4"
- process $proc$ls180.v:5567$1577
+ update $memwr$\storage_1$ls180.v:5582$18_ADDR $0$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1577
+ update $memwr$\storage_1$ls180.v:5582$18_DATA $0$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1578
+ update $memwr$\storage_1$ls180.v:5582$18_EN $0$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1579
+ attribute \src "ls180.v:5582.3-5582.120"
+ memwr \storage_1 $1$memwr$\storage_1$ls180.v:5582$18_ADDR[2:0]$1580 $1$memwr$\storage_1$ls180.v:5582$18_DATA[24:0]$1581 $1$memwr$\storage_1$ls180.v:5582$18_EN[24:0]$1582 0'
+ end
+ attribute \src "ls180.v:5586.1-5587.4"
+ process $proc$ls180.v:5586$1584
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:5575.1-5579.4"
- process $proc$ls180.v:5575$1579
+ attribute \src "ls180.v:5594.1-5598.4"
+ process $proc$ls180.v:5594$1586
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1580 $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583
- assign $0$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1581 $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584
- assign $0$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1582 $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585
- assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5578$1586_DATA
- attribute \src "ls180.v:5576.2-5577.121"
+ assign $0$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1587 $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590
+ assign $0$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1588 $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591
+ assign $0$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1589 $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592
+ assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5597$1593_DATA
+ attribute \src "ls180.v:5595.2-5596.121"
switch \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:5576.6-5576.55"
+ attribute \src "ls180.v:5595.6-5595.55"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
- assign $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
- assign $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 25'1111111111111111111111111
+ assign $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr
+ assign $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w
+ assign $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592 25'1111111111111111111111111
case
- assign $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 3'xxx
- assign $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 25'0000000000000000000000000
+ assign $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590 3'xxx
+ assign $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592 25'0000000000000000000000000
end
sync posedge \sys_clk_1
update \memdat_2 $0\memdat_2[24:0]
- update $memwr$\storage_2$ls180.v:5577$19_ADDR $0$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1580
- update $memwr$\storage_2$ls180.v:5577$19_DATA $0$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1581
- update $memwr$\storage_2$ls180.v:5577$19_EN $0$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1582
- attribute \src "ls180.v:5577.3-5577.120"
- memwr \storage_2 $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 0'
- end
- attribute \src "ls180.v:558.5-558.46"
- process $proc$ls180.v:558$1828
- assign { } { }
- assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0]
- end
- attribute \src "ls180.v:5581.1-5582.4"
- process $proc$ls180.v:5581$1587
+ update $memwr$\storage_2$ls180.v:5596$19_ADDR $0$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1587
+ update $memwr$\storage_2$ls180.v:5596$19_DATA $0$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1588
+ update $memwr$\storage_2$ls180.v:5596$19_EN $0$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1589
+ attribute \src "ls180.v:5596.3-5596.120"
+ memwr \storage_2 $1$memwr$\storage_2$ls180.v:5596$19_ADDR[2:0]$1590 $1$memwr$\storage_2$ls180.v:5596$19_DATA[24:0]$1591 $1$memwr$\storage_2$ls180.v:5596$19_EN[24:0]$1592 0'
+ end
+ attribute \src "ls180.v:5600.1-5601.4"
+ process $proc$ls180.v:5600$1594
sync posedge \sys_clk_1
end
- attribute \src "ls180.v:5589.1-5593.4"
- process $proc$ls180.v:5589$1589
+ attribute \src "ls180.v:5608.1-5612.4"
+ process $proc$ls180.v:5608$1596
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1590 $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593
- assign $0$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1591 $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594
- assign $0$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1592 $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595
- assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5592$1596_DATA
- attribute \src "ls180.v:5590.2-5591.121"
+ assign $0$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1597 $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600
+ assign $0$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1598 $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601
+ assign $0$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1599 $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602
+ assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5611$1603_DATA
+ attribute \src "ls180.v:5609.2-5610.121"
switch \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we
- attribute \src "ls180.v:5590.6-5590.55"
+ attribute \src "ls180.v:5609.6-5609.55"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
- assign $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
- assign $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 25'1111111111111111111111111
+ assign $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr
+ assign $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w
+ assign $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602 25'1111111111111111111111111
case
- assign $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 3'xxx
- assign $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 25'xxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 25'0000000000000000000000000
+ assign $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600 3'xxx
+ assign $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601 25'xxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602 25'0000000000000000000000000
end
sync posedge \sys_clk_1
update \memdat_3 $0\memdat_3[24:0]
- update $memwr$\storage_3$ls180.v:5591$20_ADDR $0$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1590
- update $memwr$\storage_3$ls180.v:5591$20_DATA $0$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1591
- update $memwr$\storage_3$ls180.v:5591$20_EN $0$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1592
- attribute \src "ls180.v:5591.3-5591.120"
- memwr \storage_3 $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 0'
+ update $memwr$\storage_3$ls180.v:5610$20_ADDR $0$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1597
+ update $memwr$\storage_3$ls180.v:5610$20_DATA $0$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1598
+ update $memwr$\storage_3$ls180.v:5610$20_EN $0$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1599
+ attribute \src "ls180.v:5610.3-5610.120"
+ memwr \storage_3 $1$memwr$\storage_3$ls180.v:5610$20_ADDR[2:0]$1600 $1$memwr$\storage_3$ls180.v:5610$20_DATA[24:0]$1601 $1$memwr$\storage_3$ls180.v:5610$20_EN[24:0]$1602 0'
+ end
+ attribute \src "ls180.v:5614.1-5615.4"
+ process $proc$ls180.v:5614$1604
+ sync posedge \sys_clk_1
end
- attribute \src "ls180.v:559.5-559.46"
- process $proc$ls180.v:559$1829
+ attribute \src "ls180.v:562.5-562.46"
+ process $proc$ls180.v:562$1835
assign { } { }
- assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0
+ assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0
sync always
sync init
- update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0]
- end
- attribute \src "ls180.v:5595.1-5596.4"
- process $proc$ls180.v:5595$1597
- sync posedge \sys_clk_1
+ update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:5604.1-5608.4"
- process $proc$ls180.v:5604$1599
+ attribute \src "ls180.v:5623.1-5627.4"
+ process $proc$ls180.v:5623$1606
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1600 $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603
- assign $0$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1601 $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604
- assign $0$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1602 $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605
- assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5607$1606_DATA
- attribute \src "ls180.v:5605.2-5606.57"
+ assign $0$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1607 $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610
+ assign $0$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1608 $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611
+ assign $0$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1609 $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612
+ assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5626$1613_DATA
+ attribute \src "ls180.v:5624.2-5625.57"
switch \tx_fifo_wrport_we
- attribute \src "ls180.v:5605.6-5605.23"
+ attribute \src "ls180.v:5624.6-5624.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 \tx_fifo_wrport_adr
- assign $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 \tx_fifo_wrport_dat_w
- assign $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 10'1111111111
+ assign $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610 \tx_fifo_wrport_adr
+ assign $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611 \tx_fifo_wrport_dat_w
+ assign $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612 10'1111111111
case
- assign $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 4'xxxx
- assign $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 10'xxxxxxxxxx
- assign $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 10'0000000000
+ assign $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610 4'xxxx
+ assign $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611 10'xxxxxxxxxx
+ assign $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612 10'0000000000
end
sync posedge \sys_clk_1
update \memdat_4 $0\memdat_4[9:0]
- update $memwr$\storage_4$ls180.v:5606$21_ADDR $0$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1600
- update $memwr$\storage_4$ls180.v:5606$21_DATA $0$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1601
- update $memwr$\storage_4$ls180.v:5606$21_EN $0$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1602
- attribute \src "ls180.v:5606.3-5606.56"
- memwr \storage_4 $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 0'
- end
- attribute \src "ls180.v:561.5-561.42"
- process $proc$ls180.v:561$1830
- assign { } { }
- assign $1\sdram_bankmachine2_refresh_gnt[0:0] 1'0
- sync always
- sync init
- update \sdram_bankmachine2_refresh_gnt $1\sdram_bankmachine2_refresh_gnt[0:0]
- end
- attribute \src "ls180.v:5610.1-5613.4"
- process $proc$ls180.v:5610$1607
+ update $memwr$\storage_4$ls180.v:5625$21_ADDR $0$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1607
+ update $memwr$\storage_4$ls180.v:5625$21_DATA $0$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1608
+ update $memwr$\storage_4$ls180.v:5625$21_EN $0$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1609
+ attribute \src "ls180.v:5625.3-5625.56"
+ memwr \storage_4 $1$memwr$\storage_4$ls180.v:5625$21_ADDR[3:0]$1610 $1$memwr$\storage_4$ls180.v:5625$21_DATA[9:0]$1611 $1$memwr$\storage_4$ls180.v:5625$21_EN[9:0]$1612 0'
+ end
+ attribute \src "ls180.v:5629.1-5632.4"
+ process $proc$ls180.v:5629$1614
assign $0\memdat_5[9:0] \memdat_5
- attribute \src "ls180.v:5611.2-5612.45"
+ attribute \src "ls180.v:5630.2-5631.45"
switch \tx_fifo_rdport_re
- attribute \src "ls180.v:5611.6-5611.23"
+ attribute \src "ls180.v:5630.6-5630.23"
case 1'1
- assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5612$1608_DATA
+ assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5631$1615_DATA
case
end
sync posedge \sys_clk_1
update \memdat_5 $0\memdat_5[9:0]
end
- attribute \src "ls180.v:562.5-562.40"
- process $proc$ls180.v:562$1831
+ attribute \src "ls180.v:563.5-563.46"
+ process $proc$ls180.v:563$1836
assign { } { }
- assign $1\sdram_bankmachine2_cmd_valid[0:0] 1'0
+ assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0
sync always
sync init
- update \sdram_bankmachine2_cmd_valid $1\sdram_bankmachine2_cmd_valid[0:0]
+ update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:5621.1-5625.4"
- process $proc$ls180.v:5621$1609
+ attribute \src "ls180.v:5640.1-5644.4"
+ process $proc$ls180.v:5640$1616
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1610 $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613
- assign $0$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1611 $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614
- assign $0$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1612 $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615
- assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5624$1616_DATA
- attribute \src "ls180.v:5622.2-5623.57"
+ assign $0$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1617 $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620
+ assign $0$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1618 $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621
+ assign $0$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1619 $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622
+ assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5643$1623_DATA
+ attribute \src "ls180.v:5641.2-5642.57"
switch \rx_fifo_wrport_we
- attribute \src "ls180.v:5622.6-5622.23"
+ attribute \src "ls180.v:5641.6-5641.23"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 \rx_fifo_wrport_adr
- assign $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 \rx_fifo_wrport_dat_w
- assign $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 10'1111111111
+ assign $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620 \rx_fifo_wrport_adr
+ assign $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621 \rx_fifo_wrport_dat_w
+ assign $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622 10'1111111111
case
- assign $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 4'xxxx
- assign $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 10'xxxxxxxxxx
- assign $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 10'0000000000
+ assign $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620 4'xxxx
+ assign $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621 10'xxxxxxxxxx
+ assign $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622 10'0000000000
end
sync posedge \sys_clk_1
update \memdat_6 $0\memdat_6[9:0]
- update $memwr$\storage_5$ls180.v:5623$22_ADDR $0$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1610
- update $memwr$\storage_5$ls180.v:5623$22_DATA $0$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1611
- update $memwr$\storage_5$ls180.v:5623$22_EN $0$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1612
- attribute \src "ls180.v:5623.3-5623.56"
- memwr \storage_5 $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 0'
- end
- attribute \src "ls180.v:5627.1-5630.4"
- process $proc$ls180.v:5627$1617
+ update $memwr$\storage_5$ls180.v:5642$22_ADDR $0$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1617
+ update $memwr$\storage_5$ls180.v:5642$22_DATA $0$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1618
+ update $memwr$\storage_5$ls180.v:5642$22_EN $0$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1619
+ attribute \src "ls180.v:5642.3-5642.56"
+ memwr \storage_5 $1$memwr$\storage_5$ls180.v:5642$22_ADDR[3:0]$1620 $1$memwr$\storage_5$ls180.v:5642$22_DATA[9:0]$1621 $1$memwr$\storage_5$ls180.v:5642$22_EN[9:0]$1622 0'
+ end
+ attribute \src "ls180.v:5646.1-5649.4"
+ process $proc$ls180.v:5646$1624
assign $0\memdat_7[9:0] \memdat_7
- attribute \src "ls180.v:5628.2-5629.45"
+ attribute \src "ls180.v:5647.2-5648.45"
switch \rx_fifo_rdport_re
- attribute \src "ls180.v:5628.6-5628.23"
+ attribute \src "ls180.v:5647.6-5647.23"
case 1'1
- assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5629$1618_DATA
+ assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5648$1625_DATA
case
end
sync posedge \sys_clk_1
update \memdat_7 $0\memdat_7[9:0]
end
- attribute \src "ls180.v:563.5-563.40"
- process $proc$ls180.v:563$1832
+ attribute \src "ls180.v:565.5-565.42"
+ process $proc$ls180.v:565$1837
+ assign { } { }
+ assign $1\sdram_bankmachine2_refresh_gnt[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine2_refresh_gnt $1\sdram_bankmachine2_refresh_gnt[0:0]
+ end
+ attribute \src "ls180.v:566.5-566.40"
+ process $proc$ls180.v:566$1838
+ assign { } { }
+ assign $1\sdram_bankmachine2_cmd_valid[0:0] 1'0
+ sync always
+ sync init
+ update \sdram_bankmachine2_cmd_valid $1\sdram_bankmachine2_cmd_valid[0:0]
+ end
+ attribute \src "ls180.v:567.5-567.40"
+ process $proc$ls180.v:567$1839
assign { } { }
assign $1\sdram_bankmachine2_cmd_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_ready $1\sdram_bankmachine2_cmd_ready[0:0]
end
- attribute \src "ls180.v:564.12-564.52"
- process $proc$ls180.v:564$1833
+ attribute \src "ls180.v:568.12-568.52"
+ process $proc$ls180.v:568$1840
assign { } { }
assign $1\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
update \sdram_bankmachine2_cmd_payload_a $1\sdram_bankmachine2_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:566.5-566.46"
- process $proc$ls180.v:566$1834
+ attribute \src "ls180.v:570.5-570.46"
+ process $proc$ls180.v:570$1841
assign { } { }
assign $1\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_payload_cas $1\sdram_bankmachine2_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:567.5-567.46"
- process $proc$ls180.v:567$1835
+ attribute \src "ls180.v:571.5-571.46"
+ process $proc$ls180.v:571$1842
assign { } { }
assign $1\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_payload_ras $1\sdram_bankmachine2_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:568.5-568.45"
- process $proc$ls180.v:568$1836
+ attribute \src "ls180.v:572.5-572.45"
+ process $proc$ls180.v:572$1843
assign { } { }
assign $1\sdram_bankmachine2_cmd_payload_we[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_payload_we $1\sdram_bankmachine2_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:569.5-569.49"
- process $proc$ls180.v:569$1837
+ attribute \src "ls180.v:573.5-573.49"
+ process $proc$ls180.v:573$1844
assign { } { }
assign $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_payload_is_cmd $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:570.5-570.50"
- process $proc$ls180.v:570$1838
+ attribute \src "ls180.v:574.5-574.50"
+ process $proc$ls180.v:574$1845
assign { } { }
assign $1\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_payload_is_read $1\sdram_bankmachine2_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:571.5-571.51"
- process $proc$ls180.v:571$1839
+ attribute \src "ls180.v:575.5-575.51"
+ process $proc$ls180.v:575$1846
assign { } { }
assign $1\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_payload_is_write $1\sdram_bankmachine2_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:572.5-572.45"
- process $proc$ls180.v:572$1840
+ attribute \src "ls180.v:576.5-576.45"
+ process $proc$ls180.v:576$1847
assign { } { }
assign $1\sdram_bankmachine2_auto_precharge[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_auto_precharge $1\sdram_bankmachine2_auto_precharge[0:0]
end
- attribute \src "ls180.v:575.5-575.62"
- process $proc$ls180.v:575$1841
+ attribute \src "ls180.v:579.5-579.62"
+ process $proc$ls180.v:579$1848
assign { } { }
assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:576.5-576.61"
- process $proc$ls180.v:576$1842
+ attribute \src "ls180.v:580.5-580.61"
+ process $proc$ls180.v:580$1849
assign { } { }
assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:591.11-591.63"
- process $proc$ls180.v:591$1843
+ attribute \src "ls180.v:595.11-595.63"
+ process $proc$ls180.v:595$1850
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_lookahead_level $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:592.5-592.59"
- process $proc$ls180.v:592$1844
+ attribute \src "ls180.v:596.5-596.59"
+ process $proc$ls180.v:596$1851
assign { } { }
assign $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \sdram_bankmachine2_cmd_buffer_lookahead_replace $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0]
sync init
end
- attribute \src "ls180.v:593.11-593.65"
- process $proc$ls180.v:593$1845
+ attribute \src "ls180.v:597.11-597.65"
+ process $proc$ls180.v:597$1852
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_lookahead_produce $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:594.11-594.65"
- process $proc$ls180.v:594$1846
+ attribute \src "ls180.v:598.11-598.65"
+ process $proc$ls180.v:598$1853
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_lookahead_consume $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:595.11-595.68"
- process $proc$ls180.v:595$1847
+ attribute \src "ls180.v:599.11-599.68"
+ process $proc$ls180.v:599$1854
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:616.5-616.54"
- process $proc$ls180.v:616$1848
+ attribute \src "ls180.v:620.5-620.54"
+ process $proc$ls180.v:620$1855
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_source_valid $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:618.5-618.54"
- process $proc$ls180.v:618$1849
+ attribute \src "ls180.v:622.5-622.54"
+ process $proc$ls180.v:622$1856
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_source_first $1\sdram_bankmachine2_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:619.5-619.53"
- process $proc$ls180.v:619$1850
+ attribute \src "ls180.v:623.5-623.53"
+ process $proc$ls180.v:623$1857
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_source_last $1\sdram_bankmachine2_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:62.11-62.47"
- process $proc$ls180.v:62$1626
- assign { } { }
- assign $0\libresocsim_libresoc_dbus_cti[2:0] 3'000
- sync always
- update \libresocsim_libresoc_dbus_cti $0\libresocsim_libresoc_dbus_cti[2:0]
- sync init
- end
- attribute \src "ls180.v:620.5-620.59"
- process $proc$ls180.v:620$1851
+ attribute \src "ls180.v:624.5-624.59"
+ process $proc$ls180.v:624$1858
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_source_payload_we $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:621.12-621.69"
- process $proc$ls180.v:621$1852
+ attribute \src "ls180.v:625.12-625.69"
+ process $proc$ls180.v:625$1859
assign { } { }
assign $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \sdram_bankmachine2_cmd_buffer_source_payload_addr $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:622.12-622.42"
- process $proc$ls180.v:622$1853
+ attribute \src "ls180.v:626.12-626.42"
+ process $proc$ls180.v:626$1860
assign { } { }
assign $1\sdram_bankmachine2_row[12:0] 13'0000000000000
sync always
sync init
update \sdram_bankmachine2_row $1\sdram_bankmachine2_row[12:0]
end
- attribute \src "ls180.v:623.5-623.41"
- process $proc$ls180.v:623$1854
+ attribute \src "ls180.v:627.5-627.41"
+ process $proc$ls180.v:627$1861
assign { } { }
assign $1\sdram_bankmachine2_row_opened[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_row_opened $1\sdram_bankmachine2_row_opened[0:0]
end
- attribute \src "ls180.v:625.5-625.39"
- process $proc$ls180.v:625$1855
+ attribute \src "ls180.v:629.5-629.39"
+ process $proc$ls180.v:629$1862
assign { } { }
assign $1\sdram_bankmachine2_row_open[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_row_open $1\sdram_bankmachine2_row_open[0:0]
end
- attribute \src "ls180.v:626.5-626.40"
- process $proc$ls180.v:626$1856
+ attribute \src "ls180.v:630.5-630.40"
+ process $proc$ls180.v:630$1863
assign { } { }
assign $1\sdram_bankmachine2_row_close[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_row_close $1\sdram_bankmachine2_row_close[0:0]
end
- attribute \src "ls180.v:627.5-627.49"
- process $proc$ls180.v:627$1857
+ attribute \src "ls180.v:631.5-631.49"
+ process $proc$ls180.v:631$1864
assign { } { }
assign $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_row_col_n_addr_sel $1\sdram_bankmachine2_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:629.32-629.71"
- process $proc$ls180.v:629$1858
+ attribute \src "ls180.v:633.32-633.71"
+ process $proc$ls180.v:633$1865
assign { } { }
assign $1\sdram_bankmachine2_twtpcon_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine2_twtpcon_ready $1\sdram_bankmachine2_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:63.11-63.47"
- process $proc$ls180.v:63$1627
- assign { } { }
- assign $0\libresocsim_libresoc_dbus_bte[1:0] 2'00
- sync always
- update \libresocsim_libresoc_dbus_bte $0\libresocsim_libresoc_dbus_bte[1:0]
- sync init
- end
- attribute \src "ls180.v:630.11-630.50"
- process $proc$ls180.v:630$1859
+ attribute \src "ls180.v:634.11-634.50"
+ process $proc$ls180.v:634$1866
assign { } { }
assign $1\sdram_bankmachine2_twtpcon_count[2:0] 3'000
sync always
sync init
update \sdram_bankmachine2_twtpcon_count $1\sdram_bankmachine2_twtpcon_count[2:0]
end
- attribute \src "ls180.v:632.32-632.70"
- process $proc$ls180.v:632$1860
+ attribute \src "ls180.v:636.32-636.70"
+ process $proc$ls180.v:636$1867
assign { } { }
assign $0\sdram_bankmachine2_trccon_ready[0:0] 1'1
sync always
update \sdram_bankmachine2_trccon_ready $0\sdram_bankmachine2_trccon_ready[0:0]
sync init
end
- attribute \src "ls180.v:634.32-634.71"
- process $proc$ls180.v:634$1861
+ attribute \src "ls180.v:638.32-638.71"
+ process $proc$ls180.v:638$1868
assign { } { }
assign $0\sdram_bankmachine2_trascon_ready[0:0] 1'1
sync always
update \sdram_bankmachine2_trascon_ready $0\sdram_bankmachine2_trascon_ready[0:0]
sync init
end
- attribute \src "ls180.v:640.5-640.46"
- process $proc$ls180.v:640$1862
+ attribute \src "ls180.v:64.11-64.47"
+ process $proc$ls180.v:64$1633
+ assign { } { }
+ assign $0\libresocsim_libresoc_dbus_cti[2:0] 3'000
+ sync always
+ update \libresocsim_libresoc_dbus_cti $0\libresocsim_libresoc_dbus_cti[2:0]
+ sync init
+ end
+ attribute \src "ls180.v:644.5-644.46"
+ process $proc$ls180.v:644$1869
assign { } { }
assign $1\sdram_bankmachine3_req_wdata_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_req_wdata_ready $1\sdram_bankmachine3_req_wdata_ready[0:0]
end
- attribute \src "ls180.v:641.5-641.46"
- process $proc$ls180.v:641$1863
+ attribute \src "ls180.v:645.5-645.46"
+ process $proc$ls180.v:645$1870
assign { } { }
assign $1\sdram_bankmachine3_req_rdata_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_req_rdata_valid $1\sdram_bankmachine3_req_rdata_valid[0:0]
end
- attribute \src "ls180.v:643.5-643.42"
- process $proc$ls180.v:643$1864
+ attribute \src "ls180.v:647.5-647.42"
+ process $proc$ls180.v:647$1871
assign { } { }
assign $1\sdram_bankmachine3_refresh_gnt[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_refresh_gnt $1\sdram_bankmachine3_refresh_gnt[0:0]
end
- attribute \src "ls180.v:644.5-644.40"
- process $proc$ls180.v:644$1865
+ attribute \src "ls180.v:648.5-648.40"
+ process $proc$ls180.v:648$1872
assign { } { }
assign $1\sdram_bankmachine3_cmd_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_valid $1\sdram_bankmachine3_cmd_valid[0:0]
end
- attribute \src "ls180.v:645.5-645.40"
- process $proc$ls180.v:645$1866
+ attribute \src "ls180.v:649.5-649.40"
+ process $proc$ls180.v:649$1873
assign { } { }
assign $1\sdram_bankmachine3_cmd_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_ready $1\sdram_bankmachine3_cmd_ready[0:0]
end
- attribute \src "ls180.v:646.12-646.52"
- process $proc$ls180.v:646$1867
+ attribute \src "ls180.v:65.11-65.47"
+ process $proc$ls180.v:65$1634
+ assign { } { }
+ assign $0\libresocsim_libresoc_dbus_bte[1:0] 2'00
+ sync always
+ update \libresocsim_libresoc_dbus_bte $0\libresocsim_libresoc_dbus_bte[1:0]
+ sync init
+ end
+ attribute \src "ls180.v:650.12-650.52"
+ process $proc$ls180.v:650$1874
assign { } { }
assign $1\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
sync always
sync init
update \sdram_bankmachine3_cmd_payload_a $1\sdram_bankmachine3_cmd_payload_a[12:0]
end
- attribute \src "ls180.v:648.5-648.46"
- process $proc$ls180.v:648$1868
+ attribute \src "ls180.v:652.5-652.46"
+ process $proc$ls180.v:652$1875
assign { } { }
assign $1\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_payload_cas $1\sdram_bankmachine3_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:649.5-649.46"
- process $proc$ls180.v:649$1869
+ attribute \src "ls180.v:653.5-653.46"
+ process $proc$ls180.v:653$1876
assign { } { }
assign $1\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_payload_ras $1\sdram_bankmachine3_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:650.5-650.45"
- process $proc$ls180.v:650$1870
+ attribute \src "ls180.v:654.5-654.45"
+ process $proc$ls180.v:654$1877
assign { } { }
assign $1\sdram_bankmachine3_cmd_payload_we[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_payload_we $1\sdram_bankmachine3_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:651.5-651.49"
- process $proc$ls180.v:651$1871
+ attribute \src "ls180.v:655.5-655.49"
+ process $proc$ls180.v:655$1878
assign { } { }
assign $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_payload_is_cmd $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0]
end
- attribute \src "ls180.v:652.5-652.50"
- process $proc$ls180.v:652$1872
+ attribute \src "ls180.v:656.5-656.50"
+ process $proc$ls180.v:656$1879
assign { } { }
assign $1\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_payload_is_read $1\sdram_bankmachine3_cmd_payload_is_read[0:0]
end
- attribute \src "ls180.v:653.5-653.51"
- process $proc$ls180.v:653$1873
+ attribute \src "ls180.v:657.5-657.51"
+ process $proc$ls180.v:657$1880
assign { } { }
assign $1\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_payload_is_write $1\sdram_bankmachine3_cmd_payload_is_write[0:0]
end
- attribute \src "ls180.v:654.5-654.45"
- process $proc$ls180.v:654$1874
+ attribute \src "ls180.v:658.5-658.45"
+ process $proc$ls180.v:658$1881
assign { } { }
assign $1\sdram_bankmachine3_auto_precharge[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_auto_precharge $1\sdram_bankmachine3_auto_precharge[0:0]
end
- attribute \src "ls180.v:657.5-657.62"
- process $proc$ls180.v:657$1875
+ attribute \src "ls180.v:661.5-661.62"
+ process $proc$ls180.v:661$1882
assign { } { }
assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:658.5-658.61"
- process $proc$ls180.v:658$1876
+ attribute \src "ls180.v:662.5-662.61"
+ process $proc$ls180.v:662$1883
assign { } { }
assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:673.11-673.63"
- process $proc$ls180.v:673$1877
+ attribute \src "ls180.v:677.11-677.63"
+ process $proc$ls180.v:677$1884
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_lookahead_level $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]
end
- attribute \src "ls180.v:674.5-674.59"
- process $proc$ls180.v:674$1878
+ attribute \src "ls180.v:678.5-678.59"
+ process $proc$ls180.v:678$1885
assign { } { }
assign $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
update \sdram_bankmachine3_cmd_buffer_lookahead_replace $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0]
sync init
end
- attribute \src "ls180.v:675.11-675.65"
- process $proc$ls180.v:675$1879
+ attribute \src "ls180.v:679.11-679.65"
+ process $proc$ls180.v:679$1886
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_lookahead_produce $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]
end
- attribute \src "ls180.v:676.11-676.65"
- process $proc$ls180.v:676$1880
+ attribute \src "ls180.v:680.11-680.65"
+ process $proc$ls180.v:680$1887
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_lookahead_consume $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
end
- attribute \src "ls180.v:677.11-677.68"
- process $proc$ls180.v:677$1881
+ attribute \src "ls180.v:681.11-681.68"
+ process $proc$ls180.v:681$1888
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
- attribute \src "ls180.v:698.5-698.54"
- process $proc$ls180.v:698$1882
+ attribute \src "ls180.v:702.5-702.54"
+ process $proc$ls180.v:702$1889
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_source_valid $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0]
end
- attribute \src "ls180.v:700.5-700.54"
- process $proc$ls180.v:700$1883
+ attribute \src "ls180.v:704.5-704.54"
+ process $proc$ls180.v:704$1890
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_source_first $1\sdram_bankmachine3_cmd_buffer_source_first[0:0]
end
- attribute \src "ls180.v:701.5-701.53"
- process $proc$ls180.v:701$1884
+ attribute \src "ls180.v:705.5-705.53"
+ process $proc$ls180.v:705$1891
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_source_last $1\sdram_bankmachine3_cmd_buffer_source_last[0:0]
end
- attribute \src "ls180.v:702.5-702.59"
- process $proc$ls180.v:702$1885
+ attribute \src "ls180.v:706.5-706.59"
+ process $proc$ls180.v:706$1892
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_source_payload_we $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]
end
- attribute \src "ls180.v:703.12-703.69"
- process $proc$ls180.v:703$1886
+ attribute \src "ls180.v:707.12-707.69"
+ process $proc$ls180.v:707$1893
assign { } { }
assign $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
sync init
update \sdram_bankmachine3_cmd_buffer_source_payload_addr $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
end
- attribute \src "ls180.v:704.12-704.42"
- process $proc$ls180.v:704$1887
+ attribute \src "ls180.v:708.12-708.42"
+ process $proc$ls180.v:708$1894
assign { } { }
assign $1\sdram_bankmachine3_row[12:0] 13'0000000000000
sync always
sync init
update \sdram_bankmachine3_row $1\sdram_bankmachine3_row[12:0]
end
- attribute \src "ls180.v:705.5-705.41"
- process $proc$ls180.v:705$1888
+ attribute \src "ls180.v:709.5-709.41"
+ process $proc$ls180.v:709$1895
assign { } { }
assign $1\sdram_bankmachine3_row_opened[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_row_opened $1\sdram_bankmachine3_row_opened[0:0]
end
- attribute \src "ls180.v:707.5-707.39"
- process $proc$ls180.v:707$1889
+ attribute \src "ls180.v:711.5-711.39"
+ process $proc$ls180.v:711$1896
assign { } { }
assign $1\sdram_bankmachine3_row_open[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_row_open $1\sdram_bankmachine3_row_open[0:0]
end
- attribute \src "ls180.v:708.5-708.40"
- process $proc$ls180.v:708$1890
+ attribute \src "ls180.v:712.5-712.40"
+ process $proc$ls180.v:712$1897
assign { } { }
assign $1\sdram_bankmachine3_row_close[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_row_close $1\sdram_bankmachine3_row_close[0:0]
end
- attribute \src "ls180.v:709.5-709.49"
- process $proc$ls180.v:709$1891
+ attribute \src "ls180.v:713.5-713.49"
+ process $proc$ls180.v:713$1898
assign { } { }
assign $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_row_col_n_addr_sel $1\sdram_bankmachine3_row_col_n_addr_sel[0:0]
end
- attribute \src "ls180.v:711.32-711.71"
- process $proc$ls180.v:711$1892
+ attribute \src "ls180.v:715.32-715.71"
+ process $proc$ls180.v:715$1899
assign { } { }
assign $1\sdram_bankmachine3_twtpcon_ready[0:0] 1'0
sync always
sync init
update \sdram_bankmachine3_twtpcon_ready $1\sdram_bankmachine3_twtpcon_ready[0:0]
end
- attribute \src "ls180.v:712.11-712.50"
- process $proc$ls180.v:712$1893
+ attribute \src "ls180.v:716.11-716.50"
+ process $proc$ls180.v:716$1900
assign { } { }
assign $1\sdram_bankmachine3_twtpcon_count[2:0] 3'000
sync always
sync init
update \sdram_bankmachine3_twtpcon_count $1\sdram_bankmachine3_twtpcon_count[2:0]
end
- attribute \src "ls180.v:714.32-714.70"
- process $proc$ls180.v:714$1894
+ attribute \src "ls180.v:718.32-718.70"
+ process $proc$ls180.v:718$1901
assign { } { }
assign $0\sdram_bankmachine3_trccon_ready[0:0] 1'1
sync always
update \sdram_bankmachine3_trccon_ready $0\sdram_bankmachine3_trccon_ready[0:0]
sync init
end
- attribute \src "ls180.v:716.32-716.71"
- process $proc$ls180.v:716$1895
+ attribute \src "ls180.v:720.32-720.71"
+ process $proc$ls180.v:720$1902
assign { } { }
assign $0\sdram_bankmachine3_trascon_ready[0:0] 1'1
sync always
update \sdram_bankmachine3_trascon_ready $0\sdram_bankmachine3_trascon_ready[0:0]
sync init
end
- attribute \src "ls180.v:719.5-719.39"
- process $proc$ls180.v:719$1896
+ attribute \src "ls180.v:723.5-723.39"
+ process $proc$ls180.v:723$1903
assign { } { }
assign $0\sdram_choose_cmd_want_reads[0:0] 1'0
sync always
update \sdram_choose_cmd_want_reads $0\sdram_choose_cmd_want_reads[0:0]
sync init
end
- attribute \src "ls180.v:720.5-720.40"
- process $proc$ls180.v:720$1897
+ attribute \src "ls180.v:724.5-724.40"
+ process $proc$ls180.v:724$1904
assign { } { }
assign $0\sdram_choose_cmd_want_writes[0:0] 1'0
sync always
update \sdram_choose_cmd_want_writes $0\sdram_choose_cmd_want_writes[0:0]
sync init
end
- attribute \src "ls180.v:721.5-721.38"
- process $proc$ls180.v:721$1898
+ attribute \src "ls180.v:725.5-725.38"
+ process $proc$ls180.v:725$1905
assign { } { }
assign $0\sdram_choose_cmd_want_cmds[0:0] 1'0
sync always
update \sdram_choose_cmd_want_cmds $0\sdram_choose_cmd_want_cmds[0:0]
sync init
end
- attribute \src "ls180.v:722.5-722.43"
- process $proc$ls180.v:722$1899
+ attribute \src "ls180.v:726.5-726.43"
+ process $proc$ls180.v:726$1906
assign { } { }
assign $0\sdram_choose_cmd_want_activates[0:0] 1'0
sync always
update \sdram_choose_cmd_want_activates $0\sdram_choose_cmd_want_activates[0:0]
sync init
end
- attribute \src "ls180.v:724.5-724.38"
- process $proc$ls180.v:724$1900
+ attribute \src "ls180.v:728.5-728.38"
+ process $proc$ls180.v:728$1907
assign { } { }
assign $0\sdram_choose_cmd_cmd_ready[0:0] 1'0
sync always
update \sdram_choose_cmd_cmd_ready $0\sdram_choose_cmd_cmd_ready[0:0]
sync init
end
- attribute \src "ls180.v:727.5-727.44"
- process $proc$ls180.v:727$1901
+ attribute \src "ls180.v:731.5-731.44"
+ process $proc$ls180.v:731$1908
assign { } { }
assign $1\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \sdram_choose_cmd_cmd_payload_cas $1\sdram_choose_cmd_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:728.5-728.44"
- process $proc$ls180.v:728$1902
+ attribute \src "ls180.v:732.5-732.44"
+ process $proc$ls180.v:732$1909
assign { } { }
assign $1\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \sdram_choose_cmd_cmd_payload_ras $1\sdram_choose_cmd_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:729.5-729.43"
- process $proc$ls180.v:729$1903
+ attribute \src "ls180.v:733.5-733.43"
+ process $proc$ls180.v:733$1910
assign { } { }
assign $1\sdram_choose_cmd_cmd_payload_we[0:0] 1'0
sync always
sync init
update \sdram_choose_cmd_cmd_payload_we $1\sdram_choose_cmd_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:73.11-73.47"
- process $proc$ls180.v:73$1628
- assign { } { }
- assign $0\libresocsim_libresoc_ibus_cti[2:0] 3'000
- sync always
- update \libresocsim_libresoc_ibus_cti $0\libresocsim_libresoc_ibus_cti[2:0]
- sync init
- end
- attribute \src "ls180.v:733.11-733.41"
- process $proc$ls180.v:733$1904
+ attribute \src "ls180.v:737.11-737.41"
+ process $proc$ls180.v:737$1911
assign { } { }
assign $1\sdram_choose_cmd_valids[3:0] 4'0000
sync always
sync init
update \sdram_choose_cmd_valids $1\sdram_choose_cmd_valids[3:0]
end
- attribute \src "ls180.v:735.11-735.40"
- process $proc$ls180.v:735$1905
+ attribute \src "ls180.v:739.11-739.40"
+ process $proc$ls180.v:739$1912
assign { } { }
assign $1\sdram_choose_cmd_grant[1:0] 2'00
sync always
sync init
update \sdram_choose_cmd_grant $1\sdram_choose_cmd_grant[1:0]
end
- attribute \src "ls180.v:737.5-737.39"
- process $proc$ls180.v:737$1906
+ attribute \src "ls180.v:741.5-741.39"
+ process $proc$ls180.v:741$1913
assign { } { }
assign $1\sdram_choose_req_want_reads[0:0] 1'0
sync always
sync init
update \sdram_choose_req_want_reads $1\sdram_choose_req_want_reads[0:0]
end
- attribute \src "ls180.v:738.5-738.40"
- process $proc$ls180.v:738$1907
+ attribute \src "ls180.v:742.5-742.40"
+ process $proc$ls180.v:742$1914
assign { } { }
assign $1\sdram_choose_req_want_writes[0:0] 1'0
sync always
sync init
update \sdram_choose_req_want_writes $1\sdram_choose_req_want_writes[0:0]
end
- attribute \src "ls180.v:74.11-74.47"
- process $proc$ls180.v:74$1629
- assign { } { }
- assign $0\libresocsim_libresoc_ibus_bte[1:0] 2'00
- sync always
- update \libresocsim_libresoc_ibus_bte $0\libresocsim_libresoc_ibus_bte[1:0]
- sync init
- end
- attribute \src "ls180.v:740.5-740.43"
- process $proc$ls180.v:740$1908
+ attribute \src "ls180.v:744.5-744.43"
+ process $proc$ls180.v:744$1915
assign { } { }
assign $1\sdram_choose_req_want_activates[0:0] 1'0
sync always
sync init
update \sdram_choose_req_want_activates $1\sdram_choose_req_want_activates[0:0]
end
- attribute \src "ls180.v:742.5-742.38"
- process $proc$ls180.v:742$1909
+ attribute \src "ls180.v:746.5-746.38"
+ process $proc$ls180.v:746$1916
assign { } { }
assign $1\sdram_choose_req_cmd_ready[0:0] 1'0
sync always
sync init
update \sdram_choose_req_cmd_ready $1\sdram_choose_req_cmd_ready[0:0]
end
- attribute \src "ls180.v:745.5-745.44"
- process $proc$ls180.v:745$1910
+ attribute \src "ls180.v:749.5-749.44"
+ process $proc$ls180.v:749$1917
assign { } { }
assign $1\sdram_choose_req_cmd_payload_cas[0:0] 1'0
sync always
sync init
update \sdram_choose_req_cmd_payload_cas $1\sdram_choose_req_cmd_payload_cas[0:0]
end
- attribute \src "ls180.v:746.5-746.44"
- process $proc$ls180.v:746$1911
+ attribute \src "ls180.v:75.11-75.47"
+ process $proc$ls180.v:75$1635
+ assign { } { }
+ assign $0\libresocsim_libresoc_ibus_cti[2:0] 3'000
+ sync always
+ update \libresocsim_libresoc_ibus_cti $0\libresocsim_libresoc_ibus_cti[2:0]
+ sync init
+ end
+ attribute \src "ls180.v:750.5-750.44"
+ process $proc$ls180.v:750$1918
assign { } { }
assign $1\sdram_choose_req_cmd_payload_ras[0:0] 1'0
sync always
sync init
update \sdram_choose_req_cmd_payload_ras $1\sdram_choose_req_cmd_payload_ras[0:0]
end
- attribute \src "ls180.v:747.5-747.43"
- process $proc$ls180.v:747$1912
+ attribute \src "ls180.v:751.5-751.43"
+ process $proc$ls180.v:751$1919
assign { } { }
assign $1\sdram_choose_req_cmd_payload_we[0:0] 1'0
sync always
sync init
update \sdram_choose_req_cmd_payload_we $1\sdram_choose_req_cmd_payload_we[0:0]
end
- attribute \src "ls180.v:751.11-751.41"
- process $proc$ls180.v:751$1913
+ attribute \src "ls180.v:755.11-755.41"
+ process $proc$ls180.v:755$1920
assign { } { }
assign $1\sdram_choose_req_valids[3:0] 4'0000
sync always
sync init
update \sdram_choose_req_valids $1\sdram_choose_req_valids[3:0]
end
- attribute \src "ls180.v:753.11-753.40"
- process $proc$ls180.v:753$1914
+ attribute \src "ls180.v:757.11-757.40"
+ process $proc$ls180.v:757$1921
assign { } { }
assign $1\sdram_choose_req_grant[1:0] 2'00
sync always
sync init
update \sdram_choose_req_grant $1\sdram_choose_req_grant[1:0]
end
- attribute \src "ls180.v:755.12-755.31"
- process $proc$ls180.v:755$1915
+ attribute \src "ls180.v:759.12-759.31"
+ process $proc$ls180.v:759$1922
assign { } { }
assign $0\sdram_nop_a[12:0] 13'0000000000000
sync always
update \sdram_nop_a $0\sdram_nop_a[12:0]
sync init
end
- attribute \src "ls180.v:756.11-756.30"
- process $proc$ls180.v:756$1916
+ attribute \src "ls180.v:76.11-76.47"
+ process $proc$ls180.v:76$1636
+ assign { } { }
+ assign $0\libresocsim_libresoc_ibus_bte[1:0] 2'00
+ sync always
+ update \libresocsim_libresoc_ibus_bte $0\libresocsim_libresoc_ibus_bte[1:0]
+ sync init
+ end
+ attribute \src "ls180.v:760.11-760.30"
+ process $proc$ls180.v:760$1923
assign { } { }
assign $0\sdram_nop_ba[1:0] 2'00
sync always
update \sdram_nop_ba $0\sdram_nop_ba[1:0]
sync init
end
- attribute \src "ls180.v:757.11-757.35"
- process $proc$ls180.v:757$1917
+ attribute \src "ls180.v:761.11-761.35"
+ process $proc$ls180.v:761$1924
assign { } { }
assign $1\sdram_steerer_sel[1:0] 2'00
sync always
sync init
update \sdram_steerer_sel $1\sdram_steerer_sel[1:0]
end
- attribute \src "ls180.v:758.5-758.26"
- process $proc$ls180.v:758$1918
+ attribute \src "ls180.v:762.5-762.26"
+ process $proc$ls180.v:762$1925
assign { } { }
assign $0\sdram_steerer0[0:0] 1'1
sync always
update \sdram_steerer0 $0\sdram_steerer0[0:0]
sync init
end
- attribute \src "ls180.v:759.5-759.26"
- process $proc$ls180.v:759$1919
+ attribute \src "ls180.v:763.5-763.26"
+ process $proc$ls180.v:763$1926
assign { } { }
assign $0\sdram_steerer1[0:0] 1'1
sync always
update \sdram_steerer1 $0\sdram_steerer1[0:0]
sync init
end
- attribute \src "ls180.v:76.12-76.53"
- process $proc$ls180.v:76$1630
- assign { } { }
- assign $1\libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000
- sync always
- sync init
- update \libresocsim_libresoc_xics_icp_adr $1\libresocsim_libresoc_xics_icp_adr[29:0]
- end
- attribute \src "ls180.v:761.32-761.58"
- process $proc$ls180.v:761$1920
+ attribute \src "ls180.v:765.32-765.58"
+ process $proc$ls180.v:765$1927
assign { } { }
assign $0\sdram_trrdcon_ready[0:0] 1'1
sync always
update \sdram_trrdcon_ready $0\sdram_trrdcon_ready[0:0]
sync init
end
- attribute \src "ls180.v:763.32-763.58"
- process $proc$ls180.v:763$1921
+ attribute \src "ls180.v:767.32-767.58"
+ process $proc$ls180.v:767$1928
assign { } { }
assign $0\sdram_tfawcon_ready[0:0] 1'1
sync always
update \sdram_tfawcon_ready $0\sdram_tfawcon_ready[0:0]
sync init
end
- attribute \src "ls180.v:765.32-765.58"
- process $proc$ls180.v:765$1922
+ attribute \src "ls180.v:769.32-769.58"
+ process $proc$ls180.v:769$1929
assign { } { }
assign $1\sdram_tccdcon_ready[0:0] 1'0
sync always
sync init
update \sdram_tccdcon_ready $1\sdram_tccdcon_ready[0:0]
end
- attribute \src "ls180.v:766.5-766.31"
- process $proc$ls180.v:766$1923
+ attribute \src "ls180.v:770.5-770.31"
+ process $proc$ls180.v:770$1930
assign { } { }
assign $1\sdram_tccdcon_count[0:0] 1'0
sync always
sync init
update \sdram_tccdcon_count $1\sdram_tccdcon_count[0:0]
end
- attribute \src "ls180.v:768.32-768.58"
- process $proc$ls180.v:768$1924
+ attribute \src "ls180.v:772.32-772.58"
+ process $proc$ls180.v:772$1931
assign { } { }
assign $1\sdram_twtrcon_ready[0:0] 1'0
sync always
sync init
update \sdram_twtrcon_ready $1\sdram_twtrcon_ready[0:0]
end
- attribute \src "ls180.v:769.11-769.37"
- process $proc$ls180.v:769$1925
+ attribute \src "ls180.v:773.11-773.37"
+ process $proc$ls180.v:773$1932
assign { } { }
assign $1\sdram_twtrcon_count[2:0] 3'000
sync always
sync init
update \sdram_twtrcon_count $1\sdram_twtrcon_count[2:0]
end
- attribute \src "ls180.v:77.12-77.55"
- process $proc$ls180.v:77$1631
- assign { } { }
- assign $1\libresocsim_libresoc_xics_icp_dat_w[31:0] 0
- sync always
- sync init
- update \libresocsim_libresoc_xics_icp_dat_w $1\libresocsim_libresoc_xics_icp_dat_w[31:0]
- end
- attribute \src "ls180.v:772.5-772.21"
- process $proc$ls180.v:772$1926
+ attribute \src "ls180.v:776.5-776.21"
+ process $proc$ls180.v:776$1933
assign { } { }
assign $1\sdram_en0[0:0] 1'0
sync always
sync init
update \sdram_en0 $1\sdram_en0[0:0]
end
- attribute \src "ls180.v:774.11-774.29"
- process $proc$ls180.v:774$1927
+ attribute \src "ls180.v:778.11-778.29"
+ process $proc$ls180.v:778$1934
assign { } { }
assign $1\sdram_time0[4:0] 5'00000
sync always
sync init
update \sdram_time0 $1\sdram_time0[4:0]
end
- attribute \src "ls180.v:775.5-775.21"
- process $proc$ls180.v:775$1928
+ attribute \src "ls180.v:779.5-779.21"
+ process $proc$ls180.v:779$1935
assign { } { }
assign $1\sdram_en1[0:0] 1'0
sync always
sync init
update \sdram_en1 $1\sdram_en1[0:0]
end
- attribute \src "ls180.v:777.11-777.29"
- process $proc$ls180.v:777$1929
+ attribute \src "ls180.v:78.12-78.53"
+ process $proc$ls180.v:78$1637
+ assign { } { }
+ assign $1\libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000
+ sync always
+ sync init
+ update \libresocsim_libresoc_xics_icp_adr $1\libresocsim_libresoc_xics_icp_adr[29:0]
+ end
+ attribute \src "ls180.v:781.11-781.29"
+ process $proc$ls180.v:781$1936
assign { } { }
assign $1\sdram_time1[3:0] 4'0000
sync always
sync init
update \sdram_time1 $1\sdram_time1[3:0]
end
- attribute \src "ls180.v:79.11-79.51"
- process $proc$ls180.v:79$1632
+ attribute \src "ls180.v:79.12-79.55"
+ process $proc$ls180.v:79$1638
assign { } { }
- assign $1\libresocsim_libresoc_xics_icp_sel[3:0] 4'0000
+ assign $1\libresocsim_libresoc_xics_icp_dat_w[31:0] 0
sync always
sync init
- update \libresocsim_libresoc_xics_icp_sel $1\libresocsim_libresoc_xics_icp_sel[3:0]
+ update \libresocsim_libresoc_xics_icp_dat_w $1\libresocsim_libresoc_xics_icp_dat_w[31:0]
end
- attribute \src "ls180.v:792.12-792.32"
- process $proc$ls180.v:792$1930
+ attribute \src "ls180.v:796.12-796.32"
+ process $proc$ls180.v:796$1937
assign { } { }
assign $1\wb_sdram_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
update \wb_sdram_adr $1\wb_sdram_adr[29:0]
end
- attribute \src "ls180.v:793.12-793.34"
- process $proc$ls180.v:793$1931
+ attribute \src "ls180.v:797.12-797.34"
+ process $proc$ls180.v:797$1938
assign { } { }
assign $1\wb_sdram_dat_w[31:0] 0
sync always
sync init
update \wb_sdram_dat_w $1\wb_sdram_dat_w[31:0]
end
- attribute \src "ls180.v:795.11-795.30"
- process $proc$ls180.v:795$1932
+ attribute \src "ls180.v:799.11-799.30"
+ process $proc$ls180.v:799$1939
assign { } { }
assign $1\wb_sdram_sel[3:0] 4'0000
sync always
sync init
update \wb_sdram_sel $1\wb_sdram_sel[3:0]
end
- attribute \src "ls180.v:796.5-796.24"
- process $proc$ls180.v:796$1933
+ attribute \src "ls180.v:800.5-800.24"
+ process $proc$ls180.v:800$1940
assign { } { }
assign $1\wb_sdram_cyc[0:0] 1'0
sync always
sync init
update \wb_sdram_cyc $1\wb_sdram_cyc[0:0]
end
- attribute \src "ls180.v:797.5-797.24"
- process $proc$ls180.v:797$1934
+ attribute \src "ls180.v:801.5-801.24"
+ process $proc$ls180.v:801$1941
assign { } { }
assign $1\wb_sdram_stb[0:0] 1'0
sync always
sync init
update \wb_sdram_stb $1\wb_sdram_stb[0:0]
end
- attribute \src "ls180.v:798.5-798.24"
- process $proc$ls180.v:798$1935
+ attribute \src "ls180.v:802.5-802.24"
+ process $proc$ls180.v:802$1942
assign { } { }
assign $1\wb_sdram_ack[0:0] 1'0
sync always
sync init
update \wb_sdram_ack $1\wb_sdram_ack[0:0]
end
- attribute \src "ls180.v:799.5-799.23"
- process $proc$ls180.v:799$1936
+ attribute \src "ls180.v:803.5-803.23"
+ process $proc$ls180.v:803$1943
assign { } { }
assign $1\wb_sdram_we[0:0] 1'0
sync always
sync init
update \wb_sdram_we $1\wb_sdram_we[0:0]
end
- attribute \src "ls180.v:80.5-80.45"
- process $proc$ls180.v:80$1633
+ attribute \src "ls180.v:81.11-81.51"
+ process $proc$ls180.v:81$1639
assign { } { }
- assign $1\libresocsim_libresoc_xics_icp_cyc[0:0] 1'0
+ assign $1\libresocsim_libresoc_xics_icp_sel[3:0] 4'0000
sync always
sync init
- update \libresocsim_libresoc_xics_icp_cyc $1\libresocsim_libresoc_xics_icp_cyc[0:0]
+ update \libresocsim_libresoc_xics_icp_sel $1\libresocsim_libresoc_xics_icp_sel[3:0]
end
- attribute \src "ls180.v:806.5-806.49"
- process $proc$ls180.v:806$1937
+ attribute \src "ls180.v:810.5-810.49"
+ process $proc$ls180.v:810$1944
assign { } { }
assign $1\socbushandler_converted_interface_ack[0:0] 1'0
sync always
sync init
update \socbushandler_converted_interface_ack $1\socbushandler_converted_interface_ack[0:0]
end
- attribute \src "ls180.v:81.5-81.45"
- process $proc$ls180.v:81$1634
- assign { } { }
- assign $1\libresocsim_libresoc_xics_icp_stb[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_xics_icp_stb $1\libresocsim_libresoc_xics_icp_stb[0:0]
- end
- attribute \src "ls180.v:810.5-810.49"
- process $proc$ls180.v:810$1938
+ attribute \src "ls180.v:814.5-814.49"
+ process $proc$ls180.v:814$1945
assign { } { }
assign $0\socbushandler_converted_interface_err[0:0] 1'0
sync always
update \socbushandler_converted_interface_err $0\socbushandler_converted_interface_err[0:0]
sync init
end
- attribute \src "ls180.v:811.5-811.30"
- process $proc$ls180.v:811$1939
+ attribute \src "ls180.v:815.5-815.30"
+ process $proc$ls180.v:815$1946
assign { } { }
assign $1\socbushandler_skip[0:0] 1'0
sync always
sync init
update \socbushandler_skip $1\socbushandler_skip[0:0]
end
- attribute \src "ls180.v:812.5-812.33"
- process $proc$ls180.v:812$1940
+ attribute \src "ls180.v:816.5-816.33"
+ process $proc$ls180.v:816$1947
assign { } { }
assign $1\socbushandler_counter[0:0] 1'0
sync always
sync init
update \socbushandler_counter $1\socbushandler_counter[0:0]
end
- attribute \src "ls180.v:814.12-814.39"
- process $proc$ls180.v:814$1941
+ attribute \src "ls180.v:818.12-818.39"
+ process $proc$ls180.v:818$1948
assign { } { }
assign $1\socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \socbushandler_dat_r $1\socbushandler_dat_r[63:0]
end
- attribute \src "ls180.v:815.12-815.35"
- process $proc$ls180.v:815$1942
+ attribute \src "ls180.v:819.12-819.35"
+ process $proc$ls180.v:819$1949
assign { } { }
assign $1\litedram_wb_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
update \litedram_wb_adr $1\litedram_wb_adr[29:0]
end
- attribute \src "ls180.v:816.12-816.37"
- process $proc$ls180.v:816$1943
+ attribute \src "ls180.v:82.5-82.45"
+ process $proc$ls180.v:82$1640
+ assign { } { }
+ assign $1\libresocsim_libresoc_xics_icp_cyc[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_xics_icp_cyc $1\libresocsim_libresoc_xics_icp_cyc[0:0]
+ end
+ attribute \src "ls180.v:820.12-820.37"
+ process $proc$ls180.v:820$1950
assign { } { }
assign $1\litedram_wb_dat_w[15:0] 16'0000000000000000
sync always
sync init
update \litedram_wb_dat_w $1\litedram_wb_dat_w[15:0]
end
- attribute \src "ls180.v:818.11-818.33"
- process $proc$ls180.v:818$1944
+ attribute \src "ls180.v:822.11-822.33"
+ process $proc$ls180.v:822$1951
assign { } { }
assign $1\litedram_wb_sel[1:0] 2'00
sync always
sync init
update \litedram_wb_sel $1\litedram_wb_sel[1:0]
end
- attribute \src "ls180.v:819.5-819.27"
- process $proc$ls180.v:819$1945
+ attribute \src "ls180.v:823.5-823.27"
+ process $proc$ls180.v:823$1952
assign { } { }
assign $1\litedram_wb_cyc[0:0] 1'0
sync always
sync init
update \litedram_wb_cyc $1\litedram_wb_cyc[0:0]
end
- attribute \src "ls180.v:820.5-820.27"
- process $proc$ls180.v:820$1946
+ attribute \src "ls180.v:824.5-824.27"
+ process $proc$ls180.v:824$1953
assign { } { }
assign $1\litedram_wb_stb[0:0] 1'0
sync always
sync init
update \litedram_wb_stb $1\litedram_wb_stb[0:0]
end
- attribute \src "ls180.v:822.5-822.26"
- process $proc$ls180.v:822$1947
+ attribute \src "ls180.v:826.5-826.26"
+ process $proc$ls180.v:826$1954
assign { } { }
assign $1\litedram_wb_we[0:0] 1'0
sync always
sync init
update \litedram_wb_we $1\litedram_wb_we[0:0]
end
- attribute \src "ls180.v:823.5-823.26"
- process $proc$ls180.v:823$1948
+ attribute \src "ls180.v:827.5-827.26"
+ process $proc$ls180.v:827$1955
assign { } { }
assign $1\converter_skip[0:0] 1'0
sync always
sync init
update \converter_skip $1\converter_skip[0:0]
end
- attribute \src "ls180.v:824.5-824.29"
- process $proc$ls180.v:824$1949
+ attribute \src "ls180.v:828.5-828.29"
+ process $proc$ls180.v:828$1956
assign { } { }
assign $1\converter_counter[0:0] 1'0
sync always
sync init
update \converter_counter $1\converter_counter[0:0]
end
- attribute \src "ls180.v:826.12-826.35"
- process $proc$ls180.v:826$1950
+ attribute \src "ls180.v:83.5-83.45"
+ process $proc$ls180.v:83$1641
+ assign { } { }
+ assign $1\libresocsim_libresoc_xics_icp_stb[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_xics_icp_stb $1\libresocsim_libresoc_xics_icp_stb[0:0]
+ end
+ attribute \src "ls180.v:830.12-830.35"
+ process $proc$ls180.v:830$1957
assign { } { }
assign $1\converter_dat_r[31:0] 0
sync always
sync init
update \converter_dat_r $1\converter_dat_r[31:0]
end
- attribute \src "ls180.v:827.5-827.24"
- process $proc$ls180.v:827$1951
+ attribute \src "ls180.v:831.5-831.24"
+ process $proc$ls180.v:831$1958
assign { } { }
assign $1\cmd_consumed[0:0] 1'0
sync always
sync init
update \cmd_consumed $1\cmd_consumed[0:0]
end
- attribute \src "ls180.v:828.5-828.26"
- process $proc$ls180.v:828$1952
+ attribute \src "ls180.v:832.5-832.26"
+ process $proc$ls180.v:832$1959
assign { } { }
assign $1\wdata_consumed[0:0] 1'0
sync always
sync init
update \wdata_consumed $1\wdata_consumed[0:0]
end
- attribute \src "ls180.v:83.5-83.44"
- process $proc$ls180.v:83$1635
- assign { } { }
- assign $1\libresocsim_libresoc_xics_icp_we[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_xics_icp_we $1\libresocsim_libresoc_xics_icp_we[0:0]
- end
- attribute \src "ls180.v:832.12-832.42"
- process $proc$ls180.v:832$1953
+ attribute \src "ls180.v:836.12-836.42"
+ process $proc$ls180.v:836$1960
assign { } { }
assign $1\uart_phy_storage[31:0] 9895604
sync always
sync init
update \uart_phy_storage $1\uart_phy_storage[31:0]
end
- attribute \src "ls180.v:833.5-833.23"
- process $proc$ls180.v:833$1954
+ attribute \src "ls180.v:837.5-837.23"
+ process $proc$ls180.v:837$1961
assign { } { }
assign $1\uart_phy_re[0:0] 1'0
sync always
sync init
update \uart_phy_re $1\uart_phy_re[0:0]
end
- attribute \src "ls180.v:835.5-835.31"
- process $proc$ls180.v:835$1955
+ attribute \src "ls180.v:839.5-839.31"
+ process $proc$ls180.v:839$1962
assign { } { }
assign $1\uart_phy_sink_ready[0:0] 1'0
sync always
sync init
update \uart_phy_sink_ready $1\uart_phy_sink_ready[0:0]
end
- attribute \src "ls180.v:839.5-839.34"
- process $proc$ls180.v:839$1956
+ attribute \src "ls180.v:843.5-843.34"
+ process $proc$ls180.v:843$1963
assign { } { }
assign $1\uart_phy_uart_clk_txen[0:0] 1'0
sync always
sync init
update \uart_phy_uart_clk_txen $1\uart_phy_uart_clk_txen[0:0]
end
- attribute \src "ls180.v:840.12-840.49"
- process $proc$ls180.v:840$1957
+ attribute \src "ls180.v:844.12-844.49"
+ process $proc$ls180.v:844$1964
assign { } { }
assign $1\uart_phy_phase_accumulator_tx[31:0] 0
sync always
sync init
update \uart_phy_phase_accumulator_tx $1\uart_phy_phase_accumulator_tx[31:0]
end
- attribute \src "ls180.v:841.11-841.33"
- process $proc$ls180.v:841$1958
+ attribute \src "ls180.v:845.11-845.33"
+ process $proc$ls180.v:845$1965
assign { } { }
assign $1\uart_phy_tx_reg[7:0] 8'00000000
sync always
sync init
update \uart_phy_tx_reg $1\uart_phy_tx_reg[7:0]
end
- attribute \src "ls180.v:842.11-842.38"
- process $proc$ls180.v:842$1959
+ attribute \src "ls180.v:846.11-846.38"
+ process $proc$ls180.v:846$1966
assign { } { }
assign $1\uart_phy_tx_bitcount[3:0] 4'0000
sync always
sync init
update \uart_phy_tx_bitcount $1\uart_phy_tx_bitcount[3:0]
end
- attribute \src "ls180.v:843.5-843.28"
- process $proc$ls180.v:843$1960
+ attribute \src "ls180.v:847.5-847.28"
+ process $proc$ls180.v:847$1967
assign { } { }
assign $1\uart_phy_tx_busy[0:0] 1'0
sync always
sync init
update \uart_phy_tx_busy $1\uart_phy_tx_busy[0:0]
end
- attribute \src "ls180.v:844.5-844.33"
- process $proc$ls180.v:844$1961
+ attribute \src "ls180.v:848.5-848.33"
+ process $proc$ls180.v:848$1968
assign { } { }
assign $1\uart_phy_source_valid[0:0] 1'0
sync always
sync init
update \uart_phy_source_valid $1\uart_phy_source_valid[0:0]
end
- attribute \src "ls180.v:846.5-846.33"
- process $proc$ls180.v:846$1962
+ attribute \src "ls180.v:85.5-85.44"
+ process $proc$ls180.v:85$1642
+ assign { } { }
+ assign $1\libresocsim_libresoc_xics_icp_we[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_xics_icp_we $1\libresocsim_libresoc_xics_icp_we[0:0]
+ end
+ attribute \src "ls180.v:850.5-850.33"
+ process $proc$ls180.v:850$1969
assign { } { }
assign $0\uart_phy_source_first[0:0] 1'0
sync always
update \uart_phy_source_first $0\uart_phy_source_first[0:0]
sync init
end
- attribute \src "ls180.v:847.5-847.32"
- process $proc$ls180.v:847$1963
+ attribute \src "ls180.v:851.5-851.32"
+ process $proc$ls180.v:851$1970
assign { } { }
assign $0\uart_phy_source_last[0:0] 1'0
sync always
update \uart_phy_source_last $0\uart_phy_source_last[0:0]
sync init
end
- attribute \src "ls180.v:848.11-848.46"
- process $proc$ls180.v:848$1964
+ attribute \src "ls180.v:852.11-852.46"
+ process $proc$ls180.v:852$1971
assign { } { }
assign $1\uart_phy_source_payload_data[7:0] 8'00000000
sync always
sync init
update \uart_phy_source_payload_data $1\uart_phy_source_payload_data[7:0]
end
- attribute \src "ls180.v:849.5-849.34"
- process $proc$ls180.v:849$1965
+ attribute \src "ls180.v:853.5-853.34"
+ process $proc$ls180.v:853$1972
assign { } { }
assign $1\uart_phy_uart_clk_rxen[0:0] 1'0
sync always
sync init
update \uart_phy_uart_clk_rxen $1\uart_phy_uart_clk_rxen[0:0]
end
- attribute \src "ls180.v:85.12-85.53"
- process $proc$ls180.v:85$1636
- assign { } { }
- assign $1\libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000
- sync always
- sync init
- update \libresocsim_libresoc_xics_ics_adr $1\libresocsim_libresoc_xics_ics_adr[29:0]
- end
- attribute \src "ls180.v:850.12-850.49"
- process $proc$ls180.v:850$1966
+ attribute \src "ls180.v:854.12-854.49"
+ process $proc$ls180.v:854$1973
assign { } { }
assign $1\uart_phy_phase_accumulator_rx[31:0] 0
sync always
sync init
update \uart_phy_phase_accumulator_rx $1\uart_phy_phase_accumulator_rx[31:0]
end
- attribute \src "ls180.v:852.5-852.25"
- process $proc$ls180.v:852$1967
+ attribute \src "ls180.v:856.5-856.25"
+ process $proc$ls180.v:856$1974
assign { } { }
assign $1\uart_phy_rx_r[0:0] 1'0
sync always
sync init
update \uart_phy_rx_r $1\uart_phy_rx_r[0:0]
end
- attribute \src "ls180.v:853.11-853.33"
- process $proc$ls180.v:853$1968
+ attribute \src "ls180.v:857.11-857.33"
+ process $proc$ls180.v:857$1975
assign { } { }
assign $1\uart_phy_rx_reg[7:0] 8'00000000
sync always
sync init
update \uart_phy_rx_reg $1\uart_phy_rx_reg[7:0]
end
- attribute \src "ls180.v:854.11-854.38"
- process $proc$ls180.v:854$1969
+ attribute \src "ls180.v:858.11-858.38"
+ process $proc$ls180.v:858$1976
assign { } { }
assign $1\uart_phy_rx_bitcount[3:0] 4'0000
sync always
sync init
update \uart_phy_rx_bitcount $1\uart_phy_rx_bitcount[3:0]
end
- attribute \src "ls180.v:855.5-855.28"
- process $proc$ls180.v:855$1970
+ attribute \src "ls180.v:859.5-859.28"
+ process $proc$ls180.v:859$1977
assign { } { }
assign $1\uart_phy_rx_busy[0:0] 1'0
sync always
sync init
update \uart_phy_rx_busy $1\uart_phy_rx_busy[0:0]
end
- attribute \src "ls180.v:86.12-86.55"
- process $proc$ls180.v:86$1637
+ attribute \src "ls180.v:87.12-87.53"
+ process $proc$ls180.v:87$1643
assign { } { }
- assign $1\libresocsim_libresoc_xics_ics_dat_w[31:0] 0
+ assign $1\libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000
sync always
sync init
- update \libresocsim_libresoc_xics_ics_dat_w $1\libresocsim_libresoc_xics_ics_dat_w[31:0]
+ update \libresocsim_libresoc_xics_ics_adr $1\libresocsim_libresoc_xics_ics_adr[29:0]
end
- attribute \src "ls180.v:866.5-866.22"
- process $proc$ls180.v:866$1971
+ attribute \src "ls180.v:870.5-870.22"
+ process $proc$ls180.v:870$1978
assign { } { }
assign $1\tx_pending[0:0] 1'0
sync always
sync init
update \tx_pending $1\tx_pending[0:0]
end
- attribute \src "ls180.v:868.5-868.20"
- process $proc$ls180.v:868$1972
+ attribute \src "ls180.v:872.5-872.20"
+ process $proc$ls180.v:872$1979
assign { } { }
assign $1\tx_clear[0:0] 1'0
sync always
sync init
update \tx_clear $1\tx_clear[0:0]
end
- attribute \src "ls180.v:869.5-869.26"
- process $proc$ls180.v:869$1973
+ attribute \src "ls180.v:873.5-873.26"
+ process $proc$ls180.v:873$1980
assign { } { }
assign $1\tx_old_trigger[0:0] 1'0
sync always
sync init
update \tx_old_trigger $1\tx_old_trigger[0:0]
end
- attribute \src "ls180.v:871.5-871.22"
- process $proc$ls180.v:871$1974
+ attribute \src "ls180.v:875.5-875.22"
+ process $proc$ls180.v:875$1981
assign { } { }
assign $1\rx_pending[0:0] 1'0
sync always
sync init
update \rx_pending $1\rx_pending[0:0]
end
- attribute \src "ls180.v:873.5-873.20"
- process $proc$ls180.v:873$1975
+ attribute \src "ls180.v:877.5-877.20"
+ process $proc$ls180.v:877$1982
assign { } { }
assign $1\rx_clear[0:0] 1'0
sync always
sync init
update \rx_clear $1\rx_clear[0:0]
end
- attribute \src "ls180.v:874.5-874.26"
- process $proc$ls180.v:874$1976
+ attribute \src "ls180.v:878.5-878.26"
+ process $proc$ls180.v:878$1983
assign { } { }
assign $1\rx_old_trigger[0:0] 1'0
sync always
sync init
update \rx_old_trigger $1\rx_old_trigger[0:0]
end
- attribute \src "ls180.v:878.11-878.39"
- process $proc$ls180.v:878$1977
+ attribute \src "ls180.v:88.12-88.55"
+ process $proc$ls180.v:88$1644
assign { } { }
- assign $1\eventmanager_status_w[1:0] 2'00
+ assign $1\libresocsim_libresoc_xics_ics_dat_w[31:0] 0
sync always
sync init
- update \eventmanager_status_w $1\eventmanager_status_w[1:0]
+ update \libresocsim_libresoc_xics_ics_dat_w $1\libresocsim_libresoc_xics_ics_dat_w[31:0]
end
- attribute \src "ls180.v:88.11-88.51"
- process $proc$ls180.v:88$1638
+ attribute \src "ls180.v:882.11-882.39"
+ process $proc$ls180.v:882$1984
assign { } { }
- assign $1\libresocsim_libresoc_xics_ics_sel[3:0] 4'0000
+ assign $1\eventmanager_status_w[1:0] 2'00
sync always
sync init
- update \libresocsim_libresoc_xics_ics_sel $1\libresocsim_libresoc_xics_ics_sel[3:0]
+ update \eventmanager_status_w $1\eventmanager_status_w[1:0]
end
- attribute \src "ls180.v:882.11-882.40"
- process $proc$ls180.v:882$1978
+ attribute \src "ls180.v:886.11-886.40"
+ process $proc$ls180.v:886$1985
assign { } { }
assign $1\eventmanager_pending_w[1:0] 2'00
sync always
sync init
update \eventmanager_pending_w $1\eventmanager_pending_w[1:0]
end
- attribute \src "ls180.v:883.11-883.38"
- process $proc$ls180.v:883$1979
+ attribute \src "ls180.v:887.11-887.38"
+ process $proc$ls180.v:887$1986
assign { } { }
assign $1\eventmanager_storage[1:0] 2'00
sync always
sync init
update \eventmanager_storage $1\eventmanager_storage[1:0]
end
- attribute \src "ls180.v:884.5-884.27"
- process $proc$ls180.v:884$1980
+ attribute \src "ls180.v:888.5-888.27"
+ process $proc$ls180.v:888$1987
assign { } { }
assign $1\eventmanager_re[0:0] 1'0
sync always
sync init
update \eventmanager_re $1\eventmanager_re[0:0]
end
- attribute \src "ls180.v:89.5-89.45"
- process $proc$ls180.v:89$1639
- assign { } { }
- assign $1\libresocsim_libresoc_xics_ics_cyc[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_xics_ics_cyc $1\libresocsim_libresoc_xics_ics_cyc[0:0]
- end
- attribute \src "ls180.v:90.5-90.45"
- process $proc$ls180.v:90$1640
+ attribute \src "ls180.v:90.11-90.51"
+ process $proc$ls180.v:90$1645
assign { } { }
- assign $1\libresocsim_libresoc_xics_ics_stb[0:0] 1'0
+ assign $1\libresocsim_libresoc_xics_ics_sel[3:0] 4'0000
sync always
sync init
- update \libresocsim_libresoc_xics_ics_stb $1\libresocsim_libresoc_xics_ics_stb[0:0]
+ update \libresocsim_libresoc_xics_ics_sel $1\libresocsim_libresoc_xics_ics_sel[3:0]
end
- attribute \src "ls180.v:901.5-901.30"
- process $proc$ls180.v:901$1981
+ attribute \src "ls180.v:905.5-905.30"
+ process $proc$ls180.v:905$1988
assign { } { }
assign $0\tx_fifo_sink_first[0:0] 1'0
sync always
update \tx_fifo_sink_first $0\tx_fifo_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:902.5-902.29"
- process $proc$ls180.v:902$1982
+ attribute \src "ls180.v:906.5-906.29"
+ process $proc$ls180.v:906$1989
assign { } { }
assign $0\tx_fifo_sink_last[0:0] 1'0
sync always
update \tx_fifo_sink_last $0\tx_fifo_sink_last[0:0]
sync init
end
- attribute \src "ls180.v:910.5-910.28"
- process $proc$ls180.v:910$1983
+ attribute \src "ls180.v:91.5-91.45"
+ process $proc$ls180.v:91$1646
+ assign { } { }
+ assign $1\libresocsim_libresoc_xics_ics_cyc[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_xics_ics_cyc $1\libresocsim_libresoc_xics_ics_cyc[0:0]
+ end
+ attribute \src "ls180.v:914.5-914.28"
+ process $proc$ls180.v:914$1990
assign { } { }
assign $1\tx_fifo_readable[0:0] 1'0
sync always
sync init
update \tx_fifo_readable $1\tx_fifo_readable[0:0]
end
- attribute \src "ls180.v:917.11-917.32"
- process $proc$ls180.v:917$1984
+ attribute \src "ls180.v:92.5-92.45"
+ process $proc$ls180.v:92$1647
+ assign { } { }
+ assign $1\libresocsim_libresoc_xics_ics_stb[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_xics_ics_stb $1\libresocsim_libresoc_xics_ics_stb[0:0]
+ end
+ attribute \src "ls180.v:921.11-921.32"
+ process $proc$ls180.v:921$1991
assign { } { }
assign $1\tx_fifo_level0[4:0] 5'00000
sync always
sync init
update \tx_fifo_level0 $1\tx_fifo_level0[4:0]
end
- attribute \src "ls180.v:918.5-918.27"
- process $proc$ls180.v:918$1985
+ attribute \src "ls180.v:922.5-922.27"
+ process $proc$ls180.v:922$1992
assign { } { }
assign $0\tx_fifo_replace[0:0] 1'0
sync always
update \tx_fifo_replace $0\tx_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:919.11-919.33"
- process $proc$ls180.v:919$1986
+ attribute \src "ls180.v:923.11-923.33"
+ process $proc$ls180.v:923$1993
assign { } { }
assign $1\tx_fifo_produce[3:0] 4'0000
sync always
sync init
update \tx_fifo_produce $1\tx_fifo_produce[3:0]
end
- attribute \src "ls180.v:92.5-92.44"
- process $proc$ls180.v:92$1641
- assign { } { }
- assign $1\libresocsim_libresoc_xics_ics_we[0:0] 1'0
- sync always
- sync init
- update \libresocsim_libresoc_xics_ics_we $1\libresocsim_libresoc_xics_ics_we[0:0]
- end
- attribute \src "ls180.v:920.11-920.33"
- process $proc$ls180.v:920$1987
+ attribute \src "ls180.v:924.11-924.33"
+ process $proc$ls180.v:924$1994
assign { } { }
assign $1\tx_fifo_consume[3:0] 4'0000
sync always
sync init
update \tx_fifo_consume $1\tx_fifo_consume[3:0]
end
- attribute \src "ls180.v:921.11-921.36"
- process $proc$ls180.v:921$1988
+ attribute \src "ls180.v:925.11-925.36"
+ process $proc$ls180.v:925$1995
assign { } { }
assign $1\tx_fifo_wrport_adr[3:0] 4'0000
sync always
sync init
update \tx_fifo_wrport_adr $1\tx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:947.5-947.28"
- process $proc$ls180.v:947$1989
+ attribute \src "ls180.v:94.5-94.44"
+ process $proc$ls180.v:94$1648
+ assign { } { }
+ assign $1\libresocsim_libresoc_xics_ics_we[0:0] 1'0
+ sync always
+ sync init
+ update \libresocsim_libresoc_xics_ics_we $1\libresocsim_libresoc_xics_ics_we[0:0]
+ end
+ attribute \src "ls180.v:951.5-951.28"
+ process $proc$ls180.v:951$1996
assign { } { }
assign $1\rx_fifo_readable[0:0] 1'0
sync always
sync init
update \rx_fifo_readable $1\rx_fifo_readable[0:0]
end
- attribute \src "ls180.v:954.11-954.32"
- process $proc$ls180.v:954$1990
+ attribute \src "ls180.v:958.11-958.32"
+ process $proc$ls180.v:958$1997
assign { } { }
assign $1\rx_fifo_level0[4:0] 5'00000
sync always
sync init
update \rx_fifo_level0 $1\rx_fifo_level0[4:0]
end
- attribute \src "ls180.v:955.5-955.27"
- process $proc$ls180.v:955$1991
+ attribute \src "ls180.v:959.5-959.27"
+ process $proc$ls180.v:959$1998
assign { } { }
assign $0\rx_fifo_replace[0:0] 1'0
sync always
update \rx_fifo_replace $0\rx_fifo_replace[0:0]
sync init
end
- attribute \src "ls180.v:956.11-956.33"
- process $proc$ls180.v:956$1992
+ attribute \src "ls180.v:960.11-960.33"
+ process $proc$ls180.v:960$1999
assign { } { }
assign $1\rx_fifo_produce[3:0] 4'0000
sync always
sync init
update \rx_fifo_produce $1\rx_fifo_produce[3:0]
end
- attribute \src "ls180.v:957.11-957.33"
- process $proc$ls180.v:957$1993
+ attribute \src "ls180.v:961.11-961.33"
+ process $proc$ls180.v:961$2000
assign { } { }
assign $1\rx_fifo_consume[3:0] 4'0000
sync always
sync init
update \rx_fifo_consume $1\rx_fifo_consume[3:0]
end
- attribute \src "ls180.v:958.11-958.36"
- process $proc$ls180.v:958$1994
+ attribute \src "ls180.v:962.11-962.36"
+ process $proc$ls180.v:962$2001
assign { } { }
assign $1\rx_fifo_wrport_adr[3:0] 4'0000
sync always
sync init
update \rx_fifo_wrport_adr $1\rx_fifo_wrport_adr[3:0]
end
- attribute \src "ls180.v:973.5-973.17"
- process $proc$ls180.v:973$1995
+ attribute \src "ls180.v:977.5-977.17"
+ process $proc$ls180.v:977$2002
assign { } { }
assign $0\reset[0:0] 1'0
sync always
update \reset $0\reset[0:0]
sync init
end
- attribute \src "ls180.v:974.11-974.34"
- process $proc$ls180.v:974$1996
+ attribute \src "ls180.v:978.11-978.34"
+ process $proc$ls180.v:978$2003
assign { } { }
assign $1\gpio0_oe_storage[7:0] 8'00000000
sync always
sync init
update \gpio0_oe_storage $1\gpio0_oe_storage[7:0]
end
- attribute \src "ls180.v:975.5-975.23"
- process $proc$ls180.v:975$1997
+ attribute \src "ls180.v:979.5-979.23"
+ process $proc$ls180.v:979$2004
assign { } { }
assign $1\gpio0_oe_re[0:0] 1'0
sync always
sync init
update \gpio0_oe_re $1\gpio0_oe_re[0:0]
end
- attribute \src "ls180.v:976.11-976.30"
- process $proc$ls180.v:976$1998
+ attribute \src "ls180.v:980.11-980.30"
+ process $proc$ls180.v:980$2005
assign { } { }
assign $1\gpio0_status[7:0] 8'00000000
sync always
sync init
update \gpio0_status $1\gpio0_status[7:0]
end
- attribute \src "ls180.v:978.11-978.35"
- process $proc$ls180.v:978$1999
+ attribute \src "ls180.v:982.11-982.35"
+ process $proc$ls180.v:982$2006
assign { } { }
assign $1\gpio0_out_storage[7:0] 8'00000000
sync always
sync init
update \gpio0_out_storage $1\gpio0_out_storage[7:0]
end
- attribute \src "ls180.v:979.5-979.24"
- process $proc$ls180.v:979$2000
+ attribute \src "ls180.v:983.5-983.24"
+ process $proc$ls180.v:983$2007
assign { } { }
assign $1\gpio0_out_re[0:0] 1'0
sync always
sync init
update \gpio0_out_re $1\gpio0_out_re[0:0]
end
- attribute \src "ls180.v:980.11-980.35"
- process $proc$ls180.v:980$2001
+ attribute \src "ls180.v:984.11-984.35"
+ process $proc$ls180.v:984$2008
assign { } { }
assign $1\gpio0_pads_gpio0i[7:0] 8'00000000
sync always
sync init
update \gpio0_pads_gpio0i $1\gpio0_pads_gpio0i[7:0]
end
- attribute \src "ls180.v:981.11-981.35"
- process $proc$ls180.v:981$2002
+ attribute \src "ls180.v:985.11-985.35"
+ process $proc$ls180.v:985$2009
assign { } { }
assign $1\gpio0_pads_gpio0o[7:0] 8'00000000
sync always
sync init
update \gpio0_pads_gpio0o $1\gpio0_pads_gpio0o[7:0]
end
- attribute \src "ls180.v:982.11-982.36"
- process $proc$ls180.v:982$2003
+ attribute \src "ls180.v:986.11-986.36"
+ process $proc$ls180.v:986$2010
assign { } { }
assign $1\gpio0_pads_gpio0oe[7:0] 8'00000000
sync always
sync init
update \gpio0_pads_gpio0oe $1\gpio0_pads_gpio0oe[7:0]
end
- attribute \src "ls180.v:983.11-983.34"
- process $proc$ls180.v:983$2004
+ attribute \src "ls180.v:987.11-987.34"
+ process $proc$ls180.v:987$2011
assign { } { }
assign $1\gpio1_oe_storage[7:0] 8'00000000
sync always
sync init
update \gpio1_oe_storage $1\gpio1_oe_storage[7:0]
end
- attribute \src "ls180.v:984.5-984.23"
- process $proc$ls180.v:984$2005
+ attribute \src "ls180.v:988.5-988.23"
+ process $proc$ls180.v:988$2012
assign { } { }
assign $1\gpio1_oe_re[0:0] 1'0
sync always
sync init
update \gpio1_oe_re $1\gpio1_oe_re[0:0]
end
- attribute \src "ls180.v:985.11-985.30"
- process $proc$ls180.v:985$2006
+ attribute \src "ls180.v:989.11-989.30"
+ process $proc$ls180.v:989$2013
assign { } { }
assign $1\gpio1_status[7:0] 8'00000000
sync always
sync init
update \gpio1_status $1\gpio1_status[7:0]
end
- attribute \src "ls180.v:987.11-987.35"
- process $proc$ls180.v:987$2007
+ attribute \src "ls180.v:991.11-991.35"
+ process $proc$ls180.v:991$2014
assign { } { }
assign $1\gpio1_out_storage[7:0] 8'00000000
sync always
sync init
update \gpio1_out_storage $1\gpio1_out_storage[7:0]
end
- attribute \src "ls180.v:988.5-988.24"
- process $proc$ls180.v:988$2008
+ attribute \src "ls180.v:992.5-992.24"
+ process $proc$ls180.v:992$2015
assign { } { }
assign $1\gpio1_out_re[0:0] 1'0
sync always
sync init
update \gpio1_out_re $1\gpio1_out_re[0:0]
end
- attribute \src "ls180.v:989.11-989.35"
- process $proc$ls180.v:989$2009
+ attribute \src "ls180.v:993.11-993.35"
+ process $proc$ls180.v:993$2016
assign { } { }
assign $1\gpio1_pads_gpio1i[7:0] 8'00000000
sync always
sync init
update \gpio1_pads_gpio1i $1\gpio1_pads_gpio1i[7:0]
end
- attribute \src "ls180.v:990.11-990.35"
- process $proc$ls180.v:990$2010
+ attribute \src "ls180.v:994.11-994.35"
+ process $proc$ls180.v:994$2017
assign { } { }
assign $1\gpio1_pads_gpio1o[7:0] 8'00000000
sync always
sync init
update \gpio1_pads_gpio1o $1\gpio1_pads_gpio1o[7:0]
end
- attribute \src "ls180.v:991.11-991.36"
- process $proc$ls180.v:991$2011
+ attribute \src "ls180.v:995.11-995.36"
+ process $proc$ls180.v:995$2018
assign { } { }
assign $1\gpio1_pads_gpio1oe[7:0] 8'00000000
sync always
sync init
update \gpio1_pads_gpio1oe $1\gpio1_pads_gpio1oe[7:0]
end
- attribute \src "ls180.v:993.12-993.25"
- process $proc$ls180.v:993$2012
+ attribute \src "ls180.v:996.11-996.26"
+ process $proc$ls180.v:996$2019
assign { } { }
- assign $1\dummy[29:0] 30'000000000000000000000000000000
+ assign $1\eint_tmp[2:0] 3'000
sync always
sync init
- update \dummy $1\dummy[29:0]
+ update \eint_tmp $1\eint_tmp[2:0]
end
- attribute \src "ls180.v:997.11-997.29"
- process $proc$ls180.v:997$2013
+ attribute \src "ls180.v:998.12-998.25"
+ process $proc$ls180.v:998$2020
assign { } { }
- assign $1\i2c_storage[2:0] 3'000
- sync always
- sync init
- update \i2c_storage $1\i2c_storage[2:0]
- end
- attribute \src "ls180.v:998.5-998.18"
- process $proc$ls180.v:998$2014
- assign { } { }
- assign $1\i2c_re[0:0] 1'0
+ assign $1\dummy[35:0] 36'000000000000000000000000000000000000
sync always
sync init
- update \i2c_re $1\i2c_re[0:0]
+ update \dummy $1\dummy[35:0]
end
connect \libresocsim_libresoc_reset \libresocsim_reset
connect \libresocsim_libresoc_clk_sel \sys_clksel_i
connect \jtag_tdo \libresocsim_libresoc_jtag_tdo
connect \nc_1 \nc
connect \libresocsim_bus_error \libresocsim_error
- connect \converter0_reset $not$ls180.v:1513$24_Y
+ connect \converter0_reset $not$ls180.v:1526$25_Y
connect \interface0_converted_interface_dat_r { \libresocsim_libresoc_xics_icp_dat_r \converter0_dat_r [63:32] }
- connect \converter1_reset $not$ls180.v:1573$35_Y
+ connect \converter1_reset $not$ls180.v:1586$36_Y
connect \interface1_converted_interface_dat_r { \libresocsim_libresoc_xics_ics_dat_r \converter1_dat_r [63:32] }
- connect \socbushandler_reset $not$ls180.v:1633$46_Y
+ connect \socbushandler_reset $not$ls180.v:1646$47_Y
connect \socbushandler_converted_interface_dat_r { \wb_sdram_dat_r \socbushandler_dat_r [63:32] }
connect \libresocsim_reset \libresocsim_reset_re
connect \libresocsim_bus_errors_status \libresocsim_bus_errors
connect \libresocsim_adr \libresocsim_ram_bus_adr [5:0]
connect \libresocsim_ram_bus_dat_r \libresocsim_dat_r
connect \libresocsim_dat_w \libresocsim_ram_bus_dat_w
- connect \libresocsim_zero_trigger $ne$ls180.v:1709$82_Y
+ connect \libresocsim_zero_trigger $ne$ls180.v:1722$83_Y
connect \libresocsim_eventmanager_status_w \libresocsim_zero_status
connect \libresocsim_eventmanager_pending_w \libresocsim_zero_pending
- connect \libresocsim_irq $and$ls180.v:1718$85_Y
+ connect \libresocsim_irq $and$ls180.v:1731$86_Y
connect \libresocsim_zero_status \libresocsim_zero_trigger
connect \ram_adr \ram_bus_ram_bus_adr [3:0]
connect \ram_bus_ram_bus_dat_r \ram_dat_r
connect \sdram_inti_p0_reset_n \sdram_reset_n
connect \sdram_inti_p0_address \sdram_address_storage
connect \sdram_inti_p0_bank \sdram_baddress_storage
- connect \sdram_inti_p0_wrdata_en $and$ls180.v:1846$117_Y
- connect \sdram_inti_p0_rddata_en $and$ls180.v:1847$118_Y
+ connect \sdram_inti_p0_wrdata_en $and$ls180.v:1859$118_Y
+ connect \sdram_inti_p0_rddata_en $and$ls180.v:1860$119_Y
connect \sdram_inti_p0_wrdata \sdram_wrdata_storage
connect \sdram_inti_p0_wrdata_mask 2'00
connect \sdram_bankmachine0_req_valid \sdram_interface_bank0_valid
connect \sdram_interface_bank3_lock \sdram_bankmachine3_req_lock
connect \sdram_interface_bank3_wdata_ready \sdram_bankmachine3_req_wdata_ready
connect \sdram_interface_bank3_rdata_valid \sdram_bankmachine3_req_rdata_valid
- connect \sdram_timer_wait $not$ls180.v:1878$119_Y
+ connect \sdram_timer_wait $not$ls180.v:1891$120_Y
connect \sdram_postponer_req_i \sdram_timer_done0
connect \sdram_wants_refresh \sdram_postponer_req_o
- connect \sdram_timer_done1 $eq$ls180.v:1881$120_Y
+ connect \sdram_timer_done1 $eq$ls180.v:1894$121_Y
connect \sdram_timer_done0 \sdram_timer_done1
connect \sdram_timer_count0 \sdram_timer_count1
- connect \sdram_sequencer_start1 $or$ls180.v:1884$122_Y
- connect \sdram_sequencer_done0 $and$ls180.v:1885$124_Y
+ connect \sdram_sequencer_start1 $or$ls180.v:1897$123_Y
+ connect \sdram_sequencer_done0 $and$ls180.v:1898$125_Y
connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \sdram_bankmachine0_req_valid
connect \sdram_bankmachine0_req_ready \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready
connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine0_req_we
connect \sdram_bankmachine0_cmd_buffer_sink_last \sdram_bankmachine0_cmd_buffer_lookahead_source_last
connect \sdram_bankmachine0_cmd_buffer_sink_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we
connect \sdram_bankmachine0_cmd_buffer_sink_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr
- connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1927$126_Y
- connect \sdram_bankmachine0_req_lock $or$ls180.v:1928$127_Y
- connect \sdram_bankmachine0_row_hit $eq$ls180.v:1929$128_Y
+ connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1940$127_Y
+ connect \sdram_bankmachine0_req_lock $or$ls180.v:1941$128_Y
+ connect \sdram_bankmachine0_row_hit $eq$ls180.v:1942$129_Y
connect \sdram_bankmachine0_cmd_payload_ba 2'00
- connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1939$133_Y
- connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1940$135_Y
- connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1941$137_Y
+ connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1952$134_Y
+ connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1953$136_Y
+ connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1954$138_Y
connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout
connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable
connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr
connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \sdram_bankmachine0_cmd_buffer_lookahead_source_ready
connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din
- connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1973$145_Y
- connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1974$146_Y
+ connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1986$146_Y
+ connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1987$147_Y
connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine0_cmd_buffer_lookahead_consume
connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r
- connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1977$147_Y
- connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1978$148_Y
- connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1979$150_Y
+ connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1990$148_Y
+ connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1991$149_Y
+ connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1992$151_Y
connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \sdram_bankmachine1_req_valid
connect \sdram_bankmachine1_req_ready \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready
connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine1_req_we
connect \sdram_bankmachine1_cmd_buffer_sink_last \sdram_bankmachine1_cmd_buffer_lookahead_source_last
connect \sdram_bankmachine1_cmd_buffer_sink_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we
connect \sdram_bankmachine1_cmd_buffer_sink_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr
- connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2084$156_Y
- connect \sdram_bankmachine1_req_lock $or$ls180.v:2085$157_Y
- connect \sdram_bankmachine1_row_hit $eq$ls180.v:2086$158_Y
+ connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2097$157_Y
+ connect \sdram_bankmachine1_req_lock $or$ls180.v:2098$158_Y
+ connect \sdram_bankmachine1_row_hit $eq$ls180.v:2099$159_Y
connect \sdram_bankmachine1_cmd_payload_ba 2'01
- connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2096$163_Y
- connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2097$165_Y
- connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2098$167_Y
+ connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2109$164_Y
+ connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2110$166_Y
+ connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2111$168_Y
connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout
connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable
connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr
connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \sdram_bankmachine1_cmd_buffer_lookahead_source_ready
connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din
- connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2130$175_Y
- connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2131$176_Y
+ connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2143$176_Y
+ connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2144$177_Y
connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine1_cmd_buffer_lookahead_consume
connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r
- connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2134$177_Y
- connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2135$178_Y
- connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2136$180_Y
+ connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2147$178_Y
+ connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2148$179_Y
+ connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2149$181_Y
connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \sdram_bankmachine2_req_valid
connect \sdram_bankmachine2_req_ready \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready
connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine2_req_we
connect \sdram_bankmachine2_cmd_buffer_sink_last \sdram_bankmachine2_cmd_buffer_lookahead_source_last
connect \sdram_bankmachine2_cmd_buffer_sink_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we
connect \sdram_bankmachine2_cmd_buffer_sink_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr
- connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2241$186_Y
- connect \sdram_bankmachine2_req_lock $or$ls180.v:2242$187_Y
- connect \sdram_bankmachine2_row_hit $eq$ls180.v:2243$188_Y
+ connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2254$187_Y
+ connect \sdram_bankmachine2_req_lock $or$ls180.v:2255$188_Y
+ connect \sdram_bankmachine2_row_hit $eq$ls180.v:2256$189_Y
connect \sdram_bankmachine2_cmd_payload_ba 2'10
- connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2253$193_Y
- connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2254$195_Y
- connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2255$197_Y
+ connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2266$194_Y
+ connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2267$196_Y
+ connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2268$198_Y
connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout
connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable
connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr
connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \sdram_bankmachine2_cmd_buffer_lookahead_source_ready
connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din
- connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2287$205_Y
- connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2288$206_Y
+ connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2300$206_Y
+ connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2301$207_Y
connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine2_cmd_buffer_lookahead_consume
connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r
- connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2291$207_Y
- connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2292$208_Y
- connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2293$210_Y
+ connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2304$208_Y
+ connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2305$209_Y
+ connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2306$211_Y
connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \sdram_bankmachine3_req_valid
connect \sdram_bankmachine3_req_ready \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready
connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine3_req_we
connect \sdram_bankmachine3_cmd_buffer_sink_last \sdram_bankmachine3_cmd_buffer_lookahead_source_last
connect \sdram_bankmachine3_cmd_buffer_sink_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we
connect \sdram_bankmachine3_cmd_buffer_sink_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr
- connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2398$216_Y
- connect \sdram_bankmachine3_req_lock $or$ls180.v:2399$217_Y
- connect \sdram_bankmachine3_row_hit $eq$ls180.v:2400$218_Y
+ connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2411$217_Y
+ connect \sdram_bankmachine3_req_lock $or$ls180.v:2412$218_Y
+ connect \sdram_bankmachine3_row_hit $eq$ls180.v:2413$219_Y
connect \sdram_bankmachine3_cmd_payload_ba 2'11
- connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2410$223_Y
- connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2411$225_Y
- connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2412$227_Y
+ connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2423$224_Y
+ connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2424$226_Y
+ connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2425$228_Y
connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we }
connect { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout
connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable
connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr
connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \sdram_bankmachine3_cmd_buffer_lookahead_source_ready
connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din
- connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2444$235_Y
- connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2445$236_Y
+ connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2457$236_Y
+ connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2458$237_Y
connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine3_cmd_buffer_lookahead_consume
connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r
- connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2448$237_Y
- connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2449$238_Y
- connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2450$240_Y
+ connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2461$238_Y
+ connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2462$239_Y
+ connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2463$241_Y
connect \sdram_choose_req_want_cmds 1'1
- connect \sdram_trrdcon_valid $and$ls180.v:2546$251_Y
- connect \sdram_tfawcon_valid $and$ls180.v:2547$257_Y
- connect \sdram_ras_allowed $and$ls180.v:2548$258_Y
- connect \sdram_tccdcon_valid $and$ls180.v:2549$261_Y
+ connect \sdram_trrdcon_valid $and$ls180.v:2559$252_Y
+ connect \sdram_tfawcon_valid $and$ls180.v:2560$258_Y
+ connect \sdram_ras_allowed $and$ls180.v:2561$259_Y
+ connect \sdram_tccdcon_valid $and$ls180.v:2562$262_Y
connect \sdram_cas_allowed \sdram_tccdcon_ready
- connect \sdram_twtrcon_valid $and$ls180.v:2551$263_Y
- connect \sdram_read_available $or$ls180.v:2552$270_Y
- connect \sdram_write_available $or$ls180.v:2553$277_Y
- connect \sdram_max_time0 $eq$ls180.v:2554$278_Y
- connect \sdram_max_time1 $eq$ls180.v:2555$279_Y
+ connect \sdram_twtrcon_valid $and$ls180.v:2564$264_Y
+ connect \sdram_read_available $or$ls180.v:2565$271_Y
+ connect \sdram_write_available $or$ls180.v:2566$278_Y
+ connect \sdram_max_time0 $eq$ls180.v:2567$279_Y
+ connect \sdram_max_time1 $eq$ls180.v:2568$280_Y
connect \sdram_bankmachine0_refresh_req \sdram_cmd_valid
connect \sdram_bankmachine1_refresh_req \sdram_cmd_valid
connect \sdram_bankmachine2_refresh_req \sdram_cmd_valid
connect \sdram_bankmachine3_refresh_req \sdram_cmd_valid
- connect \sdram_go_to_refresh $and$ls180.v:2560$282_Y
+ connect \sdram_go_to_refresh $and$ls180.v:2573$283_Y
connect \sdram_interface_rdata \sdram_dfi_p0_rddata
connect \sdram_dfi_p0_wrdata \sdram_interface_wdata
- connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2563$283_Y
+ connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2576$284_Y
connect \sdram_choose_cmd_request \sdram_choose_cmd_valids
connect \sdram_choose_cmd_cmd_valid \rhs_array_muxed0
connect \sdram_choose_cmd_cmd_payload_a \rhs_array_muxed1
connect \sdram_choose_cmd_cmd_payload_is_read \rhs_array_muxed3
connect \sdram_choose_cmd_cmd_payload_is_write \rhs_array_muxed4
connect \sdram_choose_cmd_cmd_payload_is_cmd \rhs_array_muxed5
- connect \sdram_choose_cmd_ce $or$ls180.v:2596$341_Y
+ connect \sdram_choose_cmd_ce $or$ls180.v:2609$342_Y
connect \sdram_choose_req_request \sdram_choose_req_valids
connect \sdram_choose_req_cmd_valid \rhs_array_muxed6
connect \sdram_choose_req_cmd_payload_a \rhs_array_muxed7
connect \sdram_choose_req_cmd_payload_is_read \rhs_array_muxed9
connect \sdram_choose_req_cmd_payload_is_write \rhs_array_muxed10
connect \sdram_choose_req_cmd_payload_is_cmd \rhs_array_muxed11
- connect \sdram_choose_req_ce $or$ls180.v:2665$427_Y
+ connect \sdram_choose_req_ce $or$ls180.v:2678$428_Y
connect \sdram_dfi_p0_reset_n 1'1
connect \sdram_dfi_p0_cke \sdram_steerer0
connect \sdram_dfi_p0_odt \sdram_steerer1
- connect \subfragments_roundrobin0_request $and$ls180.v:2742$459_Y
- connect \subfragments_roundrobin0_ce $and$ls180.v:2743$462_Y
+ connect \subfragments_roundrobin0_request $and$ls180.v:2755$460_Y
+ connect \subfragments_roundrobin0_ce $and$ls180.v:2756$463_Y
connect \sdram_interface_bank0_addr \rhs_array_muxed12
connect \sdram_interface_bank0_we \rhs_array_muxed13
connect \sdram_interface_bank0_valid \rhs_array_muxed14
- connect \subfragments_roundrobin1_request $and$ls180.v:2747$475_Y
- connect \subfragments_roundrobin1_ce $and$ls180.v:2748$478_Y
+ connect \subfragments_roundrobin1_request $and$ls180.v:2760$476_Y
+ connect \subfragments_roundrobin1_ce $and$ls180.v:2761$479_Y
connect \sdram_interface_bank1_addr \rhs_array_muxed15
connect \sdram_interface_bank1_we \rhs_array_muxed16
connect \sdram_interface_bank1_valid \rhs_array_muxed17
- connect \subfragments_roundrobin2_request $and$ls180.v:2752$491_Y
- connect \subfragments_roundrobin2_ce $and$ls180.v:2753$494_Y
+ connect \subfragments_roundrobin2_request $and$ls180.v:2765$492_Y
+ connect \subfragments_roundrobin2_ce $and$ls180.v:2766$495_Y
connect \sdram_interface_bank2_addr \rhs_array_muxed18
connect \sdram_interface_bank2_we \rhs_array_muxed19
connect \sdram_interface_bank2_valid \rhs_array_muxed20
- connect \subfragments_roundrobin3_request $and$ls180.v:2757$507_Y
- connect \subfragments_roundrobin3_ce $and$ls180.v:2758$510_Y
+ connect \subfragments_roundrobin3_request $and$ls180.v:2770$508_Y
+ connect \subfragments_roundrobin3_ce $and$ls180.v:2771$511_Y
connect \sdram_interface_bank3_addr \rhs_array_muxed21
connect \sdram_interface_bank3_we \rhs_array_muxed22
connect \sdram_interface_bank3_valid \rhs_array_muxed23
- connect \port_cmd_ready $or$ls180.v:2762$574_Y
+ connect \port_cmd_ready $or$ls180.v:2775$575_Y
connect \port_wdata_ready \subfragments_new_master_wdata_ready
connect \port_rdata_valid \subfragments_new_master_rdata_valid3
connect \port_rdata_payload_data \sdram_interface_rdata
connect \subfragments_roundrobin1_grant 1'0
connect \subfragments_roundrobin2_grant 1'0
connect \subfragments_roundrobin3_grant 1'0
- connect \converter_reset $not$ls180.v:2784$576_Y
+ connect \converter_reset $not$ls180.v:2797$577_Y
connect \wb_sdram_dat_r { \litedram_wb_dat_r \converter_dat_r [31:16] }
- connect \port_cmd_payload_addr $sub$ls180.v:2844$587_Y [23:0]
+ connect \port_cmd_payload_addr $sub$ls180.v:2857$588_Y [23:0]
connect \port_cmd_payload_we \litedram_wb_we
connect \port_wdata_payload_data \litedram_wb_dat_w
connect \port_wdata_payload_we \litedram_wb_sel
connect \litedram_wb_dat_r \port_rdata_payload_data
- connect \port_flush $not$ls180.v:2849$588_Y
- connect \port_cmd_last $not$ls180.v:2850$589_Y
- connect \port_cmd_valid $and$ls180.v:2851$592_Y
- connect \port_wdata_valid $and$ls180.v:2852$596_Y
- connect \port_rdata_ready $and$ls180.v:2853$599_Y
- connect \litedram_wb_ack $and$ls180.v:2854$604_Y
- connect \ack_cmd $or$ls180.v:2855$606_Y
- connect \ack_wdata $or$ls180.v:2856$608_Y
- connect \ack_rdata $and$ls180.v:2857$609_Y
+ connect \port_flush $not$ls180.v:2862$589_Y
+ connect \port_cmd_last $not$ls180.v:2863$590_Y
+ connect \port_cmd_valid $and$ls180.v:2864$593_Y
+ connect \port_wdata_valid $and$ls180.v:2865$597_Y
+ connect \port_rdata_ready $and$ls180.v:2866$600_Y
+ connect \litedram_wb_ack $and$ls180.v:2867$605_Y
+ connect \ack_cmd $or$ls180.v:2868$607_Y
+ connect \ack_wdata $or$ls180.v:2869$609_Y
+ connect \ack_rdata $and$ls180.v:2870$610_Y
connect \uart_sink_valid \uart_phy_source_valid
connect \uart_phy_source_ready \uart_sink_ready
connect \uart_sink_first \uart_phy_source_first
connect \uart_phy_sink_payload_data \uart_source_payload_data
connect \tx_fifo_sink_valid \rxtx_re
connect \tx_fifo_sink_payload_data \rxtx_r
- connect \txfull_status $not$ls180.v:2870$610_Y
- connect \txempty_status $not$ls180.v:2871$611_Y
+ connect \txfull_status $not$ls180.v:2883$611_Y
+ connect \txempty_status $not$ls180.v:2884$612_Y
connect \uart_source_valid \tx_fifo_source_valid
connect \tx_fifo_source_ready \uart_source_ready
connect \uart_source_first \tx_fifo_source_first
connect \uart_source_last \tx_fifo_source_last
connect \uart_source_payload_data \tx_fifo_source_payload_data
- connect \tx_trigger $not$ls180.v:2877$612_Y
+ connect \tx_trigger $not$ls180.v:2890$613_Y
connect \rx_fifo_sink_valid \uart_sink_valid
connect \uart_sink_ready \rx_fifo_sink_ready
connect \rx_fifo_sink_first \uart_sink_first
connect \rx_fifo_sink_last \uart_sink_last
connect \rx_fifo_sink_payload_data \uart_sink_payload_data
- connect \rxempty_status $not$ls180.v:2883$613_Y
- connect \rxfull_status $not$ls180.v:2884$614_Y
+ connect \rxempty_status $not$ls180.v:2896$614_Y
+ connect \rxfull_status $not$ls180.v:2897$615_Y
connect \rxtx_w \rx_fifo_source_payload_data
- connect \rx_fifo_source_ready $or$ls180.v:2886$616_Y
- connect \rx_trigger $not$ls180.v:2887$617_Y
- connect \irq $or$ls180.v:2910$626_Y
+ connect \rx_fifo_source_ready $or$ls180.v:2899$617_Y
+ connect \rx_trigger $not$ls180.v:2900$618_Y
+ connect \irq $or$ls180.v:2923$627_Y
connect \tx_status \tx_trigger
connect \rx_status \rx_trigger
connect \tx_fifo_syncfifo_din { \tx_fifo_fifo_in_last \tx_fifo_fifo_in_first \tx_fifo_fifo_in_payload_data }
connect \tx_fifo_source_last \tx_fifo_fifo_out_last
connect \tx_fifo_source_payload_data \tx_fifo_fifo_out_payload_data
connect \tx_fifo_re \tx_fifo_source_ready
- connect \tx_fifo_syncfifo_re $and$ls180.v:2925$629_Y
- connect \tx_fifo_level1 $add$ls180.v:2926$630_Y
+ connect \tx_fifo_syncfifo_re $and$ls180.v:2938$630_Y
+ connect \tx_fifo_level1 $add$ls180.v:2939$631_Y
connect \tx_fifo_wrport_dat_w \tx_fifo_syncfifo_din
- connect \tx_fifo_wrport_we $and$ls180.v:2936$634_Y
- connect \tx_fifo_do_read $and$ls180.v:2937$635_Y
+ connect \tx_fifo_wrport_we $and$ls180.v:2949$635_Y
+ connect \tx_fifo_do_read $and$ls180.v:2950$636_Y
connect \tx_fifo_rdport_adr \tx_fifo_consume
connect \tx_fifo_syncfifo_dout \tx_fifo_rdport_dat_r
connect \tx_fifo_rdport_re \tx_fifo_do_read
- connect \tx_fifo_syncfifo_writable $ne$ls180.v:2941$636_Y
- connect \tx_fifo_syncfifo_readable $ne$ls180.v:2942$637_Y
+ connect \tx_fifo_syncfifo_writable $ne$ls180.v:2954$637_Y
+ connect \tx_fifo_syncfifo_readable $ne$ls180.v:2955$638_Y
connect \rx_fifo_syncfifo_din { \rx_fifo_fifo_in_last \rx_fifo_fifo_in_first \rx_fifo_fifo_in_payload_data }
connect { \rx_fifo_fifo_out_last \rx_fifo_fifo_out_first \rx_fifo_fifo_out_payload_data } \rx_fifo_syncfifo_dout
connect \rx_fifo_sink_ready \rx_fifo_syncfifo_writable
connect \rx_fifo_source_last \rx_fifo_fifo_out_last
connect \rx_fifo_source_payload_data \rx_fifo_fifo_out_payload_data
connect \rx_fifo_re \rx_fifo_source_ready
- connect \rx_fifo_syncfifo_re $and$ls180.v:2955$640_Y
- connect \rx_fifo_level1 $add$ls180.v:2956$641_Y
+ connect \rx_fifo_syncfifo_re $and$ls180.v:2968$641_Y
+ connect \rx_fifo_level1 $add$ls180.v:2969$642_Y
connect \rx_fifo_wrport_dat_w \rx_fifo_syncfifo_din
- connect \rx_fifo_wrport_we $and$ls180.v:2966$645_Y
- connect \rx_fifo_do_read $and$ls180.v:2967$646_Y
+ connect \rx_fifo_wrport_we $and$ls180.v:2979$646_Y
+ connect \rx_fifo_do_read $and$ls180.v:2980$647_Y
connect \rx_fifo_rdport_adr \rx_fifo_consume
connect \rx_fifo_syncfifo_dout \rx_fifo_rdport_dat_r
connect \rx_fifo_rdport_re \rx_fifo_do_read
- connect \rx_fifo_syncfifo_writable $ne$ls180.v:2971$647_Y
- connect \rx_fifo_syncfifo_readable $ne$ls180.v:2972$648_Y
- connect \libresocsim_libresoc_constraintmanager_obj_i2c_scl \i2c_scl_1
- connect \libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe \i2c_oe
- connect \libresocsim_libresoc_constraintmanager_obj_i2c_sda_o \i2c_sda0
- connect \i2c_sda1 \libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
+ connect \rx_fifo_syncfifo_writable $ne$ls180.v:2984$648_Y
+ connect \rx_fifo_syncfifo_readable $ne$ls180.v:2985$649_Y
+ connect \libresocsim_libresoc_constraintmanager_i2c_scl \i2c_scl_1
+ connect \libresocsim_libresoc_constraintmanager_i2c_sda_oe \i2c_oe
+ connect \libresocsim_libresoc_constraintmanager_i2c_sda_o \i2c_sda0
+ connect \i2c_sda1 \libresocsim_libresoc_constraintmanager_i2c_sda_i
connect \libresocsim_shared_adr { 1'0 \rhs_array_muxed24 }
connect \libresocsim_shared_dat_w \rhs_array_muxed25 [31:0]
connect \libresocsim_shared_sel \rhs_array_muxed26 [3:0]
connect \libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r }
connect \libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r }
connect \libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r }
- connect \libresocsim_libresoc_ibus_ack $and$ls180.v:3085$658_Y
- connect \libresocsim_libresoc_dbus_ack $and$ls180.v:3086$660_Y
- connect \libresocsim_libresoc_jtag_wb_ack $and$ls180.v:3087$662_Y
- connect \libresocsim_libresoc_ibus_err $and$ls180.v:3088$664_Y
- connect \libresocsim_libresoc_dbus_err $and$ls180.v:3089$666_Y
- connect \libresocsim_libresoc_jtag_wb_err $and$ls180.v:3090$668_Y
+ connect \libresocsim_libresoc_ibus_ack $and$ls180.v:3098$659_Y
+ connect \libresocsim_libresoc_dbus_ack $and$ls180.v:3099$661_Y
+ connect \libresocsim_libresoc_jtag_wb_ack $and$ls180.v:3100$663_Y
+ connect \libresocsim_libresoc_ibus_err $and$ls180.v:3101$665_Y
+ connect \libresocsim_libresoc_dbus_err $and$ls180.v:3102$667_Y
+ connect \libresocsim_libresoc_jtag_wb_err $and$ls180.v:3103$669_Y
connect \libresocsim_request { \libresocsim_libresoc_jtag_wb_cyc \libresocsim_libresoc_dbus_cyc \libresocsim_libresoc_ibus_cyc }
connect \libresocsim_ram_bus_adr \libresocsim_shared_adr
connect \libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w }
connect \libresocsim_libresocsim_converted_interface_we \libresocsim_shared_we
connect \libresocsim_libresocsim_converted_interface_cti \libresocsim_shared_cti
connect \libresocsim_libresocsim_converted_interface_bte \libresocsim_shared_bte
- connect \libresocsim_ram_bus_cyc $and$ls180.v:3143$676_Y
- connect \ram_bus_ram_bus_cyc $and$ls180.v:3144$677_Y
- connect \interface0_converted_interface_cyc $and$ls180.v:3145$678_Y
- connect \interface1_converted_interface_cyc $and$ls180.v:3146$679_Y
- connect \socbushandler_converted_interface_cyc $and$ls180.v:3147$680_Y
- connect \libresocsim_libresocsim_converted_interface_cyc $and$ls180.v:3148$681_Y
- connect \libresocsim_shared_err $or$ls180.v:3149$686_Y
- connect \libresocsim_wait $and$ls180.v:3150$689_Y
- connect \libresocsim_done $eq$ls180.v:3163$707_Y
- connect \libresocsim_csrbank0_sel $eq$ls180.v:3164$708_Y
+ connect \libresocsim_ram_bus_cyc $and$ls180.v:3156$677_Y
+ connect \ram_bus_ram_bus_cyc $and$ls180.v:3157$678_Y
+ connect \interface0_converted_interface_cyc $and$ls180.v:3158$679_Y
+ connect \interface1_converted_interface_cyc $and$ls180.v:3159$680_Y
+ connect \socbushandler_converted_interface_cyc $and$ls180.v:3160$681_Y
+ connect \libresocsim_libresocsim_converted_interface_cyc $and$ls180.v:3161$682_Y
+ connect \libresocsim_shared_err $or$ls180.v:3162$687_Y
+ connect \libresocsim_wait $and$ls180.v:3163$690_Y
+ connect \libresocsim_done $eq$ls180.v:3176$708_Y
+ connect \libresocsim_csrbank0_sel $eq$ls180.v:3177$709_Y
connect \libresocsim_csrbank0_reset0_r \libresocsim_interface0_bank_bus_dat_w [0]
- connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3166$711_Y
- connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3167$715_Y
+ connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3179$712_Y
+ connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3180$716_Y
connect \libresocsim_csrbank0_scratch3_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3169$718_Y
- connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3170$722_Y
+ connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3182$719_Y
+ connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3183$723_Y
connect \libresocsim_csrbank0_scratch2_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3172$725_Y
- connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3173$729_Y
+ connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3185$726_Y
+ connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3186$730_Y
connect \libresocsim_csrbank0_scratch1_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3175$732_Y
- connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3176$736_Y
+ connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3188$733_Y
+ connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3189$737_Y
connect \libresocsim_csrbank0_scratch0_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3178$739_Y
- connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3179$743_Y
+ connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3191$740_Y
+ connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3192$744_Y
connect \libresocsim_csrbank0_bus_errors3_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3181$746_Y
- connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3182$750_Y
+ connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3194$747_Y
+ connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3195$751_Y
connect \libresocsim_csrbank0_bus_errors2_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3184$753_Y
- connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3185$757_Y
+ connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3197$754_Y
+ connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3198$758_Y
connect \libresocsim_csrbank0_bus_errors1_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3187$760_Y
- connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3188$764_Y
+ connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3200$761_Y
+ connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3201$765_Y
connect \libresocsim_csrbank0_bus_errors0_r \libresocsim_interface0_bank_bus_dat_w
- connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3190$767_Y
- connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3191$771_Y
+ connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3203$768_Y
+ connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3204$772_Y
connect \libresocsim_csrbank0_reset0_w \libresocsim_reset_storage
connect \libresocsim_csrbank0_scratch3_w \libresocsim_scratch_storage [31:24]
connect \libresocsim_csrbank0_scratch2_w \libresocsim_scratch_storage [23:16]
connect \libresocsim_csrbank0_bus_errors1_w \libresocsim_bus_errors_status [15:8]
connect \libresocsim_csrbank0_bus_errors0_w \libresocsim_bus_errors_status [7:0]
connect \libresocsim_bus_errors_we \libresocsim_csrbank0_bus_errors0_we
- connect \libresocsim_csrbank1_sel $eq$ls180.v:3202$772_Y
+ connect \libresocsim_csrbank1_sel $eq$ls180.v:3215$773_Y
connect \libresocsim_csrbank1_oe0_r \libresocsim_interface1_bank_bus_dat_w
- connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3204$775_Y
- connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3205$779_Y
+ connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3217$776_Y
+ connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3218$780_Y
connect \libresocsim_csrbank1_in_r \libresocsim_interface1_bank_bus_dat_w
- connect \libresocsim_csrbank1_in_re $and$ls180.v:3207$782_Y
- connect \libresocsim_csrbank1_in_we $and$ls180.v:3208$786_Y
+ connect \libresocsim_csrbank1_in_re $and$ls180.v:3220$783_Y
+ connect \libresocsim_csrbank1_in_we $and$ls180.v:3221$787_Y
connect \libresocsim_csrbank1_out0_r \libresocsim_interface1_bank_bus_dat_w
- connect \libresocsim_csrbank1_out0_re $and$ls180.v:3210$789_Y
- connect \libresocsim_csrbank1_out0_we $and$ls180.v:3211$793_Y
+ connect \libresocsim_csrbank1_out0_re $and$ls180.v:3223$790_Y
+ connect \libresocsim_csrbank1_out0_we $and$ls180.v:3224$794_Y
connect \libresocsim_csrbank1_oe0_w \gpio0_oe_storage
connect \libresocsim_csrbank1_in_w \gpio0_status
connect \gpio0_we \libresocsim_csrbank1_in_we
connect \libresocsim_csrbank1_out0_w \gpio0_out_storage
- connect \libresocsim_csrbank2_sel $eq$ls180.v:3216$794_Y
+ connect \libresocsim_csrbank2_sel $eq$ls180.v:3229$795_Y
connect \libresocsim_csrbank2_oe0_r \libresocsim_interface2_bank_bus_dat_w
- connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3218$797_Y
- connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3219$801_Y
+ connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3231$798_Y
+ connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3232$802_Y
connect \libresocsim_csrbank2_in_r \libresocsim_interface2_bank_bus_dat_w
- connect \libresocsim_csrbank2_in_re $and$ls180.v:3221$804_Y
- connect \libresocsim_csrbank2_in_we $and$ls180.v:3222$808_Y
+ connect \libresocsim_csrbank2_in_re $and$ls180.v:3234$805_Y
+ connect \libresocsim_csrbank2_in_we $and$ls180.v:3235$809_Y
connect \libresocsim_csrbank2_out0_r \libresocsim_interface2_bank_bus_dat_w
- connect \libresocsim_csrbank2_out0_re $and$ls180.v:3224$811_Y
- connect \libresocsim_csrbank2_out0_we $and$ls180.v:3225$815_Y
+ connect \libresocsim_csrbank2_out0_re $and$ls180.v:3237$812_Y
+ connect \libresocsim_csrbank2_out0_we $and$ls180.v:3238$816_Y
connect \libresocsim_csrbank2_oe0_w \gpio1_oe_storage
connect \libresocsim_csrbank2_in_w \gpio1_status
connect \gpio1_we \libresocsim_csrbank2_in_we
connect \libresocsim_csrbank2_out0_w \gpio1_out_storage
- connect \libresocsim_csrbank3_sel $eq$ls180.v:3230$816_Y
+ connect \libresocsim_csrbank3_sel $eq$ls180.v:3243$817_Y
connect \libresocsim_csrbank3_w0_r \libresocsim_interface3_bank_bus_dat_w [2:0]
- connect \libresocsim_csrbank3_w0_re $and$ls180.v:3232$819_Y
- connect \libresocsim_csrbank3_w0_we $and$ls180.v:3233$823_Y
+ connect \libresocsim_csrbank3_w0_re $and$ls180.v:3245$820_Y
+ connect \libresocsim_csrbank3_w0_we $and$ls180.v:3246$824_Y
connect \libresocsim_csrbank3_r_r \libresocsim_interface3_bank_bus_dat_w [0]
- connect \libresocsim_csrbank3_r_re $and$ls180.v:3235$826_Y
- connect \libresocsim_csrbank3_r_we $and$ls180.v:3236$830_Y
+ connect \libresocsim_csrbank3_r_re $and$ls180.v:3248$827_Y
+ connect \libresocsim_csrbank3_r_we $and$ls180.v:3249$831_Y
connect \i2c_scl_1 \i2c_storage [0]
connect \i2c_oe \i2c_storage [1]
connect \i2c_sda0 \i2c_storage [2]
connect \i2c_status \i2c_sda1
connect \libresocsim_csrbank3_r_w \i2c_status
connect \i2c_we \libresocsim_csrbank3_r_we
- connect \libresocsim_csrbank4_sel $eq$ls180.v:3244$831_Y
+ connect \libresocsim_csrbank4_sel $eq$ls180.v:3257$832_Y
connect \libresocsim_csrbank4_dfii_control0_r \libresocsim_interface4_bank_bus_dat_w [3:0]
- connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3246$834_Y
- connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3247$838_Y
+ connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3259$835_Y
+ connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3260$839_Y
connect \libresocsim_csrbank4_dfii_pi0_command0_r \libresocsim_interface4_bank_bus_dat_w [5:0]
- connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3249$841_Y
- connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3250$845_Y
+ connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3262$842_Y
+ connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3263$846_Y
connect \sdram_command_issue_r \libresocsim_interface4_bank_bus_dat_w [0]
- connect \sdram_command_issue_re $and$ls180.v:3252$848_Y
- connect \sdram_command_issue_we $and$ls180.v:3253$852_Y
+ connect \sdram_command_issue_re $and$ls180.v:3265$849_Y
+ connect \sdram_command_issue_we $and$ls180.v:3266$853_Y
connect \libresocsim_csrbank4_dfii_pi0_address1_r \libresocsim_interface4_bank_bus_dat_w [4:0]
- connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3255$855_Y
- connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3256$859_Y
+ connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3268$856_Y
+ connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3269$860_Y
connect \libresocsim_csrbank4_dfii_pi0_address0_r \libresocsim_interface4_bank_bus_dat_w
- connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3258$862_Y
- connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3259$866_Y
+ connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3271$863_Y
+ connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3272$867_Y
connect \libresocsim_csrbank4_dfii_pi0_baddress0_r \libresocsim_interface4_bank_bus_dat_w [1:0]
- connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3261$869_Y
- connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3262$873_Y
+ connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3274$870_Y
+ connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3275$874_Y
connect \libresocsim_csrbank4_dfii_pi0_wrdata1_r \libresocsim_interface4_bank_bus_dat_w
- connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3264$876_Y
- connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3265$880_Y
+ connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3277$877_Y
+ connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3278$881_Y
connect \libresocsim_csrbank4_dfii_pi0_wrdata0_r \libresocsim_interface4_bank_bus_dat_w
- connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3267$883_Y
- connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3268$887_Y
+ connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3280$884_Y
+ connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3281$888_Y
connect \libresocsim_csrbank4_dfii_pi0_rddata1_r \libresocsim_interface4_bank_bus_dat_w
- connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3270$890_Y
- connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3271$894_Y
+ connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3283$891_Y
+ connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3284$895_Y
connect \libresocsim_csrbank4_dfii_pi0_rddata0_r \libresocsim_interface4_bank_bus_dat_w
- connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3273$897_Y
- connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3274$901_Y
+ connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3286$898_Y
+ connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3287$902_Y
connect \sdram_sel \sdram_storage [0]
connect \sdram_cke_1 \sdram_storage [1]
connect \sdram_odt \sdram_storage [2]
connect \libresocsim_csrbank4_dfii_pi0_rddata1_w \sdram_status [15:8]
connect \libresocsim_csrbank4_dfii_pi0_rddata0_w \sdram_status [7:0]
connect \sdram_we \libresocsim_csrbank4_dfii_pi0_rddata0_we
- connect \libresocsim_csrbank5_sel $eq$ls180.v:3289$902_Y
+ connect \libresocsim_csrbank5_sel $eq$ls180.v:3302$903_Y
connect \libresocsim_csrbank5_load3_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_load3_re $and$ls180.v:3291$905_Y
- connect \libresocsim_csrbank5_load3_we $and$ls180.v:3292$909_Y
+ connect \libresocsim_csrbank5_load3_re $and$ls180.v:3304$906_Y
+ connect \libresocsim_csrbank5_load3_we $and$ls180.v:3305$910_Y
connect \libresocsim_csrbank5_load2_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_load2_re $and$ls180.v:3294$912_Y
- connect \libresocsim_csrbank5_load2_we $and$ls180.v:3295$916_Y
+ connect \libresocsim_csrbank5_load2_re $and$ls180.v:3307$913_Y
+ connect \libresocsim_csrbank5_load2_we $and$ls180.v:3308$917_Y
connect \libresocsim_csrbank5_load1_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_load1_re $and$ls180.v:3297$919_Y
- connect \libresocsim_csrbank5_load1_we $and$ls180.v:3298$923_Y
+ connect \libresocsim_csrbank5_load1_re $and$ls180.v:3310$920_Y
+ connect \libresocsim_csrbank5_load1_we $and$ls180.v:3311$924_Y
connect \libresocsim_csrbank5_load0_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_load0_re $and$ls180.v:3300$926_Y
- connect \libresocsim_csrbank5_load0_we $and$ls180.v:3301$930_Y
+ connect \libresocsim_csrbank5_load0_re $and$ls180.v:3313$927_Y
+ connect \libresocsim_csrbank5_load0_we $and$ls180.v:3314$931_Y
connect \libresocsim_csrbank5_reload3_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3303$933_Y
- connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3304$937_Y
+ connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3316$934_Y
+ connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3317$938_Y
connect \libresocsim_csrbank5_reload2_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3306$940_Y
- connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3307$944_Y
+ connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3319$941_Y
+ connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3320$945_Y
connect \libresocsim_csrbank5_reload1_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3309$947_Y
- connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3310$951_Y
+ connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3322$948_Y
+ connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3323$952_Y
connect \libresocsim_csrbank5_reload0_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3312$954_Y
- connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3313$958_Y
+ connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3325$955_Y
+ connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3326$959_Y
connect \libresocsim_csrbank5_en0_r \libresocsim_interface5_bank_bus_dat_w [0]
- connect \libresocsim_csrbank5_en0_re $and$ls180.v:3315$961_Y
- connect \libresocsim_csrbank5_en0_we $and$ls180.v:3316$965_Y
+ connect \libresocsim_csrbank5_en0_re $and$ls180.v:3328$962_Y
+ connect \libresocsim_csrbank5_en0_we $and$ls180.v:3329$966_Y
connect \libresocsim_csrbank5_update_value0_r \libresocsim_interface5_bank_bus_dat_w [0]
- connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3318$968_Y
- connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3319$972_Y
+ connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3331$969_Y
+ connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3332$973_Y
connect \libresocsim_csrbank5_value3_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_value3_re $and$ls180.v:3321$975_Y
- connect \libresocsim_csrbank5_value3_we $and$ls180.v:3322$979_Y
+ connect \libresocsim_csrbank5_value3_re $and$ls180.v:3334$976_Y
+ connect \libresocsim_csrbank5_value3_we $and$ls180.v:3335$980_Y
connect \libresocsim_csrbank5_value2_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_value2_re $and$ls180.v:3324$982_Y
- connect \libresocsim_csrbank5_value2_we $and$ls180.v:3325$986_Y
+ connect \libresocsim_csrbank5_value2_re $and$ls180.v:3337$983_Y
+ connect \libresocsim_csrbank5_value2_we $and$ls180.v:3338$987_Y
connect \libresocsim_csrbank5_value1_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_value1_re $and$ls180.v:3327$989_Y
- connect \libresocsim_csrbank5_value1_we $and$ls180.v:3328$993_Y
+ connect \libresocsim_csrbank5_value1_re $and$ls180.v:3340$990_Y
+ connect \libresocsim_csrbank5_value1_we $and$ls180.v:3341$994_Y
connect \libresocsim_csrbank5_value0_r \libresocsim_interface5_bank_bus_dat_w
- connect \libresocsim_csrbank5_value0_re $and$ls180.v:3330$996_Y
- connect \libresocsim_csrbank5_value0_we $and$ls180.v:3331$1000_Y
+ connect \libresocsim_csrbank5_value0_re $and$ls180.v:3343$997_Y
+ connect \libresocsim_csrbank5_value0_we $and$ls180.v:3344$1001_Y
connect \libresocsim_eventmanager_status_r \libresocsim_interface5_bank_bus_dat_w [0]
- connect \libresocsim_eventmanager_status_re $and$ls180.v:3333$1003_Y
- connect \libresocsim_eventmanager_status_we $and$ls180.v:3334$1007_Y
+ connect \libresocsim_eventmanager_status_re $and$ls180.v:3346$1004_Y
+ connect \libresocsim_eventmanager_status_we $and$ls180.v:3347$1008_Y
connect \libresocsim_eventmanager_pending_r \libresocsim_interface5_bank_bus_dat_w [0]
- connect \libresocsim_eventmanager_pending_re $and$ls180.v:3336$1010_Y
- connect \libresocsim_eventmanager_pending_we $and$ls180.v:3337$1014_Y
+ connect \libresocsim_eventmanager_pending_re $and$ls180.v:3349$1011_Y
+ connect \libresocsim_eventmanager_pending_we $and$ls180.v:3350$1015_Y
connect \libresocsim_csrbank5_ev_enable0_r \libresocsim_interface5_bank_bus_dat_w [0]
- connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3339$1017_Y
- connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3340$1021_Y
+ connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3352$1018_Y
+ connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3353$1022_Y
connect \libresocsim_csrbank5_load3_w \libresocsim_load_storage [31:24]
connect \libresocsim_csrbank5_load2_w \libresocsim_load_storage [23:16]
connect \libresocsim_csrbank5_load1_w \libresocsim_load_storage [15:8]
connect \libresocsim_csrbank5_value0_w \libresocsim_value_status [7:0]
connect \libresocsim_value_we \libresocsim_csrbank5_value0_we
connect \libresocsim_csrbank5_ev_enable0_w \libresocsim_eventmanager_storage
- connect \libresocsim_csrbank6_sel $eq$ls180.v:3357$1022_Y
+ connect \libresocsim_csrbank6_sel $eq$ls180.v:3370$1023_Y
connect \rxtx_r \libresocsim_interface6_bank_bus_dat_w
- connect \rxtx_re $and$ls180.v:3359$1025_Y
- connect \rxtx_we $and$ls180.v:3360$1029_Y
+ connect \rxtx_re $and$ls180.v:3372$1026_Y
+ connect \rxtx_we $and$ls180.v:3373$1030_Y
connect \libresocsim_csrbank6_txfull_r \libresocsim_interface6_bank_bus_dat_w [0]
- connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3362$1032_Y
- connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3363$1036_Y
+ connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3375$1033_Y
+ connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3376$1037_Y
connect \libresocsim_csrbank6_rxempty_r \libresocsim_interface6_bank_bus_dat_w [0]
- connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3365$1039_Y
- connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3366$1043_Y
+ connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3378$1040_Y
+ connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3379$1044_Y
connect \eventmanager_status_r \libresocsim_interface6_bank_bus_dat_w [1:0]
- connect \eventmanager_status_re $and$ls180.v:3368$1046_Y
- connect \eventmanager_status_we $and$ls180.v:3369$1050_Y
+ connect \eventmanager_status_re $and$ls180.v:3381$1047_Y
+ connect \eventmanager_status_we $and$ls180.v:3382$1051_Y
connect \eventmanager_pending_r \libresocsim_interface6_bank_bus_dat_w [1:0]
- connect \eventmanager_pending_re $and$ls180.v:3371$1053_Y
- connect \eventmanager_pending_we $and$ls180.v:3372$1057_Y
+ connect \eventmanager_pending_re $and$ls180.v:3384$1054_Y
+ connect \eventmanager_pending_we $and$ls180.v:3385$1058_Y
connect \libresocsim_csrbank6_ev_enable0_r \libresocsim_interface6_bank_bus_dat_w [1:0]
- connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3374$1060_Y
- connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3375$1064_Y
+ connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3387$1061_Y
+ connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3388$1065_Y
connect \libresocsim_csrbank6_txempty_r \libresocsim_interface6_bank_bus_dat_w [0]
- connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3377$1067_Y
- connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3378$1071_Y
+ connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3390$1068_Y
+ connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3391$1072_Y
connect \libresocsim_csrbank6_rxfull_r \libresocsim_interface6_bank_bus_dat_w [0]
- connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3380$1074_Y
- connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3381$1078_Y
+ connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3393$1075_Y
+ connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3394$1079_Y
connect \libresocsim_csrbank6_txfull_w \txfull_status
connect \txfull_we \libresocsim_csrbank6_txfull_we
connect \libresocsim_csrbank6_rxempty_w \rxempty_status
connect \txempty_we \libresocsim_csrbank6_txempty_we
connect \libresocsim_csrbank6_rxfull_w \rxfull_status
connect \rxfull_we \libresocsim_csrbank6_rxfull_we
- connect \libresocsim_csrbank7_sel $eq$ls180.v:3391$1079_Y
+ connect \libresocsim_csrbank7_sel $eq$ls180.v:3404$1080_Y
connect \libresocsim_csrbank7_tuning_word3_r \libresocsim_interface7_bank_bus_dat_w
- connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3393$1082_Y
- connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3394$1086_Y
+ connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3406$1083_Y
+ connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3407$1087_Y
connect \libresocsim_csrbank7_tuning_word2_r \libresocsim_interface7_bank_bus_dat_w
- connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3396$1089_Y
- connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3397$1093_Y
+ connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3409$1090_Y
+ connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3410$1094_Y
connect \libresocsim_csrbank7_tuning_word1_r \libresocsim_interface7_bank_bus_dat_w
- connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3399$1096_Y
- connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3400$1100_Y
+ connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3412$1097_Y
+ connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3413$1101_Y
connect \libresocsim_csrbank7_tuning_word0_r \libresocsim_interface7_bank_bus_dat_w
- connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3402$1103_Y
- connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3403$1107_Y
+ connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3415$1104_Y
+ connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3416$1108_Y
connect \libresocsim_csrbank7_tuning_word3_w \uart_phy_storage [31:24]
connect \libresocsim_csrbank7_tuning_word2_w \uart_phy_storage [23:16]
connect \libresocsim_csrbank7_tuning_word1_w \uart_phy_storage [15:8]
connect \libresocsim_interface5_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w
connect \libresocsim_interface6_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w
connect \libresocsim_interface7_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w
- connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3436$1114_Y
+ connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3449$1115_Y
connect \sdrio_clk \sys_clk_1
connect \sdrio_clk_1 \sys_clk_1
connect \sdrio_clk_2 \sys_clk_1
connect \sdrio_clk_101 \sys_clk_1
connect \sdrio_clk_102 \sys_clk_1
connect \sdrio_clk_103 \sys_clk_1
- connect \libresocsim_dat_r $memrd$\mem$ls180.v:5511$1508_DATA
- connect \ram_dat_r $memrd$\mem_1$ls180.v:5539$1558_DATA
+ connect \libresocsim_dat_r $memrd$\mem$ls180.v:5530$1515_DATA
+ connect \ram_dat_r $memrd$\mem_1$ls180.v:5558$1565_DATA
connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat
- connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5557$1568_DATA
+ connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5576$1575_DATA
connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1
- connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5571$1578_DATA
+ connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5590$1585_DATA
connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2
- connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5585$1588_DATA
+ connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5604$1595_DATA
connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3
- connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5599$1598_DATA
+ connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5618$1605_DATA
connect \tx_fifo_wrport_dat_r \memdat_4
connect \tx_fifo_rdport_dat_r \memdat_5
connect \rx_fifo_wrport_dat_r \memdat_6
projects / soclayout.git / commitdiff