rename design of experiments10 to match ls180 chip pads

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index 81d8ed7494de52bcfa082367c1112c40e243c649..7cbabb9d01f1c35d994caa8c81792d2e36c850c8 100644 (file)
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -1,7 +1,7 @@
 # generate add.il ilang file with: python3 add.py
 #
 
 # generate add.il ilang file with: python3 add.py
 #
 

-from nmigen import Elaboratable, Signal, Module
+from nmigen import Elaboratable, Signal, Module, Const, DomainRenamer

 from nmigen.cli import verilog
 
 # to get c4m-jtag
 from nmigen.cli import verilog
 
 # to get c4m-jtag


@@ -20,10 +20,10 @@ class ADD(Elaboratable):
 
         # set up JTAG
         self.jtag = TAP(ir_width=4)
 
         # set up JTAG
         self.jtag = TAP(ir_width=4)

-        self.jtag.bus.tck.name = 'tck'
-        self.jtag.bus.tms.name = 'tms'
-        self.jtag.bus.tdo.name = 'tdo'
-        self.jtag.bus.tdi.name = 'tdi'
+        self.jtag.bus.tck.name = 'jtag_tck'
+        self.jtag.bus.tms.name = 'jtag_tms'
+        self.jtag.bus.tdo.name = 'jtag_tdo'
+        self.jtag.bus.tdi.name = 'jtag_tdi'

 
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
 
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)


@@ -39,18 +39,19 @@ class ADD(Elaboratable):
 
         # do a simple "add"
         m.d.sync += self.f.eq(self.a + self.b)
 
         # do a simple "add"
         m.d.sync += self.f.eq(self.a + self.b)

+        m.d.sync += self.f[0].eq(Const(0, 1))

 
         return m
 
 
 
         return m
 
 

-def create_ilang(dut, ports, test_name):
+def create_verilog(dut, ports, test_name):

     vl = verilog.convert(dut, name=test_name, ports=ports)
     with open("%s.v" % test_name, "w") as f:
         f.write(vl)
 
 if __name__ == "__main__":
     vl = verilog.convert(dut, name=test_name, ports=ports)
     with open("%s.v" % test_name, "w") as f:
         f.write(vl)
 
 if __name__ == "__main__":

-    alu = ADD(width=4)
-    create_ilang(alu, [alu.a, alu.b, alu.f,
+    alu = DomainRenamer("sys")(ADD(width=4))
+    create_verilog(alu, [alu.a, alu.b, alu.f,

                        alu.jtag.bus.tck,
                         alu.jtag.bus.tms,
                         alu.jtag.bus.tdo,
                        alu.jtag.bus.tck,
                         alu.jtag.bus.tms,
                         alu.jtag.bus.tdo,

diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py
index ba1f2a3b46e09624a793551b618e86a14318efe5..ec538b8b540bfe6557083ae666ea468218b53f25 100644 (file)
--- a/experiments10_verilog/coriolis2/settings.py
+++ b/experiments10_verilog/coriolis2/settings.py
@@ -35,7 +35,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
     af  = CRL.AllianceFramework.get()
     env = af.getEnvironment()
     Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
     af  = CRL.AllianceFramework.get()
     env = af.getEnvironment()

-    env.setCLOCK( '^clk|^ck|^tck' )
+    env.setCLOCK( '^sys_clk|^ck|^tck' )

     env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib', mode=CRL.Environment.Prepend )
     env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
 print( '  o  Successfully run "<>/coriolis2/settings.py".' )
     env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib', mode=CRL.Environment.Prepend )
     env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
 print( '  o  Successfully run "<>/coriolis2/settings.py".' )

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index 4aa1e5f3c2f23c43b94bf483ac837ccd3a9c1b37..b60d198f47062e281963247f18c453993f80da73 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -44,18 +44,18 @@ def scriptMain ( **kw ):
          , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
          , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'     )
          , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'     )
          , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
          , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'     )
          , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'     )

-         , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'      )
-         , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'      )
+         , (IoPin.EAST , None, 'p_tms_0'    , 'jtag_tms'    , 'jtag_tms'      )
+         , (IoPin.EAST , None, 'p_tdo_0'    , 'jtag_tdo'    , 'jtag_tdo'      )

          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )

-         , (IoPin.EAST , None, 'p_clk'      , 'clk'    , 'clk'      )
-         , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'      )
-         , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'      )
+         , (IoPin.EAST , None, 'p_sys_clk'  , 'sys_clk'    , 'sys_clk'      )
+         , (IoPin.EAST , None, 'p_tck'      , 'jtag_tck'    , 'jtag_tck'      )
+         , (IoPin.EAST , None, 'p_tdi_0'    , 'jtag_tdi'    , 'jtag_tdi'      )

          , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
          , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
          , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'     )
          , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
          , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
          , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'     )

-         , (IoPin.NORTH, None, 'rst'        , 'rst'    , 'rst'      )
+         , (IoPin.NORTH, None, 'sys_rst'    , 'sys_rst'    , 'sys_rst'      )

          , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
          , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
          , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
          , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )

diff --git a/experiments9/Makefile b/experiments9/Makefile
index 04072327ded08b8317e39307ce416233dacb19bc..d714c77d8c6131e31b75100ebeab21f83b356206 100755 (executable)
--- a/experiments9/Makefile
+++ b/experiments9/Makefile
@@ -13,7 +13,7 @@
                 #VST_FLAGS = --vst-use-concat
 
                  #NETLISTS = $(shell cat cells.lst)
                 #VST_FLAGS = --vst-use-concat
 
                  #NETLISTS = $(shell cat cells.lst)

-                 NETLISTS = ls180
+                 NETLISTS = ls180 libresoc

 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
 
 
 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
 
 

diff --git a/experiments9/build_full.sh b/experiments9/build_full.sh
index 6a0221f4e2d6fa291274cd4fed2171e05b6e6ff6..e0e97dd32b562e8b14b598cc636056d14ea2d26b 100755 (executable)
--- a/experiments9/build_full.sh
+++ b/experiments9/build_full.sh
@@ -20,7 +20,16 @@ make clean
 rm *.vst *.ap
 
 # copies over a "full" core
 rm *.vst *.ap
 
 # copies over a "full" core

-cp non_generated/full_core_ls180.il ls180.il
+#cp non_generated/full_core_ls180.il ls180.il
+cp non_generated/ls180.v ls180.v
+cp non_generated/litex_ls180.v litex_ls180.v
+cp non_generated/libresoc.v libresoc.v
+touch mem.init
+touch mem_1.init
+touch mem_2.init
+touch mem_3.init
+touch mem_4.init
+touch mem_5.init

 
 # make the vst from ilang
 make vst
 
 # make the vst from ilang
 make vst