Adding CAM class. Yet incomplete
[soc.git] / TLB / CAM.py
1 from nmigen import Array, Module, Signal
2 from nmigen.lib.coding import Encoder
3 from nmigen.cli import main
4
5 from math import log
6
7 from CamEntry import CamEntry
8
9 class CAM():
10 def __init__(self, key_size, data_size, cam_size):
11 # Internal
12 entry_array = Array(CamEntry(key_size, data_size) for x in range(cam_size))
13 encoder_input = Signal(cam_size)
14
15 # Input
16 self.write = Signal(1)
17 self.key = Signal(key_size)
18 self.data_in = Signal(key_size)
19
20 # Output
21 self.data_match = Signal(1)
22 self.data_out = Signal(data_size)
23
24 def elaborate(self, platform):
25 m = Module()
26
27 m.d.submodules.encoder = encoder = Encoder(cam_size)
28
29 for index in range(cam_size):
30 m.d.sync += [
31 entry_array[index].write.eq(self.write),
32 entry_array[index].key_in.eq(self.key),
33 entry_array[index].data_in.eq(self.data_in),
34 encoder_input[index].eq(entry_array[index].match)
35 ]
36
37
38 m.d.sync += [
39 encoder.i.eq(encoder_input),
40 # 1. Read request
41 # 2. Write request
42 If(self.write == 0,
43 # 0 denotes a mapping was found
44 If(encoder.n == 0,
45 self.data_match.eq(0),
46 self.data_out.eq(entry_array[encoder.o].data)
47 ).Else(
48 self.data_match.eq(1)
49 )
50 ).Else(
51 # 0 denotes a mapping was found
52 If(encoder.n == 0,
53 self.data_match.eq(0),
54 entry_array[encoder.o].data_in.eq(self.data_in)
55 ).Else(
56 # LRU algorithm here
57 )
58 )
59
60 ]
61
62 return m
63