TLB/TLB.py

   1 from nmigen import Memory, Module, Signal
   2 from nmigen.cli import main
   3 from PermissionValidator import PermissionValidator
   4
   5 # The expected form of the data is
   6 # Item (Bits)
   7 # Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
   8
   9 class TLB():
  10     def __init__(self):
  11         # Inputs
  12         self.xwr = Signal(3) # Execute, Write, Read
  13         self.super = Signal(1) # Supervisor Mode
  14         self.super_access = Signal(1) # Supervisor Access
  15         self.command = Signal(2) # 00=None, 01=Search, 10=Write PTE, 11=Reset
  16         self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
  17         self.asid = Signal(15) # Address Space IDentifier (ASID)
  18         self.vma = Signal(36) # Virtual Memory Address (VMA)
  19         self.pte_in = Signal(64) # To be saved Page Table Entry (PTE)
  20
  21         # Outputs
  22         self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
  23         self.valid = Signal(1) # Denotes if the permissions are correct
  24         self.pteOut = Signal(64) # PTE that was mapped to by the VMA
  25
  26         # Cam simulations
  27         mem_l1 = Memory(113, 32) # L1 TLB cache
  28         read_port_l1 = mem_l1.read_port
  29         write_port_l1 = mem_l1.write_port
  30
  31         mem_l2 = Memory(113, 128) # L2 TLB cache
  32         read_port_l2 = mem_l2.read_port
  33         write_port_l2 = mem_l2.write_port
  34
  35         def elaborate(self, platform):
  36             m = Module()
  37             m.d.submodules.perm_valid = perm_valid = PermissionValidator(113)
  38             m.d.sync += [
  39                 Case(self.command, {
  40                    # Search for PTE
  41                    1: [
  42                        # Check first entry in set
  43                        # TODO make module?
  44                        read_port_l1.addr.eq(vma[0,2]),
  45                        If(read_port_l1.data[0] == 1,
  46                           perm_valid.data.eq(read_port_l1.data),
  47                           perm_valid.xwr.eq(self.xwr),
  48                           perm_valid.super.eq(self.super),
  49                           perm_valid.super_access.eq(self.super_access),
  50                           perm_valid.asid.eq(self.asid),
  51                           self.valid,eq(perm_valid.valid)
  52                        ),
  53                        If(self.valid == 0,
  54                           read_port_l1.addr.eq(vma[0,2] + 1),
  55                           If(read_port_l1.data[0] == 1,
  56                              perm_valid.data.eq(read_port_l1.data),
  57                              perm_valid.xwr.eq(self.xwr),
  58                              perm_valid.super.eq(self.super),
  59                              perm_valid.super_access.eq(self.super_access),
  60                              perm_valid.asid.eq(self.asid),
  61                              self.valid,eq(perm_valid.valid)
  62                           )
  63                        )
  64                        ]
  65                 })
  66             ]
  67
  68 thing = TLB()
  69 print("Gottem")