1 from nmigen
import Array
, Module
, Signal
2 from nmigen
.lib
.coding
import Decoder
7 The purpose of this module is to represent a bank of registers.
10 To Write: Set the address line to the desired register in the file, set
11 write_enable HIGH, and wait one cycle
12 To Read: Set the address line to the desired register in the file, set
13 write_enable LOW, and wait one cycle.
16 def __init__(self
, data_size
, file_size
):
18 * data_size: (bit count) The number of bits in one register
19 * cam_size: (entry count) the number of registers in this file
23 self
.register_array
= Array(Signal(data_size
) for x
in range(file_size
))
26 self
.enable
= Signal(1)
27 self
.write_enable
= Signal(1)
28 self
.address
= Signal(max=file_size
)
29 self
.data_i
= Signal(data_size
)
32 self
.valid
= Signal(1)
33 self
.data_o
= Signal(data_size
)
35 def elaborate(self
, platform
=None):
38 with m
.If(self
.enable
):
40 with m
.If(self
.write_enable
):
44 self
.register_array
[self
.address
].eq(self
.data_i
)
50 self
.data_o
.eq(self
.register_array
[self
.address
])
52 # Invalidate results when not enabled