2 from nmigen
.cli
import rtlil
5 class ALU(Elaboratable
):
6 def __init__(self
, width
):
10 self
.o
= Signal(width
)
12 #self.m_clock = Signal(reset_less=True)
13 #self.p_reset = Signal(reset_less=True)
15 def elaborate(self
, platform
):
17 #m.domains.sync = ClockDomain()
18 #m.d.comb += ClockSignal().eq(self.m_clock)
20 with m
.If(self
.sel
== 0b00):
21 m
.d
.sync
+= self
.o
.eq(self
.a | self
.b
)
22 with m
.Elif(self
.sel
== 0b01):
23 m
.d
.sync
+= self
.o
.eq(self
.a
& self
.b
)
24 with m
.Elif(self
.sel
== 0b10):
25 m
.d
.sync
+= self
.o
.eq(self
.a ^ self
.b
)
27 m
.d
.sync
+= Cat(self
.o
, self
.co
).eq(self
.a
- self
.b
)
31 def create_ilang(dut
, ports
, test_name
):
32 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
33 with
open("%s.il" % test_name
, "w") as f
:
36 if __name__
== "__main__":
38 create_ilang(alu
, [alu
.o
, alu
.a
, alu
.b
, alu
.co
], "alu")