aaagh found bug in litex setup, 64 bit WB bus was truncated
[soclayout.git] / examples / alu.py
1 from nmigen import *
2 from nmigen.cli import rtlil
3
4
5 class ALU(Elaboratable):
6 def __init__(self, width):
7 self.sel = Signal(2)
8 self.a = Signal(width)
9 self.b = Signal(width)
10 self.o = Signal(width)
11 self.co = Signal()
12 #self.m_clock = Signal(reset_less=True)
13 #self.p_reset = Signal(reset_less=True)
14
15 def elaborate(self, platform):
16 m = Module()
17 #m.domains.sync = ClockDomain()
18 #m.d.comb += ClockSignal().eq(self.m_clock)
19
20 with m.If(self.sel == 0b00):
21 m.d.sync += self.o.eq(self.a | self.b)
22 with m.Elif(self.sel == 0b01):
23 m.d.sync += self.o.eq(self.a & self.b)
24 with m.Elif(self.sel == 0b10):
25 m.d.sync += self.o.eq(self.a ^ self.b)
26 with m.Else():
27 m.d.sync += Cat(self.o, self.co).eq(self.a - self.b)
28 return m
29
30
31 def create_ilang(dut, ports, test_name):
32 vl = rtlil.convert(dut, name=test_name, ports=ports)
33 with open("%s.il" % test_name, "w") as f:
34 f.write(vl)
35
36 if __name__ == "__main__":
37 alu = ALU(width=16)
38 create_ilang(alu, [alu.o, alu.a, alu.b, alu.co], "alu")
39