experiments10/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5             YOSYS_FLATTEN = No
   6                      CHIP = chip
   7                      CORE = add
   8             USE_CLOCKTREE = Yes
   9                 USE_DEBUG = No
  10                  USE_KITE = No
  11                   RM_CHIP = Yes
  12
  13                  NETLISTS = $(shell cat netlists.txt)
  14 #                PATTERNS = add_r
  15
  16
  17  include ./mk/design-flow.mk
  18
  19 chip_r.vst: add.vst
  20         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  21
  22 chip_r.ap: chip_r.vst
  23
  24
  25 blif:      add.blif
  26 vst:       add.vst
  27
  28 lvx:       lvx-chip_r
  29 druc:      druc-chip_r
  30 dreal:     dreal-chip_r
  31 flatph:    flatph-chip_r
  32 view:      cgt-chip_r
  33
  34 layout:    chip_r.ap
  35 gds:       chip_r.gds
  36 gds_flat:  chip_r_flat.gds
  37 cif:       chip_r.cif
  38
  39 view:      cgt-chip_r
  40 sim:       asimut-add_r