add non-generated add.il
[soclayout.git] / experiments10 / non_generated / add.il
1 attribute \generator "nMigen"
2 attribute \nmigen.hierarchy "add.jtag._fsm"
3 module \_fsm
4 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
5 wire width 1 output 0 \capture
6 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
7 wire width 1 output 1 \isdr
8 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
9 wire width 1 \isdr$next
10 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
11 wire width 1 output 2 \shift
12 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
13 wire width 1 output 3 \update
14 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
15 wire width 1 output 4 \isir
16 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
17 wire width 1 \isir$next
18 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
19 wire width 1 output 5 \posjtag_rst
20 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
21 wire width 1 output 6 \posjtag_clk
22 attribute \src "add.py:22"
23 wire width 1 input 7 \tck
24 attribute \src "add.py:22"
25 wire width 1 input 8 \tms
26 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:49"
27 wire width 1 \local_clk
28 process $group_0
29 assign \posjtag_clk 1'0
30 assign \posjtag_clk \tck
31 sync init
32 end
33 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:36"
34 wire width 1 \rst
35 process $group_1
36 assign \posjtag_rst 1'0
37 assign \posjtag_rst \rst
38 sync init
39 end
40 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
41 wire width 1 \negjtag_clk
42 process $group_2
43 assign \negjtag_clk 1'0
44 assign \negjtag_clk \tck
45 sync init
46 end
47 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
48 wire width 1 \negjtag_rst
49 process $group_3
50 assign \negjtag_rst 1'0
51 assign \negjtag_rst \rst
52 sync init
53 end
54 process $group_4
55 assign \local_clk 1'0
56 assign \local_clk \tck
57 sync init
58 end
59 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
60 wire width 4 \fsm_state
61 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
62 wire width 4 \fsm_state$next
63 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:113"
64 wire width 1 $1
65 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:113"
66 cell $eq $2
67 parameter \A_SIGNED 1'0
68 parameter \A_WIDTH 3'100
69 parameter \B_SIGNED 1'0
70 parameter \B_WIDTH 1'1
71 parameter \Y_WIDTH 1'1
72 connect \A \fsm_state
73 connect \B 1'0
74 connect \Y $1
75 end
76 process $group_5
77 assign \rst 1'0
78 assign \rst $1
79 sync init
80 end
81 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:114"
82 wire width 1 $3
83 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:114"
84 cell $eq $4
85 parameter \A_SIGNED 1'0
86 parameter \A_WIDTH 3'100
87 parameter \B_SIGNED 1'0
88 parameter \B_WIDTH 2'10
89 parameter \Y_WIDTH 1'1
90 connect \A \fsm_state
91 connect \B 2'11
92 connect \Y $3
93 end
94 process $group_6
95 assign \capture 1'0
96 assign \capture $3
97 sync init
98 end
99 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:115"
100 wire width 1 $5
101 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:115"
102 cell $eq $6
103 parameter \A_SIGNED 1'0
104 parameter \A_WIDTH 3'100
105 parameter \B_SIGNED 1'0
106 parameter \B_WIDTH 2'11
107 parameter \Y_WIDTH 1'1
108 connect \A \fsm_state
109 connect \B 3'101
110 connect \Y $5
111 end
112 process $group_7
113 assign \shift 1'0
114 assign \shift $5
115 sync init
116 end
117 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:116"
118 wire width 1 $7
119 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:116"
120 cell $eq $8
121 parameter \A_SIGNED 1'0
122 parameter \A_WIDTH 3'100
123 parameter \B_SIGNED 1'0
124 parameter \B_WIDTH 3'100
125 parameter \Y_WIDTH 1'1
126 connect \A \fsm_state
127 connect \B 4'1000
128 connect \Y $7
129 end
130 process $group_8
131 assign \update 1'0
132 assign \update $7
133 sync init
134 end
135 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
136 wire width 1 $9
137 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
138 cell $eq $10
139 parameter \A_SIGNED 1'0
140 parameter \A_WIDTH 1'1
141 parameter \B_SIGNED 1'0
142 parameter \B_WIDTH 1'1
143 parameter \Y_WIDTH 1'1
144 connect \A \tms
145 connect \B 1'0
146 connect \Y $9
147 end
148 process $group_9
149 assign \isir$next \isir
150 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
151 switch \fsm_state
152 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:53"
153 attribute \nmigen.decoding "TestLogicReset/0"
154 case 4'0000
155 assign \isir$next 1'0
156 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:61"
157 attribute \nmigen.decoding "RunTestIdle/1"
158 case 4'0001
159 assign \isir$next 1'0
160 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:69"
161 attribute \nmigen.decoding "SelectDRScan/2"
162 case 4'0010
163 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:75"
164 attribute \nmigen.decoding "SelectIRScan/4"
165 case 4'0100
166 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
167 switch { $9 }
168 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
169 case 1'1
170 assign \isir$next 1'1
171 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:79"
172 case
173 end
174 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:81"
175 attribute \nmigen.decoding "CaptureState/3"
176 case 4'0011
177 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:86"
178 attribute \nmigen.decoding "ShiftState/5"
179 case 4'0101
180 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:89"
181 attribute \nmigen.decoding "Exit1/6"
182 case 4'0110
183 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:94"
184 attribute \nmigen.decoding "Pause/7"
185 case 4'0111
186 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:97"
187 attribute \nmigen.decoding "Exit2/9"
188 case 4'1001
189 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:102"
190 attribute \nmigen.decoding "UpdateState/8"
191 case 4'1000
192 assign \isir$next 1'0
193 end
194 sync init
195 update \isir 1'0
196 sync posedge \local_clk
197 update \isir \isir$next
198 end
199 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
200 wire width 1 $11
201 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
202 cell $eq $12
203 parameter \A_SIGNED 1'0
204 parameter \A_WIDTH 1'1
205 parameter \B_SIGNED 1'0
206 parameter \B_WIDTH 1'1
207 parameter \Y_WIDTH 1'1
208 connect \A \tms
209 connect \B 1'0
210 connect \Y $11
211 end
212 process $group_10
213 assign \isdr$next \isdr
214 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
215 switch \fsm_state
216 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:53"
217 attribute \nmigen.decoding "TestLogicReset/0"
218 case 4'0000
219 assign \isdr$next 1'0
220 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:61"
221 attribute \nmigen.decoding "RunTestIdle/1"
222 case 4'0001
223 assign \isdr$next 1'0
224 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:69"
225 attribute \nmigen.decoding "SelectDRScan/2"
226 case 4'0010
227 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
228 switch { $11 }
229 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
230 case 1'1
231 assign \isdr$next 1'1
232 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:73"
233 case
234 end
235 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:75"
236 attribute \nmigen.decoding "SelectIRScan/4"
237 case 4'0100
238 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:81"
239 attribute \nmigen.decoding "CaptureState/3"
240 case 4'0011
241 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:86"
242 attribute \nmigen.decoding "ShiftState/5"
243 case 4'0101
244 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:89"
245 attribute \nmigen.decoding "Exit1/6"
246 case 4'0110
247 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:94"
248 attribute \nmigen.decoding "Pause/7"
249 case 4'0111
250 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:97"
251 attribute \nmigen.decoding "Exit2/9"
252 case 4'1001
253 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:102"
254 attribute \nmigen.decoding "UpdateState/8"
255 case 4'1000
256 assign \isdr$next 1'0
257 end
258 sync init
259 update \isdr 1'0
260 sync posedge \local_clk
261 update \isdr \isdr$next
262 end
263 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
264 wire width 1 $13
265 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
266 cell $eq $14
267 parameter \A_SIGNED 1'0
268 parameter \A_WIDTH 1'1
269 parameter \B_SIGNED 1'0
270 parameter \B_WIDTH 1'1
271 parameter \Y_WIDTH 1'1
272 connect \A \tms
273 connect \B 1'0
274 connect \Y $13
275 end
276 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
277 wire width 1 $15
278 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
279 cell $eq $16
280 parameter \A_SIGNED 1'0
281 parameter \A_WIDTH 1'1
282 parameter \B_SIGNED 1'0
283 parameter \B_WIDTH 1'1
284 parameter \Y_WIDTH 1'1
285 connect \A \tms
286 connect \B 1'1
287 connect \Y $15
288 end
289 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
290 wire width 1 $17
291 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
292 cell $eq $18
293 parameter \A_SIGNED 1'0
294 parameter \A_WIDTH 1'1
295 parameter \B_SIGNED 1'0
296 parameter \B_WIDTH 1'1
297 parameter \Y_WIDTH 1'1
298 connect \A \tms
299 connect \B 1'0
300 connect \Y $17
301 end
302 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
303 wire width 1 $19
304 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
305 cell $eq $20
306 parameter \A_SIGNED 1'0
307 parameter \A_WIDTH 1'1
308 parameter \B_SIGNED 1'0
309 parameter \B_WIDTH 1'1
310 parameter \Y_WIDTH 1'1
311 connect \A \tms
312 connect \B 1'0
313 connect \Y $19
314 end
315 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
316 wire width 1 $21
317 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
318 cell $eq $22
319 parameter \A_SIGNED 1'0
320 parameter \A_WIDTH 1'1
321 parameter \B_SIGNED 1'0
322 parameter \B_WIDTH 1'1
323 parameter \Y_WIDTH 1'1
324 connect \A \tms
325 connect \B 1'0
326 connect \Y $21
327 end
328 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
329 wire width 1 $23
330 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
331 cell $eq $24
332 parameter \A_SIGNED 1'0
333 parameter \A_WIDTH 1'1
334 parameter \B_SIGNED 1'0
335 parameter \B_WIDTH 1'1
336 parameter \Y_WIDTH 1'1
337 connect \A \tms
338 connect \B 1'1
339 connect \Y $23
340 end
341 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
342 wire width 1 $25
343 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
344 cell $eq $26
345 parameter \A_SIGNED 1'0
346 parameter \A_WIDTH 1'1
347 parameter \B_SIGNED 1'0
348 parameter \B_WIDTH 1'1
349 parameter \Y_WIDTH 1'1
350 connect \A \tms
351 connect \B 1'0
352 connect \Y $25
353 end
354 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
355 wire width 1 $27
356 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
357 cell $eq $28
358 parameter \A_SIGNED 1'0
359 parameter \A_WIDTH 1'1
360 parameter \B_SIGNED 1'0
361 parameter \B_WIDTH 1'1
362 parameter \Y_WIDTH 1'1
363 connect \A \tms
364 connect \B 1'1
365 connect \Y $27
366 end
367 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
368 wire width 1 $29
369 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
370 cell $eq $30
371 parameter \A_SIGNED 1'0
372 parameter \A_WIDTH 1'1
373 parameter \B_SIGNED 1'0
374 parameter \B_WIDTH 1'1
375 parameter \Y_WIDTH 1'1
376 connect \A \tms
377 connect \B 1'0
378 connect \Y $29
379 end
380 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
381 wire width 1 $31
382 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
383 cell $eq $32
384 parameter \A_SIGNED 1'0
385 parameter \A_WIDTH 1'1
386 parameter \B_SIGNED 1'0
387 parameter \B_WIDTH 1'1
388 parameter \Y_WIDTH 1'1
389 connect \A \tms
390 connect \B 1'0
391 connect \Y $31
392 end
393 process $group_11
394 assign \fsm_state$next \fsm_state
395 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
396 switch \fsm_state
397 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:53"
398 attribute \nmigen.decoding "TestLogicReset/0"
399 case 4'0000
400 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
401 switch { $13 }
402 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
403 case 1'1
404 assign \fsm_state$next 4'0001
405 end
406 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:61"
407 attribute \nmigen.decoding "RunTestIdle/1"
408 case 4'0001
409 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
410 switch { $15 }
411 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
412 case 1'1
413 assign \fsm_state$next 4'0010
414 end
415 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:69"
416 attribute \nmigen.decoding "SelectDRScan/2"
417 case 4'0010
418 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
419 switch { $17 }
420 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
421 case 1'1
422 assign \fsm_state$next 4'0011
423 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:73"
424 case
425 assign \fsm_state$next 4'0100
426 end
427 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:75"
428 attribute \nmigen.decoding "SelectIRScan/4"
429 case 4'0100
430 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
431 switch { $19 }
432 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
433 case 1'1
434 assign \fsm_state$next 4'0011
435 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:79"
436 case
437 assign \fsm_state$next 4'0000
438 end
439 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:81"
440 attribute \nmigen.decoding "CaptureState/3"
441 case 4'0011
442 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
443 switch { $21 }
444 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
445 case 1'1
446 assign \fsm_state$next 4'0101
447 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:84"
448 case
449 assign \fsm_state$next 4'0110
450 end
451 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:86"
452 attribute \nmigen.decoding "ShiftState/5"
453 case 4'0101
454 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
455 switch { $23 }
456 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
457 case 1'1
458 assign \fsm_state$next 4'0110
459 end
460 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:89"
461 attribute \nmigen.decoding "Exit1/6"
462 case 4'0110
463 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
464 switch { $25 }
465 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
466 case 1'1
467 assign \fsm_state$next 4'0111
468 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:92"
469 case
470 assign \fsm_state$next 4'1000
471 end
472 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:94"
473 attribute \nmigen.decoding "Pause/7"
474 case 4'0111
475 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
476 switch { $27 }
477 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
478 case 1'1
479 assign \fsm_state$next 4'1001
480 end
481 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:97"
482 attribute \nmigen.decoding "Exit2/9"
483 case 4'1001
484 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
485 switch { $29 }
486 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
487 case 1'1
488 assign \fsm_state$next 4'0101
489 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:100"
490 case
491 assign \fsm_state$next 4'1000
492 end
493 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:102"
494 attribute \nmigen.decoding "UpdateState/8"
495 case 4'1000
496 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
497 switch { $31 }
498 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
499 case 1'1
500 assign \fsm_state$next 4'0001
501 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:109"
502 case
503 assign \fsm_state$next 4'0010
504 end
505 end
506 sync init
507 update \fsm_state 4'0000
508 sync posedge \local_clk
509 update \fsm_state \fsm_state$next
510 end
511 end
512 attribute \generator "nMigen"
513 attribute \nmigen.hierarchy "add.jtag._irblock"
514 module \_irblock
515 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
516 wire width 4 output 0 \ir
517 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
518 wire width 4 \ir$next
519 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
520 wire width 1 input 1 \capture
521 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
522 wire width 1 input 2 \shift
523 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
524 wire width 1 input 3 \update
525 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
526 wire width 1 input 4 \isir
527 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
528 wire width 1 output 5 \tdo
529 attribute \src "add.py:22"
530 wire width 1 input 6 \tdi
531 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
532 wire width 1 input 7 \posjtag_rst
533 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
534 wire width 1 input 8 \posjtag_clk
535 process $group_0
536 assign \tdo 1'0
537 assign \tdo \ir [0]
538 sync init
539 end
540 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:138"
541 wire width 4 \shift_ir
542 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:138"
543 wire width 4 \shift_ir$next
544 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
545 wire width 1 $1
546 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
547 cell $and $2
548 parameter \A_SIGNED 1'0
549 parameter \A_WIDTH 1'1
550 parameter \B_SIGNED 1'0
551 parameter \B_WIDTH 1'1
552 parameter \Y_WIDTH 1'1
553 connect \A \isir
554 connect \B \capture
555 connect \Y $1
556 end
557 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
558 wire width 1 $3
559 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
560 cell $and $4
561 parameter \A_SIGNED 1'0
562 parameter \A_WIDTH 1'1
563 parameter \B_SIGNED 1'0
564 parameter \B_WIDTH 1'1
565 parameter \Y_WIDTH 1'1
566 connect \A \isir
567 connect \B \shift
568 connect \Y $3
569 end
570 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
571 wire width 1 $5
572 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
573 cell $and $6
574 parameter \A_SIGNED 1'0
575 parameter \A_WIDTH 1'1
576 parameter \B_SIGNED 1'0
577 parameter \B_WIDTH 1'1
578 parameter \Y_WIDTH 1'1
579 connect \A \isir
580 connect \B \update
581 connect \Y $5
582 end
583 process $group_1
584 assign \shift_ir$next \shift_ir
585 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
586 switch { $5 $3 $1 }
587 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
588 case 3'--1
589 assign \shift_ir$next \ir
590 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:143"
591 case 3'-1-
592 assign \shift_ir$next { \tdi \shift_ir [3:1] }
593 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:145"
594 case 3'1--
595 end
596 sync init
597 update \shift_ir 4'0000
598 sync posedge \posjtag_clk
599 update \shift_ir \shift_ir$next
600 end
601 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
602 wire width 1 $7
603 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
604 cell $and $8
605 parameter \A_SIGNED 1'0
606 parameter \A_WIDTH 1'1
607 parameter \B_SIGNED 1'0
608 parameter \B_WIDTH 1'1
609 parameter \Y_WIDTH 1'1
610 connect \A \isir
611 connect \B \capture
612 connect \Y $7
613 end
614 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
615 wire width 1 $9
616 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
617 cell $and $10
618 parameter \A_SIGNED 1'0
619 parameter \A_WIDTH 1'1
620 parameter \B_SIGNED 1'0
621 parameter \B_WIDTH 1'1
622 parameter \Y_WIDTH 1'1
623 connect \A \isir
624 connect \B \shift
625 connect \Y $9
626 end
627 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
628 wire width 1 $11
629 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
630 cell $and $12
631 parameter \A_SIGNED 1'0
632 parameter \A_WIDTH 1'1
633 parameter \B_SIGNED 1'0
634 parameter \B_WIDTH 1'1
635 parameter \Y_WIDTH 1'1
636 connect \A \isir
637 connect \B \update
638 connect \Y $11
639 end
640 process $group_2
641 assign \ir$next \ir
642 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
643 switch { $11 $9 $7 }
644 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
645 case 3'--1
646 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:143"
647 case 3'-1-
648 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:145"
649 case 3'1--
650 assign \ir$next \shift_ir
651 end
652 attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
653 switch \posjtag_rst
654 case 1'1
655 assign \ir$next 4'0001
656 end
657 sync init
658 update \ir 4'0001
659 sync posedge \posjtag_clk
660 update \ir \ir$next
661 end
662 end
663 attribute \generator "nMigen"
664 attribute \nmigen.hierarchy "add.jtag._idblock"
665 module \_idblock
666 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
667 wire width 4 input 0 \ir
668 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
669 wire width 1 input 1 \capture
670 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
671 wire width 1 input 2 \isdr
672 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
673 wire width 1 input 3 \shift
674 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
675 wire width 1 input 4 \update
676 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:225"
677 wire width 1 output 5 \jtag_id_tdo
678 attribute \src "add.py:22"
679 wire width 1 input 6 \tdi
680 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
681 wire width 1 input 7 \posjtag_rst
682 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
683 wire width 1 input 8 \posjtag_clk
684 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:239"
685 wire width 1 \_tdi
686 process $group_0
687 assign \_tdi 1'0
688 assign \_tdi \tdi
689 sync init
690 end
691 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:240"
692 wire width 1 \_capture
693 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
694 wire width 1 $1
695 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
696 cell $eq $2
697 parameter \A_SIGNED 1'0
698 parameter \A_WIDTH 3'100
699 parameter \B_SIGNED 1'0
700 parameter \B_WIDTH 1'1
701 parameter \Y_WIDTH 1'1
702 connect \A \ir
703 connect \B 1'1
704 connect \Y $1
705 end
706 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
707 wire width 1 $3
708 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
709 cell $eq $4
710 parameter \A_SIGNED 1'0
711 parameter \A_WIDTH 3'100
712 parameter \B_SIGNED 1'0
713 parameter \B_WIDTH 3'100
714 parameter \Y_WIDTH 1'1
715 connect \A \ir
716 connect \B 4'1111
717 connect \Y $3
718 end
719 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
720 wire width 1 $5
721 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
722 cell $or $6
723 parameter \A_SIGNED 1'0
724 parameter \A_WIDTH 1'1
725 parameter \B_SIGNED 1'0
726 parameter \B_WIDTH 1'1
727 parameter \Y_WIDTH 1'1
728 connect \A $1
729 connect \B $3
730 connect \Y $5
731 end
732 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
733 wire width 1 $7
734 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
735 cell $and $8
736 parameter \A_SIGNED 1'0
737 parameter \A_WIDTH 1'1
738 parameter \B_SIGNED 1'0
739 parameter \B_WIDTH 1'1
740 parameter \Y_WIDTH 1'1
741 connect \A \isdr
742 connect \B $5
743 connect \Y $7
744 end
745 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:379"
746 wire width 1 $9
747 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:379"
748 cell $and $10
749 parameter \A_SIGNED 1'0
750 parameter \A_WIDTH 1'1
751 parameter \B_SIGNED 1'0
752 parameter \B_WIDTH 1'1
753 parameter \Y_WIDTH 1'1
754 connect \A $7
755 connect \B \capture
756 connect \Y $9
757 end
758 process $group_1
759 assign \_capture 1'0
760 assign \_capture $9
761 sync init
762 end
763 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:241"
764 wire width 1 \_shift
765 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
766 wire width 1 $11
767 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
768 cell $eq $12
769 parameter \A_SIGNED 1'0
770 parameter \A_WIDTH 3'100
771 parameter \B_SIGNED 1'0
772 parameter \B_WIDTH 1'1
773 parameter \Y_WIDTH 1'1
774 connect \A \ir
775 connect \B 1'1
776 connect \Y $11
777 end
778 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
779 wire width 1 $13
780 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
781 cell $eq $14
782 parameter \A_SIGNED 1'0
783 parameter \A_WIDTH 3'100
784 parameter \B_SIGNED 1'0
785 parameter \B_WIDTH 3'100
786 parameter \Y_WIDTH 1'1
787 connect \A \ir
788 connect \B 4'1111
789 connect \Y $13
790 end
791 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
792 wire width 1 $15
793 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
794 cell $or $16
795 parameter \A_SIGNED 1'0
796 parameter \A_WIDTH 1'1
797 parameter \B_SIGNED 1'0
798 parameter \B_WIDTH 1'1
799 parameter \Y_WIDTH 1'1
800 connect \A $11
801 connect \B $13
802 connect \Y $15
803 end
804 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
805 wire width 1 $17
806 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
807 cell $and $18
808 parameter \A_SIGNED 1'0
809 parameter \A_WIDTH 1'1
810 parameter \B_SIGNED 1'0
811 parameter \B_WIDTH 1'1
812 parameter \Y_WIDTH 1'1
813 connect \A \isdr
814 connect \B $15
815 connect \Y $17
816 end
817 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
818 wire width 1 $19
819 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
820 cell $and $20
821 parameter \A_SIGNED 1'0
822 parameter \A_WIDTH 1'1
823 parameter \B_SIGNED 1'0
824 parameter \B_WIDTH 1'1
825 parameter \Y_WIDTH 1'1
826 connect \A $17
827 connect \B \shift
828 connect \Y $19
829 end
830 process $group_2
831 assign \_shift 1'0
832 assign \_shift $19
833 sync init
834 end
835 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:242"
836 wire width 1 \_update
837 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
838 wire width 1 $21
839 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
840 cell $eq $22
841 parameter \A_SIGNED 1'0
842 parameter \A_WIDTH 3'100
843 parameter \B_SIGNED 1'0
844 parameter \B_WIDTH 1'1
845 parameter \Y_WIDTH 1'1
846 connect \A \ir
847 connect \B 1'1
848 connect \Y $21
849 end
850 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
851 wire width 1 $23
852 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
853 cell $eq $24
854 parameter \A_SIGNED 1'0
855 parameter \A_WIDTH 3'100
856 parameter \B_SIGNED 1'0
857 parameter \B_WIDTH 3'100
858 parameter \Y_WIDTH 1'1
859 connect \A \ir
860 connect \B 4'1111
861 connect \Y $23
862 end
863 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
864 wire width 1 $25
865 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
866 cell $or $26
867 parameter \A_SIGNED 1'0
868 parameter \A_WIDTH 1'1
869 parameter \B_SIGNED 1'0
870 parameter \B_WIDTH 1'1
871 parameter \Y_WIDTH 1'1
872 connect \A $21
873 connect \B $23
874 connect \Y $25
875 end
876 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
877 wire width 1 $27
878 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
879 cell $and $28
880 parameter \A_SIGNED 1'0
881 parameter \A_WIDTH 1'1
882 parameter \B_SIGNED 1'0
883 parameter \B_WIDTH 1'1
884 parameter \Y_WIDTH 1'1
885 connect \A \isdr
886 connect \B $25
887 connect \Y $27
888 end
889 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:381"
890 wire width 1 $29
891 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:381"
892 cell $and $30
893 parameter \A_SIGNED 1'0
894 parameter \A_WIDTH 1'1
895 parameter \B_SIGNED 1'0
896 parameter \B_WIDTH 1'1
897 parameter \Y_WIDTH 1'1
898 connect \A $27
899 connect \B \update
900 connect \Y $29
901 end
902 process $group_3
903 assign \_update 1'0
904 assign \_update $29
905 sync init
906 end
907 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:243"
908 wire width 1 \_bypass
909 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:382"
910 wire width 1 $31
911 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:382"
912 cell $eq $32
913 parameter \A_SIGNED 1'0
914 parameter \A_WIDTH 3'100
915 parameter \B_SIGNED 1'0
916 parameter \B_WIDTH 3'100
917 parameter \Y_WIDTH 1'1
918 connect \A \ir
919 connect \B 4'1111
920 connect \Y $31
921 end
922 process $group_4
923 assign \_bypass 1'0
924 assign \_bypass $31
925 sync init
926 end
927 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:236"
928 wire width 32 \jtag_id_sr
929 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:236"
930 wire width 32 \jtag_id_sr$next
931 process $group_5
932 assign \jtag_id_tdo 1'0
933 assign \jtag_id_tdo \jtag_id_sr [0]
934 sync init
935 end
936 process $group_6
937 assign \jtag_id_sr$next \jtag_id_sr
938 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:254"
939 switch { \_shift \_capture }
940 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:254"
941 case 2'-1
942 assign \jtag_id_sr$next { 4'0000 16'0000000000000001 11'10001111111 1'1 }
943 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:256"
944 case 2'1-
945 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:257"
946 switch { \_bypass }
947 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:257"
948 case 1'1
949 assign \jtag_id_sr$next [0] \_tdi
950 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:259"
951 case
952 assign \jtag_id_sr$next { \_tdi \jtag_id_sr [31:1] }
953 end
954 end
955 sync init
956 update \jtag_id_sr 32'00000000000000000000000000000000
957 sync posedge \posjtag_clk
958 update \jtag_id_sr \jtag_id_sr$next
959 end
960 end
961 attribute \generator "nMigen"
962 attribute \nmigen.hierarchy "add.jtag"
963 module \jtag
964 attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
965 wire width 1 input 0 \rst
966 attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
967 wire width 1 input 1 \clk
968 attribute \src "add.py:22"
969 wire width 1 input 2 \tdi
970 attribute \src "add.py:22"
971 wire width 1 output 3 \tdo
972 attribute \src "add.py:22"
973 wire width 1 input 4 \tck
974 attribute \src "add.py:22"
975 wire width 1 input 5 \tms
976 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
977 wire width 1 \posjtag_clk
978 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
979 wire width 1 \posjtag_rst
980 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
981 wire width 1 \_fsm_capture
982 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
983 wire width 1 \_fsm_isdr
984 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
985 wire width 1 \_fsm_shift
986 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
987 wire width 1 \_fsm_update
988 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
989 wire width 1 \_fsm_isir
990 cell \_fsm \_fsm
991 connect \capture \_fsm_capture
992 connect \isdr \_fsm_isdr
993 connect \shift \_fsm_shift
994 connect \update \_fsm_update
995 connect \isir \_fsm_isir
996 connect \posjtag_rst \posjtag_rst
997 connect \posjtag_clk \posjtag_clk
998 connect \tck \tck
999 connect \tms \tms
1000 end
1001 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
1002 wire width 4 \_irblock_ir
1003 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
1004 wire width 1 \_irblock_tdo
1005 cell \_irblock \_irblock
1006 connect \ir \_irblock_ir
1007 connect \capture \_fsm_capture
1008 connect \shift \_fsm_shift
1009 connect \update \_fsm_update
1010 connect \isir \_fsm_isir
1011 connect \tdo \_irblock_tdo
1012 connect \tdi \tdi
1013 connect \posjtag_rst \posjtag_rst
1014 connect \posjtag_clk \posjtag_clk
1015 end
1016 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:225"
1017 wire width 1 \_idblock_jtag_id_tdo
1018 cell \_idblock \_idblock
1019 connect \ir \_irblock_ir
1020 connect \capture \_fsm_capture
1021 connect \isdr \_fsm_isdr
1022 connect \shift \_fsm_shift
1023 connect \update \_fsm_update
1024 connect \jtag_id_tdo \_idblock_jtag_id_tdo
1025 connect \tdi \tdi
1026 connect \posjtag_rst \posjtag_rst
1027 connect \posjtag_clk \posjtag_clk
1028 end
1029 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:387"
1030 wire width 1 \io_capture
1031 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1032 wire width 1 $1
1033 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1034 cell $eq $2
1035 parameter \A_SIGNED 1'0
1036 parameter \A_WIDTH 3'100
1037 parameter \B_SIGNED 1'0
1038 parameter \B_WIDTH 1'1
1039 parameter \Y_WIDTH 1'1
1040 connect \A \_irblock_ir
1041 connect \B 1'0
1042 connect \Y $1
1043 end
1044 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1045 wire width 1 $3
1046 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1047 cell $eq $4
1048 parameter \A_SIGNED 1'0
1049 parameter \A_WIDTH 3'100
1050 parameter \B_SIGNED 1'0
1051 parameter \B_WIDTH 2'10
1052 parameter \Y_WIDTH 1'1
1053 connect \A \_irblock_ir
1054 connect \B 2'10
1055 connect \Y $3
1056 end
1057 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1058 wire width 1 $5
1059 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1060 cell $or $6
1061 parameter \A_SIGNED 1'0
1062 parameter \A_WIDTH 1'1
1063 parameter \B_SIGNED 1'0
1064 parameter \B_WIDTH 1'1
1065 parameter \Y_WIDTH 1'1
1066 connect \A $1
1067 connect \B $3
1068 connect \Y $5
1069 end
1070 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
1071 wire width 1 $7
1072 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
1073 cell $and $8
1074 parameter \A_SIGNED 1'0
1075 parameter \A_WIDTH 1'1
1076 parameter \B_SIGNED 1'0
1077 parameter \B_WIDTH 1'1
1078 parameter \Y_WIDTH 1'1
1079 connect \A $5
1080 connect \B \_fsm_capture
1081 connect \Y $7
1082 end
1083 process $group_0
1084 assign \io_capture 1'0
1085 assign \io_capture $7
1086 sync init
1087 end
1088 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:388"
1089 wire width 1 \io_shift
1090 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1091 wire width 1 $9
1092 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1093 cell $eq $10
1094 parameter \A_SIGNED 1'0
1095 parameter \A_WIDTH 3'100
1096 parameter \B_SIGNED 1'0
1097 parameter \B_WIDTH 1'1
1098 parameter \Y_WIDTH 1'1
1099 connect \A \_irblock_ir
1100 connect \B 1'0
1101 connect \Y $9
1102 end
1103 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1104 wire width 1 $11
1105 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1106 cell $eq $12
1107 parameter \A_SIGNED 1'0
1108 parameter \A_WIDTH 3'100
1109 parameter \B_SIGNED 1'0
1110 parameter \B_WIDTH 2'10
1111 parameter \Y_WIDTH 1'1
1112 connect \A \_irblock_ir
1113 connect \B 2'10
1114 connect \Y $11
1115 end
1116 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1117 wire width 1 $13
1118 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1119 cell $or $14
1120 parameter \A_SIGNED 1'0
1121 parameter \A_WIDTH 1'1
1122 parameter \B_SIGNED 1'0
1123 parameter \B_WIDTH 1'1
1124 parameter \Y_WIDTH 1'1
1125 connect \A $9
1126 connect \B $11
1127 connect \Y $13
1128 end
1129 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
1130 wire width 1 $15
1131 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
1132 cell $eq $16
1133 parameter \A_SIGNED 1'0
1134 parameter \A_WIDTH 3'100
1135 parameter \B_SIGNED 1'0
1136 parameter \B_WIDTH 2'10
1137 parameter \Y_WIDTH 1'1
1138 connect \A \_irblock_ir
1139 connect \B 2'10
1140 connect \Y $15
1141 end
1142 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1143 wire width 1 $17
1144 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1145 cell $or $18
1146 parameter \A_SIGNED 1'0
1147 parameter \A_WIDTH 1'1
1148 parameter \B_SIGNED 1'0
1149 parameter \B_WIDTH 1'1
1150 parameter \Y_WIDTH 1'1
1151 connect \A $13
1152 connect \B $15
1153 connect \Y $17
1154 end
1155 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1156 wire width 1 $19
1157 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1158 cell $and $20
1159 parameter \A_SIGNED 1'0
1160 parameter \A_WIDTH 1'1
1161 parameter \B_SIGNED 1'0
1162 parameter \B_WIDTH 1'1
1163 parameter \Y_WIDTH 1'1
1164 connect \A \_fsm_isdr
1165 connect \B $17
1166 connect \Y $19
1167 end
1168 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
1169 wire width 1 $21
1170 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
1171 cell $and $22
1172 parameter \A_SIGNED 1'0
1173 parameter \A_WIDTH 1'1
1174 parameter \B_SIGNED 1'0
1175 parameter \B_WIDTH 1'1
1176 parameter \Y_WIDTH 1'1
1177 connect \A $19
1178 connect \B \_fsm_shift
1179 connect \Y $21
1180 end
1181 process $group_1
1182 assign \io_shift 1'0
1183 assign \io_shift $21
1184 sync init
1185 end
1186 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:389"
1187 wire width 1 \io_update
1188 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1189 wire width 1 $23
1190 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1191 cell $eq $24
1192 parameter \A_SIGNED 1'0
1193 parameter \A_WIDTH 3'100
1194 parameter \B_SIGNED 1'0
1195 parameter \B_WIDTH 1'1
1196 parameter \Y_WIDTH 1'1
1197 connect \A \_irblock_ir
1198 connect \B 1'0
1199 connect \Y $23
1200 end
1201 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1202 wire width 1 $25
1203 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1204 cell $eq $26
1205 parameter \A_SIGNED 1'0
1206 parameter \A_WIDTH 3'100
1207 parameter \B_SIGNED 1'0
1208 parameter \B_WIDTH 2'10
1209 parameter \Y_WIDTH 1'1
1210 connect \A \_irblock_ir
1211 connect \B 2'10
1212 connect \Y $25
1213 end
1214 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1215 wire width 1 $27
1216 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
1217 cell $or $28
1218 parameter \A_SIGNED 1'0
1219 parameter \A_WIDTH 1'1
1220 parameter \B_SIGNED 1'0
1221 parameter \B_WIDTH 1'1
1222 parameter \Y_WIDTH 1'1
1223 connect \A $23
1224 connect \B $25
1225 connect \Y $27
1226 end
1227 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
1228 wire width 1 $29
1229 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
1230 cell $eq $30
1231 parameter \A_SIGNED 1'0
1232 parameter \A_WIDTH 3'100
1233 parameter \B_SIGNED 1'0
1234 parameter \B_WIDTH 2'10
1235 parameter \Y_WIDTH 1'1
1236 connect \A \_irblock_ir
1237 connect \B 2'10
1238 connect \Y $29
1239 end
1240 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1241 wire width 1 $31
1242 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1243 cell $or $32
1244 parameter \A_SIGNED 1'0
1245 parameter \A_WIDTH 1'1
1246 parameter \B_SIGNED 1'0
1247 parameter \B_WIDTH 1'1
1248 parameter \Y_WIDTH 1'1
1249 connect \A $27
1250 connect \B $29
1251 connect \Y $31
1252 end
1253 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1254 wire width 1 $33
1255 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
1256 cell $and $34
1257 parameter \A_SIGNED 1'0
1258 parameter \A_WIDTH 1'1
1259 parameter \B_SIGNED 1'0
1260 parameter \B_WIDTH 1'1
1261 parameter \Y_WIDTH 1'1
1262 connect \A \_fsm_isdr
1263 connect \B $31
1264 connect \Y $33
1265 end
1266 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:399"
1267 wire width 1 $35
1268 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:399"
1269 cell $and $36
1270 parameter \A_SIGNED 1'0
1271 parameter \A_WIDTH 1'1
1272 parameter \B_SIGNED 1'0
1273 parameter \B_WIDTH 1'1
1274 parameter \Y_WIDTH 1'1
1275 connect \A $33
1276 connect \B \_fsm_update
1277 connect \Y $35
1278 end
1279 process $group_2
1280 assign \io_update 1'0
1281 assign \io_update $35
1282 sync init
1283 end
1284 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:390"
1285 wire width 1 \io_bd2io
1286 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
1287 wire width 1 $37
1288 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
1289 cell $eq $38
1290 parameter \A_SIGNED 1'0
1291 parameter \A_WIDTH 3'100
1292 parameter \B_SIGNED 1'0
1293 parameter \B_WIDTH 1'1
1294 parameter \Y_WIDTH 1'1
1295 connect \A \_irblock_ir
1296 connect \B 1'0
1297 connect \Y $37
1298 end
1299 process $group_3
1300 assign \io_bd2io 1'0
1301 assign \io_bd2io $37
1302 sync init
1303 end
1304 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:391"
1305 wire width 1 \io_bd2core
1306 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:401"
1307 wire width 1 $39
1308 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:401"
1309 cell $eq $40
1310 parameter \A_SIGNED 1'0
1311 parameter \A_WIDTH 3'100
1312 parameter \B_SIGNED 1'0
1313 parameter \B_WIDTH 1'1
1314 parameter \Y_WIDTH 1'1
1315 connect \A \_irblock_ir
1316 connect \B 1'0
1317 connect \Y $39
1318 end
1319 process $group_4
1320 assign \io_bd2core 1'0
1321 assign \io_bd2core $39
1322 sync init
1323 end
1324 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:410"
1325 wire width 1 \jtag_tdo
1326 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1327 wire width 1 $41
1328 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1329 cell $eq $42
1330 parameter \A_SIGNED 1'0
1331 parameter \A_WIDTH 3'100
1332 parameter \B_SIGNED 1'0
1333 parameter \B_WIDTH 1'1
1334 parameter \Y_WIDTH 1'1
1335 connect \A \_irblock_ir
1336 connect \B 1'1
1337 connect \Y $41
1338 end
1339 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1340 wire width 1 $43
1341 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1342 cell $eq $44
1343 parameter \A_SIGNED 1'0
1344 parameter \A_WIDTH 3'100
1345 parameter \B_SIGNED 1'0
1346 parameter \B_WIDTH 3'100
1347 parameter \Y_WIDTH 1'1
1348 connect \A \_irblock_ir
1349 connect \B 4'1111
1350 connect \Y $43
1351 end
1352 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1353 wire width 1 $45
1354 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1355 cell $or $46
1356 parameter \A_SIGNED 1'0
1357 parameter \A_WIDTH 1'1
1358 parameter \B_SIGNED 1'0
1359 parameter \B_WIDTH 1'1
1360 parameter \Y_WIDTH 1'1
1361 connect \A $41
1362 connect \B $43
1363 connect \Y $45
1364 end
1365 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1366 wire width 1 $47
1367 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
1368 cell $and $48
1369 parameter \A_SIGNED 1'0
1370 parameter \A_WIDTH 1'1
1371 parameter \B_SIGNED 1'0
1372 parameter \B_WIDTH 1'1
1373 parameter \Y_WIDTH 1'1
1374 connect \A \_fsm_isdr
1375 connect \B $45
1376 connect \Y $47
1377 end
1378 process $group_5
1379 assign \jtag_tdo 1'0
1380 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:411"
1381 switch { $47 \_fsm_isir }
1382 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:411"
1383 case 2'-1
1384 assign \jtag_tdo \_irblock_tdo
1385 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:413"
1386 case 2'1-
1387 assign \jtag_tdo \_idblock_jtag_id_tdo
1388 end
1389 sync init
1390 end
1391 attribute \src "add.py:29"
1392 wire width 3 \sr0__o
1393 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638"
1394 wire width 3 \sr0_reg
1395 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638"
1396 wire width 3 \sr0_reg$next
1397 process $group_6
1398 assign \sr0__o 3'000
1399 assign \sr0__o \sr0_reg
1400 sync init
1401 end
1402 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:641"
1403 wire width 1 \sr0_isir
1404 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
1405 wire width 1 $49
1406 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
1407 cell $eq $50
1408 parameter \A_SIGNED 1'0
1409 parameter \A_WIDTH 3'100
1410 parameter \B_SIGNED 1'0
1411 parameter \B_WIDTH 2'11
1412 parameter \Y_WIDTH 1'1
1413 connect \A \_irblock_ir
1414 connect \B 3'100
1415 connect \Y $49
1416 end
1417 process $group_7
1418 assign \sr0_isir 1'0
1419 assign \sr0_isir { $49 }
1420 sync init
1421 end
1422 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
1423 wire width 1 \sr0_capture
1424 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
1425 wire width 1 $51
1426 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
1427 cell $ne $52
1428 parameter \A_SIGNED 1'0
1429 parameter \A_WIDTH 1'1
1430 parameter \B_SIGNED 1'0
1431 parameter \B_WIDTH 1'1
1432 parameter \Y_WIDTH 1'1
1433 connect \A \sr0_isir
1434 connect \B 1'0
1435 connect \Y $51
1436 end
1437 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
1438 wire width 1 $53
1439 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
1440 cell $and $54
1441 parameter \A_SIGNED 1'0
1442 parameter \A_WIDTH 1'1
1443 parameter \B_SIGNED 1'0
1444 parameter \B_WIDTH 1'1
1445 parameter \Y_WIDTH 1'1
1446 connect \A $51
1447 connect \B \_fsm_capture
1448 connect \Y $53
1449 end
1450 process $group_8
1451 assign \sr0_capture 1'0
1452 assign \sr0_capture $53
1453 sync init
1454 end
1455 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:643"
1456 wire width 1 \sr0_shift
1457 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
1458 wire width 1 $55
1459 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
1460 cell $ne $56
1461 parameter \A_SIGNED 1'0
1462 parameter \A_WIDTH 1'1
1463 parameter \B_SIGNED 1'0
1464 parameter \B_WIDTH 1'1
1465 parameter \Y_WIDTH 1'1
1466 connect \A \sr0_isir
1467 connect \B 1'0
1468 connect \Y $55
1469 end
1470 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
1471 wire width 1 $57
1472 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
1473 cell $and $58
1474 parameter \A_SIGNED 1'0
1475 parameter \A_WIDTH 1'1
1476 parameter \B_SIGNED 1'0
1477 parameter \B_WIDTH 1'1
1478 parameter \Y_WIDTH 1'1
1479 connect \A $55
1480 connect \B \_fsm_shift
1481 connect \Y $57
1482 end
1483 process $group_9
1484 assign \sr0_shift 1'0
1485 assign \sr0_shift $57
1486 sync init
1487 end
1488 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:644"
1489 wire width 1 \sr0_update
1490 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
1491 wire width 1 $59
1492 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
1493 cell $ne $60
1494 parameter \A_SIGNED 1'0
1495 parameter \A_WIDTH 1'1
1496 parameter \B_SIGNED 1'0
1497 parameter \B_WIDTH 1'1
1498 parameter \Y_WIDTH 1'1
1499 connect \A \sr0_isir
1500 connect \B 1'0
1501 connect \Y $59
1502 end
1503 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
1504 wire width 1 $61
1505 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
1506 cell $and $62
1507 parameter \A_SIGNED 1'0
1508 parameter \A_WIDTH 1'1
1509 parameter \B_SIGNED 1'0
1510 parameter \B_WIDTH 1'1
1511 parameter \Y_WIDTH 1'1
1512 connect \A $59
1513 connect \B \_fsm_update
1514 connect \Y $61
1515 end
1516 process $group_10
1517 assign \sr0_update 1'0
1518 assign \sr0_update $61
1519 sync init
1520 end
1521 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:656"
1522 wire width 1 \sr0_update_core
1523 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:656"
1524 wire width 1 \sr0_update_core$next
1525 process $group_11
1526 assign \sr0_update_core$next \sr0_update_core
1527 assign \sr0_update_core$next \sr0_update
1528 attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
1529 switch \rst
1530 case 1'1
1531 assign \sr0_update_core$next 1'0
1532 end
1533 sync init
1534 update \sr0_update_core 1'0
1535 sync posedge \clk
1536 update \sr0_update_core \sr0_update_core$next
1537 end
1538 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:657"
1539 wire width 1 \sr0_update_core_prev
1540 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:657"
1541 wire width 1 \sr0_update_core_prev$next
1542 process $group_12
1543 assign \sr0_update_core_prev$next \sr0_update_core_prev
1544 assign \sr0_update_core_prev$next \sr0_update_core
1545 attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
1546 switch \rst
1547 case 1'1
1548 assign \sr0_update_core_prev$next 1'0
1549 end
1550 sync init
1551 update \sr0_update_core_prev 1'0
1552 sync posedge \clk
1553 update \sr0_update_core_prev \sr0_update_core_prev$next
1554 end
1555 attribute \src "add.py:29"
1556 wire width 1 \sr0__oe
1557 attribute \src "add.py:29"
1558 wire width 1 \sr0__oe$next
1559 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
1560 wire width 1 $63
1561 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
1562 cell $not $64
1563 parameter \A_SIGNED 1'0
1564 parameter \A_WIDTH 1'1
1565 parameter \Y_WIDTH 1'1
1566 connect \A \sr0_update_core
1567 connect \Y $63
1568 end
1569 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
1570 wire width 1 $65
1571 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
1572 cell $and $66
1573 parameter \A_SIGNED 1'0
1574 parameter \A_WIDTH 1'1
1575 parameter \B_SIGNED 1'0
1576 parameter \B_WIDTH 1'1
1577 parameter \Y_WIDTH 1'1
1578 connect \A \sr0_update_core_prev
1579 connect \B $63
1580 connect \Y $65
1581 end
1582 process $group_13
1583 assign \sr0__oe$next \sr0__oe
1584 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
1585 switch { $65 }
1586 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
1587 case 1'1
1588 assign \sr0__oe$next \sr0_isir
1589 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:666"
1590 case
1591 assign \sr0__oe$next 1'0
1592 end
1593 attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
1594 switch \rst
1595 case 1'1
1596 assign \sr0__oe$next 1'0
1597 end
1598 sync init
1599 update \sr0__oe 1'0
1600 sync posedge \clk
1601 update \sr0__oe \sr0__oe$next
1602 end
1603 attribute \src "add.py:29"
1604 wire width 3 \sr0__i
1605 process $group_14
1606 assign \sr0_reg$next \sr0_reg
1607 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:669"
1608 switch { \sr0_shift }
1609 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:669"
1610 case 1'1
1611 assign \sr0_reg$next { \tdi \sr0_reg [2:1] }
1612 end
1613 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:671"
1614 switch { \sr0_capture }
1615 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:671"
1616 case 1'1
1617 assign \sr0_reg$next \sr0__i
1618 end
1619 attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
1620 switch \posjtag_rst
1621 case 1'1
1622 assign \sr0_reg$next 3'000
1623 end
1624 sync init
1625 update \sr0_reg 3'000
1626 sync posedge \posjtag_clk
1627 update \sr0_reg \sr0_reg$next
1628 end
1629 process $group_15
1630 assign \tdo 1'0
1631 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:681"
1632 switch { \sr0_shift }
1633 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:681"
1634 case 1'1
1635 assign \tdo \sr0_reg [0]
1636 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:688"
1637 case
1638 assign \tdo \jtag_tdo
1639 end
1640 sync init
1641 end
1642 connect \sr0__i 3'000
1643 end
1644 attribute \generator "nMigen"
1645 attribute \top 1
1646 attribute \nmigen.hierarchy "add"
1647 module \add
1648 attribute \src "add.py:17"
1649 wire width 4 input 0 \a
1650 attribute \src "add.py:18"
1651 wire width 4 input 1 \b
1652 attribute \src "add.py:19"
1653 wire width 4 output 2 \f
1654 attribute \src "add.py:19"
1655 wire width 4 \f$next
1656 attribute \src "add.py:22"
1657 wire width 1 input 3 \tck
1658 attribute \src "add.py:22"
1659 wire width 1 input 4 \tms
1660 attribute \src "add.py:22"
1661 wire width 1 output 5 \tdo
1662 attribute \src "add.py:22"
1663 wire width 1 input 6 \tdi
1664 attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
1665 wire width 1 input 7 \clk
1666 attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
1667 wire width 1 input 8 \rst
1668 cell \jtag \jtag
1669 connect \rst \rst
1670 connect \clk \clk
1671 connect \tdi \tdi
1672 connect \tdo \tdo
1673 connect \tck \tck
1674 connect \tms \tms
1675 end
1676 attribute \src "add.py:38"
1677 wire width 5 $1
1678 attribute \src "add.py:38"
1679 wire width 5 $2
1680 attribute \src "add.py:38"
1681 cell $add $3
1682 parameter \A_SIGNED 1'0
1683 parameter \A_WIDTH 3'100
1684 parameter \B_SIGNED 1'0
1685 parameter \B_WIDTH 3'100
1686 parameter \Y_WIDTH 3'101
1687 connect \A \a
1688 connect \B \b
1689 connect \Y $2
1690 end
1691 connect $1 $2
1692 process $group_0
1693 assign \f$next \f
1694 assign \f$next $1 [3:0]
1695 attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
1696 switch \rst
1697 case 1'1
1698 assign \f$next 4'0000
1699 end
1700 sync init
1701 update \f 4'0000
1702 sync posedge \clk
1703 update \f \f$next
1704 end
1705 end