1 # generate add.il ilang file with: python3 add.py
4 from nmigen
import Elaboratable
, Signal
, Module
, Const
, DomainRenamer
5 from nmigen
.cli
import verilog
8 # clone with $ git clone gitolite3@git.libre-soc.org:c4m-jtag.git
9 # $ git clone gitolite3@git.libre-soc.org:nmigen-soc.git
10 # for each: $ python3 setup.py develop --user
12 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
15 class ADD(Elaboratable
):
16 def __init__(self
, width
):
17 self
.a
= Signal(width
)
18 self
.b
= Signal(width
)
19 self
.f
= Signal(width
)
22 self
.jtag
= TAP(ir_width
=4)
23 self
.jtag
.bus
.tck
.name
= 'jtag_tck'
24 self
.jtag
.bus
.tms
.name
= 'jtag_tms'
25 self
.jtag
.bus
.tdo
.name
= 'jtag_tdo'
26 self
.jtag
.bus
.tdi
.name
= 'jtag_tdi'
28 # have to create at least one shift register
29 self
.sr
= self
.jtag
.add_shiftreg(ircode
=4, length
=3)
32 self
.ios
= self
.jtag
.add_io(name
="test", iotype
=IOType
.In
)
34 def elaborate(self
, platform
):
37 m
.submodules
.jtag
= jtag
= self
.jtag
38 m
.d
.comb
+= self
.sr
.i
.eq(self
.sr
.o
) # loopback test
41 m
.d
.sync
+= self
.f
.eq(self
.a
+ self
.b
)
42 m
.d
.sync
+= self
.f
[0].eq(Const(0, 1))
47 def create_verilog(dut
, ports
, test_name
):
48 vl
= verilog
.convert(dut
, name
=test_name
, ports
=ports
)
49 with
open("%s.v" % test_name
, "w") as f
:
52 if __name__
== "__main__":
53 #alu = DomainRenamer("sys")(ADD(width=4))
55 create_verilog(alu
, [alu
.a
, alu
.b
, alu
.f
,
59 alu
.jtag
.bus
.tdi
], "add")