experiments10_verilog/doDesign.py

   1
   2 from   __future__ import print_function
   3 import sys
   4 import traceback
   5 import CRL
   6 import helpers
   7 from   helpers.io import ErrorMessage
   8 from   helpers.io import WarningMessage
   9 from   helpers    import trace
  10 from   helpers    import l, u, n
  11 import plugins
  12 from   Hurricane  import DbU
  13 from   plugins.alpha.block.block         import Block
  14 from   plugins.alpha.block.configuration import IoPin
  15 from   plugins.alpha.block.configuration import GaugeConf
  16 from   plugins.alpha.core2chip.niolib    import CoreToChip
  17 #from   plugins.alpha.core2chip.libresocio    import CoreToChip
  18 from   plugins.alpha.chip.configuration  import ChipConf
  19 from   plugins.alpha.chip.chip           import Chip
  20
  21
  22 af = CRL.AllianceFramework.get()
  23
  24
  25 def scriptMain ( **kw ):
  26     """The mandatory function to be called by Coriolis CGT/Unicorn."""
  27     global af
  28     rvalue = True
  29     try:
  30         coreSize = 10000
  31         helpers.setTraceLevel( 550 )
  32         cell, editor = plugins.kwParseMain( **kw )
  33         cell = af.getCell( 'add', CRL.Catalog.State.Logical )
  34         if cell is None:
  35             print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".'.format('adder') ))
  36             sys.exit( 1 )
  37         if editor: editor.setCell( cell )
  38         #     Spec:
  39         # | Side        | Pos | Instance     | Pad net   |Core net | Direction |
  40         ioPadsSpec = [
  41            (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'     )
  42          , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'     )
  43          , (IoPin.SOUTH, None, 'iopower_0'  , 'iovdd'  )
  44          , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
  45          , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'     )
  46          , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'     )
  47          , (IoPin.SOUTH, None, 'p_pll_vco'    , 'pll_vco' , 'pll_vco'     )
  48          , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms'    , 'jtag_tms'      )
  49          , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo'    , 'jtag_tdo'      )
  50          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
  51          , (IoPin.EAST , None, 'p_sys_clk'  , 'sys_clk'    , 'sys_clk'      )
  52          , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck'    , 'jtag_tck'      )
  53          , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi'    , 'jtag_tdi'      )
  54          , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
  55          , (IoPin.EAST , None, 'p_b0'       , 'b(0)'   , 'b(0)'     )
  56          , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
  57          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
  58          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
  59          , (IoPin.NORTH, None, 'p_pll_test'    , 'pll_test' , 'pll_test'     )
  60          , (IoPin.NORTH, None, 'a0'    , 'a0' , 'a0'     )
  61          , (IoPin.NORTH, None, 'a1'    , 'a1' , 'a1'     )
  62          , (IoPin.NORTH, None, 'p_sys_rst'  , 'sys_rst'    , 'sys_rst'      )
  63          , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
  64          , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
  65          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
  66          , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'     )
  67          , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'     )
  68          , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'     )
  69         ]
  70         adderConf = ChipConf( cell, ioPads=ioPadsSpec )
  71         adderConf.cfg.etesian.bloat = 'nsxlib'
  72         adderConf.cfg.etesian.uniformDensity = True
  73         adderConf.cfg.etesian.aspectRatio = 1.0
  74         adderConf.cfg.etesian.spaceMargin = 0.05
  75         adderConf.cfg.block.spareSide = l(700)
  76         adderConf.cfg.chip.padCoreSide = 'North'
  77         adderConf.editor = editor
  78         adderConf.useSpares = True
  79         adderConf.useClockTree = True
  80         #adderConf.useHFNS = True
  81         adderConf.cfg.katana.hTracksReservedMin = 9
  82         adderConf.cfg.katana.vTracksReservedMin = 2
  83         adderConf.bColumns = 2
  84         adderConf.bRows = 2
  85         adderConf.chipConf.name = 'chip'
  86         #adderConf.chipConf.ioPadGauge = 'LibreSOCIO'
  87         adderConf.chipConf.ioPadGauge = 'niolib'
  88         adderConf.useHTree('jtag_tck_from_pad')
  89         adderConf.useHTree('sys_clk_from_pad')
  90         adderConf.coreSize = ( l(coreSize), l(coreSize) )
  91         adderConf.chipSize = ( l(coreSize+3500), l(coreSize+3500) )
  92         adderToChip = CoreToChip( adderConf )
  93         adderToChip.buildChip()
  94
  95         chipBuilder = Chip( adderConf )
  96         chipBuilder.doChipFloorplan()
  97
  98         rvalue = chipBuilder.doPnR()
  99         chipBuilder.save()
 100         CRL.Gds.save(adderConf.chip)
 101
 102     except Exception, e:
 103         helpers.io.catch( e )
 104         rvalue = False
 105     sys.stdout.flush()
 106     sys.stderr.flush()
 107     return rvalue