2 # SPDX-License-Identifier: LGPL-2.1-or-later
3 # See Notices.txt for copyright information
5 from nmigen
import Signal
, Module
, Elaboratable
6 from nmigen
.back
.pysim
import Simulator
, Delay
7 from nmigen
.cli
import rtlil
9 from ieee754
.part
.partsig
import PartitionedSignal
10 from ieee754
.part_mux
.part_mux
import PMux
13 # XXX this is for coriolis2 experimentation
14 class TestLS(Elaboratable
):
15 def __init__(self
, width
, partpoints
):
16 self
.partpoints
= partpoints
17 self
.a
= PartitionedSignal(partpoints
, width
, name
="a")
18 self
.b
= PartitionedSignal(partpoints
, width
, name
="b")
19 self
.ls_output
= Signal(width
) # left shift
20 self
.dummy_output
= Signal(width
) # left shift
22 def elaborate(self
, platform
):
29 sync
+= self
.dummy_output
.eq(self
.b
.sig
) # stops sigs being ignored
30 sync
+= self
.ls_output
.eq(self
.a
<< self
.b
)
31 ppts
= self
.partpoints
36 return [self
.a
.sig
, self
.b
.sig
,
41 # XXX this is for coriolis2 experimentation
42 class TestAddMod2(Elaboratable
):
43 def __init__(self
, width
, partpoints
):
44 self
.partpoints
= partpoints
45 self
.a
= PartitionedSignal(partpoints
, width
, name
="a")
46 self
.b
= PartitionedSignal(partpoints
, width
, name
="b")
47 self
.add_output
= Signal(width
)
48 self
.ls_output
= Signal(width
) # left shift
49 self
.sub_output
= Signal(width
)
50 self
.carry_in
= Signal(len(partpoints
)+1)
51 self
.add_carry_out
= Signal(len(partpoints
)+1)
52 self
.sub_carry_out
= Signal(len(partpoints
)+1)
53 self
.neg_output
= Signal(width
)
55 def elaborate(self
, platform
):
62 add_out
, add_carry
= self
.a
.add_op(self
.a
, self
.b
,
64 sync
+= self
.add_output
.eq(add_out
)
65 sync
+= self
.add_carry_out
.eq(add_carry
)
67 sub_out
, sub_carry
= self
.a
.sub_op(self
.a
, self
.b
,
69 sync
+= self
.sub_output
.eq(sub_out
)
70 sync
+= self
.sub_carry_out
.eq(sub_carry
)
72 sync
+= self
.neg_output
.eq(-self
.a
)
74 sync
+= self
.ls_output
.eq(self
.a
<< self
.b
)
75 ppts
= self
.partpoints
80 return [self
.a
.sig
, self
.b
.sig
,