experiments2/test_partsig.py

   1 #!/usr/bin/env python3
   2 # SPDX-License-Identifier: LGPL-2.1-or-later
   3 # See Notices.txt for copyright information
   4
   5 from nmigen import Signal, Module, Elaboratable
   6 from nmigen.back.pysim import Simulator, Delay
   7 from nmigen.cli import rtlil
   8
   9 from ieee754.part.partsig import PartitionedSignal
  10 from ieee754.part_mux.part_mux import PMux
  11
  12
  13 # XXX this is for coriolis2 experimentation
  14 class TestAddMod2(Elaboratable):
  15     def __init__(self, width, partpoints):
  16         self.partpoints = partpoints
  17         self.a = PartitionedSignal(partpoints, width)
  18         self.b = PartitionedSignal(partpoints, width)
  19         self.add_output = Signal(width)
  20         self.ls_output = Signal(width) # left shift
  21         self.sub_output = Signal(width)
  22         self.carry_in = Signal(len(partpoints)+1)
  23         self.add_carry_out = Signal(len(partpoints)+1)
  24         self.sub_carry_out = Signal(len(partpoints)+1)
  25         self.neg_output = Signal(width)
  26
  27     def elaborate(self, platform):
  28         m = Module()
  29         comb = m.d.comb
  30         sync = m.d.sync
  31         self.a.set_module(m)
  32         self.b.set_module(m)
  33         # add
  34         add_out, add_carry = self.a.add_op(self.a, self.b,
  35                                            self.carry_in)
  36         sync += self.add_output.eq(add_out)
  37         sync += self.add_carry_out.eq(add_carry)
  38         # sub
  39         sub_out, sub_carry = self.a.sub_op(self.a, self.b,
  40                                            self.carry_in)
  41         sync += self.sub_output.eq(sub_out)
  42         sync += self.sub_carry_out.eq(sub_carry)
  43         # neg
  44         sync += self.neg_output.eq(-self.a)
  45         # left shift
  46         sync += self.ls_output.eq(self.a << self.b)
  47         ppts = self.partpoints
  48
  49         return m
  50
  51