2 # SPDX-License-Identifier: LGPL-2.1-or-later
3 # See Notices.txt for copyright information
5 from nmigen
import Signal
, Module
, Elaboratable
6 from nmigen
.cli
import rtlil
8 from ieee754
.part
.partsig
import PartitionedSignal
10 def create_ilang(dut
, traces
, test_name
):
11 vl
= rtlil
.convert(dut
, ports
=traces
, name
=test_name
)
12 with
open("%s.il" % test_name
, "w") as f
:
17 class TestAddMod(Elaboratable
):
18 def __init__(self
, width
, partpoints
):
19 self
.partpoints
= partpoints
20 self
.a
= PartitionedSignal(partpoints
, width
)
21 self
.b
= PartitionedSignal(partpoints
, width
)
22 self
.add_output
= Signal(width
)
23 self
.carry_in
= Signal(len(partpoints
)+1)
24 self
.add_carry_out
= Signal(len(partpoints
)+1)
26 def elaborate(self
, platform
):
33 add_out
, add_carry
= self
.a
.add_op(self
.a
, self
.b
,
35 sync
+= self
.add_output
.eq(add_out
)
36 sync
+= self
.add_carry_out
.eq(add_carry
)
40 if __name__
== '__main__':
42 pmask
= Signal(3) # divide into 4-bits
43 module
= TestAddMod(width
, pmask
)
55 add_1
= module
.a
.m
.submodules
.add_1
56 print (dir(add_1
.part_pts
))