2 -- =======================================================================
3 -- Coriolis Structural VHDL Driver
4 -- Generated on Feb 28, 2020, 20:44
6 -- To be interoperable with Alliance, it uses it's special VHDL subset.
7 -- ("man vhdl" under Alliance for more informations)
8 -- =======================================================================
10 entity alu_hier_altered is
14 ; a : in bit_vector(15 downto 0)
15 ; b : in bit_vector(15 downto 0)
16 ; o : out bit_vector(15 downto 0)
22 architecture structural of alu_hier_altered is
25 port ( a : in bit_vector(15 downto 0)
26 ; b : in bit_vector(15 downto 0)
27 ; o : out bit_vector(15 downto 0)
43 port ( a : in bit_vector(15 downto 0)
44 ; b : in bit_vector(15 downto 0)
45 ; o : out bit_vector(15 downto 0)
70 signal abc_828_new_n51 : bit;
71 signal abc_828_new_n53 : bit;
72 signal abc_828_new_n55 : bit;
73 signal abc_828_new_n57 : bit;
74 signal abc_828_new_n59 : bit;
75 signal abc_828_new_n61 : bit;
76 signal abc_828_new_n63 : bit;
77 signal abc_828_new_n65 : bit;
78 signal abc_828_new_n67 : bit;
79 signal abc_828_new_n69 : bit;
80 signal abc_828_new_n71 : bit;
81 signal abc_828_new_n73 : bit;
82 signal abc_828_new_n75 : bit;
83 signal abc_828_new_n77 : bit;
84 signal abc_828_new_n79 : bit;
85 signal abc_828_new_n81 : bit;
86 signal blockagenet : bit;
87 signal add_o : bit_vector(15 downto 0);
88 signal o_next : bit_vector(15 downto 0);
89 signal sub_o : bit_vector(15 downto 0);
94 subckt_0_nmx2_x1 : nmx2_x1
98 , nq => abc_828_new_n51
103 subckt_28_nmx2_x1 : nmx2_x1
107 , nq => abc_828_new_n79
112 subckt_31_no2_x1 : no2_x1
113 port map ( i0 => abc_828_new_n81
120 subckt_36_sff1_x4 : sff1_x4
128 subckt_44_sff1_x4 : sff1_x4
136 subckt_14_nmx2_x1 : nmx2_x1
140 , nq => abc_828_new_n65
145 subckt_21_no2_x1 : no2_x1
146 port map ( i0 => abc_828_new_n71
153 subckt_22_nmx2_x1 : nmx2_x1
157 , nq => abc_828_new_n73
162 subckt_23_no2_x1 : no2_x1
163 port map ( i0 => abc_828_new_n73
170 subckt_35_sff1_x4 : sff1_x4
178 subckt_30_nmx2_x1 : nmx2_x1
182 , nq => abc_828_new_n81
187 subckt_29_no2_x1 : no2_x1
188 port map ( i0 => abc_828_new_n79
195 subckt_27_no2_x1 : no2_x1
196 port map ( i0 => abc_828_new_n77
203 subckt_25_no2_x1 : no2_x1
204 port map ( i0 => abc_828_new_n75
211 subckt_4_nmx2_x1 : nmx2_x1
215 , nq => abc_828_new_n55
220 subckt_1_no2_x1 : no2_x1
221 port map ( i0 => abc_828_new_n51
228 subckt_43_sff1_x4 : sff1_x4
236 subckt_15_no2_x1 : no2_x1
237 port map ( i0 => abc_828_new_n65
244 subckt_18_nmx2_x1 : nmx2_x1
248 , nq => abc_828_new_n69
253 subckt_13_no2_x1 : no2_x1
254 port map ( i0 => abc_828_new_n63
261 subckt_11_no2_x1 : no2_x1
262 port map ( i0 => abc_828_new_n61
269 subckt_3_no2_x1 : no2_x1
270 port map ( i0 => abc_828_new_n53
277 subckt_5_no2_x1 : no2_x1
278 port map ( i0 => abc_828_new_n55
285 subckt_7_no2_x1 : no2_x1
286 port map ( i0 => abc_828_new_n57
293 subckt_26_nmx2_x1 : nmx2_x1
297 , nq => abc_828_new_n77
302 subckt_34_sff1_x4 : sff1_x4
310 subckt_47_sff1_x4 : sff1_x4
318 subckt_42_sff1_x4 : sff1_x4
326 subckt_20_nmx2_x1 : nmx2_x1
330 , nq => abc_828_new_n71
335 subckt_19_no2_x1 : no2_x1
336 port map ( i0 => abc_828_new_n69
343 subckt_17_no2_x1 : no2_x1
344 port map ( i0 => abc_828_new_n67
351 subckt_12_nmx2_x1 : nmx2_x1
355 , nq => abc_828_new_n63
360 subckt_9_no2_x1 : no2_x1
361 port map ( i0 => abc_828_new_n59
368 subckt_39_sff1_x4 : sff1_x4
376 subckt_41_sff1_x4 : sff1_x4
384 subckt_2_nmx2_x1 : nmx2_x1
388 , nq => abc_828_new_n53
393 subckt_8_nmx2_x1 : nmx2_x1
397 , nq => abc_828_new_n59
402 subckt_33_sff1_x4 : sff1_x4
410 subckt_38_sff1_x4 : sff1_x4
418 subckt_32_sff1_x4 : sff1_x4
426 subckt_24_nmx2_x1 : nmx2_x1
430 , nq => abc_828_new_n75
435 subckt_16_nmx2_x1 : nmx2_x1
439 , nq => abc_828_new_n67
444 subckt_46_sff1_x4 : sff1_x4
452 subckt_40_sff1_x4 : sff1_x4
460 subckt_37_sff1_x4 : sff1_x4
468 subckt_10_nmx2_x1 : nmx2_x1
472 , nq => abc_828_new_n61
477 subckt_6_nmx2_x1 : nmx2_x1
481 , nq => abc_828_new_n57
486 subckt_45_sff1_x4 : sff1_x4