experiments6/fpmul64.il

   1 attribute \generator "nMigen"
   2 attribute \nmigen.hierarchy "top.inpipe.p0"
   3 module \p0
   4   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
   5   wire width 1 input 0 \p_ready_o
   6   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
   7   wire width 1 input 1 \p_valid_i
   8   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
   9   wire width 1 \trigger
  10   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  11   wire width 1 $1
  12   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  13   cell $and $2
  14     parameter \A_SIGNED 1'0
  15     parameter \A_WIDTH 1'1
  16     parameter \B_SIGNED 1'0
  17     parameter \B_WIDTH 1'1
  18     parameter \Y_WIDTH 1'1
  19     connect \A \p_valid_i
  20     connect \B \p_ready_o
  21     connect \Y $1
  22   end
  23   process $group_0
  24     assign \trigger 1'0
  25     assign \trigger $1
  26     sync init
  27   end
  28 end
  29 attribute \generator "nMigen"
  30 attribute \nmigen.hierarchy "top.inpipe.p1"
  31 module \p1
  32   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
  33   wire width 1 input 0 \p_ready_o
  34   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
  35   wire width 1 input 1 \p_valid_i
  36   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
  37   wire width 1 \trigger
  38   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  39   wire width 1 $1
  40   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  41   cell $and $2
  42     parameter \A_SIGNED 1'0
  43     parameter \A_WIDTH 1'1
  44     parameter \B_SIGNED 1'0
  45     parameter \B_WIDTH 1'1
  46     parameter \Y_WIDTH 1'1
  47     connect \A \p_valid_i
  48     connect \B \p_ready_o
  49     connect \Y $1
  50   end
  51   process $group_0
  52     assign \trigger 1'0
  53     assign \trigger $1
  54     sync init
  55   end
  56 end
  57 attribute \generator "nMigen"
  58 attribute \nmigen.hierarchy "top.inpipe.p2"
  59 module \p2
  60   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
  61   wire width 1 input 0 \p_ready_o
  62   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
  63   wire width 1 input 1 \p_valid_i
  64   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
  65   wire width 1 \trigger
  66   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  67   wire width 1 $1
  68   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  69   cell $and $2
  70     parameter \A_SIGNED 1'0
  71     parameter \A_WIDTH 1'1
  72     parameter \B_SIGNED 1'0
  73     parameter \B_WIDTH 1'1
  74     parameter \Y_WIDTH 1'1
  75     connect \A \p_valid_i
  76     connect \B \p_ready_o
  77     connect \Y $1
  78   end
  79   process $group_0
  80     assign \trigger 1'0
  81     assign \trigger $1
  82     sync init
  83   end
  84 end
  85 attribute \generator "nMigen"
  86 attribute \nmigen.hierarchy "top.inpipe.p3"
  87 module \p3
  88   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
  89   wire width 1 input 0 \p_ready_o
  90   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
  91   wire width 1 input 1 \p_valid_i
  92   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
  93   wire width 1 \trigger
  94   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  95   wire width 1 $1
  96   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
  97   cell $and $2
  98     parameter \A_SIGNED 1'0
  99     parameter \A_WIDTH 1'1
 100     parameter \B_SIGNED 1'0
 101     parameter \B_WIDTH 1'1
 102     parameter \Y_WIDTH 1'1
 103     connect \A \p_valid_i
 104     connect \B \p_ready_o
 105     connect \Y $1
 106   end
 107   process $group_0
 108     assign \trigger 1'0
 109     assign \trigger $1
 110     sync init
 111   end
 112 end
 113 attribute \generator "nMigen"
 114 attribute \nmigen.hierarchy "top.inpipe.n"
 115 module \n
 116   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
 117   wire width 1 input 0 \n_valid_o
 118   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
 119   wire width 1 input 1 \n_ready_i
 120   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
 121   wire width 1 \trigger
 122   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
 123   wire width 1 $1
 124   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
 125   cell $and $2
 126     parameter \A_SIGNED 1'0
 127     parameter \A_WIDTH 1'1
 128     parameter \B_SIGNED 1'0
 129     parameter \B_WIDTH 1'1
 130     parameter \Y_WIDTH 1'1
 131     connect \A \n_ready_i
 132     connect \B \n_valid_o
 133     connect \Y $1
 134   end
 135   process $group_0
 136     assign \trigger 1'0
 137     assign \trigger $1
 138     sync init
 139   end
 140 end
 141 attribute \generator "nMigen"
 142 attribute \nmigen.hierarchy "top.inpipe.p_mux.selector"
 143 module \selector
 144   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
 145   wire width 4 input 0 \i
 146   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77"
 147   wire width 1 output 1 \n
 148   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
 149   wire width 2 output 2 \o
 150   process $group_0
 151     assign \o 2'00
 152     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 153     switch { \i [3] }
 154       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 155       case 1'1
 156         assign \o 2'11
 157     end
 158     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 159     switch { \i [2] }
 160       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 161       case 1'1
 162         assign \o 2'10
 163     end
 164     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 165     switch { \i [1] }
 166       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 167       case 1'1
 168         assign \o 2'01
 169     end
 170     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 171     switch { \i [0] }
 172       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
 173       case 1'1
 174         assign \o 2'00
 175     end
 176     sync init
 177   end
 178   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
 179   wire width 1 $1
 180   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
 181   cell $eq $2
 182     parameter \A_SIGNED 1'0
 183     parameter \A_WIDTH 3'100
 184     parameter \B_SIGNED 1'0
 185     parameter \B_WIDTH 1'1
 186     parameter \Y_WIDTH 1'1
 187     connect \A \i
 188     connect \B 1'0
 189     connect \Y $1
 190   end
 191   process $group_1
 192     assign \n 1'0
 193     assign \n $1
 194     sync init
 195   end
 196 end
 197 attribute \generator "nMigen"
 198 attribute \nmigen.hierarchy "top.inpipe.p_mux"
 199 module \p_mux
 200   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:542"
 201   wire width 2 output 0 \m_id
 202   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:543"
 203   wire width 1 output 1 \active
 204   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 205   wire width 1 input 2 \p_valid_i
 206   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 207   wire width 1 input 3 \p_valid_i__1
 208   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 209   wire width 1 input 4 \p_valid_i__2
 210   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 211   wire width 1 input 5 \p_valid_i__3
 212   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
 213   wire width 4 \selector_i
 214   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77"
 215   wire width 1 \selector_n
 216   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
 217   wire width 2 \selector_o
 218   cell \selector \selector
 219     connect \i \selector_i
 220     connect \n \selector_n
 221     connect \o \selector_o
 222   end
 223   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556"
 224   wire width 1 \p_valid_i__4
 225   process $group_0
 226     assign \p_valid_i__4 1'0
 227     assign \p_valid_i__4 \p_valid_i
 228     sync init
 229   end
 230   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556"
 231   wire width 1 \p_valid_i__5
 232   process $group_1
 233     assign \p_valid_i__5 1'0
 234     assign \p_valid_i__5 \p_valid_i__1
 235     sync init
 236   end
 237   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556"
 238   wire width 1 \p_valid_i__6
 239   process $group_2
 240     assign \p_valid_i__6 1'0
 241     assign \p_valid_i__6 \p_valid_i__2
 242     sync init
 243   end
 244   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556"
 245   wire width 1 \p_valid_i__7
 246   process $group_3
 247     assign \p_valid_i__7 1'0
 248     assign \p_valid_i__7 \p_valid_i__3
 249     sync init
 250   end
 251   process $group_4
 252     assign \selector_i 4'0000
 253     assign \selector_i { \p_valid_i__7 \p_valid_i__6 \p_valid_i__5 \p_valid_i__4 }
 254     sync init
 255   end
 256   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:566"
 257   wire width 1 $8
 258   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:566"
 259   cell $not $9
 260     parameter \A_SIGNED 1'0
 261     parameter \A_WIDTH 1'1
 262     parameter \Y_WIDTH 1'1
 263     connect \A \selector_n
 264     connect \Y $8
 265   end
 266   process $group_5
 267     assign \active 1'0
 268     assign \active $8
 269     sync init
 270   end
 271   process $group_6
 272     assign \m_id 2'00
 273     assign \m_id \selector_o
 274     sync init
 275   end
 276 end
 277 attribute \generator "nMigen"
 278 attribute \nmigen.hierarchy "top.inpipe"
 279 module \inpipe
 280   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
 281   wire width 1 output 0 \n_valid_o
 282   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
 283   wire width 1 input 1 \n_ready_i
 284   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 285   wire width 64 output 2 \a
 286   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 287   wire width 64 output 3 \b
 288   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 289   wire width 64 output 4 \c
 290   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
 291   wire width 2 output 5 \muxid
 292   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
 293   wire width 0 output 6 \op
 294   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
 295   wire width 1 output 7 \p_ready_o
 296   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
 297   wire width 1 output 8 \p_ready_o__1
 298   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
 299   wire width 1 output 9 \p_ready_o__2
 300   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
 301   wire width 1 output 10 \p_ready_o__3
 302   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 303   wire width 1 input 11 \p_valid_i
 304   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 305   wire width 64 input 12 \a__4
 306   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 307   wire width 64 input 13 \b__5
 308   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 309   wire width 64 input 14 \c__6
 310   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
 311   wire width 2 input 15 \muxid__7
 312   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
 313   wire width 0 input 16 \op__8
 314   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 315   wire width 1 input 17 \p_valid_i__9
 316   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 317   wire width 64 input 18 \a__10
 318   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 319   wire width 64 input 19 \b__11
 320   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 321   wire width 64 input 20 \c__12
 322   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
 323   wire width 2 input 21 \muxid__13
 324   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
 325   wire width 0 input 22 \op__14
 326   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 327   wire width 1 input 23 \p_valid_i__15
 328   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 329   wire width 64 input 24 \a__16
 330   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 331   wire width 64 input 25 \b__17
 332   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 333   wire width 64 input 26 \c__18
 334   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
 335   wire width 2 input 27 \muxid__19
 336   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
 337   wire width 0 input 28 \op__20
 338   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
 339   wire width 1 input 29 \p_valid_i__21
 340   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 341   wire width 64 input 30 \a__22
 342   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 343   wire width 64 input 31 \b__23
 344   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 345   wire width 64 input 32 \c__24
 346   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
 347   wire width 2 input 33 \muxid__25
 348   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
 349   wire width 0 input 34 \op__26
 350   cell \p0 \p0
 351     connect \p_ready_o \p_ready_o
 352     connect \p_valid_i \p_valid_i
 353   end
 354   cell \p1 \p1
 355     connect \p_ready_o \p_ready_o__1
 356     connect \p_valid_i \p_valid_i__9
 357   end
 358   cell \p2 \p2
 359     connect \p_ready_o \p_ready_o__2
 360     connect \p_valid_i \p_valid_i__15
 361   end
 362   cell \p3 \p3
 363     connect \p_ready_o \p_ready_o__3
 364     connect \p_valid_i \p_valid_i__21
 365   end
 366   cell \n \n
 367     connect \n_valid_o \n_valid_o
 368     connect \n_ready_i \n_ready_i
 369   end
 370   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:542"
 371   wire width 2 \p_mux_m_id
 372   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:543"
 373   wire width 1 \p_mux_active
 374   cell \p_mux \p_mux
 375     connect \m_id \p_mux_m_id
 376     connect \active \p_mux_active
 377     connect \p_valid_i \p_valid_i
 378     connect \p_valid_i__1 \p_valid_i__9
 379     connect \p_valid_i__2 \p_valid_i__15
 380     connect \p_valid_i__3 \p_valid_i__21
 381   end
 382   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:315"
 383   wire width 1 \nirn
 384   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:316"
 385   wire width 1 $27
 386   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:316"
 387   cell $not $28
 388     parameter \A_SIGNED 1'0
 389     parameter \A_WIDTH 1'1
 390     parameter \Y_WIDTH 1'1
 391     connect \A \n_ready_i
 392     connect \Y $27
 393   end
 394   process $group_0
 395     assign \nirn 1'0
 396     assign \nirn $27
 397     sync init
 398   end
 399   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303"
 400   wire width 1 \data_valid
 401   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303"
 402   wire width 1 \data_valid__29
 403   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303"
 404   wire width 1 \data_valid__30
 405   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303"
 406   wire width 1 \data_valid__31
 407   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304"
 408   wire width 1 \p_valid_i__32
 409   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305"
 410   wire width 1 \n_ready_in
 411   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 412   wire width 1 $33
 413   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 414   cell $or $34
 415     parameter \A_SIGNED 1'0
 416     parameter \A_WIDTH 1'1
 417     parameter \B_SIGNED 1'0
 418     parameter \B_WIDTH 1'1
 419     parameter \Y_WIDTH 1'1
 420     connect \A \p_valid_i__32
 421     connect \B \n_ready_in
 422     connect \Y $33
 423   end
 424   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304"
 425   wire width 1 \p_valid_i__35
 426   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305"
 427   wire width 1 \n_ready_in__36
 428   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 429   wire width 1 $37
 430   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 431   cell $or $38
 432     parameter \A_SIGNED 1'0
 433     parameter \A_WIDTH 1'1
 434     parameter \B_SIGNED 1'0
 435     parameter \B_WIDTH 1'1
 436     parameter \Y_WIDTH 1'1
 437     connect \A \p_valid_i__35
 438     connect \B \n_ready_in__36
 439     connect \Y $37
 440   end
 441   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304"
 442   wire width 1 \p_valid_i__39
 443   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305"
 444   wire width 1 \n_ready_in__40
 445   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 446   wire width 1 $41
 447   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 448   cell $or $42
 449     parameter \A_SIGNED 1'0
 450     parameter \A_WIDTH 1'1
 451     parameter \B_SIGNED 1'0
 452     parameter \B_WIDTH 1'1
 453     parameter \Y_WIDTH 1'1
 454     connect \A \p_valid_i__39
 455     connect \B \n_ready_in__40
 456     connect \Y $41
 457   end
 458   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304"
 459   wire width 1 \p_valid_i__43
 460   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305"
 461   wire width 1 \n_ready_in__44
 462   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 463   wire width 1 $45
 464   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341"
 465   cell $or $46
 466     parameter \A_SIGNED 1'0
 467     parameter \A_WIDTH 1'1
 468     parameter \B_SIGNED 1'0
 469     parameter \B_WIDTH 1'1
 470     parameter \Y_WIDTH 1'1
 471     connect \A \p_valid_i__43
 472     connect \B \n_ready_in__44
 473     connect \Y $45
 474   end
 475   process $group_1
 476     assign \data_valid 1'0
 477     assign \data_valid__29 1'0
 478     assign \data_valid__30 1'0
 479     assign \data_valid__31 1'0
 480     assign \data_valid 1'0
 481     assign \data_valid__29 1'0
 482     assign \data_valid__30 1'0
 483     assign \data_valid__31 1'0
 484     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:340"
 485     switch \p_mux_m_id
 486       case 2'00
 487         assign \data_valid $33
 488       case 2'01
 489         assign \data_valid__29 $37
 490       case 2'10
 491         assign \data_valid__30 $41
 492       case 2'--
 493         assign \data_valid__31 $45
 494     end
 495     sync init
 496   end
 497   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 498   wire width 1 $47
 499   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 500   cell $and $48
 501     parameter \A_SIGNED 1'0
 502     parameter \A_WIDTH 1'1
 503     parameter \B_SIGNED 1'0
 504     parameter \B_WIDTH 1'1
 505     parameter \Y_WIDTH 1'1
 506     connect \A \nirn
 507     connect \B \data_valid
 508     connect \Y $47
 509   end
 510   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 511   wire width 1 $49
 512   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 513   cell $and $50
 514     parameter \A_SIGNED 1'0
 515     parameter \A_WIDTH 1'1
 516     parameter \B_SIGNED 1'0
 517     parameter \B_WIDTH 1'1
 518     parameter \Y_WIDTH 1'1
 519     connect \A \nirn
 520     connect \B \data_valid__29
 521     connect \Y $49
 522   end
 523   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 524   wire width 1 $51
 525   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 526   cell $and $52
 527     parameter \A_SIGNED 1'0
 528     parameter \A_WIDTH 1'1
 529     parameter \B_SIGNED 1'0
 530     parameter \B_WIDTH 1'1
 531     parameter \Y_WIDTH 1'1
 532     connect \A \nirn
 533     connect \B \data_valid__30
 534     connect \Y $51
 535   end
 536   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 537   wire width 1 $53
 538   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 539   cell $and $54
 540     parameter \A_SIGNED 1'0
 541     parameter \A_WIDTH 1'1
 542     parameter \B_SIGNED 1'0
 543     parameter \B_WIDTH 1'1
 544     parameter \Y_WIDTH 1'1
 545     connect \A \nirn
 546     connect \B \data_valid__31
 547     connect \Y $53
 548   end
 549   process $group_2
 550     assign \n_ready_in 1'0
 551     assign \n_ready_in__36 1'0
 552     assign \n_ready_in__40 1'0
 553     assign \n_ready_in__44 1'0
 554     assign \n_ready_in 1'1
 555     assign \n_ready_in__36 1'1
 556     assign \n_ready_in__40 1'1
 557     assign \n_ready_in__44 1'1
 558     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333"
 559     switch \p_mux_m_id
 560       case 2'00
 561         assign \n_ready_in $47
 562       case 2'01
 563         assign \n_ready_in__36 $49
 564       case 2'10
 565         assign \n_ready_in__40 $51
 566       case 2'--
 567         assign \n_ready_in__44 $53
 568     end
 569     sync init
 570   end
 571   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:326"
 572   wire width 1 \maskedout
 573   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 574   wire width 1 $55
 575   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 576   cell $and $56
 577     parameter \A_SIGNED 1'0
 578     parameter \A_WIDTH 1'1
 579     parameter \B_SIGNED 1'0
 580     parameter \B_WIDTH 1'1
 581     parameter \Y_WIDTH 1'1
 582     connect \A \maskedout
 583     connect \B \p_mux_active
 584     connect \Y $55
 585   end
 586   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 587   wire width 1 $57
 588   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 589   cell $and $58
 590     parameter \A_SIGNED 1'0
 591     parameter \A_WIDTH 1'1
 592     parameter \B_SIGNED 1'0
 593     parameter \B_WIDTH 1'1
 594     parameter \Y_WIDTH 1'1
 595     connect \A \maskedout
 596     connect \B \p_mux_active
 597     connect \Y $57
 598   end
 599   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 600   wire width 1 $59
 601   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 602   cell $and $60
 603     parameter \A_SIGNED 1'0
 604     parameter \A_WIDTH 1'1
 605     parameter \B_SIGNED 1'0
 606     parameter \B_WIDTH 1'1
 607     parameter \Y_WIDTH 1'1
 608     connect \A \maskedout
 609     connect \B \p_mux_active
 610     connect \Y $59
 611   end
 612   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 613   wire width 1 $61
 614   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 615   cell $and $62
 616     parameter \A_SIGNED 1'0
 617     parameter \A_WIDTH 1'1
 618     parameter \B_SIGNED 1'0
 619     parameter \B_WIDTH 1'1
 620     parameter \Y_WIDTH 1'1
 621     connect \A \maskedout
 622     connect \B \p_mux_active
 623     connect \Y $61
 624   end
 625   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 626   wire width 1 $63
 627   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 628   cell $and $64
 629     parameter \A_SIGNED 1'0
 630     parameter \A_WIDTH 1'1
 631     parameter \B_SIGNED 1'0
 632     parameter \B_WIDTH 1'1
 633     parameter \Y_WIDTH 1'1
 634     connect \A \maskedout
 635     connect \B \p_mux_active
 636     connect \Y $63
 637   end
 638   process $group_3
 639     assign \p_valid_i__32 1'0
 640     assign \p_valid_i__35 1'0
 641     assign \p_valid_i__39 1'0
 642     assign \p_valid_i__43 1'0
 643     assign \p_valid_i__32 1'0
 644     assign \p_valid_i__35 1'0
 645     assign \p_valid_i__39 1'0
 646     assign \p_valid_i__43 1'0
 647     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331"
 648     switch \p_mux_m_id
 649       case 2'00
 650         assign \p_valid_i__32 $57
 651       case 2'01
 652         assign \p_valid_i__35 $59
 653       case 2'10
 654         assign \p_valid_i__39 $61
 655       case 2'--
 656         assign \p_valid_i__43 $63
 657     end
 658     sync init
 659   end
 660   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 661   wire width 1 $65
 662   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 663   wire width 1 $66
 664   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 665   cell $not $67
 666     parameter \A_SIGNED 1'0
 667     parameter \A_WIDTH 1'1
 668     parameter \Y_WIDTH 1'1
 669     connect \A \data_valid
 670     connect \Y $66
 671   end
 672   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 673   wire width 1 $68
 674   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 675   cell $or $69
 676     parameter \A_SIGNED 1'0
 677     parameter \A_WIDTH 1'1
 678     parameter \B_SIGNED 1'0
 679     parameter \B_WIDTH 1'1
 680     parameter \Y_WIDTH 1'1
 681     connect \A $66
 682     connect \B \n_ready_i
 683     connect \Y $68
 684   end
 685   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 686   wire width 1 $70
 687   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 688   cell $not $71
 689     parameter \A_SIGNED 1'0
 690     parameter \A_WIDTH 1'1
 691     parameter \Y_WIDTH 1'1
 692     connect \A \data_valid__29
 693     connect \Y $70
 694   end
 695   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 696   wire width 1 $72
 697   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 698   cell $or $73
 699     parameter \A_SIGNED 1'0
 700     parameter \A_WIDTH 1'1
 701     parameter \B_SIGNED 1'0
 702     parameter \B_WIDTH 1'1
 703     parameter \Y_WIDTH 1'1
 704     connect \A $70
 705     connect \B \n_ready_i
 706     connect \Y $72
 707   end
 708   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 709   wire width 1 $74
 710   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 711   cell $not $75
 712     parameter \A_SIGNED 1'0
 713     parameter \A_WIDTH 1'1
 714     parameter \Y_WIDTH 1'1
 715     connect \A \data_valid__30
 716     connect \Y $74
 717   end
 718   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 719   wire width 1 $76
 720   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 721   cell $or $77
 722     parameter \A_SIGNED 1'0
 723     parameter \A_WIDTH 1'1
 724     parameter \B_SIGNED 1'0
 725     parameter \B_WIDTH 1'1
 726     parameter \Y_WIDTH 1'1
 727     connect \A $74
 728     connect \B \n_ready_i
 729     connect \Y $76
 730   end
 731   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 732   wire width 1 $78
 733   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 734   cell $not $79
 735     parameter \A_SIGNED 1'0
 736     parameter \A_WIDTH 1'1
 737     parameter \Y_WIDTH 1'1
 738     connect \A \data_valid__31
 739     connect \Y $78
 740   end
 741   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 742   wire width 1 $80
 743   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 744   cell $or $81
 745     parameter \A_SIGNED 1'0
 746     parameter \A_WIDTH 1'1
 747     parameter \B_SIGNED 1'0
 748     parameter \B_WIDTH 1'1
 749     parameter \Y_WIDTH 1'1
 750     connect \A $78
 751     connect \B \n_ready_i
 752     connect \Y $80
 753   end
 754   process $group_4
 755     assign \p_ready_o 1'0
 756     assign \p_ready_o__1 1'0
 757     assign \p_ready_o__2 1'0
 758     assign \p_ready_o__3 1'0
 759     assign \p_ready_o 1'0
 760     assign \p_ready_o__1 1'0
 761     assign \p_ready_o__2 1'0
 762     assign \p_ready_o__3 1'0
 763     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332"
 764     switch \p_mux_m_id
 765       case 2'00
 766         assign \p_ready_o $68
 767       case 2'01
 768         assign \p_ready_o__1 $72
 769       case 2'10
 770         assign \p_ready_o__2 $76
 771       case 2'--
 772         assign \p_ready_o__3 $80
 773     end
 774     sync init
 775   end
 776   wire width 1 $verilog_initial_trigger
 777   process $group_17
 778     assign \maskedout 1'0
 779     assign \maskedout 1'1
 780     assign $verilog_initial_trigger $verilog_initial_trigger
 781     sync init
 782       update $verilog_initial_trigger 1'0
 783   end
 784   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:339"
 785   wire width 1 $82
 786   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:339"
 787   cell $reduce_bool $83
 788     parameter \A_SIGNED 1'0
 789     parameter \A_WIDTH 3'100
 790     parameter \Y_WIDTH 1'1
 791     connect \A { \data_valid__31 \data_valid__30 \data_valid__29 \data_valid }
 792     connect \Y $82
 793   end
 794   process $group_18
 795     assign \n_valid_o 1'0
 796     assign \n_valid_o $82
 797     sync init
 798   end
 799   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366"
 800   wire width 1 \maskedout__84
 801   process $group_19
 802     assign \maskedout__84 1'0
 803     assign \maskedout__84 1'1
 804     assign $verilog_initial_trigger $verilog_initial_trigger
 805     sync init
 806   end
 807   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365"
 808   wire width 1 \vr
 809   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 810   wire width 1 $85
 811   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 812   cell $reduce_bool $86
 813     parameter \A_SIGNED 1'0
 814     parameter \A_WIDTH 1'1
 815     parameter \Y_WIDTH 1'1
 816     connect \A \maskedout__84
 817     connect \Y $85
 818   end
 819   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 820   wire width 1 $87
 821   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 822   cell $and $88
 823     parameter \A_SIGNED 1'0
 824     parameter \A_WIDTH 1'1
 825     parameter \B_SIGNED 1'0
 826     parameter \B_WIDTH 1'1
 827     parameter \Y_WIDTH 1'1
 828     connect \A $85
 829     connect \B \p_valid_i
 830     connect \Y $87
 831   end
 832   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 833   wire width 1 $89
 834   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 835   cell $and $90
 836     parameter \A_SIGNED 1'0
 837     parameter \A_WIDTH 1'1
 838     parameter \B_SIGNED 1'0
 839     parameter \B_WIDTH 1'1
 840     parameter \Y_WIDTH 1'1
 841     connect \A $87
 842     connect \B \p_ready_o
 843     connect \Y $89
 844   end
 845   process $group_20
 846     assign \vr 1'0
 847     assign \vr $89
 848     sync init
 849   end
 850   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 851   wire width 64 \a__91
 852   process $group_21
 853     assign \a__91 64'0000000000000000000000000000000000000000000000000000000000000000
 854     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 855     switch { \vr }
 856       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 857       case 1'1
 858         assign \a__91 \a__4
 859     end
 860     sync init
 861   end
 862   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 863   wire width 64 \b__92
 864   process $group_22
 865     assign \b__92 64'0000000000000000000000000000000000000000000000000000000000000000
 866     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 867     switch { \vr }
 868       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 869       case 1'1
 870         assign \b__92 \b__5
 871     end
 872     sync init
 873   end
 874   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 875   wire width 64 \c__93
 876   process $group_23
 877     assign \c__93 64'0000000000000000000000000000000000000000000000000000000000000000
 878     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 879     switch { \vr }
 880       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 881       case 1'1
 882         assign \c__93 \c__6
 883     end
 884     sync init
 885   end
 886   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
 887   wire width 2 \muxid__94
 888   process $group_24
 889     assign \muxid__94 2'00
 890     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 891     switch { \vr }
 892       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 893       case 1'1
 894         assign \muxid__94 \muxid__7
 895     end
 896     sync init
 897   end
 898   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
 899   wire width 0 \op__95
 900   process $group_25
 901     assign \op__95 0'0
 902     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 903     switch { \vr }
 904       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 905       case 1'1
 906         assign \op__95 \op__8
 907     end
 908     sync init
 909   end
 910   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366"
 911   wire width 1 \maskedout__96
 912   process $group_26
 913     assign \maskedout__96 1'0
 914     assign \maskedout__96 1'1
 915     assign $verilog_initial_trigger $verilog_initial_trigger
 916     sync init
 917   end
 918   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365"
 919   wire width 1 \vr__97
 920   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 921   wire width 1 $98
 922   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 923   cell $reduce_bool $99
 924     parameter \A_SIGNED 1'0
 925     parameter \A_WIDTH 1'1
 926     parameter \Y_WIDTH 1'1
 927     connect \A \maskedout__96
 928     connect \Y $98
 929   end
 930   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 931   wire width 1 $100
 932   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 933   cell $and $101
 934     parameter \A_SIGNED 1'0
 935     parameter \A_WIDTH 1'1
 936     parameter \B_SIGNED 1'0
 937     parameter \B_WIDTH 1'1
 938     parameter \Y_WIDTH 1'1
 939     connect \A $98
 940     connect \B \p_valid_i__9
 941     connect \Y $100
 942   end
 943   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 944   wire width 1 $102
 945   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
 946   cell $and $103
 947     parameter \A_SIGNED 1'0
 948     parameter \A_WIDTH 1'1
 949     parameter \B_SIGNED 1'0
 950     parameter \B_WIDTH 1'1
 951     parameter \Y_WIDTH 1'1
 952     connect \A $100
 953     connect \B \p_ready_o__1
 954     connect \Y $102
 955   end
 956   process $group_27
 957     assign \vr__97 1'0
 958     assign \vr__97 $102
 959     sync init
 960   end
 961   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 962   wire width 64 \a__104
 963   process $group_28
 964     assign \a__104 64'0000000000000000000000000000000000000000000000000000000000000000
 965     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 966     switch { \vr__97 }
 967       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 968       case 1'1
 969         assign \a__104 \a__10
 970     end
 971     sync init
 972   end
 973   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 974   wire width 64 \b__105
 975   process $group_29
 976     assign \b__105 64'0000000000000000000000000000000000000000000000000000000000000000
 977     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 978     switch { \vr__97 }
 979       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 980       case 1'1
 981         assign \b__105 \b__11
 982     end
 983     sync init
 984   end
 985   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
 986   wire width 64 \c__106
 987   process $group_30
 988     assign \c__106 64'0000000000000000000000000000000000000000000000000000000000000000
 989     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 990     switch { \vr__97 }
 991       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
 992       case 1'1
 993         assign \c__106 \c__12
 994     end
 995     sync init
 996   end
 997   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
 998   wire width 2 \muxid__107
 999   process $group_31
1000     assign \muxid__107 2'00
1001     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1002     switch { \vr__97 }
1003       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1004       case 1'1
1005         assign \muxid__107 \muxid__13
1006     end
1007     sync init
1008   end
1009   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
1010   wire width 0 \op__108
1011   process $group_32
1012     assign \op__108 0'0
1013     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1014     switch { \vr__97 }
1015       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1016       case 1'1
1017         assign \op__108 \op__14
1018     end
1019     sync init
1020   end
1021   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366"
1022   wire width 1 \maskedout__109
1023   process $group_33
1024     assign \maskedout__109 1'0
1025     assign \maskedout__109 1'1
1026     assign $verilog_initial_trigger $verilog_initial_trigger
1027     sync init
1028   end
1029   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365"
1030   wire width 1 \vr__110
1031   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1032   wire width 1 $111
1033   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1034   cell $reduce_bool $112
1035     parameter \A_SIGNED 1'0
1036     parameter \A_WIDTH 1'1
1037     parameter \Y_WIDTH 1'1
1038     connect \A \maskedout__109
1039     connect \Y $111
1040   end
1041   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1042   wire width 1 $113
1043   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1044   cell $and $114
1045     parameter \A_SIGNED 1'0
1046     parameter \A_WIDTH 1'1
1047     parameter \B_SIGNED 1'0
1048     parameter \B_WIDTH 1'1
1049     parameter \Y_WIDTH 1'1
1050     connect \A $111
1051     connect \B \p_valid_i__15
1052     connect \Y $113
1053   end
1054   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1055   wire width 1 $115
1056   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1057   cell $and $116
1058     parameter \A_SIGNED 1'0
1059     parameter \A_WIDTH 1'1
1060     parameter \B_SIGNED 1'0
1061     parameter \B_WIDTH 1'1
1062     parameter \Y_WIDTH 1'1
1063     connect \A $113
1064     connect \B \p_ready_o__2
1065     connect \Y $115
1066   end
1067   process $group_34
1068     assign \vr__110 1'0
1069     assign \vr__110 $115
1070     sync init
1071   end
1072   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
1073   wire width 64 \a__117
1074   process $group_35
1075     assign \a__117 64'0000000000000000000000000000000000000000000000000000000000000000
1076     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1077     switch { \vr__110 }
1078       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1079       case 1'1
1080         assign \a__117 \a__16
1081     end
1082     sync init
1083   end
1084   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
1085   wire width 64 \b__118
1086   process $group_36
1087     assign \b__118 64'0000000000000000000000000000000000000000000000000000000000000000
1088     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1089     switch { \vr__110 }
1090       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1091       case 1'1
1092         assign \b__118 \b__17
1093     end
1094     sync init
1095   end
1096   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
1097   wire width 64 \c__119
1098   process $group_37
1099     assign \c__119 64'0000000000000000000000000000000000000000000000000000000000000000
1100     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1101     switch { \vr__110 }
1102       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1103       case 1'1
1104         assign \c__119 \c__18
1105     end
1106     sync init
1107   end
1108   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
1109   wire width 2 \muxid__120
1110   process $group_38
1111     assign \muxid__120 2'00
1112     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1113     switch { \vr__110 }
1114       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1115       case 1'1
1116         assign \muxid__120 \muxid__19
1117     end
1118     sync init
1119   end
1120   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
1121   wire width 0 \op__121
1122   process $group_39
1123     assign \op__121 0'0
1124     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1125     switch { \vr__110 }
1126       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1127       case 1'1
1128         assign \op__121 \op__20
1129     end
1130     sync init
1131   end
1132   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366"
1133   wire width 1 \maskedout__122
1134   process $group_40
1135     assign \maskedout__122 1'0
1136     assign \maskedout__122 1'1
1137     assign $verilog_initial_trigger $verilog_initial_trigger
1138     sync init
1139   end
1140   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365"
1141   wire width 1 \vr__123
1142   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1143   wire width 1 $124
1144   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1145   cell $reduce_bool $125
1146     parameter \A_SIGNED 1'0
1147     parameter \A_WIDTH 1'1
1148     parameter \Y_WIDTH 1'1
1149     connect \A \maskedout__122
1150     connect \Y $124
1151   end
1152   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1153   wire width 1 $126
1154   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1155   cell $and $127
1156     parameter \A_SIGNED 1'0
1157     parameter \A_WIDTH 1'1
1158     parameter \B_SIGNED 1'0
1159     parameter \B_WIDTH 1'1
1160     parameter \Y_WIDTH 1'1
1161     connect \A $124
1162     connect \B \p_valid_i__21
1163     connect \Y $126
1164   end
1165   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1166   wire width 1 $128
1167   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371"
1168   cell $and $129
1169     parameter \A_SIGNED 1'0
1170     parameter \A_WIDTH 1'1
1171     parameter \B_SIGNED 1'0
1172     parameter \B_WIDTH 1'1
1173     parameter \Y_WIDTH 1'1
1174     connect \A $126
1175     connect \B \p_ready_o__3
1176     connect \Y $128
1177   end
1178   process $group_41
1179     assign \vr__123 1'0
1180     assign \vr__123 $128
1181     sync init
1182   end
1183   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
1184   wire width 64 \a__130
1185   process $group_42
1186     assign \a__130 64'0000000000000000000000000000000000000000000000000000000000000000
1187     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1188     switch { \vr__123 }
1189       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1190       case 1'1
1191         assign \a__130 \a__22
1192     end
1193     sync init
1194   end
1195   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
1196   wire width 64 \b__131
1197   process $group_43
1198     assign \b__131 64'0000000000000000000000000000000000000000000000000000000000000000
1199     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1200     switch { \vr__123 }
1201       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1202       case 1'1
1203         assign \b__131 \b__23
1204     end
1205     sync init
1206   end
1207   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
1208   wire width 64 \c__132
1209   process $group_44
1210     assign \c__132 64'0000000000000000000000000000000000000000000000000000000000000000
1211     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1212     switch { \vr__123 }
1213       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1214       case 1'1
1215         assign \c__132 \c__24
1216     end
1217     sync init
1218   end
1219   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
1220   wire width 2 \muxid__133
1221   process $group_45
1222     assign \muxid__133 2'00
1223     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1224     switch { \vr__123 }
1225       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1226       case 1'1
1227         assign \muxid__133 \muxid__25
1228     end
1229     sync init
1230   end
1231   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
1232   wire width 0 \op__134
1233   process $group_46
1234     assign \op__134 0'0
1235     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1236     switch { \vr__123 }
1237       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372"
1238       case 1'1
1239         assign \op__134 \op__26
1240     end
1241     sync init
1242   end
1243   process $group_47
1244     assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
1245     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:25"
1246     switch \p_mux_m_id
1247       case 2'00
1248         assign \a \a__91
1249       case 2'01
1250         assign \a \a__104
1251       case 2'10
1252         assign \a \a__117
1253       case 2'--
1254         assign \a \a__130
1255     end
1256     sync init
1257   end
1258   process $group_48
1259     assign \b 64'0000000000000000000000000000000000000000000000000000000000000000
1260     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:25"
1261     switch \p_mux_m_id
1262       case 2'00
1263         assign \b \b__92
1264       case 2'01
1265         assign \b \b__105
1266       case 2'10
1267         assign \b \b__118
1268       case 2'--
1269         assign \b \b__131
1270     end
1271     sync init
1272   end
1273   process $group_49
1274     assign \c 64'0000000000000000000000000000000000000000000000000000000000000000
1275     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:25"
1276     switch \p_mux_m_id
1277       case 2'00
1278         assign \c \c__93
1279       case 2'01
1280         assign \c \c__106
1281       case 2'10
1282         assign \c \c__119
1283       case 2'--
1284         assign \c \c__132
1285     end
1286     sync init
1287   end
1288   process $group_50
1289     assign \muxid 2'00
1290     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:68"
1291     switch \p_mux_m_id
1292       case 2'00
1293         assign \muxid \muxid__94
1294       case 2'01
1295         assign \muxid \muxid__107
1296       case 2'10
1297         assign \muxid \muxid__120
1298       case 2'--
1299         assign \muxid \muxid__133
1300     end
1301     sync init
1302   end
1303   process $group_51
1304     assign \op 0'0
1305     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:69"
1306     switch \p_mux_m_id
1307       case 2'00
1308         assign \op \op__95
1309       case 2'01
1310         assign \op \op__108
1311       case 2'10
1312         assign \op \op__121
1313       case 2'--
1314         assign \op \op__134
1315     end
1316     sync init
1317   end
1318   connect \op 0'0
1319   connect \op__95 0'0
1320   connect \op__108 0'0
1321   connect \op__121 0'0
1322   connect \op__134 0'0
1323 end
1324 attribute \generator "nMigen"
1325 attribute \nmigen.hierarchy "top.alu.p"
1326 module \p
1327   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
1328   wire width 1 input 0 \p_valid_i
1329   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
1330   wire width 1 input 1 \p_ready_o
1331   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
1332   wire width 1 \trigger
1333   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
1334   wire width 1 $1
1335   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
1336   cell $and $2
1337     parameter \A_SIGNED 1'0
1338     parameter \A_WIDTH 1'1
1339     parameter \B_SIGNED 1'0
1340     parameter \B_WIDTH 1'1
1341     parameter \Y_WIDTH 1'1
1342     connect \A \p_valid_i
1343     connect \B \p_ready_o
1344     connect \Y $1
1345   end
1346   process $group_0
1347     assign \trigger 1'0
1348     assign \trigger $1
1349     sync init
1350   end
1351 end
1352 attribute \generator "nMigen"
1353 attribute \nmigen.hierarchy "top.alu.n"
1354 module \n__1
1355   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
1356   wire width 1 input 0 \n_valid_o
1357   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
1358   wire width 1 input 1 \n_ready_i
1359   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
1360   wire width 1 \trigger
1361   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
1362   wire width 1 $1
1363   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
1364   cell $and $2
1365     parameter \A_SIGNED 1'0
1366     parameter \A_WIDTH 1'1
1367     parameter \B_SIGNED 1'0
1368     parameter \B_WIDTH 1'1
1369     parameter \Y_WIDTH 1'1
1370     connect \A \n_ready_i
1371     connect \B \n_valid_o
1372     connect \Y $1
1373   end
1374   process $group_0
1375     assign \trigger 1'0
1376     assign \trigger $1
1377     sync init
1378   end
1379 end
1380 attribute \generator "nMigen"
1381 attribute \nmigen.hierarchy "top.alu.scnorm.p"
1382 module \p__2
1383   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
1384   wire width 1 input 0 \p_valid_i
1385   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
1386   wire width 1 input 1 \p_ready_o
1387   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
1388   wire width 1 \trigger
1389   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
1390   wire width 1 $1
1391   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
1392   cell $and $2
1393     parameter \A_SIGNED 1'0
1394     parameter \A_WIDTH 1'1
1395     parameter \B_SIGNED 1'0
1396     parameter \B_WIDTH 1'1
1397     parameter \Y_WIDTH 1'1
1398     connect \A \p_valid_i
1399     connect \B \p_ready_o
1400     connect \Y $1
1401   end
1402   process $group_0
1403     assign \trigger 1'0
1404     assign \trigger $1
1405     sync init
1406   end
1407 end
1408 attribute \generator "nMigen"
1409 attribute \nmigen.hierarchy "top.alu.scnorm.n"
1410 module \n__3
1411   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
1412   wire width 1 input 0 \n_valid_o
1413   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
1414   wire width 1 input 1 \n_ready_i
1415   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
1416   wire width 1 \trigger
1417   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
1418   wire width 1 $1
1419   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
1420   cell $and $2
1421     parameter \A_SIGNED 1'0
1422     parameter \A_WIDTH 1'1
1423     parameter \B_SIGNED 1'0
1424     parameter \B_WIDTH 1'1
1425     parameter \Y_WIDTH 1'1
1426     connect \A \n_ready_i
1427     connect \B \n_valid_o
1428     connect \Y $1
1429   end
1430   process $group_0
1431     assign \trigger 1'0
1432     assign \trigger $1
1433     sync init
1434   end
1435 end
1436 attribute \generator "nMigen"
1437 attribute \nmigen.hierarchy "top.alu.scnorm.specialcases.sc_decode_a"
1438 module \sc_decode_a
1439   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
1440   wire width 64 input 0 \v
1441   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
1442   wire width 1 output 1 \s
1443   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
1444   wire width 13 output 2 \e
1445   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
1446   wire width 53 output 3 \m
1447   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
1448   wire width 1 output 4 \is_zero
1449   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
1450   wire width 1 output 5 \is_inf
1451   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
1452   wire width 1 output 6 \is_nan
1453   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
1454   wire width 1 \exp_128
1455   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1456   wire width 1 $1
1457   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
1458   wire width 1 \m_zero
1459   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1460   cell $not $2
1461     parameter \A_SIGNED 1'0
1462     parameter \A_WIDTH 1'1
1463     parameter \Y_WIDTH 1'1
1464     connect \A \m_zero
1465     connect \Y $1
1466   end
1467   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1468   wire width 1 $3
1469   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1470   cell $and $4
1471     parameter \A_SIGNED 1'0
1472     parameter \A_WIDTH 1'1
1473     parameter \B_SIGNED 1'0
1474     parameter \B_WIDTH 1'1
1475     parameter \Y_WIDTH 1'1
1476     connect \A \exp_128
1477     connect \B $1
1478     connect \Y $3
1479   end
1480   process $group_0
1481     assign \is_nan 1'0
1482     assign \is_nan $3
1483     sync init
1484   end
1485   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
1486   wire width 1 \exp_n127
1487   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
1488   wire width 1 $5
1489   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
1490   cell $and $6
1491     parameter \A_SIGNED 1'0
1492     parameter \A_WIDTH 1'1
1493     parameter \B_SIGNED 1'0
1494     parameter \B_WIDTH 1'1
1495     parameter \Y_WIDTH 1'1
1496     connect \A \exp_n127
1497     connect \B \m_zero
1498     connect \Y $5
1499   end
1500   process $group_1
1501     assign \is_zero 1'0
1502     assign \is_zero $5
1503     sync init
1504   end
1505   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
1506   wire width 1 $7
1507   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
1508   cell $and $8
1509     parameter \A_SIGNED 1'0
1510     parameter \A_WIDTH 1'1
1511     parameter \B_SIGNED 1'0
1512     parameter \B_WIDTH 1'1
1513     parameter \Y_WIDTH 1'1
1514     connect \A \exp_128
1515     connect \B \m_zero
1516     connect \Y $7
1517   end
1518   process $group_2
1519     assign \is_inf 1'0
1520     assign \is_inf $7
1521     sync init
1522   end
1523   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
1524   wire width 1 \is_overflowed
1525   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
1526   wire width 1 \exp_gt127
1527   process $group_3
1528     assign \is_overflowed 1'0
1529     assign \is_overflowed \exp_gt127
1530     sync init
1531   end
1532   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
1533   wire width 1 \is_denormalised
1534   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
1535   wire width 1 \exp_n126
1536   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
1537   wire width 1 \m_msbzero
1538   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
1539   wire width 1 $9
1540   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
1541   cell $and $10
1542     parameter \A_SIGNED 1'0
1543     parameter \A_WIDTH 1'1
1544     parameter \B_SIGNED 1'0
1545     parameter \B_WIDTH 1'1
1546     parameter \Y_WIDTH 1'1
1547     connect \A \exp_n126
1548     connect \B \m_msbzero
1549     connect \Y $9
1550   end
1551   process $group_4
1552     assign \is_denormalised 1'0
1553     assign \is_denormalised $9
1554     sync init
1555   end
1556   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
1557   wire width 1 $11
1558   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
1559   cell $eq $12
1560     parameter \A_SIGNED 1'1
1561     parameter \A_WIDTH 4'1101
1562     parameter \B_SIGNED 1'1
1563     parameter \B_WIDTH 4'1101
1564     parameter \Y_WIDTH 1'1
1565     connect \A \e
1566     connect \B 13'0010000000000
1567     connect \Y $11
1568   end
1569   process $group_5
1570     assign \exp_128 1'0
1571     assign \exp_128 $11
1572     sync init
1573   end
1574   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
1575   wire width 13 \exp_sub_n126
1576   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
1577   wire width 14 $13
1578   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
1579   wire width 14 $14
1580   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
1581   cell $sub $15
1582     parameter \A_SIGNED 1'1
1583     parameter \A_WIDTH 4'1101
1584     parameter \B_SIGNED 1'1
1585     parameter \B_WIDTH 4'1101
1586     parameter \Y_WIDTH 4'1110
1587     connect \A \e
1588     connect \B 13'1110000000010
1589     connect \Y $14
1590   end
1591   connect $13 $14
1592   process $group_6
1593     assign \exp_sub_n126 13'0000000000000
1594     assign \exp_sub_n126 $13 [12:0]
1595     sync init
1596   end
1597   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
1598   wire width 1 \exp_gt_n126
1599   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
1600   wire width 1 $16
1601   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
1602   cell $gt $17
1603     parameter \A_SIGNED 1'1
1604     parameter \A_WIDTH 4'1101
1605     parameter \B_SIGNED 1'1
1606     parameter \B_WIDTH 4'1101
1607     parameter \Y_WIDTH 1'1
1608     connect \A \exp_sub_n126
1609     connect \B 13'0000000000000
1610     connect \Y $16
1611   end
1612   process $group_7
1613     assign \exp_gt_n126 1'0
1614     assign \exp_gt_n126 $16
1615     sync init
1616   end
1617   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
1618   wire width 1 \exp_lt_n126
1619   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
1620   wire width 1 $18
1621   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
1622   cell $lt $19
1623     parameter \A_SIGNED 1'1
1624     parameter \A_WIDTH 4'1101
1625     parameter \B_SIGNED 1'1
1626     parameter \B_WIDTH 4'1101
1627     parameter \Y_WIDTH 1'1
1628     connect \A \exp_sub_n126
1629     connect \B 13'0000000000000
1630     connect \Y $18
1631   end
1632   process $group_8
1633     assign \exp_lt_n126 1'0
1634     assign \exp_lt_n126 $18
1635     sync init
1636   end
1637   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
1638   wire width 1 \exp_zero
1639   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
1640   wire width 1 $20
1641   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
1642   cell $eq $21
1643     parameter \A_SIGNED 1'1
1644     parameter \A_WIDTH 4'1101
1645     parameter \B_SIGNED 1'1
1646     parameter \B_WIDTH 4'1101
1647     parameter \Y_WIDTH 1'1
1648     connect \A \e
1649     connect \B 13'0000000000000
1650     connect \Y $20
1651   end
1652   process $group_9
1653     assign \exp_zero 1'0
1654     assign \exp_zero $20
1655     sync init
1656   end
1657   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
1658   wire width 1 $22
1659   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
1660   cell $gt $23
1661     parameter \A_SIGNED 1'1
1662     parameter \A_WIDTH 4'1101
1663     parameter \B_SIGNED 1'1
1664     parameter \B_WIDTH 4'1101
1665     parameter \Y_WIDTH 1'1
1666     connect \A \e
1667     connect \B 13'0001111111111
1668     connect \Y $22
1669   end
1670   process $group_10
1671     assign \exp_gt127 1'0
1672     assign \exp_gt127 $22
1673     sync init
1674   end
1675   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
1676   wire width 1 $24
1677   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
1678   cell $eq $25
1679     parameter \A_SIGNED 1'1
1680     parameter \A_WIDTH 4'1101
1681     parameter \B_SIGNED 1'1
1682     parameter \B_WIDTH 4'1101
1683     parameter \Y_WIDTH 1'1
1684     connect \A \e
1685     connect \B 13'1110000000001
1686     connect \Y $24
1687   end
1688   process $group_11
1689     assign \exp_n127 1'0
1690     assign \exp_n127 $24
1691     sync init
1692   end
1693   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
1694   wire width 1 $26
1695   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
1696   cell $eq $27
1697     parameter \A_SIGNED 1'1
1698     parameter \A_WIDTH 4'1101
1699     parameter \B_SIGNED 1'1
1700     parameter \B_WIDTH 4'1101
1701     parameter \Y_WIDTH 1'1
1702     connect \A \e
1703     connect \B 13'1110000000010
1704     connect \Y $26
1705   end
1706   process $group_12
1707     assign \exp_n126 1'0
1708     assign \exp_n126 $26
1709     sync init
1710   end
1711   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
1712   wire width 1 $28
1713   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
1714   cell $eq $29
1715     parameter \A_SIGNED 1'0
1716     parameter \A_WIDTH 6'110101
1717     parameter \B_SIGNED 1'0
1718     parameter \B_WIDTH 6'110101
1719     parameter \Y_WIDTH 1'1
1720     connect \A \m
1721     connect \B 53'00000000000000000000000000000000000000000000000000000
1722     connect \Y $28
1723   end
1724   process $group_13
1725     assign \m_zero 1'0
1726     assign \m_zero $28
1727     sync init
1728   end
1729   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
1730   wire width 1 $30
1731   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
1732   cell $eq $31
1733     parameter \A_SIGNED 1'0
1734     parameter \A_WIDTH 1'1
1735     parameter \B_SIGNED 1'0
1736     parameter \B_WIDTH 1'1
1737     parameter \Y_WIDTH 1'1
1738     connect \A \m [52]
1739     connect \B 1'0
1740     connect \Y $30
1741   end
1742   process $group_14
1743     assign \m_msbzero 1'0
1744     assign \m_msbzero $30
1745     sync init
1746   end
1747   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697"
1748   wire width 53 $32
1749   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697"
1750   cell $pos $33
1751     parameter \A_SIGNED 1'0
1752     parameter \A_WIDTH 6'110100
1753     parameter \Y_WIDTH 6'110101
1754     connect \A { \v [51:0] }
1755     connect \Y $32
1756   end
1757   process $group_15
1758     assign \m 53'00000000000000000000000000000000000000000000000000000
1759     assign \m $32
1760     sync init
1761   end
1762   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698"
1763   wire width 14 $34
1764   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
1765   wire width 13 $35
1766   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
1767   cell $pos $36
1768     parameter \A_SIGNED 1'0
1769     parameter \A_WIDTH 4'1011
1770     parameter \Y_WIDTH 4'1101
1771     connect \A \v [62:52]
1772     connect \Y $35
1773   end
1774   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698"
1775   wire width 14 $37
1776   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698"
1777   cell $sub $38
1778     parameter \A_SIGNED 1'1
1779     parameter \A_WIDTH 4'1101
1780     parameter \B_SIGNED 1'1
1781     parameter \B_WIDTH 4'1101
1782     parameter \Y_WIDTH 4'1110
1783     connect \A $35
1784     connect \B 13'0001111111111
1785     connect \Y $37
1786   end
1787   connect $34 $37
1788   process $group_16
1789     assign \e 13'0000000000000
1790     assign \e $34 [12:0]
1791     sync init
1792   end
1793   process $group_17
1794     assign \s 1'0
1795     assign \s \v [63]
1796     sync init
1797   end
1798 end
1799 attribute \generator "nMigen"
1800 attribute \nmigen.hierarchy "top.alu.scnorm.specialcases.sc_decode_b"
1801 module \sc_decode_b
1802   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
1803   wire width 64 input 0 \v
1804   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
1805   wire width 1 output 1 \s
1806   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
1807   wire width 13 output 2 \e
1808   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
1809   wire width 53 output 3 \m
1810   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
1811   wire width 1 output 4 \is_zero
1812   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
1813   wire width 1 output 5 \is_inf
1814   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
1815   wire width 1 output 6 \is_nan
1816   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
1817   wire width 1 \exp_128
1818   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1819   wire width 1 $1
1820   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
1821   wire width 1 \m_zero
1822   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1823   cell $not $2
1824     parameter \A_SIGNED 1'0
1825     parameter \A_WIDTH 1'1
1826     parameter \Y_WIDTH 1'1
1827     connect \A \m_zero
1828     connect \Y $1
1829   end
1830   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1831   wire width 1 $3
1832   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
1833   cell $and $4
1834     parameter \A_SIGNED 1'0
1835     parameter \A_WIDTH 1'1
1836     parameter \B_SIGNED 1'0
1837     parameter \B_WIDTH 1'1
1838     parameter \Y_WIDTH 1'1
1839     connect \A \exp_128
1840     connect \B $1
1841     connect \Y $3
1842   end
1843   process $group_0
1844     assign \is_nan 1'0
1845     assign \is_nan $3
1846     sync init
1847   end
1848   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
1849   wire width 1 \exp_n127
1850   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
1851   wire width 1 $5
1852   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
1853   cell $and $6
1854     parameter \A_SIGNED 1'0
1855     parameter \A_WIDTH 1'1
1856     parameter \B_SIGNED 1'0
1857     parameter \B_WIDTH 1'1
1858     parameter \Y_WIDTH 1'1
1859     connect \A \exp_n127
1860     connect \B \m_zero
1861     connect \Y $5
1862   end
1863   process $group_1
1864     assign \is_zero 1'0
1865     assign \is_zero $5
1866     sync init
1867   end
1868   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
1869   wire width 1 $7
1870   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
1871   cell $and $8
1872     parameter \A_SIGNED 1'0
1873     parameter \A_WIDTH 1'1
1874     parameter \B_SIGNED 1'0
1875     parameter \B_WIDTH 1'1
1876     parameter \Y_WIDTH 1'1
1877     connect \A \exp_128
1878     connect \B \m_zero
1879     connect \Y $7
1880   end
1881   process $group_2
1882     assign \is_inf 1'0
1883     assign \is_inf $7
1884     sync init
1885   end
1886   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
1887   wire width 1 \is_overflowed
1888   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
1889   wire width 1 \exp_gt127
1890   process $group_3
1891     assign \is_overflowed 1'0
1892     assign \is_overflowed \exp_gt127
1893     sync init
1894   end
1895   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
1896   wire width 1 \is_denormalised
1897   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
1898   wire width 1 \exp_n126
1899   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
1900   wire width 1 \m_msbzero
1901   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
1902   wire width 1 $9
1903   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
1904   cell $and $10
1905     parameter \A_SIGNED 1'0
1906     parameter \A_WIDTH 1'1
1907     parameter \B_SIGNED 1'0
1908     parameter \B_WIDTH 1'1
1909     parameter \Y_WIDTH 1'1
1910     connect \A \exp_n126
1911     connect \B \m_msbzero
1912     connect \Y $9
1913   end
1914   process $group_4
1915     assign \is_denormalised 1'0
1916     assign \is_denormalised $9
1917     sync init
1918   end
1919   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
1920   wire width 1 $11
1921   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
1922   cell $eq $12
1923     parameter \A_SIGNED 1'1
1924     parameter \A_WIDTH 4'1101
1925     parameter \B_SIGNED 1'1
1926     parameter \B_WIDTH 4'1101
1927     parameter \Y_WIDTH 1'1
1928     connect \A \e
1929     connect \B 13'0010000000000
1930     connect \Y $11
1931   end
1932   process $group_5
1933     assign \exp_128 1'0
1934     assign \exp_128 $11
1935     sync init
1936   end
1937   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
1938   wire width 13 \exp_sub_n126
1939   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
1940   wire width 14 $13
1941   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
1942   wire width 14 $14
1943   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
1944   cell $sub $15
1945     parameter \A_SIGNED 1'1
1946     parameter \A_WIDTH 4'1101
1947     parameter \B_SIGNED 1'1
1948     parameter \B_WIDTH 4'1101
1949     parameter \Y_WIDTH 4'1110
1950     connect \A \e
1951     connect \B 13'1110000000010
1952     connect \Y $14
1953   end
1954   connect $13 $14
1955   process $group_6
1956     assign \exp_sub_n126 13'0000000000000
1957     assign \exp_sub_n126 $13 [12:0]
1958     sync init
1959   end
1960   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
1961   wire width 1 \exp_gt_n126
1962   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
1963   wire width 1 $16
1964   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
1965   cell $gt $17
1966     parameter \A_SIGNED 1'1
1967     parameter \A_WIDTH 4'1101
1968     parameter \B_SIGNED 1'1
1969     parameter \B_WIDTH 4'1101
1970     parameter \Y_WIDTH 1'1
1971     connect \A \exp_sub_n126
1972     connect \B 13'0000000000000
1973     connect \Y $16
1974   end
1975   process $group_7
1976     assign \exp_gt_n126 1'0
1977     assign \exp_gt_n126 $16
1978     sync init
1979   end
1980   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
1981   wire width 1 \exp_lt_n126
1982   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
1983   wire width 1 $18
1984   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
1985   cell $lt $19
1986     parameter \A_SIGNED 1'1
1987     parameter \A_WIDTH 4'1101
1988     parameter \B_SIGNED 1'1
1989     parameter \B_WIDTH 4'1101
1990     parameter \Y_WIDTH 1'1
1991     connect \A \exp_sub_n126
1992     connect \B 13'0000000000000
1993     connect \Y $18
1994   end
1995   process $group_8
1996     assign \exp_lt_n126 1'0
1997     assign \exp_lt_n126 $18
1998     sync init
1999   end
2000   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
2001   wire width 1 \exp_zero
2002   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
2003   wire width 1 $20
2004   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
2005   cell $eq $21
2006     parameter \A_SIGNED 1'1
2007     parameter \A_WIDTH 4'1101
2008     parameter \B_SIGNED 1'1
2009     parameter \B_WIDTH 4'1101
2010     parameter \Y_WIDTH 1'1
2011     connect \A \e
2012     connect \B 13'0000000000000
2013     connect \Y $20
2014   end
2015   process $group_9
2016     assign \exp_zero 1'0
2017     assign \exp_zero $20
2018     sync init
2019   end
2020   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
2021   wire width 1 $22
2022   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
2023   cell $gt $23
2024     parameter \A_SIGNED 1'1
2025     parameter \A_WIDTH 4'1101
2026     parameter \B_SIGNED 1'1
2027     parameter \B_WIDTH 4'1101
2028     parameter \Y_WIDTH 1'1
2029     connect \A \e
2030     connect \B 13'0001111111111
2031     connect \Y $22
2032   end
2033   process $group_10
2034     assign \exp_gt127 1'0
2035     assign \exp_gt127 $22
2036     sync init
2037   end
2038   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
2039   wire width 1 $24
2040   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
2041   cell $eq $25
2042     parameter \A_SIGNED 1'1
2043     parameter \A_WIDTH 4'1101
2044     parameter \B_SIGNED 1'1
2045     parameter \B_WIDTH 4'1101
2046     parameter \Y_WIDTH 1'1
2047     connect \A \e
2048     connect \B 13'1110000000001
2049     connect \Y $24
2050   end
2051   process $group_11
2052     assign \exp_n127 1'0
2053     assign \exp_n127 $24
2054     sync init
2055   end
2056   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
2057   wire width 1 $26
2058   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
2059   cell $eq $27
2060     parameter \A_SIGNED 1'1
2061     parameter \A_WIDTH 4'1101
2062     parameter \B_SIGNED 1'1
2063     parameter \B_WIDTH 4'1101
2064     parameter \Y_WIDTH 1'1
2065     connect \A \e
2066     connect \B 13'1110000000010
2067     connect \Y $26
2068   end
2069   process $group_12
2070     assign \exp_n126 1'0
2071     assign \exp_n126 $26
2072     sync init
2073   end
2074   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
2075   wire width 1 $28
2076   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
2077   cell $eq $29
2078     parameter \A_SIGNED 1'0
2079     parameter \A_WIDTH 6'110101
2080     parameter \B_SIGNED 1'0
2081     parameter \B_WIDTH 6'110101
2082     parameter \Y_WIDTH 1'1
2083     connect \A \m
2084     connect \B 53'00000000000000000000000000000000000000000000000000000
2085     connect \Y $28
2086   end
2087   process $group_13
2088     assign \m_zero 1'0
2089     assign \m_zero $28
2090     sync init
2091   end
2092   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
2093   wire width 1 $30
2094   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
2095   cell $eq $31
2096     parameter \A_SIGNED 1'0
2097     parameter \A_WIDTH 1'1
2098     parameter \B_SIGNED 1'0
2099     parameter \B_WIDTH 1'1
2100     parameter \Y_WIDTH 1'1
2101     connect \A \m [52]
2102     connect \B 1'0
2103     connect \Y $30
2104   end
2105   process $group_14
2106     assign \m_msbzero 1'0
2107     assign \m_msbzero $30
2108     sync init
2109   end
2110   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697"
2111   wire width 53 $32
2112   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697"
2113   cell $pos $33
2114     parameter \A_SIGNED 1'0
2115     parameter \A_WIDTH 6'110100
2116     parameter \Y_WIDTH 6'110101
2117     connect \A { \v [51:0] }
2118     connect \Y $32
2119   end
2120   process $group_15
2121     assign \m 53'00000000000000000000000000000000000000000000000000000
2122     assign \m $32
2123     sync init
2124   end
2125   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698"
2126   wire width 14 $34
2127   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
2128   wire width 13 $35
2129   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
2130   cell $pos $36
2131     parameter \A_SIGNED 1'0
2132     parameter \A_WIDTH 4'1011
2133     parameter \Y_WIDTH 4'1101
2134     connect \A \v [62:52]
2135     connect \Y $35
2136   end
2137   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698"
2138   wire width 14 $37
2139   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698"
2140   cell $sub $38
2141     parameter \A_SIGNED 1'1
2142     parameter \A_WIDTH 4'1101
2143     parameter \B_SIGNED 1'1
2144     parameter \B_WIDTH 4'1101
2145     parameter \Y_WIDTH 4'1110
2146     connect \A $35
2147     connect \B 13'0001111111111
2148     connect \Y $37
2149   end
2150   connect $34 $37
2151   process $group_16
2152     assign \e 13'0000000000000
2153     assign \e $34 [12:0]
2154     sync init
2155   end
2156   process $group_17
2157     assign \s 1'0
2158     assign \s \v [63]
2159     sync init
2160   end
2161 end
2162 attribute \generator "nMigen"
2163 attribute \nmigen.hierarchy "top.alu.scnorm.specialcases"
2164 module \specialcases
2165   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
2166   wire width 64 input 0 \a
2167   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
2168   wire width 64 input 1 \b
2169   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
2170   wire width 2 input 2 \muxid
2171   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
2172   wire width 0 input 3 \op
2173   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
2174   wire width 1 output 4 \out_do_z
2175   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
2176   wire width 64 output 5 \oz
2177   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
2178   wire width 1 output 6 \a_s
2179   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
2180   wire width 13 output 7 \a_e
2181   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
2182   wire width 53 output 8 \a_m
2183   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
2184   wire width 1 output 9 \b_s
2185   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
2186   wire width 13 output 10 \b_e
2187   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
2188   wire width 53 output 11 \b_m
2189   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
2190   wire width 2 output 12 \muxid__1
2191   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
2192   wire width 0 output 13 \op__2
2193   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
2194   wire width 64 \sc_decode_a_v
2195   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
2196   wire width 1 \sc_decode_a_s
2197   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
2198   wire width 13 \sc_decode_a_e
2199   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
2200   wire width 53 \sc_decode_a_m
2201   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
2202   wire width 1 \sc_decode_a_is_zero
2203   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
2204   wire width 1 \sc_decode_a_is_inf
2205   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
2206   wire width 1 \sc_decode_a_is_nan
2207   cell \sc_decode_a \sc_decode_a
2208     connect \v \sc_decode_a_v
2209     connect \s \sc_decode_a_s
2210     connect \e \sc_decode_a_e
2211     connect \m \sc_decode_a_m
2212     connect \is_zero \sc_decode_a_is_zero
2213     connect \is_inf \sc_decode_a_is_inf
2214     connect \is_nan \sc_decode_a_is_nan
2215   end
2216   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
2217   wire width 64 \sc_decode_b_v
2218   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
2219   wire width 1 \sc_decode_b_s
2220   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
2221   wire width 13 \sc_decode_b_e
2222   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
2223   wire width 53 \sc_decode_b_m
2224   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
2225   wire width 1 \sc_decode_b_is_zero
2226   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
2227   wire width 1 \sc_decode_b_is_inf
2228   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
2229   wire width 1 \sc_decode_b_is_nan
2230   cell \sc_decode_b \sc_decode_b
2231     connect \v \sc_decode_b_v
2232     connect \s \sc_decode_b_s
2233     connect \e \sc_decode_b_e
2234     connect \m \sc_decode_b_m
2235     connect \is_zero \sc_decode_b_is_zero
2236     connect \is_inf \sc_decode_b_is_inf
2237     connect \is_nan \sc_decode_b_is_nan
2238   end
2239   process $group_0
2240     assign \sc_decode_a_v 64'0000000000000000000000000000000000000000000000000000000000000000
2241     assign \sc_decode_a_v \a
2242     sync init
2243   end
2244   process $group_1
2245     assign \sc_decode_b_v 64'0000000000000000000000000000000000000000000000000000000000000000
2246     assign \sc_decode_b_v \b
2247     sync init
2248   end
2249   process $group_2
2250     assign \a_s 1'0
2251     assign \a_s \sc_decode_a_s
2252     sync init
2253   end
2254   process $group_3
2255     assign \a_e 13'0000000000000
2256     assign \a_e \sc_decode_a_e
2257     sync init
2258   end
2259   process $group_4
2260     assign \a_m 53'00000000000000000000000000000000000000000000000000000
2261     assign \a_m \sc_decode_a_m
2262     sync init
2263   end
2264   process $group_5
2265     assign \b_s 1'0
2266     assign \b_s \sc_decode_b_s
2267     sync init
2268   end
2269   process $group_6
2270     assign \b_e 13'0000000000000
2271     assign \b_e \sc_decode_b_e
2272     sync init
2273   end
2274   process $group_7
2275     assign \b_m 53'00000000000000000000000000000000000000000000000000000
2276     assign \b_m \sc_decode_b_m
2277     sync init
2278   end
2279   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:57"
2280   wire width 1 \sabx
2281   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:59"
2282   wire width 1 $3
2283   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:59"
2284   cell $xor $4
2285     parameter \A_SIGNED 1'0
2286     parameter \A_WIDTH 1'1
2287     parameter \B_SIGNED 1'0
2288     parameter \B_WIDTH 1'1
2289     parameter \Y_WIDTH 1'1
2290     connect \A \sc_decode_a_s
2291     connect \B \sc_decode_b_s
2292     connect \Y $3
2293   end
2294   process $group_8
2295     assign \sabx 1'0
2296     assign \sabx $3
2297     sync init
2298   end
2299   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:52"
2300   wire width 1 \t_obz
2301   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:60"
2302   wire width 1 $5
2303   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:60"
2304   cell $or $6
2305     parameter \A_SIGNED 1'0
2306     parameter \A_WIDTH 1'1
2307     parameter \B_SIGNED 1'0
2308     parameter \B_WIDTH 1'1
2309     parameter \Y_WIDTH 1'1
2310     connect \A \sc_decode_a_is_zero
2311     connect \B \sc_decode_b_is_zero
2312     connect \Y $5
2313   end
2314   process $group_9
2315     assign \t_obz 1'0
2316     assign \t_obz $5
2317     sync init
2318   end
2319   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:53"
2320   wire width 1 \t_a1inf
2321   process $group_10
2322     assign \t_a1inf 1'0
2323     assign \t_a1inf \sc_decode_a_is_inf
2324     sync init
2325   end
2326   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:54"
2327   wire width 1 \t_b1inf
2328   process $group_11
2329     assign \t_b1inf 1'0
2330     assign \t_b1inf \sc_decode_b_is_inf
2331     sync init
2332   end
2333   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:55"
2334   wire width 1 \t_abnan
2335   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:63"
2336   wire width 1 $7
2337   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:63"
2338   cell $or $8
2339     parameter \A_SIGNED 1'0
2340     parameter \A_WIDTH 1'1
2341     parameter \B_SIGNED 1'0
2342     parameter \B_WIDTH 1'1
2343     parameter \Y_WIDTH 1'1
2344     connect \A \sc_decode_a_is_nan
2345     connect \B \sc_decode_b_is_nan
2346     connect \Y $7
2347   end
2348   process $group_12
2349     assign \t_abnan 1'0
2350     assign \t_abnan $7
2351     sync init
2352   end
2353   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:56"
2354   wire width 1 \t_special
2355   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:64"
2356   wire width 1 $9
2357   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:64"
2358   cell $reduce_bool $10
2359     parameter \A_SIGNED 1'0
2360     parameter \A_WIDTH 3'100
2361     parameter \Y_WIDTH 1'1
2362     connect \A { \t_a1inf \t_b1inf \t_abnan \t_obz }
2363     connect \Y $9
2364   end
2365   process $group_13
2366     assign \t_special 1'0
2367     assign \t_special $9
2368     sync init
2369   end
2370   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
2371   wire width 64 \z_zero_v
2372   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2373   wire width 14 $11
2374   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2375   wire width 14 $12
2376   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2377   cell $add $13
2378     parameter \A_SIGNED 1'1
2379     parameter \A_WIDTH 4'1101
2380     parameter \B_SIGNED 1'1
2381     parameter \B_WIDTH 4'1101
2382     parameter \Y_WIDTH 4'1110
2383     connect \A 13'1110000000001
2384     connect \B 13'0001111111111
2385     connect \Y $12
2386   end
2387   connect $11 $12
2388   process $group_14
2389     assign \z_zero_v 64'0000000000000000000000000000000000000000000000000000000000000000
2390     assign \z_zero_v [51:0] 52'0000000000000000000000000000000000000000000000000000
2391     assign \z_zero_v [62:52] $11 [10:0]
2392     assign \z_zero_v [63] \sabx
2393     sync init
2394   end
2395   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
2396   wire width 64 \z_nan_v
2397   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2398   wire width 14 $14
2399   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2400   wire width 14 $15
2401   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2402   cell $add $16
2403     parameter \A_SIGNED 1'1
2404     parameter \A_WIDTH 4'1101
2405     parameter \B_SIGNED 1'1
2406     parameter \B_WIDTH 4'1101
2407     parameter \Y_WIDTH 4'1110
2408     connect \A 13'0010000000000
2409     connect \B 13'0001111111111
2410     connect \Y $15
2411   end
2412   connect $14 $15
2413   wire width 1 $verilog_initial_trigger
2414   process $group_15
2415     assign \z_nan_v 64'0000000000000000000000000000000000000000000000000000000000000000
2416     assign \z_nan_v [51:0] 52'1000000000000000000000000000000000000000000000000000
2417     assign \z_nan_v [62:52] $14 [10:0]
2418     assign \z_nan_v [63] 1'0
2419     assign $verilog_initial_trigger $verilog_initial_trigger
2420     sync init
2421       update $verilog_initial_trigger 1'0
2422   end
2423   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
2424   wire width 64 \z_inf_v
2425   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2426   wire width 14 $17
2427   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2428   wire width 14 $18
2429   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
2430   cell $add $19
2431     parameter \A_SIGNED 1'1
2432     parameter \A_WIDTH 4'1101
2433     parameter \B_SIGNED 1'1
2434     parameter \B_WIDTH 4'1101
2435     parameter \Y_WIDTH 4'1110
2436     connect \A 13'0010000000000
2437     connect \B 13'0001111111111
2438     connect \Y $18
2439   end
2440   connect $17 $18
2441   process $group_16
2442     assign \z_inf_v 64'0000000000000000000000000000000000000000000000000000000000000000
2443     assign \z_inf_v [51:0] 52'0000000000000000000000000000000000000000000000000000
2444     assign \z_inf_v [62:52] $17 [10:0]
2445     assign \z_inf_v [63] \sabx
2446     sync init
2447   end
2448   process $group_17
2449     assign \out_do_z 1'0
2450     assign \out_do_z \t_special
2451     sync init
2452   end
2453   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89"
2454   wire width 64 $20
2455   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89"
2456   cell $mux $21
2457     parameter \WIDTH 7'1000000
2458     connect \A \z_inf_v
2459     connect \B \z_nan_v
2460     connect \S \sc_decode_b_is_zero
2461     connect \Y $20
2462   end
2463   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88"
2464   wire width 64 $22
2465   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88"
2466   cell $mux $23
2467     parameter \WIDTH 7'1000000
2468     connect \A \z_inf_v
2469     connect \B \z_nan_v
2470     connect \S \sc_decode_a_is_zero
2471     connect \Y $22
2472   end
2473   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:87"
2474   wire width 64 $24
2475   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:87"
2476   cell $mux $25
2477     parameter \WIDTH 7'1000000
2478     connect \A 64'0000000000000000000000000000000000000000000000000000000000000000
2479     connect \B \z_zero_v
2480     connect \S \t_obz
2481     connect \Y $24
2482   end
2483   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88"
2484   wire width 64 $26
2485   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88"
2486   cell $mux $27
2487     parameter \WIDTH 7'1000000
2488     connect \A $24
2489     connect \B $22
2490     connect \S \t_b1inf
2491     connect \Y $26
2492   end
2493   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89"
2494   wire width 64 $28
2495   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89"
2496   cell $mux $29
2497     parameter \WIDTH 7'1000000
2498     connect \A $26
2499     connect \B $20
2500     connect \S \t_a1inf
2501     connect \Y $28
2502   end
2503   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:90"
2504   wire width 64 $30
2505   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:90"
2506   cell $mux $31
2507     parameter \WIDTH 7'1000000
2508     connect \A $28
2509     connect \B \z_nan_v
2510     connect \S \t_abnan
2511     connect \Y $30
2512   end
2513   process $group_18
2514     assign \oz 64'0000000000000000000000000000000000000000000000000000000000000000
2515     assign \oz $30
2516     sync init
2517   end
2518   process $group_19
2519     assign \muxid__1 2'00
2520     assign \muxid__1 \muxid
2521     sync init
2522   end
2523   process $group_20
2524     assign \op__2 0'0
2525     assign \op__2 \op
2526     sync init
2527   end
2528   connect \op__2 0'0
2529 end
2530 attribute \generator "nMigen"
2531 attribute \nmigen.hierarchy "top.alu.scnorm.denormalise.denorm_in_a"
2532 module \denorm_in_a
2533   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
2534   wire width 13 input 0 \a_e
2535   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
2536   wire width 53 input 1 \a_m
2537   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
2538   wire width 1 output 2 \exp_n127
2539   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
2540   wire width 1 \is_nan
2541   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
2542   wire width 1 \exp_128
2543   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2544   wire width 1 $1
2545   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
2546   wire width 1 \m_zero
2547   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2548   cell $not $2
2549     parameter \A_SIGNED 1'0
2550     parameter \A_WIDTH 1'1
2551     parameter \Y_WIDTH 1'1
2552     connect \A \m_zero
2553     connect \Y $1
2554   end
2555   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2556   wire width 1 $3
2557   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2558   cell $and $4
2559     parameter \A_SIGNED 1'0
2560     parameter \A_WIDTH 1'1
2561     parameter \B_SIGNED 1'0
2562     parameter \B_WIDTH 1'1
2563     parameter \Y_WIDTH 1'1
2564     connect \A \exp_128
2565     connect \B $1
2566     connect \Y $3
2567   end
2568   process $group_0
2569     assign \is_nan 1'0
2570     assign \is_nan $3
2571     sync init
2572   end
2573   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
2574   wire width 1 \is_zero
2575   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
2576   wire width 1 $5
2577   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
2578   cell $and $6
2579     parameter \A_SIGNED 1'0
2580     parameter \A_WIDTH 1'1
2581     parameter \B_SIGNED 1'0
2582     parameter \B_WIDTH 1'1
2583     parameter \Y_WIDTH 1'1
2584     connect \A \exp_n127
2585     connect \B \m_zero
2586     connect \Y $5
2587   end
2588   process $group_1
2589     assign \is_zero 1'0
2590     assign \is_zero $5
2591     sync init
2592   end
2593   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
2594   wire width 1 \is_inf
2595   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
2596   wire width 1 $7
2597   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
2598   cell $and $8
2599     parameter \A_SIGNED 1'0
2600     parameter \A_WIDTH 1'1
2601     parameter \B_SIGNED 1'0
2602     parameter \B_WIDTH 1'1
2603     parameter \Y_WIDTH 1'1
2604     connect \A \exp_128
2605     connect \B \m_zero
2606     connect \Y $7
2607   end
2608   process $group_2
2609     assign \is_inf 1'0
2610     assign \is_inf $7
2611     sync init
2612   end
2613   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
2614   wire width 1 \is_overflowed
2615   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
2616   wire width 1 \exp_gt127
2617   process $group_3
2618     assign \is_overflowed 1'0
2619     assign \is_overflowed \exp_gt127
2620     sync init
2621   end
2622   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
2623   wire width 1 \is_denormalised
2624   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
2625   wire width 1 \exp_n126
2626   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
2627   wire width 1 \m_msbzero
2628   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
2629   wire width 1 $9
2630   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
2631   cell $and $10
2632     parameter \A_SIGNED 1'0
2633     parameter \A_WIDTH 1'1
2634     parameter \B_SIGNED 1'0
2635     parameter \B_WIDTH 1'1
2636     parameter \Y_WIDTH 1'1
2637     connect \A \exp_n126
2638     connect \B \m_msbzero
2639     connect \Y $9
2640   end
2641   process $group_4
2642     assign \is_denormalised 1'0
2643     assign \is_denormalised $9
2644     sync init
2645   end
2646   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
2647   wire width 1 $11
2648   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
2649   cell $eq $12
2650     parameter \A_SIGNED 1'1
2651     parameter \A_WIDTH 4'1101
2652     parameter \B_SIGNED 1'1
2653     parameter \B_WIDTH 4'1101
2654     parameter \Y_WIDTH 1'1
2655     connect \A \a_e
2656     connect \B 13'0010000000000
2657     connect \Y $11
2658   end
2659   process $group_5
2660     assign \exp_128 1'0
2661     assign \exp_128 $11
2662     sync init
2663   end
2664   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
2665   wire width 13 \exp_sub_n126
2666   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
2667   wire width 14 $13
2668   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
2669   wire width 14 $14
2670   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
2671   cell $sub $15
2672     parameter \A_SIGNED 1'1
2673     parameter \A_WIDTH 4'1101
2674     parameter \B_SIGNED 1'1
2675     parameter \B_WIDTH 4'1101
2676     parameter \Y_WIDTH 4'1110
2677     connect \A \a_e
2678     connect \B 13'1110000000010
2679     connect \Y $14
2680   end
2681   connect $13 $14
2682   process $group_6
2683     assign \exp_sub_n126 13'0000000000000
2684     assign \exp_sub_n126 $13 [12:0]
2685     sync init
2686   end
2687   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
2688   wire width 1 \exp_gt_n126
2689   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
2690   wire width 1 $16
2691   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
2692   cell $gt $17
2693     parameter \A_SIGNED 1'1
2694     parameter \A_WIDTH 4'1101
2695     parameter \B_SIGNED 1'1
2696     parameter \B_WIDTH 4'1101
2697     parameter \Y_WIDTH 1'1
2698     connect \A \exp_sub_n126
2699     connect \B 13'0000000000000
2700     connect \Y $16
2701   end
2702   process $group_7
2703     assign \exp_gt_n126 1'0
2704     assign \exp_gt_n126 $16
2705     sync init
2706   end
2707   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
2708   wire width 1 \exp_lt_n126
2709   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
2710   wire width 1 $18
2711   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
2712   cell $lt $19
2713     parameter \A_SIGNED 1'1
2714     parameter \A_WIDTH 4'1101
2715     parameter \B_SIGNED 1'1
2716     parameter \B_WIDTH 4'1101
2717     parameter \Y_WIDTH 1'1
2718     connect \A \exp_sub_n126
2719     connect \B 13'0000000000000
2720     connect \Y $18
2721   end
2722   process $group_8
2723     assign \exp_lt_n126 1'0
2724     assign \exp_lt_n126 $18
2725     sync init
2726   end
2727   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
2728   wire width 1 \exp_zero
2729   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
2730   wire width 1 $20
2731   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
2732   cell $eq $21
2733     parameter \A_SIGNED 1'1
2734     parameter \A_WIDTH 4'1101
2735     parameter \B_SIGNED 1'1
2736     parameter \B_WIDTH 4'1101
2737     parameter \Y_WIDTH 1'1
2738     connect \A \a_e
2739     connect \B 13'0000000000000
2740     connect \Y $20
2741   end
2742   process $group_9
2743     assign \exp_zero 1'0
2744     assign \exp_zero $20
2745     sync init
2746   end
2747   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
2748   wire width 1 $22
2749   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
2750   cell $gt $23
2751     parameter \A_SIGNED 1'1
2752     parameter \A_WIDTH 4'1101
2753     parameter \B_SIGNED 1'1
2754     parameter \B_WIDTH 4'1101
2755     parameter \Y_WIDTH 1'1
2756     connect \A \a_e
2757     connect \B 13'0001111111111
2758     connect \Y $22
2759   end
2760   process $group_10
2761     assign \exp_gt127 1'0
2762     assign \exp_gt127 $22
2763     sync init
2764   end
2765   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
2766   wire width 1 $24
2767   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
2768   cell $eq $25
2769     parameter \A_SIGNED 1'1
2770     parameter \A_WIDTH 4'1101
2771     parameter \B_SIGNED 1'1
2772     parameter \B_WIDTH 4'1101
2773     parameter \Y_WIDTH 1'1
2774     connect \A \a_e
2775     connect \B 13'1110000000001
2776     connect \Y $24
2777   end
2778   process $group_11
2779     assign \exp_n127 1'0
2780     assign \exp_n127 $24
2781     sync init
2782   end
2783   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
2784   wire width 1 $26
2785   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
2786   cell $eq $27
2787     parameter \A_SIGNED 1'1
2788     parameter \A_WIDTH 4'1101
2789     parameter \B_SIGNED 1'1
2790     parameter \B_WIDTH 4'1101
2791     parameter \Y_WIDTH 1'1
2792     connect \A \a_e
2793     connect \B 13'1110000000010
2794     connect \Y $26
2795   end
2796   process $group_12
2797     assign \exp_n126 1'0
2798     assign \exp_n126 $26
2799     sync init
2800   end
2801   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
2802   wire width 1 $28
2803   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
2804   cell $eq $29
2805     parameter \A_SIGNED 1'0
2806     parameter \A_WIDTH 6'110101
2807     parameter \B_SIGNED 1'0
2808     parameter \B_WIDTH 6'110101
2809     parameter \Y_WIDTH 1'1
2810     connect \A \a_m
2811     connect \B 53'00000000000000000000000000000000000000000000000000000
2812     connect \Y $28
2813   end
2814   process $group_13
2815     assign \m_zero 1'0
2816     assign \m_zero $28
2817     sync init
2818   end
2819   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
2820   wire width 1 $30
2821   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
2822   cell $eq $31
2823     parameter \A_SIGNED 1'0
2824     parameter \A_WIDTH 1'1
2825     parameter \B_SIGNED 1'0
2826     parameter \B_WIDTH 1'1
2827     parameter \Y_WIDTH 1'1
2828     connect \A \a_m [52]
2829     connect \B 1'0
2830     connect \Y $30
2831   end
2832   process $group_14
2833     assign \m_msbzero 1'0
2834     assign \m_msbzero $30
2835     sync init
2836   end
2837 end
2838 attribute \generator "nMigen"
2839 attribute \nmigen.hierarchy "top.alu.scnorm.denormalise.denorm_in_b"
2840 module \denorm_in_b
2841   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
2842   wire width 13 input 0 \b_e
2843   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
2844   wire width 53 input 1 \b_m
2845   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
2846   wire width 1 output 2 \exp_n127
2847   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
2848   wire width 1 \is_nan
2849   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
2850   wire width 1 \exp_128
2851   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2852   wire width 1 $1
2853   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
2854   wire width 1 \m_zero
2855   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2856   cell $not $2
2857     parameter \A_SIGNED 1'0
2858     parameter \A_WIDTH 1'1
2859     parameter \Y_WIDTH 1'1
2860     connect \A \m_zero
2861     connect \Y $1
2862   end
2863   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2864   wire width 1 $3
2865   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
2866   cell $and $4
2867     parameter \A_SIGNED 1'0
2868     parameter \A_WIDTH 1'1
2869     parameter \B_SIGNED 1'0
2870     parameter \B_WIDTH 1'1
2871     parameter \Y_WIDTH 1'1
2872     connect \A \exp_128
2873     connect \B $1
2874     connect \Y $3
2875   end
2876   process $group_0
2877     assign \is_nan 1'0
2878     assign \is_nan $3
2879     sync init
2880   end
2881   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
2882   wire width 1 \is_zero
2883   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
2884   wire width 1 $5
2885   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
2886   cell $and $6
2887     parameter \A_SIGNED 1'0
2888     parameter \A_WIDTH 1'1
2889     parameter \B_SIGNED 1'0
2890     parameter \B_WIDTH 1'1
2891     parameter \Y_WIDTH 1'1
2892     connect \A \exp_n127
2893     connect \B \m_zero
2894     connect \Y $5
2895   end
2896   process $group_1
2897     assign \is_zero 1'0
2898     assign \is_zero $5
2899     sync init
2900   end
2901   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
2902   wire width 1 \is_inf
2903   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
2904   wire width 1 $7
2905   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
2906   cell $and $8
2907     parameter \A_SIGNED 1'0
2908     parameter \A_WIDTH 1'1
2909     parameter \B_SIGNED 1'0
2910     parameter \B_WIDTH 1'1
2911     parameter \Y_WIDTH 1'1
2912     connect \A \exp_128
2913     connect \B \m_zero
2914     connect \Y $7
2915   end
2916   process $group_2
2917     assign \is_inf 1'0
2918     assign \is_inf $7
2919     sync init
2920   end
2921   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
2922   wire width 1 \is_overflowed
2923   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
2924   wire width 1 \exp_gt127
2925   process $group_3
2926     assign \is_overflowed 1'0
2927     assign \is_overflowed \exp_gt127
2928     sync init
2929   end
2930   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
2931   wire width 1 \is_denormalised
2932   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
2933   wire width 1 \exp_n126
2934   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
2935   wire width 1 \m_msbzero
2936   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
2937   wire width 1 $9
2938   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
2939   cell $and $10
2940     parameter \A_SIGNED 1'0
2941     parameter \A_WIDTH 1'1
2942     parameter \B_SIGNED 1'0
2943     parameter \B_WIDTH 1'1
2944     parameter \Y_WIDTH 1'1
2945     connect \A \exp_n126
2946     connect \B \m_msbzero
2947     connect \Y $9
2948   end
2949   process $group_4
2950     assign \is_denormalised 1'0
2951     assign \is_denormalised $9
2952     sync init
2953   end
2954   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
2955   wire width 1 $11
2956   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
2957   cell $eq $12
2958     parameter \A_SIGNED 1'1
2959     parameter \A_WIDTH 4'1101
2960     parameter \B_SIGNED 1'1
2961     parameter \B_WIDTH 4'1101
2962     parameter \Y_WIDTH 1'1
2963     connect \A \b_e
2964     connect \B 13'0010000000000
2965     connect \Y $11
2966   end
2967   process $group_5
2968     assign \exp_128 1'0
2969     assign \exp_128 $11
2970     sync init
2971   end
2972   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
2973   wire width 13 \exp_sub_n126
2974   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
2975   wire width 14 $13
2976   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
2977   wire width 14 $14
2978   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
2979   cell $sub $15
2980     parameter \A_SIGNED 1'1
2981     parameter \A_WIDTH 4'1101
2982     parameter \B_SIGNED 1'1
2983     parameter \B_WIDTH 4'1101
2984     parameter \Y_WIDTH 4'1110
2985     connect \A \b_e
2986     connect \B 13'1110000000010
2987     connect \Y $14
2988   end
2989   connect $13 $14
2990   process $group_6
2991     assign \exp_sub_n126 13'0000000000000
2992     assign \exp_sub_n126 $13 [12:0]
2993     sync init
2994   end
2995   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
2996   wire width 1 \exp_gt_n126
2997   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
2998   wire width 1 $16
2999   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
3000   cell $gt $17
3001     parameter \A_SIGNED 1'1
3002     parameter \A_WIDTH 4'1101
3003     parameter \B_SIGNED 1'1
3004     parameter \B_WIDTH 4'1101
3005     parameter \Y_WIDTH 1'1
3006     connect \A \exp_sub_n126
3007     connect \B 13'0000000000000
3008     connect \Y $16
3009   end
3010   process $group_7
3011     assign \exp_gt_n126 1'0
3012     assign \exp_gt_n126 $16
3013     sync init
3014   end
3015   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
3016   wire width 1 \exp_lt_n126
3017   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
3018   wire width 1 $18
3019   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
3020   cell $lt $19
3021     parameter \A_SIGNED 1'1
3022     parameter \A_WIDTH 4'1101
3023     parameter \B_SIGNED 1'1
3024     parameter \B_WIDTH 4'1101
3025     parameter \Y_WIDTH 1'1
3026     connect \A \exp_sub_n126
3027     connect \B 13'0000000000000
3028     connect \Y $18
3029   end
3030   process $group_8
3031     assign \exp_lt_n126 1'0
3032     assign \exp_lt_n126 $18
3033     sync init
3034   end
3035   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
3036   wire width 1 \exp_zero
3037   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
3038   wire width 1 $20
3039   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
3040   cell $eq $21
3041     parameter \A_SIGNED 1'1
3042     parameter \A_WIDTH 4'1101
3043     parameter \B_SIGNED 1'1
3044     parameter \B_WIDTH 4'1101
3045     parameter \Y_WIDTH 1'1
3046     connect \A \b_e
3047     connect \B 13'0000000000000
3048     connect \Y $20
3049   end
3050   process $group_9
3051     assign \exp_zero 1'0
3052     assign \exp_zero $20
3053     sync init
3054   end
3055   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
3056   wire width 1 $22
3057   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
3058   cell $gt $23
3059     parameter \A_SIGNED 1'1
3060     parameter \A_WIDTH 4'1101
3061     parameter \B_SIGNED 1'1
3062     parameter \B_WIDTH 4'1101
3063     parameter \Y_WIDTH 1'1
3064     connect \A \b_e
3065     connect \B 13'0001111111111
3066     connect \Y $22
3067   end
3068   process $group_10
3069     assign \exp_gt127 1'0
3070     assign \exp_gt127 $22
3071     sync init
3072   end
3073   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
3074   wire width 1 $24
3075   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
3076   cell $eq $25
3077     parameter \A_SIGNED 1'1
3078     parameter \A_WIDTH 4'1101
3079     parameter \B_SIGNED 1'1
3080     parameter \B_WIDTH 4'1101
3081     parameter \Y_WIDTH 1'1
3082     connect \A \b_e
3083     connect \B 13'1110000000001
3084     connect \Y $24
3085   end
3086   process $group_11
3087     assign \exp_n127 1'0
3088     assign \exp_n127 $24
3089     sync init
3090   end
3091   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
3092   wire width 1 $26
3093   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
3094   cell $eq $27
3095     parameter \A_SIGNED 1'1
3096     parameter \A_WIDTH 4'1101
3097     parameter \B_SIGNED 1'1
3098     parameter \B_WIDTH 4'1101
3099     parameter \Y_WIDTH 1'1
3100     connect \A \b_e
3101     connect \B 13'1110000000010
3102     connect \Y $26
3103   end
3104   process $group_12
3105     assign \exp_n126 1'0
3106     assign \exp_n126 $26
3107     sync init
3108   end
3109   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
3110   wire width 1 $28
3111   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
3112   cell $eq $29
3113     parameter \A_SIGNED 1'0
3114     parameter \A_WIDTH 6'110101
3115     parameter \B_SIGNED 1'0
3116     parameter \B_WIDTH 6'110101
3117     parameter \Y_WIDTH 1'1
3118     connect \A \b_m
3119     connect \B 53'00000000000000000000000000000000000000000000000000000
3120     connect \Y $28
3121   end
3122   process $group_13
3123     assign \m_zero 1'0
3124     assign \m_zero $28
3125     sync init
3126   end
3127   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
3128   wire width 1 $30
3129   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
3130   cell $eq $31
3131     parameter \A_SIGNED 1'0
3132     parameter \A_WIDTH 1'1
3133     parameter \B_SIGNED 1'0
3134     parameter \B_WIDTH 1'1
3135     parameter \Y_WIDTH 1'1
3136     connect \A \b_m [52]
3137     connect \B 1'0
3138     connect \Y $30
3139   end
3140   process $group_14
3141     assign \m_msbzero 1'0
3142     assign \m_msbzero $30
3143     sync init
3144   end
3145 end
3146 attribute \generator "nMigen"
3147 attribute \nmigen.hierarchy "top.alu.scnorm.denormalise"
3148 module \denormalise
3149   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
3150   wire width 1 input 0 \z_s
3151   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3152   wire width 13 input 1 \z_e
3153   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3154   wire width 53 input 2 \z_m
3155   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
3156   wire width 1 input 3 \out_do_z
3157   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
3158   wire width 64 input 4 \oz
3159   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
3160   wire width 1 input 5 \a_s
3161   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3162   wire width 13 input 6 \a_e
3163   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3164   wire width 53 input 7 \a_m
3165   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
3166   wire width 1 input 8 \b_s
3167   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3168   wire width 13 input 9 \b_e
3169   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3170   wire width 53 input 10 \b_m
3171   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
3172   wire width 2 input 11 \muxid
3173   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
3174   wire width 0 input 12 \op
3175   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
3176   wire width 1 output 13 \z_s__1
3177   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3178   wire width 13 output 14 \z_e__2
3179   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3180   wire width 53 output 15 \z_m__3
3181   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
3182   wire width 1 output 16 \out_do_z__4
3183   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
3184   wire width 64 output 17 \oz__5
3185   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
3186   wire width 1 output 18 \a_s__6
3187   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3188   wire width 13 output 19 \a_e__7
3189   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3190   wire width 53 output 20 \a_m__8
3191   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
3192   wire width 1 output 21 \b_s__9
3193   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3194   wire width 13 output 22 \b_e__10
3195   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3196   wire width 53 output 23 \b_m__11
3197   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
3198   wire width 2 output 24 \muxid__12
3199   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
3200   wire width 0 output 25 \op__13
3201   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
3202   wire width 1 \denorm_in_a_exp_n127
3203   cell \denorm_in_a \denorm_in_a
3204     connect \a_e \a_e
3205     connect \a_m \a_m
3206     connect \exp_n127 \denorm_in_a_exp_n127
3207   end
3208   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
3209   wire width 1 \denorm_in_b_exp_n127
3210   cell \denorm_in_b \denorm_in_b
3211     connect \b_e \b_e
3212     connect \b_m \b_m
3213     connect \exp_n127 \denorm_in_b_exp_n127
3214   end
3215   process $group_0
3216     assign \a_s__6 1'0
3217     assign \a_s__6 \a_s
3218     sync init
3219   end
3220   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:40"
3221   wire width 13 $14
3222   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:40"
3223   cell $mux $15
3224     parameter \WIDTH 4'1101
3225     connect \A \a_e
3226     connect \B 13'1110000000010
3227     connect \S \denorm_in_a_exp_n127
3228     connect \Y $14
3229   end
3230   process $group_1
3231     assign \a_e__7 13'0000000000000
3232     assign \a_e__7 \a_e
3233     assign \a_e__7 $14
3234     sync init
3235   end
3236   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:41"
3237   wire width 1 $16
3238   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:41"
3239   cell $mux $17
3240     parameter \WIDTH 1'1
3241     connect \A 1'1
3242     connect \B \a_m [52]
3243     connect \S \denorm_in_a_exp_n127
3244     connect \Y $16
3245   end
3246   process $group_2
3247     assign \a_m__8 53'00000000000000000000000000000000000000000000000000000
3248     assign \a_m__8 \a_m
3249     assign \a_m__8 [52] $16
3250     sync init
3251   end
3252   process $group_3
3253     assign \b_s__9 1'0
3254     assign \b_s__9 \b_s
3255     sync init
3256   end
3257   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:48"
3258   wire width 13 $18
3259   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:48"
3260   cell $mux $19
3261     parameter \WIDTH 4'1101
3262     connect \A \b_e
3263     connect \B 13'1110000000010
3264     connect \S \denorm_in_b_exp_n127
3265     connect \Y $18
3266   end
3267   process $group_4
3268     assign \b_e__10 13'0000000000000
3269     assign \b_e__10 \b_e
3270     assign \b_e__10 $18
3271     sync init
3272   end
3273   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:49"
3274   wire width 1 $20
3275   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:49"
3276   cell $mux $21
3277     parameter \WIDTH 1'1
3278     connect \A 1'1
3279     connect \B \b_m [52]
3280     connect \S \denorm_in_b_exp_n127
3281     connect \Y $20
3282   end
3283   process $group_5
3284     assign \b_m__11 53'00000000000000000000000000000000000000000000000000000
3285     assign \b_m__11 \b_m
3286     assign \b_m__11 [52] $20
3287     sync init
3288   end
3289   process $group_6
3290     assign \muxid__12 2'00
3291     assign \muxid__12 \muxid
3292     sync init
3293   end
3294   process $group_7
3295     assign \op__13 0'0
3296     assign \op__13 \op
3297     sync init
3298   end
3299   process $group_8
3300     assign \z_s__1 1'0
3301     assign \z_s__1 \z_s
3302     sync init
3303   end
3304   process $group_9
3305     assign \z_e__2 13'0000000000000
3306     assign \z_e__2 \z_e
3307     sync init
3308   end
3309   process $group_10
3310     assign \z_m__3 53'00000000000000000000000000000000000000000000000000000
3311     assign \z_m__3 \z_m
3312     sync init
3313   end
3314   process $group_11
3315     assign \out_do_z__4 1'0
3316     assign \out_do_z__4 \out_do_z
3317     sync init
3318   end
3319   process $group_12
3320     assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000
3321     assign \oz__5 \oz
3322     sync init
3323   end
3324   connect \op__13 0'0
3325 end
3326 attribute \generator "nMigen"
3327 attribute \nmigen.hierarchy "top.alu.scnorm.align.norm1_insel_a"
3328 module \norm1_insel_a
3329   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3330   wire width 13 input 0 \a_e
3331   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3332   wire width 53 input 1 \i_a_m
3333   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
3334   wire width 1 output 2 \m_msbzero
3335   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
3336   wire width 1 \is_nan
3337   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
3338   wire width 1 \exp_128
3339   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3340   wire width 1 $1
3341   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
3342   wire width 1 \m_zero
3343   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3344   cell $not $2
3345     parameter \A_SIGNED 1'0
3346     parameter \A_WIDTH 1'1
3347     parameter \Y_WIDTH 1'1
3348     connect \A \m_zero
3349     connect \Y $1
3350   end
3351   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3352   wire width 1 $3
3353   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3354   cell $and $4
3355     parameter \A_SIGNED 1'0
3356     parameter \A_WIDTH 1'1
3357     parameter \B_SIGNED 1'0
3358     parameter \B_WIDTH 1'1
3359     parameter \Y_WIDTH 1'1
3360     connect \A \exp_128
3361     connect \B $1
3362     connect \Y $3
3363   end
3364   process $group_0
3365     assign \is_nan 1'0
3366     assign \is_nan $3
3367     sync init
3368   end
3369   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
3370   wire width 1 \is_zero
3371   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
3372   wire width 1 \exp_n127
3373   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
3374   wire width 1 $5
3375   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
3376   cell $and $6
3377     parameter \A_SIGNED 1'0
3378     parameter \A_WIDTH 1'1
3379     parameter \B_SIGNED 1'0
3380     parameter \B_WIDTH 1'1
3381     parameter \Y_WIDTH 1'1
3382     connect \A \exp_n127
3383     connect \B \m_zero
3384     connect \Y $5
3385   end
3386   process $group_1
3387     assign \is_zero 1'0
3388     assign \is_zero $5
3389     sync init
3390   end
3391   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
3392   wire width 1 \is_inf
3393   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
3394   wire width 1 $7
3395   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
3396   cell $and $8
3397     parameter \A_SIGNED 1'0
3398     parameter \A_WIDTH 1'1
3399     parameter \B_SIGNED 1'0
3400     parameter \B_WIDTH 1'1
3401     parameter \Y_WIDTH 1'1
3402     connect \A \exp_128
3403     connect \B \m_zero
3404     connect \Y $7
3405   end
3406   process $group_2
3407     assign \is_inf 1'0
3408     assign \is_inf $7
3409     sync init
3410   end
3411   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
3412   wire width 1 \is_overflowed
3413   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
3414   wire width 1 \exp_gt127
3415   process $group_3
3416     assign \is_overflowed 1'0
3417     assign \is_overflowed \exp_gt127
3418     sync init
3419   end
3420   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
3421   wire width 1 \is_denormalised
3422   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
3423   wire width 1 \exp_n126
3424   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
3425   wire width 1 $9
3426   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
3427   cell $and $10
3428     parameter \A_SIGNED 1'0
3429     parameter \A_WIDTH 1'1
3430     parameter \B_SIGNED 1'0
3431     parameter \B_WIDTH 1'1
3432     parameter \Y_WIDTH 1'1
3433     connect \A \exp_n126
3434     connect \B \m_msbzero
3435     connect \Y $9
3436   end
3437   process $group_4
3438     assign \is_denormalised 1'0
3439     assign \is_denormalised $9
3440     sync init
3441   end
3442   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
3443   wire width 1 $11
3444   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
3445   cell $eq $12
3446     parameter \A_SIGNED 1'1
3447     parameter \A_WIDTH 4'1101
3448     parameter \B_SIGNED 1'1
3449     parameter \B_WIDTH 4'1101
3450     parameter \Y_WIDTH 1'1
3451     connect \A \a_e
3452     connect \B 13'0010000000000
3453     connect \Y $11
3454   end
3455   process $group_5
3456     assign \exp_128 1'0
3457     assign \exp_128 $11
3458     sync init
3459   end
3460   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
3461   wire width 13 \exp_sub_n126
3462   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
3463   wire width 14 $13
3464   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
3465   wire width 14 $14
3466   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
3467   cell $sub $15
3468     parameter \A_SIGNED 1'1
3469     parameter \A_WIDTH 4'1101
3470     parameter \B_SIGNED 1'1
3471     parameter \B_WIDTH 4'1101
3472     parameter \Y_WIDTH 4'1110
3473     connect \A \a_e
3474     connect \B 13'1110000000010
3475     connect \Y $14
3476   end
3477   connect $13 $14
3478   process $group_6
3479     assign \exp_sub_n126 13'0000000000000
3480     assign \exp_sub_n126 $13 [12:0]
3481     sync init
3482   end
3483   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
3484   wire width 1 \exp_gt_n126
3485   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
3486   wire width 1 $16
3487   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
3488   cell $gt $17
3489     parameter \A_SIGNED 1'1
3490     parameter \A_WIDTH 4'1101
3491     parameter \B_SIGNED 1'1
3492     parameter \B_WIDTH 4'1101
3493     parameter \Y_WIDTH 1'1
3494     connect \A \exp_sub_n126
3495     connect \B 13'0000000000000
3496     connect \Y $16
3497   end
3498   process $group_7
3499     assign \exp_gt_n126 1'0
3500     assign \exp_gt_n126 $16
3501     sync init
3502   end
3503   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
3504   wire width 1 \exp_lt_n126
3505   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
3506   wire width 1 $18
3507   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
3508   cell $lt $19
3509     parameter \A_SIGNED 1'1
3510     parameter \A_WIDTH 4'1101
3511     parameter \B_SIGNED 1'1
3512     parameter \B_WIDTH 4'1101
3513     parameter \Y_WIDTH 1'1
3514     connect \A \exp_sub_n126
3515     connect \B 13'0000000000000
3516     connect \Y $18
3517   end
3518   process $group_8
3519     assign \exp_lt_n126 1'0
3520     assign \exp_lt_n126 $18
3521     sync init
3522   end
3523   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
3524   wire width 1 \exp_zero
3525   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
3526   wire width 1 $20
3527   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
3528   cell $eq $21
3529     parameter \A_SIGNED 1'1
3530     parameter \A_WIDTH 4'1101
3531     parameter \B_SIGNED 1'1
3532     parameter \B_WIDTH 4'1101
3533     parameter \Y_WIDTH 1'1
3534     connect \A \a_e
3535     connect \B 13'0000000000000
3536     connect \Y $20
3537   end
3538   process $group_9
3539     assign \exp_zero 1'0
3540     assign \exp_zero $20
3541     sync init
3542   end
3543   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
3544   wire width 1 $22
3545   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
3546   cell $gt $23
3547     parameter \A_SIGNED 1'1
3548     parameter \A_WIDTH 4'1101
3549     parameter \B_SIGNED 1'1
3550     parameter \B_WIDTH 4'1101
3551     parameter \Y_WIDTH 1'1
3552     connect \A \a_e
3553     connect \B 13'0001111111111
3554     connect \Y $22
3555   end
3556   process $group_10
3557     assign \exp_gt127 1'0
3558     assign \exp_gt127 $22
3559     sync init
3560   end
3561   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
3562   wire width 1 $24
3563   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
3564   cell $eq $25
3565     parameter \A_SIGNED 1'1
3566     parameter \A_WIDTH 4'1101
3567     parameter \B_SIGNED 1'1
3568     parameter \B_WIDTH 4'1101
3569     parameter \Y_WIDTH 1'1
3570     connect \A \a_e
3571     connect \B 13'1110000000001
3572     connect \Y $24
3573   end
3574   process $group_11
3575     assign \exp_n127 1'0
3576     assign \exp_n127 $24
3577     sync init
3578   end
3579   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
3580   wire width 1 $26
3581   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
3582   cell $eq $27
3583     parameter \A_SIGNED 1'1
3584     parameter \A_WIDTH 4'1101
3585     parameter \B_SIGNED 1'1
3586     parameter \B_WIDTH 4'1101
3587     parameter \Y_WIDTH 1'1
3588     connect \A \a_e
3589     connect \B 13'1110000000010
3590     connect \Y $26
3591   end
3592   process $group_12
3593     assign \exp_n126 1'0
3594     assign \exp_n126 $26
3595     sync init
3596   end
3597   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
3598   wire width 1 $28
3599   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
3600   cell $eq $29
3601     parameter \A_SIGNED 1'0
3602     parameter \A_WIDTH 6'110101
3603     parameter \B_SIGNED 1'0
3604     parameter \B_WIDTH 6'110101
3605     parameter \Y_WIDTH 1'1
3606     connect \A \i_a_m
3607     connect \B 53'00000000000000000000000000000000000000000000000000000
3608     connect \Y $28
3609   end
3610   process $group_13
3611     assign \m_zero 1'0
3612     assign \m_zero $28
3613     sync init
3614   end
3615   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
3616   wire width 1 $30
3617   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
3618   cell $eq $31
3619     parameter \A_SIGNED 1'0
3620     parameter \A_WIDTH 1'1
3621     parameter \B_SIGNED 1'0
3622     parameter \B_WIDTH 1'1
3623     parameter \Y_WIDTH 1'1
3624     connect \A \i_a_m [52]
3625     connect \B 1'0
3626     connect \Y $30
3627   end
3628   process $group_14
3629     assign \m_msbzero 1'0
3630     assign \m_msbzero $30
3631     sync init
3632   end
3633 end
3634 attribute \generator "nMigen"
3635 attribute \nmigen.hierarchy "top.alu.scnorm.align.norm1_insel_b"
3636 module \norm1_insel_b
3637   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
3638   wire width 13 input 0 \b_e
3639   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
3640   wire width 53 input 1 \i_b_m
3641   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
3642   wire width 1 output 2 \m_msbzero
3643   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
3644   wire width 1 \is_nan
3645   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
3646   wire width 1 \exp_128
3647   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3648   wire width 1 $1
3649   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
3650   wire width 1 \m_zero
3651   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3652   cell $not $2
3653     parameter \A_SIGNED 1'0
3654     parameter \A_WIDTH 1'1
3655     parameter \Y_WIDTH 1'1
3656     connect \A \m_zero
3657     connect \Y $1
3658   end
3659   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3660   wire width 1 $3
3661   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
3662   cell $and $4
3663     parameter \A_SIGNED 1'0
3664     parameter \A_WIDTH 1'1
3665     parameter \B_SIGNED 1'0
3666     parameter \B_WIDTH 1'1
3667     parameter \Y_WIDTH 1'1
3668     connect \A \exp_128
3669     connect \B $1
3670     connect \Y $3
3671   end
3672   process $group_0
3673     assign \is_nan 1'0
3674     assign \is_nan $3
3675     sync init
3676   end
3677   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
3678   wire width 1 \is_zero
3679   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
3680   wire width 1 \exp_n127
3681   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
3682   wire width 1 $5
3683   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
3684   cell $and $6
3685     parameter \A_SIGNED 1'0
3686     parameter \A_WIDTH 1'1
3687     parameter \B_SIGNED 1'0
3688     parameter \B_WIDTH 1'1
3689     parameter \Y_WIDTH 1'1
3690     connect \A \exp_n127
3691     connect \B \m_zero
3692     connect \Y $5
3693   end
3694   process $group_1
3695     assign \is_zero 1'0
3696     assign \is_zero $5
3697     sync init
3698   end
3699   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
3700   wire width 1 \is_inf
3701   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
3702   wire width 1 $7
3703   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
3704   cell $and $8
3705     parameter \A_SIGNED 1'0
3706     parameter \A_WIDTH 1'1
3707     parameter \B_SIGNED 1'0
3708     parameter \B_WIDTH 1'1
3709     parameter \Y_WIDTH 1'1
3710     connect \A \exp_128
3711     connect \B \m_zero
3712     connect \Y $7
3713   end
3714   process $group_2
3715     assign \is_inf 1'0
3716     assign \is_inf $7
3717     sync init
3718   end
3719   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
3720   wire width 1 \is_overflowed
3721   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
3722   wire width 1 \exp_gt127
3723   process $group_3
3724     assign \is_overflowed 1'0
3725     assign \is_overflowed \exp_gt127
3726     sync init
3727   end
3728   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
3729   wire width 1 \is_denormalised
3730   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
3731   wire width 1 \exp_n126
3732   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
3733   wire width 1 $9
3734   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
3735   cell $and $10
3736     parameter \A_SIGNED 1'0
3737     parameter \A_WIDTH 1'1
3738     parameter \B_SIGNED 1'0
3739     parameter \B_WIDTH 1'1
3740     parameter \Y_WIDTH 1'1
3741     connect \A \exp_n126
3742     connect \B \m_msbzero
3743     connect \Y $9
3744   end
3745   process $group_4
3746     assign \is_denormalised 1'0
3747     assign \is_denormalised $9
3748     sync init
3749   end
3750   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
3751   wire width 1 $11
3752   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
3753   cell $eq $12
3754     parameter \A_SIGNED 1'1
3755     parameter \A_WIDTH 4'1101
3756     parameter \B_SIGNED 1'1
3757     parameter \B_WIDTH 4'1101
3758     parameter \Y_WIDTH 1'1
3759     connect \A \b_e
3760     connect \B 13'0010000000000
3761     connect \Y $11
3762   end
3763   process $group_5
3764     assign \exp_128 1'0
3765     assign \exp_128 $11
3766     sync init
3767   end
3768   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
3769   wire width 13 \exp_sub_n126
3770   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
3771   wire width 14 $13
3772   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
3773   wire width 14 $14
3774   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
3775   cell $sub $15
3776     parameter \A_SIGNED 1'1
3777     parameter \A_WIDTH 4'1101
3778     parameter \B_SIGNED 1'1
3779     parameter \B_WIDTH 4'1101
3780     parameter \Y_WIDTH 4'1110
3781     connect \A \b_e
3782     connect \B 13'1110000000010
3783     connect \Y $14
3784   end
3785   connect $13 $14
3786   process $group_6
3787     assign \exp_sub_n126 13'0000000000000
3788     assign \exp_sub_n126 $13 [12:0]
3789     sync init
3790   end
3791   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
3792   wire width 1 \exp_gt_n126
3793   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
3794   wire width 1 $16
3795   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
3796   cell $gt $17
3797     parameter \A_SIGNED 1'1
3798     parameter \A_WIDTH 4'1101
3799     parameter \B_SIGNED 1'1
3800     parameter \B_WIDTH 4'1101
3801     parameter \Y_WIDTH 1'1
3802     connect \A \exp_sub_n126
3803     connect \B 13'0000000000000
3804     connect \Y $16
3805   end
3806   process $group_7
3807     assign \exp_gt_n126 1'0
3808     assign \exp_gt_n126 $16
3809     sync init
3810   end
3811   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
3812   wire width 1 \exp_lt_n126
3813   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
3814   wire width 1 $18
3815   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
3816   cell $lt $19
3817     parameter \A_SIGNED 1'1
3818     parameter \A_WIDTH 4'1101
3819     parameter \B_SIGNED 1'1
3820     parameter \B_WIDTH 4'1101
3821     parameter \Y_WIDTH 1'1
3822     connect \A \exp_sub_n126
3823     connect \B 13'0000000000000
3824     connect \Y $18
3825   end
3826   process $group_8
3827     assign \exp_lt_n126 1'0
3828     assign \exp_lt_n126 $18
3829     sync init
3830   end
3831   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
3832   wire width 1 \exp_zero
3833   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
3834   wire width 1 $20
3835   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
3836   cell $eq $21
3837     parameter \A_SIGNED 1'1
3838     parameter \A_WIDTH 4'1101
3839     parameter \B_SIGNED 1'1
3840     parameter \B_WIDTH 4'1101
3841     parameter \Y_WIDTH 1'1
3842     connect \A \b_e
3843     connect \B 13'0000000000000
3844     connect \Y $20
3845   end
3846   process $group_9
3847     assign \exp_zero 1'0
3848     assign \exp_zero $20
3849     sync init
3850   end
3851   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
3852   wire width 1 $22
3853   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
3854   cell $gt $23
3855     parameter \A_SIGNED 1'1
3856     parameter \A_WIDTH 4'1101
3857     parameter \B_SIGNED 1'1
3858     parameter \B_WIDTH 4'1101
3859     parameter \Y_WIDTH 1'1
3860     connect \A \b_e
3861     connect \B 13'0001111111111
3862     connect \Y $22
3863   end
3864   process $group_10
3865     assign \exp_gt127 1'0
3866     assign \exp_gt127 $22
3867     sync init
3868   end
3869   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
3870   wire width 1 $24
3871   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
3872   cell $eq $25
3873     parameter \A_SIGNED 1'1
3874     parameter \A_WIDTH 4'1101
3875     parameter \B_SIGNED 1'1
3876     parameter \B_WIDTH 4'1101
3877     parameter \Y_WIDTH 1'1
3878     connect \A \b_e
3879     connect \B 13'1110000000001
3880     connect \Y $24
3881   end
3882   process $group_11
3883     assign \exp_n127 1'0
3884     assign \exp_n127 $24
3885     sync init
3886   end
3887   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
3888   wire width 1 $26
3889   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
3890   cell $eq $27
3891     parameter \A_SIGNED 1'1
3892     parameter \A_WIDTH 4'1101
3893     parameter \B_SIGNED 1'1
3894     parameter \B_WIDTH 4'1101
3895     parameter \Y_WIDTH 1'1
3896     connect \A \b_e
3897     connect \B 13'1110000000010
3898     connect \Y $26
3899   end
3900   process $group_12
3901     assign \exp_n126 1'0
3902     assign \exp_n126 $26
3903     sync init
3904   end
3905   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
3906   wire width 1 $28
3907   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
3908   cell $eq $29
3909     parameter \A_SIGNED 1'0
3910     parameter \A_WIDTH 6'110101
3911     parameter \B_SIGNED 1'0
3912     parameter \B_WIDTH 6'110101
3913     parameter \Y_WIDTH 1'1
3914     connect \A \i_b_m
3915     connect \B 53'00000000000000000000000000000000000000000000000000000
3916     connect \Y $28
3917   end
3918   process $group_13
3919     assign \m_zero 1'0
3920     assign \m_zero $28
3921     sync init
3922   end
3923   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
3924   wire width 1 $30
3925   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
3926   cell $eq $31
3927     parameter \A_SIGNED 1'0
3928     parameter \A_WIDTH 1'1
3929     parameter \B_SIGNED 1'0
3930     parameter \B_WIDTH 1'1
3931     parameter \Y_WIDTH 1'1
3932     connect \A \i_b_m [52]
3933     connect \B 1'0
3934     connect \Y $30
3935   end
3936   process $group_14
3937     assign \m_msbzero 1'0
3938     assign \m_msbzero $30
3939     sync init
3940   end
3941 end
3942 attribute \generator "nMigen"
3943 attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_a.pe"
3944 module \pe
3945   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
3946   wire width 53 input 0 \i
3947   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
3948   wire width 6 output 1 \o
3949   process $group_0
3950     assign \o 6'000000
3951     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3952     switch { \i [52] }
3953       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3954       case 1'1
3955         assign \o 6'110100
3956     end
3957     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3958     switch { \i [51] }
3959       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3960       case 1'1
3961         assign \o 6'110011
3962     end
3963     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3964     switch { \i [50] }
3965       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3966       case 1'1
3967         assign \o 6'110010
3968     end
3969     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3970     switch { \i [49] }
3971       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3972       case 1'1
3973         assign \o 6'110001
3974     end
3975     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3976     switch { \i [48] }
3977       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3978       case 1'1
3979         assign \o 6'110000
3980     end
3981     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3982     switch { \i [47] }
3983       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3984       case 1'1
3985         assign \o 6'101111
3986     end
3987     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3988     switch { \i [46] }
3989       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3990       case 1'1
3991         assign \o 6'101110
3992     end
3993     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3994     switch { \i [45] }
3995       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
3996       case 1'1
3997         assign \o 6'101101
3998     end
3999     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4000     switch { \i [44] }
4001       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4002       case 1'1
4003         assign \o 6'101100
4004     end
4005     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4006     switch { \i [43] }
4007       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4008       case 1'1
4009         assign \o 6'101011
4010     end
4011     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4012     switch { \i [42] }
4013       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4014       case 1'1
4015         assign \o 6'101010
4016     end
4017     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4018     switch { \i [41] }
4019       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4020       case 1'1
4021         assign \o 6'101001
4022     end
4023     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4024     switch { \i [40] }
4025       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4026       case 1'1
4027         assign \o 6'101000
4028     end
4029     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4030     switch { \i [39] }
4031       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4032       case 1'1
4033         assign \o 6'100111
4034     end
4035     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4036     switch { \i [38] }
4037       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4038       case 1'1
4039         assign \o 6'100110
4040     end
4041     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4042     switch { \i [37] }
4043       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4044       case 1'1
4045         assign \o 6'100101
4046     end
4047     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4048     switch { \i [36] }
4049       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4050       case 1'1
4051         assign \o 6'100100
4052     end
4053     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4054     switch { \i [35] }
4055       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4056       case 1'1
4057         assign \o 6'100011
4058     end
4059     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4060     switch { \i [34] }
4061       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4062       case 1'1
4063         assign \o 6'100010
4064     end
4065     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4066     switch { \i [33] }
4067       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4068       case 1'1
4069         assign \o 6'100001
4070     end
4071     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4072     switch { \i [32] }
4073       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4074       case 1'1
4075         assign \o 6'100000
4076     end
4077     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4078     switch { \i [31] }
4079       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4080       case 1'1
4081         assign \o 6'011111
4082     end
4083     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4084     switch { \i [30] }
4085       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4086       case 1'1
4087         assign \o 6'011110
4088     end
4089     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4090     switch { \i [29] }
4091       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4092       case 1'1
4093         assign \o 6'011101
4094     end
4095     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4096     switch { \i [28] }
4097       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4098       case 1'1
4099         assign \o 6'011100
4100     end
4101     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4102     switch { \i [27] }
4103       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4104       case 1'1
4105         assign \o 6'011011
4106     end
4107     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4108     switch { \i [26] }
4109       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4110       case 1'1
4111         assign \o 6'011010
4112     end
4113     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4114     switch { \i [25] }
4115       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4116       case 1'1
4117         assign \o 6'011001
4118     end
4119     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4120     switch { \i [24] }
4121       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4122       case 1'1
4123         assign \o 6'011000
4124     end
4125     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4126     switch { \i [23] }
4127       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4128       case 1'1
4129         assign \o 6'010111
4130     end
4131     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4132     switch { \i [22] }
4133       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4134       case 1'1
4135         assign \o 6'010110
4136     end
4137     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4138     switch { \i [21] }
4139       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4140       case 1'1
4141         assign \o 6'010101
4142     end
4143     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4144     switch { \i [20] }
4145       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4146       case 1'1
4147         assign \o 6'010100
4148     end
4149     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4150     switch { \i [19] }
4151       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4152       case 1'1
4153         assign \o 6'010011
4154     end
4155     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4156     switch { \i [18] }
4157       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4158       case 1'1
4159         assign \o 6'010010
4160     end
4161     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4162     switch { \i [17] }
4163       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4164       case 1'1
4165         assign \o 6'010001
4166     end
4167     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4168     switch { \i [16] }
4169       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4170       case 1'1
4171         assign \o 6'010000
4172     end
4173     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4174     switch { \i [15] }
4175       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4176       case 1'1
4177         assign \o 6'001111
4178     end
4179     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4180     switch { \i [14] }
4181       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4182       case 1'1
4183         assign \o 6'001110
4184     end
4185     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4186     switch { \i [13] }
4187       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4188       case 1'1
4189         assign \o 6'001101
4190     end
4191     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4192     switch { \i [12] }
4193       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4194       case 1'1
4195         assign \o 6'001100
4196     end
4197     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4198     switch { \i [11] }
4199       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4200       case 1'1
4201         assign \o 6'001011
4202     end
4203     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4204     switch { \i [10] }
4205       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4206       case 1'1
4207         assign \o 6'001010
4208     end
4209     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4210     switch { \i [9] }
4211       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4212       case 1'1
4213         assign \o 6'001001
4214     end
4215     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4216     switch { \i [8] }
4217       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4218       case 1'1
4219         assign \o 6'001000
4220     end
4221     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4222     switch { \i [7] }
4223       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4224       case 1'1
4225         assign \o 6'000111
4226     end
4227     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4228     switch { \i [6] }
4229       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4230       case 1'1
4231         assign \o 6'000110
4232     end
4233     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4234     switch { \i [5] }
4235       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4236       case 1'1
4237         assign \o 6'000101
4238     end
4239     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4240     switch { \i [4] }
4241       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4242       case 1'1
4243         assign \o 6'000100
4244     end
4245     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4246     switch { \i [3] }
4247       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4248       case 1'1
4249         assign \o 6'000011
4250     end
4251     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4252     switch { \i [2] }
4253       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4254       case 1'1
4255         assign \o 6'000010
4256     end
4257     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4258     switch { \i [1] }
4259       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4260       case 1'1
4261         assign \o 6'000001
4262     end
4263     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4264     switch { \i [0] }
4265       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4266       case 1'1
4267         assign \o 6'000000
4268     end
4269     sync init
4270   end
4271   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77"
4272   wire width 1 \n
4273   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
4274   wire width 1 $1
4275   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
4276   cell $eq $2
4277     parameter \A_SIGNED 1'0
4278     parameter \A_WIDTH 6'110101
4279     parameter \B_SIGNED 1'0
4280     parameter \B_WIDTH 1'1
4281     parameter \Y_WIDTH 1'1
4282     connect \A \i
4283     connect \B 1'0
4284     connect \Y $1
4285   end
4286   process $group_1
4287     assign \n 1'0
4288     assign \n $1
4289     sync init
4290   end
4291 end
4292 attribute \generator "nMigen"
4293 attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_a"
4294 module \norm_pe_a
4295   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31"
4296   wire width 53 input 0 \m_in
4297   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32"
4298   wire width 13 input 1 \e_in
4299   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34"
4300   wire width 13 output 2 \e_out
4301   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33"
4302   wire width 53 output 3 \m_out
4303   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
4304   wire width 53 \pe_i
4305   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4306   wire width 6 \pe_o
4307   cell \pe \pe
4308     connect \i \pe_i
4309     connect \o \pe_o
4310   end
4311   process $group_0
4312     assign \pe_i 53'00000000000000000000000000000000000000000000000000000
4313     assign \pe_i { \m_in [0] \m_in [1] \m_in [2] \m_in [3] \m_in [4] \m_in [5] \m_in [6] \m_in [7] \m_in [8] \m_in [9] \m_in [10] \m_in [11] \m_in [12] \m_in [13] \m_in [14] \m_in [15] \m_in [16] \m_in [17] \m_in [18] \m_in [19] \m_in [20] \m_in [21] \m_in [22] \m_in [23] \m_in [24] \m_in [25] \m_in [26] \m_in [27] \m_in [28] \m_in [29] \m_in [30] \m_in [31] \m_in [32] \m_in [33] \m_in [34] \m_in [35] \m_in [36] \m_in [37] \m_in [38] \m_in [39] \m_in [40] \m_in [41] \m_in [42] \m_in [43] \m_in [44] \m_in [45] \m_in [46] \m_in [47] \m_in [48] \m_in [49] \m_in [50] \m_in [51] \m_in [52] }
4314     sync init
4315   end
4316   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:48"
4317   wire width 13 \clz
4318   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4319   wire width 13 $1
4320   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4321   cell $pos $2
4322     parameter \A_SIGNED 1'0
4323     parameter \A_WIDTH 3'110
4324     parameter \Y_WIDTH 4'1101
4325     connect \A \pe_o
4326     connect \Y $1
4327   end
4328   process $group_1
4329     assign \clz 13'0000000000000
4330     assign \clz $1
4331     sync init
4332   end
4333   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:50"
4334   wire width 13 \uclz
4335   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4336   wire width 13 $3
4337   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4338   cell $pos $4
4339     parameter \A_SIGNED 1'0
4340     parameter \A_WIDTH 3'110
4341     parameter \Y_WIDTH 4'1101
4342     connect \A \pe_o
4343     connect \Y $3
4344   end
4345   process $group_2
4346     assign \uclz 13'0000000000000
4347     assign \uclz $3
4348     sync init
4349   end
4350   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:51"
4351   wire width 53 \temp
4352   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
4353   wire width 8244 $5
4354   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
4355   wire width 8244 $6
4356   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
4357   cell $sshl $7
4358     parameter \A_SIGNED 1'0
4359     parameter \A_WIDTH 6'110101
4360     parameter \B_SIGNED 1'0
4361     parameter \B_WIDTH 4'1101
4362     parameter \Y_WIDTH 14'10000000110100
4363     connect \A \m_in
4364     connect \B \uclz
4365     connect \Y $6
4366   end
4367   connect $5 $6
4368   process $group_3
4369     assign \temp 53'00000000000000000000000000000000000000000000000000000
4370     assign \temp $5 [52:0]
4371     sync init
4372   end
4373   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
4374   wire width 14 $8
4375   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
4376   wire width 14 $9
4377   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
4378   cell $sub $10
4379     parameter \A_SIGNED 1'1
4380     parameter \A_WIDTH 4'1101
4381     parameter \B_SIGNED 1'1
4382     parameter \B_WIDTH 4'1101
4383     parameter \Y_WIDTH 4'1110
4384     connect \A \e_in
4385     connect \B \clz
4386     connect \Y $9
4387   end
4388   connect $8 $9
4389   process $group_4
4390     assign \e_out 13'0000000000000
4391     assign \e_out $8 [12:0]
4392     sync init
4393   end
4394   process $group_5
4395     assign \m_out 53'00000000000000000000000000000000000000000000000000000
4396     assign \m_out \temp
4397     sync init
4398   end
4399 end
4400 attribute \generator "nMigen"
4401 attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_b.pe"
4402 module \pe__4
4403   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
4404   wire width 53 input 0 \i
4405   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4406   wire width 6 output 1 \o
4407   process $group_0
4408     assign \o 6'000000
4409     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4410     switch { \i [52] }
4411       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4412       case 1'1
4413         assign \o 6'110100
4414     end
4415     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4416     switch { \i [51] }
4417       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4418       case 1'1
4419         assign \o 6'110011
4420     end
4421     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4422     switch { \i [50] }
4423       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4424       case 1'1
4425         assign \o 6'110010
4426     end
4427     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4428     switch { \i [49] }
4429       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4430       case 1'1
4431         assign \o 6'110001
4432     end
4433     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4434     switch { \i [48] }
4435       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4436       case 1'1
4437         assign \o 6'110000
4438     end
4439     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4440     switch { \i [47] }
4441       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4442       case 1'1
4443         assign \o 6'101111
4444     end
4445     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4446     switch { \i [46] }
4447       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4448       case 1'1
4449         assign \o 6'101110
4450     end
4451     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4452     switch { \i [45] }
4453       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4454       case 1'1
4455         assign \o 6'101101
4456     end
4457     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4458     switch { \i [44] }
4459       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4460       case 1'1
4461         assign \o 6'101100
4462     end
4463     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4464     switch { \i [43] }
4465       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4466       case 1'1
4467         assign \o 6'101011
4468     end
4469     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4470     switch { \i [42] }
4471       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4472       case 1'1
4473         assign \o 6'101010
4474     end
4475     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4476     switch { \i [41] }
4477       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4478       case 1'1
4479         assign \o 6'101001
4480     end
4481     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4482     switch { \i [40] }
4483       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4484       case 1'1
4485         assign \o 6'101000
4486     end
4487     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4488     switch { \i [39] }
4489       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4490       case 1'1
4491         assign \o 6'100111
4492     end
4493     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4494     switch { \i [38] }
4495       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4496       case 1'1
4497         assign \o 6'100110
4498     end
4499     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4500     switch { \i [37] }
4501       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4502       case 1'1
4503         assign \o 6'100101
4504     end
4505     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4506     switch { \i [36] }
4507       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4508       case 1'1
4509         assign \o 6'100100
4510     end
4511     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4512     switch { \i [35] }
4513       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4514       case 1'1
4515         assign \o 6'100011
4516     end
4517     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4518     switch { \i [34] }
4519       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4520       case 1'1
4521         assign \o 6'100010
4522     end
4523     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4524     switch { \i [33] }
4525       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4526       case 1'1
4527         assign \o 6'100001
4528     end
4529     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4530     switch { \i [32] }
4531       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4532       case 1'1
4533         assign \o 6'100000
4534     end
4535     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4536     switch { \i [31] }
4537       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4538       case 1'1
4539         assign \o 6'011111
4540     end
4541     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4542     switch { \i [30] }
4543       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4544       case 1'1
4545         assign \o 6'011110
4546     end
4547     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4548     switch { \i [29] }
4549       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4550       case 1'1
4551         assign \o 6'011101
4552     end
4553     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4554     switch { \i [28] }
4555       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4556       case 1'1
4557         assign \o 6'011100
4558     end
4559     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4560     switch { \i [27] }
4561       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4562       case 1'1
4563         assign \o 6'011011
4564     end
4565     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4566     switch { \i [26] }
4567       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4568       case 1'1
4569         assign \o 6'011010
4570     end
4571     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4572     switch { \i [25] }
4573       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4574       case 1'1
4575         assign \o 6'011001
4576     end
4577     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4578     switch { \i [24] }
4579       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4580       case 1'1
4581         assign \o 6'011000
4582     end
4583     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4584     switch { \i [23] }
4585       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4586       case 1'1
4587         assign \o 6'010111
4588     end
4589     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4590     switch { \i [22] }
4591       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4592       case 1'1
4593         assign \o 6'010110
4594     end
4595     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4596     switch { \i [21] }
4597       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4598       case 1'1
4599         assign \o 6'010101
4600     end
4601     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4602     switch { \i [20] }
4603       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4604       case 1'1
4605         assign \o 6'010100
4606     end
4607     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4608     switch { \i [19] }
4609       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4610       case 1'1
4611         assign \o 6'010011
4612     end
4613     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4614     switch { \i [18] }
4615       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4616       case 1'1
4617         assign \o 6'010010
4618     end
4619     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4620     switch { \i [17] }
4621       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4622       case 1'1
4623         assign \o 6'010001
4624     end
4625     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4626     switch { \i [16] }
4627       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4628       case 1'1
4629         assign \o 6'010000
4630     end
4631     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4632     switch { \i [15] }
4633       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4634       case 1'1
4635         assign \o 6'001111
4636     end
4637     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4638     switch { \i [14] }
4639       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4640       case 1'1
4641         assign \o 6'001110
4642     end
4643     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4644     switch { \i [13] }
4645       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4646       case 1'1
4647         assign \o 6'001101
4648     end
4649     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4650     switch { \i [12] }
4651       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4652       case 1'1
4653         assign \o 6'001100
4654     end
4655     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4656     switch { \i [11] }
4657       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4658       case 1'1
4659         assign \o 6'001011
4660     end
4661     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4662     switch { \i [10] }
4663       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4664       case 1'1
4665         assign \o 6'001010
4666     end
4667     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4668     switch { \i [9] }
4669       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4670       case 1'1
4671         assign \o 6'001001
4672     end
4673     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4674     switch { \i [8] }
4675       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4676       case 1'1
4677         assign \o 6'001000
4678     end
4679     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4680     switch { \i [7] }
4681       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4682       case 1'1
4683         assign \o 6'000111
4684     end
4685     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4686     switch { \i [6] }
4687       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4688       case 1'1
4689         assign \o 6'000110
4690     end
4691     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4692     switch { \i [5] }
4693       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4694       case 1'1
4695         assign \o 6'000101
4696     end
4697     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4698     switch { \i [4] }
4699       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4700       case 1'1
4701         assign \o 6'000100
4702     end
4703     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4704     switch { \i [3] }
4705       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4706       case 1'1
4707         assign \o 6'000011
4708     end
4709     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4710     switch { \i [2] }
4711       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4712       case 1'1
4713         assign \o 6'000010
4714     end
4715     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4716     switch { \i [1] }
4717       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4718       case 1'1
4719         assign \o 6'000001
4720     end
4721     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4722     switch { \i [0] }
4723       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
4724       case 1'1
4725         assign \o 6'000000
4726     end
4727     sync init
4728   end
4729   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77"
4730   wire width 1 \n
4731   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
4732   wire width 1 $1
4733   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
4734   cell $eq $2
4735     parameter \A_SIGNED 1'0
4736     parameter \A_WIDTH 6'110101
4737     parameter \B_SIGNED 1'0
4738     parameter \B_WIDTH 1'1
4739     parameter \Y_WIDTH 1'1
4740     connect \A \i
4741     connect \B 1'0
4742     connect \Y $1
4743   end
4744   process $group_1
4745     assign \n 1'0
4746     assign \n $1
4747     sync init
4748   end
4749 end
4750 attribute \generator "nMigen"
4751 attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_b"
4752 module \norm_pe_b
4753   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31"
4754   wire width 53 input 0 \m_in
4755   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32"
4756   wire width 13 input 1 \e_in
4757   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34"
4758   wire width 13 output 2 \e_out
4759   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33"
4760   wire width 53 output 3 \m_out
4761   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
4762   wire width 53 \pe_i
4763   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4764   wire width 6 \pe_o
4765   cell \pe__4 \pe
4766     connect \i \pe_i
4767     connect \o \pe_o
4768   end
4769   process $group_0
4770     assign \pe_i 53'00000000000000000000000000000000000000000000000000000
4771     assign \pe_i { \m_in [0] \m_in [1] \m_in [2] \m_in [3] \m_in [4] \m_in [5] \m_in [6] \m_in [7] \m_in [8] \m_in [9] \m_in [10] \m_in [11] \m_in [12] \m_in [13] \m_in [14] \m_in [15] \m_in [16] \m_in [17] \m_in [18] \m_in [19] \m_in [20] \m_in [21] \m_in [22] \m_in [23] \m_in [24] \m_in [25] \m_in [26] \m_in [27] \m_in [28] \m_in [29] \m_in [30] \m_in [31] \m_in [32] \m_in [33] \m_in [34] \m_in [35] \m_in [36] \m_in [37] \m_in [38] \m_in [39] \m_in [40] \m_in [41] \m_in [42] \m_in [43] \m_in [44] \m_in [45] \m_in [46] \m_in [47] \m_in [48] \m_in [49] \m_in [50] \m_in [51] \m_in [52] }
4772     sync init
4773   end
4774   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:48"
4775   wire width 13 \clz
4776   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4777   wire width 13 $1
4778   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4779   cell $pos $2
4780     parameter \A_SIGNED 1'0
4781     parameter \A_WIDTH 3'110
4782     parameter \Y_WIDTH 4'1101
4783     connect \A \pe_o
4784     connect \Y $1
4785   end
4786   process $group_1
4787     assign \clz 13'0000000000000
4788     assign \clz $1
4789     sync init
4790   end
4791   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:50"
4792   wire width 13 \uclz
4793   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4794   wire width 13 $3
4795   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
4796   cell $pos $4
4797     parameter \A_SIGNED 1'0
4798     parameter \A_WIDTH 3'110
4799     parameter \Y_WIDTH 4'1101
4800     connect \A \pe_o
4801     connect \Y $3
4802   end
4803   process $group_2
4804     assign \uclz 13'0000000000000
4805     assign \uclz $3
4806     sync init
4807   end
4808   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:51"
4809   wire width 53 \temp
4810   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
4811   wire width 8244 $5
4812   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
4813   wire width 8244 $6
4814   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
4815   cell $sshl $7
4816     parameter \A_SIGNED 1'0
4817     parameter \A_WIDTH 6'110101
4818     parameter \B_SIGNED 1'0
4819     parameter \B_WIDTH 4'1101
4820     parameter \Y_WIDTH 14'10000000110100
4821     connect \A \m_in
4822     connect \B \uclz
4823     connect \Y $6
4824   end
4825   connect $5 $6
4826   process $group_3
4827     assign \temp 53'00000000000000000000000000000000000000000000000000000
4828     assign \temp $5 [52:0]
4829     sync init
4830   end
4831   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
4832   wire width 14 $8
4833   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
4834   wire width 14 $9
4835   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
4836   cell $sub $10
4837     parameter \A_SIGNED 1'1
4838     parameter \A_WIDTH 4'1101
4839     parameter \B_SIGNED 1'1
4840     parameter \B_WIDTH 4'1101
4841     parameter \Y_WIDTH 4'1110
4842     connect \A \e_in
4843     connect \B \clz
4844     connect \Y $9
4845   end
4846   connect $8 $9
4847   process $group_4
4848     assign \e_out 13'0000000000000
4849     assign \e_out $8 [12:0]
4850     sync init
4851   end
4852   process $group_5
4853     assign \m_out 53'00000000000000000000000000000000000000000000000000000
4854     assign \m_out \temp
4855     sync init
4856   end
4857 end
4858 attribute \generator "nMigen"
4859 attribute \nmigen.hierarchy "top.alu.scnorm.align"
4860 module \align
4861   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
4862   wire width 1 input 0 \out_do_z
4863   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
4864   wire width 64 input 1 \oz
4865   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
4866   wire width 1 input 2 \a_s
4867   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
4868   wire width 13 input 3 \a_e
4869   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
4870   wire width 53 input 4 \i_a_m
4871   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
4872   wire width 1 input 5 \b_s
4873   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
4874   wire width 13 input 6 \b_e
4875   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
4876   wire width 53 input 7 \i_b_m
4877   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
4878   wire width 2 input 8 \muxid
4879   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
4880   wire width 0 input 9 \op
4881   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
4882   wire width 1 output 10 \out_do_z__1
4883   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
4884   wire width 64 output 11 \oz__2
4885   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
4886   wire width 1 output 12 \a_s__3
4887   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
4888   wire width 13 output 13 \a_e__4
4889   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
4890   wire width 53 output 14 \o_a_m
4891   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
4892   wire width 1 output 15 \b_s__5
4893   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
4894   wire width 13 output 16 \b_e__6
4895   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
4896   wire width 53 output 17 \o_b_m
4897   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
4898   wire width 2 output 18 \muxid__7
4899   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
4900   wire width 0 output 19 \op__8
4901   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
4902   wire width 1 \norm1_insel_a_m_msbzero
4903   cell \norm1_insel_a \norm1_insel_a
4904     connect \a_e \a_e
4905     connect \i_a_m \i_a_m
4906     connect \m_msbzero \norm1_insel_a_m_msbzero
4907   end
4908   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
4909   wire width 1 \norm1_insel_b_m_msbzero
4910   cell \norm1_insel_b \norm1_insel_b
4911     connect \b_e \b_e
4912     connect \i_b_m \i_b_m
4913     connect \m_msbzero \norm1_insel_b_m_msbzero
4914   end
4915   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31"
4916   wire width 53 \norm_pe_a_m_in
4917   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32"
4918   wire width 13 \norm_pe_a_e_in
4919   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34"
4920   wire width 13 \norm_pe_a_e_out
4921   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33"
4922   wire width 53 \norm_pe_a_m_out
4923   cell \norm_pe_a \norm_pe_a
4924     connect \m_in \norm_pe_a_m_in
4925     connect \e_in \norm_pe_a_e_in
4926     connect \e_out \norm_pe_a_e_out
4927     connect \m_out \norm_pe_a_m_out
4928   end
4929   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31"
4930   wire width 53 \norm_pe_b_m_in
4931   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32"
4932   wire width 13 \norm_pe_b_e_in
4933   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34"
4934   wire width 13 \norm_pe_b_e_out
4935   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33"
4936   wire width 53 \norm_pe_b_m_out
4937   cell \norm_pe_b \norm_pe_b
4938     connect \m_in \norm_pe_b_m_in
4939     connect \e_in \norm_pe_b_e_in
4940     connect \e_out \norm_pe_b_e_out
4941     connect \m_out \norm_pe_b_m_out
4942   end
4943   process $group_0
4944     assign \norm_pe_a_m_in 53'00000000000000000000000000000000000000000000000000000
4945     assign \norm_pe_a_m_in \i_a_m
4946     sync init
4947   end
4948   process $group_1
4949     assign \norm_pe_a_e_in 13'0000000000000
4950     assign \norm_pe_a_e_in \a_e
4951     sync init
4952   end
4953   process $group_2
4954     assign \norm_pe_b_m_in 53'00000000000000000000000000000000000000000000000000000
4955     assign \norm_pe_b_m_in \i_b_m
4956     sync init
4957   end
4958   process $group_3
4959     assign \norm_pe_b_e_in 13'0000000000000
4960     assign \norm_pe_b_e_in \b_e
4961     sync init
4962   end
4963   process $group_4
4964     assign \a_s__3 1'0
4965     assign \a_s__3 \a_s
4966     sync init
4967   end
4968   process $group_5
4969     assign \b_s__5 1'0
4970     assign \b_s__5 \b_s
4971     sync init
4972   end
4973   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:60"
4974   wire width 1 \decrease_a
4975   process $group_6
4976     assign \decrease_a 1'0
4977     assign \decrease_a \norm1_insel_a_m_msbzero
4978     sync init
4979   end
4980   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:61"
4981   wire width 1 \decrease_b
4982   process $group_7
4983     assign \decrease_b 1'0
4984     assign \decrease_b \norm1_insel_b_m_msbzero
4985     sync init
4986   end
4987   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:67"
4988   wire width 13 $9
4989   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:67"
4990   cell $mux $10
4991     parameter \WIDTH 4'1101
4992     connect \A \a_e
4993     connect \B \norm_pe_a_e_out
4994     connect \S \decrease_a
4995     connect \Y $9
4996   end
4997   process $group_8
4998     assign \a_e__4 13'0000000000000
4999     assign \a_e__4 $9
5000     sync init
5001   end
5002   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:68"
5003   wire width 53 $11
5004   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:68"
5005   cell $mux $12
5006     parameter \WIDTH 6'110101
5007     connect \A \i_a_m
5008     connect \B \norm_pe_a_m_out
5009     connect \S \decrease_a
5010     connect \Y $11
5011   end
5012   process $group_9
5013     assign \o_a_m 53'00000000000000000000000000000000000000000000000000000
5014     assign \o_a_m $11
5015     sync init
5016   end
5017   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:71"
5018   wire width 13 $13
5019   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:71"
5020   cell $mux $14
5021     parameter \WIDTH 4'1101
5022     connect \A \b_e
5023     connect \B \norm_pe_b_e_out
5024     connect \S \decrease_b
5025     connect \Y $13
5026   end
5027   process $group_10
5028     assign \b_e__6 13'0000000000000
5029     assign \b_e__6 $13
5030     sync init
5031   end
5032   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:72"
5033   wire width 53 $15
5034   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:72"
5035   cell $mux $16
5036     parameter \WIDTH 6'110101
5037     connect \A \i_b_m
5038     connect \B \norm_pe_b_m_out
5039     connect \S \decrease_b
5040     connect \Y $15
5041   end
5042   process $group_11
5043     assign \o_b_m 53'00000000000000000000000000000000000000000000000000000
5044     assign \o_b_m $15
5045     sync init
5046   end
5047   process $group_12
5048     assign \muxid__7 2'00
5049     assign \muxid__7 \muxid
5050     sync init
5051   end
5052   process $group_13
5053     assign \op__8 0'0
5054     assign \op__8 \op
5055     sync init
5056   end
5057   process $group_14
5058     assign \out_do_z__1 1'0
5059     assign \out_do_z__1 \out_do_z
5060     sync init
5061   end
5062   process $group_15
5063     assign \oz__2 64'0000000000000000000000000000000000000000000000000000000000000000
5064     assign \oz__2 \oz
5065     sync init
5066   end
5067   connect \op__8 0'0
5068 end
5069 attribute \generator "nMigen"
5070 attribute \nmigen.hierarchy "top.alu.scnorm"
5071 module \scnorm
5072   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
5073   wire width 1 output 0 \n_valid_o
5074   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
5075   wire width 1 input 1 \n_ready_i
5076   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5077   wire width 1 output 2 \z_s
5078   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5079   wire width 1 \z_s$next
5080   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5081   wire width 13 output 3 \z_e
5082   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5083   wire width 13 \z_e$next
5084   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5085   wire width 53 output 4 \z_m
5086   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5087   wire width 53 \z_m$next
5088   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5089   wire width 1 output 5 \out_do_z
5090   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5091   wire width 1 \out_do_z$next
5092   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5093   wire width 64 output 6 \oz
5094   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5095   wire width 64 \oz$next
5096   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5097   wire width 1 output 7 \a_s
5098   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5099   wire width 1 \a_s$next
5100   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5101   wire width 13 output 8 \a_e
5102   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5103   wire width 13 \a_e$next
5104   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5105   wire width 53 output 9 \a_m
5106   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5107   wire width 53 \a_m$next
5108   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5109   wire width 1 output 10 \b_s
5110   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5111   wire width 1 \b_s$next
5112   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5113   wire width 13 output 11 \b_e
5114   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5115   wire width 13 \b_e$next
5116   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5117   wire width 53 output 12 \b_m
5118   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5119   wire width 53 \b_m$next
5120   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5121   wire width 2 output 13 \muxid
5122   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5123   wire width 2 \muxid$next
5124   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5125   wire width 0 output 14 \op
5126   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5127   wire width 0 \op$next
5128   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
5129   wire width 1 input 15 \p_valid_i
5130   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
5131   wire width 1 output 16 \p_ready_o
5132   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
5133   wire width 64 input 17 \a
5134   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
5135   wire width 64 input 18 \b
5136   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
5137   wire width 64 input 19 \c
5138   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5139   wire width 2 input 20 \muxid__1
5140   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5141   wire width 0 input 21 \op__2
5142   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
5143   wire width 1 input 22 \rst
5144   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
5145   wire width 1 input 23 \clk
5146   cell \p__2 \p
5147     connect \p_valid_i \p_valid_i
5148     connect \p_ready_o \p_ready_o
5149   end
5150   cell \n__3 \n
5151     connect \n_valid_o \n_valid_o
5152     connect \n_ready_i \n_ready_i
5153   end
5154   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
5155   wire width 64 \specialcases_a
5156   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
5157   wire width 64 \specialcases_b
5158   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5159   wire width 2 \specialcases_muxid
5160   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5161   wire width 0 \specialcases_op
5162   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5163   wire width 1 \specialcases_out_do_z
5164   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5165   wire width 64 \specialcases_oz
5166   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5167   wire width 1 \specialcases_a_s
5168   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5169   wire width 13 \specialcases_a_e
5170   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5171   wire width 53 \specialcases_a_m
5172   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5173   wire width 1 \specialcases_b_s
5174   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5175   wire width 13 \specialcases_b_e
5176   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5177   wire width 53 \specialcases_b_m
5178   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5179   wire width 2 \specialcases_muxid__3
5180   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5181   wire width 0 \specialcases_op__4
5182   cell \specialcases \specialcases
5183     connect \a \specialcases_a
5184     connect \b \specialcases_b
5185     connect \muxid \specialcases_muxid
5186     connect \op \specialcases_op
5187     connect \out_do_z \specialcases_out_do_z
5188     connect \oz \specialcases_oz
5189     connect \a_s \specialcases_a_s
5190     connect \a_e \specialcases_a_e
5191     connect \a_m \specialcases_a_m
5192     connect \b_s \specialcases_b_s
5193     connect \b_e \specialcases_b_e
5194     connect \b_m \specialcases_b_m
5195     connect \muxid__1 \specialcases_muxid__3
5196     connect \op__2 \specialcases_op__4
5197   end
5198   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5199   wire width 1 \denormalise_z_s
5200   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5201   wire width 13 \denormalise_z_e
5202   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5203   wire width 53 \denormalise_z_m
5204   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5205   wire width 1 \denormalise_out_do_z
5206   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5207   wire width 64 \denormalise_oz
5208   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5209   wire width 1 \denormalise_a_s
5210   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5211   wire width 13 \denormalise_a_e
5212   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5213   wire width 53 \denormalise_a_m
5214   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5215   wire width 1 \denormalise_b_s
5216   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5217   wire width 13 \denormalise_b_e
5218   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5219   wire width 53 \denormalise_b_m
5220   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5221   wire width 2 \denormalise_muxid
5222   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5223   wire width 0 \denormalise_op
5224   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5225   wire width 1 \denormalise_z_s__5
5226   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5227   wire width 13 \denormalise_z_e__6
5228   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5229   wire width 53 \denormalise_z_m__7
5230   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5231   wire width 1 \denormalise_out_do_z__8
5232   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5233   wire width 64 \denormalise_oz__9
5234   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5235   wire width 1 \denormalise_a_s__10
5236   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5237   wire width 13 \denormalise_a_e__11
5238   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5239   wire width 53 \denormalise_a_m__12
5240   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5241   wire width 1 \denormalise_b_s__13
5242   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5243   wire width 13 \denormalise_b_e__14
5244   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5245   wire width 53 \denormalise_b_m__15
5246   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5247   wire width 2 \denormalise_muxid__16
5248   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5249   wire width 0 \denormalise_op__17
5250   cell \denormalise \denormalise
5251     connect \z_s \denormalise_z_s
5252     connect \z_e \denormalise_z_e
5253     connect \z_m \denormalise_z_m
5254     connect \out_do_z \denormalise_out_do_z
5255     connect \oz \denormalise_oz
5256     connect \a_s \denormalise_a_s
5257     connect \a_e \denormalise_a_e
5258     connect \a_m \denormalise_a_m
5259     connect \b_s \denormalise_b_s
5260     connect \b_e \denormalise_b_e
5261     connect \b_m \denormalise_b_m
5262     connect \muxid \denormalise_muxid
5263     connect \op \denormalise_op
5264     connect \z_s__1 \denormalise_z_s__5
5265     connect \z_e__2 \denormalise_z_e__6
5266     connect \z_m__3 \denormalise_z_m__7
5267     connect \out_do_z__4 \denormalise_out_do_z__8
5268     connect \oz__5 \denormalise_oz__9
5269     connect \a_s__6 \denormalise_a_s__10
5270     connect \a_e__7 \denormalise_a_e__11
5271     connect \a_m__8 \denormalise_a_m__12
5272     connect \b_s__9 \denormalise_b_s__13
5273     connect \b_e__10 \denormalise_b_e__14
5274     connect \b_m__11 \denormalise_b_m__15
5275     connect \muxid__12 \denormalise_muxid__16
5276     connect \op__13 \denormalise_op__17
5277   end
5278   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5279   wire width 1 \align_out_do_z
5280   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5281   wire width 64 \align_oz
5282   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5283   wire width 1 \align_a_s
5284   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5285   wire width 13 \align_a_e
5286   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5287   wire width 53 \align_i_a_m
5288   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5289   wire width 1 \align_b_s
5290   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5291   wire width 13 \align_b_e
5292   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5293   wire width 53 \align_i_b_m
5294   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5295   wire width 2 \align_muxid
5296   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5297   wire width 0 \align_op
5298   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5299   wire width 1 \align_out_do_z__18
5300   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5301   wire width 64 \align_oz__19
5302   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5303   wire width 1 \align_a_s__20
5304   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5305   wire width 13 \align_a_e__21
5306   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5307   wire width 53 \align_o_a_m
5308   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5309   wire width 1 \align_b_s__22
5310   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5311   wire width 13 \align_b_e__23
5312   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5313   wire width 53 \align_o_b_m
5314   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5315   wire width 2 \align_muxid__24
5316   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5317   wire width 0 \align_op__25
5318   cell \align \align
5319     connect \out_do_z \align_out_do_z
5320     connect \oz \align_oz
5321     connect \a_s \align_a_s
5322     connect \a_e \align_a_e
5323     connect \i_a_m \align_i_a_m
5324     connect \b_s \align_b_s
5325     connect \b_e \align_b_e
5326     connect \i_b_m \align_i_b_m
5327     connect \muxid \align_muxid
5328     connect \op \align_op
5329     connect \out_do_z__1 \align_out_do_z__18
5330     connect \oz__2 \align_oz__19
5331     connect \a_s__3 \align_a_s__20
5332     connect \a_e__4 \align_a_e__21
5333     connect \o_a_m \align_o_a_m
5334     connect \b_s__5 \align_b_s__22
5335     connect \b_e__6 \align_b_e__23
5336     connect \o_b_m \align_o_b_m
5337     connect \muxid__7 \align_muxid__24
5338     connect \op__8 \align_op__25
5339   end
5340   process $group_0
5341     assign \specialcases_a 64'0000000000000000000000000000000000000000000000000000000000000000
5342     assign \specialcases_a \a
5343     sync init
5344   end
5345   process $group_1
5346     assign \specialcases_b 64'0000000000000000000000000000000000000000000000000000000000000000
5347     assign \specialcases_b \b
5348     sync init
5349   end
5350   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
5351   wire width 64 \c__26
5352   process $group_2
5353     assign \c__26 64'0000000000000000000000000000000000000000000000000000000000000000
5354     assign \c__26 \c
5355     sync init
5356   end
5357   process $group_3
5358     assign \specialcases_muxid 2'00
5359     assign \specialcases_muxid \muxid__1
5360     sync init
5361   end
5362   process $group_4
5363     assign \specialcases_op 0'0
5364     assign \specialcases_op \op__2
5365     sync init
5366   end
5367   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5368   wire width 1 \z_s__27
5369   process $group_5
5370     assign \denormalise_z_s 1'0
5371     assign \denormalise_z_s \z_s__27
5372     sync init
5373   end
5374   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5375   wire width 13 \z_e__28
5376   process $group_6
5377     assign \denormalise_z_e 13'0000000000000
5378     assign \denormalise_z_e \z_e__28
5379     sync init
5380   end
5381   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5382   wire width 53 \z_m__29
5383   process $group_7
5384     assign \denormalise_z_m 53'00000000000000000000000000000000000000000000000000000
5385     assign \denormalise_z_m \z_m__29
5386     sync init
5387   end
5388   process $group_8
5389     assign \denormalise_out_do_z 1'0
5390     assign \denormalise_out_do_z \specialcases_out_do_z
5391     sync init
5392   end
5393   process $group_9
5394     assign \denormalise_oz 64'0000000000000000000000000000000000000000000000000000000000000000
5395     assign \denormalise_oz \specialcases_oz
5396     sync init
5397   end
5398   process $group_10
5399     assign \denormalise_a_s 1'0
5400     assign \denormalise_a_s \specialcases_a_s
5401     sync init
5402   end
5403   process $group_11
5404     assign \denormalise_a_e 13'0000000000000
5405     assign \denormalise_a_e \specialcases_a_e
5406     sync init
5407   end
5408   process $group_12
5409     assign \denormalise_a_m 53'00000000000000000000000000000000000000000000000000000
5410     assign \denormalise_a_m \specialcases_a_m
5411     sync init
5412   end
5413   process $group_13
5414     assign \denormalise_b_s 1'0
5415     assign \denormalise_b_s \specialcases_b_s
5416     sync init
5417   end
5418   process $group_14
5419     assign \denormalise_b_e 13'0000000000000
5420     assign \denormalise_b_e \specialcases_b_e
5421     sync init
5422   end
5423   process $group_15
5424     assign \denormalise_b_m 53'00000000000000000000000000000000000000000000000000000
5425     assign \denormalise_b_m \specialcases_b_m
5426     sync init
5427   end
5428   process $group_16
5429     assign \denormalise_muxid 2'00
5430     assign \denormalise_muxid \specialcases_muxid__3
5431     sync init
5432   end
5433   process $group_17
5434     assign \denormalise_op 0'0
5435     assign \denormalise_op \specialcases_op__4
5436     sync init
5437   end
5438   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5439   wire width 1 \z_s__30
5440   process $group_18
5441     assign \z_s__30 1'0
5442     assign \z_s__30 \denormalise_z_s__5
5443     sync init
5444   end
5445   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5446   wire width 13 \z_e__31
5447   process $group_19
5448     assign \z_e__31 13'0000000000000
5449     assign \z_e__31 \denormalise_z_e__6
5450     sync init
5451   end
5452   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5453   wire width 53 \z_m__32
5454   process $group_20
5455     assign \z_m__32 53'00000000000000000000000000000000000000000000000000000
5456     assign \z_m__32 \denormalise_z_m__7
5457     sync init
5458   end
5459   process $group_21
5460     assign \align_out_do_z 1'0
5461     assign \align_out_do_z \denormalise_out_do_z__8
5462     sync init
5463   end
5464   process $group_22
5465     assign \align_oz 64'0000000000000000000000000000000000000000000000000000000000000000
5466     assign \align_oz \denormalise_oz__9
5467     sync init
5468   end
5469   process $group_23
5470     assign \align_a_s 1'0
5471     assign \align_a_s \denormalise_a_s__10
5472     sync init
5473   end
5474   process $group_24
5475     assign \align_a_e 13'0000000000000
5476     assign \align_a_e \denormalise_a_e__11
5477     sync init
5478   end
5479   process $group_25
5480     assign \align_i_a_m 53'00000000000000000000000000000000000000000000000000000
5481     assign \align_i_a_m \denormalise_a_m__12
5482     sync init
5483   end
5484   process $group_26
5485     assign \align_b_s 1'0
5486     assign \align_b_s \denormalise_b_s__13
5487     sync init
5488   end
5489   process $group_27
5490     assign \align_b_e 13'0000000000000
5491     assign \align_b_e \denormalise_b_e__14
5492     sync init
5493   end
5494   process $group_28
5495     assign \align_i_b_m 53'00000000000000000000000000000000000000000000000000000
5496     assign \align_i_b_m \denormalise_b_m__15
5497     sync init
5498   end
5499   process $group_29
5500     assign \align_muxid 2'00
5501     assign \align_muxid \denormalise_muxid__16
5502     sync init
5503   end
5504   process $group_30
5505     assign \align_op 0'0
5506     assign \align_op \denormalise_op__17
5507     sync init
5508   end
5509   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:621"
5510   wire width 1 \p_valid_i__33
5511   process $group_31
5512     assign \p_valid_i__33 1'0
5513     assign \p_valid_i__33 \p_valid_i
5514     sync init
5515   end
5516   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:619"
5517   wire width 1 \n_i_rdy_data
5518   process $group_32
5519     assign \n_i_rdy_data 1'0
5520     assign \n_i_rdy_data \n_ready_i
5521     sync init
5522   end
5523   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:620"
5524   wire width 1 \p_valid_i_p_ready_o
5525   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624"
5526   wire width 1 $34
5527   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624"
5528   cell $and $35
5529     parameter \A_SIGNED 1'0
5530     parameter \A_WIDTH 1'1
5531     parameter \B_SIGNED 1'0
5532     parameter \B_WIDTH 1'1
5533     parameter \Y_WIDTH 1'1
5534     connect \A \p_valid_i__33
5535     connect \B \p_ready_o
5536     connect \Y $34
5537   end
5538   process $group_33
5539     assign \p_valid_i_p_ready_o 1'0
5540     assign \p_valid_i_p_ready_o $34
5541     sync init
5542   end
5543   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5544   wire width 1 \z_s__36
5545   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5546   wire width 1 \z_s__37
5547   process $group_34
5548     assign \z_s__36 1'0
5549     assign \z_s__36 \z_s__37
5550     sync init
5551   end
5552   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5553   wire width 13 \z_e__38
5554   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5555   wire width 13 \z_e__39
5556   process $group_35
5557     assign \z_e__38 13'0000000000000
5558     assign \z_e__38 \z_e__39
5559     sync init
5560   end
5561   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5562   wire width 53 \z_m__40
5563   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5564   wire width 53 \z_m__41
5565   process $group_36
5566     assign \z_m__40 53'00000000000000000000000000000000000000000000000000000
5567     assign \z_m__40 \z_m__41
5568     sync init
5569   end
5570   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5571   wire width 1 \out_do_z__42
5572   process $group_37
5573     assign \out_do_z__42 1'0
5574     assign \out_do_z__42 \align_out_do_z__18
5575     sync init
5576   end
5577   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5578   wire width 64 \oz__43
5579   process $group_38
5580     assign \oz__43 64'0000000000000000000000000000000000000000000000000000000000000000
5581     assign \oz__43 \align_oz__19
5582     sync init
5583   end
5584   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5585   wire width 1 \a_s__44
5586   process $group_39
5587     assign \a_s__44 1'0
5588     assign \a_s__44 \align_a_s__20
5589     sync init
5590   end
5591   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5592   wire width 13 \a_e__45
5593   process $group_40
5594     assign \a_e__45 13'0000000000000
5595     assign \a_e__45 \align_a_e__21
5596     sync init
5597   end
5598   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5599   wire width 53 \a_m__46
5600   process $group_41
5601     assign \a_m__46 53'00000000000000000000000000000000000000000000000000000
5602     assign \a_m__46 \align_o_a_m
5603     sync init
5604   end
5605   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5606   wire width 1 \b_s__47
5607   process $group_42
5608     assign \b_s__47 1'0
5609     assign \b_s__47 \align_b_s__22
5610     sync init
5611   end
5612   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5613   wire width 13 \b_e__48
5614   process $group_43
5615     assign \b_e__48 13'0000000000000
5616     assign \b_e__48 \align_b_e__23
5617     sync init
5618   end
5619   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5620   wire width 53 \b_m__49
5621   process $group_44
5622     assign \b_m__49 53'00000000000000000000000000000000000000000000000000000
5623     assign \b_m__49 \align_o_b_m
5624     sync init
5625   end
5626   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5627   wire width 2 \muxid__50
5628   process $group_45
5629     assign \muxid__50 2'00
5630     assign \muxid__50 \align_muxid__24
5631     sync init
5632   end
5633   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5634   wire width 0 \op__51
5635   process $group_46
5636     assign \op__51 0'0
5637     assign \op__51 \align_op__25
5638     sync init
5639   end
5640   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615"
5641   wire width 1 \r_busy
5642   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615"
5643   wire width 1 \r_busy$next
5644   process $group_47
5645     assign \r_busy$next \r_busy
5646     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5647     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5648       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5649       case 2'-1
5650         assign \r_busy$next 1'1
5651       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5652       case 2'1-
5653         assign \r_busy$next 1'0
5654     end
5655     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/xfrm.py:528"
5656     switch \rst
5657       case 1'1
5658         assign \r_busy$next 1'0
5659     end
5660     sync init
5661       update \r_busy 1'0
5662     sync posedge \clk
5663       update \r_busy \r_busy$next
5664   end
5665   process $group_48
5666     assign \z_s$next \z_s
5667     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5668     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5669       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5670       case 2'-1
5671         assign \z_s$next \z_s__36
5672       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5673       case 2'1-
5674         assign \z_s$next \z_s__36
5675     end
5676     sync init
5677       update \z_s 1'0
5678     sync posedge \clk
5679       update \z_s \z_s$next
5680   end
5681   process $group_49
5682     assign \z_e$next \z_e
5683     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5684     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5685       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5686       case 2'-1
5687         assign \z_e$next \z_e__38
5688       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5689       case 2'1-
5690         assign \z_e$next \z_e__38
5691     end
5692     sync init
5693       update \z_e 13'0000000000000
5694     sync posedge \clk
5695       update \z_e \z_e$next
5696   end
5697   process $group_50
5698     assign \z_m$next \z_m
5699     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5700     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5701       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5702       case 2'-1
5703         assign \z_m$next \z_m__40
5704       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5705       case 2'1-
5706         assign \z_m$next \z_m__40
5707     end
5708     sync init
5709       update \z_m 53'00000000000000000000000000000000000000000000000000000
5710     sync posedge \clk
5711       update \z_m \z_m$next
5712   end
5713   process $group_51
5714     assign \out_do_z$next \out_do_z
5715     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5716     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5717       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5718       case 2'-1
5719         assign \out_do_z$next \out_do_z__42
5720       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5721       case 2'1-
5722         assign \out_do_z$next \out_do_z__42
5723     end
5724     sync init
5725       update \out_do_z 1'0
5726     sync posedge \clk
5727       update \out_do_z \out_do_z$next
5728   end
5729   process $group_52
5730     assign \oz$next \oz
5731     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5732     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5733       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5734       case 2'-1
5735         assign \oz$next \oz__43
5736       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5737       case 2'1-
5738         assign \oz$next \oz__43
5739     end
5740     sync init
5741       update \oz 64'0000000000000000000000000000000000000000000000000000000000000000
5742     sync posedge \clk
5743       update \oz \oz$next
5744   end
5745   process $group_53
5746     assign \a_s$next \a_s
5747     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5748     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5749       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5750       case 2'-1
5751         assign \a_s$next \a_s__44
5752       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5753       case 2'1-
5754         assign \a_s$next \a_s__44
5755     end
5756     sync init
5757       update \a_s 1'0
5758     sync posedge \clk
5759       update \a_s \a_s$next
5760   end
5761   process $group_54
5762     assign \a_e$next \a_e
5763     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5764     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5765       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5766       case 2'-1
5767         assign \a_e$next \a_e__45
5768       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5769       case 2'1-
5770         assign \a_e$next \a_e__45
5771     end
5772     sync init
5773       update \a_e 13'0000000000000
5774     sync posedge \clk
5775       update \a_e \a_e$next
5776   end
5777   process $group_55
5778     assign \a_m$next \a_m
5779     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5780     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5781       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5782       case 2'-1
5783         assign \a_m$next \a_m__46
5784       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5785       case 2'1-
5786         assign \a_m$next \a_m__46
5787     end
5788     sync init
5789       update \a_m 53'00000000000000000000000000000000000000000000000000000
5790     sync posedge \clk
5791       update \a_m \a_m$next
5792   end
5793   process $group_56
5794     assign \b_s$next \b_s
5795     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5796     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5797       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5798       case 2'-1
5799         assign \b_s$next \b_s__47
5800       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5801       case 2'1-
5802         assign \b_s$next \b_s__47
5803     end
5804     sync init
5805       update \b_s 1'0
5806     sync posedge \clk
5807       update \b_s \b_s$next
5808   end
5809   process $group_57
5810     assign \b_e$next \b_e
5811     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5812     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5813       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5814       case 2'-1
5815         assign \b_e$next \b_e__48
5816       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5817       case 2'1-
5818         assign \b_e$next \b_e__48
5819     end
5820     sync init
5821       update \b_e 13'0000000000000
5822     sync posedge \clk
5823       update \b_e \b_e$next
5824   end
5825   process $group_58
5826     assign \b_m$next \b_m
5827     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5828     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5829       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5830       case 2'-1
5831         assign \b_m$next \b_m__49
5832       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5833       case 2'1-
5834         assign \b_m$next \b_m__49
5835     end
5836     sync init
5837       update \b_m 53'00000000000000000000000000000000000000000000000000000
5838     sync posedge \clk
5839       update \b_m \b_m$next
5840   end
5841   process $group_59
5842     assign \muxid$next \muxid
5843     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5844     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5845       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5846       case 2'-1
5847         assign \muxid$next \muxid__50
5848       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5849       case 2'1-
5850         assign \muxid$next \muxid__50
5851     end
5852     sync init
5853       update \muxid 2'00
5854     sync posedge \clk
5855       update \muxid \muxid$next
5856   end
5857   process $group_60
5858     assign \op$next \op
5859     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5860     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
5861       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
5862       case 2'-1
5863         assign \op$next \op__51
5864       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
5865       case 2'1-
5866         assign \op$next \op__51
5867     end
5868     sync init
5869       update \op 0'0
5870     sync posedge \clk
5871       update \op \op$next
5872   end
5873   process $group_61
5874     assign \n_valid_o 1'0
5875     assign \n_valid_o \r_busy
5876     sync init
5877   end
5878   process $group_62
5879     assign \p_ready_o 1'0
5880     assign \p_ready_o \n_i_rdy_data
5881     sync init
5882   end
5883   connect \op 0'0
5884   connect \specialcases_op 0'0
5885   connect \denormalise_op 0'0
5886   connect \align_op 0'0
5887   connect \z_s__27 1'0
5888   connect \z_e__28 13'0000000000000
5889   connect \z_m__29 53'00000000000000000000000000000000000000000000000000000
5890   connect \z_s__37 1'0
5891   connect \z_e__39 13'0000000000000
5892   connect \z_m__41 53'00000000000000000000000000000000000000000000000000000
5893   connect \op__51 0'0
5894 end
5895 attribute \generator "nMigen"
5896 attribute \nmigen.hierarchy "top.alu.mulstages.p"
5897 module \p__5
5898   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
5899   wire width 1 input 0 \p_valid_i
5900   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
5901   wire width 1 input 1 \p_ready_o
5902   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
5903   wire width 1 \trigger
5904   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
5905   wire width 1 $1
5906   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
5907   cell $and $2
5908     parameter \A_SIGNED 1'0
5909     parameter \A_WIDTH 1'1
5910     parameter \B_SIGNED 1'0
5911     parameter \B_WIDTH 1'1
5912     parameter \Y_WIDTH 1'1
5913     connect \A \p_valid_i
5914     connect \B \p_ready_o
5915     connect \Y $1
5916   end
5917   process $group_0
5918     assign \trigger 1'0
5919     assign \trigger $1
5920     sync init
5921   end
5922 end
5923 attribute \generator "nMigen"
5924 attribute \nmigen.hierarchy "top.alu.mulstages.n"
5925 module \n__6
5926   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
5927   wire width 1 input 0 \n_valid_o
5928   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
5929   wire width 1 input 1 \n_ready_i
5930   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
5931   wire width 1 \trigger
5932   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
5933   wire width 1 $1
5934   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
5935   cell $and $2
5936     parameter \A_SIGNED 1'0
5937     parameter \A_WIDTH 1'1
5938     parameter \B_SIGNED 1'0
5939     parameter \B_WIDTH 1'1
5940     parameter \Y_WIDTH 1'1
5941     connect \A \n_ready_i
5942     connect \B \n_valid_o
5943     connect \Y $1
5944   end
5945   process $group_0
5946     assign \trigger 1'0
5947     assign \trigger $1
5948     sync init
5949   end
5950 end
5951 attribute \generator "nMigen"
5952 attribute \nmigen.hierarchy "top.alu.mulstages.mul0"
5953 module \mul0
5954   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
5955   wire width 1 input 0 \out_do_z
5956   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
5957   wire width 64 input 1 \oz
5958   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5959   wire width 1 input 2 \a_s
5960   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5961   wire width 13 input 3 \a_e
5962   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5963   wire width 53 input 4 \a_m
5964   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5965   wire width 1 input 5 \b_s
5966   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5967   wire width 13 input 6 \b_e
5968   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
5969   wire width 53 input 7 \b_m
5970   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5971   wire width 2 input 8 \muxid
5972   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5973   wire width 0 input 9 \op
5974   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
5975   wire width 1 output 10 \s
5976   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
5977   wire width 13 output 11 \e
5978   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18"
5979   wire width 1 output 12 \out_do_z__1
5980   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19"
5981   wire width 64 output 13 \oz__2
5982   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21"
5983   wire width 108 output 14 \product
5984   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
5985   wire width 2 output 15 \muxid__3
5986   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
5987   wire width 0 output 16 \op__4
5988   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:33"
5989   wire width 54 \am0
5990   process $group_0
5991     assign \am0 54'000000000000000000000000000000000000000000000000000000
5992     assign \am0 { 1'0 \a_m }
5993     sync init
5994   end
5995   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:34"
5996   wire width 54 \bm0
5997   process $group_1
5998     assign \bm0 54'000000000000000000000000000000000000000000000000000000
5999     assign \bm0 { 1'0 \b_m }
6000     sync init
6001   end
6002   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39"
6003   wire width 15 $5
6004   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39"
6005   wire width 14 $6
6006   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39"
6007   cell $add $7
6008     parameter \A_SIGNED 1'1
6009     parameter \A_WIDTH 4'1101
6010     parameter \B_SIGNED 1'1
6011     parameter \B_WIDTH 4'1101
6012     parameter \Y_WIDTH 4'1110
6013     connect \A \a_e
6014     connect \B \b_e
6015     connect \Y $6
6016   end
6017   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39"
6018   wire width 15 $8
6019   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39"
6020   cell $add $9
6021     parameter \A_SIGNED 1'1
6022     parameter \A_WIDTH 4'1110
6023     parameter \B_SIGNED 1'1
6024     parameter \B_WIDTH 4'1110
6025     parameter \Y_WIDTH 4'1111
6026     connect \A $6
6027     connect \B 14'00000000000001
6028     connect \Y $8
6029   end
6030   connect $5 $8
6031   process $group_2
6032     assign \e 13'0000000000000
6033     assign \e $5 [12:0]
6034     sync init
6035   end
6036   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40"
6037   wire width 111 $10
6038   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40"
6039   wire width 108 $11
6040   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40"
6041   cell $mul $12
6042     parameter \A_SIGNED 1'0
6043     parameter \A_WIDTH 6'110110
6044     parameter \B_SIGNED 1'0
6045     parameter \B_WIDTH 6'110110
6046     parameter \Y_WIDTH 7'1101100
6047     connect \A \am0
6048     connect \B \bm0
6049     connect \Y $11
6050   end
6051   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40"
6052   wire width 111 $13
6053   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40"
6054   cell $mul $14
6055     parameter \A_SIGNED 1'0
6056     parameter \A_WIDTH 7'1101100
6057     parameter \B_SIGNED 1'0
6058     parameter \B_WIDTH 2'11
6059     parameter \Y_WIDTH 7'1101111
6060     connect \A $11
6061     connect \B 3'100
6062     connect \Y $13
6063   end
6064   connect $10 $13
6065   process $group_3
6066     assign \product 108'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6067     assign \product $10 [107:0]
6068     sync init
6069   end
6070   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:41"
6071   wire width 1 $15
6072   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:41"
6073   cell $xor $16
6074     parameter \A_SIGNED 1'0
6075     parameter \A_WIDTH 1'1
6076     parameter \B_SIGNED 1'0
6077     parameter \B_WIDTH 1'1
6078     parameter \Y_WIDTH 1'1
6079     connect \A \a_s
6080     connect \B \b_s
6081     connect \Y $15
6082   end
6083   process $group_4
6084     assign \s 1'0
6085     assign \s $15
6086     sync init
6087   end
6088   process $group_5
6089     assign \oz__2 64'0000000000000000000000000000000000000000000000000000000000000000
6090     assign \oz__2 \oz
6091     sync init
6092   end
6093   process $group_6
6094     assign \out_do_z__1 1'0
6095     assign \out_do_z__1 \out_do_z
6096     sync init
6097   end
6098   process $group_7
6099     assign \muxid__3 2'00
6100     assign \muxid__3 \muxid
6101     sync init
6102   end
6103   process $group_8
6104     assign \op__4 0'0
6105     assign \op__4 \op
6106     sync init
6107   end
6108   connect \op__4 0'0
6109 end
6110 attribute \generator "nMigen"
6111 attribute \nmigen.hierarchy "top.alu.mulstages.mul1"
6112 module \mul1
6113   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6114   wire width 1 input 0 \s
6115   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6116   wire width 13 input 1 \e
6117   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18"
6118   wire width 1 input 2 \out_do_z
6119   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19"
6120   wire width 64 input 3 \oz
6121   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21"
6122   wire width 108 input 4 \product
6123   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6124   wire width 2 input 5 \muxid
6125   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6126   wire width 0 input 6 \op
6127   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6128   wire width 1 output 7 \z_s
6129   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6130   wire width 13 output 8 \z_e
6131   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6132   wire width 53 output 9 \z_m
6133   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
6134   wire width 1 output 10 \out_do_z__1
6135   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
6136   wire width 64 output 11 \oz__2
6137   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
6138   wire width 1 output 12 \guard
6139   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
6140   wire width 1 output 13 \round
6141   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
6142   wire width 1 output 14 \sticky
6143   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
6144   wire width 1 output 15 \m0
6145   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6146   wire width 2 output 16 \muxid__3
6147   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6148   wire width 0 output 17 \op__4
6149   process $group_0
6150     assign \z_s 1'0
6151     assign \z_s \s
6152     sync init
6153   end
6154   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:40"
6155   wire width 1 \msb
6156   process $group_1
6157     assign \msb 1'0
6158     assign \msb \product [107]
6159     sync init
6160   end
6161   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:39"
6162   wire width 108 \p
6163   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43"
6164   wire width 109 $5
6165   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21"
6166   wire width 109 $6
6167   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21"
6168   cell $pos $7
6169     parameter \A_SIGNED 1'0
6170     parameter \A_WIDTH 7'1101100
6171     parameter \Y_WIDTH 7'1101101
6172     connect \A \product
6173     connect \Y $6
6174   end
6175   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43"
6176   wire width 109 $8
6177   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43"
6178   cell $sshl $9
6179     parameter \A_SIGNED 1'0
6180     parameter \A_WIDTH 7'1101100
6181     parameter \B_SIGNED 1'0
6182     parameter \B_WIDTH 1'1
6183     parameter \Y_WIDTH 7'1101101
6184     connect \A \product
6185     connect \B 1'1
6186     connect \Y $8
6187   end
6188   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43"
6189   wire width 109 $10
6190   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43"
6191   cell $mux $11
6192     parameter \WIDTH 7'1101101
6193     connect \A $8
6194     connect \B $6
6195     connect \S \msb
6196     connect \Y $10
6197   end
6198   connect $5 $10
6199   process $group_2
6200     assign \p 108'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6201     assign \p $5 [107:0]
6202     sync init
6203   end
6204   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44"
6205   wire width 14 $12
6206   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6207   wire width 14 $13
6208   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6209   cell $pos $14
6210     parameter \A_SIGNED 1'1
6211     parameter \A_WIDTH 4'1101
6212     parameter \Y_WIDTH 4'1110
6213     connect \A \e
6214     connect \Y $13
6215   end
6216   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44"
6217   wire width 14 $15
6218   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44"
6219   cell $sub $16
6220     parameter \A_SIGNED 1'1
6221     parameter \A_WIDTH 4'1101
6222     parameter \B_SIGNED 1'1
6223     parameter \B_WIDTH 4'1101
6224     parameter \Y_WIDTH 4'1110
6225     connect \A \e
6226     connect \B 13'0000000000001
6227     connect \Y $15
6228   end
6229   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44"
6230   wire width 14 $17
6231   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44"
6232   cell $mux $18
6233     parameter \WIDTH 4'1110
6234     connect \A $15
6235     connect \B $13
6236     connect \S \msb
6237     connect \Y $17
6238   end
6239   connect $12 $17
6240   process $group_3
6241     assign \z_e 13'0000000000000
6242     assign \z_e $12 [12:0]
6243     sync init
6244   end
6245   process $group_4
6246     assign \z_m 53'00000000000000000000000000000000000000000000000000000
6247     assign \z_m \p [107:55]
6248     sync init
6249   end
6250   process $group_5
6251     assign \m0 1'0
6252     assign \m0 \p [55]
6253     sync init
6254   end
6255   process $group_6
6256     assign \guard 1'0
6257     assign \guard \p [54]
6258     sync init
6259   end
6260   process $group_7
6261     assign \round 1'0
6262     assign \round \p [53]
6263     sync init
6264   end
6265   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:54"
6266   wire width 1 $19
6267   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:54"
6268   cell $reduce_bool $20
6269     parameter \A_SIGNED 1'0
6270     parameter \A_WIDTH 6'110101
6271     parameter \Y_WIDTH 1'1
6272     connect \A \p [52:0]
6273     connect \Y $19
6274   end
6275   process $group_8
6276     assign \sticky 1'0
6277     assign \sticky $19
6278     sync init
6279   end
6280   process $group_9
6281     assign \out_do_z__1 1'0
6282     assign \out_do_z__1 \out_do_z
6283     sync init
6284   end
6285   process $group_10
6286     assign \oz__2 64'0000000000000000000000000000000000000000000000000000000000000000
6287     assign \oz__2 \oz
6288     sync init
6289   end
6290   process $group_11
6291     assign \muxid__3 2'00
6292     assign \muxid__3 \muxid
6293     sync init
6294   end
6295   process $group_12
6296     assign \op__4 0'0
6297     assign \op__4 \op
6298     sync init
6299   end
6300   connect \op__4 0'0
6301 end
6302 attribute \generator "nMigen"
6303 attribute \nmigen.hierarchy "top.alu.mulstages"
6304 module \mulstages
6305   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
6306   wire width 1 input 0 \p_valid_i
6307   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
6308   wire width 1 output 1 \p_ready_o
6309   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6310   wire width 1 input 2 \z_s
6311   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6312   wire width 13 input 3 \z_e
6313   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6314   wire width 53 input 4 \z_m
6315   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
6316   wire width 1 input 5 \out_do_z
6317   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
6318   wire width 64 input 6 \oz
6319   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6320   wire width 1 input 7 \a_s
6321   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6322   wire width 13 input 8 \a_e
6323   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6324   wire width 53 input 9 \a_m
6325   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6326   wire width 1 input 10 \b_s
6327   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6328   wire width 13 input 11 \b_e
6329   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6330   wire width 53 input 12 \b_m
6331   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6332   wire width 2 input 13 \muxid
6333   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6334   wire width 0 input 14 \op
6335   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
6336   wire width 1 output 15 \n_valid_o
6337   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
6338   wire width 1 input 16 \n_ready_i
6339   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6340   wire width 1 output 17 \z_s__1
6341   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6342   wire width 1 \z_s__1$next
6343   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6344   wire width 13 output 18 \z_e__2
6345   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6346   wire width 13 \z_e__2$next
6347   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6348   wire width 53 output 19 \z_m__3
6349   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6350   wire width 53 \z_m__3$next
6351   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
6352   wire width 1 output 20 \out_do_z__4
6353   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
6354   wire width 1 \out_do_z__4$next
6355   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
6356   wire width 64 output 21 \oz__5
6357   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
6358   wire width 64 \oz__5$next
6359   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
6360   wire width 1 output 22 \guard
6361   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
6362   wire width 1 \guard$next
6363   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
6364   wire width 1 output 23 \round
6365   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
6366   wire width 1 \round$next
6367   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
6368   wire width 1 output 24 \sticky
6369   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
6370   wire width 1 \sticky$next
6371   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
6372   wire width 1 output 25 \m0
6373   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
6374   wire width 1 \m0$next
6375   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
6376   wire width 5 output 26 \fflags
6377   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
6378   wire width 5 \fflags$next
6379   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6380   wire width 2 output 27 \muxid__6
6381   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6382   wire width 2 \muxid__6$next
6383   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6384   wire width 0 output 28 \op__7
6385   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6386   wire width 0 \op__7$next
6387   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
6388   wire width 1 input 29 \rst
6389   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
6390   wire width 1 input 30 \clk
6391   cell \p__5 \p
6392     connect \p_valid_i \p_valid_i
6393     connect \p_ready_o \p_ready_o
6394   end
6395   cell \n__6 \n
6396     connect \n_valid_o \n_valid_o
6397     connect \n_ready_i \n_ready_i
6398   end
6399   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
6400   wire width 1 \mul0_out_do_z
6401   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
6402   wire width 64 \mul0_oz
6403   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6404   wire width 1 \mul0_a_s
6405   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6406   wire width 13 \mul0_a_e
6407   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6408   wire width 53 \mul0_a_m
6409   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6410   wire width 1 \mul0_b_s
6411   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6412   wire width 13 \mul0_b_e
6413   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6414   wire width 53 \mul0_b_m
6415   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6416   wire width 2 \mul0_muxid
6417   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6418   wire width 0 \mul0_op
6419   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6420   wire width 1 \mul0_s
6421   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6422   wire width 13 \mul0_e
6423   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18"
6424   wire width 1 \mul0_out_do_z__8
6425   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19"
6426   wire width 64 \mul0_oz__9
6427   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21"
6428   wire width 108 \mul0_product
6429   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6430   wire width 2 \mul0_muxid__10
6431   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6432   wire width 0 \mul0_op__11
6433   cell \mul0 \mul0
6434     connect \out_do_z \mul0_out_do_z
6435     connect \oz \mul0_oz
6436     connect \a_s \mul0_a_s
6437     connect \a_e \mul0_a_e
6438     connect \a_m \mul0_a_m
6439     connect \b_s \mul0_b_s
6440     connect \b_e \mul0_b_e
6441     connect \b_m \mul0_b_m
6442     connect \muxid \mul0_muxid
6443     connect \op \mul0_op
6444     connect \s \mul0_s
6445     connect \e \mul0_e
6446     connect \out_do_z__1 \mul0_out_do_z__8
6447     connect \oz__2 \mul0_oz__9
6448     connect \product \mul0_product
6449     connect \muxid__3 \mul0_muxid__10
6450     connect \op__4 \mul0_op__11
6451   end
6452   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6453   wire width 1 \mul1_s
6454   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6455   wire width 13 \mul1_e
6456   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18"
6457   wire width 1 \mul1_out_do_z
6458   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19"
6459   wire width 64 \mul1_oz
6460   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21"
6461   wire width 108 \mul1_product
6462   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6463   wire width 2 \mul1_muxid
6464   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6465   wire width 0 \mul1_op
6466   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6467   wire width 1 \mul1_z_s
6468   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6469   wire width 13 \mul1_z_e
6470   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6471   wire width 53 \mul1_z_m
6472   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
6473   wire width 1 \mul1_out_do_z__12
6474   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
6475   wire width 64 \mul1_oz__13
6476   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
6477   wire width 1 \mul1_guard
6478   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
6479   wire width 1 \mul1_round
6480   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
6481   wire width 1 \mul1_sticky
6482   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
6483   wire width 1 \mul1_m0
6484   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6485   wire width 2 \mul1_muxid__14
6486   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6487   wire width 0 \mul1_op__15
6488   cell \mul1 \mul1
6489     connect \s \mul1_s
6490     connect \e \mul1_e
6491     connect \out_do_z \mul1_out_do_z
6492     connect \oz \mul1_oz
6493     connect \product \mul1_product
6494     connect \muxid \mul1_muxid
6495     connect \op \mul1_op
6496     connect \z_s \mul1_z_s
6497     connect \z_e \mul1_z_e
6498     connect \z_m \mul1_z_m
6499     connect \out_do_z__1 \mul1_out_do_z__12
6500     connect \oz__2 \mul1_oz__13
6501     connect \guard \mul1_guard
6502     connect \round \mul1_round
6503     connect \sticky \mul1_sticky
6504     connect \m0 \mul1_m0
6505     connect \muxid__3 \mul1_muxid__14
6506     connect \op__4 \mul1_op__15
6507   end
6508   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6509   wire width 1 \z_s__16
6510   process $group_0
6511     assign \z_s__16 1'0
6512     assign \z_s__16 \z_s
6513     sync init
6514   end
6515   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6516   wire width 13 \z_e__17
6517   process $group_1
6518     assign \z_e__17 13'0000000000000
6519     assign \z_e__17 \z_e
6520     sync init
6521   end
6522   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6523   wire width 53 \z_m__18
6524   process $group_2
6525     assign \z_m__18 53'00000000000000000000000000000000000000000000000000000
6526     assign \z_m__18 \z_m
6527     sync init
6528   end
6529   process $group_3
6530     assign \mul0_out_do_z 1'0
6531     assign \mul0_out_do_z \out_do_z
6532     sync init
6533   end
6534   process $group_4
6535     assign \mul0_oz 64'0000000000000000000000000000000000000000000000000000000000000000
6536     assign \mul0_oz \oz
6537     sync init
6538   end
6539   process $group_5
6540     assign \mul0_a_s 1'0
6541     assign \mul0_a_s \a_s
6542     sync init
6543   end
6544   process $group_6
6545     assign \mul0_a_e 13'0000000000000
6546     assign \mul0_a_e \a_e
6547     sync init
6548   end
6549   process $group_7
6550     assign \mul0_a_m 53'00000000000000000000000000000000000000000000000000000
6551     assign \mul0_a_m \a_m
6552     sync init
6553   end
6554   process $group_8
6555     assign \mul0_b_s 1'0
6556     assign \mul0_b_s \b_s
6557     sync init
6558   end
6559   process $group_9
6560     assign \mul0_b_e 13'0000000000000
6561     assign \mul0_b_e \b_e
6562     sync init
6563   end
6564   process $group_10
6565     assign \mul0_b_m 53'00000000000000000000000000000000000000000000000000000
6566     assign \mul0_b_m \b_m
6567     sync init
6568   end
6569   process $group_11
6570     assign \mul0_muxid 2'00
6571     assign \mul0_muxid \muxid
6572     sync init
6573   end
6574   process $group_12
6575     assign \mul0_op 0'0
6576     assign \mul0_op \op
6577     sync init
6578   end
6579   process $group_13
6580     assign \mul1_s 1'0
6581     assign \mul1_s \mul0_s
6582     sync init
6583   end
6584   process $group_14
6585     assign \mul1_e 13'0000000000000
6586     assign \mul1_e \mul0_e
6587     sync init
6588   end
6589   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6590   wire width 53 \m
6591   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6592   wire width 53 \m__19
6593   process $group_15
6594     assign \m 53'00000000000000000000000000000000000000000000000000000
6595     assign \m \m__19
6596     sync init
6597   end
6598   process $group_16
6599     assign \mul1_out_do_z 1'0
6600     assign \mul1_out_do_z \mul0_out_do_z__8
6601     sync init
6602   end
6603   process $group_17
6604     assign \mul1_oz 64'0000000000000000000000000000000000000000000000000000000000000000
6605     assign \mul1_oz \mul0_oz__9
6606     sync init
6607   end
6608   process $group_18
6609     assign \mul1_product 108'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
6610     assign \mul1_product \mul0_product
6611     sync init
6612   end
6613   process $group_19
6614     assign \mul1_muxid 2'00
6615     assign \mul1_muxid \mul0_muxid__10
6616     sync init
6617   end
6618   process $group_20
6619     assign \mul1_op 0'0
6620     assign \mul1_op \mul0_op__11
6621     sync init
6622   end
6623   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:621"
6624   wire width 1 \p_valid_i__20
6625   process $group_21
6626     assign \p_valid_i__20 1'0
6627     assign \p_valid_i__20 \p_valid_i
6628     sync init
6629   end
6630   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:619"
6631   wire width 1 \n_i_rdy_data
6632   process $group_22
6633     assign \n_i_rdy_data 1'0
6634     assign \n_i_rdy_data \n_ready_i
6635     sync init
6636   end
6637   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:620"
6638   wire width 1 \p_valid_i_p_ready_o
6639   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624"
6640   wire width 1 $21
6641   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624"
6642   cell $and $22
6643     parameter \A_SIGNED 1'0
6644     parameter \A_WIDTH 1'1
6645     parameter \B_SIGNED 1'0
6646     parameter \B_WIDTH 1'1
6647     parameter \Y_WIDTH 1'1
6648     connect \A \p_valid_i__20
6649     connect \B \p_ready_o
6650     connect \Y $21
6651   end
6652   process $group_23
6653     assign \p_valid_i_p_ready_o 1'0
6654     assign \p_valid_i_p_ready_o $21
6655     sync init
6656   end
6657   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
6658   wire width 1 \z_s__23
6659   process $group_24
6660     assign \z_s__23 1'0
6661     assign \z_s__23 \mul1_z_s
6662     sync init
6663   end
6664   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
6665   wire width 13 \z_e__24
6666   process $group_25
6667     assign \z_e__24 13'0000000000000
6668     assign \z_e__24 \mul1_z_e
6669     sync init
6670   end
6671   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
6672   wire width 53 \z_m__25
6673   process $group_26
6674     assign \z_m__25 53'00000000000000000000000000000000000000000000000000000
6675     assign \z_m__25 \mul1_z_m
6676     sync init
6677   end
6678   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
6679   wire width 1 \out_do_z__26
6680   process $group_27
6681     assign \out_do_z__26 1'0
6682     assign \out_do_z__26 \mul1_out_do_z__12
6683     sync init
6684   end
6685   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
6686   wire width 64 \oz__27
6687   process $group_28
6688     assign \oz__27 64'0000000000000000000000000000000000000000000000000000000000000000
6689     assign \oz__27 \mul1_oz__13
6690     sync init
6691   end
6692   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
6693   wire width 1 \guard__28
6694   process $group_29
6695     assign \guard__28 1'0
6696     assign \guard__28 \mul1_guard
6697     sync init
6698   end
6699   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
6700   wire width 1 \round__29
6701   process $group_30
6702     assign \round__29 1'0
6703     assign \round__29 \mul1_round
6704     sync init
6705   end
6706   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
6707   wire width 1 \sticky__30
6708   process $group_31
6709     assign \sticky__30 1'0
6710     assign \sticky__30 \mul1_sticky
6711     sync init
6712   end
6713   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
6714   wire width 1 \m0__31
6715   process $group_32
6716     assign \m0__31 1'0
6717     assign \m0__31 \mul1_m0
6718     sync init
6719   end
6720   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
6721   wire width 5 \fflags__32
6722   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
6723   wire width 5 \fflags__33
6724   process $group_33
6725     assign \fflags__32 5'00000
6726     assign \fflags__32 \fflags__33
6727     sync init
6728   end
6729   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
6730   wire width 2 \muxid__34
6731   process $group_34
6732     assign \muxid__34 2'00
6733     assign \muxid__34 \mul1_muxid__14
6734     sync init
6735   end
6736   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
6737   wire width 0 \op__35
6738   process $group_35
6739     assign \op__35 0'0
6740     assign \op__35 \mul1_op__15
6741     sync init
6742   end
6743   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615"
6744   wire width 1 \r_busy
6745   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615"
6746   wire width 1 \r_busy$next
6747   process $group_36
6748     assign \r_busy$next \r_busy
6749     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6750     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6751       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6752       case 2'-1
6753         assign \r_busy$next 1'1
6754       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6755       case 2'1-
6756         assign \r_busy$next 1'0
6757     end
6758     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/xfrm.py:528"
6759     switch \rst
6760       case 1'1
6761         assign \r_busy$next 1'0
6762     end
6763     sync init
6764       update \r_busy 1'0
6765     sync posedge \clk
6766       update \r_busy \r_busy$next
6767   end
6768   process $group_37
6769     assign \z_s__1$next \z_s__1
6770     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6771     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6772       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6773       case 2'-1
6774         assign \z_s__1$next \z_s__23
6775       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6776       case 2'1-
6777         assign \z_s__1$next \z_s__23
6778     end
6779     sync init
6780       update \z_s__1 1'0
6781     sync posedge \clk
6782       update \z_s__1 \z_s__1$next
6783   end
6784   process $group_38
6785     assign \z_e__2$next \z_e__2
6786     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6787     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6788       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6789       case 2'-1
6790         assign \z_e__2$next \z_e__24
6791       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6792       case 2'1-
6793         assign \z_e__2$next \z_e__24
6794     end
6795     sync init
6796       update \z_e__2 13'0000000000000
6797     sync posedge \clk
6798       update \z_e__2 \z_e__2$next
6799   end
6800   process $group_39
6801     assign \z_m__3$next \z_m__3
6802     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6803     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6804       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6805       case 2'-1
6806         assign \z_m__3$next \z_m__25
6807       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6808       case 2'1-
6809         assign \z_m__3$next \z_m__25
6810     end
6811     sync init
6812       update \z_m__3 53'00000000000000000000000000000000000000000000000000000
6813     sync posedge \clk
6814       update \z_m__3 \z_m__3$next
6815   end
6816   process $group_40
6817     assign \out_do_z__4$next \out_do_z__4
6818     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6819     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6820       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6821       case 2'-1
6822         assign \out_do_z__4$next \out_do_z__26
6823       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6824       case 2'1-
6825         assign \out_do_z__4$next \out_do_z__26
6826     end
6827     sync init
6828       update \out_do_z__4 1'0
6829     sync posedge \clk
6830       update \out_do_z__4 \out_do_z__4$next
6831   end
6832   process $group_41
6833     assign \oz__5$next \oz__5
6834     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6835     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6836       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6837       case 2'-1
6838         assign \oz__5$next \oz__27
6839       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6840       case 2'1-
6841         assign \oz__5$next \oz__27
6842     end
6843     sync init
6844       update \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000
6845     sync posedge \clk
6846       update \oz__5 \oz__5$next
6847   end
6848   process $group_42
6849     assign \guard$next \guard
6850     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6851     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6852       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6853       case 2'-1
6854         assign \guard$next \guard__28
6855       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6856       case 2'1-
6857         assign \guard$next \guard__28
6858     end
6859     sync init
6860       update \guard 1'0
6861     sync posedge \clk
6862       update \guard \guard$next
6863   end
6864   process $group_43
6865     assign \round$next \round
6866     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6867     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6868       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6869       case 2'-1
6870         assign \round$next \round__29
6871       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6872       case 2'1-
6873         assign \round$next \round__29
6874     end
6875     sync init
6876       update \round 1'0
6877     sync posedge \clk
6878       update \round \round$next
6879   end
6880   process $group_44
6881     assign \sticky$next \sticky
6882     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6883     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6884       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6885       case 2'-1
6886         assign \sticky$next \sticky__30
6887       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6888       case 2'1-
6889         assign \sticky$next \sticky__30
6890     end
6891     sync init
6892       update \sticky 1'0
6893     sync posedge \clk
6894       update \sticky \sticky$next
6895   end
6896   process $group_45
6897     assign \m0$next \m0
6898     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6899     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6900       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6901       case 2'-1
6902         assign \m0$next \m0__31
6903       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6904       case 2'1-
6905         assign \m0$next \m0__31
6906     end
6907     sync init
6908       update \m0 1'0
6909     sync posedge \clk
6910       update \m0 \m0$next
6911   end
6912   process $group_46
6913     assign \fflags$next \fflags
6914     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6915     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6916       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6917       case 2'-1
6918         assign \fflags$next \fflags__32
6919       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6920       case 2'1-
6921         assign \fflags$next \fflags__32
6922     end
6923     sync init
6924       update \fflags 5'00000
6925     sync posedge \clk
6926       update \fflags \fflags$next
6927   end
6928   process $group_47
6929     assign \muxid__6$next \muxid__6
6930     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6931     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6932       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6933       case 2'-1
6934         assign \muxid__6$next \muxid__34
6935       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6936       case 2'1-
6937         assign \muxid__6$next \muxid__34
6938     end
6939     sync init
6940       update \muxid__6 2'00
6941     sync posedge \clk
6942       update \muxid__6 \muxid__6$next
6943   end
6944   process $group_48
6945     assign \op__7$next \op__7
6946     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6947     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
6948       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
6949       case 2'-1
6950         assign \op__7$next \op__35
6951       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
6952       case 2'1-
6953         assign \op__7$next \op__35
6954     end
6955     sync init
6956       update \op__7 0'0
6957     sync posedge \clk
6958       update \op__7 \op__7$next
6959   end
6960   process $group_49
6961     assign \n_valid_o 1'0
6962     assign \n_valid_o \r_busy
6963     sync init
6964   end
6965   process $group_50
6966     assign \p_ready_o 1'0
6967     assign \p_ready_o \n_i_rdy_data
6968     sync init
6969   end
6970   connect \op__7 0'0
6971   connect \mul0_op 0'0
6972   connect \mul1_op 0'0
6973   connect \m__19 53'00000000000000000000000000000000000000000000000000000
6974   connect \fflags__33 5'00000
6975   connect \op__35 0'0
6976 end
6977 attribute \generator "nMigen"
6978 attribute \nmigen.hierarchy "top.alu.normpack.p"
6979 module \p__7
6980   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
6981   wire width 1 input 0 \p_valid_i
6982   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
6983   wire width 1 input 1 \p_ready_o
6984   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
6985   wire width 1 \trigger
6986   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
6987   wire width 1 $1
6988   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
6989   cell $and $2
6990     parameter \A_SIGNED 1'0
6991     parameter \A_WIDTH 1'1
6992     parameter \B_SIGNED 1'0
6993     parameter \B_WIDTH 1'1
6994     parameter \Y_WIDTH 1'1
6995     connect \A \p_valid_i
6996     connect \B \p_ready_o
6997     connect \Y $1
6998   end
6999   process $group_0
7000     assign \trigger 1'0
7001     assign \trigger $1
7002     sync init
7003   end
7004 end
7005 attribute \generator "nMigen"
7006 attribute \nmigen.hierarchy "top.alu.normpack.n"
7007 module \n__8
7008   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
7009   wire width 1 input 0 \n_valid_o
7010   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
7011   wire width 1 input 1 \n_ready_i
7012   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
7013   wire width 1 \trigger
7014   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
7015   wire width 1 $1
7016   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
7017   cell $and $2
7018     parameter \A_SIGNED 1'0
7019     parameter \A_WIDTH 1'1
7020     parameter \B_SIGNED 1'0
7021     parameter \B_WIDTH 1'1
7022     parameter \Y_WIDTH 1'1
7023     connect \A \n_ready_i
7024     connect \B \n_valid_o
7025     connect \Y $1
7026   end
7027   process $group_0
7028     assign \trigger 1'0
7029     assign \trigger $1
7030     sync init
7031   end
7032 end
7033 attribute \generator "nMigen"
7034 attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm1_out_overflow"
7035 module \norm1_out_overflow
7036   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
7037   wire width 1 input 0 \norm1of_guard
7038   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
7039   wire width 1 input 1 \norm1of_round
7040   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
7041   wire width 1 input 2 \norm1of_sticky
7042   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
7043   wire width 1 input 3 \norm1of_m0
7044   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:921"
7045   wire width 1 output 4 \norm1of_roundz_out
7046   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913"
7047   wire width 1 $1
7048   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913"
7049   cell $or $2
7050     parameter \A_SIGNED 1'0
7051     parameter \A_WIDTH 1'1
7052     parameter \B_SIGNED 1'0
7053     parameter \B_WIDTH 1'1
7054     parameter \Y_WIDTH 1'1
7055     connect \A \norm1of_round
7056     connect \B \norm1of_sticky
7057     connect \Y $1
7058   end
7059   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913"
7060   wire width 1 $3
7061   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913"
7062   cell $or $4
7063     parameter \A_SIGNED 1'0
7064     parameter \A_WIDTH 1'1
7065     parameter \B_SIGNED 1'0
7066     parameter \B_WIDTH 1'1
7067     parameter \Y_WIDTH 1'1
7068     connect \A $1
7069     connect \B \norm1of_m0
7070     connect \Y $3
7071   end
7072   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913"
7073   wire width 1 $5
7074   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913"
7075   cell $and $6
7076     parameter \A_SIGNED 1'0
7077     parameter \A_WIDTH 1'1
7078     parameter \B_SIGNED 1'0
7079     parameter \B_WIDTH 1'1
7080     parameter \Y_WIDTH 1'1
7081     connect \A \norm1of_guard
7082     connect \B $3
7083     connect \Y $5
7084   end
7085   process $group_0
7086     assign \norm1of_roundz_out 1'0
7087     assign \norm1of_roundz_out $5
7088     sync init
7089   end
7090 end
7091 attribute \generator "nMigen"
7092 attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm1_insel_z"
7093 module \norm1_insel_z
7094   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
7095   wire width 13 input 0 \z_e
7096   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
7097   wire width 53 input 1 \z_m
7098   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
7099   wire width 1 output 2 \m_msbzero
7100   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
7101   wire width 1 output 3 \exp_gt_n126
7102   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
7103   wire width 1 output 4 \exp_lt_n126
7104   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
7105   wire width 13 output 5 \exp_sub_n126
7106   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
7107   wire width 1 \is_nan
7108   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
7109   wire width 1 \exp_128
7110   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
7111   wire width 1 $1
7112   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
7113   wire width 1 \m_zero
7114   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
7115   cell $not $2
7116     parameter \A_SIGNED 1'0
7117     parameter \A_WIDTH 1'1
7118     parameter \Y_WIDTH 1'1
7119     connect \A \m_zero
7120     connect \Y $1
7121   end
7122   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
7123   wire width 1 $3
7124   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
7125   cell $and $4
7126     parameter \A_SIGNED 1'0
7127     parameter \A_WIDTH 1'1
7128     parameter \B_SIGNED 1'0
7129     parameter \B_WIDTH 1'1
7130     parameter \Y_WIDTH 1'1
7131     connect \A \exp_128
7132     connect \B $1
7133     connect \Y $3
7134   end
7135   process $group_0
7136     assign \is_nan 1'0
7137     assign \is_nan $3
7138     sync init
7139   end
7140   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
7141   wire width 1 \is_zero
7142   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
7143   wire width 1 \exp_n127
7144   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
7145   wire width 1 $5
7146   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
7147   cell $and $6
7148     parameter \A_SIGNED 1'0
7149     parameter \A_WIDTH 1'1
7150     parameter \B_SIGNED 1'0
7151     parameter \B_WIDTH 1'1
7152     parameter \Y_WIDTH 1'1
7153     connect \A \exp_n127
7154     connect \B \m_zero
7155     connect \Y $5
7156   end
7157   process $group_1
7158     assign \is_zero 1'0
7159     assign \is_zero $5
7160     sync init
7161   end
7162   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
7163   wire width 1 \is_inf
7164   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
7165   wire width 1 $7
7166   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
7167   cell $and $8
7168     parameter \A_SIGNED 1'0
7169     parameter \A_WIDTH 1'1
7170     parameter \B_SIGNED 1'0
7171     parameter \B_WIDTH 1'1
7172     parameter \Y_WIDTH 1'1
7173     connect \A \exp_128
7174     connect \B \m_zero
7175     connect \Y $7
7176   end
7177   process $group_2
7178     assign \is_inf 1'0
7179     assign \is_inf $7
7180     sync init
7181   end
7182   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
7183   wire width 1 \is_overflowed
7184   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
7185   wire width 1 \exp_gt127
7186   process $group_3
7187     assign \is_overflowed 1'0
7188     assign \is_overflowed \exp_gt127
7189     sync init
7190   end
7191   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
7192   wire width 1 \is_denormalised
7193   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
7194   wire width 1 \exp_n126
7195   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
7196   wire width 1 $9
7197   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
7198   cell $and $10
7199     parameter \A_SIGNED 1'0
7200     parameter \A_WIDTH 1'1
7201     parameter \B_SIGNED 1'0
7202     parameter \B_WIDTH 1'1
7203     parameter \Y_WIDTH 1'1
7204     connect \A \exp_n126
7205     connect \B \m_msbzero
7206     connect \Y $9
7207   end
7208   process $group_4
7209     assign \is_denormalised 1'0
7210     assign \is_denormalised $9
7211     sync init
7212   end
7213   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
7214   wire width 1 $11
7215   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
7216   cell $eq $12
7217     parameter \A_SIGNED 1'1
7218     parameter \A_WIDTH 4'1101
7219     parameter \B_SIGNED 1'1
7220     parameter \B_WIDTH 4'1101
7221     parameter \Y_WIDTH 1'1
7222     connect \A \z_e
7223     connect \B 13'0010000000000
7224     connect \Y $11
7225   end
7226   process $group_5
7227     assign \exp_128 1'0
7228     assign \exp_128 $11
7229     sync init
7230   end
7231   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
7232   wire width 14 $13
7233   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
7234   wire width 14 $14
7235   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
7236   cell $sub $15
7237     parameter \A_SIGNED 1'1
7238     parameter \A_WIDTH 4'1101
7239     parameter \B_SIGNED 1'1
7240     parameter \B_WIDTH 4'1101
7241     parameter \Y_WIDTH 4'1110
7242     connect \A \z_e
7243     connect \B 13'1110000000010
7244     connect \Y $14
7245   end
7246   connect $13 $14
7247   process $group_6
7248     assign \exp_sub_n126 13'0000000000000
7249     assign \exp_sub_n126 $13 [12:0]
7250     sync init
7251   end
7252   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
7253   wire width 1 $16
7254   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
7255   cell $gt $17
7256     parameter \A_SIGNED 1'1
7257     parameter \A_WIDTH 4'1101
7258     parameter \B_SIGNED 1'1
7259     parameter \B_WIDTH 4'1101
7260     parameter \Y_WIDTH 1'1
7261     connect \A \exp_sub_n126
7262     connect \B 13'0000000000000
7263     connect \Y $16
7264   end
7265   process $group_7
7266     assign \exp_gt_n126 1'0
7267     assign \exp_gt_n126 $16
7268     sync init
7269   end
7270   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
7271   wire width 1 $18
7272   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
7273   cell $lt $19
7274     parameter \A_SIGNED 1'1
7275     parameter \A_WIDTH 4'1101
7276     parameter \B_SIGNED 1'1
7277     parameter \B_WIDTH 4'1101
7278     parameter \Y_WIDTH 1'1
7279     connect \A \exp_sub_n126
7280     connect \B 13'0000000000000
7281     connect \Y $18
7282   end
7283   process $group_8
7284     assign \exp_lt_n126 1'0
7285     assign \exp_lt_n126 $18
7286     sync init
7287   end
7288   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
7289   wire width 1 \exp_zero
7290   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
7291   wire width 1 $20
7292   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
7293   cell $eq $21
7294     parameter \A_SIGNED 1'1
7295     parameter \A_WIDTH 4'1101
7296     parameter \B_SIGNED 1'1
7297     parameter \B_WIDTH 4'1101
7298     parameter \Y_WIDTH 1'1
7299     connect \A \z_e
7300     connect \B 13'0000000000000
7301     connect \Y $20
7302   end
7303   process $group_9
7304     assign \exp_zero 1'0
7305     assign \exp_zero $20
7306     sync init
7307   end
7308   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
7309   wire width 1 $22
7310   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
7311   cell $gt $23
7312     parameter \A_SIGNED 1'1
7313     parameter \A_WIDTH 4'1101
7314     parameter \B_SIGNED 1'1
7315     parameter \B_WIDTH 4'1101
7316     parameter \Y_WIDTH 1'1
7317     connect \A \z_e
7318     connect \B 13'0001111111111
7319     connect \Y $22
7320   end
7321   process $group_10
7322     assign \exp_gt127 1'0
7323     assign \exp_gt127 $22
7324     sync init
7325   end
7326   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
7327   wire width 1 $24
7328   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
7329   cell $eq $25
7330     parameter \A_SIGNED 1'1
7331     parameter \A_WIDTH 4'1101
7332     parameter \B_SIGNED 1'1
7333     parameter \B_WIDTH 4'1101
7334     parameter \Y_WIDTH 1'1
7335     connect \A \z_e
7336     connect \B 13'1110000000001
7337     connect \Y $24
7338   end
7339   process $group_11
7340     assign \exp_n127 1'0
7341     assign \exp_n127 $24
7342     sync init
7343   end
7344   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
7345   wire width 1 $26
7346   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
7347   cell $eq $27
7348     parameter \A_SIGNED 1'1
7349     parameter \A_WIDTH 4'1101
7350     parameter \B_SIGNED 1'1
7351     parameter \B_WIDTH 4'1101
7352     parameter \Y_WIDTH 1'1
7353     connect \A \z_e
7354     connect \B 13'1110000000010
7355     connect \Y $26
7356   end
7357   process $group_12
7358     assign \exp_n126 1'0
7359     assign \exp_n126 $26
7360     sync init
7361   end
7362   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
7363   wire width 1 $28
7364   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
7365   cell $eq $29
7366     parameter \A_SIGNED 1'0
7367     parameter \A_WIDTH 6'110101
7368     parameter \B_SIGNED 1'0
7369     parameter \B_WIDTH 6'110101
7370     parameter \Y_WIDTH 1'1
7371     connect \A \z_m
7372     connect \B 53'00000000000000000000000000000000000000000000000000000
7373     connect \Y $28
7374   end
7375   process $group_13
7376     assign \m_zero 1'0
7377     assign \m_zero $28
7378     sync init
7379   end
7380   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
7381   wire width 1 $30
7382   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
7383   cell $eq $31
7384     parameter \A_SIGNED 1'0
7385     parameter \A_WIDTH 1'1
7386     parameter \B_SIGNED 1'0
7387     parameter \B_WIDTH 1'1
7388     parameter \Y_WIDTH 1'1
7389     connect \A \z_m [52]
7390     connect \B 1'0
7391     connect \Y $30
7392   end
7393   process $group_14
7394     assign \m_msbzero 1'0
7395     assign \m_msbzero $30
7396     sync init
7397   end
7398 end
7399 attribute \generator "nMigen"
7400 attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_exp.multishift_r"
7401 module \multishift_r
7402   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:557"
7403   wire width 57 input 0 \inp
7404   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558"
7405   wire width 13 input 1 \diff
7406   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:556"
7407   wire width 57 output 2 \m
7408   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:568"
7409   wire width 13 \maxslen
7410   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574"
7411   wire width 14 $1
7412   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558"
7413   wire width 14 $2
7414   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558"
7415   cell $pos $3
7416     parameter \A_SIGNED 1'1
7417     parameter \A_WIDTH 4'1101
7418     parameter \Y_WIDTH 4'1110
7419     connect \A \diff
7420     connect \Y $2
7421   end
7422   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574"
7423   wire width 14 $4
7424   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574"
7425   wire width 1 $5
7426   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574"
7427   cell $gt $6
7428     parameter \A_SIGNED 1'1
7429     parameter \A_WIDTH 4'1101
7430     parameter \B_SIGNED 1'1
7431     parameter \B_WIDTH 4'1101
7432     parameter \Y_WIDTH 1'1
7433     connect \A \diff
7434     connect \B 13'0000000111000
7435     connect \Y $5
7436   end
7437   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574"
7438   cell $mux $7
7439     parameter \WIDTH 4'1110
7440     connect \A $2
7441     connect \B 14'00000000111000
7442     connect \S $5
7443     connect \Y $4
7444   end
7445   connect $1 $4
7446   process $group_0
7447     assign \maxslen 13'0000000000000
7448     assign \maxslen $1 [12:0]
7449     sync init
7450   end
7451   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:569"
7452   wire width 13 \maxsleni
7453   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575"
7454   wire width 15 $8
7455   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575"
7456   wire width 15 $9
7457   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575"
7458   cell $sub $10
7459     parameter \A_SIGNED 1'1
7460     parameter \A_WIDTH 4'1101
7461     parameter \B_SIGNED 1'1
7462     parameter \B_WIDTH 4'1101
7463     parameter \Y_WIDTH 4'1111
7464     connect \A 13'0000000111000
7465     connect \B \diff
7466     connect \Y $9
7467   end
7468   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575"
7469   wire width 15 $11
7470   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575"
7471   wire width 1 $12
7472   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575"
7473   cell $gt $13
7474     parameter \A_SIGNED 1'1
7475     parameter \A_WIDTH 4'1101
7476     parameter \B_SIGNED 1'1
7477     parameter \B_WIDTH 4'1101
7478     parameter \Y_WIDTH 1'1
7479     connect \A \diff
7480     connect \B 13'0000000111000
7481     connect \Y $12
7482   end
7483   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575"
7484   cell $mux $14
7485     parameter \WIDTH 4'1111
7486     connect \A $9
7487     connect \B 15'000000000000000
7488     connect \S $12
7489     connect \Y $11
7490   end
7491   connect $8 $11
7492   process $group_1
7493     assign \maxsleni 13'0000000000000
7494     assign \maxsleni $8 [12:0]
7495     sync init
7496   end
7497   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:564"
7498   wire width 57 \rs
7499   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
7500   wire width 57 $15
7501   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319"
7502   wire width 56 $16
7503   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319"
7504   cell $sshr $17
7505     parameter \A_SIGNED 1'0
7506     parameter \A_WIDTH 6'111000
7507     parameter \B_SIGNED 1'0
7508     parameter \B_WIDTH 4'1101
7509     parameter \Y_WIDTH 6'111000
7510     connect \A \inp [56:1]
7511     connect \B \maxslen
7512     connect \Y $16
7513   end
7514   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
7515   cell $pos $18
7516     parameter \A_SIGNED 1'0
7517     parameter \A_WIDTH 6'111000
7518     parameter \Y_WIDTH 6'111001
7519     connect \A $16
7520     connect \Y $15
7521   end
7522   process $group_2
7523     assign \rs 57'000000000000000000000000000000000000000000000000000000000
7524     assign \rs $15
7525     sync init
7526   end
7527   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:565"
7528   wire width 57 \m_mask
7529   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
7530   wire width 57 $19
7531   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:581"
7532   wire width 56 $20
7533   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:581"
7534   cell $not $21
7535     parameter \A_SIGNED 1'0
7536     parameter \A_WIDTH 6'111000
7537     parameter \Y_WIDTH 6'111000
7538     connect \A 56'00000000000000000000000000000000000000000000000000000000
7539     connect \Y $20
7540   end
7541   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319"
7542   wire width 56 $22
7543   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319"
7544   cell $sshr $23
7545     parameter \A_SIGNED 1'0
7546     parameter \A_WIDTH 6'111000
7547     parameter \B_SIGNED 1'0
7548     parameter \B_WIDTH 4'1101
7549     parameter \Y_WIDTH 6'111000
7550     connect \A $20
7551     connect \B \maxsleni
7552     connect \Y $22
7553   end
7554   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223"
7555   cell $pos $24
7556     parameter \A_SIGNED 1'0
7557     parameter \A_WIDTH 6'111000
7558     parameter \Y_WIDTH 6'111001
7559     connect \A $22
7560     connect \Y $19
7561   end
7562   process $group_3
7563     assign \m_mask 57'000000000000000000000000000000000000000000000000000000000
7564     assign \m_mask $19
7565     sync init
7566   end
7567   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:566"
7568   wire width 57 \smask
7569   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:582"
7570   wire width 57 $25
7571   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:582"
7572   cell $and $26
7573     parameter \A_SIGNED 1'0
7574     parameter \A_WIDTH 6'111000
7575     parameter \B_SIGNED 1'0
7576     parameter \B_WIDTH 6'111001
7577     parameter \Y_WIDTH 6'111001
7578     connect \A \inp [56:1]
7579     connect \B \m_mask
7580     connect \Y $25
7581   end
7582   process $group_4
7583     assign \smask 57'000000000000000000000000000000000000000000000000000000000
7584     assign \smask $25
7585     sync init
7586   end
7587   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:567"
7588   wire width 1 \stickybit
7589   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584"
7590   wire width 1 $27
7591   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584"
7592   cell $reduce_bool $28
7593     parameter \A_SIGNED 1'0
7594     parameter \A_WIDTH 6'111001
7595     parameter \Y_WIDTH 1'1
7596     connect \A \smask
7597     connect \Y $27
7598   end
7599   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584"
7600   wire width 1 $29
7601   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584"
7602   cell $or $30
7603     parameter \A_SIGNED 1'0
7604     parameter \A_WIDTH 1'1
7605     parameter \B_SIGNED 1'0
7606     parameter \B_WIDTH 1'1
7607     parameter \Y_WIDTH 1'1
7608     connect \A $27
7609     connect \B \inp [0]
7610     connect \Y $29
7611   end
7612   process $group_5
7613     assign \stickybit 1'0
7614     assign \stickybit $29
7615     sync init
7616   end
7617   process $group_6
7618     assign \m 57'000000000000000000000000000000000000000000000000000000000
7619     assign \m { \rs \stickybit } [56:0]
7620     sync init
7621   end
7622 end
7623 attribute \generator "nMigen"
7624 attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_exp"
7625 module \norm_exp
7626   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:18"
7627   wire width 57 input 0 \m_in
7628   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:19"
7629   wire width 13 input 1 \e_in
7630   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:16"
7631   wire width 13 input 2 \ediff
7632   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:20"
7633   wire width 57 output 3 \m_out
7634   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:21"
7635   wire width 13 output 4 \e_out
7636   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:557"
7637   wire width 57 \multishift_r_inp
7638   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558"
7639   wire width 13 \multishift_r_diff
7640   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:556"
7641   wire width 57 \multishift_r_m
7642   cell \multishift_r \multishift_r
7643     connect \inp \multishift_r_inp
7644     connect \diff \multishift_r_diff
7645     connect \m \multishift_r_m
7646   end
7647   process $group_0
7648     assign \multishift_r_inp 57'000000000000000000000000000000000000000000000000000000000
7649     assign \multishift_r_inp \m_in
7650     sync init
7651   end
7652   process $group_1
7653     assign \multishift_r_diff 13'0000000000000
7654     assign \multishift_r_diff \ediff
7655     sync init
7656   end
7657   process $group_2
7658     assign \m_out 57'000000000000000000000000000000000000000000000000000000000
7659     assign \m_out \multishift_r_m
7660     sync init
7661   end
7662   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:37"
7663   wire width 14 $1
7664   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:37"
7665   wire width 14 $2
7666   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:37"
7667   cell $add $3
7668     parameter \A_SIGNED 1'1
7669     parameter \A_WIDTH 4'1101
7670     parameter \B_SIGNED 1'1
7671     parameter \B_WIDTH 4'1101
7672     parameter \Y_WIDTH 4'1110
7673     connect \A \e_in
7674     connect \B \ediff
7675     connect \Y $2
7676   end
7677   connect $1 $2
7678   process $group_3
7679     assign \e_out 13'0000000000000
7680     assign \e_out $1 [12:0]
7681     sync init
7682   end
7683 end
7684 attribute \generator "nMigen"
7685 attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_msb.pe"
7686 module \pe__9
7687   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
7688   wire width 56 input 0 \i
7689   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
7690   wire width 6 output 1 \o
7691   process $group_0
7692     assign \o 6'000000
7693     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7694     switch { \i [55] }
7695       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7696       case 1'1
7697         assign \o 6'110111
7698     end
7699     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7700     switch { \i [54] }
7701       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7702       case 1'1
7703         assign \o 6'110110
7704     end
7705     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7706     switch { \i [53] }
7707       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7708       case 1'1
7709         assign \o 6'110101
7710     end
7711     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7712     switch { \i [52] }
7713       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7714       case 1'1
7715         assign \o 6'110100
7716     end
7717     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7718     switch { \i [51] }
7719       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7720       case 1'1
7721         assign \o 6'110011
7722     end
7723     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7724     switch { \i [50] }
7725       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7726       case 1'1
7727         assign \o 6'110010
7728     end
7729     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7730     switch { \i [49] }
7731       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7732       case 1'1
7733         assign \o 6'110001
7734     end
7735     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7736     switch { \i [48] }
7737       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7738       case 1'1
7739         assign \o 6'110000
7740     end
7741     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7742     switch { \i [47] }
7743       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7744       case 1'1
7745         assign \o 6'101111
7746     end
7747     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7748     switch { \i [46] }
7749       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7750       case 1'1
7751         assign \o 6'101110
7752     end
7753     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7754     switch { \i [45] }
7755       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7756       case 1'1
7757         assign \o 6'101101
7758     end
7759     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7760     switch { \i [44] }
7761       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7762       case 1'1
7763         assign \o 6'101100
7764     end
7765     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7766     switch { \i [43] }
7767       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7768       case 1'1
7769         assign \o 6'101011
7770     end
7771     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7772     switch { \i [42] }
7773       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7774       case 1'1
7775         assign \o 6'101010
7776     end
7777     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7778     switch { \i [41] }
7779       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7780       case 1'1
7781         assign \o 6'101001
7782     end
7783     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7784     switch { \i [40] }
7785       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7786       case 1'1
7787         assign \o 6'101000
7788     end
7789     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7790     switch { \i [39] }
7791       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7792       case 1'1
7793         assign \o 6'100111
7794     end
7795     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7796     switch { \i [38] }
7797       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7798       case 1'1
7799         assign \o 6'100110
7800     end
7801     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7802     switch { \i [37] }
7803       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7804       case 1'1
7805         assign \o 6'100101
7806     end
7807     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7808     switch { \i [36] }
7809       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7810       case 1'1
7811         assign \o 6'100100
7812     end
7813     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7814     switch { \i [35] }
7815       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7816       case 1'1
7817         assign \o 6'100011
7818     end
7819     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7820     switch { \i [34] }
7821       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7822       case 1'1
7823         assign \o 6'100010
7824     end
7825     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7826     switch { \i [33] }
7827       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7828       case 1'1
7829         assign \o 6'100001
7830     end
7831     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7832     switch { \i [32] }
7833       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7834       case 1'1
7835         assign \o 6'100000
7836     end
7837     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7838     switch { \i [31] }
7839       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7840       case 1'1
7841         assign \o 6'011111
7842     end
7843     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7844     switch { \i [30] }
7845       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7846       case 1'1
7847         assign \o 6'011110
7848     end
7849     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7850     switch { \i [29] }
7851       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7852       case 1'1
7853         assign \o 6'011101
7854     end
7855     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7856     switch { \i [28] }
7857       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7858       case 1'1
7859         assign \o 6'011100
7860     end
7861     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7862     switch { \i [27] }
7863       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7864       case 1'1
7865         assign \o 6'011011
7866     end
7867     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7868     switch { \i [26] }
7869       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7870       case 1'1
7871         assign \o 6'011010
7872     end
7873     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7874     switch { \i [25] }
7875       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7876       case 1'1
7877         assign \o 6'011001
7878     end
7879     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7880     switch { \i [24] }
7881       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7882       case 1'1
7883         assign \o 6'011000
7884     end
7885     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7886     switch { \i [23] }
7887       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7888       case 1'1
7889         assign \o 6'010111
7890     end
7891     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7892     switch { \i [22] }
7893       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7894       case 1'1
7895         assign \o 6'010110
7896     end
7897     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7898     switch { \i [21] }
7899       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7900       case 1'1
7901         assign \o 6'010101
7902     end
7903     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7904     switch { \i [20] }
7905       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7906       case 1'1
7907         assign \o 6'010100
7908     end
7909     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7910     switch { \i [19] }
7911       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7912       case 1'1
7913         assign \o 6'010011
7914     end
7915     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7916     switch { \i [18] }
7917       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7918       case 1'1
7919         assign \o 6'010010
7920     end
7921     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7922     switch { \i [17] }
7923       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7924       case 1'1
7925         assign \o 6'010001
7926     end
7927     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7928     switch { \i [16] }
7929       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7930       case 1'1
7931         assign \o 6'010000
7932     end
7933     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7934     switch { \i [15] }
7935       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7936       case 1'1
7937         assign \o 6'001111
7938     end
7939     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7940     switch { \i [14] }
7941       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7942       case 1'1
7943         assign \o 6'001110
7944     end
7945     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7946     switch { \i [13] }
7947       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7948       case 1'1
7949         assign \o 6'001101
7950     end
7951     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7952     switch { \i [12] }
7953       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7954       case 1'1
7955         assign \o 6'001100
7956     end
7957     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7958     switch { \i [11] }
7959       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7960       case 1'1
7961         assign \o 6'001011
7962     end
7963     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7964     switch { \i [10] }
7965       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7966       case 1'1
7967         assign \o 6'001010
7968     end
7969     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7970     switch { \i [9] }
7971       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7972       case 1'1
7973         assign \o 6'001001
7974     end
7975     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7976     switch { \i [8] }
7977       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7978       case 1'1
7979         assign \o 6'001000
7980     end
7981     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7982     switch { \i [7] }
7983       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7984       case 1'1
7985         assign \o 6'000111
7986     end
7987     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7988     switch { \i [6] }
7989       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7990       case 1'1
7991         assign \o 6'000110
7992     end
7993     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7994     switch { \i [5] }
7995       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
7996       case 1'1
7997         assign \o 6'000101
7998     end
7999     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8000     switch { \i [4] }
8001       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8002       case 1'1
8003         assign \o 6'000100
8004     end
8005     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8006     switch { \i [3] }
8007       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8008       case 1'1
8009         assign \o 6'000011
8010     end
8011     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8012     switch { \i [2] }
8013       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8014       case 1'1
8015         assign \o 6'000010
8016     end
8017     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8018     switch { \i [1] }
8019       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8020       case 1'1
8021         assign \o 6'000001
8022     end
8023     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8024     switch { \i [0] }
8025       attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82"
8026       case 1'1
8027         assign \o 6'000000
8028     end
8029     sync init
8030   end
8031   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77"
8032   wire width 1 \n
8033   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
8034   wire width 1 $1
8035   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84"
8036   cell $eq $2
8037     parameter \A_SIGNED 1'0
8038     parameter \A_WIDTH 6'111000
8039     parameter \B_SIGNED 1'0
8040     parameter \B_WIDTH 1'1
8041     parameter \Y_WIDTH 1'1
8042     connect \A \i
8043     connect \B 1'0
8044     connect \Y $1
8045   end
8046   process $group_1
8047     assign \n 1'0
8048     assign \n $1
8049     sync init
8050   end
8051 end
8052 attribute \generator "nMigen"
8053 attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_msb"
8054 module \norm_msb
8055   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:29"
8056   wire width 13 input 0 \limclz
8057   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31"
8058   wire width 56 input 1 \m_in
8059   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32"
8060   wire width 13 input 2 \e_in
8061   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33"
8062   wire width 56 output 3 \m_out
8063   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34"
8064   wire width 13 output 4 \e_out
8065   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75"
8066   wire width 56 \pe_i
8067   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8068   wire width 6 \pe_o
8069   cell \pe__9 \pe
8070     connect \i \pe_i
8071     connect \o \pe_o
8072   end
8073   process $group_0
8074     assign \pe_i 56'00000000000000000000000000000000000000000000000000000000
8075     assign \pe_i { \m_in [0] \m_in [1] \m_in [2] \m_in [3] \m_in [4] \m_in [5] \m_in [6] \m_in [7] \m_in [8] \m_in [9] \m_in [10] \m_in [11] \m_in [12] \m_in [13] \m_in [14] \m_in [15] \m_in [16] \m_in [17] \m_in [18] \m_in [19] \m_in [20] \m_in [21] \m_in [22] \m_in [23] \m_in [24] \m_in [25] \m_in [26] \m_in [27] \m_in [28] \m_in [29] \m_in [30] \m_in [31] \m_in [32] \m_in [33] \m_in [34] \m_in [35] \m_in [36] \m_in [37] \m_in [38] \m_in [39] \m_in [40] \m_in [41] \m_in [42] \m_in [43] \m_in [44] \m_in [45] \m_in [46] \m_in [47] \m_in [48] \m_in [49] \m_in [50] \m_in [51] \m_in [52] \m_in [53] \m_in [54] \m_in [55] }
8076     sync init
8077   end
8078   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:48"
8079   wire width 13 \clz
8080   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8081   wire width 13 $1
8082   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8083   cell $pos $2
8084     parameter \A_SIGNED 1'0
8085     parameter \A_WIDTH 3'110
8086     parameter \Y_WIDTH 4'1101
8087     connect \A \pe_o
8088     connect \Y $1
8089   end
8090   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8091   wire width 13 $3
8092   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8093   wire width 13 $4
8094   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8095   cell $pos $5
8096     parameter \A_SIGNED 1'0
8097     parameter \A_WIDTH 3'110
8098     parameter \Y_WIDTH 4'1101
8099     connect \A \pe_o
8100     connect \Y $4
8101   end
8102   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8103   wire width 1 $6
8104   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8105   cell $gt $7
8106     parameter \A_SIGNED 1'1
8107     parameter \A_WIDTH 4'1101
8108     parameter \B_SIGNED 1'1
8109     parameter \B_WIDTH 4'1101
8110     parameter \Y_WIDTH 1'1
8111     connect \A \limclz
8112     connect \B $4
8113     connect \Y $6
8114   end
8115   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8116   cell $mux $8
8117     parameter \WIDTH 4'1101
8118     connect \A \limclz
8119     connect \B $1
8120     connect \S $6
8121     connect \Y $3
8122   end
8123   process $group_1
8124     assign \clz 13'0000000000000
8125     assign \clz $3
8126     sync init
8127   end
8128   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:50"
8129   wire width 13 \uclz
8130   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8131   wire width 13 $9
8132   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8133   cell $pos $10
8134     parameter \A_SIGNED 1'0
8135     parameter \A_WIDTH 3'110
8136     parameter \Y_WIDTH 4'1101
8137     connect \A \pe_o
8138     connect \Y $9
8139   end
8140   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8141   wire width 13 $11
8142   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8143   wire width 13 $12
8144   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76"
8145   cell $pos $13
8146     parameter \A_SIGNED 1'0
8147     parameter \A_WIDTH 3'110
8148     parameter \Y_WIDTH 4'1101
8149     connect \A \pe_o
8150     connect \Y $12
8151   end
8152   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8153   wire width 1 $14
8154   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8155   cell $gt $15
8156     parameter \A_SIGNED 1'1
8157     parameter \A_WIDTH 4'1101
8158     parameter \B_SIGNED 1'1
8159     parameter \B_WIDTH 4'1101
8160     parameter \Y_WIDTH 1'1
8161     connect \A \limclz
8162     connect \B $12
8163     connect \Y $14
8164   end
8165   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63"
8166   cell $mux $16
8167     parameter \WIDTH 4'1101
8168     connect \A \limclz
8169     connect \B $9
8170     connect \S $14
8171     connect \Y $11
8172   end
8173   process $group_2
8174     assign \uclz 13'0000000000000
8175     assign \uclz $11
8176     sync init
8177   end
8178   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:51"
8179   wire width 56 \temp
8180   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
8181   wire width 8247 $17
8182   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
8183   wire width 8247 $18
8184   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71"
8185   cell $sshl $19
8186     parameter \A_SIGNED 1'0
8187     parameter \A_WIDTH 6'111000
8188     parameter \B_SIGNED 1'0
8189     parameter \B_WIDTH 4'1101
8190     parameter \Y_WIDTH 14'10000000110111
8191     connect \A \m_in
8192     connect \B \uclz
8193     connect \Y $18
8194   end
8195   connect $17 $18
8196   process $group_3
8197     assign \temp 56'00000000000000000000000000000000000000000000000000000000
8198     assign \temp $17 [55:0]
8199     sync init
8200   end
8201   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
8202   wire width 14 $20
8203   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
8204   wire width 14 $21
8205   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72"
8206   cell $sub $22
8207     parameter \A_SIGNED 1'1
8208     parameter \A_WIDTH 4'1101
8209     parameter \B_SIGNED 1'1
8210     parameter \B_WIDTH 4'1101
8211     parameter \Y_WIDTH 4'1110
8212     connect \A \e_in
8213     connect \B \clz
8214     connect \Y $21
8215   end
8216   connect $20 $21
8217   process $group_4
8218     assign \e_out 13'0000000000000
8219     assign \e_out $20 [12:0]
8220     sync init
8221   end
8222   process $group_5
8223     assign \m_out 56'00000000000000000000000000000000000000000000000000000000
8224     assign \m_out \temp
8225     sync init
8226   end
8227 end
8228 attribute \generator "nMigen"
8229 attribute \nmigen.hierarchy "top.alu.normpack.normalise_1"
8230 module \normalise_1
8231   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
8232   wire width 1 input 0 \z_s
8233   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8234   wire width 13 input 1 \z_e
8235   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8236   wire width 53 input 2 \z_m
8237   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
8238   wire width 1 input 3 \out_do_z
8239   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
8240   wire width 64 input 4 \oz
8241   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
8242   wire width 1 input 5 \guard
8243   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
8244   wire width 1 input 6 \round
8245   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
8246   wire width 1 input 7 \sticky
8247   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
8248   wire width 1 input 8 \m0
8249   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
8250   wire width 5 input 9 \fflags
8251   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
8252   wire width 2 input 10 \muxid
8253   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
8254   wire width 0 input 11 \op
8255   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
8256   wire width 1 output 12 \z_s__1
8257   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8258   wire width 13 output 13 \z_e__2
8259   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8260   wire width 53 output 14 \z_m__3
8261   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:25"
8262   wire width 1 output 15 \out_do_z__4
8263   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:26"
8264   wire width 64 output 16 \oz__5
8265   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:23"
8266   wire width 1 output 17 \norm1_roundz
8267   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
8268   wire width 2 output 18 \muxid__6
8269   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
8270   wire width 0 output 19 \op__7
8271   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
8272   wire width 1 \norm1_out_overflow_norm1of_guard
8273   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
8274   wire width 1 \norm1_out_overflow_norm1of_round
8275   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
8276   wire width 1 \norm1_out_overflow_norm1of_sticky
8277   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
8278   wire width 1 \norm1_out_overflow_norm1of_m0
8279   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:921"
8280   wire width 1 \norm1_out_overflow_norm1of_roundz_out
8281   cell \norm1_out_overflow \norm1_out_overflow
8282     connect \norm1of_guard \norm1_out_overflow_norm1of_guard
8283     connect \norm1of_round \norm1_out_overflow_norm1of_round
8284     connect \norm1of_sticky \norm1_out_overflow_norm1of_sticky
8285     connect \norm1of_m0 \norm1_out_overflow_norm1of_m0
8286     connect \norm1of_roundz_out \norm1_out_overflow_norm1of_roundz_out
8287   end
8288   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8289   wire width 13 \norm1_insel_z_z_e
8290   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8291   wire width 53 \norm1_insel_z_z_m
8292   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
8293   wire width 1 \norm1_insel_z_m_msbzero
8294   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
8295   wire width 1 \norm1_insel_z_exp_gt_n126
8296   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
8297   wire width 1 \norm1_insel_z_exp_lt_n126
8298   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
8299   wire width 13 \norm1_insel_z_exp_sub_n126
8300   cell \norm1_insel_z \norm1_insel_z
8301     connect \z_e \norm1_insel_z_z_e
8302     connect \z_m \norm1_insel_z_z_m
8303     connect \m_msbzero \norm1_insel_z_m_msbzero
8304     connect \exp_gt_n126 \norm1_insel_z_exp_gt_n126
8305     connect \exp_lt_n126 \norm1_insel_z_exp_lt_n126
8306     connect \exp_sub_n126 \norm1_insel_z_exp_sub_n126
8307   end
8308   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:18"
8309   wire width 57 \norm_exp_m_in
8310   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:19"
8311   wire width 13 \norm_exp_e_in
8312   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:16"
8313   wire width 13 \norm_exp_ediff
8314   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:20"
8315   wire width 57 \norm_exp_m_out
8316   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:21"
8317   wire width 13 \norm_exp_e_out
8318   cell \norm_exp \norm_exp
8319     connect \m_in \norm_exp_m_in
8320     connect \e_in \norm_exp_e_in
8321     connect \ediff \norm_exp_ediff
8322     connect \m_out \norm_exp_m_out
8323     connect \e_out \norm_exp_e_out
8324   end
8325   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:29"
8326   wire width 13 \norm_msb_limclz
8327   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31"
8328   wire width 56 \norm_msb_m_in
8329   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32"
8330   wire width 13 \norm_msb_e_in
8331   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33"
8332   wire width 56 \norm_msb_m_out
8333   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34"
8334   wire width 13 \norm_msb_e_out
8335   cell \norm_msb \norm_msb
8336     connect \limclz \norm_msb_limclz
8337     connect \m_in \norm_msb_m_in
8338     connect \e_in \norm_msb_e_in
8339     connect \m_out \norm_msb_m_out
8340     connect \e_out \norm_msb_e_out
8341   end
8342   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
8343   wire width 1 \z_s__8
8344   process $group_0
8345     assign \z_s__8 1'0
8346     assign \z_s__8 \z_s
8347     sync init
8348   end
8349   process $group_1
8350     assign \norm1_insel_z_z_e 13'0000000000000
8351     assign \norm1_insel_z_z_e \z_e
8352     sync init
8353   end
8354   process $group_2
8355     assign \norm1_insel_z_z_m 53'00000000000000000000000000000000000000000000000000000
8356     assign \norm1_insel_z_z_m \z_m
8357     sync init
8358   end
8359   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
8360   wire width 1 \out_do_z__9
8361   process $group_3
8362     assign \out_do_z__9 1'0
8363     assign \out_do_z__9 \out_do_z
8364     sync init
8365   end
8366   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
8367   wire width 64 \oz__10
8368   process $group_4
8369     assign \oz__10 64'0000000000000000000000000000000000000000000000000000000000000000
8370     assign \oz__10 \oz
8371     sync init
8372   end
8373   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
8374   wire width 1 \norm1_i_of_guard
8375   process $group_5
8376     assign \norm1_i_of_guard 1'0
8377     assign \norm1_i_of_guard \guard
8378     sync init
8379   end
8380   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
8381   wire width 1 \norm1_i_of_roundbit
8382   process $group_6
8383     assign \norm1_i_of_roundbit 1'0
8384     assign \norm1_i_of_roundbit \round
8385     sync init
8386   end
8387   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
8388   wire width 1 \norm1_i_of_sticky
8389   process $group_7
8390     assign \norm1_i_of_sticky 1'0
8391     assign \norm1_i_of_sticky \sticky
8392     sync init
8393   end
8394   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
8395   wire width 1 \norm1_i_of_m0
8396   process $group_8
8397     assign \norm1_i_of_m0 1'0
8398     assign \norm1_i_of_m0 \m0
8399     sync init
8400   end
8401   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
8402   wire width 5 \fflags__11
8403   process $group_9
8404     assign \fflags__11 5'00000
8405     assign \fflags__11 \fflags
8406     sync init
8407   end
8408   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
8409   wire width 2 \muxid__12
8410   process $group_10
8411     assign \muxid__12 2'00
8412     assign \muxid__12 \muxid
8413     sync init
8414   end
8415   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
8416   wire width 0 \op__13
8417   process $group_11
8418     assign \op__13 0'0
8419     assign \op__13 \op
8420     sync init
8421   end
8422   process $group_12
8423     assign \z_s__1 1'0
8424     assign \z_s__1 \z_s__8
8425     sync init
8426   end
8427   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:75"
8428   wire width 1 \decrease
8429   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:76"
8430   wire width 1 \increase
8431   process $group_13
8432     assign \z_e__2 13'0000000000000
8433     assign \z_e__2 \norm1_insel_z_z_e
8434     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8435     switch { \increase \decrease }
8436       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8437       case 2'-1
8438         assign \z_e__2 \norm_msb_e_out
8439       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8440       case 2'1-
8441         assign \z_e__2 \norm_exp_e_out
8442     end
8443     sync init
8444   end
8445   process $group_14
8446     assign \z_m__3 53'00000000000000000000000000000000000000000000000000000
8447     assign \z_m__3 \norm1_insel_z_z_m
8448     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8449     switch { \increase \decrease }
8450       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8451       case 2'-1
8452         assign \z_m__3 \norm_msb_m_out [55:3]
8453       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8454       case 2'1-
8455         assign \z_m__3 \norm_exp_m_out [56:3] [52:0]
8456     end
8457     sync init
8458   end
8459   process $group_15
8460     assign \norm1_out_overflow_norm1of_guard 1'0
8461     assign \norm1_out_overflow_norm1of_guard \norm1_i_of_guard
8462     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8463     switch { \increase \decrease }
8464       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8465       case 2'-1
8466         assign \norm1_out_overflow_norm1of_guard \norm_msb_m_out [2]
8467       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8468       case 2'1-
8469         assign \norm1_out_overflow_norm1of_guard \norm_exp_m_out [2]
8470     end
8471     sync init
8472   end
8473   process $group_16
8474     assign \norm1_out_overflow_norm1of_round 1'0
8475     assign \norm1_out_overflow_norm1of_round \norm1_i_of_roundbit
8476     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8477     switch { \increase \decrease }
8478       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8479       case 2'-1
8480         assign \norm1_out_overflow_norm1of_round \norm_msb_m_out [1]
8481       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8482       case 2'1-
8483         assign \norm1_out_overflow_norm1of_round \norm_exp_m_out [1]
8484     end
8485     sync init
8486   end
8487   process $group_17
8488     assign \norm1_out_overflow_norm1of_sticky 1'0
8489     assign \norm1_out_overflow_norm1of_sticky \norm1_i_of_sticky
8490     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8491     switch { \increase \decrease }
8492       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8493       case 2'-1
8494       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8495       case 2'1-
8496         assign \norm1_out_overflow_norm1of_sticky \norm_exp_m_out [0]
8497     end
8498     sync init
8499   end
8500   process $group_18
8501     assign \norm1_out_overflow_norm1of_m0 1'0
8502     assign \norm1_out_overflow_norm1of_m0 \norm1_i_of_m0
8503     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8504     switch { \increase \decrease }
8505       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8506       case 2'-1
8507         assign \norm1_out_overflow_norm1of_m0 \norm_msb_m_out [3]
8508       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8509       case 2'1-
8510         assign \norm1_out_overflow_norm1of_m0 \norm_exp_m_out [3]
8511     end
8512     sync init
8513   end
8514   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
8515   wire width 5 \norm1of_fflags
8516   process $group_19
8517     assign \norm1of_fflags 5'00000
8518     assign \norm1of_fflags \fflags__11
8519     sync init
8520   end
8521   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:77"
8522   wire width 1 $14
8523   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:77"
8524   cell $and $15
8525     parameter \A_SIGNED 1'0
8526     parameter \A_WIDTH 1'1
8527     parameter \B_SIGNED 1'0
8528     parameter \B_WIDTH 1'1
8529     parameter \Y_WIDTH 1'1
8530     connect \A \norm1_insel_z_m_msbzero
8531     connect \B \norm1_insel_z_exp_gt_n126
8532     connect \Y $14
8533   end
8534   process $group_20
8535     assign \decrease 1'0
8536     assign \decrease $14
8537     sync init
8538   end
8539   process $group_21
8540     assign \increase 1'0
8541     assign \increase \norm1_insel_z_exp_lt_n126
8542     sync init
8543   end
8544   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:82"
8545   wire width 57 \temp_m
8546   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:84"
8547   wire width 57 $16
8548   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:84"
8549   cell $pos $17
8550     parameter \A_SIGNED 1'0
8551     parameter \A_WIDTH 6'111000
8552     parameter \Y_WIDTH 6'111001
8553     connect \A { \norm1_insel_z_z_m \norm1_i_of_guard \norm1_i_of_roundbit \norm1_i_of_sticky }
8554     connect \Y $16
8555   end
8556   process $group_22
8557     assign \temp_m 57'000000000000000000000000000000000000000000000000000000000
8558     assign \temp_m $16
8559     sync init
8560   end
8561   process $group_23
8562     assign \norm_msb_limclz 13'0000000000000
8563     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8564     switch { \increase \decrease }
8565       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8566       case 2'-1
8567         assign \norm_msb_limclz \norm1_insel_z_exp_sub_n126
8568       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8569       case 2'1-
8570     end
8571     sync init
8572   end
8573   process $group_24
8574     assign \norm_msb_m_in 56'00000000000000000000000000000000000000000000000000000000
8575     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8576     switch { \increase \decrease }
8577       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8578       case 2'-1
8579         assign \norm_msb_m_in \temp_m [55:0]
8580       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8581       case 2'1-
8582     end
8583     sync init
8584   end
8585   process $group_25
8586     assign \norm_msb_e_in 13'0000000000000
8587     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8588     switch { \increase \decrease }
8589       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8590       case 2'-1
8591         assign \norm_msb_e_in \norm1_insel_z_z_e
8592       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8593       case 2'1-
8594     end
8595     sync init
8596   end
8597   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:107"
8598   wire width 13 \ediff_n126
8599   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:110"
8600   wire width 14 $18
8601   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:110"
8602   wire width 14 $19
8603   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:110"
8604   cell $sub $20
8605     parameter \A_SIGNED 1'1
8606     parameter \A_WIDTH 4'1101
8607     parameter \B_SIGNED 1'1
8608     parameter \B_WIDTH 4'1101
8609     parameter \Y_WIDTH 4'1110
8610     connect \A 13'1110000000010
8611     connect \B \norm1_insel_z_z_e
8612     connect \Y $19
8613   end
8614   connect $18 $19
8615   process $group_26
8616     assign \ediff_n126 13'0000000000000
8617     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8618     switch { \increase \decrease }
8619       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8620       case 2'-1
8621       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8622       case 2'1-
8623         assign \ediff_n126 $18 [12:0]
8624     end
8625     sync init
8626   end
8627   process $group_27
8628     assign \norm_exp_m_in 57'000000000000000000000000000000000000000000000000000000000
8629     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8630     switch { \increase \decrease }
8631       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8632       case 2'-1
8633       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8634       case 2'1-
8635         assign \norm_exp_m_in \temp_m
8636     end
8637     sync init
8638   end
8639   process $group_28
8640     assign \norm_exp_e_in 13'0000000000000
8641     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8642     switch { \increase \decrease }
8643       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8644       case 2'-1
8645       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8646       case 2'1-
8647         assign \norm_exp_e_in \norm1_insel_z_z_e
8648     end
8649     sync init
8650   end
8651   process $group_29
8652     assign \norm_exp_ediff 13'0000000000000
8653     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8654     switch { \increase \decrease }
8655       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87"
8656       case 2'-1
8657       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106"
8658       case 2'1-
8659         assign \norm_exp_ediff \ediff_n126
8660     end
8661     sync init
8662   end
8663   process $group_30
8664     assign \norm1_roundz 1'0
8665     assign \norm1_roundz \norm1_out_overflow_norm1of_roundz_out
8666     sync init
8667   end
8668   process $group_31
8669     assign \muxid__6 2'00
8670     assign \muxid__6 \muxid
8671     sync init
8672   end
8673   process $group_32
8674     assign \op__7 0'0
8675     assign \op__7 \op
8676     sync init
8677   end
8678   process $group_33
8679     assign \out_do_z__4 1'0
8680     assign \out_do_z__4 \out_do_z
8681     sync init
8682   end
8683   process $group_34
8684     assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000
8685     assign \oz__5 \oz
8686     sync init
8687   end
8688   connect \op__7 0'0
8689   connect \op__13 0'0
8690 end
8691 attribute \generator "nMigen"
8692 attribute \nmigen.hierarchy "top.alu.normpack.roundz"
8693 module \roundz
8694   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
8695   wire width 1 input 0 \z_s
8696   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8697   wire width 13 input 1 \z_e
8698   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8699   wire width 53 input 2 \z_m
8700   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:25"
8701   wire width 1 input 3 \out_do_z
8702   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:26"
8703   wire width 64 input 4 \oz
8704   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:23"
8705   wire width 1 input 5 \norm1_roundz
8706   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
8707   wire width 2 input 6 \muxid
8708   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
8709   wire width 0 input 7 \op
8710   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
8711   wire width 1 output 8 \z_s__1
8712   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8713   wire width 13 output 9 \z_e__2
8714   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8715   wire width 53 output 10 \z_m__3
8716   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
8717   wire width 1 output 11 \out_do_z__4
8718   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
8719   wire width 64 output 12 \oz__5
8720   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
8721   wire width 2 output 13 \muxid__6
8722   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
8723   wire width 0 output 14 \op__7
8724   process $group_0
8725     assign \z_s__1 1'0
8726     assign \z_s__1 \z_s
8727     sync init
8728   end
8729   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52"
8730   wire width 14 $8
8731   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52"
8732   wire width 14 $9
8733   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52"
8734   cell $add $10
8735     parameter \A_SIGNED 1'1
8736     parameter \A_WIDTH 4'1101
8737     parameter \B_SIGNED 1'1
8738     parameter \B_WIDTH 4'1101
8739     parameter \Y_WIDTH 4'1110
8740     connect \A \z_e
8741     connect \B 13'0000000000001
8742     connect \Y $9
8743   end
8744   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8745   wire width 14 $11
8746   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8747   cell $pos $12
8748     parameter \A_SIGNED 1'1
8749     parameter \A_WIDTH 4'1101
8750     parameter \Y_WIDTH 4'1110
8751     connect \A \z_e
8752     connect \Y $11
8753   end
8754   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52"
8755   wire width 14 $13
8756   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:49"
8757   wire width 1 \msb1s
8758   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52"
8759   wire width 1 $14
8760   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52"
8761   cell $and $15
8762     parameter \A_SIGNED 1'0
8763     parameter \A_WIDTH 1'1
8764     parameter \B_SIGNED 1'0
8765     parameter \B_WIDTH 1'1
8766     parameter \Y_WIDTH 1'1
8767     connect \A \msb1s
8768     connect \B \norm1_roundz
8769     connect \Y $14
8770   end
8771   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52"
8772   cell $mux $16
8773     parameter \WIDTH 4'1110
8774     connect \A $11
8775     connect \B $9
8776     connect \S $14
8777     connect \Y $13
8778   end
8779   connect $8 $13
8780   process $group_1
8781     assign \z_e__2 13'0000000000000
8782     assign \z_e__2 \z_e
8783     assign \z_e__2 $8 [12:0]
8784     sync init
8785   end
8786   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51"
8787   wire width 54 $17
8788   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51"
8789   wire width 54 $18
8790   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51"
8791   cell $add $19
8792     parameter \A_SIGNED 1'0
8793     parameter \A_WIDTH 6'110101
8794     parameter \B_SIGNED 1'0
8795     parameter \B_WIDTH 1'1
8796     parameter \Y_WIDTH 6'110110
8797     connect \A \z_m
8798     connect \B 1'1
8799     connect \Y $18
8800   end
8801   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8802   wire width 54 $20
8803   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8804   cell $pos $21
8805     parameter \A_SIGNED 1'0
8806     parameter \A_WIDTH 6'110101
8807     parameter \Y_WIDTH 6'110110
8808     connect \A \z_m
8809     connect \Y $20
8810   end
8811   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51"
8812   wire width 54 $22
8813   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51"
8814   cell $mux $23
8815     parameter \WIDTH 6'110110
8816     connect \A $20
8817     connect \B $18
8818     connect \S \norm1_roundz
8819     connect \Y $22
8820   end
8821   connect $17 $22
8822   process $group_2
8823     assign \z_m__3 53'00000000000000000000000000000000000000000000000000000
8824     assign \z_m__3 \z_m
8825     assign \z_m__3 $17 [52:0]
8826     sync init
8827   end
8828   process $group_3
8829     assign \out_do_z__4 1'0
8830     assign \out_do_z__4 \out_do_z
8831     sync init
8832   end
8833   process $group_4
8834     assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000
8835     assign \oz__5 \oz
8836     sync init
8837   end
8838   process $group_5
8839     assign \muxid__6 2'00
8840     assign \muxid__6 \muxid
8841     sync init
8842   end
8843   process $group_6
8844     assign \op__7 0'0
8845     assign \op__7 \op
8846     sync init
8847   end
8848   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:50"
8849   wire width 1 $24
8850   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:50"
8851   cell $reduce_and $25
8852     parameter \A_SIGNED 1'0
8853     parameter \A_WIDTH 6'110101
8854     parameter \Y_WIDTH 1'1
8855     connect \A \z_m
8856     connect \Y $24
8857   end
8858   process $group_7
8859     assign \msb1s 1'0
8860     assign \msb1s $24
8861     sync init
8862   end
8863   connect \op__7 0'0
8864 end
8865 attribute \generator "nMigen"
8866 attribute \nmigen.hierarchy "top.alu.normpack.corrections.corr_in_z"
8867 module \corr_in_z
8868   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
8869   wire width 13 input 0 \z_e
8870   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
8871   wire width 53 input 1 \z_m
8872   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
8873   wire width 1 output 2 \is_denormalised
8874   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
8875   wire width 1 \is_nan
8876   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
8877   wire width 1 \exp_128
8878   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
8879   wire width 1 $1
8880   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
8881   wire width 1 \m_zero
8882   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
8883   cell $not $2
8884     parameter \A_SIGNED 1'0
8885     parameter \A_WIDTH 1'1
8886     parameter \Y_WIDTH 1'1
8887     connect \A \m_zero
8888     connect \Y $1
8889   end
8890   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
8891   wire width 1 $3
8892   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
8893   cell $and $4
8894     parameter \A_SIGNED 1'0
8895     parameter \A_WIDTH 1'1
8896     parameter \B_SIGNED 1'0
8897     parameter \B_WIDTH 1'1
8898     parameter \Y_WIDTH 1'1
8899     connect \A \exp_128
8900     connect \B $1
8901     connect \Y $3
8902   end
8903   process $group_0
8904     assign \is_nan 1'0
8905     assign \is_nan $3
8906     sync init
8907   end
8908   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
8909   wire width 1 \is_zero
8910   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
8911   wire width 1 \exp_n127
8912   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
8913   wire width 1 $5
8914   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
8915   cell $and $6
8916     parameter \A_SIGNED 1'0
8917     parameter \A_WIDTH 1'1
8918     parameter \B_SIGNED 1'0
8919     parameter \B_WIDTH 1'1
8920     parameter \Y_WIDTH 1'1
8921     connect \A \exp_n127
8922     connect \B \m_zero
8923     connect \Y $5
8924   end
8925   process $group_1
8926     assign \is_zero 1'0
8927     assign \is_zero $5
8928     sync init
8929   end
8930   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
8931   wire width 1 \is_inf
8932   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
8933   wire width 1 $7
8934   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
8935   cell $and $8
8936     parameter \A_SIGNED 1'0
8937     parameter \A_WIDTH 1'1
8938     parameter \B_SIGNED 1'0
8939     parameter \B_WIDTH 1'1
8940     parameter \Y_WIDTH 1'1
8941     connect \A \exp_128
8942     connect \B \m_zero
8943     connect \Y $7
8944   end
8945   process $group_2
8946     assign \is_inf 1'0
8947     assign \is_inf $7
8948     sync init
8949   end
8950   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
8951   wire width 1 \is_overflowed
8952   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
8953   wire width 1 \exp_gt127
8954   process $group_3
8955     assign \is_overflowed 1'0
8956     assign \is_overflowed \exp_gt127
8957     sync init
8958   end
8959   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
8960   wire width 1 \exp_n126
8961   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
8962   wire width 1 \m_msbzero
8963   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
8964   wire width 1 $9
8965   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
8966   cell $and $10
8967     parameter \A_SIGNED 1'0
8968     parameter \A_WIDTH 1'1
8969     parameter \B_SIGNED 1'0
8970     parameter \B_WIDTH 1'1
8971     parameter \Y_WIDTH 1'1
8972     connect \A \exp_n126
8973     connect \B \m_msbzero
8974     connect \Y $9
8975   end
8976   process $group_4
8977     assign \is_denormalised 1'0
8978     assign \is_denormalised $9
8979     sync init
8980   end
8981   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
8982   wire width 1 $11
8983   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
8984   cell $eq $12
8985     parameter \A_SIGNED 1'1
8986     parameter \A_WIDTH 4'1101
8987     parameter \B_SIGNED 1'1
8988     parameter \B_WIDTH 4'1101
8989     parameter \Y_WIDTH 1'1
8990     connect \A \z_e
8991     connect \B 13'0010000000000
8992     connect \Y $11
8993   end
8994   process $group_5
8995     assign \exp_128 1'0
8996     assign \exp_128 $11
8997     sync init
8998   end
8999   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
9000   wire width 13 \exp_sub_n126
9001   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
9002   wire width 14 $13
9003   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
9004   wire width 14 $14
9005   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
9006   cell $sub $15
9007     parameter \A_SIGNED 1'1
9008     parameter \A_WIDTH 4'1101
9009     parameter \B_SIGNED 1'1
9010     parameter \B_WIDTH 4'1101
9011     parameter \Y_WIDTH 4'1110
9012     connect \A \z_e
9013     connect \B 13'1110000000010
9014     connect \Y $14
9015   end
9016   connect $13 $14
9017   process $group_6
9018     assign \exp_sub_n126 13'0000000000000
9019     assign \exp_sub_n126 $13 [12:0]
9020     sync init
9021   end
9022   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
9023   wire width 1 \exp_gt_n126
9024   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
9025   wire width 1 $16
9026   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
9027   cell $gt $17
9028     parameter \A_SIGNED 1'1
9029     parameter \A_WIDTH 4'1101
9030     parameter \B_SIGNED 1'1
9031     parameter \B_WIDTH 4'1101
9032     parameter \Y_WIDTH 1'1
9033     connect \A \exp_sub_n126
9034     connect \B 13'0000000000000
9035     connect \Y $16
9036   end
9037   process $group_7
9038     assign \exp_gt_n126 1'0
9039     assign \exp_gt_n126 $16
9040     sync init
9041   end
9042   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
9043   wire width 1 \exp_lt_n126
9044   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
9045   wire width 1 $18
9046   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
9047   cell $lt $19
9048     parameter \A_SIGNED 1'1
9049     parameter \A_WIDTH 4'1101
9050     parameter \B_SIGNED 1'1
9051     parameter \B_WIDTH 4'1101
9052     parameter \Y_WIDTH 1'1
9053     connect \A \exp_sub_n126
9054     connect \B 13'0000000000000
9055     connect \Y $18
9056   end
9057   process $group_8
9058     assign \exp_lt_n126 1'0
9059     assign \exp_lt_n126 $18
9060     sync init
9061   end
9062   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
9063   wire width 1 \exp_zero
9064   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
9065   wire width 1 $20
9066   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
9067   cell $eq $21
9068     parameter \A_SIGNED 1'1
9069     parameter \A_WIDTH 4'1101
9070     parameter \B_SIGNED 1'1
9071     parameter \B_WIDTH 4'1101
9072     parameter \Y_WIDTH 1'1
9073     connect \A \z_e
9074     connect \B 13'0000000000000
9075     connect \Y $20
9076   end
9077   process $group_9
9078     assign \exp_zero 1'0
9079     assign \exp_zero $20
9080     sync init
9081   end
9082   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
9083   wire width 1 $22
9084   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
9085   cell $gt $23
9086     parameter \A_SIGNED 1'1
9087     parameter \A_WIDTH 4'1101
9088     parameter \B_SIGNED 1'1
9089     parameter \B_WIDTH 4'1101
9090     parameter \Y_WIDTH 1'1
9091     connect \A \z_e
9092     connect \B 13'0001111111111
9093     connect \Y $22
9094   end
9095   process $group_10
9096     assign \exp_gt127 1'0
9097     assign \exp_gt127 $22
9098     sync init
9099   end
9100   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
9101   wire width 1 $24
9102   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
9103   cell $eq $25
9104     parameter \A_SIGNED 1'1
9105     parameter \A_WIDTH 4'1101
9106     parameter \B_SIGNED 1'1
9107     parameter \B_WIDTH 4'1101
9108     parameter \Y_WIDTH 1'1
9109     connect \A \z_e
9110     connect \B 13'1110000000001
9111     connect \Y $24
9112   end
9113   process $group_11
9114     assign \exp_n127 1'0
9115     assign \exp_n127 $24
9116     sync init
9117   end
9118   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
9119   wire width 1 $26
9120   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
9121   cell $eq $27
9122     parameter \A_SIGNED 1'1
9123     parameter \A_WIDTH 4'1101
9124     parameter \B_SIGNED 1'1
9125     parameter \B_WIDTH 4'1101
9126     parameter \Y_WIDTH 1'1
9127     connect \A \z_e
9128     connect \B 13'1110000000010
9129     connect \Y $26
9130   end
9131   process $group_12
9132     assign \exp_n126 1'0
9133     assign \exp_n126 $26
9134     sync init
9135   end
9136   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
9137   wire width 1 $28
9138   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
9139   cell $eq $29
9140     parameter \A_SIGNED 1'0
9141     parameter \A_WIDTH 6'110101
9142     parameter \B_SIGNED 1'0
9143     parameter \B_WIDTH 6'110101
9144     parameter \Y_WIDTH 1'1
9145     connect \A \z_m
9146     connect \B 53'00000000000000000000000000000000000000000000000000000
9147     connect \Y $28
9148   end
9149   process $group_13
9150     assign \m_zero 1'0
9151     assign \m_zero $28
9152     sync init
9153   end
9154   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
9155   wire width 1 $30
9156   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
9157   cell $eq $31
9158     parameter \A_SIGNED 1'0
9159     parameter \A_WIDTH 1'1
9160     parameter \B_SIGNED 1'0
9161     parameter \B_WIDTH 1'1
9162     parameter \Y_WIDTH 1'1
9163     connect \A \z_m [52]
9164     connect \B 1'0
9165     connect \Y $30
9166   end
9167   process $group_14
9168     assign \m_msbzero 1'0
9169     assign \m_msbzero $30
9170     sync init
9171   end
9172 end
9173 attribute \generator "nMigen"
9174 attribute \nmigen.hierarchy "top.alu.normpack.corrections"
9175 module \corrections
9176   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9177   wire width 1 input 0 \z_s
9178   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9179   wire width 13 input 1 \z_e
9180   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9181   wire width 53 input 2 \z_m
9182   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
9183   wire width 1 input 3 \out_do_z
9184   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
9185   wire width 64 input 4 \oz
9186   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9187   wire width 2 input 5 \muxid
9188   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9189   wire width 0 input 6 \op
9190   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9191   wire width 1 output 7 \z_s__1
9192   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9193   wire width 13 output 8 \z_e__2
9194   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9195   wire width 53 output 9 \z_m__3
9196   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
9197   wire width 1 output 10 \out_do_z__4
9198   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
9199   wire width 64 output 11 \oz__5
9200   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9201   wire width 2 output 12 \muxid__6
9202   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9203   wire width 0 output 13 \op__7
9204   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
9205   wire width 1 \corr_in_z_is_denormalised
9206   cell \corr_in_z \corr_in_z
9207     connect \z_e \z_e
9208     connect \z_m \z_m
9209     connect \is_denormalised \corr_in_z_is_denormalised
9210   end
9211   process $group_0
9212     assign \z_s__1 1'0
9213     assign \z_s__1 \z_s
9214     sync init
9215   end
9216   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/corrections.py:30"
9217   wire width 13 $8
9218   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/corrections.py:30"
9219   cell $mux $9
9220     parameter \WIDTH 4'1101
9221     connect \A \z_e
9222     connect \B 13'1110000000001
9223     connect \S \corr_in_z_is_denormalised
9224     connect \Y $8
9225   end
9226   process $group_1
9227     assign \z_e__2 13'0000000000000
9228     assign \z_e__2 \z_e
9229     assign \z_e__2 $8
9230     sync init
9231   end
9232   process $group_2
9233     assign \z_m__3 53'00000000000000000000000000000000000000000000000000000
9234     assign \z_m__3 \z_m
9235     sync init
9236   end
9237   process $group_3
9238     assign \out_do_z__4 1'0
9239     assign \out_do_z__4 \out_do_z
9240     sync init
9241   end
9242   process $group_4
9243     assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000
9244     assign \oz__5 \oz
9245     sync init
9246   end
9247   process $group_5
9248     assign \muxid__6 2'00
9249     assign \muxid__6 \muxid
9250     sync init
9251   end
9252   process $group_6
9253     assign \op__7 0'0
9254     assign \op__7 \op
9255     sync init
9256   end
9257   connect \op__7 0'0
9258 end
9259 attribute \generator "nMigen"
9260 attribute \nmigen.hierarchy "top.alu.normpack.pack.pack_in_z"
9261 module \pack_in_z
9262   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9263   wire width 13 input 0 \z_e
9264   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9265   wire width 53 input 1 \z_m
9266   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
9267   wire width 1 output 2 \is_overflowed
9268   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471"
9269   wire width 1 \is_nan
9270   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476"
9271   wire width 1 \exp_128
9272   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
9273   wire width 1 $1
9274   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484"
9275   wire width 1 \m_zero
9276   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
9277   cell $not $2
9278     parameter \A_SIGNED 1'0
9279     parameter \A_WIDTH 1'1
9280     parameter \Y_WIDTH 1'1
9281     connect \A \m_zero
9282     connect \Y $1
9283   end
9284   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
9285   wire width 1 $3
9286   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508"
9287   cell $and $4
9288     parameter \A_SIGNED 1'0
9289     parameter \A_WIDTH 1'1
9290     parameter \B_SIGNED 1'0
9291     parameter \B_WIDTH 1'1
9292     parameter \Y_WIDTH 1'1
9293     connect \A \exp_128
9294     connect \B $1
9295     connect \Y $3
9296   end
9297   process $group_0
9298     assign \is_nan 1'0
9299     assign \is_nan $3
9300     sync init
9301   end
9302   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472"
9303   wire width 1 \is_zero
9304   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482"
9305   wire width 1 \exp_n127
9306   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
9307   wire width 1 $5
9308   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514"
9309   cell $and $6
9310     parameter \A_SIGNED 1'0
9311     parameter \A_WIDTH 1'1
9312     parameter \B_SIGNED 1'0
9313     parameter \B_WIDTH 1'1
9314     parameter \Y_WIDTH 1'1
9315     connect \A \exp_n127
9316     connect \B \m_zero
9317     connect \Y $5
9318   end
9319   process $group_1
9320     assign \is_zero 1'0
9321     assign \is_zero $5
9322     sync init
9323   end
9324   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473"
9325   wire width 1 \is_inf
9326   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
9327   wire width 1 $7
9328   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511"
9329   cell $and $8
9330     parameter \A_SIGNED 1'0
9331     parameter \A_WIDTH 1'1
9332     parameter \B_SIGNED 1'0
9333     parameter \B_WIDTH 1'1
9334     parameter \Y_WIDTH 1'1
9335     connect \A \exp_128
9336     connect \B \m_zero
9337     connect \Y $7
9338   end
9339   process $group_2
9340     assign \is_inf 1'0
9341     assign \is_inf $7
9342     sync init
9343   end
9344   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481"
9345   wire width 1 \exp_gt127
9346   process $group_3
9347     assign \is_overflowed 1'0
9348     assign \is_overflowed \exp_gt127
9349     sync init
9350   end
9351   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475"
9352   wire width 1 \is_denormalised
9353   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483"
9354   wire width 1 \exp_n126
9355   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485"
9356   wire width 1 \m_msbzero
9357   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
9358   wire width 1 $9
9359   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522"
9360   cell $and $10
9361     parameter \A_SIGNED 1'0
9362     parameter \A_WIDTH 1'1
9363     parameter \B_SIGNED 1'0
9364     parameter \B_WIDTH 1'1
9365     parameter \Y_WIDTH 1'1
9366     connect \A \exp_n126
9367     connect \B \m_msbzero
9368     connect \Y $9
9369   end
9370   process $group_4
9371     assign \is_denormalised 1'0
9372     assign \is_denormalised $9
9373     sync init
9374   end
9375   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
9376   wire width 1 $11
9377   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494"
9378   cell $eq $12
9379     parameter \A_SIGNED 1'1
9380     parameter \A_WIDTH 4'1101
9381     parameter \B_SIGNED 1'1
9382     parameter \B_WIDTH 4'1101
9383     parameter \Y_WIDTH 1'1
9384     connect \A \z_e
9385     connect \B 13'0010000000000
9386     connect \Y $11
9387   end
9388   process $group_5
9389     assign \exp_128 1'0
9390     assign \exp_128 $11
9391     sync init
9392   end
9393   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477"
9394   wire width 13 \exp_sub_n126
9395   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
9396   wire width 14 $13
9397   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
9398   wire width 14 $14
9399   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495"
9400   cell $sub $15
9401     parameter \A_SIGNED 1'1
9402     parameter \A_WIDTH 4'1101
9403     parameter \B_SIGNED 1'1
9404     parameter \B_WIDTH 4'1101
9405     parameter \Y_WIDTH 4'1110
9406     connect \A \z_e
9407     connect \B 13'1110000000010
9408     connect \Y $14
9409   end
9410   connect $13 $14
9411   process $group_6
9412     assign \exp_sub_n126 13'0000000000000
9413     assign \exp_sub_n126 $13 [12:0]
9414     sync init
9415   end
9416   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480"
9417   wire width 1 \exp_gt_n126
9418   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
9419   wire width 1 $16
9420   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496"
9421   cell $gt $17
9422     parameter \A_SIGNED 1'1
9423     parameter \A_WIDTH 4'1101
9424     parameter \B_SIGNED 1'1
9425     parameter \B_WIDTH 4'1101
9426     parameter \Y_WIDTH 1'1
9427     connect \A \exp_sub_n126
9428     connect \B 13'0000000000000
9429     connect \Y $16
9430   end
9431   process $group_7
9432     assign \exp_gt_n126 1'0
9433     assign \exp_gt_n126 $16
9434     sync init
9435   end
9436   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478"
9437   wire width 1 \exp_lt_n126
9438   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
9439   wire width 1 $18
9440   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497"
9441   cell $lt $19
9442     parameter \A_SIGNED 1'1
9443     parameter \A_WIDTH 4'1101
9444     parameter \B_SIGNED 1'1
9445     parameter \B_WIDTH 4'1101
9446     parameter \Y_WIDTH 1'1
9447     connect \A \exp_sub_n126
9448     connect \B 13'0000000000000
9449     connect \Y $18
9450   end
9451   process $group_8
9452     assign \exp_lt_n126 1'0
9453     assign \exp_lt_n126 $18
9454     sync init
9455   end
9456   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479"
9457   wire width 1 \exp_zero
9458   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
9459   wire width 1 $20
9460   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498"
9461   cell $eq $21
9462     parameter \A_SIGNED 1'1
9463     parameter \A_WIDTH 4'1101
9464     parameter \B_SIGNED 1'1
9465     parameter \B_WIDTH 4'1101
9466     parameter \Y_WIDTH 1'1
9467     connect \A \z_e
9468     connect \B 13'0000000000000
9469     connect \Y $20
9470   end
9471   process $group_9
9472     assign \exp_zero 1'0
9473     assign \exp_zero $20
9474     sync init
9475   end
9476   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
9477   wire width 1 $22
9478   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499"
9479   cell $gt $23
9480     parameter \A_SIGNED 1'1
9481     parameter \A_WIDTH 4'1101
9482     parameter \B_SIGNED 1'1
9483     parameter \B_WIDTH 4'1101
9484     parameter \Y_WIDTH 1'1
9485     connect \A \z_e
9486     connect \B 13'0001111111111
9487     connect \Y $22
9488   end
9489   process $group_10
9490     assign \exp_gt127 1'0
9491     assign \exp_gt127 $22
9492     sync init
9493   end
9494   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
9495   wire width 1 $24
9496   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500"
9497   cell $eq $25
9498     parameter \A_SIGNED 1'1
9499     parameter \A_WIDTH 4'1101
9500     parameter \B_SIGNED 1'1
9501     parameter \B_WIDTH 4'1101
9502     parameter \Y_WIDTH 1'1
9503     connect \A \z_e
9504     connect \B 13'1110000000001
9505     connect \Y $24
9506   end
9507   process $group_11
9508     assign \exp_n127 1'0
9509     assign \exp_n127 $24
9510     sync init
9511   end
9512   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
9513   wire width 1 $26
9514   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501"
9515   cell $eq $27
9516     parameter \A_SIGNED 1'1
9517     parameter \A_WIDTH 4'1101
9518     parameter \B_SIGNED 1'1
9519     parameter \B_WIDTH 4'1101
9520     parameter \Y_WIDTH 1'1
9521     connect \A \z_e
9522     connect \B 13'1110000000010
9523     connect \Y $26
9524   end
9525   process $group_12
9526     assign \exp_n126 1'0
9527     assign \exp_n126 $26
9528     sync init
9529   end
9530   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
9531   wire width 1 $28
9532   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502"
9533   cell $eq $29
9534     parameter \A_SIGNED 1'0
9535     parameter \A_WIDTH 6'110101
9536     parameter \B_SIGNED 1'0
9537     parameter \B_WIDTH 6'110101
9538     parameter \Y_WIDTH 1'1
9539     connect \A \z_m
9540     connect \B 53'00000000000000000000000000000000000000000000000000000
9541     connect \Y $28
9542   end
9543   process $group_13
9544     assign \m_zero 1'0
9545     assign \m_zero $28
9546     sync init
9547   end
9548   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
9549   wire width 1 $30
9550   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503"
9551   cell $eq $31
9552     parameter \A_SIGNED 1'0
9553     parameter \A_WIDTH 1'1
9554     parameter \B_SIGNED 1'0
9555     parameter \B_WIDTH 1'1
9556     parameter \Y_WIDTH 1'1
9557     connect \A \z_m [52]
9558     connect \B 1'0
9559     connect \Y $30
9560   end
9561   process $group_14
9562     assign \m_msbzero 1'0
9563     assign \m_msbzero $30
9564     sync init
9565   end
9566 end
9567 attribute \generator "nMigen"
9568 attribute \nmigen.hierarchy "top.alu.normpack.pack"
9569 module \pack
9570   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9571   wire width 1 input 0 \z_s
9572   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9573   wire width 13 input 1 \z_e
9574   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9575   wire width 53 input 2 \z_m
9576   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
9577   wire width 1 input 3 \out_do_z
9578   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
9579   wire width 64 input 4 \oz
9580   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9581   wire width 2 input 5 \muxid
9582   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9583   wire width 0 input 6 \op
9584   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
9585   wire width 64 output 7 \z
9586   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9587   wire width 2 output 8 \muxid__1
9588   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9589   wire width 0 output 9 \op__2
9590   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474"
9591   wire width 1 \pack_in_z_is_overflowed
9592   cell \pack_in_z \pack_in_z
9593     connect \z_e \z_e
9594     connect \z_m \z_m
9595     connect \is_overflowed \pack_in_z_is_overflowed
9596   end
9597   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366"
9598   wire width 64 \z_v
9599   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33"
9600   wire width 1 $3
9601   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33"
9602   cell $not $4
9603     parameter \A_SIGNED 1'0
9604     parameter \A_WIDTH 1'1
9605     parameter \Y_WIDTH 1'1
9606     connect \A \out_do_z
9607     connect \Y $3
9608   end
9609   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
9610   wire width 14 $5
9611   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
9612   wire width 14 $6
9613   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
9614   cell $add $7
9615     parameter \A_SIGNED 1'1
9616     parameter \A_WIDTH 4'1101
9617     parameter \B_SIGNED 1'1
9618     parameter \B_WIDTH 4'1101
9619     parameter \Y_WIDTH 4'1110
9620     connect \A 13'0010000000000
9621     connect \B 13'0001111111111
9622     connect \Y $6
9623   end
9624   connect $5 $6
9625   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
9626   wire width 14 $8
9627   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
9628   wire width 14 $9
9629   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412"
9630   cell $add $10
9631     parameter \A_SIGNED 1'1
9632     parameter \A_WIDTH 4'1101
9633     parameter \B_SIGNED 1'1
9634     parameter \B_WIDTH 4'1101
9635     parameter \Y_WIDTH 4'1110
9636     connect \A \z_e
9637     connect \B 13'0001111111111
9638     connect \Y $9
9639   end
9640   connect $8 $9
9641   process $group_0
9642     assign \z_v 64'0000000000000000000000000000000000000000000000000000000000000000
9643     attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33"
9644     switch { $3 }
9645       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33"
9646       case 1'1
9647         attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:34"
9648         switch { \pack_in_z_is_overflowed }
9649           attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:34"
9650           case 1'1
9651             assign \z_v [51:0] 52'0000000000000000000000000000000000000000000000000000
9652             assign \z_v [62:52] $5 [10:0]
9653             assign \z_v [63] \z_s
9654           attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:36"
9655           case
9656             assign \z_v [51:0] \z_m [51:0]
9657             assign \z_v [62:52] $8 [10:0]
9658             assign \z_v [63] \z_s
9659         end
9660       attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:38"
9661       case
9662         assign \z_v \oz
9663     end
9664     sync init
9665   end
9666   process $group_1
9667     assign \muxid__1 2'00
9668     assign \muxid__1 \muxid
9669     sync init
9670   end
9671   process $group_2
9672     assign \op__2 0'0
9673     assign \op__2 \op
9674     sync init
9675   end
9676   process $group_3
9677     assign \z 64'0000000000000000000000000000000000000000000000000000000000000000
9678     assign \z \z_v
9679     sync init
9680   end
9681   connect \op__2 0'0
9682 end
9683 attribute \generator "nMigen"
9684 attribute \nmigen.hierarchy "top.alu.normpack"
9685 module \normpack
9686   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
9687   wire width 1 input 0 \p_valid_i
9688   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
9689   wire width 1 output 1 \p_ready_o
9690   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9691   wire width 1 input 2 \z_s
9692   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9693   wire width 13 input 3 \z_e
9694   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9695   wire width 53 input 4 \z_m
9696   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
9697   wire width 1 input 5 \out_do_z
9698   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
9699   wire width 64 input 6 \oz
9700   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
9701   wire width 1 input 7 \guard
9702   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
9703   wire width 1 input 8 \round
9704   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
9705   wire width 1 input 9 \sticky
9706   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
9707   wire width 1 input 10 \m0
9708   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
9709   wire width 5 input 11 \fflags
9710   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9711   wire width 2 input 12 \muxid
9712   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9713   wire width 0 input 13 \op
9714   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
9715   wire width 1 output 14 \n_valid_o
9716   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
9717   wire width 1 input 15 \n_ready_i
9718   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
9719   wire width 64 output 16 \z
9720   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
9721   wire width 64 \z$next
9722   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9723   wire width 2 output 17 \muxid__1
9724   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9725   wire width 2 \muxid__1$next
9726   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9727   wire width 0 output 18 \op__2
9728   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9729   wire width 0 \op__2$next
9730   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
9731   wire width 1 input 19 \rst
9732   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
9733   wire width 1 input 20 \clk
9734   cell \p__7 \p
9735     connect \p_valid_i \p_valid_i
9736     connect \p_ready_o \p_ready_o
9737   end
9738   cell \n__8 \n
9739     connect \n_valid_o \n_valid_o
9740     connect \n_ready_i \n_ready_i
9741   end
9742   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9743   wire width 1 \normalise_1_z_s
9744   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9745   wire width 13 \normalise_1_z_e
9746   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9747   wire width 53 \normalise_1_z_m
9748   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
9749   wire width 1 \normalise_1_out_do_z
9750   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
9751   wire width 64 \normalise_1_oz
9752   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
9753   wire width 1 \normalise_1_guard
9754   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
9755   wire width 1 \normalise_1_round
9756   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
9757   wire width 1 \normalise_1_sticky
9758   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
9759   wire width 1 \normalise_1_m0
9760   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
9761   wire width 5 \normalise_1_fflags
9762   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9763   wire width 2 \normalise_1_muxid
9764   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9765   wire width 0 \normalise_1_op
9766   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9767   wire width 1 \normalise_1_z_s__3
9768   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9769   wire width 13 \normalise_1_z_e__4
9770   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9771   wire width 53 \normalise_1_z_m__5
9772   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:25"
9773   wire width 1 \normalise_1_out_do_z__6
9774   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:26"
9775   wire width 64 \normalise_1_oz__7
9776   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:23"
9777   wire width 1 \normalise_1_norm1_roundz
9778   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9779   wire width 2 \normalise_1_muxid__8
9780   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9781   wire width 0 \normalise_1_op__9
9782   cell \normalise_1 \normalise_1
9783     connect \z_s \normalise_1_z_s
9784     connect \z_e \normalise_1_z_e
9785     connect \z_m \normalise_1_z_m
9786     connect \out_do_z \normalise_1_out_do_z
9787     connect \oz \normalise_1_oz
9788     connect \guard \normalise_1_guard
9789     connect \round \normalise_1_round
9790     connect \sticky \normalise_1_sticky
9791     connect \m0 \normalise_1_m0
9792     connect \fflags \normalise_1_fflags
9793     connect \muxid \normalise_1_muxid
9794     connect \op \normalise_1_op
9795     connect \z_s__1 \normalise_1_z_s__3
9796     connect \z_e__2 \normalise_1_z_e__4
9797     connect \z_m__3 \normalise_1_z_m__5
9798     connect \out_do_z__4 \normalise_1_out_do_z__6
9799     connect \oz__5 \normalise_1_oz__7
9800     connect \norm1_roundz \normalise_1_norm1_roundz
9801     connect \muxid__6 \normalise_1_muxid__8
9802     connect \op__7 \normalise_1_op__9
9803   end
9804   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9805   wire width 1 \roundz_z_s
9806   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9807   wire width 13 \roundz_z_e
9808   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9809   wire width 53 \roundz_z_m
9810   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:25"
9811   wire width 1 \roundz_out_do_z
9812   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:26"
9813   wire width 64 \roundz_oz
9814   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:23"
9815   wire width 1 \roundz_norm1_roundz
9816   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9817   wire width 2 \roundz_muxid
9818   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9819   wire width 0 \roundz_op
9820   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9821   wire width 1 \roundz_z_s__10
9822   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9823   wire width 13 \roundz_z_e__11
9824   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9825   wire width 53 \roundz_z_m__12
9826   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
9827   wire width 1 \roundz_out_do_z__13
9828   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
9829   wire width 64 \roundz_oz__14
9830   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9831   wire width 2 \roundz_muxid__15
9832   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9833   wire width 0 \roundz_op__16
9834   cell \roundz \roundz
9835     connect \z_s \roundz_z_s
9836     connect \z_e \roundz_z_e
9837     connect \z_m \roundz_z_m
9838     connect \out_do_z \roundz_out_do_z
9839     connect \oz \roundz_oz
9840     connect \norm1_roundz \roundz_norm1_roundz
9841     connect \muxid \roundz_muxid
9842     connect \op \roundz_op
9843     connect \z_s__1 \roundz_z_s__10
9844     connect \z_e__2 \roundz_z_e__11
9845     connect \z_m__3 \roundz_z_m__12
9846     connect \out_do_z__4 \roundz_out_do_z__13
9847     connect \oz__5 \roundz_oz__14
9848     connect \muxid__6 \roundz_muxid__15
9849     connect \op__7 \roundz_op__16
9850   end
9851   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9852   wire width 1 \corrections_z_s
9853   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9854   wire width 13 \corrections_z_e
9855   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9856   wire width 53 \corrections_z_m
9857   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
9858   wire width 1 \corrections_out_do_z
9859   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
9860   wire width 64 \corrections_oz
9861   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9862   wire width 2 \corrections_muxid
9863   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9864   wire width 0 \corrections_op
9865   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9866   wire width 1 \corrections_z_s__17
9867   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9868   wire width 13 \corrections_z_e__18
9869   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9870   wire width 53 \corrections_z_m__19
9871   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
9872   wire width 1 \corrections_out_do_z__20
9873   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
9874   wire width 64 \corrections_oz__21
9875   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9876   wire width 2 \corrections_muxid__22
9877   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9878   wire width 0 \corrections_op__23
9879   cell \corrections \corrections
9880     connect \z_s \corrections_z_s
9881     connect \z_e \corrections_z_e
9882     connect \z_m \corrections_z_m
9883     connect \out_do_z \corrections_out_do_z
9884     connect \oz \corrections_oz
9885     connect \muxid \corrections_muxid
9886     connect \op \corrections_op
9887     connect \z_s__1 \corrections_z_s__17
9888     connect \z_e__2 \corrections_z_e__18
9889     connect \z_m__3 \corrections_z_m__19
9890     connect \out_do_z__4 \corrections_out_do_z__20
9891     connect \oz__5 \corrections_oz__21
9892     connect \muxid__6 \corrections_muxid__22
9893     connect \op__7 \corrections_op__23
9894   end
9895   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
9896   wire width 1 \pack_z_s
9897   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
9898   wire width 13 \pack_z_e
9899   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
9900   wire width 53 \pack_z_m
9901   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22"
9902   wire width 1 \pack_out_do_z
9903   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23"
9904   wire width 64 \pack_oz
9905   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9906   wire width 2 \pack_muxid
9907   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9908   wire width 0 \pack_op
9909   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
9910   wire width 64 \pack_z
9911   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
9912   wire width 2 \pack_muxid__24
9913   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
9914   wire width 0 \pack_op__25
9915   cell \pack \pack
9916     connect \z_s \pack_z_s
9917     connect \z_e \pack_z_e
9918     connect \z_m \pack_z_m
9919     connect \out_do_z \pack_out_do_z
9920     connect \oz \pack_oz
9921     connect \muxid \pack_muxid
9922     connect \op \pack_op
9923     connect \z \pack_z
9924     connect \muxid__1 \pack_muxid__24
9925     connect \op__2 \pack_op__25
9926   end
9927   process $group_0
9928     assign \normalise_1_z_s 1'0
9929     assign \normalise_1_z_s \z_s
9930     sync init
9931   end
9932   process $group_1
9933     assign \normalise_1_z_e 13'0000000000000
9934     assign \normalise_1_z_e \z_e
9935     sync init
9936   end
9937   process $group_2
9938     assign \normalise_1_z_m 53'00000000000000000000000000000000000000000000000000000
9939     assign \normalise_1_z_m \z_m
9940     sync init
9941   end
9942   process $group_3
9943     assign \normalise_1_out_do_z 1'0
9944     assign \normalise_1_out_do_z \out_do_z
9945     sync init
9946   end
9947   process $group_4
9948     assign \normalise_1_oz 64'0000000000000000000000000000000000000000000000000000000000000000
9949     assign \normalise_1_oz \oz
9950     sync init
9951   end
9952   process $group_5
9953     assign \normalise_1_guard 1'0
9954     assign \normalise_1_guard \guard
9955     sync init
9956   end
9957   process $group_6
9958     assign \normalise_1_round 1'0
9959     assign \normalise_1_round \round
9960     sync init
9961   end
9962   process $group_7
9963     assign \normalise_1_sticky 1'0
9964     assign \normalise_1_sticky \sticky
9965     sync init
9966   end
9967   process $group_8
9968     assign \normalise_1_m0 1'0
9969     assign \normalise_1_m0 \m0
9970     sync init
9971   end
9972   process $group_9
9973     assign \normalise_1_fflags 5'00000
9974     assign \normalise_1_fflags \fflags
9975     sync init
9976   end
9977   process $group_10
9978     assign \normalise_1_muxid 2'00
9979     assign \normalise_1_muxid \muxid
9980     sync init
9981   end
9982   process $group_11
9983     assign \normalise_1_op 0'0
9984     assign \normalise_1_op \op
9985     sync init
9986   end
9987   process $group_12
9988     assign \roundz_z_s 1'0
9989     assign \roundz_z_s \normalise_1_z_s__3
9990     sync init
9991   end
9992   process $group_13
9993     assign \roundz_z_e 13'0000000000000
9994     assign \roundz_z_e \normalise_1_z_e__4
9995     sync init
9996   end
9997   process $group_14
9998     assign \roundz_z_m 53'00000000000000000000000000000000000000000000000000000
9999     assign \roundz_z_m \normalise_1_z_m__5
10000     sync init
10001   end
10002   process $group_15
10003     assign \roundz_out_do_z 1'0
10004     assign \roundz_out_do_z \normalise_1_out_do_z__6
10005     sync init
10006   end
10007   process $group_16
10008     assign \roundz_oz 64'0000000000000000000000000000000000000000000000000000000000000000
10009     assign \roundz_oz \normalise_1_oz__7
10010     sync init
10011   end
10012   process $group_17
10013     assign \roundz_norm1_roundz 1'0
10014     assign \roundz_norm1_roundz \normalise_1_norm1_roundz
10015     sync init
10016   end
10017   process $group_18
10018     assign \roundz_muxid 2'00
10019     assign \roundz_muxid \normalise_1_muxid__8
10020     sync init
10021   end
10022   process $group_19
10023     assign \roundz_op 0'0
10024     assign \roundz_op \normalise_1_op__9
10025     sync init
10026   end
10027   process $group_20
10028     assign \corrections_z_s 1'0
10029     assign \corrections_z_s \roundz_z_s__10
10030     sync init
10031   end
10032   process $group_21
10033     assign \corrections_z_e 13'0000000000000
10034     assign \corrections_z_e \roundz_z_e__11
10035     sync init
10036   end
10037   process $group_22
10038     assign \corrections_z_m 53'00000000000000000000000000000000000000000000000000000
10039     assign \corrections_z_m \roundz_z_m__12
10040     sync init
10041   end
10042   process $group_23
10043     assign \corrections_out_do_z 1'0
10044     assign \corrections_out_do_z \roundz_out_do_z__13
10045     sync init
10046   end
10047   process $group_24
10048     assign \corrections_oz 64'0000000000000000000000000000000000000000000000000000000000000000
10049     assign \corrections_oz \roundz_oz__14
10050     sync init
10051   end
10052   process $group_25
10053     assign \corrections_muxid 2'00
10054     assign \corrections_muxid \roundz_muxid__15
10055     sync init
10056   end
10057   process $group_26
10058     assign \corrections_op 0'0
10059     assign \corrections_op \roundz_op__16
10060     sync init
10061   end
10062   process $group_27
10063     assign \pack_z_s 1'0
10064     assign \pack_z_s \corrections_z_s__17
10065     sync init
10066   end
10067   process $group_28
10068     assign \pack_z_e 13'0000000000000
10069     assign \pack_z_e \corrections_z_e__18
10070     sync init
10071   end
10072   process $group_29
10073     assign \pack_z_m 53'00000000000000000000000000000000000000000000000000000
10074     assign \pack_z_m \corrections_z_m__19
10075     sync init
10076   end
10077   process $group_30
10078     assign \pack_out_do_z 1'0
10079     assign \pack_out_do_z \corrections_out_do_z__20
10080     sync init
10081   end
10082   process $group_31
10083     assign \pack_oz 64'0000000000000000000000000000000000000000000000000000000000000000
10084     assign \pack_oz \corrections_oz__21
10085     sync init
10086   end
10087   process $group_32
10088     assign \pack_muxid 2'00
10089     assign \pack_muxid \corrections_muxid__22
10090     sync init
10091   end
10092   process $group_33
10093     assign \pack_op 0'0
10094     assign \pack_op \corrections_op__23
10095     sync init
10096   end
10097   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:621"
10098   wire width 1 \p_valid_i__26
10099   process $group_34
10100     assign \p_valid_i__26 1'0
10101     assign \p_valid_i__26 \p_valid_i
10102     sync init
10103   end
10104   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:619"
10105   wire width 1 \n_i_rdy_data
10106   process $group_35
10107     assign \n_i_rdy_data 1'0
10108     assign \n_i_rdy_data \n_ready_i
10109     sync init
10110   end
10111   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:620"
10112   wire width 1 \p_valid_i_p_ready_o
10113   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624"
10114   wire width 1 $27
10115   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624"
10116   cell $and $28
10117     parameter \A_SIGNED 1'0
10118     parameter \A_WIDTH 1'1
10119     parameter \B_SIGNED 1'0
10120     parameter \B_WIDTH 1'1
10121     parameter \Y_WIDTH 1'1
10122     connect \A \p_valid_i__26
10123     connect \B \p_ready_o
10124     connect \Y $27
10125   end
10126   process $group_36
10127     assign \p_valid_i_p_ready_o 1'0
10128     assign \p_valid_i_p_ready_o $27
10129     sync init
10130   end
10131   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10132   wire width 64 \z__29
10133   process $group_37
10134     assign \z__29 64'0000000000000000000000000000000000000000000000000000000000000000
10135     assign \z__29 \pack_z
10136     sync init
10137   end
10138   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10139   wire width 2 \muxid__30
10140   process $group_38
10141     assign \muxid__30 2'00
10142     assign \muxid__30 \pack_muxid__24
10143     sync init
10144   end
10145   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10146   wire width 0 \op__31
10147   process $group_39
10148     assign \op__31 0'0
10149     assign \op__31 \pack_op__25
10150     sync init
10151   end
10152   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615"
10153   wire width 1 \r_busy
10154   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615"
10155   wire width 1 \r_busy$next
10156   process $group_40
10157     assign \r_busy$next \r_busy
10158     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10159     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
10160       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10161       case 2'-1
10162         assign \r_busy$next 1'1
10163       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
10164       case 2'1-
10165         assign \r_busy$next 1'0
10166     end
10167     attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/xfrm.py:528"
10168     switch \rst
10169       case 1'1
10170         assign \r_busy$next 1'0
10171     end
10172     sync init
10173       update \r_busy 1'0
10174     sync posedge \clk
10175       update \r_busy \r_busy$next
10176   end
10177   process $group_41
10178     assign \z$next \z
10179     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10180     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
10181       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10182       case 2'-1
10183         assign \z$next \z__29
10184       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
10185       case 2'1-
10186         assign \z$next \z__29
10187     end
10188     sync init
10189       update \z 64'0000000000000000000000000000000000000000000000000000000000000000
10190     sync posedge \clk
10191       update \z \z$next
10192   end
10193   process $group_42
10194     assign \muxid__1$next \muxid__1
10195     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10196     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
10197       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10198       case 2'-1
10199         assign \muxid__1$next \muxid__30
10200       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
10201       case 2'1-
10202         assign \muxid__1$next \muxid__30
10203     end
10204     sync init
10205       update \muxid__1 2'00
10206     sync posedge \clk
10207       update \muxid__1 \muxid__1$next
10208   end
10209   process $group_43
10210     assign \op__2$next \op__2
10211     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10212     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
10213       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631"
10214       case 2'-1
10215         assign \op__2$next \op__31
10216       attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637"
10217       case 2'1-
10218         assign \op__2$next \op__31
10219     end
10220     sync init
10221       update \op__2 0'0
10222     sync posedge \clk
10223       update \op__2 \op__2$next
10224   end
10225   process $group_44
10226     assign \n_valid_o 1'0
10227     assign \n_valid_o \r_busy
10228     sync init
10229   end
10230   process $group_45
10231     assign \p_ready_o 1'0
10232     assign \p_ready_o \n_i_rdy_data
10233     sync init
10234   end
10235   connect \op__2 0'0
10236   connect \normalise_1_op 0'0
10237   connect \roundz_op 0'0
10238   connect \corrections_op 0'0
10239   connect \pack_op 0'0
10240   connect \op__31 0'0
10241 end
10242 attribute \generator "nMigen"
10243 attribute \nmigen.hierarchy "top.alu"
10244 module \alu
10245   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
10246   wire width 1 input 0 \p_valid_i
10247   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
10248   wire width 1 output 1 \p_ready_o
10249   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
10250   wire width 64 input 2 \a
10251   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
10252   wire width 64 input 3 \b
10253   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
10254   wire width 64 input 4 \c
10255   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10256   wire width 2 input 5 \muxid
10257   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10258   wire width 0 input 6 \op
10259   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10260   wire width 1 output 7 \n_valid_o
10261   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10262   wire width 1 input 8 \n_ready_i
10263   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10264   wire width 64 output 9 \z
10265   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10266   wire width 2 output 10 \muxid__1
10267   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10268   wire width 0 output 11 \op__2
10269   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
10270   wire width 1 input 12 \rst
10271   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
10272   wire width 1 input 13 \clk
10273   cell \p \p
10274     connect \p_valid_i \p_valid_i
10275     connect \p_ready_o \p_ready_o
10276   end
10277   cell \n__1 \n
10278     connect \n_valid_o \n_valid_o
10279     connect \n_ready_i \n_ready_i
10280   end
10281   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10282   wire width 1 \scnorm_n_valid_o
10283   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10284   wire width 1 \scnorm_n_ready_i
10285   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10286   wire width 1 \scnorm_z_s
10287   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10288   wire width 13 \scnorm_z_e
10289   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10290   wire width 53 \scnorm_z_m
10291   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
10292   wire width 1 \scnorm_out_do_z
10293   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
10294   wire width 64 \scnorm_oz
10295   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10296   wire width 1 \scnorm_a_s
10297   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10298   wire width 13 \scnorm_a_e
10299   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10300   wire width 53 \scnorm_a_m
10301   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10302   wire width 1 \scnorm_b_s
10303   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10304   wire width 13 \scnorm_b_e
10305   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10306   wire width 53 \scnorm_b_m
10307   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10308   wire width 2 \scnorm_muxid
10309   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10310   wire width 0 \scnorm_op
10311   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
10312   wire width 1 \scnorm_p_valid_i
10313   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
10314   wire width 1 \scnorm_p_ready_o
10315   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
10316   wire width 64 \scnorm_a
10317   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
10318   wire width 64 \scnorm_b
10319   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
10320   wire width 64 \scnorm_c
10321   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10322   wire width 2 \scnorm_muxid__3
10323   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10324   wire width 0 \scnorm_op__4
10325   cell \scnorm \scnorm
10326     connect \n_valid_o \scnorm_n_valid_o
10327     connect \n_ready_i \scnorm_n_ready_i
10328     connect \z_s \scnorm_z_s
10329     connect \z_e \scnorm_z_e
10330     connect \z_m \scnorm_z_m
10331     connect \out_do_z \scnorm_out_do_z
10332     connect \oz \scnorm_oz
10333     connect \a_s \scnorm_a_s
10334     connect \a_e \scnorm_a_e
10335     connect \a_m \scnorm_a_m
10336     connect \b_s \scnorm_b_s
10337     connect \b_e \scnorm_b_e
10338     connect \b_m \scnorm_b_m
10339     connect \muxid \scnorm_muxid
10340     connect \op \scnorm_op
10341     connect \p_valid_i \scnorm_p_valid_i
10342     connect \p_ready_o \scnorm_p_ready_o
10343     connect \a \scnorm_a
10344     connect \b \scnorm_b
10345     connect \c \scnorm_c
10346     connect \muxid__1 \scnorm_muxid__3
10347     connect \op__2 \scnorm_op__4
10348     connect \rst \rst
10349     connect \clk \clk
10350   end
10351   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
10352   wire width 1 \mulstages_p_valid_i
10353   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
10354   wire width 1 \mulstages_p_ready_o
10355   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10356   wire width 1 \mulstages_z_s
10357   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10358   wire width 13 \mulstages_z_e
10359   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10360   wire width 53 \mulstages_z_m
10361   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24"
10362   wire width 1 \mulstages_out_do_z
10363   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23"
10364   wire width 64 \mulstages_oz
10365   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10366   wire width 1 \mulstages_a_s
10367   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10368   wire width 13 \mulstages_a_e
10369   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10370   wire width 53 \mulstages_a_m
10371   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10372   wire width 1 \mulstages_b_s
10373   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10374   wire width 13 \mulstages_b_e
10375   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10376   wire width 53 \mulstages_b_m
10377   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10378   wire width 2 \mulstages_muxid
10379   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10380   wire width 0 \mulstages_op
10381   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10382   wire width 1 \mulstages_n_valid_o
10383   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10384   wire width 1 \mulstages_n_ready_i
10385   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10386   wire width 1 \mulstages_z_s__5
10387   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10388   wire width 13 \mulstages_z_e__6
10389   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10390   wire width 53 \mulstages_z_m__7
10391   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
10392   wire width 1 \mulstages_out_do_z__8
10393   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
10394   wire width 64 \mulstages_oz__9
10395   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
10396   wire width 1 \mulstages_guard
10397   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
10398   wire width 1 \mulstages_round
10399   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
10400   wire width 1 \mulstages_sticky
10401   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
10402   wire width 1 \mulstages_m0
10403   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
10404   wire width 5 \mulstages_fflags
10405   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10406   wire width 2 \mulstages_muxid__10
10407   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10408   wire width 0 \mulstages_op__11
10409   cell \mulstages \mulstages
10410     connect \p_valid_i \mulstages_p_valid_i
10411     connect \p_ready_o \mulstages_p_ready_o
10412     connect \z_s \mulstages_z_s
10413     connect \z_e \mulstages_z_e
10414     connect \z_m \mulstages_z_m
10415     connect \out_do_z \mulstages_out_do_z
10416     connect \oz \mulstages_oz
10417     connect \a_s \mulstages_a_s
10418     connect \a_e \mulstages_a_e
10419     connect \a_m \mulstages_a_m
10420     connect \b_s \mulstages_b_s
10421     connect \b_e \mulstages_b_e
10422     connect \b_m \mulstages_b_m
10423     connect \muxid \mulstages_muxid
10424     connect \op \mulstages_op
10425     connect \n_valid_o \mulstages_n_valid_o
10426     connect \n_ready_i \mulstages_n_ready_i
10427     connect \z_s__1 \mulstages_z_s__5
10428     connect \z_e__2 \mulstages_z_e__6
10429     connect \z_m__3 \mulstages_z_m__7
10430     connect \out_do_z__4 \mulstages_out_do_z__8
10431     connect \oz__5 \mulstages_oz__9
10432     connect \guard \mulstages_guard
10433     connect \round \mulstages_round
10434     connect \sticky \mulstages_sticky
10435     connect \m0 \mulstages_m0
10436     connect \fflags \mulstages_fflags
10437     connect \muxid__6 \mulstages_muxid__10
10438     connect \op__7 \mulstages_op__11
10439     connect \rst \rst
10440     connect \clk \clk
10441   end
10442   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
10443   wire width 1 \normpack_p_valid_i
10444   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
10445   wire width 1 \normpack_p_ready_o
10446   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370"
10447   wire width 1 \normpack_z_s
10448   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369"
10449   wire width 13 \normpack_z_e
10450   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367"
10451   wire width 53 \normpack_z_m
10452   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15"
10453   wire width 1 \normpack_out_do_z
10454   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16"
10455   wire width 64 \normpack_oz
10456   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889"
10457   wire width 1 \normpack_guard
10458   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890"
10459   wire width 1 \normpack_round
10460   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891"
10461   wire width 1 \normpack_sticky
10462   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892"
10463   wire width 1 \normpack_m0
10464   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893"
10465   wire width 5 \normpack_fflags
10466   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10467   wire width 2 \normpack_muxid
10468   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10469   wire width 0 \normpack_op
10470   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10471   wire width 1 \normpack_n_valid_o
10472   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10473   wire width 1 \normpack_n_ready_i
10474   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10475   wire width 64 \normpack_z
10476   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10477   wire width 2 \normpack_muxid__12
10478   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10479   wire width 0 \normpack_op__13
10480   cell \normpack \normpack
10481     connect \p_valid_i \normpack_p_valid_i
10482     connect \p_ready_o \normpack_p_ready_o
10483     connect \z_s \normpack_z_s
10484     connect \z_e \normpack_z_e
10485     connect \z_m \normpack_z_m
10486     connect \out_do_z \normpack_out_do_z
10487     connect \oz \normpack_oz
10488     connect \guard \normpack_guard
10489     connect \round \normpack_round
10490     connect \sticky \normpack_sticky
10491     connect \m0 \normpack_m0
10492     connect \fflags \normpack_fflags
10493     connect \muxid \normpack_muxid
10494     connect \op \normpack_op
10495     connect \n_valid_o \normpack_n_valid_o
10496     connect \n_ready_i \normpack_n_ready_i
10497     connect \z \normpack_z
10498     connect \muxid__1 \normpack_muxid__12
10499     connect \op__2 \normpack_op__13
10500     connect \rst \rst
10501     connect \clk \clk
10502   end
10503   process $group_0
10504     assign \mulstages_p_valid_i 1'0
10505     assign \mulstages_p_valid_i \scnorm_n_valid_o
10506     sync init
10507   end
10508   process $group_1
10509     assign \scnorm_n_ready_i 1'0
10510     assign \scnorm_n_ready_i \mulstages_p_ready_o
10511     sync init
10512   end
10513   process $group_2
10514     assign \mulstages_z_s 1'0
10515     assign \mulstages_z_s \scnorm_z_s
10516     sync init
10517   end
10518   process $group_3
10519     assign \mulstages_z_e 13'0000000000000
10520     assign \mulstages_z_e \scnorm_z_e
10521     sync init
10522   end
10523   process $group_4
10524     assign \mulstages_z_m 53'00000000000000000000000000000000000000000000000000000
10525     assign \mulstages_z_m \scnorm_z_m
10526     sync init
10527   end
10528   process $group_5
10529     assign \mulstages_out_do_z 1'0
10530     assign \mulstages_out_do_z \scnorm_out_do_z
10531     sync init
10532   end
10533   process $group_6
10534     assign \mulstages_oz 64'0000000000000000000000000000000000000000000000000000000000000000
10535     assign \mulstages_oz \scnorm_oz
10536     sync init
10537   end
10538   process $group_7
10539     assign \mulstages_a_s 1'0
10540     assign \mulstages_a_s \scnorm_a_s
10541     sync init
10542   end
10543   process $group_8
10544     assign \mulstages_a_e 13'0000000000000
10545     assign \mulstages_a_e \scnorm_a_e
10546     sync init
10547   end
10548   process $group_9
10549     assign \mulstages_a_m 53'00000000000000000000000000000000000000000000000000000
10550     assign \mulstages_a_m \scnorm_a_m
10551     sync init
10552   end
10553   process $group_10
10554     assign \mulstages_b_s 1'0
10555     assign \mulstages_b_s \scnorm_b_s
10556     sync init
10557   end
10558   process $group_11
10559     assign \mulstages_b_e 13'0000000000000
10560     assign \mulstages_b_e \scnorm_b_e
10561     sync init
10562   end
10563   process $group_12
10564     assign \mulstages_b_m 53'00000000000000000000000000000000000000000000000000000
10565     assign \mulstages_b_m \scnorm_b_m
10566     sync init
10567   end
10568   process $group_13
10569     assign \mulstages_muxid 2'00
10570     assign \mulstages_muxid \scnorm_muxid
10571     sync init
10572   end
10573   process $group_14
10574     assign \mulstages_op 0'0
10575     assign \mulstages_op \scnorm_op
10576     sync init
10577   end
10578   process $group_15
10579     assign \normpack_p_valid_i 1'0
10580     assign \normpack_p_valid_i \mulstages_n_valid_o
10581     sync init
10582   end
10583   process $group_16
10584     assign \mulstages_n_ready_i 1'0
10585     assign \mulstages_n_ready_i \normpack_p_ready_o
10586     sync init
10587   end
10588   process $group_17
10589     assign \normpack_z_s 1'0
10590     assign \normpack_z_s \mulstages_z_s__5
10591     sync init
10592   end
10593   process $group_18
10594     assign \normpack_z_e 13'0000000000000
10595     assign \normpack_z_e \mulstages_z_e__6
10596     sync init
10597   end
10598   process $group_19
10599     assign \normpack_z_m 53'00000000000000000000000000000000000000000000000000000
10600     assign \normpack_z_m \mulstages_z_m__7
10601     sync init
10602   end
10603   process $group_20
10604     assign \normpack_out_do_z 1'0
10605     assign \normpack_out_do_z \mulstages_out_do_z__8
10606     sync init
10607   end
10608   process $group_21
10609     assign \normpack_oz 64'0000000000000000000000000000000000000000000000000000000000000000
10610     assign \normpack_oz \mulstages_oz__9
10611     sync init
10612   end
10613   process $group_22
10614     assign \normpack_guard 1'0
10615     assign \normpack_guard \mulstages_guard
10616     sync init
10617   end
10618   process $group_23
10619     assign \normpack_round 1'0
10620     assign \normpack_round \mulstages_round
10621     sync init
10622   end
10623   process $group_24
10624     assign \normpack_sticky 1'0
10625     assign \normpack_sticky \mulstages_sticky
10626     sync init
10627   end
10628   process $group_25
10629     assign \normpack_m0 1'0
10630     assign \normpack_m0 \mulstages_m0
10631     sync init
10632   end
10633   process $group_26
10634     assign \normpack_fflags 5'00000
10635     assign \normpack_fflags \mulstages_fflags
10636     sync init
10637   end
10638   process $group_27
10639     assign \normpack_muxid 2'00
10640     assign \normpack_muxid \mulstages_muxid__10
10641     sync init
10642   end
10643   process $group_28
10644     assign \normpack_op 0'0
10645     assign \normpack_op \mulstages_op__11
10646     sync init
10647   end
10648   process $group_29
10649     assign \scnorm_p_valid_i 1'0
10650     assign \scnorm_p_valid_i \p_valid_i
10651     sync init
10652   end
10653   process $group_30
10654     assign \p_ready_o 1'0
10655     assign \p_ready_o \scnorm_p_ready_o
10656     sync init
10657   end
10658   process $group_31
10659     assign \scnorm_a 64'0000000000000000000000000000000000000000000000000000000000000000
10660     assign \scnorm_a \a
10661     sync init
10662   end
10663   process $group_32
10664     assign \scnorm_b 64'0000000000000000000000000000000000000000000000000000000000000000
10665     assign \scnorm_b \b
10666     sync init
10667   end
10668   process $group_33
10669     assign \scnorm_c 64'0000000000000000000000000000000000000000000000000000000000000000
10670     assign \scnorm_c \c
10671     sync init
10672   end
10673   process $group_34
10674     assign \scnorm_muxid__3 2'00
10675     assign \scnorm_muxid__3 \muxid
10676     sync init
10677   end
10678   process $group_35
10679     assign \scnorm_op__4 0'0
10680     assign \scnorm_op__4 \op
10681     sync init
10682   end
10683   process $group_36
10684     assign \n_valid_o 1'0
10685     assign \n_valid_o \normpack_n_valid_o
10686     sync init
10687   end
10688   process $group_37
10689     assign \normpack_n_ready_i 1'0
10690     assign \normpack_n_ready_i \n_ready_i
10691     sync init
10692   end
10693   process $group_38
10694     assign \z 64'0000000000000000000000000000000000000000000000000000000000000000
10695     assign \z \normpack_z
10696     sync init
10697   end
10698   process $group_39
10699     assign \muxid__1 2'00
10700     assign \muxid__1 \normpack_muxid__12
10701     sync init
10702   end
10703   process $group_40
10704     assign \op__2 0'0
10705     assign \op__2 \normpack_op__13
10706     sync init
10707   end
10708   connect \op__2 0'0
10709   connect \scnorm_op__4 0'0
10710   connect \mulstages_op 0'0
10711   connect \normpack_op 0'0
10712 end
10713 attribute \generator "nMigen"
10714 attribute \nmigen.hierarchy "top.outpipe.p"
10715 module \p__10
10716   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
10717   wire width 1 input 0 \p_valid_i
10718   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
10719   wire width 1 input 1 \p_ready_o
10720   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126"
10721   wire width 1 \trigger
10722   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
10723   wire width 1 $1
10724   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173"
10725   cell $and $2
10726     parameter \A_SIGNED 1'0
10727     parameter \A_WIDTH 1'1
10728     parameter \B_SIGNED 1'0
10729     parameter \B_WIDTH 1'1
10730     parameter \Y_WIDTH 1'1
10731     connect \A \p_valid_i
10732     connect \B \p_ready_o
10733     connect \Y $1
10734   end
10735   process $group_0
10736     assign \trigger 1'0
10737     assign \trigger $1
10738     sync init
10739   end
10740 end
10741 attribute \generator "nMigen"
10742 attribute \nmigen.hierarchy "top.outpipe.n0"
10743 module \n0
10744   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10745   wire width 1 input 0 \n_valid_o
10746   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10747   wire width 1 input 1 \n_ready_i
10748   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
10749   wire width 1 \trigger
10750   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10751   wire width 1 $1
10752   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10753   cell $and $2
10754     parameter \A_SIGNED 1'0
10755     parameter \A_WIDTH 1'1
10756     parameter \B_SIGNED 1'0
10757     parameter \B_WIDTH 1'1
10758     parameter \Y_WIDTH 1'1
10759     connect \A \n_ready_i
10760     connect \B \n_valid_o
10761     connect \Y $1
10762   end
10763   process $group_0
10764     assign \trigger 1'0
10765     assign \trigger $1
10766     sync init
10767   end
10768 end
10769 attribute \generator "nMigen"
10770 attribute \nmigen.hierarchy "top.outpipe.n1"
10771 module \n1
10772   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10773   wire width 1 input 0 \n_valid_o
10774   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10775   wire width 1 input 1 \n_ready_i
10776   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
10777   wire width 1 \trigger
10778   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10779   wire width 1 $1
10780   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10781   cell $and $2
10782     parameter \A_SIGNED 1'0
10783     parameter \A_WIDTH 1'1
10784     parameter \B_SIGNED 1'0
10785     parameter \B_WIDTH 1'1
10786     parameter \Y_WIDTH 1'1
10787     connect \A \n_ready_i
10788     connect \B \n_valid_o
10789     connect \Y $1
10790   end
10791   process $group_0
10792     assign \trigger 1'0
10793     assign \trigger $1
10794     sync init
10795   end
10796 end
10797 attribute \generator "nMigen"
10798 attribute \nmigen.hierarchy "top.outpipe.n2"
10799 module \n2
10800   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10801   wire width 1 input 0 \n_valid_o
10802   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10803   wire width 1 input 1 \n_ready_i
10804   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
10805   wire width 1 \trigger
10806   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10807   wire width 1 $1
10808   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10809   cell $and $2
10810     parameter \A_SIGNED 1'0
10811     parameter \A_WIDTH 1'1
10812     parameter \B_SIGNED 1'0
10813     parameter \B_WIDTH 1'1
10814     parameter \Y_WIDTH 1'1
10815     connect \A \n_ready_i
10816     connect \B \n_valid_o
10817     connect \Y $1
10818   end
10819   process $group_0
10820     assign \trigger 1'0
10821     assign \trigger $1
10822     sync init
10823   end
10824 end
10825 attribute \generator "nMigen"
10826 attribute \nmigen.hierarchy "top.outpipe.n3"
10827 module \n3
10828   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10829   wire width 1 input 0 \n_valid_o
10830   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10831   wire width 1 input 1 \n_ready_i
10832   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218"
10833   wire width 1 \trigger
10834   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10835   wire width 1 $1
10836   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264"
10837   cell $and $2
10838     parameter \A_SIGNED 1'0
10839     parameter \A_WIDTH 1'1
10840     parameter \B_SIGNED 1'0
10841     parameter \B_WIDTH 1'1
10842     parameter \Y_WIDTH 1'1
10843     connect \A \n_ready_i
10844     connect \B \n_valid_o
10845     connect \Y $1
10846   end
10847   process $group_0
10848     assign \trigger 1'0
10849     assign \trigger $1
10850     sync init
10851   end
10852 end
10853 attribute \generator "nMigen"
10854 attribute \nmigen.hierarchy "top.outpipe"
10855 module \outpipe
10856   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
10857   wire width 1 input 0 \p_valid_i
10858   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
10859   wire width 1 output 1 \p_ready_o
10860   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10861   wire width 64 input 2 \z
10862   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10863   wire width 2 input 3 \m_id
10864   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10865   wire width 0 input 4 \op
10866   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10867   wire width 1 output 5 \n_valid_o
10868   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10869   wire width 1 output 6 \n_valid_o__1
10870   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10871   wire width 1 output 7 \n_valid_o__2
10872   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
10873   wire width 1 output 8 \n_valid_o__3
10874   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10875   wire width 1 input 9 \n_ready_i
10876   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10877   wire width 1 input 10 \n_ready_i__4
10878   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10879   wire width 1 input 11 \n_ready_i__5
10880   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
10881   wire width 1 input 12 \n_ready_i__6
10882   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10883   wire width 64 output 13 \z__7
10884   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10885   wire width 64 output 14 \z__8
10886   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10887   wire width 64 output 15 \z__9
10888   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
10889   wire width 64 output 16 \z__10
10890   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10891   wire width 2 output 17 \muxid
10892   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10893   wire width 2 output 18 \muxid__11
10894   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10895   wire width 2 output 19 \muxid__12
10896   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
10897   wire width 2 output 20 \muxid__13
10898   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10899   wire width 0 output 21 \op__14
10900   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10901   wire width 0 output 22 \op__15
10902   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10903   wire width 0 output 23 \op__16
10904   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
10905   wire width 0 output 24 \op__17
10906   cell \p__10 \p
10907     connect \p_valid_i \p_valid_i
10908     connect \p_ready_o \p_ready_o
10909   end
10910   cell \n0 \n0
10911     connect \n_valid_o \n_valid_o
10912     connect \n_ready_i \n_ready_i
10913   end
10914   cell \n1 \n1
10915     connect \n_valid_o \n_valid_o__1
10916     connect \n_ready_i \n_ready_i__4
10917   end
10918   cell \n2 \n2
10919     connect \n_valid_o \n_valid_o__2
10920     connect \n_ready_i \n_ready_i__5
10921   end
10922   cell \n3 \n3
10923     connect \n_valid_o \n_valid_o__3
10924     connect \n_ready_i \n_ready_i__6
10925   end
10926   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:210"
10927   wire width 1 \p_valid_i__18
10928   process $group_0
10929     assign \p_valid_i__18 1'0
10930     assign \p_valid_i__18 \p_valid_i
10931     sync init
10932   end
10933   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:211"
10934   wire width 1 \pv
10935   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:214"
10936   wire width 1 $19
10937   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:214"
10938   cell $and $20
10939     parameter \A_SIGNED 1'0
10940     parameter \A_WIDTH 1'1
10941     parameter \B_SIGNED 1'0
10942     parameter \B_WIDTH 1'1
10943     parameter \Y_WIDTH 1'1
10944     connect \A \p_valid_i
10945     connect \B \p_ready_o
10946     connect \Y $19
10947   end
10948   process $group_1
10949     assign \pv 1'0
10950     assign \pv $19
10951     sync init
10952   end
10953   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10954   wire width 1 $21
10955   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10956   wire width 1 $22
10957   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10958   cell $not $23
10959     parameter \A_SIGNED 1'0
10960     parameter \A_WIDTH 1'1
10961     parameter \Y_WIDTH 1'1
10962     connect \A \n_ready_i
10963     connect \Y $22
10964   end
10965   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10966   wire width 1 $24
10967   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10968   cell $and $25
10969     parameter \A_SIGNED 1'0
10970     parameter \A_WIDTH 1'1
10971     parameter \B_SIGNED 1'0
10972     parameter \B_WIDTH 1'1
10973     parameter \Y_WIDTH 1'1
10974     connect \A $22
10975     connect \B \n_valid_o
10976     connect \Y $24
10977   end
10978   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10979   wire width 1 $26
10980   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10981   cell $or $27
10982     parameter \A_SIGNED 1'0
10983     parameter \A_WIDTH 1'1
10984     parameter \B_SIGNED 1'0
10985     parameter \B_WIDTH 1'1
10986     parameter \Y_WIDTH 1'1
10987     connect \A \p_valid_i__18
10988     connect \B $24
10989     connect \Y $26
10990   end
10991   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10992   wire width 1 $28
10993   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
10994   cell $not $29
10995     parameter \A_SIGNED 1'0
10996     parameter \A_WIDTH 1'1
10997     parameter \Y_WIDTH 1'1
10998     connect \A \n_ready_i__4
10999     connect \Y $28
11000   end
11001   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11002   wire width 1 $30
11003   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11004   cell $and $31
11005     parameter \A_SIGNED 1'0
11006     parameter \A_WIDTH 1'1
11007     parameter \B_SIGNED 1'0
11008     parameter \B_WIDTH 1'1
11009     parameter \Y_WIDTH 1'1
11010     connect \A $28
11011     connect \B \n_valid_o__1
11012     connect \Y $30
11013   end
11014   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11015   wire width 1 $32
11016   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11017   cell $or $33
11018     parameter \A_SIGNED 1'0
11019     parameter \A_WIDTH 1'1
11020     parameter \B_SIGNED 1'0
11021     parameter \B_WIDTH 1'1
11022     parameter \Y_WIDTH 1'1
11023     connect \A \p_valid_i__18
11024     connect \B $30
11025     connect \Y $32
11026   end
11027   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11028   wire width 1 $34
11029   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11030   cell $not $35
11031     parameter \A_SIGNED 1'0
11032     parameter \A_WIDTH 1'1
11033     parameter \Y_WIDTH 1'1
11034     connect \A \n_ready_i__5
11035     connect \Y $34
11036   end
11037   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11038   wire width 1 $36
11039   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11040   cell $and $37
11041     parameter \A_SIGNED 1'0
11042     parameter \A_WIDTH 1'1
11043     parameter \B_SIGNED 1'0
11044     parameter \B_WIDTH 1'1
11045     parameter \Y_WIDTH 1'1
11046     connect \A $34
11047     connect \B \n_valid_o__2
11048     connect \Y $36
11049   end
11050   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11051   wire width 1 $38
11052   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11053   cell $or $39
11054     parameter \A_SIGNED 1'0
11055     parameter \A_WIDTH 1'1
11056     parameter \B_SIGNED 1'0
11057     parameter \B_WIDTH 1'1
11058     parameter \Y_WIDTH 1'1
11059     connect \A \p_valid_i__18
11060     connect \B $36
11061     connect \Y $38
11062   end
11063   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11064   wire width 1 $40
11065   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11066   cell $not $41
11067     parameter \A_SIGNED 1'0
11068     parameter \A_WIDTH 1'1
11069     parameter \Y_WIDTH 1'1
11070     connect \A \n_ready_i__6
11071     connect \Y $40
11072   end
11073   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11074   wire width 1 $42
11075   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11076   cell $and $43
11077     parameter \A_SIGNED 1'0
11078     parameter \A_WIDTH 1'1
11079     parameter \B_SIGNED 1'0
11080     parameter \B_WIDTH 1'1
11081     parameter \Y_WIDTH 1'1
11082     connect \A $40
11083     connect \B \n_valid_o__3
11084     connect \Y $42
11085   end
11086   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11087   wire width 1 $44
11088   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11089   cell $or $45
11090     parameter \A_SIGNED 1'0
11091     parameter \A_WIDTH 1'1
11092     parameter \B_SIGNED 1'0
11093     parameter \B_WIDTH 1'1
11094     parameter \Y_WIDTH 1'1
11095     connect \A \p_valid_i__18
11096     connect \B $42
11097     connect \Y $44
11098   end
11099   process $group_2
11100     assign \n_valid_o 1'0
11101     assign \n_valid_o__1 1'0
11102     assign \n_valid_o__2 1'0
11103     assign \n_valid_o__3 1'0
11104     assign \n_valid_o 1'0
11105     assign \n_valid_o__1 1'0
11106     assign \n_valid_o__2 1'0
11107     assign \n_valid_o__3 1'0
11108     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228"
11109     switch \m_id
11110       case 2'00
11111         assign \n_valid_o $26
11112       case 2'01
11113         assign \n_valid_o__1 $32
11114       case 2'10
11115         assign \n_valid_o__2 $38
11116       case 2'--
11117         assign \n_valid_o__3 $44
11118     end
11119     sync init
11120   end
11121   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11122   wire width 1 $46
11123   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11124   wire width 1 $47
11125   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11126   cell $not $48
11127     parameter \A_SIGNED 1'0
11128     parameter \A_WIDTH 1'1
11129     parameter \Y_WIDTH 1'1
11130     connect \A \n_valid_o
11131     connect \Y $47
11132   end
11133   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11134   wire width 1 $49
11135   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11136   cell $or $50
11137     parameter \A_SIGNED 1'0
11138     parameter \A_WIDTH 1'1
11139     parameter \B_SIGNED 1'0
11140     parameter \B_WIDTH 1'1
11141     parameter \Y_WIDTH 1'1
11142     connect \A $47
11143     connect \B \n_ready_i
11144     connect \Y $49
11145   end
11146   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11147   wire width 1 $51
11148   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11149   cell $not $52
11150     parameter \A_SIGNED 1'0
11151     parameter \A_WIDTH 1'1
11152     parameter \Y_WIDTH 1'1
11153     connect \A \n_valid_o__1
11154     connect \Y $51
11155   end
11156   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11157   wire width 1 $53
11158   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11159   cell $or $54
11160     parameter \A_SIGNED 1'0
11161     parameter \A_WIDTH 1'1
11162     parameter \B_SIGNED 1'0
11163     parameter \B_WIDTH 1'1
11164     parameter \Y_WIDTH 1'1
11165     connect \A $51
11166     connect \B \n_ready_i__4
11167     connect \Y $53
11168   end
11169   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11170   wire width 1 $55
11171   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11172   cell $not $56
11173     parameter \A_SIGNED 1'0
11174     parameter \A_WIDTH 1'1
11175     parameter \Y_WIDTH 1'1
11176     connect \A \n_valid_o__2
11177     connect \Y $55
11178   end
11179   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11180   wire width 1 $57
11181   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11182   cell $or $58
11183     parameter \A_SIGNED 1'0
11184     parameter \A_WIDTH 1'1
11185     parameter \B_SIGNED 1'0
11186     parameter \B_WIDTH 1'1
11187     parameter \Y_WIDTH 1'1
11188     connect \A $55
11189     connect \B \n_ready_i__5
11190     connect \Y $57
11191   end
11192   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11193   wire width 1 $59
11194   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11195   cell $not $60
11196     parameter \A_SIGNED 1'0
11197     parameter \A_WIDTH 1'1
11198     parameter \Y_WIDTH 1'1
11199     connect \A \n_valid_o__3
11200     connect \Y $59
11201   end
11202   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11203   wire width 1 $61
11204   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226"
11205   cell $or $62
11206     parameter \A_SIGNED 1'0
11207     parameter \A_WIDTH 1'1
11208     parameter \B_SIGNED 1'0
11209     parameter \B_WIDTH 1'1
11210     parameter \Y_WIDTH 1'1
11211     connect \A $59
11212     connect \B \n_ready_i__6
11213     connect \Y $61
11214   end
11215   process $group_6
11216     assign \p_ready_o 1'0
11217     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:225"
11218     switch \m_id
11219       case 2'00
11220         assign \p_ready_o $49
11221       case 2'01
11222         assign \p_ready_o $53
11223       case 2'10
11224         assign \p_ready_o $57
11225       case 2'--
11226         assign \p_ready_o $61
11227     end
11228     sync init
11229   end
11230   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
11231   wire width 64 \z__63
11232   process $group_7
11233     assign \z__63 64'0000000000000000000000000000000000000000000000000000000000000000
11234     assign \z__63 \z
11235     sync init
11236   end
11237   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11238   wire width 2 \muxid__64
11239   process $group_8
11240     assign \muxid__64 2'00
11241     assign \muxid__64 \m_id
11242     sync init
11243   end
11244   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11245   wire width 0 \op__65
11246   process $group_9
11247     assign \op__65 0'0
11248     assign \op__65 \op
11249     sync init
11250   end
11251   process $group_10
11252     assign \z__7 64'0000000000000000000000000000000000000000000000000000000000000000
11253     assign \z__8 64'0000000000000000000000000000000000000000000000000000000000000000
11254     assign \z__9 64'0000000000000000000000000000000000000000000000000000000000000000
11255     assign \z__10 64'0000000000000000000000000000000000000000000000000000000000000000
11256     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/nmoperator.py:99"
11257     switch \m_id
11258       case 2'00
11259         assign \z__7 \z__63
11260       case 2'01
11261         assign \z__8 \z__63
11262       case 2'10
11263         assign \z__9 \z__63
11264       case 2'--
11265         assign \z__10 \z__63
11266     end
11267     sync init
11268   end
11269   process $group_14
11270     assign \muxid 2'00
11271     assign \muxid__11 2'00
11272     assign \muxid__12 2'00
11273     assign \muxid__13 2'00
11274     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/nmoperator.py:99"
11275     switch \m_id
11276       case 2'00
11277         assign \muxid \muxid__64
11278       case 2'01
11279         assign \muxid__11 \muxid__64
11280       case 2'10
11281         assign \muxid__12 \muxid__64
11282       case 2'--
11283         assign \muxid__13 \muxid__64
11284     end
11285     sync init
11286   end
11287   process $group_18
11288     assign \op__14 0'0
11289     assign \op__15 0'0
11290     assign \op__16 0'0
11291     assign \op__17 0'0
11292     attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/nmoperator.py:99"
11293     switch \m_id
11294       case 2'00
11295         assign \op__14 \op__65
11296       case 2'01
11297         assign \op__15 \op__65
11298       case 2'10
11299         assign \op__16 \op__65
11300       case 2'--
11301         assign \op__17 \op__65
11302     end
11303     sync init
11304   end
11305   connect \op__14 0'0
11306   connect \op__15 0'0
11307   connect \op__16 0'0
11308   connect \op__17 0'0
11309   connect \op__65 0'0
11310 end
11311 attribute \generator "nMigen"
11312 attribute \top 1
11313 attribute \nmigen.hierarchy "top"
11314 module \fpmul64
11315   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
11316   wire width 1 input 0 \p_valid_i
11317   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
11318   wire width 1 output 1 \p_ready_o
11319   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11320   wire width 64 input 2 \a
11321   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11322   wire width 64 input 3 \b
11323   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11324   wire width 64 input 4 \c
11325   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11326   wire width 2 input 5 \muxid
11327   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11328   wire width 0 input 6 \op
11329   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
11330   wire width 1 input 7 \p_valid_i__1
11331   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
11332   wire width 1 output 8 \p_ready_o__2
11333   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11334   wire width 64 input 9 \a__3
11335   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11336   wire width 64 input 10 \b__4
11337   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11338   wire width 64 input 11 \c__5
11339   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11340   wire width 2 input 12 \muxid__6
11341   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11342   wire width 0 input 13 \op__7
11343   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
11344   wire width 1 input 14 \p_valid_i__8
11345   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
11346   wire width 1 output 15 \p_ready_o__9
11347   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11348   wire width 64 input 16 \a__10
11349   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11350   wire width 64 input 17 \b__11
11351   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11352   wire width 64 input 18 \c__12
11353   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11354   wire width 2 input 19 \muxid__13
11355   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11356   wire width 0 input 20 \op__14
11357   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
11358   wire width 1 input 21 \p_valid_i__15
11359   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
11360   wire width 1 output 22 \p_ready_o__16
11361   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11362   wire width 64 input 23 \a__17
11363   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11364   wire width 64 input 24 \b__18
11365   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11366   wire width 64 input 25 \c__19
11367   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11368   wire width 2 input 26 \muxid__20
11369   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11370   wire width 0 input 27 \op__21
11371   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
11372   wire width 1 output 28 \n_ready_i
11373   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
11374   wire width 1 output 29 \n_valid_o
11375   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11376   wire width 64 output 30 \a__22
11377   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11378   wire width 64 output 31 \b__23
11379   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11380   wire width 64 output 32 \c__24
11381   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11382   wire width 2 output 33 \muxid__25
11383   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11384   wire width 0 output 34 \op__26
11385   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
11386   wire width 1 output 35 \p_valid_i__27
11387   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
11388   wire width 1 output 36 \p_ready_o__28
11389   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
11390   wire width 64 output 37 \z
11391   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11392   wire width 2 output 38 \m_id
11393   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11394   wire width 0 output 39 \op__29
11395   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
11396   wire width 1 input 40 \n_ready_i__30
11397   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
11398   wire width 1 output 41 \n_valid_o__31
11399   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
11400   wire width 64 output 42 \z__32
11401   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11402   wire width 2 output 43 \muxid__33
11403   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11404   wire width 0 output 44 \op__34
11405   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
11406   wire width 1 input 45 \n_ready_i__35
11407   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
11408   wire width 1 output 46 \n_valid_o__36
11409   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
11410   wire width 64 output 47 \z__37
11411   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11412   wire width 2 output 48 \muxid__38
11413   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11414   wire width 0 output 49 \op__39
11415   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
11416   wire width 1 input 50 \n_ready_i__40
11417   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
11418   wire width 1 output 51 \n_valid_o__41
11419   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
11420   wire width 64 output 52 \z__42
11421   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11422   wire width 2 output 53 \muxid__43
11423   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11424   wire width 0 output 54 \op__44
11425   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
11426   wire width 1 input 55 \n_ready_i__45
11427   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
11428   wire width 1 output 56 \n_valid_o__46
11429   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
11430   wire width 64 output 57 \z__47
11431   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11432   wire width 2 output 58 \muxid__48
11433   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11434   wire width 0 output 59 \op__49
11435   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
11436   wire width 1 input 60 \clk
11437   attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540"
11438   wire width 1 input 61 \rst
11439   cell \inpipe \inpipe
11440     connect \n_valid_o \n_valid_o
11441     connect \n_ready_i \n_ready_i
11442     connect \a \a__22
11443     connect \b \b__23
11444     connect \c \c__24
11445     connect \muxid \muxid__25
11446     connect \op \op__26
11447     connect \p_ready_o \p_ready_o
11448     connect \p_ready_o__1 \p_ready_o__2
11449     connect \p_ready_o__2 \p_ready_o__9
11450     connect \p_ready_o__3 \p_ready_o__16
11451     connect \p_valid_i \p_valid_i
11452     connect \a__4 \a
11453     connect \b__5 \b
11454     connect \c__6 \c
11455     connect \muxid__7 \muxid
11456     connect \op__8 \op
11457     connect \p_valid_i__9 \p_valid_i__1
11458     connect \a__10 \a__3
11459     connect \b__11 \b__4
11460     connect \c__12 \c__5
11461     connect \muxid__13 \muxid__6
11462     connect \op__14 \op__7
11463     connect \p_valid_i__15 \p_valid_i__8
11464     connect \a__16 \a__10
11465     connect \b__17 \b__11
11466     connect \c__18 \c__12
11467     connect \muxid__19 \muxid__13
11468     connect \op__20 \op__14
11469     connect \p_valid_i__21 \p_valid_i__15
11470     connect \a__22 \a__17
11471     connect \b__23 \b__18
11472     connect \c__24 \c__19
11473     connect \muxid__25 \muxid__20
11474     connect \op__26 \op__21
11475   end
11476   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121"
11477   wire width 1 \alu_p_valid_i
11478   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122"
11479   wire width 1 \alu_p_ready_o
11480   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11481   wire width 64 \alu_a
11482   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11483   wire width 64 \alu_b
11484   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17"
11485   wire width 64 \alu_c
11486   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11487   wire width 2 \alu_muxid
11488   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11489   wire width 0 \alu_op
11490   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213"
11491   wire width 1 \alu_n_valid_o
11492   attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214"
11493   wire width 1 \alu_n_ready_i
11494   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13"
11495   wire width 64 \alu_z
11496   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
11497   wire width 2 \alu_muxid__50
11498   attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63"
11499   wire width 0 \alu_op__51
11500   cell \alu \alu
11501     connect \p_valid_i \alu_p_valid_i
11502     connect \p_ready_o \alu_p_ready_o
11503     connect \a \alu_a
11504     connect \b \alu_b
11505     connect \c \alu_c
11506     connect \muxid \alu_muxid
11507     connect \op \alu_op
11508     connect \n_valid_o \alu_n_valid_o
11509     connect \n_ready_i \alu_n_ready_i
11510     connect \z \alu_z
11511     connect \muxid__1 \alu_muxid__50
11512     connect \op__2 \alu_op__51
11513     connect \rst \rst
11514     connect \clk \clk
11515   end
11516   cell \outpipe \outpipe
11517     connect \p_valid_i \p_valid_i__27
11518     connect \p_ready_o \p_ready_o__28
11519     connect \z \z
11520     connect \m_id \m_id
11521     connect \op \op__29
11522     connect \n_valid_o \n_valid_o__31
11523     connect \n_valid_o__1 \n_valid_o__36
11524     connect \n_valid_o__2 \n_valid_o__41
11525     connect \n_valid_o__3 \n_valid_o__46
11526     connect \n_ready_i \n_ready_i__30
11527     connect \n_ready_i__4 \n_ready_i__35
11528     connect \n_ready_i__5 \n_ready_i__40
11529     connect \n_ready_i__6 \n_ready_i__45
11530     connect \z__7 \z__32
11531     connect \z__8 \z__37
11532     connect \z__9 \z__42
11533     connect \z__10 \z__47
11534     connect \muxid \muxid__33
11535     connect \muxid__11 \muxid__38
11536     connect \muxid__12 \muxid__43
11537     connect \muxid__13 \muxid__48
11538     connect \op__14 \op__34
11539     connect \op__15 \op__39
11540     connect \op__16 \op__44
11541     connect \op__17 \op__49
11542   end
11543   process $group_0
11544     assign \alu_p_valid_i 1'0
11545     assign \alu_p_valid_i \n_valid_o
11546     sync init
11547   end
11548   process $group_1
11549     assign \n_ready_i 1'0
11550     assign \n_ready_i \alu_p_ready_o
11551     sync init
11552   end
11553   process $group_2
11554     assign \alu_a 64'0000000000000000000000000000000000000000000000000000000000000000
11555     assign \alu_a \a__22
11556     sync init
11557   end
11558   process $group_3
11559     assign \alu_b 64'0000000000000000000000000000000000000000000000000000000000000000
11560     assign \alu_b \b__23
11561     sync init
11562   end
11563   process $group_4
11564     assign \alu_c 64'0000000000000000000000000000000000000000000000000000000000000000
11565     assign \alu_c \c__24
11566     sync init
11567   end
11568   process $group_5
11569     assign \alu_muxid 2'00
11570     assign \alu_muxid \muxid__25
11571     sync init
11572   end
11573   process $group_6
11574     assign \alu_op 0'0
11575     assign \alu_op \op__26
11576     sync init
11577   end
11578   process $group_7
11579     assign \p_valid_i__27 1'0
11580     assign \p_valid_i__27 \alu_n_valid_o
11581     sync init
11582   end
11583   process $group_8
11584     assign \alu_n_ready_i 1'0
11585     assign \alu_n_ready_i \p_ready_o__28
11586     sync init
11587   end
11588   process $group_9
11589     assign \z 64'0000000000000000000000000000000000000000000000000000000000000000
11590     assign \z \alu_z
11591     sync init
11592   end
11593   process $group_10
11594     assign \m_id 2'00
11595     assign \m_id \alu_muxid__50
11596     sync init
11597   end
11598   process $group_11
11599     assign \op__29 0'0
11600     assign \op__29 \alu_op__51
11601     sync init
11602   end
11603   connect \op__29 0'0
11604   connect \alu_op 0'0
11605 end