sort-of got layout positions ok
[soclayout.git] / experiments7 / doAlu16.py
1 #!/usr/bin/env python
2 # -*- coding: utf-8 -*-
3 from __future__ import print_function
4 import sys
5
6 import CRL
7 import Cfg
8 from Hurricane import Box
9 from Hurricane import Transformation
10 from coriolis2.settings import af
11 from utils import Module, SessionManager, Config
12
13 import symbolic.cmos # do not remove
14
15 BIT_WIDTH = 16
16
17
18 def coriolis_setup():
19 with Config(Cfg.Parameter.Priority.UserFile) as cfg:
20 cfg.misc_catchCore = False
21 cfg.misc_info = False
22 cfg.misc_paranoid = False
23 cfg.misc_bug = False
24 cfg.misc_logMode = True
25 cfg.misc_verboseLevel1 = True
26 cfg.misc_verboseLevel2 = True
27 cfg.etesian_effort = 2
28 cfg.etesian_spaceMargin = "20.0%"
29 cfg.etesian_aspectRatio = "100.0%"
30 cfg.etesian_uniformDensity = True
31 cfg.anabatic_edgeLenght = 24
32 cfg.anabatic_edgeWidth = 8
33 cfg.anabatic_topRoutingLayer = 'METAL5'
34 cfg.katana_searchHalo = 30
35 cfg.katana_eventsLimit = 1000000
36 cfg.katana_hTracksReservedLocal = 7
37 cfg.katana_vTracksReservedLocal = 6
38
39 env = af.getEnvironment()
40 env.setCLOCK('^clk$|m_clock')
41 env.setPOWER('vdd')
42 env.setGROUND('vss')
43
44
45 class AddSub(Module):
46
47 def build(self):
48 """ Main routine. """
49
50 with SessionManager():
51 self.compute_ab()
52 self.create_pins()
53
54 if self.editor:
55 self.editor.setCell(self.cell)
56
57 result = self.place_and_route()
58
59 with SessionManager():
60 self.create_pads()
61
62 self.save()
63 return result
64
65
66 class ALU16(Module):
67
68 def save(self):
69 self.name = self.name + '_r'
70 self.af.saveCell(self.cell, CRL.Catalog.State.Views)
71 super(ALU16, self).save()
72
73 def build(self):
74
75 h_margin = 25.0
76 v_margin = 10.0
77
78 if not self.build_submodules():
79 return False
80
81 # at this point we have the (auto-calculated) submodules' dimensions
82 # in their `ab` properties.
83
84 add, sub = self.submodules
85
86 with SessionManager():
87 self.compute_ab()
88
89 width = self.from_dbu(
90 self.ab.getWidth() + add.ab.getWidth() + sub.ab.getWidth()
91 ) + 4*h_margin
92 height = self.from_dbu(max([
93 self.ab.getHeight(), add.ab.getHeight(), sub.ab.getHeight()
94 ])) + 2*v_margin
95
96 # experiment, over-ride
97 width = 1300
98 height = 370
99
100 self.ab = Box(0, 0, self.to_dbu(width), self.to_dbu(height))
101
102 add_wid = self.from_dbu(add.ab.getWidth())
103 sub_ht = self.from_dbu(sub.ab.getHeight())
104 self.place_submodule(add, h_margin, v_margin+add_wid)
105 self.place_submodule(sub, width-sub.ab_width-h_margin+sub_ht-45,
106 v_margin)
107
108 # TODO: replace with some form of lazy evaluation?
109 y_north = self.from_dbu(self.ab.getYMax())
110 for pin_conf in self.north_pins:
111 pin_conf['y'] = y_north
112
113 self.create_pins()
114
115 if self.editor:
116 self.editor.setCell(self.cell)
117
118 # place first (in middle, between two)
119 # this puts all the remaining cells (little ones)
120 # into this (small) space so that they do not go
121 # "all over the place" around the add and sub
122
123 # XXX this doesn't work: box is far too big, covers the entire
124 # area (including "under" the add and sub)
125 self.ab = Box(
126 self.to_dbu((width-self.ab_width)/2 - h_margin),
127 self.to_dbu(v_margin),
128 self.to_dbu((width+self.ab_width)/2 + h_margin),
129 self.to_dbu(height - v_margin)
130 )
131 self.ab = Box(self.to_dbu(450), self.to_dbu(15),
132 self.to_dbu(835), self.to_dbu(370))
133 self.place() # place only
134
135 # then route (globally)
136 # this connects up not just in the remaining (little) cells,
137 # it connects *to add and sub and the outside world as well*
138 self.ab = Box(0, 0, self.to_dbu(width), self.to_dbu(height))
139 result = self.route()
140
141 self.save()
142 return result
143
144
145 def ScriptMain(editor=None, **kwargs):
146 coriolis_setup()
147
148 add = AddSub(
149 'add', editor,
150 north_pins=[
151 {'net': 'a({})', 'x': 10.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
152 {'net': 'b({})', 'x': 15.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
153 {'net': 'o({})', 'x': 180.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
154 ],
155 south_pins=[
156 ],
157 pads={
158 'b({})'.format(BIT_WIDTH-1): (
159 'BLOCKAGE2', 'BLOCKAGE3', 'BLOCKAGE4',
160 ),
161 },
162 orientation=Transformation.Orientation.R3,
163 )
164 sub = AddSub(
165 'sub', editor,
166 north_pins=[
167 {'net': 'a({})', 'x': 180.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
168 {'net': 'b({})', 'x': 185.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
169 {'net': 'o({})', 'x': 10.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
170 ],
171 south_pins=[
172 ],
173 pads={
174 'b({})'.format(BIT_WIDTH-1): (
175 'BLOCKAGE2', 'BLOCKAGE3', 'BLOCKAGE4',
176 ),
177 },
178 orientation=Transformation.Orientation.R1,
179 )
180
181 alu16 = ALU16(
182 'alu16', editor, submodules=[add, sub],
183 north_pins=[
184 {'net': 'o({})', 'x': 500.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
185 {'net': 'op'},
186 ],
187 south_pins=[
188 {'net': 'a({})', 'x': 500.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
189 {'net': 'b({})', 'x': 700.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
190 ],
191 west_pins=[
192 {'net': 'rst', 'y': 140.0, 'layer': 'METAL2'},
193 ],
194 )
195 return alu16.build()
196
197
198 if __name__ == '__main__':
199 kwargs = {}
200 success = ScriptMain(**kwargs)
201 shellSuccess = 0
202 if not success:
203 shellSuccess = 1
204
205 sys.exit(shellSuccess)