aaagh found bug in litex setup, 64 bit WB bus was truncated
[soclayout.git] / experiments8 / Makefile
1 LOGICAL_SYNTHESIS = Yosys
2 PHYSICAL_SYNTHESIS = Coriolis
3 DESIGN_KIT = sxlib
4
5 USE_CLOCKTREE = No
6 USE_DEBUG = No
7 USE_KITE = No
8 VST_FLAGS = --vst-use-concat
9
10 NETLISTS = test_fu_fu_matrix
11
12
13 include ./mk/design-flow.mk
14
15
16 %_flat.vst: %.vst ; $(FLATLO) -r $* $*_flat
17
18
19 blif: test_fu_fu_matrix.blif
20 vst: test_fu_fu_matrix.vst
21 vstf: test_fu_fu_matrix_flat.vst
22
23 #blif: test_fu_reg_matrix.blif
24 #vst: test_fu_reg_matrix.vst
25 #layout: test_fu_reg_matrix_r.ap
26 #gds: test_fu_reg_matrix_r.gds
27 #
28 #lvx: lvx-test_fu_reg_matrix_r
29 #druc: druc-test_fu_reg_matrix_r
30 #view: cgt-test_fu_reg_matrix_r
31 viewf: cgt-test_fu_fu_matrix_flat
32 #sim: asimut-test_fu_reg_matrix_r