experiments8/test_fu_reg_matrix.il

   1 attribute \generator "nMigen"
   2 attribute \nmigen.hierarchy "top.dr_fu0.dst1_c"
   3 module \dst1_c
   4   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   5   wire width 4 input 0 \r_dst0
   6   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
   7   wire width 4 input 1 \s_dst0
   8   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   9   wire width 4 output 2 \q_dst0
  10   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
  11   wire width 4 output 3 \qlq_dst0
  12   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  13   wire width 1 input 4 \rst
  14   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
  15   wire width 1 input 5 \clk
  16   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  17   wire width 4 \q_int
  18   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
  19   wire width 4 \q_int$next
  20   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  21   wire width 4 $1
  22   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  23   cell $not $2
  24     parameter \A_SIGNED 1'0
  25     parameter \A_WIDTH 3'100
  26     parameter \Y_WIDTH 3'100
  27     connect \A \r_dst0
  28     connect \Y $1
  29   end
  30   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  31   wire width 4 $3
  32   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  33   cell $and $4
  34     parameter \A_SIGNED 1'0
  35     parameter \A_WIDTH 3'100
  36     parameter \B_SIGNED 1'0
  37     parameter \B_WIDTH 3'100
  38     parameter \Y_WIDTH 3'100
  39     connect \A \q_int
  40     connect \B $1
  41     connect \Y $3
  42   end
  43   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  44   wire width 4 $5
  45   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
  46   cell $or $6
  47     parameter \A_SIGNED 1'0
  48     parameter \A_WIDTH 3'100
  49     parameter \B_SIGNED 1'0
  50     parameter \B_WIDTH 3'100
  51     parameter \Y_WIDTH 3'100
  52     connect \A $3
  53     connect \B \s_dst0
  54     connect \Y $5
  55   end
  56   process $group_0
  57     assign \q_int$next \q_int
  58     assign \q_int$next $5
  59     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
  60     switch \rst
  61       case 1'1
  62         assign \q_int$next 4'0000
  63     end
  64     sync init
  65       update \q_int 4'0000
  66     sync posedge \clk
  67       update \q_int \q_int$next
  68   end
  69   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  70   wire width 4 $7
  71   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  72   cell $not $8
  73     parameter \A_SIGNED 1'0
  74     parameter \A_WIDTH 3'100
  75     parameter \Y_WIDTH 3'100
  76     connect \A \r_dst0
  77     connect \Y $7
  78   end
  79   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  80   wire width 4 $9
  81   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  82   cell $and $10
  83     parameter \A_SIGNED 1'0
  84     parameter \A_WIDTH 3'100
  85     parameter \B_SIGNED 1'0
  86     parameter \B_WIDTH 3'100
  87     parameter \Y_WIDTH 3'100
  88     connect \A \q_int
  89     connect \B $7
  90     connect \Y $9
  91   end
  92   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  93   wire width 4 $11
  94   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
  95   cell $or $12
  96     parameter \A_SIGNED 1'0
  97     parameter \A_WIDTH 3'100
  98     parameter \B_SIGNED 1'0
  99     parameter \B_WIDTH 3'100
 100     parameter \Y_WIDTH 3'100
 101     connect \A $9
 102     connect \B \s_dst0
 103     connect \Y $11
 104   end
 105   process $group_1
 106     assign \q_dst0 4'0000
 107     assign \q_dst0 $11
 108     sync init
 109   end
 110   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 111   wire width 4 \qn_dst0
 112   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 113   wire width 4 $13
 114   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 115   cell $not $14
 116     parameter \A_SIGNED 1'0
 117     parameter \A_WIDTH 3'100
 118     parameter \Y_WIDTH 3'100
 119     connect \A \q_dst0
 120     connect \Y $13
 121   end
 122   process $group_2
 123     assign \qn_dst0 4'0000
 124     assign \qn_dst0 $13
 125     sync init
 126   end
 127   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 128   wire width 4 $15
 129   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 130   cell $or $16
 131     parameter \A_SIGNED 1'0
 132     parameter \A_WIDTH 3'100
 133     parameter \B_SIGNED 1'0
 134     parameter \B_WIDTH 3'100
 135     parameter \Y_WIDTH 3'100
 136     connect \A \q_dst0
 137     connect \B \q_int
 138     connect \Y $15
 139   end
 140   process $group_3
 141     assign \qlq_dst0 4'0000
 142     assign \qlq_dst0 $15
 143     sync init
 144   end
 145 end
 146 attribute \generator "nMigen"
 147 attribute \nmigen.hierarchy "top.dr_fu0.dst2_c"
 148 module \dst2_c
 149   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 150   wire width 4 input 0 \r_dst1
 151   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 152   wire width 4 input 1 \s_dst1
 153   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 154   wire width 4 output 2 \q_dst1
 155   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 156   wire width 4 output 3 \qlq_dst1
 157   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 158   wire width 1 input 4 \rst
 159   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 160   wire width 1 input 5 \clk
 161   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 162   wire width 4 \q_int
 163   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 164   wire width 4 \q_int$next
 165   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 166   wire width 4 $1
 167   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 168   cell $not $2
 169     parameter \A_SIGNED 1'0
 170     parameter \A_WIDTH 3'100
 171     parameter \Y_WIDTH 3'100
 172     connect \A \r_dst1
 173     connect \Y $1
 174   end
 175   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 176   wire width 4 $3
 177   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 178   cell $and $4
 179     parameter \A_SIGNED 1'0
 180     parameter \A_WIDTH 3'100
 181     parameter \B_SIGNED 1'0
 182     parameter \B_WIDTH 3'100
 183     parameter \Y_WIDTH 3'100
 184     connect \A \q_int
 185     connect \B $1
 186     connect \Y $3
 187   end
 188   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 189   wire width 4 $5
 190   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 191   cell $or $6
 192     parameter \A_SIGNED 1'0
 193     parameter \A_WIDTH 3'100
 194     parameter \B_SIGNED 1'0
 195     parameter \B_WIDTH 3'100
 196     parameter \Y_WIDTH 3'100
 197     connect \A $3
 198     connect \B \s_dst1
 199     connect \Y $5
 200   end
 201   process $group_0
 202     assign \q_int$next \q_int
 203     assign \q_int$next $5
 204     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
 205     switch \rst
 206       case 1'1
 207         assign \q_int$next 4'0000
 208     end
 209     sync init
 210       update \q_int 4'0000
 211     sync posedge \clk
 212       update \q_int \q_int$next
 213   end
 214   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 215   wire width 4 $7
 216   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 217   cell $not $8
 218     parameter \A_SIGNED 1'0
 219     parameter \A_WIDTH 3'100
 220     parameter \Y_WIDTH 3'100
 221     connect \A \r_dst1
 222     connect \Y $7
 223   end
 224   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 225   wire width 4 $9
 226   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 227   cell $and $10
 228     parameter \A_SIGNED 1'0
 229     parameter \A_WIDTH 3'100
 230     parameter \B_SIGNED 1'0
 231     parameter \B_WIDTH 3'100
 232     parameter \Y_WIDTH 3'100
 233     connect \A \q_int
 234     connect \B $7
 235     connect \Y $9
 236   end
 237   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 238   wire width 4 $11
 239   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 240   cell $or $12
 241     parameter \A_SIGNED 1'0
 242     parameter \A_WIDTH 3'100
 243     parameter \B_SIGNED 1'0
 244     parameter \B_WIDTH 3'100
 245     parameter \Y_WIDTH 3'100
 246     connect \A $9
 247     connect \B \s_dst1
 248     connect \Y $11
 249   end
 250   process $group_1
 251     assign \q_dst1 4'0000
 252     assign \q_dst1 $11
 253     sync init
 254   end
 255   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 256   wire width 4 \qn_dst1
 257   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 258   wire width 4 $13
 259   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 260   cell $not $14
 261     parameter \A_SIGNED 1'0
 262     parameter \A_WIDTH 3'100
 263     parameter \Y_WIDTH 3'100
 264     connect \A \q_dst1
 265     connect \Y $13
 266   end
 267   process $group_2
 268     assign \qn_dst1 4'0000
 269     assign \qn_dst1 $13
 270     sync init
 271   end
 272   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 273   wire width 4 $15
 274   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 275   cell $or $16
 276     parameter \A_SIGNED 1'0
 277     parameter \A_WIDTH 3'100
 278     parameter \B_SIGNED 1'0
 279     parameter \B_WIDTH 3'100
 280     parameter \Y_WIDTH 3'100
 281     connect \A \q_dst1
 282     connect \B \q_int
 283     connect \Y $15
 284   end
 285   process $group_3
 286     assign \qlq_dst1 4'0000
 287     assign \qlq_dst1 $15
 288     sync init
 289   end
 290 end
 291 attribute \generator "nMigen"
 292 attribute \nmigen.hierarchy "top.dr_fu0.src1_c"
 293 module \src1_c
 294   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 295   wire width 4 input 0 \r_src0
 296   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 297   wire width 4 input 1 \s_src0
 298   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 299   wire width 4 output 2 \q_src0
 300   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 301   wire width 4 output 3 \qlq_src0
 302   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 303   wire width 1 input 4 \rst
 304   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 305   wire width 1 input 5 \clk
 306   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 307   wire width 4 \q_int
 308   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 309   wire width 4 \q_int$next
 310   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 311   wire width 4 $1
 312   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 313   cell $not $2
 314     parameter \A_SIGNED 1'0
 315     parameter \A_WIDTH 3'100
 316     parameter \Y_WIDTH 3'100
 317     connect \A \r_src0
 318     connect \Y $1
 319   end
 320   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 321   wire width 4 $3
 322   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 323   cell $and $4
 324     parameter \A_SIGNED 1'0
 325     parameter \A_WIDTH 3'100
 326     parameter \B_SIGNED 1'0
 327     parameter \B_WIDTH 3'100
 328     parameter \Y_WIDTH 3'100
 329     connect \A \q_int
 330     connect \B $1
 331     connect \Y $3
 332   end
 333   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 334   wire width 4 $5
 335   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 336   cell $or $6
 337     parameter \A_SIGNED 1'0
 338     parameter \A_WIDTH 3'100
 339     parameter \B_SIGNED 1'0
 340     parameter \B_WIDTH 3'100
 341     parameter \Y_WIDTH 3'100
 342     connect \A $3
 343     connect \B \s_src0
 344     connect \Y $5
 345   end
 346   process $group_0
 347     assign \q_int$next \q_int
 348     assign \q_int$next $5
 349     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
 350     switch \rst
 351       case 1'1
 352         assign \q_int$next 4'0000
 353     end
 354     sync init
 355       update \q_int 4'0000
 356     sync posedge \clk
 357       update \q_int \q_int$next
 358   end
 359   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 360   wire width 4 $7
 361   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 362   cell $not $8
 363     parameter \A_SIGNED 1'0
 364     parameter \A_WIDTH 3'100
 365     parameter \Y_WIDTH 3'100
 366     connect \A \r_src0
 367     connect \Y $7
 368   end
 369   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 370   wire width 4 $9
 371   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 372   cell $and $10
 373     parameter \A_SIGNED 1'0
 374     parameter \A_WIDTH 3'100
 375     parameter \B_SIGNED 1'0
 376     parameter \B_WIDTH 3'100
 377     parameter \Y_WIDTH 3'100
 378     connect \A \q_int
 379     connect \B $7
 380     connect \Y $9
 381   end
 382   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 383   wire width 4 $11
 384   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 385   cell $or $12
 386     parameter \A_SIGNED 1'0
 387     parameter \A_WIDTH 3'100
 388     parameter \B_SIGNED 1'0
 389     parameter \B_WIDTH 3'100
 390     parameter \Y_WIDTH 3'100
 391     connect \A $9
 392     connect \B \s_src0
 393     connect \Y $11
 394   end
 395   process $group_1
 396     assign \q_src0 4'0000
 397     assign \q_src0 $11
 398     sync init
 399   end
 400   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 401   wire width 4 \qn_src0
 402   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 403   wire width 4 $13
 404   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 405   cell $not $14
 406     parameter \A_SIGNED 1'0
 407     parameter \A_WIDTH 3'100
 408     parameter \Y_WIDTH 3'100
 409     connect \A \q_src0
 410     connect \Y $13
 411   end
 412   process $group_2
 413     assign \qn_src0 4'0000
 414     assign \qn_src0 $13
 415     sync init
 416   end
 417   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 418   wire width 4 $15
 419   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 420   cell $or $16
 421     parameter \A_SIGNED 1'0
 422     parameter \A_WIDTH 3'100
 423     parameter \B_SIGNED 1'0
 424     parameter \B_WIDTH 3'100
 425     parameter \Y_WIDTH 3'100
 426     connect \A \q_src0
 427     connect \B \q_int
 428     connect \Y $15
 429   end
 430   process $group_3
 431     assign \qlq_src0 4'0000
 432     assign \qlq_src0 $15
 433     sync init
 434   end
 435 end
 436 attribute \generator "nMigen"
 437 attribute \nmigen.hierarchy "top.dr_fu0.src2_c"
 438 module \src2_c
 439   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 440   wire width 4 input 0 \r_src1
 441   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 442   wire width 4 input 1 \s_src1
 443   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 444   wire width 4 output 2 \q_src1
 445   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 446   wire width 4 output 3 \qlq_src1
 447   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 448   wire width 1 input 4 \rst
 449   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 450   wire width 1 input 5 \clk
 451   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 452   wire width 4 \q_int
 453   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
 454   wire width 4 \q_int$next
 455   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 456   wire width 4 $1
 457   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 458   cell $not $2
 459     parameter \A_SIGNED 1'0
 460     parameter \A_WIDTH 3'100
 461     parameter \Y_WIDTH 3'100
 462     connect \A \r_src1
 463     connect \Y $1
 464   end
 465   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 466   wire width 4 $3
 467   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 468   cell $and $4
 469     parameter \A_SIGNED 1'0
 470     parameter \A_WIDTH 3'100
 471     parameter \B_SIGNED 1'0
 472     parameter \B_WIDTH 3'100
 473     parameter \Y_WIDTH 3'100
 474     connect \A \q_int
 475     connect \B $1
 476     connect \Y $3
 477   end
 478   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 479   wire width 4 $5
 480   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
 481   cell $or $6
 482     parameter \A_SIGNED 1'0
 483     parameter \A_WIDTH 3'100
 484     parameter \B_SIGNED 1'0
 485     parameter \B_WIDTH 3'100
 486     parameter \Y_WIDTH 3'100
 487     connect \A $3
 488     connect \B \s_src1
 489     connect \Y $5
 490   end
 491   process $group_0
 492     assign \q_int$next \q_int
 493     assign \q_int$next $5
 494     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
 495     switch \rst
 496       case 1'1
 497         assign \q_int$next 4'0000
 498     end
 499     sync init
 500       update \q_int 4'0000
 501     sync posedge \clk
 502       update \q_int \q_int$next
 503   end
 504   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 505   wire width 4 $7
 506   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 507   cell $not $8
 508     parameter \A_SIGNED 1'0
 509     parameter \A_WIDTH 3'100
 510     parameter \Y_WIDTH 3'100
 511     connect \A \r_src1
 512     connect \Y $7
 513   end
 514   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 515   wire width 4 $9
 516   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 517   cell $and $10
 518     parameter \A_SIGNED 1'0
 519     parameter \A_WIDTH 3'100
 520     parameter \B_SIGNED 1'0
 521     parameter \B_WIDTH 3'100
 522     parameter \Y_WIDTH 3'100
 523     connect \A \q_int
 524     connect \B $7
 525     connect \Y $9
 526   end
 527   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 528   wire width 4 $11
 529   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
 530   cell $or $12
 531     parameter \A_SIGNED 1'0
 532     parameter \A_WIDTH 3'100
 533     parameter \B_SIGNED 1'0
 534     parameter \B_WIDTH 3'100
 535     parameter \Y_WIDTH 3'100
 536     connect \A $9
 537     connect \B \s_src1
 538     connect \Y $11
 539   end
 540   process $group_1
 541     assign \q_src1 4'0000
 542     assign \q_src1 $11
 543     sync init
 544   end
 545   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
 546   wire width 4 \qn_src1
 547   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 548   wire width 4 $13
 549   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
 550   cell $not $14
 551     parameter \A_SIGNED 1'0
 552     parameter \A_WIDTH 3'100
 553     parameter \Y_WIDTH 3'100
 554     connect \A \q_src1
 555     connect \Y $13
 556   end
 557   process $group_2
 558     assign \qn_src1 4'0000
 559     assign \qn_src1 $13
 560     sync init
 561   end
 562   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 563   wire width 4 $15
 564   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
 565   cell $or $16
 566     parameter \A_SIGNED 1'0
 567     parameter \A_WIDTH 3'100
 568     parameter \B_SIGNED 1'0
 569     parameter \B_WIDTH 3'100
 570     parameter \Y_WIDTH 3'100
 571     connect \A \q_src1
 572     connect \B \q_int
 573     connect \Y $15
 574   end
 575   process $group_3
 576     assign \qlq_src1 4'0000
 577     assign \qlq_src1 $15
 578     sync init
 579   end
 580 end
 581 attribute \generator "nMigen"
 582 attribute \nmigen.hierarchy "top.dr_fu0"
 583 module \dr_fu0
 584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
 585   wire width 4 output 0 \dst1_fwd_o
 586   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
 587   wire width 4 output 1 \dst2_fwd_o
 588   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
 589   wire width 4 output 2 \src1_fwd_o
 590   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
 591   wire width 4 output 3 \src2_fwd_o
 592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
 593   wire width 4 output 4 \dst1_rsel_o
 594   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
 595   wire width 4 output 5 \dst2_rsel_o
 596   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
 597   wire width 4 output 6 \src1_rsel_o
 598   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
 599   wire width 4 output 7 \src2_rsel_o
 600   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
 601   wire width 4 input 8 \rd_pend_i
 602   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
 603   wire width 4 input 9 \wr_pend_i
 604   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
 605   wire width 4 input 10 \dst1
 606   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
 607   wire width 4 input 11 \dst2
 608   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
 609   wire width 4 input 12 \src1
 610   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
 611   wire width 4 input 13 \src2
 612   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
 613   wire width 1 input 14 \issue_i
 614   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
 615   wire width 2 input 15 \go_rd_i
 616   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
 617   wire width 2 input 16 \go_wr_i
 618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
 619   wire width 1 input 17 \go_die_i
 620   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
 621   wire width 4 output 18 \v_rd_rsel_o
 622   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
 623   wire width 4 output 19 \v_wr_rsel_o
 624   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 625   wire width 1 input 20 \rst
 626   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
 627   wire width 1 input 21 \clk
 628   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 629   wire width 4 \dst1_c_r_dst0
 630   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 631   wire width 4 \dst1_c_s_dst0
 632   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 633   wire width 4 \dst1_c_q_dst0
 634   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 635   wire width 4 \dst1_c_qlq_dst0
 636   cell \dst1_c \dst1_c
 637     connect \r_dst0 \dst1_c_r_dst0
 638     connect \s_dst0 \dst1_c_s_dst0
 639     connect \q_dst0 \dst1_c_q_dst0
 640     connect \qlq_dst0 \dst1_c_qlq_dst0
 641     connect \rst \rst
 642     connect \clk \clk
 643   end
 644   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 645   wire width 4 \dst2_c_r_dst1
 646   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 647   wire width 4 \dst2_c_s_dst1
 648   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 649   wire width 4 \dst2_c_q_dst1
 650   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 651   wire width 4 \dst2_c_qlq_dst1
 652   cell \dst2_c \dst2_c
 653     connect \r_dst1 \dst2_c_r_dst1
 654     connect \s_dst1 \dst2_c_s_dst1
 655     connect \q_dst1 \dst2_c_q_dst1
 656     connect \qlq_dst1 \dst2_c_qlq_dst1
 657     connect \rst \rst
 658     connect \clk \clk
 659   end
 660   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 661   wire width 4 \src1_c_r_src0
 662   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 663   wire width 4 \src1_c_s_src0
 664   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 665   wire width 4 \src1_c_q_src0
 666   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 667   wire width 4 \src1_c_qlq_src0
 668   cell \src1_c \src1_c
 669     connect \r_src0 \src1_c_r_src0
 670     connect \s_src0 \src1_c_s_src0
 671     connect \q_src0 \src1_c_q_src0
 672     connect \qlq_src0 \src1_c_qlq_src0
 673     connect \rst \rst
 674     connect \clk \clk
 675   end
 676   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
 677   wire width 4 \src2_c_r_src1
 678   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
 679   wire width 4 \src2_c_s_src1
 680   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
 681   wire width 4 \src2_c_q_src1
 682   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
 683   wire width 4 \src2_c_qlq_src1
 684   cell \src2_c \src2_c
 685     connect \r_src1 \src2_c_r_src1
 686     connect \s_src1 \src2_c_s_src1
 687     connect \q_src1 \src2_c_q_src1
 688     connect \qlq_src1 \src2_c_qlq_src1
 689     connect \rst \rst
 690     connect \clk \clk
 691   end
 692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
 693   wire width 4 \wdi0
 694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
 695   wire width 4 $1
 696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
 697   cell $or $2
 698     parameter \A_SIGNED 1'0
 699     parameter \A_WIDTH 3'100
 700     parameter \B_SIGNED 1'0
 701     parameter \B_WIDTH 3'100
 702     parameter \Y_WIDTH 3'100
 703     connect \A { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
 704     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
 705     connect \Y $1
 706   end
 707   process $group_0
 708     assign \wdi0 4'0000
 709     assign \wdi0 $1
 710     sync init
 711   end
 712   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
 713   wire width 4 \wdi1
 714   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
 715   wire width 4 $3
 716   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
 717   cell $or $4
 718     parameter \A_SIGNED 1'0
 719     parameter \A_WIDTH 3'100
 720     parameter \B_SIGNED 1'0
 721     parameter \B_WIDTH 3'100
 722     parameter \Y_WIDTH 3'100
 723     connect \A { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
 724     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
 725     connect \Y $3
 726   end
 727   process $group_1
 728     assign \wdi1 4'0000
 729     assign \wdi1 $3
 730     sync init
 731   end
 732   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
 733   wire width 4 \rdi0
 734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
 735   wire width 4 $5
 736   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
 737   cell $or $6
 738     parameter \A_SIGNED 1'0
 739     parameter \A_WIDTH 3'100
 740     parameter \B_SIGNED 1'0
 741     parameter \B_WIDTH 3'100
 742     parameter \Y_WIDTH 3'100
 743     connect \A { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
 744     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
 745     connect \Y $5
 746   end
 747   process $group_2
 748     assign \rdi0 4'0000
 749     assign \rdi0 $5
 750     sync init
 751   end
 752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
 753   wire width 4 \rdi1
 754   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
 755   wire width 4 $7
 756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
 757   cell $or $8
 758     parameter \A_SIGNED 1'0
 759     parameter \A_WIDTH 3'100
 760     parameter \B_SIGNED 1'0
 761     parameter \B_WIDTH 3'100
 762     parameter \Y_WIDTH 3'100
 763     connect \A { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
 764     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
 765     connect \Y $7
 766   end
 767   process $group_3
 768     assign \rdi1 4'0000
 769     assign \rdi1 $7
 770     sync init
 771   end
 772   process $group_4
 773     assign \src1_c_r_src0 4'1111
 774     assign \src1_c_r_src0 \rdi0
 775     sync init
 776   end
 777   process $group_5
 778     assign \src2_c_r_src1 4'1111
 779     assign \src2_c_r_src1 \rdi1
 780     sync init
 781   end
 782   process $group_6
 783     assign \dst1_c_r_dst0 4'1111
 784     assign \dst1_c_r_dst0 \wdi0
 785     sync init
 786   end
 787   process $group_7
 788     assign \dst2_c_r_dst1 4'1111
 789     assign \dst2_c_r_dst1 \wdi1
 790     sync init
 791   end
 792   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
 793   wire width 4 $9
 794   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
 795   cell $and $10
 796     parameter \A_SIGNED 1'0
 797     parameter \A_WIDTH 3'100
 798     parameter \B_SIGNED 1'0
 799     parameter \B_WIDTH 3'100
 800     parameter \Y_WIDTH 3'100
 801     connect \A { \issue_i \issue_i \issue_i \issue_i }
 802     connect \B \dst1
 803     connect \Y $9
 804   end
 805   process $group_8
 806     assign \dst1_c_s_dst0 4'0000
 807     assign \dst1_c_s_dst0 $9
 808     sync init
 809   end
 810   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
 811   wire width 4 $11
 812   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
 813   cell $and $12
 814     parameter \A_SIGNED 1'0
 815     parameter \A_WIDTH 3'100
 816     parameter \B_SIGNED 1'0
 817     parameter \B_WIDTH 3'100
 818     parameter \Y_WIDTH 3'100
 819     connect \A { \issue_i \issue_i \issue_i \issue_i }
 820     connect \B \dst2
 821     connect \Y $11
 822   end
 823   process $group_9
 824     assign \dst2_c_s_dst1 4'0000
 825     assign \dst2_c_s_dst1 $11
 826     sync init
 827   end
 828   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
 829   wire width 4 $13
 830   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
 831   cell $and $14
 832     parameter \A_SIGNED 1'0
 833     parameter \A_WIDTH 3'100
 834     parameter \B_SIGNED 1'0
 835     parameter \B_WIDTH 3'100
 836     parameter \Y_WIDTH 3'100
 837     connect \A { \issue_i \issue_i \issue_i \issue_i }
 838     connect \B \src1
 839     connect \Y $13
 840   end
 841   process $group_10
 842     assign \src1_c_s_src0 4'0000
 843     assign \src1_c_s_src0 $13
 844     sync init
 845   end
 846   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
 847   wire width 4 $15
 848   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
 849   cell $and $16
 850     parameter \A_SIGNED 1'0
 851     parameter \A_WIDTH 3'100
 852     parameter \B_SIGNED 1'0
 853     parameter \B_WIDTH 3'100
 854     parameter \Y_WIDTH 3'100
 855     connect \A { \issue_i \issue_i \issue_i \issue_i }
 856     connect \B \src2
 857     connect \Y $15
 858   end
 859   process $group_11
 860     assign \src2_c_s_src1 4'0000
 861     assign \src2_c_s_src1 $15
 862     sync init
 863   end
 864   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
 865   wire width 4 $17
 866   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
 867   cell $and $18
 868     parameter \A_SIGNED 1'0
 869     parameter \A_WIDTH 3'100
 870     parameter \B_SIGNED 1'0
 871     parameter \B_WIDTH 3'100
 872     parameter \Y_WIDTH 3'100
 873     connect \A \dst1_c_q_dst0
 874     connect \B \rd_pend_i
 875     connect \Y $17
 876   end
 877   process $group_12
 878     assign \dst1_fwd_o 4'0000
 879     assign \dst1_fwd_o $17
 880     sync init
 881   end
 882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
 883   wire width 4 $19
 884   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
 885   cell $and $20
 886     parameter \A_SIGNED 1'0
 887     parameter \A_WIDTH 3'100
 888     parameter \B_SIGNED 1'0
 889     parameter \B_WIDTH 3'100
 890     parameter \Y_WIDTH 3'100
 891     connect \A \dst2_c_q_dst1
 892     connect \B \rd_pend_i
 893     connect \Y $19
 894   end
 895   process $group_13
 896     assign \dst2_fwd_o 4'0000
 897     assign \dst2_fwd_o $19
 898     sync init
 899   end
 900   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
 901   wire width 4 $21
 902   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
 903   cell $and $22
 904     parameter \A_SIGNED 1'0
 905     parameter \A_WIDTH 3'100
 906     parameter \B_SIGNED 1'0
 907     parameter \B_WIDTH 3'100
 908     parameter \Y_WIDTH 3'100
 909     connect \A \src1_c_q_src0
 910     connect \B \wr_pend_i
 911     connect \Y $21
 912   end
 913   process $group_14
 914     assign \src1_fwd_o 4'0000
 915     assign \src1_fwd_o $21
 916     sync init
 917   end
 918   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
 919   wire width 4 $23
 920   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
 921   cell $and $24
 922     parameter \A_SIGNED 1'0
 923     parameter \A_WIDTH 3'100
 924     parameter \B_SIGNED 1'0
 925     parameter \B_WIDTH 3'100
 926     parameter \Y_WIDTH 3'100
 927     connect \A \src2_c_q_src1
 928     connect \B \wr_pend_i
 929     connect \Y $23
 930   end
 931   process $group_15
 932     assign \src2_fwd_o 4'0000
 933     assign \src2_fwd_o $23
 934     sync init
 935   end
 936   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
 937   wire width 4 $25
 938   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
 939   cell $and $26
 940     parameter \A_SIGNED 1'0
 941     parameter \A_WIDTH 3'100
 942     parameter \B_SIGNED 1'0
 943     parameter \B_WIDTH 3'100
 944     parameter \Y_WIDTH 3'100
 945     connect \A \dst1_c_qlq_dst0
 946     connect \B { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
 947     connect \Y $25
 948   end
 949   process $group_16
 950     assign \dst1_rsel_o 4'0000
 951     assign \dst1_rsel_o $25
 952     sync init
 953   end
 954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
 955   wire width 4 $27
 956   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
 957   cell $and $28
 958     parameter \A_SIGNED 1'0
 959     parameter \A_WIDTH 3'100
 960     parameter \B_SIGNED 1'0
 961     parameter \B_WIDTH 3'100
 962     parameter \Y_WIDTH 3'100
 963     connect \A \dst2_c_qlq_dst1
 964     connect \B { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
 965     connect \Y $27
 966   end
 967   process $group_17
 968     assign \dst2_rsel_o 4'0000
 969     assign \dst2_rsel_o $27
 970     sync init
 971   end
 972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
 973   wire width 4 $29
 974   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
 975   cell $and $30
 976     parameter \A_SIGNED 1'0
 977     parameter \A_WIDTH 3'100
 978     parameter \B_SIGNED 1'0
 979     parameter \B_WIDTH 3'100
 980     parameter \Y_WIDTH 3'100
 981     connect \A \src1_c_qlq_src0
 982     connect \B { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
 983     connect \Y $29
 984   end
 985   process $group_18
 986     assign \src1_rsel_o 4'0000
 987     assign \src1_rsel_o $29
 988     sync init
 989   end
 990   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
 991   wire width 4 $31
 992   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
 993   cell $and $32
 994     parameter \A_SIGNED 1'0
 995     parameter \A_WIDTH 3'100
 996     parameter \B_SIGNED 1'0
 997     parameter \B_WIDTH 3'100
 998     parameter \Y_WIDTH 3'100
 999     connect \A \src2_c_qlq_src1
1000     connect \B { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
1001     connect \Y $31
1002   end
1003   process $group_19
1004     assign \src2_rsel_o 4'0000
1005     assign \src2_rsel_o $31
1006     sync init
1007   end
1008   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
1009   wire width 4 $33
1010   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
1011   cell $or $34
1012     parameter \A_SIGNED 1'0
1013     parameter \A_WIDTH 3'100
1014     parameter \B_SIGNED 1'0
1015     parameter \B_WIDTH 3'100
1016     parameter \Y_WIDTH 3'100
1017     connect \A \src1_c_qlq_src0
1018     connect \B \src2_c_qlq_src1
1019     connect \Y $33
1020   end
1021   process $group_20
1022     assign \v_rd_rsel_o 4'0000
1023     assign \v_rd_rsel_o $33
1024     sync init
1025   end
1026   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
1027   wire width 4 $35
1028   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
1029   cell $or $36
1030     parameter \A_SIGNED 1'0
1031     parameter \A_WIDTH 3'100
1032     parameter \B_SIGNED 1'0
1033     parameter \B_WIDTH 3'100
1034     parameter \Y_WIDTH 3'100
1035     connect \A \dst1_c_qlq_dst0
1036     connect \B \dst2_c_qlq_dst1
1037     connect \Y $35
1038   end
1039   process $group_21
1040     assign \v_wr_rsel_o 4'0000
1041     assign \v_wr_rsel_o $35
1042     sync init
1043   end
1044 end
1045 attribute \generator "nMigen"
1046 attribute \nmigen.hierarchy "top.dr_fu1.dst1_c"
1047 module \dst1_c$1
1048   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1049   wire width 1 input 0 \rst
1050   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1051   wire width 1 input 1 \clk
1052   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1053   wire width 4 input 2 \r_dst0
1054   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1055   wire width 4 input 3 \s_dst0
1056   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1057   wire width 4 output 4 \q_dst0
1058   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1059   wire width 4 output 5 \qlq_dst0
1060   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1061   wire width 4 \q_int
1062   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1063   wire width 4 \q_int$next
1064   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1065   wire width 4 $1
1066   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1067   cell $not $2
1068     parameter \A_SIGNED 1'0
1069     parameter \A_WIDTH 3'100
1070     parameter \Y_WIDTH 3'100
1071     connect \A \r_dst0
1072     connect \Y $1
1073   end
1074   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1075   wire width 4 $3
1076   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1077   cell $and $4
1078     parameter \A_SIGNED 1'0
1079     parameter \A_WIDTH 3'100
1080     parameter \B_SIGNED 1'0
1081     parameter \B_WIDTH 3'100
1082     parameter \Y_WIDTH 3'100
1083     connect \A \q_int
1084     connect \B $1
1085     connect \Y $3
1086   end
1087   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1088   wire width 4 $5
1089   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1090   cell $or $6
1091     parameter \A_SIGNED 1'0
1092     parameter \A_WIDTH 3'100
1093     parameter \B_SIGNED 1'0
1094     parameter \B_WIDTH 3'100
1095     parameter \Y_WIDTH 3'100
1096     connect \A $3
1097     connect \B \s_dst0
1098     connect \Y $5
1099   end
1100   process $group_0
1101     assign \q_int$next \q_int
1102     assign \q_int$next $5
1103     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1104     switch \rst
1105       case 1'1
1106         assign \q_int$next 4'0000
1107     end
1108     sync init
1109       update \q_int 4'0000
1110     sync posedge \clk
1111       update \q_int \q_int$next
1112   end
1113   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1114   wire width 4 $7
1115   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1116   cell $not $8
1117     parameter \A_SIGNED 1'0
1118     parameter \A_WIDTH 3'100
1119     parameter \Y_WIDTH 3'100
1120     connect \A \r_dst0
1121     connect \Y $7
1122   end
1123   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1124   wire width 4 $9
1125   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1126   cell $and $10
1127     parameter \A_SIGNED 1'0
1128     parameter \A_WIDTH 3'100
1129     parameter \B_SIGNED 1'0
1130     parameter \B_WIDTH 3'100
1131     parameter \Y_WIDTH 3'100
1132     connect \A \q_int
1133     connect \B $7
1134     connect \Y $9
1135   end
1136   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1137   wire width 4 $11
1138   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1139   cell $or $12
1140     parameter \A_SIGNED 1'0
1141     parameter \A_WIDTH 3'100
1142     parameter \B_SIGNED 1'0
1143     parameter \B_WIDTH 3'100
1144     parameter \Y_WIDTH 3'100
1145     connect \A $9
1146     connect \B \s_dst0
1147     connect \Y $11
1148   end
1149   process $group_1
1150     assign \q_dst0 4'0000
1151     assign \q_dst0 $11
1152     sync init
1153   end
1154   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1155   wire width 4 \qn_dst0
1156   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1157   wire width 4 $13
1158   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1159   cell $not $14
1160     parameter \A_SIGNED 1'0
1161     parameter \A_WIDTH 3'100
1162     parameter \Y_WIDTH 3'100
1163     connect \A \q_dst0
1164     connect \Y $13
1165   end
1166   process $group_2
1167     assign \qn_dst0 4'0000
1168     assign \qn_dst0 $13
1169     sync init
1170   end
1171   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1172   wire width 4 $15
1173   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1174   cell $or $16
1175     parameter \A_SIGNED 1'0
1176     parameter \A_WIDTH 3'100
1177     parameter \B_SIGNED 1'0
1178     parameter \B_WIDTH 3'100
1179     parameter \Y_WIDTH 3'100
1180     connect \A \q_dst0
1181     connect \B \q_int
1182     connect \Y $15
1183   end
1184   process $group_3
1185     assign \qlq_dst0 4'0000
1186     assign \qlq_dst0 $15
1187     sync init
1188   end
1189 end
1190 attribute \generator "nMigen"
1191 attribute \nmigen.hierarchy "top.dr_fu1.dst2_c"
1192 module \dst2_c$2
1193   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1194   wire width 1 input 0 \rst
1195   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1196   wire width 1 input 1 \clk
1197   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1198   wire width 4 input 2 \r_dst1
1199   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1200   wire width 4 input 3 \s_dst1
1201   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1202   wire width 4 output 4 \q_dst1
1203   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1204   wire width 4 output 5 \qlq_dst1
1205   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1206   wire width 4 \q_int
1207   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1208   wire width 4 \q_int$next
1209   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1210   wire width 4 $1
1211   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1212   cell $not $2
1213     parameter \A_SIGNED 1'0
1214     parameter \A_WIDTH 3'100
1215     parameter \Y_WIDTH 3'100
1216     connect \A \r_dst1
1217     connect \Y $1
1218   end
1219   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1220   wire width 4 $3
1221   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1222   cell $and $4
1223     parameter \A_SIGNED 1'0
1224     parameter \A_WIDTH 3'100
1225     parameter \B_SIGNED 1'0
1226     parameter \B_WIDTH 3'100
1227     parameter \Y_WIDTH 3'100
1228     connect \A \q_int
1229     connect \B $1
1230     connect \Y $3
1231   end
1232   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1233   wire width 4 $5
1234   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1235   cell $or $6
1236     parameter \A_SIGNED 1'0
1237     parameter \A_WIDTH 3'100
1238     parameter \B_SIGNED 1'0
1239     parameter \B_WIDTH 3'100
1240     parameter \Y_WIDTH 3'100
1241     connect \A $3
1242     connect \B \s_dst1
1243     connect \Y $5
1244   end
1245   process $group_0
1246     assign \q_int$next \q_int
1247     assign \q_int$next $5
1248     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1249     switch \rst
1250       case 1'1
1251         assign \q_int$next 4'0000
1252     end
1253     sync init
1254       update \q_int 4'0000
1255     sync posedge \clk
1256       update \q_int \q_int$next
1257   end
1258   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1259   wire width 4 $7
1260   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1261   cell $not $8
1262     parameter \A_SIGNED 1'0
1263     parameter \A_WIDTH 3'100
1264     parameter \Y_WIDTH 3'100
1265     connect \A \r_dst1
1266     connect \Y $7
1267   end
1268   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1269   wire width 4 $9
1270   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1271   cell $and $10
1272     parameter \A_SIGNED 1'0
1273     parameter \A_WIDTH 3'100
1274     parameter \B_SIGNED 1'0
1275     parameter \B_WIDTH 3'100
1276     parameter \Y_WIDTH 3'100
1277     connect \A \q_int
1278     connect \B $7
1279     connect \Y $9
1280   end
1281   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1282   wire width 4 $11
1283   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1284   cell $or $12
1285     parameter \A_SIGNED 1'0
1286     parameter \A_WIDTH 3'100
1287     parameter \B_SIGNED 1'0
1288     parameter \B_WIDTH 3'100
1289     parameter \Y_WIDTH 3'100
1290     connect \A $9
1291     connect \B \s_dst1
1292     connect \Y $11
1293   end
1294   process $group_1
1295     assign \q_dst1 4'0000
1296     assign \q_dst1 $11
1297     sync init
1298   end
1299   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1300   wire width 4 \qn_dst1
1301   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1302   wire width 4 $13
1303   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1304   cell $not $14
1305     parameter \A_SIGNED 1'0
1306     parameter \A_WIDTH 3'100
1307     parameter \Y_WIDTH 3'100
1308     connect \A \q_dst1
1309     connect \Y $13
1310   end
1311   process $group_2
1312     assign \qn_dst1 4'0000
1313     assign \qn_dst1 $13
1314     sync init
1315   end
1316   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1317   wire width 4 $15
1318   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1319   cell $or $16
1320     parameter \A_SIGNED 1'0
1321     parameter \A_WIDTH 3'100
1322     parameter \B_SIGNED 1'0
1323     parameter \B_WIDTH 3'100
1324     parameter \Y_WIDTH 3'100
1325     connect \A \q_dst1
1326     connect \B \q_int
1327     connect \Y $15
1328   end
1329   process $group_3
1330     assign \qlq_dst1 4'0000
1331     assign \qlq_dst1 $15
1332     sync init
1333   end
1334 end
1335 attribute \generator "nMigen"
1336 attribute \nmigen.hierarchy "top.dr_fu1.src1_c"
1337 module \src1_c$3
1338   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1339   wire width 1 input 0 \rst
1340   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1341   wire width 1 input 1 \clk
1342   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1343   wire width 4 input 2 \r_src0
1344   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1345   wire width 4 input 3 \s_src0
1346   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1347   wire width 4 output 4 \q_src0
1348   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1349   wire width 4 output 5 \qlq_src0
1350   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1351   wire width 4 \q_int
1352   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1353   wire width 4 \q_int$next
1354   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1355   wire width 4 $1
1356   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1357   cell $not $2
1358     parameter \A_SIGNED 1'0
1359     parameter \A_WIDTH 3'100
1360     parameter \Y_WIDTH 3'100
1361     connect \A \r_src0
1362     connect \Y $1
1363   end
1364   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1365   wire width 4 $3
1366   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1367   cell $and $4
1368     parameter \A_SIGNED 1'0
1369     parameter \A_WIDTH 3'100
1370     parameter \B_SIGNED 1'0
1371     parameter \B_WIDTH 3'100
1372     parameter \Y_WIDTH 3'100
1373     connect \A \q_int
1374     connect \B $1
1375     connect \Y $3
1376   end
1377   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1378   wire width 4 $5
1379   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1380   cell $or $6
1381     parameter \A_SIGNED 1'0
1382     parameter \A_WIDTH 3'100
1383     parameter \B_SIGNED 1'0
1384     parameter \B_WIDTH 3'100
1385     parameter \Y_WIDTH 3'100
1386     connect \A $3
1387     connect \B \s_src0
1388     connect \Y $5
1389   end
1390   process $group_0
1391     assign \q_int$next \q_int
1392     assign \q_int$next $5
1393     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1394     switch \rst
1395       case 1'1
1396         assign \q_int$next 4'0000
1397     end
1398     sync init
1399       update \q_int 4'0000
1400     sync posedge \clk
1401       update \q_int \q_int$next
1402   end
1403   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1404   wire width 4 $7
1405   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1406   cell $not $8
1407     parameter \A_SIGNED 1'0
1408     parameter \A_WIDTH 3'100
1409     parameter \Y_WIDTH 3'100
1410     connect \A \r_src0
1411     connect \Y $7
1412   end
1413   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1414   wire width 4 $9
1415   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1416   cell $and $10
1417     parameter \A_SIGNED 1'0
1418     parameter \A_WIDTH 3'100
1419     parameter \B_SIGNED 1'0
1420     parameter \B_WIDTH 3'100
1421     parameter \Y_WIDTH 3'100
1422     connect \A \q_int
1423     connect \B $7
1424     connect \Y $9
1425   end
1426   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1427   wire width 4 $11
1428   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1429   cell $or $12
1430     parameter \A_SIGNED 1'0
1431     parameter \A_WIDTH 3'100
1432     parameter \B_SIGNED 1'0
1433     parameter \B_WIDTH 3'100
1434     parameter \Y_WIDTH 3'100
1435     connect \A $9
1436     connect \B \s_src0
1437     connect \Y $11
1438   end
1439   process $group_1
1440     assign \q_src0 4'0000
1441     assign \q_src0 $11
1442     sync init
1443   end
1444   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1445   wire width 4 \qn_src0
1446   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1447   wire width 4 $13
1448   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1449   cell $not $14
1450     parameter \A_SIGNED 1'0
1451     parameter \A_WIDTH 3'100
1452     parameter \Y_WIDTH 3'100
1453     connect \A \q_src0
1454     connect \Y $13
1455   end
1456   process $group_2
1457     assign \qn_src0 4'0000
1458     assign \qn_src0 $13
1459     sync init
1460   end
1461   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1462   wire width 4 $15
1463   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1464   cell $or $16
1465     parameter \A_SIGNED 1'0
1466     parameter \A_WIDTH 3'100
1467     parameter \B_SIGNED 1'0
1468     parameter \B_WIDTH 3'100
1469     parameter \Y_WIDTH 3'100
1470     connect \A \q_src0
1471     connect \B \q_int
1472     connect \Y $15
1473   end
1474   process $group_3
1475     assign \qlq_src0 4'0000
1476     assign \qlq_src0 $15
1477     sync init
1478   end
1479 end
1480 attribute \generator "nMigen"
1481 attribute \nmigen.hierarchy "top.dr_fu1.src2_c"
1482 module \src2_c$4
1483   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1484   wire width 1 input 0 \rst
1485   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1486   wire width 1 input 1 \clk
1487   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1488   wire width 4 input 2 \r_src1
1489   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1490   wire width 4 input 3 \s_src1
1491   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1492   wire width 4 output 4 \q_src1
1493   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1494   wire width 4 output 5 \qlq_src1
1495   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1496   wire width 4 \q_int
1497   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1498   wire width 4 \q_int$next
1499   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1500   wire width 4 $1
1501   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1502   cell $not $2
1503     parameter \A_SIGNED 1'0
1504     parameter \A_WIDTH 3'100
1505     parameter \Y_WIDTH 3'100
1506     connect \A \r_src1
1507     connect \Y $1
1508   end
1509   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1510   wire width 4 $3
1511   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1512   cell $and $4
1513     parameter \A_SIGNED 1'0
1514     parameter \A_WIDTH 3'100
1515     parameter \B_SIGNED 1'0
1516     parameter \B_WIDTH 3'100
1517     parameter \Y_WIDTH 3'100
1518     connect \A \q_int
1519     connect \B $1
1520     connect \Y $3
1521   end
1522   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1523   wire width 4 $5
1524   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1525   cell $or $6
1526     parameter \A_SIGNED 1'0
1527     parameter \A_WIDTH 3'100
1528     parameter \B_SIGNED 1'0
1529     parameter \B_WIDTH 3'100
1530     parameter \Y_WIDTH 3'100
1531     connect \A $3
1532     connect \B \s_src1
1533     connect \Y $5
1534   end
1535   process $group_0
1536     assign \q_int$next \q_int
1537     assign \q_int$next $5
1538     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1539     switch \rst
1540       case 1'1
1541         assign \q_int$next 4'0000
1542     end
1543     sync init
1544       update \q_int 4'0000
1545     sync posedge \clk
1546       update \q_int \q_int$next
1547   end
1548   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1549   wire width 4 $7
1550   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1551   cell $not $8
1552     parameter \A_SIGNED 1'0
1553     parameter \A_WIDTH 3'100
1554     parameter \Y_WIDTH 3'100
1555     connect \A \r_src1
1556     connect \Y $7
1557   end
1558   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1559   wire width 4 $9
1560   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1561   cell $and $10
1562     parameter \A_SIGNED 1'0
1563     parameter \A_WIDTH 3'100
1564     parameter \B_SIGNED 1'0
1565     parameter \B_WIDTH 3'100
1566     parameter \Y_WIDTH 3'100
1567     connect \A \q_int
1568     connect \B $7
1569     connect \Y $9
1570   end
1571   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1572   wire width 4 $11
1573   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1574   cell $or $12
1575     parameter \A_SIGNED 1'0
1576     parameter \A_WIDTH 3'100
1577     parameter \B_SIGNED 1'0
1578     parameter \B_WIDTH 3'100
1579     parameter \Y_WIDTH 3'100
1580     connect \A $9
1581     connect \B \s_src1
1582     connect \Y $11
1583   end
1584   process $group_1
1585     assign \q_src1 4'0000
1586     assign \q_src1 $11
1587     sync init
1588   end
1589   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1590   wire width 4 \qn_src1
1591   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1592   wire width 4 $13
1593   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1594   cell $not $14
1595     parameter \A_SIGNED 1'0
1596     parameter \A_WIDTH 3'100
1597     parameter \Y_WIDTH 3'100
1598     connect \A \q_src1
1599     connect \Y $13
1600   end
1601   process $group_2
1602     assign \qn_src1 4'0000
1603     assign \qn_src1 $13
1604     sync init
1605   end
1606   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1607   wire width 4 $15
1608   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1609   cell $or $16
1610     parameter \A_SIGNED 1'0
1611     parameter \A_WIDTH 3'100
1612     parameter \B_SIGNED 1'0
1613     parameter \B_WIDTH 3'100
1614     parameter \Y_WIDTH 3'100
1615     connect \A \q_src1
1616     connect \B \q_int
1617     connect \Y $15
1618   end
1619   process $group_3
1620     assign \qlq_src1 4'0000
1621     assign \qlq_src1 $15
1622     sync init
1623   end
1624 end
1625 attribute \generator "nMigen"
1626 attribute \nmigen.hierarchy "top.dr_fu1"
1627 module \dr_fu1
1628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
1629   wire width 4 output 0 \dst1_fwd_o
1630   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
1631   wire width 4 output 1 \dst2_fwd_o
1632   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
1633   wire width 4 output 2 \src1_fwd_o
1634   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
1635   wire width 4 output 3 \src2_fwd_o
1636   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
1637   wire width 4 output 4 \dst1_rsel_o
1638   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
1639   wire width 4 output 5 \dst2_rsel_o
1640   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
1641   wire width 4 output 6 \src1_rsel_o
1642   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
1643   wire width 4 output 7 \src2_rsel_o
1644   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
1645   wire width 4 input 8 \rd_pend_i
1646   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
1647   wire width 4 input 9 \wr_pend_i
1648   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
1649   wire width 4 input 10 \dst1
1650   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
1651   wire width 4 input 11 \dst2
1652   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
1653   wire width 4 input 12 \src1
1654   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
1655   wire width 4 input 13 \src2
1656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
1657   wire width 1 input 14 \issue_i
1658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
1659   wire width 2 input 15 \go_rd_i
1660   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
1661   wire width 2 input 16 \go_wr_i
1662   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
1663   wire width 1 input 17 \go_die_i
1664   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1665   wire width 1 input 18 \rst
1666   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1667   wire width 1 input 19 \clk
1668   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
1669   wire width 4 output 20 \v_rd_rsel_o
1670   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
1671   wire width 4 output 21 \v_wr_rsel_o
1672   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1673   wire width 4 \dst1_c_r_dst0
1674   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1675   wire width 4 \dst1_c_s_dst0
1676   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1677   wire width 4 \dst1_c_q_dst0
1678   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1679   wire width 4 \dst1_c_qlq_dst0
1680   cell \dst1_c$1 \dst1_c
1681     connect \rst \rst
1682     connect \clk \clk
1683     connect \r_dst0 \dst1_c_r_dst0
1684     connect \s_dst0 \dst1_c_s_dst0
1685     connect \q_dst0 \dst1_c_q_dst0
1686     connect \qlq_dst0 \dst1_c_qlq_dst0
1687   end
1688   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1689   wire width 4 \dst2_c_r_dst1
1690   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1691   wire width 4 \dst2_c_s_dst1
1692   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1693   wire width 4 \dst2_c_q_dst1
1694   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1695   wire width 4 \dst2_c_qlq_dst1
1696   cell \dst2_c$2 \dst2_c
1697     connect \rst \rst
1698     connect \clk \clk
1699     connect \r_dst1 \dst2_c_r_dst1
1700     connect \s_dst1 \dst2_c_s_dst1
1701     connect \q_dst1 \dst2_c_q_dst1
1702     connect \qlq_dst1 \dst2_c_qlq_dst1
1703   end
1704   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1705   wire width 4 \src1_c_r_src0
1706   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1707   wire width 4 \src1_c_s_src0
1708   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1709   wire width 4 \src1_c_q_src0
1710   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1711   wire width 4 \src1_c_qlq_src0
1712   cell \src1_c$3 \src1_c
1713     connect \rst \rst
1714     connect \clk \clk
1715     connect \r_src0 \src1_c_r_src0
1716     connect \s_src0 \src1_c_s_src0
1717     connect \q_src0 \src1_c_q_src0
1718     connect \qlq_src0 \src1_c_qlq_src0
1719   end
1720   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1721   wire width 4 \src2_c_r_src1
1722   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1723   wire width 4 \src2_c_s_src1
1724   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1725   wire width 4 \src2_c_q_src1
1726   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1727   wire width 4 \src2_c_qlq_src1
1728   cell \src2_c$4 \src2_c
1729     connect \rst \rst
1730     connect \clk \clk
1731     connect \r_src1 \src2_c_r_src1
1732     connect \s_src1 \src2_c_s_src1
1733     connect \q_src1 \src2_c_q_src1
1734     connect \qlq_src1 \src2_c_qlq_src1
1735   end
1736   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
1737   wire width 4 \wdi0
1738   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
1739   wire width 4 $1
1740   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
1741   cell $or $2
1742     parameter \A_SIGNED 1'0
1743     parameter \A_WIDTH 3'100
1744     parameter \B_SIGNED 1'0
1745     parameter \B_WIDTH 3'100
1746     parameter \Y_WIDTH 3'100
1747     connect \A { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
1748     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
1749     connect \Y $1
1750   end
1751   process $group_0
1752     assign \wdi0 4'0000
1753     assign \wdi0 $1
1754     sync init
1755   end
1756   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
1757   wire width 4 \wdi1
1758   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
1759   wire width 4 $3
1760   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
1761   cell $or $4
1762     parameter \A_SIGNED 1'0
1763     parameter \A_WIDTH 3'100
1764     parameter \B_SIGNED 1'0
1765     parameter \B_WIDTH 3'100
1766     parameter \Y_WIDTH 3'100
1767     connect \A { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
1768     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
1769     connect \Y $3
1770   end
1771   process $group_1
1772     assign \wdi1 4'0000
1773     assign \wdi1 $3
1774     sync init
1775   end
1776   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
1777   wire width 4 \rdi0
1778   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
1779   wire width 4 $5
1780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
1781   cell $or $6
1782     parameter \A_SIGNED 1'0
1783     parameter \A_WIDTH 3'100
1784     parameter \B_SIGNED 1'0
1785     parameter \B_WIDTH 3'100
1786     parameter \Y_WIDTH 3'100
1787     connect \A { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
1788     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
1789     connect \Y $5
1790   end
1791   process $group_2
1792     assign \rdi0 4'0000
1793     assign \rdi0 $5
1794     sync init
1795   end
1796   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
1797   wire width 4 \rdi1
1798   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
1799   wire width 4 $7
1800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
1801   cell $or $8
1802     parameter \A_SIGNED 1'0
1803     parameter \A_WIDTH 3'100
1804     parameter \B_SIGNED 1'0
1805     parameter \B_WIDTH 3'100
1806     parameter \Y_WIDTH 3'100
1807     connect \A { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
1808     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
1809     connect \Y $7
1810   end
1811   process $group_3
1812     assign \rdi1 4'0000
1813     assign \rdi1 $7
1814     sync init
1815   end
1816   process $group_4
1817     assign \src1_c_r_src0 4'1111
1818     assign \src1_c_r_src0 \rdi0
1819     sync init
1820   end
1821   process $group_5
1822     assign \src2_c_r_src1 4'1111
1823     assign \src2_c_r_src1 \rdi1
1824     sync init
1825   end
1826   process $group_6
1827     assign \dst1_c_r_dst0 4'1111
1828     assign \dst1_c_r_dst0 \wdi0
1829     sync init
1830   end
1831   process $group_7
1832     assign \dst2_c_r_dst1 4'1111
1833     assign \dst2_c_r_dst1 \wdi1
1834     sync init
1835   end
1836   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
1837   wire width 4 $9
1838   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
1839   cell $and $10
1840     parameter \A_SIGNED 1'0
1841     parameter \A_WIDTH 3'100
1842     parameter \B_SIGNED 1'0
1843     parameter \B_WIDTH 3'100
1844     parameter \Y_WIDTH 3'100
1845     connect \A { \issue_i \issue_i \issue_i \issue_i }
1846     connect \B \dst1
1847     connect \Y $9
1848   end
1849   process $group_8
1850     assign \dst1_c_s_dst0 4'0000
1851     assign \dst1_c_s_dst0 $9
1852     sync init
1853   end
1854   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
1855   wire width 4 $11
1856   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
1857   cell $and $12
1858     parameter \A_SIGNED 1'0
1859     parameter \A_WIDTH 3'100
1860     parameter \B_SIGNED 1'0
1861     parameter \B_WIDTH 3'100
1862     parameter \Y_WIDTH 3'100
1863     connect \A { \issue_i \issue_i \issue_i \issue_i }
1864     connect \B \dst2
1865     connect \Y $11
1866   end
1867   process $group_9
1868     assign \dst2_c_s_dst1 4'0000
1869     assign \dst2_c_s_dst1 $11
1870     sync init
1871   end
1872   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
1873   wire width 4 $13
1874   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
1875   cell $and $14
1876     parameter \A_SIGNED 1'0
1877     parameter \A_WIDTH 3'100
1878     parameter \B_SIGNED 1'0
1879     parameter \B_WIDTH 3'100
1880     parameter \Y_WIDTH 3'100
1881     connect \A { \issue_i \issue_i \issue_i \issue_i }
1882     connect \B \src1
1883     connect \Y $13
1884   end
1885   process $group_10
1886     assign \src1_c_s_src0 4'0000
1887     assign \src1_c_s_src0 $13
1888     sync init
1889   end
1890   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
1891   wire width 4 $15
1892   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
1893   cell $and $16
1894     parameter \A_SIGNED 1'0
1895     parameter \A_WIDTH 3'100
1896     parameter \B_SIGNED 1'0
1897     parameter \B_WIDTH 3'100
1898     parameter \Y_WIDTH 3'100
1899     connect \A { \issue_i \issue_i \issue_i \issue_i }
1900     connect \B \src2
1901     connect \Y $15
1902   end
1903   process $group_11
1904     assign \src2_c_s_src1 4'0000
1905     assign \src2_c_s_src1 $15
1906     sync init
1907   end
1908   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
1909   wire width 4 $17
1910   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
1911   cell $and $18
1912     parameter \A_SIGNED 1'0
1913     parameter \A_WIDTH 3'100
1914     parameter \B_SIGNED 1'0
1915     parameter \B_WIDTH 3'100
1916     parameter \Y_WIDTH 3'100
1917     connect \A \dst1_c_q_dst0
1918     connect \B \rd_pend_i
1919     connect \Y $17
1920   end
1921   process $group_12
1922     assign \dst1_fwd_o 4'0000
1923     assign \dst1_fwd_o $17
1924     sync init
1925   end
1926   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
1927   wire width 4 $19
1928   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
1929   cell $and $20
1930     parameter \A_SIGNED 1'0
1931     parameter \A_WIDTH 3'100
1932     parameter \B_SIGNED 1'0
1933     parameter \B_WIDTH 3'100
1934     parameter \Y_WIDTH 3'100
1935     connect \A \dst2_c_q_dst1
1936     connect \B \rd_pend_i
1937     connect \Y $19
1938   end
1939   process $group_13
1940     assign \dst2_fwd_o 4'0000
1941     assign \dst2_fwd_o $19
1942     sync init
1943   end
1944   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
1945   wire width 4 $21
1946   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
1947   cell $and $22
1948     parameter \A_SIGNED 1'0
1949     parameter \A_WIDTH 3'100
1950     parameter \B_SIGNED 1'0
1951     parameter \B_WIDTH 3'100
1952     parameter \Y_WIDTH 3'100
1953     connect \A \src1_c_q_src0
1954     connect \B \wr_pend_i
1955     connect \Y $21
1956   end
1957   process $group_14
1958     assign \src1_fwd_o 4'0000
1959     assign \src1_fwd_o $21
1960     sync init
1961   end
1962   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
1963   wire width 4 $23
1964   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
1965   cell $and $24
1966     parameter \A_SIGNED 1'0
1967     parameter \A_WIDTH 3'100
1968     parameter \B_SIGNED 1'0
1969     parameter \B_WIDTH 3'100
1970     parameter \Y_WIDTH 3'100
1971     connect \A \src2_c_q_src1
1972     connect \B \wr_pend_i
1973     connect \Y $23
1974   end
1975   process $group_15
1976     assign \src2_fwd_o 4'0000
1977     assign \src2_fwd_o $23
1978     sync init
1979   end
1980   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
1981   wire width 4 $25
1982   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
1983   cell $and $26
1984     parameter \A_SIGNED 1'0
1985     parameter \A_WIDTH 3'100
1986     parameter \B_SIGNED 1'0
1987     parameter \B_WIDTH 3'100
1988     parameter \Y_WIDTH 3'100
1989     connect \A \dst1_c_qlq_dst0
1990     connect \B { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
1991     connect \Y $25
1992   end
1993   process $group_16
1994     assign \dst1_rsel_o 4'0000
1995     assign \dst1_rsel_o $25
1996     sync init
1997   end
1998   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
1999   wire width 4 $27
2000   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
2001   cell $and $28
2002     parameter \A_SIGNED 1'0
2003     parameter \A_WIDTH 3'100
2004     parameter \B_SIGNED 1'0
2005     parameter \B_WIDTH 3'100
2006     parameter \Y_WIDTH 3'100
2007     connect \A \dst2_c_qlq_dst1
2008     connect \B { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
2009     connect \Y $27
2010   end
2011   process $group_17
2012     assign \dst2_rsel_o 4'0000
2013     assign \dst2_rsel_o $27
2014     sync init
2015   end
2016   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
2017   wire width 4 $29
2018   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
2019   cell $and $30
2020     parameter \A_SIGNED 1'0
2021     parameter \A_WIDTH 3'100
2022     parameter \B_SIGNED 1'0
2023     parameter \B_WIDTH 3'100
2024     parameter \Y_WIDTH 3'100
2025     connect \A \src1_c_qlq_src0
2026     connect \B { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
2027     connect \Y $29
2028   end
2029   process $group_18
2030     assign \src1_rsel_o 4'0000
2031     assign \src1_rsel_o $29
2032     sync init
2033   end
2034   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
2035   wire width 4 $31
2036   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
2037   cell $and $32
2038     parameter \A_SIGNED 1'0
2039     parameter \A_WIDTH 3'100
2040     parameter \B_SIGNED 1'0
2041     parameter \B_WIDTH 3'100
2042     parameter \Y_WIDTH 3'100
2043     connect \A \src2_c_qlq_src1
2044     connect \B { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
2045     connect \Y $31
2046   end
2047   process $group_19
2048     assign \src2_rsel_o 4'0000
2049     assign \src2_rsel_o $31
2050     sync init
2051   end
2052   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
2053   wire width 4 $33
2054   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
2055   cell $or $34
2056     parameter \A_SIGNED 1'0
2057     parameter \A_WIDTH 3'100
2058     parameter \B_SIGNED 1'0
2059     parameter \B_WIDTH 3'100
2060     parameter \Y_WIDTH 3'100
2061     connect \A \src1_c_qlq_src0
2062     connect \B \src2_c_qlq_src1
2063     connect \Y $33
2064   end
2065   process $group_20
2066     assign \v_rd_rsel_o 4'0000
2067     assign \v_rd_rsel_o $33
2068     sync init
2069   end
2070   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
2071   wire width 4 $35
2072   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
2073   cell $or $36
2074     parameter \A_SIGNED 1'0
2075     parameter \A_WIDTH 3'100
2076     parameter \B_SIGNED 1'0
2077     parameter \B_WIDTH 3'100
2078     parameter \Y_WIDTH 3'100
2079     connect \A \dst1_c_qlq_dst0
2080     connect \B \dst2_c_qlq_dst1
2081     connect \Y $35
2082   end
2083   process $group_21
2084     assign \v_wr_rsel_o 4'0000
2085     assign \v_wr_rsel_o $35
2086     sync init
2087   end
2088 end
2089 attribute \generator "nMigen"
2090 attribute \nmigen.hierarchy "top.dr_fu2.dst1_c"
2091 module \dst1_c$5
2092   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2093   wire width 1 input 0 \rst
2094   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2095   wire width 1 input 1 \clk
2096   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2097   wire width 4 input 2 \r_dst0
2098   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2099   wire width 4 input 3 \s_dst0
2100   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2101   wire width 4 output 4 \q_dst0
2102   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2103   wire width 4 output 5 \qlq_dst0
2104   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2105   wire width 4 \q_int
2106   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2107   wire width 4 \q_int$next
2108   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2109   wire width 4 $1
2110   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2111   cell $not $2
2112     parameter \A_SIGNED 1'0
2113     parameter \A_WIDTH 3'100
2114     parameter \Y_WIDTH 3'100
2115     connect \A \r_dst0
2116     connect \Y $1
2117   end
2118   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2119   wire width 4 $3
2120   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2121   cell $and $4
2122     parameter \A_SIGNED 1'0
2123     parameter \A_WIDTH 3'100
2124     parameter \B_SIGNED 1'0
2125     parameter \B_WIDTH 3'100
2126     parameter \Y_WIDTH 3'100
2127     connect \A \q_int
2128     connect \B $1
2129     connect \Y $3
2130   end
2131   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2132   wire width 4 $5
2133   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2134   cell $or $6
2135     parameter \A_SIGNED 1'0
2136     parameter \A_WIDTH 3'100
2137     parameter \B_SIGNED 1'0
2138     parameter \B_WIDTH 3'100
2139     parameter \Y_WIDTH 3'100
2140     connect \A $3
2141     connect \B \s_dst0
2142     connect \Y $5
2143   end
2144   process $group_0
2145     assign \q_int$next \q_int
2146     assign \q_int$next $5
2147     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2148     switch \rst
2149       case 1'1
2150         assign \q_int$next 4'0000
2151     end
2152     sync init
2153       update \q_int 4'0000
2154     sync posedge \clk
2155       update \q_int \q_int$next
2156   end
2157   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2158   wire width 4 $7
2159   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2160   cell $not $8
2161     parameter \A_SIGNED 1'0
2162     parameter \A_WIDTH 3'100
2163     parameter \Y_WIDTH 3'100
2164     connect \A \r_dst0
2165     connect \Y $7
2166   end
2167   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2168   wire width 4 $9
2169   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2170   cell $and $10
2171     parameter \A_SIGNED 1'0
2172     parameter \A_WIDTH 3'100
2173     parameter \B_SIGNED 1'0
2174     parameter \B_WIDTH 3'100
2175     parameter \Y_WIDTH 3'100
2176     connect \A \q_int
2177     connect \B $7
2178     connect \Y $9
2179   end
2180   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2181   wire width 4 $11
2182   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2183   cell $or $12
2184     parameter \A_SIGNED 1'0
2185     parameter \A_WIDTH 3'100
2186     parameter \B_SIGNED 1'0
2187     parameter \B_WIDTH 3'100
2188     parameter \Y_WIDTH 3'100
2189     connect \A $9
2190     connect \B \s_dst0
2191     connect \Y $11
2192   end
2193   process $group_1
2194     assign \q_dst0 4'0000
2195     assign \q_dst0 $11
2196     sync init
2197   end
2198   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2199   wire width 4 \qn_dst0
2200   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2201   wire width 4 $13
2202   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2203   cell $not $14
2204     parameter \A_SIGNED 1'0
2205     parameter \A_WIDTH 3'100
2206     parameter \Y_WIDTH 3'100
2207     connect \A \q_dst0
2208     connect \Y $13
2209   end
2210   process $group_2
2211     assign \qn_dst0 4'0000
2212     assign \qn_dst0 $13
2213     sync init
2214   end
2215   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2216   wire width 4 $15
2217   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2218   cell $or $16
2219     parameter \A_SIGNED 1'0
2220     parameter \A_WIDTH 3'100
2221     parameter \B_SIGNED 1'0
2222     parameter \B_WIDTH 3'100
2223     parameter \Y_WIDTH 3'100
2224     connect \A \q_dst0
2225     connect \B \q_int
2226     connect \Y $15
2227   end
2228   process $group_3
2229     assign \qlq_dst0 4'0000
2230     assign \qlq_dst0 $15
2231     sync init
2232   end
2233 end
2234 attribute \generator "nMigen"
2235 attribute \nmigen.hierarchy "top.dr_fu2.dst2_c"
2236 module \dst2_c$6
2237   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2238   wire width 1 input 0 \rst
2239   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2240   wire width 1 input 1 \clk
2241   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2242   wire width 4 input 2 \r_dst1
2243   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2244   wire width 4 input 3 \s_dst1
2245   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2246   wire width 4 output 4 \q_dst1
2247   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2248   wire width 4 output 5 \qlq_dst1
2249   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2250   wire width 4 \q_int
2251   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2252   wire width 4 \q_int$next
2253   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2254   wire width 4 $1
2255   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2256   cell $not $2
2257     parameter \A_SIGNED 1'0
2258     parameter \A_WIDTH 3'100
2259     parameter \Y_WIDTH 3'100
2260     connect \A \r_dst1
2261     connect \Y $1
2262   end
2263   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2264   wire width 4 $3
2265   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2266   cell $and $4
2267     parameter \A_SIGNED 1'0
2268     parameter \A_WIDTH 3'100
2269     parameter \B_SIGNED 1'0
2270     parameter \B_WIDTH 3'100
2271     parameter \Y_WIDTH 3'100
2272     connect \A \q_int
2273     connect \B $1
2274     connect \Y $3
2275   end
2276   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2277   wire width 4 $5
2278   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2279   cell $or $6
2280     parameter \A_SIGNED 1'0
2281     parameter \A_WIDTH 3'100
2282     parameter \B_SIGNED 1'0
2283     parameter \B_WIDTH 3'100
2284     parameter \Y_WIDTH 3'100
2285     connect \A $3
2286     connect \B \s_dst1
2287     connect \Y $5
2288   end
2289   process $group_0
2290     assign \q_int$next \q_int
2291     assign \q_int$next $5
2292     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2293     switch \rst
2294       case 1'1
2295         assign \q_int$next 4'0000
2296     end
2297     sync init
2298       update \q_int 4'0000
2299     sync posedge \clk
2300       update \q_int \q_int$next
2301   end
2302   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2303   wire width 4 $7
2304   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2305   cell $not $8
2306     parameter \A_SIGNED 1'0
2307     parameter \A_WIDTH 3'100
2308     parameter \Y_WIDTH 3'100
2309     connect \A \r_dst1
2310     connect \Y $7
2311   end
2312   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2313   wire width 4 $9
2314   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2315   cell $and $10
2316     parameter \A_SIGNED 1'0
2317     parameter \A_WIDTH 3'100
2318     parameter \B_SIGNED 1'0
2319     parameter \B_WIDTH 3'100
2320     parameter \Y_WIDTH 3'100
2321     connect \A \q_int
2322     connect \B $7
2323     connect \Y $9
2324   end
2325   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2326   wire width 4 $11
2327   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2328   cell $or $12
2329     parameter \A_SIGNED 1'0
2330     parameter \A_WIDTH 3'100
2331     parameter \B_SIGNED 1'0
2332     parameter \B_WIDTH 3'100
2333     parameter \Y_WIDTH 3'100
2334     connect \A $9
2335     connect \B \s_dst1
2336     connect \Y $11
2337   end
2338   process $group_1
2339     assign \q_dst1 4'0000
2340     assign \q_dst1 $11
2341     sync init
2342   end
2343   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2344   wire width 4 \qn_dst1
2345   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2346   wire width 4 $13
2347   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2348   cell $not $14
2349     parameter \A_SIGNED 1'0
2350     parameter \A_WIDTH 3'100
2351     parameter \Y_WIDTH 3'100
2352     connect \A \q_dst1
2353     connect \Y $13
2354   end
2355   process $group_2
2356     assign \qn_dst1 4'0000
2357     assign \qn_dst1 $13
2358     sync init
2359   end
2360   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2361   wire width 4 $15
2362   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2363   cell $or $16
2364     parameter \A_SIGNED 1'0
2365     parameter \A_WIDTH 3'100
2366     parameter \B_SIGNED 1'0
2367     parameter \B_WIDTH 3'100
2368     parameter \Y_WIDTH 3'100
2369     connect \A \q_dst1
2370     connect \B \q_int
2371     connect \Y $15
2372   end
2373   process $group_3
2374     assign \qlq_dst1 4'0000
2375     assign \qlq_dst1 $15
2376     sync init
2377   end
2378 end
2379 attribute \generator "nMigen"
2380 attribute \nmigen.hierarchy "top.dr_fu2.src1_c"
2381 module \src1_c$7
2382   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2383   wire width 1 input 0 \rst
2384   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2385   wire width 1 input 1 \clk
2386   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2387   wire width 4 input 2 \r_src0
2388   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2389   wire width 4 input 3 \s_src0
2390   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2391   wire width 4 output 4 \q_src0
2392   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2393   wire width 4 output 5 \qlq_src0
2394   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2395   wire width 4 \q_int
2396   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2397   wire width 4 \q_int$next
2398   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2399   wire width 4 $1
2400   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2401   cell $not $2
2402     parameter \A_SIGNED 1'0
2403     parameter \A_WIDTH 3'100
2404     parameter \Y_WIDTH 3'100
2405     connect \A \r_src0
2406     connect \Y $1
2407   end
2408   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2409   wire width 4 $3
2410   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2411   cell $and $4
2412     parameter \A_SIGNED 1'0
2413     parameter \A_WIDTH 3'100
2414     parameter \B_SIGNED 1'0
2415     parameter \B_WIDTH 3'100
2416     parameter \Y_WIDTH 3'100
2417     connect \A \q_int
2418     connect \B $1
2419     connect \Y $3
2420   end
2421   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2422   wire width 4 $5
2423   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2424   cell $or $6
2425     parameter \A_SIGNED 1'0
2426     parameter \A_WIDTH 3'100
2427     parameter \B_SIGNED 1'0
2428     parameter \B_WIDTH 3'100
2429     parameter \Y_WIDTH 3'100
2430     connect \A $3
2431     connect \B \s_src0
2432     connect \Y $5
2433   end
2434   process $group_0
2435     assign \q_int$next \q_int
2436     assign \q_int$next $5
2437     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2438     switch \rst
2439       case 1'1
2440         assign \q_int$next 4'0000
2441     end
2442     sync init
2443       update \q_int 4'0000
2444     sync posedge \clk
2445       update \q_int \q_int$next
2446   end
2447   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2448   wire width 4 $7
2449   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2450   cell $not $8
2451     parameter \A_SIGNED 1'0
2452     parameter \A_WIDTH 3'100
2453     parameter \Y_WIDTH 3'100
2454     connect \A \r_src0
2455     connect \Y $7
2456   end
2457   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2458   wire width 4 $9
2459   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2460   cell $and $10
2461     parameter \A_SIGNED 1'0
2462     parameter \A_WIDTH 3'100
2463     parameter \B_SIGNED 1'0
2464     parameter \B_WIDTH 3'100
2465     parameter \Y_WIDTH 3'100
2466     connect \A \q_int
2467     connect \B $7
2468     connect \Y $9
2469   end
2470   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2471   wire width 4 $11
2472   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2473   cell $or $12
2474     parameter \A_SIGNED 1'0
2475     parameter \A_WIDTH 3'100
2476     parameter \B_SIGNED 1'0
2477     parameter \B_WIDTH 3'100
2478     parameter \Y_WIDTH 3'100
2479     connect \A $9
2480     connect \B \s_src0
2481     connect \Y $11
2482   end
2483   process $group_1
2484     assign \q_src0 4'0000
2485     assign \q_src0 $11
2486     sync init
2487   end
2488   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2489   wire width 4 \qn_src0
2490   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2491   wire width 4 $13
2492   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2493   cell $not $14
2494     parameter \A_SIGNED 1'0
2495     parameter \A_WIDTH 3'100
2496     parameter \Y_WIDTH 3'100
2497     connect \A \q_src0
2498     connect \Y $13
2499   end
2500   process $group_2
2501     assign \qn_src0 4'0000
2502     assign \qn_src0 $13
2503     sync init
2504   end
2505   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2506   wire width 4 $15
2507   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2508   cell $or $16
2509     parameter \A_SIGNED 1'0
2510     parameter \A_WIDTH 3'100
2511     parameter \B_SIGNED 1'0
2512     parameter \B_WIDTH 3'100
2513     parameter \Y_WIDTH 3'100
2514     connect \A \q_src0
2515     connect \B \q_int
2516     connect \Y $15
2517   end
2518   process $group_3
2519     assign \qlq_src0 4'0000
2520     assign \qlq_src0 $15
2521     sync init
2522   end
2523 end
2524 attribute \generator "nMigen"
2525 attribute \nmigen.hierarchy "top.dr_fu2.src2_c"
2526 module \src2_c$8
2527   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2528   wire width 1 input 0 \rst
2529   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2530   wire width 1 input 1 \clk
2531   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2532   wire width 4 input 2 \r_src1
2533   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2534   wire width 4 input 3 \s_src1
2535   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2536   wire width 4 output 4 \q_src1
2537   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2538   wire width 4 output 5 \qlq_src1
2539   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2540   wire width 4 \q_int
2541   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2542   wire width 4 \q_int$next
2543   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2544   wire width 4 $1
2545   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2546   cell $not $2
2547     parameter \A_SIGNED 1'0
2548     parameter \A_WIDTH 3'100
2549     parameter \Y_WIDTH 3'100
2550     connect \A \r_src1
2551     connect \Y $1
2552   end
2553   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2554   wire width 4 $3
2555   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2556   cell $and $4
2557     parameter \A_SIGNED 1'0
2558     parameter \A_WIDTH 3'100
2559     parameter \B_SIGNED 1'0
2560     parameter \B_WIDTH 3'100
2561     parameter \Y_WIDTH 3'100
2562     connect \A \q_int
2563     connect \B $1
2564     connect \Y $3
2565   end
2566   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2567   wire width 4 $5
2568   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2569   cell $or $6
2570     parameter \A_SIGNED 1'0
2571     parameter \A_WIDTH 3'100
2572     parameter \B_SIGNED 1'0
2573     parameter \B_WIDTH 3'100
2574     parameter \Y_WIDTH 3'100
2575     connect \A $3
2576     connect \B \s_src1
2577     connect \Y $5
2578   end
2579   process $group_0
2580     assign \q_int$next \q_int
2581     assign \q_int$next $5
2582     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2583     switch \rst
2584       case 1'1
2585         assign \q_int$next 4'0000
2586     end
2587     sync init
2588       update \q_int 4'0000
2589     sync posedge \clk
2590       update \q_int \q_int$next
2591   end
2592   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2593   wire width 4 $7
2594   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2595   cell $not $8
2596     parameter \A_SIGNED 1'0
2597     parameter \A_WIDTH 3'100
2598     parameter \Y_WIDTH 3'100
2599     connect \A \r_src1
2600     connect \Y $7
2601   end
2602   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2603   wire width 4 $9
2604   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2605   cell $and $10
2606     parameter \A_SIGNED 1'0
2607     parameter \A_WIDTH 3'100
2608     parameter \B_SIGNED 1'0
2609     parameter \B_WIDTH 3'100
2610     parameter \Y_WIDTH 3'100
2611     connect \A \q_int
2612     connect \B $7
2613     connect \Y $9
2614   end
2615   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2616   wire width 4 $11
2617   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2618   cell $or $12
2619     parameter \A_SIGNED 1'0
2620     parameter \A_WIDTH 3'100
2621     parameter \B_SIGNED 1'0
2622     parameter \B_WIDTH 3'100
2623     parameter \Y_WIDTH 3'100
2624     connect \A $9
2625     connect \B \s_src1
2626     connect \Y $11
2627   end
2628   process $group_1
2629     assign \q_src1 4'0000
2630     assign \q_src1 $11
2631     sync init
2632   end
2633   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2634   wire width 4 \qn_src1
2635   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2636   wire width 4 $13
2637   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2638   cell $not $14
2639     parameter \A_SIGNED 1'0
2640     parameter \A_WIDTH 3'100
2641     parameter \Y_WIDTH 3'100
2642     connect \A \q_src1
2643     connect \Y $13
2644   end
2645   process $group_2
2646     assign \qn_src1 4'0000
2647     assign \qn_src1 $13
2648     sync init
2649   end
2650   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2651   wire width 4 $15
2652   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2653   cell $or $16
2654     parameter \A_SIGNED 1'0
2655     parameter \A_WIDTH 3'100
2656     parameter \B_SIGNED 1'0
2657     parameter \B_WIDTH 3'100
2658     parameter \Y_WIDTH 3'100
2659     connect \A \q_src1
2660     connect \B \q_int
2661     connect \Y $15
2662   end
2663   process $group_3
2664     assign \qlq_src1 4'0000
2665     assign \qlq_src1 $15
2666     sync init
2667   end
2668 end
2669 attribute \generator "nMigen"
2670 attribute \nmigen.hierarchy "top.dr_fu2"
2671 module \dr_fu2
2672   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
2673   wire width 4 output 0 \dst1_fwd_o
2674   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
2675   wire width 4 output 1 \dst2_fwd_o
2676   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
2677   wire width 4 output 2 \src1_fwd_o
2678   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
2679   wire width 4 output 3 \src2_fwd_o
2680   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
2681   wire width 4 output 4 \dst1_rsel_o
2682   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
2683   wire width 4 output 5 \dst2_rsel_o
2684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
2685   wire width 4 output 6 \src1_rsel_o
2686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
2687   wire width 4 output 7 \src2_rsel_o
2688   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
2689   wire width 4 input 8 \rd_pend_i
2690   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
2691   wire width 4 input 9 \wr_pend_i
2692   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
2693   wire width 4 input 10 \dst1
2694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
2695   wire width 4 input 11 \dst2
2696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
2697   wire width 4 input 12 \src1
2698   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
2699   wire width 4 input 13 \src2
2700   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
2701   wire width 1 input 14 \issue_i
2702   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
2703   wire width 2 input 15 \go_rd_i
2704   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
2705   wire width 2 input 16 \go_wr_i
2706   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
2707   wire width 1 input 17 \go_die_i
2708   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2709   wire width 1 input 18 \rst
2710   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2711   wire width 1 input 19 \clk
2712   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
2713   wire width 4 output 20 \v_rd_rsel_o
2714   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
2715   wire width 4 output 21 \v_wr_rsel_o
2716   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2717   wire width 4 \dst1_c_r_dst0
2718   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2719   wire width 4 \dst1_c_s_dst0
2720   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2721   wire width 4 \dst1_c_q_dst0
2722   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2723   wire width 4 \dst1_c_qlq_dst0
2724   cell \dst1_c$5 \dst1_c
2725     connect \rst \rst
2726     connect \clk \clk
2727     connect \r_dst0 \dst1_c_r_dst0
2728     connect \s_dst0 \dst1_c_s_dst0
2729     connect \q_dst0 \dst1_c_q_dst0
2730     connect \qlq_dst0 \dst1_c_qlq_dst0
2731   end
2732   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2733   wire width 4 \dst2_c_r_dst1
2734   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2735   wire width 4 \dst2_c_s_dst1
2736   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2737   wire width 4 \dst2_c_q_dst1
2738   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2739   wire width 4 \dst2_c_qlq_dst1
2740   cell \dst2_c$6 \dst2_c
2741     connect \rst \rst
2742     connect \clk \clk
2743     connect \r_dst1 \dst2_c_r_dst1
2744     connect \s_dst1 \dst2_c_s_dst1
2745     connect \q_dst1 \dst2_c_q_dst1
2746     connect \qlq_dst1 \dst2_c_qlq_dst1
2747   end
2748   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2749   wire width 4 \src1_c_r_src0
2750   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2751   wire width 4 \src1_c_s_src0
2752   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2753   wire width 4 \src1_c_q_src0
2754   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2755   wire width 4 \src1_c_qlq_src0
2756   cell \src1_c$7 \src1_c
2757     connect \rst \rst
2758     connect \clk \clk
2759     connect \r_src0 \src1_c_r_src0
2760     connect \s_src0 \src1_c_s_src0
2761     connect \q_src0 \src1_c_q_src0
2762     connect \qlq_src0 \src1_c_qlq_src0
2763   end
2764   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2765   wire width 4 \src2_c_r_src1
2766   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2767   wire width 4 \src2_c_s_src1
2768   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2769   wire width 4 \src2_c_q_src1
2770   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2771   wire width 4 \src2_c_qlq_src1
2772   cell \src2_c$8 \src2_c
2773     connect \rst \rst
2774     connect \clk \clk
2775     connect \r_src1 \src2_c_r_src1
2776     connect \s_src1 \src2_c_s_src1
2777     connect \q_src1 \src2_c_q_src1
2778     connect \qlq_src1 \src2_c_qlq_src1
2779   end
2780   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
2781   wire width 4 \wdi0
2782   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
2783   wire width 4 $1
2784   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
2785   cell $or $2
2786     parameter \A_SIGNED 1'0
2787     parameter \A_WIDTH 3'100
2788     parameter \B_SIGNED 1'0
2789     parameter \B_WIDTH 3'100
2790     parameter \Y_WIDTH 3'100
2791     connect \A { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
2792     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
2793     connect \Y $1
2794   end
2795   process $group_0
2796     assign \wdi0 4'0000
2797     assign \wdi0 $1
2798     sync init
2799   end
2800   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:107"
2801   wire width 4 \wdi1
2802   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
2803   wire width 4 $3
2804   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:108"
2805   cell $or $4
2806     parameter \A_SIGNED 1'0
2807     parameter \A_WIDTH 3'100
2808     parameter \B_SIGNED 1'0
2809     parameter \B_WIDTH 3'100
2810     parameter \Y_WIDTH 3'100
2811     connect \A { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
2812     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
2813     connect \Y $3
2814   end
2815   process $group_1
2816     assign \wdi1 4'0000
2817     assign \wdi1 $3
2818     sync init
2819   end
2820   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
2821   wire width 4 \rdi0
2822   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
2823   wire width 4 $5
2824   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
2825   cell $or $6
2826     parameter \A_SIGNED 1'0
2827     parameter \A_WIDTH 3'100
2828     parameter \B_SIGNED 1'0
2829     parameter \B_WIDTH 3'100
2830     parameter \Y_WIDTH 3'100
2831     connect \A { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
2832     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
2833     connect \Y $5
2834   end
2835   process $group_2
2836     assign \rdi0 4'0000
2837     assign \rdi0 $5
2838     sync init
2839   end
2840   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:112"
2841   wire width 4 \rdi1
2842   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
2843   wire width 4 $7
2844   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:113"
2845   cell $or $8
2846     parameter \A_SIGNED 1'0
2847     parameter \A_WIDTH 3'100
2848     parameter \B_SIGNED 1'0
2849     parameter \B_WIDTH 3'100
2850     parameter \Y_WIDTH 3'100
2851     connect \A { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
2852     connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
2853     connect \Y $7
2854   end
2855   process $group_3
2856     assign \rdi1 4'0000
2857     assign \rdi1 $7
2858     sync init
2859   end
2860   process $group_4
2861     assign \src1_c_r_src0 4'1111
2862     assign \src1_c_r_src0 \rdi0
2863     sync init
2864   end
2865   process $group_5
2866     assign \src2_c_r_src1 4'1111
2867     assign \src2_c_r_src1 \rdi1
2868     sync init
2869   end
2870   process $group_6
2871     assign \dst1_c_r_dst0 4'1111
2872     assign \dst1_c_r_dst0 \wdi0
2873     sync init
2874   end
2875   process $group_7
2876     assign \dst2_c_r_dst1 4'1111
2877     assign \dst2_c_r_dst1 \wdi1
2878     sync init
2879   end
2880   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
2881   wire width 4 $9
2882   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
2883   cell $and $10
2884     parameter \A_SIGNED 1'0
2885     parameter \A_WIDTH 3'100
2886     parameter \B_SIGNED 1'0
2887     parameter \B_WIDTH 3'100
2888     parameter \Y_WIDTH 3'100
2889     connect \A { \issue_i \issue_i \issue_i \issue_i }
2890     connect \B \dst1
2891     connect \Y $9
2892   end
2893   process $group_8
2894     assign \dst1_c_s_dst0 4'0000
2895     assign \dst1_c_s_dst0 $9
2896     sync init
2897   end
2898   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
2899   wire width 4 $11
2900   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:123"
2901   cell $and $12
2902     parameter \A_SIGNED 1'0
2903     parameter \A_WIDTH 3'100
2904     parameter \B_SIGNED 1'0
2905     parameter \B_WIDTH 3'100
2906     parameter \Y_WIDTH 3'100
2907     connect \A { \issue_i \issue_i \issue_i \issue_i }
2908     connect \B \dst2
2909     connect \Y $11
2910   end
2911   process $group_9
2912     assign \dst2_c_s_dst1 4'0000
2913     assign \dst2_c_s_dst1 $11
2914     sync init
2915   end
2916   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
2917   wire width 4 $13
2918   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
2919   cell $and $14
2920     parameter \A_SIGNED 1'0
2921     parameter \A_WIDTH 3'100
2922     parameter \B_SIGNED 1'0
2923     parameter \B_WIDTH 3'100
2924     parameter \Y_WIDTH 3'100
2925     connect \A { \issue_i \issue_i \issue_i \issue_i }
2926     connect \B \src1
2927     connect \Y $13
2928   end
2929   process $group_10
2930     assign \src1_c_s_src0 4'0000
2931     assign \src1_c_s_src0 $13
2932     sync init
2933   end
2934   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
2935   wire width 4 $15
2936   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:125"
2937   cell $and $16
2938     parameter \A_SIGNED 1'0
2939     parameter \A_WIDTH 3'100
2940     parameter \B_SIGNED 1'0
2941     parameter \B_WIDTH 3'100
2942     parameter \Y_WIDTH 3'100
2943     connect \A { \issue_i \issue_i \issue_i \issue_i }
2944     connect \B \src2
2945     connect \Y $15
2946   end
2947   process $group_11
2948     assign \src2_c_s_src1 4'0000
2949     assign \src2_c_s_src1 $15
2950     sync init
2951   end
2952   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
2953   wire width 4 $17
2954   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
2955   cell $and $18
2956     parameter \A_SIGNED 1'0
2957     parameter \A_WIDTH 3'100
2958     parameter \B_SIGNED 1'0
2959     parameter \B_WIDTH 3'100
2960     parameter \Y_WIDTH 3'100
2961     connect \A \dst1_c_q_dst0
2962     connect \B \rd_pend_i
2963     connect \Y $17
2964   end
2965   process $group_12
2966     assign \dst1_fwd_o 4'0000
2967     assign \dst1_fwd_o $17
2968     sync init
2969   end
2970   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
2971   wire width 4 $19
2972   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:129"
2973   cell $and $20
2974     parameter \A_SIGNED 1'0
2975     parameter \A_WIDTH 3'100
2976     parameter \B_SIGNED 1'0
2977     parameter \B_WIDTH 3'100
2978     parameter \Y_WIDTH 3'100
2979     connect \A \dst2_c_q_dst1
2980     connect \B \rd_pend_i
2981     connect \Y $19
2982   end
2983   process $group_13
2984     assign \dst2_fwd_o 4'0000
2985     assign \dst2_fwd_o $19
2986     sync init
2987   end
2988   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
2989   wire width 4 $21
2990   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
2991   cell $and $22
2992     parameter \A_SIGNED 1'0
2993     parameter \A_WIDTH 3'100
2994     parameter \B_SIGNED 1'0
2995     parameter \B_WIDTH 3'100
2996     parameter \Y_WIDTH 3'100
2997     connect \A \src1_c_q_src0
2998     connect \B \wr_pend_i
2999     connect \Y $21
3000   end
3001   process $group_14
3002     assign \src1_fwd_o 4'0000
3003     assign \src1_fwd_o $21
3004     sync init
3005   end
3006   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
3007   wire width 4 $23
3008   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:131"
3009   cell $and $24
3010     parameter \A_SIGNED 1'0
3011     parameter \A_WIDTH 3'100
3012     parameter \B_SIGNED 1'0
3013     parameter \B_WIDTH 3'100
3014     parameter \Y_WIDTH 3'100
3015     connect \A \src2_c_q_src1
3016     connect \B \wr_pend_i
3017     connect \Y $23
3018   end
3019   process $group_15
3020     assign \src2_fwd_o 4'0000
3021     assign \src2_fwd_o $23
3022     sync init
3023   end
3024   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
3025   wire width 4 $25
3026   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
3027   cell $and $26
3028     parameter \A_SIGNED 1'0
3029     parameter \A_WIDTH 3'100
3030     parameter \B_SIGNED 1'0
3031     parameter \B_WIDTH 3'100
3032     parameter \Y_WIDTH 3'100
3033     connect \A \dst1_c_qlq_dst0
3034     connect \B { \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] \go_wr_i [0] }
3035     connect \Y $25
3036   end
3037   process $group_16
3038     assign \dst1_rsel_o 4'0000
3039     assign \dst1_rsel_o $25
3040     sync init
3041   end
3042   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
3043   wire width 4 $27
3044   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:136"
3045   cell $and $28
3046     parameter \A_SIGNED 1'0
3047     parameter \A_WIDTH 3'100
3048     parameter \B_SIGNED 1'0
3049     parameter \B_WIDTH 3'100
3050     parameter \Y_WIDTH 3'100
3051     connect \A \dst2_c_qlq_dst1
3052     connect \B { \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] \go_wr_i [1] }
3053     connect \Y $27
3054   end
3055   process $group_17
3056     assign \dst2_rsel_o 4'0000
3057     assign \dst2_rsel_o $27
3058     sync init
3059   end
3060   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
3061   wire width 4 $29
3062   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
3063   cell $and $30
3064     parameter \A_SIGNED 1'0
3065     parameter \A_WIDTH 3'100
3066     parameter \B_SIGNED 1'0
3067     parameter \B_WIDTH 3'100
3068     parameter \Y_WIDTH 3'100
3069     connect \A \src1_c_qlq_src0
3070     connect \B { \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] \go_rd_i [0] }
3071     connect \Y $29
3072   end
3073   process $group_18
3074     assign \src1_rsel_o 4'0000
3075     assign \src1_rsel_o $29
3076     sync init
3077   end
3078   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
3079   wire width 4 $31
3080   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:139"
3081   cell $and $32
3082     parameter \A_SIGNED 1'0
3083     parameter \A_WIDTH 3'100
3084     parameter \B_SIGNED 1'0
3085     parameter \B_WIDTH 3'100
3086     parameter \Y_WIDTH 3'100
3087     connect \A \src2_c_qlq_src1
3088     connect \B { \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] \go_rd_i [1] }
3089     connect \Y $31
3090   end
3091   process $group_19
3092     assign \src2_rsel_o 4'0000
3093     assign \src2_rsel_o $31
3094     sync init
3095   end
3096   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
3097   wire width 4 $33
3098   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:146"
3099   cell $or $34
3100     parameter \A_SIGNED 1'0
3101     parameter \A_WIDTH 3'100
3102     parameter \B_SIGNED 1'0
3103     parameter \B_WIDTH 3'100
3104     parameter \Y_WIDTH 3'100
3105     connect \A \src1_c_qlq_src0
3106     connect \B \src2_c_qlq_src1
3107     connect \Y $33
3108   end
3109   process $group_20
3110     assign \v_rd_rsel_o 4'0000
3111     assign \v_rd_rsel_o $33
3112     sync init
3113   end
3114   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
3115   wire width 4 $35
3116   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:150"
3117   cell $or $36
3118     parameter \A_SIGNED 1'0
3119     parameter \A_WIDTH 3'100
3120     parameter \B_SIGNED 1'0
3121     parameter \B_WIDTH 3'100
3122     parameter \Y_WIDTH 3'100
3123     connect \A \dst1_c_qlq_dst0
3124     connect \B \dst2_c_qlq_dst1
3125     connect \Y $35
3126   end
3127   process $group_21
3128     assign \v_wr_rsel_o 4'0000
3129     assign \v_wr_rsel_o $35
3130     sync init
3131   end
3132 end
3133 attribute \generator "nMigen"
3134 attribute \nmigen.hierarchy "top.fu_fu0"
3135 module \fu_fu0
3136   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
3137   wire width 1 output 0 \reg_wr_pend_o
3138   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
3139   wire width 1 output 1 \reg_rd_pend_o
3140   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
3141   wire width 4 input 2 \dfwd1_i
3142   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
3143   wire width 2 output 3 \reg_wr_dst_pend_o
3144   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
3145   wire width 4 input 4 \dfwd2_i
3146   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
3147   wire width 4 input 5 \sfwd1_i
3148   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
3149   wire width 2 output 6 \reg_rd_src_pend_o
3150   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
3151   wire width 4 input 7 \sfwd2_i
3152   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3153   wire width 1 $1
3154   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3155   cell $reduce_bool $2
3156     parameter \A_SIGNED 1'0
3157     parameter \A_WIDTH 3'100
3158     parameter \Y_WIDTH 1'1
3159     connect \A \sfwd1_i
3160     connect \Y $1
3161   end
3162   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3163   wire width 1 $3
3164   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3165   cell $reduce_bool $4
3166     parameter \A_SIGNED 1'0
3167     parameter \A_WIDTH 3'100
3168     parameter \Y_WIDTH 1'1
3169     connect \A \sfwd2_i
3170     connect \Y $3
3171   end
3172   process $group_0
3173     assign \reg_rd_src_pend_o 2'00
3174     assign \reg_rd_src_pend_o [0] $1
3175     assign \reg_rd_src_pend_o [1] $3
3176     sync init
3177   end
3178   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
3179   wire width 1 $5
3180   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
3181   cell $reduce_bool $6
3182     parameter \A_SIGNED 1'0
3183     parameter \A_WIDTH 2'10
3184     parameter \Y_WIDTH 1'1
3185     connect \A \reg_rd_src_pend_o
3186     connect \Y $5
3187   end
3188   process $group_1
3189     assign \reg_rd_pend_o 1'0
3190     assign \reg_rd_pend_o $5
3191     sync init
3192   end
3193   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3194   wire width 1 $7
3195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3196   cell $reduce_bool $8
3197     parameter \A_SIGNED 1'0
3198     parameter \A_WIDTH 3'100
3199     parameter \Y_WIDTH 1'1
3200     connect \A \dfwd1_i
3201     connect \Y $7
3202   end
3203   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3204   wire width 1 $9
3205   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3206   cell $reduce_bool $10
3207     parameter \A_SIGNED 1'0
3208     parameter \A_WIDTH 3'100
3209     parameter \Y_WIDTH 1'1
3210     connect \A \dfwd2_i
3211     connect \Y $9
3212   end
3213   process $group_2
3214     assign \reg_wr_dst_pend_o 2'00
3215     assign \reg_wr_dst_pend_o [0] $7
3216     assign \reg_wr_dst_pend_o [1] $9
3217     sync init
3218   end
3219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
3220   wire width 1 $11
3221   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
3222   cell $reduce_bool $12
3223     parameter \A_SIGNED 1'0
3224     parameter \A_WIDTH 2'10
3225     parameter \Y_WIDTH 1'1
3226     connect \A \reg_wr_dst_pend_o
3227     connect \Y $11
3228   end
3229   process $group_3
3230     assign \reg_wr_pend_o 1'0
3231     assign \reg_wr_pend_o $11
3232     sync init
3233   end
3234 end
3235 attribute \generator "nMigen"
3236 attribute \nmigen.hierarchy "top.fu_fu1"
3237 module \fu_fu1
3238   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
3239   wire width 1 output 0 \reg_wr_pend_o
3240   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
3241   wire width 1 output 1 \reg_rd_pend_o
3242   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
3243   wire width 4 input 2 \dfwd1_i
3244   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
3245   wire width 2 output 3 \reg_wr_dst_pend_o
3246   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
3247   wire width 4 input 4 \dfwd2_i
3248   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
3249   wire width 4 input 5 \sfwd1_i
3250   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
3251   wire width 2 output 6 \reg_rd_src_pend_o
3252   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
3253   wire width 4 input 7 \sfwd2_i
3254   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3255   wire width 1 $1
3256   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3257   cell $reduce_bool $2
3258     parameter \A_SIGNED 1'0
3259     parameter \A_WIDTH 3'100
3260     parameter \Y_WIDTH 1'1
3261     connect \A \sfwd1_i
3262     connect \Y $1
3263   end
3264   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3265   wire width 1 $3
3266   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3267   cell $reduce_bool $4
3268     parameter \A_SIGNED 1'0
3269     parameter \A_WIDTH 3'100
3270     parameter \Y_WIDTH 1'1
3271     connect \A \sfwd2_i
3272     connect \Y $3
3273   end
3274   process $group_0
3275     assign \reg_rd_src_pend_o 2'00
3276     assign \reg_rd_src_pend_o [0] $1
3277     assign \reg_rd_src_pend_o [1] $3
3278     sync init
3279   end
3280   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
3281   wire width 1 $5
3282   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
3283   cell $reduce_bool $6
3284     parameter \A_SIGNED 1'0
3285     parameter \A_WIDTH 2'10
3286     parameter \Y_WIDTH 1'1
3287     connect \A \reg_rd_src_pend_o
3288     connect \Y $5
3289   end
3290   process $group_1
3291     assign \reg_rd_pend_o 1'0
3292     assign \reg_rd_pend_o $5
3293     sync init
3294   end
3295   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3296   wire width 1 $7
3297   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3298   cell $reduce_bool $8
3299     parameter \A_SIGNED 1'0
3300     parameter \A_WIDTH 3'100
3301     parameter \Y_WIDTH 1'1
3302     connect \A \dfwd1_i
3303     connect \Y $7
3304   end
3305   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3306   wire width 1 $9
3307   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3308   cell $reduce_bool $10
3309     parameter \A_SIGNED 1'0
3310     parameter \A_WIDTH 3'100
3311     parameter \Y_WIDTH 1'1
3312     connect \A \dfwd2_i
3313     connect \Y $9
3314   end
3315   process $group_2
3316     assign \reg_wr_dst_pend_o 2'00
3317     assign \reg_wr_dst_pend_o [0] $7
3318     assign \reg_wr_dst_pend_o [1] $9
3319     sync init
3320   end
3321   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
3322   wire width 1 $11
3323   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
3324   cell $reduce_bool $12
3325     parameter \A_SIGNED 1'0
3326     parameter \A_WIDTH 2'10
3327     parameter \Y_WIDTH 1'1
3328     connect \A \reg_wr_dst_pend_o
3329     connect \Y $11
3330   end
3331   process $group_3
3332     assign \reg_wr_pend_o 1'0
3333     assign \reg_wr_pend_o $11
3334     sync init
3335   end
3336 end
3337 attribute \generator "nMigen"
3338 attribute \nmigen.hierarchy "top.fu_fu2"
3339 module \fu_fu2
3340   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
3341   wire width 1 output 0 \reg_wr_pend_o
3342   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
3343   wire width 1 output 1 \reg_rd_pend_o
3344   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
3345   wire width 4 input 2 \dfwd1_i
3346   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
3347   wire width 2 output 3 \reg_wr_dst_pend_o
3348   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
3349   wire width 4 input 4 \dfwd2_i
3350   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
3351   wire width 4 input 5 \sfwd1_i
3352   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
3353   wire width 2 output 6 \reg_rd_src_pend_o
3354   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
3355   wire width 4 input 7 \sfwd2_i
3356   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3357   wire width 1 $1
3358   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3359   cell $reduce_bool $2
3360     parameter \A_SIGNED 1'0
3361     parameter \A_WIDTH 3'100
3362     parameter \Y_WIDTH 1'1
3363     connect \A \sfwd1_i
3364     connect \Y $1
3365   end
3366   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3367   wire width 1 $3
3368   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:33"
3369   cell $reduce_bool $4
3370     parameter \A_SIGNED 1'0
3371     parameter \A_WIDTH 3'100
3372     parameter \Y_WIDTH 1'1
3373     connect \A \sfwd2_i
3374     connect \Y $3
3375   end
3376   process $group_0
3377     assign \reg_rd_src_pend_o 2'00
3378     assign \reg_rd_src_pend_o [0] $1
3379     assign \reg_rd_src_pend_o [1] $3
3380     sync init
3381   end
3382   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
3383   wire width 1 $5
3384   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:35"
3385   cell $reduce_bool $6
3386     parameter \A_SIGNED 1'0
3387     parameter \A_WIDTH 2'10
3388     parameter \Y_WIDTH 1'1
3389     connect \A \reg_rd_src_pend_o
3390     connect \Y $5
3391   end
3392   process $group_1
3393     assign \reg_rd_pend_o 1'0
3394     assign \reg_rd_pend_o $5
3395     sync init
3396   end
3397   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3398   wire width 1 $7
3399   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3400   cell $reduce_bool $8
3401     parameter \A_SIGNED 1'0
3402     parameter \A_WIDTH 3'100
3403     parameter \Y_WIDTH 1'1
3404     connect \A \dfwd1_i
3405     connect \Y $7
3406   end
3407   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3408   wire width 1 $9
3409   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:39"
3410   cell $reduce_bool $10
3411     parameter \A_SIGNED 1'0
3412     parameter \A_WIDTH 3'100
3413     parameter \Y_WIDTH 1'1
3414     connect \A \dfwd2_i
3415     connect \Y $9
3416   end
3417   process $group_2
3418     assign \reg_wr_dst_pend_o 2'00
3419     assign \reg_wr_dst_pend_o [0] $7
3420     assign \reg_wr_dst_pend_o [1] $9
3421     sync init
3422   end
3423   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
3424   wire width 1 $11
3425   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:40"
3426   cell $reduce_bool $12
3427     parameter \A_SIGNED 1'0
3428     parameter \A_WIDTH 2'10
3429     parameter \Y_WIDTH 1'1
3430     connect \A \reg_wr_dst_pend_o
3431     connect \Y $11
3432   end
3433   process $group_3
3434     assign \reg_wr_pend_o 1'0
3435     assign \reg_wr_pend_o $11
3436     sync init
3437   end
3438 end
3439 attribute \generator "nMigen"
3440 attribute \nmigen.hierarchy "top.rr_r0"
3441 module \rr_r0
3442   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3443   wire width 3 input 0 \dst_rsel_i
3444   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3445   wire width 3 input 1 \dst_rsel_i$1
3446   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
3447   wire width 2 output 2 \dest_rsel_o
3448   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3449   wire width 3 input 3 \src_rsel_i
3450   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
3451   wire width 2 output 4 \src_rsel_o
3452   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3453   wire width 3 input 5 \src_rsel_i$2
3454   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3455   wire width 1 $3
3456   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3457   cell $reduce_bool $4
3458     parameter \A_SIGNED 1'0
3459     parameter \A_WIDTH 2'11
3460     parameter \Y_WIDTH 1'1
3461     connect \A \dst_rsel_i
3462     connect \Y $3
3463   end
3464   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3465   wire width 1 $5
3466   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3467   cell $reduce_bool $6
3468     parameter \A_SIGNED 1'0
3469     parameter \A_WIDTH 2'11
3470     parameter \Y_WIDTH 1'1
3471     connect \A \dst_rsel_i$1
3472     connect \Y $5
3473   end
3474   process $group_0
3475     assign \dest_rsel_o 2'00
3476     assign \dest_rsel_o [0] $3
3477     assign \dest_rsel_o [1] $5
3478     sync init
3479   end
3480   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3481   wire width 1 $7
3482   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3483   cell $reduce_bool $8
3484     parameter \A_SIGNED 1'0
3485     parameter \A_WIDTH 2'11
3486     parameter \Y_WIDTH 1'1
3487     connect \A \src_rsel_i
3488     connect \Y $7
3489   end
3490   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3491   wire width 1 $9
3492   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3493   cell $reduce_bool $10
3494     parameter \A_SIGNED 1'0
3495     parameter \A_WIDTH 2'11
3496     parameter \Y_WIDTH 1'1
3497     connect \A \src_rsel_i$2
3498     connect \Y $9
3499   end
3500   process $group_1
3501     assign \src_rsel_o 2'00
3502     assign \src_rsel_o [0] $7
3503     assign \src_rsel_o [1] $9
3504     sync init
3505   end
3506 end
3507 attribute \generator "nMigen"
3508 attribute \nmigen.hierarchy "top.rr_r1"
3509 module \rr_r1
3510   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3511   wire width 3 input 0 \dst_rsel_i
3512   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3513   wire width 3 input 1 \dst_rsel_i$1
3514   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
3515   wire width 2 output 2 \dest_rsel_o
3516   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3517   wire width 3 input 3 \src_rsel_i
3518   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
3519   wire width 2 output 4 \src_rsel_o
3520   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3521   wire width 3 input 5 \src_rsel_i$2
3522   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3523   wire width 1 $3
3524   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3525   cell $reduce_bool $4
3526     parameter \A_SIGNED 1'0
3527     parameter \A_WIDTH 2'11
3528     parameter \Y_WIDTH 1'1
3529     connect \A \dst_rsel_i
3530     connect \Y $3
3531   end
3532   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3533   wire width 1 $5
3534   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3535   cell $reduce_bool $6
3536     parameter \A_SIGNED 1'0
3537     parameter \A_WIDTH 2'11
3538     parameter \Y_WIDTH 1'1
3539     connect \A \dst_rsel_i$1
3540     connect \Y $5
3541   end
3542   process $group_0
3543     assign \dest_rsel_o 2'00
3544     assign \dest_rsel_o [0] $3
3545     assign \dest_rsel_o [1] $5
3546     sync init
3547   end
3548   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3549   wire width 1 $7
3550   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3551   cell $reduce_bool $8
3552     parameter \A_SIGNED 1'0
3553     parameter \A_WIDTH 2'11
3554     parameter \Y_WIDTH 1'1
3555     connect \A \src_rsel_i
3556     connect \Y $7
3557   end
3558   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3559   wire width 1 $9
3560   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3561   cell $reduce_bool $10
3562     parameter \A_SIGNED 1'0
3563     parameter \A_WIDTH 2'11
3564     parameter \Y_WIDTH 1'1
3565     connect \A \src_rsel_i$2
3566     connect \Y $9
3567   end
3568   process $group_1
3569     assign \src_rsel_o 2'00
3570     assign \src_rsel_o [0] $7
3571     assign \src_rsel_o [1] $9
3572     sync init
3573   end
3574 end
3575 attribute \generator "nMigen"
3576 attribute \nmigen.hierarchy "top.rr_r2"
3577 module \rr_r2
3578   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3579   wire width 3 input 0 \dst_rsel_i
3580   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3581   wire width 3 input 1 \dst_rsel_i$1
3582   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
3583   wire width 2 output 2 \dest_rsel_o
3584   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3585   wire width 3 input 3 \src_rsel_i
3586   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
3587   wire width 2 output 4 \src_rsel_o
3588   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3589   wire width 3 input 5 \src_rsel_i$2
3590   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3591   wire width 1 $3
3592   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3593   cell $reduce_bool $4
3594     parameter \A_SIGNED 1'0
3595     parameter \A_WIDTH 2'11
3596     parameter \Y_WIDTH 1'1
3597     connect \A \dst_rsel_i
3598     connect \Y $3
3599   end
3600   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3601   wire width 1 $5
3602   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3603   cell $reduce_bool $6
3604     parameter \A_SIGNED 1'0
3605     parameter \A_WIDTH 2'11
3606     parameter \Y_WIDTH 1'1
3607     connect \A \dst_rsel_i$1
3608     connect \Y $5
3609   end
3610   process $group_0
3611     assign \dest_rsel_o 2'00
3612     assign \dest_rsel_o [0] $3
3613     assign \dest_rsel_o [1] $5
3614     sync init
3615   end
3616   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3617   wire width 1 $7
3618   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3619   cell $reduce_bool $8
3620     parameter \A_SIGNED 1'0
3621     parameter \A_WIDTH 2'11
3622     parameter \Y_WIDTH 1'1
3623     connect \A \src_rsel_i
3624     connect \Y $7
3625   end
3626   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3627   wire width 1 $9
3628   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3629   cell $reduce_bool $10
3630     parameter \A_SIGNED 1'0
3631     parameter \A_WIDTH 2'11
3632     parameter \Y_WIDTH 1'1
3633     connect \A \src_rsel_i$2
3634     connect \Y $9
3635   end
3636   process $group_1
3637     assign \src_rsel_o 2'00
3638     assign \src_rsel_o [0] $7
3639     assign \src_rsel_o [1] $9
3640     sync init
3641   end
3642 end
3643 attribute \generator "nMigen"
3644 attribute \nmigen.hierarchy "top.rr_r3"
3645 module \rr_r3
3646   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3647   wire width 3 input 0 \dst_rsel_i
3648   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
3649   wire width 3 input 1 \dst_rsel_i$1
3650   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
3651   wire width 2 output 2 \dest_rsel_o
3652   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3653   wire width 3 input 3 \src_rsel_i
3654   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
3655   wire width 2 output 4 \src_rsel_o
3656   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
3657   wire width 3 input 5 \src_rsel_i$2
3658   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3659   wire width 1 $3
3660   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3661   cell $reduce_bool $4
3662     parameter \A_SIGNED 1'0
3663     parameter \A_WIDTH 2'11
3664     parameter \Y_WIDTH 1'1
3665     connect \A \dst_rsel_i
3666     connect \Y $3
3667   end
3668   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3669   wire width 1 $5
3670   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:24"
3671   cell $reduce_bool $6
3672     parameter \A_SIGNED 1'0
3673     parameter \A_WIDTH 2'11
3674     parameter \Y_WIDTH 1'1
3675     connect \A \dst_rsel_i$1
3676     connect \Y $5
3677   end
3678   process $group_0
3679     assign \dest_rsel_o 2'00
3680     assign \dest_rsel_o [0] $3
3681     assign \dest_rsel_o [1] $5
3682     sync init
3683   end
3684   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3685   wire width 1 $7
3686   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3687   cell $reduce_bool $8
3688     parameter \A_SIGNED 1'0
3689     parameter \A_WIDTH 2'11
3690     parameter \Y_WIDTH 1'1
3691     connect \A \src_rsel_i
3692     connect \Y $7
3693   end
3694   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3695   wire width 1 $9
3696   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:26"
3697   cell $reduce_bool $10
3698     parameter \A_SIGNED 1'0
3699     parameter \A_WIDTH 2'11
3700     parameter \Y_WIDTH 1'1
3701     connect \A \src_rsel_i$2
3702     connect \Y $9
3703   end
3704   process $group_1
3705     assign \src_rsel_o 2'00
3706     assign \src_rsel_o [0] $7
3707     assign \src_rsel_o [1] $9
3708     sync init
3709   end
3710 end
3711 attribute \generator "nMigen"
3712 attribute \nmigen.hierarchy "top.rd_v"
3713 module \rd_v
3714   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
3715   wire width 4 output 0 \g_pend_o
3716   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
3717   wire width 4 input 1 \v_rd_rsel_o
3718   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
3719   wire width 4 input 2 \v_rd_rsel_o$1
3720   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
3721   wire width 4 input 3 \v_rd_rsel_o$2
3722   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3723   wire width 1 $3
3724   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3725   cell $reduce_bool $4
3726     parameter \A_SIGNED 1'0
3727     parameter \A_WIDTH 2'11
3728     parameter \Y_WIDTH 1'1
3729     connect \A { \v_rd_rsel_o$2 [0] \v_rd_rsel_o$1 [0] \v_rd_rsel_o [0] }
3730     connect \Y $3
3731   end
3732   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3733   wire width 1 $5
3734   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3735   cell $reduce_bool $6
3736     parameter \A_SIGNED 1'0
3737     parameter \A_WIDTH 2'11
3738     parameter \Y_WIDTH 1'1
3739     connect \A { \v_rd_rsel_o$2 [1] \v_rd_rsel_o$1 [1] \v_rd_rsel_o [1] }
3740     connect \Y $5
3741   end
3742   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3743   wire width 1 $7
3744   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3745   cell $reduce_bool $8
3746     parameter \A_SIGNED 1'0
3747     parameter \A_WIDTH 2'11
3748     parameter \Y_WIDTH 1'1
3749     connect \A { \v_rd_rsel_o$2 [2] \v_rd_rsel_o$1 [2] \v_rd_rsel_o [2] }
3750     connect \Y $7
3751   end
3752   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3753   wire width 1 $9
3754   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3755   cell $reduce_bool $10
3756     parameter \A_SIGNED 1'0
3757     parameter \A_WIDTH 2'11
3758     parameter \Y_WIDTH 1'1
3759     connect \A { \v_rd_rsel_o$2 [3] \v_rd_rsel_o$1 [3] \v_rd_rsel_o [3] }
3760     connect \Y $9
3761   end
3762   process $group_0
3763     assign \g_pend_o 4'0000
3764     assign \g_pend_o { $9 $7 $5 $3 }
3765     sync init
3766   end
3767 end
3768 attribute \generator "nMigen"
3769 attribute \nmigen.hierarchy "top.wr_v"
3770 module \wr_v
3771   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
3772   wire width 4 output 0 \g_pend_o
3773   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
3774   wire width 4 input 1 \v_wr_rsel_o
3775   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
3776   wire width 4 input 2 \v_wr_rsel_o$1
3777   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
3778   wire width 4 input 3 \v_wr_rsel_o$2
3779   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3780   wire width 1 $3
3781   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3782   cell $reduce_bool $4
3783     parameter \A_SIGNED 1'0
3784     parameter \A_WIDTH 2'11
3785     parameter \Y_WIDTH 1'1
3786     connect \A { \v_wr_rsel_o$2 [0] \v_wr_rsel_o$1 [0] \v_wr_rsel_o [0] }
3787     connect \Y $3
3788   end
3789   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3790   wire width 1 $5
3791   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3792   cell $reduce_bool $6
3793     parameter \A_SIGNED 1'0
3794     parameter \A_WIDTH 2'11
3795     parameter \Y_WIDTH 1'1
3796     connect \A { \v_wr_rsel_o$2 [1] \v_wr_rsel_o$1 [1] \v_wr_rsel_o [1] }
3797     connect \Y $5
3798   end
3799   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3800   wire width 1 $7
3801   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3802   cell $reduce_bool $8
3803     parameter \A_SIGNED 1'0
3804     parameter \A_WIDTH 2'11
3805     parameter \Y_WIDTH 1'1
3806     connect \A { \v_wr_rsel_o$2 [2] \v_wr_rsel_o$1 [2] \v_wr_rsel_o [2] }
3807     connect \Y $7
3808   end
3809   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3810   wire width 1 $9
3811   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:45"
3812   cell $reduce_bool $10
3813     parameter \A_SIGNED 1'0
3814     parameter \A_WIDTH 2'11
3815     parameter \Y_WIDTH 1'1
3816     connect \A { \v_wr_rsel_o$2 [3] \v_wr_rsel_o$1 [3] \v_wr_rsel_o [3] }
3817     connect \Y $9
3818   end
3819   process $group_0
3820     assign \g_pend_o 4'0000
3821     assign \g_pend_o { $9 $7 $5 $3 }
3822     sync init
3823   end
3824 end
3825 attribute \generator "nMigen"
3826 attribute \top 1
3827 attribute \nmigen.hierarchy "top"
3828 module \test_fu_reg_matrix
3829   attribute \src "scoremulti/fu_reg_matrix.py:51"
3830   wire width 4 input 0 \dst1
3831   attribute \src "scoremulti/fu_reg_matrix.py:51"
3832   wire width 4 input 1 \dst2
3833   attribute \src "scoremulti/fu_reg_matrix.py:43"
3834   wire width 4 input 2 \src1
3835   attribute \src "scoremulti/fu_reg_matrix.py:43"
3836   wire width 4 input 3 \src2
3837   attribute \src "scoremulti/fu_reg_matrix.py:73"
3838   wire width 3 input 4 \issue_i
3839   attribute \src "scoremulti/fu_reg_matrix.py:53"
3840   wire width 3 input 5 \gowr1_i
3841   attribute \src "scoremulti/fu_reg_matrix.py:53"
3842   wire width 3 input 6 \gowr2_i
3843   attribute \src "scoremulti/fu_reg_matrix.py:45"
3844   wire width 3 input 7 \gord1_i
3845   attribute \src "scoremulti/fu_reg_matrix.py:45"
3846   wire width 3 input 8 \gord2_i
3847   attribute \src "scoremulti/fu_reg_matrix.py:76"
3848   wire width 3 input 9 \go_die_i
3849   attribute \src "scoremulti/fu_reg_matrix.py:52"
3850   wire width 4 input 10 \dst1_rsel_o
3851   attribute \src "scoremulti/fu_reg_matrix.py:52"
3852   wire width 4 output 11 \dst2_rsel_o
3853   attribute \src "scoremulti/fu_reg_matrix.py:44"
3854   wire width 4 output 12 \src1_rsel_o
3855   attribute \src "scoremulti/fu_reg_matrix.py:44"
3856   wire width 4 output 13 \src2_rsel_o
3857   attribute \src "scoremulti/fu_reg_matrix.py:89"
3858   wire width 3 output 14 \wr_pend_o
3859   attribute \src "scoremulti/fu_reg_matrix.py:90"
3860   wire width 3 output 15 \rd_pend_o
3861   attribute \src "scoremulti/fu_reg_matrix.py:68"
3862   wire width 4 input 16 \wr_pend_i
3863   attribute \src "scoremulti/fu_reg_matrix.py:69"
3864   wire width 4 input 17 \rd_pend_i
3865   attribute \src "scoremulti/fu_reg_matrix.py:70"
3866   wire width 4 output 18 \v_wr_rsel_o
3867   attribute \src "scoremulti/fu_reg_matrix.py:71"
3868   wire width 4 output 19 \v_rd_rsel_o
3869   attribute \src "scoremulti/fu_reg_matrix.py:58"
3870   wire width 3 output 20 \rd_src1_pend_o
3871   attribute \src "scoremulti/fu_reg_matrix.py:58"
3872   wire width 3 output 21 \rd_src2_pend_o
3873   attribute \src "scoremulti/fu_reg_matrix.py:58"
3874   wire width 3 input 22 \rd_src3_pend_o
3875   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3876   wire width 1 input 23 \clk
3877   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3878   wire width 1 input 24 \rst
3879   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
3880   wire width 4 \dr_fu0_dst1_fwd_o
3881   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
3882   wire width 4 \dr_fu0_dst2_fwd_o
3883   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
3884   wire width 4 \dr_fu0_src1_fwd_o
3885   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
3886   wire width 4 \dr_fu0_src2_fwd_o
3887   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
3888   wire width 4 \dr_fu0_dst1_rsel_o
3889   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
3890   wire width 4 \dr_fu0_dst2_rsel_o
3891   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
3892   wire width 4 \dr_fu0_src1_rsel_o
3893   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
3894   wire width 4 \dr_fu0_src2_rsel_o
3895   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
3896   wire width 4 \dr_fu0_rd_pend_i
3897   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
3898   wire width 4 \dr_fu0_wr_pend_i
3899   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
3900   wire width 4 \dr_fu0_dst1
3901   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
3902   wire width 4 \dr_fu0_dst2
3903   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
3904   wire width 4 \dr_fu0_src1
3905   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
3906   wire width 4 \dr_fu0_src2
3907   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
3908   wire width 1 \dr_fu0_issue_i
3909   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
3910   wire width 2 \dr_fu0_go_rd_i
3911   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
3912   wire width 2 \dr_fu0_go_wr_i
3913   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
3914   wire width 1 \dr_fu0_go_die_i
3915   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
3916   wire width 4 \dr_fu0_v_rd_rsel_o
3917   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
3918   wire width 4 \dr_fu0_v_wr_rsel_o
3919   cell \dr_fu0 \dr_fu0
3920     connect \dst1_fwd_o \dr_fu0_dst1_fwd_o
3921     connect \dst2_fwd_o \dr_fu0_dst2_fwd_o
3922     connect \src1_fwd_o \dr_fu0_src1_fwd_o
3923     connect \src2_fwd_o \dr_fu0_src2_fwd_o
3924     connect \dst1_rsel_o \dr_fu0_dst1_rsel_o
3925     connect \dst2_rsel_o \dr_fu0_dst2_rsel_o
3926     connect \src1_rsel_o \dr_fu0_src1_rsel_o
3927     connect \src2_rsel_o \dr_fu0_src2_rsel_o
3928     connect \rd_pend_i \dr_fu0_rd_pend_i
3929     connect \wr_pend_i \dr_fu0_wr_pend_i
3930     connect \dst1 \dr_fu0_dst1
3931     connect \dst2 \dr_fu0_dst2
3932     connect \src1 \dr_fu0_src1
3933     connect \src2 \dr_fu0_src2
3934     connect \issue_i \dr_fu0_issue_i
3935     connect \go_rd_i \dr_fu0_go_rd_i
3936     connect \go_wr_i \dr_fu0_go_wr_i
3937     connect \go_die_i \dr_fu0_go_die_i
3938     connect \v_rd_rsel_o \dr_fu0_v_rd_rsel_o
3939     connect \v_wr_rsel_o \dr_fu0_v_wr_rsel_o
3940     connect \rst \rst
3941     connect \clk \clk
3942   end
3943   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
3944   wire width 4 \dr_fu1_dst1_fwd_o
3945   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
3946   wire width 4 \dr_fu1_dst2_fwd_o
3947   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
3948   wire width 4 \dr_fu1_src1_fwd_o
3949   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
3950   wire width 4 \dr_fu1_src2_fwd_o
3951   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
3952   wire width 4 \dr_fu1_dst1_rsel_o
3953   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
3954   wire width 4 \dr_fu1_dst2_rsel_o
3955   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
3956   wire width 4 \dr_fu1_src1_rsel_o
3957   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
3958   wire width 4 \dr_fu1_src2_rsel_o
3959   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
3960   wire width 4 \dr_fu1_rd_pend_i
3961   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
3962   wire width 4 \dr_fu1_wr_pend_i
3963   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
3964   wire width 4 \dr_fu1_dst1
3965   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
3966   wire width 4 \dr_fu1_dst2
3967   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
3968   wire width 4 \dr_fu1_src1
3969   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
3970   wire width 4 \dr_fu1_src2
3971   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
3972   wire width 1 \dr_fu1_issue_i
3973   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
3974   wire width 2 \dr_fu1_go_rd_i
3975   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
3976   wire width 2 \dr_fu1_go_wr_i
3977   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
3978   wire width 1 \dr_fu1_go_die_i
3979   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
3980   wire width 4 \dr_fu1_v_rd_rsel_o
3981   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
3982   wire width 4 \dr_fu1_v_wr_rsel_o
3983   cell \dr_fu1 \dr_fu1
3984     connect \dst1_fwd_o \dr_fu1_dst1_fwd_o
3985     connect \dst2_fwd_o \dr_fu1_dst2_fwd_o
3986     connect \src1_fwd_o \dr_fu1_src1_fwd_o
3987     connect \src2_fwd_o \dr_fu1_src2_fwd_o
3988     connect \dst1_rsel_o \dr_fu1_dst1_rsel_o
3989     connect \dst2_rsel_o \dr_fu1_dst2_rsel_o
3990     connect \src1_rsel_o \dr_fu1_src1_rsel_o
3991     connect \src2_rsel_o \dr_fu1_src2_rsel_o
3992     connect \rd_pend_i \dr_fu1_rd_pend_i
3993     connect \wr_pend_i \dr_fu1_wr_pend_i
3994     connect \dst1 \dr_fu1_dst1
3995     connect \dst2 \dr_fu1_dst2
3996     connect \src1 \dr_fu1_src1
3997     connect \src2 \dr_fu1_src2
3998     connect \issue_i \dr_fu1_issue_i
3999     connect \go_rd_i \dr_fu1_go_rd_i
4000     connect \go_wr_i \dr_fu1_go_wr_i
4001     connect \go_die_i \dr_fu1_go_die_i
4002     connect \rst \rst
4003     connect \clk \clk
4004     connect \v_rd_rsel_o \dr_fu1_v_rd_rsel_o
4005     connect \v_wr_rsel_o \dr_fu1_v_wr_rsel_o
4006   end
4007   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
4008   wire width 4 \dr_fu2_dst1_fwd_o
4009   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:55"
4010   wire width 4 \dr_fu2_dst2_fwd_o
4011   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
4012   wire width 4 \dr_fu2_src1_fwd_o
4013   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:45"
4014   wire width 4 \dr_fu2_src2_fwd_o
4015   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
4016   wire width 4 \dr_fu2_dst1_rsel_o
4017   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:54"
4018   wire width 4 \dr_fu2_dst2_rsel_o
4019   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
4020   wire width 4 \dr_fu2_src1_rsel_o
4021   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:44"
4022   wire width 4 \dr_fu2_src2_rsel_o
4023   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:62"
4024   wire width 4 \dr_fu2_rd_pend_i
4025   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:63"
4026   wire width 4 \dr_fu2_wr_pend_i
4027   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
4028   wire width 4 \dr_fu2_dst1
4029   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:53"
4030   wire width 4 \dr_fu2_dst2
4031   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
4032   wire width 4 \dr_fu2_src1
4033   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:43"
4034   wire width 4 \dr_fu2_src2
4035   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:60"
4036   wire width 1 \dr_fu2_issue_i
4037   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:68"
4038   wire width 2 \dr_fu2_go_rd_i
4039   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:67"
4040   wire width 2 \dr_fu2_go_wr_i
4041   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:73"
4042   wire width 1 \dr_fu2_go_die_i
4043   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:64"
4044   wire width 4 \dr_fu2_v_rd_rsel_o
4045   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/dependence_cell.py:65"
4046   wire width 4 \dr_fu2_v_wr_rsel_o
4047   cell \dr_fu2 \dr_fu2
4048     connect \dst1_fwd_o \dr_fu2_dst1_fwd_o
4049     connect \dst2_fwd_o \dr_fu2_dst2_fwd_o
4050     connect \src1_fwd_o \dr_fu2_src1_fwd_o
4051     connect \src2_fwd_o \dr_fu2_src2_fwd_o
4052     connect \dst1_rsel_o \dr_fu2_dst1_rsel_o
4053     connect \dst2_rsel_o \dr_fu2_dst2_rsel_o
4054     connect \src1_rsel_o \dr_fu2_src1_rsel_o
4055     connect \src2_rsel_o \dr_fu2_src2_rsel_o
4056     connect \rd_pend_i \dr_fu2_rd_pend_i
4057     connect \wr_pend_i \dr_fu2_wr_pend_i
4058     connect \dst1 \dr_fu2_dst1
4059     connect \dst2 \dr_fu2_dst2
4060     connect \src1 \dr_fu2_src1
4061     connect \src2 \dr_fu2_src2
4062     connect \issue_i \dr_fu2_issue_i
4063     connect \go_rd_i \dr_fu2_go_rd_i
4064     connect \go_wr_i \dr_fu2_go_wr_i
4065     connect \go_die_i \dr_fu2_go_die_i
4066     connect \rst \rst
4067     connect \clk \clk
4068     connect \v_rd_rsel_o \dr_fu2_v_rd_rsel_o
4069     connect \v_wr_rsel_o \dr_fu2_v_wr_rsel_o
4070   end
4071   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
4072   wire width 1 \fu_fu0_reg_wr_pend_o
4073   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
4074   wire width 1 \fu_fu0_reg_rd_pend_o
4075   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
4076   wire width 4 \fu_fu0_dfwd1_i
4077   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
4078   wire width 2 \fu_fu0_reg_wr_dst_pend_o
4079   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
4080   wire width 4 \fu_fu0_dfwd2_i
4081   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
4082   wire width 4 \fu_fu0_sfwd1_i
4083   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
4084   wire width 2 \fu_fu0_reg_rd_src_pend_o
4085   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
4086   wire width 4 \fu_fu0_sfwd2_i
4087   cell \fu_fu0 \fu_fu0
4088     connect \reg_wr_pend_o \fu_fu0_reg_wr_pend_o
4089     connect \reg_rd_pend_o \fu_fu0_reg_rd_pend_o
4090     connect \dfwd1_i \fu_fu0_dfwd1_i
4091     connect \reg_wr_dst_pend_o \fu_fu0_reg_wr_dst_pend_o
4092     connect \dfwd2_i \fu_fu0_dfwd2_i
4093     connect \sfwd1_i \fu_fu0_sfwd1_i
4094     connect \reg_rd_src_pend_o \fu_fu0_reg_rd_src_pend_o
4095     connect \sfwd2_i \fu_fu0_sfwd2_i
4096   end
4097   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
4098   wire width 1 \fu_fu1_reg_wr_pend_o
4099   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
4100   wire width 1 \fu_fu1_reg_rd_pend_o
4101   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
4102   wire width 4 \fu_fu1_dfwd1_i
4103   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
4104   wire width 2 \fu_fu1_reg_wr_dst_pend_o
4105   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
4106   wire width 4 \fu_fu1_dfwd2_i
4107   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
4108   wire width 4 \fu_fu1_sfwd1_i
4109   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
4110   wire width 2 \fu_fu1_reg_rd_src_pend_o
4111   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
4112   wire width 4 \fu_fu1_sfwd2_i
4113   cell \fu_fu1 \fu_fu1
4114     connect \reg_wr_pend_o \fu_fu1_reg_wr_pend_o
4115     connect \reg_rd_pend_o \fu_fu1_reg_rd_pend_o
4116     connect \dfwd1_i \fu_fu1_dfwd1_i
4117     connect \reg_wr_dst_pend_o \fu_fu1_reg_wr_dst_pend_o
4118     connect \dfwd2_i \fu_fu1_dfwd2_i
4119     connect \sfwd1_i \fu_fu1_sfwd1_i
4120     connect \reg_rd_src_pend_o \fu_fu1_reg_rd_src_pend_o
4121     connect \sfwd2_i \fu_fu1_sfwd2_i
4122   end
4123   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:23"
4124   wire width 1 \fu_fu2_reg_wr_pend_o
4125   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:24"
4126   wire width 1 \fu_fu2_reg_rd_pend_o
4127   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
4128   wire width 4 \fu_fu2_dfwd1_i
4129   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:26"
4130   wire width 2 \fu_fu2_reg_wr_dst_pend_o
4131   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:15"
4132   wire width 4 \fu_fu2_dfwd2_i
4133   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
4134   wire width 4 \fu_fu2_sfwd1_i
4135   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:25"
4136   wire width 2 \fu_fu2_reg_rd_src_pend_o
4137   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_wr_pending.py:20"
4138   wire width 4 \fu_fu2_sfwd2_i
4139   cell \fu_fu2 \fu_fu2
4140     connect \reg_wr_pend_o \fu_fu2_reg_wr_pend_o
4141     connect \reg_rd_pend_o \fu_fu2_reg_rd_pend_o
4142     connect \dfwd1_i \fu_fu2_dfwd1_i
4143     connect \reg_wr_dst_pend_o \fu_fu2_reg_wr_dst_pend_o
4144     connect \dfwd2_i \fu_fu2_dfwd2_i
4145     connect \sfwd1_i \fu_fu2_sfwd1_i
4146     connect \reg_rd_src_pend_o \fu_fu2_reg_rd_src_pend_o
4147     connect \sfwd2_i \fu_fu2_sfwd2_i
4148   end
4149   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4150   wire width 3 \rr_r0_dst_rsel_i
4151   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4152   wire width 3 \rr_r0_dst_rsel_i$1
4153   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
4154   wire width 2 \rr_r0_dest_rsel_o
4155   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4156   wire width 3 \rr_r0_src_rsel_i
4157   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
4158   wire width 2 \rr_r0_src_rsel_o
4159   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4160   wire width 3 \rr_r0_src_rsel_i$2
4161   cell \rr_r0 \rr_r0
4162     connect \dst_rsel_i \rr_r0_dst_rsel_i
4163     connect \dst_rsel_i$1 \rr_r0_dst_rsel_i$1
4164     connect \dest_rsel_o \rr_r0_dest_rsel_o
4165     connect \src_rsel_i \rr_r0_src_rsel_i
4166     connect \src_rsel_o \rr_r0_src_rsel_o
4167     connect \src_rsel_i$2 \rr_r0_src_rsel_i$2
4168   end
4169   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4170   wire width 3 \rr_r1_dst_rsel_i
4171   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4172   wire width 3 \rr_r1_dst_rsel_i$3
4173   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
4174   wire width 2 \rr_r1_dest_rsel_o
4175   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4176   wire width 3 \rr_r1_src_rsel_i
4177   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
4178   wire width 2 \rr_r1_src_rsel_o
4179   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4180   wire width 3 \rr_r1_src_rsel_i$4
4181   cell \rr_r1 \rr_r1
4182     connect \dst_rsel_i \rr_r1_dst_rsel_i
4183     connect \dst_rsel_i$1 \rr_r1_dst_rsel_i$3
4184     connect \dest_rsel_o \rr_r1_dest_rsel_o
4185     connect \src_rsel_i \rr_r1_src_rsel_i
4186     connect \src_rsel_o \rr_r1_src_rsel_o
4187     connect \src_rsel_i$2 \rr_r1_src_rsel_i$4
4188   end
4189   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4190   wire width 3 \rr_r2_dst_rsel_i
4191   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4192   wire width 3 \rr_r2_dst_rsel_i$5
4193   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
4194   wire width 2 \rr_r2_dest_rsel_o
4195   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4196   wire width 3 \rr_r2_src_rsel_i
4197   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
4198   wire width 2 \rr_r2_src_rsel_o
4199   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4200   wire width 3 \rr_r2_src_rsel_i$6
4201   cell \rr_r2 \rr_r2
4202     connect \dst_rsel_i \rr_r2_dst_rsel_i
4203     connect \dst_rsel_i$1 \rr_r2_dst_rsel_i$5
4204     connect \dest_rsel_o \rr_r2_dest_rsel_o
4205     connect \src_rsel_i \rr_r2_src_rsel_i
4206     connect \src_rsel_o \rr_r2_src_rsel_o
4207     connect \src_rsel_i$2 \rr_r2_src_rsel_i$6
4208   end
4209   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4210   wire width 3 \rr_r3_dst_rsel_i
4211   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:14"
4212   wire width 3 \rr_r3_dst_rsel_i$7
4213   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:18"
4214   wire width 2 \rr_r3_dest_rsel_o
4215   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4216   wire width 3 \rr_r3_src_rsel_i
4217   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:19"
4218   wire width 2 \rr_r3_src_rsel_o
4219   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/reg_sel.py:17"
4220   wire width 3 \rr_r3_src_rsel_i$8
4221   cell \rr_r3 \rr_r3
4222     connect \dst_rsel_i \rr_r3_dst_rsel_i
4223     connect \dst_rsel_i$1 \rr_r3_dst_rsel_i$7
4224     connect \dest_rsel_o \rr_r3_dest_rsel_o
4225     connect \src_rsel_i \rr_r3_src_rsel_i
4226     connect \src_rsel_o \rr_r3_src_rsel_o
4227     connect \src_rsel_i$2 \rr_r3_src_rsel_i$8
4228   end
4229   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
4230   wire width 4 \rd_v_g_pend_o
4231   cell \rd_v \rd_v
4232     connect \g_pend_o \rd_v_g_pend_o
4233     connect \v_rd_rsel_o \dr_fu0_v_rd_rsel_o
4234     connect \v_rd_rsel_o$1 \dr_fu1_v_rd_rsel_o
4235     connect \v_rd_rsel_o$2 \dr_fu2_v_rd_rsel_o
4236   end
4237   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/global_pending.py:35"
4238   wire width 4 \wr_v_g_pend_o
4239   cell \wr_v \wr_v
4240     connect \g_pend_o \wr_v_g_pend_o
4241     connect \v_wr_rsel_o \dr_fu0_v_wr_rsel_o
4242     connect \v_wr_rsel_o$1 \dr_fu1_v_wr_rsel_o
4243     connect \v_wr_rsel_o$2 \dr_fu2_v_wr_rsel_o
4244   end
4245   process $group_0
4246     assign \wr_pend_o 3'000
4247     assign \wr_pend_o { \fu_fu2_reg_wr_pend_o \fu_fu1_reg_wr_pend_o \fu_fu0_reg_wr_pend_o }
4248     sync init
4249   end
4250   process $group_1
4251     assign \rd_pend_o 3'000
4252     assign \rd_pend_o { \fu_fu2_reg_rd_pend_o \fu_fu1_reg_rd_pend_o \fu_fu0_reg_rd_pend_o }
4253     sync init
4254   end
4255   process $group_2
4256     assign \fu_fu0_dfwd1_i 4'0000
4257     assign \fu_fu0_dfwd1_i { \dr_fu0_dst1_fwd_o [3] \dr_fu0_dst1_fwd_o [2] \dr_fu0_dst1_fwd_o [1] \dr_fu0_dst1_fwd_o [0] }
4258     sync init
4259   end
4260   process $group_3
4261     assign \fu_fu1_dfwd1_i 4'0000
4262     assign \fu_fu1_dfwd1_i { \dr_fu1_dst1_fwd_o [3] \dr_fu1_dst1_fwd_o [2] \dr_fu1_dst1_fwd_o [1] \dr_fu1_dst1_fwd_o [0] }
4263     sync init
4264   end
4265   process $group_4
4266     assign \fu_fu2_dfwd1_i 4'0000
4267     assign \fu_fu2_dfwd1_i { \dr_fu2_dst1_fwd_o [3] \dr_fu2_dst1_fwd_o [2] \dr_fu2_dst1_fwd_o [1] \dr_fu2_dst1_fwd_o [0] }
4268     sync init
4269   end
4270   attribute \src "scoremulti/fu_reg_matrix.py:59"
4271   wire width 3 \wr_dst1_pend_o
4272   process $group_5
4273     assign \wr_dst1_pend_o 3'000
4274     assign \wr_dst1_pend_o { \fu_fu2_reg_wr_dst_pend_o [0] \fu_fu1_reg_wr_dst_pend_o [0] \fu_fu0_reg_wr_dst_pend_o [0] }
4275     sync init
4276   end
4277   process $group_6
4278     assign \fu_fu0_dfwd2_i 4'0000
4279     assign \fu_fu0_dfwd2_i { \dr_fu0_dst2_fwd_o [3] \dr_fu0_dst2_fwd_o [2] \dr_fu0_dst2_fwd_o [1] \dr_fu0_dst2_fwd_o [0] }
4280     sync init
4281   end
4282   process $group_7
4283     assign \fu_fu1_dfwd2_i 4'0000
4284     assign \fu_fu1_dfwd2_i { \dr_fu1_dst2_fwd_o [3] \dr_fu1_dst2_fwd_o [2] \dr_fu1_dst2_fwd_o [1] \dr_fu1_dst2_fwd_o [0] }
4285     sync init
4286   end
4287   process $group_8
4288     assign \fu_fu2_dfwd2_i 4'0000
4289     assign \fu_fu2_dfwd2_i { \dr_fu2_dst2_fwd_o [3] \dr_fu2_dst2_fwd_o [2] \dr_fu2_dst2_fwd_o [1] \dr_fu2_dst2_fwd_o [0] }
4290     sync init
4291   end
4292   attribute \src "scoremulti/fu_reg_matrix.py:59"
4293   wire width 3 \wr_dst2_pend_o
4294   process $group_9
4295     assign \wr_dst2_pend_o 3'000
4296     assign \wr_dst2_pend_o { \fu_fu2_reg_wr_dst_pend_o [1] \fu_fu1_reg_wr_dst_pend_o [1] \fu_fu0_reg_wr_dst_pend_o [1] }
4297     sync init
4298   end
4299   process $group_10
4300     assign \fu_fu0_sfwd1_i 4'0000
4301     assign \fu_fu0_sfwd1_i { \dr_fu0_src1_fwd_o [3] \dr_fu0_src1_fwd_o [2] \dr_fu0_src1_fwd_o [1] \dr_fu0_src1_fwd_o [0] }
4302     sync init
4303   end
4304   process $group_11
4305     assign \fu_fu1_sfwd1_i 4'0000
4306     assign \fu_fu1_sfwd1_i { \dr_fu1_src1_fwd_o [3] \dr_fu1_src1_fwd_o [2] \dr_fu1_src1_fwd_o [1] \dr_fu1_src1_fwd_o [0] }
4307     sync init
4308   end
4309   process $group_12
4310     assign \fu_fu2_sfwd1_i 4'0000
4311     assign \fu_fu2_sfwd1_i { \dr_fu2_src1_fwd_o [3] \dr_fu2_src1_fwd_o [2] \dr_fu2_src1_fwd_o [1] \dr_fu2_src1_fwd_o [0] }
4312     sync init
4313   end
4314   process $group_13
4315     assign \rd_src1_pend_o 3'000
4316     assign \rd_src1_pend_o { \fu_fu2_reg_rd_src_pend_o [0] \fu_fu1_reg_rd_src_pend_o [0] \fu_fu0_reg_rd_src_pend_o [0] }
4317     sync init
4318   end
4319   process $group_14
4320     assign \fu_fu0_sfwd2_i 4'0000
4321     assign \fu_fu0_sfwd2_i { \dr_fu0_src2_fwd_o [3] \dr_fu0_src2_fwd_o [2] \dr_fu0_src2_fwd_o [1] \dr_fu0_src2_fwd_o [0] }
4322     sync init
4323   end
4324   process $group_15
4325     assign \fu_fu1_sfwd2_i 4'0000
4326     assign \fu_fu1_sfwd2_i { \dr_fu1_src2_fwd_o [3] \dr_fu1_src2_fwd_o [2] \dr_fu1_src2_fwd_o [1] \dr_fu1_src2_fwd_o [0] }
4327     sync init
4328   end
4329   process $group_16
4330     assign \fu_fu2_sfwd2_i 4'0000
4331     assign \fu_fu2_sfwd2_i { \dr_fu2_src2_fwd_o [3] \dr_fu2_src2_fwd_o [2] \dr_fu2_src2_fwd_o [1] \dr_fu2_src2_fwd_o [0] }
4332     sync init
4333   end
4334   process $group_17
4335     assign \rd_src2_pend_o 3'000
4336     assign \rd_src2_pend_o { \fu_fu2_reg_rd_src_pend_o [1] \fu_fu1_reg_rd_src_pend_o [1] \fu_fu0_reg_rd_src_pend_o [1] }
4337     sync init
4338   end
4339   process $group_18
4340     assign \rr_r0_dst_rsel_i 3'000
4341     assign \rr_r0_dst_rsel_i { \dr_fu2_dst1_rsel_o [0] \dr_fu1_dst1_rsel_o [0] \dr_fu0_dst1_rsel_o [0] }
4342     sync init
4343   end
4344   process $group_19
4345     assign \rr_r1_dst_rsel_i 3'000
4346     assign \rr_r1_dst_rsel_i { \dr_fu2_dst1_rsel_o [1] \dr_fu1_dst1_rsel_o [1] \dr_fu0_dst1_rsel_o [1] }
4347     sync init
4348   end
4349   process $group_20
4350     assign \rr_r2_dst_rsel_i 3'000
4351     assign \rr_r2_dst_rsel_i { \dr_fu2_dst1_rsel_o [2] \dr_fu1_dst1_rsel_o [2] \dr_fu0_dst1_rsel_o [2] }
4352     sync init
4353   end
4354   process $group_21
4355     assign \rr_r3_dst_rsel_i 3'000
4356     assign \rr_r3_dst_rsel_i { \dr_fu2_dst1_rsel_o [3] \dr_fu1_dst1_rsel_o [3] \dr_fu0_dst1_rsel_o [3] }
4357     sync init
4358   end
4359   process $group_22
4360     assign \rr_r0_dst_rsel_i$1 3'000
4361     assign \rr_r0_dst_rsel_i$1 { \dr_fu2_dst2_rsel_o [0] \dr_fu1_dst2_rsel_o [0] \dr_fu0_dst2_rsel_o [0] }
4362     sync init
4363   end
4364   process $group_23
4365     assign \rr_r1_dst_rsel_i$3 3'000
4366     assign \rr_r1_dst_rsel_i$3 { \dr_fu2_dst2_rsel_o [1] \dr_fu1_dst2_rsel_o [1] \dr_fu0_dst2_rsel_o [1] }
4367     sync init
4368   end
4369   process $group_24
4370     assign \rr_r2_dst_rsel_i$5 3'000
4371     assign \rr_r2_dst_rsel_i$5 { \dr_fu2_dst2_rsel_o [2] \dr_fu1_dst2_rsel_o [2] \dr_fu0_dst2_rsel_o [2] }
4372     sync init
4373   end
4374   process $group_25
4375     assign \rr_r3_dst_rsel_i$7 3'000
4376     assign \rr_r3_dst_rsel_i$7 { \dr_fu2_dst2_rsel_o [3] \dr_fu1_dst2_rsel_o [3] \dr_fu0_dst2_rsel_o [3] }
4377     sync init
4378   end
4379   process $group_26
4380     assign \dst2_rsel_o 4'0000
4381     assign \dst2_rsel_o { \rr_r3_dest_rsel_o [1] \rr_r2_dest_rsel_o [1] \rr_r1_dest_rsel_o [1] \rr_r0_dest_rsel_o [1] }
4382     sync init
4383   end
4384   process $group_27
4385     assign \rr_r0_src_rsel_i 3'000
4386     assign \rr_r0_src_rsel_i { \dr_fu2_src1_rsel_o [0] \dr_fu1_src1_rsel_o [0] \dr_fu0_src1_rsel_o [0] }
4387     sync init
4388   end
4389   process $group_28
4390     assign \rr_r1_src_rsel_i 3'000
4391     assign \rr_r1_src_rsel_i { \dr_fu2_src1_rsel_o [1] \dr_fu1_src1_rsel_o [1] \dr_fu0_src1_rsel_o [1] }
4392     sync init
4393   end
4394   process $group_29
4395     assign \rr_r2_src_rsel_i 3'000
4396     assign \rr_r2_src_rsel_i { \dr_fu2_src1_rsel_o [2] \dr_fu1_src1_rsel_o [2] \dr_fu0_src1_rsel_o [2] }
4397     sync init
4398   end
4399   process $group_30
4400     assign \rr_r3_src_rsel_i 3'000
4401     assign \rr_r3_src_rsel_i { \dr_fu2_src1_rsel_o [3] \dr_fu1_src1_rsel_o [3] \dr_fu0_src1_rsel_o [3] }
4402     sync init
4403   end
4404   process $group_31
4405     assign \src1_rsel_o 4'0000
4406     assign \src1_rsel_o { \rr_r3_src_rsel_o [0] \rr_r2_src_rsel_o [0] \rr_r1_src_rsel_o [0] \rr_r0_src_rsel_o [0] }
4407     sync init
4408   end
4409   process $group_32
4410     assign \rr_r0_src_rsel_i$2 3'000
4411     assign \rr_r0_src_rsel_i$2 { \dr_fu2_src2_rsel_o [0] \dr_fu1_src2_rsel_o [0] \dr_fu0_src2_rsel_o [0] }
4412     sync init
4413   end
4414   process $group_33
4415     assign \rr_r1_src_rsel_i$4 3'000
4416     assign \rr_r1_src_rsel_i$4 { \dr_fu2_src2_rsel_o [1] \dr_fu1_src2_rsel_o [1] \dr_fu0_src2_rsel_o [1] }
4417     sync init
4418   end
4419   process $group_34
4420     assign \rr_r2_src_rsel_i$6 3'000
4421     assign \rr_r2_src_rsel_i$6 { \dr_fu2_src2_rsel_o [2] \dr_fu1_src2_rsel_o [2] \dr_fu0_src2_rsel_o [2] }
4422     sync init
4423   end
4424   process $group_35
4425     assign \rr_r3_src_rsel_i$8 3'000
4426     assign \rr_r3_src_rsel_i$8 { \dr_fu2_src2_rsel_o [3] \dr_fu1_src2_rsel_o [3] \dr_fu0_src2_rsel_o [3] }
4427     sync init
4428   end
4429   process $group_36
4430     assign \src2_rsel_o 4'0000
4431     assign \src2_rsel_o { \rr_r3_src_rsel_o [1] \rr_r2_src_rsel_o [1] \rr_r1_src_rsel_o [1] \rr_r0_src_rsel_o [1] }
4432     sync init
4433   end
4434   process $group_37
4435     assign \dr_fu0_rd_pend_i 4'0000
4436     assign \dr_fu0_rd_pend_i \rd_pend_i
4437     sync init
4438   end
4439   process $group_38
4440     assign \dr_fu0_wr_pend_i 4'0000
4441     assign \dr_fu0_wr_pend_i \wr_pend_i
4442     sync init
4443   end
4444   process $group_39
4445     assign \dr_fu1_rd_pend_i 4'0000
4446     assign \dr_fu1_rd_pend_i \rd_pend_i
4447     sync init
4448   end
4449   process $group_40
4450     assign \dr_fu1_wr_pend_i 4'0000
4451     assign \dr_fu1_wr_pend_i \wr_pend_i
4452     sync init
4453   end
4454   process $group_41
4455     assign \dr_fu2_rd_pend_i 4'0000
4456     assign \dr_fu2_rd_pend_i \rd_pend_i
4457     sync init
4458   end
4459   process $group_42
4460     assign \dr_fu2_wr_pend_i 4'0000
4461     assign \dr_fu2_wr_pend_i \wr_pend_i
4462     sync init
4463   end
4464   process $group_43
4465     assign \dr_fu0_dst1 4'0000
4466     assign \dr_fu0_dst1 \dst1
4467     sync init
4468   end
4469   process $group_44
4470     assign \dr_fu1_dst1 4'0000
4471     assign \dr_fu1_dst1 \dst1
4472     sync init
4473   end
4474   process $group_45
4475     assign \dr_fu2_dst1 4'0000
4476     assign \dr_fu2_dst1 \dst1
4477     sync init
4478   end
4479   process $group_46
4480     assign \dr_fu0_dst2 4'0000
4481     assign \dr_fu0_dst2 \dst2
4482     sync init
4483   end
4484   process $group_47
4485     assign \dr_fu1_dst2 4'0000
4486     assign \dr_fu1_dst2 \dst2
4487     sync init
4488   end
4489   process $group_48
4490     assign \dr_fu2_dst2 4'0000
4491     assign \dr_fu2_dst2 \dst2
4492     sync init
4493   end
4494   process $group_49
4495     assign \dr_fu0_src1 4'0000
4496     assign \dr_fu0_src1 \src1
4497     sync init
4498   end
4499   process $group_50
4500     assign \dr_fu1_src1 4'0000
4501     assign \dr_fu1_src1 \src1
4502     sync init
4503   end
4504   process $group_51
4505     assign \dr_fu2_src1 4'0000
4506     assign \dr_fu2_src1 \src1
4507     sync init
4508   end
4509   process $group_52
4510     assign \dr_fu0_src2 4'0000
4511     assign \dr_fu0_src2 \src2
4512     sync init
4513   end
4514   process $group_53
4515     assign \dr_fu1_src2 4'0000
4516     assign \dr_fu1_src2 \src2
4517     sync init
4518   end
4519   process $group_54
4520     assign \dr_fu2_src2 4'0000
4521     assign \dr_fu2_src2 \src2
4522     sync init
4523   end
4524   process $group_55
4525     assign \v_rd_rsel_o 4'0000
4526     assign \v_rd_rsel_o \rd_v_g_pend_o
4527     sync init
4528   end
4529   process $group_56
4530     assign \v_wr_rsel_o 4'0000
4531     assign \v_wr_rsel_o \wr_v_g_pend_o
4532     sync init
4533   end
4534   process $group_57
4535     assign \dr_fu0_issue_i 1'0
4536     assign \dr_fu1_issue_i 1'0
4537     assign \dr_fu2_issue_i 1'0
4538     assign { \dr_fu2_issue_i \dr_fu1_issue_i \dr_fu0_issue_i } \issue_i
4539     sync init
4540   end
4541   process $group_60
4542     assign \dr_fu0_go_rd_i 2'00
4543     assign \dr_fu1_go_rd_i 2'00
4544     assign \dr_fu2_go_rd_i 2'00
4545     assign { \dr_fu2_go_rd_i [0] \dr_fu1_go_rd_i [0] \dr_fu0_go_rd_i [0] } \gord1_i
4546     assign { \dr_fu2_go_rd_i [1] \dr_fu1_go_rd_i [1] \dr_fu0_go_rd_i [1] } \gord2_i
4547     sync init
4548   end
4549   process $group_63
4550     assign \dr_fu0_go_wr_i 2'00
4551     assign \dr_fu1_go_wr_i 2'00
4552     assign \dr_fu2_go_wr_i 2'00
4553     assign { \dr_fu2_go_wr_i [0] \dr_fu1_go_wr_i [0] \dr_fu0_go_wr_i [0] } \gowr1_i
4554     assign { \dr_fu2_go_wr_i [1] \dr_fu1_go_wr_i [1] \dr_fu0_go_wr_i [1] } \gowr2_i
4555     sync init
4556   end
4557   process $group_66
4558     assign \dr_fu0_go_die_i 1'0
4559     assign \dr_fu1_go_die_i 1'0
4560     assign \dr_fu2_go_die_i 1'0
4561     assign { \dr_fu2_go_die_i \dr_fu1_go_die_i \dr_fu0_go_die_i } \go_die_i
4562     sync init
4563   end
4564 end