experiments9/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5              YOSYS_FLATTEN = No
   6 #            YOSYS_SET_TOP = Yes
   7                     CHIP  = chip
   8                     CORE  = ls180
   9             USE_CLOCKTREE = Yes
  10                 USE_DEBUG = No
  11                  USE_KITE = No
  12                  RM_CHIP  = Yes
  13                 #VST_FLAGS = --vst-use-concat
  14
  15                  #NETLISTS = $(shell cat cells.lst)
  16                  NETLISTS = ls180
  17 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
  18
  19
  20
  21  include ./mk/design-flow.mk
  22
  23 chip_r.vst: ls180.vst
  24         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  25
  26 chip_r.ap: chip_r.vst
  27
  28 pinmux:
  29         (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  30         ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
  31         ln -f -s coriolis2/ls180 ls180
  32
  33 # comment out for now
  34 blif:      ls180.blif
  35 vst:       ls180.vst
  36
  37 lvx:       lvx-chip_r
  38 druc:      druc-chip_r
  39 dreal:     dreal-chip_r
  40 flatph:     flatph-chip_r
  41 view:      cgt-chip_r
  42
  43 layout:    chip_r.ap
  44 gds:       chip_r.gds
  45 gds_flat:  chip_r_flat.gds
  46 cif:       chip_r.cif
  47
  48
  49 view:      cgt-chip_r
  50 sim:       asimut-ls180_r