experiments9/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5             YOSYS_FLATTEN = No
   6          YOSYS_BLACKBOXES = pll \
   7                             spblock512w64b8w_0 \
   8                             spblock512w64b8w_1 \
   9                             spblock512w64b8w_2 \
  10                             spblock512w64b8w_3
  11 #            YOSYS_SET_TOP = Yes
  12                     CHIP  = chip
  13                     CORE  = ls180
  14             USE_CLOCKTREE = Yes
  15                 USE_DEBUG = No
  16                  USE_KITE = No
  17                  RM_CHIP  = Yes
  18                  # must make VST names unique (for re-importing to GHDL)
  19                 VST_FLAGS = --vst-uniquify-uppercase
  20
  21                  #NETLISTS = $(shell cat cells.lst)
  22                  NETLISTS = ls180 libresoc
  23 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
  24
  25
  26
  27  include ./mk/design-flow.mk
  28
  29 chip_r.vst: ls180.vst
  30         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  31
  32 chip_r.ap: chip_r.vst
  33
  34 pinmux:
  35         (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  36         ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
  37         ln -f -s coriolis2/ls180 ls180
  38
  39 # comment out for now
  40 blif:      ls180.blif
  41 vst:       ls180.vst
  42
  43 lvx:       lvx-chip_r
  44 druc:      druc-chip_r
  45 dreal:     dreal-chip_r
  46 flatph:     flatph-chip_r
  47 view:      cgt-chip_r
  48
  49 layout:    chip_r.ap
  50 gds:       chip_r.gds
  51 gds_flat:  chip_r_flat.gds
  52 cif:       chip_r.cif
  53
  54
  55 view:      cgt-chip_r
  56 sim:       asimut-ls180_r