experiments9/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = sxlib
   5
   6 #            YOSYS_SET_TOP = Yes
   7                     CHIP  = chip
   8                     #CORE  = ls180
   9                    MARGIN = 2
  10                    BOOMOPT =
  11                    BOOGOPT =
  12                    LOONOPT =
  13                    NSL2VHOPT = -vasy # -split -p
  14             USE_CLOCKTREE = Yes
  15                 USE_DEBUG = No
  16                  USE_KITE = No
  17                 #VST_FLAGS = --vst-use-concat
  18
  19                  #NETLISTS = $(shell cat cells.lst)
  20                  NETLISTS = ls180
  21 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
  22
  23
  24
  25  include ./mk/design-flow.mk
  26
  27 pinmux:
  28         (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  29         ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
  30
  31 # comment out for now
  32 #blif:      ls180.blif
  33 #vst:       ls180.vst
  34
  35 lvx:       lvx-chip_cts_r
  36 druc:      druc-chip_cts_r
  37 dreal:     dreal-chip_cts_r
  38 flatph:     flatph-chip_cts_r
  39 view:      cgt-chip_cts_r
  40
  41 layout:    chip_cts_r.ap
  42 gds:       chip_cts_r.gds
  43 gds_flat:  chip_cts_r_flat.gds
  44 cif:       chip_cts_r.cif
  45
  46
  47 view:      cgt-chip_cts_r
  48 sim:       asimut-ls180_cts_r