experiments9/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5             YOSYS_FLATTEN = No
   6          YOSYS_BLACKBOXES = pll \
   7                             spblock_512w64b8w
   8 #            YOSYS_SET_TOP = Yes
   9                     CHIP  = chip
  10                     CORE  = ls180
  11             USE_CLOCKTREE = Yes
  12                 USE_DEBUG = No
  13                  USE_KITE = No
  14                  RM_CHIP  = Yes
  15                  # must make VST names unique (for re-importing to GHDL)
  16                 VST_FLAGS = --vst-uniquify-uppercase
  17
  18                  #NETLISTS = $(shell cat cells.lst)
  19                  NETLISTS = ls180 libresoc
  20 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
  21
  22
  23
  24  include ./mk/design-flow.mk
  25
  26 chip_r.vst: ls180.vst
  27         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  28
  29 chip_r.ap: chip_r.vst
  30
  31 pinmux:
  32         (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  33         ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py
  34         ln -f -s coriolis2/ls180 ls180
  35
  36 # comment out for now
  37 blif:      ls180.blif
  38 vst:       ls180.vst
  39
  40 lvx:       lvx-chip_r
  41 druc:      druc-chip_r
  42 dreal:     dreal-chip_r
  43 flatph:     flatph-chip_r
  44 view:      cgt-chip_r
  45
  46 layout:    chip_r.ap
  47 gds:       chip_r.gds
  48 gds_flat:  chip_r_flat.gds
  49 cif:       chip_r.cif
  50
  51
  52 view:      cgt-chip_r
  53 sim:       asimut-ls180_r