first attempt putting in litex pins instead of bare core
[soclayout.git] / experiments9 / Makefile
1
2 LOGICAL_SYNTHESIS = Yosys
3 PHYSICAL_SYNTHESIS = Coriolis
4 DESIGN_KIT = sxlib
5
6 YOSYS_SET_TOP = Yes
7 USE_CLOCKTREE = No
8 USE_DEBUG = No
9 USE_KITE = No
10 VST_FLAGS = --vst-use-concat
11
12 NETLISTS = $(shell cat cells.lst)
13 # YOSYS_FLATTEN = $(shell cat flatten.lst)
14
15
16
17 include ./mk/design-flow.mk
18
19
20 blif: ls180.blif
21 vst: ls180.vst
22
23 layout: ls180_r.ap
24 gds: ls180_r.gds
25
26 lvx: lvx-ls180_r
27 druc: druc-ls180_r
28 view: cgt-ls180_r
29 viewn: cgt-ls180