experiments9/doDesign.py

   1
   2 from   __future__ import print_function
   3 import sys
   4 import traceback
   5 import CRL
   6 import Cfg
   7 import helpers
   8 from   helpers.io      import ErrorMessage
   9 from   helpers.io      import WarningMessage
  10 from   helpers.overlay import CfgCache
  11 from   helpers         import trace, l
  12 import plugins
  13 from   Hurricane  import DbU
  14 from   Hurricane  import Pin
  15 from   Hurricane  import Transformation
  16 from   plugins.alpha.block.block         import Block
  17 from   plugins.alpha.block.configuration import IoPin
  18
  19
  20 af = CRL.AllianceFramework.get()
  21
  22
  23 def coriolis_setup():
  24     with CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
  25         cfg.misc.catchCore = False
  26         cfg.misc.info = False
  27         cfg.misc.paranoid = False
  28         cfg.misc.bug = False
  29         cfg.misc.logMode = True
  30         cfg.misc.verboseLevel1 = True
  31         cfg.misc.verboseLevel2 = True
  32         cfg.etesian.effort = 2
  33         cfg.etesian.spaceMargin = 0.10  # 10%
  34         cfg.etesian.aspectRatio = 1.0   # 100%
  35         cfg.etesian.uniformDensity = True
  36         cfg.anabatic.edgeLenght = 24
  37         cfg.anabatic.edgeWidth = 8
  38         cfg.anabatic.topRoutingLayer = 'METAL5'
  39         cfg.katana.searchHalo = 30
  40         cfg.katana.eventsLimit = 1000000
  41         cfg.katana.hTracksReservedLocal = 7
  42         cfg.katana.vTracksReservedLocal = 6
  43
  44         env = af.getEnvironment()
  45         env.setCLOCK('^clk$|m_clock')
  46         env.setPOWER('vdd')
  47         env.setGROUND('vss')
  48
  49
  50 def scriptMain ( **kw ):
  51     """The mandatory function that Coriolis CGT/Unicorn will look for."""
  52     global af
  53
  54     IW = IoPin.WEST
  55     IE = IoPin.EAST
  56     IS = IoPin.SOUTH
  57     IN = IoPin.NORTH
  58     AB = IoPin.A_BEGIN
  59     AE = IoPin.A_END
  60
  61     alup=[
  62         (IW | AB, 'coresync_clk'                    , 0 ),
  63         (IW | AB, 'cu_issue_i'                      , 0 ),
  64         (IW | AB, 'oper_i_alu_alu0_imm_data_imm_ok' , 0 ),
  65         (IW | AB, 'oper_i_alu_alu0_invert_a'        , 0 ),
  66         (IW | AB, 'oper_i_alu_alu0_invert_out'      , 0 ),
  67         (IW | AB, 'oper_i_alu_alu0_is_32bit'        , 0 ),
  68         (IW | AB, 'oper_i_alu_alu0_is_signed'       , 0 ),
  69         (IW | AB, 'oper_i_alu_alu0_oe_oe'           , 0 ),
  70         (IW | AB, 'oper_i_alu_alu0_oe_oe_ok'        , 0 ),
  71         (IW | AB, 'oper_i_alu_alu0_output_carry'    , 0 ),
  72         (IW | AB, 'oper_i_alu_alu0_rc_rc'           , 0 ),
  73         (IW | AB, 'oper_i_alu_alu0_rc_rc_ok'        , 0 ),
  74         (IW | AB, 'oper_i_alu_alu0_write_cr0'       , 0 ),
  75         (IW | AB, 'oper_i_alu_alu0_zero_a'          , 0 ),
  76         (IW | AB, 'coresync_rst'                    , 0 ),
  77         (IW | AB, 'src3_i'                          , 0 ),
  78         (IW | AB, 'oper_i_alu_alu0_input_carry({})' , 0, l( 10.0),  2),
  79         (IW | AB, 'src4_i({})'                      , 0, l( 10.0),  2),
  80         (IW | AB, 'oper_i_alu_alu0_data_len({})'    , 0, l( 10.0),  4),
  81         (IW | AB, 'cu_rd_go_i({})'                  , 0, l( 10.0),  4),
  82         (IW | AB, 'cu_rdmaskn_i({})'                , 0, l( 10.0),  4),
  83         (IW | AB, 'cu_wr_go_i({})'                  , 0, l( 10.0),  5),
  84         (IW | AB, 'oper_i_alu_alu0_insn_type({})'   , 0, l( 10.0),  7),
  85         (IW | AB, 'oper_i_alu_alu0_fn_unit({})'     , 0, l( 10.0), 11),
  86         (IW | AB, 'oper_i_alu_alu0_insn({})'        , 0, l( 10.0), 32),
  87         (IW | AB, 'oper_i_alu_alu0_imm_data_imm({})', 0, l( 15.0), 64),
  88         (IS     , 'src1_i({})'                      , l(10), l( 15.0), 64),
  89         (IS     , 'src2_i({})'                      , l(15), l( 15.0), 64),
  90         (IN     , 'dest1_o({})'                     , l(20), l( 15.0), 64),
  91         (IE | AE, 'cu_busy_o'                       , 0 ),
  92         (IE | AE, 'cr_a_ok'                         , 0 ),
  93         (IE | AE, 'dest5_o'                         , 0 ),
  94         (IE | AE, 'o_ok'                            , 0 ),
  95         (IE | AE, 'xer_ca_ok'                       , 0 ),
  96         (IE | AE, 'xer_ov_ok'                       , 0 ),
  97         (IE | AE, 'xer_so_ok'                       , 0 ),
  98         (IE | AE, 'dest3_o({})'                     , 0, l( 20.0),  2),
  99         (IE | AE, 'dest4_o({})'                     , 0, l( 20.0),  2),
 100         (IE | AE, 'dest2_o({})'                     , 0, l( 20.0),  4),
 101         (IE | AE, 'cu_rd_rel_o({})'                 , 0, l( 20.0),  4),
 102         (IE | AE, 'cu_wr_rel_o({})'                 , 0, l( 20.0),  5),
 103         ]
 104
 105     rvalue = True
 106     try:
 107         helpers.setTraceLevel( 550 )
 108         cell, editor = plugins.kwParseMain( **kw )
 109
 110         alu0 = af.getCell( 'alu0', CRL.Catalog.State.Views )
 111         blockAlu0 = Block.create (alu0, ioPins = alup)
 112         blockAlu0.state.cfg.etesian.spaceMargin = 0.05
 113         blockAlu0.state.fixedHeight = l(5000)
 114         blockAlu0.state.useSpares   = False
 115        #rvalue = blockAlu0.build()
 116
 117         mulp=[
 118             (IN     , 'coresync_clk'                    , l(4500.0) ),
 119             (IW | AB, 'cu_issue_i'                      , 0, l(20) ),
 120             (IW | AB, 'oper_i_alu_mul0_imm_data_imm_ok' , 0, l(20) ),
 121             (IW | AB, 'oper_i_alu_mul0_invert_a'        , 0, l(20) ),
 122             (IW | AB, 'oper_i_alu_mul0_invert_out'      , 0, l(20) ),
 123             (IW | AB, 'oper_i_alu_mul0_is_32bit'        , 0, l(20) ),
 124             (IW | AB, 'oper_i_alu_mul0_is_signed'       , 0, l(20) ),
 125             (IW | AB, 'oper_i_alu_mul0_oe_oe'           , 0, l(20) ),
 126             (IW | AB, 'oper_i_alu_mul0_oe_oe_ok'        , 0, l(20) ),
 127             (IW | AB, 'oper_i_alu_mul0_rc_rc'           , 0, l(20) ),
 128             (IW | AB, 'oper_i_alu_mul0_rc_rc_ok'        , 0, l(20) ),
 129             (IW | AB, 'oper_i_alu_mul0_write_cr0'       , 0, l(20) ),
 130             (IW | AB, 'oper_i_alu_mul0_zero_a'          , 0, l(20) ),
 131             (IW | AB, 'coresync_rst'                    , 0, l(20) ),
 132             (IW | AB, 'src3_i'                          , 0, l(20) ),
 133             (IW | AB, 'cu_rd_go_i({})'                  , 0, l(10.0),  3),
 134             (IW | AB, 'cu_rdmaskn_i({})'                , 0, l(10.0),  3),
 135             (IW | AB, 'cu_wr_go_i({})'                  , 0, l(10.0),  4),
 136             (IW | AB, 'oper_i_alu_mul0_insn_type({})'   , 0, l(10.0),  7),
 137             (IW | AB, 'oper_i_alu_mul0_fn_unit({})'     , 0, l(10.0), 11),
 138             (IW | AB, 'oper_i_alu_mul0_insn({})'        , 0, l(10.0), 32),
 139             (IW | AB, 'oper_i_alu_mul0_imm_data_imm({})', 0, l(15.0), 64),
 140             (IS | AB, 'src1_i({})'                      , l(10.0), l(50.0), 64),
 141             (IS | AB, 'src2_i({})'                      , l(20.0), l(50.0), 64),
 142             (IE | AE, 'cu_busy_o'                       , 0 ),
 143             (IE | AE, 'cr_a_ok'                         , 0 ),
 144             (IE | AE, 'dest4_o'                         , 0 ),
 145             (IE | AE, 'o_ok'                            , 0 ),
 146             (IE | AE, 'xer_ov_ok'                       , 0 ),
 147             (IE | AE, 'xer_so_ok'                       , 0 ),
 148             (IE | AE, 'dest3_o({})'                     , 0, l( 20.0),  2),
 149             (IE | AE, 'dest2_o({})'                     , 0, l( 20.0),  4),
 150             (IE | AE, 'cu_rd_rel_o({})'                 , 0, l( 20.0),  3),
 151             (IE | AE, 'cu_wr_rel_o({})'                 , 0, l( 20.0),  4),
 152             (IN | AE, 'dest1_o({})'                     , 0, l( 30.0), 64),
 153              ]
 154         mul0 = af.getCell( 'mul0', CRL.Catalog.State.Views )
 155         blockMul0 = Block.create ( mul0 , ioPins=mulp)
 156         blockMul0.state.cfg.etesian.uniformDensity = True
 157         blockMul0.state.cfg.etesian.spaceMargin    = 0.15
 158         blockMul0.state.cfg.katana.searchHalo      = 1
 159         blockMul0.state.fixedHeight = l(5000)
 160         blockMul0.state.useSpares   = False
 161        #rvalue = blockMul0.build()
 162
 163         divp=[
 164             (IN     , 'coresync_clk'                    , l(4500.0) ),
 165             (IW | AB, 'cu_issue_i'                      , 0, l(20) ),
 166             (IW | AB, 'oper_i_alu_div0_imm_data_imm_ok' , 0, l(20) ),
 167             (IW | AB, 'oper_i_alu_div0_invert_a'        , 0, l(20) ),
 168             (IW | AB, 'oper_i_alu_div0_invert_out'      , 0, l(20) ),
 169             (IW | AB, 'oper_i_alu_div0_is_32bit'        , 0, l(20) ),
 170             (IW | AB, 'oper_i_alu_div0_is_signed'       , 0, l(20) ),
 171             (IW | AB, 'oper_i_alu_div0_oe_oe'           , 0, l(20) ),
 172             (IW | AB, 'oper_i_alu_div0_oe_oe_ok'        , 0, l(20) ),
 173             (IW | AB, 'oper_i_alu_div0_output_carry'    , 0, l(20) ),
 174             (IW | AB, 'oper_i_alu_div0_rc_rc'           , 0, l(20) ),
 175             (IW | AB, 'oper_i_alu_div0_rc_rc_ok'        , 0, l(20) ),
 176             (IW | AB, 'oper_i_alu_div0_write_cr0'       , 0, l(20) ),
 177             (IW | AB, 'oper_i_alu_div0_zero_a'          , 0, l(20) ),
 178             (IW | AB, 'coresync_rst'                    , 0, l(20) ),
 179             (IW | AB, 'src3_i'                          , 0, l(20) ),
 180             (IW | AB, 'cu_rd_go_i({})'                  , 0, l(10.0),  3),
 181             (IW | AB, 'cu_rdmaskn_i({})'                , 0, l(10.0),  3),
 182             (IW | AB, 'cu_wr_go_i({})'                  , 0, l(10.0),  4),
 183             (IW | AB, 'oper_i_alu_div0_data_len({})'    , 0, l(10.0),  7),
 184             (IW | AB, 'oper_i_alu_div0_insn_type({})'   , 0, l(10.0),  7),
 185             (IW | AB, 'oper_i_alu_div0_fn_unit({})'     , 0, l(10.0), 11),
 186             (IW | AB, 'oper_i_alu_div0_insn({})'        , 0, l(10.0), 32),
 187             (IW | AB, 'oper_i_alu_div0_imm_data_imm({})', 0, l(15.0), 64),
 188             (IS | AB, 'src1_i({})'                      , l(10.0), l(50.0), 64),
 189             (IS | AB, 'src2_i({})'                      , l(20.0), l(50.0), 64),
 190             (IE | AE, 'cu_busy_o'                       , 0 ),
 191             (IE | AE, 'cr_a_ok'                         , 0 ),
 192             (IE | AE, 'dest4_o'                         , 0 ),
 193             (IE | AE, 'o_ok'                            , 0 ),
 194             (IE | AE, 'xer_ov_ok'                       , 0 ),
 195             (IE | AE, 'xer_so_ok'                       , 0 ),
 196             (IE | AE, 'dest3_o({})'                     , 0, l( 20.0),  2),
 197             (IE | AE, 'dest2_o({})'                     , 0, l( 20.0),  4),
 198             (IE | AE, 'cu_rd_rel_o({})'                 , 0, l( 20.0),  3),
 199             (IE | AE, 'cu_wr_rel_o({})'                 , 0, l( 20.0),  4),
 200             (IN | AE, 'dest1_o({})'                     , 0, l( 30.0), 64),
 201              ]
 202         div0 = af.getCell( 'div0', CRL.Catalog.State.Views )
 203         blockDiv0 = Block.create ( div0 , ioPins=divp)
 204         blockDiv0.state.cfg.etesian.uniformDensity = True
 205         blockDiv0.state.cfg.etesian.spaceMargin    = 0.10
 206         blockDiv0.state.cfg.katana.searchHalo      = 1
 207         blockDiv0.state.fixedHeight = l(2000)
 208         blockDiv0.state.useSpares   = False
 209        #rvalue = blockDiv0.build()
 210
 211         branchp=[
 212           (IN, 'coresync_clk'                       , l( 805.0) ),
 213           (IW, 'cu_issue_i'                         , l(  30.0) ),
 214           (IW, 'oper_i_alu_branch0_imm_data_imm_ok' , l(  40.0) ),
 215           (IW, 'oper_i_alu_branch0_is_32bit'        , l(  70.0) ),
 216           (IW, 'oper_i_alu_branch0_lk'              , l( 150.0) ),
 217           (IW, 'coresync_rst'                       , l( 160.0) ),
 218           (IW, 'src3_i({})'                         , l( 180.0), l( 10.0),  4),
 219           (IW, 'cu_rd_go_i({})'                     , l( 270.0), l( 10.0),  3),
 220           (IW, 'cu_rdmaskn_i({})'                   , l( 310.0), l( 10.0),  3),
 221           (IW, 'cu_wr_go_i({})'                     , l( 350.0), l( 10.0),  3),
 222           (IW, 'oper_i_alu_branch0_insn_type({})'   , l( 400.0), l( 10.0),  7),
 223           (IW, 'oper_i_alu_branch0_fn_unit({})'     , l( 470.0), l( 10.0), 11),
 224           (IW, 'oper_i_alu_branch0_insn({})'        , l( 580.0), l( 10.0), 32),
 225           (IW, 'oper_i_alu_branch0_imm_data_imm({})', l( 900.0), l( 10.0), 64),
 226           (IW, 'oper_i_alu_branch0_cia({})'         , l(1540.0), l( 10.0), 64),
 227           (IS, 'src1_i({})'                         , l(  10.0), l( 20.0), 64),
 228           (IS, 'src2_i({})'                         , l(  15.0), l( 20.0), 64),
 229           (IE, 'cu_busy_o'                          , l(3500.0) ),
 230           (IE, 'fast1_ok'                           , l(3520.0) ),
 231           (IE, 'fast2_ok'                           , l(3540.0) ),
 232           (IE, 'nia_ok'                             , l(3560.0) ),
 233           (IE, 'dest2_o({})'                        , l(3580.0), l( 10.0), 64),
 234           (IE, 'dest3_o({})'                        , l(4220.0), l( 10.0), 64),
 235           (IE, 'cu_rd_rel_o({})'                    , l(4860.0), l( 20.0),  3),
 236           (IE, 'cu_wr_rel_o({})'                    , l(4920.0), l( 20.0),  3),
 237           (IN, 'dest1_o({})'                        , l( 500.0), l( 10.0), 64),
 238         ]
 239         branch0 = af.getCell( 'branch0', CRL.Catalog.State.Views )
 240         blockBranch0 = Block.create ( branch0 , ioPins=branchp)
 241         blockBranch0.state.cfg.etesian.spaceMargin = 0.07
 242         blockBranch0.state.fixedHeight = l(5000)
 243         blockBranch0.state.useSpares   = False
 244        #rvalue = blockBranch0.build()
 245
 246         cr0 = af.getCell( 'cr0', CRL.Catalog.State.Views )
 247         blockCr0 = Block.create \
 248             ( cr0
 249             , ioPins=[
 250                 (IN, 'coresync_clk'                       , l( 805.0) ),
 251                 (IW, 'cu_issue_i'                         , l(  30.0) ),
 252                 (IW, 'oper_i_alu_cr0_read_cr_whole'       , l(  40.0) ),
 253                 (IW, 'oper_i_alu_cr0_write_cr_whole'      , l(  70.0) ),
 254                 (IW, 'coresync_rst'                       , l( 160.0) ),
 255                 (IW, 'src4_i({})'                         , l( 180.0), l( 10.0),  4),
 256                 (IW, 'src5_i({})'                         , l( 220.0), l( 10.0),  4),
 257                 (IW, 'src6_i({})'                         , l( 260.0), l( 10.0),  4),
 258                 (IW, 'cu_rd_go_i({})'                     , l( 300.0), l( 10.0),  6),
 259                 (IW, 'cu_rdmaskn_i({})'                   , l( 360.0), l( 10.0),  6),
 260                 (IW, 'cu_wr_go_i({})'                     , l( 420.0), l( 10.0),  3),
 261                 (IW, 'oper_i_alu_cr0_insn_type({})'       , l( 450.0), l( 10.0),  7),
 262                 (IW, 'oper_i_alu_cr0_fn_unit({})'         , l( 520.0), l( 10.0), 11),
 263                 (IW, 'oper_i_alu_cr0_insn({})'            , l( 630.0), l( 10.0), 32),
 264                 (IS, 'src1_i({})'                         , l(  10.0), l( 10.0), 64),
 265                 (IS, 'src2_i({})'                         , l(  15.0), l( 10.0), 64),
 266                 (IE, 'src3_i({})'                         , l(  10.0), l( 20.0), 32),
 267                 (IE, 'cu_busy_o'                          , l(4320.0) ),
 268                 (IE, 'cr_a_ok'                            , l(4340.0) ),
 269                 (IE, 'full_cr_ok'                         , l(4360.0) ),
 270                 (IE, 'o_ok'                               , l(4380.0) ),
 271                 (IE, 'dest2_o({})'                        , l(4400.0), l( 10.0), 32),
 272                 (IE, 'dest3_o({})'                        , l(4720.0), l( 10.0),  4),
 273                 (IE, 'cu_rd_rel_o({})'                    , l(4800.0), l( 20.0),  6),
 274                 (IE, 'cu_wr_rel_o({})'                    , l(4920.0), l( 20.0),  3),
 275                 (IN, 'dest1_o({})'                        , l( 100.0), l( 10.0), 64)
 276             ]
 277             )
 278         blockCr0.state.cfg.etesian.spaceMargin = 0.10
 279         blockCr0.state.fixedHeight = l(5000)
 280         blockCr0.state.useSpares   = False
 281        #rvalue = blockCr0.build()
 282
 283         ldst0 = af.getCell( 'ldst0', CRL.Catalog.State.Views )
 284         blockLdst0 = Block.create \
 285             ( ldst0
 286             , ioPins=[
 287                 (IN     , 'coresync_clk'                       , l(805.0) ),
 288                 (IW | AB, 'cu_ad_go_i'                         , 0, l(20),  1),
 289                 (IW | AB, 'cu_issue_i'                         , 0, l(20),  1),
 290                 (IW | AB, 'ldst_port0_addr_exc_o'              , 0, l(20),  1),
 291                 (IW | AB, 'ldst_port0_addr_ok_o'               , 0, l(20),  1),
 292                 (IW | AB, 'ldst_port0_ld_data_o_ok'            , 0, l(20),  1),
 293                 (IW | AB, 'oper_i_ldst_ldst0_byte_reverse'     , 0, l(20),  1),
 294                 (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm_ok'  , 0, l(20),  1),
 295                 (IW | AB, 'oper_i_ldst_ldst0_is_32bit'         , 0, l(20),  1),
 296                 (IW | AB, 'oper_i_ldst_ldst0_is_signed'        , 0, l(20),  1),
 297                 (IW | AB, 'oper_i_ldst_ldst0_oe_oe'            , 0, l(20),  1),
 298                 (IW | AB, 'oper_i_ldst_ldst0_oe_oe_ok'         , 0, l(20),  1),
 299                 (IW | AB, 'oper_i_ldst_ldst0_rc_rc'            , 0, l(20),  1),
 300                 (IW | AB, 'oper_i_ldst_ldst0_rc_rc_ok'         , 0, l(20),  1),
 301                 (IW | AB, 'oper_i_ldst_ldst0_sign_extend'      , 0, l(20),  1),
 302                 (IW | AB, 'oper_i_ldst_ldst0_zero_a'           , 0, l(20),  1),
 303                 (IW | AB, 'coresync_rst'                       , 0, l(20),  1),
 304                 (IW | AB, 'cu_st_go_i'                         , 0, l(20),  1),
 305                 (IW | AB, 'oper_i_ldst_ldst0_ldst_mode({})'    , 0, l(20),  2),
 306                 (IW | AB, 'cu_rd_go_i({})'                     , 0, l(20),  3),
 307                 (IW | AB, 'cu_rdmaskn_i({})'                   , 0, l(20),  3),
 308                 (IW | AB, 'cu_wr_go_i({})'                     , 0, l(20),  2),
 309                 (IW | AB, 'oper_i_ldst_ldst0_data_len({})'     , 0, l(20),  4),
 310                 (IW | AB, 'oper_i_ldst_ldst0_insn_type({})'    , 0, l(20),  7),
 311                 (IW | AB, 'ldst_port0_ld_data_o({})'           , 0, l(20), 64),
 312                 (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm({})' , 0, l(20), 64),
 313                 (IS | AB, 'src1_i({})'                         , 0,  l(5), 64),
 314                 (IS | AB, 'src2_i({})'                         , 0,  l(5), 64),
 315                 (IE | AE, 'src3_i({})'                         , 0,     0, 64),
 316                 (IE | AE, 'cu_busy_o'                          , 0, l(20),  1),
 317                 (IE | AE, 'cu_ad_rel_o'                        , 0, l(20),  1),
 318                 (IE | AE, 'ldst_port0_addr_i_ok'               , 0, l(20),  1),
 319                 (IE | AE, 'ldst_port0_is_ld_i'                 , 0, l(20),  1),
 320                 (IE | AE, 'ldst_port0_is_st_i'                 , 0, l(20),  1),
 321                 (IE | AE, 'load_mem_o'                         , 0, l(20),  1),
 322                 (IE | AE, 'cu_st_rel_o'                        , 0, l(20),  1),
 323                 (IE | AE, 'stwd_mem_o'                         , 0, l(20),  1),
 324                 (IE | AE, 'ea({})'                             , 0, l(20), 64),
 325                 (IE | AE, 'ldst_port0_st_data_i({})'           , 0, l(20), 64),
 326                 (IE | AE, 'cu_rd_rel_o({})'                    , 0,    0,   3),
 327                 (IE | AE, 'cu_wr_rel_o({})'                    , 0,    0,   2),
 328                 (IE | AE, 'ldst_port0_addr_i_95'               , 0, l(20),  1),
 329                 (IE | AE, 'ldst_port0_addr_i_{}'               , 0, l(20), 64),
 330                 (IN | AE, 'o({})'                              , 0,     0, 64),
 331             ]
 332             )
 333         blockLdst0.state.cfg.etesian.uniformDensity      = True
 334         blockLdst0.state.cfg.etesian.spaceMargin         = 0.20
 335         blockLdst0.state.cfg.katana.searchHalo           = 1
 336         blockLdst0.state.cfg.katana.hTracksReservedLocal = 10
 337         blockLdst0.state.cfg.katana.vTracksReservedLocal = 10
 338         blockLdst0.state.fixedHeight = l(5000)
 339         blockLdst0.state.useSpares   = False
 340        #rvalue = blockLdst0.build()
 341
 342         logical0 = af.getCell( 'logical0', CRL.Catalog.State.Views )
 343         blockLogical0 = Block.create \
 344             ( logical0
 345             , ioPins=[
 346                 (IN     , 'coresync_clk'                        , l(805.0) ),
 347                 (IW | AB, 'cu_issue_i'                          , 0, l(20),  1),
 348                 (IW | AB, 'oper_i_alu_logical0_imm_data_imm_ok' , 0, l(20),  1),
 349                 (IW | AB, 'oper_i_alu_logical0_invert_a'        , 0, l(20),  1),
 350                 (IW | AB, 'oper_i_alu_logical0_invert_out'      , 0, l(20),  1),
 351                 (IW | AB, 'oper_i_alu_logical0_is_32bit'        , 0, l(20),  1),
 352                 (IW | AB, 'oper_i_alu_logical0_is_signed'       , 0, l(20),  1),
 353                 (IW | AB, 'oper_i_alu_logical0_oe_oe'           , 0, l(20),  1),
 354                 (IW | AB, 'oper_i_alu_logical0_oe_oe_ok'        , 0, l(20),  1),
 355                 (IW | AB, 'oper_i_alu_logical0_output_carry'    , 0, l(20),  1),
 356                 (IW | AB, 'oper_i_alu_logical0_rc_rc'           , 0, l(20),  1),
 357                 (IW | AB, 'oper_i_alu_logical0_rc_rc_ok'        , 0, l(20),  1),
 358                 (IW | AB, 'oper_i_alu_logical0_write_cr0'       , 0, l(20),  1),
 359                 (IW | AB, 'oper_i_alu_logical0_zero_a'          , 0, l(20),  1),
 360                 (IW | AB, 'coresync_rst'                        , 0, l(20),  1),
 361                 (IW | AB, 'oper_i_alu_logical0_input_carry({})' , 0, l(20),  2),
 362                 (IW | AB, 'cu_rd_go_i({})'                      , 0, l(20),  2),
 363                 (IW | AB, 'cu_rdmaskn_i({})'                    , 0, l(20),  2),
 364                 (IW | AB, 'cu_wr_go_i({})'                      , 0, l(20),  3),
 365                 (IW | AB, 'oper_i_alu_logical0_data_len({})'    , 0, l(20),  4),
 366                 (IW | AB, 'oper_i_alu_logical0_insn_type({})'   , 0, l(20),  7),
 367                 (IW | AB, 'oper_i_alu_logical0_fn_unit({})'     , 0, l(20), 11),
 368                 (IW | AB, 'oper_i_alu_logical0_insn({})'        , 0, l(20), 32),
 369                 (IW | AB, 'oper_i_alu_logical0_imm_data_imm({})', 0, l(20), 64),
 370                 (IS | AB, 'src1_i({})'                          , 0, l(10), 64),
 371                 (IS | AB, 'src2_i({})'                          , 0,  l(5), 64),
 372                 (IE | AE, 'cu_busy_o'                           , 0, l(20),  1),
 373                 (IE | AE, 'cr_a_ok'                             , 0, l(20),  1),
 374                 (IE | AE, 'o_ok'                                , 0, l(20),  1),
 375                 (IE | AE, 'xer_ca_ok'                           , 0, l(20),  1),
 376                 (IE | AE, 'cu_rd_rel_o({})'                     , 0,     0,  2),
 377                 (IE | AE, 'cu_wr_rel_o({})'                     , 0,     0,  3),
 378                 (IN | AE, 'dest3_o({})'                         , 0,     0,  2),
 379                 (IN | AE, 'dest2_o({})'                         , 0,     0,  4),
 380                 (IN | AE, 'dest1_o({})'                         , 0,     0, 64),
 381             ]
 382             )
 383         blockLogical0.state.cfg.etesian.uniformDensity = True
 384         blockLogical0.state.cfg.etesian.spaceMargin    = 0.07
 385         blockLogical0.state.cfg.katana.searchHalo      = 1
 386         blockLogical0.state.fixedHeight = l(5000)
 387         blockLogical0.state.useSpares   = False
 388        #rvalue = blockLogical0.build()
 389
 390         shiftrot0 = af.getCell( 'shiftrot0', CRL.Catalog.State.Views )
 391         blockShiftrot0 = Block.create \
 392             ( shiftrot0
 393             , ioPins=[
 394                 (IN     , 'coresync_clk'                          , l(805.0) ),
 395                 (IW | AB, 'cu_issue_i'                            , 0, l(20),  1),
 396                 (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm_ok' , 0, l(20),  1),
 397                 (IW | AB, 'oper_i_alu_shift_rot0_input_cr'        , 0, l(20),  1),
 398                 (IW | AB, 'oper_i_alu_shift_rot0_is_32bit'        , 0, l(20),  1),
 399                 (IW | AB, 'oper_i_alu_shift_rot0_is_signed'       , 0, l(20),  1),
 400                 (IW | AB, 'oper_i_alu_shift_rot0_oe_oe'           , 0, l(20),  1),
 401                 (IW | AB, 'oper_i_alu_shift_rot0_oe_oe_ok'        , 0, l(20),  1),
 402                 (IW | AB, 'oper_i_alu_shift_rot0_output_carry'    , 0, l(20),  1),
 403                 (IW | AB, 'oper_i_alu_shift_rot0_output_cr'       , 0, l(20),  1),
 404                 (IW | AB, 'oper_i_alu_shift_rot0_rc_rc'           , 0, l(20),  1),
 405                 (IW | AB, 'oper_i_alu_shift_rot0_rc_rc_ok'        , 0, l(20),  1),
 406                 (IW | AB, 'coresync_rst'                          , 0, l(20),  1),
 407                 (IW | AB, 'oper_i_alu_shift_rot0_input_carry({})' , 0, l(20),  2),
 408                 (IW | AB, 'src4_i({})'                            , 0, l(10),  2),
 409                 (IW | AB, 'cu_rd_go_i({})'                        , 0, l(20),  4),
 410                 (IW | AB, 'cu_rdmaskn_i({})'                      , 0, l(20),  4),
 411                 (IW | AB, 'cu_wr_go_i({})'                        , 0, l(20),  3),
 412                 (IW | AB, 'oper_i_alu_shift_rot0_insn_type({})'   , 0, l(20),  7),
 413                 (IW | AB, 'oper_i_alu_shift_rot0_fn_unit({})'     , 0, l(20), 11),
 414                 (IW | AB, 'oper_i_alu_shift_rot0_insn({})'        , 0, l(20), 32),
 415                 (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm({})', 0, l(20), 64),
 416                 (IW | AB, 'src3_i({})'                            , 0, l(10), 64),
 417                 (IS | AB, 'src1_i({})'                            , 0, l(10), 64),
 418                 (IS | AB, 'src2_i({})'                            , 0,  l(5), 64),
 419                 (IE | AE, 'cu_busy_o'                             , 0, l(20),  1),
 420                 (IE | AE, 'cr_a_ok'                               , 0, l(20),  1),
 421                 (IE | AE, 'o_ok'                                  , 0, l(20),  1),
 422                 (IE | AE, 'xer_ca_ok'                             , 0, l(20),  1),
 423                 (IE | AE, 'cu_rd_rel_o({})'                       , 0,     0,  4),
 424                 (IE | AE, 'cu_wr_rel_o({})'                       , 0,     0,  3),
 425                 (IN | AE, 'dest3_o({})'                           , 0,     0,  2),
 426                 (IN | AE, 'dest2_o({})'                           , 0,     0,  4),
 427                 (IN | AE, 'dest1_o({})'                           , 0,     0, 64),
 428             ]
 429             )
 430         blockShiftrot0.state.cfg.etesian.uniformDensity = True
 431         blockShiftrot0.state.cfg.etesian.spaceMargin    = 0.7
 432         blockShiftrot0.state.cfg.katana.searchHalo      = 1
 433         blockShiftrot0.state.fixedHeight = l(5000)
 434         blockShiftrot0.state.useSpares   = False
 435        #rvalue = blockShiftrot0.build()
 436
 437         spr0 = af.getCell( 'spr0', CRL.Catalog.State.Views )
 438         blockSpr0 = Block.create \
 439             ( spr0
 440             , ioPins=[
 441                 (IN     , 'coresync_clk'                 , l(805.0) ),
 442                 (IW | AB, 'cu_issue_i'                   , 0, l(20),  1),
 443                 (IW | AB, 'oper_i_alu_spr0_is_32bit'     , 0, l(20),  1),
 444                 (IW | AB, 'coresync_rst'                 , 0, l(20),  1),
 445                 (IW | AB, 'src4_i'                       , 0, l(10),  1),
 446                 (IW | AB, 'src5_i({})'                   , 0, l(10),  2),
 447                 (IW | AB, 'src6_i({})'                   , 0, l(10),  2),
 448                 (IW | AB, 'cu_rd_go_i({})'               , 0, l(20),  6),
 449                 (IW | AB, 'cu_rdmaskn_i({})'             , 0, l(20),  6),
 450                 (IW | AB, 'cu_wr_go_i({})'               , 0, l(20),  6),
 451                 (IW | AB, 'oper_i_alu_spr0_insn_type({})', 0, l(20),  7),
 452                 (IW | AB, 'oper_i_alu_spr0_fn_unit({})'  , 0, l(20), 11),
 453                 (IW | AB, 'oper_i_alu_spr0_insn({})'     , 0, l(20), 32),
 454                 (IW | AB, 'src3_i({})'                   , 0, l(10), 64),
 455                 (IS | AB, 'src1_i({})'                   , 0, l(10), 64),
 456                 (IS | AB, 'src2_i({})'                   , 0,  l(5), 64),
 457                 (IE | AE, 'cu_busy_o'                    , 0, l(20),  1),
 458                 (IE | AE, 'dest4_o'                      , 0, l(20),  1),
 459                 (IE | AE, 'fast1_ok'                     , 0, l(20),  1),
 460                 (IE | AE, 'o_ok'                         , 0, l(20),  1),
 461                 (IE | AE, 'spr1_ok'                      , 0, l(20),  1),
 462                 (IE | AE, 'xer_ca_ok'                    , 0, l(20),  1),
 463                 (IE | AE, 'xer_ov_ok'                    , 0, l(20),  1),
 464                 (IE | AE, 'xer_so_ok'                    , 0, l(20),  1),
 465                 (IE | AE, 'cu_rd_rel_o({})'              , 0,     0,  6),
 466                 (IE | AE, 'cu_wr_rel_o({})'              , 0,     0,  6),
 467                 (IN | AE, 'dest5_o({})'                  , 0,     0,  2),
 468                 (IN | AE, 'dest6_o({})'                  , 0,     0,  2),
 469                 (IE | AE, 'dest3_o({})'                  , 0, l(20), 64),
 470                 (IE | AE, 'dest2_o({})'                  , 0, l(20), 64),
 471                 (IE | AE, 'dest1_o({})'                  , 0, l(20), 64),
 472             ]
 473             )
 474         blockSpr0.state.cfg.etesian.uniformDensity = True
 475         blockSpr0.state.cfg.etesian.spaceMargin    = 0.5
 476         blockSpr0.state.cfg.katana.searchHalo      = 1
 477         blockSpr0.state.fixedHeight = l(4500)
 478         blockSpr0.state.useSpares   = False
 479        #rvalue = blockSpr0.build()
 480
 481         trap0 = af.getCell( 'trap0', CRL.Catalog.State.Views )
 482         blockTrap0 = Block.create \
 483             ( trap0
 484             , ioPins=[
 485                 (IN     , 'coresync_clk'                  , l(805.0) ),
 486                 (IW | AB, 'cu_issue_i'                    , 0, l(20),  1),
 487                 (IW | AB, 'oper_i_alu_trap0_is_32bit'     , 0, l(20),  1),
 488                 (IW | AB, 'coresync_rst'                  , 0, l(20),  1),
 489                 (IW | AB, 'cu_rd_go_i({})'                , 0, l(20),  4),
 490                 (IW | AB, 'cu_rdmaskn_i({})'              , 0, l(20),  4),
 491                 (IW | AB, 'cu_wr_go_i({})'                , 0, l(20),  5),
 492                 (IW | AB, 'oper_i_alu_trap0_traptype({})' , 0, l(20),  5),
 493                 (IW | AB, 'oper_i_alu_trap0_insn_type({})', 0, l(20),  7),
 494                 (IW | AB, 'oper_i_alu_trap0_fn_unit({})'  , 0, l(20), 11),
 495                 (IW | AB, 'oper_i_alu_trap0_trapaddr({})' , 0, l(20), 13),
 496                 (IW | AB, 'oper_i_alu_trap0_insn({})'     , 0, l(20), 32),
 497                 (IW | AB, 'oper_i_alu_trap0_cia({})'      , 0, l(20), 64),
 498                 (IW | AB, 'oper_i_alu_trap0_msr({})'      , 0, l(20), 64),
 499                 (IW | AB, 'src3_i({})'                    , 0, l(10), 64),
 500                 (IS | AB, 'src4_i({})'                    , 0, l(10), 64),
 501                 (IS | AB, 'src1_i({})'                    , 0, l(10), 64),
 502                 (IS | AB, 'src2_i({})'                    , 0,  l(5), 64),
 503                 (IE | AE, 'cu_busy_o'                     , 0, l(20),  1),
 504                 (IE | AE, 'fast1_ok'                      , 0, l(20),  1),
 505                 (IE | AE, 'fast2_ok'                      , 0, l(20),  1),
 506                 (IE | AE, 'msr_ok'                        , 0, l(20),  1),
 507                 (IE | AE, 'nia_ok'                        , 0, l(20),  1),
 508                 (IE | AE, 'o_ok'                          , 0, l(20),  1),
 509                 (IE | AE, 'cu_rd_rel_o({})'               , 0,     0,  4),
 510                 (IE | AE, 'cu_wr_rel_o({})'               , 0,     0,  5),
 511                 (IN | AE, 'dest5_o({})'                   , 0, l(10), 64),
 512                 (IN | AE, 'dest4_o({})'                   , 0, l(10), 64),
 513                 (IE | AE, 'dest3_o({})'                   , 0, l(10), 64),
 514                 (IE | AE, 'dest2_o({})'                   , 0, l(10), 64),
 515                 (IE | AE, 'dest1_o({})'                   , 0, l(10), 64),
 516             ]
 517             )
 518         blockTrap0.state.cfg.etesian.uniformDensity = True
 519         blockTrap0.state.cfg.etesian.spaceMargin    = 0.5
 520         blockTrap0.state.cfg.katana.searchHalo      = 1
 521         blockTrap0.state.fixedHeight = l(5000)
 522         blockTrap0.state.useSpares   = False
 523        #rvalue = blockTrap0.build()
 524
 525         fast = af.getCell( 'fast', CRL.Catalog.State.Views )
 526         blockFast = Block.create \
 527             ( fast
 528             , ioPins=[
 529                 (IN     , 'coresync_clk'    , l(805.0) ),
 530                 (IW | AB, 'coresync_rst'    , 0, l(20),  1),
 531                 (IW | AB, 'cia_ren({})'     , 0, l(20),  8),
 532                 (IW | AB, 'fast_nia_wen({})', 0, l(20),  8),
 533                 (IW | AB, 'msr_ren({})'     , 0, l(20),  8),
 534                 (IW | AB, 'src1_ren({})'    , 0, l(20),  8),
 535                 (IW | AB, 'src2_ren({})'    , 0, l(20),  8),
 536                 (IW | AB, 'wen({})'         , 0, l(20),  8),
 537                 (IW | AB, 'wen_1({})'       , 0, l(20),  8),
 538                 (IW | AB, 'wen_3({})'       , 0, l(20),  8),
 539                 (IW | AB, 'wen_6({})'       , 0, l(20),  8),
 540                 (IS | AB, 'data_i({})'      , 0, l(20), 64),
 541                 (IS | AB, 'data_i_2({})'    , 0, l(20), 64),
 542                 (IS | AB, 'data_i_4({})'    , 0, l(10), 64),
 543                 (IS | AB, 'data_i_5({})'    , 0, l(10), 64),
 544                 (IS | AB, 'data_i_7({})'    , 0, l(10), 64),
 545                 (IN | AE, 'cia_data_o({})'  , 0, l(20), 64),
 546                 (IN | AE, 'msr_data_o({})'  , 0, l(10), 64),
 547                 (IN | AE, 'src1_data_o({})' , 0, l(10), 64),
 548                 (IN | AE, 'src2_data_o({})' , 0, l(10), 64),
 549             ]
 550             )
 551         blockFast.state.cfg.etesian.uniformDensity = True
 552         blockFast.state.cfg.etesian.aspectRatio    = 1.0
 553         blockFast.state.cfg.etesian.spaceMargin    = 0.6
 554         blockFast.state.cfg.katana.searchHalo      = 1
 555         blockFast.state.useSpares   = False
 556        #rvalue = blockFast.build()
 557
 558         cellInt  = af.getCell( 'int', CRL.Catalog.State.Views )
 559         blockInt = Block.create \
 560             ( cellInt
 561             , ioPins=[
 562                 (IN     , 'coresync_clk'    , l(805.0) ),
 563                 (IW | AB, 'coresync_rst'    , 0, l(20),  1),
 564                 (IW | AB, 'wen({})'         , 0, l(20), 32),
 565                 (IW | AB, 'wen_1({})'       , 0, l(20), 32),
 566                 (IW | AB, 'src1_ren({})'    , 0, l(20), 32),
 567                 (IW | AB, 'src2_ren({})'    , 0, l(20), 32),
 568                 (IW | AB, 'src3_ren({})'    , 0, l(20), 32),
 569                 (IS | AB, 'data_i({})'      , 0, l(20), 64),
 570                 (IS | AB, 'data_i_2({})'    , 0, l(20), 64),
 571                 (IN | AE, 'src1_data_o({})' , 0, l(10), 64),
 572                 (IN | AE, 'src2_data_o({})' , 0, l(10), 64),
 573                 (IN | AE, 'src3_data_o({})' , 0, l(10), 64),
 574             ]
 575             )
 576         blockInt.state.cfg.etesian.uniformDensity = True
 577         blockInt.state.cfg.etesian.aspectRatio    = 1.0
 578         blockInt.state.cfg.etesian.spaceMargin    = 0.07
 579         blockInt.state.cfg.katana.searchHalo      = 1
 580         blockInt.state.useSpares   = False
 581        #rvalue = blockInt.build()
 582
 583         issuer      = af.getCell( 'test_issuer' , CRL.Catalog.State.Logical )
 584         blockIssuer = Block.create \
 585             ( issuer
 586             , ioPins=[]
 587             )
 588
 589         # Cell width:
 590         #
 591         # ================  =================
 592         # alu0              1200
 593         # branch0           1750
 594         # cr0                950
 595         # ldst0             1100
 596         # logical0          1800
 597         # mul0              9600
 598         # shiftrot0         2350
 599         # spr0              1550
 600         # trap0             3250
 601         # fast              ?
 602         # int               ?
 603         # pdecode           ?
 604         # ================  =================
 605
 606         blockIssuer.useBlockInstance(
 607                     'subckt_1150_core.subckt_2227_fus.subckt_0_alu0',
 608                     Transformation( l(1000), l(4000),
 609                     Transformation.Orientation.ID ))
 610         blockIssuer.useBlockInstance(
 611                     'subckt_1150_core.subckt_2227_fus.subckt_1_branch0',
 612                     Transformation( l(2700), l(4000),
 613                     Transformation.Orientation.ID ))
 614         blockIssuer.useBlockInstance(
 615                     'subckt_1150_core.subckt_2227_fus.subckt_2_cr0' ,
 616                     Transformation( l(4950), l(4000),
 617                     Transformation.Orientation.ID ))
 618         blockIssuer.useBlockInstance(
 619                     'subckt_1150_core.subckt_2227_fus.subckt_3_div0' ,
 620                     Transformation( l(27000), l(4000),
 621                         Transformation.Orientation.ID ))
 622         blockIssuer.useBlockInstance(
 623                     'subckt_1150_core.subckt_2227_fus.subckt_4_ldst0' ,
 624                     Transformation( l(6400), l(4000),
 625                         Transformation.Orientation.ID ))
 626         blockIssuer.useBlockInstance(
 627                     'subckt_1150_core.subckt_2227_fus.subckt_5_logical0' ,
 628                     Transformation( l(8000), l(4000),
 629                         Transformation.Orientation.ID ))
 630         blockIssuer.useBlockInstance(
 631                     'subckt_1150_core.subckt_2227_fus.subckt_6_mul0' ,
 632                     Transformation( l(10300), l(4000),
 633                         Transformation.Orientation.ID ))
 634         blockIssuer.useBlockInstance(
 635                     'subckt_1150_core.subckt_2227_fus.subckt_7_shiftrot0' ,
 636                     Transformation( l(20400), l(4000),
 637                         Transformation.Orientation.ID ))
 638         blockIssuer.useBlockInstance(
 639                     'subckt_1150_core.subckt_2227_fus.subckt_8_spr0' ,
 640                     Transformation( l(23250), l(4000),
 641                         Transformation.Orientation.ID ))
 642         blockIssuer.useBlockInstance(
 643                     'subckt_1150_core.subckt_2227_fus.subckt_9_trap0' ,
 644                     Transformation( l(25300), l(4000),
 645                         Transformation.Orientation.ID ))
 646         blockIssuer.useBlockInstance(
 647                     'subckt_1150_core.subckt_2226_fast' ,
 648                     Transformation( l(1000), l(4000),
 649                         Transformation.Orientation.ID ))
 650         blockIssuer.useBlockInstance(
 651                     'subckt_1150_core.subckt_2228_int' ,
 652                     Transformation( l(1000), l(4000),
 653                         Transformation.Orientation.ID ))
 654         # TODO, create pdecode2 block
 655         #blockIssuer.useBlockInstance(
 656         #            'subckt_1150_core.subckt_2230_pdecode2' ,
 657         #            Transformation( l(1000), l(4000),
 658         #                Transformation.Orientation.ID ))
 659
 660         blockIssuer.state.cfg.etesian.uniformDensity = True
 661         blockIssuer.state.cfg.etesian.aspectRatio    = 1.0
 662         blockIssuer.state.cfg.etesian.spaceMargin    = 0.07
 663         blockIssuer.state.cfg.katana.searchHalo      = 10000
 664         blockIssuer.state.fixedHeight = l(15000)
 665         blockIssuer.state.fixedWidth  = l(31550)
 666         blockIssuer.state.useSpares   = False
 667         blockIssuer.state.editor      = editor
 668         rvalue = blockIssuer.build()
 669     except Exception, e:
 670         helpers.io.catch( e )
 671         rvalue = False
 672
 673     sys.stdout.flush()
 674     sys.stderr.flush()
 675
 676     return rvalue
 677
 678
 679 if __name__ == '__main__':
 680     coriolis_setup()
 681     kwargs = {}
 682     success = scriptMain(**kwargs)
 683     shellSuccess = 0
 684     if not success:
 685         shellSuccess = 1
 686
 687     sys.exit(shellSuccess)