include (but do not use) FreePDK45 in experiments10
[soclayout.git] / experiments9 / doDesignFlat.py
1
2 from __future__ import print_function
3 import sys
4 import traceback
5 import CRL
6 import Cfg
7 import helpers
8 from helpers.io import ErrorMessage
9 from helpers.io import WarningMessage
10 from helpers.overlay import CfgCache
11 from helpers import trace, l
12 import plugins
13 from Hurricane import DbU
14 from Hurricane import Pin
15 from Hurricane import Transformation
16 from plugins.alpha.block.block import Block
17 from plugins.alpha.block.configuration import IoPin
18
19
20 af = CRL.AllianceFramework.get()
21
22
23 def coriolis_setup():
24 with CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
25 cfg.misc.catchCore = False
26 cfg.misc.info = False
27 cfg.misc.paranoid = False
28 cfg.misc.bug = False
29 cfg.misc.logMode = True
30 cfg.misc.verboseLevel1 = True
31 cfg.misc.verboseLevel2 = True
32 cfg.etesian.effort = 2
33 cfg.etesian.spaceMargin = 0.10 # 10%
34 cfg.etesian.aspectRatio = 1.0 # 100%
35 cfg.etesian.uniformDensity = True
36 cfg.anabatic.edgeLenght = 24
37 cfg.anabatic.edgeWidth = 8
38 cfg.anabatic.topRoutingLayer = 'METAL5'
39 cfg.katana.searchHalo = 30
40 cfg.katana.eventsLimit = 1000000
41 cfg.katana.hTracksReservedLocal = 7
42 cfg.katana.vTracksReservedLocal = 6
43
44 env = af.getEnvironment()
45 env.setCLOCK('^clk$|m_clock')
46 env.setPOWER('vdd')
47 env.setGROUND('vss')
48
49
50 def scriptMain ( **kw ):
51 """The mandatory function that Coriolis CGT/Unicorn will look for."""
52 global af
53
54 IW = IoPin.WEST
55 IE = IoPin.EAST
56 IS = IoPin.SOUTH
57 IN = IoPin.NORTH
58 AB = IoPin.A_BEGIN
59 AE = IoPin.A_END
60
61 rvalue = True
62 try:
63 #helpers.setTraceLevel( 550 )
64 cell, editor = plugins.kwParseMain( **kw )
65
66 # Quick and simple placement. I/O busses are grouped together.
67 # It may be useful to better choose the sides to give a hint to
68 # the placer about how to "blocks" must be positionned inside the
69 # chip.
70 #
71 # Note: Yes, blocks should be kept by the placer, in a fuzzy way.
72 issuerp = [
73 # Bit inputs.
74 (IN , 'clk' , l( 7050.0) ),
75 (IN | AB, 'rst' , l( 7000.0) ),
76 (IN | AB, 'core_bigendian_i', l( 7100.0) ),
77 (IN | AB, 'dbus_ack' , l( 7200.0) ),
78 (IN | AB, 'dbus_err' , l( 7300.0) ),
79 (IN | AB, 'ibus_ack' , l( 7400.0) ),
80 (IN | AB, 'ibus_err' , l( 7500.0) ),
81 (IN | AB, 'ibus_we' , l( 7600.0) ),
82 (IN | AE, 'ibus_stb' , l( 7700.0) ),
83 (IN | AB, 'dmi_req_i' , l( 7800.0) ),
84 (IN | AB, 'dmi_we_i' , l( 7900.0) ),
85 (IN | AB, 'memerr_o' , l( 8000.0) ),
86 (IN | AB, 'pc_i_ok' , l( 8100.0) ),
87 # Bit output.
88 (IN | AB, 'busy_o' , l( 8200.0) ),
89 (IN | AB, 'dbus_cyc' , l( 8300.0) ),
90 (IN | AB, 'dbus_stb' , l( 8400.0) ),
91 (IN | AB, 'dbus_we' , l( 8500.0) ),
92 (IN | AB, 'dmi_ack_o' , l( 8600.0) ),
93 (IN | AB, 'ibus_cyc' , l( 8700.0) ),
94 # Busses.
95 (IW | AB, 'dbus_bte({})' , l( 500.0), l( 50.0), 2),
96 (IW | AB, 'dbus_cti({})' , l( 600.0), l( 50.0), 3),
97 (IW | AB, 'dbus_sel({})' , l( 750.0), l( 50.0), 8),
98 (IW | AB, 'dbus_adr({})' , l( 1150.0), l( 50.0), 45),
99 (IW | AB, 'dbus_dat_r({})' , l( 3400.0), l( 50.0), 64),
100 (IW | AB, 'dbus_dat_w({})' , l( 6600.0), l( 50.0), 64),
101 (IW | AB, 'ibus_bte({})' , l( 9800.0), l( 50.0), 2),
102 (IW | AB, 'ibus_cti({})' , l( 9900.0), l( 50.0), 3),
103 (IW | AB, 'ibus_sel({})' , l(10050.0), l( 50.0), 8),
104 (IW | AB, 'ibus_adr({})' , l(10450.0), l( 50.0), 45),
105 (IN | AB, 'ibus_dat_r({})' , l( 500.0), l( 50.0), 64),
106 (IN | AE, 'ibus_dat_w({})' , l( 3700.0), l( 50.0), 64),
107 (IS | AB, 'dmi_addr_i({})' , l( 500.0), l( 50.0), 4),
108 (IS | AB, 'dmi_din({})' , l( 700.0), l( 50.0), 64),
109 (IS | AB, 'dmi_dout({})' , l( 3900.0), l( 50.0), 64),
110 (IS | AB, 'pc_i({})' , l( 7100.0), l( 50.0), 64),
111 (IS | AB, 'pc_o({})' , l(10300.0), l( 25.0), 64),
112 ]
113
114 issuer = af.getCell( 'test_issuer' , CRL.Catalog.State.Logical )
115 blockIssuer = Block.create( issuer , ioPins=issuerp )
116 blockIssuer.state.cfg.etesian.uniformDensity = True
117 blockIssuer.state.cfg.etesian.aspectRatio = 1.0
118 blockIssuer.state.cfg.etesian.spaceMargin = 0.15
119 blockIssuer.state.cfg.katana.searchHalo = 1
120 blockIssuer.state.cfg.katana.vTracksReservedLocal = 7
121 blockIssuer.state.cfg.katana.hTracksReservedLocal = 6
122 blockIssuer.state.cfg.katana.hTracksReservedMin = 2
123 blockIssuer.state.cfg.katana.vTracksReservedMin = 1
124 blockIssuer.state.cfg.katana.bloatOverloadAdd = 4
125 blockIssuer.state.cfg.block.spareSide = l(400)
126 #blockIssuer.state.fixedHeight = l(15000)
127 #blockIssuer.state.fixedWidth = l(31550)
128 blockIssuer.state.editor = editor
129 blockIssuer.state.useSpares = True
130 blockIssuer.state.useClockTree = True
131 blockIssuer.state.bColumns = 6
132 blockIssuer.state.bRows = 6
133 rvalue = blockIssuer.build()
134 except Exception, e:
135 helpers.io.catch( e )
136 rvalue = False
137
138 sys.stdout.flush()
139 sys.stderr.flush()
140 return rvalue
141
142
143 if __name__ == '__main__':
144 coriolis_setup()
145 kwargs = {}
146 success = scriptMain(**kwargs)
147 shellSuccess = 0
148 if not success:
149 shellSuccess = 1
150
151 sys.exit(shellSuccess)