experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v

   1 //--------------------------------------------------------------------------------
   2 // Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 20:07:56
   3 //--------------------------------------------------------------------------------
   4 module ls180(
   5         input wire uart_tx,
   6         input wire uart_rx,
   7         output wire i2c_scl,
   8         input wire i2c_sda_i,
   9         output wire i2c_sda_o,
  10         output wire i2c_sda_oe,
  11         output wire [12:0] sdram_a,
  12         input wire [15:0] sdram_dq_i,
  13         output wire [15:0] sdram_dq_o,
  14         output wire [15:0] sdram_dq_oe,
  15         output wire sdram_we_n,
  16         output wire sdram_ras_n,
  17         output wire sdram_cas_n,
  18         output wire sdram_cs_n,
  19         output wire sdram_cke,
  20         output wire [1:0] sdram_ba,
  21         output wire [1:0] sdram_dm,
  22         output wire sdram_clock,
  23         input wire eint_0,
  24         input wire eint_1,
  25         input wire eint_2,
  26         output wire spimaster_clk,
  27         output wire spimaster_mosi,
  28         output wire spimaster_cs_n,
  29         input wire spimaster_miso,
  30         input wire [15:0] gpio_i,
  31         output wire [15:0] gpio_o,
  32         output wire [15:0] gpio_oe,
  33         input wire sys_rst,
  34         input wire [1:0] sys_clksel_i,
  35         output wire sys_pll_testout_o,
  36         output wire sys_pll_vco_o,
  37         input wire sys_pllclk,
  38         input wire jtag_tms,
  39         input wire jtag_tck,
  40         input wire jtag_tdi,
  41         output wire jtag_tdo,
  42         input wire [19:0] nc
  43 );
  44
  45 (* ram_style = "distributed" *) reg main_libresocsim_reset_storage = 1'd0;
  46 reg main_libresocsim_reset_re = 1'd0;
  47 (* ram_style = "distributed" *) reg [31:0] main_libresocsim_scratch_storage = 32'd305419896;
  48 reg main_libresocsim_scratch_re = 1'd0;
  49 wire [31:0] main_libresocsim_bus_errors_status;
  50 wire main_libresocsim_bus_errors_we;
  51 wire main_libresocsim_reset;
  52 wire main_libresocsim_bus_error;
  53 reg [31:0] main_libresocsim_bus_errors = 32'd0;
  54 wire main_libresocsim_libresoc_reset;
  55 reg [15:0] main_libresocsim_libresoc_interrupt = 16'd0;
  56 wire [28:0] main_libresocsim_libresoc_dbus_adr;
  57 wire [63:0] main_libresocsim_libresoc_dbus_dat_w;
  58 wire [63:0] main_libresocsim_libresoc_dbus_dat_r;
  59 wire [7:0] main_libresocsim_libresoc_dbus_sel;
  60 wire main_libresocsim_libresoc_dbus_cyc;
  61 wire main_libresocsim_libresoc_dbus_stb;
  62 reg main_libresocsim_libresoc_dbus_ack = 1'd0;
  63 wire main_libresocsim_libresoc_dbus_we;
  64 reg main_libresocsim_libresoc_dbus_err = 1'd0;
  65 wire [28:0] main_libresocsim_libresoc_ibus_adr;
  66 wire [63:0] main_libresocsim_libresoc_ibus_dat_w;
  67 wire [63:0] main_libresocsim_libresoc_ibus_dat_r;
  68 wire [7:0] main_libresocsim_libresoc_ibus_sel;
  69 wire main_libresocsim_libresoc_ibus_cyc;
  70 wire main_libresocsim_libresoc_ibus_stb;
  71 reg main_libresocsim_libresoc_ibus_ack = 1'd0;
  72 wire main_libresocsim_libresoc_ibus_we;
  73 reg main_libresocsim_libresoc_ibus_err = 1'd0;
  74 wire [29:0] main_libresocsim_libresoc_xics_icp_adr;
  75 wire [31:0] main_libresocsim_libresoc_xics_icp_dat_w;
  76 wire [31:0] main_libresocsim_libresoc_xics_icp_dat_r;
  77 wire [3:0] main_libresocsim_libresoc_xics_icp_sel;
  78 wire main_libresocsim_libresoc_xics_icp_cyc;
  79 wire main_libresocsim_libresoc_xics_icp_stb;
  80 wire main_libresocsim_libresoc_xics_icp_ack;
  81 wire main_libresocsim_libresoc_xics_icp_we;
  82 wire [2:0] main_libresocsim_libresoc_xics_icp_cti;
  83 wire [1:0] main_libresocsim_libresoc_xics_icp_bte;
  84 wire main_libresocsim_libresoc_xics_icp_err;
  85 wire [29:0] main_libresocsim_libresoc_xics_ics_adr;
  86 wire [31:0] main_libresocsim_libresoc_xics_ics_dat_w;
  87 wire [31:0] main_libresocsim_libresoc_xics_ics_dat_r;
  88 wire [3:0] main_libresocsim_libresoc_xics_ics_sel;
  89 wire main_libresocsim_libresoc_xics_ics_cyc;
  90 wire main_libresocsim_libresoc_xics_ics_stb;
  91 wire main_libresocsim_libresoc_xics_ics_ack;
  92 wire main_libresocsim_libresoc_xics_ics_we;
  93 wire [2:0] main_libresocsim_libresoc_xics_ics_cti;
  94 wire [1:0] main_libresocsim_libresoc_xics_ics_bte;
  95 wire main_libresocsim_libresoc_xics_ics_err;
  96 wire [29:0] main_libresocsim_libresoc_jtag_wb_adr;
  97 wire [31:0] main_libresocsim_libresoc_jtag_wb_dat_w;
  98 wire [31:0] main_libresocsim_libresoc_jtag_wb_dat_r;
  99 wire [3:0] main_libresocsim_libresoc_jtag_wb_sel;
 100 wire main_libresocsim_libresoc_jtag_wb_cyc;
 101 wire main_libresocsim_libresoc_jtag_wb_stb;
 102 wire main_libresocsim_libresoc_jtag_wb_ack;
 103 wire main_libresocsim_libresoc_jtag_wb_we;
 104 reg [2:0] main_libresocsim_libresoc_jtag_wb_cti = 3'd0;
 105 reg [1:0] main_libresocsim_libresoc_jtag_wb_bte = 2'd0;
 106 wire main_libresocsim_libresoc_jtag_wb_err;
 107 reg [28:0] main_libresocsim_libresoc_interface0_adr = 29'd0;
 108 reg [63:0] main_libresocsim_libresoc_interface0_dat_w = 64'd0;
 109 wire [63:0] main_libresocsim_libresoc_interface0_dat_r;
 110 reg [7:0] main_libresocsim_libresoc_interface0_sel = 8'd0;
 111 wire main_libresocsim_libresoc_interface0_cyc;
 112 wire main_libresocsim_libresoc_interface0_stb;
 113 wire main_libresocsim_libresoc_interface0_ack;
 114 wire main_libresocsim_libresoc_interface0_we;
 115 wire [2:0] main_libresocsim_libresoc_interface0_cti;
 116 wire [1:0] main_libresocsim_libresoc_interface0_bte;
 117 reg main_libresocsim_libresoc_interface0_err = 1'd0;
 118 reg [28:0] main_libresocsim_libresoc_interface1_adr = 29'd0;
 119 reg [63:0] main_libresocsim_libresoc_interface1_dat_w = 64'd0;
 120 wire [63:0] main_libresocsim_libresoc_interface1_dat_r;
 121 reg [7:0] main_libresocsim_libresoc_interface1_sel = 8'd0;
 122 wire main_libresocsim_libresoc_interface1_cyc;
 123 wire main_libresocsim_libresoc_interface1_stb;
 124 wire main_libresocsim_libresoc_interface1_ack;
 125 wire main_libresocsim_libresoc_interface1_we;
 126 wire [2:0] main_libresocsim_libresoc_interface1_cti;
 127 wire [1:0] main_libresocsim_libresoc_interface1_bte;
 128 reg main_libresocsim_libresoc_interface1_err = 1'd0;
 129 reg [28:0] main_libresocsim_libresoc_interface2_adr = 29'd0;
 130 reg [63:0] main_libresocsim_libresoc_interface2_dat_w = 64'd0;
 131 wire [63:0] main_libresocsim_libresoc_interface2_dat_r;
 132 reg [7:0] main_libresocsim_libresoc_interface2_sel = 8'd0;
 133 wire main_libresocsim_libresoc_interface2_cyc;
 134 wire main_libresocsim_libresoc_interface2_stb;
 135 wire main_libresocsim_libresoc_interface2_ack;
 136 wire main_libresocsim_libresoc_interface2_we;
 137 wire [2:0] main_libresocsim_libresoc_interface2_cti;
 138 wire [1:0] main_libresocsim_libresoc_interface2_bte;
 139 reg main_libresocsim_libresoc_interface2_err = 1'd0;
 140 reg [28:0] main_libresocsim_libresoc_interface3_adr = 29'd0;
 141 reg [63:0] main_libresocsim_libresoc_interface3_dat_w = 64'd0;
 142 wire [63:0] main_libresocsim_libresoc_interface3_dat_r;
 143 reg [7:0] main_libresocsim_libresoc_interface3_sel = 8'd0;
 144 wire main_libresocsim_libresoc_interface3_cyc;
 145 wire main_libresocsim_libresoc_interface3_stb;
 146 wire main_libresocsim_libresoc_interface3_ack;
 147 wire main_libresocsim_libresoc_interface3_we;
 148 wire [2:0] main_libresocsim_libresoc_interface3_cti;
 149 wire [1:0] main_libresocsim_libresoc_interface3_bte;
 150 reg main_libresocsim_libresoc_interface3_err = 1'd0;
 151 wire main_libresocsim_libresoc_jtag_tck;
 152 wire main_libresocsim_libresoc_jtag_tms;
 153 wire main_libresocsim_libresoc_jtag_tdi;
 154 wire main_libresocsim_libresoc_jtag_tdo;
 155 reg [63:0] main_libresocsim_libresoc0 = 64'd0;
 156 wire main_libresocsim_libresoc1;
 157 wire main_libresocsim_libresoc2;
 158 wire [63:0] main_libresocsim_libresoc3;
 159 wire main_libresocsim_libresoc_pll_vco_o;
 160 wire [1:0] main_libresocsim_libresoc_clk_sel;
 161 wire main_libresocsim_libresoc_pll_test_o;
 162 wire main_libresocsim_libresoc_pll_24_i;
 163 reg main_libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
 164 reg main_libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
 165 wire main_libresocsim_libresoc_constraintmanager_i2c_scl;
 166 wire main_libresocsim_libresoc_constraintmanager_i2c_sda_i;
 167 wire main_libresocsim_libresoc_constraintmanager_i2c_sda_o;
 168 wire main_libresocsim_libresoc_constraintmanager_i2c_sda_oe;
 169 reg [12:0] main_libresocsim_libresoc_constraintmanager_sdram_a = 13'd0;
 170 wire [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_i;
 171 reg [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0;
 172 reg [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_oe = 16'd0;
 173 reg main_libresocsim_libresoc_constraintmanager_sdram_we_n = 1'd0;
 174 reg main_libresocsim_libresoc_constraintmanager_sdram_ras_n = 1'd0;
 175 reg main_libresocsim_libresoc_constraintmanager_sdram_cas_n = 1'd0;
 176 reg main_libresocsim_libresoc_constraintmanager_sdram_cs_n = 1'd0;
 177 reg main_libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0;
 178 reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0;
 179 reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0;
 180 reg main_libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0;
 181 wire main_libresocsim_libresoc_constraintmanager_eint_0;
 182 wire main_libresocsim_libresoc_constraintmanager_eint_1;
 183 wire main_libresocsim_libresoc_constraintmanager_eint_2;
 184 reg main_libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0;
 185 reg main_libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0;
 186 reg main_libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0;
 187 wire main_libresocsim_libresoc_constraintmanager_spimaster_miso;
 188 wire [15:0] main_libresocsim_libresoc_constraintmanager_gpio_i;
 189 reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_o = 16'd0;
 190 reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0;
 191 reg [29:0] main_libresocsim_interface0_converted_interface_adr = 30'd0;
 192 reg [31:0] main_libresocsim_interface0_converted_interface_dat_w = 32'd0;
 193 wire [31:0] main_libresocsim_interface0_converted_interface_dat_r;
 194 reg [3:0] main_libresocsim_interface0_converted_interface_sel = 4'd0;
 195 reg main_libresocsim_interface0_converted_interface_cyc = 1'd0;
 196 reg main_libresocsim_interface0_converted_interface_stb = 1'd0;
 197 wire main_libresocsim_interface0_converted_interface_ack;
 198 reg main_libresocsim_interface0_converted_interface_we = 1'd0;
 199 reg [2:0] main_libresocsim_interface0_converted_interface_cti = 3'd0;
 200 reg [1:0] main_libresocsim_interface0_converted_interface_bte = 2'd0;
 201 wire main_libresocsim_interface0_converted_interface_err;
 202 reg main_libresocsim_converter0_skip = 1'd0;
 203 reg main_libresocsim_converter0_counter = 1'd0;
 204 wire main_libresocsim_converter0_reset;
 205 reg [63:0] main_libresocsim_converter0_dat_r = 64'd0;
 206 reg [29:0] main_libresocsim_interface1_converted_interface_adr = 30'd0;
 207 reg [31:0] main_libresocsim_interface1_converted_interface_dat_w = 32'd0;
 208 wire [31:0] main_libresocsim_interface1_converted_interface_dat_r;
 209 reg [3:0] main_libresocsim_interface1_converted_interface_sel = 4'd0;
 210 reg main_libresocsim_interface1_converted_interface_cyc = 1'd0;
 211 reg main_libresocsim_interface1_converted_interface_stb = 1'd0;
 212 wire main_libresocsim_interface1_converted_interface_ack;
 213 reg main_libresocsim_interface1_converted_interface_we = 1'd0;
 214 reg [2:0] main_libresocsim_interface1_converted_interface_cti = 3'd0;
 215 reg [1:0] main_libresocsim_interface1_converted_interface_bte = 2'd0;
 216 wire main_libresocsim_interface1_converted_interface_err;
 217 reg main_libresocsim_converter1_skip = 1'd0;
 218 reg main_libresocsim_converter1_counter = 1'd0;
 219 wire main_libresocsim_converter1_reset;
 220 reg [63:0] main_libresocsim_converter1_dat_r = 64'd0;
 221 wire [29:0] main_libresocsim_ram_bus_adr;
 222 wire [31:0] main_libresocsim_ram_bus_dat_w;
 223 wire [31:0] main_libresocsim_ram_bus_dat_r;
 224 wire [3:0] main_libresocsim_ram_bus_sel;
 225 wire main_libresocsim_ram_bus_cyc;
 226 wire main_libresocsim_ram_bus_stb;
 227 reg main_libresocsim_ram_bus_ack = 1'd0;
 228 wire main_libresocsim_ram_bus_we;
 229 wire [2:0] main_libresocsim_ram_bus_cti;
 230 wire [1:0] main_libresocsim_ram_bus_bte;
 231 reg main_libresocsim_ram_bus_err = 1'd0;
 232 wire [4:0] main_libresocsim_adr;
 233 wire [31:0] main_libresocsim_dat_r;
 234 reg [3:0] main_libresocsim_we = 4'd0;
 235 wire [31:0] main_libresocsim_dat_w;
 236 (* ram_style = "distributed" *) reg [31:0] main_libresocsim_load_storage = 32'd0;
 237 reg main_libresocsim_load_re = 1'd0;
 238 (* ram_style = "distributed" *) reg [31:0] main_libresocsim_reload_storage = 32'd0;
 239 reg main_libresocsim_reload_re = 1'd0;
 240 (* ram_style = "distributed" *) reg main_libresocsim_en_storage = 1'd0;
 241 reg main_libresocsim_en_re = 1'd0;
 242 (* ram_style = "distributed" *) reg main_libresocsim_update_value_storage = 1'd0;
 243 reg main_libresocsim_update_value_re = 1'd0;
 244 reg [31:0] main_libresocsim_value_status = 32'd0;
 245 wire main_libresocsim_value_we;
 246 wire main_libresocsim_irq;
 247 wire main_libresocsim_zero_status;
 248 reg main_libresocsim_zero_pending = 1'd0;
 249 wire main_libresocsim_zero_trigger;
 250 reg main_libresocsim_zero_clear = 1'd0;
 251 reg main_libresocsim_zero_old_trigger = 1'd0;
 252 wire main_libresocsim_eventmanager_status_re;
 253 wire main_libresocsim_eventmanager_status_r;
 254 wire main_libresocsim_eventmanager_status_we;
 255 wire main_libresocsim_eventmanager_status_w;
 256 wire main_libresocsim_eventmanager_pending_re;
 257 wire main_libresocsim_eventmanager_pending_r;
 258 wire main_libresocsim_eventmanager_pending_we;
 259 wire main_libresocsim_eventmanager_pending_w;
 260 (* ram_style = "distributed" *) reg main_libresocsim_eventmanager_storage = 1'd0;
 261 reg main_libresocsim_eventmanager_re = 1'd0;
 262 reg [31:0] main_libresocsim_value = 32'd0;
 263 wire [29:0] main_ram_bus_ram_bus_adr;
 264 wire [31:0] main_ram_bus_ram_bus_dat_w;
 265 wire [31:0] main_ram_bus_ram_bus_dat_r;
 266 wire [3:0] main_ram_bus_ram_bus_sel;
 267 wire main_ram_bus_ram_bus_cyc;
 268 wire main_ram_bus_ram_bus_stb;
 269 reg main_ram_bus_ram_bus_ack = 1'd0;
 270 wire main_ram_bus_ram_bus_we;
 271 wire [2:0] main_ram_bus_ram_bus_cti;
 272 wire [1:0] main_ram_bus_ram_bus_bte;
 273 reg main_ram_bus_ram_bus_err = 1'd0;
 274 wire [4:0] main_ram_adr;
 275 wire [31:0] main_ram_dat_r;
 276 reg [3:0] main_ram_we = 4'd0;
 277 wire [31:0] main_ram_dat_w;
 278 wire [29:0] main_interface0_converted_interface_adr;
 279 wire [31:0] main_interface0_converted_interface_dat_w;
 280 reg [31:0] main_interface0_converted_interface_dat_r = 32'd0;
 281 wire [3:0] main_interface0_converted_interface_sel;
 282 wire main_interface0_converted_interface_cyc;
 283 wire main_interface0_converted_interface_stb;
 284 wire main_interface0_converted_interface_ack;
 285 wire main_interface0_converted_interface_we;
 286 wire [2:0] main_interface0_converted_interface_cti;
 287 wire [1:0] main_interface0_converted_interface_bte;
 288 wire main_interface0_converted_interface_err;
 289 wire [29:0] main_interface1_converted_interface_adr;
 290 wire [31:0] main_interface1_converted_interface_dat_w;
 291 reg [31:0] main_interface1_converted_interface_dat_r = 32'd0;
 292 wire [3:0] main_interface1_converted_interface_sel;
 293 wire main_interface1_converted_interface_cyc;
 294 wire main_interface1_converted_interface_stb;
 295 wire main_interface1_converted_interface_ack;
 296 wire main_interface1_converted_interface_we;
 297 wire [2:0] main_interface1_converted_interface_cti;
 298 wire [1:0] main_interface1_converted_interface_bte;
 299 wire main_interface1_converted_interface_err;
 300 wire [29:0] main_interface2_converted_interface_adr;
 301 wire [31:0] main_interface2_converted_interface_dat_w;
 302 reg [31:0] main_interface2_converted_interface_dat_r = 32'd0;
 303 wire [3:0] main_interface2_converted_interface_sel;
 304 wire main_interface2_converted_interface_cyc;
 305 wire main_interface2_converted_interface_stb;
 306 wire main_interface2_converted_interface_ack;
 307 wire main_interface2_converted_interface_we;
 308 wire [2:0] main_interface2_converted_interface_cti;
 309 wire [1:0] main_interface2_converted_interface_bte;
 310 wire main_interface2_converted_interface_err;
 311 wire [29:0] main_interface3_converted_interface_adr;
 312 wire [31:0] main_interface3_converted_interface_dat_w;
 313 reg [31:0] main_interface3_converted_interface_dat_r = 32'd0;
 314 wire [3:0] main_interface3_converted_interface_sel;
 315 wire main_interface3_converted_interface_cyc;
 316 wire main_interface3_converted_interface_stb;
 317 wire main_interface3_converted_interface_ack;
 318 wire main_interface3_converted_interface_we;
 319 wire [2:0] main_interface3_converted_interface_cti;
 320 wire [1:0] main_interface3_converted_interface_bte;
 321 wire main_interface3_converted_interface_err;
 322 wire sys_clk;
 323 wire sys_rst_1;
 324 wire por_clk;
 325 reg main_int_rst = 1'd1;
 326 wire pll_clk;
 327 wire [12:0] main_dfi_p0_address;
 328 wire [1:0] main_dfi_p0_bank;
 329 wire main_dfi_p0_cas_n;
 330 wire main_dfi_p0_cs_n;
 331 wire main_dfi_p0_ras_n;
 332 wire main_dfi_p0_we_n;
 333 wire main_dfi_p0_cke;
 334 wire main_dfi_p0_odt;
 335 wire main_dfi_p0_reset_n;
 336 wire main_dfi_p0_act_n;
 337 wire [15:0] main_dfi_p0_wrdata;
 338 wire main_dfi_p0_wrdata_en;
 339 wire [1:0] main_dfi_p0_wrdata_mask;
 340 wire main_dfi_p0_rddata_en;
 341 reg [15:0] main_dfi_p0_rddata = 16'd0;
 342 reg main_dfi_p0_rddata_valid = 1'd0;
 343 reg [2:0] main_rddata_en = 3'd0;
 344 wire [12:0] main_sdram_inti_p0_address;
 345 wire [1:0] main_sdram_inti_p0_bank;
 346 reg main_sdram_inti_p0_cas_n = 1'd1;
 347 reg main_sdram_inti_p0_cs_n = 1'd1;
 348 reg main_sdram_inti_p0_ras_n = 1'd1;
 349 reg main_sdram_inti_p0_we_n = 1'd1;
 350 wire main_sdram_inti_p0_cke;
 351 wire main_sdram_inti_p0_odt;
 352 wire main_sdram_inti_p0_reset_n;
 353 reg main_sdram_inti_p0_act_n = 1'd1;
 354 wire [15:0] main_sdram_inti_p0_wrdata;
 355 wire main_sdram_inti_p0_wrdata_en;
 356 wire [1:0] main_sdram_inti_p0_wrdata_mask;
 357 wire main_sdram_inti_p0_rddata_en;
 358 reg [15:0] main_sdram_inti_p0_rddata = 16'd0;
 359 reg main_sdram_inti_p0_rddata_valid = 1'd0;
 360 wire [12:0] main_sdram_slave_p0_address;
 361 wire [1:0] main_sdram_slave_p0_bank;
 362 wire main_sdram_slave_p0_cas_n;
 363 wire main_sdram_slave_p0_cs_n;
 364 wire main_sdram_slave_p0_ras_n;
 365 wire main_sdram_slave_p0_we_n;
 366 wire main_sdram_slave_p0_cke;
 367 wire main_sdram_slave_p0_odt;
 368 wire main_sdram_slave_p0_reset_n;
 369 wire main_sdram_slave_p0_act_n;
 370 wire [15:0] main_sdram_slave_p0_wrdata;
 371 wire main_sdram_slave_p0_wrdata_en;
 372 wire [1:0] main_sdram_slave_p0_wrdata_mask;
 373 wire main_sdram_slave_p0_rddata_en;
 374 reg [15:0] main_sdram_slave_p0_rddata = 16'd0;
 375 reg main_sdram_slave_p0_rddata_valid = 1'd0;
 376 reg [12:0] main_sdram_master_p0_address = 13'd0;
 377 reg [1:0] main_sdram_master_p0_bank = 2'd0;
 378 reg main_sdram_master_p0_cas_n = 1'd1;
 379 reg main_sdram_master_p0_cs_n = 1'd1;
 380 reg main_sdram_master_p0_ras_n = 1'd1;
 381 reg main_sdram_master_p0_we_n = 1'd1;
 382 reg main_sdram_master_p0_cke = 1'd0;
 383 reg main_sdram_master_p0_odt = 1'd0;
 384 reg main_sdram_master_p0_reset_n = 1'd0;
 385 reg main_sdram_master_p0_act_n = 1'd1;
 386 reg [15:0] main_sdram_master_p0_wrdata = 16'd0;
 387 reg main_sdram_master_p0_wrdata_en = 1'd0;
 388 reg [1:0] main_sdram_master_p0_wrdata_mask = 2'd0;
 389 reg main_sdram_master_p0_rddata_en = 1'd0;
 390 wire [15:0] main_sdram_master_p0_rddata;
 391 wire main_sdram_master_p0_rddata_valid;
 392 wire main_sdram_sel;
 393 wire main_sdram_cke;
 394 wire main_sdram_odt;
 395 wire main_sdram_reset_n;
 396 (* ram_style = "distributed" *) reg [3:0] main_sdram_storage = 4'd1;
 397 reg main_sdram_re = 1'd0;
 398 (* ram_style = "distributed" *) reg [5:0] main_sdram_command_storage = 6'd0;
 399 reg main_sdram_command_re = 1'd0;
 400 wire main_sdram_command_issue_re;
 401 wire main_sdram_command_issue_r;
 402 wire main_sdram_command_issue_we;
 403 reg main_sdram_command_issue_w = 1'd0;
 404 (* ram_style = "distributed" *) reg [12:0] main_sdram_address_storage = 13'd0;
 405 reg main_sdram_address_re = 1'd0;
 406 (* ram_style = "distributed" *) reg [1:0] main_sdram_baddress_storage = 2'd0;
 407 reg main_sdram_baddress_re = 1'd0;
 408 (* ram_style = "distributed" *) reg [15:0] main_sdram_wrdata_storage = 16'd0;
 409 reg main_sdram_wrdata_re = 1'd0;
 410 reg [15:0] main_sdram_status = 16'd0;
 411 wire main_sdram_we;
 412 wire main_sdram_interface_bank0_valid;
 413 wire main_sdram_interface_bank0_ready;
 414 wire main_sdram_interface_bank0_we;
 415 wire [21:0] main_sdram_interface_bank0_addr;
 416 wire main_sdram_interface_bank0_lock;
 417 wire main_sdram_interface_bank0_wdata_ready;
 418 wire main_sdram_interface_bank0_rdata_valid;
 419 wire main_sdram_interface_bank1_valid;
 420 wire main_sdram_interface_bank1_ready;
 421 wire main_sdram_interface_bank1_we;
 422 wire [21:0] main_sdram_interface_bank1_addr;
 423 wire main_sdram_interface_bank1_lock;
 424 wire main_sdram_interface_bank1_wdata_ready;
 425 wire main_sdram_interface_bank1_rdata_valid;
 426 wire main_sdram_interface_bank2_valid;
 427 wire main_sdram_interface_bank2_ready;
 428 wire main_sdram_interface_bank2_we;
 429 wire [21:0] main_sdram_interface_bank2_addr;
 430 wire main_sdram_interface_bank2_lock;
 431 wire main_sdram_interface_bank2_wdata_ready;
 432 wire main_sdram_interface_bank2_rdata_valid;
 433 wire main_sdram_interface_bank3_valid;
 434 wire main_sdram_interface_bank3_ready;
 435 wire main_sdram_interface_bank3_we;
 436 wire [21:0] main_sdram_interface_bank3_addr;
 437 wire main_sdram_interface_bank3_lock;
 438 wire main_sdram_interface_bank3_wdata_ready;
 439 wire main_sdram_interface_bank3_rdata_valid;
 440 reg [15:0] main_sdram_interface_wdata = 16'd0;
 441 reg [1:0] main_sdram_interface_wdata_we = 2'd0;
 442 wire [15:0] main_sdram_interface_rdata;
 443 reg [12:0] main_sdram_dfi_p0_address = 13'd0;
 444 reg [1:0] main_sdram_dfi_p0_bank = 2'd0;
 445 reg main_sdram_dfi_p0_cas_n = 1'd1;
 446 reg main_sdram_dfi_p0_cs_n = 1'd1;
 447 reg main_sdram_dfi_p0_ras_n = 1'd1;
 448 reg main_sdram_dfi_p0_we_n = 1'd1;
 449 wire main_sdram_dfi_p0_cke;
 450 wire main_sdram_dfi_p0_odt;
 451 wire main_sdram_dfi_p0_reset_n;
 452 reg main_sdram_dfi_p0_act_n = 1'd1;
 453 wire [15:0] main_sdram_dfi_p0_wrdata;
 454 reg main_sdram_dfi_p0_wrdata_en = 1'd0;
 455 wire [1:0] main_sdram_dfi_p0_wrdata_mask;
 456 reg main_sdram_dfi_p0_rddata_en = 1'd0;
 457 wire [15:0] main_sdram_dfi_p0_rddata;
 458 wire main_sdram_dfi_p0_rddata_valid;
 459 reg main_sdram_cmd_valid = 1'd0;
 460 reg main_sdram_cmd_ready = 1'd0;
 461 reg main_sdram_cmd_last = 1'd0;
 462 reg [12:0] main_sdram_cmd_payload_a = 13'd0;
 463 reg [1:0] main_sdram_cmd_payload_ba = 2'd0;
 464 reg main_sdram_cmd_payload_cas = 1'd0;
 465 reg main_sdram_cmd_payload_ras = 1'd0;
 466 reg main_sdram_cmd_payload_we = 1'd0;
 467 reg main_sdram_cmd_payload_is_read = 1'd0;
 468 reg main_sdram_cmd_payload_is_write = 1'd0;
 469 wire main_sdram_wants_refresh;
 470 wire main_sdram_timer_wait;
 471 wire main_sdram_timer_done0;
 472 wire [9:0] main_sdram_timer_count0;
 473 wire main_sdram_timer_done1;
 474 reg [9:0] main_sdram_timer_count1 = 10'd781;
 475 wire main_sdram_postponer_req_i;
 476 reg main_sdram_postponer_req_o = 1'd0;
 477 reg main_sdram_postponer_count = 1'd0;
 478 reg main_sdram_sequencer_start0 = 1'd0;
 479 wire main_sdram_sequencer_done0;
 480 wire main_sdram_sequencer_start1;
 481 reg main_sdram_sequencer_done1 = 1'd0;
 482 reg [3:0] main_sdram_sequencer_counter = 4'd0;
 483 reg main_sdram_sequencer_count = 1'd0;
 484 wire main_sdram_bankmachine0_req_valid;
 485 wire main_sdram_bankmachine0_req_ready;
 486 wire main_sdram_bankmachine0_req_we;
 487 wire [21:0] main_sdram_bankmachine0_req_addr;
 488 wire main_sdram_bankmachine0_req_lock;
 489 reg main_sdram_bankmachine0_req_wdata_ready = 1'd0;
 490 reg main_sdram_bankmachine0_req_rdata_valid = 1'd0;
 491 wire main_sdram_bankmachine0_refresh_req;
 492 reg main_sdram_bankmachine0_refresh_gnt = 1'd0;
 493 reg main_sdram_bankmachine0_cmd_valid = 1'd0;
 494 reg main_sdram_bankmachine0_cmd_ready = 1'd0;
 495 reg [12:0] main_sdram_bankmachine0_cmd_payload_a = 13'd0;
 496 wire [1:0] main_sdram_bankmachine0_cmd_payload_ba;
 497 reg main_sdram_bankmachine0_cmd_payload_cas = 1'd0;
 498 reg main_sdram_bankmachine0_cmd_payload_ras = 1'd0;
 499 reg main_sdram_bankmachine0_cmd_payload_we = 1'd0;
 500 reg main_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
 501 reg main_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
 502 reg main_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
 503 reg main_sdram_bankmachine0_auto_precharge = 1'd0;
 504 wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
 505 wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
 506 reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
 507 reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 508 wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 509 wire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 510 wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
 511 wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
 512 wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
 513 wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
 514 wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
 515 wire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
 516 wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
 517 wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
 518 wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 519 wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 520 wire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 521 wire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
 522 reg [3:0] main_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;
 523 reg main_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
 524 reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;
 525 reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;
 526 reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;
 527 wire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 528 wire main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
 529 wire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
 530 wire main_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
 531 wire [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
 532 wire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
 533 wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
 534 wire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
 535 wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
 536 wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
 537 wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 538 wire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 539 wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
 540 wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
 541 wire main_sdram_bankmachine0_cmd_buffer_sink_valid;
 542 wire main_sdram_bankmachine0_cmd_buffer_sink_ready;
 543 wire main_sdram_bankmachine0_cmd_buffer_sink_first;
 544 wire main_sdram_bankmachine0_cmd_buffer_sink_last;
 545 wire main_sdram_bankmachine0_cmd_buffer_sink_payload_we;
 546 wire [21:0] main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
 547 reg main_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
 548 wire main_sdram_bankmachine0_cmd_buffer_source_ready;
 549 reg main_sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
 550 reg main_sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
 551 reg main_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
 552 reg [21:0] main_sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
 553 reg [12:0] main_sdram_bankmachine0_row = 13'd0;
 554 reg main_sdram_bankmachine0_row_opened = 1'd0;
 555 wire main_sdram_bankmachine0_row_hit;
 556 reg main_sdram_bankmachine0_row_open = 1'd0;
 557 reg main_sdram_bankmachine0_row_close = 1'd0;
 558 reg main_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
 559 wire main_sdram_bankmachine0_twtpcon_valid;
 560 (* no_retiming = "true" *) reg main_sdram_bankmachine0_twtpcon_ready = 1'd0;
 561 reg [2:0] main_sdram_bankmachine0_twtpcon_count = 3'd0;
 562 wire main_sdram_bankmachine0_trccon_valid;
 563 (* no_retiming = "true" *) reg main_sdram_bankmachine0_trccon_ready = 1'd1;
 564 wire main_sdram_bankmachine0_trascon_valid;
 565 (* no_retiming = "true" *) reg main_sdram_bankmachine0_trascon_ready = 1'd1;
 566 wire main_sdram_bankmachine1_req_valid;
 567 wire main_sdram_bankmachine1_req_ready;
 568 wire main_sdram_bankmachine1_req_we;
 569 wire [21:0] main_sdram_bankmachine1_req_addr;
 570 wire main_sdram_bankmachine1_req_lock;
 571 reg main_sdram_bankmachine1_req_wdata_ready = 1'd0;
 572 reg main_sdram_bankmachine1_req_rdata_valid = 1'd0;
 573 wire main_sdram_bankmachine1_refresh_req;
 574 reg main_sdram_bankmachine1_refresh_gnt = 1'd0;
 575 reg main_sdram_bankmachine1_cmd_valid = 1'd0;
 576 reg main_sdram_bankmachine1_cmd_ready = 1'd0;
 577 reg [12:0] main_sdram_bankmachine1_cmd_payload_a = 13'd0;
 578 wire [1:0] main_sdram_bankmachine1_cmd_payload_ba;
 579 reg main_sdram_bankmachine1_cmd_payload_cas = 1'd0;
 580 reg main_sdram_bankmachine1_cmd_payload_ras = 1'd0;
 581 reg main_sdram_bankmachine1_cmd_payload_we = 1'd0;
 582 reg main_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
 583 reg main_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
 584 reg main_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
 585 reg main_sdram_bankmachine1_auto_precharge = 1'd0;
 586 wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
 587 wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
 588 reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
 589 reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 590 wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 591 wire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 592 wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
 593 wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
 594 wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
 595 wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
 596 wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
 597 wire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
 598 wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
 599 wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
 600 wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 601 wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 602 wire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 603 wire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
 604 reg [3:0] main_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;
 605 reg main_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
 606 reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;
 607 reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;
 608 reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;
 609 wire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 610 wire main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
 611 wire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
 612 wire main_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
 613 wire [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
 614 wire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
 615 wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
 616 wire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
 617 wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
 618 wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
 619 wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 620 wire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 621 wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
 622 wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
 623 wire main_sdram_bankmachine1_cmd_buffer_sink_valid;
 624 wire main_sdram_bankmachine1_cmd_buffer_sink_ready;
 625 wire main_sdram_bankmachine1_cmd_buffer_sink_first;
 626 wire main_sdram_bankmachine1_cmd_buffer_sink_last;
 627 wire main_sdram_bankmachine1_cmd_buffer_sink_payload_we;
 628 wire [21:0] main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
 629 reg main_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
 630 wire main_sdram_bankmachine1_cmd_buffer_source_ready;
 631 reg main_sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
 632 reg main_sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
 633 reg main_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
 634 reg [21:0] main_sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
 635 reg [12:0] main_sdram_bankmachine1_row = 13'd0;
 636 reg main_sdram_bankmachine1_row_opened = 1'd0;
 637 wire main_sdram_bankmachine1_row_hit;
 638 reg main_sdram_bankmachine1_row_open = 1'd0;
 639 reg main_sdram_bankmachine1_row_close = 1'd0;
 640 reg main_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
 641 wire main_sdram_bankmachine1_twtpcon_valid;
 642 (* no_retiming = "true" *) reg main_sdram_bankmachine1_twtpcon_ready = 1'd0;
 643 reg [2:0] main_sdram_bankmachine1_twtpcon_count = 3'd0;
 644 wire main_sdram_bankmachine1_trccon_valid;
 645 (* no_retiming = "true" *) reg main_sdram_bankmachine1_trccon_ready = 1'd1;
 646 wire main_sdram_bankmachine1_trascon_valid;
 647 (* no_retiming = "true" *) reg main_sdram_bankmachine1_trascon_ready = 1'd1;
 648 wire main_sdram_bankmachine2_req_valid;
 649 wire main_sdram_bankmachine2_req_ready;
 650 wire main_sdram_bankmachine2_req_we;
 651 wire [21:0] main_sdram_bankmachine2_req_addr;
 652 wire main_sdram_bankmachine2_req_lock;
 653 reg main_sdram_bankmachine2_req_wdata_ready = 1'd0;
 654 reg main_sdram_bankmachine2_req_rdata_valid = 1'd0;
 655 wire main_sdram_bankmachine2_refresh_req;
 656 reg main_sdram_bankmachine2_refresh_gnt = 1'd0;
 657 reg main_sdram_bankmachine2_cmd_valid = 1'd0;
 658 reg main_sdram_bankmachine2_cmd_ready = 1'd0;
 659 reg [12:0] main_sdram_bankmachine2_cmd_payload_a = 13'd0;
 660 wire [1:0] main_sdram_bankmachine2_cmd_payload_ba;
 661 reg main_sdram_bankmachine2_cmd_payload_cas = 1'd0;
 662 reg main_sdram_bankmachine2_cmd_payload_ras = 1'd0;
 663 reg main_sdram_bankmachine2_cmd_payload_we = 1'd0;
 664 reg main_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
 665 reg main_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
 666 reg main_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
 667 reg main_sdram_bankmachine2_auto_precharge = 1'd0;
 668 wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
 669 wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
 670 reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
 671 reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 672 wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 673 wire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 674 wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
 675 wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
 676 wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
 677 wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
 678 wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
 679 wire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
 680 wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
 681 wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
 682 wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 683 wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 684 wire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 685 wire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
 686 reg [3:0] main_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;
 687 reg main_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
 688 reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;
 689 reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;
 690 reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;
 691 wire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 692 wire main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
 693 wire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
 694 wire main_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
 695 wire [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
 696 wire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
 697 wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
 698 wire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
 699 wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
 700 wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
 701 wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 702 wire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 703 wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
 704 wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
 705 wire main_sdram_bankmachine2_cmd_buffer_sink_valid;
 706 wire main_sdram_bankmachine2_cmd_buffer_sink_ready;
 707 wire main_sdram_bankmachine2_cmd_buffer_sink_first;
 708 wire main_sdram_bankmachine2_cmd_buffer_sink_last;
 709 wire main_sdram_bankmachine2_cmd_buffer_sink_payload_we;
 710 wire [21:0] main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
 711 reg main_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
 712 wire main_sdram_bankmachine2_cmd_buffer_source_ready;
 713 reg main_sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
 714 reg main_sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
 715 reg main_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
 716 reg [21:0] main_sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
 717 reg [12:0] main_sdram_bankmachine2_row = 13'd0;
 718 reg main_sdram_bankmachine2_row_opened = 1'd0;
 719 wire main_sdram_bankmachine2_row_hit;
 720 reg main_sdram_bankmachine2_row_open = 1'd0;
 721 reg main_sdram_bankmachine2_row_close = 1'd0;
 722 reg main_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
 723 wire main_sdram_bankmachine2_twtpcon_valid;
 724 (* no_retiming = "true" *) reg main_sdram_bankmachine2_twtpcon_ready = 1'd0;
 725 reg [2:0] main_sdram_bankmachine2_twtpcon_count = 3'd0;
 726 wire main_sdram_bankmachine2_trccon_valid;
 727 (* no_retiming = "true" *) reg main_sdram_bankmachine2_trccon_ready = 1'd1;
 728 wire main_sdram_bankmachine2_trascon_valid;
 729 (* no_retiming = "true" *) reg main_sdram_bankmachine2_trascon_ready = 1'd1;
 730 wire main_sdram_bankmachine3_req_valid;
 731 wire main_sdram_bankmachine3_req_ready;
 732 wire main_sdram_bankmachine3_req_we;
 733 wire [21:0] main_sdram_bankmachine3_req_addr;
 734 wire main_sdram_bankmachine3_req_lock;
 735 reg main_sdram_bankmachine3_req_wdata_ready = 1'd0;
 736 reg main_sdram_bankmachine3_req_rdata_valid = 1'd0;
 737 wire main_sdram_bankmachine3_refresh_req;
 738 reg main_sdram_bankmachine3_refresh_gnt = 1'd0;
 739 reg main_sdram_bankmachine3_cmd_valid = 1'd0;
 740 reg main_sdram_bankmachine3_cmd_ready = 1'd0;
 741 reg [12:0] main_sdram_bankmachine3_cmd_payload_a = 13'd0;
 742 wire [1:0] main_sdram_bankmachine3_cmd_payload_ba;
 743 reg main_sdram_bankmachine3_cmd_payload_cas = 1'd0;
 744 reg main_sdram_bankmachine3_cmd_payload_ras = 1'd0;
 745 reg main_sdram_bankmachine3_cmd_payload_we = 1'd0;
 746 reg main_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
 747 reg main_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
 748 reg main_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
 749 reg main_sdram_bankmachine3_auto_precharge = 1'd0;
 750 wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
 751 wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
 752 reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
 753 reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 754 wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 755 wire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 756 wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
 757 wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
 758 wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
 759 wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
 760 wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
 761 wire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
 762 wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
 763 wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
 764 wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 765 wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 766 wire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 767 wire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
 768 reg [3:0] main_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;
 769 reg main_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
 770 reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;
 771 reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;
 772 reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;
 773 wire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 774 wire main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
 775 wire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
 776 wire main_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
 777 wire [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
 778 wire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
 779 wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
 780 wire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
 781 wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
 782 wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
 783 wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 784 wire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 785 wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
 786 wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
 787 wire main_sdram_bankmachine3_cmd_buffer_sink_valid;
 788 wire main_sdram_bankmachine3_cmd_buffer_sink_ready;
 789 wire main_sdram_bankmachine3_cmd_buffer_sink_first;
 790 wire main_sdram_bankmachine3_cmd_buffer_sink_last;
 791 wire main_sdram_bankmachine3_cmd_buffer_sink_payload_we;
 792 wire [21:0] main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
 793 reg main_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
 794 wire main_sdram_bankmachine3_cmd_buffer_source_ready;
 795 reg main_sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
 796 reg main_sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
 797 reg main_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
 798 reg [21:0] main_sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
 799 reg [12:0] main_sdram_bankmachine3_row = 13'd0;
 800 reg main_sdram_bankmachine3_row_opened = 1'd0;
 801 wire main_sdram_bankmachine3_row_hit;
 802 reg main_sdram_bankmachine3_row_open = 1'd0;
 803 reg main_sdram_bankmachine3_row_close = 1'd0;
 804 reg main_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
 805 wire main_sdram_bankmachine3_twtpcon_valid;
 806 (* no_retiming = "true" *) reg main_sdram_bankmachine3_twtpcon_ready = 1'd0;
 807 reg [2:0] main_sdram_bankmachine3_twtpcon_count = 3'd0;
 808 wire main_sdram_bankmachine3_trccon_valid;
 809 (* no_retiming = "true" *) reg main_sdram_bankmachine3_trccon_ready = 1'd1;
 810 wire main_sdram_bankmachine3_trascon_valid;
 811 (* no_retiming = "true" *) reg main_sdram_bankmachine3_trascon_ready = 1'd1;
 812 wire main_sdram_ras_allowed;
 813 wire main_sdram_cas_allowed;
 814 reg main_sdram_choose_cmd_want_reads = 1'd0;
 815 reg main_sdram_choose_cmd_want_writes = 1'd0;
 816 reg main_sdram_choose_cmd_want_cmds = 1'd0;
 817 reg main_sdram_choose_cmd_want_activates = 1'd0;
 818 wire main_sdram_choose_cmd_cmd_valid;
 819 reg main_sdram_choose_cmd_cmd_ready = 1'd0;
 820 wire [12:0] main_sdram_choose_cmd_cmd_payload_a;
 821 wire [1:0] main_sdram_choose_cmd_cmd_payload_ba;
 822 reg main_sdram_choose_cmd_cmd_payload_cas = 1'd0;
 823 reg main_sdram_choose_cmd_cmd_payload_ras = 1'd0;
 824 reg main_sdram_choose_cmd_cmd_payload_we = 1'd0;
 825 wire main_sdram_choose_cmd_cmd_payload_is_cmd;
 826 wire main_sdram_choose_cmd_cmd_payload_is_read;
 827 wire main_sdram_choose_cmd_cmd_payload_is_write;
 828 reg [3:0] main_sdram_choose_cmd_valids = 4'd0;
 829 wire [3:0] main_sdram_choose_cmd_request;
 830 reg [1:0] main_sdram_choose_cmd_grant = 2'd0;
 831 wire main_sdram_choose_cmd_ce;
 832 reg main_sdram_choose_req_want_reads = 1'd0;
 833 reg main_sdram_choose_req_want_writes = 1'd0;
 834 wire main_sdram_choose_req_want_cmds;
 835 reg main_sdram_choose_req_want_activates = 1'd0;
 836 wire main_sdram_choose_req_cmd_valid;
 837 reg main_sdram_choose_req_cmd_ready = 1'd0;
 838 wire [12:0] main_sdram_choose_req_cmd_payload_a;
 839 wire [1:0] main_sdram_choose_req_cmd_payload_ba;
 840 reg main_sdram_choose_req_cmd_payload_cas = 1'd0;
 841 reg main_sdram_choose_req_cmd_payload_ras = 1'd0;
 842 reg main_sdram_choose_req_cmd_payload_we = 1'd0;
 843 wire main_sdram_choose_req_cmd_payload_is_cmd;
 844 wire main_sdram_choose_req_cmd_payload_is_read;
 845 wire main_sdram_choose_req_cmd_payload_is_write;
 846 reg [3:0] main_sdram_choose_req_valids = 4'd0;
 847 wire [3:0] main_sdram_choose_req_request;
 848 reg [1:0] main_sdram_choose_req_grant = 2'd0;
 849 wire main_sdram_choose_req_ce;
 850 reg [12:0] main_sdram_nop_a = 13'd0;
 851 reg [1:0] main_sdram_nop_ba = 2'd0;
 852 reg [1:0] main_sdram_steerer_sel = 2'd0;
 853 reg main_sdram_steerer0 = 1'd1;
 854 reg main_sdram_steerer1 = 1'd1;
 855 wire main_sdram_trrdcon_valid;
 856 (* no_retiming = "true" *) reg main_sdram_trrdcon_ready = 1'd1;
 857 wire main_sdram_tfawcon_valid;
 858 (* no_retiming = "true" *) reg main_sdram_tfawcon_ready = 1'd1;
 859 wire main_sdram_tccdcon_valid;
 860 (* no_retiming = "true" *) reg main_sdram_tccdcon_ready = 1'd0;
 861 reg main_sdram_tccdcon_count = 1'd0;
 862 wire main_sdram_twtrcon_valid;
 863 (* no_retiming = "true" *) reg main_sdram_twtrcon_ready = 1'd0;
 864 reg [2:0] main_sdram_twtrcon_count = 3'd0;
 865 wire main_sdram_read_available;
 866 wire main_sdram_write_available;
 867 reg main_sdram_en0 = 1'd0;
 868 wire main_sdram_max_time0;
 869 reg [4:0] main_sdram_time0 = 5'd0;
 870 reg main_sdram_en1 = 1'd0;
 871 wire main_sdram_max_time1;
 872 reg [3:0] main_sdram_time1 = 4'd0;
 873 wire main_sdram_go_to_refresh;
 874 wire main_port_flush;
 875 wire main_port_cmd_valid;
 876 wire main_port_cmd_ready;
 877 wire main_port_cmd_last;
 878 wire main_port_cmd_payload_we;
 879 wire [23:0] main_port_cmd_payload_addr;
 880 wire main_port_wdata_valid;
 881 wire main_port_wdata_ready;
 882 wire [15:0] main_port_wdata_payload_data;
 883 wire [1:0] main_port_wdata_payload_we;
 884 wire main_port_rdata_valid;
 885 wire main_port_rdata_ready;
 886 wire [15:0] main_port_rdata_payload_data;
 887 wire [29:0] main_wb_sdram_adr;
 888 wire [31:0] main_wb_sdram_dat_w;
 889 wire [31:0] main_wb_sdram_dat_r;
 890 wire [3:0] main_wb_sdram_sel;
 891 wire main_wb_sdram_cyc;
 892 wire main_wb_sdram_stb;
 893 reg main_wb_sdram_ack = 1'd0;
 894 wire main_wb_sdram_we;
 895 wire [2:0] main_wb_sdram_cti;
 896 wire [1:0] main_wb_sdram_bte;
 897 reg main_wb_sdram_err = 1'd0;
 898 reg [29:0] main_litedram_wb_adr = 30'd0;
 899 reg [15:0] main_litedram_wb_dat_w = 16'd0;
 900 wire [15:0] main_litedram_wb_dat_r;
 901 reg [1:0] main_litedram_wb_sel = 2'd0;
 902 reg main_litedram_wb_cyc = 1'd0;
 903 reg main_litedram_wb_stb = 1'd0;
 904 wire main_litedram_wb_ack;
 905 reg main_litedram_wb_we = 1'd0;
 906 reg main_converter_skip = 1'd0;
 907 reg main_converter_counter = 1'd0;
 908 wire main_converter_reset;
 909 reg [31:0] main_converter_dat_r = 32'd0;
 910 reg main_cmd_consumed = 1'd0;
 911 reg main_wdata_consumed = 1'd0;
 912 wire main_ack_cmd;
 913 wire main_ack_wdata;
 914 wire main_ack_rdata;
 915 (* ram_style = "distributed" *) reg [31:0] main_uart_phy_storage = 32'd9895604;
 916 reg main_uart_phy_re = 1'd0;
 917 wire main_uart_phy_sink_valid;
 918 reg main_uart_phy_sink_ready = 1'd0;
 919 wire main_uart_phy_sink_first;
 920 wire main_uart_phy_sink_last;
 921 wire [7:0] main_uart_phy_sink_payload_data;
 922 reg main_uart_phy_uart_clk_txen = 1'd0;
 923 reg [31:0] main_uart_phy_phase_accumulator_tx = 32'd0;
 924 reg [7:0] main_uart_phy_tx_reg = 8'd0;
 925 reg [3:0] main_uart_phy_tx_bitcount = 4'd0;
 926 reg main_uart_phy_tx_busy = 1'd0;
 927 reg main_uart_phy_source_valid = 1'd0;
 928 wire main_uart_phy_source_ready;
 929 reg main_uart_phy_source_first = 1'd0;
 930 reg main_uart_phy_source_last = 1'd0;
 931 reg [7:0] main_uart_phy_source_payload_data = 8'd0;
 932 reg main_uart_phy_uart_clk_rxen = 1'd0;
 933 reg [31:0] main_uart_phy_phase_accumulator_rx = 32'd0;
 934 wire main_uart_phy_rx;
 935 reg main_uart_phy_rx_r = 1'd0;
 936 reg [7:0] main_uart_phy_rx_reg = 8'd0;
 937 reg [3:0] main_uart_phy_rx_bitcount = 4'd0;
 938 reg main_uart_phy_rx_busy = 1'd0;
 939 wire main_rxtx_re;
 940 wire [7:0] main_rxtx_r;
 941 wire main_rxtx_we;
 942 wire [7:0] main_rxtx_w;
 943 wire main_txfull_status;
 944 wire main_txfull_we;
 945 wire main_rxempty_status;
 946 wire main_rxempty_we;
 947 wire main_irq;
 948 wire main_tx_status;
 949 reg main_tx_pending = 1'd0;
 950 wire main_tx_trigger;
 951 reg main_tx_clear = 1'd0;
 952 reg main_tx_old_trigger = 1'd0;
 953 wire main_rx_status;
 954 reg main_rx_pending = 1'd0;
 955 wire main_rx_trigger;
 956 reg main_rx_clear = 1'd0;
 957 reg main_rx_old_trigger = 1'd0;
 958 wire main_eventmanager_status_re;
 959 wire [1:0] main_eventmanager_status_r;
 960 wire main_eventmanager_status_we;
 961 reg [1:0] main_eventmanager_status_w = 2'd0;
 962 wire main_eventmanager_pending_re;
 963 wire [1:0] main_eventmanager_pending_r;
 964 wire main_eventmanager_pending_we;
 965 reg [1:0] main_eventmanager_pending_w = 2'd0;
 966 (* ram_style = "distributed" *) reg [1:0] main_eventmanager_storage = 2'd0;
 967 reg main_eventmanager_re = 1'd0;
 968 wire main_txempty_status;
 969 wire main_txempty_we;
 970 wire main_rxfull_status;
 971 wire main_rxfull_we;
 972 wire main_uart_sink_valid;
 973 wire main_uart_sink_ready;
 974 wire main_uart_sink_first;
 975 wire main_uart_sink_last;
 976 wire [7:0] main_uart_sink_payload_data;
 977 wire main_uart_source_valid;
 978 wire main_uart_source_ready;
 979 wire main_uart_source_first;
 980 wire main_uart_source_last;
 981 wire [7:0] main_uart_source_payload_data;
 982 wire main_tx_fifo_sink_valid;
 983 wire main_tx_fifo_sink_ready;
 984 reg main_tx_fifo_sink_first = 1'd0;
 985 reg main_tx_fifo_sink_last = 1'd0;
 986 wire [7:0] main_tx_fifo_sink_payload_data;
 987 wire main_tx_fifo_source_valid;
 988 wire main_tx_fifo_source_ready;
 989 wire main_tx_fifo_source_first;
 990 wire main_tx_fifo_source_last;
 991 wire [7:0] main_tx_fifo_source_payload_data;
 992 wire main_tx_fifo_re;
 993 reg main_tx_fifo_readable = 1'd0;
 994 wire main_tx_fifo_syncfifo_we;
 995 wire main_tx_fifo_syncfifo_writable;
 996 wire main_tx_fifo_syncfifo_re;
 997 wire main_tx_fifo_syncfifo_readable;
 998 wire [9:0] main_tx_fifo_syncfifo_din;
 999 wire [9:0] main_tx_fifo_syncfifo_dout;
1000 reg [4:0] main_tx_fifo_level0 = 5'd0;
1001 reg main_tx_fifo_replace = 1'd0;
1002 reg [3:0] main_tx_fifo_produce = 4'd0;
1003 reg [3:0] main_tx_fifo_consume = 4'd0;
1004 reg [3:0] main_tx_fifo_wrport_adr = 4'd0;
1005 wire [9:0] main_tx_fifo_wrport_dat_r;
1006 wire main_tx_fifo_wrport_we;
1007 wire [9:0] main_tx_fifo_wrport_dat_w;
1008 wire main_tx_fifo_do_read;
1009 wire [3:0] main_tx_fifo_rdport_adr;
1010 wire [9:0] main_tx_fifo_rdport_dat_r;
1011 wire main_tx_fifo_rdport_re;
1012 wire [4:0] main_tx_fifo_level1;
1013 wire [7:0] main_tx_fifo_fifo_in_payload_data;
1014 wire main_tx_fifo_fifo_in_first;
1015 wire main_tx_fifo_fifo_in_last;
1016 wire [7:0] main_tx_fifo_fifo_out_payload_data;
1017 wire main_tx_fifo_fifo_out_first;
1018 wire main_tx_fifo_fifo_out_last;
1019 wire main_rx_fifo_sink_valid;
1020 wire main_rx_fifo_sink_ready;
1021 wire main_rx_fifo_sink_first;
1022 wire main_rx_fifo_sink_last;
1023 wire [7:0] main_rx_fifo_sink_payload_data;
1024 wire main_rx_fifo_source_valid;
1025 wire main_rx_fifo_source_ready;
1026 wire main_rx_fifo_source_first;
1027 wire main_rx_fifo_source_last;
1028 wire [7:0] main_rx_fifo_source_payload_data;
1029 wire main_rx_fifo_re;
1030 reg main_rx_fifo_readable = 1'd0;
1031 wire main_rx_fifo_syncfifo_we;
1032 wire main_rx_fifo_syncfifo_writable;
1033 wire main_rx_fifo_syncfifo_re;
1034 wire main_rx_fifo_syncfifo_readable;
1035 wire [9:0] main_rx_fifo_syncfifo_din;
1036 wire [9:0] main_rx_fifo_syncfifo_dout;
1037 reg [4:0] main_rx_fifo_level0 = 5'd0;
1038 reg main_rx_fifo_replace = 1'd0;
1039 reg [3:0] main_rx_fifo_produce = 4'd0;
1040 reg [3:0] main_rx_fifo_consume = 4'd0;
1041 reg [3:0] main_rx_fifo_wrport_adr = 4'd0;
1042 wire [9:0] main_rx_fifo_wrport_dat_r;
1043 wire main_rx_fifo_wrport_we;
1044 wire [9:0] main_rx_fifo_wrport_dat_w;
1045 wire main_rx_fifo_do_read;
1046 wire [3:0] main_rx_fifo_rdport_adr;
1047 wire [9:0] main_rx_fifo_rdport_dat_r;
1048 wire main_rx_fifo_rdport_re;
1049 wire [4:0] main_rx_fifo_level1;
1050 wire [7:0] main_rx_fifo_fifo_in_payload_data;
1051 wire main_rx_fifo_fifo_in_first;
1052 wire main_rx_fifo_fifo_in_last;
1053 wire [7:0] main_rx_fifo_fifo_out_payload_data;
1054 wire main_rx_fifo_fifo_out_first;
1055 wire main_rx_fifo_fifo_out_last;
1056 reg main_reset = 1'd0;
1057 (* ram_style = "distributed" *) reg [7:0] main_gpio0_oe_storage = 8'd0;
1058 reg main_gpio0_oe_re = 1'd0;
1059 reg [7:0] main_gpio0_status = 8'd0;
1060 wire main_gpio0_we;
1061 (* ram_style = "distributed" *) reg [7:0] main_gpio0_out_storage = 8'd0;
1062 reg main_gpio0_out_re = 1'd0;
1063 reg [7:0] main_gpio0_pads_gpio0i = 8'd0;
1064 reg [7:0] main_gpio0_pads_gpio0o = 8'd0;
1065 reg [7:0] main_gpio0_pads_gpio0oe = 8'd0;
1066 (* ram_style = "distributed" *) reg [7:0] main_gpio1_oe_storage = 8'd0;
1067 reg main_gpio1_oe_re = 1'd0;
1068 reg [7:0] main_gpio1_status = 8'd0;
1069 wire main_gpio1_we;
1070 (* ram_style = "distributed" *) reg [7:0] main_gpio1_out_storage = 8'd0;
1071 reg main_gpio1_out_re = 1'd0;
1072 reg [7:0] main_gpio1_pads_gpio1i = 8'd0;
1073 reg [7:0] main_gpio1_pads_gpio1o = 8'd0;
1074 reg [7:0] main_gpio1_pads_gpio1oe = 8'd0;
1075 reg [2:0] main_eint_tmp = 3'd0;
1076 wire [19:0] main_nc;
1077 reg [19:0] main_dummy = 20'd0;
1078 wire main_i2c_scl;
1079 wire main_i2c_oe;
1080 wire main_i2c_sda0;
1081 (* ram_style = "distributed" *) reg [2:0] main_i2c_storage = 3'd0;
1082 reg main_i2c_re = 1'd0;
1083 wire main_i2c_sda1;
1084 wire main_i2c_status;
1085 wire main_i2c_we;
1086 reg builder_subfragments_converter0_state = 1'd0;
1087 reg builder_subfragments_converter0_next_state = 1'd0;
1088 reg main_libresocsim_converter0_counter_subfragments_converter0_next_value = 1'd0;
1089 reg main_libresocsim_converter0_counter_subfragments_converter0_next_value_ce = 1'd0;
1090 reg builder_subfragments_converter1_state = 1'd0;
1091 reg builder_subfragments_converter1_next_state = 1'd0;
1092 reg main_libresocsim_converter1_counter_subfragments_converter1_next_value = 1'd0;
1093 reg main_libresocsim_converter1_counter_subfragments_converter1_next_value_ce = 1'd0;
1094 reg [1:0] builder_subfragments_refresher_state = 2'd0;
1095 reg [1:0] builder_subfragments_refresher_next_state = 2'd0;
1096 reg [2:0] builder_subfragments_bankmachine0_state = 3'd0;
1097 reg [2:0] builder_subfragments_bankmachine0_next_state = 3'd0;
1098 reg [2:0] builder_subfragments_bankmachine1_state = 3'd0;
1099 reg [2:0] builder_subfragments_bankmachine1_next_state = 3'd0;
1100 reg [2:0] builder_subfragments_bankmachine2_state = 3'd0;
1101 reg [2:0] builder_subfragments_bankmachine2_next_state = 3'd0;
1102 reg [2:0] builder_subfragments_bankmachine3_state = 3'd0;
1103 reg [2:0] builder_subfragments_bankmachine3_next_state = 3'd0;
1104 reg [2:0] builder_subfragments_multiplexer_state = 3'd0;
1105 reg [2:0] builder_subfragments_multiplexer_next_state = 3'd0;
1106 wire builder_subfragments_roundrobin0_request;
1107 wire builder_subfragments_roundrobin0_grant;
1108 wire builder_subfragments_roundrobin0_ce;
1109 wire builder_subfragments_roundrobin1_request;
1110 wire builder_subfragments_roundrobin1_grant;
1111 wire builder_subfragments_roundrobin1_ce;
1112 wire builder_subfragments_roundrobin2_request;
1113 wire builder_subfragments_roundrobin2_grant;
1114 wire builder_subfragments_roundrobin2_ce;
1115 wire builder_subfragments_roundrobin3_request;
1116 wire builder_subfragments_roundrobin3_grant;
1117 wire builder_subfragments_roundrobin3_ce;
1118 reg builder_subfragments_locked0 = 1'd0;
1119 reg builder_subfragments_locked1 = 1'd0;
1120 reg builder_subfragments_locked2 = 1'd0;
1121 reg builder_subfragments_locked3 = 1'd0;
1122 reg builder_subfragments_new_master_wdata_ready = 1'd0;
1123 reg builder_subfragments_new_master_rdata_valid0 = 1'd0;
1124 reg builder_subfragments_new_master_rdata_valid1 = 1'd0;
1125 reg builder_subfragments_new_master_rdata_valid2 = 1'd0;
1126 reg builder_subfragments_new_master_rdata_valid3 = 1'd0;
1127 reg builder_subfragments_state = 1'd0;
1128 reg builder_subfragments_next_state = 1'd0;
1129 reg main_converter_counter_subfragments_next_value = 1'd0;
1130 reg main_converter_counter_subfragments_next_value_ce = 1'd0;
1131 reg [12:0] builder_libresocsim_libresocsim_adr = 13'd0;
1132 reg builder_libresocsim_libresocsim_we = 1'd0;
1133 reg [7:0] builder_libresocsim_libresocsim_dat_w = 8'd0;
1134 wire [7:0] builder_libresocsim_libresocsim_dat_r;
1135 wire [29:0] builder_libresocsim_libresocsim_wishbone_adr;
1136 wire [31:0] builder_libresocsim_libresocsim_wishbone_dat_w;
1137 reg [31:0] builder_libresocsim_libresocsim_wishbone_dat_r = 32'd0;
1138 wire [3:0] builder_libresocsim_libresocsim_wishbone_sel;
1139 wire builder_libresocsim_libresocsim_wishbone_cyc;
1140 wire builder_libresocsim_libresocsim_wishbone_stb;
1141 reg builder_libresocsim_libresocsim_wishbone_ack = 1'd0;
1142 wire builder_libresocsim_libresocsim_wishbone_we;
1143 wire [2:0] builder_libresocsim_libresocsim_wishbone_cti;
1144 wire [1:0] builder_libresocsim_libresocsim_wishbone_bte;
1145 reg builder_libresocsim_libresocsim_wishbone_err = 1'd0;
1146 wire [29:0] builder_libresocsim_shared_adr;
1147 wire [31:0] builder_libresocsim_shared_dat_w;
1148 reg [31:0] builder_libresocsim_shared_dat_r = 32'd0;
1149 wire [3:0] builder_libresocsim_shared_sel;
1150 wire builder_libresocsim_shared_cyc;
1151 wire builder_libresocsim_shared_stb;
1152 reg builder_libresocsim_shared_ack = 1'd0;
1153 wire builder_libresocsim_shared_we;
1154 wire [2:0] builder_libresocsim_shared_cti;
1155 wire [1:0] builder_libresocsim_shared_bte;
1156 wire builder_libresocsim_shared_err;
1157 wire [2:0] builder_libresocsim_request;
1158 reg [1:0] builder_libresocsim_grant = 2'd0;
1159 reg [9:0] builder_libresocsim_slave_sel = 10'd0;
1160 reg [9:0] builder_libresocsim_slave_sel_r = 10'd0;
1161 reg builder_libresocsim_error = 1'd0;
1162 wire builder_libresocsim_wait;
1163 wire builder_libresocsim_done;
1164 reg [19:0] builder_libresocsim_count = 20'd1000000;
1165 wire [12:0] builder_libresocsim_interface0_bank_bus_adr;
1166 wire builder_libresocsim_interface0_bank_bus_we;
1167 wire [7:0] builder_libresocsim_interface0_bank_bus_dat_w;
1168 reg [7:0] builder_libresocsim_interface0_bank_bus_dat_r = 8'd0;
1169 wire builder_libresocsim_csrbank0_reset0_re;
1170 wire builder_libresocsim_csrbank0_reset0_r;
1171 wire builder_libresocsim_csrbank0_reset0_we;
1172 wire builder_libresocsim_csrbank0_reset0_w;
1173 wire builder_libresocsim_csrbank0_scratch3_re;
1174 wire [7:0] builder_libresocsim_csrbank0_scratch3_r;
1175 wire builder_libresocsim_csrbank0_scratch3_we;
1176 wire [7:0] builder_libresocsim_csrbank0_scratch3_w;
1177 wire builder_libresocsim_csrbank0_scratch2_re;
1178 wire [7:0] builder_libresocsim_csrbank0_scratch2_r;
1179 wire builder_libresocsim_csrbank0_scratch2_we;
1180 wire [7:0] builder_libresocsim_csrbank0_scratch2_w;
1181 wire builder_libresocsim_csrbank0_scratch1_re;
1182 wire [7:0] builder_libresocsim_csrbank0_scratch1_r;
1183 wire builder_libresocsim_csrbank0_scratch1_we;
1184 wire [7:0] builder_libresocsim_csrbank0_scratch1_w;
1185 wire builder_libresocsim_csrbank0_scratch0_re;
1186 wire [7:0] builder_libresocsim_csrbank0_scratch0_r;
1187 wire builder_libresocsim_csrbank0_scratch0_we;
1188 wire [7:0] builder_libresocsim_csrbank0_scratch0_w;
1189 wire builder_libresocsim_csrbank0_bus_errors3_re;
1190 wire [7:0] builder_libresocsim_csrbank0_bus_errors3_r;
1191 wire builder_libresocsim_csrbank0_bus_errors3_we;
1192 wire [7:0] builder_libresocsim_csrbank0_bus_errors3_w;
1193 wire builder_libresocsim_csrbank0_bus_errors2_re;
1194 wire [7:0] builder_libresocsim_csrbank0_bus_errors2_r;
1195 wire builder_libresocsim_csrbank0_bus_errors2_we;
1196 wire [7:0] builder_libresocsim_csrbank0_bus_errors2_w;
1197 wire builder_libresocsim_csrbank0_bus_errors1_re;
1198 wire [7:0] builder_libresocsim_csrbank0_bus_errors1_r;
1199 wire builder_libresocsim_csrbank0_bus_errors1_we;
1200 wire [7:0] builder_libresocsim_csrbank0_bus_errors1_w;
1201 wire builder_libresocsim_csrbank0_bus_errors0_re;
1202 wire [7:0] builder_libresocsim_csrbank0_bus_errors0_r;
1203 wire builder_libresocsim_csrbank0_bus_errors0_we;
1204 wire [7:0] builder_libresocsim_csrbank0_bus_errors0_w;
1205 wire builder_libresocsim_csrbank0_sel;
1206 wire [12:0] builder_libresocsim_interface1_bank_bus_adr;
1207 wire builder_libresocsim_interface1_bank_bus_we;
1208 wire [7:0] builder_libresocsim_interface1_bank_bus_dat_w;
1209 reg [7:0] builder_libresocsim_interface1_bank_bus_dat_r = 8'd0;
1210 wire builder_libresocsim_csrbank1_oe0_re;
1211 wire [7:0] builder_libresocsim_csrbank1_oe0_r;
1212 wire builder_libresocsim_csrbank1_oe0_we;
1213 wire [7:0] builder_libresocsim_csrbank1_oe0_w;
1214 wire builder_libresocsim_csrbank1_in_re;
1215 wire [7:0] builder_libresocsim_csrbank1_in_r;
1216 wire builder_libresocsim_csrbank1_in_we;
1217 wire [7:0] builder_libresocsim_csrbank1_in_w;
1218 wire builder_libresocsim_csrbank1_out0_re;
1219 wire [7:0] builder_libresocsim_csrbank1_out0_r;
1220 wire builder_libresocsim_csrbank1_out0_we;
1221 wire [7:0] builder_libresocsim_csrbank1_out0_w;
1222 wire builder_libresocsim_csrbank1_sel;
1223 wire [12:0] builder_libresocsim_interface2_bank_bus_adr;
1224 wire builder_libresocsim_interface2_bank_bus_we;
1225 wire [7:0] builder_libresocsim_interface2_bank_bus_dat_w;
1226 reg [7:0] builder_libresocsim_interface2_bank_bus_dat_r = 8'd0;
1227 wire builder_libresocsim_csrbank2_oe0_re;
1228 wire [7:0] builder_libresocsim_csrbank2_oe0_r;
1229 wire builder_libresocsim_csrbank2_oe0_we;
1230 wire [7:0] builder_libresocsim_csrbank2_oe0_w;
1231 wire builder_libresocsim_csrbank2_in_re;
1232 wire [7:0] builder_libresocsim_csrbank2_in_r;
1233 wire builder_libresocsim_csrbank2_in_we;
1234 wire [7:0] builder_libresocsim_csrbank2_in_w;
1235 wire builder_libresocsim_csrbank2_out0_re;
1236 wire [7:0] builder_libresocsim_csrbank2_out0_r;
1237 wire builder_libresocsim_csrbank2_out0_we;
1238 wire [7:0] builder_libresocsim_csrbank2_out0_w;
1239 wire builder_libresocsim_csrbank2_sel;
1240 wire [12:0] builder_libresocsim_interface3_bank_bus_adr;
1241 wire builder_libresocsim_interface3_bank_bus_we;
1242 wire [7:0] builder_libresocsim_interface3_bank_bus_dat_w;
1243 reg [7:0] builder_libresocsim_interface3_bank_bus_dat_r = 8'd0;
1244 wire builder_libresocsim_csrbank3_w0_re;
1245 wire [2:0] builder_libresocsim_csrbank3_w0_r;
1246 wire builder_libresocsim_csrbank3_w0_we;
1247 wire [2:0] builder_libresocsim_csrbank3_w0_w;
1248 wire builder_libresocsim_csrbank3_r_re;
1249 wire builder_libresocsim_csrbank3_r_r;
1250 wire builder_libresocsim_csrbank3_r_we;
1251 wire builder_libresocsim_csrbank3_r_w;
1252 wire builder_libresocsim_csrbank3_sel;
1253 wire [12:0] builder_libresocsim_interface4_bank_bus_adr;
1254 wire builder_libresocsim_interface4_bank_bus_we;
1255 wire [7:0] builder_libresocsim_interface4_bank_bus_dat_w;
1256 reg [7:0] builder_libresocsim_interface4_bank_bus_dat_r = 8'd0;
1257 wire builder_libresocsim_csrbank4_dfii_control0_re;
1258 wire [3:0] builder_libresocsim_csrbank4_dfii_control0_r;
1259 wire builder_libresocsim_csrbank4_dfii_control0_we;
1260 wire [3:0] builder_libresocsim_csrbank4_dfii_control0_w;
1261 wire builder_libresocsim_csrbank4_dfii_pi0_command0_re;
1262 wire [5:0] builder_libresocsim_csrbank4_dfii_pi0_command0_r;
1263 wire builder_libresocsim_csrbank4_dfii_pi0_command0_we;
1264 wire [5:0] builder_libresocsim_csrbank4_dfii_pi0_command0_w;
1265 wire builder_libresocsim_csrbank4_dfii_pi0_address1_re;
1266 wire [4:0] builder_libresocsim_csrbank4_dfii_pi0_address1_r;
1267 wire builder_libresocsim_csrbank4_dfii_pi0_address1_we;
1268 wire [4:0] builder_libresocsim_csrbank4_dfii_pi0_address1_w;
1269 wire builder_libresocsim_csrbank4_dfii_pi0_address0_re;
1270 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_address0_r;
1271 wire builder_libresocsim_csrbank4_dfii_pi0_address0_we;
1272 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_address0_w;
1273 wire builder_libresocsim_csrbank4_dfii_pi0_baddress0_re;
1274 wire [1:0] builder_libresocsim_csrbank4_dfii_pi0_baddress0_r;
1275 wire builder_libresocsim_csrbank4_dfii_pi0_baddress0_we;
1276 wire [1:0] builder_libresocsim_csrbank4_dfii_pi0_baddress0_w;
1277 wire builder_libresocsim_csrbank4_dfii_pi0_wrdata1_re;
1278 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_wrdata1_r;
1279 wire builder_libresocsim_csrbank4_dfii_pi0_wrdata1_we;
1280 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_wrdata1_w;
1281 wire builder_libresocsim_csrbank4_dfii_pi0_wrdata0_re;
1282 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_wrdata0_r;
1283 wire builder_libresocsim_csrbank4_dfii_pi0_wrdata0_we;
1284 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_wrdata0_w;
1285 wire builder_libresocsim_csrbank4_dfii_pi0_rddata1_re;
1286 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_rddata1_r;
1287 wire builder_libresocsim_csrbank4_dfii_pi0_rddata1_we;
1288 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_rddata1_w;
1289 wire builder_libresocsim_csrbank4_dfii_pi0_rddata0_re;
1290 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_rddata0_r;
1291 wire builder_libresocsim_csrbank4_dfii_pi0_rddata0_we;
1292 wire [7:0] builder_libresocsim_csrbank4_dfii_pi0_rddata0_w;
1293 wire builder_libresocsim_csrbank4_sel;
1294 wire [12:0] builder_libresocsim_interface5_bank_bus_adr;
1295 wire builder_libresocsim_interface5_bank_bus_we;
1296 wire [7:0] builder_libresocsim_interface5_bank_bus_dat_w;
1297 reg [7:0] builder_libresocsim_interface5_bank_bus_dat_r = 8'd0;
1298 wire builder_libresocsim_csrbank5_load3_re;
1299 wire [7:0] builder_libresocsim_csrbank5_load3_r;
1300 wire builder_libresocsim_csrbank5_load3_we;
1301 wire [7:0] builder_libresocsim_csrbank5_load3_w;
1302 wire builder_libresocsim_csrbank5_load2_re;
1303 wire [7:0] builder_libresocsim_csrbank5_load2_r;
1304 wire builder_libresocsim_csrbank5_load2_we;
1305 wire [7:0] builder_libresocsim_csrbank5_load2_w;
1306 wire builder_libresocsim_csrbank5_load1_re;
1307 wire [7:0] builder_libresocsim_csrbank5_load1_r;
1308 wire builder_libresocsim_csrbank5_load1_we;
1309 wire [7:0] builder_libresocsim_csrbank5_load1_w;
1310 wire builder_libresocsim_csrbank5_load0_re;
1311 wire [7:0] builder_libresocsim_csrbank5_load0_r;
1312 wire builder_libresocsim_csrbank5_load0_we;
1313 wire [7:0] builder_libresocsim_csrbank5_load0_w;
1314 wire builder_libresocsim_csrbank5_reload3_re;
1315 wire [7:0] builder_libresocsim_csrbank5_reload3_r;
1316 wire builder_libresocsim_csrbank5_reload3_we;
1317 wire [7:0] builder_libresocsim_csrbank5_reload3_w;
1318 wire builder_libresocsim_csrbank5_reload2_re;
1319 wire [7:0] builder_libresocsim_csrbank5_reload2_r;
1320 wire builder_libresocsim_csrbank5_reload2_we;
1321 wire [7:0] builder_libresocsim_csrbank5_reload2_w;
1322 wire builder_libresocsim_csrbank5_reload1_re;
1323 wire [7:0] builder_libresocsim_csrbank5_reload1_r;
1324 wire builder_libresocsim_csrbank5_reload1_we;
1325 wire [7:0] builder_libresocsim_csrbank5_reload1_w;
1326 wire builder_libresocsim_csrbank5_reload0_re;
1327 wire [7:0] builder_libresocsim_csrbank5_reload0_r;
1328 wire builder_libresocsim_csrbank5_reload0_we;
1329 wire [7:0] builder_libresocsim_csrbank5_reload0_w;
1330 wire builder_libresocsim_csrbank5_en0_re;
1331 wire builder_libresocsim_csrbank5_en0_r;
1332 wire builder_libresocsim_csrbank5_en0_we;
1333 wire builder_libresocsim_csrbank5_en0_w;
1334 wire builder_libresocsim_csrbank5_update_value0_re;
1335 wire builder_libresocsim_csrbank5_update_value0_r;
1336 wire builder_libresocsim_csrbank5_update_value0_we;
1337 wire builder_libresocsim_csrbank5_update_value0_w;
1338 wire builder_libresocsim_csrbank5_value3_re;
1339 wire [7:0] builder_libresocsim_csrbank5_value3_r;
1340 wire builder_libresocsim_csrbank5_value3_we;
1341 wire [7:0] builder_libresocsim_csrbank5_value3_w;
1342 wire builder_libresocsim_csrbank5_value2_re;
1343 wire [7:0] builder_libresocsim_csrbank5_value2_r;
1344 wire builder_libresocsim_csrbank5_value2_we;
1345 wire [7:0] builder_libresocsim_csrbank5_value2_w;
1346 wire builder_libresocsim_csrbank5_value1_re;
1347 wire [7:0] builder_libresocsim_csrbank5_value1_r;
1348 wire builder_libresocsim_csrbank5_value1_we;
1349 wire [7:0] builder_libresocsim_csrbank5_value1_w;
1350 wire builder_libresocsim_csrbank5_value0_re;
1351 wire [7:0] builder_libresocsim_csrbank5_value0_r;
1352 wire builder_libresocsim_csrbank5_value0_we;
1353 wire [7:0] builder_libresocsim_csrbank5_value0_w;
1354 wire builder_libresocsim_csrbank5_ev_enable0_re;
1355 wire builder_libresocsim_csrbank5_ev_enable0_r;
1356 wire builder_libresocsim_csrbank5_ev_enable0_we;
1357 wire builder_libresocsim_csrbank5_ev_enable0_w;
1358 wire builder_libresocsim_csrbank5_sel;
1359 wire [12:0] builder_libresocsim_interface6_bank_bus_adr;
1360 wire builder_libresocsim_interface6_bank_bus_we;
1361 wire [7:0] builder_libresocsim_interface6_bank_bus_dat_w;
1362 reg [7:0] builder_libresocsim_interface6_bank_bus_dat_r = 8'd0;
1363 wire builder_libresocsim_csrbank6_txfull_re;
1364 wire builder_libresocsim_csrbank6_txfull_r;
1365 wire builder_libresocsim_csrbank6_txfull_we;
1366 wire builder_libresocsim_csrbank6_txfull_w;
1367 wire builder_libresocsim_csrbank6_rxempty_re;
1368 wire builder_libresocsim_csrbank6_rxempty_r;
1369 wire builder_libresocsim_csrbank6_rxempty_we;
1370 wire builder_libresocsim_csrbank6_rxempty_w;
1371 wire builder_libresocsim_csrbank6_ev_enable0_re;
1372 wire [1:0] builder_libresocsim_csrbank6_ev_enable0_r;
1373 wire builder_libresocsim_csrbank6_ev_enable0_we;
1374 wire [1:0] builder_libresocsim_csrbank6_ev_enable0_w;
1375 wire builder_libresocsim_csrbank6_txempty_re;
1376 wire builder_libresocsim_csrbank6_txempty_r;
1377 wire builder_libresocsim_csrbank6_txempty_we;
1378 wire builder_libresocsim_csrbank6_txempty_w;
1379 wire builder_libresocsim_csrbank6_rxfull_re;
1380 wire builder_libresocsim_csrbank6_rxfull_r;
1381 wire builder_libresocsim_csrbank6_rxfull_we;
1382 wire builder_libresocsim_csrbank6_rxfull_w;
1383 wire builder_libresocsim_csrbank6_sel;
1384 wire [12:0] builder_libresocsim_interface7_bank_bus_adr;
1385 wire builder_libresocsim_interface7_bank_bus_we;
1386 wire [7:0] builder_libresocsim_interface7_bank_bus_dat_w;
1387 reg [7:0] builder_libresocsim_interface7_bank_bus_dat_r = 8'd0;
1388 wire builder_libresocsim_csrbank7_tuning_word3_re;
1389 wire [7:0] builder_libresocsim_csrbank7_tuning_word3_r;
1390 wire builder_libresocsim_csrbank7_tuning_word3_we;
1391 wire [7:0] builder_libresocsim_csrbank7_tuning_word3_w;
1392 wire builder_libresocsim_csrbank7_tuning_word2_re;
1393 wire [7:0] builder_libresocsim_csrbank7_tuning_word2_r;
1394 wire builder_libresocsim_csrbank7_tuning_word2_we;
1395 wire [7:0] builder_libresocsim_csrbank7_tuning_word2_w;
1396 wire builder_libresocsim_csrbank7_tuning_word1_re;
1397 wire [7:0] builder_libresocsim_csrbank7_tuning_word1_r;
1398 wire builder_libresocsim_csrbank7_tuning_word1_we;
1399 wire [7:0] builder_libresocsim_csrbank7_tuning_word1_w;
1400 wire builder_libresocsim_csrbank7_tuning_word0_re;
1401 wire [7:0] builder_libresocsim_csrbank7_tuning_word0_r;
1402 wire builder_libresocsim_csrbank7_tuning_word0_we;
1403 wire [7:0] builder_libresocsim_csrbank7_tuning_word0_w;
1404 wire builder_libresocsim_csrbank7_sel;
1405 wire [12:0] builder_libresocsim_csr_interconnect_adr;
1406 wire builder_libresocsim_csr_interconnect_we;
1407 wire [7:0] builder_libresocsim_csr_interconnect_dat_w;
1408 wire [7:0] builder_libresocsim_csr_interconnect_dat_r;
1409 reg [1:0] builder_libresocsim_state = 2'd0;
1410 reg [1:0] builder_libresocsim_next_state = 2'd0;
1411 reg [7:0] builder_libresocsim_libresocsim_dat_w_libresocsim_next_value0 = 8'd0;
1412 reg builder_libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 = 1'd0;
1413 reg [12:0] builder_libresocsim_libresocsim_adr_libresocsim_next_value1 = 13'd0;
1414 reg builder_libresocsim_libresocsim_adr_libresocsim_next_value_ce1 = 1'd0;
1415 reg builder_libresocsim_libresocsim_we_libresocsim_next_value2 = 1'd0;
1416 reg builder_libresocsim_libresocsim_we_libresocsim_next_value_ce2 = 1'd0;
1417 reg builder_rhs_array_muxed0 = 1'd0;
1418 reg [12:0] builder_rhs_array_muxed1 = 13'd0;
1419 reg [1:0] builder_rhs_array_muxed2 = 2'd0;
1420 reg builder_rhs_array_muxed3 = 1'd0;
1421 reg builder_rhs_array_muxed4 = 1'd0;
1422 reg builder_rhs_array_muxed5 = 1'd0;
1423 reg builder_t_array_muxed0 = 1'd0;
1424 reg builder_t_array_muxed1 = 1'd0;
1425 reg builder_t_array_muxed2 = 1'd0;
1426 reg builder_rhs_array_muxed6 = 1'd0;
1427 reg [12:0] builder_rhs_array_muxed7 = 13'd0;
1428 reg [1:0] builder_rhs_array_muxed8 = 2'd0;
1429 reg builder_rhs_array_muxed9 = 1'd0;
1430 reg builder_rhs_array_muxed10 = 1'd0;
1431 reg builder_rhs_array_muxed11 = 1'd0;
1432 reg builder_t_array_muxed3 = 1'd0;
1433 reg builder_t_array_muxed4 = 1'd0;
1434 reg builder_t_array_muxed5 = 1'd0;
1435 reg [21:0] builder_rhs_array_muxed12 = 22'd0;
1436 reg builder_rhs_array_muxed13 = 1'd0;
1437 reg builder_rhs_array_muxed14 = 1'd0;
1438 reg [21:0] builder_rhs_array_muxed15 = 22'd0;
1439 reg builder_rhs_array_muxed16 = 1'd0;
1440 reg builder_rhs_array_muxed17 = 1'd0;
1441 reg [21:0] builder_rhs_array_muxed18 = 22'd0;
1442 reg builder_rhs_array_muxed19 = 1'd0;
1443 reg builder_rhs_array_muxed20 = 1'd0;
1444 reg [21:0] builder_rhs_array_muxed21 = 22'd0;
1445 reg builder_rhs_array_muxed22 = 1'd0;
1446 reg builder_rhs_array_muxed23 = 1'd0;
1447 reg [29:0] builder_rhs_array_muxed24 = 30'd0;
1448 reg [31:0] builder_rhs_array_muxed25 = 32'd0;
1449 reg [3:0] builder_rhs_array_muxed26 = 4'd0;
1450 reg builder_rhs_array_muxed27 = 1'd0;
1451 reg builder_rhs_array_muxed28 = 1'd0;
1452 reg builder_rhs_array_muxed29 = 1'd0;
1453 reg [2:0] builder_rhs_array_muxed30 = 3'd0;
1454 reg [1:0] builder_rhs_array_muxed31 = 2'd0;
1455 reg [1:0] builder_array_muxed0 = 2'd0;
1456 reg [12:0] builder_array_muxed1 = 13'd0;
1457 reg builder_array_muxed2 = 1'd0;
1458 reg builder_array_muxed3 = 1'd0;
1459 reg builder_array_muxed4 = 1'd0;
1460 reg builder_array_muxed5 = 1'd0;
1461 reg builder_array_muxed6 = 1'd0;
1462 wire sdrio_clk;
1463 wire sdrio_clk_1;
1464 wire sdrio_clk_2;
1465 wire sdrio_clk_3;
1466 wire sdrio_clk_4;
1467 wire sdrio_clk_5;
1468 wire sdrio_clk_6;
1469 wire sdrio_clk_7;
1470 wire sdrio_clk_8;
1471 wire sdrio_clk_9;
1472 wire sdrio_clk_10;
1473 wire sdrio_clk_11;
1474 wire sdrio_clk_12;
1475 wire sdrio_clk_13;
1476 wire sdrio_clk_14;
1477 wire sdrio_clk_15;
1478 wire sdrio_clk_16;
1479 wire sdrio_clk_17;
1480 wire sdrio_clk_18;
1481 wire sdrio_clk_19;
1482 wire sdrio_clk_20;
1483 wire sdrio_clk_21;
1484 wire sdrio_clk_22;
1485 wire sdrio_clk_23;
1486 wire sdrio_clk_24;
1487 wire sdrio_clk_25;
1488 wire sdrio_clk_26;
1489 wire sdrio_clk_27;
1490 wire sdrio_clk_28;
1491 wire sdrio_clk_29;
1492 wire sdrio_clk_30;
1493 wire sdrio_clk_31;
1494 wire sdrio_clk_32;
1495 wire sdrio_clk_33;
1496 wire sdrio_clk_34;
1497 wire sdrio_clk_35;
1498 wire sdrio_clk_36;
1499 wire sdrio_clk_37;
1500 wire sdrio_clk_38;
1501 wire sdrio_clk_39;
1502 wire sdrio_clk_40;
1503 wire sdrio_clk_41;
1504 wire sdrio_clk_42;
1505 wire sdrio_clk_43;
1506 wire sdrio_clk_44;
1507 wire sdrio_clk_45;
1508 wire sdrio_clk_46;
1509 wire sdrio_clk_47;
1510 wire sdrio_clk_48;
1511 wire sdrio_clk_49;
1512 wire sdrio_clk_50;
1513 wire sdrio_clk_51;
1514 wire sdrio_clk_52;
1515 wire sdrio_clk_53;
1516 wire sdrio_clk_54;
1517 wire sdrio_clk_55;
1518 wire sdrio_clk_56;
1519 wire sdrio_clk_57;
1520 wire sdrio_clk_58;
1521 wire sdrio_clk_59;
1522 wire sdrio_clk_60;
1523 wire sdrio_clk_61;
1524 wire sdrio_clk_62;
1525 wire sdrio_clk_63;
1526 wire sdrio_clk_64;
1527 wire sdrio_clk_65;
1528 wire sdrio_clk_66;
1529 wire sdrio_clk_67;
1530 wire sdrio_clk_68;
1531 wire sdrio_clk_69;
1532 wire sdrio_clk_70;
1533 (* no_retiming = "true" *) reg builder_regs0 = 1'd0;
1534 (* no_retiming = "true" *) reg builder_regs1 = 1'd0;
1535 wire sdrio_clk_71;
1536 wire sdrio_clk_72;
1537 wire sdrio_clk_73;
1538 wire sdrio_clk_74;
1539 wire sdrio_clk_75;
1540 wire sdrio_clk_76;
1541 wire sdrio_clk_77;
1542 wire sdrio_clk_78;
1543 wire sdrio_clk_79;
1544 wire sdrio_clk_80;
1545 wire sdrio_clk_81;
1546 wire sdrio_clk_82;
1547 wire sdrio_clk_83;
1548 wire sdrio_clk_84;
1549 wire sdrio_clk_85;
1550 wire sdrio_clk_86;
1551 wire sdrio_clk_87;
1552 wire sdrio_clk_88;
1553 wire sdrio_clk_89;
1554 wire sdrio_clk_90;
1555 wire sdrio_clk_91;
1556 wire sdrio_clk_92;
1557 wire sdrio_clk_93;
1558 wire sdrio_clk_94;
1559 wire sdrio_clk_95;
1560 wire sdrio_clk_96;
1561 wire sdrio_clk_97;
1562 wire sdrio_clk_98;
1563 wire sdrio_clk_99;
1564 wire sdrio_clk_100;
1565 wire sdrio_clk_101;
1566 wire sdrio_clk_102;
1567 wire sdrio_clk_103;
1568 wire sdrio_clk_104;
1569 wire sdrio_clk_105;
1570 wire sdrio_clk_106;
1571 wire sdrio_clk_107;
1572 wire sdrio_clk_108;
1573 wire sdrio_clk_109;
1574 wire sdrio_clk_110;
1575 wire sdrio_clk_111;
1576 wire sdrio_clk_112;
1577 wire sdrio_clk_113;
1578 wire sdrio_clk_114;
1579 wire sdrio_clk_115;
1580 wire sdrio_clk_116;
1581 wire sdrio_clk_117;
1582 wire sdrio_clk_118;
1583
1584 assign main_libresocsim_libresoc_reset = main_libresocsim_reset;
1585 assign main_libresocsim_libresoc_clk_sel = sys_clksel_i;
1586 assign sys_pll_testout_o = main_libresocsim_libresoc_pll_test_o;
1587 assign sys_pll_vco_o = main_libresocsim_libresoc_pll_vco_o;
1588 assign main_libresocsim_libresoc_pll_24_i = sys_pllclk;
1589 assign pll_clk = pll_clk;
1590 always @(*) begin
1591         main_eint_tmp <= 3'd0;
1592         main_eint_tmp[0] <= main_libresocsim_libresoc_constraintmanager_eint_0;
1593         main_eint_tmp[1] <= main_libresocsim_libresoc_constraintmanager_eint_1;
1594         main_eint_tmp[2] <= main_libresocsim_libresoc_constraintmanager_eint_2;
1595 end
1596 assign main_libresocsim_libresoc_jtag_tck = jtag_tck;
1597 assign main_libresocsim_libresoc_jtag_tms = jtag_tms;
1598 assign main_libresocsim_libresoc_jtag_tdi = jtag_tdi;
1599 assign jtag_tdo = main_libresocsim_libresoc_jtag_tdo;
1600 assign main_nc = nc;
1601 assign main_libresocsim_bus_error = builder_libresocsim_error;
1602 always @(*) begin
1603         main_libresocsim_libresoc_interrupt <= 16'd0;
1604         main_libresocsim_libresoc_interrupt[13] <= main_eint_tmp[0];
1605         main_libresocsim_libresoc_interrupt[14] <= main_eint_tmp[1];
1606         main_libresocsim_libresoc_interrupt[15] <= main_eint_tmp[2];
1607         main_libresocsim_libresoc_interrupt[0] <= main_libresocsim_irq;
1608         main_libresocsim_libresoc_interrupt[1] <= main_irq;
1609 end
1610 assign main_libresocsim_converter0_reset = (~main_libresocsim_libresoc_ibus_cyc);
1611 always @(*) begin
1612         main_libresocsim_interface0_converted_interface_dat_w <= 32'd0;
1613         case (main_libresocsim_converter0_counter)
1614                 1'd0: begin
1615                         main_libresocsim_interface0_converted_interface_dat_w <= main_libresocsim_libresoc_ibus_dat_w[63:0];
1616                 end
1617                 1'd1: begin
1618                         main_libresocsim_interface0_converted_interface_dat_w <= main_libresocsim_libresoc_ibus_dat_w[63:32];
1619                 end
1620         endcase
1621 end
1622 assign main_libresocsim_libresoc_ibus_dat_r = {main_libresocsim_interface0_converted_interface_dat_r, main_libresocsim_converter0_dat_r[63:32]};
1623 always @(*) begin
1624         main_libresocsim_interface0_converted_interface_sel <= 4'd0;
1625         main_libresocsim_interface0_converted_interface_cyc <= 1'd0;
1626         main_libresocsim_libresoc_ibus_ack <= 1'd0;
1627         main_libresocsim_interface0_converted_interface_stb <= 1'd0;
1628         main_libresocsim_interface0_converted_interface_we <= 1'd0;
1629         builder_subfragments_converter0_next_state <= 1'd0;
1630         main_libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1631         main_libresocsim_converter0_skip <= 1'd0;
1632         main_libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0;
1633         main_libresocsim_interface0_converted_interface_adr <= 30'd0;
1634         builder_subfragments_converter0_next_state <= builder_subfragments_converter0_state;
1635         case (builder_subfragments_converter0_state)
1636                 1'd1: begin
1637                         main_libresocsim_interface0_converted_interface_adr <= {main_libresocsim_libresoc_ibus_adr, main_libresocsim_converter0_counter};
1638                         case (main_libresocsim_converter0_counter)
1639                                 1'd0: begin
1640                                         main_libresocsim_interface0_converted_interface_sel <= main_libresocsim_libresoc_ibus_sel[7:0];
1641                                 end
1642                                 1'd1: begin
1643                                         main_libresocsim_interface0_converted_interface_sel <= main_libresocsim_libresoc_ibus_sel[7:4];
1644                                 end
1645                         endcase
1646                         if ((main_libresocsim_libresoc_ibus_stb & main_libresocsim_libresoc_ibus_cyc)) begin
1647                                 main_libresocsim_converter0_skip <= (main_libresocsim_interface0_converted_interface_sel == 1'd0);
1648                                 main_libresocsim_interface0_converted_interface_we <= main_libresocsim_libresoc_ibus_we;
1649                                 main_libresocsim_interface0_converted_interface_cyc <= (~main_libresocsim_converter0_skip);
1650                                 main_libresocsim_interface0_converted_interface_stb <= (~main_libresocsim_converter0_skip);
1651                                 if ((main_libresocsim_interface0_converted_interface_ack | main_libresocsim_converter0_skip)) begin
1652                                         main_libresocsim_converter0_counter_subfragments_converter0_next_value <= (main_libresocsim_converter0_counter + 1'd1);
1653                                         main_libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1654                                         if ((main_libresocsim_converter0_counter == 1'd1)) begin
1655                                                 main_libresocsim_libresoc_ibus_ack <= 1'd1;
1656                                                 builder_subfragments_converter0_next_state <= 1'd0;
1657                                         end
1658                                 end
1659                         end
1660                 end
1661                 default: begin
1662                         main_libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1663                         main_libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1664                         if ((main_libresocsim_libresoc_ibus_stb & main_libresocsim_libresoc_ibus_cyc)) begin
1665                                 builder_subfragments_converter0_next_state <= 1'd1;
1666                         end
1667                 end
1668         endcase
1669 end
1670 assign main_libresocsim_converter1_reset = (~main_libresocsim_libresoc_dbus_cyc);
1671 always @(*) begin
1672         main_libresocsim_interface1_converted_interface_dat_w <= 32'd0;
1673         case (main_libresocsim_converter1_counter)
1674                 1'd0: begin
1675                         main_libresocsim_interface1_converted_interface_dat_w <= main_libresocsim_libresoc_dbus_dat_w[63:0];
1676                 end
1677                 1'd1: begin
1678                         main_libresocsim_interface1_converted_interface_dat_w <= main_libresocsim_libresoc_dbus_dat_w[63:32];
1679                 end
1680         endcase
1681 end
1682 assign main_libresocsim_libresoc_dbus_dat_r = {main_libresocsim_interface1_converted_interface_dat_r, main_libresocsim_converter1_dat_r[63:32]};
1683 always @(*) begin
1684         main_libresocsim_interface1_converted_interface_we <= 1'd0;
1685         main_libresocsim_converter1_skip <= 1'd0;
1686         builder_subfragments_converter1_next_state <= 1'd0;
1687         main_libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1688         main_libresocsim_libresoc_dbus_ack <= 1'd0;
1689         main_libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0;
1690         main_libresocsim_interface1_converted_interface_adr <= 30'd0;
1691         main_libresocsim_interface1_converted_interface_sel <= 4'd0;
1692         main_libresocsim_interface1_converted_interface_cyc <= 1'd0;
1693         main_libresocsim_interface1_converted_interface_stb <= 1'd0;
1694         builder_subfragments_converter1_next_state <= builder_subfragments_converter1_state;
1695         case (builder_subfragments_converter1_state)
1696                 1'd1: begin
1697                         main_libresocsim_interface1_converted_interface_adr <= {main_libresocsim_libresoc_dbus_adr, main_libresocsim_converter1_counter};
1698                         case (main_libresocsim_converter1_counter)
1699                                 1'd0: begin
1700                                         main_libresocsim_interface1_converted_interface_sel <= main_libresocsim_libresoc_dbus_sel[7:0];
1701                                 end
1702                                 1'd1: begin
1703                                         main_libresocsim_interface1_converted_interface_sel <= main_libresocsim_libresoc_dbus_sel[7:4];
1704                                 end
1705                         endcase
1706                         if ((main_libresocsim_libresoc_dbus_stb & main_libresocsim_libresoc_dbus_cyc)) begin
1707                                 main_libresocsim_converter1_skip <= (main_libresocsim_interface1_converted_interface_sel == 1'd0);
1708                                 main_libresocsim_interface1_converted_interface_we <= main_libresocsim_libresoc_dbus_we;
1709                                 main_libresocsim_interface1_converted_interface_cyc <= (~main_libresocsim_converter1_skip);
1710                                 main_libresocsim_interface1_converted_interface_stb <= (~main_libresocsim_converter1_skip);
1711                                 if ((main_libresocsim_interface1_converted_interface_ack | main_libresocsim_converter1_skip)) begin
1712                                         main_libresocsim_converter1_counter_subfragments_converter1_next_value <= (main_libresocsim_converter1_counter + 1'd1);
1713                                         main_libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1714                                         if ((main_libresocsim_converter1_counter == 1'd1)) begin
1715                                                 main_libresocsim_libresoc_dbus_ack <= 1'd1;
1716                                                 builder_subfragments_converter1_next_state <= 1'd0;
1717                                         end
1718                                 end
1719                         end
1720                 end
1721                 default: begin
1722                         main_libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1723                         main_libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1724                         if ((main_libresocsim_libresoc_dbus_stb & main_libresocsim_libresoc_dbus_cyc)) begin
1725                                 builder_subfragments_converter1_next_state <= 1'd1;
1726                         end
1727                 end
1728         endcase
1729 end
1730 assign main_libresocsim_libresoc_interface0_cyc = main_interface0_converted_interface_cyc;
1731 assign main_libresocsim_libresoc_interface0_stb = main_interface0_converted_interface_stb;
1732 assign main_interface0_converted_interface_ack = main_libresocsim_libresoc_interface0_ack;
1733 assign main_libresocsim_libresoc_interface0_we = main_interface0_converted_interface_we;
1734 assign main_libresocsim_libresoc_interface0_cti = main_interface0_converted_interface_cti;
1735 assign main_libresocsim_libresoc_interface0_bte = main_interface0_converted_interface_bte;
1736 assign main_interface0_converted_interface_err = main_libresocsim_libresoc_interface0_err;
1737 always @(*) begin
1738         main_libresocsim_libresoc_interface0_adr <= 29'd0;
1739         main_libresocsim_libresoc_interface0_dat_w <= 64'd0;
1740         main_interface0_converted_interface_dat_r <= 32'd0;
1741         main_libresocsim_libresoc_interface0_sel <= 8'd0;
1742         case (main_interface0_converted_interface_adr[0])
1743                 1'd0: begin
1744                         main_libresocsim_libresoc_interface0_adr <= main_interface0_converted_interface_adr[29:1];
1745                         main_libresocsim_libresoc_interface0_sel[3:0] <= 4'd15;
1746                         main_libresocsim_libresoc_interface0_dat_w[31:0] <= main_interface0_converted_interface_dat_w;
1747                         main_interface0_converted_interface_dat_r <= main_libresocsim_libresoc_interface0_dat_r[31:0];
1748                 end
1749                 1'd1: begin
1750                         main_libresocsim_libresoc_interface0_adr <= main_interface0_converted_interface_adr[29:1];
1751                         main_libresocsim_libresoc_interface0_sel[7:4] <= 4'd15;
1752                         main_libresocsim_libresoc_interface0_dat_w[63:32] <= main_interface0_converted_interface_dat_w;
1753                         main_interface0_converted_interface_dat_r <= main_libresocsim_libresoc_interface0_dat_r[63:32];
1754                 end
1755         endcase
1756 end
1757 assign main_libresocsim_libresoc_interface1_cyc = main_interface1_converted_interface_cyc;
1758 assign main_libresocsim_libresoc_interface1_stb = main_interface1_converted_interface_stb;
1759 assign main_interface1_converted_interface_ack = main_libresocsim_libresoc_interface1_ack;
1760 assign main_libresocsim_libresoc_interface1_we = main_interface1_converted_interface_we;
1761 assign main_libresocsim_libresoc_interface1_cti = main_interface1_converted_interface_cti;
1762 assign main_libresocsim_libresoc_interface1_bte = main_interface1_converted_interface_bte;
1763 assign main_interface1_converted_interface_err = main_libresocsim_libresoc_interface1_err;
1764 always @(*) begin
1765         main_interface1_converted_interface_dat_r <= 32'd0;
1766         main_libresocsim_libresoc_interface1_dat_w <= 64'd0;
1767         main_libresocsim_libresoc_interface1_sel <= 8'd0;
1768         main_libresocsim_libresoc_interface1_adr <= 29'd0;
1769         case (main_interface1_converted_interface_adr[0])
1770                 1'd0: begin
1771                         main_libresocsim_libresoc_interface1_adr <= main_interface1_converted_interface_adr[29:1];
1772                         main_libresocsim_libresoc_interface1_sel[3:0] <= 4'd15;
1773                         main_libresocsim_libresoc_interface1_dat_w[31:0] <= main_interface1_converted_interface_dat_w;
1774                         main_interface1_converted_interface_dat_r <= main_libresocsim_libresoc_interface1_dat_r[31:0];
1775                 end
1776                 1'd1: begin
1777                         main_libresocsim_libresoc_interface1_adr <= main_interface1_converted_interface_adr[29:1];
1778                         main_libresocsim_libresoc_interface1_sel[7:4] <= 4'd15;
1779                         main_libresocsim_libresoc_interface1_dat_w[63:32] <= main_interface1_converted_interface_dat_w;
1780                         main_interface1_converted_interface_dat_r <= main_libresocsim_libresoc_interface1_dat_r[63:32];
1781                 end
1782         endcase
1783 end
1784 assign main_libresocsim_libresoc_interface2_cyc = main_interface2_converted_interface_cyc;
1785 assign main_libresocsim_libresoc_interface2_stb = main_interface2_converted_interface_stb;
1786 assign main_interface2_converted_interface_ack = main_libresocsim_libresoc_interface2_ack;
1787 assign main_libresocsim_libresoc_interface2_we = main_interface2_converted_interface_we;
1788 assign main_libresocsim_libresoc_interface2_cti = main_interface2_converted_interface_cti;
1789 assign main_libresocsim_libresoc_interface2_bte = main_interface2_converted_interface_bte;
1790 assign main_interface2_converted_interface_err = main_libresocsim_libresoc_interface2_err;
1791 always @(*) begin
1792         main_libresocsim_libresoc_interface2_sel <= 8'd0;
1793         main_libresocsim_libresoc_interface2_adr <= 29'd0;
1794         main_interface2_converted_interface_dat_r <= 32'd0;
1795         main_libresocsim_libresoc_interface2_dat_w <= 64'd0;
1796         case (main_interface2_converted_interface_adr[0])
1797                 1'd0: begin
1798                         main_libresocsim_libresoc_interface2_adr <= main_interface2_converted_interface_adr[29:1];
1799                         main_libresocsim_libresoc_interface2_sel[3:0] <= 4'd15;
1800                         main_libresocsim_libresoc_interface2_dat_w[31:0] <= main_interface2_converted_interface_dat_w;
1801                         main_interface2_converted_interface_dat_r <= main_libresocsim_libresoc_interface2_dat_r[31:0];
1802                 end
1803                 1'd1: begin
1804                         main_libresocsim_libresoc_interface2_adr <= main_interface2_converted_interface_adr[29:1];
1805                         main_libresocsim_libresoc_interface2_sel[7:4] <= 4'd15;
1806                         main_libresocsim_libresoc_interface2_dat_w[63:32] <= main_interface2_converted_interface_dat_w;
1807                         main_interface2_converted_interface_dat_r <= main_libresocsim_libresoc_interface2_dat_r[63:32];
1808                 end
1809         endcase
1810 end
1811 assign main_libresocsim_libresoc_interface3_cyc = main_interface3_converted_interface_cyc;
1812 assign main_libresocsim_libresoc_interface3_stb = main_interface3_converted_interface_stb;
1813 assign main_interface3_converted_interface_ack = main_libresocsim_libresoc_interface3_ack;
1814 assign main_libresocsim_libresoc_interface3_we = main_interface3_converted_interface_we;
1815 assign main_libresocsim_libresoc_interface3_cti = main_interface3_converted_interface_cti;
1816 assign main_libresocsim_libresoc_interface3_bte = main_interface3_converted_interface_bte;
1817 assign main_interface3_converted_interface_err = main_libresocsim_libresoc_interface3_err;
1818 always @(*) begin
1819         main_libresocsim_libresoc_interface3_sel <= 8'd0;
1820         main_libresocsim_libresoc_interface3_adr <= 29'd0;
1821         main_libresocsim_libresoc_interface3_dat_w <= 64'd0;
1822         main_interface3_converted_interface_dat_r <= 32'd0;
1823         case (main_interface3_converted_interface_adr[0])
1824                 1'd0: begin
1825                         main_libresocsim_libresoc_interface3_adr <= main_interface3_converted_interface_adr[29:1];
1826                         main_libresocsim_libresoc_interface3_sel[3:0] <= 4'd15;
1827                         main_libresocsim_libresoc_interface3_dat_w[31:0] <= main_interface3_converted_interface_dat_w;
1828                         main_interface3_converted_interface_dat_r <= main_libresocsim_libresoc_interface3_dat_r[31:0];
1829                 end
1830                 1'd1: begin
1831                         main_libresocsim_libresoc_interface3_adr <= main_interface3_converted_interface_adr[29:1];
1832                         main_libresocsim_libresoc_interface3_sel[7:4] <= 4'd15;
1833                         main_libresocsim_libresoc_interface3_dat_w[63:32] <= main_interface3_converted_interface_dat_w;
1834                         main_interface3_converted_interface_dat_r <= main_libresocsim_libresoc_interface3_dat_r[63:32];
1835                 end
1836         endcase
1837 end
1838 assign main_libresocsim_reset = main_libresocsim_reset_re;
1839 assign main_libresocsim_bus_errors_status = main_libresocsim_bus_errors;
1840 always @(*) begin
1841         main_libresocsim_we <= 4'd0;
1842         main_libresocsim_we[0] <= (((main_libresocsim_ram_bus_cyc & main_libresocsim_ram_bus_stb) & main_libresocsim_ram_bus_we) & main_libresocsim_ram_bus_sel[0]);
1843         main_libresocsim_we[1] <= (((main_libresocsim_ram_bus_cyc & main_libresocsim_ram_bus_stb) & main_libresocsim_ram_bus_we) & main_libresocsim_ram_bus_sel[1]);
1844         main_libresocsim_we[2] <= (((main_libresocsim_ram_bus_cyc & main_libresocsim_ram_bus_stb) & main_libresocsim_ram_bus_we) & main_libresocsim_ram_bus_sel[2]);
1845         main_libresocsim_we[3] <= (((main_libresocsim_ram_bus_cyc & main_libresocsim_ram_bus_stb) & main_libresocsim_ram_bus_we) & main_libresocsim_ram_bus_sel[3]);
1846 end
1847 assign main_libresocsim_adr = main_libresocsim_ram_bus_adr[4:0];
1848 assign main_libresocsim_ram_bus_dat_r = main_libresocsim_dat_r;
1849 assign main_libresocsim_dat_w = main_libresocsim_ram_bus_dat_w;
1850 assign main_libresocsim_zero_trigger = (main_libresocsim_value != 1'd0);
1851 assign main_libresocsim_eventmanager_status_w = main_libresocsim_zero_status;
1852 always @(*) begin
1853         main_libresocsim_zero_clear <= 1'd0;
1854         if ((main_libresocsim_eventmanager_pending_re & main_libresocsim_eventmanager_pending_r)) begin
1855                 main_libresocsim_zero_clear <= 1'd1;
1856         end
1857 end
1858 assign main_libresocsim_eventmanager_pending_w = main_libresocsim_zero_pending;
1859 assign main_libresocsim_irq = (main_libresocsim_eventmanager_pending_w & main_libresocsim_eventmanager_storage);
1860 assign main_libresocsim_zero_status = main_libresocsim_zero_trigger;
1861 always @(*) begin
1862         main_ram_we <= 4'd0;
1863         main_ram_we[0] <= (((main_ram_bus_ram_bus_cyc & main_ram_bus_ram_bus_stb) & main_ram_bus_ram_bus_we) & main_ram_bus_ram_bus_sel[0]);
1864         main_ram_we[1] <= (((main_ram_bus_ram_bus_cyc & main_ram_bus_ram_bus_stb) & main_ram_bus_ram_bus_we) & main_ram_bus_ram_bus_sel[1]);
1865         main_ram_we[2] <= (((main_ram_bus_ram_bus_cyc & main_ram_bus_ram_bus_stb) & main_ram_bus_ram_bus_we) & main_ram_bus_ram_bus_sel[2]);
1866         main_ram_we[3] <= (((main_ram_bus_ram_bus_cyc & main_ram_bus_ram_bus_stb) & main_ram_bus_ram_bus_we) & main_ram_bus_ram_bus_sel[3]);
1867 end
1868 assign main_ram_adr = main_ram_bus_ram_bus_adr[4:0];
1869 assign main_ram_bus_ram_bus_dat_r = main_ram_dat_r;
1870 assign main_ram_dat_w = main_ram_bus_ram_bus_dat_w;
1871 assign sys_clk = pll_clk;
1872 assign por_clk = pll_clk;
1873 assign sys_rst_1 = main_int_rst;
1874 assign main_dfi_p0_address = main_sdram_master_p0_address;
1875 assign main_dfi_p0_bank = main_sdram_master_p0_bank;
1876 assign main_dfi_p0_cas_n = main_sdram_master_p0_cas_n;
1877 assign main_dfi_p0_cs_n = main_sdram_master_p0_cs_n;
1878 assign main_dfi_p0_ras_n = main_sdram_master_p0_ras_n;
1879 assign main_dfi_p0_we_n = main_sdram_master_p0_we_n;
1880 assign main_dfi_p0_cke = main_sdram_master_p0_cke;
1881 assign main_dfi_p0_odt = main_sdram_master_p0_odt;
1882 assign main_dfi_p0_reset_n = main_sdram_master_p0_reset_n;
1883 assign main_dfi_p0_act_n = main_sdram_master_p0_act_n;
1884 assign main_dfi_p0_wrdata = main_sdram_master_p0_wrdata;
1885 assign main_dfi_p0_wrdata_en = main_sdram_master_p0_wrdata_en;
1886 assign main_dfi_p0_wrdata_mask = main_sdram_master_p0_wrdata_mask;
1887 assign main_dfi_p0_rddata_en = main_sdram_master_p0_rddata_en;
1888 assign main_sdram_master_p0_rddata = main_dfi_p0_rddata;
1889 assign main_sdram_master_p0_rddata_valid = main_dfi_p0_rddata_valid;
1890 assign main_sdram_slave_p0_address = main_sdram_dfi_p0_address;
1891 assign main_sdram_slave_p0_bank = main_sdram_dfi_p0_bank;
1892 assign main_sdram_slave_p0_cas_n = main_sdram_dfi_p0_cas_n;
1893 assign main_sdram_slave_p0_cs_n = main_sdram_dfi_p0_cs_n;
1894 assign main_sdram_slave_p0_ras_n = main_sdram_dfi_p0_ras_n;
1895 assign main_sdram_slave_p0_we_n = main_sdram_dfi_p0_we_n;
1896 assign main_sdram_slave_p0_cke = main_sdram_dfi_p0_cke;
1897 assign main_sdram_slave_p0_odt = main_sdram_dfi_p0_odt;
1898 assign main_sdram_slave_p0_reset_n = main_sdram_dfi_p0_reset_n;
1899 assign main_sdram_slave_p0_act_n = main_sdram_dfi_p0_act_n;
1900 assign main_sdram_slave_p0_wrdata = main_sdram_dfi_p0_wrdata;
1901 assign main_sdram_slave_p0_wrdata_en = main_sdram_dfi_p0_wrdata_en;
1902 assign main_sdram_slave_p0_wrdata_mask = main_sdram_dfi_p0_wrdata_mask;
1903 assign main_sdram_slave_p0_rddata_en = main_sdram_dfi_p0_rddata_en;
1904 assign main_sdram_dfi_p0_rddata = main_sdram_slave_p0_rddata;
1905 assign main_sdram_dfi_p0_rddata_valid = main_sdram_slave_p0_rddata_valid;
1906 always @(*) begin
1907         main_sdram_master_p0_reset_n <= 1'd0;
1908         main_sdram_master_p0_act_n <= 1'd1;
1909         main_sdram_inti_p0_rddata <= 16'd0;
1910         main_sdram_master_p0_wrdata <= 16'd0;
1911         main_sdram_inti_p0_rddata_valid <= 1'd0;
1912         main_sdram_master_p0_wrdata_en <= 1'd0;
1913         main_sdram_master_p0_wrdata_mask <= 2'd0;
1914         main_sdram_master_p0_rddata_en <= 1'd0;
1915         main_sdram_slave_p0_rddata <= 16'd0;
1916         main_sdram_slave_p0_rddata_valid <= 1'd0;
1917         main_sdram_master_p0_address <= 13'd0;
1918         main_sdram_master_p0_bank <= 2'd0;
1919         main_sdram_master_p0_cas_n <= 1'd1;
1920         main_sdram_master_p0_cs_n <= 1'd1;
1921         main_sdram_master_p0_ras_n <= 1'd1;
1922         main_sdram_master_p0_we_n <= 1'd1;
1923         main_sdram_master_p0_cke <= 1'd0;
1924         main_sdram_master_p0_odt <= 1'd0;
1925         if (main_sdram_sel) begin
1926                 main_sdram_master_p0_address <= main_sdram_slave_p0_address;
1927                 main_sdram_master_p0_bank <= main_sdram_slave_p0_bank;
1928                 main_sdram_master_p0_cas_n <= main_sdram_slave_p0_cas_n;
1929                 main_sdram_master_p0_cs_n <= main_sdram_slave_p0_cs_n;
1930                 main_sdram_master_p0_ras_n <= main_sdram_slave_p0_ras_n;
1931                 main_sdram_master_p0_we_n <= main_sdram_slave_p0_we_n;
1932                 main_sdram_master_p0_cke <= main_sdram_slave_p0_cke;
1933                 main_sdram_master_p0_odt <= main_sdram_slave_p0_odt;
1934                 main_sdram_master_p0_reset_n <= main_sdram_slave_p0_reset_n;
1935                 main_sdram_master_p0_act_n <= main_sdram_slave_p0_act_n;
1936                 main_sdram_master_p0_wrdata <= main_sdram_slave_p0_wrdata;
1937                 main_sdram_master_p0_wrdata_en <= main_sdram_slave_p0_wrdata_en;
1938                 main_sdram_master_p0_wrdata_mask <= main_sdram_slave_p0_wrdata_mask;
1939                 main_sdram_master_p0_rddata_en <= main_sdram_slave_p0_rddata_en;
1940                 main_sdram_slave_p0_rddata <= main_sdram_master_p0_rddata;
1941                 main_sdram_slave_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;
1942         end else begin
1943                 main_sdram_master_p0_address <= main_sdram_inti_p0_address;
1944                 main_sdram_master_p0_bank <= main_sdram_inti_p0_bank;
1945                 main_sdram_master_p0_cas_n <= main_sdram_inti_p0_cas_n;
1946                 main_sdram_master_p0_cs_n <= main_sdram_inti_p0_cs_n;
1947                 main_sdram_master_p0_ras_n <= main_sdram_inti_p0_ras_n;
1948                 main_sdram_master_p0_we_n <= main_sdram_inti_p0_we_n;
1949                 main_sdram_master_p0_cke <= main_sdram_inti_p0_cke;
1950                 main_sdram_master_p0_odt <= main_sdram_inti_p0_odt;
1951                 main_sdram_master_p0_reset_n <= main_sdram_inti_p0_reset_n;
1952                 main_sdram_master_p0_act_n <= main_sdram_inti_p0_act_n;
1953                 main_sdram_master_p0_wrdata <= main_sdram_inti_p0_wrdata;
1954                 main_sdram_master_p0_wrdata_en <= main_sdram_inti_p0_wrdata_en;
1955                 main_sdram_master_p0_wrdata_mask <= main_sdram_inti_p0_wrdata_mask;
1956                 main_sdram_master_p0_rddata_en <= main_sdram_inti_p0_rddata_en;
1957                 main_sdram_inti_p0_rddata <= main_sdram_master_p0_rddata;
1958                 main_sdram_inti_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;
1959         end
1960 end
1961 assign main_sdram_inti_p0_cke = main_sdram_cke;
1962 assign main_sdram_inti_p0_odt = main_sdram_odt;
1963 assign main_sdram_inti_p0_reset_n = main_sdram_reset_n;
1964 always @(*) begin
1965         main_sdram_inti_p0_we_n <= 1'd1;
1966         main_sdram_inti_p0_cas_n <= 1'd1;
1967         main_sdram_inti_p0_cs_n <= 1'd1;
1968         main_sdram_inti_p0_ras_n <= 1'd1;
1969         if (main_sdram_command_issue_re) begin
1970                 main_sdram_inti_p0_cs_n <= {1{(~main_sdram_command_storage[0])}};
1971                 main_sdram_inti_p0_we_n <= (~main_sdram_command_storage[1]);
1972                 main_sdram_inti_p0_cas_n <= (~main_sdram_command_storage[2]);
1973                 main_sdram_inti_p0_ras_n <= (~main_sdram_command_storage[3]);
1974         end else begin
1975                 main_sdram_inti_p0_cs_n <= {1{1'd1}};
1976                 main_sdram_inti_p0_we_n <= 1'd1;
1977                 main_sdram_inti_p0_cas_n <= 1'd1;
1978                 main_sdram_inti_p0_ras_n <= 1'd1;
1979         end
1980 end
1981 assign main_sdram_inti_p0_address = main_sdram_address_storage;
1982 assign main_sdram_inti_p0_bank = main_sdram_baddress_storage;
1983 assign main_sdram_inti_p0_wrdata_en = (main_sdram_command_issue_re & main_sdram_command_storage[4]);
1984 assign main_sdram_inti_p0_rddata_en = (main_sdram_command_issue_re & main_sdram_command_storage[5]);
1985 assign main_sdram_inti_p0_wrdata = main_sdram_wrdata_storage;
1986 assign main_sdram_inti_p0_wrdata_mask = 1'd0;
1987 assign main_sdram_bankmachine0_req_valid = main_sdram_interface_bank0_valid;
1988 assign main_sdram_interface_bank0_ready = main_sdram_bankmachine0_req_ready;
1989 assign main_sdram_bankmachine0_req_we = main_sdram_interface_bank0_we;
1990 assign main_sdram_bankmachine0_req_addr = main_sdram_interface_bank0_addr;
1991 assign main_sdram_interface_bank0_lock = main_sdram_bankmachine0_req_lock;
1992 assign main_sdram_interface_bank0_wdata_ready = main_sdram_bankmachine0_req_wdata_ready;
1993 assign main_sdram_interface_bank0_rdata_valid = main_sdram_bankmachine0_req_rdata_valid;
1994 assign main_sdram_bankmachine1_req_valid = main_sdram_interface_bank1_valid;
1995 assign main_sdram_interface_bank1_ready = main_sdram_bankmachine1_req_ready;
1996 assign main_sdram_bankmachine1_req_we = main_sdram_interface_bank1_we;
1997 assign main_sdram_bankmachine1_req_addr = main_sdram_interface_bank1_addr;
1998 assign main_sdram_interface_bank1_lock = main_sdram_bankmachine1_req_lock;
1999 assign main_sdram_interface_bank1_wdata_ready = main_sdram_bankmachine1_req_wdata_ready;
2000 assign main_sdram_interface_bank1_rdata_valid = main_sdram_bankmachine1_req_rdata_valid;
2001 assign main_sdram_bankmachine2_req_valid = main_sdram_interface_bank2_valid;
2002 assign main_sdram_interface_bank2_ready = main_sdram_bankmachine2_req_ready;
2003 assign main_sdram_bankmachine2_req_we = main_sdram_interface_bank2_we;
2004 assign main_sdram_bankmachine2_req_addr = main_sdram_interface_bank2_addr;
2005 assign main_sdram_interface_bank2_lock = main_sdram_bankmachine2_req_lock;
2006 assign main_sdram_interface_bank2_wdata_ready = main_sdram_bankmachine2_req_wdata_ready;
2007 assign main_sdram_interface_bank2_rdata_valid = main_sdram_bankmachine2_req_rdata_valid;
2008 assign main_sdram_bankmachine3_req_valid = main_sdram_interface_bank3_valid;
2009 assign main_sdram_interface_bank3_ready = main_sdram_bankmachine3_req_ready;
2010 assign main_sdram_bankmachine3_req_we = main_sdram_interface_bank3_we;
2011 assign main_sdram_bankmachine3_req_addr = main_sdram_interface_bank3_addr;
2012 assign main_sdram_interface_bank3_lock = main_sdram_bankmachine3_req_lock;
2013 assign main_sdram_interface_bank3_wdata_ready = main_sdram_bankmachine3_req_wdata_ready;
2014 assign main_sdram_interface_bank3_rdata_valid = main_sdram_bankmachine3_req_rdata_valid;
2015 assign main_sdram_timer_wait = (~main_sdram_timer_done0);
2016 assign main_sdram_postponer_req_i = main_sdram_timer_done0;
2017 assign main_sdram_wants_refresh = main_sdram_postponer_req_o;
2018 assign main_sdram_timer_done1 = (main_sdram_timer_count1 == 1'd0);
2019 assign main_sdram_timer_done0 = main_sdram_timer_done1;
2020 assign main_sdram_timer_count0 = main_sdram_timer_count1;
2021 assign main_sdram_sequencer_start1 = (main_sdram_sequencer_start0 | (main_sdram_sequencer_count != 1'd0));
2022 assign main_sdram_sequencer_done0 = (main_sdram_sequencer_done1 & (main_sdram_sequencer_count == 1'd0));
2023 always @(*) begin
2024         main_sdram_cmd_valid <= 1'd0;
2025         main_sdram_cmd_last <= 1'd0;
2026         main_sdram_sequencer_start0 <= 1'd0;
2027         builder_subfragments_refresher_next_state <= 2'd0;
2028         builder_subfragments_refresher_next_state <= builder_subfragments_refresher_state;
2029         case (builder_subfragments_refresher_state)
2030                 1'd1: begin
2031                         main_sdram_cmd_valid <= 1'd1;
2032                         if (main_sdram_cmd_ready) begin
2033                                 main_sdram_sequencer_start0 <= 1'd1;
2034                                 builder_subfragments_refresher_next_state <= 2'd2;
2035                         end
2036                 end
2037                 2'd2: begin
2038                         main_sdram_cmd_valid <= 1'd1;
2039                         if (main_sdram_sequencer_done0) begin
2040                                 main_sdram_cmd_valid <= 1'd0;
2041                                 main_sdram_cmd_last <= 1'd1;
2042                                 builder_subfragments_refresher_next_state <= 1'd0;
2043                         end
2044                 end
2045                 default: begin
2046                         if (1'd1) begin
2047                                 if (main_sdram_wants_refresh) begin
2048                                         builder_subfragments_refresher_next_state <= 1'd1;
2049                                 end
2050                         end
2051                 end
2052         endcase
2053 end
2054 assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine0_req_valid;
2055 assign main_sdram_bankmachine0_req_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
2056 assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine0_req_we;
2057 assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine0_req_addr;
2058 assign main_sdram_bankmachine0_cmd_buffer_sink_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
2059 assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine0_cmd_buffer_sink_ready;
2060 assign main_sdram_bankmachine0_cmd_buffer_sink_first = main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
2061 assign main_sdram_bankmachine0_cmd_buffer_sink_last = main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
2062 assign main_sdram_bankmachine0_cmd_buffer_sink_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
2063 assign main_sdram_bankmachine0_cmd_buffer_sink_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
2064 assign main_sdram_bankmachine0_cmd_buffer_source_ready = (main_sdram_bankmachine0_req_wdata_ready | main_sdram_bankmachine0_req_rdata_valid);
2065 assign main_sdram_bankmachine0_req_lock = (main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine0_cmd_buffer_source_valid);
2066 assign main_sdram_bankmachine0_row_hit = (main_sdram_bankmachine0_row == main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]);
2067 assign main_sdram_bankmachine0_cmd_payload_ba = 1'd0;
2068 always @(*) begin
2069         main_sdram_bankmachine0_cmd_payload_a <= 13'd0;
2070         if (main_sdram_bankmachine0_row_col_n_addr_sel) begin
2071                 main_sdram_bankmachine0_cmd_payload_a <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
2072         end else begin
2073                 main_sdram_bankmachine0_cmd_payload_a <= ((main_sdram_bankmachine0_auto_precharge <<< 4'd10) | {main_sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2074         end
2075 end
2076 assign main_sdram_bankmachine0_twtpcon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_cmd_payload_is_write);
2077 assign main_sdram_bankmachine0_trccon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);
2078 assign main_sdram_bankmachine0_trascon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);
2079 always @(*) begin
2080         main_sdram_bankmachine0_auto_precharge <= 1'd0;
2081         if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine0_cmd_buffer_source_valid)) begin
2082                 if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9])) begin
2083                         main_sdram_bankmachine0_auto_precharge <= (main_sdram_bankmachine0_row_close == 1'd0);
2084                 end
2085         end
2086 end
2087 assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
2088 assign {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
2089 assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
2090 assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
2091 assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
2092 assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
2093 assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
2094 assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
2095 assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
2096 assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_first = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
2097 assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_last = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
2098 assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
2099 assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
2100 assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
2101 always @(*) begin
2102         main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2103         if (main_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
2104                 main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
2105         end else begin
2106                 main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine0_cmd_buffer_lookahead_produce;
2107         end
2108 end
2109 assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
2110 assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_sdram_bankmachine0_cmd_buffer_lookahead_replace));
2111 assign main_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
2112 assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine0_cmd_buffer_lookahead_consume;
2113 assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
2114 assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
2115 assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
2116 assign main_sdram_bankmachine0_cmd_buffer_sink_ready = ((~main_sdram_bankmachine0_cmd_buffer_source_valid) | main_sdram_bankmachine0_cmd_buffer_source_ready);
2117 always @(*) begin
2118         main_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
2119         main_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
2120         main_sdram_bankmachine0_req_wdata_ready <= 1'd0;
2121         main_sdram_bankmachine0_req_rdata_valid <= 1'd0;
2122         main_sdram_bankmachine0_refresh_gnt <= 1'd0;
2123         main_sdram_bankmachine0_cmd_valid <= 1'd0;
2124         main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
2125         main_sdram_bankmachine0_row_open <= 1'd0;
2126         main_sdram_bankmachine0_row_close <= 1'd0;
2127         main_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
2128         main_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
2129         builder_subfragments_bankmachine0_next_state <= 3'd0;
2130         main_sdram_bankmachine0_cmd_payload_we <= 1'd0;
2131         main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
2132         builder_subfragments_bankmachine0_next_state <= builder_subfragments_bankmachine0_state;
2133         case (builder_subfragments_bankmachine0_state)
2134                 1'd1: begin
2135                         if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin
2136                                 main_sdram_bankmachine0_cmd_valid <= 1'd1;
2137                                 if (main_sdram_bankmachine0_cmd_ready) begin
2138                                         builder_subfragments_bankmachine0_next_state <= 3'd5;
2139                                 end
2140                                 main_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
2141                                 main_sdram_bankmachine0_cmd_payload_we <= 1'd1;
2142                                 main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2143                         end
2144                         main_sdram_bankmachine0_row_close <= 1'd1;
2145                 end
2146                 2'd2: begin
2147                         if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin
2148                                 builder_subfragments_bankmachine0_next_state <= 3'd5;
2149                         end
2150                         main_sdram_bankmachine0_row_close <= 1'd1;
2151                 end
2152                 2'd3: begin
2153                         if (main_sdram_bankmachine0_trccon_ready) begin
2154                                 main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
2155                                 main_sdram_bankmachine0_row_open <= 1'd1;
2156                                 main_sdram_bankmachine0_cmd_valid <= 1'd1;
2157                                 main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2158                                 if (main_sdram_bankmachine0_cmd_ready) begin
2159                                         builder_subfragments_bankmachine0_next_state <= 3'd6;
2160                                 end
2161                                 main_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
2162                         end
2163                 end
2164                 3'd4: begin
2165                         if (main_sdram_bankmachine0_twtpcon_ready) begin
2166                                 main_sdram_bankmachine0_refresh_gnt <= 1'd1;
2167                         end
2168                         main_sdram_bankmachine0_row_close <= 1'd1;
2169                         main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2170                         if ((~main_sdram_bankmachine0_refresh_req)) begin
2171                                 builder_subfragments_bankmachine0_next_state <= 1'd0;
2172                         end
2173                 end
2174                 3'd5: begin
2175                         builder_subfragments_bankmachine0_next_state <= 2'd3;
2176                 end
2177                 3'd6: begin
2178                         builder_subfragments_bankmachine0_next_state <= 1'd0;
2179                 end
2180                 default: begin
2181                         if (main_sdram_bankmachine0_refresh_req) begin
2182                                 builder_subfragments_bankmachine0_next_state <= 3'd4;
2183                         end else begin
2184                                 if (main_sdram_bankmachine0_cmd_buffer_source_valid) begin
2185                                         if (main_sdram_bankmachine0_row_opened) begin
2186                                                 if (main_sdram_bankmachine0_row_hit) begin
2187                                                         main_sdram_bankmachine0_cmd_valid <= 1'd1;
2188                                                         if (main_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
2189                                                                 main_sdram_bankmachine0_req_wdata_ready <= main_sdram_bankmachine0_cmd_ready;
2190                                                                 main_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
2191                                                                 main_sdram_bankmachine0_cmd_payload_we <= 1'd1;
2192                                                         end else begin
2193                                                                 main_sdram_bankmachine0_req_rdata_valid <= main_sdram_bankmachine0_cmd_ready;
2194                                                                 main_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
2195                                                         end
2196                                                         main_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
2197                                                         if ((main_sdram_bankmachine0_cmd_ready & main_sdram_bankmachine0_auto_precharge)) begin
2198                                                                 builder_subfragments_bankmachine0_next_state <= 2'd2;
2199                                                         end
2200                                                 end else begin
2201                                                         builder_subfragments_bankmachine0_next_state <= 1'd1;
2202                                                 end
2203                                         end else begin
2204                                                 builder_subfragments_bankmachine0_next_state <= 2'd3;
2205                                         end
2206                                 end
2207                         end
2208                 end
2209         endcase
2210 end
2211 assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine1_req_valid;
2212 assign main_sdram_bankmachine1_req_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
2213 assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine1_req_we;
2214 assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine1_req_addr;
2215 assign main_sdram_bankmachine1_cmd_buffer_sink_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
2216 assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine1_cmd_buffer_sink_ready;
2217 assign main_sdram_bankmachine1_cmd_buffer_sink_first = main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
2218 assign main_sdram_bankmachine1_cmd_buffer_sink_last = main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
2219 assign main_sdram_bankmachine1_cmd_buffer_sink_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
2220 assign main_sdram_bankmachine1_cmd_buffer_sink_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
2221 assign main_sdram_bankmachine1_cmd_buffer_source_ready = (main_sdram_bankmachine1_req_wdata_ready | main_sdram_bankmachine1_req_rdata_valid);
2222 assign main_sdram_bankmachine1_req_lock = (main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine1_cmd_buffer_source_valid);
2223 assign main_sdram_bankmachine1_row_hit = (main_sdram_bankmachine1_row == main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]);
2224 assign main_sdram_bankmachine1_cmd_payload_ba = 1'd1;
2225 always @(*) begin
2226         main_sdram_bankmachine1_cmd_payload_a <= 13'd0;
2227         if (main_sdram_bankmachine1_row_col_n_addr_sel) begin
2228                 main_sdram_bankmachine1_cmd_payload_a <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
2229         end else begin
2230                 main_sdram_bankmachine1_cmd_payload_a <= ((main_sdram_bankmachine1_auto_precharge <<< 4'd10) | {main_sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2231         end
2232 end
2233 assign main_sdram_bankmachine1_twtpcon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_cmd_payload_is_write);
2234 assign main_sdram_bankmachine1_trccon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);
2235 assign main_sdram_bankmachine1_trascon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);
2236 always @(*) begin
2237         main_sdram_bankmachine1_auto_precharge <= 1'd0;
2238         if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine1_cmd_buffer_source_valid)) begin
2239                 if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9])) begin
2240                         main_sdram_bankmachine1_auto_precharge <= (main_sdram_bankmachine1_row_close == 1'd0);
2241                 end
2242         end
2243 end
2244 assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
2245 assign {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
2246 assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
2247 assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
2248 assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
2249 assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
2250 assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
2251 assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
2252 assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
2253 assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_first = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
2254 assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_last = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
2255 assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
2256 assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
2257 assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
2258 always @(*) begin
2259         main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2260         if (main_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
2261                 main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
2262         end else begin
2263                 main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine1_cmd_buffer_lookahead_produce;
2264         end
2265 end
2266 assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
2267 assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_sdram_bankmachine1_cmd_buffer_lookahead_replace));
2268 assign main_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
2269 assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine1_cmd_buffer_lookahead_consume;
2270 assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
2271 assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
2272 assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
2273 assign main_sdram_bankmachine1_cmd_buffer_sink_ready = ((~main_sdram_bankmachine1_cmd_buffer_source_valid) | main_sdram_bankmachine1_cmd_buffer_source_ready);
2274 always @(*) begin
2275         main_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
2276         main_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
2277         main_sdram_bankmachine1_cmd_payload_we <= 1'd0;
2278         main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
2279         main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
2280         main_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
2281         main_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
2282         main_sdram_bankmachine1_req_wdata_ready <= 1'd0;
2283         main_sdram_bankmachine1_req_rdata_valid <= 1'd0;
2284         main_sdram_bankmachine1_refresh_gnt <= 1'd0;
2285         main_sdram_bankmachine1_cmd_valid <= 1'd0;
2286         builder_subfragments_bankmachine1_next_state <= 3'd0;
2287         main_sdram_bankmachine1_row_open <= 1'd0;
2288         main_sdram_bankmachine1_row_close <= 1'd0;
2289         builder_subfragments_bankmachine1_next_state <= builder_subfragments_bankmachine1_state;
2290         case (builder_subfragments_bankmachine1_state)
2291                 1'd1: begin
2292                         if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin
2293                                 main_sdram_bankmachine1_cmd_valid <= 1'd1;
2294                                 if (main_sdram_bankmachine1_cmd_ready) begin
2295                                         builder_subfragments_bankmachine1_next_state <= 3'd5;
2296                                 end
2297                                 main_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2298                                 main_sdram_bankmachine1_cmd_payload_we <= 1'd1;
2299                                 main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2300                         end
2301                         main_sdram_bankmachine1_row_close <= 1'd1;
2302                 end
2303                 2'd2: begin
2304                         if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin
2305                                 builder_subfragments_bankmachine1_next_state <= 3'd5;
2306                         end
2307                         main_sdram_bankmachine1_row_close <= 1'd1;
2308                 end
2309                 2'd3: begin
2310                         if (main_sdram_bankmachine1_trccon_ready) begin
2311                                 main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
2312                                 main_sdram_bankmachine1_row_open <= 1'd1;
2313                                 main_sdram_bankmachine1_cmd_valid <= 1'd1;
2314                                 main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2315                                 if (main_sdram_bankmachine1_cmd_ready) begin
2316                                         builder_subfragments_bankmachine1_next_state <= 3'd6;
2317                                 end
2318                                 main_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2319                         end
2320                 end
2321                 3'd4: begin
2322                         if (main_sdram_bankmachine1_twtpcon_ready) begin
2323                                 main_sdram_bankmachine1_refresh_gnt <= 1'd1;
2324                         end
2325                         main_sdram_bankmachine1_row_close <= 1'd1;
2326                         main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2327                         if ((~main_sdram_bankmachine1_refresh_req)) begin
2328                                 builder_subfragments_bankmachine1_next_state <= 1'd0;
2329                         end
2330                 end
2331                 3'd5: begin
2332                         builder_subfragments_bankmachine1_next_state <= 2'd3;
2333                 end
2334                 3'd6: begin
2335                         builder_subfragments_bankmachine1_next_state <= 1'd0;
2336                 end
2337                 default: begin
2338                         if (main_sdram_bankmachine1_refresh_req) begin
2339                                 builder_subfragments_bankmachine1_next_state <= 3'd4;
2340                         end else begin
2341                                 if (main_sdram_bankmachine1_cmd_buffer_source_valid) begin
2342                                         if (main_sdram_bankmachine1_row_opened) begin
2343                                                 if (main_sdram_bankmachine1_row_hit) begin
2344                                                         main_sdram_bankmachine1_cmd_valid <= 1'd1;
2345                                                         if (main_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
2346                                                                 main_sdram_bankmachine1_req_wdata_ready <= main_sdram_bankmachine1_cmd_ready;
2347                                                                 main_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
2348                                                                 main_sdram_bankmachine1_cmd_payload_we <= 1'd1;
2349                                                         end else begin
2350                                                                 main_sdram_bankmachine1_req_rdata_valid <= main_sdram_bankmachine1_cmd_ready;
2351                                                                 main_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
2352                                                         end
2353                                                         main_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
2354                                                         if ((main_sdram_bankmachine1_cmd_ready & main_sdram_bankmachine1_auto_precharge)) begin
2355                                                                 builder_subfragments_bankmachine1_next_state <= 2'd2;
2356                                                         end
2357                                                 end else begin
2358                                                         builder_subfragments_bankmachine1_next_state <= 1'd1;
2359                                                 end
2360                                         end else begin
2361                                                 builder_subfragments_bankmachine1_next_state <= 2'd3;
2362                                         end
2363                                 end
2364                         end
2365                 end
2366         endcase
2367 end
2368 assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine2_req_valid;
2369 assign main_sdram_bankmachine2_req_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
2370 assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine2_req_we;
2371 assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine2_req_addr;
2372 assign main_sdram_bankmachine2_cmd_buffer_sink_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
2373 assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine2_cmd_buffer_sink_ready;
2374 assign main_sdram_bankmachine2_cmd_buffer_sink_first = main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
2375 assign main_sdram_bankmachine2_cmd_buffer_sink_last = main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
2376 assign main_sdram_bankmachine2_cmd_buffer_sink_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
2377 assign main_sdram_bankmachine2_cmd_buffer_sink_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
2378 assign main_sdram_bankmachine2_cmd_buffer_source_ready = (main_sdram_bankmachine2_req_wdata_ready | main_sdram_bankmachine2_req_rdata_valid);
2379 assign main_sdram_bankmachine2_req_lock = (main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine2_cmd_buffer_source_valid);
2380 assign main_sdram_bankmachine2_row_hit = (main_sdram_bankmachine2_row == main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]);
2381 assign main_sdram_bankmachine2_cmd_payload_ba = 2'd2;
2382 always @(*) begin
2383         main_sdram_bankmachine2_cmd_payload_a <= 13'd0;
2384         if (main_sdram_bankmachine2_row_col_n_addr_sel) begin
2385                 main_sdram_bankmachine2_cmd_payload_a <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
2386         end else begin
2387                 main_sdram_bankmachine2_cmd_payload_a <= ((main_sdram_bankmachine2_auto_precharge <<< 4'd10) | {main_sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2388         end
2389 end
2390 assign main_sdram_bankmachine2_twtpcon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_cmd_payload_is_write);
2391 assign main_sdram_bankmachine2_trccon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);
2392 assign main_sdram_bankmachine2_trascon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);
2393 always @(*) begin
2394         main_sdram_bankmachine2_auto_precharge <= 1'd0;
2395         if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine2_cmd_buffer_source_valid)) begin
2396                 if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9])) begin
2397                         main_sdram_bankmachine2_auto_precharge <= (main_sdram_bankmachine2_row_close == 1'd0);
2398                 end
2399         end
2400 end
2401 assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
2402 assign {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
2403 assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
2404 assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
2405 assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
2406 assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
2407 assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
2408 assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
2409 assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
2410 assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_first = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
2411 assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_last = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
2412 assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
2413 assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
2414 assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
2415 always @(*) begin
2416         main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2417         if (main_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
2418                 main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
2419         end else begin
2420                 main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine2_cmd_buffer_lookahead_produce;
2421         end
2422 end
2423 assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
2424 assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_sdram_bankmachine2_cmd_buffer_lookahead_replace));
2425 assign main_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
2426 assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine2_cmd_buffer_lookahead_consume;
2427 assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
2428 assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
2429 assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
2430 assign main_sdram_bankmachine2_cmd_buffer_sink_ready = ((~main_sdram_bankmachine2_cmd_buffer_source_valid) | main_sdram_bankmachine2_cmd_buffer_source_ready);
2431 always @(*) begin
2432         main_sdram_bankmachine2_row_open <= 1'd0;
2433         main_sdram_bankmachine2_row_close <= 1'd0;
2434         main_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
2435         main_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
2436         main_sdram_bankmachine2_cmd_payload_we <= 1'd0;
2437         main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
2438         main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
2439         main_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
2440         main_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
2441         builder_subfragments_bankmachine2_next_state <= 3'd0;
2442         main_sdram_bankmachine2_req_wdata_ready <= 1'd0;
2443         main_sdram_bankmachine2_req_rdata_valid <= 1'd0;
2444         main_sdram_bankmachine2_refresh_gnt <= 1'd0;
2445         main_sdram_bankmachine2_cmd_valid <= 1'd0;
2446         builder_subfragments_bankmachine2_next_state <= builder_subfragments_bankmachine2_state;
2447         case (builder_subfragments_bankmachine2_state)
2448                 1'd1: begin
2449                         if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin
2450                                 main_sdram_bankmachine2_cmd_valid <= 1'd1;
2451                                 if (main_sdram_bankmachine2_cmd_ready) begin
2452                                         builder_subfragments_bankmachine2_next_state <= 3'd5;
2453                                 end
2454                                 main_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2455                                 main_sdram_bankmachine2_cmd_payload_we <= 1'd1;
2456                                 main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2457                         end
2458                         main_sdram_bankmachine2_row_close <= 1'd1;
2459                 end
2460                 2'd2: begin
2461                         if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin
2462                                 builder_subfragments_bankmachine2_next_state <= 3'd5;
2463                         end
2464                         main_sdram_bankmachine2_row_close <= 1'd1;
2465                 end
2466                 2'd3: begin
2467                         if (main_sdram_bankmachine2_trccon_ready) begin
2468                                 main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
2469                                 main_sdram_bankmachine2_row_open <= 1'd1;
2470                                 main_sdram_bankmachine2_cmd_valid <= 1'd1;
2471                                 main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2472                                 if (main_sdram_bankmachine2_cmd_ready) begin
2473                                         builder_subfragments_bankmachine2_next_state <= 3'd6;
2474                                 end
2475                                 main_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2476                         end
2477                 end
2478                 3'd4: begin
2479                         if (main_sdram_bankmachine2_twtpcon_ready) begin
2480                                 main_sdram_bankmachine2_refresh_gnt <= 1'd1;
2481                         end
2482                         main_sdram_bankmachine2_row_close <= 1'd1;
2483                         main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2484                         if ((~main_sdram_bankmachine2_refresh_req)) begin
2485                                 builder_subfragments_bankmachine2_next_state <= 1'd0;
2486                         end
2487                 end
2488                 3'd5: begin
2489                         builder_subfragments_bankmachine2_next_state <= 2'd3;
2490                 end
2491                 3'd6: begin
2492                         builder_subfragments_bankmachine2_next_state <= 1'd0;
2493                 end
2494                 default: begin
2495                         if (main_sdram_bankmachine2_refresh_req) begin
2496                                 builder_subfragments_bankmachine2_next_state <= 3'd4;
2497                         end else begin
2498                                 if (main_sdram_bankmachine2_cmd_buffer_source_valid) begin
2499                                         if (main_sdram_bankmachine2_row_opened) begin
2500                                                 if (main_sdram_bankmachine2_row_hit) begin
2501                                                         main_sdram_bankmachine2_cmd_valid <= 1'd1;
2502                                                         if (main_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
2503                                                                 main_sdram_bankmachine2_req_wdata_ready <= main_sdram_bankmachine2_cmd_ready;
2504                                                                 main_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
2505                                                                 main_sdram_bankmachine2_cmd_payload_we <= 1'd1;
2506                                                         end else begin
2507                                                                 main_sdram_bankmachine2_req_rdata_valid <= main_sdram_bankmachine2_cmd_ready;
2508                                                                 main_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
2509                                                         end
2510                                                         main_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
2511                                                         if ((main_sdram_bankmachine2_cmd_ready & main_sdram_bankmachine2_auto_precharge)) begin
2512                                                                 builder_subfragments_bankmachine2_next_state <= 2'd2;
2513                                                         end
2514                                                 end else begin
2515                                                         builder_subfragments_bankmachine2_next_state <= 1'd1;
2516                                                 end
2517                                         end else begin
2518                                                 builder_subfragments_bankmachine2_next_state <= 2'd3;
2519                                         end
2520                                 end
2521                         end
2522                 end
2523         endcase
2524 end
2525 assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine3_req_valid;
2526 assign main_sdram_bankmachine3_req_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
2527 assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine3_req_we;
2528 assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine3_req_addr;
2529 assign main_sdram_bankmachine3_cmd_buffer_sink_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
2530 assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine3_cmd_buffer_sink_ready;
2531 assign main_sdram_bankmachine3_cmd_buffer_sink_first = main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
2532 assign main_sdram_bankmachine3_cmd_buffer_sink_last = main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
2533 assign main_sdram_bankmachine3_cmd_buffer_sink_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
2534 assign main_sdram_bankmachine3_cmd_buffer_sink_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
2535 assign main_sdram_bankmachine3_cmd_buffer_source_ready = (main_sdram_bankmachine3_req_wdata_ready | main_sdram_bankmachine3_req_rdata_valid);
2536 assign main_sdram_bankmachine3_req_lock = (main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine3_cmd_buffer_source_valid);
2537 assign main_sdram_bankmachine3_row_hit = (main_sdram_bankmachine3_row == main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]);
2538 assign main_sdram_bankmachine3_cmd_payload_ba = 2'd3;
2539 always @(*) begin
2540         main_sdram_bankmachine3_cmd_payload_a <= 13'd0;
2541         if (main_sdram_bankmachine3_row_col_n_addr_sel) begin
2542                 main_sdram_bankmachine3_cmd_payload_a <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
2543         end else begin
2544                 main_sdram_bankmachine3_cmd_payload_a <= ((main_sdram_bankmachine3_auto_precharge <<< 4'd10) | {main_sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2545         end
2546 end
2547 assign main_sdram_bankmachine3_twtpcon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_cmd_payload_is_write);
2548 assign main_sdram_bankmachine3_trccon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);
2549 assign main_sdram_bankmachine3_trascon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);
2550 always @(*) begin
2551         main_sdram_bankmachine3_auto_precharge <= 1'd0;
2552         if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine3_cmd_buffer_source_valid)) begin
2553                 if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9])) begin
2554                         main_sdram_bankmachine3_auto_precharge <= (main_sdram_bankmachine3_row_close == 1'd0);
2555                 end
2556         end
2557 end
2558 assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
2559 assign {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
2560 assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
2561 assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
2562 assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
2563 assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
2564 assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
2565 assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
2566 assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
2567 assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_first = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
2568 assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_last = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
2569 assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
2570 assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
2571 assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
2572 always @(*) begin
2573         main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2574         if (main_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
2575                 main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
2576         end else begin
2577                 main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine3_cmd_buffer_lookahead_produce;
2578         end
2579 end
2580 assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
2581 assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_sdram_bankmachine3_cmd_buffer_lookahead_replace));
2582 assign main_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
2583 assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine3_cmd_buffer_lookahead_consume;
2584 assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
2585 assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
2586 assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
2587 assign main_sdram_bankmachine3_cmd_buffer_sink_ready = ((~main_sdram_bankmachine3_cmd_buffer_source_valid) | main_sdram_bankmachine3_cmd_buffer_source_ready);
2588 always @(*) begin
2589         main_sdram_bankmachine3_refresh_gnt <= 1'd0;
2590         main_sdram_bankmachine3_cmd_valid <= 1'd0;
2591         main_sdram_bankmachine3_row_open <= 1'd0;
2592         main_sdram_bankmachine3_row_close <= 1'd0;
2593         builder_subfragments_bankmachine3_next_state <= 3'd0;
2594         main_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
2595         main_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
2596         main_sdram_bankmachine3_cmd_payload_we <= 1'd0;
2597         main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
2598         main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
2599         main_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
2600         main_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
2601         main_sdram_bankmachine3_req_wdata_ready <= 1'd0;
2602         main_sdram_bankmachine3_req_rdata_valid <= 1'd0;
2603         builder_subfragments_bankmachine3_next_state <= builder_subfragments_bankmachine3_state;
2604         case (builder_subfragments_bankmachine3_state)
2605                 1'd1: begin
2606                         if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin
2607                                 main_sdram_bankmachine3_cmd_valid <= 1'd1;
2608                                 if (main_sdram_bankmachine3_cmd_ready) begin
2609                                         builder_subfragments_bankmachine3_next_state <= 3'd5;
2610                                 end
2611                                 main_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2612                                 main_sdram_bankmachine3_cmd_payload_we <= 1'd1;
2613                                 main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2614                         end
2615                         main_sdram_bankmachine3_row_close <= 1'd1;
2616                 end
2617                 2'd2: begin
2618                         if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin
2619                                 builder_subfragments_bankmachine3_next_state <= 3'd5;
2620                         end
2621                         main_sdram_bankmachine3_row_close <= 1'd1;
2622                 end
2623                 2'd3: begin
2624                         if (main_sdram_bankmachine3_trccon_ready) begin
2625                                 main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
2626                                 main_sdram_bankmachine3_row_open <= 1'd1;
2627                                 main_sdram_bankmachine3_cmd_valid <= 1'd1;
2628                                 main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2629                                 if (main_sdram_bankmachine3_cmd_ready) begin
2630                                         builder_subfragments_bankmachine3_next_state <= 3'd6;
2631                                 end
2632                                 main_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2633                         end
2634                 end
2635                 3'd4: begin
2636                         if (main_sdram_bankmachine3_twtpcon_ready) begin
2637                                 main_sdram_bankmachine3_refresh_gnt <= 1'd1;
2638                         end
2639                         main_sdram_bankmachine3_row_close <= 1'd1;
2640                         main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2641                         if ((~main_sdram_bankmachine3_refresh_req)) begin
2642                                 builder_subfragments_bankmachine3_next_state <= 1'd0;
2643                         end
2644                 end
2645                 3'd5: begin
2646                         builder_subfragments_bankmachine3_next_state <= 2'd3;
2647                 end
2648                 3'd6: begin
2649                         builder_subfragments_bankmachine3_next_state <= 1'd0;
2650                 end
2651                 default: begin
2652                         if (main_sdram_bankmachine3_refresh_req) begin
2653                                 builder_subfragments_bankmachine3_next_state <= 3'd4;
2654                         end else begin
2655                                 if (main_sdram_bankmachine3_cmd_buffer_source_valid) begin
2656                                         if (main_sdram_bankmachine3_row_opened) begin
2657                                                 if (main_sdram_bankmachine3_row_hit) begin
2658                                                         main_sdram_bankmachine3_cmd_valid <= 1'd1;
2659                                                         if (main_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
2660                                                                 main_sdram_bankmachine3_req_wdata_ready <= main_sdram_bankmachine3_cmd_ready;
2661                                                                 main_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
2662                                                                 main_sdram_bankmachine3_cmd_payload_we <= 1'd1;
2663                                                         end else begin
2664                                                                 main_sdram_bankmachine3_req_rdata_valid <= main_sdram_bankmachine3_cmd_ready;
2665                                                                 main_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
2666                                                         end
2667                                                         main_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
2668                                                         if ((main_sdram_bankmachine3_cmd_ready & main_sdram_bankmachine3_auto_precharge)) begin
2669                                                                 builder_subfragments_bankmachine3_next_state <= 2'd2;
2670                                                         end
2671                                                 end else begin
2672                                                         builder_subfragments_bankmachine3_next_state <= 1'd1;
2673                                                 end
2674                                         end else begin
2675                                                 builder_subfragments_bankmachine3_next_state <= 2'd3;
2676                                         end
2677                                 end
2678                         end
2679                 end
2680         endcase
2681 end
2682 assign main_sdram_choose_req_want_cmds = 1'd1;
2683 assign main_sdram_trrdcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & ((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we)));
2684 assign main_sdram_tfawcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & ((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we)));
2685 assign main_sdram_ras_allowed = (main_sdram_trrdcon_ready & main_sdram_tfawcon_ready);
2686 assign main_sdram_tccdcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_cmd_payload_is_write | main_sdram_choose_req_cmd_payload_is_read));
2687 assign main_sdram_cas_allowed = main_sdram_tccdcon_ready;
2688 assign main_sdram_twtrcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
2689 assign main_sdram_read_available = ((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_read) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_read)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_read)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_read));
2690 assign main_sdram_write_available = ((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_write) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_write)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_write)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_write));
2691 assign main_sdram_max_time0 = (main_sdram_time0 == 1'd0);
2692 assign main_sdram_max_time1 = (main_sdram_time1 == 1'd0);
2693 assign main_sdram_bankmachine0_refresh_req = main_sdram_cmd_valid;
2694 assign main_sdram_bankmachine1_refresh_req = main_sdram_cmd_valid;
2695 assign main_sdram_bankmachine2_refresh_req = main_sdram_cmd_valid;
2696 assign main_sdram_bankmachine3_refresh_req = main_sdram_cmd_valid;
2697 assign main_sdram_go_to_refresh = (((main_sdram_bankmachine0_refresh_gnt & main_sdram_bankmachine1_refresh_gnt) & main_sdram_bankmachine2_refresh_gnt) & main_sdram_bankmachine3_refresh_gnt);
2698 assign main_sdram_interface_rdata = {main_sdram_dfi_p0_rddata};
2699 assign {main_sdram_dfi_p0_wrdata} = main_sdram_interface_wdata;
2700 assign {main_sdram_dfi_p0_wrdata_mask} = (~main_sdram_interface_wdata_we);
2701 always @(*) begin
2702         main_sdram_choose_cmd_valids <= 4'd0;
2703         main_sdram_choose_cmd_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
2704         main_sdram_choose_cmd_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
2705         main_sdram_choose_cmd_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
2706         main_sdram_choose_cmd_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
2707 end
2708 assign main_sdram_choose_cmd_request = main_sdram_choose_cmd_valids;
2709 assign main_sdram_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
2710 assign main_sdram_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
2711 assign main_sdram_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
2712 assign main_sdram_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
2713 assign main_sdram_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
2714 assign main_sdram_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
2715 always @(*) begin
2716         main_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
2717         if (main_sdram_choose_cmd_cmd_valid) begin
2718                 main_sdram_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
2719         end
2720 end
2721 always @(*) begin
2722         main_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
2723         if (main_sdram_choose_cmd_cmd_valid) begin
2724                 main_sdram_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
2725         end
2726 end
2727 always @(*) begin
2728         main_sdram_choose_cmd_cmd_payload_we <= 1'd0;
2729         if (main_sdram_choose_cmd_cmd_valid) begin
2730                 main_sdram_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
2731         end
2732 end
2733 assign main_sdram_choose_cmd_ce = (main_sdram_choose_cmd_cmd_ready | (~main_sdram_choose_cmd_cmd_valid));
2734 always @(*) begin
2735         main_sdram_choose_req_valids <= 4'd0;
2736         main_sdram_choose_req_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
2737         main_sdram_choose_req_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
2738         main_sdram_choose_req_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
2739         main_sdram_choose_req_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
2740 end
2741 assign main_sdram_choose_req_request = main_sdram_choose_req_valids;
2742 assign main_sdram_choose_req_cmd_valid = builder_rhs_array_muxed6;
2743 assign main_sdram_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
2744 assign main_sdram_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
2745 assign main_sdram_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
2746 assign main_sdram_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
2747 assign main_sdram_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
2748 always @(*) begin
2749         main_sdram_choose_req_cmd_payload_cas <= 1'd0;
2750         if (main_sdram_choose_req_cmd_valid) begin
2751                 main_sdram_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
2752         end
2753 end
2754 always @(*) begin
2755         main_sdram_choose_req_cmd_payload_ras <= 1'd0;
2756         if (main_sdram_choose_req_cmd_valid) begin
2757                 main_sdram_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
2758         end
2759 end
2760 always @(*) begin
2761         main_sdram_choose_req_cmd_payload_we <= 1'd0;
2762         if (main_sdram_choose_req_cmd_valid) begin
2763                 main_sdram_choose_req_cmd_payload_we <= builder_t_array_muxed5;
2764         end
2765 end
2766 always @(*) begin
2767         main_sdram_bankmachine0_cmd_ready <= 1'd0;
2768         if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd0))) begin
2769                 main_sdram_bankmachine0_cmd_ready <= 1'd1;
2770         end
2771         if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd0))) begin
2772                 main_sdram_bankmachine0_cmd_ready <= 1'd1;
2773         end
2774 end
2775 always @(*) begin
2776         main_sdram_bankmachine1_cmd_ready <= 1'd0;
2777         if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd1))) begin
2778                 main_sdram_bankmachine1_cmd_ready <= 1'd1;
2779         end
2780         if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd1))) begin
2781                 main_sdram_bankmachine1_cmd_ready <= 1'd1;
2782         end
2783 end
2784 always @(*) begin
2785         main_sdram_bankmachine2_cmd_ready <= 1'd0;
2786         if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd2))) begin
2787                 main_sdram_bankmachine2_cmd_ready <= 1'd1;
2788         end
2789         if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd2))) begin
2790                 main_sdram_bankmachine2_cmd_ready <= 1'd1;
2791         end
2792 end
2793 always @(*) begin
2794         main_sdram_bankmachine3_cmd_ready <= 1'd0;
2795         if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd3))) begin
2796                 main_sdram_bankmachine3_cmd_ready <= 1'd1;
2797         end
2798         if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd3))) begin
2799                 main_sdram_bankmachine3_cmd_ready <= 1'd1;
2800         end
2801 end
2802 assign main_sdram_choose_req_ce = (main_sdram_choose_req_cmd_ready | (~main_sdram_choose_req_cmd_valid));
2803 assign main_sdram_dfi_p0_reset_n = 1'd1;
2804 assign main_sdram_dfi_p0_cke = {1{main_sdram_steerer0}};
2805 assign main_sdram_dfi_p0_odt = {1{main_sdram_steerer1}};
2806 always @(*) begin
2807         main_sdram_choose_req_want_writes <= 1'd0;
2808         main_sdram_cmd_ready <= 1'd0;
2809         main_sdram_choose_req_want_activates <= 1'd0;
2810         main_sdram_choose_req_cmd_ready <= 1'd0;
2811         main_sdram_steerer_sel <= 2'd0;
2812         builder_subfragments_multiplexer_next_state <= 3'd0;
2813         main_sdram_en0 <= 1'd0;
2814         main_sdram_en1 <= 1'd0;
2815         main_sdram_choose_req_want_reads <= 1'd0;
2816         main_sdram_choose_req_want_activates <= main_sdram_ras_allowed;
2817         builder_subfragments_multiplexer_next_state <= builder_subfragments_multiplexer_state;
2818         case (builder_subfragments_multiplexer_state)
2819                 1'd1: begin
2820                         main_sdram_en1 <= 1'd1;
2821                         main_sdram_choose_req_want_writes <= 1'd1;
2822                         if (1'd1) begin
2823                                 main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));
2824                         end else begin
2825                                 main_sdram_choose_req_want_activates <= main_sdram_ras_allowed;
2826                                 main_sdram_choose_req_cmd_ready <= ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed);
2827                                 main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;
2828                         end
2829                         main_sdram_steerer_sel <= 2'd2;
2830                         if (main_sdram_read_available) begin
2831                                 if (((~main_sdram_write_available) | main_sdram_max_time1)) begin
2832                                         builder_subfragments_multiplexer_next_state <= 2'd3;
2833                                 end
2834                         end
2835                         if (main_sdram_go_to_refresh) begin
2836                                 builder_subfragments_multiplexer_next_state <= 2'd2;
2837                         end
2838                 end
2839                 2'd2: begin
2840                         main_sdram_steerer_sel <= 2'd3;
2841                         main_sdram_cmd_ready <= 1'd1;
2842                         if (main_sdram_cmd_last) begin
2843                                 builder_subfragments_multiplexer_next_state <= 1'd0;
2844                         end
2845                 end
2846                 2'd3: begin
2847                         if (main_sdram_twtrcon_ready) begin
2848                                 builder_subfragments_multiplexer_next_state <= 1'd0;
2849                         end
2850                 end
2851                 3'd4: begin
2852                         builder_subfragments_multiplexer_next_state <= 3'd5;
2853                 end
2854                 3'd5: begin
2855                         builder_subfragments_multiplexer_next_state <= 1'd1;
2856                 end
2857                 default: begin
2858                         main_sdram_en0 <= 1'd1;
2859                         main_sdram_choose_req_want_reads <= 1'd1;
2860                         if (1'd1) begin
2861                                 main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));
2862                         end else begin
2863                                 main_sdram_choose_req_want_activates <= main_sdram_ras_allowed;
2864                                 main_sdram_choose_req_cmd_ready <= ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed);
2865                                 main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;
2866                         end
2867                         main_sdram_steerer_sel <= 2'd2;
2868                         if (main_sdram_write_available) begin
2869                                 if (((~main_sdram_read_available) | main_sdram_max_time0)) begin
2870                                         builder_subfragments_multiplexer_next_state <= 3'd4;
2871                                 end
2872                         end
2873                         if (main_sdram_go_to_refresh) begin
2874                                 builder_subfragments_multiplexer_next_state <= 2'd2;
2875                         end
2876                 end
2877         endcase
2878 end
2879 assign builder_subfragments_roundrobin0_request = {(((main_port_cmd_payload_addr[10:9] == 1'd0) & (~(((builder_subfragments_locked0 | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid)};
2880 assign builder_subfragments_roundrobin0_ce = ((~main_sdram_interface_bank0_valid) & (~main_sdram_interface_bank0_lock));
2881 assign main_sdram_interface_bank0_addr = builder_rhs_array_muxed12;
2882 assign main_sdram_interface_bank0_we = builder_rhs_array_muxed13;
2883 assign main_sdram_interface_bank0_valid = builder_rhs_array_muxed14;
2884 assign builder_subfragments_roundrobin1_request = {(((main_port_cmd_payload_addr[10:9] == 1'd1) & (~(((builder_subfragments_locked1 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid)};
2885 assign builder_subfragments_roundrobin1_ce = ((~main_sdram_interface_bank1_valid) & (~main_sdram_interface_bank1_lock));
2886 assign main_sdram_interface_bank1_addr = builder_rhs_array_muxed15;
2887 assign main_sdram_interface_bank1_we = builder_rhs_array_muxed16;
2888 assign main_sdram_interface_bank1_valid = builder_rhs_array_muxed17;
2889 assign builder_subfragments_roundrobin2_request = {(((main_port_cmd_payload_addr[10:9] == 2'd2) & (~(((builder_subfragments_locked2 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid)};
2890 assign builder_subfragments_roundrobin2_ce = ((~main_sdram_interface_bank2_valid) & (~main_sdram_interface_bank2_lock));
2891 assign main_sdram_interface_bank2_addr = builder_rhs_array_muxed18;
2892 assign main_sdram_interface_bank2_we = builder_rhs_array_muxed19;
2893 assign main_sdram_interface_bank2_valid = builder_rhs_array_muxed20;
2894 assign builder_subfragments_roundrobin3_request = {(((main_port_cmd_payload_addr[10:9] == 2'd3) & (~(((builder_subfragments_locked3 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))))) & main_port_cmd_valid)};
2895 assign builder_subfragments_roundrobin3_ce = ((~main_sdram_interface_bank3_valid) & (~main_sdram_interface_bank3_lock));
2896 assign main_sdram_interface_bank3_addr = builder_rhs_array_muxed21;
2897 assign main_sdram_interface_bank3_we = builder_rhs_array_muxed22;
2898 assign main_sdram_interface_bank3_valid = builder_rhs_array_muxed23;
2899 assign main_port_cmd_ready = ((((1'd0 | (((builder_subfragments_roundrobin0_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 1'd0) & (~(((builder_subfragments_locked0 | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0)))))) & main_sdram_interface_bank0_ready)) | (((builder_subfragments_roundrobin1_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 1'd1) & (~(((builder_subfragments_locked1 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0)))))) & main_sdram_interface_bank1_ready)) | (((builder_subfragments_roundrobin2_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 2'd2) & (~(((builder_subfragments_locked2 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0)))))) & main_sdram_interface_bank2_ready)) | (((builder_subfragments_roundrobin3_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 2'd3) & (~(((builder_subfragments_locked3 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0)))))) & main_sdram_interface_bank3_ready));
2900 assign main_port_wdata_ready = builder_subfragments_new_master_wdata_ready;
2901 assign main_port_rdata_valid = builder_subfragments_new_master_rdata_valid3;
2902 always @(*) begin
2903         main_sdram_interface_wdata_we <= 2'd0;
2904         main_sdram_interface_wdata <= 16'd0;
2905         case ({builder_subfragments_new_master_wdata_ready})
2906                 1'd1: begin
2907                         main_sdram_interface_wdata <= main_port_wdata_payload_data;
2908                         main_sdram_interface_wdata_we <= main_port_wdata_payload_we;
2909                 end
2910                 default: begin
2911                         main_sdram_interface_wdata <= 1'd0;
2912                         main_sdram_interface_wdata_we <= 1'd0;
2913                 end
2914         endcase
2915 end
2916 assign main_port_rdata_payload_data = main_sdram_interface_rdata;
2917 assign builder_subfragments_roundrobin0_grant = 1'd0;
2918 assign builder_subfragments_roundrobin1_grant = 1'd0;
2919 assign builder_subfragments_roundrobin2_grant = 1'd0;
2920 assign builder_subfragments_roundrobin3_grant = 1'd0;
2921 assign main_converter_reset = (~main_wb_sdram_cyc);
2922 always @(*) begin
2923         main_litedram_wb_dat_w <= 16'd0;
2924         case (main_converter_counter)
2925                 1'd0: begin
2926                         main_litedram_wb_dat_w <= main_wb_sdram_dat_w[31:0];
2927                 end
2928                 1'd1: begin
2929                         main_litedram_wb_dat_w <= main_wb_sdram_dat_w[31:16];
2930                 end
2931         endcase
2932 end
2933 assign main_wb_sdram_dat_r = {main_litedram_wb_dat_r, main_converter_dat_r[31:16]};
2934 always @(*) begin
2935         main_litedram_wb_cyc <= 1'd0;
2936         main_litedram_wb_adr <= 30'd0;
2937         main_litedram_wb_stb <= 1'd0;
2938         main_litedram_wb_we <= 1'd0;
2939         main_converter_skip <= 1'd0;
2940         main_wb_sdram_ack <= 1'd0;
2941         builder_subfragments_next_state <= 1'd0;
2942         main_converter_counter_subfragments_next_value <= 1'd0;
2943         main_converter_counter_subfragments_next_value_ce <= 1'd0;
2944         main_litedram_wb_sel <= 2'd0;
2945         builder_subfragments_next_state <= builder_subfragments_state;
2946         case (builder_subfragments_state)
2947                 1'd1: begin
2948                         main_litedram_wb_adr <= {main_wb_sdram_adr, main_converter_counter};
2949                         case (main_converter_counter)
2950                                 1'd0: begin
2951                                         main_litedram_wb_sel <= main_wb_sdram_sel[3:0];
2952                                 end
2953                                 1'd1: begin
2954                                         main_litedram_wb_sel <= main_wb_sdram_sel[3:2];
2955                                 end
2956                         endcase
2957                         if ((main_wb_sdram_stb & main_wb_sdram_cyc)) begin
2958                                 main_converter_skip <= (main_litedram_wb_sel == 1'd0);
2959                                 main_litedram_wb_we <= main_wb_sdram_we;
2960                                 main_litedram_wb_cyc <= (~main_converter_skip);
2961                                 main_litedram_wb_stb <= (~main_converter_skip);
2962                                 if ((main_litedram_wb_ack | main_converter_skip)) begin
2963                                         main_converter_counter_subfragments_next_value <= (main_converter_counter + 1'd1);
2964                                         main_converter_counter_subfragments_next_value_ce <= 1'd1;
2965                                         if ((main_converter_counter == 1'd1)) begin
2966                                                 main_wb_sdram_ack <= 1'd1;
2967                                                 builder_subfragments_next_state <= 1'd0;
2968                                         end
2969                                 end
2970                         end
2971                 end
2972                 default: begin
2973                         main_converter_counter_subfragments_next_value <= 1'd0;
2974                         main_converter_counter_subfragments_next_value_ce <= 1'd1;
2975                         if ((main_wb_sdram_stb & main_wb_sdram_cyc)) begin
2976                                 builder_subfragments_next_state <= 1'd1;
2977                         end
2978                 end
2979         endcase
2980 end
2981 assign main_port_cmd_payload_addr = (main_litedram_wb_adr - 31'd1207959552);
2982 assign main_port_cmd_payload_we = main_litedram_wb_we;
2983 assign main_port_wdata_payload_data = main_litedram_wb_dat_w;
2984 assign main_port_wdata_payload_we = main_litedram_wb_sel;
2985 assign main_litedram_wb_dat_r = main_port_rdata_payload_data;
2986 assign main_port_flush = (~main_litedram_wb_cyc);
2987 assign main_port_cmd_last = (~main_litedram_wb_we);
2988 assign main_port_cmd_valid = ((main_litedram_wb_cyc & main_litedram_wb_stb) & (~main_cmd_consumed));
2989 assign main_port_wdata_valid = (((main_port_cmd_valid | main_cmd_consumed) & main_port_cmd_payload_we) & (~main_wdata_consumed));
2990 assign main_port_rdata_ready = ((main_port_cmd_valid | main_cmd_consumed) & (~main_port_cmd_payload_we));
2991 assign main_litedram_wb_ack = (main_ack_cmd & ((main_litedram_wb_we & main_ack_wdata) | ((~main_litedram_wb_we) & main_ack_rdata)));
2992 assign main_ack_cmd = ((main_port_cmd_valid & main_port_cmd_ready) | main_cmd_consumed);
2993 assign main_ack_wdata = ((main_port_wdata_valid & main_port_wdata_ready) | main_wdata_consumed);
2994 assign main_ack_rdata = (main_port_rdata_valid & main_port_rdata_ready);
2995 assign main_uart_sink_valid = main_uart_phy_source_valid;
2996 assign main_uart_phy_source_ready = main_uart_sink_ready;
2997 assign main_uart_sink_first = main_uart_phy_source_first;
2998 assign main_uart_sink_last = main_uart_phy_source_last;
2999 assign main_uart_sink_payload_data = main_uart_phy_source_payload_data;
3000 assign main_uart_phy_sink_valid = main_uart_source_valid;
3001 assign main_uart_source_ready = main_uart_phy_sink_ready;
3002 assign main_uart_phy_sink_first = main_uart_source_first;
3003 assign main_uart_phy_sink_last = main_uart_source_last;
3004 assign main_uart_phy_sink_payload_data = main_uart_source_payload_data;
3005 assign main_tx_fifo_sink_valid = main_rxtx_re;
3006 assign main_tx_fifo_sink_payload_data = main_rxtx_r;
3007 assign main_txfull_status = (~main_tx_fifo_sink_ready);
3008 assign main_txempty_status = (~main_tx_fifo_source_valid);
3009 assign main_uart_source_valid = main_tx_fifo_source_valid;
3010 assign main_tx_fifo_source_ready = main_uart_source_ready;
3011 assign main_uart_source_first = main_tx_fifo_source_first;
3012 assign main_uart_source_last = main_tx_fifo_source_last;
3013 assign main_uart_source_payload_data = main_tx_fifo_source_payload_data;
3014 assign main_tx_trigger = (~main_tx_fifo_sink_ready);
3015 assign main_rx_fifo_sink_valid = main_uart_sink_valid;
3016 assign main_uart_sink_ready = main_rx_fifo_sink_ready;
3017 assign main_rx_fifo_sink_first = main_uart_sink_first;
3018 assign main_rx_fifo_sink_last = main_uart_sink_last;
3019 assign main_rx_fifo_sink_payload_data = main_uart_sink_payload_data;
3020 assign main_rxempty_status = (~main_rx_fifo_source_valid);
3021 assign main_rxfull_status = (~main_rx_fifo_sink_ready);
3022 assign main_rxtx_w = main_rx_fifo_source_payload_data;
3023 assign main_rx_fifo_source_ready = (main_rx_clear | (1'd0 & main_rxtx_we));
3024 assign main_rx_trigger = (~main_rx_fifo_source_valid);
3025 always @(*) begin
3026         main_tx_clear <= 1'd0;
3027         if ((main_eventmanager_pending_re & main_eventmanager_pending_r[0])) begin
3028                 main_tx_clear <= 1'd1;
3029         end
3030 end
3031 always @(*) begin
3032         main_eventmanager_status_w <= 2'd0;
3033         main_eventmanager_status_w[0] <= main_tx_status;
3034         main_eventmanager_status_w[1] <= main_rx_status;
3035 end
3036 always @(*) begin
3037         main_rx_clear <= 1'd0;
3038         if ((main_eventmanager_pending_re & main_eventmanager_pending_r[1])) begin
3039                 main_rx_clear <= 1'd1;
3040         end
3041 end
3042 always @(*) begin
3043         main_eventmanager_pending_w <= 2'd0;
3044         main_eventmanager_pending_w[0] <= main_tx_pending;
3045         main_eventmanager_pending_w[1] <= main_rx_pending;
3046 end
3047 assign main_irq = ((main_eventmanager_pending_w[0] & main_eventmanager_storage[0]) | (main_eventmanager_pending_w[1] & main_eventmanager_storage[1]));
3048 assign main_tx_status = main_tx_trigger;
3049 assign main_rx_status = main_rx_trigger;
3050 assign main_tx_fifo_syncfifo_din = {main_tx_fifo_fifo_in_last, main_tx_fifo_fifo_in_first, main_tx_fifo_fifo_in_payload_data};
3051 assign {main_tx_fifo_fifo_out_last, main_tx_fifo_fifo_out_first, main_tx_fifo_fifo_out_payload_data} = main_tx_fifo_syncfifo_dout;
3052 assign main_tx_fifo_sink_ready = main_tx_fifo_syncfifo_writable;
3053 assign main_tx_fifo_syncfifo_we = main_tx_fifo_sink_valid;
3054 assign main_tx_fifo_fifo_in_first = main_tx_fifo_sink_first;
3055 assign main_tx_fifo_fifo_in_last = main_tx_fifo_sink_last;
3056 assign main_tx_fifo_fifo_in_payload_data = main_tx_fifo_sink_payload_data;
3057 assign main_tx_fifo_source_valid = main_tx_fifo_readable;
3058 assign main_tx_fifo_source_first = main_tx_fifo_fifo_out_first;
3059 assign main_tx_fifo_source_last = main_tx_fifo_fifo_out_last;
3060 assign main_tx_fifo_source_payload_data = main_tx_fifo_fifo_out_payload_data;
3061 assign main_tx_fifo_re = main_tx_fifo_source_ready;
3062 assign main_tx_fifo_syncfifo_re = (main_tx_fifo_syncfifo_readable & ((~main_tx_fifo_readable) | main_tx_fifo_re));
3063 assign main_tx_fifo_level1 = (main_tx_fifo_level0 + main_tx_fifo_readable);
3064 always @(*) begin
3065         main_tx_fifo_wrport_adr <= 4'd0;
3066         if (main_tx_fifo_replace) begin
3067                 main_tx_fifo_wrport_adr <= (main_tx_fifo_produce - 1'd1);
3068         end else begin
3069                 main_tx_fifo_wrport_adr <= main_tx_fifo_produce;
3070         end
3071 end
3072 assign main_tx_fifo_wrport_dat_w = main_tx_fifo_syncfifo_din;
3073 assign main_tx_fifo_wrport_we = (main_tx_fifo_syncfifo_we & (main_tx_fifo_syncfifo_writable | main_tx_fifo_replace));
3074 assign main_tx_fifo_do_read = (main_tx_fifo_syncfifo_readable & main_tx_fifo_syncfifo_re);
3075 assign main_tx_fifo_rdport_adr = main_tx_fifo_consume;
3076 assign main_tx_fifo_syncfifo_dout = main_tx_fifo_rdport_dat_r;
3077 assign main_tx_fifo_rdport_re = main_tx_fifo_do_read;
3078 assign main_tx_fifo_syncfifo_writable = (main_tx_fifo_level0 != 5'd16);
3079 assign main_tx_fifo_syncfifo_readable = (main_tx_fifo_level0 != 1'd0);
3080 assign main_rx_fifo_syncfifo_din = {main_rx_fifo_fifo_in_last, main_rx_fifo_fifo_in_first, main_rx_fifo_fifo_in_payload_data};
3081 assign {main_rx_fifo_fifo_out_last, main_rx_fifo_fifo_out_first, main_rx_fifo_fifo_out_payload_data} = main_rx_fifo_syncfifo_dout;
3082 assign main_rx_fifo_sink_ready = main_rx_fifo_syncfifo_writable;
3083 assign main_rx_fifo_syncfifo_we = main_rx_fifo_sink_valid;
3084 assign main_rx_fifo_fifo_in_first = main_rx_fifo_sink_first;
3085 assign main_rx_fifo_fifo_in_last = main_rx_fifo_sink_last;
3086 assign main_rx_fifo_fifo_in_payload_data = main_rx_fifo_sink_payload_data;
3087 assign main_rx_fifo_source_valid = main_rx_fifo_readable;
3088 assign main_rx_fifo_source_first = main_rx_fifo_fifo_out_first;
3089 assign main_rx_fifo_source_last = main_rx_fifo_fifo_out_last;
3090 assign main_rx_fifo_source_payload_data = main_rx_fifo_fifo_out_payload_data;
3091 assign main_rx_fifo_re = main_rx_fifo_source_ready;
3092 assign main_rx_fifo_syncfifo_re = (main_rx_fifo_syncfifo_readable & ((~main_rx_fifo_readable) | main_rx_fifo_re));
3093 assign main_rx_fifo_level1 = (main_rx_fifo_level0 + main_rx_fifo_readable);
3094 always @(*) begin
3095         main_rx_fifo_wrport_adr <= 4'd0;
3096         if (main_rx_fifo_replace) begin
3097                 main_rx_fifo_wrport_adr <= (main_rx_fifo_produce - 1'd1);
3098         end else begin
3099                 main_rx_fifo_wrport_adr <= main_rx_fifo_produce;
3100         end
3101 end
3102 assign main_rx_fifo_wrport_dat_w = main_rx_fifo_syncfifo_din;
3103 assign main_rx_fifo_wrport_we = (main_rx_fifo_syncfifo_we & (main_rx_fifo_syncfifo_writable | main_rx_fifo_replace));
3104 assign main_rx_fifo_do_read = (main_rx_fifo_syncfifo_readable & main_rx_fifo_syncfifo_re);
3105 assign main_rx_fifo_rdport_adr = main_rx_fifo_consume;
3106 assign main_rx_fifo_syncfifo_dout = main_rx_fifo_rdport_dat_r;
3107 assign main_rx_fifo_rdport_re = main_rx_fifo_do_read;
3108 assign main_rx_fifo_syncfifo_writable = (main_rx_fifo_level0 != 5'd16);
3109 assign main_rx_fifo_syncfifo_readable = (main_rx_fifo_level0 != 1'd0);
3110 always @(*) begin
3111         main_gpio0_pads_gpio0i <= 8'd0;
3112         main_gpio0_pads_gpio0i[0] <= main_libresocsim_libresoc_constraintmanager_gpio_i[0];
3113         main_gpio0_pads_gpio0i[1] <= main_libresocsim_libresoc_constraintmanager_gpio_i[1];
3114         main_gpio0_pads_gpio0i[2] <= main_libresocsim_libresoc_constraintmanager_gpio_i[2];
3115         main_gpio0_pads_gpio0i[3] <= main_libresocsim_libresoc_constraintmanager_gpio_i[3];
3116         main_gpio0_pads_gpio0i[4] <= main_libresocsim_libresoc_constraintmanager_gpio_i[4];
3117         main_gpio0_pads_gpio0i[5] <= main_libresocsim_libresoc_constraintmanager_gpio_i[5];
3118         main_gpio0_pads_gpio0i[6] <= main_libresocsim_libresoc_constraintmanager_gpio_i[6];
3119         main_gpio0_pads_gpio0i[7] <= main_libresocsim_libresoc_constraintmanager_gpio_i[7];
3120 end
3121 always @(*) begin
3122         main_gpio1_pads_gpio1i <= 8'd0;
3123         main_gpio1_pads_gpio1i[0] <= main_libresocsim_libresoc_constraintmanager_gpio_i[8];
3124         main_gpio1_pads_gpio1i[1] <= main_libresocsim_libresoc_constraintmanager_gpio_i[9];
3125         main_gpio1_pads_gpio1i[2] <= main_libresocsim_libresoc_constraintmanager_gpio_i[10];
3126         main_gpio1_pads_gpio1i[3] <= main_libresocsim_libresoc_constraintmanager_gpio_i[11];
3127         main_gpio1_pads_gpio1i[4] <= main_libresocsim_libresoc_constraintmanager_gpio_i[12];
3128         main_gpio1_pads_gpio1i[5] <= main_libresocsim_libresoc_constraintmanager_gpio_i[13];
3129         main_gpio1_pads_gpio1i[6] <= main_libresocsim_libresoc_constraintmanager_gpio_i[14];
3130         main_gpio1_pads_gpio1i[7] <= main_libresocsim_libresoc_constraintmanager_gpio_i[15];
3131 end
3132 always @(*) begin
3133         main_libresocsim_libresoc_constraintmanager_gpio_o <= 16'd0;
3134         main_libresocsim_libresoc_constraintmanager_gpio_o[0] <= main_gpio0_pads_gpio0o[0];
3135         main_libresocsim_libresoc_constraintmanager_gpio_o[1] <= main_gpio0_pads_gpio0o[1];
3136         main_libresocsim_libresoc_constraintmanager_gpio_o[2] <= main_gpio0_pads_gpio0o[2];
3137         main_libresocsim_libresoc_constraintmanager_gpio_o[3] <= main_gpio0_pads_gpio0o[3];
3138         main_libresocsim_libresoc_constraintmanager_gpio_o[4] <= main_gpio0_pads_gpio0o[4];
3139         main_libresocsim_libresoc_constraintmanager_gpio_o[5] <= main_gpio0_pads_gpio0o[5];
3140         main_libresocsim_libresoc_constraintmanager_gpio_o[6] <= main_gpio0_pads_gpio0o[6];
3141         main_libresocsim_libresoc_constraintmanager_gpio_o[7] <= main_gpio0_pads_gpio0o[7];
3142         main_libresocsim_libresoc_constraintmanager_gpio_o[8] <= main_gpio1_pads_gpio1o[0];
3143         main_libresocsim_libresoc_constraintmanager_gpio_o[9] <= main_gpio1_pads_gpio1o[1];
3144         main_libresocsim_libresoc_constraintmanager_gpio_o[10] <= main_gpio1_pads_gpio1o[2];
3145         main_libresocsim_libresoc_constraintmanager_gpio_o[11] <= main_gpio1_pads_gpio1o[3];
3146         main_libresocsim_libresoc_constraintmanager_gpio_o[12] <= main_gpio1_pads_gpio1o[4];
3147         main_libresocsim_libresoc_constraintmanager_gpio_o[13] <= main_gpio1_pads_gpio1o[5];
3148         main_libresocsim_libresoc_constraintmanager_gpio_o[14] <= main_gpio1_pads_gpio1o[6];
3149         main_libresocsim_libresoc_constraintmanager_gpio_o[15] <= main_gpio1_pads_gpio1o[7];
3150 end
3151 always @(*) begin
3152         main_libresocsim_libresoc_constraintmanager_gpio_oe <= 16'd0;
3153         main_libresocsim_libresoc_constraintmanager_gpio_oe[0] <= main_gpio0_pads_gpio0oe[0];
3154         main_libresocsim_libresoc_constraintmanager_gpio_oe[1] <= main_gpio0_pads_gpio0oe[1];
3155         main_libresocsim_libresoc_constraintmanager_gpio_oe[2] <= main_gpio0_pads_gpio0oe[2];
3156         main_libresocsim_libresoc_constraintmanager_gpio_oe[3] <= main_gpio0_pads_gpio0oe[3];
3157         main_libresocsim_libresoc_constraintmanager_gpio_oe[4] <= main_gpio0_pads_gpio0oe[4];
3158         main_libresocsim_libresoc_constraintmanager_gpio_oe[5] <= main_gpio0_pads_gpio0oe[5];
3159         main_libresocsim_libresoc_constraintmanager_gpio_oe[6] <= main_gpio0_pads_gpio0oe[6];
3160         main_libresocsim_libresoc_constraintmanager_gpio_oe[7] <= main_gpio0_pads_gpio0oe[7];
3161         main_libresocsim_libresoc_constraintmanager_gpio_oe[8] <= main_gpio1_pads_gpio1oe[0];
3162         main_libresocsim_libresoc_constraintmanager_gpio_oe[9] <= main_gpio1_pads_gpio1oe[1];
3163         main_libresocsim_libresoc_constraintmanager_gpio_oe[10] <= main_gpio1_pads_gpio1oe[2];
3164         main_libresocsim_libresoc_constraintmanager_gpio_oe[11] <= main_gpio1_pads_gpio1oe[3];
3165         main_libresocsim_libresoc_constraintmanager_gpio_oe[12] <= main_gpio1_pads_gpio1oe[4];
3166         main_libresocsim_libresoc_constraintmanager_gpio_oe[13] <= main_gpio1_pads_gpio1oe[5];
3167         main_libresocsim_libresoc_constraintmanager_gpio_oe[14] <= main_gpio1_pads_gpio1oe[6];
3168         main_libresocsim_libresoc_constraintmanager_gpio_oe[15] <= main_gpio1_pads_gpio1oe[7];
3169 end
3170 assign main_libresocsim_libresoc_constraintmanager_i2c_scl = main_i2c_scl;
3171 assign main_libresocsim_libresoc_constraintmanager_i2c_sda_oe = main_i2c_oe;
3172 assign main_libresocsim_libresoc_constraintmanager_i2c_sda_o = main_i2c_sda0;
3173 assign main_i2c_sda1 = main_libresocsim_libresoc_constraintmanager_i2c_sda_i;
3174 always @(*) begin
3175         builder_libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0;
3176         builder_libresocsim_libresocsim_wishbone_ack <= 1'd0;
3177         builder_libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0;
3178         builder_libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0;
3179         builder_libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0;
3180         builder_libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
3181         builder_libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0;
3182         builder_libresocsim_libresocsim_wishbone_dat_r <= 32'd0;
3183         builder_libresocsim_next_state <= 2'd0;
3184         builder_libresocsim_next_state <= builder_libresocsim_state;
3185         case (builder_libresocsim_state)
3186                 1'd1: begin
3187                         builder_libresocsim_libresocsim_adr_libresocsim_next_value1 <= 1'd0;
3188                         builder_libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
3189                         builder_libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
3190                         builder_libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
3191                         builder_libresocsim_next_state <= 2'd2;
3192                 end
3193                 2'd2: begin
3194                         builder_libresocsim_libresocsim_wishbone_ack <= 1'd1;
3195                         builder_libresocsim_libresocsim_wishbone_dat_r <= builder_libresocsim_libresocsim_dat_r;
3196                         builder_libresocsim_next_state <= 1'd0;
3197                 end
3198                 default: begin
3199                         builder_libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= builder_libresocsim_libresocsim_wishbone_dat_w;
3200                         builder_libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd1;
3201                         if ((builder_libresocsim_libresocsim_wishbone_cyc & builder_libresocsim_libresocsim_wishbone_stb)) begin
3202                                 builder_libresocsim_libresocsim_adr_libresocsim_next_value1 <= builder_libresocsim_libresocsim_wishbone_adr;
3203                                 builder_libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
3204                                 builder_libresocsim_libresocsim_we_libresocsim_next_value2 <= (builder_libresocsim_libresocsim_wishbone_we & (builder_libresocsim_libresocsim_wishbone_sel != 1'd0));
3205                                 builder_libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
3206                                 builder_libresocsim_next_state <= 1'd1;
3207                         end
3208                 end
3209         endcase
3210 end
3211 assign builder_libresocsim_shared_adr = builder_rhs_array_muxed24;
3212 assign builder_libresocsim_shared_dat_w = builder_rhs_array_muxed25;
3213 assign builder_libresocsim_shared_sel = builder_rhs_array_muxed26;
3214 assign builder_libresocsim_shared_cyc = builder_rhs_array_muxed27;
3215 assign builder_libresocsim_shared_stb = builder_rhs_array_muxed28;
3216 assign builder_libresocsim_shared_we = builder_rhs_array_muxed29;
3217 assign builder_libresocsim_shared_cti = builder_rhs_array_muxed30;
3218 assign builder_libresocsim_shared_bte = builder_rhs_array_muxed31;
3219 assign main_libresocsim_interface0_converted_interface_dat_r = builder_libresocsim_shared_dat_r;
3220 assign main_libresocsim_interface1_converted_interface_dat_r = builder_libresocsim_shared_dat_r;
3221 assign main_libresocsim_libresoc_jtag_wb_dat_r = builder_libresocsim_shared_dat_r;
3222 assign main_libresocsim_interface0_converted_interface_ack = (builder_libresocsim_shared_ack & (builder_libresocsim_grant == 1'd0));
3223 assign main_libresocsim_interface1_converted_interface_ack = (builder_libresocsim_shared_ack & (builder_libresocsim_grant == 1'd1));
3224 assign main_libresocsim_libresoc_jtag_wb_ack = (builder_libresocsim_shared_ack & (builder_libresocsim_grant == 2'd2));
3225 assign main_libresocsim_interface0_converted_interface_err = (builder_libresocsim_shared_err & (builder_libresocsim_grant == 1'd0));
3226 assign main_libresocsim_interface1_converted_interface_err = (builder_libresocsim_shared_err & (builder_libresocsim_grant == 1'd1));
3227 assign main_libresocsim_libresoc_jtag_wb_err = (builder_libresocsim_shared_err & (builder_libresocsim_grant == 2'd2));
3228 assign builder_libresocsim_request = {main_libresocsim_libresoc_jtag_wb_cyc, main_libresocsim_interface1_converted_interface_cyc, main_libresocsim_interface0_converted_interface_cyc};
3229 always @(*) begin
3230         builder_libresocsim_slave_sel <= 10'd0;
3231         builder_libresocsim_slave_sel[0] <= (builder_libresocsim_shared_adr[29:5] == 1'd0);
3232         builder_libresocsim_slave_sel[1] <= (builder_libresocsim_shared_adr[29:5] == 4'd14);
3233         builder_libresocsim_slave_sel[2] <= (builder_libresocsim_shared_adr[29:3] == 27'd100665344);
3234         builder_libresocsim_slave_sel[3] <= (builder_libresocsim_shared_adr[29:10] == 20'd786449);
3235         builder_libresocsim_slave_sel[4] <= (builder_libresocsim_shared_adr[29:10] == 1'd1);
3236         builder_libresocsim_slave_sel[5] <= (builder_libresocsim_shared_adr[29:10] == 2'd2);
3237         builder_libresocsim_slave_sel[6] <= (builder_libresocsim_shared_adr[29:10] == 2'd3);
3238         builder_libresocsim_slave_sel[7] <= (builder_libresocsim_shared_adr[29:10] == 3'd4);
3239         builder_libresocsim_slave_sel[8] <= (builder_libresocsim_shared_adr[29:23] == 7'd72);
3240         builder_libresocsim_slave_sel[9] <= (builder_libresocsim_shared_adr[29:13] == 17'd98304);
3241 end
3242 assign main_libresocsim_ram_bus_adr = builder_libresocsim_shared_adr;
3243 assign main_libresocsim_ram_bus_dat_w = builder_libresocsim_shared_dat_w;
3244 assign main_libresocsim_ram_bus_sel = builder_libresocsim_shared_sel;
3245 assign main_libresocsim_ram_bus_stb = builder_libresocsim_shared_stb;
3246 assign main_libresocsim_ram_bus_we = builder_libresocsim_shared_we;
3247 assign main_libresocsim_ram_bus_cti = builder_libresocsim_shared_cti;
3248 assign main_libresocsim_ram_bus_bte = builder_libresocsim_shared_bte;
3249 assign main_ram_bus_ram_bus_adr = builder_libresocsim_shared_adr;
3250 assign main_ram_bus_ram_bus_dat_w = builder_libresocsim_shared_dat_w;
3251 assign main_ram_bus_ram_bus_sel = builder_libresocsim_shared_sel;
3252 assign main_ram_bus_ram_bus_stb = builder_libresocsim_shared_stb;
3253 assign main_ram_bus_ram_bus_we = builder_libresocsim_shared_we;
3254 assign main_ram_bus_ram_bus_cti = builder_libresocsim_shared_cti;
3255 assign main_ram_bus_ram_bus_bte = builder_libresocsim_shared_bte;
3256 assign main_libresocsim_libresoc_xics_icp_adr = builder_libresocsim_shared_adr;
3257 assign main_libresocsim_libresoc_xics_icp_dat_w = builder_libresocsim_shared_dat_w;
3258 assign main_libresocsim_libresoc_xics_icp_sel = builder_libresocsim_shared_sel;
3259 assign main_libresocsim_libresoc_xics_icp_stb = builder_libresocsim_shared_stb;
3260 assign main_libresocsim_libresoc_xics_icp_we = builder_libresocsim_shared_we;
3261 assign main_libresocsim_libresoc_xics_icp_cti = builder_libresocsim_shared_cti;
3262 assign main_libresocsim_libresoc_xics_icp_bte = builder_libresocsim_shared_bte;
3263 assign main_libresocsim_libresoc_xics_ics_adr = builder_libresocsim_shared_adr;
3264 assign main_libresocsim_libresoc_xics_ics_dat_w = builder_libresocsim_shared_dat_w;
3265 assign main_libresocsim_libresoc_xics_ics_sel = builder_libresocsim_shared_sel;
3266 assign main_libresocsim_libresoc_xics_ics_stb = builder_libresocsim_shared_stb;
3267 assign main_libresocsim_libresoc_xics_ics_we = builder_libresocsim_shared_we;
3268 assign main_libresocsim_libresoc_xics_ics_cti = builder_libresocsim_shared_cti;
3269 assign main_libresocsim_libresoc_xics_ics_bte = builder_libresocsim_shared_bte;
3270 assign main_interface0_converted_interface_adr = builder_libresocsim_shared_adr;
3271 assign main_interface0_converted_interface_dat_w = builder_libresocsim_shared_dat_w;
3272 assign main_interface0_converted_interface_sel = builder_libresocsim_shared_sel;
3273 assign main_interface0_converted_interface_stb = builder_libresocsim_shared_stb;
3274 assign main_interface0_converted_interface_we = builder_libresocsim_shared_we;
3275 assign main_interface0_converted_interface_cti = builder_libresocsim_shared_cti;
3276 assign main_interface0_converted_interface_bte = builder_libresocsim_shared_bte;
3277 assign main_interface1_converted_interface_adr = builder_libresocsim_shared_adr;
3278 assign main_interface1_converted_interface_dat_w = builder_libresocsim_shared_dat_w;
3279 assign main_interface1_converted_interface_sel = builder_libresocsim_shared_sel;
3280 assign main_interface1_converted_interface_stb = builder_libresocsim_shared_stb;
3281 assign main_interface1_converted_interface_we = builder_libresocsim_shared_we;
3282 assign main_interface1_converted_interface_cti = builder_libresocsim_shared_cti;
3283 assign main_interface1_converted_interface_bte = builder_libresocsim_shared_bte;
3284 assign main_interface2_converted_interface_adr = builder_libresocsim_shared_adr;
3285 assign main_interface2_converted_interface_dat_w = builder_libresocsim_shared_dat_w;
3286 assign main_interface2_converted_interface_sel = builder_libresocsim_shared_sel;
3287 assign main_interface2_converted_interface_stb = builder_libresocsim_shared_stb;
3288 assign main_interface2_converted_interface_we = builder_libresocsim_shared_we;
3289 assign main_interface2_converted_interface_cti = builder_libresocsim_shared_cti;
3290 assign main_interface2_converted_interface_bte = builder_libresocsim_shared_bte;
3291 assign main_interface3_converted_interface_adr = builder_libresocsim_shared_adr;
3292 assign main_interface3_converted_interface_dat_w = builder_libresocsim_shared_dat_w;
3293 assign main_interface3_converted_interface_sel = builder_libresocsim_shared_sel;
3294 assign main_interface3_converted_interface_stb = builder_libresocsim_shared_stb;
3295 assign main_interface3_converted_interface_we = builder_libresocsim_shared_we;
3296 assign main_interface3_converted_interface_cti = builder_libresocsim_shared_cti;
3297 assign main_interface3_converted_interface_bte = builder_libresocsim_shared_bte;
3298 assign main_wb_sdram_adr = builder_libresocsim_shared_adr;
3299 assign main_wb_sdram_dat_w = builder_libresocsim_shared_dat_w;
3300 assign main_wb_sdram_sel = builder_libresocsim_shared_sel;
3301 assign main_wb_sdram_stb = builder_libresocsim_shared_stb;
3302 assign main_wb_sdram_we = builder_libresocsim_shared_we;
3303 assign main_wb_sdram_cti = builder_libresocsim_shared_cti;
3304 assign main_wb_sdram_bte = builder_libresocsim_shared_bte;
3305 assign builder_libresocsim_libresocsim_wishbone_adr = builder_libresocsim_shared_adr;
3306 assign builder_libresocsim_libresocsim_wishbone_dat_w = builder_libresocsim_shared_dat_w;
3307 assign builder_libresocsim_libresocsim_wishbone_sel = builder_libresocsim_shared_sel;
3308 assign builder_libresocsim_libresocsim_wishbone_stb = builder_libresocsim_shared_stb;
3309 assign builder_libresocsim_libresocsim_wishbone_we = builder_libresocsim_shared_we;
3310 assign builder_libresocsim_libresocsim_wishbone_cti = builder_libresocsim_shared_cti;
3311 assign builder_libresocsim_libresocsim_wishbone_bte = builder_libresocsim_shared_bte;
3312 assign main_libresocsim_ram_bus_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[0]);
3313 assign main_ram_bus_ram_bus_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[1]);
3314 assign main_libresocsim_libresoc_xics_icp_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[2]);
3315 assign main_libresocsim_libresoc_xics_ics_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[3]);
3316 assign main_interface0_converted_interface_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[4]);
3317 assign main_interface1_converted_interface_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[5]);
3318 assign main_interface2_converted_interface_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[6]);
3319 assign main_interface3_converted_interface_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[7]);
3320 assign main_wb_sdram_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[8]);
3321 assign builder_libresocsim_libresocsim_wishbone_cyc = (builder_libresocsim_shared_cyc & builder_libresocsim_slave_sel[9]);
3322 assign builder_libresocsim_shared_err = (((((((((main_libresocsim_ram_bus_err | main_ram_bus_ram_bus_err) | main_libresocsim_libresoc_xics_icp_err) | main_libresocsim_libresoc_xics_ics_err) | main_interface0_converted_interface_err) | main_interface1_converted_interface_err) | main_interface2_converted_interface_err) | main_interface3_converted_interface_err) | main_wb_sdram_err) | builder_libresocsim_libresocsim_wishbone_err);
3323 assign builder_libresocsim_wait = ((builder_libresocsim_shared_stb & builder_libresocsim_shared_cyc) & (~builder_libresocsim_shared_ack));
3324 always @(*) begin
3325         builder_libresocsim_shared_ack <= 1'd0;
3326         builder_libresocsim_error <= 1'd0;
3327         builder_libresocsim_shared_dat_r <= 32'd0;
3328         builder_libresocsim_shared_ack <= (((((((((main_libresocsim_ram_bus_ack | main_ram_bus_ram_bus_ack) | main_libresocsim_libresoc_xics_icp_ack) | main_libresocsim_libresoc_xics_ics_ack) | main_interface0_converted_interface_ack) | main_interface1_converted_interface_ack) | main_interface2_converted_interface_ack) | main_interface3_converted_interface_ack) | main_wb_sdram_ack) | builder_libresocsim_libresocsim_wishbone_ack);
3329         builder_libresocsim_shared_dat_r <= (((((((((({32{builder_libresocsim_slave_sel_r[0]}} & main_libresocsim_ram_bus_dat_r) | ({32{builder_libresocsim_slave_sel_r[1]}} & main_ram_bus_ram_bus_dat_r)) | ({32{builder_libresocsim_slave_sel_r[2]}} & main_libresocsim_libresoc_xics_icp_dat_r)) | ({32{builder_libresocsim_slave_sel_r[3]}} & main_libresocsim_libresoc_xics_ics_dat_r)) | ({32{builder_libresocsim_slave_sel_r[4]}} & main_interface0_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[5]}} & main_interface1_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[6]}} & main_interface2_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[7]}} & main_interface3_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[8]}} & main_wb_sdram_dat_r)) | ({32{builder_libresocsim_slave_sel_r[9]}} & builder_libresocsim_libresocsim_wishbone_dat_r));
3330         if (builder_libresocsim_done) begin
3331                 builder_libresocsim_shared_dat_r <= 32'd4294967295;
3332                 builder_libresocsim_shared_ack <= 1'd1;
3333                 builder_libresocsim_error <= 1'd1;
3334         end
3335 end
3336 assign builder_libresocsim_done = (builder_libresocsim_count == 1'd0);
3337 assign builder_libresocsim_csrbank0_sel = (builder_libresocsim_interface0_bank_bus_adr[12:9] == 1'd0);
3338 assign builder_libresocsim_csrbank0_reset0_r = builder_libresocsim_interface0_bank_bus_dat_w[0];
3339 assign builder_libresocsim_csrbank0_reset0_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3340 assign builder_libresocsim_csrbank0_reset0_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3341 assign builder_libresocsim_csrbank0_scratch3_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3342 assign builder_libresocsim_csrbank0_scratch3_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3343 assign builder_libresocsim_csrbank0_scratch3_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3344 assign builder_libresocsim_csrbank0_scratch2_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3345 assign builder_libresocsim_csrbank0_scratch2_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3346 assign builder_libresocsim_csrbank0_scratch2_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3347 assign builder_libresocsim_csrbank0_scratch1_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3348 assign builder_libresocsim_csrbank0_scratch1_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3349 assign builder_libresocsim_csrbank0_scratch1_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3350 assign builder_libresocsim_csrbank0_scratch0_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3351 assign builder_libresocsim_csrbank0_scratch0_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3352 assign builder_libresocsim_csrbank0_scratch0_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3353 assign builder_libresocsim_csrbank0_bus_errors3_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3354 assign builder_libresocsim_csrbank0_bus_errors3_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3355 assign builder_libresocsim_csrbank0_bus_errors3_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3356 assign builder_libresocsim_csrbank0_bus_errors2_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3357 assign builder_libresocsim_csrbank0_bus_errors2_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3358 assign builder_libresocsim_csrbank0_bus_errors2_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3359 assign builder_libresocsim_csrbank0_bus_errors1_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3360 assign builder_libresocsim_csrbank0_bus_errors1_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3361 assign builder_libresocsim_csrbank0_bus_errors1_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3362 assign builder_libresocsim_csrbank0_bus_errors0_r = builder_libresocsim_interface0_bank_bus_dat_w[7:0];
3363 assign builder_libresocsim_csrbank0_bus_errors0_re = ((builder_libresocsim_csrbank0_sel & builder_libresocsim_interface0_bank_bus_we) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3364 assign builder_libresocsim_csrbank0_bus_errors0_we = ((builder_libresocsim_csrbank0_sel & (~builder_libresocsim_interface0_bank_bus_we)) & (builder_libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3365 assign builder_libresocsim_csrbank0_reset0_w = main_libresocsim_reset_storage;
3366 assign builder_libresocsim_csrbank0_scratch3_w = main_libresocsim_scratch_storage[31:24];
3367 assign builder_libresocsim_csrbank0_scratch2_w = main_libresocsim_scratch_storage[23:16];
3368 assign builder_libresocsim_csrbank0_scratch1_w = main_libresocsim_scratch_storage[15:8];
3369 assign builder_libresocsim_csrbank0_scratch0_w = main_libresocsim_scratch_storage[7:0];
3370 assign builder_libresocsim_csrbank0_bus_errors3_w = main_libresocsim_bus_errors_status[31:24];
3371 assign builder_libresocsim_csrbank0_bus_errors2_w = main_libresocsim_bus_errors_status[23:16];
3372 assign builder_libresocsim_csrbank0_bus_errors1_w = main_libresocsim_bus_errors_status[15:8];
3373 assign builder_libresocsim_csrbank0_bus_errors0_w = main_libresocsim_bus_errors_status[7:0];
3374 assign main_libresocsim_bus_errors_we = builder_libresocsim_csrbank0_bus_errors0_we;
3375 assign builder_libresocsim_csrbank1_sel = (builder_libresocsim_interface1_bank_bus_adr[12:9] == 3'd6);
3376 assign builder_libresocsim_csrbank1_oe0_r = builder_libresocsim_interface1_bank_bus_dat_w[7:0];
3377 assign builder_libresocsim_csrbank1_oe0_re = ((builder_libresocsim_csrbank1_sel & builder_libresocsim_interface1_bank_bus_we) & (builder_libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3378 assign builder_libresocsim_csrbank1_oe0_we = ((builder_libresocsim_csrbank1_sel & (~builder_libresocsim_interface1_bank_bus_we)) & (builder_libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3379 assign builder_libresocsim_csrbank1_in_r = builder_libresocsim_interface1_bank_bus_dat_w[7:0];
3380 assign builder_libresocsim_csrbank1_in_re = ((builder_libresocsim_csrbank1_sel & builder_libresocsim_interface1_bank_bus_we) & (builder_libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3381 assign builder_libresocsim_csrbank1_in_we = ((builder_libresocsim_csrbank1_sel & (~builder_libresocsim_interface1_bank_bus_we)) & (builder_libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3382 assign builder_libresocsim_csrbank1_out0_r = builder_libresocsim_interface1_bank_bus_dat_w[7:0];
3383 assign builder_libresocsim_csrbank1_out0_re = ((builder_libresocsim_csrbank1_sel & builder_libresocsim_interface1_bank_bus_we) & (builder_libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3384 assign builder_libresocsim_csrbank1_out0_we = ((builder_libresocsim_csrbank1_sel & (~builder_libresocsim_interface1_bank_bus_we)) & (builder_libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3385 assign builder_libresocsim_csrbank1_oe0_w = main_gpio0_oe_storage[7:0];
3386 assign builder_libresocsim_csrbank1_in_w = main_gpio0_status[7:0];
3387 assign main_gpio0_we = builder_libresocsim_csrbank1_in_we;
3388 assign builder_libresocsim_csrbank1_out0_w = main_gpio0_out_storage[7:0];
3389 assign builder_libresocsim_csrbank2_sel = (builder_libresocsim_interface2_bank_bus_adr[12:9] == 3'd7);
3390 assign builder_libresocsim_csrbank2_oe0_r = builder_libresocsim_interface2_bank_bus_dat_w[7:0];
3391 assign builder_libresocsim_csrbank2_oe0_re = ((builder_libresocsim_csrbank2_sel & builder_libresocsim_interface2_bank_bus_we) & (builder_libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3392 assign builder_libresocsim_csrbank2_oe0_we = ((builder_libresocsim_csrbank2_sel & (~builder_libresocsim_interface2_bank_bus_we)) & (builder_libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3393 assign builder_libresocsim_csrbank2_in_r = builder_libresocsim_interface2_bank_bus_dat_w[7:0];
3394 assign builder_libresocsim_csrbank2_in_re = ((builder_libresocsim_csrbank2_sel & builder_libresocsim_interface2_bank_bus_we) & (builder_libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3395 assign builder_libresocsim_csrbank2_in_we = ((builder_libresocsim_csrbank2_sel & (~builder_libresocsim_interface2_bank_bus_we)) & (builder_libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3396 assign builder_libresocsim_csrbank2_out0_r = builder_libresocsim_interface2_bank_bus_dat_w[7:0];
3397 assign builder_libresocsim_csrbank2_out0_re = ((builder_libresocsim_csrbank2_sel & builder_libresocsim_interface2_bank_bus_we) & (builder_libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3398 assign builder_libresocsim_csrbank2_out0_we = ((builder_libresocsim_csrbank2_sel & (~builder_libresocsim_interface2_bank_bus_we)) & (builder_libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3399 assign builder_libresocsim_csrbank2_oe0_w = main_gpio1_oe_storage[7:0];
3400 assign builder_libresocsim_csrbank2_in_w = main_gpio1_status[7:0];
3401 assign main_gpio1_we = builder_libresocsim_csrbank2_in_we;
3402 assign builder_libresocsim_csrbank2_out0_w = main_gpio1_out_storage[7:0];
3403 assign builder_libresocsim_csrbank3_sel = (builder_libresocsim_interface3_bank_bus_adr[12:9] == 4'd8);
3404 assign builder_libresocsim_csrbank3_w0_r = builder_libresocsim_interface3_bank_bus_dat_w[2:0];
3405 assign builder_libresocsim_csrbank3_w0_re = ((builder_libresocsim_csrbank3_sel & builder_libresocsim_interface3_bank_bus_we) & (builder_libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3406 assign builder_libresocsim_csrbank3_w0_we = ((builder_libresocsim_csrbank3_sel & (~builder_libresocsim_interface3_bank_bus_we)) & (builder_libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3407 assign builder_libresocsim_csrbank3_r_r = builder_libresocsim_interface3_bank_bus_dat_w[0];
3408 assign builder_libresocsim_csrbank3_r_re = ((builder_libresocsim_csrbank3_sel & builder_libresocsim_interface3_bank_bus_we) & (builder_libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3409 assign builder_libresocsim_csrbank3_r_we = ((builder_libresocsim_csrbank3_sel & (~builder_libresocsim_interface3_bank_bus_we)) & (builder_libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3410 assign main_i2c_scl = main_i2c_storage[0];
3411 assign main_i2c_oe = main_i2c_storage[1];
3412 assign main_i2c_sda0 = main_i2c_storage[2];
3413 assign builder_libresocsim_csrbank3_w0_w = main_i2c_storage[2:0];
3414 assign main_i2c_status = main_i2c_sda1;
3415 assign builder_libresocsim_csrbank3_r_w = main_i2c_status;
3416 assign main_i2c_we = builder_libresocsim_csrbank3_r_we;
3417 assign builder_libresocsim_csrbank4_sel = (builder_libresocsim_interface4_bank_bus_adr[12:9] == 2'd3);
3418 assign builder_libresocsim_csrbank4_dfii_control0_r = builder_libresocsim_interface4_bank_bus_dat_w[3:0];
3419 assign builder_libresocsim_csrbank4_dfii_control0_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3420 assign builder_libresocsim_csrbank4_dfii_control0_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3421 assign builder_libresocsim_csrbank4_dfii_pi0_command0_r = builder_libresocsim_interface4_bank_bus_dat_w[5:0];
3422 assign builder_libresocsim_csrbank4_dfii_pi0_command0_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3423 assign builder_libresocsim_csrbank4_dfii_pi0_command0_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3424 assign main_sdram_command_issue_r = builder_libresocsim_interface4_bank_bus_dat_w[0];
3425 assign main_sdram_command_issue_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3426 assign main_sdram_command_issue_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3427 assign builder_libresocsim_csrbank4_dfii_pi0_address1_r = builder_libresocsim_interface4_bank_bus_dat_w[4:0];
3428 assign builder_libresocsim_csrbank4_dfii_pi0_address1_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3429 assign builder_libresocsim_csrbank4_dfii_pi0_address1_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3430 assign builder_libresocsim_csrbank4_dfii_pi0_address0_r = builder_libresocsim_interface4_bank_bus_dat_w[7:0];
3431 assign builder_libresocsim_csrbank4_dfii_pi0_address0_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3432 assign builder_libresocsim_csrbank4_dfii_pi0_address0_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3433 assign builder_libresocsim_csrbank4_dfii_pi0_baddress0_r = builder_libresocsim_interface4_bank_bus_dat_w[1:0];
3434 assign builder_libresocsim_csrbank4_dfii_pi0_baddress0_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3435 assign builder_libresocsim_csrbank4_dfii_pi0_baddress0_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3436 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata1_r = builder_libresocsim_interface4_bank_bus_dat_w[7:0];
3437 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata1_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3438 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata1_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3439 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata0_r = builder_libresocsim_interface4_bank_bus_dat_w[7:0];
3440 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata0_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3441 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata0_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3442 assign builder_libresocsim_csrbank4_dfii_pi0_rddata1_r = builder_libresocsim_interface4_bank_bus_dat_w[7:0];
3443 assign builder_libresocsim_csrbank4_dfii_pi0_rddata1_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3444 assign builder_libresocsim_csrbank4_dfii_pi0_rddata1_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3445 assign builder_libresocsim_csrbank4_dfii_pi0_rddata0_r = builder_libresocsim_interface4_bank_bus_dat_w[7:0];
3446 assign builder_libresocsim_csrbank4_dfii_pi0_rddata0_re = ((builder_libresocsim_csrbank4_sel & builder_libresocsim_interface4_bank_bus_we) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3447 assign builder_libresocsim_csrbank4_dfii_pi0_rddata0_we = ((builder_libresocsim_csrbank4_sel & (~builder_libresocsim_interface4_bank_bus_we)) & (builder_libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3448 assign main_sdram_sel = main_sdram_storage[0];
3449 assign main_sdram_cke = main_sdram_storage[1];
3450 assign main_sdram_odt = main_sdram_storage[2];
3451 assign main_sdram_reset_n = main_sdram_storage[3];
3452 assign builder_libresocsim_csrbank4_dfii_control0_w = main_sdram_storage[3:0];
3453 assign builder_libresocsim_csrbank4_dfii_pi0_command0_w = main_sdram_command_storage[5:0];
3454 assign builder_libresocsim_csrbank4_dfii_pi0_address1_w = main_sdram_address_storage[12:8];
3455 assign builder_libresocsim_csrbank4_dfii_pi0_address0_w = main_sdram_address_storage[7:0];
3456 assign builder_libresocsim_csrbank4_dfii_pi0_baddress0_w = main_sdram_baddress_storage[1:0];
3457 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata1_w = main_sdram_wrdata_storage[15:8];
3458 assign builder_libresocsim_csrbank4_dfii_pi0_wrdata0_w = main_sdram_wrdata_storage[7:0];
3459 assign builder_libresocsim_csrbank4_dfii_pi0_rddata1_w = main_sdram_status[15:8];
3460 assign builder_libresocsim_csrbank4_dfii_pi0_rddata0_w = main_sdram_status[7:0];
3461 assign main_sdram_we = builder_libresocsim_csrbank4_dfii_pi0_rddata0_we;
3462 assign builder_libresocsim_csrbank5_sel = (builder_libresocsim_interface5_bank_bus_adr[12:9] == 2'd2);
3463 assign builder_libresocsim_csrbank5_load3_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3464 assign builder_libresocsim_csrbank5_load3_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3465 assign builder_libresocsim_csrbank5_load3_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3466 assign builder_libresocsim_csrbank5_load2_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3467 assign builder_libresocsim_csrbank5_load2_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3468 assign builder_libresocsim_csrbank5_load2_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3469 assign builder_libresocsim_csrbank5_load1_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3470 assign builder_libresocsim_csrbank5_load1_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3471 assign builder_libresocsim_csrbank5_load1_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3472 assign builder_libresocsim_csrbank5_load0_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3473 assign builder_libresocsim_csrbank5_load0_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3474 assign builder_libresocsim_csrbank5_load0_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3475 assign builder_libresocsim_csrbank5_reload3_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3476 assign builder_libresocsim_csrbank5_reload3_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3477 assign builder_libresocsim_csrbank5_reload3_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3478 assign builder_libresocsim_csrbank5_reload2_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3479 assign builder_libresocsim_csrbank5_reload2_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3480 assign builder_libresocsim_csrbank5_reload2_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3481 assign builder_libresocsim_csrbank5_reload1_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3482 assign builder_libresocsim_csrbank5_reload1_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3483 assign builder_libresocsim_csrbank5_reload1_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3484 assign builder_libresocsim_csrbank5_reload0_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3485 assign builder_libresocsim_csrbank5_reload0_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3486 assign builder_libresocsim_csrbank5_reload0_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3487 assign builder_libresocsim_csrbank5_en0_r = builder_libresocsim_interface5_bank_bus_dat_w[0];
3488 assign builder_libresocsim_csrbank5_en0_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3489 assign builder_libresocsim_csrbank5_en0_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3490 assign builder_libresocsim_csrbank5_update_value0_r = builder_libresocsim_interface5_bank_bus_dat_w[0];
3491 assign builder_libresocsim_csrbank5_update_value0_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3492 assign builder_libresocsim_csrbank5_update_value0_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3493 assign builder_libresocsim_csrbank5_value3_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3494 assign builder_libresocsim_csrbank5_value3_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3495 assign builder_libresocsim_csrbank5_value3_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3496 assign builder_libresocsim_csrbank5_value2_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3497 assign builder_libresocsim_csrbank5_value2_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3498 assign builder_libresocsim_csrbank5_value2_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3499 assign builder_libresocsim_csrbank5_value1_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3500 assign builder_libresocsim_csrbank5_value1_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3501 assign builder_libresocsim_csrbank5_value1_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3502 assign builder_libresocsim_csrbank5_value0_r = builder_libresocsim_interface5_bank_bus_dat_w[7:0];
3503 assign builder_libresocsim_csrbank5_value0_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3504 assign builder_libresocsim_csrbank5_value0_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3505 assign main_libresocsim_eventmanager_status_r = builder_libresocsim_interface5_bank_bus_dat_w[0];
3506 assign main_libresocsim_eventmanager_status_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3507 assign main_libresocsim_eventmanager_status_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3508 assign main_libresocsim_eventmanager_pending_r = builder_libresocsim_interface5_bank_bus_dat_w[0];
3509 assign main_libresocsim_eventmanager_pending_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3510 assign main_libresocsim_eventmanager_pending_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3511 assign builder_libresocsim_csrbank5_ev_enable0_r = builder_libresocsim_interface5_bank_bus_dat_w[0];
3512 assign builder_libresocsim_csrbank5_ev_enable0_re = ((builder_libresocsim_csrbank5_sel & builder_libresocsim_interface5_bank_bus_we) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3513 assign builder_libresocsim_csrbank5_ev_enable0_we = ((builder_libresocsim_csrbank5_sel & (~builder_libresocsim_interface5_bank_bus_we)) & (builder_libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3514 assign builder_libresocsim_csrbank5_load3_w = main_libresocsim_load_storage[31:24];
3515 assign builder_libresocsim_csrbank5_load2_w = main_libresocsim_load_storage[23:16];
3516 assign builder_libresocsim_csrbank5_load1_w = main_libresocsim_load_storage[15:8];
3517 assign builder_libresocsim_csrbank5_load0_w = main_libresocsim_load_storage[7:0];
3518 assign builder_libresocsim_csrbank5_reload3_w = main_libresocsim_reload_storage[31:24];
3519 assign builder_libresocsim_csrbank5_reload2_w = main_libresocsim_reload_storage[23:16];
3520 assign builder_libresocsim_csrbank5_reload1_w = main_libresocsim_reload_storage[15:8];
3521 assign builder_libresocsim_csrbank5_reload0_w = main_libresocsim_reload_storage[7:0];
3522 assign builder_libresocsim_csrbank5_en0_w = main_libresocsim_en_storage;
3523 assign builder_libresocsim_csrbank5_update_value0_w = main_libresocsim_update_value_storage;
3524 assign builder_libresocsim_csrbank5_value3_w = main_libresocsim_value_status[31:24];
3525 assign builder_libresocsim_csrbank5_value2_w = main_libresocsim_value_status[23:16];
3526 assign builder_libresocsim_csrbank5_value1_w = main_libresocsim_value_status[15:8];
3527 assign builder_libresocsim_csrbank5_value0_w = main_libresocsim_value_status[7:0];
3528 assign main_libresocsim_value_we = builder_libresocsim_csrbank5_value0_we;
3529 assign builder_libresocsim_csrbank5_ev_enable0_w = main_libresocsim_eventmanager_storage;
3530 assign builder_libresocsim_csrbank6_sel = (builder_libresocsim_interface6_bank_bus_adr[12:9] == 3'd5);
3531 assign main_rxtx_r = builder_libresocsim_interface6_bank_bus_dat_w[7:0];
3532 assign main_rxtx_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3533 assign main_rxtx_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3534 assign builder_libresocsim_csrbank6_txfull_r = builder_libresocsim_interface6_bank_bus_dat_w[0];
3535 assign builder_libresocsim_csrbank6_txfull_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3536 assign builder_libresocsim_csrbank6_txfull_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3537 assign builder_libresocsim_csrbank6_rxempty_r = builder_libresocsim_interface6_bank_bus_dat_w[0];
3538 assign builder_libresocsim_csrbank6_rxempty_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3539 assign builder_libresocsim_csrbank6_rxempty_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3540 assign main_eventmanager_status_r = builder_libresocsim_interface6_bank_bus_dat_w[1:0];
3541 assign main_eventmanager_status_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3542 assign main_eventmanager_status_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3543 assign main_eventmanager_pending_r = builder_libresocsim_interface6_bank_bus_dat_w[1:0];
3544 assign main_eventmanager_pending_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3545 assign main_eventmanager_pending_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3546 assign builder_libresocsim_csrbank6_ev_enable0_r = builder_libresocsim_interface6_bank_bus_dat_w[1:0];
3547 assign builder_libresocsim_csrbank6_ev_enable0_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3548 assign builder_libresocsim_csrbank6_ev_enable0_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3549 assign builder_libresocsim_csrbank6_txempty_r = builder_libresocsim_interface6_bank_bus_dat_w[0];
3550 assign builder_libresocsim_csrbank6_txempty_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3551 assign builder_libresocsim_csrbank6_txempty_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3552 assign builder_libresocsim_csrbank6_rxfull_r = builder_libresocsim_interface6_bank_bus_dat_w[0];
3553 assign builder_libresocsim_csrbank6_rxfull_re = ((builder_libresocsim_csrbank6_sel & builder_libresocsim_interface6_bank_bus_we) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3554 assign builder_libresocsim_csrbank6_rxfull_we = ((builder_libresocsim_csrbank6_sel & (~builder_libresocsim_interface6_bank_bus_we)) & (builder_libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3555 assign builder_libresocsim_csrbank6_txfull_w = main_txfull_status;
3556 assign main_txfull_we = builder_libresocsim_csrbank6_txfull_we;
3557 assign builder_libresocsim_csrbank6_rxempty_w = main_rxempty_status;
3558 assign main_rxempty_we = builder_libresocsim_csrbank6_rxempty_we;
3559 assign builder_libresocsim_csrbank6_ev_enable0_w = main_eventmanager_storage[1:0];
3560 assign builder_libresocsim_csrbank6_txempty_w = main_txempty_status;
3561 assign main_txempty_we = builder_libresocsim_csrbank6_txempty_we;
3562 assign builder_libresocsim_csrbank6_rxfull_w = main_rxfull_status;
3563 assign main_rxfull_we = builder_libresocsim_csrbank6_rxfull_we;
3564 assign builder_libresocsim_csrbank7_sel = (builder_libresocsim_interface7_bank_bus_adr[12:9] == 3'd4);
3565 assign builder_libresocsim_csrbank7_tuning_word3_r = builder_libresocsim_interface7_bank_bus_dat_w[7:0];
3566 assign builder_libresocsim_csrbank7_tuning_word3_re = ((builder_libresocsim_csrbank7_sel & builder_libresocsim_interface7_bank_bus_we) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3567 assign builder_libresocsim_csrbank7_tuning_word3_we = ((builder_libresocsim_csrbank7_sel & (~builder_libresocsim_interface7_bank_bus_we)) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3568 assign builder_libresocsim_csrbank7_tuning_word2_r = builder_libresocsim_interface7_bank_bus_dat_w[7:0];
3569 assign builder_libresocsim_csrbank7_tuning_word2_re = ((builder_libresocsim_csrbank7_sel & builder_libresocsim_interface7_bank_bus_we) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3570 assign builder_libresocsim_csrbank7_tuning_word2_we = ((builder_libresocsim_csrbank7_sel & (~builder_libresocsim_interface7_bank_bus_we)) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3571 assign builder_libresocsim_csrbank7_tuning_word1_r = builder_libresocsim_interface7_bank_bus_dat_w[7:0];
3572 assign builder_libresocsim_csrbank7_tuning_word1_re = ((builder_libresocsim_csrbank7_sel & builder_libresocsim_interface7_bank_bus_we) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3573 assign builder_libresocsim_csrbank7_tuning_word1_we = ((builder_libresocsim_csrbank7_sel & (~builder_libresocsim_interface7_bank_bus_we)) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3574 assign builder_libresocsim_csrbank7_tuning_word0_r = builder_libresocsim_interface7_bank_bus_dat_w[7:0];
3575 assign builder_libresocsim_csrbank7_tuning_word0_re = ((builder_libresocsim_csrbank7_sel & builder_libresocsim_interface7_bank_bus_we) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3576 assign builder_libresocsim_csrbank7_tuning_word0_we = ((builder_libresocsim_csrbank7_sel & (~builder_libresocsim_interface7_bank_bus_we)) & (builder_libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3577 assign builder_libresocsim_csrbank7_tuning_word3_w = main_uart_phy_storage[31:24];
3578 assign builder_libresocsim_csrbank7_tuning_word2_w = main_uart_phy_storage[23:16];
3579 assign builder_libresocsim_csrbank7_tuning_word1_w = main_uart_phy_storage[15:8];
3580 assign builder_libresocsim_csrbank7_tuning_word0_w = main_uart_phy_storage[7:0];
3581 assign builder_libresocsim_csr_interconnect_adr = builder_libresocsim_libresocsim_adr;
3582 assign builder_libresocsim_csr_interconnect_we = builder_libresocsim_libresocsim_we;
3583 assign builder_libresocsim_csr_interconnect_dat_w = builder_libresocsim_libresocsim_dat_w;
3584 assign builder_libresocsim_libresocsim_dat_r = builder_libresocsim_csr_interconnect_dat_r;
3585 assign builder_libresocsim_interface0_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3586 assign builder_libresocsim_interface1_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3587 assign builder_libresocsim_interface2_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3588 assign builder_libresocsim_interface3_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3589 assign builder_libresocsim_interface4_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3590 assign builder_libresocsim_interface5_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3591 assign builder_libresocsim_interface6_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3592 assign builder_libresocsim_interface7_bank_bus_adr = builder_libresocsim_csr_interconnect_adr;
3593 assign builder_libresocsim_interface0_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3594 assign builder_libresocsim_interface1_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3595 assign builder_libresocsim_interface2_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3596 assign builder_libresocsim_interface3_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3597 assign builder_libresocsim_interface4_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3598 assign builder_libresocsim_interface5_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3599 assign builder_libresocsim_interface6_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3600 assign builder_libresocsim_interface7_bank_bus_we = builder_libresocsim_csr_interconnect_we;
3601 assign builder_libresocsim_interface0_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3602 assign builder_libresocsim_interface1_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3603 assign builder_libresocsim_interface2_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3604 assign builder_libresocsim_interface3_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3605 assign builder_libresocsim_interface4_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3606 assign builder_libresocsim_interface5_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3607 assign builder_libresocsim_interface6_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3608 assign builder_libresocsim_interface7_bank_bus_dat_w = builder_libresocsim_csr_interconnect_dat_w;
3609 assign builder_libresocsim_csr_interconnect_dat_r = (((((((builder_libresocsim_interface0_bank_bus_dat_r | builder_libresocsim_interface1_bank_bus_dat_r) | builder_libresocsim_interface2_bank_bus_dat_r) | builder_libresocsim_interface3_bank_bus_dat_r) | builder_libresocsim_interface4_bank_bus_dat_r) | builder_libresocsim_interface5_bank_bus_dat_r) | builder_libresocsim_interface6_bank_bus_dat_r) | builder_libresocsim_interface7_bank_bus_dat_r);
3610 always @(*) begin
3611         builder_rhs_array_muxed0 <= 1'd0;
3612         case (main_sdram_choose_cmd_grant)
3613                 1'd0: begin
3614                         builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[0];
3615                 end
3616                 1'd1: begin
3617                         builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[1];
3618                 end
3619                 2'd2: begin
3620                         builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[2];
3621                 end
3622                 default: begin
3623                         builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[3];
3624                 end
3625         endcase
3626 end
3627 always @(*) begin
3628         builder_rhs_array_muxed1 <= 13'd0;
3629         case (main_sdram_choose_cmd_grant)
3630                 1'd0: begin
3631                         builder_rhs_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_a;
3632                 end
3633                 1'd1: begin
3634                         builder_rhs_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_a;
3635                 end
3636                 2'd2: begin
3637                         builder_rhs_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_a;
3638                 end
3639                 default: begin
3640                         builder_rhs_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_a;
3641                 end
3642         endcase
3643 end
3644 always @(*) begin
3645         builder_rhs_array_muxed2 <= 2'd0;
3646         case (main_sdram_choose_cmd_grant)
3647                 1'd0: begin
3648                         builder_rhs_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_ba;
3649                 end
3650                 1'd1: begin
3651                         builder_rhs_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_ba;
3652                 end
3653                 2'd2: begin
3654                         builder_rhs_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_ba;
3655                 end
3656                 default: begin
3657                         builder_rhs_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_ba;
3658                 end
3659         endcase
3660 end
3661 always @(*) begin
3662         builder_rhs_array_muxed3 <= 1'd0;
3663         case (main_sdram_choose_cmd_grant)
3664                 1'd0: begin
3665                         builder_rhs_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_is_read;
3666                 end
3667                 1'd1: begin
3668                         builder_rhs_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_is_read;
3669                 end
3670                 2'd2: begin
3671                         builder_rhs_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_is_read;
3672                 end
3673                 default: begin
3674                         builder_rhs_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_is_read;
3675                 end
3676         endcase
3677 end
3678 always @(*) begin
3679         builder_rhs_array_muxed4 <= 1'd0;
3680         case (main_sdram_choose_cmd_grant)
3681                 1'd0: begin
3682                         builder_rhs_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_is_write;
3683                 end
3684                 1'd1: begin
3685                         builder_rhs_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_is_write;
3686                 end
3687                 2'd2: begin
3688                         builder_rhs_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_is_write;
3689                 end
3690                 default: begin
3691                         builder_rhs_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_is_write;
3692                 end
3693         endcase
3694 end
3695 always @(*) begin
3696         builder_rhs_array_muxed5 <= 1'd0;
3697         case (main_sdram_choose_cmd_grant)
3698                 1'd0: begin
3699                         builder_rhs_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_is_cmd;
3700                 end
3701                 1'd1: begin
3702                         builder_rhs_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_is_cmd;
3703                 end
3704                 2'd2: begin
3705                         builder_rhs_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_is_cmd;
3706                 end
3707                 default: begin
3708                         builder_rhs_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_is_cmd;
3709                 end
3710         endcase
3711 end
3712 always @(*) begin
3713         builder_t_array_muxed0 <= 1'd0;
3714         case (main_sdram_choose_cmd_grant)
3715                 1'd0: begin
3716                         builder_t_array_muxed0 <= main_sdram_bankmachine0_cmd_payload_cas;
3717                 end
3718                 1'd1: begin
3719                         builder_t_array_muxed0 <= main_sdram_bankmachine1_cmd_payload_cas;
3720                 end
3721                 2'd2: begin
3722                         builder_t_array_muxed0 <= main_sdram_bankmachine2_cmd_payload_cas;
3723                 end
3724                 default: begin
3725                         builder_t_array_muxed0 <= main_sdram_bankmachine3_cmd_payload_cas;
3726                 end
3727         endcase
3728 end
3729 always @(*) begin
3730         builder_t_array_muxed1 <= 1'd0;
3731         case (main_sdram_choose_cmd_grant)
3732                 1'd0: begin
3733                         builder_t_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_ras;
3734                 end
3735                 1'd1: begin
3736                         builder_t_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_ras;
3737                 end
3738                 2'd2: begin
3739                         builder_t_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_ras;
3740                 end
3741                 default: begin
3742                         builder_t_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_ras;
3743                 end
3744         endcase
3745 end
3746 always @(*) begin
3747         builder_t_array_muxed2 <= 1'd0;
3748         case (main_sdram_choose_cmd_grant)
3749                 1'd0: begin
3750                         builder_t_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_we;
3751                 end
3752                 1'd1: begin
3753                         builder_t_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_we;
3754                 end
3755                 2'd2: begin
3756                         builder_t_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_we;
3757                 end
3758                 default: begin
3759                         builder_t_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_we;
3760                 end
3761         endcase
3762 end
3763 always @(*) begin
3764         builder_rhs_array_muxed6 <= 1'd0;
3765         case (main_sdram_choose_req_grant)
3766                 1'd0: begin
3767                         builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[0];
3768                 end
3769                 1'd1: begin
3770                         builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[1];
3771                 end
3772                 2'd2: begin
3773                         builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[2];
3774                 end
3775                 default: begin
3776                         builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[3];
3777                 end
3778         endcase
3779 end
3780 always @(*) begin
3781         builder_rhs_array_muxed7 <= 13'd0;
3782         case (main_sdram_choose_req_grant)
3783                 1'd0: begin
3784                         builder_rhs_array_muxed7 <= main_sdram_bankmachine0_cmd_payload_a;
3785                 end
3786                 1'd1: begin
3787                         builder_rhs_array_muxed7 <= main_sdram_bankmachine1_cmd_payload_a;
3788                 end
3789                 2'd2: begin
3790                         builder_rhs_array_muxed7 <= main_sdram_bankmachine2_cmd_payload_a;
3791                 end
3792                 default: begin
3793                         builder_rhs_array_muxed7 <= main_sdram_bankmachine3_cmd_payload_a;
3794                 end
3795         endcase
3796 end
3797 always @(*) begin
3798         builder_rhs_array_muxed8 <= 2'd0;
3799         case (main_sdram_choose_req_grant)
3800                 1'd0: begin
3801                         builder_rhs_array_muxed8 <= main_sdram_bankmachine0_cmd_payload_ba;
3802                 end
3803                 1'd1: begin
3804                         builder_rhs_array_muxed8 <= main_sdram_bankmachine1_cmd_payload_ba;
3805                 end
3806                 2'd2: begin
3807                         builder_rhs_array_muxed8 <= main_sdram_bankmachine2_cmd_payload_ba;
3808                 end
3809                 default: begin
3810                         builder_rhs_array_muxed8 <= main_sdram_bankmachine3_cmd_payload_ba;
3811                 end
3812         endcase
3813 end
3814 always @(*) begin
3815         builder_rhs_array_muxed9 <= 1'd0;
3816         case (main_sdram_choose_req_grant)
3817                 1'd0: begin
3818                         builder_rhs_array_muxed9 <= main_sdram_bankmachine0_cmd_payload_is_read;
3819                 end
3820                 1'd1: begin
3821                         builder_rhs_array_muxed9 <= main_sdram_bankmachine1_cmd_payload_is_read;
3822                 end
3823                 2'd2: begin
3824                         builder_rhs_array_muxed9 <= main_sdram_bankmachine2_cmd_payload_is_read;
3825                 end
3826                 default: begin
3827                         builder_rhs_array_muxed9 <= main_sdram_bankmachine3_cmd_payload_is_read;
3828                 end
3829         endcase
3830 end
3831 always @(*) begin
3832         builder_rhs_array_muxed10 <= 1'd0;
3833         case (main_sdram_choose_req_grant)
3834                 1'd0: begin
3835                         builder_rhs_array_muxed10 <= main_sdram_bankmachine0_cmd_payload_is_write;
3836                 end
3837                 1'd1: begin
3838                         builder_rhs_array_muxed10 <= main_sdram_bankmachine1_cmd_payload_is_write;
3839                 end
3840                 2'd2: begin
3841                         builder_rhs_array_muxed10 <= main_sdram_bankmachine2_cmd_payload_is_write;
3842                 end
3843                 default: begin
3844                         builder_rhs_array_muxed10 <= main_sdram_bankmachine3_cmd_payload_is_write;
3845                 end
3846         endcase
3847 end
3848 always @(*) begin
3849         builder_rhs_array_muxed11 <= 1'd0;
3850         case (main_sdram_choose_req_grant)
3851                 1'd0: begin
3852                         builder_rhs_array_muxed11 <= main_sdram_bankmachine0_cmd_payload_is_cmd;
3853                 end
3854                 1'd1: begin
3855                         builder_rhs_array_muxed11 <= main_sdram_bankmachine1_cmd_payload_is_cmd;
3856                 end
3857                 2'd2: begin
3858                         builder_rhs_array_muxed11 <= main_sdram_bankmachine2_cmd_payload_is_cmd;
3859                 end
3860                 default: begin
3861                         builder_rhs_array_muxed11 <= main_sdram_bankmachine3_cmd_payload_is_cmd;
3862                 end
3863         endcase
3864 end
3865 always @(*) begin
3866         builder_t_array_muxed3 <= 1'd0;
3867         case (main_sdram_choose_req_grant)
3868                 1'd0: begin
3869                         builder_t_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_cas;
3870                 end
3871                 1'd1: begin
3872                         builder_t_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_cas;
3873                 end
3874                 2'd2: begin
3875                         builder_t_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_cas;
3876                 end
3877                 default: begin
3878                         builder_t_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_cas;
3879                 end
3880         endcase
3881 end
3882 always @(*) begin
3883         builder_t_array_muxed4 <= 1'd0;
3884         case (main_sdram_choose_req_grant)
3885                 1'd0: begin
3886                         builder_t_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_ras;
3887                 end
3888                 1'd1: begin
3889                         builder_t_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_ras;
3890                 end
3891                 2'd2: begin
3892                         builder_t_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_ras;
3893                 end
3894                 default: begin
3895                         builder_t_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_ras;
3896                 end
3897         endcase
3898 end
3899 always @(*) begin
3900         builder_t_array_muxed5 <= 1'd0;
3901         case (main_sdram_choose_req_grant)
3902                 1'd0: begin
3903                         builder_t_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_we;
3904                 end
3905                 1'd1: begin
3906                         builder_t_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_we;
3907                 end
3908                 2'd2: begin
3909                         builder_t_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_we;
3910                 end
3911                 default: begin
3912                         builder_t_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_we;
3913                 end
3914         endcase
3915 end
3916 always @(*) begin
3917         builder_rhs_array_muxed12 <= 22'd0;
3918         case (builder_subfragments_roundrobin0_grant)
3919                 default: begin
3920                         builder_rhs_array_muxed12 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};
3921                 end
3922         endcase
3923 end
3924 always @(*) begin
3925         builder_rhs_array_muxed13 <= 1'd0;
3926         case (builder_subfragments_roundrobin0_grant)
3927                 default: begin
3928                         builder_rhs_array_muxed13 <= main_port_cmd_payload_we;
3929                 end
3930         endcase
3931 end
3932 always @(*) begin
3933         builder_rhs_array_muxed14 <= 1'd0;
3934         case (builder_subfragments_roundrobin0_grant)
3935                 default: begin
3936                         builder_rhs_array_muxed14 <= (((main_port_cmd_payload_addr[10:9] == 1'd0) & (~(((builder_subfragments_locked0 | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid);
3937                 end
3938         endcase
3939 end
3940 always @(*) begin
3941         builder_rhs_array_muxed15 <= 22'd0;
3942         case (builder_subfragments_roundrobin1_grant)
3943                 default: begin
3944                         builder_rhs_array_muxed15 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};
3945                 end
3946         endcase
3947 end
3948 always @(*) begin
3949         builder_rhs_array_muxed16 <= 1'd0;
3950         case (builder_subfragments_roundrobin1_grant)
3951                 default: begin
3952                         builder_rhs_array_muxed16 <= main_port_cmd_payload_we;
3953                 end
3954         endcase
3955 end
3956 always @(*) begin
3957         builder_rhs_array_muxed17 <= 1'd0;
3958         case (builder_subfragments_roundrobin1_grant)
3959                 default: begin
3960                         builder_rhs_array_muxed17 <= (((main_port_cmd_payload_addr[10:9] == 1'd1) & (~(((builder_subfragments_locked1 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid);
3961                 end
3962         endcase
3963 end
3964 always @(*) begin
3965         builder_rhs_array_muxed18 <= 22'd0;
3966         case (builder_subfragments_roundrobin2_grant)
3967                 default: begin
3968                         builder_rhs_array_muxed18 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};
3969                 end
3970         endcase
3971 end
3972 always @(*) begin
3973         builder_rhs_array_muxed19 <= 1'd0;
3974         case (builder_subfragments_roundrobin2_grant)
3975                 default: begin
3976                         builder_rhs_array_muxed19 <= main_port_cmd_payload_we;
3977                 end
3978         endcase
3979 end
3980 always @(*) begin
3981         builder_rhs_array_muxed20 <= 1'd0;
3982         case (builder_subfragments_roundrobin2_grant)
3983                 default: begin
3984                         builder_rhs_array_muxed20 <= (((main_port_cmd_payload_addr[10:9] == 2'd2) & (~(((builder_subfragments_locked2 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_subfragments_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid);
3985                 end
3986         endcase
3987 end
3988 always @(*) begin
3989         builder_rhs_array_muxed21 <= 22'd0;
3990         case (builder_subfragments_roundrobin3_grant)
3991                 default: begin
3992                         builder_rhs_array_muxed21 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};
3993                 end
3994         endcase
3995 end
3996 always @(*) begin
3997         builder_rhs_array_muxed22 <= 1'd0;
3998         case (builder_subfragments_roundrobin3_grant)
3999                 default: begin
4000                         builder_rhs_array_muxed22 <= main_port_cmd_payload_we;
4001                 end
4002         endcase
4003 end
4004 always @(*) begin
4005         builder_rhs_array_muxed23 <= 1'd0;
4006         case (builder_subfragments_roundrobin3_grant)
4007                 default: begin
4008                         builder_rhs_array_muxed23 <= (((main_port_cmd_payload_addr[10:9] == 2'd3) & (~(((builder_subfragments_locked3 | (main_sdram_interface_bank0_lock & (builder_subfragments_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_subfragments_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_subfragments_roundrobin2_grant == 1'd0))))) & main_port_cmd_valid);
4009                 end
4010         endcase
4011 end
4012 always @(*) begin
4013         builder_rhs_array_muxed24 <= 30'd0;
4014         case (builder_libresocsim_grant)
4015                 1'd0: begin
4016                         builder_rhs_array_muxed24 <= main_libresocsim_interface0_converted_interface_adr;
4017                 end
4018                 1'd1: begin
4019                         builder_rhs_array_muxed24 <= main_libresocsim_interface1_converted_interface_adr;
4020                 end
4021                 default: begin
4022                         builder_rhs_array_muxed24 <= main_libresocsim_libresoc_jtag_wb_adr;
4023                 end
4024         endcase
4025 end
4026 always @(*) begin
4027         builder_rhs_array_muxed25 <= 32'd0;
4028         case (builder_libresocsim_grant)
4029                 1'd0: begin
4030                         builder_rhs_array_muxed25 <= main_libresocsim_interface0_converted_interface_dat_w;
4031                 end
4032                 1'd1: begin
4033                         builder_rhs_array_muxed25 <= main_libresocsim_interface1_converted_interface_dat_w;
4034                 end
4035                 default: begin
4036                         builder_rhs_array_muxed25 <= main_libresocsim_libresoc_jtag_wb_dat_w;
4037                 end
4038         endcase
4039 end
4040 always @(*) begin
4041         builder_rhs_array_muxed26 <= 4'd0;
4042         case (builder_libresocsim_grant)
4043                 1'd0: begin
4044                         builder_rhs_array_muxed26 <= main_libresocsim_interface0_converted_interface_sel;
4045                 end
4046                 1'd1: begin
4047                         builder_rhs_array_muxed26 <= main_libresocsim_interface1_converted_interface_sel;
4048                 end
4049                 default: begin
4050                         builder_rhs_array_muxed26 <= main_libresocsim_libresoc_jtag_wb_sel;
4051                 end
4052         endcase
4053 end
4054 always @(*) begin
4055         builder_rhs_array_muxed27 <= 1'd0;
4056         case (builder_libresocsim_grant)
4057                 1'd0: begin
4058                         builder_rhs_array_muxed27 <= main_libresocsim_interface0_converted_interface_cyc;
4059                 end
4060                 1'd1: begin
4061                         builder_rhs_array_muxed27 <= main_libresocsim_interface1_converted_interface_cyc;
4062                 end
4063                 default: begin
4064                         builder_rhs_array_muxed27 <= main_libresocsim_libresoc_jtag_wb_cyc;
4065                 end
4066         endcase
4067 end
4068 always @(*) begin
4069         builder_rhs_array_muxed28 <= 1'd0;
4070         case (builder_libresocsim_grant)
4071                 1'd0: begin
4072                         builder_rhs_array_muxed28 <= main_libresocsim_interface0_converted_interface_stb;
4073                 end
4074                 1'd1: begin
4075                         builder_rhs_array_muxed28 <= main_libresocsim_interface1_converted_interface_stb;
4076                 end
4077                 default: begin
4078                         builder_rhs_array_muxed28 <= main_libresocsim_libresoc_jtag_wb_stb;
4079                 end
4080         endcase
4081 end
4082 always @(*) begin
4083         builder_rhs_array_muxed29 <= 1'd0;
4084         case (builder_libresocsim_grant)
4085                 1'd0: begin
4086                         builder_rhs_array_muxed29 <= main_libresocsim_interface0_converted_interface_we;
4087                 end
4088                 1'd1: begin
4089                         builder_rhs_array_muxed29 <= main_libresocsim_interface1_converted_interface_we;
4090                 end
4091                 default: begin
4092                         builder_rhs_array_muxed29 <= main_libresocsim_libresoc_jtag_wb_we;
4093                 end
4094         endcase
4095 end
4096 always @(*) begin
4097         builder_rhs_array_muxed30 <= 3'd0;
4098         case (builder_libresocsim_grant)
4099                 1'd0: begin
4100                         builder_rhs_array_muxed30 <= main_libresocsim_interface0_converted_interface_cti;
4101                 end
4102                 1'd1: begin
4103                         builder_rhs_array_muxed30 <= main_libresocsim_interface1_converted_interface_cti;
4104                 end
4105                 default: begin
4106                         builder_rhs_array_muxed30 <= main_libresocsim_libresoc_jtag_wb_cti;
4107                 end
4108         endcase
4109 end
4110 always @(*) begin
4111         builder_rhs_array_muxed31 <= 2'd0;
4112         case (builder_libresocsim_grant)
4113                 1'd0: begin
4114                         builder_rhs_array_muxed31 <= main_libresocsim_interface0_converted_interface_bte;
4115                 end
4116                 1'd1: begin
4117                         builder_rhs_array_muxed31 <= main_libresocsim_interface1_converted_interface_bte;
4118                 end
4119                 default: begin
4120                         builder_rhs_array_muxed31 <= main_libresocsim_libresoc_jtag_wb_bte;
4121                 end
4122         endcase
4123 end
4124 always @(*) begin
4125         builder_array_muxed0 <= 2'd0;
4126         case (main_sdram_steerer_sel)
4127                 1'd0: begin
4128                         builder_array_muxed0 <= main_sdram_nop_ba[1:0];
4129                 end
4130                 1'd1: begin
4131                         builder_array_muxed0 <= main_sdram_choose_req_cmd_payload_ba[1:0];
4132                 end
4133                 2'd2: begin
4134                         builder_array_muxed0 <= main_sdram_choose_req_cmd_payload_ba[1:0];
4135                 end
4136                 default: begin
4137                         builder_array_muxed0 <= main_sdram_cmd_payload_ba[1:0];
4138                 end
4139         endcase
4140 end
4141 always @(*) begin
4142         builder_array_muxed1 <= 13'd0;
4143         case (main_sdram_steerer_sel)
4144                 1'd0: begin
4145                         builder_array_muxed1 <= main_sdram_nop_a;
4146                 end
4147                 1'd1: begin
4148                         builder_array_muxed1 <= main_sdram_choose_req_cmd_payload_a;
4149                 end
4150                 2'd2: begin
4151                         builder_array_muxed1 <= main_sdram_choose_req_cmd_payload_a;
4152                 end
4153                 default: begin
4154                         builder_array_muxed1 <= main_sdram_cmd_payload_a;
4155                 end
4156         endcase
4157 end
4158 always @(*) begin
4159         builder_array_muxed2 <= 1'd0;
4160         case (main_sdram_steerer_sel)
4161                 1'd0: begin
4162                         builder_array_muxed2 <= 1'd0;
4163                 end
4164                 1'd1: begin
4165                         builder_array_muxed2 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
4166                 end
4167                 2'd2: begin
4168                         builder_array_muxed2 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
4169                 end
4170                 default: begin
4171                         builder_array_muxed2 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
4172                 end
4173         endcase
4174 end
4175 always @(*) begin
4176         builder_array_muxed3 <= 1'd0;
4177         case (main_sdram_steerer_sel)
4178                 1'd0: begin
4179                         builder_array_muxed3 <= 1'd0;
4180                 end
4181                 1'd1: begin
4182                         builder_array_muxed3 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
4183                 end
4184                 2'd2: begin
4185                         builder_array_muxed3 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
4186                 end
4187                 default: begin
4188                         builder_array_muxed3 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
4189                 end
4190         endcase
4191 end
4192 always @(*) begin
4193         builder_array_muxed4 <= 1'd0;
4194         case (main_sdram_steerer_sel)
4195                 1'd0: begin
4196                         builder_array_muxed4 <= 1'd0;
4197                 end
4198                 1'd1: begin
4199                         builder_array_muxed4 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
4200                 end
4201                 2'd2: begin
4202                         builder_array_muxed4 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
4203                 end
4204                 default: begin
4205                         builder_array_muxed4 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
4206                 end
4207         endcase
4208 end
4209 always @(*) begin
4210         builder_array_muxed5 <= 1'd0;
4211         case (main_sdram_steerer_sel)
4212                 1'd0: begin
4213                         builder_array_muxed5 <= 1'd0;
4214                 end
4215                 1'd1: begin
4216                         builder_array_muxed5 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
4217                 end
4218                 2'd2: begin
4219                         builder_array_muxed5 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
4220                 end
4221                 default: begin
4222                         builder_array_muxed5 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
4223                 end
4224         endcase
4225 end
4226 always @(*) begin
4227         builder_array_muxed6 <= 1'd0;
4228         case (main_sdram_steerer_sel)
4229                 1'd0: begin
4230                         builder_array_muxed6 <= 1'd0;
4231                 end
4232                 1'd1: begin
4233                         builder_array_muxed6 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
4234                 end
4235                 2'd2: begin
4236                         builder_array_muxed6 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
4237                 end
4238                 default: begin
4239                         builder_array_muxed6 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
4240                 end
4241         endcase
4242 end
4243 assign sdrio_clk = sys_clk;
4244 assign sdrio_clk_1 = sys_clk;
4245 assign sdrio_clk_2 = sys_clk;
4246 assign sdrio_clk_3 = sys_clk;
4247 assign sdrio_clk_4 = sys_clk;
4248 assign sdrio_clk_5 = sys_clk;
4249 assign sdrio_clk_6 = sys_clk;
4250 assign sdrio_clk_7 = sys_clk;
4251 assign sdrio_clk_8 = sys_clk;
4252 assign sdrio_clk_9 = sys_clk;
4253 assign sdrio_clk_10 = sys_clk;
4254 assign sdrio_clk_11 = sys_clk;
4255 assign sdrio_clk_12 = sys_clk;
4256 assign sdrio_clk_13 = sys_clk;
4257 assign sdrio_clk_14 = sys_clk;
4258 assign sdrio_clk_15 = sys_clk;
4259 assign sdrio_clk_16 = sys_clk;
4260 assign sdrio_clk_17 = sys_clk;
4261 assign sdrio_clk_18 = sys_clk;
4262 assign sdrio_clk_19 = sys_clk;
4263 assign sdrio_clk_20 = sys_clk;
4264 assign sdrio_clk_21 = sys_clk;
4265 assign sdrio_clk_22 = sys_clk;
4266 assign sdrio_clk_23 = sys_clk;
4267 assign sdrio_clk_24 = sys_clk;
4268 assign sdrio_clk_25 = sys_clk;
4269 assign sdrio_clk_26 = sys_clk;
4270 assign sdrio_clk_27 = sys_clk;
4271 assign sdrio_clk_28 = sys_clk;
4272 assign sdrio_clk_29 = sys_clk;
4273 assign sdrio_clk_30 = sys_clk;
4274 assign sdrio_clk_31 = sys_clk;
4275 assign sdrio_clk_32 = sys_clk;
4276 assign sdrio_clk_33 = sys_clk;
4277 assign sdrio_clk_34 = sys_clk;
4278 assign sdrio_clk_35 = sys_clk;
4279 assign sdrio_clk_36 = sys_clk;
4280 assign sdrio_clk_37 = sys_clk;
4281 assign sdrio_clk_38 = sys_clk;
4282 assign sdrio_clk_39 = sys_clk;
4283 assign sdrio_clk_40 = sys_clk;
4284 assign sdrio_clk_41 = sys_clk;
4285 assign sdrio_clk_42 = sys_clk;
4286 assign sdrio_clk_43 = sys_clk;
4287 assign sdrio_clk_44 = sys_clk;
4288 assign sdrio_clk_45 = sys_clk;
4289 assign sdrio_clk_46 = sys_clk;
4290 assign sdrio_clk_47 = sys_clk;
4291 assign sdrio_clk_48 = sys_clk;
4292 assign sdrio_clk_49 = sys_clk;
4293 assign sdrio_clk_50 = sys_clk;
4294 assign sdrio_clk_51 = sys_clk;
4295 assign sdrio_clk_52 = sys_clk;
4296 assign sdrio_clk_53 = sys_clk;
4297 assign sdrio_clk_54 = sys_clk;
4298 assign sdrio_clk_55 = sys_clk;
4299 assign sdrio_clk_56 = sys_clk;
4300 assign sdrio_clk_57 = sys_clk;
4301 assign sdrio_clk_58 = sys_clk;
4302 assign sdrio_clk_59 = sys_clk;
4303 assign sdrio_clk_60 = sys_clk;
4304 assign sdrio_clk_61 = sys_clk;
4305 assign sdrio_clk_62 = sys_clk;
4306 assign sdrio_clk_63 = sys_clk;
4307 assign sdrio_clk_64 = sys_clk;
4308 assign sdrio_clk_65 = sys_clk;
4309 assign sdrio_clk_66 = sys_clk;
4310 assign sdrio_clk_67 = sys_clk;
4311 assign sdrio_clk_68 = sys_clk;
4312 assign sdrio_clk_69 = sys_clk;
4313 assign sdrio_clk_70 = sys_clk;
4314 assign main_uart_phy_rx = builder_regs1;
4315 assign sdrio_clk_71 = sys_clk;
4316 assign sdrio_clk_72 = sys_clk;
4317 assign sdrio_clk_73 = sys_clk;
4318 assign sdrio_clk_74 = sys_clk;
4319 assign sdrio_clk_75 = sys_clk;
4320 assign sdrio_clk_76 = sys_clk;
4321 assign sdrio_clk_77 = sys_clk;
4322 assign sdrio_clk_78 = sys_clk;
4323 assign sdrio_clk_79 = sys_clk;
4324 assign sdrio_clk_80 = sys_clk;
4325 assign sdrio_clk_81 = sys_clk;
4326 assign sdrio_clk_82 = sys_clk;
4327 assign sdrio_clk_83 = sys_clk;
4328 assign sdrio_clk_84 = sys_clk;
4329 assign sdrio_clk_85 = sys_clk;
4330 assign sdrio_clk_86 = sys_clk;
4331 assign sdrio_clk_87 = sys_clk;
4332 assign sdrio_clk_88 = sys_clk;
4333 assign sdrio_clk_89 = sys_clk;
4334 assign sdrio_clk_90 = sys_clk;
4335 assign sdrio_clk_91 = sys_clk;
4336 assign sdrio_clk_92 = sys_clk;
4337 assign sdrio_clk_93 = sys_clk;
4338 assign sdrio_clk_94 = sys_clk;
4339 assign sdrio_clk_95 = sys_clk;
4340 assign sdrio_clk_96 = sys_clk;
4341 assign sdrio_clk_97 = sys_clk;
4342 assign sdrio_clk_98 = sys_clk;
4343 assign sdrio_clk_99 = sys_clk;
4344 assign sdrio_clk_100 = sys_clk;
4345 assign sdrio_clk_101 = sys_clk;
4346 assign sdrio_clk_102 = sys_clk;
4347 assign sdrio_clk_103 = sys_clk;
4348 assign sdrio_clk_104 = sys_clk;
4349 assign sdrio_clk_105 = sys_clk;
4350 assign sdrio_clk_106 = sys_clk;
4351 assign sdrio_clk_107 = sys_clk;
4352 assign sdrio_clk_108 = sys_clk;
4353 assign sdrio_clk_109 = sys_clk;
4354 assign sdrio_clk_110 = sys_clk;
4355 assign sdrio_clk_111 = sys_clk;
4356 assign sdrio_clk_112 = sys_clk;
4357 assign sdrio_clk_113 = sys_clk;
4358 assign sdrio_clk_114 = sys_clk;
4359 assign sdrio_clk_115 = sys_clk;
4360 assign sdrio_clk_116 = sys_clk;
4361 assign sdrio_clk_117 = sys_clk;
4362 assign sdrio_clk_118 = sys_clk;
4363
4364 always @(posedge por_clk) begin
4365         main_int_rst <= sys_rst;
4366 end
4367
4368 always @(posedge sdrio_clk) begin
4369         main_libresocsim_libresoc_constraintmanager_sdram_a[0] <= main_dfi_p0_address[0];
4370         main_libresocsim_libresoc_constraintmanager_sdram_a[1] <= main_dfi_p0_address[1];
4371         main_libresocsim_libresoc_constraintmanager_sdram_a[2] <= main_dfi_p0_address[2];
4372         main_libresocsim_libresoc_constraintmanager_sdram_a[3] <= main_dfi_p0_address[3];
4373         main_libresocsim_libresoc_constraintmanager_sdram_a[4] <= main_dfi_p0_address[4];
4374         main_libresocsim_libresoc_constraintmanager_sdram_a[5] <= main_dfi_p0_address[5];
4375         main_libresocsim_libresoc_constraintmanager_sdram_a[6] <= main_dfi_p0_address[6];
4376         main_libresocsim_libresoc_constraintmanager_sdram_a[7] <= main_dfi_p0_address[7];
4377         main_libresocsim_libresoc_constraintmanager_sdram_a[8] <= main_dfi_p0_address[8];
4378         main_libresocsim_libresoc_constraintmanager_sdram_a[9] <= main_dfi_p0_address[9];
4379         main_libresocsim_libresoc_constraintmanager_sdram_a[10] <= main_dfi_p0_address[10];
4380         main_libresocsim_libresoc_constraintmanager_sdram_a[11] <= main_dfi_p0_address[11];
4381         main_libresocsim_libresoc_constraintmanager_sdram_a[12] <= main_dfi_p0_address[12];
4382         main_libresocsim_libresoc_constraintmanager_sdram_ba[0] <= main_dfi_p0_bank[0];
4383         main_libresocsim_libresoc_constraintmanager_sdram_ba[1] <= main_dfi_p0_bank[1];
4384         main_libresocsim_libresoc_constraintmanager_sdram_cas_n <= main_dfi_p0_cas_n;
4385         main_libresocsim_libresoc_constraintmanager_sdram_ras_n <= main_dfi_p0_ras_n;
4386         main_libresocsim_libresoc_constraintmanager_sdram_we_n <= main_dfi_p0_we_n;
4387         main_libresocsim_libresoc_constraintmanager_sdram_cke <= main_dfi_p0_cke;
4388         main_libresocsim_libresoc_constraintmanager_sdram_cs_n <= main_dfi_p0_cs_n;
4389         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[0] <= main_dfi_p0_wrdata_en;
4390         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[0] <= main_dfi_p0_wrdata[0];
4391         main_dfi_p0_rddata[0] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[0];
4392         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[1] <= main_dfi_p0_wrdata_en;
4393         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[1] <= main_dfi_p0_wrdata[1];
4394         main_dfi_p0_rddata[1] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[1];
4395         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[2] <= main_dfi_p0_wrdata_en;
4396         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[2] <= main_dfi_p0_wrdata[2];
4397         main_dfi_p0_rddata[2] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[2];
4398         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[3] <= main_dfi_p0_wrdata_en;
4399         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[3] <= main_dfi_p0_wrdata[3];
4400         main_dfi_p0_rddata[3] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[3];
4401         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[4] <= main_dfi_p0_wrdata_en;
4402         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[4] <= main_dfi_p0_wrdata[4];
4403         main_dfi_p0_rddata[4] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[4];
4404         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[5] <= main_dfi_p0_wrdata_en;
4405         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[5] <= main_dfi_p0_wrdata[5];
4406         main_dfi_p0_rddata[5] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[5];
4407         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[6] <= main_dfi_p0_wrdata_en;
4408         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[6] <= main_dfi_p0_wrdata[6];
4409         main_dfi_p0_rddata[6] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[6];
4410         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[7] <= main_dfi_p0_wrdata_en;
4411         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[7] <= main_dfi_p0_wrdata[7];
4412         main_dfi_p0_rddata[7] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[7];
4413         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[8] <= main_dfi_p0_wrdata_en;
4414         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[8] <= main_dfi_p0_wrdata[8];
4415         main_dfi_p0_rddata[8] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[8];
4416         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[9] <= main_dfi_p0_wrdata_en;
4417         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[9] <= main_dfi_p0_wrdata[9];
4418         main_dfi_p0_rddata[9] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[9];
4419         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[10] <= main_dfi_p0_wrdata_en;
4420         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[10] <= main_dfi_p0_wrdata[10];
4421         main_dfi_p0_rddata[10] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[10];
4422         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[11] <= main_dfi_p0_wrdata_en;
4423         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[11] <= main_dfi_p0_wrdata[11];
4424         main_dfi_p0_rddata[11] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[11];
4425         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[12] <= main_dfi_p0_wrdata_en;
4426         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[12] <= main_dfi_p0_wrdata[12];
4427         main_dfi_p0_rddata[12] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[12];
4428         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[13] <= main_dfi_p0_wrdata_en;
4429         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[13] <= main_dfi_p0_wrdata[13];
4430         main_dfi_p0_rddata[13] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[13];
4431         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[14] <= main_dfi_p0_wrdata_en;
4432         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[14] <= main_dfi_p0_wrdata[14];
4433         main_dfi_p0_rddata[14] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[14];
4434         main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[15] <= main_dfi_p0_wrdata_en;
4435         main_libresocsim_libresoc_constraintmanager_sdram_dq_o[15] <= main_dfi_p0_wrdata[15];
4436         main_dfi_p0_rddata[15] <= main_libresocsim_libresoc_constraintmanager_sdram_dq_i[15];
4437         main_libresocsim_libresoc_constraintmanager_sdram_dm[0] <= (main_dfi_p0_wrdata_en & main_dfi_p0_wrdata_mask[0]);
4438         main_libresocsim_libresoc_constraintmanager_sdram_dm[1] <= (main_dfi_p0_wrdata_en & main_dfi_p0_wrdata_mask[1]);
4439         main_libresocsim_libresoc_constraintmanager_sdram_clock <= sys_clk;
4440         main_gpio0_pads_gpio0oe[0] <= main_gpio0_oe_storage[0];
4441         main_gpio0_pads_gpio0o[0] <= main_gpio0_out_storage[0];
4442         main_gpio0_status[0] <= main_gpio0_pads_gpio0i[0];
4443         main_gpio0_pads_gpio0oe[1] <= main_gpio0_oe_storage[1];
4444         main_gpio0_pads_gpio0o[1] <= main_gpio0_out_storage[1];
4445         main_gpio0_status[1] <= main_gpio0_pads_gpio0i[1];
4446         main_gpio0_pads_gpio0oe[2] <= main_gpio0_oe_storage[2];
4447         main_gpio0_pads_gpio0o[2] <= main_gpio0_out_storage[2];
4448         main_gpio0_status[2] <= main_gpio0_pads_gpio0i[2];
4449         main_gpio0_pads_gpio0oe[3] <= main_gpio0_oe_storage[3];
4450         main_gpio0_pads_gpio0o[3] <= main_gpio0_out_storage[3];
4451         main_gpio0_status[3] <= main_gpio0_pads_gpio0i[3];
4452         main_gpio0_pads_gpio0oe[4] <= main_gpio0_oe_storage[4];
4453         main_gpio0_pads_gpio0o[4] <= main_gpio0_out_storage[4];
4454         main_gpio0_status[4] <= main_gpio0_pads_gpio0i[4];
4455         main_gpio0_pads_gpio0oe[5] <= main_gpio0_oe_storage[5];
4456         main_gpio0_pads_gpio0o[5] <= main_gpio0_out_storage[5];
4457         main_gpio0_status[5] <= main_gpio0_pads_gpio0i[5];
4458         main_gpio0_pads_gpio0oe[6] <= main_gpio0_oe_storage[6];
4459         main_gpio0_pads_gpio0o[6] <= main_gpio0_out_storage[6];
4460         main_gpio0_status[6] <= main_gpio0_pads_gpio0i[6];
4461         main_gpio0_pads_gpio0oe[7] <= main_gpio0_oe_storage[7];
4462         main_gpio0_pads_gpio0o[7] <= main_gpio0_out_storage[7];
4463         main_gpio0_status[7] <= main_gpio0_pads_gpio0i[7];
4464         main_gpio1_pads_gpio1oe[0] <= main_gpio1_oe_storage[0];
4465         main_gpio1_pads_gpio1o[0] <= main_gpio1_out_storage[0];
4466         main_gpio1_status[0] <= main_gpio1_pads_gpio1i[0];
4467         main_gpio1_pads_gpio1oe[1] <= main_gpio1_oe_storage[1];
4468         main_gpio1_pads_gpio1o[1] <= main_gpio1_out_storage[1];
4469         main_gpio1_status[1] <= main_gpio1_pads_gpio1i[1];
4470         main_gpio1_pads_gpio1oe[2] <= main_gpio1_oe_storage[2];
4471         main_gpio1_pads_gpio1o[2] <= main_gpio1_out_storage[2];
4472         main_gpio1_status[2] <= main_gpio1_pads_gpio1i[2];
4473         main_gpio1_pads_gpio1oe[3] <= main_gpio1_oe_storage[3];
4474         main_gpio1_pads_gpio1o[3] <= main_gpio1_out_storage[3];
4475         main_gpio1_status[3] <= main_gpio1_pads_gpio1i[3];
4476         main_gpio1_pads_gpio1oe[4] <= main_gpio1_oe_storage[4];
4477         main_gpio1_pads_gpio1o[4] <= main_gpio1_out_storage[4];
4478         main_gpio1_status[4] <= main_gpio1_pads_gpio1i[4];
4479         main_gpio1_pads_gpio1oe[5] <= main_gpio1_oe_storage[5];
4480         main_gpio1_pads_gpio1o[5] <= main_gpio1_out_storage[5];
4481         main_gpio1_status[5] <= main_gpio1_pads_gpio1i[5];
4482         main_gpio1_pads_gpio1oe[6] <= main_gpio1_oe_storage[6];
4483         main_gpio1_pads_gpio1o[6] <= main_gpio1_out_storage[6];
4484         main_gpio1_status[6] <= main_gpio1_pads_gpio1i[6];
4485         main_gpio1_pads_gpio1oe[7] <= main_gpio1_oe_storage[7];
4486         main_gpio1_pads_gpio1o[7] <= main_gpio1_out_storage[7];
4487         main_gpio1_status[7] <= main_gpio1_pads_gpio1i[7];
4488 end
4489
4490 always @(posedge sys_clk) begin
4491         main_dummy[0] <= (main_nc[0] | main_libresocsim_libresoc_interrupt[0]);
4492         main_dummy[1] <= (main_nc[1] | main_libresocsim_libresoc_interrupt[0]);
4493         main_dummy[2] <= (main_nc[2] | main_libresocsim_libresoc_interrupt[0]);
4494         main_dummy[3] <= (main_nc[3] | main_libresocsim_libresoc_interrupt[0]);
4495         main_dummy[4] <= (main_nc[4] | main_libresocsim_libresoc_interrupt[0]);
4496         main_dummy[5] <= (main_nc[5] | main_libresocsim_libresoc_interrupt[0]);
4497         main_dummy[6] <= (main_nc[6] | main_libresocsim_libresoc_interrupt[0]);
4498         main_dummy[7] <= (main_nc[7] | main_libresocsim_libresoc_interrupt[0]);
4499         main_dummy[8] <= (main_nc[8] | main_libresocsim_libresoc_interrupt[0]);
4500         main_dummy[9] <= (main_nc[9] | main_libresocsim_libresoc_interrupt[0]);
4501         main_dummy[10] <= (main_nc[10] | main_libresocsim_libresoc_interrupt[0]);
4502         main_dummy[11] <= (main_nc[11] | main_libresocsim_libresoc_interrupt[0]);
4503         main_dummy[12] <= (main_nc[12] | main_libresocsim_libresoc_interrupt[0]);
4504         main_dummy[13] <= (main_nc[13] | main_libresocsim_libresoc_interrupt[0]);
4505         main_dummy[14] <= (main_nc[14] | main_libresocsim_libresoc_interrupt[0]);
4506         main_dummy[15] <= (main_nc[15] | main_libresocsim_libresoc_interrupt[0]);
4507         main_dummy[16] <= (main_nc[16] | main_libresocsim_libresoc_interrupt[0]);
4508         main_dummy[17] <= (main_nc[17] | main_libresocsim_libresoc_interrupt[0]);
4509         main_dummy[18] <= (main_nc[18] | main_libresocsim_libresoc_interrupt[0]);
4510         main_dummy[19] <= (main_nc[19] | main_libresocsim_libresoc_interrupt[0]);
4511         if ((main_libresocsim_interface0_converted_interface_ack | main_libresocsim_converter0_skip)) begin
4512                 main_libresocsim_converter0_dat_r <= main_libresocsim_libresoc_ibus_dat_r;
4513         end
4514         builder_subfragments_converter0_state <= builder_subfragments_converter0_next_state;
4515         if (main_libresocsim_converter0_counter_subfragments_converter0_next_value_ce) begin
4516                 main_libresocsim_converter0_counter <= main_libresocsim_converter0_counter_subfragments_converter0_next_value;
4517         end
4518         if (main_libresocsim_converter0_reset) begin
4519                 main_libresocsim_converter0_counter <= 1'd0;
4520                 builder_subfragments_converter0_state <= 1'd0;
4521         end
4522         if ((main_libresocsim_interface1_converted_interface_ack | main_libresocsim_converter1_skip)) begin
4523                 main_libresocsim_converter1_dat_r <= main_libresocsim_libresoc_dbus_dat_r;
4524         end
4525         builder_subfragments_converter1_state <= builder_subfragments_converter1_next_state;
4526         if (main_libresocsim_converter1_counter_subfragments_converter1_next_value_ce) begin
4527                 main_libresocsim_converter1_counter <= main_libresocsim_converter1_counter_subfragments_converter1_next_value;
4528         end
4529         if (main_libresocsim_converter1_reset) begin
4530                 main_libresocsim_converter1_counter <= 1'd0;
4531                 builder_subfragments_converter1_state <= 1'd0;
4532         end
4533         if ((main_libresocsim_bus_errors != 32'd4294967295)) begin
4534                 if (main_libresocsim_bus_error) begin
4535                         main_libresocsim_bus_errors <= (main_libresocsim_bus_errors + 1'd1);
4536                 end
4537         end
4538         main_libresocsim_ram_bus_ack <= 1'd0;
4539         if (((main_libresocsim_ram_bus_cyc & main_libresocsim_ram_bus_stb) & (~main_libresocsim_ram_bus_ack))) begin
4540                 main_libresocsim_ram_bus_ack <= 1'd1;
4541         end
4542         if (main_libresocsim_en_storage) begin
4543                 if ((main_libresocsim_value == 1'd0)) begin
4544                         main_libresocsim_value <= main_libresocsim_reload_storage;
4545                 end else begin
4546                         main_libresocsim_value <= (main_libresocsim_value - 1'd1);
4547                 end
4548         end else begin
4549                 main_libresocsim_value <= main_libresocsim_load_storage;
4550         end
4551         if (main_libresocsim_update_value_re) begin
4552                 main_libresocsim_value_status <= main_libresocsim_value;
4553         end
4554         if (main_libresocsim_zero_clear) begin
4555                 main_libresocsim_zero_pending <= 1'd0;
4556         end
4557         main_libresocsim_zero_old_trigger <= main_libresocsim_zero_trigger;
4558         if (((~main_libresocsim_zero_trigger) & main_libresocsim_zero_old_trigger)) begin
4559                 main_libresocsim_zero_pending <= 1'd1;
4560         end
4561         main_ram_bus_ram_bus_ack <= 1'd0;
4562         if (((main_ram_bus_ram_bus_cyc & main_ram_bus_ram_bus_stb) & (~main_ram_bus_ram_bus_ack))) begin
4563                 main_ram_bus_ram_bus_ack <= 1'd1;
4564         end
4565         main_rddata_en <= {main_rddata_en, main_dfi_p0_rddata_en};
4566         main_dfi_p0_rddata_valid <= main_rddata_en[2];
4567         if (main_sdram_inti_p0_rddata_valid) begin
4568                 main_sdram_status <= main_sdram_inti_p0_rddata;
4569         end
4570         if ((main_sdram_timer_wait & (~main_sdram_timer_done0))) begin
4571                 main_sdram_timer_count1 <= (main_sdram_timer_count1 - 1'd1);
4572         end else begin
4573                 main_sdram_timer_count1 <= 10'd781;
4574         end
4575         main_sdram_postponer_req_o <= 1'd0;
4576         if (main_sdram_postponer_req_i) begin
4577                 main_sdram_postponer_count <= (main_sdram_postponer_count - 1'd1);
4578                 if ((main_sdram_postponer_count == 1'd0)) begin
4579                         main_sdram_postponer_count <= 1'd0;
4580                         main_sdram_postponer_req_o <= 1'd1;
4581                 end
4582         end
4583         if (main_sdram_sequencer_start0) begin
4584                 main_sdram_sequencer_count <= 1'd0;
4585         end else begin
4586                 if (main_sdram_sequencer_done1) begin
4587                         if ((main_sdram_sequencer_count != 1'd0)) begin
4588                                 main_sdram_sequencer_count <= (main_sdram_sequencer_count - 1'd1);
4589                         end
4590                 end
4591         end
4592         main_sdram_cmd_payload_a <= 1'd0;
4593         main_sdram_cmd_payload_ba <= 1'd0;
4594         main_sdram_cmd_payload_cas <= 1'd0;
4595         main_sdram_cmd_payload_ras <= 1'd0;
4596         main_sdram_cmd_payload_we <= 1'd0;
4597         main_sdram_sequencer_done1 <= 1'd0;
4598         if ((main_sdram_sequencer_start1 & (main_sdram_sequencer_counter == 1'd0))) begin
4599                 main_sdram_cmd_payload_a <= 11'd1024;
4600                 main_sdram_cmd_payload_ba <= 1'd0;
4601                 main_sdram_cmd_payload_cas <= 1'd0;
4602                 main_sdram_cmd_payload_ras <= 1'd1;
4603                 main_sdram_cmd_payload_we <= 1'd1;
4604         end
4605         if ((main_sdram_sequencer_counter == 2'd2)) begin
4606                 main_sdram_cmd_payload_a <= 1'd0;
4607                 main_sdram_cmd_payload_ba <= 1'd0;
4608                 main_sdram_cmd_payload_cas <= 1'd1;
4609                 main_sdram_cmd_payload_ras <= 1'd1;
4610                 main_sdram_cmd_payload_we <= 1'd0;
4611         end
4612         if ((main_sdram_sequencer_counter == 4'd8)) begin
4613                 main_sdram_cmd_payload_a <= 1'd0;
4614                 main_sdram_cmd_payload_ba <= 1'd0;
4615                 main_sdram_cmd_payload_cas <= 1'd0;
4616                 main_sdram_cmd_payload_ras <= 1'd0;
4617                 main_sdram_cmd_payload_we <= 1'd0;
4618                 main_sdram_sequencer_done1 <= 1'd1;
4619         end
4620         if ((main_sdram_sequencer_counter == 4'd8)) begin
4621                 main_sdram_sequencer_counter <= 1'd0;
4622         end else begin
4623                 if ((main_sdram_sequencer_counter != 1'd0)) begin
4624                         main_sdram_sequencer_counter <= (main_sdram_sequencer_counter + 1'd1);
4625                 end else begin
4626                         if (main_sdram_sequencer_start1) begin
4627                                 main_sdram_sequencer_counter <= 1'd1;
4628                         end
4629                 end
4630         end
4631         builder_subfragments_refresher_state <= builder_subfragments_refresher_next_state;
4632         if (main_sdram_bankmachine0_row_close) begin
4633                 main_sdram_bankmachine0_row_opened <= 1'd0;
4634         end else begin
4635                 if (main_sdram_bankmachine0_row_open) begin
4636                         main_sdram_bankmachine0_row_opened <= 1'd1;
4637                         main_sdram_bankmachine0_row <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
4638                 end
4639         end
4640         if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4641                 main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
4642         end
4643         if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4644                 main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
4645         end
4646         if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4647                 if ((~main_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
4648                         main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
4649                 end
4650         end else begin
4651                 if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4652                         main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
4653                 end
4654         end
4655         if (((~main_sdram_bankmachine0_cmd_buffer_source_valid) | main_sdram_bankmachine0_cmd_buffer_source_ready)) begin
4656                 main_sdram_bankmachine0_cmd_buffer_source_valid <= main_sdram_bankmachine0_cmd_buffer_sink_valid;
4657                 main_sdram_bankmachine0_cmd_buffer_source_first <= main_sdram_bankmachine0_cmd_buffer_sink_first;
4658                 main_sdram_bankmachine0_cmd_buffer_source_last <= main_sdram_bankmachine0_cmd_buffer_sink_last;
4659                 main_sdram_bankmachine0_cmd_buffer_source_payload_we <= main_sdram_bankmachine0_cmd_buffer_sink_payload_we;
4660                 main_sdram_bankmachine0_cmd_buffer_source_payload_addr <= main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
4661         end
4662         if (main_sdram_bankmachine0_twtpcon_valid) begin
4663                 main_sdram_bankmachine0_twtpcon_count <= 3'd4;
4664                 if (1'd0) begin
4665                         main_sdram_bankmachine0_twtpcon_ready <= 1'd1;
4666                 end else begin
4667                         main_sdram_bankmachine0_twtpcon_ready <= 1'd0;
4668                 end
4669         end else begin
4670                 if ((~main_sdram_bankmachine0_twtpcon_ready)) begin
4671                         main_sdram_bankmachine0_twtpcon_count <= (main_sdram_bankmachine0_twtpcon_count - 1'd1);
4672                         if ((main_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
4673                                 main_sdram_bankmachine0_twtpcon_ready <= 1'd1;
4674                         end
4675                 end
4676         end
4677         builder_subfragments_bankmachine0_state <= builder_subfragments_bankmachine0_next_state;
4678         if (main_sdram_bankmachine1_row_close) begin
4679                 main_sdram_bankmachine1_row_opened <= 1'd0;
4680         end else begin
4681                 if (main_sdram_bankmachine1_row_open) begin
4682                         main_sdram_bankmachine1_row_opened <= 1'd1;
4683                         main_sdram_bankmachine1_row <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
4684                 end
4685         end
4686         if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4687                 main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
4688         end
4689         if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4690                 main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
4691         end
4692         if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4693                 if ((~main_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
4694                         main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
4695                 end
4696         end else begin
4697                 if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4698                         main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
4699                 end
4700         end
4701         if (((~main_sdram_bankmachine1_cmd_buffer_source_valid) | main_sdram_bankmachine1_cmd_buffer_source_ready)) begin
4702                 main_sdram_bankmachine1_cmd_buffer_source_valid <= main_sdram_bankmachine1_cmd_buffer_sink_valid;
4703                 main_sdram_bankmachine1_cmd_buffer_source_first <= main_sdram_bankmachine1_cmd_buffer_sink_first;
4704                 main_sdram_bankmachine1_cmd_buffer_source_last <= main_sdram_bankmachine1_cmd_buffer_sink_last;
4705                 main_sdram_bankmachine1_cmd_buffer_source_payload_we <= main_sdram_bankmachine1_cmd_buffer_sink_payload_we;
4706                 main_sdram_bankmachine1_cmd_buffer_source_payload_addr <= main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
4707         end
4708         if (main_sdram_bankmachine1_twtpcon_valid) begin
4709                 main_sdram_bankmachine1_twtpcon_count <= 3'd4;
4710                 if (1'd0) begin
4711                         main_sdram_bankmachine1_twtpcon_ready <= 1'd1;
4712                 end else begin
4713                         main_sdram_bankmachine1_twtpcon_ready <= 1'd0;
4714                 end
4715         end else begin
4716                 if ((~main_sdram_bankmachine1_twtpcon_ready)) begin
4717                         main_sdram_bankmachine1_twtpcon_count <= (main_sdram_bankmachine1_twtpcon_count - 1'd1);
4718                         if ((main_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
4719                                 main_sdram_bankmachine1_twtpcon_ready <= 1'd1;
4720                         end
4721                 end
4722         end
4723         builder_subfragments_bankmachine1_state <= builder_subfragments_bankmachine1_next_state;
4724         if (main_sdram_bankmachine2_row_close) begin
4725                 main_sdram_bankmachine2_row_opened <= 1'd0;
4726         end else begin
4727                 if (main_sdram_bankmachine2_row_open) begin
4728                         main_sdram_bankmachine2_row_opened <= 1'd1;
4729                         main_sdram_bankmachine2_row <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
4730                 end
4731         end
4732         if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4733                 main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
4734         end
4735         if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4736                 main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
4737         end
4738         if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4739                 if ((~main_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
4740                         main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
4741                 end
4742         end else begin
4743                 if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4744                         main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
4745                 end
4746         end
4747         if (((~main_sdram_bankmachine2_cmd_buffer_source_valid) | main_sdram_bankmachine2_cmd_buffer_source_ready)) begin
4748                 main_sdram_bankmachine2_cmd_buffer_source_valid <= main_sdram_bankmachine2_cmd_buffer_sink_valid;
4749                 main_sdram_bankmachine2_cmd_buffer_source_first <= main_sdram_bankmachine2_cmd_buffer_sink_first;
4750                 main_sdram_bankmachine2_cmd_buffer_source_last <= main_sdram_bankmachine2_cmd_buffer_sink_last;
4751                 main_sdram_bankmachine2_cmd_buffer_source_payload_we <= main_sdram_bankmachine2_cmd_buffer_sink_payload_we;
4752                 main_sdram_bankmachine2_cmd_buffer_source_payload_addr <= main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
4753         end
4754         if (main_sdram_bankmachine2_twtpcon_valid) begin
4755                 main_sdram_bankmachine2_twtpcon_count <= 3'd4;
4756                 if (1'd0) begin
4757                         main_sdram_bankmachine2_twtpcon_ready <= 1'd1;
4758                 end else begin
4759                         main_sdram_bankmachine2_twtpcon_ready <= 1'd0;
4760                 end
4761         end else begin
4762                 if ((~main_sdram_bankmachine2_twtpcon_ready)) begin
4763                         main_sdram_bankmachine2_twtpcon_count <= (main_sdram_bankmachine2_twtpcon_count - 1'd1);
4764                         if ((main_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
4765                                 main_sdram_bankmachine2_twtpcon_ready <= 1'd1;
4766                         end
4767                 end
4768         end
4769         builder_subfragments_bankmachine2_state <= builder_subfragments_bankmachine2_next_state;
4770         if (main_sdram_bankmachine3_row_close) begin
4771                 main_sdram_bankmachine3_row_opened <= 1'd0;
4772         end else begin
4773                 if (main_sdram_bankmachine3_row_open) begin
4774                         main_sdram_bankmachine3_row_opened <= 1'd1;
4775                         main_sdram_bankmachine3_row <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
4776                 end
4777         end
4778         if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4779                 main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
4780         end
4781         if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4782                 main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
4783         end
4784         if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4785                 if ((~main_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
4786                         main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
4787                 end
4788         end else begin
4789                 if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4790                         main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
4791                 end
4792         end
4793         if (((~main_sdram_bankmachine3_cmd_buffer_source_valid) | main_sdram_bankmachine3_cmd_buffer_source_ready)) begin
4794                 main_sdram_bankmachine3_cmd_buffer_source_valid <= main_sdram_bankmachine3_cmd_buffer_sink_valid;
4795                 main_sdram_bankmachine3_cmd_buffer_source_first <= main_sdram_bankmachine3_cmd_buffer_sink_first;
4796                 main_sdram_bankmachine3_cmd_buffer_source_last <= main_sdram_bankmachine3_cmd_buffer_sink_last;
4797                 main_sdram_bankmachine3_cmd_buffer_source_payload_we <= main_sdram_bankmachine3_cmd_buffer_sink_payload_we;
4798                 main_sdram_bankmachine3_cmd_buffer_source_payload_addr <= main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
4799         end
4800         if (main_sdram_bankmachine3_twtpcon_valid) begin
4801                 main_sdram_bankmachine3_twtpcon_count <= 3'd4;
4802                 if (1'd0) begin
4803                         main_sdram_bankmachine3_twtpcon_ready <= 1'd1;
4804                 end else begin
4805                         main_sdram_bankmachine3_twtpcon_ready <= 1'd0;
4806                 end
4807         end else begin
4808                 if ((~main_sdram_bankmachine3_twtpcon_ready)) begin
4809                         main_sdram_bankmachine3_twtpcon_count <= (main_sdram_bankmachine3_twtpcon_count - 1'd1);
4810                         if ((main_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
4811                                 main_sdram_bankmachine3_twtpcon_ready <= 1'd1;
4812                         end
4813                 end
4814         end
4815         builder_subfragments_bankmachine3_state <= builder_subfragments_bankmachine3_next_state;
4816         if ((~main_sdram_en0)) begin
4817                 main_sdram_time0 <= 5'd31;
4818         end else begin
4819                 if ((~main_sdram_max_time0)) begin
4820                         main_sdram_time0 <= (main_sdram_time0 - 1'd1);
4821                 end
4822         end
4823         if ((~main_sdram_en1)) begin
4824                 main_sdram_time1 <= 4'd15;
4825         end else begin
4826                 if ((~main_sdram_max_time1)) begin
4827                         main_sdram_time1 <= (main_sdram_time1 - 1'd1);
4828                 end
4829         end
4830         if (main_sdram_choose_cmd_ce) begin
4831                 case (main_sdram_choose_cmd_grant)
4832                         1'd0: begin
4833                                 if (main_sdram_choose_cmd_request[1]) begin
4834                                         main_sdram_choose_cmd_grant <= 1'd1;
4835                                 end else begin
4836                                         if (main_sdram_choose_cmd_request[2]) begin
4837                                                 main_sdram_choose_cmd_grant <= 2'd2;
4838                                         end else begin
4839                                                 if (main_sdram_choose_cmd_request[3]) begin
4840                                                         main_sdram_choose_cmd_grant <= 2'd3;
4841                                                 end
4842                                         end
4843                                 end
4844                         end
4845                         1'd1: begin
4846                                 if (main_sdram_choose_cmd_request[2]) begin
4847                                         main_sdram_choose_cmd_grant <= 2'd2;
4848                                 end else begin
4849                                         if (main_sdram_choose_cmd_request[3]) begin
4850                                                 main_sdram_choose_cmd_grant <= 2'd3;
4851                                         end else begin
4852                                                 if (main_sdram_choose_cmd_request[0]) begin
4853                                                         main_sdram_choose_cmd_grant <= 1'd0;
4854                                                 end
4855                                         end
4856                                 end
4857                         end
4858                         2'd2: begin
4859                                 if (main_sdram_choose_cmd_request[3]) begin
4860                                         main_sdram_choose_cmd_grant <= 2'd3;
4861                                 end else begin
4862                                         if (main_sdram_choose_cmd_request[0]) begin
4863                                                 main_sdram_choose_cmd_grant <= 1'd0;
4864                                         end else begin
4865                                                 if (main_sdram_choose_cmd_request[1]) begin
4866                                                         main_sdram_choose_cmd_grant <= 1'd1;
4867                                                 end
4868                                         end
4869                                 end
4870                         end
4871                         2'd3: begin
4872                                 if (main_sdram_choose_cmd_request[0]) begin
4873                                         main_sdram_choose_cmd_grant <= 1'd0;
4874                                 end else begin
4875                                         if (main_sdram_choose_cmd_request[1]) begin
4876                                                 main_sdram_choose_cmd_grant <= 1'd1;
4877                                         end else begin
4878                                                 if (main_sdram_choose_cmd_request[2]) begin
4879                                                         main_sdram_choose_cmd_grant <= 2'd2;
4880                                                 end
4881                                         end
4882                                 end
4883                         end
4884                 endcase
4885         end
4886         if (main_sdram_choose_req_ce) begin
4887                 case (main_sdram_choose_req_grant)
4888                         1'd0: begin
4889                                 if (main_sdram_choose_req_request[1]) begin
4890                                         main_sdram_choose_req_grant <= 1'd1;
4891                                 end else begin
4892                                         if (main_sdram_choose_req_request[2]) begin
4893                                                 main_sdram_choose_req_grant <= 2'd2;
4894                                         end else begin
4895                                                 if (main_sdram_choose_req_request[3]) begin
4896                                                         main_sdram_choose_req_grant <= 2'd3;
4897                                                 end
4898                                         end
4899                                 end
4900                         end
4901                         1'd1: begin
4902                                 if (main_sdram_choose_req_request[2]) begin
4903                                         main_sdram_choose_req_grant <= 2'd2;
4904                                 end else begin
4905                                         if (main_sdram_choose_req_request[3]) begin
4906                                                 main_sdram_choose_req_grant <= 2'd3;
4907                                         end else begin
4908                                                 if (main_sdram_choose_req_request[0]) begin
4909                                                         main_sdram_choose_req_grant <= 1'd0;
4910                                                 end
4911                                         end
4912                                 end
4913                         end
4914                         2'd2: begin
4915                                 if (main_sdram_choose_req_request[3]) begin
4916                                         main_sdram_choose_req_grant <= 2'd3;
4917                                 end else begin
4918                                         if (main_sdram_choose_req_request[0]) begin
4919                                                 main_sdram_choose_req_grant <= 1'd0;
4920                                         end else begin
4921                                                 if (main_sdram_choose_req_request[1]) begin
4922                                                         main_sdram_choose_req_grant <= 1'd1;
4923                                                 end
4924                                         end
4925                                 end
4926                         end
4927                         2'd3: begin
4928                                 if (main_sdram_choose_req_request[0]) begin
4929                                         main_sdram_choose_req_grant <= 1'd0;
4930                                 end else begin
4931                                         if (main_sdram_choose_req_request[1]) begin
4932                                                 main_sdram_choose_req_grant <= 1'd1;
4933                                         end else begin
4934                                                 if (main_sdram_choose_req_request[2]) begin
4935                                                         main_sdram_choose_req_grant <= 2'd2;
4936                                                 end
4937                                         end
4938                                 end
4939                         end
4940                 endcase
4941         end
4942         main_sdram_dfi_p0_cs_n <= 1'd0;
4943         main_sdram_dfi_p0_bank <= builder_array_muxed0;
4944         main_sdram_dfi_p0_address <= builder_array_muxed1;
4945         main_sdram_dfi_p0_cas_n <= (~builder_array_muxed2);
4946         main_sdram_dfi_p0_ras_n <= (~builder_array_muxed3);
4947         main_sdram_dfi_p0_we_n <= (~builder_array_muxed4);
4948         main_sdram_dfi_p0_rddata_en <= builder_array_muxed5;
4949         main_sdram_dfi_p0_wrdata_en <= builder_array_muxed6;
4950         if (main_sdram_tccdcon_valid) begin
4951                 main_sdram_tccdcon_count <= 1'd0;
4952                 if (1'd1) begin
4953                         main_sdram_tccdcon_ready <= 1'd1;
4954                 end else begin
4955                         main_sdram_tccdcon_ready <= 1'd0;
4956                 end
4957         end else begin
4958                 if ((~main_sdram_tccdcon_ready)) begin
4959                         main_sdram_tccdcon_count <= (main_sdram_tccdcon_count - 1'd1);
4960                         if ((main_sdram_tccdcon_count == 1'd1)) begin
4961                                 main_sdram_tccdcon_ready <= 1'd1;
4962                         end
4963                 end
4964         end
4965         if (main_sdram_twtrcon_valid) begin
4966                 main_sdram_twtrcon_count <= 3'd4;
4967                 if (1'd0) begin
4968                         main_sdram_twtrcon_ready <= 1'd1;
4969                 end else begin
4970                         main_sdram_twtrcon_ready <= 1'd0;
4971                 end
4972         end else begin
4973                 if ((~main_sdram_twtrcon_ready)) begin
4974                         main_sdram_twtrcon_count <= (main_sdram_twtrcon_count - 1'd1);
4975                         if ((main_sdram_twtrcon_count == 1'd1)) begin
4976                                 main_sdram_twtrcon_ready <= 1'd1;
4977                         end
4978                 end
4979         end
4980         builder_subfragments_multiplexer_state <= builder_subfragments_multiplexer_next_state;
4981         builder_subfragments_new_master_wdata_ready <= ((((1'd0 | ((builder_subfragments_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) | ((builder_subfragments_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) | ((builder_subfragments_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) | ((builder_subfragments_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready));
4982         builder_subfragments_new_master_rdata_valid0 <= ((((1'd0 | ((builder_subfragments_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) | ((builder_subfragments_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) | ((builder_subfragments_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) | ((builder_subfragments_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid));
4983         builder_subfragments_new_master_rdata_valid1 <= builder_subfragments_new_master_rdata_valid0;
4984         builder_subfragments_new_master_rdata_valid2 <= builder_subfragments_new_master_rdata_valid1;
4985         builder_subfragments_new_master_rdata_valid3 <= builder_subfragments_new_master_rdata_valid2;
4986         if ((main_litedram_wb_ack | main_converter_skip)) begin
4987                 main_converter_dat_r <= main_wb_sdram_dat_r;
4988         end
4989         builder_subfragments_state <= builder_subfragments_next_state;
4990         if (main_converter_counter_subfragments_next_value_ce) begin
4991                 main_converter_counter <= main_converter_counter_subfragments_next_value;
4992         end
4993         if (main_converter_reset) begin
4994                 main_converter_counter <= 1'd0;
4995                 builder_subfragments_state <= 1'd0;
4996         end
4997         if (main_litedram_wb_ack) begin
4998                 main_cmd_consumed <= 1'd0;
4999                 main_wdata_consumed <= 1'd0;
5000         end else begin
5001                 if ((main_port_cmd_valid & main_port_cmd_ready)) begin
5002                         main_cmd_consumed <= 1'd1;
5003                 end
5004                 if ((main_port_wdata_valid & main_port_wdata_ready)) begin
5005                         main_wdata_consumed <= 1'd1;
5006                 end
5007         end
5008         main_uart_phy_sink_ready <= 1'd0;
5009         if (((main_uart_phy_sink_valid & (~main_uart_phy_tx_busy)) & (~main_uart_phy_sink_ready))) begin
5010                 main_uart_phy_tx_reg <= main_uart_phy_sink_payload_data;
5011                 main_uart_phy_tx_bitcount <= 1'd0;
5012                 main_uart_phy_tx_busy <= 1'd1;
5013                 main_libresocsim_libresoc_constraintmanager_uart_tx <= 1'd0;
5014         end else begin
5015                 if ((main_uart_phy_uart_clk_txen & main_uart_phy_tx_busy)) begin
5016                         main_uart_phy_tx_bitcount <= (main_uart_phy_tx_bitcount + 1'd1);
5017                         if ((main_uart_phy_tx_bitcount == 4'd8)) begin
5018                                 main_libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5019                         end else begin
5020                                 if ((main_uart_phy_tx_bitcount == 4'd9)) begin
5021                                         main_libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5022                                         main_uart_phy_tx_busy <= 1'd0;
5023                                         main_uart_phy_sink_ready <= 1'd1;
5024                                 end else begin
5025                                         main_libresocsim_libresoc_constraintmanager_uart_tx <= main_uart_phy_tx_reg[0];
5026                                         main_uart_phy_tx_reg <= {1'd0, main_uart_phy_tx_reg[7:1]};
5027                                 end
5028                         end
5029                 end
5030         end
5031         if (main_uart_phy_tx_busy) begin
5032                 {main_uart_phy_uart_clk_txen, main_uart_phy_phase_accumulator_tx} <= (main_uart_phy_phase_accumulator_tx + main_uart_phy_storage);
5033         end else begin
5034                 {main_uart_phy_uart_clk_txen, main_uart_phy_phase_accumulator_tx} <= main_uart_phy_storage;
5035         end
5036         main_uart_phy_source_valid <= 1'd0;
5037         main_uart_phy_rx_r <= main_uart_phy_rx;
5038         if ((~main_uart_phy_rx_busy)) begin
5039                 if (((~main_uart_phy_rx) & main_uart_phy_rx_r)) begin
5040                         main_uart_phy_rx_busy <= 1'd1;
5041                         main_uart_phy_rx_bitcount <= 1'd0;
5042                 end
5043         end else begin
5044                 if (main_uart_phy_uart_clk_rxen) begin
5045                         main_uart_phy_rx_bitcount <= (main_uart_phy_rx_bitcount + 1'd1);
5046                         if ((main_uart_phy_rx_bitcount == 1'd0)) begin
5047                                 if (main_uart_phy_rx) begin
5048                                         main_uart_phy_rx_busy <= 1'd0;
5049                                 end
5050                         end else begin
5051                                 if ((main_uart_phy_rx_bitcount == 4'd9)) begin
5052                                         main_uart_phy_rx_busy <= 1'd0;
5053                                         if (main_uart_phy_rx) begin
5054                                                 main_uart_phy_source_payload_data <= main_uart_phy_rx_reg;
5055                                                 main_uart_phy_source_valid <= 1'd1;
5056                                         end
5057                                 end else begin
5058                                         main_uart_phy_rx_reg <= {main_uart_phy_rx, main_uart_phy_rx_reg[7:1]};
5059                                 end
5060                         end
5061                 end
5062         end
5063         if (main_uart_phy_rx_busy) begin
5064                 {main_uart_phy_uart_clk_rxen, main_uart_phy_phase_accumulator_rx} <= (main_uart_phy_phase_accumulator_rx + main_uart_phy_storage);
5065         end else begin
5066                 {main_uart_phy_uart_clk_rxen, main_uart_phy_phase_accumulator_rx} <= 32'd2147483648;
5067         end
5068         if (main_tx_clear) begin
5069                 main_tx_pending <= 1'd0;
5070         end
5071         main_tx_old_trigger <= main_tx_trigger;
5072         if (((~main_tx_trigger) & main_tx_old_trigger)) begin
5073                 main_tx_pending <= 1'd1;
5074         end
5075         if (main_rx_clear) begin
5076                 main_rx_pending <= 1'd0;
5077         end
5078         main_rx_old_trigger <= main_rx_trigger;
5079         if (((~main_rx_trigger) & main_rx_old_trigger)) begin
5080                 main_rx_pending <= 1'd1;
5081         end
5082         if (main_tx_fifo_syncfifo_re) begin
5083                 main_tx_fifo_readable <= 1'd1;
5084         end else begin
5085                 if (main_tx_fifo_re) begin
5086                         main_tx_fifo_readable <= 1'd0;
5087                 end
5088         end
5089         if (((main_tx_fifo_syncfifo_we & main_tx_fifo_syncfifo_writable) & (~main_tx_fifo_replace))) begin
5090                 main_tx_fifo_produce <= (main_tx_fifo_produce + 1'd1);
5091         end
5092         if (main_tx_fifo_do_read) begin
5093                 main_tx_fifo_consume <= (main_tx_fifo_consume + 1'd1);
5094         end
5095         if (((main_tx_fifo_syncfifo_we & main_tx_fifo_syncfifo_writable) & (~main_tx_fifo_replace))) begin
5096                 if ((~main_tx_fifo_do_read)) begin
5097                         main_tx_fifo_level0 <= (main_tx_fifo_level0 + 1'd1);
5098                 end
5099         end else begin
5100                 if (main_tx_fifo_do_read) begin
5101                         main_tx_fifo_level0 <= (main_tx_fifo_level0 - 1'd1);
5102                 end
5103         end
5104         if (main_rx_fifo_syncfifo_re) begin
5105                 main_rx_fifo_readable <= 1'd1;
5106         end else begin
5107                 if (main_rx_fifo_re) begin
5108                         main_rx_fifo_readable <= 1'd0;
5109                 end
5110         end
5111         if (((main_rx_fifo_syncfifo_we & main_rx_fifo_syncfifo_writable) & (~main_rx_fifo_replace))) begin
5112                 main_rx_fifo_produce <= (main_rx_fifo_produce + 1'd1);
5113         end
5114         if (main_rx_fifo_do_read) begin
5115                 main_rx_fifo_consume <= (main_rx_fifo_consume + 1'd1);
5116         end
5117         if (((main_rx_fifo_syncfifo_we & main_rx_fifo_syncfifo_writable) & (~main_rx_fifo_replace))) begin
5118                 if ((~main_rx_fifo_do_read)) begin
5119                         main_rx_fifo_level0 <= (main_rx_fifo_level0 + 1'd1);
5120                 end
5121         end else begin
5122                 if (main_rx_fifo_do_read) begin
5123                         main_rx_fifo_level0 <= (main_rx_fifo_level0 - 1'd1);
5124                 end
5125         end
5126         if (main_reset) begin
5127                 main_tx_pending <= 1'd0;
5128                 main_tx_old_trigger <= 1'd0;
5129                 main_rx_pending <= 1'd0;
5130                 main_rx_old_trigger <= 1'd0;
5131                 main_tx_fifo_readable <= 1'd0;
5132                 main_tx_fifo_level0 <= 5'd0;
5133                 main_tx_fifo_produce <= 4'd0;
5134                 main_tx_fifo_consume <= 4'd0;
5135                 main_rx_fifo_readable <= 1'd0;
5136                 main_rx_fifo_level0 <= 5'd0;
5137                 main_rx_fifo_produce <= 4'd0;
5138                 main_rx_fifo_consume <= 4'd0;
5139         end
5140         builder_libresocsim_state <= builder_libresocsim_next_state;
5141         if (builder_libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0) begin
5142                 builder_libresocsim_libresocsim_dat_w <= builder_libresocsim_libresocsim_dat_w_libresocsim_next_value0;
5143         end
5144         if (builder_libresocsim_libresocsim_adr_libresocsim_next_value_ce1) begin
5145                 builder_libresocsim_libresocsim_adr <= builder_libresocsim_libresocsim_adr_libresocsim_next_value1;
5146         end
5147         if (builder_libresocsim_libresocsim_we_libresocsim_next_value_ce2) begin
5148                 builder_libresocsim_libresocsim_we <= builder_libresocsim_libresocsim_we_libresocsim_next_value2;
5149         end
5150         case (builder_libresocsim_grant)
5151                 1'd0: begin
5152                         if ((~builder_libresocsim_request[0])) begin
5153                                 if (builder_libresocsim_request[1]) begin
5154                                         builder_libresocsim_grant <= 1'd1;
5155                                 end else begin
5156                                         if (builder_libresocsim_request[2]) begin
5157                                                 builder_libresocsim_grant <= 2'd2;
5158                                         end
5159                                 end
5160                         end
5161                 end
5162                 1'd1: begin
5163                         if ((~builder_libresocsim_request[1])) begin
5164                                 if (builder_libresocsim_request[2]) begin
5165                                         builder_libresocsim_grant <= 2'd2;
5166                                 end else begin
5167                                         if (builder_libresocsim_request[0]) begin
5168                                                 builder_libresocsim_grant <= 1'd0;
5169                                         end
5170                                 end
5171                         end
5172                 end
5173                 2'd2: begin
5174                         if ((~builder_libresocsim_request[2])) begin
5175                                 if (builder_libresocsim_request[0]) begin
5176                                         builder_libresocsim_grant <= 1'd0;
5177                                 end else begin
5178                                         if (builder_libresocsim_request[1]) begin
5179                                                 builder_libresocsim_grant <= 1'd1;
5180                                         end
5181                                 end
5182                         end
5183                 end
5184         endcase
5185         builder_libresocsim_slave_sel_r <= builder_libresocsim_slave_sel;
5186         if (builder_libresocsim_wait) begin
5187                 if ((~builder_libresocsim_done)) begin
5188                         builder_libresocsim_count <= (builder_libresocsim_count - 1'd1);
5189                 end
5190         end else begin
5191                 builder_libresocsim_count <= 20'd1000000;
5192         end
5193         builder_libresocsim_interface0_bank_bus_dat_r <= 1'd0;
5194         if (builder_libresocsim_csrbank0_sel) begin
5195                 case (builder_libresocsim_interface0_bank_bus_adr[3:0])
5196                         1'd0: begin
5197                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_reset0_w;
5198                         end
5199                         1'd1: begin
5200                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_scratch3_w;
5201                         end
5202                         2'd2: begin
5203                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_scratch2_w;
5204                         end
5205                         2'd3: begin
5206                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_scratch1_w;
5207                         end
5208                         3'd4: begin
5209                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_scratch0_w;
5210                         end
5211                         3'd5: begin
5212                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_bus_errors3_w;
5213                         end
5214                         3'd6: begin
5215                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_bus_errors2_w;
5216                         end
5217                         3'd7: begin
5218                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_bus_errors1_w;
5219                         end
5220                         4'd8: begin
5221                                 builder_libresocsim_interface0_bank_bus_dat_r <= builder_libresocsim_csrbank0_bus_errors0_w;
5222                         end
5223                 endcase
5224         end
5225         if (builder_libresocsim_csrbank0_reset0_re) begin
5226                 main_libresocsim_reset_storage <= builder_libresocsim_csrbank0_reset0_r;
5227         end
5228         main_libresocsim_reset_re <= builder_libresocsim_csrbank0_reset0_re;
5229         if (builder_libresocsim_csrbank0_scratch3_re) begin
5230                 main_libresocsim_scratch_storage[31:24] <= builder_libresocsim_csrbank0_scratch3_r;
5231         end
5232         if (builder_libresocsim_csrbank0_scratch2_re) begin
5233                 main_libresocsim_scratch_storage[23:16] <= builder_libresocsim_csrbank0_scratch2_r;
5234         end
5235         if (builder_libresocsim_csrbank0_scratch1_re) begin
5236                 main_libresocsim_scratch_storage[15:8] <= builder_libresocsim_csrbank0_scratch1_r;
5237         end
5238         if (builder_libresocsim_csrbank0_scratch0_re) begin
5239                 main_libresocsim_scratch_storage[7:0] <= builder_libresocsim_csrbank0_scratch0_r;
5240         end
5241         main_libresocsim_scratch_re <= builder_libresocsim_csrbank0_scratch0_re;
5242         builder_libresocsim_interface1_bank_bus_dat_r <= 1'd0;
5243         if (builder_libresocsim_csrbank1_sel) begin
5244                 case (builder_libresocsim_interface1_bank_bus_adr[1:0])
5245                         1'd0: begin
5246                                 builder_libresocsim_interface1_bank_bus_dat_r <= builder_libresocsim_csrbank1_oe0_w;
5247                         end
5248                         1'd1: begin
5249                                 builder_libresocsim_interface1_bank_bus_dat_r <= builder_libresocsim_csrbank1_in_w;
5250                         end
5251                         2'd2: begin
5252                                 builder_libresocsim_interface1_bank_bus_dat_r <= builder_libresocsim_csrbank1_out0_w;
5253                         end
5254                 endcase
5255         end
5256         if (builder_libresocsim_csrbank1_oe0_re) begin
5257                 main_gpio0_oe_storage[7:0] <= builder_libresocsim_csrbank1_oe0_r;
5258         end
5259         main_gpio0_oe_re <= builder_libresocsim_csrbank1_oe0_re;
5260         if (builder_libresocsim_csrbank1_out0_re) begin
5261                 main_gpio0_out_storage[7:0] <= builder_libresocsim_csrbank1_out0_r;
5262         end
5263         main_gpio0_out_re <= builder_libresocsim_csrbank1_out0_re;
5264         builder_libresocsim_interface2_bank_bus_dat_r <= 1'd0;
5265         if (builder_libresocsim_csrbank2_sel) begin
5266                 case (builder_libresocsim_interface2_bank_bus_adr[1:0])
5267                         1'd0: begin
5268                                 builder_libresocsim_interface2_bank_bus_dat_r <= builder_libresocsim_csrbank2_oe0_w;
5269                         end
5270                         1'd1: begin
5271                                 builder_libresocsim_interface2_bank_bus_dat_r <= builder_libresocsim_csrbank2_in_w;
5272                         end
5273                         2'd2: begin
5274                                 builder_libresocsim_interface2_bank_bus_dat_r <= builder_libresocsim_csrbank2_out0_w;
5275                         end
5276                 endcase
5277         end
5278         if (builder_libresocsim_csrbank2_oe0_re) begin
5279                 main_gpio1_oe_storage[7:0] <= builder_libresocsim_csrbank2_oe0_r;
5280         end
5281         main_gpio1_oe_re <= builder_libresocsim_csrbank2_oe0_re;
5282         if (builder_libresocsim_csrbank2_out0_re) begin
5283                 main_gpio1_out_storage[7:0] <= builder_libresocsim_csrbank2_out0_r;
5284         end
5285         main_gpio1_out_re <= builder_libresocsim_csrbank2_out0_re;
5286         builder_libresocsim_interface3_bank_bus_dat_r <= 1'd0;
5287         if (builder_libresocsim_csrbank3_sel) begin
5288                 case (builder_libresocsim_interface3_bank_bus_adr[0])
5289                         1'd0: begin
5290                                 builder_libresocsim_interface3_bank_bus_dat_r <= builder_libresocsim_csrbank3_w0_w;
5291                         end
5292                         1'd1: begin
5293                                 builder_libresocsim_interface3_bank_bus_dat_r <= builder_libresocsim_csrbank3_r_w;
5294                         end
5295                 endcase
5296         end
5297         if (builder_libresocsim_csrbank3_w0_re) begin
5298                 main_i2c_storage[2:0] <= builder_libresocsim_csrbank3_w0_r;
5299         end
5300         main_i2c_re <= builder_libresocsim_csrbank3_w0_re;
5301         builder_libresocsim_interface4_bank_bus_dat_r <= 1'd0;
5302         if (builder_libresocsim_csrbank4_sel) begin
5303                 case (builder_libresocsim_interface4_bank_bus_adr[3:0])
5304                         1'd0: begin
5305                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_control0_w;
5306                         end
5307                         1'd1: begin
5308                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_command0_w;
5309                         end
5310                         2'd2: begin
5311                                 builder_libresocsim_interface4_bank_bus_dat_r <= main_sdram_command_issue_w;
5312                         end
5313                         2'd3: begin
5314                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_address1_w;
5315                         end
5316                         3'd4: begin
5317                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_address0_w;
5318                         end
5319                         3'd5: begin
5320                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_baddress0_w;
5321                         end
5322                         3'd6: begin
5323                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_wrdata1_w;
5324                         end
5325                         3'd7: begin
5326                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_wrdata0_w;
5327                         end
5328                         4'd8: begin
5329                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_rddata1_w;
5330                         end
5331                         4'd9: begin
5332                                 builder_libresocsim_interface4_bank_bus_dat_r <= builder_libresocsim_csrbank4_dfii_pi0_rddata0_w;
5333                         end
5334                 endcase
5335         end
5336         if (builder_libresocsim_csrbank4_dfii_control0_re) begin
5337                 main_sdram_storage[3:0] <= builder_libresocsim_csrbank4_dfii_control0_r;
5338         end
5339         main_sdram_re <= builder_libresocsim_csrbank4_dfii_control0_re;
5340         if (builder_libresocsim_csrbank4_dfii_pi0_command0_re) begin
5341                 main_sdram_command_storage[5:0] <= builder_libresocsim_csrbank4_dfii_pi0_command0_r;
5342         end
5343         main_sdram_command_re <= builder_libresocsim_csrbank4_dfii_pi0_command0_re;
5344         if (builder_libresocsim_csrbank4_dfii_pi0_address1_re) begin
5345                 main_sdram_address_storage[12:8] <= builder_libresocsim_csrbank4_dfii_pi0_address1_r;
5346         end
5347         if (builder_libresocsim_csrbank4_dfii_pi0_address0_re) begin
5348                 main_sdram_address_storage[7:0] <= builder_libresocsim_csrbank4_dfii_pi0_address0_r;
5349         end
5350         main_sdram_address_re <= builder_libresocsim_csrbank4_dfii_pi0_address0_re;
5351         if (builder_libresocsim_csrbank4_dfii_pi0_baddress0_re) begin
5352                 main_sdram_baddress_storage[1:0] <= builder_libresocsim_csrbank4_dfii_pi0_baddress0_r;
5353         end
5354         main_sdram_baddress_re <= builder_libresocsim_csrbank4_dfii_pi0_baddress0_re;
5355         if (builder_libresocsim_csrbank4_dfii_pi0_wrdata1_re) begin
5356                 main_sdram_wrdata_storage[15:8] <= builder_libresocsim_csrbank4_dfii_pi0_wrdata1_r;
5357         end
5358         if (builder_libresocsim_csrbank4_dfii_pi0_wrdata0_re) begin
5359                 main_sdram_wrdata_storage[7:0] <= builder_libresocsim_csrbank4_dfii_pi0_wrdata0_r;
5360         end
5361         main_sdram_wrdata_re <= builder_libresocsim_csrbank4_dfii_pi0_wrdata0_re;
5362         builder_libresocsim_interface5_bank_bus_dat_r <= 1'd0;
5363         if (builder_libresocsim_csrbank5_sel) begin
5364                 case (builder_libresocsim_interface5_bank_bus_adr[4:0])
5365                         1'd0: begin
5366                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_load3_w;
5367                         end
5368                         1'd1: begin
5369                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_load2_w;
5370                         end
5371                         2'd2: begin
5372                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_load1_w;
5373                         end
5374                         2'd3: begin
5375                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_load0_w;
5376                         end
5377                         3'd4: begin
5378                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_reload3_w;
5379                         end
5380                         3'd5: begin
5381                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_reload2_w;
5382                         end
5383                         3'd6: begin
5384                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_reload1_w;
5385                         end
5386                         3'd7: begin
5387                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_reload0_w;
5388                         end
5389                         4'd8: begin
5390                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_en0_w;
5391                         end
5392                         4'd9: begin
5393                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_update_value0_w;
5394                         end
5395                         4'd10: begin
5396                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_value3_w;
5397                         end
5398                         4'd11: begin
5399                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_value2_w;
5400                         end
5401                         4'd12: begin
5402                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_value1_w;
5403                         end
5404                         4'd13: begin
5405                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_value0_w;
5406                         end
5407                         4'd14: begin
5408                                 builder_libresocsim_interface5_bank_bus_dat_r <= main_libresocsim_eventmanager_status_w;
5409                         end
5410                         4'd15: begin
5411                                 builder_libresocsim_interface5_bank_bus_dat_r <= main_libresocsim_eventmanager_pending_w;
5412                         end
5413                         5'd16: begin
5414                                 builder_libresocsim_interface5_bank_bus_dat_r <= builder_libresocsim_csrbank5_ev_enable0_w;
5415                         end
5416                 endcase
5417         end
5418         if (builder_libresocsim_csrbank5_load3_re) begin
5419                 main_libresocsim_load_storage[31:24] <= builder_libresocsim_csrbank5_load3_r;
5420         end
5421         if (builder_libresocsim_csrbank5_load2_re) begin
5422                 main_libresocsim_load_storage[23:16] <= builder_libresocsim_csrbank5_load2_r;
5423         end
5424         if (builder_libresocsim_csrbank5_load1_re) begin
5425                 main_libresocsim_load_storage[15:8] <= builder_libresocsim_csrbank5_load1_r;
5426         end
5427         if (builder_libresocsim_csrbank5_load0_re) begin
5428                 main_libresocsim_load_storage[7:0] <= builder_libresocsim_csrbank5_load0_r;
5429         end
5430         main_libresocsim_load_re <= builder_libresocsim_csrbank5_load0_re;
5431         if (builder_libresocsim_csrbank5_reload3_re) begin
5432                 main_libresocsim_reload_storage[31:24] <= builder_libresocsim_csrbank5_reload3_r;
5433         end
5434         if (builder_libresocsim_csrbank5_reload2_re) begin
5435                 main_libresocsim_reload_storage[23:16] <= builder_libresocsim_csrbank5_reload2_r;
5436         end
5437         if (builder_libresocsim_csrbank5_reload1_re) begin
5438                 main_libresocsim_reload_storage[15:8] <= builder_libresocsim_csrbank5_reload1_r;
5439         end
5440         if (builder_libresocsim_csrbank5_reload0_re) begin
5441                 main_libresocsim_reload_storage[7:0] <= builder_libresocsim_csrbank5_reload0_r;
5442         end
5443         main_libresocsim_reload_re <= builder_libresocsim_csrbank5_reload0_re;
5444         if (builder_libresocsim_csrbank5_en0_re) begin
5445                 main_libresocsim_en_storage <= builder_libresocsim_csrbank5_en0_r;
5446         end
5447         main_libresocsim_en_re <= builder_libresocsim_csrbank5_en0_re;
5448         if (builder_libresocsim_csrbank5_update_value0_re) begin
5449                 main_libresocsim_update_value_storage <= builder_libresocsim_csrbank5_update_value0_r;
5450         end
5451         main_libresocsim_update_value_re <= builder_libresocsim_csrbank5_update_value0_re;
5452         if (builder_libresocsim_csrbank5_ev_enable0_re) begin
5453                 main_libresocsim_eventmanager_storage <= builder_libresocsim_csrbank5_ev_enable0_r;
5454         end
5455         main_libresocsim_eventmanager_re <= builder_libresocsim_csrbank5_ev_enable0_re;
5456         builder_libresocsim_interface6_bank_bus_dat_r <= 1'd0;
5457         if (builder_libresocsim_csrbank6_sel) begin
5458                 case (builder_libresocsim_interface6_bank_bus_adr[2:0])
5459                         1'd0: begin
5460                                 builder_libresocsim_interface6_bank_bus_dat_r <= main_rxtx_w;
5461                         end
5462                         1'd1: begin
5463                                 builder_libresocsim_interface6_bank_bus_dat_r <= builder_libresocsim_csrbank6_txfull_w;
5464                         end
5465                         2'd2: begin
5466                                 builder_libresocsim_interface6_bank_bus_dat_r <= builder_libresocsim_csrbank6_rxempty_w;
5467                         end
5468                         2'd3: begin
5469                                 builder_libresocsim_interface6_bank_bus_dat_r <= main_eventmanager_status_w;
5470                         end
5471                         3'd4: begin
5472                                 builder_libresocsim_interface6_bank_bus_dat_r <= main_eventmanager_pending_w;
5473                         end
5474                         3'd5: begin
5475                                 builder_libresocsim_interface6_bank_bus_dat_r <= builder_libresocsim_csrbank6_ev_enable0_w;
5476                         end
5477                         3'd6: begin
5478                                 builder_libresocsim_interface6_bank_bus_dat_r <= builder_libresocsim_csrbank6_txempty_w;
5479                         end
5480                         3'd7: begin
5481                                 builder_libresocsim_interface6_bank_bus_dat_r <= builder_libresocsim_csrbank6_rxfull_w;
5482                         end
5483                 endcase
5484         end
5485         if (builder_libresocsim_csrbank6_ev_enable0_re) begin
5486                 main_eventmanager_storage[1:0] <= builder_libresocsim_csrbank6_ev_enable0_r;
5487         end
5488         main_eventmanager_re <= builder_libresocsim_csrbank6_ev_enable0_re;
5489         builder_libresocsim_interface7_bank_bus_dat_r <= 1'd0;
5490         if (builder_libresocsim_csrbank7_sel) begin
5491                 case (builder_libresocsim_interface7_bank_bus_adr[1:0])
5492                         1'd0: begin
5493                                 builder_libresocsim_interface7_bank_bus_dat_r <= builder_libresocsim_csrbank7_tuning_word3_w;
5494                         end
5495                         1'd1: begin
5496                                 builder_libresocsim_interface7_bank_bus_dat_r <= builder_libresocsim_csrbank7_tuning_word2_w;
5497                         end
5498                         2'd2: begin
5499                                 builder_libresocsim_interface7_bank_bus_dat_r <= builder_libresocsim_csrbank7_tuning_word1_w;
5500                         end
5501                         2'd3: begin
5502                                 builder_libresocsim_interface7_bank_bus_dat_r <= builder_libresocsim_csrbank7_tuning_word0_w;
5503                         end
5504                 endcase
5505         end
5506         if (builder_libresocsim_csrbank7_tuning_word3_re) begin
5507                 main_uart_phy_storage[31:24] <= builder_libresocsim_csrbank7_tuning_word3_r;
5508         end
5509         if (builder_libresocsim_csrbank7_tuning_word2_re) begin
5510                 main_uart_phy_storage[23:16] <= builder_libresocsim_csrbank7_tuning_word2_r;
5511         end
5512         if (builder_libresocsim_csrbank7_tuning_word1_re) begin
5513                 main_uart_phy_storage[15:8] <= builder_libresocsim_csrbank7_tuning_word1_r;
5514         end
5515         if (builder_libresocsim_csrbank7_tuning_word0_re) begin
5516                 main_uart_phy_storage[7:0] <= builder_libresocsim_csrbank7_tuning_word0_r;
5517         end
5518         main_uart_phy_re <= builder_libresocsim_csrbank7_tuning_word0_re;
5519         if (sys_rst_1) begin
5520                 main_libresocsim_reset_storage <= 1'd0;
5521                 main_libresocsim_reset_re <= 1'd0;
5522                 main_libresocsim_scratch_storage <= 32'd305419896;
5523                 main_libresocsim_scratch_re <= 1'd0;
5524                 main_libresocsim_bus_errors <= 32'd0;
5525                 main_libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5526                 main_libresocsim_converter0_counter <= 1'd0;
5527                 main_libresocsim_converter1_counter <= 1'd0;
5528                 main_libresocsim_ram_bus_ack <= 1'd0;
5529                 main_libresocsim_load_storage <= 32'd0;
5530                 main_libresocsim_load_re <= 1'd0;
5531                 main_libresocsim_reload_storage <= 32'd0;
5532                 main_libresocsim_reload_re <= 1'd0;
5533                 main_libresocsim_en_storage <= 1'd0;
5534                 main_libresocsim_en_re <= 1'd0;
5535                 main_libresocsim_update_value_storage <= 1'd0;
5536                 main_libresocsim_update_value_re <= 1'd0;
5537                 main_libresocsim_value_status <= 32'd0;
5538                 main_libresocsim_zero_pending <= 1'd0;
5539                 main_libresocsim_zero_old_trigger <= 1'd0;
5540                 main_libresocsim_eventmanager_storage <= 1'd0;
5541                 main_libresocsim_eventmanager_re <= 1'd0;
5542                 main_libresocsim_value <= 32'd0;
5543                 main_ram_bus_ram_bus_ack <= 1'd0;
5544                 main_dfi_p0_rddata_valid <= 1'd0;
5545                 main_rddata_en <= 3'd0;
5546                 main_sdram_storage <= 4'd1;
5547                 main_sdram_re <= 1'd0;
5548                 main_sdram_command_storage <= 6'd0;
5549                 main_sdram_command_re <= 1'd0;
5550                 main_sdram_address_re <= 1'd0;
5551                 main_sdram_baddress_re <= 1'd0;
5552                 main_sdram_wrdata_re <= 1'd0;
5553                 main_sdram_status <= 16'd0;
5554                 main_sdram_dfi_p0_address <= 13'd0;
5555                 main_sdram_dfi_p0_bank <= 2'd0;
5556                 main_sdram_dfi_p0_cas_n <= 1'd1;
5557                 main_sdram_dfi_p0_cs_n <= 1'd1;
5558                 main_sdram_dfi_p0_ras_n <= 1'd1;
5559                 main_sdram_dfi_p0_we_n <= 1'd1;
5560                 main_sdram_dfi_p0_wrdata_en <= 1'd0;
5561                 main_sdram_dfi_p0_rddata_en <= 1'd0;
5562                 main_sdram_timer_count1 <= 10'd781;
5563                 main_sdram_postponer_req_o <= 1'd0;
5564                 main_sdram_postponer_count <= 1'd0;
5565                 main_sdram_sequencer_done1 <= 1'd0;
5566                 main_sdram_sequencer_counter <= 4'd0;
5567                 main_sdram_sequencer_count <= 1'd0;
5568                 main_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;
5569                 main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;
5570                 main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;
5571                 main_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
5572                 main_sdram_bankmachine0_row <= 13'd0;
5573                 main_sdram_bankmachine0_row_opened <= 1'd0;
5574                 main_sdram_bankmachine0_twtpcon_ready <= 1'd0;
5575                 main_sdram_bankmachine0_twtpcon_count <= 3'd0;
5576                 main_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;
5577                 main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;
5578                 main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;
5579                 main_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
5580                 main_sdram_bankmachine1_row <= 13'd0;
5581                 main_sdram_bankmachine1_row_opened <= 1'd0;
5582                 main_sdram_bankmachine1_twtpcon_ready <= 1'd0;
5583                 main_sdram_bankmachine1_twtpcon_count <= 3'd0;
5584                 main_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;
5585                 main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;
5586                 main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;
5587                 main_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
5588                 main_sdram_bankmachine2_row <= 13'd0;
5589                 main_sdram_bankmachine2_row_opened <= 1'd0;
5590                 main_sdram_bankmachine2_twtpcon_ready <= 1'd0;
5591                 main_sdram_bankmachine2_twtpcon_count <= 3'd0;
5592                 main_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;
5593                 main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;
5594                 main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;
5595                 main_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
5596                 main_sdram_bankmachine3_row <= 13'd0;
5597                 main_sdram_bankmachine3_row_opened <= 1'd0;
5598                 main_sdram_bankmachine3_twtpcon_ready <= 1'd0;
5599                 main_sdram_bankmachine3_twtpcon_count <= 3'd0;
5600                 main_sdram_choose_cmd_grant <= 2'd0;
5601                 main_sdram_choose_req_grant <= 2'd0;
5602                 main_sdram_tccdcon_ready <= 1'd0;
5603                 main_sdram_tccdcon_count <= 1'd0;
5604                 main_sdram_twtrcon_ready <= 1'd0;
5605                 main_sdram_twtrcon_count <= 3'd0;
5606                 main_sdram_time0 <= 5'd0;
5607                 main_sdram_time1 <= 4'd0;
5608                 main_converter_counter <= 1'd0;
5609                 main_cmd_consumed <= 1'd0;
5610                 main_wdata_consumed <= 1'd0;
5611                 main_uart_phy_storage <= 32'd9895604;
5612                 main_uart_phy_re <= 1'd0;
5613                 main_uart_phy_sink_ready <= 1'd0;
5614                 main_uart_phy_uart_clk_txen <= 1'd0;
5615                 main_uart_phy_tx_busy <= 1'd0;
5616                 main_uart_phy_source_valid <= 1'd0;
5617                 main_uart_phy_uart_clk_rxen <= 1'd0;
5618                 main_uart_phy_rx_r <= 1'd0;
5619                 main_uart_phy_rx_busy <= 1'd0;
5620                 main_tx_pending <= 1'd0;
5621                 main_tx_old_trigger <= 1'd0;
5622                 main_rx_pending <= 1'd0;
5623                 main_rx_old_trigger <= 1'd0;
5624                 main_eventmanager_storage <= 2'd0;
5625                 main_eventmanager_re <= 1'd0;
5626                 main_tx_fifo_readable <= 1'd0;
5627                 main_tx_fifo_level0 <= 5'd0;
5628                 main_tx_fifo_produce <= 4'd0;
5629                 main_tx_fifo_consume <= 4'd0;
5630                 main_rx_fifo_readable <= 1'd0;
5631                 main_rx_fifo_level0 <= 5'd0;
5632                 main_rx_fifo_produce <= 4'd0;
5633                 main_rx_fifo_consume <= 4'd0;
5634                 main_gpio0_oe_storage <= 8'd0;
5635                 main_gpio0_oe_re <= 1'd0;
5636                 main_gpio0_out_storage <= 8'd0;
5637                 main_gpio0_out_re <= 1'd0;
5638                 main_gpio1_oe_storage <= 8'd0;
5639                 main_gpio1_oe_re <= 1'd0;
5640                 main_gpio1_out_storage <= 8'd0;
5641                 main_gpio1_out_re <= 1'd0;
5642                 main_dummy <= 20'd0;
5643                 main_i2c_storage <= 3'd0;
5644                 main_i2c_re <= 1'd0;
5645                 builder_subfragments_converter0_state <= 1'd0;
5646                 builder_subfragments_converter1_state <= 1'd0;
5647                 builder_subfragments_refresher_state <= 2'd0;
5648                 builder_subfragments_bankmachine0_state <= 3'd0;
5649                 builder_subfragments_bankmachine1_state <= 3'd0;
5650                 builder_subfragments_bankmachine2_state <= 3'd0;
5651                 builder_subfragments_bankmachine3_state <= 3'd0;
5652                 builder_subfragments_multiplexer_state <= 3'd0;
5653                 builder_subfragments_new_master_wdata_ready <= 1'd0;
5654                 builder_subfragments_new_master_rdata_valid0 <= 1'd0;
5655                 builder_subfragments_new_master_rdata_valid1 <= 1'd0;
5656                 builder_subfragments_new_master_rdata_valid2 <= 1'd0;
5657                 builder_subfragments_new_master_rdata_valid3 <= 1'd0;
5658                 builder_subfragments_state <= 1'd0;
5659                 builder_libresocsim_libresocsim_we <= 1'd0;
5660                 builder_libresocsim_grant <= 2'd0;
5661                 builder_libresocsim_slave_sel_r <= 10'd0;
5662                 builder_libresocsim_count <= 20'd1000000;
5663                 builder_libresocsim_state <= 2'd0;
5664         end
5665         builder_regs0 <= main_libresocsim_libresoc_constraintmanager_uart_rx;
5666         builder_regs1 <= builder_regs0;
5667 end
5668
5669 reg [31:0] mem[0:31];
5670 reg [4:0] memadr;
5671 always @(posedge sys_clk) begin
5672         if (main_libresocsim_we[0])
5673                 mem[main_libresocsim_adr][7:0] <= main_libresocsim_dat_w[7:0];
5674         if (main_libresocsim_we[1])
5675                 mem[main_libresocsim_adr][15:8] <= main_libresocsim_dat_w[15:8];
5676         if (main_libresocsim_we[2])
5677                 mem[main_libresocsim_adr][23:16] <= main_libresocsim_dat_w[23:16];
5678         if (main_libresocsim_we[3])
5679                 mem[main_libresocsim_adr][31:24] <= main_libresocsim_dat_w[31:24];
5680         memadr <= main_libresocsim_adr;
5681 end
5682
5683 assign main_libresocsim_dat_r = mem[memadr];
5684
5685 initial begin
5686         $readmemh("mem.init", mem);
5687 end
5688
5689 reg [31:0] mem_1[0:31];
5690 reg [4:0] memadr_1;
5691 always @(posedge sys_clk) begin
5692         if (main_ram_we[0])
5693                 mem_1[main_ram_adr][7:0] <= main_ram_dat_w[7:0];
5694         if (main_ram_we[1])
5695                 mem_1[main_ram_adr][15:8] <= main_ram_dat_w[15:8];
5696         if (main_ram_we[2])
5697                 mem_1[main_ram_adr][23:16] <= main_ram_dat_w[23:16];
5698         if (main_ram_we[3])
5699                 mem_1[main_ram_adr][31:24] <= main_ram_dat_w[31:24];
5700         memadr_1 <= main_ram_adr;
5701 end
5702
5703 assign main_ram_dat_r = mem_1[memadr_1];
5704
5705 initial begin
5706         $readmemh("mem_1.init", mem_1);
5707 end
5708
5709 reg [24:0] storage[0:7];
5710 reg [24:0] memdat;
5711 always @(posedge sys_clk) begin
5712         if (main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
5713                 storage[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
5714         memdat <= storage[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
5715 end
5716
5717 always @(posedge sys_clk) begin
5718 end
5719
5720 assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
5721 assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
5722
5723 reg [24:0] storage_1[0:7];
5724 reg [24:0] memdat_1;
5725 always @(posedge sys_clk) begin
5726         if (main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
5727                 storage_1[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
5728         memdat_1 <= storage_1[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
5729 end
5730
5731 always @(posedge sys_clk) begin
5732 end
5733
5734 assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
5735 assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
5736
5737 reg [24:0] storage_2[0:7];
5738 reg [24:0] memdat_2;
5739 always @(posedge sys_clk) begin
5740         if (main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
5741                 storage_2[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
5742         memdat_2 <= storage_2[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
5743 end
5744
5745 always @(posedge sys_clk) begin
5746 end
5747
5748 assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
5749 assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
5750
5751 reg [24:0] storage_3[0:7];
5752 reg [24:0] memdat_3;
5753 always @(posedge sys_clk) begin
5754         if (main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
5755                 storage_3[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
5756         memdat_3 <= storage_3[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
5757 end
5758
5759 always @(posedge sys_clk) begin
5760 end
5761
5762 assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
5763 assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
5764
5765 reg [9:0] storage_4[0:15];
5766 reg [9:0] memdat_4;
5767 reg [9:0] memdat_5;
5768 always @(posedge sys_clk) begin
5769         if (main_tx_fifo_wrport_we)
5770                 storage_4[main_tx_fifo_wrport_adr] <= main_tx_fifo_wrport_dat_w;
5771         memdat_4 <= storage_4[main_tx_fifo_wrport_adr];
5772 end
5773
5774 always @(posedge sys_clk) begin
5775         if (main_tx_fifo_rdport_re)
5776                 memdat_5 <= storage_4[main_tx_fifo_rdport_adr];
5777 end
5778
5779 assign main_tx_fifo_wrport_dat_r = memdat_4;
5780 assign main_tx_fifo_rdport_dat_r = memdat_5;
5781
5782 reg [9:0] storage_5[0:15];
5783 reg [9:0] memdat_6;
5784 reg [9:0] memdat_7;
5785 always @(posedge sys_clk) begin
5786         if (main_rx_fifo_wrport_we)
5787                 storage_5[main_rx_fifo_wrport_adr] <= main_rx_fifo_wrport_dat_w;
5788         memdat_6 <= storage_5[main_rx_fifo_wrport_adr];
5789 end
5790
5791 always @(posedge sys_clk) begin
5792         if (main_rx_fifo_rdport_re)
5793                 memdat_7 <= storage_5[main_rx_fifo_rdport_adr];
5794 end
5795
5796 assign main_rx_fifo_wrport_dat_r = memdat_6;
5797 assign main_rx_fifo_rdport_dat_r = memdat_7;
5798
5799 test_issuer test_issuer(
5800         .TAP_bus__tck(main_libresocsim_libresoc_jtag_tck),
5801         .TAP_bus__tdi(main_libresocsim_libresoc_jtag_tdi),
5802         .TAP_bus__tms(main_libresocsim_libresoc_jtag_tms),
5803         .clk(sys_clk),
5804         .clk_24_i(main_libresocsim_libresoc_pll_24_i),
5805         .clk_sel_i(main_libresocsim_libresoc_clk_sel),
5806         .core_bigendian_i(1'd0),
5807         .dbus__ack(main_libresocsim_libresoc_dbus_ack),
5808         .dbus__bte(1'd0),
5809         .dbus__cti(1'd0),
5810         .dbus__dat_r(main_libresocsim_libresoc_dbus_dat_r),
5811         .dbus__err(main_libresocsim_libresoc_dbus_err),
5812         .eint_0__pad__i(eint_0),
5813         .eint_1__pad__i(eint_1),
5814         .eint_2__pad__i(eint_2),
5815         .gpio_e10__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[10]),
5816         .gpio_e10__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[10]),
5817         .gpio_e10__pad__i(gpio_i[10]),
5818         .gpio_e11__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[11]),
5819         .gpio_e11__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[11]),
5820         .gpio_e11__pad__i(gpio_i[11]),
5821         .gpio_e12__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[12]),
5822         .gpio_e12__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[12]),
5823         .gpio_e12__pad__i(gpio_i[12]),
5824         .gpio_e13__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[13]),
5825         .gpio_e13__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[13]),
5826         .gpio_e13__pad__i(gpio_i[13]),
5827         .gpio_e14__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[14]),
5828         .gpio_e14__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[14]),
5829         .gpio_e14__pad__i(gpio_i[14]),
5830         .gpio_e15__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[15]),
5831         .gpio_e15__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[15]),
5832         .gpio_e15__pad__i(gpio_i[15]),
5833         .gpio_e8__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[8]),
5834         .gpio_e8__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[8]),
5835         .gpio_e8__pad__i(gpio_i[8]),
5836         .gpio_e9__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[9]),
5837         .gpio_e9__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[9]),
5838         .gpio_e9__pad__i(gpio_i[9]),
5839         .gpio_s0__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[0]),
5840         .gpio_s0__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[0]),
5841         .gpio_s0__pad__i(gpio_i[0]),
5842         .gpio_s1__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[1]),
5843         .gpio_s1__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[1]),
5844         .gpio_s1__pad__i(gpio_i[1]),
5845         .gpio_s2__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[2]),
5846         .gpio_s2__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[2]),
5847         .gpio_s2__pad__i(gpio_i[2]),
5848         .gpio_s3__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[3]),
5849         .gpio_s3__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[3]),
5850         .gpio_s3__pad__i(gpio_i[3]),
5851         .gpio_s4__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[4]),
5852         .gpio_s4__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[4]),
5853         .gpio_s4__pad__i(gpio_i[4]),
5854         .gpio_s5__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[5]),
5855         .gpio_s5__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[5]),
5856         .gpio_s5__pad__i(gpio_i[5]),
5857         .gpio_s6__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[6]),
5858         .gpio_s6__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[6]),
5859         .gpio_s6__pad__i(gpio_i[6]),
5860         .gpio_s7__core__o(main_libresocsim_libresoc_constraintmanager_gpio_o[7]),
5861         .gpio_s7__core__oe(main_libresocsim_libresoc_constraintmanager_gpio_oe[7]),
5862         .gpio_s7__pad__i(gpio_i[7]),
5863         .ibus__ack(main_libresocsim_libresoc_ibus_ack),
5864         .ibus__bte(1'd0),
5865         .ibus__cti(1'd0),
5866         .ibus__dat_r(main_libresocsim_libresoc_ibus_dat_r),
5867         .ibus__err(main_libresocsim_libresoc_ibus_err),
5868         .icp_wb__adr(main_libresocsim_libresoc_xics_icp_adr),
5869         .icp_wb__cyc(main_libresocsim_libresoc_xics_icp_cyc),
5870         .icp_wb__dat_w(main_libresocsim_libresoc_xics_icp_dat_w),
5871         .icp_wb__sel(main_libresocsim_libresoc_xics_icp_sel),
5872         .icp_wb__stb(main_libresocsim_libresoc_xics_icp_stb),
5873         .icp_wb__we(main_libresocsim_libresoc_xics_icp_we),
5874         .ics_wb__adr(main_libresocsim_libresoc_xics_ics_adr),
5875         .ics_wb__cyc(main_libresocsim_libresoc_xics_ics_cyc),
5876         .ics_wb__dat_w(main_libresocsim_libresoc_xics_ics_dat_w),
5877         .ics_wb__sel(main_libresocsim_libresoc_xics_ics_sel),
5878         .ics_wb__stb(main_libresocsim_libresoc_xics_ics_stb),
5879         .ics_wb__we(main_libresocsim_libresoc_xics_ics_we),
5880         .int_level_i(main_libresocsim_libresoc_interrupt),
5881         .jtag_wb__ack(main_libresocsim_libresoc_jtag_wb_ack),
5882         .jtag_wb__dat_r(main_libresocsim_libresoc_jtag_wb_dat_r),
5883         .jtag_wb__err(main_libresocsim_libresoc_jtag_wb_err),
5884         .mspi0_clk__core__o(main_libresocsim_libresoc_constraintmanager_spimaster_clk),
5885         .mspi0_cs_n__core__o(main_libresocsim_libresoc_constraintmanager_spimaster_cs_n),
5886         .mspi0_miso__pad__i(spimaster_miso),
5887         .mspi0_mosi__core__o(main_libresocsim_libresoc_constraintmanager_spimaster_mosi),
5888         .mtwi_scl__core__o(main_libresocsim_libresoc_constraintmanager_i2c_scl),
5889         .mtwi_sda__core__o(main_libresocsim_libresoc_constraintmanager_i2c_sda_o),
5890         .mtwi_sda__core__oe(main_libresocsim_libresoc_constraintmanager_i2c_sda_oe),
5891         .mtwi_sda__pad__i(i2c_sda_i),
5892         .pc_i(main_libresocsim_libresoc0),
5893         .pc_i_ok(1'd0),
5894         .rst((sys_rst_1 | main_libresocsim_libresoc_reset)),
5895         .sdr_a_0__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[0]),
5896         .sdr_a_10__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[10]),
5897         .sdr_a_11__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[11]),
5898         .sdr_a_12__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[12]),
5899         .sdr_a_1__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[1]),
5900         .sdr_a_2__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[2]),
5901         .sdr_a_3__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[3]),
5902         .sdr_a_4__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[4]),
5903         .sdr_a_5__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[5]),
5904         .sdr_a_6__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[6]),
5905         .sdr_a_7__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[7]),
5906         .sdr_a_8__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[8]),
5907         .sdr_a_9__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[9]),
5908         .sdr_ba_0__core__o(main_libresocsim_libresoc_constraintmanager_sdram_ba[0]),
5909         .sdr_ba_1__core__o(main_libresocsim_libresoc_constraintmanager_sdram_ba[1]),
5910         .sdr_cas_n__core__o(main_libresocsim_libresoc_constraintmanager_sdram_cas_n),
5911         .sdr_cke__core__o(main_libresocsim_libresoc_constraintmanager_sdram_cke),
5912         .sdr_clock__core__o(main_libresocsim_libresoc_constraintmanager_sdram_clock),
5913         .sdr_cs_n__core__o(main_libresocsim_libresoc_constraintmanager_sdram_cs_n),
5914         .sdr_dm_0__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dm[0]),
5915         .sdr_dm_1__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dm[1]),
5916         .sdr_dq_0__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[0]),
5917         .sdr_dq_0__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[0]),
5918         .sdr_dq_0__pad__i(sdram_dq_i[0]),
5919         .sdr_dq_10__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[10]),
5920         .sdr_dq_10__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[10]),
5921         .sdr_dq_10__pad__i(sdram_dq_i[10]),
5922         .sdr_dq_11__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[11]),
5923         .sdr_dq_11__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[11]),
5924         .sdr_dq_11__pad__i(sdram_dq_i[11]),
5925         .sdr_dq_12__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[12]),
5926         .sdr_dq_12__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[12]),
5927         .sdr_dq_12__pad__i(sdram_dq_i[12]),
5928         .sdr_dq_13__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[13]),
5929         .sdr_dq_13__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[13]),
5930         .sdr_dq_13__pad__i(sdram_dq_i[13]),
5931         .sdr_dq_14__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[14]),
5932         .sdr_dq_14__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[14]),
5933         .sdr_dq_14__pad__i(sdram_dq_i[14]),
5934         .sdr_dq_15__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[15]),
5935         .sdr_dq_15__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[15]),
5936         .sdr_dq_15__pad__i(sdram_dq_i[15]),
5937         .sdr_dq_1__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[1]),
5938         .sdr_dq_1__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[1]),
5939         .sdr_dq_1__pad__i(sdram_dq_i[1]),
5940         .sdr_dq_2__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[2]),
5941         .sdr_dq_2__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[2]),
5942         .sdr_dq_2__pad__i(sdram_dq_i[2]),
5943         .sdr_dq_3__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[3]),
5944         .sdr_dq_3__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[3]),
5945         .sdr_dq_3__pad__i(sdram_dq_i[3]),
5946         .sdr_dq_4__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[4]),
5947         .sdr_dq_4__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[4]),
5948         .sdr_dq_4__pad__i(sdram_dq_i[4]),
5949         .sdr_dq_5__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[5]),
5950         .sdr_dq_5__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[5]),
5951         .sdr_dq_5__pad__i(sdram_dq_i[5]),
5952         .sdr_dq_6__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[6]),
5953         .sdr_dq_6__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[6]),
5954         .sdr_dq_6__pad__i(sdram_dq_i[6]),
5955         .sdr_dq_7__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[7]),
5956         .sdr_dq_7__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[7]),
5957         .sdr_dq_7__pad__i(sdram_dq_i[7]),
5958         .sdr_dq_8__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[8]),
5959         .sdr_dq_8__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[8]),
5960         .sdr_dq_8__pad__i(sdram_dq_i[8]),
5961         .sdr_dq_9__core__o(main_libresocsim_libresoc_constraintmanager_sdram_dq_o[9]),
5962         .sdr_dq_9__core__oe(main_libresocsim_libresoc_constraintmanager_sdram_dq_oe[9]),
5963         .sdr_dq_9__pad__i(sdram_dq_i[9]),
5964         .sdr_ras_n__core__o(main_libresocsim_libresoc_constraintmanager_sdram_ras_n),
5965         .sdr_we_n__core__o(main_libresocsim_libresoc_constraintmanager_sdram_we_n),
5966         .sram4k_0_wb__adr(main_libresocsim_libresoc_interface0_adr),
5967         .sram4k_0_wb__cyc(main_libresocsim_libresoc_interface0_cyc),
5968         .sram4k_0_wb__dat_w(main_libresocsim_libresoc_interface0_dat_w),
5969         .sram4k_0_wb__sel(main_libresocsim_libresoc_interface0_sel),
5970         .sram4k_0_wb__stb(main_libresocsim_libresoc_interface0_stb),
5971         .sram4k_0_wb__we(main_libresocsim_libresoc_interface0_we),
5972         .sram4k_1_wb__adr(main_libresocsim_libresoc_interface1_adr),
5973         .sram4k_1_wb__cyc(main_libresocsim_libresoc_interface1_cyc),
5974         .sram4k_1_wb__dat_w(main_libresocsim_libresoc_interface1_dat_w),
5975         .sram4k_1_wb__sel(main_libresocsim_libresoc_interface1_sel),
5976         .sram4k_1_wb__stb(main_libresocsim_libresoc_interface1_stb),
5977         .sram4k_1_wb__we(main_libresocsim_libresoc_interface1_we),
5978         .sram4k_2_wb__adr(main_libresocsim_libresoc_interface2_adr),
5979         .sram4k_2_wb__cyc(main_libresocsim_libresoc_interface2_cyc),
5980         .sram4k_2_wb__dat_w(main_libresocsim_libresoc_interface2_dat_w),
5981         .sram4k_2_wb__sel(main_libresocsim_libresoc_interface2_sel),
5982         .sram4k_2_wb__stb(main_libresocsim_libresoc_interface2_stb),
5983         .sram4k_2_wb__we(main_libresocsim_libresoc_interface2_we),
5984         .sram4k_3_wb__adr(main_libresocsim_libresoc_interface3_adr),
5985         .sram4k_3_wb__cyc(main_libresocsim_libresoc_interface3_cyc),
5986         .sram4k_3_wb__dat_w(main_libresocsim_libresoc_interface3_dat_w),
5987         .sram4k_3_wb__sel(main_libresocsim_libresoc_interface3_sel),
5988         .sram4k_3_wb__stb(main_libresocsim_libresoc_interface3_stb),
5989         .sram4k_3_wb__we(main_libresocsim_libresoc_interface3_we),
5990         .TAP_bus__tdo(main_libresocsim_libresoc_jtag_tdo),
5991         .busy_o(main_libresocsim_libresoc1),
5992         .dbus__adr(main_libresocsim_libresoc_dbus_adr),
5993         .dbus__cyc(main_libresocsim_libresoc_dbus_cyc),
5994         .dbus__dat_w(main_libresocsim_libresoc_dbus_dat_w),
5995         .dbus__sel(main_libresocsim_libresoc_dbus_sel),
5996         .dbus__stb(main_libresocsim_libresoc_dbus_stb),
5997         .dbus__we(main_libresocsim_libresoc_dbus_we),
5998         .eint_0__core__i(main_libresocsim_libresoc_constraintmanager_eint_0),
5999         .eint_1__core__i(main_libresocsim_libresoc_constraintmanager_eint_1),
6000         .eint_2__core__i(main_libresocsim_libresoc_constraintmanager_eint_2),
6001         .gpio_e10__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[10]),
6002         .gpio_e10__pad__o(gpio_o[10]),
6003         .gpio_e10__pad__oe(gpio_oe[10]),
6004         .gpio_e11__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[11]),
6005         .gpio_e11__pad__o(gpio_o[11]),
6006         .gpio_e11__pad__oe(gpio_oe[11]),
6007         .gpio_e12__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[12]),
6008         .gpio_e12__pad__o(gpio_o[12]),
6009         .gpio_e12__pad__oe(gpio_oe[12]),
6010         .gpio_e13__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[13]),
6011         .gpio_e13__pad__o(gpio_o[13]),
6012         .gpio_e13__pad__oe(gpio_oe[13]),
6013         .gpio_e14__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[14]),
6014         .gpio_e14__pad__o(gpio_o[14]),
6015         .gpio_e14__pad__oe(gpio_oe[14]),
6016         .gpio_e15__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[15]),
6017         .gpio_e15__pad__o(gpio_o[15]),
6018         .gpio_e15__pad__oe(gpio_oe[15]),
6019         .gpio_e8__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[8]),
6020         .gpio_e8__pad__o(gpio_o[8]),
6021         .gpio_e8__pad__oe(gpio_oe[8]),
6022         .gpio_e9__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[9]),
6023         .gpio_e9__pad__o(gpio_o[9]),
6024         .gpio_e9__pad__oe(gpio_oe[9]),
6025         .gpio_s0__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[0]),
6026         .gpio_s0__pad__o(gpio_o[0]),
6027         .gpio_s0__pad__oe(gpio_oe[0]),
6028         .gpio_s1__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[1]),
6029         .gpio_s1__pad__o(gpio_o[1]),
6030         .gpio_s1__pad__oe(gpio_oe[1]),
6031         .gpio_s2__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[2]),
6032         .gpio_s2__pad__o(gpio_o[2]),
6033         .gpio_s2__pad__oe(gpio_oe[2]),
6034         .gpio_s3__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[3]),
6035         .gpio_s3__pad__o(gpio_o[3]),
6036         .gpio_s3__pad__oe(gpio_oe[3]),
6037         .gpio_s4__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[4]),
6038         .gpio_s4__pad__o(gpio_o[4]),
6039         .gpio_s4__pad__oe(gpio_oe[4]),
6040         .gpio_s5__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[5]),
6041         .gpio_s5__pad__o(gpio_o[5]),
6042         .gpio_s5__pad__oe(gpio_oe[5]),
6043         .gpio_s6__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[6]),
6044         .gpio_s6__pad__o(gpio_o[6]),
6045         .gpio_s6__pad__oe(gpio_oe[6]),
6046         .gpio_s7__core__i(main_libresocsim_libresoc_constraintmanager_gpio_i[7]),
6047         .gpio_s7__pad__o(gpio_o[7]),
6048         .gpio_s7__pad__oe(gpio_oe[7]),
6049         .ibus__adr(main_libresocsim_libresoc_ibus_adr),
6050         .ibus__cyc(main_libresocsim_libresoc_ibus_cyc),
6051         .ibus__dat_w(main_libresocsim_libresoc_ibus_dat_w),
6052         .ibus__sel(main_libresocsim_libresoc_ibus_sel),
6053         .ibus__stb(main_libresocsim_libresoc_ibus_stb),
6054         .ibus__we(main_libresocsim_libresoc_ibus_we),
6055         .icp_wb__ack(main_libresocsim_libresoc_xics_icp_ack),
6056         .icp_wb__dat_r(main_libresocsim_libresoc_xics_icp_dat_r),
6057         .icp_wb__err(main_libresocsim_libresoc_xics_icp_err),
6058         .ics_wb__ack(main_libresocsim_libresoc_xics_ics_ack),
6059         .ics_wb__dat_r(main_libresocsim_libresoc_xics_ics_dat_r),
6060         .ics_wb__err(main_libresocsim_libresoc_xics_ics_err),
6061         .jtag_wb__adr(main_libresocsim_libresoc_jtag_wb_adr),
6062         .jtag_wb__cyc(main_libresocsim_libresoc_jtag_wb_cyc),
6063         .jtag_wb__dat_w(main_libresocsim_libresoc_jtag_wb_dat_w),
6064         .jtag_wb__sel(main_libresocsim_libresoc_jtag_wb_sel),
6065         .jtag_wb__stb(main_libresocsim_libresoc_jtag_wb_stb),
6066         .jtag_wb__we(main_libresocsim_libresoc_jtag_wb_we),
6067         .memerr_o(main_libresocsim_libresoc2),
6068         .mspi0_clk__pad__o(spimaster_clk),
6069         .mspi0_cs_n__pad__o(spimaster_cs_n),
6070         .mspi0_miso__core__i(main_libresocsim_libresoc_constraintmanager_spimaster_miso),
6071         .mspi0_mosi__pad__o(spimaster_mosi),
6072         .mtwi_scl__pad__o(i2c_scl),
6073         .mtwi_sda__core__i(main_libresocsim_libresoc_constraintmanager_i2c_sda_i),
6074         .mtwi_sda__pad__o(i2c_sda_o),
6075         .mtwi_sda__pad__oe(i2c_sda_oe),
6076         .pc_o(main_libresocsim_libresoc3),
6077         .pll_test_o(main_libresocsim_libresoc_pll_test_o),
6078         .pll_vco_o(main_libresocsim_libresoc_pll_vco_o),
6079         .pllclk_clk(pll_clk),
6080         .sdr_a_0__pad__o(sdram_a[0]),
6081         .sdr_a_10__pad__o(sdram_a[10]),
6082         .sdr_a_11__pad__o(sdram_a[11]),
6083         .sdr_a_12__pad__o(sdram_a[12]),
6084         .sdr_a_1__pad__o(sdram_a[1]),
6085         .sdr_a_2__pad__o(sdram_a[2]),
6086         .sdr_a_3__pad__o(sdram_a[3]),
6087         .sdr_a_4__pad__o(sdram_a[4]),
6088         .sdr_a_5__pad__o(sdram_a[5]),
6089         .sdr_a_6__pad__o(sdram_a[6]),
6090         .sdr_a_7__pad__o(sdram_a[7]),
6091         .sdr_a_8__pad__o(sdram_a[8]),
6092         .sdr_a_9__pad__o(sdram_a[9]),
6093         .sdr_ba_0__pad__o(sdram_ba[0]),
6094         .sdr_ba_1__pad__o(sdram_ba[1]),
6095         .sdr_cas_n__pad__o(sdram_cas_n),
6096         .sdr_cke__pad__o(sdram_cke),
6097         .sdr_clock__pad__o(sdram_clock),
6098         .sdr_cs_n__pad__o(sdram_cs_n),
6099         .sdr_dm_0__pad__o(sdram_dm[0]),
6100         .sdr_dm_1__pad__o(sdram_dm[1]),
6101         .sdr_dq_0__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[0]),
6102         .sdr_dq_0__pad__o(sdram_dq_o[0]),
6103         .sdr_dq_0__pad__oe(sdram_dq_oe[0]),
6104         .sdr_dq_10__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[10]),
6105         .sdr_dq_10__pad__o(sdram_dq_o[10]),
6106         .sdr_dq_10__pad__oe(sdram_dq_oe[10]),
6107         .sdr_dq_11__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[11]),
6108         .sdr_dq_11__pad__o(sdram_dq_o[11]),
6109         .sdr_dq_11__pad__oe(sdram_dq_oe[11]),
6110         .sdr_dq_12__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[12]),
6111         .sdr_dq_12__pad__o(sdram_dq_o[12]),
6112         .sdr_dq_12__pad__oe(sdram_dq_oe[12]),
6113         .sdr_dq_13__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[13]),
6114         .sdr_dq_13__pad__o(sdram_dq_o[13]),
6115         .sdr_dq_13__pad__oe(sdram_dq_oe[13]),
6116         .sdr_dq_14__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[14]),
6117         .sdr_dq_14__pad__o(sdram_dq_o[14]),
6118         .sdr_dq_14__pad__oe(sdram_dq_oe[14]),
6119         .sdr_dq_15__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[15]),
6120         .sdr_dq_15__pad__o(sdram_dq_o[15]),
6121         .sdr_dq_15__pad__oe(sdram_dq_oe[15]),
6122         .sdr_dq_1__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[1]),
6123         .sdr_dq_1__pad__o(sdram_dq_o[1]),
6124         .sdr_dq_1__pad__oe(sdram_dq_oe[1]),
6125         .sdr_dq_2__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[2]),
6126         .sdr_dq_2__pad__o(sdram_dq_o[2]),
6127         .sdr_dq_2__pad__oe(sdram_dq_oe[2]),
6128         .sdr_dq_3__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[3]),
6129         .sdr_dq_3__pad__o(sdram_dq_o[3]),
6130         .sdr_dq_3__pad__oe(sdram_dq_oe[3]),
6131         .sdr_dq_4__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[4]),
6132         .sdr_dq_4__pad__o(sdram_dq_o[4]),
6133         .sdr_dq_4__pad__oe(sdram_dq_oe[4]),
6134         .sdr_dq_5__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[5]),
6135         .sdr_dq_5__pad__o(sdram_dq_o[5]),
6136         .sdr_dq_5__pad__oe(sdram_dq_oe[5]),
6137         .sdr_dq_6__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[6]),
6138         .sdr_dq_6__pad__o(sdram_dq_o[6]),
6139         .sdr_dq_6__pad__oe(sdram_dq_oe[6]),
6140         .sdr_dq_7__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[7]),
6141         .sdr_dq_7__pad__o(sdram_dq_o[7]),
6142         .sdr_dq_7__pad__oe(sdram_dq_oe[7]),
6143         .sdr_dq_8__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[8]),
6144         .sdr_dq_8__pad__o(sdram_dq_o[8]),
6145         .sdr_dq_8__pad__oe(sdram_dq_oe[8]),
6146         .sdr_dq_9__core__i(main_libresocsim_libresoc_constraintmanager_sdram_dq_i[9]),
6147         .sdr_dq_9__pad__o(sdram_dq_o[9]),
6148         .sdr_dq_9__pad__oe(sdram_dq_oe[9]),
6149         .sdr_ras_n__pad__o(sdram_ras_n),
6150         .sdr_we_n__pad__o(sdram_we_n),
6151         .sram4k_0_wb__ack(main_libresocsim_libresoc_interface0_ack),
6152         .sram4k_0_wb__dat_r(main_libresocsim_libresoc_interface0_dat_r),
6153         .sram4k_1_wb__ack(main_libresocsim_libresoc_interface1_ack),
6154         .sram4k_1_wb__dat_r(main_libresocsim_libresoc_interface1_dat_r),
6155         .sram4k_2_wb__ack(main_libresocsim_libresoc_interface2_ack),
6156         .sram4k_2_wb__dat_r(main_libresocsim_libresoc_interface2_dat_r),
6157         .sram4k_3_wb__ack(main_libresocsim_libresoc_interface3_ack),
6158         .sram4k_3_wb__dat_r(main_libresocsim_libresoc_interface3_dat_r)
6159 );
6160
6161 endmodule