experiments9/non_generated/litex_ls180.v

   1 //--------------------------------------------------------------------------------
   2 // Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-09 00:25:38
   3 //--------------------------------------------------------------------------------
   4 module ls180(
   5         input wire uart_tx,
   6         input wire uart_rx,
   7         output wire i2c_scl,
   8         input wire i2c_sda_i,
   9         output wire i2c_sda_o,
  10         output wire i2c_sda_oe,
  11         output wire spimaster_clk,
  12         output wire spimaster_mosi,
  13         output wire spimaster_cs_n,
  14         input wire spimaster_miso,
  15         input wire [15:0] gpio_i,
  16         output wire [15:0] gpio_o,
  17         output wire [15:0] gpio_oe,
  18         input wire eint_0,
  19         input wire eint_1,
  20         input wire eint_2,
  21         output wire [12:0] sdram_a,
  22         input wire [15:0] sdram_dq_i,
  23         output wire [15:0] sdram_dq_o,
  24         output wire [15:0] sdram_dq_oe,
  25         output wire sdram_we_n,
  26         output wire sdram_ras_n,
  27         output wire sdram_cas_n,
  28         output wire sdram_cs_n,
  29         output wire sdram_cke,
  30         output wire [1:0] sdram_ba,
  31         output wire [1:0] sdram_dm,
  32         output wire sdram_clock,
  33         input wire sys_clk,
  34         input wire sys_rst,
  35         input wire jtag_tms,
  36         input wire jtag_tck,
  37         input wire jtag_tdi,
  38         output wire jtag_tdo,
  39         input wire [39:0] nc
  40 );
  41
  42 reg libresocsim_reset_storage = 1'd0;
  43 reg libresocsim_reset_re = 1'd0;
  44 reg [31:0] libresocsim_scratch_storage = 32'd305419896;
  45 reg libresocsim_scratch_re = 1'd0;
  46 wire [31:0] libresocsim_bus_errors_status;
  47 wire libresocsim_bus_errors_we;
  48 wire libresocsim_reset;
  49 wire libresocsim_bus_error;
  50 reg [31:0] libresocsim_bus_errors = 32'd0;
  51 wire libresocsim_libresoc_reset;
  52 reg [15:0] libresocsim_libresoc_interrupt = 16'd0;
  53 wire [28:0] libresocsim_libresoc_dbus_adr;
  54 wire [63:0] libresocsim_libresoc_dbus_dat_w;
  55 wire [63:0] libresocsim_libresoc_dbus_dat_r;
  56 wire [7:0] libresocsim_libresoc_dbus_sel;
  57 wire libresocsim_libresoc_dbus_cyc;
  58 wire libresocsim_libresoc_dbus_stb;
  59 reg libresocsim_libresoc_dbus_ack = 1'd0;
  60 wire libresocsim_libresoc_dbus_we;
  61 reg libresocsim_libresoc_dbus_err = 1'd0;
  62 wire [28:0] libresocsim_libresoc_ibus_adr;
  63 wire [63:0] libresocsim_libresoc_ibus_dat_w;
  64 wire [63:0] libresocsim_libresoc_ibus_dat_r;
  65 wire [7:0] libresocsim_libresoc_ibus_sel;
  66 wire libresocsim_libresoc_ibus_cyc;
  67 wire libresocsim_libresoc_ibus_stb;
  68 reg libresocsim_libresoc_ibus_ack = 1'd0;
  69 wire libresocsim_libresoc_ibus_we;
  70 reg libresocsim_libresoc_ibus_err = 1'd0;
  71 wire [29:0] libresocsim_libresoc_xics_icp_adr;
  72 wire [31:0] libresocsim_libresoc_xics_icp_dat_w;
  73 wire [31:0] libresocsim_libresoc_xics_icp_dat_r;
  74 wire [3:0] libresocsim_libresoc_xics_icp_sel;
  75 wire libresocsim_libresoc_xics_icp_cyc;
  76 wire libresocsim_libresoc_xics_icp_stb;
  77 wire libresocsim_libresoc_xics_icp_ack;
  78 wire libresocsim_libresoc_xics_icp_we;
  79 wire [2:0] libresocsim_libresoc_xics_icp_cti;
  80 wire [1:0] libresocsim_libresoc_xics_icp_bte;
  81 wire libresocsim_libresoc_xics_icp_err;
  82 wire [29:0] libresocsim_libresoc_xics_ics_adr;
  83 wire [31:0] libresocsim_libresoc_xics_ics_dat_w;
  84 wire [31:0] libresocsim_libresoc_xics_ics_dat_r;
  85 wire [3:0] libresocsim_libresoc_xics_ics_sel;
  86 wire libresocsim_libresoc_xics_ics_cyc;
  87 wire libresocsim_libresoc_xics_ics_stb;
  88 wire libresocsim_libresoc_xics_ics_ack;
  89 wire libresocsim_libresoc_xics_ics_we;
  90 wire [2:0] libresocsim_libresoc_xics_ics_cti;
  91 wire [1:0] libresocsim_libresoc_xics_ics_bte;
  92 wire libresocsim_libresoc_xics_ics_err;
  93 wire [29:0] libresocsim_libresoc_jtag_wb_adr;
  94 wire [31:0] libresocsim_libresoc_jtag_wb_dat_w;
  95 wire [31:0] libresocsim_libresoc_jtag_wb_dat_r;
  96 wire [3:0] libresocsim_libresoc_jtag_wb_sel;
  97 wire libresocsim_libresoc_jtag_wb_cyc;
  98 wire libresocsim_libresoc_jtag_wb_stb;
  99 wire libresocsim_libresoc_jtag_wb_ack;
 100 wire libresocsim_libresoc_jtag_wb_we;
 101 reg [2:0] libresocsim_libresoc_jtag_wb_cti = 3'd0;
 102 reg [1:0] libresocsim_libresoc_jtag_wb_bte = 2'd0;
 103 wire libresocsim_libresoc_jtag_wb_err;
 104 wire libresocsim_libresoc_jtag_tck;
 105 wire libresocsim_libresoc_jtag_tms;
 106 wire libresocsim_libresoc_jtag_tdi;
 107 wire libresocsim_libresoc_jtag_tdo;
 108 reg [63:0] libresocsim_libresoc0 = 64'd0;
 109 wire libresocsim_libresoc1;
 110 wire libresocsim_libresoc2;
 111 wire [63:0] libresocsim_libresoc3;
 112 reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
 113 reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
 114 wire libresocsim_libresoc_constraintmanager_i2c_scl;
 115 wire libresocsim_libresoc_constraintmanager_i2c_sda_i;
 116 wire libresocsim_libresoc_constraintmanager_i2c_sda_o;
 117 wire libresocsim_libresoc_constraintmanager_i2c_sda_oe;
 118 reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0;
 119 reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0;
 120 reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0;
 121 wire libresocsim_libresoc_constraintmanager_spimaster_miso;
 122 wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i;
 123 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0;
 124 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0;
 125 wire libresocsim_libresoc_constraintmanager_eint_0;
 126 wire libresocsim_libresoc_constraintmanager_eint_1;
 127 wire libresocsim_libresoc_constraintmanager_eint_2;
 128 reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0;
 129 wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i;
 130 reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0;
 131 reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_oe = 16'd0;
 132 reg libresocsim_libresoc_constraintmanager_sdram_we_n = 1'd0;
 133 reg libresocsim_libresoc_constraintmanager_sdram_ras_n = 1'd0;
 134 reg libresocsim_libresoc_constraintmanager_sdram_cas_n = 1'd0;
 135 reg libresocsim_libresoc_constraintmanager_sdram_cs_n = 1'd0;
 136 reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0;
 137 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0;
 138 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0;
 139 reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0;
 140 reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0;
 141 reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0;
 142 wire [31:0] libresocsim_interface0_converted_interface_dat_r;
 143 reg [3:0] libresocsim_interface0_converted_interface_sel = 4'd0;
 144 reg libresocsim_interface0_converted_interface_cyc = 1'd0;
 145 reg libresocsim_interface0_converted_interface_stb = 1'd0;
 146 wire libresocsim_interface0_converted_interface_ack;
 147 reg libresocsim_interface0_converted_interface_we = 1'd0;
 148 reg [2:0] libresocsim_interface0_converted_interface_cti = 3'd0;
 149 reg [1:0] libresocsim_interface0_converted_interface_bte = 2'd0;
 150 wire libresocsim_interface0_converted_interface_err;
 151 reg libresocsim_converter0_skip = 1'd0;
 152 reg libresocsim_converter0_counter = 1'd0;
 153 wire libresocsim_converter0_reset;
 154 reg [63:0] libresocsim_converter0_dat_r = 64'd0;
 155 reg [29:0] libresocsim_interface1_converted_interface_adr = 30'd0;
 156 reg [31:0] libresocsim_interface1_converted_interface_dat_w = 32'd0;
 157 wire [31:0] libresocsim_interface1_converted_interface_dat_r;
 158 reg [3:0] libresocsim_interface1_converted_interface_sel = 4'd0;
 159 reg libresocsim_interface1_converted_interface_cyc = 1'd0;
 160 reg libresocsim_interface1_converted_interface_stb = 1'd0;
 161 wire libresocsim_interface1_converted_interface_ack;
 162 reg libresocsim_interface1_converted_interface_we = 1'd0;
 163 reg [2:0] libresocsim_interface1_converted_interface_cti = 3'd0;
 164 reg [1:0] libresocsim_interface1_converted_interface_bte = 2'd0;
 165 wire libresocsim_interface1_converted_interface_err;
 166 reg libresocsim_converter1_skip = 1'd0;
 167 reg libresocsim_converter1_counter = 1'd0;
 168 wire libresocsim_converter1_reset;
 169 reg [63:0] libresocsim_converter1_dat_r = 64'd0;
 170 wire [29:0] libresocsim_ram_bus_adr;
 171 wire [31:0] libresocsim_ram_bus_dat_w;
 172 wire [31:0] libresocsim_ram_bus_dat_r;
 173 wire [3:0] libresocsim_ram_bus_sel;
 174 wire libresocsim_ram_bus_cyc;
 175 wire libresocsim_ram_bus_stb;
 176 reg libresocsim_ram_bus_ack = 1'd0;
 177 wire libresocsim_ram_bus_we;
 178 wire [2:0] libresocsim_ram_bus_cti;
 179 wire [1:0] libresocsim_ram_bus_bte;
 180 reg libresocsim_ram_bus_err = 1'd0;
 181 wire [6:0] libresocsim_adr;
 182 wire [31:0] libresocsim_dat_r;
 183 reg [3:0] libresocsim_we = 4'd0;
 184 wire [31:0] libresocsim_dat_w;
 185 reg [31:0] libresocsim_load_storage = 32'd0;
 186 reg libresocsim_load_re = 1'd0;
 187 reg [31:0] libresocsim_reload_storage = 32'd0;
 188 reg libresocsim_reload_re = 1'd0;
 189 reg libresocsim_en_storage = 1'd0;
 190 reg libresocsim_en_re = 1'd0;
 191 reg libresocsim_update_value_storage = 1'd0;
 192 reg libresocsim_update_value_re = 1'd0;
 193 reg [31:0] libresocsim_value_status = 32'd0;
 194 wire libresocsim_value_we;
 195 wire libresocsim_irq;
 196 wire libresocsim_zero_status;
 197 reg libresocsim_zero_pending = 1'd0;
 198 wire libresocsim_zero_trigger;
 199 reg libresocsim_zero_clear = 1'd0;
 200 reg libresocsim_zero_old_trigger = 1'd0;
 201 wire libresocsim_eventmanager_status_re;
 202 wire libresocsim_eventmanager_status_r;
 203 wire libresocsim_eventmanager_status_we;
 204 wire libresocsim_eventmanager_status_w;
 205 wire libresocsim_eventmanager_pending_re;
 206 wire libresocsim_eventmanager_pending_r;
 207 wire libresocsim_eventmanager_pending_we;
 208 wire libresocsim_eventmanager_pending_w;
 209 reg libresocsim_eventmanager_storage = 1'd0;
 210 reg libresocsim_eventmanager_re = 1'd0;
 211 reg [31:0] libresocsim_value = 32'd0;
 212 wire [29:0] ram_bus_ram_bus_adr;
 213 wire [31:0] ram_bus_ram_bus_dat_w;
 214 wire [31:0] ram_bus_ram_bus_dat_r;
 215 wire [3:0] ram_bus_ram_bus_sel;
 216 wire ram_bus_ram_bus_cyc;
 217 wire ram_bus_ram_bus_stb;
 218 reg ram_bus_ram_bus_ack = 1'd0;
 219 wire ram_bus_ram_bus_we;
 220 wire [2:0] ram_bus_ram_bus_cti;
 221 wire [1:0] ram_bus_ram_bus_bte;
 222 reg ram_bus_ram_bus_err = 1'd0;
 223 wire [4:0] ram_adr;
 224 wire [31:0] ram_dat_r;
 225 reg [3:0] ram_we = 4'd0;
 226 wire [31:0] ram_dat_w;
 227 wire sys_clk_1;
 228 wire sys_rst_1;
 229 wire por_clk;
 230 reg int_rst = 1'd1;
 231 wire [12:0] dfi_p0_address;
 232 wire [1:0] dfi_p0_bank;
 233 wire dfi_p0_cas_n;
 234 wire dfi_p0_cs_n;
 235 wire dfi_p0_ras_n;
 236 wire dfi_p0_we_n;
 237 wire dfi_p0_cke;
 238 wire dfi_p0_odt;
 239 wire dfi_p0_reset_n;
 240 wire dfi_p0_act_n;
 241 wire [15:0] dfi_p0_wrdata;
 242 wire dfi_p0_wrdata_en;
 243 wire [1:0] dfi_p0_wrdata_mask;
 244 wire dfi_p0_rddata_en;
 245 reg [15:0] dfi_p0_rddata = 16'd0;
 246 reg dfi_p0_rddata_valid = 1'd0;
 247 reg [2:0] rddata_en = 3'd0;
 248 wire [12:0] sdram_inti_p0_address;
 249 wire [1:0] sdram_inti_p0_bank;
 250 reg sdram_inti_p0_cas_n = 1'd1;
 251 reg sdram_inti_p0_cs_n = 1'd1;
 252 reg sdram_inti_p0_ras_n = 1'd1;
 253 reg sdram_inti_p0_we_n = 1'd1;
 254 wire sdram_inti_p0_cke;
 255 wire sdram_inti_p0_odt;
 256 wire sdram_inti_p0_reset_n;
 257 reg sdram_inti_p0_act_n = 1'd1;
 258 wire [15:0] sdram_inti_p0_wrdata;
 259 wire sdram_inti_p0_wrdata_en;
 260 wire [1:0] sdram_inti_p0_wrdata_mask;
 261 wire sdram_inti_p0_rddata_en;
 262 reg [15:0] sdram_inti_p0_rddata = 16'd0;
 263 reg sdram_inti_p0_rddata_valid = 1'd0;
 264 wire [12:0] sdram_slave_p0_address;
 265 wire [1:0] sdram_slave_p0_bank;
 266 wire sdram_slave_p0_cas_n;
 267 wire sdram_slave_p0_cs_n;
 268 wire sdram_slave_p0_ras_n;
 269 wire sdram_slave_p0_we_n;
 270 wire sdram_slave_p0_cke;
 271 wire sdram_slave_p0_odt;
 272 wire sdram_slave_p0_reset_n;
 273 wire sdram_slave_p0_act_n;
 274 wire [15:0] sdram_slave_p0_wrdata;
 275 wire sdram_slave_p0_wrdata_en;
 276 wire [1:0] sdram_slave_p0_wrdata_mask;
 277 wire sdram_slave_p0_rddata_en;
 278 reg [15:0] sdram_slave_p0_rddata = 16'd0;
 279 reg sdram_slave_p0_rddata_valid = 1'd0;
 280 reg [12:0] sdram_master_p0_address = 13'd0;
 281 reg [1:0] sdram_master_p0_bank = 2'd0;
 282 reg sdram_master_p0_cas_n = 1'd1;
 283 reg sdram_master_p0_cs_n = 1'd1;
 284 reg sdram_master_p0_ras_n = 1'd1;
 285 reg sdram_master_p0_we_n = 1'd1;
 286 reg sdram_master_p0_cke = 1'd0;
 287 reg sdram_master_p0_odt = 1'd0;
 288 reg sdram_master_p0_reset_n = 1'd0;
 289 reg sdram_master_p0_act_n = 1'd1;
 290 reg [15:0] sdram_master_p0_wrdata = 16'd0;
 291 reg sdram_master_p0_wrdata_en = 1'd0;
 292 reg [1:0] sdram_master_p0_wrdata_mask = 2'd0;
 293 reg sdram_master_p0_rddata_en = 1'd0;
 294 wire [15:0] sdram_master_p0_rddata;
 295 wire sdram_master_p0_rddata_valid;
 296 wire sdram_sel;
 297 wire sdram_cke_1;
 298 wire sdram_odt;
 299 wire sdram_reset_n;
 300 reg [3:0] sdram_storage = 4'd1;
 301 reg sdram_re = 1'd0;
 302 reg [5:0] sdram_command_storage = 6'd0;
 303 reg sdram_command_re = 1'd0;
 304 wire sdram_command_issue_re;
 305 wire sdram_command_issue_r;
 306 wire sdram_command_issue_we;
 307 reg sdram_command_issue_w = 1'd0;
 308 reg [12:0] sdram_address_storage = 13'd0;
 309 reg sdram_address_re = 1'd0;
 310 reg [1:0] sdram_baddress_storage = 2'd0;
 311 reg sdram_baddress_re = 1'd0;
 312 reg [15:0] sdram_wrdata_storage = 16'd0;
 313 reg sdram_wrdata_re = 1'd0;
 314 reg [15:0] sdram_status = 16'd0;
 315 wire sdram_we;
 316 wire sdram_interface_bank0_valid;
 317 wire sdram_interface_bank0_ready;
 318 wire sdram_interface_bank0_we;
 319 wire [21:0] sdram_interface_bank0_addr;
 320 wire sdram_interface_bank0_lock;
 321 wire sdram_interface_bank0_wdata_ready;
 322 wire sdram_interface_bank0_rdata_valid;
 323 wire sdram_interface_bank1_valid;
 324 wire sdram_interface_bank1_ready;
 325 wire sdram_interface_bank1_we;
 326 wire [21:0] sdram_interface_bank1_addr;
 327 wire sdram_interface_bank1_lock;
 328 wire sdram_interface_bank1_wdata_ready;
 329 wire sdram_interface_bank1_rdata_valid;
 330 wire sdram_interface_bank2_valid;
 331 wire sdram_interface_bank2_ready;
 332 wire sdram_interface_bank2_we;
 333 wire [21:0] sdram_interface_bank2_addr;
 334 wire sdram_interface_bank2_lock;
 335 wire sdram_interface_bank2_wdata_ready;
 336 wire sdram_interface_bank2_rdata_valid;
 337 wire sdram_interface_bank3_valid;
 338 wire sdram_interface_bank3_ready;
 339 wire sdram_interface_bank3_we;
 340 wire [21:0] sdram_interface_bank3_addr;
 341 wire sdram_interface_bank3_lock;
 342 wire sdram_interface_bank3_wdata_ready;
 343 wire sdram_interface_bank3_rdata_valid;
 344 reg [15:0] sdram_interface_wdata = 16'd0;
 345 reg [1:0] sdram_interface_wdata_we = 2'd0;
 346 wire [15:0] sdram_interface_rdata;
 347 reg [12:0] sdram_dfi_p0_address = 13'd0;
 348 reg [1:0] sdram_dfi_p0_bank = 2'd0;
 349 reg sdram_dfi_p0_cas_n = 1'd1;
 350 reg sdram_dfi_p0_cs_n = 1'd1;
 351 reg sdram_dfi_p0_ras_n = 1'd1;
 352 reg sdram_dfi_p0_we_n = 1'd1;
 353 wire sdram_dfi_p0_cke;
 354 wire sdram_dfi_p0_odt;
 355 wire sdram_dfi_p0_reset_n;
 356 reg sdram_dfi_p0_act_n = 1'd1;
 357 wire [15:0] sdram_dfi_p0_wrdata;
 358 reg sdram_dfi_p0_wrdata_en = 1'd0;
 359 wire [1:0] sdram_dfi_p0_wrdata_mask;
 360 reg sdram_dfi_p0_rddata_en = 1'd0;
 361 wire [15:0] sdram_dfi_p0_rddata;
 362 wire sdram_dfi_p0_rddata_valid;
 363 reg sdram_cmd_valid = 1'd0;
 364 reg sdram_cmd_ready = 1'd0;
 365 reg sdram_cmd_last = 1'd0;
 366 reg [12:0] sdram_cmd_payload_a = 13'd0;
 367 reg [1:0] sdram_cmd_payload_ba = 2'd0;
 368 reg sdram_cmd_payload_cas = 1'd0;
 369 reg sdram_cmd_payload_ras = 1'd0;
 370 reg sdram_cmd_payload_we = 1'd0;
 371 reg sdram_cmd_payload_is_read = 1'd0;
 372 reg sdram_cmd_payload_is_write = 1'd0;
 373 wire sdram_wants_refresh;
 374 wire sdram_timer_wait;
 375 wire sdram_timer_done0;
 376 wire [9:0] sdram_timer_count0;
 377 wire sdram_timer_done1;
 378 reg [9:0] sdram_timer_count1 = 10'd781;
 379 wire sdram_postponer_req_i;
 380 reg sdram_postponer_req_o = 1'd0;
 381 reg sdram_postponer_count = 1'd0;
 382 reg sdram_sequencer_start0 = 1'd0;
 383 wire sdram_sequencer_done0;
 384 wire sdram_sequencer_start1;
 385 reg sdram_sequencer_done1 = 1'd0;
 386 reg [3:0] sdram_sequencer_counter = 4'd0;
 387 reg sdram_sequencer_count = 1'd0;
 388 wire sdram_bankmachine0_req_valid;
 389 wire sdram_bankmachine0_req_ready;
 390 wire sdram_bankmachine0_req_we;
 391 wire [21:0] sdram_bankmachine0_req_addr;
 392 wire sdram_bankmachine0_req_lock;
 393 reg sdram_bankmachine0_req_wdata_ready = 1'd0;
 394 reg sdram_bankmachine0_req_rdata_valid = 1'd0;
 395 wire sdram_bankmachine0_refresh_req;
 396 reg sdram_bankmachine0_refresh_gnt = 1'd0;
 397 reg sdram_bankmachine0_cmd_valid = 1'd0;
 398 reg sdram_bankmachine0_cmd_ready = 1'd0;
 399 reg [12:0] sdram_bankmachine0_cmd_payload_a = 13'd0;
 400 wire [1:0] sdram_bankmachine0_cmd_payload_ba;
 401 reg sdram_bankmachine0_cmd_payload_cas = 1'd0;
 402 reg sdram_bankmachine0_cmd_payload_ras = 1'd0;
 403 reg sdram_bankmachine0_cmd_payload_we = 1'd0;
 404 reg sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
 405 reg sdram_bankmachine0_cmd_payload_is_read = 1'd0;
 406 reg sdram_bankmachine0_cmd_payload_is_write = 1'd0;
 407 reg sdram_bankmachine0_auto_precharge = 1'd0;
 408 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
 409 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
 410 reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
 411 reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 412 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 413 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 414 wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
 415 wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
 416 wire sdram_bankmachine0_cmd_buffer_lookahead_source_first;
 417 wire sdram_bankmachine0_cmd_buffer_lookahead_source_last;
 418 wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
 419 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
 420 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
 421 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
 422 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 423 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 424 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 425 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
 426 reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;
 427 reg sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
 428 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;
 429 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;
 430 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;
 431 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 432 wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
 433 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
 434 wire sdram_bankmachine0_cmd_buffer_lookahead_do_read;
 435 wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
 436 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
 437 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
 438 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
 439 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
 440 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
 441 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 442 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 443 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
 444 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
 445 wire sdram_bankmachine0_cmd_buffer_sink_valid;
 446 wire sdram_bankmachine0_cmd_buffer_sink_ready;
 447 wire sdram_bankmachine0_cmd_buffer_sink_first;
 448 wire sdram_bankmachine0_cmd_buffer_sink_last;
 449 wire sdram_bankmachine0_cmd_buffer_sink_payload_we;
 450 wire [21:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr;
 451 reg sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
 452 wire sdram_bankmachine0_cmd_buffer_source_ready;
 453 reg sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
 454 reg sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
 455 reg sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
 456 reg [21:0] sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
 457 reg [12:0] sdram_bankmachine0_row = 13'd0;
 458 reg sdram_bankmachine0_row_opened = 1'd0;
 459 wire sdram_bankmachine0_row_hit;
 460 reg sdram_bankmachine0_row_open = 1'd0;
 461 reg sdram_bankmachine0_row_close = 1'd0;
 462 reg sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
 463 wire sdram_bankmachine0_twtpcon_valid;
 464 (* no_retiming = "true" *) reg sdram_bankmachine0_twtpcon_ready = 1'd0;
 465 reg [2:0] sdram_bankmachine0_twtpcon_count = 3'd0;
 466 wire sdram_bankmachine0_trccon_valid;
 467 (* no_retiming = "true" *) reg sdram_bankmachine0_trccon_ready = 1'd1;
 468 wire sdram_bankmachine0_trascon_valid;
 469 (* no_retiming = "true" *) reg sdram_bankmachine0_trascon_ready = 1'd1;
 470 wire sdram_bankmachine1_req_valid;
 471 wire sdram_bankmachine1_req_ready;
 472 wire sdram_bankmachine1_req_we;
 473 wire [21:0] sdram_bankmachine1_req_addr;
 474 wire sdram_bankmachine1_req_lock;
 475 reg sdram_bankmachine1_req_wdata_ready = 1'd0;
 476 reg sdram_bankmachine1_req_rdata_valid = 1'd0;
 477 wire sdram_bankmachine1_refresh_req;
 478 reg sdram_bankmachine1_refresh_gnt = 1'd0;
 479 reg sdram_bankmachine1_cmd_valid = 1'd0;
 480 reg sdram_bankmachine1_cmd_ready = 1'd0;
 481 reg [12:0] sdram_bankmachine1_cmd_payload_a = 13'd0;
 482 wire [1:0] sdram_bankmachine1_cmd_payload_ba;
 483 reg sdram_bankmachine1_cmd_payload_cas = 1'd0;
 484 reg sdram_bankmachine1_cmd_payload_ras = 1'd0;
 485 reg sdram_bankmachine1_cmd_payload_we = 1'd0;
 486 reg sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
 487 reg sdram_bankmachine1_cmd_payload_is_read = 1'd0;
 488 reg sdram_bankmachine1_cmd_payload_is_write = 1'd0;
 489 reg sdram_bankmachine1_auto_precharge = 1'd0;
 490 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
 491 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
 492 reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
 493 reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 494 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 495 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 496 wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
 497 wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
 498 wire sdram_bankmachine1_cmd_buffer_lookahead_source_first;
 499 wire sdram_bankmachine1_cmd_buffer_lookahead_source_last;
 500 wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
 501 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
 502 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
 503 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
 504 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 505 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 506 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 507 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
 508 reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;
 509 reg sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
 510 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;
 511 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;
 512 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;
 513 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 514 wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
 515 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
 516 wire sdram_bankmachine1_cmd_buffer_lookahead_do_read;
 517 wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
 518 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
 519 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
 520 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
 521 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
 522 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
 523 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 524 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 525 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
 526 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
 527 wire sdram_bankmachine1_cmd_buffer_sink_valid;
 528 wire sdram_bankmachine1_cmd_buffer_sink_ready;
 529 wire sdram_bankmachine1_cmd_buffer_sink_first;
 530 wire sdram_bankmachine1_cmd_buffer_sink_last;
 531 wire sdram_bankmachine1_cmd_buffer_sink_payload_we;
 532 wire [21:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr;
 533 reg sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
 534 wire sdram_bankmachine1_cmd_buffer_source_ready;
 535 reg sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
 536 reg sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
 537 reg sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
 538 reg [21:0] sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
 539 reg [12:0] sdram_bankmachine1_row = 13'd0;
 540 reg sdram_bankmachine1_row_opened = 1'd0;
 541 wire sdram_bankmachine1_row_hit;
 542 reg sdram_bankmachine1_row_open = 1'd0;
 543 reg sdram_bankmachine1_row_close = 1'd0;
 544 reg sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
 545 wire sdram_bankmachine1_twtpcon_valid;
 546 (* no_retiming = "true" *) reg sdram_bankmachine1_twtpcon_ready = 1'd0;
 547 reg [2:0] sdram_bankmachine1_twtpcon_count = 3'd0;
 548 wire sdram_bankmachine1_trccon_valid;
 549 (* no_retiming = "true" *) reg sdram_bankmachine1_trccon_ready = 1'd1;
 550 wire sdram_bankmachine1_trascon_valid;
 551 (* no_retiming = "true" *) reg sdram_bankmachine1_trascon_ready = 1'd1;
 552 wire sdram_bankmachine2_req_valid;
 553 wire sdram_bankmachine2_req_ready;
 554 wire sdram_bankmachine2_req_we;
 555 wire [21:0] sdram_bankmachine2_req_addr;
 556 wire sdram_bankmachine2_req_lock;
 557 reg sdram_bankmachine2_req_wdata_ready = 1'd0;
 558 reg sdram_bankmachine2_req_rdata_valid = 1'd0;
 559 wire sdram_bankmachine2_refresh_req;
 560 reg sdram_bankmachine2_refresh_gnt = 1'd0;
 561 reg sdram_bankmachine2_cmd_valid = 1'd0;
 562 reg sdram_bankmachine2_cmd_ready = 1'd0;
 563 reg [12:0] sdram_bankmachine2_cmd_payload_a = 13'd0;
 564 wire [1:0] sdram_bankmachine2_cmd_payload_ba;
 565 reg sdram_bankmachine2_cmd_payload_cas = 1'd0;
 566 reg sdram_bankmachine2_cmd_payload_ras = 1'd0;
 567 reg sdram_bankmachine2_cmd_payload_we = 1'd0;
 568 reg sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
 569 reg sdram_bankmachine2_cmd_payload_is_read = 1'd0;
 570 reg sdram_bankmachine2_cmd_payload_is_write = 1'd0;
 571 reg sdram_bankmachine2_auto_precharge = 1'd0;
 572 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
 573 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
 574 reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
 575 reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 576 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 577 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 578 wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
 579 wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
 580 wire sdram_bankmachine2_cmd_buffer_lookahead_source_first;
 581 wire sdram_bankmachine2_cmd_buffer_lookahead_source_last;
 582 wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
 583 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
 584 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
 585 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
 586 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 587 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 588 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 589 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
 590 reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;
 591 reg sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
 592 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;
 593 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;
 594 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;
 595 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 596 wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
 597 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
 598 wire sdram_bankmachine2_cmd_buffer_lookahead_do_read;
 599 wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
 600 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
 601 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
 602 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
 603 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
 604 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
 605 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 606 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 607 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
 608 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
 609 wire sdram_bankmachine2_cmd_buffer_sink_valid;
 610 wire sdram_bankmachine2_cmd_buffer_sink_ready;
 611 wire sdram_bankmachine2_cmd_buffer_sink_first;
 612 wire sdram_bankmachine2_cmd_buffer_sink_last;
 613 wire sdram_bankmachine2_cmd_buffer_sink_payload_we;
 614 wire [21:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr;
 615 reg sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
 616 wire sdram_bankmachine2_cmd_buffer_source_ready;
 617 reg sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
 618 reg sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
 619 reg sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
 620 reg [21:0] sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
 621 reg [12:0] sdram_bankmachine2_row = 13'd0;
 622 reg sdram_bankmachine2_row_opened = 1'd0;
 623 wire sdram_bankmachine2_row_hit;
 624 reg sdram_bankmachine2_row_open = 1'd0;
 625 reg sdram_bankmachine2_row_close = 1'd0;
 626 reg sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
 627 wire sdram_bankmachine2_twtpcon_valid;
 628 (* no_retiming = "true" *) reg sdram_bankmachine2_twtpcon_ready = 1'd0;
 629 reg [2:0] sdram_bankmachine2_twtpcon_count = 3'd0;
 630 wire sdram_bankmachine2_trccon_valid;
 631 (* no_retiming = "true" *) reg sdram_bankmachine2_trccon_ready = 1'd1;
 632 wire sdram_bankmachine2_trascon_valid;
 633 (* no_retiming = "true" *) reg sdram_bankmachine2_trascon_ready = 1'd1;
 634 wire sdram_bankmachine3_req_valid;
 635 wire sdram_bankmachine3_req_ready;
 636 wire sdram_bankmachine3_req_we;
 637 wire [21:0] sdram_bankmachine3_req_addr;
 638 wire sdram_bankmachine3_req_lock;
 639 reg sdram_bankmachine3_req_wdata_ready = 1'd0;
 640 reg sdram_bankmachine3_req_rdata_valid = 1'd0;
 641 wire sdram_bankmachine3_refresh_req;
 642 reg sdram_bankmachine3_refresh_gnt = 1'd0;
 643 reg sdram_bankmachine3_cmd_valid = 1'd0;
 644 reg sdram_bankmachine3_cmd_ready = 1'd0;
 645 reg [12:0] sdram_bankmachine3_cmd_payload_a = 13'd0;
 646 wire [1:0] sdram_bankmachine3_cmd_payload_ba;
 647 reg sdram_bankmachine3_cmd_payload_cas = 1'd0;
 648 reg sdram_bankmachine3_cmd_payload_ras = 1'd0;
 649 reg sdram_bankmachine3_cmd_payload_we = 1'd0;
 650 reg sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
 651 reg sdram_bankmachine3_cmd_payload_is_read = 1'd0;
 652 reg sdram_bankmachine3_cmd_payload_is_write = 1'd0;
 653 reg sdram_bankmachine3_auto_precharge = 1'd0;
 654 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
 655 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
 656 reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
 657 reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 658 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 659 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 660 wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
 661 wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
 662 wire sdram_bankmachine3_cmd_buffer_lookahead_source_first;
 663 wire sdram_bankmachine3_cmd_buffer_lookahead_source_last;
 664 wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
 665 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
 666 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
 667 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
 668 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 669 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 670 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 671 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
 672 reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;
 673 reg sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
 674 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;
 675 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;
 676 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;
 677 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 678 wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
 679 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
 680 wire sdram_bankmachine3_cmd_buffer_lookahead_do_read;
 681 wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
 682 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
 683 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
 684 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
 685 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
 686 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
 687 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 688 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 689 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
 690 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
 691 wire sdram_bankmachine3_cmd_buffer_sink_valid;
 692 wire sdram_bankmachine3_cmd_buffer_sink_ready;
 693 wire sdram_bankmachine3_cmd_buffer_sink_first;
 694 wire sdram_bankmachine3_cmd_buffer_sink_last;
 695 wire sdram_bankmachine3_cmd_buffer_sink_payload_we;
 696 wire [21:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr;
 697 reg sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
 698 wire sdram_bankmachine3_cmd_buffer_source_ready;
 699 reg sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
 700 reg sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
 701 reg sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
 702 reg [21:0] sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
 703 reg [12:0] sdram_bankmachine3_row = 13'd0;
 704 reg sdram_bankmachine3_row_opened = 1'd0;
 705 wire sdram_bankmachine3_row_hit;
 706 reg sdram_bankmachine3_row_open = 1'd0;
 707 reg sdram_bankmachine3_row_close = 1'd0;
 708 reg sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
 709 wire sdram_bankmachine3_twtpcon_valid;
 710 (* no_retiming = "true" *) reg sdram_bankmachine3_twtpcon_ready = 1'd0;
 711 reg [2:0] sdram_bankmachine3_twtpcon_count = 3'd0;
 712 wire sdram_bankmachine3_trccon_valid;
 713 (* no_retiming = "true" *) reg sdram_bankmachine3_trccon_ready = 1'd1;
 714 wire sdram_bankmachine3_trascon_valid;
 715 (* no_retiming = "true" *) reg sdram_bankmachine3_trascon_ready = 1'd1;
 716 wire sdram_ras_allowed;
 717 wire sdram_cas_allowed;
 718 reg sdram_choose_cmd_want_reads = 1'd0;
 719 reg sdram_choose_cmd_want_writes = 1'd0;
 720 reg sdram_choose_cmd_want_cmds = 1'd0;
 721 reg sdram_choose_cmd_want_activates = 1'd0;
 722 wire sdram_choose_cmd_cmd_valid;
 723 reg sdram_choose_cmd_cmd_ready = 1'd0;
 724 wire [12:0] sdram_choose_cmd_cmd_payload_a;
 725 wire [1:0] sdram_choose_cmd_cmd_payload_ba;
 726 reg sdram_choose_cmd_cmd_payload_cas = 1'd0;
 727 reg sdram_choose_cmd_cmd_payload_ras = 1'd0;
 728 reg sdram_choose_cmd_cmd_payload_we = 1'd0;
 729 wire sdram_choose_cmd_cmd_payload_is_cmd;
 730 wire sdram_choose_cmd_cmd_payload_is_read;
 731 wire sdram_choose_cmd_cmd_payload_is_write;
 732 reg [3:0] sdram_choose_cmd_valids = 4'd0;
 733 wire [3:0] sdram_choose_cmd_request;
 734 reg [1:0] sdram_choose_cmd_grant = 2'd0;
 735 wire sdram_choose_cmd_ce;
 736 reg sdram_choose_req_want_reads = 1'd0;
 737 reg sdram_choose_req_want_writes = 1'd0;
 738 wire sdram_choose_req_want_cmds;
 739 reg sdram_choose_req_want_activates = 1'd0;
 740 wire sdram_choose_req_cmd_valid;
 741 reg sdram_choose_req_cmd_ready = 1'd0;
 742 wire [12:0] sdram_choose_req_cmd_payload_a;
 743 wire [1:0] sdram_choose_req_cmd_payload_ba;
 744 reg sdram_choose_req_cmd_payload_cas = 1'd0;
 745 reg sdram_choose_req_cmd_payload_ras = 1'd0;
 746 reg sdram_choose_req_cmd_payload_we = 1'd0;
 747 wire sdram_choose_req_cmd_payload_is_cmd;
 748 wire sdram_choose_req_cmd_payload_is_read;
 749 wire sdram_choose_req_cmd_payload_is_write;
 750 reg [3:0] sdram_choose_req_valids = 4'd0;
 751 wire [3:0] sdram_choose_req_request;
 752 reg [1:0] sdram_choose_req_grant = 2'd0;
 753 wire sdram_choose_req_ce;
 754 reg [12:0] sdram_nop_a = 13'd0;
 755 reg [1:0] sdram_nop_ba = 2'd0;
 756 reg [1:0] sdram_steerer_sel = 2'd0;
 757 reg sdram_steerer0 = 1'd1;
 758 reg sdram_steerer1 = 1'd1;
 759 wire sdram_trrdcon_valid;
 760 (* no_retiming = "true" *) reg sdram_trrdcon_ready = 1'd1;
 761 wire sdram_tfawcon_valid;
 762 (* no_retiming = "true" *) reg sdram_tfawcon_ready = 1'd1;
 763 wire sdram_tccdcon_valid;
 764 (* no_retiming = "true" *) reg sdram_tccdcon_ready = 1'd0;
 765 reg sdram_tccdcon_count = 1'd0;
 766 wire sdram_twtrcon_valid;
 767 (* no_retiming = "true" *) reg sdram_twtrcon_ready = 1'd0;
 768 reg [2:0] sdram_twtrcon_count = 3'd0;
 769 wire sdram_read_available;
 770 wire sdram_write_available;
 771 reg sdram_en0 = 1'd0;
 772 wire sdram_max_time0;
 773 reg [4:0] sdram_time0 = 5'd0;
 774 reg sdram_en1 = 1'd0;
 775 wire sdram_max_time1;
 776 reg [3:0] sdram_time1 = 4'd0;
 777 wire sdram_go_to_refresh;
 778 wire port_flush;
 779 wire port_cmd_valid;
 780 wire port_cmd_ready;
 781 wire port_cmd_last;
 782 wire port_cmd_payload_we;
 783 wire [23:0] port_cmd_payload_addr;
 784 wire port_wdata_valid;
 785 wire port_wdata_ready;
 786 wire [15:0] port_wdata_payload_data;
 787 wire [1:0] port_wdata_payload_we;
 788 wire port_rdata_valid;
 789 wire port_rdata_ready;
 790 wire [15:0] port_rdata_payload_data;
 791 wire [29:0] wb_sdram_adr;
 792 wire [31:0] wb_sdram_dat_w;
 793 wire [31:0] wb_sdram_dat_r;
 794 wire [3:0] wb_sdram_sel;
 795 wire wb_sdram_cyc;
 796 wire wb_sdram_stb;
 797 reg wb_sdram_ack = 1'd0;
 798 wire wb_sdram_we;
 799 wire [2:0] wb_sdram_cti;
 800 wire [1:0] wb_sdram_bte;
 801 reg wb_sdram_err = 1'd0;
 802 reg [29:0] litedram_wb_adr = 30'd0;
 803 reg [15:0] litedram_wb_dat_w = 16'd0;
 804 wire [15:0] litedram_wb_dat_r;
 805 reg [1:0] litedram_wb_sel = 2'd0;
 806 reg litedram_wb_cyc = 1'd0;
 807 reg litedram_wb_stb = 1'd0;
 808 wire litedram_wb_ack;
 809 reg litedram_wb_we = 1'd0;
 810 reg converter_skip = 1'd0;
 811 reg converter_counter = 1'd0;
 812 wire converter_reset;
 813 reg [31:0] converter_dat_r = 32'd0;
 814 reg cmd_consumed = 1'd0;
 815 reg wdata_consumed = 1'd0;
 816 wire ack_cmd;
 817 wire ack_wdata;
 818 wire ack_rdata;
 819 reg [31:0] uart_phy_storage = 32'd9895604;
 820 reg uart_phy_re = 1'd0;
 821 wire uart_phy_sink_valid;
 822 reg uart_phy_sink_ready = 1'd0;
 823 wire uart_phy_sink_first;
 824 wire uart_phy_sink_last;
 825 wire [7:0] uart_phy_sink_payload_data;
 826 reg uart_phy_uart_clk_txen = 1'd0;
 827 reg [31:0] uart_phy_phase_accumulator_tx = 32'd0;
 828 reg [7:0] uart_phy_tx_reg = 8'd0;
 829 reg [3:0] uart_phy_tx_bitcount = 4'd0;
 830 reg uart_phy_tx_busy = 1'd0;
 831 reg uart_phy_source_valid = 1'd0;
 832 wire uart_phy_source_ready;
 833 reg uart_phy_source_first = 1'd0;
 834 reg uart_phy_source_last = 1'd0;
 835 reg [7:0] uart_phy_source_payload_data = 8'd0;
 836 reg uart_phy_uart_clk_rxen = 1'd0;
 837 reg [31:0] uart_phy_phase_accumulator_rx = 32'd0;
 838 wire uart_phy_rx;
 839 reg uart_phy_rx_r = 1'd0;
 840 reg [7:0] uart_phy_rx_reg = 8'd0;
 841 reg [3:0] uart_phy_rx_bitcount = 4'd0;
 842 reg uart_phy_rx_busy = 1'd0;
 843 wire rxtx_re;
 844 wire [7:0] rxtx_r;
 845 wire rxtx_we;
 846 wire [7:0] rxtx_w;
 847 wire txfull_status;
 848 wire txfull_we;
 849 wire rxempty_status;
 850 wire rxempty_we;
 851 wire irq;
 852 wire tx_status;
 853 reg tx_pending = 1'd0;
 854 wire tx_trigger;
 855 reg tx_clear = 1'd0;
 856 reg tx_old_trigger = 1'd0;
 857 wire rx_status;
 858 reg rx_pending = 1'd0;
 859 wire rx_trigger;
 860 reg rx_clear = 1'd0;
 861 reg rx_old_trigger = 1'd0;
 862 wire eventmanager_status_re;
 863 wire [1:0] eventmanager_status_r;
 864 wire eventmanager_status_we;
 865 reg [1:0] eventmanager_status_w = 2'd0;
 866 wire eventmanager_pending_re;
 867 wire [1:0] eventmanager_pending_r;
 868 wire eventmanager_pending_we;
 869 reg [1:0] eventmanager_pending_w = 2'd0;
 870 reg [1:0] eventmanager_storage = 2'd0;
 871 reg eventmanager_re = 1'd0;
 872 wire txempty_status;
 873 wire txempty_we;
 874 wire rxfull_status;
 875 wire rxfull_we;
 876 wire uart_sink_valid;
 877 wire uart_sink_ready;
 878 wire uart_sink_first;
 879 wire uart_sink_last;
 880 wire [7:0] uart_sink_payload_data;
 881 wire uart_source_valid;
 882 wire uart_source_ready;
 883 wire uart_source_first;
 884 wire uart_source_last;
 885 wire [7:0] uart_source_payload_data;
 886 wire tx_fifo_sink_valid;
 887 wire tx_fifo_sink_ready;
 888 reg tx_fifo_sink_first = 1'd0;
 889 reg tx_fifo_sink_last = 1'd0;
 890 wire [7:0] tx_fifo_sink_payload_data;
 891 wire tx_fifo_source_valid;
 892 wire tx_fifo_source_ready;
 893 wire tx_fifo_source_first;
 894 wire tx_fifo_source_last;
 895 wire [7:0] tx_fifo_source_payload_data;
 896 wire tx_fifo_re;
 897 reg tx_fifo_readable = 1'd0;
 898 wire tx_fifo_syncfifo_we;
 899 wire tx_fifo_syncfifo_writable;
 900 wire tx_fifo_syncfifo_re;
 901 wire tx_fifo_syncfifo_readable;
 902 wire [9:0] tx_fifo_syncfifo_din;
 903 wire [9:0] tx_fifo_syncfifo_dout;
 904 reg [4:0] tx_fifo_level0 = 5'd0;
 905 reg tx_fifo_replace = 1'd0;
 906 reg [3:0] tx_fifo_produce = 4'd0;
 907 reg [3:0] tx_fifo_consume = 4'd0;
 908 reg [3:0] tx_fifo_wrport_adr = 4'd0;
 909 wire [9:0] tx_fifo_wrport_dat_r;
 910 wire tx_fifo_wrport_we;
 911 wire [9:0] tx_fifo_wrport_dat_w;
 912 wire tx_fifo_do_read;
 913 wire [3:0] tx_fifo_rdport_adr;
 914 wire [9:0] tx_fifo_rdport_dat_r;
 915 wire tx_fifo_rdport_re;
 916 wire [4:0] tx_fifo_level1;
 917 wire [7:0] tx_fifo_fifo_in_payload_data;
 918 wire tx_fifo_fifo_in_first;
 919 wire tx_fifo_fifo_in_last;
 920 wire [7:0] tx_fifo_fifo_out_payload_data;
 921 wire tx_fifo_fifo_out_first;
 922 wire tx_fifo_fifo_out_last;
 923 wire rx_fifo_sink_valid;
 924 wire rx_fifo_sink_ready;
 925 wire rx_fifo_sink_first;
 926 wire rx_fifo_sink_last;
 927 wire [7:0] rx_fifo_sink_payload_data;
 928 wire rx_fifo_source_valid;
 929 wire rx_fifo_source_ready;
 930 wire rx_fifo_source_first;
 931 wire rx_fifo_source_last;
 932 wire [7:0] rx_fifo_source_payload_data;
 933 wire rx_fifo_re;
 934 reg rx_fifo_readable = 1'd0;
 935 wire rx_fifo_syncfifo_we;
 936 wire rx_fifo_syncfifo_writable;
 937 wire rx_fifo_syncfifo_re;
 938 wire rx_fifo_syncfifo_readable;
 939 wire [9:0] rx_fifo_syncfifo_din;
 940 wire [9:0] rx_fifo_syncfifo_dout;
 941 reg [4:0] rx_fifo_level0 = 5'd0;
 942 reg rx_fifo_replace = 1'd0;
 943 reg [3:0] rx_fifo_produce = 4'd0;
 944 reg [3:0] rx_fifo_consume = 4'd0;
 945 reg [3:0] rx_fifo_wrport_adr = 4'd0;
 946 wire [9:0] rx_fifo_wrport_dat_r;
 947 wire rx_fifo_wrport_we;
 948 wire [9:0] rx_fifo_wrport_dat_w;
 949 wire rx_fifo_do_read;
 950 wire [3:0] rx_fifo_rdport_adr;
 951 wire [9:0] rx_fifo_rdport_dat_r;
 952 wire rx_fifo_rdport_re;
 953 wire [4:0] rx_fifo_level1;
 954 wire [7:0] rx_fifo_fifo_in_payload_data;
 955 wire rx_fifo_fifo_in_first;
 956 wire rx_fifo_fifo_in_last;
 957 wire [7:0] rx_fifo_fifo_out_payload_data;
 958 wire rx_fifo_fifo_out_first;
 959 wire rx_fifo_fifo_out_last;
 960 reg reset = 1'd0;
 961 reg [7:0] gpio0_oe_storage = 8'd0;
 962 reg gpio0_oe_re = 1'd0;
 963 reg [7:0] gpio0_status = 8'd0;
 964 wire gpio0_we;
 965 reg [7:0] gpio0_out_storage = 8'd0;
 966 reg gpio0_out_re = 1'd0;
 967 reg [7:0] gpio0_pads_gpio0i = 8'd0;
 968 reg [7:0] gpio0_pads_gpio0o = 8'd0;
 969 reg [7:0] gpio0_pads_gpio0oe = 8'd0;
 970 reg [7:0] gpio1_oe_storage = 8'd0;
 971 reg gpio1_oe_re = 1'd0;
 972 reg [7:0] gpio1_status = 8'd0;
 973 wire gpio1_we;
 974 reg [7:0] gpio1_out_storage = 8'd0;
 975 reg gpio1_out_re = 1'd0;
 976 reg [7:0] gpio1_pads_gpio1i = 8'd0;
 977 reg [7:0] gpio1_pads_gpio1o = 8'd0;
 978 reg [7:0] gpio1_pads_gpio1oe = 8'd0;
 979 reg [2:0] eint_tmp = 3'd0;
 980 wire [39:0] nc_1;
 981 reg [39:0] dummy = 40'd0;
 982 wire i2c_scl_1;
 983 wire i2c_oe;
 984 wire i2c_sda0;
 985 reg [2:0] i2c_storage = 3'd0;
 986 reg i2c_re = 1'd0;
 987 wire i2c_sda1;
 988 wire i2c_status;
 989 wire i2c_we;
 990 reg subfragments_converter0_state = 1'd0;
 991 reg subfragments_converter0_next_state = 1'd0;
 992 reg libresocsim_converter0_counter_subfragments_converter0_next_value = 1'd0;
 993 reg libresocsim_converter0_counter_subfragments_converter0_next_value_ce = 1'd0;
 994 reg subfragments_converter1_state = 1'd0;
 995 reg subfragments_converter1_next_state = 1'd0;
 996 reg libresocsim_converter1_counter_subfragments_converter1_next_value = 1'd0;
 997 reg libresocsim_converter1_counter_subfragments_converter1_next_value_ce = 1'd0;
 998 reg [1:0] subfragments_refresher_state = 2'd0;
 999 reg [1:0] subfragments_refresher_next_state = 2'd0;
1000 reg [2:0] subfragments_bankmachine0_state = 3'd0;
1001 reg [2:0] subfragments_bankmachine0_next_state = 3'd0;
1002 reg [2:0] subfragments_bankmachine1_state = 3'd0;
1003 reg [2:0] subfragments_bankmachine1_next_state = 3'd0;
1004 reg [2:0] subfragments_bankmachine2_state = 3'd0;
1005 reg [2:0] subfragments_bankmachine2_next_state = 3'd0;
1006 reg [2:0] subfragments_bankmachine3_state = 3'd0;
1007 reg [2:0] subfragments_bankmachine3_next_state = 3'd0;
1008 reg [2:0] subfragments_multiplexer_state = 3'd0;
1009 reg [2:0] subfragments_multiplexer_next_state = 3'd0;
1010 wire subfragments_roundrobin0_request;
1011 wire subfragments_roundrobin0_grant;
1012 wire subfragments_roundrobin0_ce;
1013 wire subfragments_roundrobin1_request;
1014 wire subfragments_roundrobin1_grant;
1015 wire subfragments_roundrobin1_ce;
1016 wire subfragments_roundrobin2_request;
1017 wire subfragments_roundrobin2_grant;
1018 wire subfragments_roundrobin2_ce;
1019 wire subfragments_roundrobin3_request;
1020 wire subfragments_roundrobin3_grant;
1021 wire subfragments_roundrobin3_ce;
1022 reg subfragments_locked0 = 1'd0;
1023 reg subfragments_locked1 = 1'd0;
1024 reg subfragments_locked2 = 1'd0;
1025 reg subfragments_locked3 = 1'd0;
1026 reg subfragments_new_master_wdata_ready = 1'd0;
1027 reg subfragments_new_master_rdata_valid0 = 1'd0;
1028 reg subfragments_new_master_rdata_valid1 = 1'd0;
1029 reg subfragments_new_master_rdata_valid2 = 1'd0;
1030 reg subfragments_new_master_rdata_valid3 = 1'd0;
1031 reg subfragments_state = 1'd0;
1032 reg subfragments_next_state = 1'd0;
1033 reg converter_counter_subfragments_next_value = 1'd0;
1034 reg converter_counter_subfragments_next_value_ce = 1'd0;
1035 reg [13:0] libresocsim_libresocsim_adr = 14'd0;
1036 reg libresocsim_libresocsim_we = 1'd0;
1037 reg [7:0] libresocsim_libresocsim_dat_w = 8'd0;
1038 wire [7:0] libresocsim_libresocsim_dat_r;
1039 wire [29:0] libresocsim_libresocsim_wishbone_adr;
1040 wire [31:0] libresocsim_libresocsim_wishbone_dat_w;
1041 reg [31:0] libresocsim_libresocsim_wishbone_dat_r = 32'd0;
1042 wire [3:0] libresocsim_libresocsim_wishbone_sel;
1043 wire libresocsim_libresocsim_wishbone_cyc;
1044 wire libresocsim_libresocsim_wishbone_stb;
1045 reg libresocsim_libresocsim_wishbone_ack = 1'd0;
1046 wire libresocsim_libresocsim_wishbone_we;
1047 wire [2:0] libresocsim_libresocsim_wishbone_cti;
1048 wire [1:0] libresocsim_libresocsim_wishbone_bte;
1049 reg libresocsim_libresocsim_wishbone_err = 1'd0;
1050 wire [29:0] libresocsim_shared_adr;
1051 wire [31:0] libresocsim_shared_dat_w;
1052 reg [31:0] libresocsim_shared_dat_r = 32'd0;
1053 wire [3:0] libresocsim_shared_sel;
1054 wire libresocsim_shared_cyc;
1055 wire libresocsim_shared_stb;
1056 reg libresocsim_shared_ack = 1'd0;
1057 wire libresocsim_shared_we;
1058 wire [2:0] libresocsim_shared_cti;
1059 wire [1:0] libresocsim_shared_bte;
1060 wire libresocsim_shared_err;
1061 wire [2:0] libresocsim_request;
1062 reg [1:0] libresocsim_grant = 2'd0;
1063 reg [5:0] libresocsim_slave_sel = 6'd0;
1064 reg [5:0] libresocsim_slave_sel_r = 6'd0;
1065 reg libresocsim_error = 1'd0;
1066 wire libresocsim_wait;
1067 wire libresocsim_done;
1068 reg [19:0] libresocsim_count = 20'd1000000;
1069 wire [13:0] libresocsim_interface0_bank_bus_adr;
1070 wire libresocsim_interface0_bank_bus_we;
1071 wire [7:0] libresocsim_interface0_bank_bus_dat_w;
1072 reg [7:0] libresocsim_interface0_bank_bus_dat_r = 8'd0;
1073 wire libresocsim_csrbank0_reset0_re;
1074 wire libresocsim_csrbank0_reset0_r;
1075 wire libresocsim_csrbank0_reset0_we;
1076 wire libresocsim_csrbank0_reset0_w;
1077 wire libresocsim_csrbank0_scratch3_re;
1078 wire [7:0] libresocsim_csrbank0_scratch3_r;
1079 wire libresocsim_csrbank0_scratch3_we;
1080 wire [7:0] libresocsim_csrbank0_scratch3_w;
1081 wire libresocsim_csrbank0_scratch2_re;
1082 wire [7:0] libresocsim_csrbank0_scratch2_r;
1083 wire libresocsim_csrbank0_scratch2_we;
1084 wire [7:0] libresocsim_csrbank0_scratch2_w;
1085 wire libresocsim_csrbank0_scratch1_re;
1086 wire [7:0] libresocsim_csrbank0_scratch1_r;
1087 wire libresocsim_csrbank0_scratch1_we;
1088 wire [7:0] libresocsim_csrbank0_scratch1_w;
1089 wire libresocsim_csrbank0_scratch0_re;
1090 wire [7:0] libresocsim_csrbank0_scratch0_r;
1091 wire libresocsim_csrbank0_scratch0_we;
1092 wire [7:0] libresocsim_csrbank0_scratch0_w;
1093 wire libresocsim_csrbank0_bus_errors3_re;
1094 wire [7:0] libresocsim_csrbank0_bus_errors3_r;
1095 wire libresocsim_csrbank0_bus_errors3_we;
1096 wire [7:0] libresocsim_csrbank0_bus_errors3_w;
1097 wire libresocsim_csrbank0_bus_errors2_re;
1098 wire [7:0] libresocsim_csrbank0_bus_errors2_r;
1099 wire libresocsim_csrbank0_bus_errors2_we;
1100 wire [7:0] libresocsim_csrbank0_bus_errors2_w;
1101 wire libresocsim_csrbank0_bus_errors1_re;
1102 wire [7:0] libresocsim_csrbank0_bus_errors1_r;
1103 wire libresocsim_csrbank0_bus_errors1_we;
1104 wire [7:0] libresocsim_csrbank0_bus_errors1_w;
1105 wire libresocsim_csrbank0_bus_errors0_re;
1106 wire [7:0] libresocsim_csrbank0_bus_errors0_r;
1107 wire libresocsim_csrbank0_bus_errors0_we;
1108 wire [7:0] libresocsim_csrbank0_bus_errors0_w;
1109 wire libresocsim_csrbank0_sel;
1110 wire [13:0] libresocsim_interface1_bank_bus_adr;
1111 wire libresocsim_interface1_bank_bus_we;
1112 wire [7:0] libresocsim_interface1_bank_bus_dat_w;
1113 reg [7:0] libresocsim_interface1_bank_bus_dat_r = 8'd0;
1114 wire libresocsim_csrbank1_oe0_re;
1115 wire [7:0] libresocsim_csrbank1_oe0_r;
1116 wire libresocsim_csrbank1_oe0_we;
1117 wire [7:0] libresocsim_csrbank1_oe0_w;
1118 wire libresocsim_csrbank1_in_re;
1119 wire [7:0] libresocsim_csrbank1_in_r;
1120 wire libresocsim_csrbank1_in_we;
1121 wire [7:0] libresocsim_csrbank1_in_w;
1122 wire libresocsim_csrbank1_out0_re;
1123 wire [7:0] libresocsim_csrbank1_out0_r;
1124 wire libresocsim_csrbank1_out0_we;
1125 wire [7:0] libresocsim_csrbank1_out0_w;
1126 wire libresocsim_csrbank1_sel;
1127 wire [13:0] libresocsim_interface2_bank_bus_adr;
1128 wire libresocsim_interface2_bank_bus_we;
1129 wire [7:0] libresocsim_interface2_bank_bus_dat_w;
1130 reg [7:0] libresocsim_interface2_bank_bus_dat_r = 8'd0;
1131 wire libresocsim_csrbank2_oe0_re;
1132 wire [7:0] libresocsim_csrbank2_oe0_r;
1133 wire libresocsim_csrbank2_oe0_we;
1134 wire [7:0] libresocsim_csrbank2_oe0_w;
1135 wire libresocsim_csrbank2_in_re;
1136 wire [7:0] libresocsim_csrbank2_in_r;
1137 wire libresocsim_csrbank2_in_we;
1138 wire [7:0] libresocsim_csrbank2_in_w;
1139 wire libresocsim_csrbank2_out0_re;
1140 wire [7:0] libresocsim_csrbank2_out0_r;
1141 wire libresocsim_csrbank2_out0_we;
1142 wire [7:0] libresocsim_csrbank2_out0_w;
1143 wire libresocsim_csrbank2_sel;
1144 wire [13:0] libresocsim_interface3_bank_bus_adr;
1145 wire libresocsim_interface3_bank_bus_we;
1146 wire [7:0] libresocsim_interface3_bank_bus_dat_w;
1147 reg [7:0] libresocsim_interface3_bank_bus_dat_r = 8'd0;
1148 wire libresocsim_csrbank3_w0_re;
1149 wire [2:0] libresocsim_csrbank3_w0_r;
1150 wire libresocsim_csrbank3_w0_we;
1151 wire [2:0] libresocsim_csrbank3_w0_w;
1152 wire libresocsim_csrbank3_r_re;
1153 wire libresocsim_csrbank3_r_r;
1154 wire libresocsim_csrbank3_r_we;
1155 wire libresocsim_csrbank3_r_w;
1156 wire libresocsim_csrbank3_sel;
1157 wire [13:0] libresocsim_interface4_bank_bus_adr;
1158 wire libresocsim_interface4_bank_bus_we;
1159 wire [7:0] libresocsim_interface4_bank_bus_dat_w;
1160 reg [7:0] libresocsim_interface4_bank_bus_dat_r = 8'd0;
1161 wire libresocsim_csrbank4_dfii_control0_re;
1162 wire [3:0] libresocsim_csrbank4_dfii_control0_r;
1163 wire libresocsim_csrbank4_dfii_control0_we;
1164 wire [3:0] libresocsim_csrbank4_dfii_control0_w;
1165 wire libresocsim_csrbank4_dfii_pi0_command0_re;
1166 wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_r;
1167 wire libresocsim_csrbank4_dfii_pi0_command0_we;
1168 wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_w;
1169 wire libresocsim_csrbank4_dfii_pi0_address1_re;
1170 wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_r;
1171 wire libresocsim_csrbank4_dfii_pi0_address1_we;
1172 wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_w;
1173 wire libresocsim_csrbank4_dfii_pi0_address0_re;
1174 wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_r;
1175 wire libresocsim_csrbank4_dfii_pi0_address0_we;
1176 wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_w;
1177 wire libresocsim_csrbank4_dfii_pi0_baddress0_re;
1178 wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_r;
1179 wire libresocsim_csrbank4_dfii_pi0_baddress0_we;
1180 wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_w;
1181 wire libresocsim_csrbank4_dfii_pi0_wrdata1_re;
1182 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_r;
1183 wire libresocsim_csrbank4_dfii_pi0_wrdata1_we;
1184 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_w;
1185 wire libresocsim_csrbank4_dfii_pi0_wrdata0_re;
1186 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_r;
1187 wire libresocsim_csrbank4_dfii_pi0_wrdata0_we;
1188 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_w;
1189 wire libresocsim_csrbank4_dfii_pi0_rddata1_re;
1190 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_r;
1191 wire libresocsim_csrbank4_dfii_pi0_rddata1_we;
1192 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_w;
1193 wire libresocsim_csrbank4_dfii_pi0_rddata0_re;
1194 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_r;
1195 wire libresocsim_csrbank4_dfii_pi0_rddata0_we;
1196 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_w;
1197 wire libresocsim_csrbank4_sel;
1198 wire [13:0] libresocsim_interface5_bank_bus_adr;
1199 wire libresocsim_interface5_bank_bus_we;
1200 wire [7:0] libresocsim_interface5_bank_bus_dat_w;
1201 reg [7:0] libresocsim_interface5_bank_bus_dat_r = 8'd0;
1202 wire libresocsim_csrbank5_load3_re;
1203 wire [7:0] libresocsim_csrbank5_load3_r;
1204 wire libresocsim_csrbank5_load3_we;
1205 wire [7:0] libresocsim_csrbank5_load3_w;
1206 wire libresocsim_csrbank5_load2_re;
1207 wire [7:0] libresocsim_csrbank5_load2_r;
1208 wire libresocsim_csrbank5_load2_we;
1209 wire [7:0] libresocsim_csrbank5_load2_w;
1210 wire libresocsim_csrbank5_load1_re;
1211 wire [7:0] libresocsim_csrbank5_load1_r;
1212 wire libresocsim_csrbank5_load1_we;
1213 wire [7:0] libresocsim_csrbank5_load1_w;
1214 wire libresocsim_csrbank5_load0_re;
1215 wire [7:0] libresocsim_csrbank5_load0_r;
1216 wire libresocsim_csrbank5_load0_we;
1217 wire [7:0] libresocsim_csrbank5_load0_w;
1218 wire libresocsim_csrbank5_reload3_re;
1219 wire [7:0] libresocsim_csrbank5_reload3_r;
1220 wire libresocsim_csrbank5_reload3_we;
1221 wire [7:0] libresocsim_csrbank5_reload3_w;
1222 wire libresocsim_csrbank5_reload2_re;
1223 wire [7:0] libresocsim_csrbank5_reload2_r;
1224 wire libresocsim_csrbank5_reload2_we;
1225 wire [7:0] libresocsim_csrbank5_reload2_w;
1226 wire libresocsim_csrbank5_reload1_re;
1227 wire [7:0] libresocsim_csrbank5_reload1_r;
1228 wire libresocsim_csrbank5_reload1_we;
1229 wire [7:0] libresocsim_csrbank5_reload1_w;
1230 wire libresocsim_csrbank5_reload0_re;
1231 wire [7:0] libresocsim_csrbank5_reload0_r;
1232 wire libresocsim_csrbank5_reload0_we;
1233 wire [7:0] libresocsim_csrbank5_reload0_w;
1234 wire libresocsim_csrbank5_en0_re;
1235 wire libresocsim_csrbank5_en0_r;
1236 wire libresocsim_csrbank5_en0_we;
1237 wire libresocsim_csrbank5_en0_w;
1238 wire libresocsim_csrbank5_update_value0_re;
1239 wire libresocsim_csrbank5_update_value0_r;
1240 wire libresocsim_csrbank5_update_value0_we;
1241 wire libresocsim_csrbank5_update_value0_w;
1242 wire libresocsim_csrbank5_value3_re;
1243 wire [7:0] libresocsim_csrbank5_value3_r;
1244 wire libresocsim_csrbank5_value3_we;
1245 wire [7:0] libresocsim_csrbank5_value3_w;
1246 wire libresocsim_csrbank5_value2_re;
1247 wire [7:0] libresocsim_csrbank5_value2_r;
1248 wire libresocsim_csrbank5_value2_we;
1249 wire [7:0] libresocsim_csrbank5_value2_w;
1250 wire libresocsim_csrbank5_value1_re;
1251 wire [7:0] libresocsim_csrbank5_value1_r;
1252 wire libresocsim_csrbank5_value1_we;
1253 wire [7:0] libresocsim_csrbank5_value1_w;
1254 wire libresocsim_csrbank5_value0_re;
1255 wire [7:0] libresocsim_csrbank5_value0_r;
1256 wire libresocsim_csrbank5_value0_we;
1257 wire [7:0] libresocsim_csrbank5_value0_w;
1258 wire libresocsim_csrbank5_ev_enable0_re;
1259 wire libresocsim_csrbank5_ev_enable0_r;
1260 wire libresocsim_csrbank5_ev_enable0_we;
1261 wire libresocsim_csrbank5_ev_enable0_w;
1262 wire libresocsim_csrbank5_sel;
1263 wire [13:0] libresocsim_interface6_bank_bus_adr;
1264 wire libresocsim_interface6_bank_bus_we;
1265 wire [7:0] libresocsim_interface6_bank_bus_dat_w;
1266 reg [7:0] libresocsim_interface6_bank_bus_dat_r = 8'd0;
1267 wire libresocsim_csrbank6_txfull_re;
1268 wire libresocsim_csrbank6_txfull_r;
1269 wire libresocsim_csrbank6_txfull_we;
1270 wire libresocsim_csrbank6_txfull_w;
1271 wire libresocsim_csrbank6_rxempty_re;
1272 wire libresocsim_csrbank6_rxempty_r;
1273 wire libresocsim_csrbank6_rxempty_we;
1274 wire libresocsim_csrbank6_rxempty_w;
1275 wire libresocsim_csrbank6_ev_enable0_re;
1276 wire [1:0] libresocsim_csrbank6_ev_enable0_r;
1277 wire libresocsim_csrbank6_ev_enable0_we;
1278 wire [1:0] libresocsim_csrbank6_ev_enable0_w;
1279 wire libresocsim_csrbank6_txempty_re;
1280 wire libresocsim_csrbank6_txempty_r;
1281 wire libresocsim_csrbank6_txempty_we;
1282 wire libresocsim_csrbank6_txempty_w;
1283 wire libresocsim_csrbank6_rxfull_re;
1284 wire libresocsim_csrbank6_rxfull_r;
1285 wire libresocsim_csrbank6_rxfull_we;
1286 wire libresocsim_csrbank6_rxfull_w;
1287 wire libresocsim_csrbank6_sel;
1288 wire [13:0] libresocsim_interface7_bank_bus_adr;
1289 wire libresocsim_interface7_bank_bus_we;
1290 wire [7:0] libresocsim_interface7_bank_bus_dat_w;
1291 reg [7:0] libresocsim_interface7_bank_bus_dat_r = 8'd0;
1292 wire libresocsim_csrbank7_tuning_word3_re;
1293 wire [7:0] libresocsim_csrbank7_tuning_word3_r;
1294 wire libresocsim_csrbank7_tuning_word3_we;
1295 wire [7:0] libresocsim_csrbank7_tuning_word3_w;
1296 wire libresocsim_csrbank7_tuning_word2_re;
1297 wire [7:0] libresocsim_csrbank7_tuning_word2_r;
1298 wire libresocsim_csrbank7_tuning_word2_we;
1299 wire [7:0] libresocsim_csrbank7_tuning_word2_w;
1300 wire libresocsim_csrbank7_tuning_word1_re;
1301 wire [7:0] libresocsim_csrbank7_tuning_word1_r;
1302 wire libresocsim_csrbank7_tuning_word1_we;
1303 wire [7:0] libresocsim_csrbank7_tuning_word1_w;
1304 wire libresocsim_csrbank7_tuning_word0_re;
1305 wire [7:0] libresocsim_csrbank7_tuning_word0_r;
1306 wire libresocsim_csrbank7_tuning_word0_we;
1307 wire [7:0] libresocsim_csrbank7_tuning_word0_w;
1308 wire libresocsim_csrbank7_sel;
1309 wire [13:0] libresocsim_csr_interconnect_adr;
1310 wire libresocsim_csr_interconnect_we;
1311 wire [7:0] libresocsim_csr_interconnect_dat_w;
1312 wire [7:0] libresocsim_csr_interconnect_dat_r;
1313 reg [1:0] libresocsim_state = 2'd0;
1314 reg [1:0] libresocsim_next_state = 2'd0;
1315 reg [7:0] libresocsim_libresocsim_dat_w_libresocsim_next_value0 = 8'd0;
1316 reg libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 = 1'd0;
1317 reg [13:0] libresocsim_libresocsim_adr_libresocsim_next_value1 = 14'd0;
1318 reg libresocsim_libresocsim_adr_libresocsim_next_value_ce1 = 1'd0;
1319 reg libresocsim_libresocsim_we_libresocsim_next_value2 = 1'd0;
1320 reg libresocsim_libresocsim_we_libresocsim_next_value_ce2 = 1'd0;
1321 reg rhs_array_muxed0 = 1'd0;
1322 reg [12:0] rhs_array_muxed1 = 13'd0;
1323 reg [1:0] rhs_array_muxed2 = 2'd0;
1324 reg rhs_array_muxed3 = 1'd0;
1325 reg rhs_array_muxed4 = 1'd0;
1326 reg rhs_array_muxed5 = 1'd0;
1327 reg t_array_muxed0 = 1'd0;
1328 reg t_array_muxed1 = 1'd0;
1329 reg t_array_muxed2 = 1'd0;
1330 reg rhs_array_muxed6 = 1'd0;
1331 reg [12:0] rhs_array_muxed7 = 13'd0;
1332 reg [1:0] rhs_array_muxed8 = 2'd0;
1333 reg rhs_array_muxed9 = 1'd0;
1334 reg rhs_array_muxed10 = 1'd0;
1335 reg rhs_array_muxed11 = 1'd0;
1336 reg t_array_muxed3 = 1'd0;
1337 reg t_array_muxed4 = 1'd0;
1338 reg t_array_muxed5 = 1'd0;
1339 reg [21:0] rhs_array_muxed12 = 22'd0;
1340 reg rhs_array_muxed13 = 1'd0;
1341 reg rhs_array_muxed14 = 1'd0;
1342 reg [21:0] rhs_array_muxed15 = 22'd0;
1343 reg rhs_array_muxed16 = 1'd0;
1344 reg rhs_array_muxed17 = 1'd0;
1345 reg [21:0] rhs_array_muxed18 = 22'd0;
1346 reg rhs_array_muxed19 = 1'd0;
1347 reg rhs_array_muxed20 = 1'd0;
1348 reg [21:0] rhs_array_muxed21 = 22'd0;
1349 reg rhs_array_muxed22 = 1'd0;
1350 reg rhs_array_muxed23 = 1'd0;
1351 reg [29:0] rhs_array_muxed24 = 30'd0;
1352 reg [31:0] rhs_array_muxed25 = 32'd0;
1353 reg [3:0] rhs_array_muxed26 = 4'd0;
1354 reg rhs_array_muxed27 = 1'd0;
1355 reg rhs_array_muxed28 = 1'd0;
1356 reg rhs_array_muxed29 = 1'd0;
1357 reg [2:0] rhs_array_muxed30 = 3'd0;
1358 reg [1:0] rhs_array_muxed31 = 2'd0;
1359 reg [1:0] array_muxed0 = 2'd0;
1360 reg [12:0] array_muxed1 = 13'd0;
1361 reg array_muxed2 = 1'd0;
1362 reg array_muxed3 = 1'd0;
1363 reg array_muxed4 = 1'd0;
1364 reg array_muxed5 = 1'd0;
1365 reg array_muxed6 = 1'd0;
1366 wire sdrio_clk;
1367 wire sdrio_clk_1;
1368 wire sdrio_clk_2;
1369 wire sdrio_clk_3;
1370 wire sdrio_clk_4;
1371 wire sdrio_clk_5;
1372 wire sdrio_clk_6;
1373 wire sdrio_clk_7;
1374 wire sdrio_clk_8;
1375 wire sdrio_clk_9;
1376 wire sdrio_clk_10;
1377 wire sdrio_clk_11;
1378 wire sdrio_clk_12;
1379 wire sdrio_clk_13;
1380 wire sdrio_clk_14;
1381 wire sdrio_clk_15;
1382 wire sdrio_clk_16;
1383 wire sdrio_clk_17;
1384 wire sdrio_clk_18;
1385 wire sdrio_clk_19;
1386 wire sdrio_clk_20;
1387 wire sdrio_clk_21;
1388 wire sdrio_clk_22;
1389 wire sdrio_clk_23;
1390 wire sdrio_clk_24;
1391 wire sdrio_clk_25;
1392 wire sdrio_clk_26;
1393 wire sdrio_clk_27;
1394 wire sdrio_clk_28;
1395 wire sdrio_clk_29;
1396 wire sdrio_clk_30;
1397 wire sdrio_clk_31;
1398 wire sdrio_clk_32;
1399 wire sdrio_clk_33;
1400 wire sdrio_clk_34;
1401 wire sdrio_clk_35;
1402 wire sdrio_clk_36;
1403 wire sdrio_clk_37;
1404 wire sdrio_clk_38;
1405 wire sdrio_clk_39;
1406 wire sdrio_clk_40;
1407 wire sdrio_clk_41;
1408 wire sdrio_clk_42;
1409 wire sdrio_clk_43;
1410 wire sdrio_clk_44;
1411 wire sdrio_clk_45;
1412 wire sdrio_clk_46;
1413 wire sdrio_clk_47;
1414 wire sdrio_clk_48;
1415 wire sdrio_clk_49;
1416 wire sdrio_clk_50;
1417 wire sdrio_clk_51;
1418 wire sdrio_clk_52;
1419 wire sdrio_clk_53;
1420 wire sdrio_clk_54;
1421 wire sdrio_clk_55;
1422 wire sdrio_clk_56;
1423 wire sdrio_clk_57;
1424 wire sdrio_clk_58;
1425 wire sdrio_clk_59;
1426 wire sdrio_clk_60;
1427 wire sdrio_clk_61;
1428 wire sdrio_clk_62;
1429 wire sdrio_clk_63;
1430 wire sdrio_clk_64;
1431 wire sdrio_clk_65;
1432 wire sdrio_clk_66;
1433 wire sdrio_clk_67;
1434 wire sdrio_clk_68;
1435 wire sdrio_clk_69;
1436 wire sdrio_clk_70;
1437 (* no_retiming = "true" *) reg regs0 = 1'd0;
1438 (* no_retiming = "true" *) reg regs1 = 1'd0;
1439 wire sdrio_clk_71;
1440 wire sdrio_clk_72;
1441 wire sdrio_clk_73;
1442 wire sdrio_clk_74;
1443 wire sdrio_clk_75;
1444 wire sdrio_clk_76;
1445 wire sdrio_clk_77;
1446 wire sdrio_clk_78;
1447 wire sdrio_clk_79;
1448 wire sdrio_clk_80;
1449 wire sdrio_clk_81;
1450 wire sdrio_clk_82;
1451 wire sdrio_clk_83;
1452 wire sdrio_clk_84;
1453 wire sdrio_clk_85;
1454 wire sdrio_clk_86;
1455 wire sdrio_clk_87;
1456 wire sdrio_clk_88;
1457 wire sdrio_clk_89;
1458 wire sdrio_clk_90;
1459 wire sdrio_clk_91;
1460 wire sdrio_clk_92;
1461 wire sdrio_clk_93;
1462 wire sdrio_clk_94;
1463 wire sdrio_clk_95;
1464 wire sdrio_clk_96;
1465 wire sdrio_clk_97;
1466 wire sdrio_clk_98;
1467 wire sdrio_clk_99;
1468 wire sdrio_clk_100;
1469 wire sdrio_clk_101;
1470 wire sdrio_clk_102;
1471 wire sdrio_clk_103;
1472 wire sdrio_clk_104;
1473 wire sdrio_clk_105;
1474 wire sdrio_clk_106;
1475 wire sdrio_clk_107;
1476 wire sdrio_clk_108;
1477 wire sdrio_clk_109;
1478 wire sdrio_clk_110;
1479 wire sdrio_clk_111;
1480 wire sdrio_clk_112;
1481 wire sdrio_clk_113;
1482 wire sdrio_clk_114;
1483 wire sdrio_clk_115;
1484 wire sdrio_clk_116;
1485 wire sdrio_clk_117;
1486 wire sdrio_clk_118;
1487
1488 assign libresocsim_libresoc_reset = libresocsim_reset;
1489 always @(*) begin
1490         eint_tmp <= 3'd0;
1491         eint_tmp[0] <= libresocsim_libresoc_constraintmanager_eint_0;
1492         eint_tmp[1] <= libresocsim_libresoc_constraintmanager_eint_1;
1493         eint_tmp[2] <= libresocsim_libresoc_constraintmanager_eint_2;
1494 end
1495 assign libresocsim_libresoc_jtag_tck = jtag_tck;
1496 assign libresocsim_libresoc_jtag_tms = jtag_tms;
1497 assign libresocsim_libresoc_jtag_tdi = jtag_tdi;
1498 assign jtag_tdo = libresocsim_libresoc_jtag_tdo;
1499 assign nc_1 = nc;
1500 assign libresocsim_bus_error = libresocsim_error;
1501 always @(*) begin
1502         libresocsim_libresoc_interrupt <= 16'd0;
1503         libresocsim_libresoc_interrupt[13] <= eint_tmp[0];
1504         libresocsim_libresoc_interrupt[14] <= eint_tmp[1];
1505         libresocsim_libresoc_interrupt[15] <= eint_tmp[2];
1506         libresocsim_libresoc_interrupt[0] <= libresocsim_irq;
1507         libresocsim_libresoc_interrupt[1] <= irq;
1508 end
1509 assign libresocsim_converter0_reset = (~libresocsim_libresoc_ibus_cyc);
1510 always @(*) begin
1511         libresocsim_interface0_converted_interface_dat_w <= 32'd0;
1512         case (libresocsim_converter0_counter)
1513                 1'd0: begin
1514                         libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:0];
1515                 end
1516                 1'd1: begin
1517                         libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:32];
1518                 end
1519         endcase
1520 end
1521 assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]};
1522 always @(*) begin
1523         libresocsim_interface0_converted_interface_sel <= 4'd0;
1524         libresocsim_interface0_converted_interface_cyc <= 1'd0;
1525         libresocsim_libresoc_ibus_ack <= 1'd0;
1526         libresocsim_interface0_converted_interface_stb <= 1'd0;
1527         subfragments_converter0_next_state <= 1'd0;
1528         libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1529         libresocsim_interface0_converted_interface_we <= 1'd0;
1530         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0;
1531         libresocsim_converter0_skip <= 1'd0;
1532         libresocsim_interface0_converted_interface_adr <= 30'd0;
1533         subfragments_converter0_next_state <= subfragments_converter0_state;
1534         case (subfragments_converter0_state)
1535                 1'd1: begin
1536                         libresocsim_interface0_converted_interface_adr <= {libresocsim_libresoc_ibus_adr, libresocsim_converter0_counter};
1537                         case (libresocsim_converter0_counter)
1538                                 1'd0: begin
1539                                         libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:0];
1540                                 end
1541                                 1'd1: begin
1542                                         libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:4];
1543                                 end
1544                         endcase
1545                         if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin
1546                                 libresocsim_converter0_skip <= (libresocsim_interface0_converted_interface_sel == 1'd0);
1547                                 libresocsim_interface0_converted_interface_we <= libresocsim_libresoc_ibus_we;
1548                                 libresocsim_interface0_converted_interface_cyc <= (~libresocsim_converter0_skip);
1549                                 libresocsim_interface0_converted_interface_stb <= (~libresocsim_converter0_skip);
1550                                 if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin
1551                                         libresocsim_converter0_counter_subfragments_converter0_next_value <= (libresocsim_converter0_counter + 1'd1);
1552                                         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1553                                         if ((libresocsim_converter0_counter == 1'd1)) begin
1554                                                 libresocsim_libresoc_ibus_ack <= 1'd1;
1555                                                 subfragments_converter0_next_state <= 1'd0;
1556                                         end
1557                                 end
1558                         end
1559                 end
1560                 default: begin
1561                         libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1562                         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1563                         if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin
1564                                 subfragments_converter0_next_state <= 1'd1;
1565                         end
1566                 end
1567         endcase
1568 end
1569 assign libresocsim_converter1_reset = (~libresocsim_libresoc_dbus_cyc);
1570 always @(*) begin
1571         libresocsim_interface1_converted_interface_dat_w <= 32'd0;
1572         case (libresocsim_converter1_counter)
1573                 1'd0: begin
1574                         libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:0];
1575                 end
1576                 1'd1: begin
1577                         libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:32];
1578                 end
1579         endcase
1580 end
1581 assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]};
1582 always @(*) begin
1583         libresocsim_interface1_converted_interface_we <= 1'd0;
1584         subfragments_converter1_next_state <= 1'd0;
1585         libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1586         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0;
1587         libresocsim_converter1_skip <= 1'd0;
1588         libresocsim_libresoc_dbus_ack <= 1'd0;
1589         libresocsim_interface1_converted_interface_adr <= 30'd0;
1590         libresocsim_interface1_converted_interface_sel <= 4'd0;
1591         libresocsim_interface1_converted_interface_cyc <= 1'd0;
1592         libresocsim_interface1_converted_interface_stb <= 1'd0;
1593         subfragments_converter1_next_state <= subfragments_converter1_state;
1594         case (subfragments_converter1_state)
1595                 1'd1: begin
1596                         libresocsim_interface1_converted_interface_adr <= {libresocsim_libresoc_dbus_adr, libresocsim_converter1_counter};
1597                         case (libresocsim_converter1_counter)
1598                                 1'd0: begin
1599                                         libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:0];
1600                                 end
1601                                 1'd1: begin
1602                                         libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:4];
1603                                 end
1604                         endcase
1605                         if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin
1606                                 libresocsim_converter1_skip <= (libresocsim_interface1_converted_interface_sel == 1'd0);
1607                                 libresocsim_interface1_converted_interface_we <= libresocsim_libresoc_dbus_we;
1608                                 libresocsim_interface1_converted_interface_cyc <= (~libresocsim_converter1_skip);
1609                                 libresocsim_interface1_converted_interface_stb <= (~libresocsim_converter1_skip);
1610                                 if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin
1611                                         libresocsim_converter1_counter_subfragments_converter1_next_value <= (libresocsim_converter1_counter + 1'd1);
1612                                         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1613                                         if ((libresocsim_converter1_counter == 1'd1)) begin
1614                                                 libresocsim_libresoc_dbus_ack <= 1'd1;
1615                                                 subfragments_converter1_next_state <= 1'd0;
1616                                         end
1617                                 end
1618                         end
1619                 end
1620                 default: begin
1621                         libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1622                         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1623                         if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin
1624                                 subfragments_converter1_next_state <= 1'd1;
1625                         end
1626                 end
1627         endcase
1628 end
1629 assign libresocsim_reset = libresocsim_reset_re;
1630 assign libresocsim_bus_errors_status = libresocsim_bus_errors;
1631 always @(*) begin
1632         libresocsim_we <= 4'd0;
1633         libresocsim_we[0] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[0]);
1634         libresocsim_we[1] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[1]);
1635         libresocsim_we[2] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[2]);
1636         libresocsim_we[3] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[3]);
1637 end
1638 assign libresocsim_adr = libresocsim_ram_bus_adr[6:0];
1639 assign libresocsim_ram_bus_dat_r = libresocsim_dat_r;
1640 assign libresocsim_dat_w = libresocsim_ram_bus_dat_w;
1641 assign libresocsim_zero_trigger = (libresocsim_value != 1'd0);
1642 assign libresocsim_eventmanager_status_w = libresocsim_zero_status;
1643 always @(*) begin
1644         libresocsim_zero_clear <= 1'd0;
1645         if ((libresocsim_eventmanager_pending_re & libresocsim_eventmanager_pending_r)) begin
1646                 libresocsim_zero_clear <= 1'd1;
1647         end
1648 end
1649 assign libresocsim_eventmanager_pending_w = libresocsim_zero_pending;
1650 assign libresocsim_irq = (libresocsim_eventmanager_pending_w & libresocsim_eventmanager_storage);
1651 assign libresocsim_zero_status = libresocsim_zero_trigger;
1652 always @(*) begin
1653         ram_we <= 4'd0;
1654         ram_we[0] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[0]);
1655         ram_we[1] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[1]);
1656         ram_we[2] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[2]);
1657         ram_we[3] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[3]);
1658 end
1659 assign ram_adr = ram_bus_ram_bus_adr[4:0];
1660 assign ram_bus_ram_bus_dat_r = ram_dat_r;
1661 assign ram_dat_w = ram_bus_ram_bus_dat_w;
1662 assign sys_clk_1 = sys_clk;
1663 assign por_clk = sys_clk;
1664 assign sys_rst_1 = int_rst;
1665 assign dfi_p0_address = sdram_master_p0_address;
1666 assign dfi_p0_bank = sdram_master_p0_bank;
1667 assign dfi_p0_cas_n = sdram_master_p0_cas_n;
1668 assign dfi_p0_cs_n = sdram_master_p0_cs_n;
1669 assign dfi_p0_ras_n = sdram_master_p0_ras_n;
1670 assign dfi_p0_we_n = sdram_master_p0_we_n;
1671 assign dfi_p0_cke = sdram_master_p0_cke;
1672 assign dfi_p0_odt = sdram_master_p0_odt;
1673 assign dfi_p0_reset_n = sdram_master_p0_reset_n;
1674 assign dfi_p0_act_n = sdram_master_p0_act_n;
1675 assign dfi_p0_wrdata = sdram_master_p0_wrdata;
1676 assign dfi_p0_wrdata_en = sdram_master_p0_wrdata_en;
1677 assign dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask;
1678 assign dfi_p0_rddata_en = sdram_master_p0_rddata_en;
1679 assign sdram_master_p0_rddata = dfi_p0_rddata;
1680 assign sdram_master_p0_rddata_valid = dfi_p0_rddata_valid;
1681 assign sdram_slave_p0_address = sdram_dfi_p0_address;
1682 assign sdram_slave_p0_bank = sdram_dfi_p0_bank;
1683 assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n;
1684 assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n;
1685 assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n;
1686 assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n;
1687 assign sdram_slave_p0_cke = sdram_dfi_p0_cke;
1688 assign sdram_slave_p0_odt = sdram_dfi_p0_odt;
1689 assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n;
1690 assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n;
1691 assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata;
1692 assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en;
1693 assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask;
1694 assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en;
1695 assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata;
1696 assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid;
1697 always @(*) begin
1698         sdram_master_p0_ras_n <= 1'd1;
1699         sdram_master_p0_we_n <= 1'd1;
1700         sdram_master_p0_cke <= 1'd0;
1701         sdram_master_p0_odt <= 1'd0;
1702         sdram_master_p0_reset_n <= 1'd0;
1703         sdram_master_p0_act_n <= 1'd1;
1704         sdram_inti_p0_rddata <= 16'd0;
1705         sdram_master_p0_wrdata <= 16'd0;
1706         sdram_inti_p0_rddata_valid <= 1'd0;
1707         sdram_master_p0_wrdata_en <= 1'd0;
1708         sdram_master_p0_wrdata_mask <= 2'd0;
1709         sdram_master_p0_rddata_en <= 1'd0;
1710         sdram_slave_p0_rddata <= 16'd0;
1711         sdram_slave_p0_rddata_valid <= 1'd0;
1712         sdram_master_p0_address <= 13'd0;
1713         sdram_master_p0_bank <= 2'd0;
1714         sdram_master_p0_cas_n <= 1'd1;
1715         sdram_master_p0_cs_n <= 1'd1;
1716         if (sdram_sel) begin
1717                 sdram_master_p0_address <= sdram_slave_p0_address;
1718                 sdram_master_p0_bank <= sdram_slave_p0_bank;
1719                 sdram_master_p0_cas_n <= sdram_slave_p0_cas_n;
1720                 sdram_master_p0_cs_n <= sdram_slave_p0_cs_n;
1721                 sdram_master_p0_ras_n <= sdram_slave_p0_ras_n;
1722                 sdram_master_p0_we_n <= sdram_slave_p0_we_n;
1723                 sdram_master_p0_cke <= sdram_slave_p0_cke;
1724                 sdram_master_p0_odt <= sdram_slave_p0_odt;
1725                 sdram_master_p0_reset_n <= sdram_slave_p0_reset_n;
1726                 sdram_master_p0_act_n <= sdram_slave_p0_act_n;
1727                 sdram_master_p0_wrdata <= sdram_slave_p0_wrdata;
1728                 sdram_master_p0_wrdata_en <= sdram_slave_p0_wrdata_en;
1729                 sdram_master_p0_wrdata_mask <= sdram_slave_p0_wrdata_mask;
1730                 sdram_master_p0_rddata_en <= sdram_slave_p0_rddata_en;
1731                 sdram_slave_p0_rddata <= sdram_master_p0_rddata;
1732                 sdram_slave_p0_rddata_valid <= sdram_master_p0_rddata_valid;
1733         end else begin
1734                 sdram_master_p0_address <= sdram_inti_p0_address;
1735                 sdram_master_p0_bank <= sdram_inti_p0_bank;
1736                 sdram_master_p0_cas_n <= sdram_inti_p0_cas_n;
1737                 sdram_master_p0_cs_n <= sdram_inti_p0_cs_n;
1738                 sdram_master_p0_ras_n <= sdram_inti_p0_ras_n;
1739                 sdram_master_p0_we_n <= sdram_inti_p0_we_n;
1740                 sdram_master_p0_cke <= sdram_inti_p0_cke;
1741                 sdram_master_p0_odt <= sdram_inti_p0_odt;
1742                 sdram_master_p0_reset_n <= sdram_inti_p0_reset_n;
1743                 sdram_master_p0_act_n <= sdram_inti_p0_act_n;
1744                 sdram_master_p0_wrdata <= sdram_inti_p0_wrdata;
1745                 sdram_master_p0_wrdata_en <= sdram_inti_p0_wrdata_en;
1746                 sdram_master_p0_wrdata_mask <= sdram_inti_p0_wrdata_mask;
1747                 sdram_master_p0_rddata_en <= sdram_inti_p0_rddata_en;
1748                 sdram_inti_p0_rddata <= sdram_master_p0_rddata;
1749                 sdram_inti_p0_rddata_valid <= sdram_master_p0_rddata_valid;
1750         end
1751 end
1752 assign sdram_inti_p0_cke = sdram_cke_1;
1753 assign sdram_inti_p0_odt = sdram_odt;
1754 assign sdram_inti_p0_reset_n = sdram_reset_n;
1755 always @(*) begin
1756         sdram_inti_p0_we_n <= 1'd1;
1757         sdram_inti_p0_cas_n <= 1'd1;
1758         sdram_inti_p0_cs_n <= 1'd1;
1759         sdram_inti_p0_ras_n <= 1'd1;
1760         if (sdram_command_issue_re) begin
1761                 sdram_inti_p0_cs_n <= {1{(~sdram_command_storage[0])}};
1762                 sdram_inti_p0_we_n <= (~sdram_command_storage[1]);
1763                 sdram_inti_p0_cas_n <= (~sdram_command_storage[2]);
1764                 sdram_inti_p0_ras_n <= (~sdram_command_storage[3]);
1765         end else begin
1766                 sdram_inti_p0_cs_n <= {1{1'd1}};
1767                 sdram_inti_p0_we_n <= 1'd1;
1768                 sdram_inti_p0_cas_n <= 1'd1;
1769                 sdram_inti_p0_ras_n <= 1'd1;
1770         end
1771 end
1772 assign sdram_inti_p0_address = sdram_address_storage;
1773 assign sdram_inti_p0_bank = sdram_baddress_storage;
1774 assign sdram_inti_p0_wrdata_en = (sdram_command_issue_re & sdram_command_storage[4]);
1775 assign sdram_inti_p0_rddata_en = (sdram_command_issue_re & sdram_command_storage[5]);
1776 assign sdram_inti_p0_wrdata = sdram_wrdata_storage;
1777 assign sdram_inti_p0_wrdata_mask = 1'd0;
1778 assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid;
1779 assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready;
1780 assign sdram_bankmachine0_req_we = sdram_interface_bank0_we;
1781 assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr;
1782 assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock;
1783 assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready;
1784 assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid;
1785 assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid;
1786 assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready;
1787 assign sdram_bankmachine1_req_we = sdram_interface_bank1_we;
1788 assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr;
1789 assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock;
1790 assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready;
1791 assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid;
1792 assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid;
1793 assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready;
1794 assign sdram_bankmachine2_req_we = sdram_interface_bank2_we;
1795 assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr;
1796 assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock;
1797 assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready;
1798 assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid;
1799 assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid;
1800 assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready;
1801 assign sdram_bankmachine3_req_we = sdram_interface_bank3_we;
1802 assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr;
1803 assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock;
1804 assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready;
1805 assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid;
1806 assign sdram_timer_wait = (~sdram_timer_done0);
1807 assign sdram_postponer_req_i = sdram_timer_done0;
1808 assign sdram_wants_refresh = sdram_postponer_req_o;
1809 assign sdram_timer_done1 = (sdram_timer_count1 == 1'd0);
1810 assign sdram_timer_done0 = sdram_timer_done1;
1811 assign sdram_timer_count0 = sdram_timer_count1;
1812 assign sdram_sequencer_start1 = (sdram_sequencer_start0 | (sdram_sequencer_count != 1'd0));
1813 assign sdram_sequencer_done0 = (sdram_sequencer_done1 & (sdram_sequencer_count == 1'd0));
1814 always @(*) begin
1815         sdram_sequencer_start0 <= 1'd0;
1816         subfragments_refresher_next_state <= 2'd0;
1817         sdram_cmd_valid <= 1'd0;
1818         sdram_cmd_last <= 1'd0;
1819         subfragments_refresher_next_state <= subfragments_refresher_state;
1820         case (subfragments_refresher_state)
1821                 1'd1: begin
1822                         sdram_cmd_valid <= 1'd1;
1823                         if (sdram_cmd_ready) begin
1824                                 sdram_sequencer_start0 <= 1'd1;
1825                                 subfragments_refresher_next_state <= 2'd2;
1826                         end
1827                 end
1828                 2'd2: begin
1829                         sdram_cmd_valid <= 1'd1;
1830                         if (sdram_sequencer_done0) begin
1831                                 sdram_cmd_valid <= 1'd0;
1832                                 sdram_cmd_last <= 1'd1;
1833                                 subfragments_refresher_next_state <= 1'd0;
1834                         end
1835                 end
1836                 default: begin
1837                         if (1'd1) begin
1838                                 if (sdram_wants_refresh) begin
1839                                         subfragments_refresher_next_state <= 1'd1;
1840                                 end
1841                         end
1842                 end
1843         endcase
1844 end
1845 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid;
1846 assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
1847 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we;
1848 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr;
1849 assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
1850 assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready;
1851 assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first;
1852 assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last;
1853 assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
1854 assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
1855 assign sdram_bankmachine0_cmd_buffer_source_ready = (sdram_bankmachine0_req_wdata_ready | sdram_bankmachine0_req_rdata_valid);
1856 assign sdram_bankmachine0_req_lock = (sdram_bankmachine0_cmd_buffer_lookahead_source_valid | sdram_bankmachine0_cmd_buffer_source_valid);
1857 assign sdram_bankmachine0_row_hit = (sdram_bankmachine0_row == sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]);
1858 assign sdram_bankmachine0_cmd_payload_ba = 1'd0;
1859 always @(*) begin
1860         sdram_bankmachine0_cmd_payload_a <= 13'd0;
1861         if (sdram_bankmachine0_row_col_n_addr_sel) begin
1862                 sdram_bankmachine0_cmd_payload_a <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
1863         end else begin
1864                 sdram_bankmachine0_cmd_payload_a <= ((sdram_bankmachine0_auto_precharge <<< 4'd10) | {sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
1865         end
1866 end
1867 assign sdram_bankmachine0_twtpcon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_cmd_payload_is_write);
1868 assign sdram_bankmachine0_trccon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open);
1869 assign sdram_bankmachine0_trascon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open);
1870 always @(*) begin
1871         sdram_bankmachine0_auto_precharge <= 1'd0;
1872         if ((sdram_bankmachine0_cmd_buffer_lookahead_source_valid & sdram_bankmachine0_cmd_buffer_source_valid)) begin
1873                 if ((sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9])) begin
1874                         sdram_bankmachine0_auto_precharge <= (sdram_bankmachine0_row_close == 1'd0);
1875                 end
1876         end
1877 end
1878 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
1879 assign {sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
1880 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
1881 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
1882 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
1883 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
1884 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
1885 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
1886 assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
1887 assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
1888 assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
1889 assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
1890 assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
1891 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
1892 always @(*) begin
1893         sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
1894         if (sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
1895                 sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
1896         end else begin
1897                 sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine0_cmd_buffer_lookahead_produce;
1898         end
1899 end
1900 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
1901 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | sdram_bankmachine0_cmd_buffer_lookahead_replace));
1902 assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
1903 assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume;
1904 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
1905 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
1906 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
1907 assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready);
1908 always @(*) begin
1909         sdram_bankmachine0_cmd_payload_cas <= 1'd0;
1910         sdram_bankmachine0_cmd_payload_ras <= 1'd0;
1911         sdram_bankmachine0_cmd_payload_we <= 1'd0;
1912         sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
1913         sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
1914         sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
1915         sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
1916         sdram_bankmachine0_req_wdata_ready <= 1'd0;
1917         sdram_bankmachine0_req_rdata_valid <= 1'd0;
1918         sdram_bankmachine0_refresh_gnt <= 1'd0;
1919         subfragments_bankmachine0_next_state <= 3'd0;
1920         sdram_bankmachine0_cmd_valid <= 1'd0;
1921         sdram_bankmachine0_row_open <= 1'd0;
1922         sdram_bankmachine0_row_close <= 1'd0;
1923         subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state;
1924         case (subfragments_bankmachine0_state)
1925                 1'd1: begin
1926                         if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin
1927                                 sdram_bankmachine0_cmd_valid <= 1'd1;
1928                                 if (sdram_bankmachine0_cmd_ready) begin
1929                                         subfragments_bankmachine0_next_state <= 3'd5;
1930                                 end
1931                                 sdram_bankmachine0_cmd_payload_ras <= 1'd1;
1932                                 sdram_bankmachine0_cmd_payload_we <= 1'd1;
1933                                 sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
1934                         end
1935                         sdram_bankmachine0_row_close <= 1'd1;
1936                 end
1937                 2'd2: begin
1938                         if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin
1939                                 subfragments_bankmachine0_next_state <= 3'd5;
1940                         end
1941                         sdram_bankmachine0_row_close <= 1'd1;
1942                 end
1943                 2'd3: begin
1944                         if (sdram_bankmachine0_trccon_ready) begin
1945                                 sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
1946                                 sdram_bankmachine0_row_open <= 1'd1;
1947                                 sdram_bankmachine0_cmd_valid <= 1'd1;
1948                                 sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
1949                                 if (sdram_bankmachine0_cmd_ready) begin
1950                                         subfragments_bankmachine0_next_state <= 3'd6;
1951                                 end
1952                                 sdram_bankmachine0_cmd_payload_ras <= 1'd1;
1953                         end
1954                 end
1955                 3'd4: begin
1956                         if (sdram_bankmachine0_twtpcon_ready) begin
1957                                 sdram_bankmachine0_refresh_gnt <= 1'd1;
1958                         end
1959                         sdram_bankmachine0_row_close <= 1'd1;
1960                         sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
1961                         if ((~sdram_bankmachine0_refresh_req)) begin
1962                                 subfragments_bankmachine0_next_state <= 1'd0;
1963                         end
1964                 end
1965                 3'd5: begin
1966                         subfragments_bankmachine0_next_state <= 2'd3;
1967                 end
1968                 3'd6: begin
1969                         subfragments_bankmachine0_next_state <= 1'd0;
1970                 end
1971                 default: begin
1972                         if (sdram_bankmachine0_refresh_req) begin
1973                                 subfragments_bankmachine0_next_state <= 3'd4;
1974                         end else begin
1975                                 if (sdram_bankmachine0_cmd_buffer_source_valid) begin
1976                                         if (sdram_bankmachine0_row_opened) begin
1977                                                 if (sdram_bankmachine0_row_hit) begin
1978                                                         sdram_bankmachine0_cmd_valid <= 1'd1;
1979                                                         if (sdram_bankmachine0_cmd_buffer_source_payload_we) begin
1980                                                                 sdram_bankmachine0_req_wdata_ready <= sdram_bankmachine0_cmd_ready;
1981                                                                 sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
1982                                                                 sdram_bankmachine0_cmd_payload_we <= 1'd1;
1983                                                         end else begin
1984                                                                 sdram_bankmachine0_req_rdata_valid <= sdram_bankmachine0_cmd_ready;
1985                                                                 sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
1986                                                         end
1987                                                         sdram_bankmachine0_cmd_payload_cas <= 1'd1;
1988                                                         if ((sdram_bankmachine0_cmd_ready & sdram_bankmachine0_auto_precharge)) begin
1989                                                                 subfragments_bankmachine0_next_state <= 2'd2;
1990                                                         end
1991                                                 end else begin
1992                                                         subfragments_bankmachine0_next_state <= 1'd1;
1993                                                 end
1994                                         end else begin
1995                                                 subfragments_bankmachine0_next_state <= 2'd3;
1996                                         end
1997                                 end
1998                         end
1999                 end
2000         endcase
2001 end
2002 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid;
2003 assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
2004 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we;
2005 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr;
2006 assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
2007 assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready;
2008 assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first;
2009 assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last;
2010 assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
2011 assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
2012 assign sdram_bankmachine1_cmd_buffer_source_ready = (sdram_bankmachine1_req_wdata_ready | sdram_bankmachine1_req_rdata_valid);
2013 assign sdram_bankmachine1_req_lock = (sdram_bankmachine1_cmd_buffer_lookahead_source_valid | sdram_bankmachine1_cmd_buffer_source_valid);
2014 assign sdram_bankmachine1_row_hit = (sdram_bankmachine1_row == sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]);
2015 assign sdram_bankmachine1_cmd_payload_ba = 1'd1;
2016 always @(*) begin
2017         sdram_bankmachine1_cmd_payload_a <= 13'd0;
2018         if (sdram_bankmachine1_row_col_n_addr_sel) begin
2019                 sdram_bankmachine1_cmd_payload_a <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
2020         end else begin
2021                 sdram_bankmachine1_cmd_payload_a <= ((sdram_bankmachine1_auto_precharge <<< 4'd10) | {sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2022         end
2023 end
2024 assign sdram_bankmachine1_twtpcon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_cmd_payload_is_write);
2025 assign sdram_bankmachine1_trccon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open);
2026 assign sdram_bankmachine1_trascon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open);
2027 always @(*) begin
2028         sdram_bankmachine1_auto_precharge <= 1'd0;
2029         if ((sdram_bankmachine1_cmd_buffer_lookahead_source_valid & sdram_bankmachine1_cmd_buffer_source_valid)) begin
2030                 if ((sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9])) begin
2031                         sdram_bankmachine1_auto_precharge <= (sdram_bankmachine1_row_close == 1'd0);
2032                 end
2033         end
2034 end
2035 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
2036 assign {sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
2037 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
2038 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
2039 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
2040 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
2041 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
2042 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
2043 assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
2044 assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
2045 assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
2046 assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
2047 assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
2048 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
2049 always @(*) begin
2050         sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2051         if (sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
2052                 sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
2053         end else begin
2054                 sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine1_cmd_buffer_lookahead_produce;
2055         end
2056 end
2057 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
2058 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | sdram_bankmachine1_cmd_buffer_lookahead_replace));
2059 assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
2060 assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume;
2061 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
2062 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
2063 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
2064 assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready);
2065 always @(*) begin
2066         sdram_bankmachine1_row_open <= 1'd0;
2067         sdram_bankmachine1_row_close <= 1'd0;
2068         sdram_bankmachine1_cmd_payload_cas <= 1'd0;
2069         sdram_bankmachine1_cmd_payload_ras <= 1'd0;
2070         sdram_bankmachine1_cmd_payload_we <= 1'd0;
2071         sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
2072         sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
2073         subfragments_bankmachine1_next_state <= 3'd0;
2074         sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
2075         sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
2076         sdram_bankmachine1_req_wdata_ready <= 1'd0;
2077         sdram_bankmachine1_req_rdata_valid <= 1'd0;
2078         sdram_bankmachine1_refresh_gnt <= 1'd0;
2079         sdram_bankmachine1_cmd_valid <= 1'd0;
2080         subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state;
2081         case (subfragments_bankmachine1_state)
2082                 1'd1: begin
2083                         if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin
2084                                 sdram_bankmachine1_cmd_valid <= 1'd1;
2085                                 if (sdram_bankmachine1_cmd_ready) begin
2086                                         subfragments_bankmachine1_next_state <= 3'd5;
2087                                 end
2088                                 sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2089                                 sdram_bankmachine1_cmd_payload_we <= 1'd1;
2090                                 sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2091                         end
2092                         sdram_bankmachine1_row_close <= 1'd1;
2093                 end
2094                 2'd2: begin
2095                         if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin
2096                                 subfragments_bankmachine1_next_state <= 3'd5;
2097                         end
2098                         sdram_bankmachine1_row_close <= 1'd1;
2099                 end
2100                 2'd3: begin
2101                         if (sdram_bankmachine1_trccon_ready) begin
2102                                 sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
2103                                 sdram_bankmachine1_row_open <= 1'd1;
2104                                 sdram_bankmachine1_cmd_valid <= 1'd1;
2105                                 sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2106                                 if (sdram_bankmachine1_cmd_ready) begin
2107                                         subfragments_bankmachine1_next_state <= 3'd6;
2108                                 end
2109                                 sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2110                         end
2111                 end
2112                 3'd4: begin
2113                         if (sdram_bankmachine1_twtpcon_ready) begin
2114                                 sdram_bankmachine1_refresh_gnt <= 1'd1;
2115                         end
2116                         sdram_bankmachine1_row_close <= 1'd1;
2117                         sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2118                         if ((~sdram_bankmachine1_refresh_req)) begin
2119                                 subfragments_bankmachine1_next_state <= 1'd0;
2120                         end
2121                 end
2122                 3'd5: begin
2123                         subfragments_bankmachine1_next_state <= 2'd3;
2124                 end
2125                 3'd6: begin
2126                         subfragments_bankmachine1_next_state <= 1'd0;
2127                 end
2128                 default: begin
2129                         if (sdram_bankmachine1_refresh_req) begin
2130                                 subfragments_bankmachine1_next_state <= 3'd4;
2131                         end else begin
2132                                 if (sdram_bankmachine1_cmd_buffer_source_valid) begin
2133                                         if (sdram_bankmachine1_row_opened) begin
2134                                                 if (sdram_bankmachine1_row_hit) begin
2135                                                         sdram_bankmachine1_cmd_valid <= 1'd1;
2136                                                         if (sdram_bankmachine1_cmd_buffer_source_payload_we) begin
2137                                                                 sdram_bankmachine1_req_wdata_ready <= sdram_bankmachine1_cmd_ready;
2138                                                                 sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
2139                                                                 sdram_bankmachine1_cmd_payload_we <= 1'd1;
2140                                                         end else begin
2141                                                                 sdram_bankmachine1_req_rdata_valid <= sdram_bankmachine1_cmd_ready;
2142                                                                 sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
2143                                                         end
2144                                                         sdram_bankmachine1_cmd_payload_cas <= 1'd1;
2145                                                         if ((sdram_bankmachine1_cmd_ready & sdram_bankmachine1_auto_precharge)) begin
2146                                                                 subfragments_bankmachine1_next_state <= 2'd2;
2147                                                         end
2148                                                 end else begin
2149                                                         subfragments_bankmachine1_next_state <= 1'd1;
2150                                                 end
2151                                         end else begin
2152                                                 subfragments_bankmachine1_next_state <= 2'd3;
2153                                         end
2154                                 end
2155                         end
2156                 end
2157         endcase
2158 end
2159 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid;
2160 assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
2161 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we;
2162 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr;
2163 assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
2164 assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready;
2165 assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first;
2166 assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last;
2167 assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
2168 assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
2169 assign sdram_bankmachine2_cmd_buffer_source_ready = (sdram_bankmachine2_req_wdata_ready | sdram_bankmachine2_req_rdata_valid);
2170 assign sdram_bankmachine2_req_lock = (sdram_bankmachine2_cmd_buffer_lookahead_source_valid | sdram_bankmachine2_cmd_buffer_source_valid);
2171 assign sdram_bankmachine2_row_hit = (sdram_bankmachine2_row == sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]);
2172 assign sdram_bankmachine2_cmd_payload_ba = 2'd2;
2173 always @(*) begin
2174         sdram_bankmachine2_cmd_payload_a <= 13'd0;
2175         if (sdram_bankmachine2_row_col_n_addr_sel) begin
2176                 sdram_bankmachine2_cmd_payload_a <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
2177         end else begin
2178                 sdram_bankmachine2_cmd_payload_a <= ((sdram_bankmachine2_auto_precharge <<< 4'd10) | {sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2179         end
2180 end
2181 assign sdram_bankmachine2_twtpcon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_cmd_payload_is_write);
2182 assign sdram_bankmachine2_trccon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open);
2183 assign sdram_bankmachine2_trascon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open);
2184 always @(*) begin
2185         sdram_bankmachine2_auto_precharge <= 1'd0;
2186         if ((sdram_bankmachine2_cmd_buffer_lookahead_source_valid & sdram_bankmachine2_cmd_buffer_source_valid)) begin
2187                 if ((sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9])) begin
2188                         sdram_bankmachine2_auto_precharge <= (sdram_bankmachine2_row_close == 1'd0);
2189                 end
2190         end
2191 end
2192 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
2193 assign {sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
2194 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
2195 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
2196 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
2197 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
2198 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
2199 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
2200 assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
2201 assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
2202 assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
2203 assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
2204 assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
2205 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
2206 always @(*) begin
2207         sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2208         if (sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
2209                 sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
2210         end else begin
2211                 sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine2_cmd_buffer_lookahead_produce;
2212         end
2213 end
2214 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
2215 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | sdram_bankmachine2_cmd_buffer_lookahead_replace));
2216 assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
2217 assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume;
2218 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
2219 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
2220 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
2221 assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready);
2222 always @(*) begin
2223         sdram_bankmachine2_refresh_gnt <= 1'd0;
2224         sdram_bankmachine2_cmd_valid <= 1'd0;
2225         subfragments_bankmachine2_next_state <= 3'd0;
2226         sdram_bankmachine2_row_open <= 1'd0;
2227         sdram_bankmachine2_row_close <= 1'd0;
2228         sdram_bankmachine2_cmd_payload_cas <= 1'd0;
2229         sdram_bankmachine2_cmd_payload_ras <= 1'd0;
2230         sdram_bankmachine2_cmd_payload_we <= 1'd0;
2231         sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
2232         sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
2233         sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
2234         sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
2235         sdram_bankmachine2_req_wdata_ready <= 1'd0;
2236         sdram_bankmachine2_req_rdata_valid <= 1'd0;
2237         subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state;
2238         case (subfragments_bankmachine2_state)
2239                 1'd1: begin
2240                         if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin
2241                                 sdram_bankmachine2_cmd_valid <= 1'd1;
2242                                 if (sdram_bankmachine2_cmd_ready) begin
2243                                         subfragments_bankmachine2_next_state <= 3'd5;
2244                                 end
2245                                 sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2246                                 sdram_bankmachine2_cmd_payload_we <= 1'd1;
2247                                 sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2248                         end
2249                         sdram_bankmachine2_row_close <= 1'd1;
2250                 end
2251                 2'd2: begin
2252                         if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin
2253                                 subfragments_bankmachine2_next_state <= 3'd5;
2254                         end
2255                         sdram_bankmachine2_row_close <= 1'd1;
2256                 end
2257                 2'd3: begin
2258                         if (sdram_bankmachine2_trccon_ready) begin
2259                                 sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
2260                                 sdram_bankmachine2_row_open <= 1'd1;
2261                                 sdram_bankmachine2_cmd_valid <= 1'd1;
2262                                 sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2263                                 if (sdram_bankmachine2_cmd_ready) begin
2264                                         subfragments_bankmachine2_next_state <= 3'd6;
2265                                 end
2266                                 sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2267                         end
2268                 end
2269                 3'd4: begin
2270                         if (sdram_bankmachine2_twtpcon_ready) begin
2271                                 sdram_bankmachine2_refresh_gnt <= 1'd1;
2272                         end
2273                         sdram_bankmachine2_row_close <= 1'd1;
2274                         sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2275                         if ((~sdram_bankmachine2_refresh_req)) begin
2276                                 subfragments_bankmachine2_next_state <= 1'd0;
2277                         end
2278                 end
2279                 3'd5: begin
2280                         subfragments_bankmachine2_next_state <= 2'd3;
2281                 end
2282                 3'd6: begin
2283                         subfragments_bankmachine2_next_state <= 1'd0;
2284                 end
2285                 default: begin
2286                         if (sdram_bankmachine2_refresh_req) begin
2287                                 subfragments_bankmachine2_next_state <= 3'd4;
2288                         end else begin
2289                                 if (sdram_bankmachine2_cmd_buffer_source_valid) begin
2290                                         if (sdram_bankmachine2_row_opened) begin
2291                                                 if (sdram_bankmachine2_row_hit) begin
2292                                                         sdram_bankmachine2_cmd_valid <= 1'd1;
2293                                                         if (sdram_bankmachine2_cmd_buffer_source_payload_we) begin
2294                                                                 sdram_bankmachine2_req_wdata_ready <= sdram_bankmachine2_cmd_ready;
2295                                                                 sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
2296                                                                 sdram_bankmachine2_cmd_payload_we <= 1'd1;
2297                                                         end else begin
2298                                                                 sdram_bankmachine2_req_rdata_valid <= sdram_bankmachine2_cmd_ready;
2299                                                                 sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
2300                                                         end
2301                                                         sdram_bankmachine2_cmd_payload_cas <= 1'd1;
2302                                                         if ((sdram_bankmachine2_cmd_ready & sdram_bankmachine2_auto_precharge)) begin
2303                                                                 subfragments_bankmachine2_next_state <= 2'd2;
2304                                                         end
2305                                                 end else begin
2306                                                         subfragments_bankmachine2_next_state <= 1'd1;
2307                                                 end
2308                                         end else begin
2309                                                 subfragments_bankmachine2_next_state <= 2'd3;
2310                                         end
2311                                 end
2312                         end
2313                 end
2314         endcase
2315 end
2316 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid;
2317 assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
2318 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we;
2319 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr;
2320 assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
2321 assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready;
2322 assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first;
2323 assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last;
2324 assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
2325 assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
2326 assign sdram_bankmachine3_cmd_buffer_source_ready = (sdram_bankmachine3_req_wdata_ready | sdram_bankmachine3_req_rdata_valid);
2327 assign sdram_bankmachine3_req_lock = (sdram_bankmachine3_cmd_buffer_lookahead_source_valid | sdram_bankmachine3_cmd_buffer_source_valid);
2328 assign sdram_bankmachine3_row_hit = (sdram_bankmachine3_row == sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]);
2329 assign sdram_bankmachine3_cmd_payload_ba = 2'd3;
2330 always @(*) begin
2331         sdram_bankmachine3_cmd_payload_a <= 13'd0;
2332         if (sdram_bankmachine3_row_col_n_addr_sel) begin
2333                 sdram_bankmachine3_cmd_payload_a <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
2334         end else begin
2335                 sdram_bankmachine3_cmd_payload_a <= ((sdram_bankmachine3_auto_precharge <<< 4'd10) | {sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2336         end
2337 end
2338 assign sdram_bankmachine3_twtpcon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_cmd_payload_is_write);
2339 assign sdram_bankmachine3_trccon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open);
2340 assign sdram_bankmachine3_trascon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open);
2341 always @(*) begin
2342         sdram_bankmachine3_auto_precharge <= 1'd0;
2343         if ((sdram_bankmachine3_cmd_buffer_lookahead_source_valid & sdram_bankmachine3_cmd_buffer_source_valid)) begin
2344                 if ((sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9])) begin
2345                         sdram_bankmachine3_auto_precharge <= (sdram_bankmachine3_row_close == 1'd0);
2346                 end
2347         end
2348 end
2349 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
2350 assign {sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
2351 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
2352 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
2353 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
2354 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
2355 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
2356 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
2357 assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
2358 assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
2359 assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
2360 assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
2361 assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
2362 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
2363 always @(*) begin
2364         sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2365         if (sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
2366                 sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
2367         end else begin
2368                 sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine3_cmd_buffer_lookahead_produce;
2369         end
2370 end
2371 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
2372 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | sdram_bankmachine3_cmd_buffer_lookahead_replace));
2373 assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
2374 assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume;
2375 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
2376 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
2377 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
2378 assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready);
2379 always @(*) begin
2380         sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
2381         sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
2382         sdram_bankmachine3_req_wdata_ready <= 1'd0;
2383         sdram_bankmachine3_req_rdata_valid <= 1'd0;
2384         subfragments_bankmachine3_next_state <= 3'd0;
2385         sdram_bankmachine3_refresh_gnt <= 1'd0;
2386         sdram_bankmachine3_cmd_valid <= 1'd0;
2387         sdram_bankmachine3_row_open <= 1'd0;
2388         sdram_bankmachine3_row_close <= 1'd0;
2389         sdram_bankmachine3_cmd_payload_cas <= 1'd0;
2390         sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
2391         sdram_bankmachine3_cmd_payload_ras <= 1'd0;
2392         sdram_bankmachine3_cmd_payload_we <= 1'd0;
2393         sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
2394         subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state;
2395         case (subfragments_bankmachine3_state)
2396                 1'd1: begin
2397                         if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin
2398                                 sdram_bankmachine3_cmd_valid <= 1'd1;
2399                                 if (sdram_bankmachine3_cmd_ready) begin
2400                                         subfragments_bankmachine3_next_state <= 3'd5;
2401                                 end
2402                                 sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2403                                 sdram_bankmachine3_cmd_payload_we <= 1'd1;
2404                                 sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2405                         end
2406                         sdram_bankmachine3_row_close <= 1'd1;
2407                 end
2408                 2'd2: begin
2409                         if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin
2410                                 subfragments_bankmachine3_next_state <= 3'd5;
2411                         end
2412                         sdram_bankmachine3_row_close <= 1'd1;
2413                 end
2414                 2'd3: begin
2415                         if (sdram_bankmachine3_trccon_ready) begin
2416                                 sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
2417                                 sdram_bankmachine3_row_open <= 1'd1;
2418                                 sdram_bankmachine3_cmd_valid <= 1'd1;
2419                                 sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2420                                 if (sdram_bankmachine3_cmd_ready) begin
2421                                         subfragments_bankmachine3_next_state <= 3'd6;
2422                                 end
2423                                 sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2424                         end
2425                 end
2426                 3'd4: begin
2427                         if (sdram_bankmachine3_twtpcon_ready) begin
2428                                 sdram_bankmachine3_refresh_gnt <= 1'd1;
2429                         end
2430                         sdram_bankmachine3_row_close <= 1'd1;
2431                         sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2432                         if ((~sdram_bankmachine3_refresh_req)) begin
2433                                 subfragments_bankmachine3_next_state <= 1'd0;
2434                         end
2435                 end
2436                 3'd5: begin
2437                         subfragments_bankmachine3_next_state <= 2'd3;
2438                 end
2439                 3'd6: begin
2440                         subfragments_bankmachine3_next_state <= 1'd0;
2441                 end
2442                 default: begin
2443                         if (sdram_bankmachine3_refresh_req) begin
2444                                 subfragments_bankmachine3_next_state <= 3'd4;
2445                         end else begin
2446                                 if (sdram_bankmachine3_cmd_buffer_source_valid) begin
2447                                         if (sdram_bankmachine3_row_opened) begin
2448                                                 if (sdram_bankmachine3_row_hit) begin
2449                                                         sdram_bankmachine3_cmd_valid <= 1'd1;
2450                                                         if (sdram_bankmachine3_cmd_buffer_source_payload_we) begin
2451                                                                 sdram_bankmachine3_req_wdata_ready <= sdram_bankmachine3_cmd_ready;
2452                                                                 sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
2453                                                                 sdram_bankmachine3_cmd_payload_we <= 1'd1;
2454                                                         end else begin
2455                                                                 sdram_bankmachine3_req_rdata_valid <= sdram_bankmachine3_cmd_ready;
2456                                                                 sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
2457                                                         end
2458                                                         sdram_bankmachine3_cmd_payload_cas <= 1'd1;
2459                                                         if ((sdram_bankmachine3_cmd_ready & sdram_bankmachine3_auto_precharge)) begin
2460                                                                 subfragments_bankmachine3_next_state <= 2'd2;
2461                                                         end
2462                                                 end else begin
2463                                                         subfragments_bankmachine3_next_state <= 1'd1;
2464                                                 end
2465                                         end else begin
2466                                                 subfragments_bankmachine3_next_state <= 2'd3;
2467                                         end
2468                                 end
2469                         end
2470                 end
2471         endcase
2472 end
2473 assign sdram_choose_req_want_cmds = 1'd1;
2474 assign sdram_trrdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we)));
2475 assign sdram_tfawcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we)));
2476 assign sdram_ras_allowed = (sdram_trrdcon_ready & sdram_tfawcon_ready);
2477 assign sdram_tccdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_cmd_payload_is_write | sdram_choose_req_cmd_payload_is_read));
2478 assign sdram_cas_allowed = sdram_tccdcon_ready;
2479 assign sdram_twtrcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
2480 assign sdram_read_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_read) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_read)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_read)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_read));
2481 assign sdram_write_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_write) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_write)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_write)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_write));
2482 assign sdram_max_time0 = (sdram_time0 == 1'd0);
2483 assign sdram_max_time1 = (sdram_time1 == 1'd0);
2484 assign sdram_bankmachine0_refresh_req = sdram_cmd_valid;
2485 assign sdram_bankmachine1_refresh_req = sdram_cmd_valid;
2486 assign sdram_bankmachine2_refresh_req = sdram_cmd_valid;
2487 assign sdram_bankmachine3_refresh_req = sdram_cmd_valid;
2488 assign sdram_go_to_refresh = (((sdram_bankmachine0_refresh_gnt & sdram_bankmachine1_refresh_gnt) & sdram_bankmachine2_refresh_gnt) & sdram_bankmachine3_refresh_gnt);
2489 assign sdram_interface_rdata = {sdram_dfi_p0_rddata};
2490 assign {sdram_dfi_p0_wrdata} = sdram_interface_wdata;
2491 assign {sdram_dfi_p0_wrdata_mask} = (~sdram_interface_wdata_we);
2492 always @(*) begin
2493         sdram_choose_cmd_valids <= 4'd0;
2494         sdram_choose_cmd_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2495         sdram_choose_cmd_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2496         sdram_choose_cmd_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2497         sdram_choose_cmd_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2498 end
2499 assign sdram_choose_cmd_request = sdram_choose_cmd_valids;
2500 assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0;
2501 assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1;
2502 assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
2503 assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
2504 assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
2505 assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
2506 always @(*) begin
2507         sdram_choose_cmd_cmd_payload_cas <= 1'd0;
2508         if (sdram_choose_cmd_cmd_valid) begin
2509                 sdram_choose_cmd_cmd_payload_cas <= t_array_muxed0;
2510         end
2511 end
2512 always @(*) begin
2513         sdram_choose_cmd_cmd_payload_ras <= 1'd0;
2514         if (sdram_choose_cmd_cmd_valid) begin
2515                 sdram_choose_cmd_cmd_payload_ras <= t_array_muxed1;
2516         end
2517 end
2518 always @(*) begin
2519         sdram_choose_cmd_cmd_payload_we <= 1'd0;
2520         if (sdram_choose_cmd_cmd_valid) begin
2521                 sdram_choose_cmd_cmd_payload_we <= t_array_muxed2;
2522         end
2523 end
2524 assign sdram_choose_cmd_ce = (sdram_choose_cmd_cmd_ready | (~sdram_choose_cmd_cmd_valid));
2525 always @(*) begin
2526         sdram_choose_req_valids <= 4'd0;
2527         sdram_choose_req_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_req_want_writes))));
2528         sdram_choose_req_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_req_want_writes))));
2529         sdram_choose_req_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_req_want_writes))));
2530         sdram_choose_req_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_req_want_writes))));
2531 end
2532 assign sdram_choose_req_request = sdram_choose_req_valids;
2533 assign sdram_choose_req_cmd_valid = rhs_array_muxed6;
2534 assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7;
2535 assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8;
2536 assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9;
2537 assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10;
2538 assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
2539 always @(*) begin
2540         sdram_choose_req_cmd_payload_cas <= 1'd0;
2541         if (sdram_choose_req_cmd_valid) begin
2542                 sdram_choose_req_cmd_payload_cas <= t_array_muxed3;
2543         end
2544 end
2545 always @(*) begin
2546         sdram_choose_req_cmd_payload_ras <= 1'd0;
2547         if (sdram_choose_req_cmd_valid) begin
2548                 sdram_choose_req_cmd_payload_ras <= t_array_muxed4;
2549         end
2550 end
2551 always @(*) begin
2552         sdram_choose_req_cmd_payload_we <= 1'd0;
2553         if (sdram_choose_req_cmd_valid) begin
2554                 sdram_choose_req_cmd_payload_we <= t_array_muxed5;
2555         end
2556 end
2557 always @(*) begin
2558         sdram_bankmachine0_cmd_ready <= 1'd0;
2559         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd0))) begin
2560                 sdram_bankmachine0_cmd_ready <= 1'd1;
2561         end
2562         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd0))) begin
2563                 sdram_bankmachine0_cmd_ready <= 1'd1;
2564         end
2565 end
2566 always @(*) begin
2567         sdram_bankmachine1_cmd_ready <= 1'd0;
2568         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd1))) begin
2569                 sdram_bankmachine1_cmd_ready <= 1'd1;
2570         end
2571         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd1))) begin
2572                 sdram_bankmachine1_cmd_ready <= 1'd1;
2573         end
2574 end
2575 always @(*) begin
2576         sdram_bankmachine2_cmd_ready <= 1'd0;
2577         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd2))) begin
2578                 sdram_bankmachine2_cmd_ready <= 1'd1;
2579         end
2580         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd2))) begin
2581                 sdram_bankmachine2_cmd_ready <= 1'd1;
2582         end
2583 end
2584 always @(*) begin
2585         sdram_bankmachine3_cmd_ready <= 1'd0;
2586         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd3))) begin
2587                 sdram_bankmachine3_cmd_ready <= 1'd1;
2588         end
2589         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd3))) begin
2590                 sdram_bankmachine3_cmd_ready <= 1'd1;
2591         end
2592 end
2593 assign sdram_choose_req_ce = (sdram_choose_req_cmd_ready | (~sdram_choose_req_cmd_valid));
2594 assign sdram_dfi_p0_reset_n = 1'd1;
2595 assign sdram_dfi_p0_cke = {1{sdram_steerer0}};
2596 assign sdram_dfi_p0_odt = {1{sdram_steerer1}};
2597 always @(*) begin
2598         subfragments_multiplexer_next_state <= 3'd0;
2599         sdram_en1 <= 1'd0;
2600         sdram_choose_req_want_reads <= 1'd0;
2601         sdram_choose_req_want_writes <= 1'd0;
2602         sdram_cmd_ready <= 1'd0;
2603         sdram_choose_req_want_activates <= 1'd0;
2604         sdram_steerer_sel <= 2'd0;
2605         sdram_choose_req_cmd_ready <= 1'd0;
2606         sdram_en0 <= 1'd0;
2607         sdram_choose_req_want_activates <= sdram_ras_allowed;
2608         subfragments_multiplexer_next_state <= subfragments_multiplexer_state;
2609         case (subfragments_multiplexer_state)
2610                 1'd1: begin
2611                         sdram_en1 <= 1'd1;
2612                         sdram_choose_req_want_writes <= 1'd1;
2613                         if (1'd1) begin
2614                                 sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed));
2615                         end else begin
2616                                 sdram_choose_req_want_activates <= sdram_ras_allowed;
2617                                 sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed);
2618                                 sdram_choose_req_cmd_ready <= sdram_cas_allowed;
2619                         end
2620                         sdram_steerer_sel <= 2'd2;
2621                         if (sdram_read_available) begin
2622                                 if (((~sdram_write_available) | sdram_max_time1)) begin
2623                                         subfragments_multiplexer_next_state <= 2'd3;
2624                                 end
2625                         end
2626                         if (sdram_go_to_refresh) begin
2627                                 subfragments_multiplexer_next_state <= 2'd2;
2628                         end
2629                 end
2630                 2'd2: begin
2631                         sdram_steerer_sel <= 2'd3;
2632                         sdram_cmd_ready <= 1'd1;
2633                         if (sdram_cmd_last) begin
2634                                 subfragments_multiplexer_next_state <= 1'd0;
2635                         end
2636                 end
2637                 2'd3: begin
2638                         if (sdram_twtrcon_ready) begin
2639                                 subfragments_multiplexer_next_state <= 1'd0;
2640                         end
2641                 end
2642                 3'd4: begin
2643                         subfragments_multiplexer_next_state <= 3'd5;
2644                 end
2645                 3'd5: begin
2646                         subfragments_multiplexer_next_state <= 1'd1;
2647                 end
2648                 default: begin
2649                         sdram_en0 <= 1'd1;
2650                         sdram_choose_req_want_reads <= 1'd1;
2651                         if (1'd1) begin
2652                                 sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed));
2653                         end else begin
2654                                 sdram_choose_req_want_activates <= sdram_ras_allowed;
2655                                 sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed);
2656                                 sdram_choose_req_cmd_ready <= sdram_cas_allowed;
2657                         end
2658                         sdram_steerer_sel <= 2'd2;
2659                         if (sdram_write_available) begin
2660                                 if (((~sdram_read_available) | sdram_max_time0)) begin
2661                                         subfragments_multiplexer_next_state <= 3'd4;
2662                                 end
2663                         end
2664                         if (sdram_go_to_refresh) begin
2665                                 subfragments_multiplexer_next_state <= 2'd2;
2666                         end
2667                 end
2668         endcase
2669 end
2670 assign subfragments_roundrobin0_request = {(((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2671 assign subfragments_roundrobin0_ce = ((~sdram_interface_bank0_valid) & (~sdram_interface_bank0_lock));
2672 assign sdram_interface_bank0_addr = rhs_array_muxed12;
2673 assign sdram_interface_bank0_we = rhs_array_muxed13;
2674 assign sdram_interface_bank0_valid = rhs_array_muxed14;
2675 assign subfragments_roundrobin1_request = {(((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2676 assign subfragments_roundrobin1_ce = ((~sdram_interface_bank1_valid) & (~sdram_interface_bank1_lock));
2677 assign sdram_interface_bank1_addr = rhs_array_muxed15;
2678 assign sdram_interface_bank1_we = rhs_array_muxed16;
2679 assign sdram_interface_bank1_valid = rhs_array_muxed17;
2680 assign subfragments_roundrobin2_request = {(((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2681 assign subfragments_roundrobin2_ce = ((~sdram_interface_bank2_valid) & (~sdram_interface_bank2_lock));
2682 assign sdram_interface_bank2_addr = rhs_array_muxed18;
2683 assign sdram_interface_bank2_we = rhs_array_muxed19;
2684 assign sdram_interface_bank2_valid = rhs_array_muxed20;
2685 assign subfragments_roundrobin3_request = {(((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid)};
2686 assign subfragments_roundrobin3_ce = ((~sdram_interface_bank3_valid) & (~sdram_interface_bank3_lock));
2687 assign sdram_interface_bank3_addr = rhs_array_muxed21;
2688 assign sdram_interface_bank3_we = rhs_array_muxed22;
2689 assign sdram_interface_bank3_valid = rhs_array_muxed23;
2690 assign port_cmd_ready = ((((1'd0 | (((subfragments_roundrobin0_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank0_ready)) | (((subfragments_roundrobin1_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank1_ready)) | (((subfragments_roundrobin2_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank2_ready)) | (((subfragments_roundrobin3_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0)))))) & sdram_interface_bank3_ready));
2691 assign port_wdata_ready = subfragments_new_master_wdata_ready;
2692 assign port_rdata_valid = subfragments_new_master_rdata_valid3;
2693 always @(*) begin
2694         sdram_interface_wdata <= 16'd0;
2695         sdram_interface_wdata_we <= 2'd0;
2696         case ({subfragments_new_master_wdata_ready})
2697                 1'd1: begin
2698                         sdram_interface_wdata <= port_wdata_payload_data;
2699                         sdram_interface_wdata_we <= port_wdata_payload_we;
2700                 end
2701                 default: begin
2702                         sdram_interface_wdata <= 1'd0;
2703                         sdram_interface_wdata_we <= 1'd0;
2704                 end
2705         endcase
2706 end
2707 assign port_rdata_payload_data = sdram_interface_rdata;
2708 assign subfragments_roundrobin0_grant = 1'd0;
2709 assign subfragments_roundrobin1_grant = 1'd0;
2710 assign subfragments_roundrobin2_grant = 1'd0;
2711 assign subfragments_roundrobin3_grant = 1'd0;
2712 assign converter_reset = (~wb_sdram_cyc);
2713 always @(*) begin
2714         litedram_wb_dat_w <= 16'd0;
2715         case (converter_counter)
2716                 1'd0: begin
2717                         litedram_wb_dat_w <= wb_sdram_dat_w[31:0];
2718                 end
2719                 1'd1: begin
2720                         litedram_wb_dat_w <= wb_sdram_dat_w[31:16];
2721                 end
2722         endcase
2723 end
2724 assign wb_sdram_dat_r = {litedram_wb_dat_r, converter_dat_r[31:16]};
2725 always @(*) begin
2726         litedram_wb_sel <= 2'd0;
2727         litedram_wb_cyc <= 1'd0;
2728         litedram_wb_stb <= 1'd0;
2729         subfragments_next_state <= 1'd0;
2730         converter_counter_subfragments_next_value <= 1'd0;
2731         litedram_wb_we <= 1'd0;
2732         converter_counter_subfragments_next_value_ce <= 1'd0;
2733         converter_skip <= 1'd0;
2734         wb_sdram_ack <= 1'd0;
2735         litedram_wb_adr <= 30'd0;
2736         subfragments_next_state <= subfragments_state;
2737         case (subfragments_state)
2738                 1'd1: begin
2739                         litedram_wb_adr <= {wb_sdram_adr, converter_counter};
2740                         case (converter_counter)
2741                                 1'd0: begin
2742                                         litedram_wb_sel <= wb_sdram_sel[3:0];
2743                                 end
2744                                 1'd1: begin
2745                                         litedram_wb_sel <= wb_sdram_sel[3:2];
2746                                 end
2747                         endcase
2748                         if ((wb_sdram_stb & wb_sdram_cyc)) begin
2749                                 converter_skip <= (litedram_wb_sel == 1'd0);
2750                                 litedram_wb_we <= wb_sdram_we;
2751                                 litedram_wb_cyc <= (~converter_skip);
2752                                 litedram_wb_stb <= (~converter_skip);
2753                                 if ((litedram_wb_ack | converter_skip)) begin
2754                                         converter_counter_subfragments_next_value <= (converter_counter + 1'd1);
2755                                         converter_counter_subfragments_next_value_ce <= 1'd1;
2756                                         if ((converter_counter == 1'd1)) begin
2757                                                 wb_sdram_ack <= 1'd1;
2758                                                 subfragments_next_state <= 1'd0;
2759                                         end
2760                                 end
2761                         end
2762                 end
2763                 default: begin
2764                         converter_counter_subfragments_next_value <= 1'd0;
2765                         converter_counter_subfragments_next_value_ce <= 1'd1;
2766                         if ((wb_sdram_stb & wb_sdram_cyc)) begin
2767                                 subfragments_next_state <= 1'd1;
2768                         end
2769                 end
2770         endcase
2771 end
2772 assign port_cmd_payload_addr = (litedram_wb_adr - 31'd1207959552);
2773 assign port_cmd_payload_we = litedram_wb_we;
2774 assign port_wdata_payload_data = litedram_wb_dat_w;
2775 assign port_wdata_payload_we = litedram_wb_sel;
2776 assign litedram_wb_dat_r = port_rdata_payload_data;
2777 assign port_flush = (~litedram_wb_cyc);
2778 assign port_cmd_last = (~litedram_wb_we);
2779 assign port_cmd_valid = ((litedram_wb_cyc & litedram_wb_stb) & (~cmd_consumed));
2780 assign port_wdata_valid = (((port_cmd_valid | cmd_consumed) & port_cmd_payload_we) & (~wdata_consumed));
2781 assign port_rdata_ready = ((port_cmd_valid | cmd_consumed) & (~port_cmd_payload_we));
2782 assign litedram_wb_ack = (ack_cmd & ((litedram_wb_we & ack_wdata) | ((~litedram_wb_we) & ack_rdata)));
2783 assign ack_cmd = ((port_cmd_valid & port_cmd_ready) | cmd_consumed);
2784 assign ack_wdata = ((port_wdata_valid & port_wdata_ready) | wdata_consumed);
2785 assign ack_rdata = (port_rdata_valid & port_rdata_ready);
2786 assign uart_sink_valid = uart_phy_source_valid;
2787 assign uart_phy_source_ready = uart_sink_ready;
2788 assign uart_sink_first = uart_phy_source_first;
2789 assign uart_sink_last = uart_phy_source_last;
2790 assign uart_sink_payload_data = uart_phy_source_payload_data;
2791 assign uart_phy_sink_valid = uart_source_valid;
2792 assign uart_source_ready = uart_phy_sink_ready;
2793 assign uart_phy_sink_first = uart_source_first;
2794 assign uart_phy_sink_last = uart_source_last;
2795 assign uart_phy_sink_payload_data = uart_source_payload_data;
2796 assign tx_fifo_sink_valid = rxtx_re;
2797 assign tx_fifo_sink_payload_data = rxtx_r;
2798 assign txfull_status = (~tx_fifo_sink_ready);
2799 assign txempty_status = (~tx_fifo_source_valid);
2800 assign uart_source_valid = tx_fifo_source_valid;
2801 assign tx_fifo_source_ready = uart_source_ready;
2802 assign uart_source_first = tx_fifo_source_first;
2803 assign uart_source_last = tx_fifo_source_last;
2804 assign uart_source_payload_data = tx_fifo_source_payload_data;
2805 assign tx_trigger = (~tx_fifo_sink_ready);
2806 assign rx_fifo_sink_valid = uart_sink_valid;
2807 assign uart_sink_ready = rx_fifo_sink_ready;
2808 assign rx_fifo_sink_first = uart_sink_first;
2809 assign rx_fifo_sink_last = uart_sink_last;
2810 assign rx_fifo_sink_payload_data = uart_sink_payload_data;
2811 assign rxempty_status = (~rx_fifo_source_valid);
2812 assign rxfull_status = (~rx_fifo_sink_ready);
2813 assign rxtx_w = rx_fifo_source_payload_data;
2814 assign rx_fifo_source_ready = (rx_clear | (1'd0 & rxtx_we));
2815 assign rx_trigger = (~rx_fifo_source_valid);
2816 always @(*) begin
2817         tx_clear <= 1'd0;
2818         if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin
2819                 tx_clear <= 1'd1;
2820         end
2821 end
2822 always @(*) begin
2823         eventmanager_status_w <= 2'd0;
2824         eventmanager_status_w[0] <= tx_status;
2825         eventmanager_status_w[1] <= rx_status;
2826 end
2827 always @(*) begin
2828         rx_clear <= 1'd0;
2829         if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin
2830                 rx_clear <= 1'd1;
2831         end
2832 end
2833 always @(*) begin
2834         eventmanager_pending_w <= 2'd0;
2835         eventmanager_pending_w[0] <= tx_pending;
2836         eventmanager_pending_w[1] <= rx_pending;
2837 end
2838 assign irq = ((eventmanager_pending_w[0] & eventmanager_storage[0]) | (eventmanager_pending_w[1] & eventmanager_storage[1]));
2839 assign tx_status = tx_trigger;
2840 assign rx_status = rx_trigger;
2841 assign tx_fifo_syncfifo_din = {tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data};
2842 assign {tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data} = tx_fifo_syncfifo_dout;
2843 assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable;
2844 assign tx_fifo_syncfifo_we = tx_fifo_sink_valid;
2845 assign tx_fifo_fifo_in_first = tx_fifo_sink_first;
2846 assign tx_fifo_fifo_in_last = tx_fifo_sink_last;
2847 assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data;
2848 assign tx_fifo_source_valid = tx_fifo_readable;
2849 assign tx_fifo_source_first = tx_fifo_fifo_out_first;
2850 assign tx_fifo_source_last = tx_fifo_fifo_out_last;
2851 assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data;
2852 assign tx_fifo_re = tx_fifo_source_ready;
2853 assign tx_fifo_syncfifo_re = (tx_fifo_syncfifo_readable & ((~tx_fifo_readable) | tx_fifo_re));
2854 assign tx_fifo_level1 = (tx_fifo_level0 + tx_fifo_readable);
2855 always @(*) begin
2856         tx_fifo_wrport_adr <= 4'd0;
2857         if (tx_fifo_replace) begin
2858                 tx_fifo_wrport_adr <= (tx_fifo_produce - 1'd1);
2859         end else begin
2860                 tx_fifo_wrport_adr <= tx_fifo_produce;
2861         end
2862 end
2863 assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din;
2864 assign tx_fifo_wrport_we = (tx_fifo_syncfifo_we & (tx_fifo_syncfifo_writable | tx_fifo_replace));
2865 assign tx_fifo_do_read = (tx_fifo_syncfifo_readable & tx_fifo_syncfifo_re);
2866 assign tx_fifo_rdport_adr = tx_fifo_consume;
2867 assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r;
2868 assign tx_fifo_rdport_re = tx_fifo_do_read;
2869 assign tx_fifo_syncfifo_writable = (tx_fifo_level0 != 5'd16);
2870 assign tx_fifo_syncfifo_readable = (tx_fifo_level0 != 1'd0);
2871 assign rx_fifo_syncfifo_din = {rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data};
2872 assign {rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data} = rx_fifo_syncfifo_dout;
2873 assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable;
2874 assign rx_fifo_syncfifo_we = rx_fifo_sink_valid;
2875 assign rx_fifo_fifo_in_first = rx_fifo_sink_first;
2876 assign rx_fifo_fifo_in_last = rx_fifo_sink_last;
2877 assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data;
2878 assign rx_fifo_source_valid = rx_fifo_readable;
2879 assign rx_fifo_source_first = rx_fifo_fifo_out_first;
2880 assign rx_fifo_source_last = rx_fifo_fifo_out_last;
2881 assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data;
2882 assign rx_fifo_re = rx_fifo_source_ready;
2883 assign rx_fifo_syncfifo_re = (rx_fifo_syncfifo_readable & ((~rx_fifo_readable) | rx_fifo_re));
2884 assign rx_fifo_level1 = (rx_fifo_level0 + rx_fifo_readable);
2885 always @(*) begin
2886         rx_fifo_wrport_adr <= 4'd0;
2887         if (rx_fifo_replace) begin
2888                 rx_fifo_wrport_adr <= (rx_fifo_produce - 1'd1);
2889         end else begin
2890                 rx_fifo_wrport_adr <= rx_fifo_produce;
2891         end
2892 end
2893 assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din;
2894 assign rx_fifo_wrport_we = (rx_fifo_syncfifo_we & (rx_fifo_syncfifo_writable | rx_fifo_replace));
2895 assign rx_fifo_do_read = (rx_fifo_syncfifo_readable & rx_fifo_syncfifo_re);
2896 assign rx_fifo_rdport_adr = rx_fifo_consume;
2897 assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r;
2898 assign rx_fifo_rdport_re = rx_fifo_do_read;
2899 assign rx_fifo_syncfifo_writable = (rx_fifo_level0 != 5'd16);
2900 assign rx_fifo_syncfifo_readable = (rx_fifo_level0 != 1'd0);
2901 always @(*) begin
2902         gpio0_pads_gpio0i <= 8'd0;
2903         gpio0_pads_gpio0i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[0];
2904         gpio0_pads_gpio0i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[1];
2905         gpio0_pads_gpio0i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[2];
2906         gpio0_pads_gpio0i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[3];
2907         gpio0_pads_gpio0i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[4];
2908         gpio0_pads_gpio0i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[5];
2909         gpio0_pads_gpio0i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[6];
2910         gpio0_pads_gpio0i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[7];
2911 end
2912 always @(*) begin
2913         gpio1_pads_gpio1i <= 8'd0;
2914         gpio1_pads_gpio1i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[8];
2915         gpio1_pads_gpio1i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[9];
2916         gpio1_pads_gpio1i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[10];
2917         gpio1_pads_gpio1i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[11];
2918         gpio1_pads_gpio1i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[12];
2919         gpio1_pads_gpio1i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[13];
2920         gpio1_pads_gpio1i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[14];
2921         gpio1_pads_gpio1i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[15];
2922 end
2923 always @(*) begin
2924         libresocsim_libresoc_constraintmanager_gpio_o <= 16'd0;
2925         libresocsim_libresoc_constraintmanager_gpio_o[0] <= gpio0_pads_gpio0o[0];
2926         libresocsim_libresoc_constraintmanager_gpio_o[1] <= gpio0_pads_gpio0o[1];
2927         libresocsim_libresoc_constraintmanager_gpio_o[2] <= gpio0_pads_gpio0o[2];
2928         libresocsim_libresoc_constraintmanager_gpio_o[3] <= gpio0_pads_gpio0o[3];
2929         libresocsim_libresoc_constraintmanager_gpio_o[4] <= gpio0_pads_gpio0o[4];
2930         libresocsim_libresoc_constraintmanager_gpio_o[5] <= gpio0_pads_gpio0o[5];
2931         libresocsim_libresoc_constraintmanager_gpio_o[6] <= gpio0_pads_gpio0o[6];
2932         libresocsim_libresoc_constraintmanager_gpio_o[7] <= gpio0_pads_gpio0o[7];
2933         libresocsim_libresoc_constraintmanager_gpio_o[8] <= gpio1_pads_gpio1o[0];
2934         libresocsim_libresoc_constraintmanager_gpio_o[9] <= gpio1_pads_gpio1o[1];
2935         libresocsim_libresoc_constraintmanager_gpio_o[10] <= gpio1_pads_gpio1o[2];
2936         libresocsim_libresoc_constraintmanager_gpio_o[11] <= gpio1_pads_gpio1o[3];
2937         libresocsim_libresoc_constraintmanager_gpio_o[12] <= gpio1_pads_gpio1o[4];
2938         libresocsim_libresoc_constraintmanager_gpio_o[13] <= gpio1_pads_gpio1o[5];
2939         libresocsim_libresoc_constraintmanager_gpio_o[14] <= gpio1_pads_gpio1o[6];
2940         libresocsim_libresoc_constraintmanager_gpio_o[15] <= gpio1_pads_gpio1o[7];
2941 end
2942 always @(*) begin
2943         libresocsim_libresoc_constraintmanager_gpio_oe <= 16'd0;
2944         libresocsim_libresoc_constraintmanager_gpio_oe[0] <= gpio0_pads_gpio0oe[0];
2945         libresocsim_libresoc_constraintmanager_gpio_oe[1] <= gpio0_pads_gpio0oe[1];
2946         libresocsim_libresoc_constraintmanager_gpio_oe[2] <= gpio0_pads_gpio0oe[2];
2947         libresocsim_libresoc_constraintmanager_gpio_oe[3] <= gpio0_pads_gpio0oe[3];
2948         libresocsim_libresoc_constraintmanager_gpio_oe[4] <= gpio0_pads_gpio0oe[4];
2949         libresocsim_libresoc_constraintmanager_gpio_oe[5] <= gpio0_pads_gpio0oe[5];
2950         libresocsim_libresoc_constraintmanager_gpio_oe[6] <= gpio0_pads_gpio0oe[6];
2951         libresocsim_libresoc_constraintmanager_gpio_oe[7] <= gpio0_pads_gpio0oe[7];
2952         libresocsim_libresoc_constraintmanager_gpio_oe[8] <= gpio1_pads_gpio1oe[0];
2953         libresocsim_libresoc_constraintmanager_gpio_oe[9] <= gpio1_pads_gpio1oe[1];
2954         libresocsim_libresoc_constraintmanager_gpio_oe[10] <= gpio1_pads_gpio1oe[2];
2955         libresocsim_libresoc_constraintmanager_gpio_oe[11] <= gpio1_pads_gpio1oe[3];
2956         libresocsim_libresoc_constraintmanager_gpio_oe[12] <= gpio1_pads_gpio1oe[4];
2957         libresocsim_libresoc_constraintmanager_gpio_oe[13] <= gpio1_pads_gpio1oe[5];
2958         libresocsim_libresoc_constraintmanager_gpio_oe[14] <= gpio1_pads_gpio1oe[6];
2959         libresocsim_libresoc_constraintmanager_gpio_oe[15] <= gpio1_pads_gpio1oe[7];
2960 end
2961 assign libresocsim_libresoc_constraintmanager_i2c_scl = i2c_scl_1;
2962 assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe;
2963 assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0;
2964 assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i;
2965 always @(*) begin
2966         libresocsim_next_state <= 2'd0;
2967         libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0;
2968         libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0;
2969         libresocsim_libresocsim_adr_libresocsim_next_value1 <= 14'd0;
2970         libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0;
2971         libresocsim_libresocsim_wishbone_dat_r <= 32'd0;
2972         libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
2973         libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0;
2974         libresocsim_libresocsim_wishbone_ack <= 1'd0;
2975         libresocsim_next_state <= libresocsim_state;
2976         case (libresocsim_state)
2977                 1'd1: begin
2978                         libresocsim_libresocsim_adr_libresocsim_next_value1 <= 1'd0;
2979                         libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
2980                         libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
2981                         libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
2982                         libresocsim_next_state <= 2'd2;
2983                 end
2984                 2'd2: begin
2985                         libresocsim_libresocsim_wishbone_ack <= 1'd1;
2986                         libresocsim_libresocsim_wishbone_dat_r <= libresocsim_libresocsim_dat_r;
2987                         libresocsim_next_state <= 1'd0;
2988                 end
2989                 default: begin
2990                         libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= libresocsim_libresocsim_wishbone_dat_w;
2991                         libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd1;
2992                         if ((libresocsim_libresocsim_wishbone_cyc & libresocsim_libresocsim_wishbone_stb)) begin
2993                                 libresocsim_libresocsim_adr_libresocsim_next_value1 <= libresocsim_libresocsim_wishbone_adr;
2994                                 libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
2995                                 libresocsim_libresocsim_we_libresocsim_next_value2 <= (libresocsim_libresocsim_wishbone_we & (libresocsim_libresocsim_wishbone_sel != 1'd0));
2996                                 libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
2997                                 libresocsim_next_state <= 1'd1;
2998                         end
2999                 end
3000         endcase
3001 end
3002 assign libresocsim_shared_adr = rhs_array_muxed24;
3003 assign libresocsim_shared_dat_w = rhs_array_muxed25;
3004 assign libresocsim_shared_sel = rhs_array_muxed26;
3005 assign libresocsim_shared_cyc = rhs_array_muxed27;
3006 assign libresocsim_shared_stb = rhs_array_muxed28;
3007 assign libresocsim_shared_we = rhs_array_muxed29;
3008 assign libresocsim_shared_cti = rhs_array_muxed30;
3009 assign libresocsim_shared_bte = rhs_array_muxed31;
3010 assign libresocsim_interface0_converted_interface_dat_r = libresocsim_shared_dat_r;
3011 assign libresocsim_interface1_converted_interface_dat_r = libresocsim_shared_dat_r;
3012 assign libresocsim_libresoc_jtag_wb_dat_r = libresocsim_shared_dat_r;
3013 assign libresocsim_interface0_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd0));
3014 assign libresocsim_interface1_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd1));
3015 assign libresocsim_libresoc_jtag_wb_ack = (libresocsim_shared_ack & (libresocsim_grant == 2'd2));
3016 assign libresocsim_interface0_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd0));
3017 assign libresocsim_interface1_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd1));
3018 assign libresocsim_libresoc_jtag_wb_err = (libresocsim_shared_err & (libresocsim_grant == 2'd2));
3019 assign libresocsim_request = {libresocsim_libresoc_jtag_wb_cyc, libresocsim_interface1_converted_interface_cyc, libresocsim_interface0_converted_interface_cyc};
3020 always @(*) begin
3021         libresocsim_slave_sel <= 6'd0;
3022         libresocsim_slave_sel[0] <= (libresocsim_shared_adr[29:7] == 1'd0);
3023         libresocsim_slave_sel[1] <= (libresocsim_shared_adr[29:5] == 4'd14);
3024         libresocsim_slave_sel[2] <= (libresocsim_shared_adr[29:3] == 27'd100665344);
3025         libresocsim_slave_sel[3] <= (libresocsim_shared_adr[29:10] == 20'd786449);
3026         libresocsim_slave_sel[4] <= (libresocsim_shared_adr[29:23] == 7'd72);
3027         libresocsim_slave_sel[5] <= (libresocsim_shared_adr[29:14] == 16'd49152);
3028 end
3029 assign libresocsim_ram_bus_adr = libresocsim_shared_adr;
3030 assign libresocsim_ram_bus_dat_w = libresocsim_shared_dat_w;
3031 assign libresocsim_ram_bus_sel = libresocsim_shared_sel;
3032 assign libresocsim_ram_bus_stb = libresocsim_shared_stb;
3033 assign libresocsim_ram_bus_we = libresocsim_shared_we;
3034 assign libresocsim_ram_bus_cti = libresocsim_shared_cti;
3035 assign libresocsim_ram_bus_bte = libresocsim_shared_bte;
3036 assign ram_bus_ram_bus_adr = libresocsim_shared_adr;
3037 assign ram_bus_ram_bus_dat_w = libresocsim_shared_dat_w;
3038 assign ram_bus_ram_bus_sel = libresocsim_shared_sel;
3039 assign ram_bus_ram_bus_stb = libresocsim_shared_stb;
3040 assign ram_bus_ram_bus_we = libresocsim_shared_we;
3041 assign ram_bus_ram_bus_cti = libresocsim_shared_cti;
3042 assign ram_bus_ram_bus_bte = libresocsim_shared_bte;
3043 assign libresocsim_libresoc_xics_icp_adr = libresocsim_shared_adr;
3044 assign libresocsim_libresoc_xics_icp_dat_w = libresocsim_shared_dat_w;
3045 assign libresocsim_libresoc_xics_icp_sel = libresocsim_shared_sel;
3046 assign libresocsim_libresoc_xics_icp_stb = libresocsim_shared_stb;
3047 assign libresocsim_libresoc_xics_icp_we = libresocsim_shared_we;
3048 assign libresocsim_libresoc_xics_icp_cti = libresocsim_shared_cti;
3049 assign libresocsim_libresoc_xics_icp_bte = libresocsim_shared_bte;
3050 assign libresocsim_libresoc_xics_ics_adr = libresocsim_shared_adr;
3051 assign libresocsim_libresoc_xics_ics_dat_w = libresocsim_shared_dat_w;
3052 assign libresocsim_libresoc_xics_ics_sel = libresocsim_shared_sel;
3053 assign libresocsim_libresoc_xics_ics_stb = libresocsim_shared_stb;
3054 assign libresocsim_libresoc_xics_ics_we = libresocsim_shared_we;
3055 assign libresocsim_libresoc_xics_ics_cti = libresocsim_shared_cti;
3056 assign libresocsim_libresoc_xics_ics_bte = libresocsim_shared_bte;
3057 assign wb_sdram_adr = libresocsim_shared_adr;
3058 assign wb_sdram_dat_w = libresocsim_shared_dat_w;
3059 assign wb_sdram_sel = libresocsim_shared_sel;
3060 assign wb_sdram_stb = libresocsim_shared_stb;
3061 assign wb_sdram_we = libresocsim_shared_we;
3062 assign wb_sdram_cti = libresocsim_shared_cti;
3063 assign wb_sdram_bte = libresocsim_shared_bte;
3064 assign libresocsim_libresocsim_wishbone_adr = libresocsim_shared_adr;
3065 assign libresocsim_libresocsim_wishbone_dat_w = libresocsim_shared_dat_w;
3066 assign libresocsim_libresocsim_wishbone_sel = libresocsim_shared_sel;
3067 assign libresocsim_libresocsim_wishbone_stb = libresocsim_shared_stb;
3068 assign libresocsim_libresocsim_wishbone_we = libresocsim_shared_we;
3069 assign libresocsim_libresocsim_wishbone_cti = libresocsim_shared_cti;
3070 assign libresocsim_libresocsim_wishbone_bte = libresocsim_shared_bte;
3071 assign libresocsim_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[0]);
3072 assign ram_bus_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[1]);
3073 assign libresocsim_libresoc_xics_icp_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[2]);
3074 assign libresocsim_libresoc_xics_ics_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[3]);
3075 assign wb_sdram_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[4]);
3076 assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[5]);
3077 assign libresocsim_shared_err = (((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err);
3078 assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack));
3079 always @(*) begin
3080         libresocsim_shared_ack <= 1'd0;
3081         libresocsim_error <= 1'd0;
3082         libresocsim_shared_dat_r <= 32'd0;
3083         libresocsim_shared_ack <= (((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack);
3084         libresocsim_shared_dat_r <= (((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & libresocsim_libresocsim_wishbone_dat_r));
3085         if (libresocsim_done) begin
3086                 libresocsim_shared_dat_r <= 32'd4294967295;
3087                 libresocsim_shared_ack <= 1'd1;
3088                 libresocsim_error <= 1'd1;
3089         end
3090 end
3091 assign libresocsim_done = (libresocsim_count == 1'd0);
3092 assign libresocsim_csrbank0_sel = (libresocsim_interface0_bank_bus_adr[13:9] == 1'd0);
3093 assign libresocsim_csrbank0_reset0_r = libresocsim_interface0_bank_bus_dat_w[0];
3094 assign libresocsim_csrbank0_reset0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3095 assign libresocsim_csrbank0_reset0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3096 assign libresocsim_csrbank0_scratch3_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3097 assign libresocsim_csrbank0_scratch3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3098 assign libresocsim_csrbank0_scratch3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3099 assign libresocsim_csrbank0_scratch2_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3100 assign libresocsim_csrbank0_scratch2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3101 assign libresocsim_csrbank0_scratch2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3102 assign libresocsim_csrbank0_scratch1_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3103 assign libresocsim_csrbank0_scratch1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3104 assign libresocsim_csrbank0_scratch1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3105 assign libresocsim_csrbank0_scratch0_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3106 assign libresocsim_csrbank0_scratch0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3107 assign libresocsim_csrbank0_scratch0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3108 assign libresocsim_csrbank0_bus_errors3_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3109 assign libresocsim_csrbank0_bus_errors3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3110 assign libresocsim_csrbank0_bus_errors3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3111 assign libresocsim_csrbank0_bus_errors2_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3112 assign libresocsim_csrbank0_bus_errors2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3113 assign libresocsim_csrbank0_bus_errors2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3114 assign libresocsim_csrbank0_bus_errors1_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3115 assign libresocsim_csrbank0_bus_errors1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3116 assign libresocsim_csrbank0_bus_errors1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3117 assign libresocsim_csrbank0_bus_errors0_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3118 assign libresocsim_csrbank0_bus_errors0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3119 assign libresocsim_csrbank0_bus_errors0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3120 assign libresocsim_csrbank0_reset0_w = libresocsim_reset_storage;
3121 assign libresocsim_csrbank0_scratch3_w = libresocsim_scratch_storage[31:24];
3122 assign libresocsim_csrbank0_scratch2_w = libresocsim_scratch_storage[23:16];
3123 assign libresocsim_csrbank0_scratch1_w = libresocsim_scratch_storage[15:8];
3124 assign libresocsim_csrbank0_scratch0_w = libresocsim_scratch_storage[7:0];
3125 assign libresocsim_csrbank0_bus_errors3_w = libresocsim_bus_errors_status[31:24];
3126 assign libresocsim_csrbank0_bus_errors2_w = libresocsim_bus_errors_status[23:16];
3127 assign libresocsim_csrbank0_bus_errors1_w = libresocsim_bus_errors_status[15:8];
3128 assign libresocsim_csrbank0_bus_errors0_w = libresocsim_bus_errors_status[7:0];
3129 assign libresocsim_bus_errors_we = libresocsim_csrbank0_bus_errors0_we;
3130 assign libresocsim_csrbank1_sel = (libresocsim_interface1_bank_bus_adr[13:9] == 3'd6);
3131 assign libresocsim_csrbank1_oe0_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3132 assign libresocsim_csrbank1_oe0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3133 assign libresocsim_csrbank1_oe0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3134 assign libresocsim_csrbank1_in_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3135 assign libresocsim_csrbank1_in_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3136 assign libresocsim_csrbank1_in_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3137 assign libresocsim_csrbank1_out0_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3138 assign libresocsim_csrbank1_out0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3139 assign libresocsim_csrbank1_out0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3140 assign libresocsim_csrbank1_oe0_w = gpio0_oe_storage[7:0];
3141 assign libresocsim_csrbank1_in_w = gpio0_status[7:0];
3142 assign gpio0_we = libresocsim_csrbank1_in_we;
3143 assign libresocsim_csrbank1_out0_w = gpio0_out_storage[7:0];
3144 assign libresocsim_csrbank2_sel = (libresocsim_interface2_bank_bus_adr[13:9] == 3'd7);
3145 assign libresocsim_csrbank2_oe0_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3146 assign libresocsim_csrbank2_oe0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3147 assign libresocsim_csrbank2_oe0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3148 assign libresocsim_csrbank2_in_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3149 assign libresocsim_csrbank2_in_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3150 assign libresocsim_csrbank2_in_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3151 assign libresocsim_csrbank2_out0_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3152 assign libresocsim_csrbank2_out0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3153 assign libresocsim_csrbank2_out0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3154 assign libresocsim_csrbank2_oe0_w = gpio1_oe_storage[7:0];
3155 assign libresocsim_csrbank2_in_w = gpio1_status[7:0];
3156 assign gpio1_we = libresocsim_csrbank2_in_we;
3157 assign libresocsim_csrbank2_out0_w = gpio1_out_storage[7:0];
3158 assign libresocsim_csrbank3_sel = (libresocsim_interface3_bank_bus_adr[13:9] == 4'd8);
3159 assign libresocsim_csrbank3_w0_r = libresocsim_interface3_bank_bus_dat_w[2:0];
3160 assign libresocsim_csrbank3_w0_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3161 assign libresocsim_csrbank3_w0_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3162 assign libresocsim_csrbank3_r_r = libresocsim_interface3_bank_bus_dat_w[0];
3163 assign libresocsim_csrbank3_r_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3164 assign libresocsim_csrbank3_r_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3165 assign i2c_scl_1 = i2c_storage[0];
3166 assign i2c_oe = i2c_storage[1];
3167 assign i2c_sda0 = i2c_storage[2];
3168 assign libresocsim_csrbank3_w0_w = i2c_storage[2:0];
3169 assign i2c_status = i2c_sda1;
3170 assign libresocsim_csrbank3_r_w = i2c_status;
3171 assign i2c_we = libresocsim_csrbank3_r_we;
3172 assign libresocsim_csrbank4_sel = (libresocsim_interface4_bank_bus_adr[13:9] == 2'd3);
3173 assign libresocsim_csrbank4_dfii_control0_r = libresocsim_interface4_bank_bus_dat_w[3:0];
3174 assign libresocsim_csrbank4_dfii_control0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3175 assign libresocsim_csrbank4_dfii_control0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3176 assign libresocsim_csrbank4_dfii_pi0_command0_r = libresocsim_interface4_bank_bus_dat_w[5:0];
3177 assign libresocsim_csrbank4_dfii_pi0_command0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3178 assign libresocsim_csrbank4_dfii_pi0_command0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3179 assign sdram_command_issue_r = libresocsim_interface4_bank_bus_dat_w[0];
3180 assign sdram_command_issue_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3181 assign sdram_command_issue_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3182 assign libresocsim_csrbank4_dfii_pi0_address1_r = libresocsim_interface4_bank_bus_dat_w[4:0];
3183 assign libresocsim_csrbank4_dfii_pi0_address1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3184 assign libresocsim_csrbank4_dfii_pi0_address1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3185 assign libresocsim_csrbank4_dfii_pi0_address0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3186 assign libresocsim_csrbank4_dfii_pi0_address0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3187 assign libresocsim_csrbank4_dfii_pi0_address0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3188 assign libresocsim_csrbank4_dfii_pi0_baddress0_r = libresocsim_interface4_bank_bus_dat_w[1:0];
3189 assign libresocsim_csrbank4_dfii_pi0_baddress0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3190 assign libresocsim_csrbank4_dfii_pi0_baddress0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3191 assign libresocsim_csrbank4_dfii_pi0_wrdata1_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3192 assign libresocsim_csrbank4_dfii_pi0_wrdata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3193 assign libresocsim_csrbank4_dfii_pi0_wrdata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3194 assign libresocsim_csrbank4_dfii_pi0_wrdata0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3195 assign libresocsim_csrbank4_dfii_pi0_wrdata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3196 assign libresocsim_csrbank4_dfii_pi0_wrdata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3197 assign libresocsim_csrbank4_dfii_pi0_rddata1_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3198 assign libresocsim_csrbank4_dfii_pi0_rddata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3199 assign libresocsim_csrbank4_dfii_pi0_rddata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3200 assign libresocsim_csrbank4_dfii_pi0_rddata0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3201 assign libresocsim_csrbank4_dfii_pi0_rddata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3202 assign libresocsim_csrbank4_dfii_pi0_rddata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3203 assign sdram_sel = sdram_storage[0];
3204 assign sdram_cke_1 = sdram_storage[1];
3205 assign sdram_odt = sdram_storage[2];
3206 assign sdram_reset_n = sdram_storage[3];
3207 assign libresocsim_csrbank4_dfii_control0_w = sdram_storage[3:0];
3208 assign libresocsim_csrbank4_dfii_pi0_command0_w = sdram_command_storage[5:0];
3209 assign libresocsim_csrbank4_dfii_pi0_address1_w = sdram_address_storage[12:8];
3210 assign libresocsim_csrbank4_dfii_pi0_address0_w = sdram_address_storage[7:0];
3211 assign libresocsim_csrbank4_dfii_pi0_baddress0_w = sdram_baddress_storage[1:0];
3212 assign libresocsim_csrbank4_dfii_pi0_wrdata1_w = sdram_wrdata_storage[15:8];
3213 assign libresocsim_csrbank4_dfii_pi0_wrdata0_w = sdram_wrdata_storage[7:0];
3214 assign libresocsim_csrbank4_dfii_pi0_rddata1_w = sdram_status[15:8];
3215 assign libresocsim_csrbank4_dfii_pi0_rddata0_w = sdram_status[7:0];
3216 assign sdram_we = libresocsim_csrbank4_dfii_pi0_rddata0_we;
3217 assign libresocsim_csrbank5_sel = (libresocsim_interface5_bank_bus_adr[13:9] == 2'd2);
3218 assign libresocsim_csrbank5_load3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3219 assign libresocsim_csrbank5_load3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3220 assign libresocsim_csrbank5_load3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3221 assign libresocsim_csrbank5_load2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3222 assign libresocsim_csrbank5_load2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3223 assign libresocsim_csrbank5_load2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3224 assign libresocsim_csrbank5_load1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3225 assign libresocsim_csrbank5_load1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3226 assign libresocsim_csrbank5_load1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3227 assign libresocsim_csrbank5_load0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3228 assign libresocsim_csrbank5_load0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3229 assign libresocsim_csrbank5_load0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3230 assign libresocsim_csrbank5_reload3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3231 assign libresocsim_csrbank5_reload3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3232 assign libresocsim_csrbank5_reload3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3233 assign libresocsim_csrbank5_reload2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3234 assign libresocsim_csrbank5_reload2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3235 assign libresocsim_csrbank5_reload2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3236 assign libresocsim_csrbank5_reload1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3237 assign libresocsim_csrbank5_reload1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3238 assign libresocsim_csrbank5_reload1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3239 assign libresocsim_csrbank5_reload0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3240 assign libresocsim_csrbank5_reload0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3241 assign libresocsim_csrbank5_reload0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3242 assign libresocsim_csrbank5_en0_r = libresocsim_interface5_bank_bus_dat_w[0];
3243 assign libresocsim_csrbank5_en0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3244 assign libresocsim_csrbank5_en0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3245 assign libresocsim_csrbank5_update_value0_r = libresocsim_interface5_bank_bus_dat_w[0];
3246 assign libresocsim_csrbank5_update_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3247 assign libresocsim_csrbank5_update_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3248 assign libresocsim_csrbank5_value3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3249 assign libresocsim_csrbank5_value3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3250 assign libresocsim_csrbank5_value3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3251 assign libresocsim_csrbank5_value2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3252 assign libresocsim_csrbank5_value2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3253 assign libresocsim_csrbank5_value2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3254 assign libresocsim_csrbank5_value1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3255 assign libresocsim_csrbank5_value1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3256 assign libresocsim_csrbank5_value1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3257 assign libresocsim_csrbank5_value0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3258 assign libresocsim_csrbank5_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3259 assign libresocsim_csrbank5_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3260 assign libresocsim_eventmanager_status_r = libresocsim_interface5_bank_bus_dat_w[0];
3261 assign libresocsim_eventmanager_status_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3262 assign libresocsim_eventmanager_status_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3263 assign libresocsim_eventmanager_pending_r = libresocsim_interface5_bank_bus_dat_w[0];
3264 assign libresocsim_eventmanager_pending_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3265 assign libresocsim_eventmanager_pending_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3266 assign libresocsim_csrbank5_ev_enable0_r = libresocsim_interface5_bank_bus_dat_w[0];
3267 assign libresocsim_csrbank5_ev_enable0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3268 assign libresocsim_csrbank5_ev_enable0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3269 assign libresocsim_csrbank5_load3_w = libresocsim_load_storage[31:24];
3270 assign libresocsim_csrbank5_load2_w = libresocsim_load_storage[23:16];
3271 assign libresocsim_csrbank5_load1_w = libresocsim_load_storage[15:8];
3272 assign libresocsim_csrbank5_load0_w = libresocsim_load_storage[7:0];
3273 assign libresocsim_csrbank5_reload3_w = libresocsim_reload_storage[31:24];
3274 assign libresocsim_csrbank5_reload2_w = libresocsim_reload_storage[23:16];
3275 assign libresocsim_csrbank5_reload1_w = libresocsim_reload_storage[15:8];
3276 assign libresocsim_csrbank5_reload0_w = libresocsim_reload_storage[7:0];
3277 assign libresocsim_csrbank5_en0_w = libresocsim_en_storage;
3278 assign libresocsim_csrbank5_update_value0_w = libresocsim_update_value_storage;
3279 assign libresocsim_csrbank5_value3_w = libresocsim_value_status[31:24];
3280 assign libresocsim_csrbank5_value2_w = libresocsim_value_status[23:16];
3281 assign libresocsim_csrbank5_value1_w = libresocsim_value_status[15:8];
3282 assign libresocsim_csrbank5_value0_w = libresocsim_value_status[7:0];
3283 assign libresocsim_value_we = libresocsim_csrbank5_value0_we;
3284 assign libresocsim_csrbank5_ev_enable0_w = libresocsim_eventmanager_storage;
3285 assign libresocsim_csrbank6_sel = (libresocsim_interface6_bank_bus_adr[13:9] == 3'd5);
3286 assign rxtx_r = libresocsim_interface6_bank_bus_dat_w[7:0];
3287 assign rxtx_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3288 assign rxtx_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3289 assign libresocsim_csrbank6_txfull_r = libresocsim_interface6_bank_bus_dat_w[0];
3290 assign libresocsim_csrbank6_txfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3291 assign libresocsim_csrbank6_txfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3292 assign libresocsim_csrbank6_rxempty_r = libresocsim_interface6_bank_bus_dat_w[0];
3293 assign libresocsim_csrbank6_rxempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3294 assign libresocsim_csrbank6_rxempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3295 assign eventmanager_status_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3296 assign eventmanager_status_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3297 assign eventmanager_status_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3298 assign eventmanager_pending_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3299 assign eventmanager_pending_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3300 assign eventmanager_pending_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3301 assign libresocsim_csrbank6_ev_enable0_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3302 assign libresocsim_csrbank6_ev_enable0_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3303 assign libresocsim_csrbank6_ev_enable0_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3304 assign libresocsim_csrbank6_txempty_r = libresocsim_interface6_bank_bus_dat_w[0];
3305 assign libresocsim_csrbank6_txempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3306 assign libresocsim_csrbank6_txempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3307 assign libresocsim_csrbank6_rxfull_r = libresocsim_interface6_bank_bus_dat_w[0];
3308 assign libresocsim_csrbank6_rxfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3309 assign libresocsim_csrbank6_rxfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3310 assign libresocsim_csrbank6_txfull_w = txfull_status;
3311 assign txfull_we = libresocsim_csrbank6_txfull_we;
3312 assign libresocsim_csrbank6_rxempty_w = rxempty_status;
3313 assign rxempty_we = libresocsim_csrbank6_rxempty_we;
3314 assign libresocsim_csrbank6_ev_enable0_w = eventmanager_storage[1:0];
3315 assign libresocsim_csrbank6_txempty_w = txempty_status;
3316 assign txempty_we = libresocsim_csrbank6_txempty_we;
3317 assign libresocsim_csrbank6_rxfull_w = rxfull_status;
3318 assign rxfull_we = libresocsim_csrbank6_rxfull_we;
3319 assign libresocsim_csrbank7_sel = (libresocsim_interface7_bank_bus_adr[13:9] == 3'd4);
3320 assign libresocsim_csrbank7_tuning_word3_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3321 assign libresocsim_csrbank7_tuning_word3_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3322 assign libresocsim_csrbank7_tuning_word3_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3323 assign libresocsim_csrbank7_tuning_word2_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3324 assign libresocsim_csrbank7_tuning_word2_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3325 assign libresocsim_csrbank7_tuning_word2_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3326 assign libresocsim_csrbank7_tuning_word1_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3327 assign libresocsim_csrbank7_tuning_word1_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3328 assign libresocsim_csrbank7_tuning_word1_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3329 assign libresocsim_csrbank7_tuning_word0_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3330 assign libresocsim_csrbank7_tuning_word0_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3331 assign libresocsim_csrbank7_tuning_word0_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3332 assign libresocsim_csrbank7_tuning_word3_w = uart_phy_storage[31:24];
3333 assign libresocsim_csrbank7_tuning_word2_w = uart_phy_storage[23:16];
3334 assign libresocsim_csrbank7_tuning_word1_w = uart_phy_storage[15:8];
3335 assign libresocsim_csrbank7_tuning_word0_w = uart_phy_storage[7:0];
3336 assign libresocsim_csr_interconnect_adr = libresocsim_libresocsim_adr;
3337 assign libresocsim_csr_interconnect_we = libresocsim_libresocsim_we;
3338 assign libresocsim_csr_interconnect_dat_w = libresocsim_libresocsim_dat_w;
3339 assign libresocsim_libresocsim_dat_r = libresocsim_csr_interconnect_dat_r;
3340 assign libresocsim_interface0_bank_bus_adr = libresocsim_csr_interconnect_adr;
3341 assign libresocsim_interface1_bank_bus_adr = libresocsim_csr_interconnect_adr;
3342 assign libresocsim_interface2_bank_bus_adr = libresocsim_csr_interconnect_adr;
3343 assign libresocsim_interface3_bank_bus_adr = libresocsim_csr_interconnect_adr;
3344 assign libresocsim_interface4_bank_bus_adr = libresocsim_csr_interconnect_adr;
3345 assign libresocsim_interface5_bank_bus_adr = libresocsim_csr_interconnect_adr;
3346 assign libresocsim_interface6_bank_bus_adr = libresocsim_csr_interconnect_adr;
3347 assign libresocsim_interface7_bank_bus_adr = libresocsim_csr_interconnect_adr;
3348 assign libresocsim_interface0_bank_bus_we = libresocsim_csr_interconnect_we;
3349 assign libresocsim_interface1_bank_bus_we = libresocsim_csr_interconnect_we;
3350 assign libresocsim_interface2_bank_bus_we = libresocsim_csr_interconnect_we;
3351 assign libresocsim_interface3_bank_bus_we = libresocsim_csr_interconnect_we;
3352 assign libresocsim_interface4_bank_bus_we = libresocsim_csr_interconnect_we;
3353 assign libresocsim_interface5_bank_bus_we = libresocsim_csr_interconnect_we;
3354 assign libresocsim_interface6_bank_bus_we = libresocsim_csr_interconnect_we;
3355 assign libresocsim_interface7_bank_bus_we = libresocsim_csr_interconnect_we;
3356 assign libresocsim_interface0_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3357 assign libresocsim_interface1_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3358 assign libresocsim_interface2_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3359 assign libresocsim_interface3_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3360 assign libresocsim_interface4_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3361 assign libresocsim_interface5_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3362 assign libresocsim_interface6_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3363 assign libresocsim_interface7_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3364 assign libresocsim_csr_interconnect_dat_r = (((((((libresocsim_interface0_bank_bus_dat_r | libresocsim_interface1_bank_bus_dat_r) | libresocsim_interface2_bank_bus_dat_r) | libresocsim_interface3_bank_bus_dat_r) | libresocsim_interface4_bank_bus_dat_r) | libresocsim_interface5_bank_bus_dat_r) | libresocsim_interface6_bank_bus_dat_r) | libresocsim_interface7_bank_bus_dat_r);
3365 always @(*) begin
3366         rhs_array_muxed0 <= 1'd0;
3367         case (sdram_choose_cmd_grant)
3368                 1'd0: begin
3369                         rhs_array_muxed0 <= sdram_choose_cmd_valids[0];
3370                 end
3371                 1'd1: begin
3372                         rhs_array_muxed0 <= sdram_choose_cmd_valids[1];
3373                 end
3374                 2'd2: begin
3375                         rhs_array_muxed0 <= sdram_choose_cmd_valids[2];
3376                 end
3377                 default: begin
3378                         rhs_array_muxed0 <= sdram_choose_cmd_valids[3];
3379                 end
3380         endcase
3381 end
3382 always @(*) begin
3383         rhs_array_muxed1 <= 13'd0;
3384         case (sdram_choose_cmd_grant)
3385                 1'd0: begin
3386                         rhs_array_muxed1 <= sdram_bankmachine0_cmd_payload_a;
3387                 end
3388                 1'd1: begin
3389                         rhs_array_muxed1 <= sdram_bankmachine1_cmd_payload_a;
3390                 end
3391                 2'd2: begin
3392                         rhs_array_muxed1 <= sdram_bankmachine2_cmd_payload_a;
3393                 end
3394                 default: begin
3395                         rhs_array_muxed1 <= sdram_bankmachine3_cmd_payload_a;
3396                 end
3397         endcase
3398 end
3399 always @(*) begin
3400         rhs_array_muxed2 <= 2'd0;
3401         case (sdram_choose_cmd_grant)
3402                 1'd0: begin
3403                         rhs_array_muxed2 <= sdram_bankmachine0_cmd_payload_ba;
3404                 end
3405                 1'd1: begin
3406                         rhs_array_muxed2 <= sdram_bankmachine1_cmd_payload_ba;
3407                 end
3408                 2'd2: begin
3409                         rhs_array_muxed2 <= sdram_bankmachine2_cmd_payload_ba;
3410                 end
3411                 default: begin
3412                         rhs_array_muxed2 <= sdram_bankmachine3_cmd_payload_ba;
3413                 end
3414         endcase
3415 end
3416 always @(*) begin
3417         rhs_array_muxed3 <= 1'd0;
3418         case (sdram_choose_cmd_grant)
3419                 1'd0: begin
3420                         rhs_array_muxed3 <= sdram_bankmachine0_cmd_payload_is_read;
3421                 end
3422                 1'd1: begin
3423                         rhs_array_muxed3 <= sdram_bankmachine1_cmd_payload_is_read;
3424                 end
3425                 2'd2: begin
3426                         rhs_array_muxed3 <= sdram_bankmachine2_cmd_payload_is_read;
3427                 end
3428                 default: begin
3429                         rhs_array_muxed3 <= sdram_bankmachine3_cmd_payload_is_read;
3430                 end
3431         endcase
3432 end
3433 always @(*) begin
3434         rhs_array_muxed4 <= 1'd0;
3435         case (sdram_choose_cmd_grant)
3436                 1'd0: begin
3437                         rhs_array_muxed4 <= sdram_bankmachine0_cmd_payload_is_write;
3438                 end
3439                 1'd1: begin
3440                         rhs_array_muxed4 <= sdram_bankmachine1_cmd_payload_is_write;
3441                 end
3442                 2'd2: begin
3443                         rhs_array_muxed4 <= sdram_bankmachine2_cmd_payload_is_write;
3444                 end
3445                 default: begin
3446                         rhs_array_muxed4 <= sdram_bankmachine3_cmd_payload_is_write;
3447                 end
3448         endcase
3449 end
3450 always @(*) begin
3451         rhs_array_muxed5 <= 1'd0;
3452         case (sdram_choose_cmd_grant)
3453                 1'd0: begin
3454                         rhs_array_muxed5 <= sdram_bankmachine0_cmd_payload_is_cmd;
3455                 end
3456                 1'd1: begin
3457                         rhs_array_muxed5 <= sdram_bankmachine1_cmd_payload_is_cmd;
3458                 end
3459                 2'd2: begin
3460                         rhs_array_muxed5 <= sdram_bankmachine2_cmd_payload_is_cmd;
3461                 end
3462                 default: begin
3463                         rhs_array_muxed5 <= sdram_bankmachine3_cmd_payload_is_cmd;
3464                 end
3465         endcase
3466 end
3467 always @(*) begin
3468         t_array_muxed0 <= 1'd0;
3469         case (sdram_choose_cmd_grant)
3470                 1'd0: begin
3471                         t_array_muxed0 <= sdram_bankmachine0_cmd_payload_cas;
3472                 end
3473                 1'd1: begin
3474                         t_array_muxed0 <= sdram_bankmachine1_cmd_payload_cas;
3475                 end
3476                 2'd2: begin
3477                         t_array_muxed0 <= sdram_bankmachine2_cmd_payload_cas;
3478                 end
3479                 default: begin
3480                         t_array_muxed0 <= sdram_bankmachine3_cmd_payload_cas;
3481                 end
3482         endcase
3483 end
3484 always @(*) begin
3485         t_array_muxed1 <= 1'd0;
3486         case (sdram_choose_cmd_grant)
3487                 1'd0: begin
3488                         t_array_muxed1 <= sdram_bankmachine0_cmd_payload_ras;
3489                 end
3490                 1'd1: begin
3491                         t_array_muxed1 <= sdram_bankmachine1_cmd_payload_ras;
3492                 end
3493                 2'd2: begin
3494                         t_array_muxed1 <= sdram_bankmachine2_cmd_payload_ras;
3495                 end
3496                 default: begin
3497                         t_array_muxed1 <= sdram_bankmachine3_cmd_payload_ras;
3498                 end
3499         endcase
3500 end
3501 always @(*) begin
3502         t_array_muxed2 <= 1'd0;
3503         case (sdram_choose_cmd_grant)
3504                 1'd0: begin
3505                         t_array_muxed2 <= sdram_bankmachine0_cmd_payload_we;
3506                 end
3507                 1'd1: begin
3508                         t_array_muxed2 <= sdram_bankmachine1_cmd_payload_we;
3509                 end
3510                 2'd2: begin
3511                         t_array_muxed2 <= sdram_bankmachine2_cmd_payload_we;
3512                 end
3513                 default: begin
3514                         t_array_muxed2 <= sdram_bankmachine3_cmd_payload_we;
3515                 end
3516         endcase
3517 end
3518 always @(*) begin
3519         rhs_array_muxed6 <= 1'd0;
3520         case (sdram_choose_req_grant)
3521                 1'd0: begin
3522                         rhs_array_muxed6 <= sdram_choose_req_valids[0];
3523                 end
3524                 1'd1: begin
3525                         rhs_array_muxed6 <= sdram_choose_req_valids[1];
3526                 end
3527                 2'd2: begin
3528                         rhs_array_muxed6 <= sdram_choose_req_valids[2];
3529                 end
3530                 default: begin
3531                         rhs_array_muxed6 <= sdram_choose_req_valids[3];
3532                 end
3533         endcase
3534 end
3535 always @(*) begin
3536         rhs_array_muxed7 <= 13'd0;
3537         case (sdram_choose_req_grant)
3538                 1'd0: begin
3539                         rhs_array_muxed7 <= sdram_bankmachine0_cmd_payload_a;
3540                 end
3541                 1'd1: begin
3542                         rhs_array_muxed7 <= sdram_bankmachine1_cmd_payload_a;
3543                 end
3544                 2'd2: begin
3545                         rhs_array_muxed7 <= sdram_bankmachine2_cmd_payload_a;
3546                 end
3547                 default: begin
3548                         rhs_array_muxed7 <= sdram_bankmachine3_cmd_payload_a;
3549                 end
3550         endcase
3551 end
3552 always @(*) begin
3553         rhs_array_muxed8 <= 2'd0;
3554         case (sdram_choose_req_grant)
3555                 1'd0: begin
3556                         rhs_array_muxed8 <= sdram_bankmachine0_cmd_payload_ba;
3557                 end
3558                 1'd1: begin
3559                         rhs_array_muxed8 <= sdram_bankmachine1_cmd_payload_ba;
3560                 end
3561                 2'd2: begin
3562                         rhs_array_muxed8 <= sdram_bankmachine2_cmd_payload_ba;
3563                 end
3564                 default: begin
3565                         rhs_array_muxed8 <= sdram_bankmachine3_cmd_payload_ba;
3566                 end
3567         endcase
3568 end
3569 always @(*) begin
3570         rhs_array_muxed9 <= 1'd0;
3571         case (sdram_choose_req_grant)
3572                 1'd0: begin
3573                         rhs_array_muxed9 <= sdram_bankmachine0_cmd_payload_is_read;
3574                 end
3575                 1'd1: begin
3576                         rhs_array_muxed9 <= sdram_bankmachine1_cmd_payload_is_read;
3577                 end
3578                 2'd2: begin
3579                         rhs_array_muxed9 <= sdram_bankmachine2_cmd_payload_is_read;
3580                 end
3581                 default: begin
3582                         rhs_array_muxed9 <= sdram_bankmachine3_cmd_payload_is_read;
3583                 end
3584         endcase
3585 end
3586 always @(*) begin
3587         rhs_array_muxed10 <= 1'd0;
3588         case (sdram_choose_req_grant)
3589                 1'd0: begin
3590                         rhs_array_muxed10 <= sdram_bankmachine0_cmd_payload_is_write;
3591                 end
3592                 1'd1: begin
3593                         rhs_array_muxed10 <= sdram_bankmachine1_cmd_payload_is_write;
3594                 end
3595                 2'd2: begin
3596                         rhs_array_muxed10 <= sdram_bankmachine2_cmd_payload_is_write;
3597                 end
3598                 default: begin
3599                         rhs_array_muxed10 <= sdram_bankmachine3_cmd_payload_is_write;
3600                 end
3601         endcase
3602 end
3603 always @(*) begin
3604         rhs_array_muxed11 <= 1'd0;
3605         case (sdram_choose_req_grant)
3606                 1'd0: begin
3607                         rhs_array_muxed11 <= sdram_bankmachine0_cmd_payload_is_cmd;
3608                 end
3609                 1'd1: begin
3610                         rhs_array_muxed11 <= sdram_bankmachine1_cmd_payload_is_cmd;
3611                 end
3612                 2'd2: begin
3613                         rhs_array_muxed11 <= sdram_bankmachine2_cmd_payload_is_cmd;
3614                 end
3615                 default: begin
3616                         rhs_array_muxed11 <= sdram_bankmachine3_cmd_payload_is_cmd;
3617                 end
3618         endcase
3619 end
3620 always @(*) begin
3621         t_array_muxed3 <= 1'd0;
3622         case (sdram_choose_req_grant)
3623                 1'd0: begin
3624                         t_array_muxed3 <= sdram_bankmachine0_cmd_payload_cas;
3625                 end
3626                 1'd1: begin
3627                         t_array_muxed3 <= sdram_bankmachine1_cmd_payload_cas;
3628                 end
3629                 2'd2: begin
3630                         t_array_muxed3 <= sdram_bankmachine2_cmd_payload_cas;
3631                 end
3632                 default: begin
3633                         t_array_muxed3 <= sdram_bankmachine3_cmd_payload_cas;
3634                 end
3635         endcase
3636 end
3637 always @(*) begin
3638         t_array_muxed4 <= 1'd0;
3639         case (sdram_choose_req_grant)
3640                 1'd0: begin
3641                         t_array_muxed4 <= sdram_bankmachine0_cmd_payload_ras;
3642                 end
3643                 1'd1: begin
3644                         t_array_muxed4 <= sdram_bankmachine1_cmd_payload_ras;
3645                 end
3646                 2'd2: begin
3647                         t_array_muxed4 <= sdram_bankmachine2_cmd_payload_ras;
3648                 end
3649                 default: begin
3650                         t_array_muxed4 <= sdram_bankmachine3_cmd_payload_ras;
3651                 end
3652         endcase
3653 end
3654 always @(*) begin
3655         t_array_muxed5 <= 1'd0;
3656         case (sdram_choose_req_grant)
3657                 1'd0: begin
3658                         t_array_muxed5 <= sdram_bankmachine0_cmd_payload_we;
3659                 end
3660                 1'd1: begin
3661                         t_array_muxed5 <= sdram_bankmachine1_cmd_payload_we;
3662                 end
3663                 2'd2: begin
3664                         t_array_muxed5 <= sdram_bankmachine2_cmd_payload_we;
3665                 end
3666                 default: begin
3667                         t_array_muxed5 <= sdram_bankmachine3_cmd_payload_we;
3668                 end
3669         endcase
3670 end
3671 always @(*) begin
3672         rhs_array_muxed12 <= 22'd0;
3673         case (subfragments_roundrobin0_grant)
3674                 default: begin
3675                         rhs_array_muxed12 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3676                 end
3677         endcase
3678 end
3679 always @(*) begin
3680         rhs_array_muxed13 <= 1'd0;
3681         case (subfragments_roundrobin0_grant)
3682                 default: begin
3683                         rhs_array_muxed13 <= port_cmd_payload_we;
3684                 end
3685         endcase
3686 end
3687 always @(*) begin
3688         rhs_array_muxed14 <= 1'd0;
3689         case (subfragments_roundrobin0_grant)
3690                 default: begin
3691                         rhs_array_muxed14 <= (((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3692                 end
3693         endcase
3694 end
3695 always @(*) begin
3696         rhs_array_muxed15 <= 22'd0;
3697         case (subfragments_roundrobin1_grant)
3698                 default: begin
3699                         rhs_array_muxed15 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3700                 end
3701         endcase
3702 end
3703 always @(*) begin
3704         rhs_array_muxed16 <= 1'd0;
3705         case (subfragments_roundrobin1_grant)
3706                 default: begin
3707                         rhs_array_muxed16 <= port_cmd_payload_we;
3708                 end
3709         endcase
3710 end
3711 always @(*) begin
3712         rhs_array_muxed17 <= 1'd0;
3713         case (subfragments_roundrobin1_grant)
3714                 default: begin
3715                         rhs_array_muxed17 <= (((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3716                 end
3717         endcase
3718 end
3719 always @(*) begin
3720         rhs_array_muxed18 <= 22'd0;
3721         case (subfragments_roundrobin2_grant)
3722                 default: begin
3723                         rhs_array_muxed18 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3724                 end
3725         endcase
3726 end
3727 always @(*) begin
3728         rhs_array_muxed19 <= 1'd0;
3729         case (subfragments_roundrobin2_grant)
3730                 default: begin
3731                         rhs_array_muxed19 <= port_cmd_payload_we;
3732                 end
3733         endcase
3734 end
3735 always @(*) begin
3736         rhs_array_muxed20 <= 1'd0;
3737         case (subfragments_roundrobin2_grant)
3738                 default: begin
3739                         rhs_array_muxed20 <= (((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3740                 end
3741         endcase
3742 end
3743 always @(*) begin
3744         rhs_array_muxed21 <= 22'd0;
3745         case (subfragments_roundrobin3_grant)
3746                 default: begin
3747                         rhs_array_muxed21 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3748                 end
3749         endcase
3750 end
3751 always @(*) begin
3752         rhs_array_muxed22 <= 1'd0;
3753         case (subfragments_roundrobin3_grant)
3754                 default: begin
3755                         rhs_array_muxed22 <= port_cmd_payload_we;
3756                 end
3757         endcase
3758 end
3759 always @(*) begin
3760         rhs_array_muxed23 <= 1'd0;
3761         case (subfragments_roundrobin3_grant)
3762                 default: begin
3763                         rhs_array_muxed23 <= (((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid);
3764                 end
3765         endcase
3766 end
3767 always @(*) begin
3768         rhs_array_muxed24 <= 30'd0;
3769         case (libresocsim_grant)
3770                 1'd0: begin
3771                         rhs_array_muxed24 <= libresocsim_interface0_converted_interface_adr;
3772                 end
3773                 1'd1: begin
3774                         rhs_array_muxed24 <= libresocsim_interface1_converted_interface_adr;
3775                 end
3776                 default: begin
3777                         rhs_array_muxed24 <= libresocsim_libresoc_jtag_wb_adr;
3778                 end
3779         endcase
3780 end
3781 always @(*) begin
3782         rhs_array_muxed25 <= 32'd0;
3783         case (libresocsim_grant)
3784                 1'd0: begin
3785                         rhs_array_muxed25 <= libresocsim_interface0_converted_interface_dat_w;
3786                 end
3787                 1'd1: begin
3788                         rhs_array_muxed25 <= libresocsim_interface1_converted_interface_dat_w;
3789                 end
3790                 default: begin
3791                         rhs_array_muxed25 <= libresocsim_libresoc_jtag_wb_dat_w;
3792                 end
3793         endcase
3794 end
3795 always @(*) begin
3796         rhs_array_muxed26 <= 4'd0;
3797         case (libresocsim_grant)
3798                 1'd0: begin
3799                         rhs_array_muxed26 <= libresocsim_interface0_converted_interface_sel;
3800                 end
3801                 1'd1: begin
3802                         rhs_array_muxed26 <= libresocsim_interface1_converted_interface_sel;
3803                 end
3804                 default: begin
3805                         rhs_array_muxed26 <= libresocsim_libresoc_jtag_wb_sel;
3806                 end
3807         endcase
3808 end
3809 always @(*) begin
3810         rhs_array_muxed27 <= 1'd0;
3811         case (libresocsim_grant)
3812                 1'd0: begin
3813                         rhs_array_muxed27 <= libresocsim_interface0_converted_interface_cyc;
3814                 end
3815                 1'd1: begin
3816                         rhs_array_muxed27 <= libresocsim_interface1_converted_interface_cyc;
3817                 end
3818                 default: begin
3819                         rhs_array_muxed27 <= libresocsim_libresoc_jtag_wb_cyc;
3820                 end
3821         endcase
3822 end
3823 always @(*) begin
3824         rhs_array_muxed28 <= 1'd0;
3825         case (libresocsim_grant)
3826                 1'd0: begin
3827                         rhs_array_muxed28 <= libresocsim_interface0_converted_interface_stb;
3828                 end
3829                 1'd1: begin
3830                         rhs_array_muxed28 <= libresocsim_interface1_converted_interface_stb;
3831                 end
3832                 default: begin
3833                         rhs_array_muxed28 <= libresocsim_libresoc_jtag_wb_stb;
3834                 end
3835         endcase
3836 end
3837 always @(*) begin
3838         rhs_array_muxed29 <= 1'd0;
3839         case (libresocsim_grant)
3840                 1'd0: begin
3841                         rhs_array_muxed29 <= libresocsim_interface0_converted_interface_we;
3842                 end
3843                 1'd1: begin
3844                         rhs_array_muxed29 <= libresocsim_interface1_converted_interface_we;
3845                 end
3846                 default: begin
3847                         rhs_array_muxed29 <= libresocsim_libresoc_jtag_wb_we;
3848                 end
3849         endcase
3850 end
3851 always @(*) begin
3852         rhs_array_muxed30 <= 3'd0;
3853         case (libresocsim_grant)
3854                 1'd0: begin
3855                         rhs_array_muxed30 <= libresocsim_interface0_converted_interface_cti;
3856                 end
3857                 1'd1: begin
3858                         rhs_array_muxed30 <= libresocsim_interface1_converted_interface_cti;
3859                 end
3860                 default: begin
3861                         rhs_array_muxed30 <= libresocsim_libresoc_jtag_wb_cti;
3862                 end
3863         endcase
3864 end
3865 always @(*) begin
3866         rhs_array_muxed31 <= 2'd0;
3867         case (libresocsim_grant)
3868                 1'd0: begin
3869                         rhs_array_muxed31 <= libresocsim_interface0_converted_interface_bte;
3870                 end
3871                 1'd1: begin
3872                         rhs_array_muxed31 <= libresocsim_interface1_converted_interface_bte;
3873                 end
3874                 default: begin
3875                         rhs_array_muxed31 <= libresocsim_libresoc_jtag_wb_bte;
3876                 end
3877         endcase
3878 end
3879 always @(*) begin
3880         array_muxed0 <= 2'd0;
3881         case (sdram_steerer_sel)
3882                 1'd0: begin
3883                         array_muxed0 <= sdram_nop_ba[1:0];
3884                 end
3885                 1'd1: begin
3886                         array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0];
3887                 end
3888                 2'd2: begin
3889                         array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0];
3890                 end
3891                 default: begin
3892                         array_muxed0 <= sdram_cmd_payload_ba[1:0];
3893                 end
3894         endcase
3895 end
3896 always @(*) begin
3897         array_muxed1 <= 13'd0;
3898         case (sdram_steerer_sel)
3899                 1'd0: begin
3900                         array_muxed1 <= sdram_nop_a;
3901                 end
3902                 1'd1: begin
3903                         array_muxed1 <= sdram_choose_req_cmd_payload_a;
3904                 end
3905                 2'd2: begin
3906                         array_muxed1 <= sdram_choose_req_cmd_payload_a;
3907                 end
3908                 default: begin
3909                         array_muxed1 <= sdram_cmd_payload_a;
3910                 end
3911         endcase
3912 end
3913 always @(*) begin
3914         array_muxed2 <= 1'd0;
3915         case (sdram_steerer_sel)
3916                 1'd0: begin
3917                         array_muxed2 <= 1'd0;
3918                 end
3919                 1'd1: begin
3920                         array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas);
3921                 end
3922                 2'd2: begin
3923                         array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas);
3924                 end
3925                 default: begin
3926                         array_muxed2 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas);
3927                 end
3928         endcase
3929 end
3930 always @(*) begin
3931         array_muxed3 <= 1'd0;
3932         case (sdram_steerer_sel)
3933                 1'd0: begin
3934                         array_muxed3 <= 1'd0;
3935                 end
3936                 1'd1: begin
3937                         array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras);
3938                 end
3939                 2'd2: begin
3940                         array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras);
3941                 end
3942                 default: begin
3943                         array_muxed3 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras);
3944                 end
3945         endcase
3946 end
3947 always @(*) begin
3948         array_muxed4 <= 1'd0;
3949         case (sdram_steerer_sel)
3950                 1'd0: begin
3951                         array_muxed4 <= 1'd0;
3952                 end
3953                 1'd1: begin
3954                         array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we);
3955                 end
3956                 2'd2: begin
3957                         array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we);
3958                 end
3959                 default: begin
3960                         array_muxed4 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we);
3961                 end
3962         endcase
3963 end
3964 always @(*) begin
3965         array_muxed5 <= 1'd0;
3966         case (sdram_steerer_sel)
3967                 1'd0: begin
3968                         array_muxed5 <= 1'd0;
3969                 end
3970                 1'd1: begin
3971                         array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read);
3972                 end
3973                 2'd2: begin
3974                         array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read);
3975                 end
3976                 default: begin
3977                         array_muxed5 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read);
3978                 end
3979         endcase
3980 end
3981 always @(*) begin
3982         array_muxed6 <= 1'd0;
3983         case (sdram_steerer_sel)
3984                 1'd0: begin
3985                         array_muxed6 <= 1'd0;
3986                 end
3987                 1'd1: begin
3988                         array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
3989                 end
3990                 2'd2: begin
3991                         array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
3992                 end
3993                 default: begin
3994                         array_muxed6 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write);
3995                 end
3996         endcase
3997 end
3998 assign sdrio_clk = sys_clk_1;
3999 assign sdrio_clk_1 = sys_clk_1;
4000 assign sdrio_clk_2 = sys_clk_1;
4001 assign sdrio_clk_3 = sys_clk_1;
4002 assign sdrio_clk_4 = sys_clk_1;
4003 assign sdrio_clk_5 = sys_clk_1;
4004 assign sdrio_clk_6 = sys_clk_1;
4005 assign sdrio_clk_7 = sys_clk_1;
4006 assign sdrio_clk_8 = sys_clk_1;
4007 assign sdrio_clk_9 = sys_clk_1;
4008 assign sdrio_clk_10 = sys_clk_1;
4009 assign sdrio_clk_11 = sys_clk_1;
4010 assign sdrio_clk_12 = sys_clk_1;
4011 assign sdrio_clk_13 = sys_clk_1;
4012 assign sdrio_clk_14 = sys_clk_1;
4013 assign sdrio_clk_15 = sys_clk_1;
4014 assign sdrio_clk_16 = sys_clk_1;
4015 assign sdrio_clk_17 = sys_clk_1;
4016 assign sdrio_clk_18 = sys_clk_1;
4017 assign sdrio_clk_19 = sys_clk_1;
4018 assign sdrio_clk_20 = sys_clk_1;
4019 assign sdrio_clk_21 = sys_clk_1;
4020 assign sdrio_clk_22 = sys_clk_1;
4021 assign sdrio_clk_23 = sys_clk_1;
4022 assign sdrio_clk_24 = sys_clk_1;
4023 assign sdrio_clk_25 = sys_clk_1;
4024 assign sdrio_clk_26 = sys_clk_1;
4025 assign sdrio_clk_27 = sys_clk_1;
4026 assign sdrio_clk_28 = sys_clk_1;
4027 assign sdrio_clk_29 = sys_clk_1;
4028 assign sdrio_clk_30 = sys_clk_1;
4029 assign sdrio_clk_31 = sys_clk_1;
4030 assign sdrio_clk_32 = sys_clk_1;
4031 assign sdrio_clk_33 = sys_clk_1;
4032 assign sdrio_clk_34 = sys_clk_1;
4033 assign sdrio_clk_35 = sys_clk_1;
4034 assign sdrio_clk_36 = sys_clk_1;
4035 assign sdrio_clk_37 = sys_clk_1;
4036 assign sdrio_clk_38 = sys_clk_1;
4037 assign sdrio_clk_39 = sys_clk_1;
4038 assign sdrio_clk_40 = sys_clk_1;
4039 assign sdrio_clk_41 = sys_clk_1;
4040 assign sdrio_clk_42 = sys_clk_1;
4041 assign sdrio_clk_43 = sys_clk_1;
4042 assign sdrio_clk_44 = sys_clk_1;
4043 assign sdrio_clk_45 = sys_clk_1;
4044 assign sdrio_clk_46 = sys_clk_1;
4045 assign sdrio_clk_47 = sys_clk_1;
4046 assign sdrio_clk_48 = sys_clk_1;
4047 assign sdrio_clk_49 = sys_clk_1;
4048 assign sdrio_clk_50 = sys_clk_1;
4049 assign sdrio_clk_51 = sys_clk_1;
4050 assign sdrio_clk_52 = sys_clk_1;
4051 assign sdrio_clk_53 = sys_clk_1;
4052 assign sdrio_clk_54 = sys_clk_1;
4053 assign sdrio_clk_55 = sys_clk_1;
4054 assign sdrio_clk_56 = sys_clk_1;
4055 assign sdrio_clk_57 = sys_clk_1;
4056 assign sdrio_clk_58 = sys_clk_1;
4057 assign sdrio_clk_59 = sys_clk_1;
4058 assign sdrio_clk_60 = sys_clk_1;
4059 assign sdrio_clk_61 = sys_clk_1;
4060 assign sdrio_clk_62 = sys_clk_1;
4061 assign sdrio_clk_63 = sys_clk_1;
4062 assign sdrio_clk_64 = sys_clk_1;
4063 assign sdrio_clk_65 = sys_clk_1;
4064 assign sdrio_clk_66 = sys_clk_1;
4065 assign sdrio_clk_67 = sys_clk_1;
4066 assign sdrio_clk_68 = sys_clk_1;
4067 assign sdrio_clk_69 = sys_clk_1;
4068 assign sdrio_clk_70 = sys_clk_1;
4069 assign uart_phy_rx = regs1;
4070 assign sdrio_clk_71 = sys_clk_1;
4071 assign sdrio_clk_72 = sys_clk_1;
4072 assign sdrio_clk_73 = sys_clk_1;
4073 assign sdrio_clk_74 = sys_clk_1;
4074 assign sdrio_clk_75 = sys_clk_1;
4075 assign sdrio_clk_76 = sys_clk_1;
4076 assign sdrio_clk_77 = sys_clk_1;
4077 assign sdrio_clk_78 = sys_clk_1;
4078 assign sdrio_clk_79 = sys_clk_1;
4079 assign sdrio_clk_80 = sys_clk_1;
4080 assign sdrio_clk_81 = sys_clk_1;
4081 assign sdrio_clk_82 = sys_clk_1;
4082 assign sdrio_clk_83 = sys_clk_1;
4083 assign sdrio_clk_84 = sys_clk_1;
4084 assign sdrio_clk_85 = sys_clk_1;
4085 assign sdrio_clk_86 = sys_clk_1;
4086 assign sdrio_clk_87 = sys_clk_1;
4087 assign sdrio_clk_88 = sys_clk_1;
4088 assign sdrio_clk_89 = sys_clk_1;
4089 assign sdrio_clk_90 = sys_clk_1;
4090 assign sdrio_clk_91 = sys_clk_1;
4091 assign sdrio_clk_92 = sys_clk_1;
4092 assign sdrio_clk_93 = sys_clk_1;
4093 assign sdrio_clk_94 = sys_clk_1;
4094 assign sdrio_clk_95 = sys_clk_1;
4095 assign sdrio_clk_96 = sys_clk_1;
4096 assign sdrio_clk_97 = sys_clk_1;
4097 assign sdrio_clk_98 = sys_clk_1;
4098 assign sdrio_clk_99 = sys_clk_1;
4099 assign sdrio_clk_100 = sys_clk_1;
4100 assign sdrio_clk_101 = sys_clk_1;
4101 assign sdrio_clk_102 = sys_clk_1;
4102 assign sdrio_clk_103 = sys_clk_1;
4103 assign sdrio_clk_104 = sys_clk_1;
4104 assign sdrio_clk_105 = sys_clk_1;
4105 assign sdrio_clk_106 = sys_clk_1;
4106 assign sdrio_clk_107 = sys_clk_1;
4107 assign sdrio_clk_108 = sys_clk_1;
4108 assign sdrio_clk_109 = sys_clk_1;
4109 assign sdrio_clk_110 = sys_clk_1;
4110 assign sdrio_clk_111 = sys_clk_1;
4111 assign sdrio_clk_112 = sys_clk_1;
4112 assign sdrio_clk_113 = sys_clk_1;
4113 assign sdrio_clk_114 = sys_clk_1;
4114 assign sdrio_clk_115 = sys_clk_1;
4115 assign sdrio_clk_116 = sys_clk_1;
4116 assign sdrio_clk_117 = sys_clk_1;
4117 assign sdrio_clk_118 = sys_clk_1;
4118
4119 always @(posedge por_clk) begin
4120         int_rst <= sys_rst;
4121 end
4122
4123 always @(posedge sdrio_clk) begin
4124         libresocsim_libresoc_constraintmanager_sdram_a[0] <= dfi_p0_address[0];
4125         libresocsim_libresoc_constraintmanager_sdram_a[1] <= dfi_p0_address[1];
4126         libresocsim_libresoc_constraintmanager_sdram_a[2] <= dfi_p0_address[2];
4127         libresocsim_libresoc_constraintmanager_sdram_a[3] <= dfi_p0_address[3];
4128         libresocsim_libresoc_constraintmanager_sdram_a[4] <= dfi_p0_address[4];
4129         libresocsim_libresoc_constraintmanager_sdram_a[5] <= dfi_p0_address[5];
4130         libresocsim_libresoc_constraintmanager_sdram_a[6] <= dfi_p0_address[6];
4131         libresocsim_libresoc_constraintmanager_sdram_a[7] <= dfi_p0_address[7];
4132         libresocsim_libresoc_constraintmanager_sdram_a[8] <= dfi_p0_address[8];
4133         libresocsim_libresoc_constraintmanager_sdram_a[9] <= dfi_p0_address[9];
4134         libresocsim_libresoc_constraintmanager_sdram_a[10] <= dfi_p0_address[10];
4135         libresocsim_libresoc_constraintmanager_sdram_a[11] <= dfi_p0_address[11];
4136         libresocsim_libresoc_constraintmanager_sdram_a[12] <= dfi_p0_address[12];
4137         libresocsim_libresoc_constraintmanager_sdram_ba[0] <= dfi_p0_bank[0];
4138         libresocsim_libresoc_constraintmanager_sdram_ba[1] <= dfi_p0_bank[1];
4139         libresocsim_libresoc_constraintmanager_sdram_cas_n <= dfi_p0_cas_n;
4140         libresocsim_libresoc_constraintmanager_sdram_ras_n <= dfi_p0_ras_n;
4141         libresocsim_libresoc_constraintmanager_sdram_we_n <= dfi_p0_we_n;
4142         libresocsim_libresoc_constraintmanager_sdram_cke <= dfi_p0_cke;
4143         libresocsim_libresoc_constraintmanager_sdram_cs_n <= dfi_p0_cs_n;
4144         libresocsim_libresoc_constraintmanager_sdram_dq_oe[0] <= dfi_p0_wrdata_en;
4145         libresocsim_libresoc_constraintmanager_sdram_dq_o[0] <= dfi_p0_wrdata[0];
4146         dfi_p0_rddata[0] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[0];
4147         libresocsim_libresoc_constraintmanager_sdram_dq_oe[1] <= dfi_p0_wrdata_en;
4148         libresocsim_libresoc_constraintmanager_sdram_dq_o[1] <= dfi_p0_wrdata[1];
4149         dfi_p0_rddata[1] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[1];
4150         libresocsim_libresoc_constraintmanager_sdram_dq_oe[2] <= dfi_p0_wrdata_en;
4151         libresocsim_libresoc_constraintmanager_sdram_dq_o[2] <= dfi_p0_wrdata[2];
4152         dfi_p0_rddata[2] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[2];
4153         libresocsim_libresoc_constraintmanager_sdram_dq_oe[3] <= dfi_p0_wrdata_en;
4154         libresocsim_libresoc_constraintmanager_sdram_dq_o[3] <= dfi_p0_wrdata[3];
4155         dfi_p0_rddata[3] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[3];
4156         libresocsim_libresoc_constraintmanager_sdram_dq_oe[4] <= dfi_p0_wrdata_en;
4157         libresocsim_libresoc_constraintmanager_sdram_dq_o[4] <= dfi_p0_wrdata[4];
4158         dfi_p0_rddata[4] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[4];
4159         libresocsim_libresoc_constraintmanager_sdram_dq_oe[5] <= dfi_p0_wrdata_en;
4160         libresocsim_libresoc_constraintmanager_sdram_dq_o[5] <= dfi_p0_wrdata[5];
4161         dfi_p0_rddata[5] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[5];
4162         libresocsim_libresoc_constraintmanager_sdram_dq_oe[6] <= dfi_p0_wrdata_en;
4163         libresocsim_libresoc_constraintmanager_sdram_dq_o[6] <= dfi_p0_wrdata[6];
4164         dfi_p0_rddata[6] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[6];
4165         libresocsim_libresoc_constraintmanager_sdram_dq_oe[7] <= dfi_p0_wrdata_en;
4166         libresocsim_libresoc_constraintmanager_sdram_dq_o[7] <= dfi_p0_wrdata[7];
4167         dfi_p0_rddata[7] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[7];
4168         libresocsim_libresoc_constraintmanager_sdram_dq_oe[8] <= dfi_p0_wrdata_en;
4169         libresocsim_libresoc_constraintmanager_sdram_dq_o[8] <= dfi_p0_wrdata[8];
4170         dfi_p0_rddata[8] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[8];
4171         libresocsim_libresoc_constraintmanager_sdram_dq_oe[9] <= dfi_p0_wrdata_en;
4172         libresocsim_libresoc_constraintmanager_sdram_dq_o[9] <= dfi_p0_wrdata[9];
4173         dfi_p0_rddata[9] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[9];
4174         libresocsim_libresoc_constraintmanager_sdram_dq_oe[10] <= dfi_p0_wrdata_en;
4175         libresocsim_libresoc_constraintmanager_sdram_dq_o[10] <= dfi_p0_wrdata[10];
4176         dfi_p0_rddata[10] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[10];
4177         libresocsim_libresoc_constraintmanager_sdram_dq_oe[11] <= dfi_p0_wrdata_en;
4178         libresocsim_libresoc_constraintmanager_sdram_dq_o[11] <= dfi_p0_wrdata[11];
4179         dfi_p0_rddata[11] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[11];
4180         libresocsim_libresoc_constraintmanager_sdram_dq_oe[12] <= dfi_p0_wrdata_en;
4181         libresocsim_libresoc_constraintmanager_sdram_dq_o[12] <= dfi_p0_wrdata[12];
4182         dfi_p0_rddata[12] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[12];
4183         libresocsim_libresoc_constraintmanager_sdram_dq_oe[13] <= dfi_p0_wrdata_en;
4184         libresocsim_libresoc_constraintmanager_sdram_dq_o[13] <= dfi_p0_wrdata[13];
4185         dfi_p0_rddata[13] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[13];
4186         libresocsim_libresoc_constraintmanager_sdram_dq_oe[14] <= dfi_p0_wrdata_en;
4187         libresocsim_libresoc_constraintmanager_sdram_dq_o[14] <= dfi_p0_wrdata[14];
4188         dfi_p0_rddata[14] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[14];
4189         libresocsim_libresoc_constraintmanager_sdram_dq_oe[15] <= dfi_p0_wrdata_en;
4190         libresocsim_libresoc_constraintmanager_sdram_dq_o[15] <= dfi_p0_wrdata[15];
4191         dfi_p0_rddata[15] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[15];
4192         libresocsim_libresoc_constraintmanager_sdram_dm[0] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[0]);
4193         libresocsim_libresoc_constraintmanager_sdram_dm[1] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[1]);
4194         libresocsim_libresoc_constraintmanager_sdram_clock <= sys_clk_1;
4195         gpio0_pads_gpio0oe[0] <= gpio0_oe_storage[0];
4196         gpio0_pads_gpio0o[0] <= gpio0_out_storage[0];
4197         gpio0_status[0] <= gpio0_pads_gpio0i[0];
4198         gpio0_pads_gpio0oe[1] <= gpio0_oe_storage[1];
4199         gpio0_pads_gpio0o[1] <= gpio0_out_storage[1];
4200         gpio0_status[1] <= gpio0_pads_gpio0i[1];
4201         gpio0_pads_gpio0oe[2] <= gpio0_oe_storage[2];
4202         gpio0_pads_gpio0o[2] <= gpio0_out_storage[2];
4203         gpio0_status[2] <= gpio0_pads_gpio0i[2];
4204         gpio0_pads_gpio0oe[3] <= gpio0_oe_storage[3];
4205         gpio0_pads_gpio0o[3] <= gpio0_out_storage[3];
4206         gpio0_status[3] <= gpio0_pads_gpio0i[3];
4207         gpio0_pads_gpio0oe[4] <= gpio0_oe_storage[4];
4208         gpio0_pads_gpio0o[4] <= gpio0_out_storage[4];
4209         gpio0_status[4] <= gpio0_pads_gpio0i[4];
4210         gpio0_pads_gpio0oe[5] <= gpio0_oe_storage[5];
4211         gpio0_pads_gpio0o[5] <= gpio0_out_storage[5];
4212         gpio0_status[5] <= gpio0_pads_gpio0i[5];
4213         gpio0_pads_gpio0oe[6] <= gpio0_oe_storage[6];
4214         gpio0_pads_gpio0o[6] <= gpio0_out_storage[6];
4215         gpio0_status[6] <= gpio0_pads_gpio0i[6];
4216         gpio0_pads_gpio0oe[7] <= gpio0_oe_storage[7];
4217         gpio0_pads_gpio0o[7] <= gpio0_out_storage[7];
4218         gpio0_status[7] <= gpio0_pads_gpio0i[7];
4219         gpio1_pads_gpio1oe[0] <= gpio1_oe_storage[0];
4220         gpio1_pads_gpio1o[0] <= gpio1_out_storage[0];
4221         gpio1_status[0] <= gpio1_pads_gpio1i[0];
4222         gpio1_pads_gpio1oe[1] <= gpio1_oe_storage[1];
4223         gpio1_pads_gpio1o[1] <= gpio1_out_storage[1];
4224         gpio1_status[1] <= gpio1_pads_gpio1i[1];
4225         gpio1_pads_gpio1oe[2] <= gpio1_oe_storage[2];
4226         gpio1_pads_gpio1o[2] <= gpio1_out_storage[2];
4227         gpio1_status[2] <= gpio1_pads_gpio1i[2];
4228         gpio1_pads_gpio1oe[3] <= gpio1_oe_storage[3];
4229         gpio1_pads_gpio1o[3] <= gpio1_out_storage[3];
4230         gpio1_status[3] <= gpio1_pads_gpio1i[3];
4231         gpio1_pads_gpio1oe[4] <= gpio1_oe_storage[4];
4232         gpio1_pads_gpio1o[4] <= gpio1_out_storage[4];
4233         gpio1_status[4] <= gpio1_pads_gpio1i[4];
4234         gpio1_pads_gpio1oe[5] <= gpio1_oe_storage[5];
4235         gpio1_pads_gpio1o[5] <= gpio1_out_storage[5];
4236         gpio1_status[5] <= gpio1_pads_gpio1i[5];
4237         gpio1_pads_gpio1oe[6] <= gpio1_oe_storage[6];
4238         gpio1_pads_gpio1o[6] <= gpio1_out_storage[6];
4239         gpio1_status[6] <= gpio1_pads_gpio1i[6];
4240         gpio1_pads_gpio1oe[7] <= gpio1_oe_storage[7];
4241         gpio1_pads_gpio1o[7] <= gpio1_out_storage[7];
4242         gpio1_status[7] <= gpio1_pads_gpio1i[7];
4243 end
4244
4245 always @(posedge sys_clk_1) begin
4246         dummy[0] <= (nc_1[0] | libresocsim_libresoc_interrupt[0]);
4247         dummy[1] <= (nc_1[1] | libresocsim_libresoc_interrupt[0]);
4248         dummy[2] <= (nc_1[2] | libresocsim_libresoc_interrupt[0]);
4249         dummy[3] <= (nc_1[3] | libresocsim_libresoc_interrupt[0]);
4250         dummy[4] <= (nc_1[4] | libresocsim_libresoc_interrupt[0]);
4251         dummy[5] <= (nc_1[5] | libresocsim_libresoc_interrupt[0]);
4252         dummy[6] <= (nc_1[6] | libresocsim_libresoc_interrupt[0]);
4253         dummy[7] <= (nc_1[7] | libresocsim_libresoc_interrupt[0]);
4254         dummy[8] <= (nc_1[8] | libresocsim_libresoc_interrupt[0]);
4255         dummy[9] <= (nc_1[9] | libresocsim_libresoc_interrupt[0]);
4256         dummy[10] <= (nc_1[10] | libresocsim_libresoc_interrupt[0]);
4257         dummy[11] <= (nc_1[11] | libresocsim_libresoc_interrupt[0]);
4258         dummy[12] <= (nc_1[12] | libresocsim_libresoc_interrupt[0]);
4259         dummy[13] <= (nc_1[13] | libresocsim_libresoc_interrupt[0]);
4260         dummy[14] <= (nc_1[14] | libresocsim_libresoc_interrupt[0]);
4261         dummy[15] <= (nc_1[15] | libresocsim_libresoc_interrupt[0]);
4262         dummy[16] <= (nc_1[16] | libresocsim_libresoc_interrupt[0]);
4263         dummy[17] <= (nc_1[17] | libresocsim_libresoc_interrupt[0]);
4264         dummy[18] <= (nc_1[18] | libresocsim_libresoc_interrupt[0]);
4265         dummy[19] <= (nc_1[19] | libresocsim_libresoc_interrupt[0]);
4266         dummy[20] <= (nc_1[20] | libresocsim_libresoc_interrupt[0]);
4267         dummy[21] <= (nc_1[21] | libresocsim_libresoc_interrupt[0]);
4268         dummy[22] <= (nc_1[22] | libresocsim_libresoc_interrupt[0]);
4269         dummy[23] <= (nc_1[23] | libresocsim_libresoc_interrupt[0]);
4270         dummy[24] <= (nc_1[24] | libresocsim_libresoc_interrupt[0]);
4271         dummy[25] <= (nc_1[25] | libresocsim_libresoc_interrupt[0]);
4272         dummy[26] <= (nc_1[26] | libresocsim_libresoc_interrupt[0]);
4273         dummy[27] <= (nc_1[27] | libresocsim_libresoc_interrupt[0]);
4274         dummy[28] <= (nc_1[28] | libresocsim_libresoc_interrupt[0]);
4275         dummy[29] <= (nc_1[29] | libresocsim_libresoc_interrupt[0]);
4276         dummy[30] <= (nc_1[30] | libresocsim_libresoc_interrupt[0]);
4277         dummy[31] <= (nc_1[31] | libresocsim_libresoc_interrupt[0]);
4278         dummy[32] <= (nc_1[32] | libresocsim_libresoc_interrupt[0]);
4279         dummy[33] <= (nc_1[33] | libresocsim_libresoc_interrupt[0]);
4280         dummy[34] <= (nc_1[34] | libresocsim_libresoc_interrupt[0]);
4281         dummy[35] <= (nc_1[35] | libresocsim_libresoc_interrupt[0]);
4282         dummy[36] <= (nc_1[36] | libresocsim_libresoc_interrupt[0]);
4283         dummy[37] <= (nc_1[37] | libresocsim_libresoc_interrupt[0]);
4284         dummy[38] <= (nc_1[38] | libresocsim_libresoc_interrupt[0]);
4285         dummy[39] <= (nc_1[39] | libresocsim_libresoc_interrupt[0]);
4286         if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin
4287                 libresocsim_converter0_dat_r <= libresocsim_libresoc_ibus_dat_r;
4288         end
4289         subfragments_converter0_state <= subfragments_converter0_next_state;
4290         if (libresocsim_converter0_counter_subfragments_converter0_next_value_ce) begin
4291                 libresocsim_converter0_counter <= libresocsim_converter0_counter_subfragments_converter0_next_value;
4292         end
4293         if (libresocsim_converter0_reset) begin
4294                 libresocsim_converter0_counter <= 1'd0;
4295                 subfragments_converter0_state <= 1'd0;
4296         end
4297         if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin
4298                 libresocsim_converter1_dat_r <= libresocsim_libresoc_dbus_dat_r;
4299         end
4300         subfragments_converter1_state <= subfragments_converter1_next_state;
4301         if (libresocsim_converter1_counter_subfragments_converter1_next_value_ce) begin
4302                 libresocsim_converter1_counter <= libresocsim_converter1_counter_subfragments_converter1_next_value;
4303         end
4304         if (libresocsim_converter1_reset) begin
4305                 libresocsim_converter1_counter <= 1'd0;
4306                 subfragments_converter1_state <= 1'd0;
4307         end
4308         if ((libresocsim_bus_errors != 32'd4294967295)) begin
4309                 if (libresocsim_bus_error) begin
4310                         libresocsim_bus_errors <= (libresocsim_bus_errors + 1'd1);
4311                 end
4312         end
4313         libresocsim_ram_bus_ack <= 1'd0;
4314         if (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & (~libresocsim_ram_bus_ack))) begin
4315                 libresocsim_ram_bus_ack <= 1'd1;
4316         end
4317         if (libresocsim_en_storage) begin
4318                 if ((libresocsim_value == 1'd0)) begin
4319                         libresocsim_value <= libresocsim_reload_storage;
4320                 end else begin
4321                         libresocsim_value <= (libresocsim_value - 1'd1);
4322                 end
4323         end else begin
4324                 libresocsim_value <= libresocsim_load_storage;
4325         end
4326         if (libresocsim_update_value_re) begin
4327                 libresocsim_value_status <= libresocsim_value;
4328         end
4329         if (libresocsim_zero_clear) begin
4330                 libresocsim_zero_pending <= 1'd0;
4331         end
4332         libresocsim_zero_old_trigger <= libresocsim_zero_trigger;
4333         if (((~libresocsim_zero_trigger) & libresocsim_zero_old_trigger)) begin
4334                 libresocsim_zero_pending <= 1'd1;
4335         end
4336         ram_bus_ram_bus_ack <= 1'd0;
4337         if (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & (~ram_bus_ram_bus_ack))) begin
4338                 ram_bus_ram_bus_ack <= 1'd1;
4339         end
4340         rddata_en <= {rddata_en, dfi_p0_rddata_en};
4341         dfi_p0_rddata_valid <= rddata_en[2];
4342         if (sdram_inti_p0_rddata_valid) begin
4343                 sdram_status <= sdram_inti_p0_rddata;
4344         end
4345         if ((sdram_timer_wait & (~sdram_timer_done0))) begin
4346                 sdram_timer_count1 <= (sdram_timer_count1 - 1'd1);
4347         end else begin
4348                 sdram_timer_count1 <= 10'd781;
4349         end
4350         sdram_postponer_req_o <= 1'd0;
4351         if (sdram_postponer_req_i) begin
4352                 sdram_postponer_count <= (sdram_postponer_count - 1'd1);
4353                 if ((sdram_postponer_count == 1'd0)) begin
4354                         sdram_postponer_count <= 1'd0;
4355                         sdram_postponer_req_o <= 1'd1;
4356                 end
4357         end
4358         if (sdram_sequencer_start0) begin
4359                 sdram_sequencer_count <= 1'd0;
4360         end else begin
4361                 if (sdram_sequencer_done1) begin
4362                         if ((sdram_sequencer_count != 1'd0)) begin
4363                                 sdram_sequencer_count <= (sdram_sequencer_count - 1'd1);
4364                         end
4365                 end
4366         end
4367         sdram_cmd_payload_a <= 1'd0;
4368         sdram_cmd_payload_ba <= 1'd0;
4369         sdram_cmd_payload_cas <= 1'd0;
4370         sdram_cmd_payload_ras <= 1'd0;
4371         sdram_cmd_payload_we <= 1'd0;
4372         sdram_sequencer_done1 <= 1'd0;
4373         if ((sdram_sequencer_start1 & (sdram_sequencer_counter == 1'd0))) begin
4374                 sdram_cmd_payload_a <= 11'd1024;
4375                 sdram_cmd_payload_ba <= 1'd0;
4376                 sdram_cmd_payload_cas <= 1'd0;
4377                 sdram_cmd_payload_ras <= 1'd1;
4378                 sdram_cmd_payload_we <= 1'd1;
4379         end
4380         if ((sdram_sequencer_counter == 2'd2)) begin
4381                 sdram_cmd_payload_a <= 1'd0;
4382                 sdram_cmd_payload_ba <= 1'd0;
4383                 sdram_cmd_payload_cas <= 1'd1;
4384                 sdram_cmd_payload_ras <= 1'd1;
4385                 sdram_cmd_payload_we <= 1'd0;
4386         end
4387         if ((sdram_sequencer_counter == 4'd8)) begin
4388                 sdram_cmd_payload_a <= 1'd0;
4389                 sdram_cmd_payload_ba <= 1'd0;
4390                 sdram_cmd_payload_cas <= 1'd0;
4391                 sdram_cmd_payload_ras <= 1'd0;
4392                 sdram_cmd_payload_we <= 1'd0;
4393                 sdram_sequencer_done1 <= 1'd1;
4394         end
4395         if ((sdram_sequencer_counter == 4'd8)) begin
4396                 sdram_sequencer_counter <= 1'd0;
4397         end else begin
4398                 if ((sdram_sequencer_counter != 1'd0)) begin
4399                         sdram_sequencer_counter <= (sdram_sequencer_counter + 1'd1);
4400                 end else begin
4401                         if (sdram_sequencer_start1) begin
4402                                 sdram_sequencer_counter <= 1'd1;
4403                         end
4404                 end
4405         end
4406         subfragments_refresher_state <= subfragments_refresher_next_state;
4407         if (sdram_bankmachine0_row_close) begin
4408                 sdram_bankmachine0_row_opened <= 1'd0;
4409         end else begin
4410                 if (sdram_bankmachine0_row_open) begin
4411                         sdram_bankmachine0_row_opened <= 1'd1;
4412                         sdram_bankmachine0_row <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
4413                 end
4414         end
4415         if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4416                 sdram_bankmachine0_cmd_buffer_lookahead_produce <= (sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
4417         end
4418         if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4419                 sdram_bankmachine0_cmd_buffer_lookahead_consume <= (sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
4420         end
4421         if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4422                 if ((~sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
4423                         sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
4424                 end
4425         end else begin
4426                 if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4427                         sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
4428                 end
4429         end
4430         if (((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready)) begin
4431                 sdram_bankmachine0_cmd_buffer_source_valid <= sdram_bankmachine0_cmd_buffer_sink_valid;
4432                 sdram_bankmachine0_cmd_buffer_source_first <= sdram_bankmachine0_cmd_buffer_sink_first;
4433                 sdram_bankmachine0_cmd_buffer_source_last <= sdram_bankmachine0_cmd_buffer_sink_last;
4434                 sdram_bankmachine0_cmd_buffer_source_payload_we <= sdram_bankmachine0_cmd_buffer_sink_payload_we;
4435                 sdram_bankmachine0_cmd_buffer_source_payload_addr <= sdram_bankmachine0_cmd_buffer_sink_payload_addr;
4436         end
4437         if (sdram_bankmachine0_twtpcon_valid) begin
4438                 sdram_bankmachine0_twtpcon_count <= 3'd4;
4439                 if (1'd0) begin
4440                         sdram_bankmachine0_twtpcon_ready <= 1'd1;
4441                 end else begin
4442                         sdram_bankmachine0_twtpcon_ready <= 1'd0;
4443                 end
4444         end else begin
4445                 if ((~sdram_bankmachine0_twtpcon_ready)) begin
4446                         sdram_bankmachine0_twtpcon_count <= (sdram_bankmachine0_twtpcon_count - 1'd1);
4447                         if ((sdram_bankmachine0_twtpcon_count == 1'd1)) begin
4448                                 sdram_bankmachine0_twtpcon_ready <= 1'd1;
4449                         end
4450                 end
4451         end
4452         subfragments_bankmachine0_state <= subfragments_bankmachine0_next_state;
4453         if (sdram_bankmachine1_row_close) begin
4454                 sdram_bankmachine1_row_opened <= 1'd0;
4455         end else begin
4456                 if (sdram_bankmachine1_row_open) begin
4457                         sdram_bankmachine1_row_opened <= 1'd1;
4458                         sdram_bankmachine1_row <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
4459                 end
4460         end
4461         if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4462                 sdram_bankmachine1_cmd_buffer_lookahead_produce <= (sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
4463         end
4464         if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4465                 sdram_bankmachine1_cmd_buffer_lookahead_consume <= (sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
4466         end
4467         if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4468                 if ((~sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
4469                         sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
4470                 end
4471         end else begin
4472                 if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4473                         sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
4474                 end
4475         end
4476         if (((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready)) begin
4477                 sdram_bankmachine1_cmd_buffer_source_valid <= sdram_bankmachine1_cmd_buffer_sink_valid;
4478                 sdram_bankmachine1_cmd_buffer_source_first <= sdram_bankmachine1_cmd_buffer_sink_first;
4479                 sdram_bankmachine1_cmd_buffer_source_last <= sdram_bankmachine1_cmd_buffer_sink_last;
4480                 sdram_bankmachine1_cmd_buffer_source_payload_we <= sdram_bankmachine1_cmd_buffer_sink_payload_we;
4481                 sdram_bankmachine1_cmd_buffer_source_payload_addr <= sdram_bankmachine1_cmd_buffer_sink_payload_addr;
4482         end
4483         if (sdram_bankmachine1_twtpcon_valid) begin
4484                 sdram_bankmachine1_twtpcon_count <= 3'd4;
4485                 if (1'd0) begin
4486                         sdram_bankmachine1_twtpcon_ready <= 1'd1;
4487                 end else begin
4488                         sdram_bankmachine1_twtpcon_ready <= 1'd0;
4489                 end
4490         end else begin
4491                 if ((~sdram_bankmachine1_twtpcon_ready)) begin
4492                         sdram_bankmachine1_twtpcon_count <= (sdram_bankmachine1_twtpcon_count - 1'd1);
4493                         if ((sdram_bankmachine1_twtpcon_count == 1'd1)) begin
4494                                 sdram_bankmachine1_twtpcon_ready <= 1'd1;
4495                         end
4496                 end
4497         end
4498         subfragments_bankmachine1_state <= subfragments_bankmachine1_next_state;
4499         if (sdram_bankmachine2_row_close) begin
4500                 sdram_bankmachine2_row_opened <= 1'd0;
4501         end else begin
4502                 if (sdram_bankmachine2_row_open) begin
4503                         sdram_bankmachine2_row_opened <= 1'd1;
4504                         sdram_bankmachine2_row <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
4505                 end
4506         end
4507         if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4508                 sdram_bankmachine2_cmd_buffer_lookahead_produce <= (sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
4509         end
4510         if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4511                 sdram_bankmachine2_cmd_buffer_lookahead_consume <= (sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
4512         end
4513         if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4514                 if ((~sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
4515                         sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
4516                 end
4517         end else begin
4518                 if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4519                         sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
4520                 end
4521         end
4522         if (((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready)) begin
4523                 sdram_bankmachine2_cmd_buffer_source_valid <= sdram_bankmachine2_cmd_buffer_sink_valid;
4524                 sdram_bankmachine2_cmd_buffer_source_first <= sdram_bankmachine2_cmd_buffer_sink_first;
4525                 sdram_bankmachine2_cmd_buffer_source_last <= sdram_bankmachine2_cmd_buffer_sink_last;
4526                 sdram_bankmachine2_cmd_buffer_source_payload_we <= sdram_bankmachine2_cmd_buffer_sink_payload_we;
4527                 sdram_bankmachine2_cmd_buffer_source_payload_addr <= sdram_bankmachine2_cmd_buffer_sink_payload_addr;
4528         end
4529         if (sdram_bankmachine2_twtpcon_valid) begin
4530                 sdram_bankmachine2_twtpcon_count <= 3'd4;
4531                 if (1'd0) begin
4532                         sdram_bankmachine2_twtpcon_ready <= 1'd1;
4533                 end else begin
4534                         sdram_bankmachine2_twtpcon_ready <= 1'd0;
4535                 end
4536         end else begin
4537                 if ((~sdram_bankmachine2_twtpcon_ready)) begin
4538                         sdram_bankmachine2_twtpcon_count <= (sdram_bankmachine2_twtpcon_count - 1'd1);
4539                         if ((sdram_bankmachine2_twtpcon_count == 1'd1)) begin
4540                                 sdram_bankmachine2_twtpcon_ready <= 1'd1;
4541                         end
4542                 end
4543         end
4544         subfragments_bankmachine2_state <= subfragments_bankmachine2_next_state;
4545         if (sdram_bankmachine3_row_close) begin
4546                 sdram_bankmachine3_row_opened <= 1'd0;
4547         end else begin
4548                 if (sdram_bankmachine3_row_open) begin
4549                         sdram_bankmachine3_row_opened <= 1'd1;
4550                         sdram_bankmachine3_row <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
4551                 end
4552         end
4553         if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4554                 sdram_bankmachine3_cmd_buffer_lookahead_produce <= (sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
4555         end
4556         if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4557                 sdram_bankmachine3_cmd_buffer_lookahead_consume <= (sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
4558         end
4559         if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4560                 if ((~sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
4561                         sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
4562                 end
4563         end else begin
4564                 if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4565                         sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
4566                 end
4567         end
4568         if (((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready)) begin
4569                 sdram_bankmachine3_cmd_buffer_source_valid <= sdram_bankmachine3_cmd_buffer_sink_valid;
4570                 sdram_bankmachine3_cmd_buffer_source_first <= sdram_bankmachine3_cmd_buffer_sink_first;
4571                 sdram_bankmachine3_cmd_buffer_source_last <= sdram_bankmachine3_cmd_buffer_sink_last;
4572                 sdram_bankmachine3_cmd_buffer_source_payload_we <= sdram_bankmachine3_cmd_buffer_sink_payload_we;
4573                 sdram_bankmachine3_cmd_buffer_source_payload_addr <= sdram_bankmachine3_cmd_buffer_sink_payload_addr;
4574         end
4575         if (sdram_bankmachine3_twtpcon_valid) begin
4576                 sdram_bankmachine3_twtpcon_count <= 3'd4;
4577                 if (1'd0) begin
4578                         sdram_bankmachine3_twtpcon_ready <= 1'd1;
4579                 end else begin
4580                         sdram_bankmachine3_twtpcon_ready <= 1'd0;
4581                 end
4582         end else begin
4583                 if ((~sdram_bankmachine3_twtpcon_ready)) begin
4584                         sdram_bankmachine3_twtpcon_count <= (sdram_bankmachine3_twtpcon_count - 1'd1);
4585                         if ((sdram_bankmachine3_twtpcon_count == 1'd1)) begin
4586                                 sdram_bankmachine3_twtpcon_ready <= 1'd1;
4587                         end
4588                 end
4589         end
4590         subfragments_bankmachine3_state <= subfragments_bankmachine3_next_state;
4591         if ((~sdram_en0)) begin
4592                 sdram_time0 <= 5'd31;
4593         end else begin
4594                 if ((~sdram_max_time0)) begin
4595                         sdram_time0 <= (sdram_time0 - 1'd1);
4596                 end
4597         end
4598         if ((~sdram_en1)) begin
4599                 sdram_time1 <= 4'd15;
4600         end else begin
4601                 if ((~sdram_max_time1)) begin
4602                         sdram_time1 <= (sdram_time1 - 1'd1);
4603                 end
4604         end
4605         if (sdram_choose_cmd_ce) begin
4606                 case (sdram_choose_cmd_grant)
4607                         1'd0: begin
4608                                 if (sdram_choose_cmd_request[1]) begin
4609                                         sdram_choose_cmd_grant <= 1'd1;
4610                                 end else begin
4611                                         if (sdram_choose_cmd_request[2]) begin
4612                                                 sdram_choose_cmd_grant <= 2'd2;
4613                                         end else begin
4614                                                 if (sdram_choose_cmd_request[3]) begin
4615                                                         sdram_choose_cmd_grant <= 2'd3;
4616                                                 end
4617                                         end
4618                                 end
4619                         end
4620                         1'd1: begin
4621                                 if (sdram_choose_cmd_request[2]) begin
4622                                         sdram_choose_cmd_grant <= 2'd2;
4623                                 end else begin
4624                                         if (sdram_choose_cmd_request[3]) begin
4625                                                 sdram_choose_cmd_grant <= 2'd3;
4626                                         end else begin
4627                                                 if (sdram_choose_cmd_request[0]) begin
4628                                                         sdram_choose_cmd_grant <= 1'd0;
4629                                                 end
4630                                         end
4631                                 end
4632                         end
4633                         2'd2: begin
4634                                 if (sdram_choose_cmd_request[3]) begin
4635                                         sdram_choose_cmd_grant <= 2'd3;
4636                                 end else begin
4637                                         if (sdram_choose_cmd_request[0]) begin
4638                                                 sdram_choose_cmd_grant <= 1'd0;
4639                                         end else begin
4640                                                 if (sdram_choose_cmd_request[1]) begin
4641                                                         sdram_choose_cmd_grant <= 1'd1;
4642                                                 end
4643                                         end
4644                                 end
4645                         end
4646                         2'd3: begin
4647                                 if (sdram_choose_cmd_request[0]) begin
4648                                         sdram_choose_cmd_grant <= 1'd0;
4649                                 end else begin
4650                                         if (sdram_choose_cmd_request[1]) begin
4651                                                 sdram_choose_cmd_grant <= 1'd1;
4652                                         end else begin
4653                                                 if (sdram_choose_cmd_request[2]) begin
4654                                                         sdram_choose_cmd_grant <= 2'd2;
4655                                                 end
4656                                         end
4657                                 end
4658                         end
4659                 endcase
4660         end
4661         if (sdram_choose_req_ce) begin
4662                 case (sdram_choose_req_grant)
4663                         1'd0: begin
4664                                 if (sdram_choose_req_request[1]) begin
4665                                         sdram_choose_req_grant <= 1'd1;
4666                                 end else begin
4667                                         if (sdram_choose_req_request[2]) begin
4668                                                 sdram_choose_req_grant <= 2'd2;
4669                                         end else begin
4670                                                 if (sdram_choose_req_request[3]) begin
4671                                                         sdram_choose_req_grant <= 2'd3;
4672                                                 end
4673                                         end
4674                                 end
4675                         end
4676                         1'd1: begin
4677                                 if (sdram_choose_req_request[2]) begin
4678                                         sdram_choose_req_grant <= 2'd2;
4679                                 end else begin
4680                                         if (sdram_choose_req_request[3]) begin
4681                                                 sdram_choose_req_grant <= 2'd3;
4682                                         end else begin
4683                                                 if (sdram_choose_req_request[0]) begin
4684                                                         sdram_choose_req_grant <= 1'd0;
4685                                                 end
4686                                         end
4687                                 end
4688                         end
4689                         2'd2: begin
4690                                 if (sdram_choose_req_request[3]) begin
4691                                         sdram_choose_req_grant <= 2'd3;
4692                                 end else begin
4693                                         if (sdram_choose_req_request[0]) begin
4694                                                 sdram_choose_req_grant <= 1'd0;
4695                                         end else begin
4696                                                 if (sdram_choose_req_request[1]) begin
4697                                                         sdram_choose_req_grant <= 1'd1;
4698                                                 end
4699                                         end
4700                                 end
4701                         end
4702                         2'd3: begin
4703                                 if (sdram_choose_req_request[0]) begin
4704                                         sdram_choose_req_grant <= 1'd0;
4705                                 end else begin
4706                                         if (sdram_choose_req_request[1]) begin
4707                                                 sdram_choose_req_grant <= 1'd1;
4708                                         end else begin
4709                                                 if (sdram_choose_req_request[2]) begin
4710                                                         sdram_choose_req_grant <= 2'd2;
4711                                                 end
4712                                         end
4713                                 end
4714                         end
4715                 endcase
4716         end
4717         sdram_dfi_p0_cs_n <= 1'd0;
4718         sdram_dfi_p0_bank <= array_muxed0;
4719         sdram_dfi_p0_address <= array_muxed1;
4720         sdram_dfi_p0_cas_n <= (~array_muxed2);
4721         sdram_dfi_p0_ras_n <= (~array_muxed3);
4722         sdram_dfi_p0_we_n <= (~array_muxed4);
4723         sdram_dfi_p0_rddata_en <= array_muxed5;
4724         sdram_dfi_p0_wrdata_en <= array_muxed6;
4725         if (sdram_tccdcon_valid) begin
4726                 sdram_tccdcon_count <= 1'd0;
4727                 if (1'd1) begin
4728                         sdram_tccdcon_ready <= 1'd1;
4729                 end else begin
4730                         sdram_tccdcon_ready <= 1'd0;
4731                 end
4732         end else begin
4733                 if ((~sdram_tccdcon_ready)) begin
4734                         sdram_tccdcon_count <= (sdram_tccdcon_count - 1'd1);
4735                         if ((sdram_tccdcon_count == 1'd1)) begin
4736                                 sdram_tccdcon_ready <= 1'd1;
4737                         end
4738                 end
4739         end
4740         if (sdram_twtrcon_valid) begin
4741                 sdram_twtrcon_count <= 3'd4;
4742                 if (1'd0) begin
4743                         sdram_twtrcon_ready <= 1'd1;
4744                 end else begin
4745                         sdram_twtrcon_ready <= 1'd0;
4746                 end
4747         end else begin
4748                 if ((~sdram_twtrcon_ready)) begin
4749                         sdram_twtrcon_count <= (sdram_twtrcon_count - 1'd1);
4750                         if ((sdram_twtrcon_count == 1'd1)) begin
4751                                 sdram_twtrcon_ready <= 1'd1;
4752                         end
4753                 end
4754         end
4755         subfragments_multiplexer_state <= subfragments_multiplexer_next_state;
4756         subfragments_new_master_wdata_ready <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_wdata_ready)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_wdata_ready)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_wdata_ready)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_wdata_ready));
4757         subfragments_new_master_rdata_valid0 <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_rdata_valid)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_rdata_valid)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_rdata_valid)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_rdata_valid));
4758         subfragments_new_master_rdata_valid1 <= subfragments_new_master_rdata_valid0;
4759         subfragments_new_master_rdata_valid2 <= subfragments_new_master_rdata_valid1;
4760         subfragments_new_master_rdata_valid3 <= subfragments_new_master_rdata_valid2;
4761         if ((litedram_wb_ack | converter_skip)) begin
4762                 converter_dat_r <= wb_sdram_dat_r;
4763         end
4764         subfragments_state <= subfragments_next_state;
4765         if (converter_counter_subfragments_next_value_ce) begin
4766                 converter_counter <= converter_counter_subfragments_next_value;
4767         end
4768         if (converter_reset) begin
4769                 converter_counter <= 1'd0;
4770                 subfragments_state <= 1'd0;
4771         end
4772         if (litedram_wb_ack) begin
4773                 cmd_consumed <= 1'd0;
4774                 wdata_consumed <= 1'd0;
4775         end else begin
4776                 if ((port_cmd_valid & port_cmd_ready)) begin
4777                         cmd_consumed <= 1'd1;
4778                 end
4779                 if ((port_wdata_valid & port_wdata_ready)) begin
4780                         wdata_consumed <= 1'd1;
4781                 end
4782         end
4783         uart_phy_sink_ready <= 1'd0;
4784         if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin
4785                 uart_phy_tx_reg <= uart_phy_sink_payload_data;
4786                 uart_phy_tx_bitcount <= 1'd0;
4787                 uart_phy_tx_busy <= 1'd1;
4788                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd0;
4789         end else begin
4790                 if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin
4791                         uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1);
4792                         if ((uart_phy_tx_bitcount == 4'd8)) begin
4793                                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
4794                         end else begin
4795                                 if ((uart_phy_tx_bitcount == 4'd9)) begin
4796                                         libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
4797                                         uart_phy_tx_busy <= 1'd0;
4798                                         uart_phy_sink_ready <= 1'd1;
4799                                 end else begin
4800                                         libresocsim_libresoc_constraintmanager_uart_tx <= uart_phy_tx_reg[0];
4801                                         uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]};
4802                                 end
4803                         end
4804                 end
4805         end
4806         if (uart_phy_tx_busy) begin
4807                 {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage);
4808         end else begin
4809                 {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= uart_phy_storage;
4810         end
4811         uart_phy_source_valid <= 1'd0;
4812         uart_phy_rx_r <= uart_phy_rx;
4813         if ((~uart_phy_rx_busy)) begin
4814                 if (((~uart_phy_rx) & uart_phy_rx_r)) begin
4815                         uart_phy_rx_busy <= 1'd1;
4816                         uart_phy_rx_bitcount <= 1'd0;
4817                 end
4818         end else begin
4819                 if (uart_phy_uart_clk_rxen) begin
4820                         uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1);
4821                         if ((uart_phy_rx_bitcount == 1'd0)) begin
4822                                 if (uart_phy_rx) begin
4823                                         uart_phy_rx_busy <= 1'd0;
4824                                 end
4825                         end else begin
4826                                 if ((uart_phy_rx_bitcount == 4'd9)) begin
4827                                         uart_phy_rx_busy <= 1'd0;
4828                                         if (uart_phy_rx) begin
4829                                                 uart_phy_source_payload_data <= uart_phy_rx_reg;
4830                                                 uart_phy_source_valid <= 1'd1;
4831                                         end
4832                                 end else begin
4833                                         uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]};
4834                                 end
4835                         end
4836                 end
4837         end
4838         if (uart_phy_rx_busy) begin
4839                 {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage);
4840         end else begin
4841                 {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648;
4842         end
4843         if (tx_clear) begin
4844                 tx_pending <= 1'd0;
4845         end
4846         tx_old_trigger <= tx_trigger;
4847         if (((~tx_trigger) & tx_old_trigger)) begin
4848                 tx_pending <= 1'd1;
4849         end
4850         if (rx_clear) begin
4851                 rx_pending <= 1'd0;
4852         end
4853         rx_old_trigger <= rx_trigger;
4854         if (((~rx_trigger) & rx_old_trigger)) begin
4855                 rx_pending <= 1'd1;
4856         end
4857         if (tx_fifo_syncfifo_re) begin
4858                 tx_fifo_readable <= 1'd1;
4859         end else begin
4860                 if (tx_fifo_re) begin
4861                         tx_fifo_readable <= 1'd0;
4862                 end
4863         end
4864         if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin
4865                 tx_fifo_produce <= (tx_fifo_produce + 1'd1);
4866         end
4867         if (tx_fifo_do_read) begin
4868                 tx_fifo_consume <= (tx_fifo_consume + 1'd1);
4869         end
4870         if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin
4871                 if ((~tx_fifo_do_read)) begin
4872                         tx_fifo_level0 <= (tx_fifo_level0 + 1'd1);
4873                 end
4874         end else begin
4875                 if (tx_fifo_do_read) begin
4876                         tx_fifo_level0 <= (tx_fifo_level0 - 1'd1);
4877                 end
4878         end
4879         if (rx_fifo_syncfifo_re) begin
4880                 rx_fifo_readable <= 1'd1;
4881         end else begin
4882                 if (rx_fifo_re) begin
4883                         rx_fifo_readable <= 1'd0;
4884                 end
4885         end
4886         if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin
4887                 rx_fifo_produce <= (rx_fifo_produce + 1'd1);
4888         end
4889         if (rx_fifo_do_read) begin
4890                 rx_fifo_consume <= (rx_fifo_consume + 1'd1);
4891         end
4892         if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin
4893                 if ((~rx_fifo_do_read)) begin
4894                         rx_fifo_level0 <= (rx_fifo_level0 + 1'd1);
4895                 end
4896         end else begin
4897                 if (rx_fifo_do_read) begin
4898                         rx_fifo_level0 <= (rx_fifo_level0 - 1'd1);
4899                 end
4900         end
4901         if (reset) begin
4902                 tx_pending <= 1'd0;
4903                 tx_old_trigger <= 1'd0;
4904                 rx_pending <= 1'd0;
4905                 rx_old_trigger <= 1'd0;
4906                 tx_fifo_readable <= 1'd0;
4907                 tx_fifo_level0 <= 5'd0;
4908                 tx_fifo_produce <= 4'd0;
4909                 tx_fifo_consume <= 4'd0;
4910                 rx_fifo_readable <= 1'd0;
4911                 rx_fifo_level0 <= 5'd0;
4912                 rx_fifo_produce <= 4'd0;
4913                 rx_fifo_consume <= 4'd0;
4914         end
4915         libresocsim_state <= libresocsim_next_state;
4916         if (libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0) begin
4917                 libresocsim_libresocsim_dat_w <= libresocsim_libresocsim_dat_w_libresocsim_next_value0;
4918         end
4919         if (libresocsim_libresocsim_adr_libresocsim_next_value_ce1) begin
4920                 libresocsim_libresocsim_adr <= libresocsim_libresocsim_adr_libresocsim_next_value1;
4921         end
4922         if (libresocsim_libresocsim_we_libresocsim_next_value_ce2) begin
4923                 libresocsim_libresocsim_we <= libresocsim_libresocsim_we_libresocsim_next_value2;
4924         end
4925         case (libresocsim_grant)
4926                 1'd0: begin
4927                         if ((~libresocsim_request[0])) begin
4928                                 if (libresocsim_request[1]) begin
4929                                         libresocsim_grant <= 1'd1;
4930                                 end else begin
4931                                         if (libresocsim_request[2]) begin
4932                                                 libresocsim_grant <= 2'd2;
4933                                         end
4934                                 end
4935                         end
4936                 end
4937                 1'd1: begin
4938                         if ((~libresocsim_request[1])) begin
4939                                 if (libresocsim_request[2]) begin
4940                                         libresocsim_grant <= 2'd2;
4941                                 end else begin
4942                                         if (libresocsim_request[0]) begin
4943                                                 libresocsim_grant <= 1'd0;
4944                                         end
4945                                 end
4946                         end
4947                 end
4948                 2'd2: begin
4949                         if ((~libresocsim_request[2])) begin
4950                                 if (libresocsim_request[0]) begin
4951                                         libresocsim_grant <= 1'd0;
4952                                 end else begin
4953                                         if (libresocsim_request[1]) begin
4954                                                 libresocsim_grant <= 1'd1;
4955                                         end
4956                                 end
4957                         end
4958                 end
4959         endcase
4960         libresocsim_slave_sel_r <= libresocsim_slave_sel;
4961         if (libresocsim_wait) begin
4962                 if ((~libresocsim_done)) begin
4963                         libresocsim_count <= (libresocsim_count - 1'd1);
4964                 end
4965         end else begin
4966                 libresocsim_count <= 20'd1000000;
4967         end
4968         libresocsim_interface0_bank_bus_dat_r <= 1'd0;
4969         if (libresocsim_csrbank0_sel) begin
4970                 case (libresocsim_interface0_bank_bus_adr[3:0])
4971                         1'd0: begin
4972                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_reset0_w;
4973                         end
4974                         1'd1: begin
4975                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch3_w;
4976                         end
4977                         2'd2: begin
4978                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch2_w;
4979                         end
4980                         2'd3: begin
4981                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch1_w;
4982                         end
4983                         3'd4: begin
4984                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch0_w;
4985                         end
4986                         3'd5: begin
4987                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors3_w;
4988                         end
4989                         3'd6: begin
4990                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors2_w;
4991                         end
4992                         3'd7: begin
4993                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors1_w;
4994                         end
4995                         4'd8: begin
4996                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors0_w;
4997                         end
4998                 endcase
4999         end
5000         if (libresocsim_csrbank0_reset0_re) begin
5001                 libresocsim_reset_storage <= libresocsim_csrbank0_reset0_r;
5002         end
5003         libresocsim_reset_re <= libresocsim_csrbank0_reset0_re;
5004         if (libresocsim_csrbank0_scratch3_re) begin
5005                 libresocsim_scratch_storage[31:24] <= libresocsim_csrbank0_scratch3_r;
5006         end
5007         if (libresocsim_csrbank0_scratch2_re) begin
5008                 libresocsim_scratch_storage[23:16] <= libresocsim_csrbank0_scratch2_r;
5009         end
5010         if (libresocsim_csrbank0_scratch1_re) begin
5011                 libresocsim_scratch_storage[15:8] <= libresocsim_csrbank0_scratch1_r;
5012         end
5013         if (libresocsim_csrbank0_scratch0_re) begin
5014                 libresocsim_scratch_storage[7:0] <= libresocsim_csrbank0_scratch0_r;
5015         end
5016         libresocsim_scratch_re <= libresocsim_csrbank0_scratch0_re;
5017         libresocsim_interface1_bank_bus_dat_r <= 1'd0;
5018         if (libresocsim_csrbank1_sel) begin
5019                 case (libresocsim_interface1_bank_bus_adr[1:0])
5020                         1'd0: begin
5021                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_oe0_w;
5022                         end
5023                         1'd1: begin
5024                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_in_w;
5025                         end
5026                         2'd2: begin
5027                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_out0_w;
5028                         end
5029                 endcase
5030         end
5031         if (libresocsim_csrbank1_oe0_re) begin
5032                 gpio0_oe_storage[7:0] <= libresocsim_csrbank1_oe0_r;
5033         end
5034         gpio0_oe_re <= libresocsim_csrbank1_oe0_re;
5035         if (libresocsim_csrbank1_out0_re) begin
5036                 gpio0_out_storage[7:0] <= libresocsim_csrbank1_out0_r;
5037         end
5038         gpio0_out_re <= libresocsim_csrbank1_out0_re;
5039         libresocsim_interface2_bank_bus_dat_r <= 1'd0;
5040         if (libresocsim_csrbank2_sel) begin
5041                 case (libresocsim_interface2_bank_bus_adr[1:0])
5042                         1'd0: begin
5043                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_oe0_w;
5044                         end
5045                         1'd1: begin
5046                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_in_w;
5047                         end
5048                         2'd2: begin
5049                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_out0_w;
5050                         end
5051                 endcase
5052         end
5053         if (libresocsim_csrbank2_oe0_re) begin
5054                 gpio1_oe_storage[7:0] <= libresocsim_csrbank2_oe0_r;
5055         end
5056         gpio1_oe_re <= libresocsim_csrbank2_oe0_re;
5057         if (libresocsim_csrbank2_out0_re) begin
5058                 gpio1_out_storage[7:0] <= libresocsim_csrbank2_out0_r;
5059         end
5060         gpio1_out_re <= libresocsim_csrbank2_out0_re;
5061         libresocsim_interface3_bank_bus_dat_r <= 1'd0;
5062         if (libresocsim_csrbank3_sel) begin
5063                 case (libresocsim_interface3_bank_bus_adr[0])
5064                         1'd0: begin
5065                                 libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_w0_w;
5066                         end
5067                         1'd1: begin
5068                                 libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_r_w;
5069                         end
5070                 endcase
5071         end
5072         if (libresocsim_csrbank3_w0_re) begin
5073                 i2c_storage[2:0] <= libresocsim_csrbank3_w0_r;
5074         end
5075         i2c_re <= libresocsim_csrbank3_w0_re;
5076         libresocsim_interface4_bank_bus_dat_r <= 1'd0;
5077         if (libresocsim_csrbank4_sel) begin
5078                 case (libresocsim_interface4_bank_bus_adr[3:0])
5079                         1'd0: begin
5080                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_control0_w;
5081                         end
5082                         1'd1: begin
5083                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_command0_w;
5084                         end
5085                         2'd2: begin
5086                                 libresocsim_interface4_bank_bus_dat_r <= sdram_command_issue_w;
5087                         end
5088                         2'd3: begin
5089                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address1_w;
5090                         end
5091                         3'd4: begin
5092                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address0_w;
5093                         end
5094                         3'd5: begin
5095                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_baddress0_w;
5096                         end
5097                         3'd6: begin
5098                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata1_w;
5099                         end
5100                         3'd7: begin
5101                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata0_w;
5102                         end
5103                         4'd8: begin
5104                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata1_w;
5105                         end
5106                         4'd9: begin
5107                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata0_w;
5108                         end
5109                 endcase
5110         end
5111         if (libresocsim_csrbank4_dfii_control0_re) begin
5112                 sdram_storage[3:0] <= libresocsim_csrbank4_dfii_control0_r;
5113         end
5114         sdram_re <= libresocsim_csrbank4_dfii_control0_re;
5115         if (libresocsim_csrbank4_dfii_pi0_command0_re) begin
5116                 sdram_command_storage[5:0] <= libresocsim_csrbank4_dfii_pi0_command0_r;
5117         end
5118         sdram_command_re <= libresocsim_csrbank4_dfii_pi0_command0_re;
5119         if (libresocsim_csrbank4_dfii_pi0_address1_re) begin
5120                 sdram_address_storage[12:8] <= libresocsim_csrbank4_dfii_pi0_address1_r;
5121         end
5122         if (libresocsim_csrbank4_dfii_pi0_address0_re) begin
5123                 sdram_address_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_address0_r;
5124         end
5125         sdram_address_re <= libresocsim_csrbank4_dfii_pi0_address0_re;
5126         if (libresocsim_csrbank4_dfii_pi0_baddress0_re) begin
5127                 sdram_baddress_storage[1:0] <= libresocsim_csrbank4_dfii_pi0_baddress0_r;
5128         end
5129         sdram_baddress_re <= libresocsim_csrbank4_dfii_pi0_baddress0_re;
5130         if (libresocsim_csrbank4_dfii_pi0_wrdata1_re) begin
5131                 sdram_wrdata_storage[15:8] <= libresocsim_csrbank4_dfii_pi0_wrdata1_r;
5132         end
5133         if (libresocsim_csrbank4_dfii_pi0_wrdata0_re) begin
5134                 sdram_wrdata_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_wrdata0_r;
5135         end
5136         sdram_wrdata_re <= libresocsim_csrbank4_dfii_pi0_wrdata0_re;
5137         libresocsim_interface5_bank_bus_dat_r <= 1'd0;
5138         if (libresocsim_csrbank5_sel) begin
5139                 case (libresocsim_interface5_bank_bus_adr[4:0])
5140                         1'd0: begin
5141                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load3_w;
5142                         end
5143                         1'd1: begin
5144                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load2_w;
5145                         end
5146                         2'd2: begin
5147                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load1_w;
5148                         end
5149                         2'd3: begin
5150                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load0_w;
5151                         end
5152                         3'd4: begin
5153                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload3_w;
5154                         end
5155                         3'd5: begin
5156                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload2_w;
5157                         end
5158                         3'd6: begin
5159                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload1_w;
5160                         end
5161                         3'd7: begin
5162                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload0_w;
5163                         end
5164                         4'd8: begin
5165                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_en0_w;
5166                         end
5167                         4'd9: begin
5168                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_update_value0_w;
5169                         end
5170                         4'd10: begin
5171                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value3_w;
5172                         end
5173                         4'd11: begin
5174                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value2_w;
5175                         end
5176                         4'd12: begin
5177                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value1_w;
5178                         end
5179                         4'd13: begin
5180                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value0_w;
5181                         end
5182                         4'd14: begin
5183                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_status_w;
5184                         end
5185                         4'd15: begin
5186                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_pending_w;
5187                         end
5188                         5'd16: begin
5189                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_ev_enable0_w;
5190                         end
5191                 endcase
5192         end
5193         if (libresocsim_csrbank5_load3_re) begin
5194                 libresocsim_load_storage[31:24] <= libresocsim_csrbank5_load3_r;
5195         end
5196         if (libresocsim_csrbank5_load2_re) begin
5197                 libresocsim_load_storage[23:16] <= libresocsim_csrbank5_load2_r;
5198         end
5199         if (libresocsim_csrbank5_load1_re) begin
5200                 libresocsim_load_storage[15:8] <= libresocsim_csrbank5_load1_r;
5201         end
5202         if (libresocsim_csrbank5_load0_re) begin
5203                 libresocsim_load_storage[7:0] <= libresocsim_csrbank5_load0_r;
5204         end
5205         libresocsim_load_re <= libresocsim_csrbank5_load0_re;
5206         if (libresocsim_csrbank5_reload3_re) begin
5207                 libresocsim_reload_storage[31:24] <= libresocsim_csrbank5_reload3_r;
5208         end
5209         if (libresocsim_csrbank5_reload2_re) begin
5210                 libresocsim_reload_storage[23:16] <= libresocsim_csrbank5_reload2_r;
5211         end
5212         if (libresocsim_csrbank5_reload1_re) begin
5213                 libresocsim_reload_storage[15:8] <= libresocsim_csrbank5_reload1_r;
5214         end
5215         if (libresocsim_csrbank5_reload0_re) begin
5216                 libresocsim_reload_storage[7:0] <= libresocsim_csrbank5_reload0_r;
5217         end
5218         libresocsim_reload_re <= libresocsim_csrbank5_reload0_re;
5219         if (libresocsim_csrbank5_en0_re) begin
5220                 libresocsim_en_storage <= libresocsim_csrbank5_en0_r;
5221         end
5222         libresocsim_en_re <= libresocsim_csrbank5_en0_re;
5223         if (libresocsim_csrbank5_update_value0_re) begin
5224                 libresocsim_update_value_storage <= libresocsim_csrbank5_update_value0_r;
5225         end
5226         libresocsim_update_value_re <= libresocsim_csrbank5_update_value0_re;
5227         if (libresocsim_csrbank5_ev_enable0_re) begin
5228                 libresocsim_eventmanager_storage <= libresocsim_csrbank5_ev_enable0_r;
5229         end
5230         libresocsim_eventmanager_re <= libresocsim_csrbank5_ev_enable0_re;
5231         libresocsim_interface6_bank_bus_dat_r <= 1'd0;
5232         if (libresocsim_csrbank6_sel) begin
5233                 case (libresocsim_interface6_bank_bus_adr[2:0])
5234                         1'd0: begin
5235                                 libresocsim_interface6_bank_bus_dat_r <= rxtx_w;
5236                         end
5237                         1'd1: begin
5238                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txfull_w;
5239                         end
5240                         2'd2: begin
5241                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxempty_w;
5242                         end
5243                         2'd3: begin
5244                                 libresocsim_interface6_bank_bus_dat_r <= eventmanager_status_w;
5245                         end
5246                         3'd4: begin
5247                                 libresocsim_interface6_bank_bus_dat_r <= eventmanager_pending_w;
5248                         end
5249                         3'd5: begin
5250                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_ev_enable0_w;
5251                         end
5252                         3'd6: begin
5253                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txempty_w;
5254                         end
5255                         3'd7: begin
5256                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxfull_w;
5257                         end
5258                 endcase
5259         end
5260         if (libresocsim_csrbank6_ev_enable0_re) begin
5261                 eventmanager_storage[1:0] <= libresocsim_csrbank6_ev_enable0_r;
5262         end
5263         eventmanager_re <= libresocsim_csrbank6_ev_enable0_re;
5264         libresocsim_interface7_bank_bus_dat_r <= 1'd0;
5265         if (libresocsim_csrbank7_sel) begin
5266                 case (libresocsim_interface7_bank_bus_adr[1:0])
5267                         1'd0: begin
5268                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word3_w;
5269                         end
5270                         1'd1: begin
5271                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word2_w;
5272                         end
5273                         2'd2: begin
5274                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word1_w;
5275                         end
5276                         2'd3: begin
5277                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word0_w;
5278                         end
5279                 endcase
5280         end
5281         if (libresocsim_csrbank7_tuning_word3_re) begin
5282                 uart_phy_storage[31:24] <= libresocsim_csrbank7_tuning_word3_r;
5283         end
5284         if (libresocsim_csrbank7_tuning_word2_re) begin
5285                 uart_phy_storage[23:16] <= libresocsim_csrbank7_tuning_word2_r;
5286         end
5287         if (libresocsim_csrbank7_tuning_word1_re) begin
5288                 uart_phy_storage[15:8] <= libresocsim_csrbank7_tuning_word1_r;
5289         end
5290         if (libresocsim_csrbank7_tuning_word0_re) begin
5291                 uart_phy_storage[7:0] <= libresocsim_csrbank7_tuning_word0_r;
5292         end
5293         uart_phy_re <= libresocsim_csrbank7_tuning_word0_re;
5294         if (sys_rst_1) begin
5295                 libresocsim_reset_storage <= 1'd0;
5296                 libresocsim_reset_re <= 1'd0;
5297                 libresocsim_scratch_storage <= 32'd305419896;
5298                 libresocsim_scratch_re <= 1'd0;
5299                 libresocsim_bus_errors <= 32'd0;
5300                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5301                 libresocsim_converter0_counter <= 1'd0;
5302                 libresocsim_converter1_counter <= 1'd0;
5303                 libresocsim_ram_bus_ack <= 1'd0;
5304                 libresocsim_load_storage <= 32'd0;
5305                 libresocsim_load_re <= 1'd0;
5306                 libresocsim_reload_storage <= 32'd0;
5307                 libresocsim_reload_re <= 1'd0;
5308                 libresocsim_en_storage <= 1'd0;
5309                 libresocsim_en_re <= 1'd0;
5310                 libresocsim_update_value_storage <= 1'd0;
5311                 libresocsim_update_value_re <= 1'd0;
5312                 libresocsim_value_status <= 32'd0;
5313                 libresocsim_zero_pending <= 1'd0;
5314                 libresocsim_zero_old_trigger <= 1'd0;
5315                 libresocsim_eventmanager_storage <= 1'd0;
5316                 libresocsim_eventmanager_re <= 1'd0;
5317                 libresocsim_value <= 32'd0;
5318                 ram_bus_ram_bus_ack <= 1'd0;
5319                 dfi_p0_rddata_valid <= 1'd0;
5320                 rddata_en <= 3'd0;
5321                 sdram_storage <= 4'd1;
5322                 sdram_re <= 1'd0;
5323                 sdram_command_storage <= 6'd0;
5324                 sdram_command_re <= 1'd0;
5325                 sdram_address_re <= 1'd0;
5326                 sdram_baddress_re <= 1'd0;
5327                 sdram_wrdata_re <= 1'd0;
5328                 sdram_status <= 16'd0;
5329                 sdram_dfi_p0_address <= 13'd0;
5330                 sdram_dfi_p0_bank <= 2'd0;
5331                 sdram_dfi_p0_cas_n <= 1'd1;
5332                 sdram_dfi_p0_cs_n <= 1'd1;
5333                 sdram_dfi_p0_ras_n <= 1'd1;
5334                 sdram_dfi_p0_we_n <= 1'd1;
5335                 sdram_dfi_p0_wrdata_en <= 1'd0;
5336                 sdram_dfi_p0_rddata_en <= 1'd0;
5337                 sdram_timer_count1 <= 10'd781;
5338                 sdram_postponer_req_o <= 1'd0;
5339                 sdram_postponer_count <= 1'd0;
5340                 sdram_sequencer_done1 <= 1'd0;
5341                 sdram_sequencer_counter <= 4'd0;
5342                 sdram_sequencer_count <= 1'd0;
5343                 sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;
5344                 sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;
5345                 sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;
5346                 sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
5347                 sdram_bankmachine0_row <= 13'd0;
5348                 sdram_bankmachine0_row_opened <= 1'd0;
5349                 sdram_bankmachine0_twtpcon_ready <= 1'd0;
5350                 sdram_bankmachine0_twtpcon_count <= 3'd0;
5351                 sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;
5352                 sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;
5353                 sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;
5354                 sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
5355                 sdram_bankmachine1_row <= 13'd0;
5356                 sdram_bankmachine1_row_opened <= 1'd0;
5357                 sdram_bankmachine1_twtpcon_ready <= 1'd0;
5358                 sdram_bankmachine1_twtpcon_count <= 3'd0;
5359                 sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;
5360                 sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;
5361                 sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;
5362                 sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
5363                 sdram_bankmachine2_row <= 13'd0;
5364                 sdram_bankmachine2_row_opened <= 1'd0;
5365                 sdram_bankmachine2_twtpcon_ready <= 1'd0;
5366                 sdram_bankmachine2_twtpcon_count <= 3'd0;
5367                 sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;
5368                 sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;
5369                 sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;
5370                 sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
5371                 sdram_bankmachine3_row <= 13'd0;
5372                 sdram_bankmachine3_row_opened <= 1'd0;
5373                 sdram_bankmachine3_twtpcon_ready <= 1'd0;
5374                 sdram_bankmachine3_twtpcon_count <= 3'd0;
5375                 sdram_choose_cmd_grant <= 2'd0;
5376                 sdram_choose_req_grant <= 2'd0;
5377                 sdram_tccdcon_ready <= 1'd0;
5378                 sdram_tccdcon_count <= 1'd0;
5379                 sdram_twtrcon_ready <= 1'd0;
5380                 sdram_twtrcon_count <= 3'd0;
5381                 sdram_time0 <= 5'd0;
5382                 sdram_time1 <= 4'd0;
5383                 converter_counter <= 1'd0;
5384                 cmd_consumed <= 1'd0;
5385                 wdata_consumed <= 1'd0;
5386                 uart_phy_storage <= 32'd9895604;
5387                 uart_phy_re <= 1'd0;
5388                 uart_phy_sink_ready <= 1'd0;
5389                 uart_phy_uart_clk_txen <= 1'd0;
5390                 uart_phy_tx_busy <= 1'd0;
5391                 uart_phy_source_valid <= 1'd0;
5392                 uart_phy_uart_clk_rxen <= 1'd0;
5393                 uart_phy_rx_r <= 1'd0;
5394                 uart_phy_rx_busy <= 1'd0;
5395                 tx_pending <= 1'd0;
5396                 tx_old_trigger <= 1'd0;
5397                 rx_pending <= 1'd0;
5398                 rx_old_trigger <= 1'd0;
5399                 eventmanager_storage <= 2'd0;
5400                 eventmanager_re <= 1'd0;
5401                 tx_fifo_readable <= 1'd0;
5402                 tx_fifo_level0 <= 5'd0;
5403                 tx_fifo_produce <= 4'd0;
5404                 tx_fifo_consume <= 4'd0;
5405                 rx_fifo_readable <= 1'd0;
5406                 rx_fifo_level0 <= 5'd0;
5407                 rx_fifo_produce <= 4'd0;
5408                 rx_fifo_consume <= 4'd0;
5409                 gpio0_oe_storage <= 8'd0;
5410                 gpio0_oe_re <= 1'd0;
5411                 gpio0_out_storage <= 8'd0;
5412                 gpio0_out_re <= 1'd0;
5413                 gpio1_oe_storage <= 8'd0;
5414                 gpio1_oe_re <= 1'd0;
5415                 gpio1_out_storage <= 8'd0;
5416                 gpio1_out_re <= 1'd0;
5417                 dummy <= 40'd0;
5418                 i2c_storage <= 3'd0;
5419                 i2c_re <= 1'd0;
5420                 subfragments_converter0_state <= 1'd0;
5421                 subfragments_converter1_state <= 1'd0;
5422                 subfragments_refresher_state <= 2'd0;
5423                 subfragments_bankmachine0_state <= 3'd0;
5424                 subfragments_bankmachine1_state <= 3'd0;
5425                 subfragments_bankmachine2_state <= 3'd0;
5426                 subfragments_bankmachine3_state <= 3'd0;
5427                 subfragments_multiplexer_state <= 3'd0;
5428                 subfragments_new_master_wdata_ready <= 1'd0;
5429                 subfragments_new_master_rdata_valid0 <= 1'd0;
5430                 subfragments_new_master_rdata_valid1 <= 1'd0;
5431                 subfragments_new_master_rdata_valid2 <= 1'd0;
5432                 subfragments_new_master_rdata_valid3 <= 1'd0;
5433                 subfragments_state <= 1'd0;
5434                 libresocsim_libresocsim_we <= 1'd0;
5435                 libresocsim_grant <= 2'd0;
5436                 libresocsim_slave_sel_r <= 6'd0;
5437                 libresocsim_count <= 20'd1000000;
5438                 libresocsim_state <= 2'd0;
5439         end
5440         regs0 <= libresocsim_libresoc_constraintmanager_uart_rx;
5441         regs1 <= regs0;
5442 end
5443
5444 reg [31:0] mem[0:127];
5445 reg [6:0] memadr;
5446 always @(posedge sys_clk_1) begin
5447         if (libresocsim_we[0])
5448                 mem[libresocsim_adr][7:0] <= libresocsim_dat_w[7:0];
5449         if (libresocsim_we[1])
5450                 mem[libresocsim_adr][15:8] <= libresocsim_dat_w[15:8];
5451         if (libresocsim_we[2])
5452                 mem[libresocsim_adr][23:16] <= libresocsim_dat_w[23:16];
5453         if (libresocsim_we[3])
5454                 mem[libresocsim_adr][31:24] <= libresocsim_dat_w[31:24];
5455         memadr <= libresocsim_adr;
5456 end
5457
5458 assign libresocsim_dat_r = mem[memadr];
5459
5460 initial begin
5461         $readmemh("mem.init", mem);
5462 end
5463
5464 reg [31:0] mem_1[0:31];
5465 reg [4:0] memadr_1;
5466 always @(posedge sys_clk_1) begin
5467         if (ram_we[0])
5468                 mem_1[ram_adr][7:0] <= ram_dat_w[7:0];
5469         if (ram_we[1])
5470                 mem_1[ram_adr][15:8] <= ram_dat_w[15:8];
5471         if (ram_we[2])
5472                 mem_1[ram_adr][23:16] <= ram_dat_w[23:16];
5473         if (ram_we[3])
5474                 mem_1[ram_adr][31:24] <= ram_dat_w[31:24];
5475         memadr_1 <= ram_adr;
5476 end
5477
5478 assign ram_dat_r = mem_1[memadr_1];
5479
5480 initial begin
5481         $readmemh("mem_1.init", mem_1);
5482 end
5483
5484 reg [24:0] storage[0:7];
5485 reg [24:0] memdat;
5486 always @(posedge sys_clk_1) begin
5487         if (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
5488                 storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
5489         memdat <= storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
5490 end
5491
5492 always @(posedge sys_clk_1) begin
5493 end
5494
5495 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
5496 assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
5497
5498 reg [24:0] storage_1[0:7];
5499 reg [24:0] memdat_1;
5500 always @(posedge sys_clk_1) begin
5501         if (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
5502                 storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
5503         memdat_1 <= storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
5504 end
5505
5506 always @(posedge sys_clk_1) begin
5507 end
5508
5509 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
5510 assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
5511
5512 reg [24:0] storage_2[0:7];
5513 reg [24:0] memdat_2;
5514 always @(posedge sys_clk_1) begin
5515         if (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
5516                 storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
5517         memdat_2 <= storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
5518 end
5519
5520 always @(posedge sys_clk_1) begin
5521 end
5522
5523 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
5524 assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
5525
5526 reg [24:0] storage_3[0:7];
5527 reg [24:0] memdat_3;
5528 always @(posedge sys_clk_1) begin
5529         if (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
5530                 storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
5531         memdat_3 <= storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
5532 end
5533
5534 always @(posedge sys_clk_1) begin
5535 end
5536
5537 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
5538 assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
5539
5540 reg [9:0] storage_4[0:15];
5541 reg [9:0] memdat_4;
5542 reg [9:0] memdat_5;
5543 always @(posedge sys_clk_1) begin
5544         if (tx_fifo_wrport_we)
5545                 storage_4[tx_fifo_wrport_adr] <= tx_fifo_wrport_dat_w;
5546         memdat_4 <= storage_4[tx_fifo_wrport_adr];
5547 end
5548
5549 always @(posedge sys_clk_1) begin
5550         if (tx_fifo_rdport_re)
5551                 memdat_5 <= storage_4[tx_fifo_rdport_adr];
5552 end
5553
5554 assign tx_fifo_wrport_dat_r = memdat_4;
5555 assign tx_fifo_rdport_dat_r = memdat_5;
5556
5557 reg [9:0] storage_5[0:15];
5558 reg [9:0] memdat_6;
5559 reg [9:0] memdat_7;
5560 always @(posedge sys_clk_1) begin
5561         if (rx_fifo_wrport_we)
5562                 storage_5[rx_fifo_wrport_adr] <= rx_fifo_wrport_dat_w;
5563         memdat_6 <= storage_5[rx_fifo_wrport_adr];
5564 end
5565
5566 always @(posedge sys_clk_1) begin
5567         if (rx_fifo_rdport_re)
5568                 memdat_7 <= storage_5[rx_fifo_rdport_adr];
5569 end
5570
5571 assign rx_fifo_wrport_dat_r = memdat_6;
5572 assign rx_fifo_rdport_dat_r = memdat_7;
5573
5574 test_issuer test_issuer(
5575         .TAP_bus__tck(libresocsim_libresoc_jtag_tck),
5576         .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi),
5577         .TAP_bus__tms(libresocsim_libresoc_jtag_tms),
5578         .clk(sys_clk_1),
5579         .core_bigendian_i(1'd0),
5580         .dbus__ack(libresocsim_libresoc_dbus_ack),
5581         .dbus__bte(1'd0),
5582         .dbus__cti(1'd0),
5583         .dbus__dat_r(libresocsim_libresoc_dbus_dat_r),
5584         .dbus__err(libresocsim_libresoc_dbus_err),
5585         .eint_0__pad__i(eint_0),
5586         .eint_1__pad__i(eint_1),
5587         .eint_2__pad__i(eint_2),
5588         .gpio_e10__core__o(libresocsim_libresoc_constraintmanager_gpio_o[10]),
5589         .gpio_e10__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[10]),
5590         .gpio_e10__pad__i(gpio_i[10]),
5591         .gpio_e11__core__o(libresocsim_libresoc_constraintmanager_gpio_o[11]),
5592         .gpio_e11__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[11]),
5593         .gpio_e11__pad__i(gpio_i[11]),
5594         .gpio_e12__core__o(libresocsim_libresoc_constraintmanager_gpio_o[12]),
5595         .gpio_e12__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[12]),
5596         .gpio_e12__pad__i(gpio_i[12]),
5597         .gpio_e13__core__o(libresocsim_libresoc_constraintmanager_gpio_o[13]),
5598         .gpio_e13__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[13]),
5599         .gpio_e13__pad__i(gpio_i[13]),
5600         .gpio_e14__core__o(libresocsim_libresoc_constraintmanager_gpio_o[14]),
5601         .gpio_e14__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[14]),
5602         .gpio_e14__pad__i(gpio_i[14]),
5603         .gpio_e15__core__o(libresocsim_libresoc_constraintmanager_gpio_o[15]),
5604         .gpio_e15__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[15]),
5605         .gpio_e15__pad__i(gpio_i[15]),
5606         .gpio_e8__core__o(libresocsim_libresoc_constraintmanager_gpio_o[8]),
5607         .gpio_e8__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[8]),
5608         .gpio_e8__pad__i(gpio_i[8]),
5609         .gpio_e9__core__o(libresocsim_libresoc_constraintmanager_gpio_o[9]),
5610         .gpio_e9__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[9]),
5611         .gpio_e9__pad__i(gpio_i[9]),
5612         .gpio_s0__core__o(libresocsim_libresoc_constraintmanager_gpio_o[0]),
5613         .gpio_s0__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[0]),
5614         .gpio_s0__pad__i(gpio_i[0]),
5615         .gpio_s1__core__o(libresocsim_libresoc_constraintmanager_gpio_o[1]),
5616         .gpio_s1__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[1]),
5617         .gpio_s1__pad__i(gpio_i[1]),
5618         .gpio_s2__core__o(libresocsim_libresoc_constraintmanager_gpio_o[2]),
5619         .gpio_s2__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[2]),
5620         .gpio_s2__pad__i(gpio_i[2]),
5621         .gpio_s3__core__o(libresocsim_libresoc_constraintmanager_gpio_o[3]),
5622         .gpio_s3__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[3]),
5623         .gpio_s3__pad__i(gpio_i[3]),
5624         .gpio_s4__core__o(libresocsim_libresoc_constraintmanager_gpio_o[4]),
5625         .gpio_s4__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[4]),
5626         .gpio_s4__pad__i(gpio_i[4]),
5627         .gpio_s5__core__o(libresocsim_libresoc_constraintmanager_gpio_o[5]),
5628         .gpio_s5__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[5]),
5629         .gpio_s5__pad__i(gpio_i[5]),
5630         .gpio_s6__core__o(libresocsim_libresoc_constraintmanager_gpio_o[6]),
5631         .gpio_s6__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[6]),
5632         .gpio_s6__pad__i(gpio_i[6]),
5633         .gpio_s7__core__o(libresocsim_libresoc_constraintmanager_gpio_o[7]),
5634         .gpio_s7__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[7]),
5635         .gpio_s7__pad__i(gpio_i[7]),
5636         .ibus__ack(libresocsim_libresoc_ibus_ack),
5637         .ibus__bte(1'd0),
5638         .ibus__cti(1'd0),
5639         .ibus__dat_r(libresocsim_libresoc_ibus_dat_r),
5640         .ibus__err(libresocsim_libresoc_ibus_err),
5641         .icp_wb__adr(libresocsim_libresoc_xics_icp_adr),
5642         .icp_wb__cyc(libresocsim_libresoc_xics_icp_cyc),
5643         .icp_wb__dat_w(libresocsim_libresoc_xics_icp_dat_w),
5644         .icp_wb__sel(libresocsim_libresoc_xics_icp_sel),
5645         .icp_wb__stb(libresocsim_libresoc_xics_icp_stb),
5646         .icp_wb__we(libresocsim_libresoc_xics_icp_we),
5647         .ics_wb__adr(libresocsim_libresoc_xics_ics_adr),
5648         .ics_wb__cyc(libresocsim_libresoc_xics_ics_cyc),
5649         .ics_wb__dat_w(libresocsim_libresoc_xics_ics_dat_w),
5650         .ics_wb__sel(libresocsim_libresoc_xics_ics_sel),
5651         .ics_wb__stb(libresocsim_libresoc_xics_ics_stb),
5652         .ics_wb__we(libresocsim_libresoc_xics_ics_we),
5653         .int_level_i(libresocsim_libresoc_interrupt),
5654         .jtag_wb__ack(libresocsim_libresoc_jtag_wb_ack),
5655         .jtag_wb__dat_r(libresocsim_libresoc_jtag_wb_dat_r),
5656         .jtag_wb__err(libresocsim_libresoc_jtag_wb_err),
5657         .mspi0_clk__core__o(libresocsim_libresoc_constraintmanager_spimaster_clk),
5658         .mspi0_cs_n__core__o(libresocsim_libresoc_constraintmanager_spimaster_cs_n),
5659         .mspi0_miso__pad__i(spimaster_miso),
5660         .mspi0_mosi__core__o(libresocsim_libresoc_constraintmanager_spimaster_mosi),
5661         .mtwi_scl__core__o(libresocsim_libresoc_constraintmanager_i2c_scl),
5662         .mtwi_sda__core__o(libresocsim_libresoc_constraintmanager_i2c_sda_o),
5663         .mtwi_sda__core__oe(libresocsim_libresoc_constraintmanager_i2c_sda_oe),
5664         .mtwi_sda__pad__i(i2c_sda_i),
5665         .pc_i(libresocsim_libresoc0),
5666         .pc_i_ok(1'd0),
5667         .rst((sys_rst_1 | libresocsim_libresoc_reset)),
5668         .sdr_a_0__core__o(libresocsim_libresoc_constraintmanager_sdram_a[0]),
5669         .sdr_a_10__core__o(libresocsim_libresoc_constraintmanager_sdram_a[10]),
5670         .sdr_a_11__core__o(libresocsim_libresoc_constraintmanager_sdram_a[11]),
5671         .sdr_a_12__core__o(libresocsim_libresoc_constraintmanager_sdram_a[12]),
5672         .sdr_a_1__core__o(libresocsim_libresoc_constraintmanager_sdram_a[1]),
5673         .sdr_a_2__core__o(libresocsim_libresoc_constraintmanager_sdram_a[2]),
5674         .sdr_a_3__core__o(libresocsim_libresoc_constraintmanager_sdram_a[3]),
5675         .sdr_a_4__core__o(libresocsim_libresoc_constraintmanager_sdram_a[4]),
5676         .sdr_a_5__core__o(libresocsim_libresoc_constraintmanager_sdram_a[5]),
5677         .sdr_a_6__core__o(libresocsim_libresoc_constraintmanager_sdram_a[6]),
5678         .sdr_a_7__core__o(libresocsim_libresoc_constraintmanager_sdram_a[7]),
5679         .sdr_a_8__core__o(libresocsim_libresoc_constraintmanager_sdram_a[8]),
5680         .sdr_a_9__core__o(libresocsim_libresoc_constraintmanager_sdram_a[9]),
5681         .sdr_ba_0__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[0]),
5682         .sdr_ba_1__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[1]),
5683         .sdr_cas_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cas_n),
5684         .sdr_cke__core__o(libresocsim_libresoc_constraintmanager_sdram_cke),
5685         .sdr_clock__core__o(libresocsim_libresoc_constraintmanager_sdram_clock),
5686         .sdr_cs_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cs_n),
5687         .sdr_dm_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[0]),
5688         .sdr_dm_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[1]),
5689         .sdr_dq_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[0]),
5690         .sdr_dq_0__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[0]),
5691         .sdr_dq_0__pad__i(sdram_dq_i[0]),
5692         .sdr_dq_10__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[10]),
5693         .sdr_dq_10__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[10]),
5694         .sdr_dq_10__pad__i(sdram_dq_i[10]),
5695         .sdr_dq_11__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[11]),
5696         .sdr_dq_11__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[11]),
5697         .sdr_dq_11__pad__i(sdram_dq_i[11]),
5698         .sdr_dq_12__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[12]),
5699         .sdr_dq_12__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[12]),
5700         .sdr_dq_12__pad__i(sdram_dq_i[12]),
5701         .sdr_dq_13__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[13]),
5702         .sdr_dq_13__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[13]),
5703         .sdr_dq_13__pad__i(sdram_dq_i[13]),
5704         .sdr_dq_14__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[14]),
5705         .sdr_dq_14__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[14]),
5706         .sdr_dq_14__pad__i(sdram_dq_i[14]),
5707         .sdr_dq_15__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[15]),
5708         .sdr_dq_15__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[15]),
5709         .sdr_dq_15__pad__i(sdram_dq_i[15]),
5710         .sdr_dq_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[1]),
5711         .sdr_dq_1__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[1]),
5712         .sdr_dq_1__pad__i(sdram_dq_i[1]),
5713         .sdr_dq_2__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[2]),
5714         .sdr_dq_2__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[2]),
5715         .sdr_dq_2__pad__i(sdram_dq_i[2]),
5716         .sdr_dq_3__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[3]),
5717         .sdr_dq_3__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[3]),
5718         .sdr_dq_3__pad__i(sdram_dq_i[3]),
5719         .sdr_dq_4__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[4]),
5720         .sdr_dq_4__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[4]),
5721         .sdr_dq_4__pad__i(sdram_dq_i[4]),
5722         .sdr_dq_5__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[5]),
5723         .sdr_dq_5__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[5]),
5724         .sdr_dq_5__pad__i(sdram_dq_i[5]),
5725         .sdr_dq_6__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[6]),
5726         .sdr_dq_6__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[6]),
5727         .sdr_dq_6__pad__i(sdram_dq_i[6]),
5728         .sdr_dq_7__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[7]),
5729         .sdr_dq_7__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[7]),
5730         .sdr_dq_7__pad__i(sdram_dq_i[7]),
5731         .sdr_dq_8__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[8]),
5732         .sdr_dq_8__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[8]),
5733         .sdr_dq_8__pad__i(sdram_dq_i[8]),
5734         .sdr_dq_9__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[9]),
5735         .sdr_dq_9__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[9]),
5736         .sdr_dq_9__pad__i(sdram_dq_i[9]),
5737         .sdr_ras_n__core__o(libresocsim_libresoc_constraintmanager_sdram_ras_n),
5738         .sdr_we_n__core__o(libresocsim_libresoc_constraintmanager_sdram_we_n),
5739         .TAP_bus__tdo(libresocsim_libresoc_jtag_tdo),
5740         .busy_o(libresocsim_libresoc1),
5741         .dbus__adr(libresocsim_libresoc_dbus_adr),
5742         .dbus__cyc(libresocsim_libresoc_dbus_cyc),
5743         .dbus__dat_w(libresocsim_libresoc_dbus_dat_w),
5744         .dbus__sel(libresocsim_libresoc_dbus_sel),
5745         .dbus__stb(libresocsim_libresoc_dbus_stb),
5746         .dbus__we(libresocsim_libresoc_dbus_we),
5747         .eint_0__core__i(libresocsim_libresoc_constraintmanager_eint_0),
5748         .eint_1__core__i(libresocsim_libresoc_constraintmanager_eint_1),
5749         .eint_2__core__i(libresocsim_libresoc_constraintmanager_eint_2),
5750         .gpio_e10__core__i(libresocsim_libresoc_constraintmanager_gpio_i[10]),
5751         .gpio_e10__pad__o(gpio_o[10]),
5752         .gpio_e10__pad__oe(gpio_oe[10]),
5753         .gpio_e11__core__i(libresocsim_libresoc_constraintmanager_gpio_i[11]),
5754         .gpio_e11__pad__o(gpio_o[11]),
5755         .gpio_e11__pad__oe(gpio_oe[11]),
5756         .gpio_e12__core__i(libresocsim_libresoc_constraintmanager_gpio_i[12]),
5757         .gpio_e12__pad__o(gpio_o[12]),
5758         .gpio_e12__pad__oe(gpio_oe[12]),
5759         .gpio_e13__core__i(libresocsim_libresoc_constraintmanager_gpio_i[13]),
5760         .gpio_e13__pad__o(gpio_o[13]),
5761         .gpio_e13__pad__oe(gpio_oe[13]),
5762         .gpio_e14__core__i(libresocsim_libresoc_constraintmanager_gpio_i[14]),
5763         .gpio_e14__pad__o(gpio_o[14]),
5764         .gpio_e14__pad__oe(gpio_oe[14]),
5765         .gpio_e15__core__i(libresocsim_libresoc_constraintmanager_gpio_i[15]),
5766         .gpio_e15__pad__o(gpio_o[15]),
5767         .gpio_e15__pad__oe(gpio_oe[15]),
5768         .gpio_e8__core__i(libresocsim_libresoc_constraintmanager_gpio_i[8]),
5769         .gpio_e8__pad__o(gpio_o[8]),
5770         .gpio_e8__pad__oe(gpio_oe[8]),
5771         .gpio_e9__core__i(libresocsim_libresoc_constraintmanager_gpio_i[9]),
5772         .gpio_e9__pad__o(gpio_o[9]),
5773         .gpio_e9__pad__oe(gpio_oe[9]),
5774         .gpio_s0__core__i(libresocsim_libresoc_constraintmanager_gpio_i[0]),
5775         .gpio_s0__pad__o(gpio_o[0]),
5776         .gpio_s0__pad__oe(gpio_oe[0]),
5777         .gpio_s1__core__i(libresocsim_libresoc_constraintmanager_gpio_i[1]),
5778         .gpio_s1__pad__o(gpio_o[1]),
5779         .gpio_s1__pad__oe(gpio_oe[1]),
5780         .gpio_s2__core__i(libresocsim_libresoc_constraintmanager_gpio_i[2]),
5781         .gpio_s2__pad__o(gpio_o[2]),
5782         .gpio_s2__pad__oe(gpio_oe[2]),
5783         .gpio_s3__core__i(libresocsim_libresoc_constraintmanager_gpio_i[3]),
5784         .gpio_s3__pad__o(gpio_o[3]),
5785         .gpio_s3__pad__oe(gpio_oe[3]),
5786         .gpio_s4__core__i(libresocsim_libresoc_constraintmanager_gpio_i[4]),
5787         .gpio_s4__pad__o(gpio_o[4]),
5788         .gpio_s4__pad__oe(gpio_oe[4]),
5789         .gpio_s5__core__i(libresocsim_libresoc_constraintmanager_gpio_i[5]),
5790         .gpio_s5__pad__o(gpio_o[5]),
5791         .gpio_s5__pad__oe(gpio_oe[5]),
5792         .gpio_s6__core__i(libresocsim_libresoc_constraintmanager_gpio_i[6]),
5793         .gpio_s6__pad__o(gpio_o[6]),
5794         .gpio_s6__pad__oe(gpio_oe[6]),
5795         .gpio_s7__core__i(libresocsim_libresoc_constraintmanager_gpio_i[7]),
5796         .gpio_s7__pad__o(gpio_o[7]),
5797         .gpio_s7__pad__oe(gpio_oe[7]),
5798         .ibus__adr(libresocsim_libresoc_ibus_adr),
5799         .ibus__cyc(libresocsim_libresoc_ibus_cyc),
5800         .ibus__dat_w(libresocsim_libresoc_ibus_dat_w),
5801         .ibus__sel(libresocsim_libresoc_ibus_sel),
5802         .ibus__stb(libresocsim_libresoc_ibus_stb),
5803         .ibus__we(libresocsim_libresoc_ibus_we),
5804         .icp_wb__ack(libresocsim_libresoc_xics_icp_ack),
5805         .icp_wb__dat_r(libresocsim_libresoc_xics_icp_dat_r),
5806         .icp_wb__err(libresocsim_libresoc_xics_icp_err),
5807         .ics_wb__ack(libresocsim_libresoc_xics_ics_ack),
5808         .ics_wb__dat_r(libresocsim_libresoc_xics_ics_dat_r),
5809         .ics_wb__err(libresocsim_libresoc_xics_ics_err),
5810         .jtag_wb__adr(libresocsim_libresoc_jtag_wb_adr),
5811         .jtag_wb__cyc(libresocsim_libresoc_jtag_wb_cyc),
5812         .jtag_wb__dat_w(libresocsim_libresoc_jtag_wb_dat_w),
5813         .jtag_wb__sel(libresocsim_libresoc_jtag_wb_sel),
5814         .jtag_wb__stb(libresocsim_libresoc_jtag_wb_stb),
5815         .jtag_wb__we(libresocsim_libresoc_jtag_wb_we),
5816         .memerr_o(libresocsim_libresoc2),
5817         .mspi0_clk__pad__o(spimaster_clk),
5818         .mspi0_cs_n__pad__o(spimaster_cs_n),
5819         .mspi0_miso__core__i(libresocsim_libresoc_constraintmanager_spimaster_miso),
5820         .mspi0_mosi__pad__o(spimaster_mosi),
5821         .mtwi_scl__pad__o(i2c_scl),
5822         .mtwi_sda__core__i(libresocsim_libresoc_constraintmanager_i2c_sda_i),
5823         .mtwi_sda__pad__o(i2c_sda_o),
5824         .mtwi_sda__pad__oe(i2c_sda_oe),
5825         .pc_o(libresocsim_libresoc3),
5826         .sdr_a_0__pad__o(sdram_a[0]),
5827         .sdr_a_10__pad__o(sdram_a[10]),
5828         .sdr_a_11__pad__o(sdram_a[11]),
5829         .sdr_a_12__pad__o(sdram_a[12]),
5830         .sdr_a_1__pad__o(sdram_a[1]),
5831         .sdr_a_2__pad__o(sdram_a[2]),
5832         .sdr_a_3__pad__o(sdram_a[3]),
5833         .sdr_a_4__pad__o(sdram_a[4]),
5834         .sdr_a_5__pad__o(sdram_a[5]),
5835         .sdr_a_6__pad__o(sdram_a[6]),
5836         .sdr_a_7__pad__o(sdram_a[7]),
5837         .sdr_a_8__pad__o(sdram_a[8]),
5838         .sdr_a_9__pad__o(sdram_a[9]),
5839         .sdr_ba_0__pad__o(sdram_ba[0]),
5840         .sdr_ba_1__pad__o(sdram_ba[1]),
5841         .sdr_cas_n__pad__o(sdram_cas_n),
5842         .sdr_cke__pad__o(sdram_cke),
5843         .sdr_clock__pad__o(sdram_clock),
5844         .sdr_cs_n__pad__o(sdram_cs_n),
5845         .sdr_dm_0__pad__o(sdram_dm[0]),
5846         .sdr_dm_1__pad__o(sdram_dm[1]),
5847         .sdr_dq_0__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[0]),
5848         .sdr_dq_0__pad__o(sdram_dq_o[0]),
5849         .sdr_dq_0__pad__oe(sdram_dq_oe[0]),
5850         .sdr_dq_10__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[10]),
5851         .sdr_dq_10__pad__o(sdram_dq_o[10]),
5852         .sdr_dq_10__pad__oe(sdram_dq_oe[10]),
5853         .sdr_dq_11__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[11]),
5854         .sdr_dq_11__pad__o(sdram_dq_o[11]),
5855         .sdr_dq_11__pad__oe(sdram_dq_oe[11]),
5856         .sdr_dq_12__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[12]),
5857         .sdr_dq_12__pad__o(sdram_dq_o[12]),
5858         .sdr_dq_12__pad__oe(sdram_dq_oe[12]),
5859         .sdr_dq_13__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[13]),
5860         .sdr_dq_13__pad__o(sdram_dq_o[13]),
5861         .sdr_dq_13__pad__oe(sdram_dq_oe[13]),
5862         .sdr_dq_14__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[14]),
5863         .sdr_dq_14__pad__o(sdram_dq_o[14]),
5864         .sdr_dq_14__pad__oe(sdram_dq_oe[14]),
5865         .sdr_dq_15__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[15]),
5866         .sdr_dq_15__pad__o(sdram_dq_o[15]),
5867         .sdr_dq_15__pad__oe(sdram_dq_oe[15]),
5868         .sdr_dq_1__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[1]),
5869         .sdr_dq_1__pad__o(sdram_dq_o[1]),
5870         .sdr_dq_1__pad__oe(sdram_dq_oe[1]),
5871         .sdr_dq_2__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[2]),
5872         .sdr_dq_2__pad__o(sdram_dq_o[2]),
5873         .sdr_dq_2__pad__oe(sdram_dq_oe[2]),
5874         .sdr_dq_3__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[3]),
5875         .sdr_dq_3__pad__o(sdram_dq_o[3]),
5876         .sdr_dq_3__pad__oe(sdram_dq_oe[3]),
5877         .sdr_dq_4__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[4]),
5878         .sdr_dq_4__pad__o(sdram_dq_o[4]),
5879         .sdr_dq_4__pad__oe(sdram_dq_oe[4]),
5880         .sdr_dq_5__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[5]),
5881         .sdr_dq_5__pad__o(sdram_dq_o[5]),
5882         .sdr_dq_5__pad__oe(sdram_dq_oe[5]),
5883         .sdr_dq_6__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[6]),
5884         .sdr_dq_6__pad__o(sdram_dq_o[6]),
5885         .sdr_dq_6__pad__oe(sdram_dq_oe[6]),
5886         .sdr_dq_7__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[7]),
5887         .sdr_dq_7__pad__o(sdram_dq_o[7]),
5888         .sdr_dq_7__pad__oe(sdram_dq_oe[7]),
5889         .sdr_dq_8__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[8]),
5890         .sdr_dq_8__pad__o(sdram_dq_o[8]),
5891         .sdr_dq_8__pad__oe(sdram_dq_oe[8]),
5892         .sdr_dq_9__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[9]),
5893         .sdr_dq_9__pad__o(sdram_dq_o[9]),
5894         .sdr_dq_9__pad__oe(sdram_dq_oe[9]),
5895         .sdr_ras_n__pad__o(sdram_ras_n),
5896         .sdr_we_n__pad__o(sdram_we_n)
5897 );
5898
5899 endmodule