experiments9/symbolic/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4 #              DESIGN_KIT = FlexLib018
   5                DESIGN_KIT = cmos45
   6              YOSYS_FLATTEN = No
   7 #            YOSYS_SET_TOP = Yes
   8                     CHIP  = chip
   9                     CORE  = ls180
  10             USE_CLOCKTREE = Yes
  11                 USE_DEBUG = No
  12                  RM_CHIP  = Yes
  13                 VST_FLAGS = --vst-no-lowercase
  14
  15                 #NETLISTS = $(shell cat netlists.lst)
  16                  NETLISTS = ls180
  17 #           YOSYS_FLATTEN = $(shell cat flatten.lst)
  18
  19  include ./mk/design-flow.mk
  20
  21 chip_r.vst: ls180.vst
  22         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  23
  24 chip_r.ap: chip_r.vst
  25
  26 pinmux:
  27         (cd coriolis2 && python ../../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  28         ln -f -s ../../../pinmux/src/parse.py coriolis2/pinparse.py
  29         ln -f -s coriolis2/ls180 ls180
  30
  31 # comment out for now
  32 blif:      ls180.blif
  33 vst:       ls180.vst
  34
  35 lvx:       lvx-chip_r
  36 druc:      druc-chip_r
  37 dreal:     dreal-chip_r
  38 flatph:     flatph-chip_r
  39 view:      cgt-chip_r
  40
  41 layout:    chip_r.ap
  42 gds:       chip_r.gds
  43 gds_flat:  chip_r_flat.gds
  44 cif:       chip_r.cif
  45
  46
  47 view:      cgt-chip_r
  48 sim:       asimut-ls180_r