experiments9/tsmc_c018/build_full_4ksram_recon.sh

   1 #!/bin/sh
   2
   3 # full core build including QTY 4of 4k SRAMs: please remember to alter
   4 # doDesign.py before running!
   5 # change the settings to the larger chip/corona size
   6 #
   7 # also contains Staf's manually re-connected PLL edits to the verilog
   8 # see  commits 24cbbcc and 227a0f69
   9 #
  10 # Include tweaks dedicated to jpc's slightly different build environment.
  11
  12 echo "remember to check doDesign core size"
  13 echo "also use yosys 049e3abf9"
  14 if [ "${USER}" = "jpc" ]; then echo "Using \"jpc\" configuration."; fi
  15
  16 # initialise/update the pinmux submodule
  17 if [ "${USER}" = "jpc" ]; then
  18   # Must be done in the root of the repository when cloning anew.
  19   (cd ../..; git submodule update --init --remote)
  20 else
  21   git submodule update --init --remote
  22 fi
  23
  24 # makes symlinks to alliance
  25 if [ ! -e "./mk" ]; then
  26   if [ "${USER}" = "jpc" ]; then
  27     ln -s ../../../../alliance-check-toolkit/etc/mk .
  28   else
  29     ./mksyms.sh
  30   fi
  31 fi
  32
  33 # generates the io pads needed for ioring.py
  34 make pinmux
  35
  36 # clear out
  37 make clean
  38 rm -f *.vst *.ap
  39
  40 # copies over a "full" core
  41 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il
  42 cp non_generated/full_core_4_4ksram_ls180.v ls180.v
  43 cp non_generated/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
  44 cp non_generated/full_core_4_4ksram_libresoc_recon.v libresoc.v
  45 cp non_generated/spblock*.v .
  46 cp non_generated/spblock*.vbe .
  47 cp non_generated/pll.v .
  48 touch mem.init
  49 touch mem_1.init
  50 touch mem_2.init
  51 touch mem_3.init
  52 touch mem_4.init
  53 touch mem_5.init
  54
  55 if [ "${USER}" != "jpc" ]; then
  56   # make the vst from verilog
  57   make vst
  58
  59   # starts the build.
  60   make layout
  61 fi