3 { stdenv, python3Packages }:
13 nativeBuildInputs = with python3Packages; [ nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa ];
15 configurePhase = "true";
20 export PYTHONPATH="$PWD:$PYTHONPATH"
21 python3 soc/simple/issuer_verilog.py \
22 --debug=jtag --enable-core --enable-pll \
23 --enable-xics --enable-sram4x4kblock --disable-svp64 \