add first gather instruction pseudocode
[openpower-isa.git] / openpower / isa / bitmanip.mdwn
1 <!-- Draft Instructions here described in -->
2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
3 <!-- These instructions are *not yet official* -->
4
5 # Gather instruction
6
7 X-Form
8
9 * gbbd RT,RA
10
11 Pseudo-code:
12
13 result <- [0] * 64
14 do j = 0 to 7
15 do k = 0 to 7
16 b <- (RA)[k*8+j]
17 result[j*8+k] <- b
18 RT <- result
19
20 Special Registers Altered:
21
22 CR0 (if Rc=1)
23
24 # Ternary Bitwise Logic Immediate
25
26 TLI-Form
27
28 * ternlogi RT,RA,RB,TLI (Rc=0)
29 * ternlogi. RT,RA,RB,TLI (Rc=1)
30
31 Pseudo-code:
32
33 result <- [0] * XLEN
34 do i = 0 to XLEN - 1
35 idx <- (RT)[i] || (RA)[i] || (RB)[i]
36 result[i] <- TLI[7-idx]
37 RT <- result
38
39 Special Registers Altered:
40
41 CR0 (if Rc=1)
42
43 # Add With Shift By Immediate
44
45 Z23-Form
46
47 * sadd RT,RA,RB,SH (Rc=0)
48 * sadd. RT,RA,RB,SH (Rc=1)
49
50 Pseudo-code:
51
52 n <- (RB)
53 m <- ((0b0 || SH) + 1)
54 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
55
56 Special Registers Altered:
57
58 CR0 (if Rc=1)
59
60 # Add With Shift By Immediate Word
61
62 Z23-Form
63
64 * saddw RT,RA,RB,SH (Rc=0)
65 * saddw. RT,RA,RB,SH (Rc=1)
66
67 Pseudo-code:
68
69 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
70 if (RB)[XLEN/2] = 1 then
71 n[0:XLEN/2-1] <- [1]*(XLEN/2)
72 m <- ((0b0 || SH) + 1)
73 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
74
75 Special Registers Altered:
76
77 CR0 (if Rc=1)
78
79 # Add With Shift By Immediate Unsigned Word
80
81 Z23-Form
82
83 * sadduw RT,RA,RB,SH (Rc=0)
84 * sadduw. RT,RA,RB,SH (Rc=1)
85
86 Pseudo-code:
87
88 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
89 m <- ((0b0 || SH) + 1)
90 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
91
92 Special Registers Altered:
93
94 CR0 (if Rc=1)