1 <!-- Draft Instructions here described in -->
2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
3 <!-- These instructions are *not yet official* -->
20 Special Registers Altered:
24 # Ternary Bitwise Logic Immediate
28 * ternlogi RT,RA,RB,TLI (Rc=0)
29 * ternlogi. RT,RA,RB,TLI (Rc=1)
35 idx <- (RT)[i] || (RA)[i] || (RB)[i]
36 result[i] <- TLI[7-idx]
39 Special Registers Altered:
43 # Add With Shift By Immediate
47 * sadd RT,RA,RB,SH (Rc=0)
48 * sadd. RT,RA,RB,SH (Rc=1)
53 m <- ((0b0 || SH) + 1)
54 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
56 Special Registers Altered:
60 # Add With Shift By Immediate Word
64 * saddw RT,RA,RB,SH (Rc=0)
65 * saddw. RT,RA,RB,SH (Rc=1)
69 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
70 if (RB)[XLEN/2] = 1 then
71 n[0:XLEN/2-1] <- [1]*(XLEN/2)
72 m <- ((0b0 || SH) + 1)
73 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
75 Special Registers Altered:
79 # Add With Shift By Immediate Unsigned Word
83 * sadduw RT,RA,RB,SH (Rc=0)
84 * sadduw. RT,RA,RB,SH (Rc=1)
88 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
89 m <- ((0b0 || SH) + 1)
90 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
92 Special Registers Altered: