1 <!-- Draft Instructions here described in -->
2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
3 <!-- These instructions are *not yet official* -->
5 # Gather instruction
7 X-Form
9 * gbbd RT,RA
11 Pseudo-code:
13 result <- [0] * 64
14 do j = 0 to 7
15 do k = 0 to 7
16 b <- (RA)[k*8+j]
17 result[j*8+k] <- b
18 RT <- result
20 Special Registers Altered:
22 CR0 (if Rc=1)
24 # Ternary Bitwise Logic Immediate
26 TLI-Form
28 * ternlogi RT,RA,RB,TLI (Rc=0)
29 * ternlogi. RT,RA,RB,TLI (Rc=1)
31 Pseudo-code:
33 result <- [0] * XLEN
34 do i = 0 to XLEN - 1
35 idx <- (RT)[i] || (RA)[i] || (RB)[i]
36 result[i] <- TLI[idx]
37 RT <- result
39 Special Registers Altered:
41 CR0 (if Rc=1)
43 # GPR Dynamic Binary Logic
45 BM2-Form
47 * binlog RT,RA,RB,RC,nh
49 Pseudo-code:
51 if nh = 1 then lut <- (RC)[56:59]
52 else lut <- (RC)[60:63]
53 result <- [0] * 64
54 do i = 0 to 63
55 idx <- (RA)[i] || (RB)[i]
56 result[i] <- lut[idx]
57 RT <- result
59 Description:
61 If nh contains a 0, let lut be the four LSBs of RC
62 (bits 60 to 63). Otherwise let lut be the next
63 four LSBs of RC (bits 56 to 59).
65 Let j be the value of the concatenation of the
66 contents of bit i of RT with bit i of RB.
68 The value of bit j of lut is placed into bit i of RT.
70 Special registers altered:
72 None
74 # Condition Register Ternary Bitwise Logic Immediate
76 CRB-Form
78 * crfternlogi BF,BFA,BFB,TLI,msk
80 Pseudo-code:
82 bf <- CR[4*BF+32:4*BF+35]
83 bfa <- CR[4*BFA+32:4*BFA+35]
84 bfb <- CR[4*BFB+32:4*BFB+35]
86 result <- [0] * 4
87 do i = 0 to 3
88 idx <- bf[i] || bfa[i] || bfb[i]
89 result[i] <- TLI[idx]
90 do i = 0 to 3
91 if msk[i] = 1 then
92 CR[4*BF+32+i] <- result[i]
94 Special Registers Altered:
96 CR field BF
98 # Condition Register Field Ternary Bitwise Logic Immediate
100 TLI-Form
102 * crternlogi BT,BA,BB,TLI
104 Pseudo-code:
106 idx <- CR[BT+32] || CR[BA+32] || CR[BB+32]
107 CR[BT+32] <- TLI[idx]
109 Special Registers Altered:
111 CR field BF
113 # Condition Register Field Dynamic Binary Logic
115 CRB-Form
117 * crfbinlog BF,BFA,BFB,msk
119 Pseudo-code:
121 a <- CR[4*BF+32:4*BFA+35]
122 b <- CR[4*BFA+32:4*BFA+35]
123 lut <- CR[4*BFB+32:4*BFB+35]
125 result <- [0] * 4
126 do i = 0 to 3
127 idx <- a[i] || b[i]
128 result[i] <- lut[idx]
129 do i = 0 to 3
130 if msk[i] = 1 then
131 CR[4*BF+32+i] <- result[i]
133 Description:
135 For each integer value i, 0 to 3, do the following.
137 Let j be the value of the concatenation of the
138 contents of bit i of CR Field BF with bit i of CR Field BFA.
140 If bit i of msk is set to 1 then the value of bit j of
141 CR Field BFB is placed into bit i of CR Field BF.
143 Otherwise, if bit i of msk is a zero then bit i of
144 CR Field BF is unchanged.
146 If `msk` is zero an Illegal Instruction trap is raised.
148 Special registers altered:
150 CR field BF
152 # Condition Register Dynamic Binary Logic
154 X-Form
156 * crbinlog BT,BA,BFB
158 Pseudo-code:
160 lut <- CR[4*BFB+32:4*BFB+35]
161 idx <- CR[BT+32] || CR[BA+32]
162 CR[BT+32] <- lut[idx]
164 Special registers altered:
166 CR[BT+32]
168 # Add With Shift By Immediate
170 Z23-Form
175 Pseudo-code:
177 n <- (RB)
178 m <- ((0b0 || SH) + 1)
179 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
181 Special Registers Altered:
183 CR0 (if Rc=1)
185 # Add With Shift By Immediate Word
187 Z23-Form
192 Pseudo-code:
194 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
195 if (RB)[XLEN/2] = 1 then
196 n[0:XLEN/2-1] <- [1]*(XLEN/2)
197 m <- ((0b0 || SH) + 1)
198 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
200 Special Registers Altered:
202 CR0 (if Rc=1)
204 # Add With Shift By Immediate Unsigned Word
206 Z23-Form