openpower/isa/bitmanip.mdwn

   1 <!-- Draft Instructions here described in -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- These instructions are *not yet official* -->
   4
   5 # Gather instruction
   6
   7 X-Form
   8
   9 * gbbd RT,RA
  10
  11 Pseudo-code:
  12
  13     result <- [0] * 64
  14     do j = 0 to 7
  15         do k = 0 to 7
  16             b <- (RA)[k*8+j]
  17             result[j*8+k] <- b
  18     RT <- result
  19
  20 Special Registers Altered:
  21
  22     CR0                    (if Rc=1)
  23
  24 # Ternary Bitwise Logic Immediate
  25
  26 TLI-Form
  27
  28 * ternlogi RT,RA,RB,TLI (Rc=0)
  29 * ternlogi. RT,RA,RB,TLI (Rc=1)
  30
  31 Pseudo-code:
  32
  33     result <- [0] * XLEN
  34     do i = 0 to XLEN - 1
  35       idx <- (RT)[i] || (RA)[i] || (RB)[i]
  36       result[i] <- TLI[idx]
  37     RT <- result
  38
  39 Special Registers Altered:
  40
  41     CR0                    (if Rc=1)
  42
  43 # GPR Dynamic Binary Logic
  44
  45 BM2-Form
  46
  47 * binlog RT,RA,RB,RC,nh
  48
  49 Pseudo-code:
  50
  51     if nh = 1 then lut <- (RC)[56:59]
  52     else           lut <- (RC)[60:63]
  53     result <- [0] * 64
  54     do i = 0 to 63
  55       idx <- (RA)[i] || (RB)[i]
  56       result[i] <- lut[idx]
  57     RT <- result
  58
  59 Description:
  60
  61     If nh contains a 0, let lut be the four LSBs of RC
  62     (bits 60 to 63).  Otherwise let lut be the next
  63     four LSBs of RC (bits 56 to 59).
  64
  65     Let j be the value of the concatenation of the
  66     contents of bit i of RT with bit i of RB.
  67
  68     The value of bit j of lut is placed into bit i of RT.
  69
  70 Special registers altered:
  71
  72     None
  73
  74 # Condition Register Ternary Bitwise Logic Immediate
  75
  76 CRB-Form
  77
  78 * crfternlogi BF,BFA,BFB,TLI,msk
  79
  80 Pseudo-code:
  81
  82     bf <- CR[4*BF+32:4*BF+35]
  83     bfa <- CR[4*BFA+32:4*BFA+35]
  84     bfb <- CR[4*BFB+32:4*BFB+35]
  85
  86     result <- [0] * 4
  87     do i = 0 to 3
  88       idx <- bf[i] || bfa[i] || bfb[i]
  89       result[i] <- TLI[idx]
  90     do i = 0 to 3
  91         if msk[i] = 1 then
  92             CR[4*BF+32+i] <- result[i]
  93
  94 Special Registers Altered:
  95
  96      CR field BF
  97
  98 # Condition Register Field Ternary Bitwise Logic Immediate
  99
 100 TLI-Form
 101
 102 * crternlogi BT,BA,BB,TLI
 103
 104 Pseudo-code:
 105
 106     idx <- CR[BT+32] || CR[BA+32] || CR[BB+32]
 107     CR[BT+32] <- TLI[idx]
 108
 109 Special Registers Altered:
 110
 111      CR field BF
 112
 113 # Condition Register Field Dynamic Binary Logic
 114
 115 CRB-Form
 116
 117 * crfbinlog BF,BFA,BFB,msk
 118
 119 Pseudo-code:
 120
 121     a <- CR[4*BF+32:4*BFA+35]
 122     b <- CR[4*BFA+32:4*BFA+35]
 123     lut <- CR[4*BFB+32:4*BFB+35]
 124
 125     result <- [0] * 4
 126     do i = 0 to 3
 127       idx <- a[i] || b[i]
 128       result[i] <- lut[idx]
 129     do i = 0 to 3
 130         if msk[i] = 1 then
 131             CR[4*BF+32+i] <- result[i]
 132
 133 Description:
 134
 135     For each integer value i, 0 to 3, do the following.
 136
 137     Let j be the value of the concatenation of the
 138     contents of bit i of CR Field BF with bit i of CR Field BFA.
 139
 140     If bit i of msk is set to 1 then the value of bit j of
 141     CR Field BFB is placed into bit i of CR Field BF.
 142
 143     Otherwise, if bit i of msk is a zero then bit i of
 144     CR Field BF is unchanged.
 145
 146     If `msk` is zero an Illegal Instruction trap is raised.
 147
 148 Special registers altered:
 149
 150     CR field BF
 151
 152 # Condition Register Dynamic Binary Logic
 153
 154 X-Form
 155
 156 * crbinlog BT,BA,BFB
 157
 158 Pseudo-code:
 159
 160     lut <- CR[4*BFB+32:4*BFB+35]
 161     idx <- CR[BT+32] || CR[BA+32]
 162     CR[BT+32] <- lut[idx]
 163
 164 Special registers altered:
 165
 166     CR[BT+32]
 167
 168 # Add With Shift By Immediate
 169
 170 Z23-Form
 171
 172 * sadd RT,RA,RB,SH (Rc=0)
 173 * sadd. RT,RA,RB,SH (Rc=1)
 174
 175 Pseudo-code:
 176
 177     n <- (RB)
 178     m <- ((0b0 || SH) + 1)
 179     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 180
 181 Special Registers Altered:
 182
 183     CR0                    (if Rc=1)
 184
 185 # Add With Shift By Immediate Word
 186
 187 Z23-Form
 188
 189 * saddw RT,RA,RB,SH (Rc=0)
 190 * saddw. RT,RA,RB,SH (Rc=1)
 191
 192 Pseudo-code:
 193
 194     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
 195     if (RB)[XLEN/2] = 1 then
 196         n[0:XLEN/2-1] <- [1]*(XLEN/2)
 197     m <- ((0b0 || SH) + 1)
 198     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 199
 200 Special Registers Altered:
 201
 202     CR0                    (if Rc=1)
 203
 204 # Add With Shift By Immediate Unsigned Word
 205
 206 Z23-Form
 207
 208 * sadduw RT,RA,RB,SH (Rc=0)
 209 * sadduw. RT,RA,RB,SH (Rc=1)
 210
 211 Pseudo-code:
 212
 213     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
 214     m <- ((0b0 || SH) + 1)
 215     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 216
 217 Special Registers Altered:
 218
 219     CR0                    (if Rc=1)