openpower/isa/bitmanip.mdwn

   1 <!-- Draft Instructions here described in -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- These instructions are *not yet official* -->
   4
   5 # Ternary Bitwise Logic Immediate
   6
   7 TLI-Form
   8
   9 * ternlogi RT,RA,RB,TLI (Rc=0)
  10 * ternlogi. RT,RA,RB,TLI (Rc=1)
  11
  12 Pseudo-code:
  13
  14     result <- [0] * XLEN
  15     do i = 0 to XLEN - 1
  16       idx <- (RT)[i] || (RA)[i] || (RB)[i]
  17       result[i] <- TLI[7-idx]
  18     RT <- result
  19
  20 Special Registers Altered:
  21
  22     CR0                    (if Rc=1)
  23
  24 # Add With Shift By Immediate
  25
  26 Z23-Form
  27
  28 * sadd RT,RA,RB,SH (Rc=0)
  29 * sadd. RT,RA,RB,SH (Rc=1)
  30
  31 Pseudo-code:
  32
  33     n <- (RB)
  34     m <- ((0b0 || SH) + 1)
  35     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
  36
  37 Special Registers Altered:
  38
  39     CR0                    (if Rc=1)
  40
  41 # Add With Shift By Immediate Word
  42
  43 Z23-Form
  44
  45 * saddw RT,RA,RB,SH (Rc=0)
  46 * saddw. RT,RA,RB,SH (Rc=1)
  47
  48 Pseudo-code:
  49
  50     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
  51     if (RB)[XLEN/2] = 1 then
  52         n[0:XLEN/2-1] <- [1]*(XLEN/2)
  53     m <- ((0b0 || SH) + 1)
  54     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
  55
  56 Special Registers Altered:
  57
  58     CR0                    (if Rc=1)
  59
  60 # Add With Shift By Immediate Unsigned Word
  61
  62 Z23-Form
  63
  64 * sadduw RT,RA,RB,SH (Rc=0)
  65 * sadduw. RT,RA,RB,SH (Rc=1)
  66
  67 Pseudo-code:
  68
  69     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
  70     m <- ((0b0 || SH) + 1)
  71     RT <- (n[m:XLEN-1] || [0]*m) + (RA)
  72
  73 Special Registers Altered:
  74
  75     CR0                    (if Rc=1)