openpower/isa/bitmanip.mdwn

   1 <!-- Draft Instructions here described in -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- These instructions are *not yet official* -->
   4
   5 # Ternary Bitwise Logic Immediate
   6
   7 TLI-Form
   8
   9 * ternlogi RT,RA,RB,TLI
  10 * ternlogi. RT,RA,RB,TLI
  11
  12 Pseudo-code:
  13
  14     result <- [0] * XLEN
  15     do i = 0 to XLEN - 1
  16       idx <- (RT)[i] || (RA)[i] || (RB)[i]
  17       result[i] <- TLI[7-idx]
  18     RT <- result
  19
  20 Special Registers Altered:
  21
  22     CR0                    (if Rc=1)
  23
  24 # Generalized Bit-Reverse
  25
  26 X-Form
  27
  28 * grev RT,RA,RB (Rc=0)
  29 * grev. RT,RA,RB (Rc=1)
  30
  31 Pseudo-code:
  32
  33     result <- [0] * XLEN
  34     b <- EXTZ64(RB)
  35     do i = 0 to XLEN - 1
  36       idx <- b[64-log2(XLEN):63] ^ i
  37       result[i] <- (RA)[idx]
  38     RT <- result
  39
  40 Special Registers Altered:
  41
  42     CR0                    (if Rc=1)
  43
  44 # Generalized Bit-Reverse Immediate
  45
  46 XB-Form
  47
  48 * grevi RT,RA,XBI (Rc=0)
  49 * grevi. RT,RA,XBI (Rc=1)
  50
  51 Pseudo-code:
  52
  53     result <- [0] * XLEN
  54     do i = 0 to XLEN - 1
  55       idx <- XBI[6-log2(XLEN):5] ^ i
  56       result[i] <- (RA)[idx]
  57     RT <- result
  58
  59 Special Registers Altered:
  60
  61     CR0                    (if Rc=1)
  62
  63 # Generalized Bit-Reverse Word
  64
  65 X-Form
  66
  67 * grevw RT,RA,RB (Rc=0)
  68 * grevw. RT,RA,RB (Rc=1)
  69
  70 Pseudo-code:
  71
  72     result <- [0] * (XLEN / 2)
  73     a <- (RA)[XLEN/2:XLEN-1]
  74     b <- EXTZ64(RB)
  75     do i = 0 to XLEN / 2 - 1
  76       idx <- b[64-log2(XLEN/2):63] ^ i
  77       result[i] <- a[idx]
  78     RT <- ([0] * (XLEN / 2)) || result
  79
  80 Special Registers Altered:
  81
  82     CR0                    (if Rc=1)
  83
  84 # Generalized Bit-Reverse Word Immediate
  85
  86 X-Form
  87
  88 * grevwi RT,RA,SH (Rc=0)
  89 * grevwi. RT,RA,SH (Rc=1)
  90
  91 Pseudo-code:
  92
  93     result <- [0] * (XLEN / 2)
  94     a <- (RA)[XLEN/2:XLEN-1]
  95     do i = 0 to XLEN / 2 - 1
  96       idx <- SH[5-log2(XLEN/2):4] ^ i
  97       result[i] <- a[idx]
  98     RT <- ([0] * (XLEN / 2)) || result
  99
 100 Special Registers Altered:
 101
 102     CR0                    (if Rc=1)
 103
 104 # Add With Shift By Immediate
 105
 106 Z23-Form
 107
 108 * shadd RT,RA,RB,sm (Rc=0)
 109 * shadd. RT,RA,RB,sm (Rc=1)
 110
 111 Pseudo-code:
 112
 113     n <- (RB)
 114     switch (sm)
 115         case (0): sum[0:XLEN-1] = (n[0:XLEN-1-1] || [0]*1) + (RA)
 116         case (1): sum[0:XLEN-1] = (n[0:XLEN-2-1] || [0]*2) + (RA)
 117         case (2): sum[0:XLEN-1] = (n[0:XLEN-3-1] || [0]*3) + (RA)
 118         default:  sum[0:XLEN-1] = (n[0:XLEN-4-1] || [0]*4) + (RA)
 119     RT <- sum
 120
 121 Special Registers Altered:
 122
 123     CR0                    (if Rc=1)
 124
 125 # Add With Shift By Immediate Unsinged Word
 126
 127 Z23-Form
 128
 129 * shadduw RT,RA,RB,sm (Rc=0)
 130 * shadduw. RT,RA,RB,sm (Rc=1)
 131
 132 Pseudo-code:
 133
 134     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
 135     switch (sm)
 136         case (0): sum[0:XLEN-1] = (n[0:XLEN-1-1] || [0]*1) + (RA)
 137         case (1): sum[0:XLEN-1] = (n[0:XLEN-2-1] || [0]*2) + (RA)
 138         case (2): sum[0:XLEN-1] = (n[0:XLEN-3-1] || [0]*3) + (RA)
 139         default:  sum[0:XLEN-1] = (n[0:XLEN-4-1] || [0]*4) + (RA)
 140     RT <- sum
 141
 142 Special Registers Altered:
 143
 144     CR0                    (if Rc=1)