1 <!-- Draft Instructions here described in https://libre-soc.org/openpower/sv/bitmanip/ -->
2 <!-- These instructions are *not yet official* -->
4 # Ternary Bitwise Logic Immediate
8 * ternlogi RT,RA,RB,TLI
9 * ternlogi. RT,RA,RB,TLI
15 idx <- (RT)[i] || (RA)[i] || (RB)[i]
16 result[i] <- TLI[7-idx]
19 Special Registers Altered:
23 # Generalized Bit-Reverse
27 * grev RT,RA,RB (Rc=0)
28 * grev. RT,RA,RB (Rc=1)
35 idx <- b[64-log2(XLEN):63] ^ i
36 result[i] <- (RA)[idx]
39 Special Registers Altered:
43 # Generalized Bit-Reverse Immediate
47 * grevi RT,RA,XBI (Rc=0)
48 * grevi. RT,RA,XBI (Rc=1)
54 idx <- XBI[6-log2(XLEN):5] ^ i
55 result[i] <- (RA)[idx]
58 Special Registers Altered:
62 # Generalized Bit-Reverse Word
66 * grevw RT,RA,RB (Rc=0)
67 * grevw. RT,RA,RB (Rc=1)
71 result <- [0] * (XLEN / 2)
72 a <- (RA)[XLEN/2:XLEN-1]
74 do i = 0 to XLEN / 2 - 1
75 idx <- b[64-log2(XLEN/2):63] ^ i
77 RT <- ([0] * (XLEN / 2)) || result
79 Special Registers Altered:
83 # Generalized Bit-Reverse Word Immediate
87 * grevwi RT,RA,SH (Rc=0)
88 * grevwi. RT,RA,SH (Rc=1)
92 result <- [0] * (XLEN / 2)
93 a <- (RA)[XLEN/2:XLEN-1]
94 do i = 0 to XLEN / 2 - 1
95 idx <- SH[5-log2(XLEN/2):4] ^ i
97 RT <- ([0] * (XLEN / 2)) || result
99 Special Registers Altered: