1 <!-- Draft Instructions here described in -->
2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
3 <!-- These instructions are *not yet official* -->
5 # Ternary Bitwise Logic Immediate
9 * ternlogi RT,RA,RB,TLI (Rc=0)
10 * ternlogi. RT,RA,RB,TLI (Rc=1)
16 idx <- (RT)[i] || (RA)[i] || (RB)[i]
17 result[i] <- TLI[7-idx]
20 Special Registers Altered:
24 # Generalized Bit-Reverse
28 * grev RT,RA,RB (Rc=0)
29 * grev. RT,RA,RB (Rc=1)
36 idx <- b[64-log2(XLEN):63] ^ i
37 result[i] <- (RA)[idx]
40 Special Registers Altered:
44 # Generalized Bit-Reverse Immediate
48 * grevi RT,RA,XBI (Rc=0)
49 * grevi. RT,RA,XBI (Rc=1)
55 idx <- XBI[6-log2(XLEN):5] ^ i
56 result[i] <- (RA)[idx]
59 Special Registers Altered:
63 # Generalized Bit-Reverse Word
67 * grevw RT,RA,RB (Rc=0)
68 * grevw. RT,RA,RB (Rc=1)
72 result <- [0] * (XLEN / 2)
73 a <- (RA)[XLEN/2:XLEN-1]
75 do i = 0 to XLEN / 2 - 1
76 idx <- b[64-log2(XLEN/2):63] ^ i
78 RT <- ([0] * (XLEN / 2)) || result
80 Special Registers Altered:
84 # Generalized Bit-Reverse Word Immediate
88 * grevwi RT,RA,SH (Rc=0)
89 * grevwi. RT,RA,SH (Rc=1)
93 result <- [0] * (XLEN / 2)
94 a <- (RA)[XLEN/2:XLEN-1]
95 do i = 0 to XLEN / 2 - 1
96 idx <- SH[5-log2(XLEN/2):4] ^ i
98 RT <- ([0] * (XLEN / 2)) || result
100 Special Registers Altered:
104 # Add With Shift By Immediate
108 * shadd RT,RA,RB,sm (Rc=0)
109 * shadd. RT,RA,RB,sm (Rc=1)
114 m <- ((0b0 || sm) + 1)
115 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
117 Special Registers Altered:
121 # Add With Shift By Immediate Unsinged Word
125 * shadduw RT,RA,RB,sm (Rc=0)
126 * shadduw. RT,RA,RB,sm (Rc=1)
130 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
131 m <- ((0b0 || sm) + 1)
132 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
134 Special Registers Altered: