grev[w][i][.] pseudo-code works
[openpower-isa.git] / openpower / isa / bitmanip.mdwn
1 <!-- Draft Instructions here described in https://libre-soc.org/openpower/sv/bitmanip/ -->
2 <!-- These instructions are *not yet official* -->
3
4 # Ternary Bitwise Logic Immediate
5
6 TLI-Form
7
8 * ternlogi RT, RA, RB, TLI
9
10 Pseudo-code:
11
12 result <- [0] * XLEN
13 do i = 0 to XLEN - 1
14 idx <- (RT)[i] || (RA)[i] || (RB)[i]
15 result[i] <- TLI[7-idx]
16 RT <- result
17
18 Special Registers Altered:
19
20 None
21
22 # Generalized Bit-Reverse
23
24 X-Form
25
26 * grev RT, RA, RB (Rc=0)
27 * grev. RT, RA, RB (Rc=1)
28
29 Pseudo-code:
30
31 result <- [0] * XLEN
32 b <- EXTZ64(RB)
33 do i = 0 to XLEN - 1
34 idx <- b[64-log2(XLEN):63] ^ i
35 result[i] <- (RA)[idx]
36 RT <- result
37
38 Special Registers Altered:
39
40 CR0 (if Rc=1)
41
42 # Generalized Bit-Reverse Immediate
43
44 XB-Form
45
46 * grevi RT, RA, XBI (Rc=0)
47 * grevi. RT, RA, XBI (Rc=1)
48
49 Pseudo-code:
50
51 result <- [0] * XLEN
52 do i = 0 to XLEN - 1
53 idx <- XBI[6-log2(XLEN):5] ^ i
54 result[i] <- (RA)[idx]
55 RT <- result
56
57 Special Registers Altered:
58
59 CR0 (if Rc=1)
60
61 # Generalized Bit-Reverse Word
62
63 X-Form
64
65 * grevw RT, RA, RB (Rc=0)
66 * grevw. RT, RA, RB (Rc=1)
67
68 Pseudo-code:
69
70 result <- [0] * (XLEN / 2)
71 a <- (RA)[XLEN/2:XLEN-1]
72 b <- EXTZ64(RB)
73 do i = 0 to XLEN / 2 - 1
74 idx <- b[64-log2(XLEN/2):63] ^ i
75 result[i] <- a[idx]
76 RT <- ([0] * (XLEN / 2)) || result
77
78 Special Registers Altered:
79
80 CR0 (if Rc=1)
81
82 # Generalized Bit-Reverse Word Immediate
83
84 X-Form
85
86 * grevwi RT, RA, SH (Rc=0)
87 * grevwi. RT, RA, SH (Rc=1)
88
89 Pseudo-code:
90
91 result <- [0] * (XLEN / 2)
92 a <- (RA)[XLEN/2:XLEN-1]
93 do i = 0 to XLEN / 2 - 1
94 idx <- SH[5-log2(XLEN/2):4] ^ i
95 result[i] <- a[idx]
96 RT <- ([0] * (XLEN / 2)) || result
97
98 Special Registers Altered:
99
100 CR0 (if Rc=1)