1 <!-- Draft Instructions here described in https://libre-soc.org/openpower/sv/bitmanip/ -->
2 <!-- These instructions are *not yet official* -->
4 # Ternary Bitwise Logic Immediate
8 * ternlogi RT, RA, RB, TLI
14 idx <- (RT)[i] || (RA)[i] || (RB)[i]
15 result[i] <- TLI[7-idx]
18 Special Registers Altered:
22 # Generalized Bit-Reverse
26 * grev RT, RA, RB (Rc=0)
27 * grev. RT, RA, RB (Rc=1)
34 idx <- b[64-log2(XLEN):63] ^ i
35 result[i] <- (RA)[idx]
38 Special Registers Altered:
42 # Generalized Bit-Reverse Immediate
46 * grevi RT, RA, XBI (Rc=0)
47 * grevi. RT, RA, XBI (Rc=1)
53 idx <- XBI[6-log2(XLEN):5] ^ i
54 result[i] <- (RA)[idx]
57 Special Registers Altered:
61 # Generalized Bit-Reverse Word
65 * grevw RT, RA, RB (Rc=0)
66 * grevw. RT, RA, RB (Rc=1)
70 result <- [0] * (XLEN / 2)
71 a <- (RA)[XLEN/2:XLEN-1]
73 do i = 0 to XLEN / 2 - 1
74 idx <- b[64-log2(XLEN/2):63] ^ i
76 RT <- ([0] * (XLEN / 2)) || result
78 Special Registers Altered:
82 # Generalized Bit-Reverse Word Immediate
86 * grevwi RT, RA, SH (Rc=0)
87 * grevwi. RT, RA, SH (Rc=1)
91 result <- [0] * (XLEN / 2)
92 a <- (RA)[XLEN/2:XLEN-1]
93 do i = 0 to XLEN / 2 - 1
94 idx <- SH[5-log2(XLEN/2):4] ^ i
96 RT <- ([0] * (XLEN / 2)) || result
98 Special Registers Altered: